]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: check connector hw/sw state
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
ab7ad7f6
KP		 1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
e9a851ed 1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
e9a851ed 1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
e9a851ed 1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
7434a255
TR		 1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1434 */
a37b9b34 1435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
a0c4da24 1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
a416edef
ED		 1491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
39fb50f6 1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
39fb50f6 1526 u32 value = 0;
a416edef
ED		 1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
39fb50f6 1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
92f2584a
JB		 1554/**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
ee7b9f93 1562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1563{
ee7b9f93 1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1565 struct intel_pch_pll *pll;
92f2584a
JB		 1566 int reg;
1567 u32 val;
1568
48da64a8 1569 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1570 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
ee7b9f93
JB		 1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
92f2584a
JB		 1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
ee7b9f93 1585 if (pll->active++ && pll->on) {
92b27b08 1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
92f2584a
JB		 1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
ee7b9f93
JB		 1598
1599 pll->on = true;
92f2584a
JB		 1600}
1601
ee7b9f93 1602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1603{
ee7b9f93
JB		 1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1606 int reg;
ee7b9f93 1607 u32 val;
4c609cb8 1608
92f2584a
JB		 1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1611 if (pll == NULL)
1612 return;
92f2584a 1613
48da64a8
CW		 1614 if (WARN_ON(pll->refcount == 0))
1615 return;
7a419866 1616
ee7b9f93
JB		 1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
7a419866 1620
48da64a8 1621 if (WARN_ON(pll->active == 0)) {
92b27b08 1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1623 return;
1624 }
1625
ee7b9f93 1626 if (--pll->active) {
92b27b08 1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1628 return;
ee7b9f93
JB		 1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1635
ee7b9f93 1636 reg = pll->pll_reg;
92f2584a
JB		 1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
ee7b9f93
JB		 1642
1643 pll->on = false;
92f2584a
JB		 1644}
1645
040484af
JB		 1646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
5f7f726d 1650 u32 val, pipeconf_val;
7c26e5c6 1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
040484af
JB		 1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
59c859d6
ED		 1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
040484af
JB		 1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
5f7f726d 1671 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
5f7f726d 1679 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1680 }
5f7f726d
PZ		 1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
040484af
JB		 1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
291906f1
JB		 1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
040484af
JB		 1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1717}
1718
b24e7179 1719/**
309cfea8 1720 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
040484af 1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
040484af
JB		 1733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
b24e7179
JB		 1735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
b24e7179
JB		 1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
00d70b15
CW		 1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
309cfea8 1765 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
00d70b15
CW		 1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
d74362c9
KP		 1801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
6f1d69b0 1805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
b24e7179
JB		 1812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
00d70b15
CW		 1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1835 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
b24e7179
JB		 1839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
47a05eca 1863static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1864 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1865{
1866 u32 val = I915_READ(reg);
4e634389 1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1869 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1870 }
47a05eca
JB		 1871}
1872
1873static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875{
1876 u32 val = I915_READ(reg);
e9a851ed 1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
f0575e92
KP		 1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
47a05eca 1880 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1881 }
47a05eca
JB		 1882}
1883
1884/* Disable any ports connected to this transcoder */
1885static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887{
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
f0575e92
KP		 1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
e9a851ed 1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
47a05eca
JB		 1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
e9a851ed 1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1519b995 1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914}
1915
127bd2ac 1916int
48b956c5 1917intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1918 struct drm_i915_gem_object *obj,
919926ae 1919 struct intel_ring_buffer *pipelined)
6b95a207 1920{
ce453d81 1921 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1922 u32 alignment;
1923 int ret;
1924
05394f39 1925 switch (obj->tiling_mode) {
6b95a207 1926 case I915_TILING_NONE:
534843da
CW		 1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
a6c45cf0 1929 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
6b95a207
KH		 1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
ce453d81 1946 dev_priv->mm.interruptible = false;
2da3b9b9 1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1948 if (ret)
ce453d81 1949 goto err_interruptible;
6b95a207
KH		 1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
06d98131 1956 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1957 if (ret)
1958 goto err_unpin;
1690e1eb 1959
9a5a53b3 1960 i915_gem_object_pin_fence(obj);
6b95a207 1961
ce453d81 1962 dev_priv->mm.interruptible = true;
6b95a207 1963 return 0;
48b956c5
CW		 1964
1965err_unpin:
1966 i915_gem_object_unpin(obj);
ce453d81
CW		 1967err_interruptible:
1968 dev_priv->mm.interruptible = true;
48b956c5 1969 return ret;
6b95a207
KH		 1970}
1971
1690e1eb
CW		 1972void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973{
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976}
1977
c2c75131
DV		 1978/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983{
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992}
1993
17638cd6
JB		 1994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
81255565
JB		 1996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
05394f39 2001 struct drm_i915_gem_object *obj;
81255565 2002 int plane = intel_crtc->plane;
e506a0c6 2003 unsigned long linear_offset;
81255565 2004 u32 dspcntr;
5eddb70b 2005 u32 reg;
81255565
JB		 2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
81255565 2018
5eddb70b
CW		 2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
81255565
JB		 2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
17638cd6 2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2039 return -EINVAL;
2040 }
a6c45cf0 2041 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2042 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
5eddb70b 2048 I915_WRITE(reg, dspcntr);
81255565 2049
e506a0c6 2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2051
c2c75131
DV		 2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
e506a0c6 2059 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2060 }
e506a0c6
DV		 2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2065 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2070 } else
e506a0c6 2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2072 POSTING_READ(reg);
81255565 2073
17638cd6
JB		 2074 return 0;
2075}
2076
2077static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
e506a0c6 2086 unsigned long linear_offset;
17638cd6
JB		 2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
27f8227b 2093 case 2:
17638cd6
JB		 2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
e506a0c6 2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2147
e506a0c6
DV		 2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2155 POSTING_READ(reg);
2156
2157 return 0;
2158}
2159
2160/* Assume fb object is pinned & idle & fenced and just update base pointers */
2161static int
2162intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164{
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2167
6b8e6ed0
CW		 2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
3dec0095 2170 intel_increase_pllclock(crtc);
81255565 2171
6b8e6ed0 2172 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2173}
2174
14667a4b
CW		 2175static int
2176intel_finish_fb(struct drm_framebuffer *old_fb)
2177{
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200}
2201
5c3b82e2 2202static int
3c4fdcfb
KH		 2203intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
79e53945
JB		 2205{
2206 struct drm_device *dev = crtc->dev;
6b8e6ed0 2207 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2210 int ret;
79e53945
JB		 2211
2212 /* no fb bound */
2213 if (!crtc->fb) {
a5071c2f 2214 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2215 return 0;
2216 }
2217
5826eca5
ED		 2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
5c3b82e2 2222 return -EINVAL;
79e53945
JB		 2223 }
2224
5c3b82e2 2225 mutex_lock(&dev->struct_mutex);
265db958
CW		 2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2228 NULL);
5c3b82e2
CW		 2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
a5071c2f 2231 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2232 return ret;
2233 }
79e53945 2234
14667a4b
CW		 2235 if (old_fb)
2236 intel_finish_fb(old_fb);
265db958 2237
6b8e6ed0 2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2239 if (ret) {
1690e1eb 2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2241 mutex_unlock(&dev->struct_mutex);
a5071c2f 2242 DRM_ERROR("failed to update base address\n");
4e6cfefc 2243 return ret;
79e53945 2244 }
3c4fdcfb 2245
b7f1de28
CW		 2246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2249 }
652c393a 2250
6b8e6ed0 2251 intel_update_fbc(dev);
5c3b82e2 2252 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2253
2254 if (!dev->primary->master)
5c3b82e2 2255 return 0;
79e53945
JB		 2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
5c3b82e2 2259 return 0;
79e53945 2260
265db958 2261 if (intel_crtc->pipe) {
79e53945
JB		 2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
79e53945 2267 }
5c3b82e2
CW		 2268
2269 return 0;
79e53945
JB		 2270}
2271
5eddb70b 2272static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2273{
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
28c97730 2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
5eddb70b 2305 POSTING_READ(DP_A);
32f9d658
ZW		 2306 udelay(500);
2307}
2308
5e84e1a4
ZW		 2309static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310{
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
61e499bf 2320 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2326 }
5e84e1a4
ZW		 2327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
357555c0
JB		 2343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2348}
2349
291427f5
JB		 2350static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360}
2361
8db9d77b
ZW		 2362/* The FDI link training functions for ILK/Ibexpeak. */
2363static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364{
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
0fc932b8 2369 int plane = intel_crtc->plane;
5eddb70b 2370 u32 reg, temp, tries;
8db9d77b 2371
0fc932b8
JB		 2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
e1a44743
AJ		 2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
5eddb70b
CW		 2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
e1a44743
AJ		 2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
e1a44743
AJ		 2384 udelay(150);
2385
8db9d77b 2386 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
77ffb597
AJ		 2389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2394
5eddb70b
CW		 2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
8db9d77b
ZW		 2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
8db9d77b
ZW		 2402 udelay(150);
2403
5b2adf89 2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
5b2adf89 2410
5eddb70b 2411 reg = FDI_RX_IIR(pipe);
e1a44743 2412 for (tries = 0; tries < 5; tries++) {
5eddb70b 2413 temp = I915_READ(reg);
8db9d77b
ZW		 2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2419 break;
2420 }
8db9d77b 2421 }
e1a44743 2422 if (tries == 5)
5eddb70b 2423 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2424
2425 /* Train 2 */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2430 I915_WRITE(reg, temp);
8db9d77b 2431
5eddb70b
CW		 2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
8db9d77b
ZW		 2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2436 I915_WRITE(reg, temp);
8db9d77b 2437
5eddb70b
CW		 2438 POSTING_READ(reg);
2439 udelay(150);
8db9d77b 2440
5eddb70b 2441 reg = FDI_RX_IIR(pipe);
e1a44743 2442 for (tries = 0; tries < 5; tries++) {
5eddb70b 2443 temp = I915_READ(reg);
8db9d77b
ZW		 2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
8db9d77b 2451 }
e1a44743 2452 if (tries == 5)
5eddb70b 2453 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2454
2455 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2456
8db9d77b
ZW		 2457}
2458
0206e353 2459static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464};
2465
2466/* The FDI link training functions for SNB/Cougarpoint. */
2467static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468{
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
fa37d39e 2473 u32 reg, temp, i, retry;
8db9d77b 2474
e1a44743
AJ		 2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
5eddb70b
CW		 2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
e1a44743
AJ		 2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
e1a44743
AJ		 2484 udelay(150);
2485
8db9d77b 2486 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
77ffb597
AJ		 2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2497
5eddb70b
CW		 2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
5eddb70b
CW		 2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
8db9d77b
ZW		 2510 udelay(150);
2511
291427f5
JB		 2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
0206e353 2515 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
8db9d77b
ZW		 2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
8db9d77b
ZW		 2523 udelay(500);
2524
fa37d39e
SP		 2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
8db9d77b 2535 }
fa37d39e
SP		 2536 if (retry < 5)
2537 break;
8db9d77b
ZW		 2538 }
2539 if (i == 4)
5eddb70b 2540 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2541
2542 /* Train 2 */
5eddb70b
CW		 2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
8db9d77b
ZW		 2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
5eddb70b 2552 I915_WRITE(reg, temp);
8db9d77b 2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596}
2597
357555c0
JB		 2598/* Manual link training for Ivy Bridge A0 parts */
2599static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2627 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2635 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
291427f5
JB		 2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
0206e353 2644 for (i = 0; i < 4; i++) {
357555c0
JB		 2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710}
2711
88cefb6c 2712static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2713{
88cefb6c 2714 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2715 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2716 int pipe = intel_crtc->pipe;
5eddb70b 2717 u32 reg, temp;
79e53945 2718
c64e311e 2719 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2722
c98e9dcf 2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
c98e9dcf
JB		 2732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
c98e9dcf
JB		 2739 udelay(200);
2740
bf507ef7
ED		 2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2749
bf507ef7
ED		 2750 POSTING_READ(reg);
2751 udelay(100);
2752 }
6be4a607 2753 }
0e23b99d
JB		 2754}
2755
88cefb6c
DV		 2756static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757{
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(100);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780 /* Wait for the clocks to turn off. */
2781 POSTING_READ(reg);
2782 udelay(100);
2783}
2784
291427f5
JB		 2785static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786{
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2795}
0fc932b8
JB		 2796static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797{
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2802 u32 reg, temp;
2803
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808 POSTING_READ(reg);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816 POSTING_READ(reg);
2817 udelay(100);
2818
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2827 }
0fc932b8
JB		 2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852}
2853
e6c3a2a6
CW		 2854static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855{
0f91128d 2856 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2857
2858 if (crtc->fb == NULL)
2859 return;
2860
0f91128d
CW		 2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2864}
2865
040484af
JB		 2866static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867{
2868 struct drm_device *dev = crtc->dev;
228d3e36 2869 struct intel_encoder *intel_encoder;
040484af
JB		 2870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
228d3e36 2875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2876
6ee8bab0
ED		 2877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2882
228d3e36 2883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885 return true;
2886 } else {
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2888 intel_encoder->type);
6ee8bab0
ED		 2889 return false;
2890 }
2891 }
2892
228d3e36 2893 switch (intel_encoder->type) {
040484af 2894 case INTEL_OUTPUT_EDP:
228d3e36 2895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902}
2903
e615efe4
ED		 2904/* Program iCLKIP clock to the desired frequency */
2905static void lpt_program_iclkip(struct drm_crtc *crtc)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2921
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2924 auxdiv = 1;
2925 divsel = 0x41;
2926 phaseinc = 0x20;
2927 } else {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2932 * precision.
2933 */
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2941
2942 auxdiv = 0;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2945 }
2946
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954 crtc->mode.clock,
2955 auxdiv,
2956 divsel,
2957 phasedir,
2958 phaseinc);
2959
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2971 temp);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2978 SBI_SSCAUXDIV6,
2979 temp);
2980
2981
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2986 SBI_SSCCTL6,
2987 temp);
2988
2989 /* Wait for initialization time */
2990 udelay(24);
2991
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993}
2994
f67a559d
JB		 2995/*
2996 * Enable PCH resources required for PCH ports:
2997 * - PCH PLLs
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3001 * - transcoder
3002 */
3003static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3004{
3005 struct drm_device *dev = crtc->dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
ee7b9f93 3009 u32 reg, temp;
2c07245f 3010
e7e164db
CW		 3011 assert_transcoder_disabled(dev_priv, pipe);
3012
c98e9dcf 3013 /* For PCH output, training FDI link */
674cf967 3014 dev_priv->display.fdi_link_train(crtc);
2c07245f 3015
6f13b7b5
CW		 3016 intel_enable_pch_pll(intel_crtc);
3017
e615efe4
ED		 3018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3022 u32 sel;
4b645f14 3023
c98e9dcf 3024 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3025 switch (pipe) {
3026 default:
3027 case 0:
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3030 break;
3031 case 1:
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3034 break;
3035 case 2:
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3038 break;
d64311ab 3039 }
ee7b9f93
JB		 3040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041 temp |= sel;
3042 else
3043 temp &= ~sel;
c98e9dcf 3044 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3045 }
5eddb70b 3046
d9b6cb56
JB		 3047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3052
5eddb70b
CW		 3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3057
f57e1e3a
ED		 3058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
5e84e1a4 3060
c98e9dcf
JB		 3061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3069 TRANS_DP_SYNC_MASK |
3070 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
9325c9f0 3073 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3074
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3079
3080 switch (intel_trans_dp_port_sel(crtc)) {
3081 case PCH_DP_B:
5eddb70b 3082 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3083 break;
3084 case PCH_DP_C:
5eddb70b 3085 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3086 break;
3087 case PCH_DP_D:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3089 break;
3090 default:
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3092 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3093 break;
32f9d658 3094 }
2c07245f 3095
5eddb70b 3096 I915_WRITE(reg, temp);
6be4a607 3097 }
b52eb4dc 3098
040484af 3099 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3100}
3101
ee7b9f93
JB		 3102static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103{
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116}
3117
3118static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119{
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
98b6bd99
DV		 3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
ee7b9f93
JB		 3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3177
e04c7350
CW		 3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
e04c7350
CW		 3182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3185 pll->on = false;
3186 return pll;
3187}
3188
d4270e57
JB		 3189void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200 udelay(250);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204 }
3205}
3206
f67a559d
JB		 3207static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3212 struct intel_encoder *encoder;
f67a559d
JB		 3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
3216 bool is_pch_port;
3217
08a48469
DV		 3218 WARN_ON(!crtc->enabled);
3219
ef9c3aee
DV		 3220 /* XXX: For compatability with the crtc helper code, call the encoder's
3221 * enable function unconditionally for now. */
f67a559d 3222 if (intel_crtc->active)
ef9c3aee 3223 goto encoders;
f67a559d
JB		 3224
3225 intel_crtc->active = true;
3226 intel_update_watermarks(dev);
3227
3228 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3229 temp = I915_READ(PCH_LVDS);
3230 if ((temp & LVDS_PORT_EN) == 0)
3231 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3232 }
3233
3234 is_pch_port = intel_crtc_driving_pch(crtc);
3235
3236 if (is_pch_port)
88cefb6c 3237 ironlake_fdi_pll_enable(intel_crtc);
f67a559d
JB		 3238 else
3239 ironlake_fdi_disable(crtc);
3240
3241 /* Enable panel fitting for LVDS */
3242 if (dev_priv->pch_pf_size &&
3243 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3244 /* Force use of hard-coded filter coefficients
3245 * as some pre-programmed values are broken,
3246 * e.g. x201.
3247 */
9db4a9c7
JB		 3248 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3249 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3250 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3251 }
3252
9c54c0dd
JB		 3253 /*
3254 * On ILK+ LUT must be loaded before the pipe is running but with
3255 * clocks enabled
3256 */
3257 intel_crtc_load_lut(crtc);
3258
f67a559d
JB		 3259 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3260 intel_enable_plane(dev_priv, plane, pipe);
3261
3262 if (is_pch_port)
3263 ironlake_pch_enable(crtc);
c98e9dcf 3264
d1ebd816 3265 mutex_lock(&dev->struct_mutex);
bed4a673 3266 intel_update_fbc(dev);
d1ebd816
BW		 3267 mutex_unlock(&dev->struct_mutex);
3268
6b383a7f 3269 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3270
3271encoders:
fa5c73b1
DV		 3272 for_each_encoder_on_crtc(dev, crtc, encoder)
3273 encoder->enable(encoder);
61b77ddd
DV		 3274
3275 if (HAS_PCH_CPT(dev))
3276 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3277}
3278
3279static void ironlake_crtc_disable(struct drm_crtc *crtc)
3280{
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3284 struct intel_encoder *encoder;
6be4a607
JB		 3285 int pipe = intel_crtc->pipe;
3286 int plane = intel_crtc->plane;
5eddb70b 3287 u32 reg, temp;
b52eb4dc 3288
ef9c3aee
DV		 3289 /* XXX: For compatability with the crtc helper code, call the encoder's
3290 * disable function unconditionally for now. */
fa5c73b1
DV		 3291 for_each_encoder_on_crtc(dev, crtc, encoder)
3292 encoder->disable(encoder);
ef9c3aee 3293
f7abfe8b
CW		 3294 if (!intel_crtc->active)
3295 return;
3296
e6c3a2a6 3297 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3298 drm_vblank_off(dev, pipe);
6b383a7f 3299 intel_crtc_update_cursor(crtc, false);
5eddb70b 3300
b24e7179 3301 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3302
973d04f9
CW		 3303 if (dev_priv->cfb_plane == plane)
3304 intel_disable_fbc(dev);
2c07245f 3305
b24e7179 3306 intel_disable_pipe(dev_priv, pipe);
32f9d658 3307
6be4a607 3308 /* Disable PF */
9db4a9c7
JB		 3309 I915_WRITE(PF_CTL(pipe), 0);
3310 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3311
0fc932b8 3312 ironlake_fdi_disable(crtc);
2c07245f 3313
47a05eca
JB		 3314 /* This is a horrible layering violation; we should be doing this in
3315 * the connector/encoder ->prepare instead, but we don't always have
3316 * enough information there about the config to know whether it will
3317 * actually be necessary or just cause undesired flicker.
3318 */
3319 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3320
040484af 3321 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3322
6be4a607
JB		 3323 if (HAS_PCH_CPT(dev)) {
3324 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3325 reg = TRANS_DP_CTL(pipe);
3326 temp = I915_READ(reg);
3327 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3328 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3329 I915_WRITE(reg, temp);
6be4a607
JB		 3330
3331 /* disable DPLL_SEL */
3332 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3333 switch (pipe) {
3334 case 0:
d64311ab 3335 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3336 break;
3337 case 1:
6be4a607 3338 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3339 break;
3340 case 2:
4b645f14 3341 /* C shares PLL A or B */
d64311ab 3342 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3343 break;
3344 default:
3345 BUG(); /* wtf */
3346 }
6be4a607 3347 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3348 }
e3421a18 3349
6be4a607 3350 /* disable PCH DPLL */
ee7b9f93 3351 intel_disable_pch_pll(intel_crtc);
8db9d77b 3352
88cefb6c 3353 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3354
f7abfe8b 3355 intel_crtc->active = false;
6b383a7f 3356 intel_update_watermarks(dev);
d1ebd816
BW		 3357
3358 mutex_lock(&dev->struct_mutex);
6b383a7f 3359 intel_update_fbc(dev);
d1ebd816 3360 mutex_unlock(&dev->struct_mutex);
6be4a607 3361}
1b3c7a47 3362
ee7b9f93
JB		 3363static void ironlake_crtc_off(struct drm_crtc *crtc)
3364{
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 intel_put_pch_pll(intel_crtc);
3367}
3368
02e792fb
DV		 3369static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3370{
02e792fb 3371 if (!enable && intel_crtc->overlay) {
23f09ce3 3372 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3373 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3374
23f09ce3 3375 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3376 dev_priv->mm.interruptible = false;
3377 (void) intel_overlay_switch_off(intel_crtc->overlay);
3378 dev_priv->mm.interruptible = true;
23f09ce3 3379 mutex_unlock(&dev->struct_mutex);
02e792fb 3380 }
02e792fb 3381
5dcdbcb0
CW		 3382 /* Let userspace switch the overlay on again. In most cases userspace
3383 * has to recompute where to put it anyway.
3384 */
02e792fb
DV		 3385}
3386
0b8765c6 3387static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3388{
3389 struct drm_device *dev = crtc->dev;
79e53945
JB		 3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3392 struct intel_encoder *encoder;
79e53945 3393 int pipe = intel_crtc->pipe;
80824003 3394 int plane = intel_crtc->plane;
79e53945 3395
08a48469
DV		 3396 WARN_ON(!crtc->enabled);
3397
ef9c3aee
DV		 3398 /* XXX: For compatability with the crtc helper code, call the encoder's
3399 * enable function unconditionally for now. */
f7abfe8b 3400 if (intel_crtc->active)
ef9c3aee 3401 goto encoders;
f7abfe8b
CW		 3402
3403 intel_crtc->active = true;
6b383a7f
CW		 3404 intel_update_watermarks(dev);
3405
63d7bbe9 3406 intel_enable_pll(dev_priv, pipe);
040484af 3407 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3408 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3409
0b8765c6 3410 intel_crtc_load_lut(crtc);
bed4a673 3411 intel_update_fbc(dev);
79e53945 3412
0b8765c6
JB		 3413 /* Give the overlay scaler a chance to enable if it's on this pipe */
3414 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3415 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3416
3417encoders:
fa5c73b1
DV		 3418 for_each_encoder_on_crtc(dev, crtc, encoder)
3419 encoder->enable(encoder);
0b8765c6 3420}
79e53945 3421
0b8765c6
JB		 3422static void i9xx_crtc_disable(struct drm_crtc *crtc)
3423{
3424 struct drm_device *dev = crtc->dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3427 struct intel_encoder *encoder;
0b8765c6
JB		 3428 int pipe = intel_crtc->pipe;
3429 int plane = intel_crtc->plane;
b690e96c 3430
ef9c3aee
DV		 3431 /* XXX: For compatability with the crtc helper code, call the encoder's
3432 * disable function unconditionally for now. */
fa5c73b1
DV		 3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->disable(encoder);
ef9c3aee 3435
f7abfe8b
CW		 3436 if (!intel_crtc->active)
3437 return;
3438
0b8765c6 3439 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3440 intel_crtc_wait_for_pending_flips(crtc);
3441 drm_vblank_off(dev, pipe);
0b8765c6 3442 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3443 intel_crtc_update_cursor(crtc, false);
0b8765c6 3444
973d04f9
CW		 3445 if (dev_priv->cfb_plane == plane)
3446 intel_disable_fbc(dev);
79e53945 3447
b24e7179 3448 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3449 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3450 intel_disable_pll(dev_priv, pipe);
0b8765c6 3451
f7abfe8b 3452 intel_crtc->active = false;
6b383a7f
CW		 3453 intel_update_fbc(dev);
3454 intel_update_watermarks(dev);
0b8765c6
JB		 3455}
3456
ee7b9f93
JB		 3457static void i9xx_crtc_off(struct drm_crtc *crtc)
3458{
3459}
3460
2c07245f
ZW		 3461/**
3462 * Sets the power management mode of the pipe and plane.
2c07245f 3463 */
b2cabb0e 3464void intel_crtc_update_dpms(struct drm_crtc *crtc)
2c07245f
ZW		 3465{
3466 struct drm_device *dev = crtc->dev;
e70236a8 3467 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3468 struct drm_i915_master_private *master_priv;
3469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b2cabb0e 3470 struct intel_encoder *intel_encoder;
2c07245f 3471 int pipe = intel_crtc->pipe;
b2cabb0e
DV		 3472 bool enabled, enable = false;
3473 int mode;
3474
3475 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3476 enable |= intel_encoder->connectors_active;
3477
3478 mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
2c07245f 3479
032d2a0d
CW		 3480 if (intel_crtc->dpms_mode == mode)
3481 return;
3482
65655d4a 3483 intel_crtc->dpms_mode = mode;
debcaddc 3484
b2cabb0e 3485 if (enable)
76e5a89c 3486 dev_priv->display.crtc_enable(crtc);
b2cabb0e 3487 else
76e5a89c 3488 dev_priv->display.crtc_disable(crtc);
79e53945
JB		 3489
3490 if (!dev->primary->master)
3491 return;
3492
3493 master_priv = dev->primary->master->driver_priv;
3494 if (!master_priv->sarea_priv)
3495 return;
3496
b2cabb0e 3497 enabled = crtc->enabled && enable;
79e53945
JB		 3498
3499 switch (pipe) {
3500 case 0:
3501 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3502 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3503 break;
3504 case 1:
3505 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3506 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3507 break;
3508 default:
9db4a9c7 3509 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3510 break;
3511 }
79e53945
JB		 3512}
3513
cdd59983
CW		 3514static void intel_crtc_disable(struct drm_crtc *crtc)
3515{
cdd59983 3516 struct drm_device *dev = crtc->dev;
ee7b9f93 3517 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3518
b2cabb0e
DV		 3519 /* crtc->disable is only called when we have no encoders, hence this
3520 * will disable the pipe. */
3521 intel_crtc_update_dpms(crtc);
ee7b9f93
JB		 3522 dev_priv->display.off(crtc);
3523
931872fc
CW		 3524 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3525 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3526
3527 if (crtc->fb) {
3528 mutex_lock(&dev->struct_mutex);
1690e1eb 3529 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3530 mutex_unlock(&dev->struct_mutex);
3531 }
3532}
3533
5ab432ef
DV		 3534void intel_encoder_disable(struct drm_encoder *encoder)
3535{
3536 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3537
3538 intel_encoder->disable(intel_encoder);
3539}
3540
ea5b213a
CW		 3541void intel_encoder_destroy(struct drm_encoder *encoder)
3542{
4ef69c7a 3543 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3544
ea5b213a
CW		 3545 drm_encoder_cleanup(encoder);
3546 kfree(intel_encoder);
3547}
3548
5ab432ef
DV		 3549/* Simple dpms helper for encodres with just one connector, no cloning and only
3550 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3551 * state of the entire output pipe. */
3552void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3553{
3554 if (mode == DRM_MODE_DPMS_ON) {
3555 encoder->connectors_active = true;
3556
b2cabb0e 3557 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3558 } else {
3559 encoder->connectors_active = false;
3560
b2cabb0e 3561 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3562 }
3563}
3564
0a91ca29
DV		 3565/* Cross check the actual hw state with our own modeset state tracking (and it's
3566 * internal consistency). */
3567void intel_connector_check_state(struct intel_connector *connector)
3568{
3569 if (connector->get_hw_state(connector)) {
3570 struct intel_encoder *encoder = connector->encoder;
3571 struct drm_crtc *crtc;
3572 bool encoder_enabled;
3573 enum pipe pipe;
3574
3575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3576 connector->base.base.id,
3577 drm_get_connector_name(&connector->base));
3578
3579 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3580 "wrong connector dpms state\n");
3581 WARN(connector->base.encoder != &encoder->base,
3582 "active connector not linked to encoder\n");
3583 WARN(!encoder->connectors_active,
3584 "encoder->connectors_active not set\n");
3585
3586 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3587 WARN(!encoder_enabled, "encoder not enabled\n");
3588 if (WARN_ON(!encoder->base.crtc))
3589 return;
3590
3591 crtc = encoder->base.crtc;
3592
3593 WARN(!crtc->enabled, "crtc not enabled\n");
3594 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3595 WARN(pipe != to_intel_crtc(crtc)->pipe,
3596 "encoder active on the wrong pipe\n");
3597 }
3598}
3599
5ab432ef
DV		 3600/* Even simpler default implementation, if there's really no special case to
3601 * consider. */
3602void intel_connector_dpms(struct drm_connector *connector, int mode)
3603{
3604 struct intel_encoder *encoder = intel_attached_encoder(connector);
3605
3606 /* All the simple cases only support two dpms states. */
3607 if (mode != DRM_MODE_DPMS_ON)
3608 mode = DRM_MODE_DPMS_OFF;
3609
3610 if (mode == connector->dpms)
3611 return;
3612
3613 connector->dpms = mode;
3614
3615 /* Only need to change hw state when actually enabled */
3616 if (encoder->base.crtc)
3617 intel_encoder_dpms(encoder, mode);
3618 else
3619 encoder->connectors_active = false;
0a91ca29
DV		 3620
3621 intel_connector_check_state(to_intel_connector(connector));
5ab432ef
DV		 3622}
3623
f0947c37
DV		 3624/* Simple connector->get_hw_state implementation for encoders that support only
3625 * one connector and no cloning and hence the encoder state determines the state
3626 * of the connector. */
3627bool intel_connector_get_hw_state(struct intel_connector *connector)
3628{
24929352 3629 enum pipe pipe = 0;
f0947c37
DV		 3630 struct intel_encoder *encoder = connector->encoder;
3631
3632 return encoder->get_hw_state(encoder, &pipe);
3633}
3634
79e53945 3635static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3636 const struct drm_display_mode *mode,
79e53945
JB		 3637 struct drm_display_mode *adjusted_mode)
3638{
2c07245f 3639 struct drm_device *dev = crtc->dev;
89749350 3640
bad720ff 3641 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3642 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3643 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3644 return false;
2c07245f 3645 }
89749350 3646
f9bef081
DV		 3647 /* All interlaced capable intel hw wants timings in frames. Note though
3648 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3649 * timings, so we need to be careful not to clobber these.*/
3650 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3651 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3652
79e53945
JB		 3653 return true;
3654}
3655
25eb05fc
JB		 3656static int valleyview_get_display_clock_speed(struct drm_device *dev)
3657{
3658 return 400000; /* FIXME */
3659}
3660
e70236a8
JB		 3661static int i945_get_display_clock_speed(struct drm_device *dev)
3662{
3663 return 400000;
3664}
79e53945 3665
e70236a8 3666static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3667{
e70236a8
JB		 3668 return 333000;
3669}
79e53945 3670
e70236a8
JB		 3671static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3672{
3673 return 200000;
3674}
79e53945 3675
e70236a8
JB		 3676static int i915gm_get_display_clock_speed(struct drm_device *dev)
3677{
3678 u16 gcfgc = 0;
79e53945 3679
e70236a8
JB		 3680 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3681
3682 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3683 return 133000;
3684 else {
3685 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3686 case GC_DISPLAY_CLOCK_333_MHZ:
3687 return 333000;
3688 default:
3689 case GC_DISPLAY_CLOCK_190_200_MHZ:
3690 return 190000;
79e53945 3691 }
e70236a8
JB		 3692 }
3693}
3694
3695static int i865_get_display_clock_speed(struct drm_device *dev)
3696{
3697 return 266000;
3698}
3699
3700static int i855_get_display_clock_speed(struct drm_device *dev)
3701{
3702 u16 hpllcc = 0;
3703 /* Assume that the hardware is in the high speed state. This
3704 * should be the default.
3705 */
3706 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3707 case GC_CLOCK_133_200:
3708 case GC_CLOCK_100_200:
3709 return 200000;
3710 case GC_CLOCK_166_250:
3711 return 250000;
3712 case GC_CLOCK_100_133:
79e53945 3713 return 133000;
e70236a8 3714 }
79e53945 3715
e70236a8
JB		 3716 /* Shouldn't happen */
3717 return 0;
3718}
79e53945 3719
e70236a8
JB		 3720static int i830_get_display_clock_speed(struct drm_device *dev)
3721{
3722 return 133000;
79e53945
JB		 3723}
3724
2c07245f
ZW		 3725struct fdi_m_n {
3726 u32 tu;
3727 u32 gmch_m;
3728 u32 gmch_n;
3729 u32 link_m;
3730 u32 link_n;
3731};
3732
3733static void
3734fdi_reduce_ratio(u32 *num, u32 *den)
3735{
3736 while (*num > 0xffffff || *den > 0xffffff) {
3737 *num >>= 1;
3738 *den >>= 1;
3739 }
3740}
3741
2c07245f 3742static void
f2b115e6
AJ		 3743ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3744 int link_clock, struct fdi_m_n *m_n)
2c07245f 3745{
2c07245f
ZW		 3746 m_n->tu = 64; /* default size */
3747
22ed1113
CW		 3748 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3749 m_n->gmch_m = bits_per_pixel * pixel_clock;
3750 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3751 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3752
22ed1113
CW		 3753 m_n->link_m = pixel_clock;
3754 m_n->link_n = link_clock;
2c07245f
ZW		 3755 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3756}
3757
a7615030
CW		 3758static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3759{
72bbe58c
KP		 3760 if (i915_panel_use_ssc >= 0)
3761 return i915_panel_use_ssc != 0;
3762 return dev_priv->lvds_use_ssc
435793df 3763 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3764}
3765
5a354204
JB		 3766/**
3767 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3768 * @crtc: CRTC structure
3b5c78a3 3769 * @mode: requested mode
5a354204
JB		 3770 *
3771 * A pipe may be connected to one or more outputs. Based on the depth of the
3772 * attached framebuffer, choose a good color depth to use on the pipe.
3773 *
3774 * If possible, match the pipe depth to the fb depth. In some cases, this
3775 * isn't ideal, because the connected output supports a lesser or restricted
3776 * set of depths. Resolve that here:
3777 * LVDS typically supports only 6bpc, so clamp down in that case
3778 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3779 * Displays may support a restricted set as well, check EDID and clamp as
3780 * appropriate.
3b5c78a3 3781 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3782 *
3783 * RETURNS:
3784 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3785 * true if they don't match).
3786 */
3787static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3788 unsigned int *pipe_bpp,
3789 struct drm_display_mode *mode)
5a354204
JB		 3790{
3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3793 struct drm_connector *connector;
6c2b7c12 3794 struct intel_encoder *intel_encoder;
5a354204
JB		 3795 unsigned int display_bpc = UINT_MAX, bpc;
3796
3797 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3798 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3799
3800 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3801 unsigned int lvds_bpc;
3802
3803 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3804 LVDS_A3_POWER_UP)
3805 lvds_bpc = 8;
3806 else
3807 lvds_bpc = 6;
3808
3809 if (lvds_bpc < display_bpc) {
82820490 3810 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3811 display_bpc = lvds_bpc;
3812 }
3813 continue;
3814 }
3815
5a354204
JB		 3816 /* Not one of the known troublemakers, check the EDID */
3817 list_for_each_entry(connector, &dev->mode_config.connector_list,
3818 head) {
6c2b7c12 3819 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3820 continue;
3821
62ac41a6
JB		 3822 /* Don't use an invalid EDID bpc value */
3823 if (connector->display_info.bpc &&
3824 connector->display_info.bpc < display_bpc) {
82820490 3825 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3826 display_bpc = connector->display_info.bpc;
3827 }
3828 }
3829
3830 /*
3831 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3832 * through, clamp it down. (Note: >12bpc will be caught below.)
3833 */
3834 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3835 if (display_bpc > 8 && display_bpc < 12) {
82820490 3836 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3837 display_bpc = 12;
3838 } else {
82820490 3839 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3840 display_bpc = 8;
3841 }
3842 }
3843 }
3844
3b5c78a3
AJ		 3845 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3846 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3847 display_bpc = 6;
3848 }
3849
5a354204
JB		 3850 /*
3851 * We could just drive the pipe at the highest bpc all the time and
3852 * enable dithering as needed, but that costs bandwidth. So choose
3853 * the minimum value that expresses the full color range of the fb but
3854 * also stays within the max display bpc discovered above.
3855 */
3856
3857 switch (crtc->fb->depth) {
3858 case 8:
3859 bpc = 8; /* since we go through a colormap */
3860 break;
3861 case 15:
3862 case 16:
3863 bpc = 6; /* min is 18bpp */
3864 break;
3865 case 24:
578393cd 3866 bpc = 8;
5a354204
JB		 3867 break;
3868 case 30:
578393cd 3869 bpc = 10;
5a354204
JB		 3870 break;
3871 case 48:
578393cd 3872 bpc = 12;
5a354204
JB		 3873 break;
3874 default:
3875 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3876 bpc = min((unsigned int)8, display_bpc);
3877 break;
3878 }
3879
578393cd
KP		 3880 display_bpc = min(display_bpc, bpc);
3881
82820490
AJ		 3882 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3883 bpc, display_bpc);
5a354204 3884
578393cd 3885 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3886
3887 return display_bpc != bpc;
3888}
3889
a0c4da24
JB		 3890static int vlv_get_refclk(struct drm_crtc *crtc)
3891{
3892 struct drm_device *dev = crtc->dev;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 int refclk = 27000; /* for DP & HDMI */
3895
3896 return 100000; /* only one validated so far */
3897
3898 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3899 refclk = 96000;
3900 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3901 if (intel_panel_use_ssc(dev_priv))
3902 refclk = 100000;
3903 else
3904 refclk = 96000;
3905 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3906 refclk = 100000;
3907 }
3908
3909 return refclk;
3910}
3911
c65d77d8
JB		 3912static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3913{
3914 struct drm_device *dev = crtc->dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916 int refclk;
3917
a0c4da24
JB		 3918 if (IS_VALLEYVIEW(dev)) {
3919 refclk = vlv_get_refclk(crtc);
3920 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3921 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3922 refclk = dev_priv->lvds_ssc_freq * 1000;
3923 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3924 refclk / 1000);
3925 } else if (!IS_GEN2(dev)) {
3926 refclk = 96000;
3927 } else {
3928 refclk = 48000;
3929 }
3930
3931 return refclk;
3932}
3933
3934static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3935 intel_clock_t *clock)
3936{
3937 /* SDVO TV has fixed PLL values depend on its clock range,
3938 this mirrors vbios setting. */
3939 if (adjusted_mode->clock >= 100000
3940 && adjusted_mode->clock < 140500) {
3941 clock->p1 = 2;
3942 clock->p2 = 10;
3943 clock->n = 3;
3944 clock->m1 = 16;
3945 clock->m2 = 8;
3946 } else if (adjusted_mode->clock >= 140500
3947 && adjusted_mode->clock <= 200000) {
3948 clock->p1 = 1;
3949 clock->p2 = 10;
3950 clock->n = 6;
3951 clock->m1 = 12;
3952 clock->m2 = 8;
3953 }
3954}
3955
a7516a05
JB		 3956static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3957 intel_clock_t *clock,
3958 intel_clock_t *reduced_clock)
3959{
3960 struct drm_device *dev = crtc->dev;
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3963 int pipe = intel_crtc->pipe;
3964 u32 fp, fp2 = 0;
3965
3966 if (IS_PINEVIEW(dev)) {
3967 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3968 if (reduced_clock)
3969 fp2 = (1 << reduced_clock->n) << 16 |
3970 reduced_clock->m1 << 8 | reduced_clock->m2;
3971 } else {
3972 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3973 if (reduced_clock)
3974 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3975 reduced_clock->m2;
3976 }
3977
3978 I915_WRITE(FP0(pipe), fp);
3979
3980 intel_crtc->lowfreq_avail = false;
3981 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3982 reduced_clock && i915_powersave) {
3983 I915_WRITE(FP1(pipe), fp2);
3984 intel_crtc->lowfreq_avail = true;
3985 } else {
3986 I915_WRITE(FP1(pipe), fp);
3987 }
3988}
3989
93e537a1
DV		 3990static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3991 struct drm_display_mode *adjusted_mode)
3992{
3993 struct drm_device *dev = crtc->dev;
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 int pipe = intel_crtc->pipe;
284d5df5 3997 u32 temp;
93e537a1
DV		 3998
3999 temp = I915_READ(LVDS);
4000 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4001 if (pipe == 1) {
4002 temp |= LVDS_PIPEB_SELECT;
4003 } else {
4004 temp &= ~LVDS_PIPEB_SELECT;
4005 }
4006 /* set the corresponsding LVDS_BORDER bit */
4007 temp |= dev_priv->lvds_border_bits;
4008 /* Set the B0-B3 data pairs corresponding to whether we're going to
4009 * set the DPLLs for dual-channel mode or not.
4010 */
4011 if (clock->p2 == 7)
4012 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4013 else
4014 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4015
4016 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4017 * appropriately here, but we need to look more thoroughly into how
4018 * panels behave in the two modes.
4019 */
4020 /* set the dithering flag on LVDS as needed */
4021 if (INTEL_INFO(dev)->gen >= 4) {
4022 if (dev_priv->lvds_dither)
4023 temp |= LVDS_ENABLE_DITHER;
4024 else
4025 temp &= ~LVDS_ENABLE_DITHER;
4026 }
284d5df5 4027 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4028 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4029 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4030 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4031 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4032 I915_WRITE(LVDS, temp);
4033}
4034
a0c4da24
JB		 4035static void vlv_update_pll(struct drm_crtc *crtc,
4036 struct drm_display_mode *mode,
4037 struct drm_display_mode *adjusted_mode,
4038 intel_clock_t *clock, intel_clock_t *reduced_clock,
4039 int refclk, int num_connectors)
4040{
4041 struct drm_device *dev = crtc->dev;
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4044 int pipe = intel_crtc->pipe;
4045 u32 dpll, mdiv, pdiv;
4046 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4047 bool is_hdmi;
4048
4049 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4050
4051 bestn = clock->n;
4052 bestm1 = clock->m1;
4053 bestm2 = clock->m2;
4054 bestp1 = clock->p1;
4055 bestp2 = clock->p2;
4056
4057 /* Enable DPIO clock input */
4058 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4059 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4060 I915_WRITE(DPLL(pipe), dpll);
4061 POSTING_READ(DPLL(pipe));
4062
4063 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4064 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4065 mdiv |= ((bestn << DPIO_N_SHIFT));
4066 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4067 mdiv |= (1 << DPIO_K_SHIFT);
4068 mdiv |= DPIO_ENABLE_CALIBRATION;
4069 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4070
4071 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4072
4073 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4074 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4075 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4076 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4077
4078 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4079
4080 dpll |= DPLL_VCO_ENABLE;
4081 I915_WRITE(DPLL(pipe), dpll);
4082 POSTING_READ(DPLL(pipe));
4083 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4084 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4085
4086 if (is_hdmi) {
4087 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4088
4089 if (temp > 1)
4090 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4091 else
4092 temp = 0;
4093
4094 I915_WRITE(DPLL_MD(pipe), temp);
4095 POSTING_READ(DPLL_MD(pipe));
4096 }
4097
4098 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4099}
4100
eb1cbe48
DV		 4101static void i9xx_update_pll(struct drm_crtc *crtc,
4102 struct drm_display_mode *mode,
4103 struct drm_display_mode *adjusted_mode,
4104 intel_clock_t *clock, intel_clock_t *reduced_clock,
4105 int num_connectors)
4106{
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4110 int pipe = intel_crtc->pipe;
4111 u32 dpll;
4112 bool is_sdvo;
4113
4114 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4115 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4116
4117 dpll = DPLL_VGA_MODE_DIS;
4118
4119 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4120 dpll |= DPLLB_MODE_LVDS;
4121 else
4122 dpll |= DPLLB_MODE_DAC_SERIAL;
4123 if (is_sdvo) {
4124 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4125 if (pixel_multiplier > 1) {
4126 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4127 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4128 }
4129 dpll |= DPLL_DVO_HIGH_SPEED;
4130 }
4131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4132 dpll |= DPLL_DVO_HIGH_SPEED;
4133
4134 /* compute bitmask from p1 value */
4135 if (IS_PINEVIEW(dev))
4136 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4137 else {
4138 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4139 if (IS_G4X(dev) && reduced_clock)
4140 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4141 }
4142 switch (clock->p2) {
4143 case 5:
4144 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4145 break;
4146 case 7:
4147 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4148 break;
4149 case 10:
4150 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4151 break;
4152 case 14:
4153 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4154 break;
4155 }
4156 if (INTEL_INFO(dev)->gen >= 4)
4157 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4158
4159 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4160 dpll |= PLL_REF_INPUT_TVCLKINBC;
4161 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4162 /* XXX: just matching BIOS for now */
4163 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4164 dpll |= 3;
4165 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4166 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4167 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4168 else
4169 dpll |= PLL_REF_INPUT_DREFCLK;
4170
4171 dpll |= DPLL_VCO_ENABLE;
4172 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4173 POSTING_READ(DPLL(pipe));
4174 udelay(150);
4175
4176 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4177 * This is an exception to the general rule that mode_set doesn't turn
4178 * things on.
4179 */
4180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4181 intel_update_lvds(crtc, clock, adjusted_mode);
4182
4183 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4184 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4185
4186 I915_WRITE(DPLL(pipe), dpll);
4187
4188 /* Wait for the clocks to stabilize. */
4189 POSTING_READ(DPLL(pipe));
4190 udelay(150);
4191
4192 if (INTEL_INFO(dev)->gen >= 4) {
4193 u32 temp = 0;
4194 if (is_sdvo) {
4195 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4196 if (temp > 1)
4197 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4198 else
4199 temp = 0;
4200 }
4201 I915_WRITE(DPLL_MD(pipe), temp);
4202 } else {
4203 /* The pixel multiplier can only be updated once the
4204 * DPLL is enabled and the clocks are stable.
4205 *
4206 * So write it again.
4207 */
4208 I915_WRITE(DPLL(pipe), dpll);
4209 }
4210}
4211
4212static void i8xx_update_pll(struct drm_crtc *crtc,
4213 struct drm_display_mode *adjusted_mode,
4214 intel_clock_t *clock,
4215 int num_connectors)
4216{
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220 int pipe = intel_crtc->pipe;
4221 u32 dpll;
4222
4223 dpll = DPLL_VGA_MODE_DIS;
4224
4225 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4226 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4227 } else {
4228 if (clock->p1 == 2)
4229 dpll |= PLL_P1_DIVIDE_BY_TWO;
4230 else
4231 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4232 if (clock->p2 == 4)
4233 dpll |= PLL_P2_DIVIDE_BY_4;
4234 }
4235
4236 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4237 /* XXX: just matching BIOS for now */
4238 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4239 dpll |= 3;
4240 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4241 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4242 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4243 else
4244 dpll |= PLL_REF_INPUT_DREFCLK;
4245
4246 dpll |= DPLL_VCO_ENABLE;
4247 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4248 POSTING_READ(DPLL(pipe));
4249 udelay(150);
4250
4251 I915_WRITE(DPLL(pipe), dpll);
4252
4253 /* Wait for the clocks to stabilize. */
4254 POSTING_READ(DPLL(pipe));
4255 udelay(150);
4256
4257 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4258 * This is an exception to the general rule that mode_set doesn't turn
4259 * things on.
4260 */
4261 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4262 intel_update_lvds(crtc, clock, adjusted_mode);
4263
4264 /* The pixel multiplier can only be updated once the
4265 * DPLL is enabled and the clocks are stable.
4266 *
4267 * So write it again.
4268 */
4269 I915_WRITE(DPLL(pipe), dpll);
4270}
4271
f564048e
EA		 4272static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4273 struct drm_display_mode *mode,
4274 struct drm_display_mode *adjusted_mode,
4275 int x, int y,
4276 struct drm_framebuffer *old_fb)
79e53945
JB		 4277{
4278 struct drm_device *dev = crtc->dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4281 int pipe = intel_crtc->pipe;
80824003 4282 int plane = intel_crtc->plane;
c751ce4f 4283 int refclk, num_connectors = 0;
652c393a 4284 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4285 u32 dspcntr, pipeconf, vsyncshift;
4286 bool ok, has_reduced_clock = false, is_sdvo = false;
4287 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4288 struct intel_encoder *encoder;
d4906093 4289 const intel_limit_t *limit;
5c3b82e2 4290 int ret;
79e53945 4291
6c2b7c12 4292 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4293 switch (encoder->type) {
79e53945
JB		 4294 case INTEL_OUTPUT_LVDS:
4295 is_lvds = true;
4296 break;
4297 case INTEL_OUTPUT_SDVO:
7d57382e 4298 case INTEL_OUTPUT_HDMI:
79e53945 4299 is_sdvo = true;
5eddb70b 4300 if (encoder->needs_tv_clock)
e2f0ba97 4301 is_tv = true;
79e53945 4302 break;
79e53945
JB		 4303 case INTEL_OUTPUT_TVOUT:
4304 is_tv = true;
4305 break;
a4fc5ed6
KP		 4306 case INTEL_OUTPUT_DISPLAYPORT:
4307 is_dp = true;
4308 break;
79e53945 4309 }
43565a06 4310
c751ce4f 4311 num_connectors++;
79e53945
JB		 4312 }
4313
c65d77d8 4314 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4315
d4906093
ML		 4316 /*
4317 * Returns a set of divisors for the desired target clock with the given
4318 * refclk, or FALSE. The returned values represent the clock equation:
4319 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4320 */
1b894b59 4321 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4322 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4323 &clock);
79e53945
JB		 4324 if (!ok) {
4325 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4326 return -EINVAL;
79e53945
JB		 4327 }
4328
cda4b7d3 4329 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4330 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4331
ddc9003c 4332 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4333 /*
4334 * Ensure we match the reduced clock's P to the target clock.
4335 * If the clocks don't match, we can't switch the display clock
4336 * by using the FP0/FP1. In such case we will disable the LVDS
4337 * downclock feature.
4338 */
ddc9003c 4339 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4340 dev_priv->lvds_downclock,
4341 refclk,
cec2f356 4342 &clock,
5eddb70b 4343 &reduced_clock);
7026d4ac
ZW		 4344 }
4345
c65d77d8
JB		 4346 if (is_sdvo && is_tv)
4347 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4348
a7516a05
JB		 4349 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4350 &reduced_clock : NULL);
79e53945 4351
eb1cbe48
DV		 4352 if (IS_GEN2(dev))
4353 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4354 else if (IS_VALLEYVIEW(dev))
4355 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4356 refclk, num_connectors);
79e53945 4357 else
eb1cbe48
DV		 4358 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4359 has_reduced_clock ? &reduced_clock : NULL,
4360 num_connectors);
79e53945
JB		 4361
4362 /* setup pipeconf */
5eddb70b 4363 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4364
4365 /* Set up the display plane register */
4366 dspcntr = DISPPLANE_GAMMA_ENABLE;
4367
929c77fb
EA		 4368 if (pipe == 0)
4369 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4370 else
4371 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4372
a6c45cf0 4373 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4374 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4375 * core speed.
4376 *
4377 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4378 * pipe == 0 check?
4379 */
e70236a8
JB		 4380 if (mode->clock >
4381 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4382 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4383 else
5eddb70b 4384 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4385 }
4386
3b5c78a3
AJ		 4387 /* default to 8bpc */
4388 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4389 if (is_dp) {
4390 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4391 pipeconf |= PIPECONF_BPP_6 |
4392 PIPECONF_DITHER_EN |
4393 PIPECONF_DITHER_TYPE_SP;
4394 }
4395 }
4396
28c97730 4397 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4398 drm_mode_debug_printmodeline(mode);
4399
a7516a05
JB		 4400 if (HAS_PIPE_CXSR(dev)) {
4401 if (intel_crtc->lowfreq_avail) {
28c97730 4402 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4403 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4404 } else {
28c97730 4405 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4406 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4407 }
4408 }
4409
617cf884 4410 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4411 if (!IS_GEN2(dev) &&
4412 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4413 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4414 /* the chip adds 2 halflines automatically */
734b4157 4415 adjusted_mode->crtc_vtotal -= 1;
734b4157 4416 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4417 vsyncshift = adjusted_mode->crtc_hsync_start
4418 - adjusted_mode->crtc_htotal/2;
4419 } else {
617cf884 4420 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4421 vsyncshift = 0;
4422 }
4423
4424 if (!IS_GEN3(dev))
4425 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4426
5eddb70b
CW		 4427 I915_WRITE(HTOTAL(pipe),
4428 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4429 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4430 I915_WRITE(HBLANK(pipe),
4431 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4432 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4433 I915_WRITE(HSYNC(pipe),
4434 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4435 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4436
4437 I915_WRITE(VTOTAL(pipe),
4438 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4439 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4440 I915_WRITE(VBLANK(pipe),
4441 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4442 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4443 I915_WRITE(VSYNC(pipe),
4444 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4445 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4446
4447 /* pipesrc and dspsize control the size that is scaled from,
4448 * which should always be the user's requested size.
79e53945 4449 */
929c77fb
EA		 4450 I915_WRITE(DSPSIZE(plane),
4451 ((mode->vdisplay - 1) << 16) |
4452 (mode->hdisplay - 1));
4453 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4454 I915_WRITE(PIPESRC(pipe),
4455 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4456
f564048e
EA		 4457 I915_WRITE(PIPECONF(pipe), pipeconf);
4458 POSTING_READ(PIPECONF(pipe));
929c77fb 4459 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4460
4461 intel_wait_for_vblank(dev, pipe);
4462
f564048e
EA		 4463 I915_WRITE(DSPCNTR(plane), dspcntr);
4464 POSTING_READ(DSPCNTR(plane));
4465
4466 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4467
4468 intel_update_watermarks(dev);
4469
f564048e
EA		 4470 return ret;
4471}
4472
9fb526db
KP		 4473/*
4474 * Initialize reference clocks when the driver loads
4475 */
4476void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4477{
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4480 struct intel_encoder *encoder;
13d83a67
JB		 4481 u32 temp;
4482 bool has_lvds = false;
199e5d79
KP		 4483 bool has_cpu_edp = false;
4484 bool has_pch_edp = false;
4485 bool has_panel = false;
99eb6a01
KP		 4486 bool has_ck505 = false;
4487 bool can_ssc = false;
13d83a67
JB		 4488
4489 /* We need to take the global config into account */
199e5d79
KP		 4490 list_for_each_entry(encoder, &mode_config->encoder_list,
4491 base.head) {
4492 switch (encoder->type) {
4493 case INTEL_OUTPUT_LVDS:
4494 has_panel = true;
4495 has_lvds = true;
4496 break;
4497 case INTEL_OUTPUT_EDP:
4498 has_panel = true;
4499 if (intel_encoder_is_pch_edp(&encoder->base))
4500 has_pch_edp = true;
4501 else
4502 has_cpu_edp = true;
4503 break;
13d83a67
JB		 4504 }
4505 }
4506
99eb6a01
KP		 4507 if (HAS_PCH_IBX(dev)) {
4508 has_ck505 = dev_priv->display_clock_mode;
4509 can_ssc = has_ck505;
4510 } else {
4511 has_ck505 = false;
4512 can_ssc = true;
4513 }
4514
4515 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4516 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4517 has_ck505);
13d83a67
JB		 4518
4519 /* Ironlake: try to setup display ref clock before DPLL
4520 * enabling. This is only under driver's control after
4521 * PCH B stepping, previous chipset stepping should be
4522 * ignoring this setting.
4523 */
4524 temp = I915_READ(PCH_DREF_CONTROL);
4525 /* Always enable nonspread source */
4526 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4527
99eb6a01
KP		 4528 if (has_ck505)
4529 temp |= DREF_NONSPREAD_CK505_ENABLE;
4530 else
4531 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4532
199e5d79
KP		 4533 if (has_panel) {
4534 temp &= ~DREF_SSC_SOURCE_MASK;
4535 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4536
199e5d79 4537 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4538 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4539 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4540 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4541 } else
4542 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4543
4544 /* Get SSC going before enabling the outputs */
4545 I915_WRITE(PCH_DREF_CONTROL, temp);
4546 POSTING_READ(PCH_DREF_CONTROL);
4547 udelay(200);
4548
13d83a67
JB		 4549 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4550
4551 /* Enable CPU source on CPU attached eDP */
199e5d79 4552 if (has_cpu_edp) {
99eb6a01 4553 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4554 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4555 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4556 }
13d83a67
JB		 4557 else
4558 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4559 } else
4560 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4561
4562 I915_WRITE(PCH_DREF_CONTROL, temp);
4563 POSTING_READ(PCH_DREF_CONTROL);
4564 udelay(200);
4565 } else {
4566 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4567
4568 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4569
4570 /* Turn off CPU output */
4571 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4572
4573 I915_WRITE(PCH_DREF_CONTROL, temp);
4574 POSTING_READ(PCH_DREF_CONTROL);
4575 udelay(200);
4576
4577 /* Turn off the SSC source */
4578 temp &= ~DREF_SSC_SOURCE_MASK;
4579 temp |= DREF_SSC_SOURCE_DISABLE;
4580
4581 /* Turn off SSC1 */
4582 temp &= ~ DREF_SSC1_ENABLE;
4583
13d83a67
JB		 4584 I915_WRITE(PCH_DREF_CONTROL, temp);
4585 POSTING_READ(PCH_DREF_CONTROL);
4586 udelay(200);
4587 }
4588}
4589
d9d444cb
JB		 4590static int ironlake_get_refclk(struct drm_crtc *crtc)
4591{
4592 struct drm_device *dev = crtc->dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 struct intel_encoder *encoder;
d9d444cb
JB		 4595 struct intel_encoder *edp_encoder = NULL;
4596 int num_connectors = 0;
4597 bool is_lvds = false;
4598
6c2b7c12 4599 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4600 switch (encoder->type) {
4601 case INTEL_OUTPUT_LVDS:
4602 is_lvds = true;
4603 break;
4604 case INTEL_OUTPUT_EDP:
4605 edp_encoder = encoder;
4606 break;
4607 }
4608 num_connectors++;
4609 }
4610
4611 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4612 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4613 dev_priv->lvds_ssc_freq);
4614 return dev_priv->lvds_ssc_freq * 1000;
4615 }
4616
4617 return 120000;
4618}
4619
f564048e
EA		 4620static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4621 struct drm_display_mode *mode,
4622 struct drm_display_mode *adjusted_mode,
4623 int x, int y,
4624 struct drm_framebuffer *old_fb)
79e53945
JB		 4625{
4626 struct drm_device *dev = crtc->dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 int pipe = intel_crtc->pipe;
80824003 4630 int plane = intel_crtc->plane;
c751ce4f 4631 int refclk, num_connectors = 0;
652c393a 4632 intel_clock_t clock, reduced_clock;
5eddb70b 4633 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4634 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4635 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4636 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4637 const intel_limit_t *limit;
5c3b82e2 4638 int ret;
2c07245f 4639 struct fdi_m_n m_n = {0};
fae14981 4640 u32 temp;
5a354204
JB		 4641 int target_clock, pixel_multiplier, lane, link_bw, factor;
4642 unsigned int pipe_bpp;
4643 bool dither;
e3aef172 4644 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4645
6c2b7c12 4646 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4647 switch (encoder->type) {
79e53945
JB		 4648 case INTEL_OUTPUT_LVDS:
4649 is_lvds = true;
4650 break;
4651 case INTEL_OUTPUT_SDVO:
7d57382e 4652 case INTEL_OUTPUT_HDMI:
79e53945 4653 is_sdvo = true;
5eddb70b 4654 if (encoder->needs_tv_clock)
e2f0ba97 4655 is_tv = true;
79e53945 4656 break;
79e53945
JB		 4657 case INTEL_OUTPUT_TVOUT:
4658 is_tv = true;
4659 break;
4660 case INTEL_OUTPUT_ANALOG:
4661 is_crt = true;
4662 break;
a4fc5ed6
KP		 4663 case INTEL_OUTPUT_DISPLAYPORT:
4664 is_dp = true;
4665 break;
32f9d658 4666 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4667 is_dp = true;
4668 if (intel_encoder_is_pch_edp(&encoder->base))
4669 is_pch_edp = true;
4670 else
4671 is_cpu_edp = true;
4672 edp_encoder = encoder;
32f9d658 4673 break;
79e53945 4674 }
43565a06 4675
c751ce4f 4676 num_connectors++;
79e53945
JB		 4677 }
4678
d9d444cb 4679 refclk = ironlake_get_refclk(crtc);
79e53945 4680
d4906093
ML		 4681 /*
4682 * Returns a set of divisors for the desired target clock with the given
4683 * refclk, or FALSE. The returned values represent the clock equation:
4684 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4685 */
1b894b59 4686 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4687 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4688 &clock);
79e53945
JB		 4689 if (!ok) {
4690 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4691 return -EINVAL;
79e53945
JB		 4692 }
4693
cda4b7d3 4694 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4695 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4696
ddc9003c 4697 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4698 /*
4699 * Ensure we match the reduced clock's P to the target clock.
4700 * If the clocks don't match, we can't switch the display clock
4701 * by using the FP0/FP1. In such case we will disable the LVDS
4702 * downclock feature.
4703 */
ddc9003c 4704 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4705 dev_priv->lvds_downclock,
4706 refclk,
cec2f356 4707 &clock,
5eddb70b 4708 &reduced_clock);
652c393a 4709 }
61e9653f
DV		 4710
4711 if (is_sdvo && is_tv)
4712 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4713
7026d4ac 4714
2c07245f 4715 /* FDI link */
8febb297
EA		 4716 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4717 lane = 0;
4718 /* CPU eDP doesn't require FDI link, so just set DP M/N
4719 according to current link config */
e3aef172 4720 if (is_cpu_edp) {
e3aef172 4721 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4722 } else {
8febb297
EA		 4723 /* FDI is a binary signal running at ~2.7GHz, encoding
4724 * each output octet as 10 bits. The actual frequency
4725 * is stored as a divider into a 100MHz clock, and the
4726 * mode pixel clock is stored in units of 1KHz.
4727 * Hence the bw of each lane in terms of the mode signal
4728 * is:
4729 */
4730 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4731 }
58a27471 4732
94bf2ced
DV		 4733 /* [e]DP over FDI requires target mode clock instead of link clock. */
4734 if (edp_encoder)
4735 target_clock = intel_edp_target_clock(edp_encoder, mode);
4736 else if (is_dp)
4737 target_clock = mode->clock;
4738 else
4739 target_clock = adjusted_mode->clock;
4740
8febb297
EA		 4741 /* determine panel color depth */
4742 temp = I915_READ(PIPECONF(pipe));
4743 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4744 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4745 switch (pipe_bpp) {
4746 case 18:
4747 temp |= PIPE_6BPC;
8febb297 4748 break;
5a354204
JB		 4749 case 24:
4750 temp |= PIPE_8BPC;
8febb297 4751 break;
5a354204
JB		 4752 case 30:
4753 temp |= PIPE_10BPC;
8febb297 4754 break;
5a354204
JB		 4755 case 36:
4756 temp |= PIPE_12BPC;
8febb297
EA		 4757 break;
4758 default:
62ac41a6
JB		 4759 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4760 pipe_bpp);
5a354204
JB		 4761 temp |= PIPE_8BPC;
4762 pipe_bpp = 24;
4763 break;
8febb297 4764 }
77ffb597 4765
5a354204
JB		 4766 intel_crtc->bpp = pipe_bpp;
4767 I915_WRITE(PIPECONF(pipe), temp);
4768
8febb297
EA		 4769 if (!lane) {
4770 /*
4771 * Account for spread spectrum to avoid
4772 * oversubscribing the link. Max center spread
4773 * is 2.5%; use 5% for safety's sake.
4774 */
5a354204 4775 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4776 lane = bps / (link_bw * 8) + 1;
5eb08b69 4777 }
2c07245f 4778
8febb297
EA		 4779 intel_crtc->fdi_lanes = lane;
4780
4781 if (pixel_multiplier > 1)
4782 link_bw *= pixel_multiplier;
5a354204
JB		 4783 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4784 &m_n);
8febb297 4785
a07d6787
EA		 4786 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4787 if (has_reduced_clock)
4788 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4789 reduced_clock.m2;
79e53945 4790
c1858123 4791 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4792 factor = 21;
4793 if (is_lvds) {
4794 if ((intel_panel_use_ssc(dev_priv) &&
4795 dev_priv->lvds_ssc_freq == 100) ||
4796 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4797 factor = 25;
4798 } else if (is_sdvo && is_tv)
4799 factor = 20;
c1858123 4800
cb0e0931 4801 if (clock.m < factor * clock.n)
8febb297 4802 fp |= FP_CB_TUNE;
2c07245f 4803
5eddb70b 4804 dpll = 0;
2c07245f 4805
a07d6787
EA		 4806 if (is_lvds)
4807 dpll |= DPLLB_MODE_LVDS;
4808 else
4809 dpll |= DPLLB_MODE_DAC_SERIAL;
4810 if (is_sdvo) {
4811 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4812 if (pixel_multiplier > 1) {
4813 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4814 }
a07d6787
EA		 4815 dpll |= DPLL_DVO_HIGH_SPEED;
4816 }
e3aef172 4817 if (is_dp && !is_cpu_edp)
a07d6787 4818 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4819
a07d6787
EA		 4820 /* compute bitmask from p1 value */
4821 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4822 /* also FPA1 */
4823 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4824
4825 switch (clock.p2) {
4826 case 5:
4827 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4828 break;
4829 case 7:
4830 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4831 break;
4832 case 10:
4833 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4834 break;
4835 case 14:
4836 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4837 break;
79e53945
JB		 4838 }
4839
43565a06
KH		 4840 if (is_sdvo && is_tv)
4841 dpll |= PLL_REF_INPUT_TVCLKINBC;
4842 else if (is_tv)
79e53945 4843 /* XXX: just matching BIOS for now */
43565a06 4844 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4845 dpll |= 3;
a7615030 4846 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4847 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4848 else
4849 dpll |= PLL_REF_INPUT_DREFCLK;
4850
4851 /* setup pipeconf */
5eddb70b 4852 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4853
4854 /* Set up the display plane register */
4855 dspcntr = DISPPLANE_GAMMA_ENABLE;
4856
f7cb34d4 4857 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4858 drm_mode_debug_printmodeline(mode);
4859
9d82aa17
ED		 4860 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4861 * pre-Haswell/LPT generation */
4862 if (HAS_PCH_LPT(dev)) {
4863 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4864 pipe);
4865 } else if (!is_cpu_edp) {
ee7b9f93 4866 struct intel_pch_pll *pll;
4b645f14 4867
ee7b9f93
JB		 4868 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4869 if (pll == NULL) {
4870 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4871 pipe);
4b645f14
JB		 4872 return -EINVAL;
4873 }
ee7b9f93
JB		 4874 } else
4875 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4876
4877 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4878 * This is an exception to the general rule that mode_set doesn't turn
4879 * things on.
4880 */
4881 if (is_lvds) {
fae14981 4882 temp = I915_READ(PCH_LVDS);
5eddb70b 4883 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4884 if (HAS_PCH_CPT(dev)) {
4885 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4886 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4887 } else {
4888 if (pipe == 1)
4889 temp |= LVDS_PIPEB_SELECT;
4890 else
4891 temp &= ~LVDS_PIPEB_SELECT;
4892 }
4b645f14 4893
a3e17eb8 4894 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4895 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4896 /* Set the B0-B3 data pairs corresponding to whether we're going to
4897 * set the DPLLs for dual-channel mode or not.
4898 */
4899 if (clock.p2 == 7)
5eddb70b 4900 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4901 else
5eddb70b 4902 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4903
4904 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4905 * appropriately here, but we need to look more thoroughly into how
4906 * panels behave in the two modes.
4907 */
284d5df5 4908 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4909 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4910 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4911 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4912 temp |= LVDS_VSYNC_POLARITY;
fae14981 4913 I915_WRITE(PCH_LVDS, temp);
79e53945 4914 }
434ed097 4915
8febb297
EA		 4916 pipeconf &= ~PIPECONF_DITHER_EN;
4917 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4918 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4919 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4920 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4921 }
e3aef172 4922 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4923 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4924 } else {
8db9d77b 4925 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4926 I915_WRITE(TRANSDATA_M1(pipe), 0);
4927 I915_WRITE(TRANSDATA_N1(pipe), 0);
4928 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4929 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4930 }
79e53945 4931
ee7b9f93
JB		 4932 if (intel_crtc->pch_pll) {
4933 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4934
32f9d658 4935 /* Wait for the clocks to stabilize. */
ee7b9f93 4936 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4937 udelay(150);
4938
8febb297
EA		 4939 /* The pixel multiplier can only be updated once the
4940 * DPLL is enabled and the clocks are stable.
4941 *
4942 * So write it again.
4943 */
ee7b9f93 4944 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4945 }
79e53945 4946
5eddb70b 4947 intel_crtc->lowfreq_avail = false;
ee7b9f93 4948 if (intel_crtc->pch_pll) {
4b645f14 4949 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4950 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4951 intel_crtc->lowfreq_avail = true;
4b645f14 4952 } else {
ee7b9f93 4953 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4954 }
4955 }
4956
617cf884 4957 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4958 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4959 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4960 /* the chip adds 2 halflines automatically */
734b4157 4961 adjusted_mode->crtc_vtotal -= 1;
734b4157 4962 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4963 I915_WRITE(VSYNCSHIFT(pipe),
4964 adjusted_mode->crtc_hsync_start
4965 - adjusted_mode->crtc_htotal/2);
4966 } else {
617cf884 4967 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4968 I915_WRITE(VSYNCSHIFT(pipe), 0);
4969 }
734b4157 4970
5eddb70b
CW		 4971 I915_WRITE(HTOTAL(pipe),
4972 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4973 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4974 I915_WRITE(HBLANK(pipe),
4975 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4976 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4977 I915_WRITE(HSYNC(pipe),
4978 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4979 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4980
4981 I915_WRITE(VTOTAL(pipe),
4982 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4983 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4984 I915_WRITE(VBLANK(pipe),
4985 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4986 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4987 I915_WRITE(VSYNC(pipe),
4988 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4989 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4990
8febb297
EA		 4991 /* pipesrc controls the size that is scaled from, which should
4992 * always be the user's requested size.
79e53945 4993 */
5eddb70b
CW		 4994 I915_WRITE(PIPESRC(pipe),
4995 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4996
8febb297
EA		 4997 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4998 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4999 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5000 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5001
e3aef172 5002 if (is_cpu_edp)
8febb297 5003 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5004
5eddb70b
CW		 5005 I915_WRITE(PIPECONF(pipe), pipeconf);
5006 POSTING_READ(PIPECONF(pipe));
79e53945 5007
9d0498a2 5008 intel_wait_for_vblank(dev, pipe);
79e53945 5009
5eddb70b 5010 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5011 POSTING_READ(DSPCNTR(plane));
79e53945 5012
5c3b82e2 5013 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5014
5015 intel_update_watermarks(dev);
5016
1f8eeabf
ED		 5017 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5018
1f803ee5 5019 return ret;
79e53945
JB		 5020}
5021
f564048e
EA		 5022static int intel_crtc_mode_set(struct drm_crtc *crtc,
5023 struct drm_display_mode *mode,
5024 struct drm_display_mode *adjusted_mode,
5025 int x, int y,
5026 struct drm_framebuffer *old_fb)
5027{
5028 struct drm_device *dev = crtc->dev;
5029 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031 int pipe = intel_crtc->pipe;
f564048e
EA		 5032 int ret;
5033
0b701d27 5034 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5035
f564048e
EA		 5036 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5037 x, y, old_fb);
79e53945 5038 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5039
d8e70a25
JB		 5040 if (ret)
5041 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5042 else
5043 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 5044
1f803ee5 5045 return ret;
79e53945
JB		 5046}
5047
3a9627f4
WF		 5048static bool intel_eld_uptodate(struct drm_connector *connector,
5049 int reg_eldv, uint32_t bits_eldv,
5050 int reg_elda, uint32_t bits_elda,
5051 int reg_edid)
5052{
5053 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5054 uint8_t *eld = connector->eld;
5055 uint32_t i;
5056
5057 i = I915_READ(reg_eldv);
5058 i &= bits_eldv;
5059
5060 if (!eld[0])
5061 return !i;
5062
5063 if (!i)
5064 return false;
5065
5066 i = I915_READ(reg_elda);
5067 i &= ~bits_elda;
5068 I915_WRITE(reg_elda, i);
5069
5070 for (i = 0; i < eld[2]; i++)
5071 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5072 return false;
5073
5074 return true;
5075}
5076
e0dac65e
WF		 5077static void g4x_write_eld(struct drm_connector *connector,
5078 struct drm_crtc *crtc)
5079{
5080 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5081 uint8_t *eld = connector->eld;
5082 uint32_t eldv;
5083 uint32_t len;
5084 uint32_t i;
5085
5086 i = I915_READ(G4X_AUD_VID_DID);
5087
5088 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5089 eldv = G4X_ELDV_DEVCL_DEVBLC;
5090 else
5091 eldv = G4X_ELDV_DEVCTG;
5092
3a9627f4
WF		 5093 if (intel_eld_uptodate(connector,
5094 G4X_AUD_CNTL_ST, eldv,
5095 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5096 G4X_HDMIW_HDMIEDID))
5097 return;
5098
e0dac65e
WF		 5099 i = I915_READ(G4X_AUD_CNTL_ST);
5100 i &= ~(eldv | G4X_ELD_ADDR);
5101 len = (i >> 9) & 0x1f; /* ELD buffer size */
5102 I915_WRITE(G4X_AUD_CNTL_ST, i);
5103
5104 if (!eld[0])
5105 return;
5106
5107 len = min_t(uint8_t, eld[2], len);
5108 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5109 for (i = 0; i < len; i++)
5110 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5111
5112 i = I915_READ(G4X_AUD_CNTL_ST);
5113 i |= eldv;
5114 I915_WRITE(G4X_AUD_CNTL_ST, i);
5115}
5116
83358c85
WX		 5117static void haswell_write_eld(struct drm_connector *connector,
5118 struct drm_crtc *crtc)
5119{
5120 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5121 uint8_t *eld = connector->eld;
5122 struct drm_device *dev = crtc->dev;
5123 uint32_t eldv;
5124 uint32_t i;
5125 int len;
5126 int pipe = to_intel_crtc(crtc)->pipe;
5127 int tmp;
5128
5129 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5130 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5131 int aud_config = HSW_AUD_CFG(pipe);
5132 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5133
5134
5135 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5136
5137 /* Audio output enable */
5138 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5139 tmp = I915_READ(aud_cntrl_st2);
5140 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5141 I915_WRITE(aud_cntrl_st2, tmp);
5142
5143 /* Wait for 1 vertical blank */
5144 intel_wait_for_vblank(dev, pipe);
5145
5146 /* Set ELD valid state */
5147 tmp = I915_READ(aud_cntrl_st2);
5148 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5149 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5150 I915_WRITE(aud_cntrl_st2, tmp);
5151 tmp = I915_READ(aud_cntrl_st2);
5152 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5153
5154 /* Enable HDMI mode */
5155 tmp = I915_READ(aud_config);
5156 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5157 /* clear N_programing_enable and N_value_index */
5158 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5159 I915_WRITE(aud_config, tmp);
5160
5161 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5162
5163 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5164
5165 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5166 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5167 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5168 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5169 } else
5170 I915_WRITE(aud_config, 0);
5171
5172 if (intel_eld_uptodate(connector,
5173 aud_cntrl_st2, eldv,
5174 aud_cntl_st, IBX_ELD_ADDRESS,
5175 hdmiw_hdmiedid))
5176 return;
5177
5178 i = I915_READ(aud_cntrl_st2);
5179 i &= ~eldv;
5180 I915_WRITE(aud_cntrl_st2, i);
5181
5182 if (!eld[0])
5183 return;
5184
5185 i = I915_READ(aud_cntl_st);
5186 i &= ~IBX_ELD_ADDRESS;
5187 I915_WRITE(aud_cntl_st, i);
5188 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5189 DRM_DEBUG_DRIVER("port num:%d\n", i);
5190
5191 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5192 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5193 for (i = 0; i < len; i++)
5194 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5195
5196 i = I915_READ(aud_cntrl_st2);
5197 i |= eldv;
5198 I915_WRITE(aud_cntrl_st2, i);
5199
5200}
5201
e0dac65e
WF		 5202static void ironlake_write_eld(struct drm_connector *connector,
5203 struct drm_crtc *crtc)
5204{
5205 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5206 uint8_t *eld = connector->eld;
5207 uint32_t eldv;
5208 uint32_t i;
5209 int len;
5210 int hdmiw_hdmiedid;
b6daa025 5211 int aud_config;
e0dac65e
WF		 5212 int aud_cntl_st;
5213 int aud_cntrl_st2;
9b138a83 5214 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5215
b3f33cbf 5216 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5217 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5218 aud_config = IBX_AUD_CFG(pipe);
5219 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5220 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5221 } else {
9b138a83
WX		 5222 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5223 aud_config = CPT_AUD_CFG(pipe);
5224 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5225 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5226 }
5227
9b138a83 5228 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5229
5230 i = I915_READ(aud_cntl_st);
9b138a83 5231 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5232 if (!i) {
5233 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5234 /* operate blindly on all ports */
1202b4c6
WF		 5235 eldv = IBX_ELD_VALIDB;
5236 eldv |= IBX_ELD_VALIDB << 4;
5237 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5238 } else {
5239 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5240 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5241 }
5242
3a9627f4
WF		 5243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5244 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5245 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5246 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5247 } else
5248 I915_WRITE(aud_config, 0);
e0dac65e 5249
3a9627f4
WF		 5250 if (intel_eld_uptodate(connector,
5251 aud_cntrl_st2, eldv,
5252 aud_cntl_st, IBX_ELD_ADDRESS,
5253 hdmiw_hdmiedid))
5254 return;
5255
e0dac65e
WF		 5256 i = I915_READ(aud_cntrl_st2);
5257 i &= ~eldv;
5258 I915_WRITE(aud_cntrl_st2, i);
5259
5260 if (!eld[0])
5261 return;
5262
e0dac65e 5263 i = I915_READ(aud_cntl_st);
1202b4c6 5264 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5265 I915_WRITE(aud_cntl_st, i);
5266
5267 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5268 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5269 for (i = 0; i < len; i++)
5270 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5271
5272 i = I915_READ(aud_cntrl_st2);
5273 i |= eldv;
5274 I915_WRITE(aud_cntrl_st2, i);
5275}
5276
5277void intel_write_eld(struct drm_encoder *encoder,
5278 struct drm_display_mode *mode)
5279{
5280 struct drm_crtc *crtc = encoder->crtc;
5281 struct drm_connector *connector;
5282 struct drm_device *dev = encoder->dev;
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5284
5285 connector = drm_select_eld(encoder, mode);
5286 if (!connector)
5287 return;
5288
5289 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5290 connector->base.id,
5291 drm_get_connector_name(connector),
5292 connector->encoder->base.id,
5293 drm_get_encoder_name(connector->encoder));
5294
5295 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5296
5297 if (dev_priv->display.write_eld)
5298 dev_priv->display.write_eld(connector, crtc);
5299}
5300
79e53945
JB		 5301/** Loads the palette/gamma unit for the CRTC with the prepared values */
5302void intel_crtc_load_lut(struct drm_crtc *crtc)
5303{
5304 struct drm_device *dev = crtc->dev;
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5307 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5308 int i;
5309
5310 /* The clocks have to be on to load the palette. */
aed3f09d 5311 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5312 return;
5313
f2b115e6 5314 /* use legacy palette for Ironlake */
bad720ff 5315 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5316 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5317
79e53945
JB		 5318 for (i = 0; i < 256; i++) {
5319 I915_WRITE(palreg + 4 * i,
5320 (intel_crtc->lut_r[i] << 16) |
5321 (intel_crtc->lut_g[i] << 8) |
5322 intel_crtc->lut_b[i]);
5323 }
5324}
5325
560b85bb
CW		 5326static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5327{
5328 struct drm_device *dev = crtc->dev;
5329 struct drm_i915_private *dev_priv = dev->dev_private;
5330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331 bool visible = base != 0;
5332 u32 cntl;
5333
5334 if (intel_crtc->cursor_visible == visible)
5335 return;
5336
9db4a9c7 5337 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5338 if (visible) {
5339 /* On these chipsets we can only modify the base whilst
5340 * the cursor is disabled.
5341 */
9db4a9c7 5342 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5343
5344 cntl &= ~(CURSOR_FORMAT_MASK);
5345 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5346 cntl |= CURSOR_ENABLE |
5347 CURSOR_GAMMA_ENABLE |
5348 CURSOR_FORMAT_ARGB;
5349 } else
5350 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5351 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5352
5353 intel_crtc->cursor_visible = visible;
5354}
5355
5356static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5357{
5358 struct drm_device *dev = crtc->dev;
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5361 int pipe = intel_crtc->pipe;
5362 bool visible = base != 0;
5363
5364 if (intel_crtc->cursor_visible != visible) {
548f245b 5365 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5366 if (base) {
5367 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5368 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5369 cntl |= pipe << 28; /* Connect to correct pipe */
5370 } else {
5371 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5372 cntl |= CURSOR_MODE_DISABLE;
5373 }
9db4a9c7 5374 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5375
5376 intel_crtc->cursor_visible = visible;
5377 }
5378 /* and commit changes on next vblank */
9db4a9c7 5379 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5380}
5381
65a21cd6
JB		 5382static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5383{
5384 struct drm_device *dev = crtc->dev;
5385 struct drm_i915_private *dev_priv = dev->dev_private;
5386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5387 int pipe = intel_crtc->pipe;
5388 bool visible = base != 0;
5389
5390 if (intel_crtc->cursor_visible != visible) {
5391 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5392 if (base) {
5393 cntl &= ~CURSOR_MODE;
5394 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5395 } else {
5396 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5397 cntl |= CURSOR_MODE_DISABLE;
5398 }
5399 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5400
5401 intel_crtc->cursor_visible = visible;
5402 }
5403 /* and commit changes on next vblank */
5404 I915_WRITE(CURBASE_IVB(pipe), base);
5405}
5406
cda4b7d3 5407/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5408static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5409 bool on)
cda4b7d3
CW		 5410{
5411 struct drm_device *dev = crtc->dev;
5412 struct drm_i915_private *dev_priv = dev->dev_private;
5413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5414 int pipe = intel_crtc->pipe;
5415 int x = intel_crtc->cursor_x;
5416 int y = intel_crtc->cursor_y;
560b85bb 5417 u32 base, pos;
cda4b7d3
CW		 5418 bool visible;
5419
5420 pos = 0;
5421
6b383a7f 5422 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5423 base = intel_crtc->cursor_addr;
5424 if (x > (int) crtc->fb->width)
5425 base = 0;
5426
5427 if (y > (int) crtc->fb->height)
5428 base = 0;
5429 } else
5430 base = 0;
5431
5432 if (x < 0) {
5433 if (x + intel_crtc->cursor_width < 0)
5434 base = 0;
5435
5436 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5437 x = -x;
5438 }
5439 pos |= x << CURSOR_X_SHIFT;
5440
5441 if (y < 0) {
5442 if (y + intel_crtc->cursor_height < 0)
5443 base = 0;
5444
5445 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5446 y = -y;
5447 }
5448 pos |= y << CURSOR_Y_SHIFT;
5449
5450 visible = base != 0;
560b85bb 5451 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5452 return;
5453
0cd83aa9 5454 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5455 I915_WRITE(CURPOS_IVB(pipe), pos);
5456 ivb_update_cursor(crtc, base);
5457 } else {
5458 I915_WRITE(CURPOS(pipe), pos);
5459 if (IS_845G(dev) || IS_I865G(dev))
5460 i845_update_cursor(crtc, base);
5461 else
5462 i9xx_update_cursor(crtc, base);
5463 }
cda4b7d3
CW		 5464}
5465
79e53945 5466static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5467 struct drm_file *file,
79e53945
JB		 5468 uint32_t handle,
5469 uint32_t width, uint32_t height)
5470{
5471 struct drm_device *dev = crtc->dev;
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5474 struct drm_i915_gem_object *obj;
cda4b7d3 5475 uint32_t addr;
3f8bc370 5476 int ret;
79e53945 5477
28c97730 5478 DRM_DEBUG_KMS("\n");
79e53945
JB		 5479
5480 /* if we want to turn off the cursor ignore width and height */
5481 if (!handle) {
28c97730 5482 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5483 addr = 0;
05394f39 5484 obj = NULL;
5004417d 5485 mutex_lock(&dev->struct_mutex);
3f8bc370 5486 goto finish;
79e53945
JB		 5487 }
5488
5489 /* Currently we only support 64x64 cursors */
5490 if (width != 64 || height != 64) {
5491 DRM_ERROR("we currently only support 64x64 cursors\n");
5492 return -EINVAL;
5493 }
5494
05394f39 5495 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5496 if (&obj->base == NULL)
79e53945
JB		 5497 return -ENOENT;
5498
05394f39 5499 if (obj->base.size < width * height * 4) {
79e53945 5500 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5501 ret = -ENOMEM;
5502 goto fail;
79e53945
JB		 5503 }
5504
71acb5eb 5505 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5506 mutex_lock(&dev->struct_mutex);
b295d1b6 5507 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5508 if (obj->tiling_mode) {
5509 DRM_ERROR("cursor cannot be tiled\n");
5510 ret = -EINVAL;
5511 goto fail_locked;
5512 }
5513
2da3b9b9 5514 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5515 if (ret) {
5516 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5517 goto fail_locked;
e7b526bb
CW		 5518 }
5519
d9e86c0e
CW		 5520 ret = i915_gem_object_put_fence(obj);
5521 if (ret) {
2da3b9b9 5522 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5523 goto fail_unpin;
5524 }
5525
05394f39 5526 addr = obj->gtt_offset;
71acb5eb 5527 } else {
6eeefaf3 5528 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5529 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5530 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5531 align);
71acb5eb
DA		 5532 if (ret) {
5533 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5534 goto fail_locked;
71acb5eb 5535 }
05394f39 5536 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5537 }
5538
a6c45cf0 5539 if (IS_GEN2(dev))
14b60391
JB		 5540 I915_WRITE(CURSIZE, (height << 12) | width);
5541
3f8bc370 5542 finish:
3f8bc370 5543 if (intel_crtc->cursor_bo) {
b295d1b6 5544 if (dev_priv->info->cursor_needs_physical) {
05394f39 5545 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5546 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5547 } else
5548 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5549 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5550 }
80824003 5551
7f9872e0 5552 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5553
5554 intel_crtc->cursor_addr = addr;
05394f39 5555 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5556 intel_crtc->cursor_width = width;
5557 intel_crtc->cursor_height = height;
5558
6b383a7f 5559 intel_crtc_update_cursor(crtc, true);
3f8bc370 5560
79e53945 5561 return 0;
e7b526bb 5562fail_unpin:
05394f39 5563 i915_gem_object_unpin(obj);
7f9872e0 5564fail_locked:
34b8686e 5565 mutex_unlock(&dev->struct_mutex);
bc9025bd 5566fail:
05394f39 5567 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5568 return ret;
79e53945
JB		 5569}
5570
5571static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5572{
79e53945 5573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5574
cda4b7d3
CW		 5575 intel_crtc->cursor_x = x;
5576 intel_crtc->cursor_y = y;
652c393a 5577
6b383a7f 5578 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5579
5580 return 0;
5581}
5582
5583/** Sets the color ramps on behalf of RandR */
5584void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5585 u16 blue, int regno)
5586{
5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5588
5589 intel_crtc->lut_r[regno] = red >> 8;
5590 intel_crtc->lut_g[regno] = green >> 8;
5591 intel_crtc->lut_b[regno] = blue >> 8;
5592}
5593
b8c00ac5
DA		 5594void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5595 u16 *blue, int regno)
5596{
5597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5598
5599 *red = intel_crtc->lut_r[regno] << 8;
5600 *green = intel_crtc->lut_g[regno] << 8;
5601 *blue = intel_crtc->lut_b[regno] << 8;
5602}
5603
79e53945 5604static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5605 u16 *blue, uint32_t start, uint32_t size)
79e53945 5606{
7203425a 5607 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5609
7203425a 5610 for (i = start; i < end; i++) {
79e53945
JB		 5611 intel_crtc->lut_r[i] = red[i] >> 8;
5612 intel_crtc->lut_g[i] = green[i] >> 8;
5613 intel_crtc->lut_b[i] = blue[i] >> 8;
5614 }
5615
5616 intel_crtc_load_lut(crtc);
5617}
5618
5619/**
5620 * Get a pipe with a simple mode set on it for doing load-based monitor
5621 * detection.
5622 *
5623 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5624 * its requirements. The pipe will be connected to no other encoders.
79e53945 5625 *
c751ce4f 5626 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5627 * configured for it. In the future, it could choose to temporarily disable
5628 * some outputs to free up a pipe for its use.
5629 *
5630 * \return crtc, or NULL if no pipes are available.
5631 */
5632
5633/* VESA 640x480x72Hz mode to set on the pipe */
5634static struct drm_display_mode load_detect_mode = {
5635 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5636 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5637};
5638
d2dff872
CW		 5639static struct drm_framebuffer *
5640intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5641 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5642 struct drm_i915_gem_object *obj)
5643{
5644 struct intel_framebuffer *intel_fb;
5645 int ret;
5646
5647 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5648 if (!intel_fb) {
5649 drm_gem_object_unreference_unlocked(&obj->base);
5650 return ERR_PTR(-ENOMEM);
5651 }
5652
5653 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5654 if (ret) {
5655 drm_gem_object_unreference_unlocked(&obj->base);
5656 kfree(intel_fb);
5657 return ERR_PTR(ret);
5658 }
5659
5660 return &intel_fb->base;
5661}
5662
5663static u32
5664intel_framebuffer_pitch_for_width(int width, int bpp)
5665{
5666 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5667 return ALIGN(pitch, 64);
5668}
5669
5670static u32
5671intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5672{
5673 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5674 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5675}
5676
5677static struct drm_framebuffer *
5678intel_framebuffer_create_for_mode(struct drm_device *dev,
5679 struct drm_display_mode *mode,
5680 int depth, int bpp)
5681{
5682 struct drm_i915_gem_object *obj;
308e5bcb 5683 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5684
5685 obj = i915_gem_alloc_object(dev,
5686 intel_framebuffer_size_for_mode(mode, bpp));
5687 if (obj == NULL)
5688 return ERR_PTR(-ENOMEM);
5689
5690 mode_cmd.width = mode->hdisplay;
5691 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5692 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5693 bpp);
5ca0c34a 5694 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5695
5696 return intel_framebuffer_create(dev, &mode_cmd, obj);
5697}
5698
5699static struct drm_framebuffer *
5700mode_fits_in_fbdev(struct drm_device *dev,
5701 struct drm_display_mode *mode)
5702{
5703 struct drm_i915_private *dev_priv = dev->dev_private;
5704 struct drm_i915_gem_object *obj;
5705 struct drm_framebuffer *fb;
5706
5707 if (dev_priv->fbdev == NULL)
5708 return NULL;
5709
5710 obj = dev_priv->fbdev->ifb.obj;
5711 if (obj == NULL)
5712 return NULL;
5713
5714 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5715 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5716 fb->bits_per_pixel))
d2dff872
CW		 5717 return NULL;
5718
01f2c773 5719 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5720 return NULL;
5721
5722 return fb;
5723}
5724
d2434ab7 5725bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5726 struct drm_display_mode *mode,
8261b191 5727 struct intel_load_detect_pipe *old)
79e53945
JB		 5728{
5729 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5730 struct intel_encoder *intel_encoder =
5731 intel_attached_encoder(connector);
79e53945 5732 struct drm_crtc *possible_crtc;
4ef69c7a 5733 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5734 struct drm_crtc *crtc = NULL;
5735 struct drm_device *dev = encoder->dev;
d2dff872 5736 struct drm_framebuffer *old_fb;
79e53945
JB		 5737 int i = -1;
5738
d2dff872
CW		 5739 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5740 connector->base.id, drm_get_connector_name(connector),
5741 encoder->base.id, drm_get_encoder_name(encoder));
5742
79e53945
JB		 5743 /*
5744 * Algorithm gets a little messy:
7a5e4805 5745 *
79e53945
JB		 5746 * - if the connector already has an assigned crtc, use it (but make
5747 * sure it's on first)
7a5e4805 5748 *
79e53945
JB		 5749 * - try to find the first unused crtc that can drive this connector,
5750 * and use that if we find one
79e53945
JB		 5751 */
5752
5753 /* See if we already have a CRTC for this connector */
5754 if (encoder->crtc) {
5755 crtc = encoder->crtc;
8261b191 5756
24218aac 5757 old->dpms_mode = connector->dpms;
8261b191
CW		 5758 old->load_detect_temp = false;
5759
5760 /* Make sure the crtc and connector are running */
24218aac
DV		 5761 if (connector->dpms != DRM_MODE_DPMS_ON)
5762 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5763
7173188d 5764 return true;
79e53945
JB		 5765 }
5766
5767 /* Find an unused one (if possible) */
5768 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5769 i++;
5770 if (!(encoder->possible_crtcs & (1 << i)))
5771 continue;
5772 if (!possible_crtc->enabled) {
5773 crtc = possible_crtc;
5774 break;
5775 }
79e53945
JB		 5776 }
5777
5778 /*
5779 * If we didn't find an unused CRTC, don't use any.
5780 */
5781 if (!crtc) {
7173188d
CW		 5782 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5783 return false;
79e53945
JB		 5784 }
5785
5786 encoder->crtc = crtc;
c1c43977 5787 connector->encoder = encoder;
79e53945
JB		 5788
5789 intel_crtc = to_intel_crtc(crtc);
24218aac 5790 old->dpms_mode = connector->dpms;
8261b191 5791 old->load_detect_temp = true;
d2dff872 5792 old->release_fb = NULL;
79e53945 5793
6492711d
CW		 5794 if (!mode)
5795 mode = &load_detect_mode;
79e53945 5796
d2dff872
CW		 5797 old_fb = crtc->fb;
5798
5799 /* We need a framebuffer large enough to accommodate all accesses
5800 * that the plane may generate whilst we perform load detection.
5801 * We can not rely on the fbcon either being present (we get called
5802 * during its initialisation to detect all boot displays, or it may
5803 * not even exist) or that it is large enough to satisfy the
5804 * requested mode.
5805 */
5806 crtc->fb = mode_fits_in_fbdev(dev, mode);
5807 if (crtc->fb == NULL) {
5808 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5809 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5810 old->release_fb = crtc->fb;
5811 } else
5812 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5813 if (IS_ERR(crtc->fb)) {
5814 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5815 goto fail;
79e53945 5816 }
79e53945 5817
a6778b3c 5818 if (!intel_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5819 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5820 if (old->release_fb)
5821 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5822 goto fail;
79e53945 5823 }
7173188d 5824
79e53945 5825 /* let the connector get through one full cycle before testing */
9d0498a2 5826 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5827
7173188d 5828 return true;
24218aac
DV		 5829fail:
5830 connector->encoder = NULL;
5831 encoder->crtc = NULL;
5832 crtc->fb = old_fb;
5833 return false;
79e53945
JB		 5834}
5835
d2434ab7 5836void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5837 struct intel_load_detect_pipe *old)
79e53945 5838{
d2434ab7
DV		 5839 struct intel_encoder *intel_encoder =
5840 intel_attached_encoder(connector);
4ef69c7a 5841 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5842 struct drm_device *dev = encoder->dev;
79e53945 5843
d2dff872
CW		 5844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5845 connector->base.id, drm_get_connector_name(connector),
5846 encoder->base.id, drm_get_encoder_name(encoder));
5847
8261b191 5848 if (old->load_detect_temp) {
c1c43977 5849 connector->encoder = NULL;
24218aac 5850 encoder->crtc = NULL;
79e53945 5851 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5852
5853 if (old->release_fb)
5854 old->release_fb->funcs->destroy(old->release_fb);
5855
0622a53c 5856 return;
79e53945
JB		 5857 }
5858
c751ce4f 5859 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5860 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5861 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5862}
5863
5864/* Returns the clock of the currently programmed mode of the given pipe. */
5865static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5866{
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5869 int pipe = intel_crtc->pipe;
548f245b 5870 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5871 u32 fp;
5872 intel_clock_t clock;
5873
5874 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5875 fp = I915_READ(FP0(pipe));
79e53945 5876 else
39adb7a5 5877 fp = I915_READ(FP1(pipe));
79e53945
JB		 5878
5879 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5880 if (IS_PINEVIEW(dev)) {
5881 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5882 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5883 } else {
5884 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5885 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5886 }
5887
a6c45cf0 5888 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5889 if (IS_PINEVIEW(dev))
5890 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5891 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5892 else
5893 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5894 DPLL_FPA01_P1_POST_DIV_SHIFT);
5895
5896 switch (dpll & DPLL_MODE_MASK) {
5897 case DPLLB_MODE_DAC_SERIAL:
5898 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5899 5 : 10;
5900 break;
5901 case DPLLB_MODE_LVDS:
5902 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5903 7 : 14;
5904 break;
5905 default:
28c97730 5906 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5907 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5908 return 0;
5909 }
5910
5911 /* XXX: Handle the 100Mhz refclk */
2177832f 5912 intel_clock(dev, 96000, &clock);
79e53945
JB		 5913 } else {
5914 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5915
5916 if (is_lvds) {
5917 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5918 DPLL_FPA01_P1_POST_DIV_SHIFT);
5919 clock.p2 = 14;
5920
5921 if ((dpll & PLL_REF_INPUT_MASK) ==
5922 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5923 /* XXX: might not be 66MHz */
2177832f 5924 intel_clock(dev, 66000, &clock);
79e53945 5925 } else
2177832f 5926 intel_clock(dev, 48000, &clock);
79e53945
JB		 5927 } else {
5928 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5929 clock.p1 = 2;
5930 else {
5931 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5932 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5933 }
5934 if (dpll & PLL_P2_DIVIDE_BY_4)
5935 clock.p2 = 4;
5936 else
5937 clock.p2 = 2;
5938
2177832f 5939 intel_clock(dev, 48000, &clock);
79e53945
JB		 5940 }
5941 }
5942
5943 /* XXX: It would be nice to validate the clocks, but we can't reuse
5944 * i830PllIsValid() because it relies on the xf86_config connector
5945 * configuration being accurate, which it isn't necessarily.
5946 */
5947
5948 return clock.dot;
5949}
5950
5951/** Returns the currently programmed mode of the given pipe. */
5952struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5953 struct drm_crtc *crtc)
5954{
548f245b 5955 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 int pipe = intel_crtc->pipe;
5958 struct drm_display_mode *mode;
548f245b
JB		 5959 int htot = I915_READ(HTOTAL(pipe));
5960 int hsync = I915_READ(HSYNC(pipe));
5961 int vtot = I915_READ(VTOTAL(pipe));
5962 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5963
5964 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5965 if (!mode)
5966 return NULL;
5967
5968 mode->clock = intel_crtc_clock_get(dev, crtc);
5969 mode->hdisplay = (htot & 0xffff) + 1;
5970 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5971 mode->hsync_start = (hsync & 0xffff) + 1;
5972 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5973 mode->vdisplay = (vtot & 0xffff) + 1;
5974 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5975 mode->vsync_start = (vsync & 0xffff) + 1;
5976 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5977
5978 drm_mode_set_name(mode);
79e53945
JB		 5979
5980 return mode;
5981}
5982
3dec0095 5983static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5984{
5985 struct drm_device *dev = crtc->dev;
5986 drm_i915_private_t *dev_priv = dev->dev_private;
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5989 int dpll_reg = DPLL(pipe);
5990 int dpll;
652c393a 5991
bad720ff 5992 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5993 return;
5994
5995 if (!dev_priv->lvds_downclock_avail)
5996 return;
5997
dbdc6479 5998 dpll = I915_READ(dpll_reg);
652c393a 5999 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6000 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6001
8ac5a6d5 6002 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6003
6004 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6005 I915_WRITE(dpll_reg, dpll);
9d0498a2 6006 intel_wait_for_vblank(dev, pipe);
dbdc6479 6007
652c393a
JB		 6008 dpll = I915_READ(dpll_reg);
6009 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6010 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6011 }
652c393a
JB		 6012}
6013
6014static void intel_decrease_pllclock(struct drm_crtc *crtc)
6015{
6016 struct drm_device *dev = crtc->dev;
6017 drm_i915_private_t *dev_priv = dev->dev_private;
6018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6019
bad720ff 6020 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6021 return;
6022
6023 if (!dev_priv->lvds_downclock_avail)
6024 return;
6025
6026 /*
6027 * Since this is called by a timer, we should never get here in
6028 * the manual case.
6029 */
6030 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6031 int pipe = intel_crtc->pipe;
6032 int dpll_reg = DPLL(pipe);
6033 int dpll;
f6e5b160 6034
44d98a61 6035 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6036
8ac5a6d5 6037 assert_panel_unlocked(dev_priv, pipe);
652c393a 6038
dc257cf1 6039 dpll = I915_READ(dpll_reg);
652c393a
JB		 6040 dpll |= DISPLAY_RATE_SELECT_FPA1;
6041 I915_WRITE(dpll_reg, dpll);
9d0498a2 6042 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6043 dpll = I915_READ(dpll_reg);
6044 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6045 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6046 }
6047
6048}
6049
f047e395
CW		 6050void intel_mark_busy(struct drm_device *dev)
6051{
f047e395
CW		 6052 i915_update_gfx_val(dev->dev_private);
6053}
6054
6055void intel_mark_idle(struct drm_device *dev)
652c393a 6056{
f047e395
CW		 6057}
6058
6059void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6060{
6061 struct drm_device *dev = obj->base.dev;
652c393a 6062 struct drm_crtc *crtc;
652c393a
JB		 6063
6064 if (!i915_powersave)
6065 return;
6066
652c393a 6067 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6068 if (!crtc->fb)
6069 continue;
6070
f047e395
CW		 6071 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6072 intel_increase_pllclock(crtc);
652c393a 6073 }
652c393a
JB		 6074}
6075
f047e395 6076void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6077{
f047e395
CW		 6078 struct drm_device *dev = obj->base.dev;
6079 struct drm_crtc *crtc;
652c393a 6080
f047e395 6081 if (!i915_powersave)
acb87dfb
CW		 6082 return;
6083
652c393a
JB		 6084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6085 if (!crtc->fb)
6086 continue;
6087
f047e395
CW		 6088 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6089 intel_decrease_pllclock(crtc);
652c393a
JB		 6090 }
6091}
6092
79e53945
JB		 6093static void intel_crtc_destroy(struct drm_crtc *crtc)
6094{
6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6096 struct drm_device *dev = crtc->dev;
6097 struct intel_unpin_work *work;
6098 unsigned long flags;
6099
6100 spin_lock_irqsave(&dev->event_lock, flags);
6101 work = intel_crtc->unpin_work;
6102 intel_crtc->unpin_work = NULL;
6103 spin_unlock_irqrestore(&dev->event_lock, flags);
6104
6105 if (work) {
6106 cancel_work_sync(&work->work);
6107 kfree(work);
6108 }
79e53945
JB		 6109
6110 drm_crtc_cleanup(crtc);
67e77c5a 6111
79e53945
JB		 6112 kfree(intel_crtc);
6113}
6114
6b95a207
KH		 6115static void intel_unpin_work_fn(struct work_struct *__work)
6116{
6117 struct intel_unpin_work *work =
6118 container_of(__work, struct intel_unpin_work, work);
6119
6120 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6121 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6122 drm_gem_object_unreference(&work->pending_flip_obj->base);
6123 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6124
7782de3b 6125 intel_update_fbc(work->dev);
6b95a207
KH		 6126 mutex_unlock(&work->dev->struct_mutex);
6127 kfree(work);
6128}
6129
1afe3e9d 6130static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6131 struct drm_crtc *crtc)
6b95a207
KH		 6132{
6133 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135 struct intel_unpin_work *work;
05394f39 6136 struct drm_i915_gem_object *obj;
6b95a207 6137 struct drm_pending_vblank_event *e;
49b14a5c 6138 struct timeval tnow, tvbl;
6b95a207
KH		 6139 unsigned long flags;
6140
6141 /* Ignore early vblank irqs */
6142 if (intel_crtc == NULL)
6143 return;
6144
49b14a5c
MK		 6145 do_gettimeofday(&tnow);
6146
6b95a207
KH		 6147 spin_lock_irqsave(&dev->event_lock, flags);
6148 work = intel_crtc->unpin_work;
6149 if (work == NULL || !work->pending) {
6150 spin_unlock_irqrestore(&dev->event_lock, flags);
6151 return;
6152 }
6153
6154 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6155
6156 if (work->event) {
6157 e = work->event;
49b14a5c 6158 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6159
6160 /* Called before vblank count and timestamps have
6161 * been updated for the vblank interval of flip
6162 * completion? Need to increment vblank count and
6163 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6164 * to account for this. We assume this happened if we
6165 * get called over 0.9 frame durations after the last
6166 * timestamped vblank.
6167 *
6168 * This calculation can not be used with vrefresh rates
6169 * below 5Hz (10Hz to be on the safe side) without
6170 * promoting to 64 integers.
0af7e4df 6171 */
49b14a5c
MK		 6172 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6173 9 * crtc->framedur_ns) {
0af7e4df 6174 e->event.sequence++;
49b14a5c
MK		 6175 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6176 crtc->framedur_ns);
0af7e4df
MK		 6177 }
6178
49b14a5c
MK		 6179 e->event.tv_sec = tvbl.tv_sec;
6180 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6181
6b95a207
KH		 6182 list_add_tail(&e->base.link,
6183 &e->base.file_priv->event_list);
6184 wake_up_interruptible(&e->base.file_priv->event_wait);
6185 }
6186
0af7e4df
MK		 6187 drm_vblank_put(dev, intel_crtc->pipe);
6188
6b95a207
KH		 6189 spin_unlock_irqrestore(&dev->event_lock, flags);
6190
05394f39 6191 obj = work->old_fb_obj;
d9e86c0e 6192
e59f2bac 6193 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6194 &obj->pending_flip.counter);
6195 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6196 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6197
6b95a207 6198 schedule_work(&work->work);
e5510fac
JB		 6199
6200 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6201}
6202
1afe3e9d
JB		 6203void intel_finish_page_flip(struct drm_device *dev, int pipe)
6204{
6205 drm_i915_private_t *dev_priv = dev->dev_private;
6206 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6207
49b14a5c 6208 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6209}
6210
6211void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6212{
6213 drm_i915_private_t *dev_priv = dev->dev_private;
6214 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6215
49b14a5c 6216 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6217}
6218
6b95a207
KH		 6219void intel_prepare_page_flip(struct drm_device *dev, int plane)
6220{
6221 drm_i915_private_t *dev_priv = dev->dev_private;
6222 struct intel_crtc *intel_crtc =
6223 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6224 unsigned long flags;
6225
6226 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6227 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6228 if ((++intel_crtc->unpin_work->pending) > 1)
6229 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6230 } else {
6231 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6232 }
6b95a207
KH		 6233 spin_unlock_irqrestore(&dev->event_lock, flags);
6234}
6235
8c9f3aaf
JB		 6236static int intel_gen2_queue_flip(struct drm_device *dev,
6237 struct drm_crtc *crtc,
6238 struct drm_framebuffer *fb,
6239 struct drm_i915_gem_object *obj)
6240{
6241 struct drm_i915_private *dev_priv = dev->dev_private;
6242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6243 u32 flip_mask;
6d90c952 6244 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6245 int ret;
6246
6d90c952 6247 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6248 if (ret)
83d4092b 6249 goto err;
8c9f3aaf 6250
6d90c952 6251 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6252 if (ret)
83d4092b 6253 goto err_unpin;
8c9f3aaf
JB		 6254
6255 /* Can't queue multiple flips, so wait for the previous
6256 * one to finish before executing the next.
6257 */
6258 if (intel_crtc->plane)
6259 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6260 else
6261 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6262 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6263 intel_ring_emit(ring, MI_NOOP);
6264 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6265 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6266 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6267 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6268 intel_ring_emit(ring, 0); /* aux display base address, unused */
6269 intel_ring_advance(ring);
83d4092b
CW		 6270 return 0;
6271
6272err_unpin:
6273 intel_unpin_fb_obj(obj);
6274err:
8c9f3aaf
JB		 6275 return ret;
6276}
6277
6278static int intel_gen3_queue_flip(struct drm_device *dev,
6279 struct drm_crtc *crtc,
6280 struct drm_framebuffer *fb,
6281 struct drm_i915_gem_object *obj)
6282{
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6285 u32 flip_mask;
6d90c952 6286 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6287 int ret;
6288
6d90c952 6289 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6290 if (ret)
83d4092b 6291 goto err;
8c9f3aaf 6292
6d90c952 6293 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6294 if (ret)
83d4092b 6295 goto err_unpin;
8c9f3aaf
JB		 6296
6297 if (intel_crtc->plane)
6298 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6299 else
6300 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6301 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6302 intel_ring_emit(ring, MI_NOOP);
6303 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6304 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6305 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6306 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6307 intel_ring_emit(ring, MI_NOOP);
6308
6309 intel_ring_advance(ring);
83d4092b
CW		 6310 return 0;
6311
6312err_unpin:
6313 intel_unpin_fb_obj(obj);
6314err:
8c9f3aaf
JB		 6315 return ret;
6316}
6317
6318static int intel_gen4_queue_flip(struct drm_device *dev,
6319 struct drm_crtc *crtc,
6320 struct drm_framebuffer *fb,
6321 struct drm_i915_gem_object *obj)
6322{
6323 struct drm_i915_private *dev_priv = dev->dev_private;
6324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6325 uint32_t pf, pipesrc;
6d90c952 6326 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6327 int ret;
6328
6d90c952 6329 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6330 if (ret)
83d4092b 6331 goto err;
8c9f3aaf 6332
6d90c952 6333 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6334 if (ret)
83d4092b 6335 goto err_unpin;
8c9f3aaf
JB		 6336
6337 /* i965+ uses the linear or tiled offsets from the
6338 * Display Registers (which do not change across a page-flip)
6339 * so we need only reprogram the base address.
6340 */
6d90c952
DV		 6341 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6343 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6344 intel_ring_emit(ring,
6345 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6346 obj->tiling_mode);
8c9f3aaf
JB		 6347
6348 /* XXX Enabling the panel-fitter across page-flip is so far
6349 * untested on non-native modes, so ignore it for now.
6350 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6351 */
6352 pf = 0;
6353 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6354 intel_ring_emit(ring, pf | pipesrc);
6355 intel_ring_advance(ring);
83d4092b
CW		 6356 return 0;
6357
6358err_unpin:
6359 intel_unpin_fb_obj(obj);
6360err:
8c9f3aaf
JB		 6361 return ret;
6362}
6363
6364static int intel_gen6_queue_flip(struct drm_device *dev,
6365 struct drm_crtc *crtc,
6366 struct drm_framebuffer *fb,
6367 struct drm_i915_gem_object *obj)
6368{
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6371 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6372 uint32_t pf, pipesrc;
6373 int ret;
6374
6d90c952 6375 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6376 if (ret)
83d4092b 6377 goto err;
8c9f3aaf 6378
6d90c952 6379 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6380 if (ret)
83d4092b 6381 goto err_unpin;
8c9f3aaf 6382
6d90c952
DV		 6383 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6385 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6386 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6387
dc257cf1
DV		 6388 /* Contrary to the suggestions in the documentation,
6389 * "Enable Panel Fitter" does not seem to be required when page
6390 * flipping with a non-native mode, and worse causes a normal
6391 * modeset to fail.
6392 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6393 */
6394 pf = 0;
8c9f3aaf 6395 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6396 intel_ring_emit(ring, pf | pipesrc);
6397 intel_ring_advance(ring);
83d4092b
CW		 6398 return 0;
6399
6400err_unpin:
6401 intel_unpin_fb_obj(obj);
6402err:
8c9f3aaf
JB		 6403 return ret;
6404}
6405
7c9017e5
JB		 6406/*
6407 * On gen7 we currently use the blit ring because (in early silicon at least)
6408 * the render ring doesn't give us interrpts for page flip completion, which
6409 * means clients will hang after the first flip is queued. Fortunately the
6410 * blit ring generates interrupts properly, so use it instead.
6411 */
6412static int intel_gen7_queue_flip(struct drm_device *dev,
6413 struct drm_crtc *crtc,
6414 struct drm_framebuffer *fb,
6415 struct drm_i915_gem_object *obj)
6416{
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6420 uint32_t plane_bit = 0;
7c9017e5
JB		 6421 int ret;
6422
6423 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6424 if (ret)
83d4092b 6425 goto err;
7c9017e5 6426
cb05d8de
DV		 6427 switch(intel_crtc->plane) {
6428 case PLANE_A:
6429 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6430 break;
6431 case PLANE_B:
6432 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6433 break;
6434 case PLANE_C:
6435 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6436 break;
6437 default:
6438 WARN_ONCE(1, "unknown plane in flip command\n");
6439 ret = -ENODEV;
ab3951eb 6440 goto err_unpin;
cb05d8de
DV		 6441 }
6442
7c9017e5
JB		 6443 ret = intel_ring_begin(ring, 4);
6444 if (ret)
83d4092b 6445 goto err_unpin;
7c9017e5 6446
cb05d8de 6447 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6448 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6449 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6450 intel_ring_emit(ring, (MI_NOOP));
6451 intel_ring_advance(ring);
83d4092b
CW		 6452 return 0;
6453
6454err_unpin:
6455 intel_unpin_fb_obj(obj);
6456err:
7c9017e5
JB		 6457 return ret;
6458}
6459
8c9f3aaf
JB		 6460static int intel_default_queue_flip(struct drm_device *dev,
6461 struct drm_crtc *crtc,
6462 struct drm_framebuffer *fb,
6463 struct drm_i915_gem_object *obj)
6464{
6465 return -ENODEV;
6466}
6467
6b95a207
KH		 6468static int intel_crtc_page_flip(struct drm_crtc *crtc,
6469 struct drm_framebuffer *fb,
6470 struct drm_pending_vblank_event *event)
6471{
6472 struct drm_device *dev = crtc->dev;
6473 struct drm_i915_private *dev_priv = dev->dev_private;
6474 struct intel_framebuffer *intel_fb;
05394f39 6475 struct drm_i915_gem_object *obj;
6b95a207
KH		 6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477 struct intel_unpin_work *work;
8c9f3aaf 6478 unsigned long flags;
52e68630 6479 int ret;
6b95a207 6480
e6a595d2
VS		 6481 /* Can't change pixel format via MI display flips. */
6482 if (fb->pixel_format != crtc->fb->pixel_format)
6483 return -EINVAL;
6484
6485 /*
6486 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6487 * Note that pitch changes could also affect these register.
6488 */
6489 if (INTEL_INFO(dev)->gen > 3 &&
6490 (fb->offsets[0] != crtc->fb->offsets[0] ||
6491 fb->pitches[0] != crtc->fb->pitches[0]))
6492 return -EINVAL;
6493
6b95a207
KH		 6494 work = kzalloc(sizeof *work, GFP_KERNEL);
6495 if (work == NULL)
6496 return -ENOMEM;
6497
6b95a207
KH		 6498 work->event = event;
6499 work->dev = crtc->dev;
6500 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6501 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6502 INIT_WORK(&work->work, intel_unpin_work_fn);
6503
7317c75e
JB		 6504 ret = drm_vblank_get(dev, intel_crtc->pipe);
6505 if (ret)
6506 goto free_work;
6507
6b95a207
KH		 6508 /* We borrow the event spin lock for protecting unpin_work */
6509 spin_lock_irqsave(&dev->event_lock, flags);
6510 if (intel_crtc->unpin_work) {
6511 spin_unlock_irqrestore(&dev->event_lock, flags);
6512 kfree(work);
7317c75e 6513 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6514
6515 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6516 return -EBUSY;
6517 }
6518 intel_crtc->unpin_work = work;
6519 spin_unlock_irqrestore(&dev->event_lock, flags);
6520
6521 intel_fb = to_intel_framebuffer(fb);
6522 obj = intel_fb->obj;
6523
79158103
CW		 6524 ret = i915_mutex_lock_interruptible(dev);
6525 if (ret)
6526 goto cleanup;
6b95a207 6527
75dfca80 6528 /* Reference the objects for the scheduled work. */
05394f39
CW		 6529 drm_gem_object_reference(&work->old_fb_obj->base);
6530 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6531
6532 crtc->fb = fb;
96b099fd 6533
e1f99ce6 6534 work->pending_flip_obj = obj;
e1f99ce6 6535
4e5359cd
SF		 6536 work->enable_stall_check = true;
6537
e1f99ce6
CW		 6538 /* Block clients from rendering to the new back buffer until
6539 * the flip occurs and the object is no longer visible.
6540 */
05394f39 6541 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6542
8c9f3aaf
JB		 6543 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6544 if (ret)
6545 goto cleanup_pending;
6b95a207 6546
7782de3b 6547 intel_disable_fbc(dev);
f047e395 6548 intel_mark_fb_busy(obj);
6b95a207
KH		 6549 mutex_unlock(&dev->struct_mutex);
6550
e5510fac
JB		 6551 trace_i915_flip_request(intel_crtc->plane, obj);
6552
6b95a207 6553 return 0;
96b099fd 6554
8c9f3aaf
JB		 6555cleanup_pending:
6556 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6557 drm_gem_object_unreference(&work->old_fb_obj->base);
6558 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6559 mutex_unlock(&dev->struct_mutex);
6560
79158103 6561cleanup:
96b099fd
CW		 6562 spin_lock_irqsave(&dev->event_lock, flags);
6563 intel_crtc->unpin_work = NULL;
6564 spin_unlock_irqrestore(&dev->event_lock, flags);
6565
7317c75e
JB		 6566 drm_vblank_put(dev, intel_crtc->pipe);
6567free_work:
96b099fd
CW		 6568 kfree(work);
6569
6570 return ret;
6b95a207
KH		 6571}
6572
f6e5b160 6573static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6574 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6575 .load_lut = intel_crtc_load_lut,
6576 .disable = intel_crtc_disable,
6577};
6578
50f56119
DV		 6579static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6580 struct drm_crtc *crtc)
6581{
6582 struct drm_device *dev;
6583 struct drm_crtc *tmp;
6584 int crtc_mask = 1;
6585
6586 WARN(!crtc, "checking null crtc?\n");
6587
6588 dev = crtc->dev;
6589
6590 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6591 if (tmp == crtc)
6592 break;
6593 crtc_mask <<= 1;
6594 }
6595
6596 if (encoder->possible_crtcs & crtc_mask)
6597 return true;
6598 return false;
6599}
6600
6601static int
6602intel_crtc_helper_disable(struct drm_crtc *crtc)
6603{
6604 struct drm_device *dev = crtc->dev;
6605 struct drm_connector *connector;
6606 struct drm_encoder *encoder;
6607
6608 /* Decouple all encoders and their attached connectors from this crtc */
6609 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6610 if (encoder->crtc != crtc)
6611 continue;
6612
6613 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6614 if (connector->encoder != encoder)
6615 continue;
6616
6617 connector->encoder = NULL;
6618 }
6619 }
6620
6621 drm_helper_disable_unused_functions(dev);
6622 return 0;
6623}
6624
a6778b3c
DV		 6625static void
6626intel_crtc_prepare_encoders(struct drm_device *dev)
6627{
821112aa 6628 struct intel_encoder *encoder;
a6778b3c 6629
821112aa 6630 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
a6778b3c 6631 /* Disable unused encoders */
821112aa
DV		 6632 if (encoder->base.crtc == NULL)
6633 encoder->disable(encoder);
a6778b3c
DV		 6634 }
6635}
6636
6637bool intel_set_mode(struct drm_crtc *crtc,
6638 struct drm_display_mode *mode,
6639 int x, int y, struct drm_framebuffer *old_fb)
6640{
6641 struct drm_device *dev = crtc->dev;
dbf2b54e 6642 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 6643 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c
DV		 6644 struct drm_encoder_helper_funcs *encoder_funcs;
6645 int saved_x, saved_y;
6646 struct drm_encoder *encoder;
6647 bool ret = true;
6648
6649 crtc->enabled = drm_helper_crtc_in_use(crtc);
6650 if (!crtc->enabled)
6651 return true;
6652
6653 adjusted_mode = drm_mode_duplicate(dev, mode);
6654 if (!adjusted_mode)
6655 return false;
6656
6657 saved_hwmode = crtc->hwmode;
6658 saved_mode = crtc->mode;
6659 saved_x = crtc->x;
6660 saved_y = crtc->y;
6661
6662 /* Update crtc values up front so the driver can rely on them for mode
6663 * setting.
6664 */
6665 crtc->mode = *mode;
6666 crtc->x = x;
6667 crtc->y = y;
6668
6669 /* Pass our mode to the connectors and the CRTC to give them a chance to
6670 * adjust it according to limitations or connector properties, and also
6671 * a chance to reject the mode entirely.
6672 */
6673 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6674
6675 if (encoder->crtc != crtc)
6676 continue;
6677 encoder_funcs = encoder->helper_private;
6678 if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
6679 adjusted_mode))) {
6680 DRM_DEBUG_KMS("Encoder fixup failed\n");
6681 goto done;
6682 }
6683 }
6684
dbf2b54e 6685 if (!(ret = intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
a6778b3c
DV		 6686 DRM_DEBUG_KMS("CRTC fixup failed\n");
6687 goto done;
6688 }
6689 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6690
a6778b3c
DV		 6691 intel_crtc_prepare_encoders(dev);
6692
dbf2b54e 6693 dev_priv->display.crtc_disable(crtc);
a6778b3c
DV		 6694
6695 /* Set up the DPLL and any encoders state that needs to adjust or depend
6696 * on the DPLL.
6697 */
dbf2b54e 6698 ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
a6778b3c
DV		 6699 if (!ret)
6700 goto done;
6701
6702 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6703
6704 if (encoder->crtc != crtc)
6705 continue;
6706
6707 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6708 encoder->base.id, drm_get_encoder_name(encoder),
6709 mode->base.id, mode->name);
6710 encoder_funcs = encoder->helper_private;
6711 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6712 }
6713
6714 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
dbf2b54e 6715 dev_priv->display.crtc_enable(crtc);
a6778b3c 6716
a6778b3c
DV		 6717 /* Store real post-adjustment hardware mode. */
6718 crtc->hwmode = *adjusted_mode;
6719
6720 /* Calculate and store various constants which
6721 * are later needed by vblank and swap-completion
6722 * timestamping. They are derived from true hwmode.
6723 */
6724 drm_calc_timestamping_constants(crtc);
6725
6726 /* FIXME: add subpixel order */
6727done:
6728 drm_mode_destroy(dev, adjusted_mode);
6729 if (!ret) {
6730 crtc->hwmode = saved_hwmode;
6731 crtc->mode = saved_mode;
6732 crtc->x = saved_x;
6733 crtc->y = saved_y;
6734 }
6735
6736 return ret;
6737}
6738
50f56119
DV		 6739static int intel_crtc_set_config(struct drm_mode_set *set)
6740{
6741 struct drm_device *dev;
6742 struct drm_crtc *save_crtcs, *new_crtc, *crtc;
6743 struct drm_encoder *save_encoders, *new_encoder, *encoder;
6744 struct drm_framebuffer *old_fb = NULL;
6745 bool mode_changed = false; /* if true do a full mode set */
6746 bool fb_changed = false; /* if true and !mode_changed just do a flip */
6747 struct drm_connector *save_connectors, *connector;
6d832d18 6748 int count = 0, ro;
50f56119
DV		 6749 struct drm_mode_set save_set;
6750 int ret;
6751 int i;
6752
6753 DRM_DEBUG_KMS("\n");
6754
6755 if (!set)
6756 return -EINVAL;
6757
6758 if (!set->crtc)
6759 return -EINVAL;
6760
6761 if (!set->crtc->helper_private)
6762 return -EINVAL;
6763
50f56119
DV		 6764 if (!set->mode)
6765 set->fb = NULL;
6766
6767 if (set->fb) {
6768 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6769 set->crtc->base.id, set->fb->base.id,
6770 (int)set->num_connectors, set->x, set->y);
6771 } else {
6772 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6773 return intel_crtc_helper_disable(set->crtc);
6774 }
6775
6776 dev = set->crtc->dev;
6777
6778 /* Allocate space for the backup of all (non-pointer) crtc, encoder and
6779 * connector data. */
6780 save_crtcs = kzalloc(dev->mode_config.num_crtc *
6781 sizeof(struct drm_crtc), GFP_KERNEL);
6782 if (!save_crtcs)
6783 return -ENOMEM;
6784
6785 save_encoders = kzalloc(dev->mode_config.num_encoder *
6786 sizeof(struct drm_encoder), GFP_KERNEL);
6787 if (!save_encoders) {
6788 kfree(save_crtcs);
6789 return -ENOMEM;
6790 }
6791
6792 save_connectors = kzalloc(dev->mode_config.num_connector *
6793 sizeof(struct drm_connector), GFP_KERNEL);
6794 if (!save_connectors) {
6795 kfree(save_crtcs);
6796 kfree(save_encoders);
6797 return -ENOMEM;
6798 }
6799
6800 /* Copy data. Note that driver private data is not affected.
6801 * Should anything bad happen only the expected state is
6802 * restored, not the drivers personal bookkeeping.
6803 */
6804 count = 0;
6805 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6806 save_crtcs[count++] = *crtc;
6807 }
6808
6809 count = 0;
6810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6811 save_encoders[count++] = *encoder;
6812 }
6813
6814 count = 0;
6815 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6816 save_connectors[count++] = *connector;
6817 }
6818
6819 save_set.crtc = set->crtc;
6820 save_set.mode = &set->crtc->mode;
6821 save_set.x = set->crtc->x;
6822 save_set.y = set->crtc->y;
6823 save_set.fb = set->crtc->fb;
6824
6825 /* We should be able to check here if the fb has the same properties
6826 * and then just flip_or_move it */
6827 if (set->crtc->fb != set->fb) {
6828 /* If we have no fb then treat it as a full mode set */
6829 if (set->crtc->fb == NULL) {
6830 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6831 mode_changed = true;
6832 } else if (set->fb == NULL) {
6833 mode_changed = true;
6834 } else if (set->fb->depth != set->crtc->fb->depth) {
6835 mode_changed = true;
6836 } else if (set->fb->bits_per_pixel !=
6837 set->crtc->fb->bits_per_pixel) {
6838 mode_changed = true;
6839 } else
6840 fb_changed = true;
6841 }
6842
6843 if (set->x != set->crtc->x || set->y != set->crtc->y)
6844 fb_changed = true;
6845
6846 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6847 DRM_DEBUG_KMS("modes are different, full mode set\n");
6848 drm_mode_debug_printmodeline(&set->crtc->mode);
6849 drm_mode_debug_printmodeline(set->mode);
6850 mode_changed = true;
6851 }
6852
6853 /* a) traverse passed in connector list and get encoders for them */
6854 count = 0;
6855 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
50f56119
DV		 6856 new_encoder = connector->encoder;
6857 for (ro = 0; ro < set->num_connectors; ro++) {
6858 if (set->connectors[ro] == connector) {
6d832d18
DV		 6859 new_encoder =
6860 &intel_attached_encoder(connector)->base;
50f56119
DV		 6861 break;
6862 }
6863 }
6864
6865 if (new_encoder != connector->encoder) {
6866 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6867 mode_changed = true;
6868 /* If the encoder is reused for another connector, then
6869 * the appropriate crtc will be set later.
6870 */
6871 if (connector->encoder)
6872 connector->encoder->crtc = NULL;
6873 connector->encoder = new_encoder;
6874 }
6875 }
6876
50f56119
DV		 6877 count = 0;
6878 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6879 if (!connector->encoder)
6880 continue;
6881
6882 if (connector->encoder->crtc == set->crtc)
6883 new_crtc = NULL;
6884 else
6885 new_crtc = connector->encoder->crtc;
6886
6887 for (ro = 0; ro < set->num_connectors; ro++) {
6888 if (set->connectors[ro] == connector)
6889 new_crtc = set->crtc;
6890 }
6891
6892 /* Make sure the new CRTC will work with the encoder */
6893 if (new_crtc &&
6894 !intel_encoder_crtc_ok(connector->encoder, new_crtc)) {
6895 ret = -EINVAL;
6896 goto fail;
6897 }
6898 if (new_crtc != connector->encoder->crtc) {
6899 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6900 mode_changed = true;
6901 connector->encoder->crtc = new_crtc;
6902 }
6903 if (new_crtc) {
6904 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6905 connector->base.id, drm_get_connector_name(connector),
6906 new_crtc->base.id);
6907 } else {
6908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6909 connector->base.id, drm_get_connector_name(connector));
6910 }
6911 }
6912
50f56119
DV		 6913 if (mode_changed) {
6914 set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
6915 if (set->crtc->enabled) {
6916 DRM_DEBUG_KMS("attempting to set mode from"
6917 " userspace\n");
6918 drm_mode_debug_printmodeline(set->mode);
6919 old_fb = set->crtc->fb;
6920 set->crtc->fb = set->fb;
a6778b3c
DV		 6921 if (!intel_set_mode(set->crtc, set->mode,
6922 set->x, set->y, old_fb)) {
50f56119
DV		 6923 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
6924 set->crtc->base.id);
6925 set->crtc->fb = old_fb;
6926 ret = -EINVAL;
6927 goto fail;
6928 }
6929 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
6930 for (i = 0; i < set->num_connectors; i++) {
6931 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
6932 drm_get_connector_name(set->connectors[i]));
6933 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
6934 }
6935 }
6936 drm_helper_disable_unused_functions(dev);
6937 } else if (fb_changed) {
6938 set->crtc->x = set->x;
6939 set->crtc->y = set->y;
6940
6941 old_fb = set->crtc->fb;
6942 if (set->crtc->fb != set->fb)
6943 set->crtc->fb = set->fb;
4f660f49
DV		 6944 ret = intel_pipe_set_base(set->crtc,
6945 set->x, set->y, old_fb);
50f56119
DV		 6946 if (ret != 0) {
6947 set->crtc->fb = old_fb;
6948 goto fail;
6949 }
6950 }
6951
6952 kfree(save_connectors);
6953 kfree(save_encoders);
6954 kfree(save_crtcs);
6955 return 0;
6956
6957fail:
6958 /* Restore all previous data. */
6959 count = 0;
6960 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6961 *crtc = save_crtcs[count++];
6962 }
6963
6964 count = 0;
6965 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6966 *encoder = save_encoders[count++];
6967 }
6968
6969 count = 0;
6970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6971 *connector = save_connectors[count++];
6972 }
6973
6974 /* Try to restore the config */
6975 if (mode_changed &&
a6778b3c
DV		 6976 !intel_set_mode(save_set.crtc, save_set.mode,
6977 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 6978 DRM_ERROR("failed to restore config after modeset failure\n");
6979
6980 kfree(save_connectors);
6981 kfree(save_encoders);
6982 kfree(save_crtcs);
6983 return ret;
6984}
6985
f6e5b160 6986static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 6987 .cursor_set = intel_crtc_cursor_set,
6988 .cursor_move = intel_crtc_cursor_move,
6989 .gamma_set = intel_crtc_gamma_set,
50f56119 6990 .set_config = intel_crtc_set_config,
f6e5b160
CW		 6991 .destroy = intel_crtc_destroy,
6992 .page_flip = intel_crtc_page_flip,
6993};
6994
ee7b9f93
JB		 6995static void intel_pch_pll_init(struct drm_device *dev)
6996{
6997 drm_i915_private_t *dev_priv = dev->dev_private;
6998 int i;
6999
7000 if (dev_priv->num_pch_pll == 0) {
7001 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7002 return;
7003 }
7004
7005 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7006 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7007 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7008 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7009 }
7010}
7011
b358d0a6 7012static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7013{
22fd0fab 7014 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7015 struct intel_crtc *intel_crtc;
7016 int i;
7017
7018 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7019 if (intel_crtc == NULL)
7020 return;
7021
7022 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7023
7024 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7025 for (i = 0; i < 256; i++) {
7026 intel_crtc->lut_r[i] = i;
7027 intel_crtc->lut_g[i] = i;
7028 intel_crtc->lut_b[i] = i;
7029 }
7030
80824003
JB		 7031 /* Swap pipes & planes for FBC on pre-965 */
7032 intel_crtc->pipe = pipe;
7033 intel_crtc->plane = pipe;
e2e767ab 7034 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7035 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7036 intel_crtc->plane = !pipe;
80824003
JB		 7037 }
7038
22fd0fab
JB		 7039 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7040 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7041 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7042 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7043
5a354204 7044 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7045
79e53945 7046 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7047}
7048
08d7b3d1 7049int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7050 struct drm_file *file)
08d7b3d1 7051{
08d7b3d1 7052 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7053 struct drm_mode_object *drmmode_obj;
7054 struct intel_crtc *crtc;
08d7b3d1 7055
1cff8f6b
DV		 7056 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7057 return -ENODEV;
08d7b3d1 7058
c05422d5
DV		 7059 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7060 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7061
c05422d5 7062 if (!drmmode_obj) {
08d7b3d1
CW		 7063 DRM_ERROR("no such CRTC id\n");
7064 return -EINVAL;
7065 }
7066
c05422d5
DV		 7067 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7068 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7069
c05422d5 7070 return 0;
08d7b3d1
CW		 7071}
7072
66a9278e 7073static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7074{
66a9278e
DV		 7075 struct drm_device *dev = encoder->base.dev;
7076 struct intel_encoder *source_encoder;
79e53945 7077 int index_mask = 0;
79e53945
JB		 7078 int entry = 0;
7079
66a9278e
DV		 7080 list_for_each_entry(source_encoder,
7081 &dev->mode_config.encoder_list, base.head) {
7082
7083 if (encoder == source_encoder)
79e53945 7084 index_mask |= (1 << entry);
66a9278e
DV		 7085
7086 /* Intel hw has only one MUX where enocoders could be cloned. */
7087 if (encoder->cloneable && source_encoder->cloneable)
7088 index_mask |= (1 << entry);
7089
79e53945
JB		 7090 entry++;
7091 }
4ef69c7a 7092
79e53945
JB		 7093 return index_mask;
7094}
7095
4d302442
CW		 7096static bool has_edp_a(struct drm_device *dev)
7097{
7098 struct drm_i915_private *dev_priv = dev->dev_private;
7099
7100 if (!IS_MOBILE(dev))
7101 return false;
7102
7103 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7104 return false;
7105
7106 if (IS_GEN5(dev) &&
7107 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7108 return false;
7109
7110 return true;
7111}
7112
79e53945
JB		 7113static void intel_setup_outputs(struct drm_device *dev)
7114{
725e30ad 7115 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7116 struct intel_encoder *encoder;
cb0953d7 7117 bool dpd_is_edp = false;
f3cfcba6 7118 bool has_lvds;
79e53945 7119
f3cfcba6 7120 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7121 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7122 /* disable the panel fitter on everything but LVDS */
7123 I915_WRITE(PFIT_CONTROL, 0);
7124 }
79e53945 7125
bad720ff 7126 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7127 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7128
4d302442 7129 if (has_edp_a(dev))
ab9d7c30 7130 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7131
cb0953d7 7132 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7133 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7134 }
7135
7136 intel_crt_init(dev);
7137
0e72a5b5
ED		 7138 if (IS_HASWELL(dev)) {
7139 int found;
7140
7141 /* Haswell uses DDI functions to detect digital outputs */
7142 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7143 /* DDI A only supports eDP */
7144 if (found)
7145 intel_ddi_init(dev, PORT_A);
7146
7147 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7148 * register */
7149 found = I915_READ(SFUSE_STRAP);
7150
7151 if (found & SFUSE_STRAP_DDIB_DETECTED)
7152 intel_ddi_init(dev, PORT_B);
7153 if (found & SFUSE_STRAP_DDIC_DETECTED)
7154 intel_ddi_init(dev, PORT_C);
7155 if (found & SFUSE_STRAP_DDID_DETECTED)
7156 intel_ddi_init(dev, PORT_D);
7157 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7158 int found;
7159
30ad48b7 7160 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7161 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7162 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7163 if (!found)
08d644ad 7164 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7165 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7166 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7167 }
7168
7169 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7170 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7171
b708a1d5 7172 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7173 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7174
5eb08b69 7175 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7176 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7177
cb0953d7 7178 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7179 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7180 } else if (IS_VALLEYVIEW(dev)) {
7181 int found;
7182
7183 if (I915_READ(SDVOB) & PORT_DETECTED) {
7184 /* SDVOB multiplex with HDMIB */
7185 found = intel_sdvo_init(dev, SDVOB, true);
7186 if (!found)
08d644ad 7187 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7188 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7189 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7190 }
7191
7192 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7193 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7194
4a87d65d
JB		 7195 /* Shares lanes with HDMI on SDVOC */
7196 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 7197 intel_dp_init(dev, DP_C, PORT_C);
103a196f 7198 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7199 bool found = false;
7d57382e 7200
725e30ad 7201 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7202 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7203 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7204 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7205 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7206 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7207 }
27185ae1 7208
b01f2c3a
JB		 7209 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7210 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7211 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7212 }
725e30ad 7213 }
13520b05
KH		 7214
7215 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7216
b01f2c3a
JB		 7217 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7218 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7219 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7220 }
27185ae1
ML		 7221
7222 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7223
b01f2c3a
JB		 7224 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7225 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7226 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7227 }
7228 if (SUPPORTS_INTEGRATED_DP(dev)) {
7229 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7230 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7231 }
725e30ad 7232 }
27185ae1 7233
b01f2c3a
JB		 7234 if (SUPPORTS_INTEGRATED_DP(dev) &&
7235 (I915_READ(DP_D) & DP_DETECTED)) {
7236 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7237 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7238 }
bad720ff 7239 } else if (IS_GEN2(dev))
79e53945
JB		 7240 intel_dvo_init(dev);
7241
103a196f 7242 if (SUPPORTS_TV(dev))
79e53945
JB		 7243 intel_tv_init(dev);
7244
4ef69c7a
CW		 7245 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7246 encoder->base.possible_crtcs = encoder->crtc_mask;
7247 encoder->base.possible_clones =
66a9278e 7248 intel_encoder_clones(encoder);
79e53945 7249 }
47356eb6 7250
40579abe 7251 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7252 ironlake_init_pch_refclk(dev);
79e53945
JB		 7253}
7254
7255static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7256{
7257 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7258
7259 drm_framebuffer_cleanup(fb);
05394f39 7260 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7261
7262 kfree(intel_fb);
7263}
7264
7265static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7266 struct drm_file *file,
79e53945
JB		 7267 unsigned int *handle)
7268{
7269 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7270 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7271
05394f39 7272 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7273}
7274
7275static const struct drm_framebuffer_funcs intel_fb_funcs = {
7276 .destroy = intel_user_framebuffer_destroy,
7277 .create_handle = intel_user_framebuffer_create_handle,
7278};
7279
38651674
DA		 7280int intel_framebuffer_init(struct drm_device *dev,
7281 struct intel_framebuffer *intel_fb,
308e5bcb 7282 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7283 struct drm_i915_gem_object *obj)
79e53945 7284{
79e53945
JB		 7285 int ret;
7286
05394f39 7287 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7288 return -EINVAL;
7289
308e5bcb 7290 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7291 return -EINVAL;
7292
308e5bcb 7293 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7294 case DRM_FORMAT_RGB332:
7295 case DRM_FORMAT_RGB565:
7296 case DRM_FORMAT_XRGB8888:
b250da79 7297 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7298 case DRM_FORMAT_ARGB8888:
7299 case DRM_FORMAT_XRGB2101010:
7300 case DRM_FORMAT_ARGB2101010:
308e5bcb 7301 /* RGB formats are common across chipsets */
b5626747 7302 break;
04b3924d
VS		 7303 case DRM_FORMAT_YUYV:
7304 case DRM_FORMAT_UYVY:
7305 case DRM_FORMAT_YVYU:
7306 case DRM_FORMAT_VYUY:
57cd6508
CW		 7307 break;
7308 default:
aca25848
ED		 7309 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7310 mode_cmd->pixel_format);
57cd6508
CW		 7311 return -EINVAL;
7312 }
7313
79e53945
JB		 7314 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7315 if (ret) {
7316 DRM_ERROR("framebuffer init failed %d\n", ret);
7317 return ret;
7318 }
7319
7320 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7321 intel_fb->obj = obj;
79e53945
JB		 7322 return 0;
7323}
7324
79e53945
JB		 7325static struct drm_framebuffer *
7326intel_user_framebuffer_create(struct drm_device *dev,
7327 struct drm_file *filp,
308e5bcb 7328 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7329{
05394f39 7330 struct drm_i915_gem_object *obj;
79e53945 7331
308e5bcb
JB		 7332 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7333 mode_cmd->handles[0]));
c8725226 7334 if (&obj->base == NULL)
cce13ff7 7335 return ERR_PTR(-ENOENT);
79e53945 7336
d2dff872 7337 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7338}
7339
79e53945 7340static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7341 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7342 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7343};
7344
e70236a8
JB		 7345/* Set up chip specific display functions */
7346static void intel_init_display(struct drm_device *dev)
7347{
7348 struct drm_i915_private *dev_priv = dev->dev_private;
7349
7350 /* We always want a DPMS function */
f564048e 7351 if (HAS_PCH_SPLIT(dev)) {
f564048e 7352 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7353 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7354 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7355 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7356 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7357 } else {
f564048e 7358 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7359 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7360 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7361 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7362 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7363 }
e70236a8 7364
e70236a8 7365 /* Returns the core display clock speed */
25eb05fc
JB		 7366 if (IS_VALLEYVIEW(dev))
7367 dev_priv->display.get_display_clock_speed =
7368 valleyview_get_display_clock_speed;
7369 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7370 dev_priv->display.get_display_clock_speed =
7371 i945_get_display_clock_speed;
7372 else if (IS_I915G(dev))
7373 dev_priv->display.get_display_clock_speed =
7374 i915_get_display_clock_speed;
f2b115e6 7375 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7376 dev_priv->display.get_display_clock_speed =
7377 i9xx_misc_get_display_clock_speed;
7378 else if (IS_I915GM(dev))
7379 dev_priv->display.get_display_clock_speed =
7380 i915gm_get_display_clock_speed;
7381 else if (IS_I865G(dev))
7382 dev_priv->display.get_display_clock_speed =
7383 i865_get_display_clock_speed;
f0f8a9ce 7384 else if (IS_I85X(dev))
e70236a8
JB		 7385 dev_priv->display.get_display_clock_speed =
7386 i855_get_display_clock_speed;
7387 else /* 852, 830 */
7388 dev_priv->display.get_display_clock_speed =
7389 i830_get_display_clock_speed;
7390
7f8a8569 7391 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7392 if (IS_GEN5(dev)) {
674cf967 7393 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7394 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7395 } else if (IS_GEN6(dev)) {
674cf967 7396 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7397 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7398 } else if (IS_IVYBRIDGE(dev)) {
7399 /* FIXME: detect B0+ stepping and use auto training */
7400 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7401 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7402 } else if (IS_HASWELL(dev)) {
7403 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7404 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7405 } else
7406 dev_priv->display.update_wm = NULL;
6067aaea 7407 } else if (IS_G4X(dev)) {
e0dac65e 7408 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7409 }
8c9f3aaf
JB		 7410
7411 /* Default just returns -ENODEV to indicate unsupported */
7412 dev_priv->display.queue_flip = intel_default_queue_flip;
7413
7414 switch (INTEL_INFO(dev)->gen) {
7415 case 2:
7416 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7417 break;
7418
7419 case 3:
7420 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7421 break;
7422
7423 case 4:
7424 case 5:
7425 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7426 break;
7427
7428 case 6:
7429 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7430 break;
7c9017e5
JB		 7431 case 7:
7432 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7433 break;
8c9f3aaf 7434 }
e70236a8
JB		 7435}
7436
b690e96c
JB		 7437/*
7438 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7439 * resume, or other times. This quirk makes sure that's the case for
7440 * affected systems.
7441 */
0206e353 7442static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7443{
7444 struct drm_i915_private *dev_priv = dev->dev_private;
7445
7446 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7447 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7448}
7449
435793df
KP		 7450/*
7451 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7452 */
7453static void quirk_ssc_force_disable(struct drm_device *dev)
7454{
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7457 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7458}
7459
4dca20ef 7460/*
5a15ab5b
CE		 7461 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7462 * brightness value
4dca20ef
CE		 7463 */
7464static void quirk_invert_brightness(struct drm_device *dev)
7465{
7466 struct drm_i915_private *dev_priv = dev->dev_private;
7467 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7468 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7469}
7470
b690e96c
JB		 7471struct intel_quirk {
7472 int device;
7473 int subsystem_vendor;
7474 int subsystem_device;
7475 void (*hook)(struct drm_device *dev);
7476};
7477
c43b5634 7478static struct intel_quirk intel_quirks[] = {
b690e96c 7479 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7480 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7481
b690e96c
JB		 7482 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7483 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7484
b690e96c
JB		 7485 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7486 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7487
7488 /* 855 & before need to leave pipe A & dpll A up */
7489 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7490 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7491 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7492
7493 /* Lenovo U160 cannot use SSC on LVDS */
7494 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7495
7496 /* Sony Vaio Y cannot use SSC on LVDS */
7497 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7498
7499 /* Acer Aspire 5734Z must invert backlight brightness */
7500 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7501};
7502
7503static void intel_init_quirks(struct drm_device *dev)
7504{
7505 struct pci_dev *d = dev->pdev;
7506 int i;
7507
7508 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7509 struct intel_quirk *q = &intel_quirks[i];
7510
7511 if (d->device == q->device &&
7512 (d->subsystem_vendor == q->subsystem_vendor ||
7513 q->subsystem_vendor == PCI_ANY_ID) &&
7514 (d->subsystem_device == q->subsystem_device ||
7515 q->subsystem_device == PCI_ANY_ID))
7516 q->hook(dev);
7517 }
7518}
7519
9cce37f4
JB		 7520/* Disable the VGA plane that we never use */
7521static void i915_disable_vga(struct drm_device *dev)
7522{
7523 struct drm_i915_private *dev_priv = dev->dev_private;
7524 u8 sr1;
7525 u32 vga_reg;
7526
7527 if (HAS_PCH_SPLIT(dev))
7528 vga_reg = CPU_VGACNTRL;
7529 else
7530 vga_reg = VGACNTRL;
7531
7532 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7533 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7534 sr1 = inb(VGA_SR_DATA);
7535 outb(sr1 | 1<<5, VGA_SR_DATA);
7536 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7537 udelay(300);
7538
7539 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7540 POSTING_READ(vga_reg);
7541}
7542
f817586c
DV		 7543void intel_modeset_init_hw(struct drm_device *dev)
7544{
0232e927
ED		 7545 /* We attempt to init the necessary power wells early in the initialization
7546 * time, so the subsystems that expect power to be enabled can work.
7547 */
7548 intel_init_power_wells(dev);
7549
a8f78b58
ED		 7550 intel_prepare_ddi(dev);
7551
f817586c
DV		 7552 intel_init_clock_gating(dev);
7553
79f5b2c7 7554 mutex_lock(&dev->struct_mutex);
8090c6b9 7555 intel_enable_gt_powersave(dev);
79f5b2c7 7556 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7557}
7558
79e53945
JB		 7559void intel_modeset_init(struct drm_device *dev)
7560{
652c393a 7561 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7562 int i, ret;
79e53945
JB		 7563
7564 drm_mode_config_init(dev);
7565
7566 dev->mode_config.min_width = 0;
7567 dev->mode_config.min_height = 0;
7568
019d96cb
DA		 7569 dev->mode_config.preferred_depth = 24;
7570 dev->mode_config.prefer_shadow = 1;
7571
e6ecefaa 7572 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7573
b690e96c
JB		 7574 intel_init_quirks(dev);
7575
1fa61106
ED		 7576 intel_init_pm(dev);
7577
e70236a8
JB		 7578 intel_init_display(dev);
7579
a6c45cf0
CW		 7580 if (IS_GEN2(dev)) {
7581 dev->mode_config.max_width = 2048;
7582 dev->mode_config.max_height = 2048;
7583 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7584 dev->mode_config.max_width = 4096;
7585 dev->mode_config.max_height = 4096;
79e53945 7586 } else {
a6c45cf0
CW		 7587 dev->mode_config.max_width = 8192;
7588 dev->mode_config.max_height = 8192;
79e53945 7589 }
dd2757f8 7590 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7591
28c97730 7592 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7593 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7594
a3524f1b 7595 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7596 intel_crtc_init(dev, i);
00c2064b
JB		 7597 ret = intel_plane_init(dev, i);
7598 if (ret)
7599 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7600 }
7601
ee7b9f93
JB		 7602 intel_pch_pll_init(dev);
7603
9cce37f4
JB		 7604 /* Just disable it once at startup */
7605 i915_disable_vga(dev);
79e53945 7606 intel_setup_outputs(dev);
2c7111db
CW		 7607}
7608
24929352
DV		 7609static void
7610intel_connector_break_all_links(struct intel_connector *connector)
7611{
7612 connector->base.dpms = DRM_MODE_DPMS_OFF;
7613 connector->base.encoder = NULL;
7614 connector->encoder->connectors_active = false;
7615 connector->encoder->base.crtc = NULL;
7616}
7617
7618static void intel_sanitize_crtc(struct intel_crtc *crtc)
7619{
7620 struct drm_device *dev = crtc->base.dev;
7621 struct drm_i915_private *dev_priv = dev->dev_private;
7622 u32 reg, val;
7623
7624 /* Clear the dpms state for compatibility with code still using that
7625 * deprecated state variable. */
7626 crtc->dpms_mode = -1;
7627
7628 /* Clear any frame start delays used for debugging left by the BIOS */
7629 reg = PIPECONF(crtc->pipe);
7630 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7631
7632 /* We need to sanitize the plane -> pipe mapping first because this will
7633 * disable the crtc (and hence change the state) if it is wrong. */
7634 if (!HAS_PCH_SPLIT(dev)) {
7635 struct intel_connector *connector;
7636 bool plane;
7637
7638 reg = DSPCNTR(crtc->plane);
7639 val = I915_READ(reg);
7640
7641 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7642 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7643 goto ok;
7644
7645 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7646 crtc->base.base.id);
7647
7648 /* Pipe has the wrong plane attached and the plane is active.
7649 * Temporarily change the plane mapping and disable everything
7650 * ... */
7651 plane = crtc->plane;
7652 crtc->plane = !plane;
7653 dev_priv->display.crtc_disable(&crtc->base);
7654 crtc->plane = plane;
7655
7656 /* ... and break all links. */
7657 list_for_each_entry(connector, &dev->mode_config.connector_list,
7658 base.head) {
7659 if (connector->encoder->base.crtc != &crtc->base)
7660 continue;
7661
7662 intel_connector_break_all_links(connector);
7663 }
7664
7665 WARN_ON(crtc->active);
7666 crtc->base.enabled = false;
7667 }
7668ok:
7669
7670 /* Adjust the state of the output pipe according to whether we
7671 * have active connectors/encoders. */
7672 intel_crtc_update_dpms(&crtc->base);
7673
7674 if (crtc->active != crtc->base.enabled) {
7675 struct intel_encoder *encoder;
7676
7677 /* This can happen either due to bugs in the get_hw_state
7678 * functions or because the pipe is force-enabled due to the
7679 * pipe A quirk. */
7680 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7681 crtc->base.base.id,
7682 crtc->base.enabled ? "enabled" : "disabled",
7683 crtc->active ? "enabled" : "disabled");
7684
7685 crtc->base.enabled = crtc->active;
7686
7687 /* Because we only establish the connector -> encoder ->
7688 * crtc links if something is active, this means the
7689 * crtc is now deactivated. Break the links. connector
7690 * -> encoder links are only establish when things are
7691 * actually up, hence no need to break them. */
7692 WARN_ON(crtc->active);
7693
7694 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7695 WARN_ON(encoder->connectors_active);
7696 encoder->base.crtc = NULL;
7697 }
7698 }
7699}
7700
7701static void intel_sanitize_encoder(struct intel_encoder *encoder)
7702{
7703 struct intel_connector *connector;
7704 struct drm_device *dev = encoder->base.dev;
7705
7706 /* We need to check both for a crtc link (meaning that the
7707 * encoder is active and trying to read from a pipe) and the
7708 * pipe itself being active. */
7709 bool has_active_crtc = encoder->base.crtc &&
7710 to_intel_crtc(encoder->base.crtc)->active;
7711
7712 if (encoder->connectors_active && !has_active_crtc) {
7713 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
7714 encoder->base.base.id,
7715 drm_get_encoder_name(&encoder->base));
7716
7717 /* Connector is active, but has no active pipe. This is
7718 * fallout from our resume register restoring. Disable
7719 * the encoder manually again. */
7720 if (encoder->base.crtc) {
7721 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
7722 encoder->base.base.id,
7723 drm_get_encoder_name(&encoder->base));
7724 encoder->disable(encoder);
7725 }
7726
7727 /* Inconsistent output/port/pipe state happens presumably due to
7728 * a bug in one of the get_hw_state functions. Or someplace else
7729 * in our code, like the register restore mess on resume. Clamp
7730 * things to off as a safer default. */
7731 list_for_each_entry(connector,
7732 &dev->mode_config.connector_list,
7733 base.head) {
7734 if (connector->encoder != encoder)
7735 continue;
7736
7737 intel_connector_break_all_links(connector);
7738 }
7739 }
7740 /* Enabled encoders without active connectors will be fixed in
7741 * the crtc fixup. */
7742}
7743
7744/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
7745 * and i915 state tracking structures. */
7746void intel_modeset_setup_hw_state(struct drm_device *dev)
7747{
7748 struct drm_i915_private *dev_priv = dev->dev_private;
7749 enum pipe pipe;
7750 u32 tmp;
7751 struct intel_crtc *crtc;
7752 struct intel_encoder *encoder;
7753 struct intel_connector *connector;
7754
7755 for_each_pipe(pipe) {
7756 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7757
7758 tmp = I915_READ(PIPECONF(pipe));
7759 if (tmp & PIPECONF_ENABLE)
7760 crtc->active = true;
7761 else
7762 crtc->active = false;
7763
7764 crtc->base.enabled = crtc->active;
7765
7766 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
7767 crtc->base.base.id,
7768 crtc->active ? "enabled" : "disabled");
7769 }
7770
7771 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7772 base.head) {
7773 pipe = 0;
7774
7775 if (encoder->get_hw_state(encoder, &pipe)) {
7776 encoder->base.crtc =
7777 dev_priv->pipe_to_crtc_mapping[pipe];
7778 } else {
7779 encoder->base.crtc = NULL;
7780 }
7781
7782 encoder->connectors_active = false;
7783 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
7784 encoder->base.base.id,
7785 drm_get_encoder_name(&encoder->base),
7786 encoder->base.crtc ? "enabled" : "disabled",
7787 pipe);
7788 }
7789
7790 list_for_each_entry(connector, &dev->mode_config.connector_list,
7791 base.head) {
7792 if (connector->get_hw_state(connector)) {
7793 connector->base.dpms = DRM_MODE_DPMS_ON;
7794 connector->encoder->connectors_active = true;
7795 connector->base.encoder = &connector->encoder->base;
7796 } else {
7797 connector->base.dpms = DRM_MODE_DPMS_OFF;
7798 connector->base.encoder = NULL;
7799 }
7800 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
7801 connector->base.base.id,
7802 drm_get_connector_name(&connector->base),
7803 connector->base.encoder ? "enabled" : "disabled");
7804 }
7805
7806 /* HW state is read out, now we need to sanitize this mess. */
7807 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7808 base.head) {
7809 intel_sanitize_encoder(encoder);
7810 }
7811
7812 for_each_pipe(pipe) {
7813 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7814 intel_sanitize_crtc(crtc);
7815 }
7816}
7817
2c7111db
CW		 7818void intel_modeset_gem_init(struct drm_device *dev)
7819{
1833b134 7820 intel_modeset_init_hw(dev);
02e792fb
DV		 7821
7822 intel_setup_overlay(dev);
24929352
DV		 7823
7824 intel_modeset_setup_hw_state(dev);
79e53945
JB		 7825}
7826
7827void intel_modeset_cleanup(struct drm_device *dev)
7828{
652c393a
JB		 7829 struct drm_i915_private *dev_priv = dev->dev_private;
7830 struct drm_crtc *crtc;
7831 struct intel_crtc *intel_crtc;
7832
f87ea761 7833 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7834 mutex_lock(&dev->struct_mutex);
7835
723bfd70
JB		 7836 intel_unregister_dsm_handler();
7837
7838
652c393a
JB		 7839 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7840 /* Skip inactive CRTCs */
7841 if (!crtc->fb)
7842 continue;
7843
7844 intel_crtc = to_intel_crtc(crtc);
3dec0095 7845 intel_increase_pllclock(crtc);
652c393a
JB		 7846 }
7847
973d04f9 7848 intel_disable_fbc(dev);
e70236a8 7849
8090c6b9 7850 intel_disable_gt_powersave(dev);
0cdab21f 7851
930ebb46
DV		 7852 ironlake_teardown_rc6(dev);
7853
57f350b6
JB		 7854 if (IS_VALLEYVIEW(dev))
7855 vlv_init_dpio(dev);
7856
69341a5e
KH		 7857 mutex_unlock(&dev->struct_mutex);
7858
6c0d9350
DV		 7859 /* Disable the irq before mode object teardown, for the irq might
7860 * enqueue unpin/hotplug work. */
7861 drm_irq_uninstall(dev);
7862 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 7863 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 7864
1630fe75
CW		 7865 /* flush any delayed tasks or pending work */
7866 flush_scheduled_work();
7867
79e53945
JB		 7868 drm_mode_config_cleanup(dev);
7869}
7870
f1c79df3
ZW		 7871/*
7872 * Return which encoder is currently attached for connector.
7873 */
df0e9248 7874struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7875{
df0e9248
CW		 7876 return &intel_attached_encoder(connector)->base;
7877}
f1c79df3 7878
df0e9248
CW		 7879void intel_connector_attach_encoder(struct intel_connector *connector,
7880 struct intel_encoder *encoder)
7881{
7882 connector->encoder = encoder;
7883 drm_mode_connector_attach_encoder(&connector->base,
7884 &encoder->base);
79e53945 7885}
28d52043
DA		 7886
7887/*
7888 * set vga decode state - true == enable VGA decode
7889 */
7890int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7891{
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7893 u16 gmch_ctrl;
7894
7895 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7896 if (state)
7897 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7898 else
7899 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7900 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7901 return 0;
7902}
c4a1d9e4
CW		 7903
7904#ifdef CONFIG_DEBUG_FS
7905#include <linux/seq_file.h>
7906
7907struct intel_display_error_state {
7908 struct intel_cursor_error_state {
7909 u32 control;
7910 u32 position;
7911 u32 base;
7912 u32 size;
52331309 7913 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 7914
7915 struct intel_pipe_error_state {
7916 u32 conf;
7917 u32 source;
7918
7919 u32 htotal;
7920 u32 hblank;
7921 u32 hsync;
7922 u32 vtotal;
7923 u32 vblank;
7924 u32 vsync;
52331309 7925 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 7926
7927 struct intel_plane_error_state {
7928 u32 control;
7929 u32 stride;
7930 u32 size;
7931 u32 pos;
7932 u32 addr;
7933 u32 surface;
7934 u32 tile_offset;
52331309 7935 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 7936};
7937
7938struct intel_display_error_state *
7939intel_display_capture_error_state(struct drm_device *dev)
7940{
0206e353 7941 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7942 struct intel_display_error_state *error;
7943 int i;
7944
7945 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7946 if (error == NULL)
7947 return NULL;
7948
52331309 7949 for_each_pipe(i) {
c4a1d9e4
CW		 7950 error->cursor[i].control = I915_READ(CURCNTR(i));
7951 error->cursor[i].position = I915_READ(CURPOS(i));
7952 error->cursor[i].base = I915_READ(CURBASE(i));
7953
7954 error->plane[i].control = I915_READ(DSPCNTR(i));
7955 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7956 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7957 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7958 error->plane[i].addr = I915_READ(DSPADDR(i));
7959 if (INTEL_INFO(dev)->gen >= 4) {
7960 error->plane[i].surface = I915_READ(DSPSURF(i));
7961 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7962 }
7963
7964 error->pipe[i].conf = I915_READ(PIPECONF(i));
7965 error->pipe[i].source = I915_READ(PIPESRC(i));
7966 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7967 error->pipe[i].hblank = I915_READ(HBLANK(i));
7968 error->pipe[i].hsync = I915_READ(HSYNC(i));
7969 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7970 error->pipe[i].vblank = I915_READ(VBLANK(i));
7971 error->pipe[i].vsync = I915_READ(VSYNC(i));
7972 }
7973
7974 return error;
7975}
7976
7977void
7978intel_display_print_error_state(struct seq_file *m,
7979 struct drm_device *dev,
7980 struct intel_display_error_state *error)
7981{
52331309 7982 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7983 int i;
7984
52331309
DL		 7985 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7986 for_each_pipe(i) {
c4a1d9e4
CW		 7987 seq_printf(m, "Pipe [%d]:\n", i);
7988 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7989 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7990 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7991 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7992 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7993 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7994 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7995 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7996
7997 seq_printf(m, "Plane [%d]:\n", i);
7998 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7999 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8000 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8001 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8002 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8003 if (INTEL_INFO(dev)->gen >= 4) {
8004 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8005 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8006 }
8007
8008 seq_printf(m, "Cursor [%d]:\n", i);
8009 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8010 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8011 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8012 }
8013}
8014#endif
ubuntu-bionic-kernel mirror