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drm/i915: add lpt_pch_enable
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a
JB		 1581/**
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
ee7b9f93 1589static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
040484af
JB		 1673static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
1724static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
14f86147
DL		 1839 if (dev_priv->info->gen >= 4)
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 else
1842 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1843}
1844
b24e7179
JB		 1845/**
1846 * intel_enable_plane - enable a display plane on a given pipe
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to enable
1849 * @pipe: pipe being fed
1850 *
1851 * Enable @plane on @pipe, making sure that @pipe is running first.
1852 */
1853static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855{
1856 int reg;
1857 u32 val;
1858
1859 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860 assert_pipe_enabled(dev_priv, pipe);
1861
1862 reg = DSPCNTR(plane);
1863 val = I915_READ(reg);
00d70b15
CW		 1864 if (val & DISPLAY_PLANE_ENABLE)
1865 return;
1866
1867 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1868 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1869 intel_wait_for_vblank(dev_priv->dev, pipe);
1870}
1871
b24e7179
JB		 1872/**
1873 * intel_disable_plane - disable a display plane
1874 * @dev_priv: i915 private structure
1875 * @plane: plane to disable
1876 * @pipe: pipe consuming the data
1877 *
1878 * Disable @plane; should be an independent operation.
1879 */
1880static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881 enum plane plane, enum pipe pipe)
1882{
1883 int reg;
1884 u32 val;
1885
1886 reg = DSPCNTR(plane);
1887 val = I915_READ(reg);
00d70b15
CW		 1888 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889 return;
1890
1891 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1892 intel_flush_display_plane(dev_priv, plane);
1893 intel_wait_for_vblank(dev_priv->dev, pipe);
1894}
1895
127bd2ac 1896int
48b956c5 1897intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1898 struct drm_i915_gem_object *obj,
919926ae 1899 struct intel_ring_buffer *pipelined)
6b95a207 1900{
ce453d81 1901 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1902 u32 alignment;
1903 int ret;
1904
05394f39 1905 switch (obj->tiling_mode) {
6b95a207 1906 case I915_TILING_NONE:
534843da
CW		 1907 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908 alignment = 128 * 1024;
a6c45cf0 1909 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1910 alignment = 4 * 1024;
1911 else
1912 alignment = 64 * 1024;
6b95a207
KH		 1913 break;
1914 case I915_TILING_X:
1915 /* pin() will align the object as required by fence */
1916 alignment = 0;
1917 break;
1918 case I915_TILING_Y:
1919 /* FIXME: Is this true? */
1920 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921 return -EINVAL;
1922 default:
1923 BUG();
1924 }
1925
ce453d81 1926 dev_priv->mm.interruptible = false;
2da3b9b9 1927 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1928 if (ret)
ce453d81 1929 goto err_interruptible;
6b95a207
KH		 1930
1931 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932 * fence, whereas 965+ only requires a fence if using
1933 * framebuffer compression. For simplicity, we always install
1934 * a fence as the cost is not that onerous.
1935 */
06d98131 1936 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1937 if (ret)
1938 goto err_unpin;
1690e1eb 1939
9a5a53b3 1940 i915_gem_object_pin_fence(obj);
6b95a207 1941
ce453d81 1942 dev_priv->mm.interruptible = true;
6b95a207 1943 return 0;
48b956c5
CW		 1944
1945err_unpin:
1946 i915_gem_object_unpin(obj);
ce453d81
CW		 1947err_interruptible:
1948 dev_priv->mm.interruptible = true;
48b956c5 1949 return ret;
6b95a207
KH		 1950}
1951
1690e1eb
CW		 1952void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953{
1954 i915_gem_object_unpin_fence(obj);
1955 i915_gem_object_unpin(obj);
1956}
1957
c2c75131
DV		 1958/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959 * is assumed to be a power-of-two. */
5a35e99e
DL		 1960unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961 unsigned int bpp,
1962 unsigned int pitch)
c2c75131
DV		 1963{
1964 int tile_rows, tiles;
1965
1966 tile_rows = *y / 8;
1967 *y %= 8;
1968 tiles = *x / (512/bpp);
1969 *x %= 512/bpp;
1970
1971 return tile_rows * pitch * 8 + tiles * 4096;
1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
1992 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2003 switch (fb->pixel_format) {
2004 case DRM_FORMAT_C8:
81255565
JB		 2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
57779d06
VS		 2007 case DRM_FORMAT_XRGB1555:
2008 case DRM_FORMAT_ARGB1555:
2009 dspcntr |= DISPPLANE_BGRX555;
81255565 2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
2013 break;
2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2029 break;
2030 default:
57779d06 2031 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2032 return -EINVAL;
2033 }
57779d06 2034
a6c45cf0 2035 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2036 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2037 dspcntr |= DISPPLANE_TILED;
2038 else
2039 dspcntr &= ~DISPPLANE_TILED;
2040 }
2041
5eddb70b 2042 I915_WRITE(reg, dspcntr);
81255565 2043
e506a0c6 2044 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2045
c2c75131
DV		 2046 if (INTEL_INFO(dev)->gen >= 4) {
2047 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2048 intel_gen4_compute_offset_xtiled(&x, &y,
2049 fb->bits_per_pixel / 8,
2050 fb->pitches[0]);
c2c75131
DV		 2051 linear_offset -= intel_crtc->dspaddr_offset;
2052 } else {
e506a0c6 2053 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2054 }
e506a0c6
DV		 2055
2056 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2057 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2058 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2059 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2060 I915_MODIFY_DISPBASE(DSPSURF(plane),
2061 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2062 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2063 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2064 } else
e506a0c6 2065 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2066 POSTING_READ(reg);
81255565 2067
17638cd6
JB		 2068 return 0;
2069}
2070
2071static int ironlake_update_plane(struct drm_crtc *crtc,
2072 struct drm_framebuffer *fb, int x, int y)
2073{
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077 struct intel_framebuffer *intel_fb;
2078 struct drm_i915_gem_object *obj;
2079 int plane = intel_crtc->plane;
e506a0c6 2080 unsigned long linear_offset;
17638cd6
JB		 2081 u32 dspcntr;
2082 u32 reg;
2083
2084 switch (plane) {
2085 case 0:
2086 case 1:
27f8227b 2087 case 2:
17638cd6
JB		 2088 break;
2089 default:
2090 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091 return -EINVAL;
2092 }
2093
2094 intel_fb = to_intel_framebuffer(fb);
2095 obj = intel_fb->obj;
2096
2097 reg = DSPCNTR(plane);
2098 dspcntr = I915_READ(reg);
2099 /* Mask out pixel format bits in case we change it */
2100 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2101 switch (fb->pixel_format) {
2102 case DRM_FORMAT_C8:
17638cd6
JB		 2103 dspcntr |= DISPPLANE_8BPP;
2104 break;
57779d06
VS		 2105 case DRM_FORMAT_RGB565:
2106 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2107 break;
57779d06
VS		 2108 case DRM_FORMAT_XRGB8888:
2109 case DRM_FORMAT_ARGB8888:
2110 dspcntr |= DISPPLANE_BGRX888;
2111 break;
2112 case DRM_FORMAT_XBGR8888:
2113 case DRM_FORMAT_ABGR8888:
2114 dspcntr |= DISPPLANE_RGBX888;
2115 break;
2116 case DRM_FORMAT_XRGB2101010:
2117 case DRM_FORMAT_ARGB2101010:
2118 dspcntr |= DISPPLANE_BGRX101010;
2119 break;
2120 case DRM_FORMAT_XBGR2101010:
2121 case DRM_FORMAT_ABGR2101010:
2122 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2123 break;
2124 default:
57779d06 2125 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2126 return -EINVAL;
2127 }
2128
2129 if (obj->tiling_mode != I915_TILING_NONE)
2130 dspcntr |= DISPPLANE_TILED;
2131 else
2132 dspcntr &= ~DISPPLANE_TILED;
2133
2134 /* must disable */
2135 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137 I915_WRITE(reg, dspcntr);
2138
e506a0c6 2139 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2140 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2141 intel_gen4_compute_offset_xtiled(&x, &y,
2142 fb->bits_per_pixel / 8,
2143 fb->pitches[0]);
c2c75131 2144 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2145
e506a0c6
DV		 2146 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2148 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2149 I915_MODIFY_DISPBASE(DSPSURF(plane),
2150 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2151 if (IS_HASWELL(dev)) {
2152 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2153 } else {
2154 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2155 I915_WRITE(DSPLINOFF(plane), linear_offset);
2156 }
17638cd6
JB		 2157 POSTING_READ(reg);
2158
2159 return 0;
2160}
2161
2162/* Assume fb object is pinned & idle & fenced and just update base pointers */
2163static int
2164intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2165 int x, int y, enum mode_set_atomic state)
2166{
2167 struct drm_device *dev = crtc->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2169
6b8e6ed0
CW		 2170 if (dev_priv->display.disable_fbc)
2171 dev_priv->display.disable_fbc(dev);
3dec0095 2172 intel_increase_pllclock(crtc);
81255565 2173
6b8e6ed0 2174 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2175}
2176
14667a4b
CW		 2177static int
2178intel_finish_fb(struct drm_framebuffer *old_fb)
2179{
2180 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2181 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182 bool was_interruptible = dev_priv->mm.interruptible;
2183 int ret;
2184
2185 wait_event(dev_priv->pending_flip_queue,
2186 atomic_read(&dev_priv->mm.wedged) ||
2187 atomic_read(&obj->pending_flip) == 0);
2188
2189 /* Big Hammer, we also need to ensure that any pending
2190 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2191 * current scanout is retired before unpinning the old
2192 * framebuffer.
2193 *
2194 * This should only fail upon a hung GPU, in which case we
2195 * can safely continue.
2196 */
2197 dev_priv->mm.interruptible = false;
2198 ret = i915_gem_object_finish_gpu(obj);
2199 dev_priv->mm.interruptible = was_interruptible;
2200
2201 return ret;
2202}
2203
198598d0
VS		 2204static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2205{
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_master_private *master_priv;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210 if (!dev->primary->master)
2211 return;
2212
2213 master_priv = dev->primary->master->driver_priv;
2214 if (!master_priv->sarea_priv)
2215 return;
2216
2217 switch (intel_crtc->pipe) {
2218 case 0:
2219 master_priv->sarea_priv->pipeA_x = x;
2220 master_priv->sarea_priv->pipeA_y = y;
2221 break;
2222 case 1:
2223 master_priv->sarea_priv->pipeB_x = x;
2224 master_priv->sarea_priv->pipeB_y = y;
2225 break;
2226 default:
2227 break;
2228 }
2229}
2230
5c3b82e2 2231static int
3c4fdcfb 2232intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2233 struct drm_framebuffer *fb)
79e53945
JB		 2234{
2235 struct drm_device *dev = crtc->dev;
6b8e6ed0 2236 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2238 struct drm_framebuffer *old_fb;
5c3b82e2 2239 int ret;
79e53945
JB		 2240
2241 /* no fb bound */
94352cf9 2242 if (!fb) {
a5071c2f 2243 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2244 return 0;
2245 }
2246
5826eca5
ED		 2247 if(intel_crtc->plane > dev_priv->num_pipe) {
2248 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2249 intel_crtc->plane,
2250 dev_priv->num_pipe);
5c3b82e2 2251 return -EINVAL;
79e53945
JB		 2252 }
2253
5c3b82e2 2254 mutex_lock(&dev->struct_mutex);
265db958 2255 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2256 to_intel_framebuffer(fb)->obj,
919926ae 2257 NULL);
5c3b82e2
CW		 2258 if (ret != 0) {
2259 mutex_unlock(&dev->struct_mutex);
a5071c2f 2260 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2261 return ret;
2262 }
79e53945 2263
94352cf9
DV		 2264 if (crtc->fb)
2265 intel_finish_fb(crtc->fb);
265db958 2266
94352cf9 2267 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2268 if (ret) {
94352cf9 2269 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2270 mutex_unlock(&dev->struct_mutex);
a5071c2f 2271 DRM_ERROR("failed to update base address\n");
4e6cfefc 2272 return ret;
79e53945 2273 }
3c4fdcfb 2274
94352cf9
DV		 2275 old_fb = crtc->fb;
2276 crtc->fb = fb;
6c4c86f5
DV		 2277 crtc->x = x;
2278 crtc->y = y;
94352cf9 2279
b7f1de28
CW		 2280 if (old_fb) {
2281 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2282 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2283 }
652c393a 2284
6b8e6ed0 2285 intel_update_fbc(dev);
5c3b82e2 2286 mutex_unlock(&dev->struct_mutex);
79e53945 2287
198598d0 2288 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2289
2290 return 0;
79e53945
JB		 2291}
2292
5eddb70b 2293static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2294{
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 u32 dpa_ctl;
2298
28c97730 2299 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2300 dpa_ctl = I915_READ(DP_A);
2301 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2302
2303 if (clock < 200000) {
2304 u32 temp;
2305 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2306 /* workaround for 160Mhz:
2307 1) program 0x4600c bits 15:0 = 0x8124
2308 2) program 0x46010 bit 0 = 1
2309 3) program 0x46034 bit 24 = 1
2310 4) program 0x64000 bit 14 = 1
2311 */
2312 temp = I915_READ(0x4600c);
2313 temp &= 0xffff0000;
2314 I915_WRITE(0x4600c, temp | 0x8124);
2315
2316 temp = I915_READ(0x46010);
2317 I915_WRITE(0x46010, temp | 1);
2318
2319 temp = I915_READ(0x46034);
2320 I915_WRITE(0x46034, temp | (1 << 24));
2321 } else {
2322 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2323 }
2324 I915_WRITE(DP_A, dpa_ctl);
2325
5eddb70b 2326 POSTING_READ(DP_A);
32f9d658
ZW		 2327 udelay(500);
2328}
2329
5e84e1a4
ZW		 2330static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331{
2332 struct drm_device *dev = crtc->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335 int pipe = intel_crtc->pipe;
2336 u32 reg, temp;
2337
2338 /* enable normal train */
2339 reg = FDI_TX_CTL(pipe);
2340 temp = I915_READ(reg);
61e499bf 2341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2344 } else {
2345 temp &= ~FDI_LINK_TRAIN_NONE;
2346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2347 }
5e84e1a4
ZW		 2348 I915_WRITE(reg, temp);
2349
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 if (HAS_PCH_CPT(dev)) {
2353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355 } else {
2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_NONE;
2358 }
2359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361 /* wait one idle pattern time */
2362 POSTING_READ(reg);
2363 udelay(1000);
357555c0
JB		 2364
2365 /* IVB wants error correction enabled */
2366 if (IS_IVYBRIDGE(dev))
2367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2369}
2370
291427f5
JB		 2371static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2372{
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 u32 flags = I915_READ(SOUTH_CHICKEN1);
2375
2376 flags |= FDI_PHASE_SYNC_OVR(pipe);
2377 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2378 flags |= FDI_PHASE_SYNC_EN(pipe);
2379 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2380 POSTING_READ(SOUTH_CHICKEN1);
2381}
2382
01a415fd
DV		 2383static void ivb_modeset_global_resources(struct drm_device *dev)
2384{
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 struct intel_crtc *pipe_B_crtc =
2387 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2388 struct intel_crtc *pipe_C_crtc =
2389 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2390 uint32_t temp;
2391
2392 /* When everything is off disable fdi C so that we could enable fdi B
2393 * with all lanes. XXX: This misses the case where a pipe is not using
2394 * any pch resources and so doesn't need any fdi lanes. */
2395 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2396 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2397 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2398
2399 temp = I915_READ(SOUTH_CHICKEN1);
2400 temp &= ~FDI_BC_BIFURCATION_SELECT;
2401 DRM_DEBUG_KMS("disabling fdi C rx\n");
2402 I915_WRITE(SOUTH_CHICKEN1, temp);
2403 }
2404}
2405
8db9d77b
ZW		 2406/* The FDI link training functions for ILK/Ibexpeak. */
2407static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
0fc932b8 2413 int plane = intel_crtc->plane;
5eddb70b 2414 u32 reg, temp, tries;
8db9d77b 2415
0fc932b8
JB		 2416 /* FDI needs bits from pipe & plane first */
2417 assert_pipe_enabled(dev_priv, pipe);
2418 assert_plane_enabled(dev_priv, plane);
2419
e1a44743
AJ		 2420 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2421 for train result */
5eddb70b
CW		 2422 reg = FDI_RX_IMR(pipe);
2423 temp = I915_READ(reg);
e1a44743
AJ		 2424 temp &= ~FDI_RX_SYMBOL_LOCK;
2425 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2426 I915_WRITE(reg, temp);
2427 I915_READ(reg);
e1a44743
AJ		 2428 udelay(150);
2429
8db9d77b 2430 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
77ffb597
AJ		 2433 temp &= ~(7 << 19);
2434 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2437 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2438
5eddb70b
CW		 2439 reg = FDI_RX_CTL(pipe);
2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2443 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2444
2445 POSTING_READ(reg);
8db9d77b
ZW		 2446 udelay(150);
2447
5b2adf89 2448 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2449 if (HAS_PCH_IBX(dev)) {
2450 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2451 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2452 FDI_RX_PHASE_SYNC_POINTER_EN);
2453 }
5b2adf89 2454
5eddb70b 2455 reg = FDI_RX_IIR(pipe);
e1a44743 2456 for (tries = 0; tries < 5; tries++) {
5eddb70b 2457 temp = I915_READ(reg);
8db9d77b
ZW		 2458 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460 if ((temp & FDI_RX_BIT_LOCK)) {
2461 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2462 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2463 break;
2464 }
8db9d77b 2465 }
e1a44743 2466 if (tries == 5)
5eddb70b 2467 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2468
2469 /* Train 2 */
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_NONE;
2473 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2474 I915_WRITE(reg, temp);
8db9d77b 2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 temp &= ~FDI_LINK_TRAIN_NONE;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2480 I915_WRITE(reg, temp);
8db9d77b 2481
5eddb70b
CW		 2482 POSTING_READ(reg);
2483 udelay(150);
8db9d77b 2484
5eddb70b 2485 reg = FDI_RX_IIR(pipe);
e1a44743 2486 for (tries = 0; tries < 5; tries++) {
5eddb70b 2487 temp = I915_READ(reg);
8db9d77b
ZW		 2488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2491 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2492 DRM_DEBUG_KMS("FDI train 2 done.\n");
2493 break;
2494 }
8db9d77b 2495 }
e1a44743 2496 if (tries == 5)
5eddb70b 2497 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2498
2499 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2500
8db9d77b
ZW		 2501}
2502
0206e353 2503static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2504 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508};
2509
2510/* The FDI link training functions for SNB/Cougarpoint. */
2511static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512{
2513 struct drm_device *dev = crtc->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516 int pipe = intel_crtc->pipe;
fa37d39e 2517 u32 reg, temp, i, retry;
8db9d77b 2518
e1a44743
AJ		 2519 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520 for train result */
5eddb70b
CW		 2521 reg = FDI_RX_IMR(pipe);
2522 temp = I915_READ(reg);
e1a44743
AJ		 2523 temp &= ~FDI_RX_SYMBOL_LOCK;
2524 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2525 I915_WRITE(reg, temp);
2526
2527 POSTING_READ(reg);
e1a44743
AJ		 2528 udelay(150);
2529
8db9d77b 2530 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
77ffb597
AJ		 2533 temp &= ~(7 << 19);
2534 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538 /* SNB-B */
2539 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2540 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2541
d74cf324
DV		 2542 I915_WRITE(FDI_RX_MISC(pipe),
2543 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
5eddb70b
CW		 2545 reg = FDI_RX_CTL(pipe);
2546 temp = I915_READ(reg);
8db9d77b
ZW		 2547 if (HAS_PCH_CPT(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550 } else {
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553 }
5eddb70b
CW		 2554 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556 POSTING_READ(reg);
8db9d77b
ZW		 2557 udelay(150);
2558
291427f5
JB		 2559 if (HAS_PCH_CPT(dev))
2560 cpt_phase_pointer_enable(dev, pipe);
2561
0206e353 2562 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
8db9d77b
ZW		 2565 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
8db9d77b
ZW		 2570 udelay(500);
2571
fa37d39e
SP		 2572 for (retry = 0; retry < 5; retry++) {
2573 reg = FDI_RX_IIR(pipe);
2574 temp = I915_READ(reg);
2575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576 if (temp & FDI_RX_BIT_LOCK) {
2577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 break;
2580 }
2581 udelay(50);
8db9d77b 2582 }
fa37d39e
SP		 2583 if (retry < 5)
2584 break;
8db9d77b
ZW		 2585 }
2586 if (i == 4)
5eddb70b 2587 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2588
2589 /* Train 2 */
5eddb70b
CW		 2590 reg = FDI_TX_CTL(pipe);
2591 temp = I915_READ(reg);
8db9d77b
ZW		 2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_2;
2594 if (IS_GEN6(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 /* SNB-B */
2597 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598 }
5eddb70b 2599 I915_WRITE(reg, temp);
8db9d77b 2600
5eddb70b
CW		 2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 if (HAS_PCH_CPT(dev)) {
2604 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606 } else {
2607 temp &= ~FDI_LINK_TRAIN_NONE;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609 }
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
8db9d77b
ZW		 2613 udelay(150);
2614
0206e353 2615 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
8db9d77b
ZW		 2623 udelay(500);
2624
fa37d39e
SP		 2625 for (retry = 0; retry < 5; retry++) {
2626 reg = FDI_RX_IIR(pipe);
2627 temp = I915_READ(reg);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629 if (temp & FDI_RX_SYMBOL_LOCK) {
2630 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 break;
2633 }
2634 udelay(50);
8db9d77b 2635 }
fa37d39e
SP		 2636 if (retry < 5)
2637 break;
8db9d77b
ZW		 2638 }
2639 if (i == 4)
5eddb70b 2640 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2641
2642 DRM_DEBUG_KMS("FDI train done.\n");
2643}
2644
357555c0
JB		 2645/* Manual link training for Ivy Bridge A0 parts */
2646static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 int pipe = intel_crtc->pipe;
2652 u32 reg, temp, i;
2653
2654 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655 for train result */
2656 reg = FDI_RX_IMR(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~FDI_RX_SYMBOL_LOCK;
2659 temp &= ~FDI_RX_BIT_LOCK;
2660 I915_WRITE(reg, temp);
2661
2662 POSTING_READ(reg);
2663 udelay(150);
2664
01a415fd
DV		 2665 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666 I915_READ(FDI_RX_IIR(pipe)));
2667
357555c0
JB		 2668 /* enable CPU FDI TX and PCH FDI RX */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~(7 << 19);
2672 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2677 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2678 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
d74cf324
DV		 2680 I915_WRITE(FDI_RX_MISC(pipe),
2681 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
357555c0
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2688 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2689 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691 POSTING_READ(reg);
2692 udelay(150);
2693
291427f5
JB		 2694 if (HAS_PCH_CPT(dev))
2695 cpt_phase_pointer_enable(dev, pipe);
2696
0206e353 2697 for (i = 0; i < 4; i++) {
357555c0
JB		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
2705 udelay(500);
2706
2707 reg = FDI_RX_IIR(pipe);
2708 temp = I915_READ(reg);
2709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711 if (temp & FDI_RX_BIT_LOCK ||
2712 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2713 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2714 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2715 break;
2716 }
2717 }
2718 if (i == 4)
2719 DRM_ERROR("FDI train 1 fail!\n");
2720
2721 /* Train 2 */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2725 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2726 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2728 I915_WRITE(reg, temp);
2729
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2733 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2734 I915_WRITE(reg, temp);
2735
2736 POSTING_READ(reg);
2737 udelay(150);
2738
0206e353 2739 for (i = 0; i < 4; i++) {
357555c0
JB		 2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2745
2746 POSTING_READ(reg);
2747 udelay(500);
2748
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753 if (temp & FDI_RX_SYMBOL_LOCK) {
2754 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2755 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2756 break;
2757 }
2758 }
2759 if (i == 4)
2760 DRM_ERROR("FDI train 2 fail!\n");
2761
2762 DRM_DEBUG_KMS("FDI train done.\n");
2763}
2764
88cefb6c 2765static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2766{
88cefb6c 2767 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2768 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2769 int pipe = intel_crtc->pipe;
5eddb70b 2770 u32 reg, temp;
79e53945 2771
c64e311e 2772
c98e9dcf 2773 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2777 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2778 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2780
2781 POSTING_READ(reg);
c98e9dcf
JB		 2782 udelay(200);
2783
2784 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp | FDI_PCDCLK);
2787
2788 POSTING_READ(reg);
c98e9dcf
JB		 2789 udelay(200);
2790
bf507ef7
ED		 2791 /* On Haswell, the PLL configuration for ports and pipes is handled
2792 * separately, as part of DDI setup */
2793 if (!IS_HASWELL(dev)) {
2794 /* Enable CPU FDI TX PLL, always on for Ironlake */
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2798 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2799
bf507ef7
ED		 2800 POSTING_READ(reg);
2801 udelay(100);
2802 }
6be4a607 2803 }
0e23b99d
JB		 2804}
2805
88cefb6c
DV		 2806static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2807{
2808 struct drm_device *dev = intel_crtc->base.dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* Switch from PCDclk to Rawclk */
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2817
2818 /* Disable CPU FDI TX PLL */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823 POSTING_READ(reg);
2824 udelay(100);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2829
2830 /* Wait for the clocks to turn off. */
2831 POSTING_READ(reg);
2832 udelay(100);
2833}
2834
291427f5
JB		 2835static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2836{
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 u32 flags = I915_READ(SOUTH_CHICKEN1);
2839
2840 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2841 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2842 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2843 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2844 POSTING_READ(SOUTH_CHICKEN1);
2845}
0fc932b8
JB		 2846static void ironlake_fdi_disable(struct drm_crtc *crtc)
2847{
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp;
2853
2854 /* disable CPU FDI tx and PCH FDI rx */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2858 POSTING_READ(reg);
2859
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~(0x7 << 16);
2863 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2864 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2865
2866 POSTING_READ(reg);
2867 udelay(100);
2868
2869 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2870 if (HAS_PCH_IBX(dev)) {
2871 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2872 I915_WRITE(FDI_RX_CHICKEN(pipe),
2873 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2874 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2875 } else if (HAS_PCH_CPT(dev)) {
2876 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2877 }
0fc932b8
JB		 2878
2879 /* still set train pattern 1 */
2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 temp &= ~FDI_LINK_TRAIN_NONE;
2883 temp |= FDI_LINK_TRAIN_PATTERN_1;
2884 I915_WRITE(reg, temp);
2885
2886 reg = FDI_RX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 if (HAS_PCH_CPT(dev)) {
2889 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2890 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2891 } else {
2892 temp &= ~FDI_LINK_TRAIN_NONE;
2893 temp |= FDI_LINK_TRAIN_PATTERN_1;
2894 }
2895 /* BPC in FDI rx is consistent with that in PIPECONF */
2896 temp &= ~(0x07 << 16);
2897 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2898 I915_WRITE(reg, temp);
2899
2900 POSTING_READ(reg);
2901 udelay(100);
2902}
2903
5bb61643
CW		 2904static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2905{
2906 struct drm_device *dev = crtc->dev;
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 unsigned long flags;
2909 bool pending;
2910
2911 if (atomic_read(&dev_priv->mm.wedged))
2912 return false;
2913
2914 spin_lock_irqsave(&dev->event_lock, flags);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918 return pending;
2919}
2920
e6c3a2a6
CW		 2921static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922{
0f91128d 2923 struct drm_device *dev = crtc->dev;
5bb61643 2924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2925
2926 if (crtc->fb == NULL)
2927 return;
2928
5bb61643
CW		 2929 wait_event(dev_priv->pending_flip_queue,
2930 !intel_crtc_has_pending_flip(crtc));
2931
0f91128d
CW		 2932 mutex_lock(&dev->struct_mutex);
2933 intel_finish_fb(crtc->fb);
2934 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2935}
2936
fc316cbe 2937static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2938{
2939 struct drm_device *dev = crtc->dev;
228d3e36 2940 struct intel_encoder *intel_encoder;
040484af
JB		 2941
2942 /*
2943 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2944 * must be driven by its own crtc; no sharing is possible.
2945 */
228d3e36 2946 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2947 switch (intel_encoder->type) {
040484af 2948 case INTEL_OUTPUT_EDP:
228d3e36 2949 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2950 return false;
2951 continue;
2952 }
2953 }
2954
2955 return true;
2956}
2957
fc316cbe
PZ		 2958static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2959{
2960 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2961}
2962
e615efe4
ED		 2963/* Program iCLKIP clock to the desired frequency */
2964static void lpt_program_iclkip(struct drm_crtc *crtc)
2965{
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969 u32 temp;
2970
2971 /* It is necessary to ungate the pixclk gate prior to programming
2972 * the divisors, and gate it back when it is done.
2973 */
2974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2975
2976 /* Disable SSCCTL */
2977 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2978 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2979 SBI_SSCCTL_DISABLE);
2980
2981 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2982 if (crtc->mode.clock == 20000) {
2983 auxdiv = 1;
2984 divsel = 0x41;
2985 phaseinc = 0x20;
2986 } else {
2987 /* The iCLK virtual clock root frequency is in MHz,
2988 * but the crtc->mode.clock in in KHz. To get the divisors,
2989 * it is necessary to divide one by another, so we
2990 * convert the virtual clock precision to KHz here for higher
2991 * precision.
2992 */
2993 u32 iclk_virtual_root_freq = 172800 * 1000;
2994 u32 iclk_pi_range = 64;
2995 u32 desired_divisor, msb_divisor_value, pi_value;
2996
2997 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2998 msb_divisor_value = desired_divisor / iclk_pi_range;
2999 pi_value = desired_divisor % iclk_pi_range;
3000
3001 auxdiv = 0;
3002 divsel = msb_divisor_value - 2;
3003 phaseinc = pi_value;
3004 }
3005
3006 /* This should not happen with any sane values */
3007 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3008 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3009 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3010 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3011
3012 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3013 crtc->mode.clock,
3014 auxdiv,
3015 divsel,
3016 phasedir,
3017 phaseinc);
3018
3019 /* Program SSCDIVINTPHASE6 */
3020 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3021 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3022 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3023 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3024 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3025 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3026 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3027
3028 intel_sbi_write(dev_priv,
3029 SBI_SSCDIVINTPHASE6,
3030 temp);
3031
3032 /* Program SSCAUXDIV */
3033 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3034 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036 intel_sbi_write(dev_priv,
3037 SBI_SSCAUXDIV6,
3038 temp);
3039
3040
3041 /* Enable modulator and associated divider */
3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3043 temp &= ~SBI_SSCCTL_DISABLE;
3044 intel_sbi_write(dev_priv,
3045 SBI_SSCCTL6,
3046 temp);
3047
3048 /* Wait for initialization time */
3049 udelay(24);
3050
3051 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3052}
3053
f67a559d
JB		 3054/*
3055 * Enable PCH resources required for PCH ports:
3056 * - PCH PLLs
3057 * - FDI training & RX/TX
3058 * - update transcoder timings
3059 * - DP transcoding bits
3060 * - transcoder
3061 */
3062static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3063{
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
ee7b9f93 3068 u32 reg, temp;
2c07245f 3069
e7e164db
CW		 3070 assert_transcoder_disabled(dev_priv, pipe);
3071
cd986abb
DV		 3072 /* Write the TU size bits before fdi link training, so that error
3073 * detection works. */
3074 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3075 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3076
c98e9dcf 3077 /* For PCH output, training FDI link */
674cf967 3078 dev_priv->display.fdi_link_train(crtc);
2c07245f 3079
572deb37
DV		 3080 /* XXX: pch pll's can be enabled any time before we enable the PCH
3081 * transcoder, and we actually should do this to not upset any PCH
3082 * transcoder that already use the clock when we share it.
3083 *
3084 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3085 * unconditionally resets the pll - we need that to have the right LVDS
3086 * enable sequence. */
6f13b7b5
CW		 3087 intel_enable_pch_pll(intel_crtc);
3088
e615efe4
ED		 3089 if (HAS_PCH_LPT(dev)) {
3090 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3091 lpt_program_iclkip(crtc);
3092 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3093 u32 sel;
4b645f14 3094
c98e9dcf 3095 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3096 switch (pipe) {
3097 default:
3098 case 0:
3099 temp |= TRANSA_DPLL_ENABLE;
3100 sel = TRANSA_DPLLB_SEL;
3101 break;
3102 case 1:
3103 temp |= TRANSB_DPLL_ENABLE;
3104 sel = TRANSB_DPLLB_SEL;
3105 break;
3106 case 2:
3107 temp |= TRANSC_DPLL_ENABLE;
3108 sel = TRANSC_DPLLB_SEL;
3109 break;
d64311ab 3110 }
ee7b9f93
JB		 3111 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3112 temp |= sel;
3113 else
3114 temp &= ~sel;
c98e9dcf 3115 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3116 }
5eddb70b 3117
d9b6cb56
JB		 3118 /* set transcoder timing, panel must allow it */
3119 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3120 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3121 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3122 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3123
5eddb70b
CW		 3124 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3125 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3126 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3127 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3128
f57e1e3a
ED		 3129 if (!IS_HASWELL(dev))
3130 intel_fdi_normal_train(crtc);
5e84e1a4 3131
c98e9dcf
JB		 3132 /* For PCH DP, enable TRANS_DP_CTL */
3133 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3134 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3135 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3136 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3137 reg = TRANS_DP_CTL(pipe);
3138 temp = I915_READ(reg);
3139 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3140 TRANS_DP_SYNC_MASK |
3141 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3142 temp |= (TRANS_DP_OUTPUT_ENABLE |
3143 TRANS_DP_ENH_FRAMING);
9325c9f0 3144 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3145
3146 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3147 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3148 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3149 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3150
3151 switch (intel_trans_dp_port_sel(crtc)) {
3152 case PCH_DP_B:
5eddb70b 3153 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3154 break;
3155 case PCH_DP_C:
5eddb70b 3156 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3157 break;
3158 case PCH_DP_D:
5eddb70b 3159 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3160 break;
3161 default:
e95d41e1 3162 BUG();
32f9d658 3163 }
2c07245f 3164
5eddb70b 3165 I915_WRITE(reg, temp);
6be4a607 3166 }
b52eb4dc 3167
040484af 3168 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3169}
3170
1507e5bd
PZ		 3171static void lpt_pch_enable(struct drm_crtc *crtc)
3172{
3173 struct drm_device *dev = crtc->dev;
3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176 int pipe = intel_crtc->pipe;
3177 u32 reg, temp;
3178
3179 assert_transcoder_disabled(dev_priv, pipe);
3180
3181 /* Write the TU size bits before fdi link training, so that error
3182 * detection works. */
3183 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3184 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3185
3186 /* For PCH output, training FDI link */
3187 dev_priv->display.fdi_link_train(crtc);
3188
3189 /* XXX: pch pll's can be enabled any time before we enable the PCH
3190 * transcoder, and we actually should do this to not upset any PCH
3191 * transcoder that already use the clock when we share it.
3192 *
3193 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3194 * unconditionally resets the pll - we need that to have the right LVDS
3195 * enable sequence. */
3196 intel_enable_pch_pll(intel_crtc);
3197
3198 if (HAS_PCH_LPT(dev)) {
3199 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3200 lpt_program_iclkip(crtc);
3201 } else if (HAS_PCH_CPT(dev)) {
3202 u32 sel;
3203
3204 temp = I915_READ(PCH_DPLL_SEL);
3205 switch (pipe) {
3206 default:
3207 case 0:
3208 temp |= TRANSA_DPLL_ENABLE;
3209 sel = TRANSA_DPLLB_SEL;
3210 break;
3211 case 1:
3212 temp |= TRANSB_DPLL_ENABLE;
3213 sel = TRANSB_DPLLB_SEL;
3214 break;
3215 case 2:
3216 temp |= TRANSC_DPLL_ENABLE;
3217 sel = TRANSC_DPLLB_SEL;
3218 break;
3219 }
3220 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3221 temp |= sel;
3222 else
3223 temp &= ~sel;
3224 I915_WRITE(PCH_DPLL_SEL, temp);
3225 }
3226
3227 /* set transcoder timing, panel must allow it */
3228 assert_panel_unlocked(dev_priv, pipe);
3229 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3230 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3231 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3232
3233 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3234 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3235 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3236 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3237
3238 if (!IS_HASWELL(dev))
3239 intel_fdi_normal_train(crtc);
3240
3241 /* For PCH DP, enable TRANS_DP_CTL */
3242 if (HAS_PCH_CPT(dev) &&
3243 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3244 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3245 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3246 reg = TRANS_DP_CTL(pipe);
3247 temp = I915_READ(reg);
3248 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3249 TRANS_DP_SYNC_MASK |
3250 TRANS_DP_BPC_MASK);
3251 temp |= (TRANS_DP_OUTPUT_ENABLE |
3252 TRANS_DP_ENH_FRAMING);
3253 temp |= bpc << 9; /* same format but at 11:9 */
3254
3255 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3256 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3257 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3258 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3259
3260 switch (intel_trans_dp_port_sel(crtc)) {
3261 case PCH_DP_B:
3262 temp |= TRANS_DP_PORT_SEL_B;
3263 break;
3264 case PCH_DP_C:
3265 temp |= TRANS_DP_PORT_SEL_C;
3266 break;
3267 case PCH_DP_D:
3268 temp |= TRANS_DP_PORT_SEL_D;
3269 break;
3270 default:
3271 BUG();
3272 }
3273
3274 I915_WRITE(reg, temp);
3275 }
3276
3277 intel_enable_transcoder(dev_priv, pipe);
3278}
3279
ee7b9f93
JB		 3280static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3281{
3282 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3283
3284 if (pll == NULL)
3285 return;
3286
3287 if (pll->refcount == 0) {
3288 WARN(1, "bad PCH PLL refcount\n");
3289 return;
3290 }
3291
3292 --pll->refcount;
3293 intel_crtc->pch_pll = NULL;
3294}
3295
3296static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3297{
3298 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3299 struct intel_pch_pll *pll;
3300 int i;
3301
3302 pll = intel_crtc->pch_pll;
3303 if (pll) {
3304 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3305 intel_crtc->base.base.id, pll->pll_reg);
3306 goto prepare;
3307 }
3308
98b6bd99
DV		 3309 if (HAS_PCH_IBX(dev_priv->dev)) {
3310 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3311 i = intel_crtc->pipe;
3312 pll = &dev_priv->pch_plls[i];
3313
3314 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3315 intel_crtc->base.base.id, pll->pll_reg);
3316
3317 goto found;
3318 }
3319
ee7b9f93
JB		 3320 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3321 pll = &dev_priv->pch_plls[i];
3322
3323 /* Only want to check enabled timings first */
3324 if (pll->refcount == 0)
3325 continue;
3326
3327 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3328 fp == I915_READ(pll->fp0_reg)) {
3329 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3330 intel_crtc->base.base.id,
3331 pll->pll_reg, pll->refcount, pll->active);
3332
3333 goto found;
3334 }
3335 }
3336
3337 /* Ok no matching timings, maybe there's a free one? */
3338 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3339 pll = &dev_priv->pch_plls[i];
3340 if (pll->refcount == 0) {
3341 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3342 intel_crtc->base.base.id, pll->pll_reg);
3343 goto found;
3344 }
3345 }
3346
3347 return NULL;
3348
3349found:
3350 intel_crtc->pch_pll = pll;
3351 pll->refcount++;
3352 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3353prepare: /* separate function? */
3354 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3355
e04c7350
CW		 3356 /* Wait for the clocks to stabilize before rewriting the regs */
3357 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3358 POSTING_READ(pll->pll_reg);
3359 udelay(150);
e04c7350
CW		 3360
3361 I915_WRITE(pll->fp0_reg, fp);
3362 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3363 pll->on = false;
3364 return pll;
3365}
3366
d4270e57
JB		 3367void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3368{
3369 struct drm_i915_private *dev_priv = dev->dev_private;
3370 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3371 u32 temp;
3372
3373 temp = I915_READ(dslreg);
3374 udelay(500);
3375 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3376 /* Without this, mode sets may fail silently on FDI */
3377 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3378 udelay(250);
3379 I915_WRITE(tc2reg, 0);
3380 if (wait_for(I915_READ(dslreg) != temp, 5))
3381 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3382 }
3383}
3384
f67a559d
JB		 3385static void ironlake_crtc_enable(struct drm_crtc *crtc)
3386{
3387 struct drm_device *dev = crtc->dev;
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3390 struct intel_encoder *encoder;
f67a559d
JB		 3391 int pipe = intel_crtc->pipe;
3392 int plane = intel_crtc->plane;
3393 u32 temp;
3394 bool is_pch_port;
3395
08a48469
DV		 3396 WARN_ON(!crtc->enabled);
3397
f67a559d
JB		 3398 if (intel_crtc->active)
3399 return;
3400
3401 intel_crtc->active = true;
3402 intel_update_watermarks(dev);
3403
3404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3405 temp = I915_READ(PCH_LVDS);
3406 if ((temp & LVDS_PORT_EN) == 0)
3407 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3408 }
3409
fc316cbe 3410 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3411
46b6f814 3412 if (is_pch_port) {
fff367c7
DV		 3413 /* Note: FDI PLL enabling _must_ be done before we enable the
3414 * cpu pipes, hence this is separate from all the other fdi/pch
3415 * enabling. */
88cefb6c 3416 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3417 } else {
3418 assert_fdi_tx_disabled(dev_priv, pipe);
3419 assert_fdi_rx_disabled(dev_priv, pipe);
3420 }
f67a559d 3421
bf49ec8c
DV		 3422 for_each_encoder_on_crtc(dev, crtc, encoder)
3423 if (encoder->pre_enable)
3424 encoder->pre_enable(encoder);
3425
f67a559d
JB		 3426 /* Enable panel fitting for LVDS */
3427 if (dev_priv->pch_pf_size &&
3428 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3429 /* Force use of hard-coded filter coefficients
3430 * as some pre-programmed values are broken,
3431 * e.g. x201.
3432 */
9db4a9c7
JB		 3433 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3434 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3435 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3436 }
3437
9c54c0dd
JB		 3438 /*
3439 * On ILK+ LUT must be loaded before the pipe is running but with
3440 * clocks enabled
3441 */
3442 intel_crtc_load_lut(crtc);
3443
f67a559d
JB		 3444 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3445 intel_enable_plane(dev_priv, plane, pipe);
3446
3447 if (is_pch_port)
3448 ironlake_pch_enable(crtc);
c98e9dcf 3449
d1ebd816 3450 mutex_lock(&dev->struct_mutex);
bed4a673 3451 intel_update_fbc(dev);
d1ebd816
BW		 3452 mutex_unlock(&dev->struct_mutex);
3453
6b383a7f 3454 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3455
fa5c73b1
DV		 3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 encoder->enable(encoder);
61b77ddd
DV		 3458
3459 if (HAS_PCH_CPT(dev))
3460 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3461
3462 /*
3463 * There seems to be a race in PCH platform hw (at least on some
3464 * outputs) where an enabled pipe still completes any pageflip right
3465 * away (as if the pipe is off) instead of waiting for vblank. As soon
3466 * as the first vblank happend, everything works as expected. Hence just
3467 * wait for one vblank before returning to avoid strange things
3468 * happening.
3469 */
3470 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3471}
3472
4f771f10
PZ		 3473static void haswell_crtc_enable(struct drm_crtc *crtc)
3474{
3475 struct drm_device *dev = crtc->dev;
3476 struct drm_i915_private *dev_priv = dev->dev_private;
3477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478 struct intel_encoder *encoder;
3479 int pipe = intel_crtc->pipe;
3480 int plane = intel_crtc->plane;
4f771f10
PZ		 3481 bool is_pch_port;
3482
3483 WARN_ON(!crtc->enabled);
3484
3485 if (intel_crtc->active)
3486 return;
3487
3488 intel_crtc->active = true;
3489 intel_update_watermarks(dev);
3490
fc316cbe 3491 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3492
83616634 3493 if (is_pch_port)
4f771f10 3494 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3495
3496 for_each_encoder_on_crtc(dev, crtc, encoder)
3497 if (encoder->pre_enable)
3498 encoder->pre_enable(encoder);
3499
1f544388 3500 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3501
1f544388
PZ		 3502 /* Enable panel fitting for eDP */
3503 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3504 /* Force use of hard-coded filter coefficients
3505 * as some pre-programmed values are broken,
3506 * e.g. x201.
3507 */
3508 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3509 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3510 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3511 }
3512
3513 /*
3514 * On ILK+ LUT must be loaded before the pipe is running but with
3515 * clocks enabled
3516 */
3517 intel_crtc_load_lut(crtc);
3518
1f544388
PZ		 3519 intel_ddi_set_pipe_settings(crtc);
3520 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3521
3522 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3523 intel_enable_plane(dev_priv, plane, pipe);
3524
3525 if (is_pch_port)
1507e5bd 3526 lpt_pch_enable(crtc);
4f771f10
PZ		 3527
3528 mutex_lock(&dev->struct_mutex);
3529 intel_update_fbc(dev);
3530 mutex_unlock(&dev->struct_mutex);
3531
3532 intel_crtc_update_cursor(crtc, true);
3533
3534 for_each_encoder_on_crtc(dev, crtc, encoder)
3535 encoder->enable(encoder);
3536
4f771f10
PZ		 3537 /*
3538 * There seems to be a race in PCH platform hw (at least on some
3539 * outputs) where an enabled pipe still completes any pageflip right
3540 * away (as if the pipe is off) instead of waiting for vblank. As soon
3541 * as the first vblank happend, everything works as expected. Hence just
3542 * wait for one vblank before returning to avoid strange things
3543 * happening.
3544 */
3545 intel_wait_for_vblank(dev, intel_crtc->pipe);
3546}
3547
6be4a607
JB		 3548static void ironlake_crtc_disable(struct drm_crtc *crtc)
3549{
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3553 struct intel_encoder *encoder;
6be4a607
JB		 3554 int pipe = intel_crtc->pipe;
3555 int plane = intel_crtc->plane;
5eddb70b 3556 u32 reg, temp;
b52eb4dc 3557
ef9c3aee 3558
f7abfe8b
CW		 3559 if (!intel_crtc->active)
3560 return;
3561
ea9d758d
DV		 3562 for_each_encoder_on_crtc(dev, crtc, encoder)
3563 encoder->disable(encoder);
3564
e6c3a2a6 3565 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3566 drm_vblank_off(dev, pipe);
6b383a7f 3567 intel_crtc_update_cursor(crtc, false);
5eddb70b 3568
b24e7179 3569 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3570
973d04f9
CW		 3571 if (dev_priv->cfb_plane == plane)
3572 intel_disable_fbc(dev);
2c07245f 3573
b24e7179 3574 intel_disable_pipe(dev_priv, pipe);
32f9d658 3575
6be4a607 3576 /* Disable PF */
9db4a9c7
JB		 3577 I915_WRITE(PF_CTL(pipe), 0);
3578 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3579
bf49ec8c
DV		 3580 for_each_encoder_on_crtc(dev, crtc, encoder)
3581 if (encoder->post_disable)
3582 encoder->post_disable(encoder);
3583
0fc932b8 3584 ironlake_fdi_disable(crtc);
2c07245f 3585
040484af 3586 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3587
6be4a607
JB		 3588 if (HAS_PCH_CPT(dev)) {
3589 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3590 reg = TRANS_DP_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3593 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3594 I915_WRITE(reg, temp);
6be4a607
JB		 3595
3596 /* disable DPLL_SEL */
3597 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3598 switch (pipe) {
3599 case 0:
d64311ab 3600 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3601 break;
3602 case 1:
6be4a607 3603 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3604 break;
3605 case 2:
4b645f14 3606 /* C shares PLL A or B */
d64311ab 3607 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3608 break;
3609 default:
3610 BUG(); /* wtf */
3611 }
6be4a607 3612 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3613 }
e3421a18 3614
6be4a607 3615 /* disable PCH DPLL */
ee7b9f93 3616 intel_disable_pch_pll(intel_crtc);
8db9d77b 3617
88cefb6c 3618 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3619
f7abfe8b 3620 intel_crtc->active = false;
6b383a7f 3621 intel_update_watermarks(dev);
d1ebd816
BW		 3622
3623 mutex_lock(&dev->struct_mutex);
6b383a7f 3624 intel_update_fbc(dev);
d1ebd816 3625 mutex_unlock(&dev->struct_mutex);
6be4a607 3626}
1b3c7a47 3627
4f771f10
PZ		 3628static void haswell_crtc_disable(struct drm_crtc *crtc)
3629{
3630 struct drm_device *dev = crtc->dev;
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3633 struct intel_encoder *encoder;
3634 int pipe = intel_crtc->pipe;
3635 int plane = intel_crtc->plane;
ad80a810 3636 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3637 bool is_pch_port;
4f771f10
PZ		 3638
3639 if (!intel_crtc->active)
3640 return;
3641
83616634
PZ		 3642 is_pch_port = haswell_crtc_driving_pch(crtc);
3643
4f771f10
PZ		 3644 for_each_encoder_on_crtc(dev, crtc, encoder)
3645 encoder->disable(encoder);
3646
3647 intel_crtc_wait_for_pending_flips(crtc);
3648 drm_vblank_off(dev, pipe);
3649 intel_crtc_update_cursor(crtc, false);
3650
3651 intel_disable_plane(dev_priv, plane, pipe);
3652
3653 if (dev_priv->cfb_plane == plane)
3654 intel_disable_fbc(dev);
3655
3656 intel_disable_pipe(dev_priv, pipe);
3657
ad80a810 3658 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3659
3660 /* Disable PF */
3661 I915_WRITE(PF_CTL(pipe), 0);
3662 I915_WRITE(PF_WIN_SZ(pipe), 0);
3663
1f544388 3664 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3665
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 if (encoder->post_disable)
3668 encoder->post_disable(encoder);
3669
83616634
PZ		 3670 if (is_pch_port) {
3671 ironlake_fdi_disable(crtc);
3672 intel_disable_transcoder(dev_priv, pipe);
3673 intel_disable_pch_pll(intel_crtc);
3674 ironlake_fdi_pll_disable(intel_crtc);
3675 }
4f771f10
PZ		 3676
3677 intel_crtc->active = false;
3678 intel_update_watermarks(dev);
3679
3680 mutex_lock(&dev->struct_mutex);
3681 intel_update_fbc(dev);
3682 mutex_unlock(&dev->struct_mutex);
3683}
3684
ee7b9f93
JB		 3685static void ironlake_crtc_off(struct drm_crtc *crtc)
3686{
3687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3688 intel_put_pch_pll(intel_crtc);
3689}
3690
6441ab5f
PZ		 3691static void haswell_crtc_off(struct drm_crtc *crtc)
3692{
a5c961d1
PZ		 3693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3694
3695 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3696 * start using it. */
3697 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3698
6441ab5f
PZ		 3699 intel_ddi_put_crtc_pll(crtc);
3700}
3701
02e792fb
DV		 3702static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3703{
02e792fb 3704 if (!enable && intel_crtc->overlay) {
23f09ce3 3705 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3706 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3707
23f09ce3 3708 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3709 dev_priv->mm.interruptible = false;
3710 (void) intel_overlay_switch_off(intel_crtc->overlay);
3711 dev_priv->mm.interruptible = true;
23f09ce3 3712 mutex_unlock(&dev->struct_mutex);
02e792fb 3713 }
02e792fb 3714
5dcdbcb0
CW		 3715 /* Let userspace switch the overlay on again. In most cases userspace
3716 * has to recompute where to put it anyway.
3717 */
02e792fb
DV		 3718}
3719
0b8765c6 3720static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3721{
3722 struct drm_device *dev = crtc->dev;
79e53945
JB		 3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3725 struct intel_encoder *encoder;
79e53945 3726 int pipe = intel_crtc->pipe;
80824003 3727 int plane = intel_crtc->plane;
79e53945 3728
08a48469
DV		 3729 WARN_ON(!crtc->enabled);
3730
f7abfe8b
CW		 3731 if (intel_crtc->active)
3732 return;
3733
3734 intel_crtc->active = true;
6b383a7f
CW		 3735 intel_update_watermarks(dev);
3736
63d7bbe9 3737 intel_enable_pll(dev_priv, pipe);
040484af 3738 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3739 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3740
0b8765c6 3741 intel_crtc_load_lut(crtc);
bed4a673 3742 intel_update_fbc(dev);
79e53945 3743
0b8765c6
JB		 3744 /* Give the overlay scaler a chance to enable if it's on this pipe */
3745 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3746 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3747
fa5c73b1
DV		 3748 for_each_encoder_on_crtc(dev, crtc, encoder)
3749 encoder->enable(encoder);
0b8765c6 3750}
79e53945 3751
0b8765c6
JB		 3752static void i9xx_crtc_disable(struct drm_crtc *crtc)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3757 struct intel_encoder *encoder;
0b8765c6
JB		 3758 int pipe = intel_crtc->pipe;
3759 int plane = intel_crtc->plane;
b690e96c 3760
ef9c3aee 3761
f7abfe8b
CW		 3762 if (!intel_crtc->active)
3763 return;
3764
ea9d758d
DV		 3765 for_each_encoder_on_crtc(dev, crtc, encoder)
3766 encoder->disable(encoder);
3767
0b8765c6 3768 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3769 intel_crtc_wait_for_pending_flips(crtc);
3770 drm_vblank_off(dev, pipe);
0b8765c6 3771 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3772 intel_crtc_update_cursor(crtc, false);
0b8765c6 3773
973d04f9
CW		 3774 if (dev_priv->cfb_plane == plane)
3775 intel_disable_fbc(dev);
79e53945 3776
b24e7179 3777 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3778 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3779 intel_disable_pll(dev_priv, pipe);
0b8765c6 3780
f7abfe8b 3781 intel_crtc->active = false;
6b383a7f
CW		 3782 intel_update_fbc(dev);
3783 intel_update_watermarks(dev);
0b8765c6
JB		 3784}
3785
ee7b9f93
JB		 3786static void i9xx_crtc_off(struct drm_crtc *crtc)
3787{
3788}
3789
976f8a20
DV		 3790static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3791 bool enabled)
2c07245f
ZW		 3792{
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_master_private *master_priv;
3795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3796 int pipe = intel_crtc->pipe;
79e53945
JB		 3797
3798 if (!dev->primary->master)
3799 return;
3800
3801 master_priv = dev->primary->master->driver_priv;
3802 if (!master_priv->sarea_priv)
3803 return;
3804
79e53945
JB		 3805 switch (pipe) {
3806 case 0:
3807 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3808 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3809 break;
3810 case 1:
3811 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3812 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3813 break;
3814 default:
9db4a9c7 3815 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3816 break;
3817 }
79e53945
JB		 3818}
3819
976f8a20
DV		 3820/**
3821 * Sets the power management mode of the pipe and plane.
3822 */
3823void intel_crtc_update_dpms(struct drm_crtc *crtc)
3824{
3825 struct drm_device *dev = crtc->dev;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 struct intel_encoder *intel_encoder;
3828 bool enable = false;
3829
3830 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3831 enable |= intel_encoder->connectors_active;
3832
3833 if (enable)
3834 dev_priv->display.crtc_enable(crtc);
3835 else
3836 dev_priv->display.crtc_disable(crtc);
3837
3838 intel_crtc_update_sarea(crtc, enable);
3839}
3840
3841static void intel_crtc_noop(struct drm_crtc *crtc)
3842{
3843}
3844
cdd59983
CW		 3845static void intel_crtc_disable(struct drm_crtc *crtc)
3846{
cdd59983 3847 struct drm_device *dev = crtc->dev;
976f8a20 3848 struct drm_connector *connector;
ee7b9f93 3849 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3850
976f8a20
DV		 3851 /* crtc should still be enabled when we disable it. */
3852 WARN_ON(!crtc->enabled);
3853
3854 dev_priv->display.crtc_disable(crtc);
3855 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3856 dev_priv->display.off(crtc);
3857
931872fc
CW		 3858 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3860
3861 if (crtc->fb) {
3862 mutex_lock(&dev->struct_mutex);
1690e1eb 3863 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3864 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3865 crtc->fb = NULL;
3866 }
3867
3868 /* Update computed state. */
3869 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870 if (!connector->encoder || !connector->encoder->crtc)
3871 continue;
3872
3873 if (connector->encoder->crtc != crtc)
3874 continue;
3875
3876 connector->dpms = DRM_MODE_DPMS_OFF;
3877 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3878 }
3879}
3880
a261b246 3881void intel_modeset_disable(struct drm_device *dev)
79e53945 3882{
a261b246
DV		 3883 struct drm_crtc *crtc;
3884
3885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3886 if (crtc->enabled)
3887 intel_crtc_disable(crtc);
3888 }
79e53945
JB		 3889}
3890
1f703855 3891void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3892{
7e7d76c3
JB		 3893}
3894
ea5b213a 3895void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3896{
4ef69c7a 3897 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3898
ea5b213a
CW		 3899 drm_encoder_cleanup(encoder);
3900 kfree(intel_encoder);
7e7d76c3
JB		 3901}
3902
5ab432ef
DV		 3903/* Simple dpms helper for encodres with just one connector, no cloning and only
3904 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3905 * state of the entire output pipe. */
3906void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3907{
5ab432ef
DV		 3908 if (mode == DRM_MODE_DPMS_ON) {
3909 encoder->connectors_active = true;
3910
b2cabb0e 3911 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3912 } else {
3913 encoder->connectors_active = false;
3914
b2cabb0e 3915 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3916 }
79e53945
JB		 3917}
3918
0a91ca29
DV		 3919/* Cross check the actual hw state with our own modeset state tracking (and it's
3920 * internal consistency). */
b980514c 3921static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3922{
0a91ca29
DV		 3923 if (connector->get_hw_state(connector)) {
3924 struct intel_encoder *encoder = connector->encoder;
3925 struct drm_crtc *crtc;
3926 bool encoder_enabled;
3927 enum pipe pipe;
3928
3929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3930 connector->base.base.id,
3931 drm_get_connector_name(&connector->base));
3932
3933 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3934 "wrong connector dpms state\n");
3935 WARN(connector->base.encoder != &encoder->base,
3936 "active connector not linked to encoder\n");
3937 WARN(!encoder->connectors_active,
3938 "encoder->connectors_active not set\n");
3939
3940 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3941 WARN(!encoder_enabled, "encoder not enabled\n");
3942 if (WARN_ON(!encoder->base.crtc))
3943 return;
3944
3945 crtc = encoder->base.crtc;
3946
3947 WARN(!crtc->enabled, "crtc not enabled\n");
3948 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3949 WARN(pipe != to_intel_crtc(crtc)->pipe,
3950 "encoder active on the wrong pipe\n");
3951 }
79e53945
JB		 3952}
3953
5ab432ef
DV		 3954/* Even simpler default implementation, if there's really no special case to
3955 * consider. */
3956void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3957{
5ab432ef 3958 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3959
5ab432ef
DV		 3960 /* All the simple cases only support two dpms states. */
3961 if (mode != DRM_MODE_DPMS_ON)
3962 mode = DRM_MODE_DPMS_OFF;
d4270e57 3963
5ab432ef
DV		 3964 if (mode == connector->dpms)
3965 return;
3966
3967 connector->dpms = mode;
3968
3969 /* Only need to change hw state when actually enabled */
3970 if (encoder->base.crtc)
3971 intel_encoder_dpms(encoder, mode);
3972 else
8af6cf88 3973 WARN_ON(encoder->connectors_active != false);
0a91ca29 3974
b980514c 3975 intel_modeset_check_state(connector->dev);
79e53945
JB		 3976}
3977
f0947c37
DV		 3978/* Simple connector->get_hw_state implementation for encoders that support only
3979 * one connector and no cloning and hence the encoder state determines the state
3980 * of the connector. */
3981bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3982{
24929352 3983 enum pipe pipe = 0;
f0947c37 3984 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3985
f0947c37 3986 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3987}
3988
79e53945 3989static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3990 const struct drm_display_mode *mode,
79e53945
JB		 3991 struct drm_display_mode *adjusted_mode)
3992{
2c07245f 3993 struct drm_device *dev = crtc->dev;
89749350 3994
bad720ff 3995 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3996 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3997 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3998 return false;
2c07245f 3999 }
89749350 4000
f9bef081
DV		 4001 /* All interlaced capable intel hw wants timings in frames. Note though
4002 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4003 * timings, so we need to be careful not to clobber these.*/
4004 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
4005 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4006
44f46b42
CW		 4007 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4008 * with a hsync front porch of 0.
4009 */
4010 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4011 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4012 return false;
4013
79e53945
JB		 4014 return true;
4015}
4016
25eb05fc
JB		 4017static int valleyview_get_display_clock_speed(struct drm_device *dev)
4018{
4019 return 400000; /* FIXME */
4020}
4021
e70236a8
JB		 4022static int i945_get_display_clock_speed(struct drm_device *dev)
4023{
4024 return 400000;
4025}
79e53945 4026
e70236a8 4027static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4028{
e70236a8
JB		 4029 return 333000;
4030}
79e53945 4031
e70236a8
JB		 4032static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4033{
4034 return 200000;
4035}
79e53945 4036
e70236a8
JB		 4037static int i915gm_get_display_clock_speed(struct drm_device *dev)
4038{
4039 u16 gcfgc = 0;
79e53945 4040
e70236a8
JB		 4041 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4042
4043 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4044 return 133000;
4045 else {
4046 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4047 case GC_DISPLAY_CLOCK_333_MHZ:
4048 return 333000;
4049 default:
4050 case GC_DISPLAY_CLOCK_190_200_MHZ:
4051 return 190000;
79e53945 4052 }
e70236a8
JB		 4053 }
4054}
4055
4056static int i865_get_display_clock_speed(struct drm_device *dev)
4057{
4058 return 266000;
4059}
4060
4061static int i855_get_display_clock_speed(struct drm_device *dev)
4062{
4063 u16 hpllcc = 0;
4064 /* Assume that the hardware is in the high speed state. This
4065 * should be the default.
4066 */
4067 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4068 case GC_CLOCK_133_200:
4069 case GC_CLOCK_100_200:
4070 return 200000;
4071 case GC_CLOCK_166_250:
4072 return 250000;
4073 case GC_CLOCK_100_133:
79e53945 4074 return 133000;
e70236a8 4075 }
79e53945 4076
e70236a8
JB		 4077 /* Shouldn't happen */
4078 return 0;
4079}
79e53945 4080
e70236a8
JB		 4081static int i830_get_display_clock_speed(struct drm_device *dev)
4082{
4083 return 133000;
79e53945
JB		 4084}
4085
2c07245f
ZW		 4086struct fdi_m_n {
4087 u32 tu;
4088 u32 gmch_m;
4089 u32 gmch_n;
4090 u32 link_m;
4091 u32 link_n;
4092};
4093
4094static void
4095fdi_reduce_ratio(u32 *num, u32 *den)
4096{
4097 while (*num > 0xffffff || *den > 0xffffff) {
4098 *num >>= 1;
4099 *den >>= 1;
4100 }
4101}
4102
2c07245f 4103static void
f2b115e6
AJ		 4104ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4105 int link_clock, struct fdi_m_n *m_n)
2c07245f 4106{
2c07245f
ZW		 4107 m_n->tu = 64; /* default size */
4108
22ed1113
CW		 4109 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4110 m_n->gmch_m = bits_per_pixel * pixel_clock;
4111 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4112 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4113
22ed1113
CW		 4114 m_n->link_m = pixel_clock;
4115 m_n->link_n = link_clock;
2c07245f
ZW		 4116 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4117}
4118
a7615030
CW		 4119static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4120{
72bbe58c
KP		 4121 if (i915_panel_use_ssc >= 0)
4122 return i915_panel_use_ssc != 0;
4123 return dev_priv->lvds_use_ssc
435793df 4124 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4125}
4126
5a354204
JB		 4127/**
4128 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4129 * @crtc: CRTC structure
3b5c78a3 4130 * @mode: requested mode
5a354204
JB		 4131 *
4132 * A pipe may be connected to one or more outputs. Based on the depth of the
4133 * attached framebuffer, choose a good color depth to use on the pipe.
4134 *
4135 * If possible, match the pipe depth to the fb depth. In some cases, this
4136 * isn't ideal, because the connected output supports a lesser or restricted
4137 * set of depths. Resolve that here:
4138 * LVDS typically supports only 6bpc, so clamp down in that case
4139 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4140 * Displays may support a restricted set as well, check EDID and clamp as
4141 * appropriate.
3b5c78a3 4142 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4143 *
4144 * RETURNS:
4145 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4146 * true if they don't match).
4147 */
4148static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4149 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4150 unsigned int *pipe_bpp,
4151 struct drm_display_mode *mode)
5a354204
JB		 4152{
4153 struct drm_device *dev = crtc->dev;
4154 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4155 struct drm_connector *connector;
6c2b7c12 4156 struct intel_encoder *intel_encoder;
5a354204
JB		 4157 unsigned int display_bpc = UINT_MAX, bpc;
4158
4159 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4160 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4161
4162 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4163 unsigned int lvds_bpc;
4164
4165 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4166 LVDS_A3_POWER_UP)
4167 lvds_bpc = 8;
4168 else
4169 lvds_bpc = 6;
4170
4171 if (lvds_bpc < display_bpc) {
82820490 4172 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4173 display_bpc = lvds_bpc;
4174 }
4175 continue;
4176 }
4177
5a354204
JB		 4178 /* Not one of the known troublemakers, check the EDID */
4179 list_for_each_entry(connector, &dev->mode_config.connector_list,
4180 head) {
6c2b7c12 4181 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4182 continue;
4183
62ac41a6
JB		 4184 /* Don't use an invalid EDID bpc value */
4185 if (connector->display_info.bpc &&
4186 connector->display_info.bpc < display_bpc) {
82820490 4187 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4188 display_bpc = connector->display_info.bpc;
4189 }
4190 }
4191
4192 /*
4193 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4194 * through, clamp it down. (Note: >12bpc will be caught below.)
4195 */
4196 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4197 if (display_bpc > 8 && display_bpc < 12) {
82820490 4198 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4199 display_bpc = 12;
4200 } else {
82820490 4201 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4202 display_bpc = 8;
4203 }
4204 }
4205 }
4206
3b5c78a3
AJ		 4207 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4208 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4209 display_bpc = 6;
4210 }
4211
5a354204
JB		 4212 /*
4213 * We could just drive the pipe at the highest bpc all the time and
4214 * enable dithering as needed, but that costs bandwidth. So choose
4215 * the minimum value that expresses the full color range of the fb but
4216 * also stays within the max display bpc discovered above.
4217 */
4218
94352cf9 4219 switch (fb->depth) {
5a354204
JB		 4220 case 8:
4221 bpc = 8; /* since we go through a colormap */
4222 break;
4223 case 15:
4224 case 16:
4225 bpc = 6; /* min is 18bpp */
4226 break;
4227 case 24:
578393cd 4228 bpc = 8;
5a354204
JB		 4229 break;
4230 case 30:
578393cd 4231 bpc = 10;
5a354204
JB		 4232 break;
4233 case 48:
578393cd 4234 bpc = 12;
5a354204
JB		 4235 break;
4236 default:
4237 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4238 bpc = min((unsigned int)8, display_bpc);
4239 break;
4240 }
4241
578393cd
KP		 4242 display_bpc = min(display_bpc, bpc);
4243
82820490
AJ		 4244 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4245 bpc, display_bpc);
5a354204 4246
578393cd 4247 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4248
4249 return display_bpc != bpc;
4250}
4251
a0c4da24
JB		 4252static int vlv_get_refclk(struct drm_crtc *crtc)
4253{
4254 struct drm_device *dev = crtc->dev;
4255 struct drm_i915_private *dev_priv = dev->dev_private;
4256 int refclk = 27000; /* for DP & HDMI */
4257
4258 return 100000; /* only one validated so far */
4259
4260 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4261 refclk = 96000;
4262 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4263 if (intel_panel_use_ssc(dev_priv))
4264 refclk = 100000;
4265 else
4266 refclk = 96000;
4267 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4268 refclk = 100000;
4269 }
4270
4271 return refclk;
4272}
4273
c65d77d8
JB		 4274static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4275{
4276 struct drm_device *dev = crtc->dev;
4277 struct drm_i915_private *dev_priv = dev->dev_private;
4278 int refclk;
4279
a0c4da24
JB		 4280 if (IS_VALLEYVIEW(dev)) {
4281 refclk = vlv_get_refclk(crtc);
4282 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4283 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4284 refclk = dev_priv->lvds_ssc_freq * 1000;
4285 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4286 refclk / 1000);
4287 } else if (!IS_GEN2(dev)) {
4288 refclk = 96000;
4289 } else {
4290 refclk = 48000;
4291 }
4292
4293 return refclk;
4294}
4295
4296static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4297 intel_clock_t *clock)
4298{
4299 /* SDVO TV has fixed PLL values depend on its clock range,
4300 this mirrors vbios setting. */
4301 if (adjusted_mode->clock >= 100000
4302 && adjusted_mode->clock < 140500) {
4303 clock->p1 = 2;
4304 clock->p2 = 10;
4305 clock->n = 3;
4306 clock->m1 = 16;
4307 clock->m2 = 8;
4308 } else if (adjusted_mode->clock >= 140500
4309 && adjusted_mode->clock <= 200000) {
4310 clock->p1 = 1;
4311 clock->p2 = 10;
4312 clock->n = 6;
4313 clock->m1 = 12;
4314 clock->m2 = 8;
4315 }
4316}
4317
a7516a05
JB		 4318static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4319 intel_clock_t *clock,
4320 intel_clock_t *reduced_clock)
4321{
4322 struct drm_device *dev = crtc->dev;
4323 struct drm_i915_private *dev_priv = dev->dev_private;
4324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4325 int pipe = intel_crtc->pipe;
4326 u32 fp, fp2 = 0;
4327
4328 if (IS_PINEVIEW(dev)) {
4329 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4330 if (reduced_clock)
4331 fp2 = (1 << reduced_clock->n) << 16 |
4332 reduced_clock->m1 << 8 | reduced_clock->m2;
4333 } else {
4334 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4335 if (reduced_clock)
4336 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4337 reduced_clock->m2;
4338 }
4339
4340 I915_WRITE(FP0(pipe), fp);
4341
4342 intel_crtc->lowfreq_avail = false;
4343 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4344 reduced_clock && i915_powersave) {
4345 I915_WRITE(FP1(pipe), fp2);
4346 intel_crtc->lowfreq_avail = true;
4347 } else {
4348 I915_WRITE(FP1(pipe), fp);
4349 }
4350}
4351
93e537a1
DV		 4352static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4353 struct drm_display_mode *adjusted_mode)
4354{
4355 struct drm_device *dev = crtc->dev;
4356 struct drm_i915_private *dev_priv = dev->dev_private;
4357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4358 int pipe = intel_crtc->pipe;
284d5df5 4359 u32 temp;
93e537a1
DV		 4360
4361 temp = I915_READ(LVDS);
4362 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4363 if (pipe == 1) {
4364 temp |= LVDS_PIPEB_SELECT;
4365 } else {
4366 temp &= ~LVDS_PIPEB_SELECT;
4367 }
4368 /* set the corresponsding LVDS_BORDER bit */
4369 temp |= dev_priv->lvds_border_bits;
4370 /* Set the B0-B3 data pairs corresponding to whether we're going to
4371 * set the DPLLs for dual-channel mode or not.
4372 */
4373 if (clock->p2 == 7)
4374 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4375 else
4376 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4377
4378 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4379 * appropriately here, but we need to look more thoroughly into how
4380 * panels behave in the two modes.
4381 */
4382 /* set the dithering flag on LVDS as needed */
4383 if (INTEL_INFO(dev)->gen >= 4) {
4384 if (dev_priv->lvds_dither)
4385 temp |= LVDS_ENABLE_DITHER;
4386 else
4387 temp &= ~LVDS_ENABLE_DITHER;
4388 }
284d5df5 4389 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4390 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4391 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4392 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4393 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4394 I915_WRITE(LVDS, temp);
4395}
4396
a0c4da24
JB		 4397static void vlv_update_pll(struct drm_crtc *crtc,
4398 struct drm_display_mode *mode,
4399 struct drm_display_mode *adjusted_mode,
4400 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4401 int num_connectors)
a0c4da24
JB		 4402{
4403 struct drm_device *dev = crtc->dev;
4404 struct drm_i915_private *dev_priv = dev->dev_private;
4405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4406 int pipe = intel_crtc->pipe;
4407 u32 dpll, mdiv, pdiv;
4408 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4409 bool is_sdvo;
4410 u32 temp;
4411
4412 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4413 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4414
2a8f64ca
VP		 4415 dpll = DPLL_VGA_MODE_DIS;
4416 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4417 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4418 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4419
4420 I915_WRITE(DPLL(pipe), dpll);
4421 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4422
4423 bestn = clock->n;
4424 bestm1 = clock->m1;
4425 bestm2 = clock->m2;
4426 bestp1 = clock->p1;
4427 bestp2 = clock->p2;
4428
2a8f64ca
VP		 4429 /*
4430 * In Valleyview PLL and program lane counter registers are exposed
4431 * through DPIO interface
4432 */
a0c4da24
JB		 4433 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4434 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4435 mdiv |= ((bestn << DPIO_N_SHIFT));
4436 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4437 mdiv |= (1 << DPIO_K_SHIFT);
4438 mdiv |= DPIO_ENABLE_CALIBRATION;
4439 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4440
4441 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4442
2a8f64ca 4443 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4444 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4445 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4446 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4447 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4448
2a8f64ca 4449 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4450
4451 dpll |= DPLL_VCO_ENABLE;
4452 I915_WRITE(DPLL(pipe), dpll);
4453 POSTING_READ(DPLL(pipe));
4454 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4455 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4456
2a8f64ca
VP		 4457 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4458
4459 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4460 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4461
4462 I915_WRITE(DPLL(pipe), dpll);
4463
4464 /* Wait for the clocks to stabilize. */
4465 POSTING_READ(DPLL(pipe));
4466 udelay(150);
a0c4da24 4467
2a8f64ca
VP		 4468 temp = 0;
4469 if (is_sdvo) {
4470 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4471 if (temp > 1)
4472 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4473 else
4474 temp = 0;
a0c4da24 4475 }
2a8f64ca
VP		 4476 I915_WRITE(DPLL_MD(pipe), temp);
4477 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4478
2a8f64ca
VP		 4479 /* Now program lane control registers */
4480 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4481 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4482 {
4483 temp = 0x1000C4;
4484 if(pipe == 1)
4485 temp |= (1 << 21);
4486 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4487 }
4488 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4489 {
4490 temp = 0x1000C4;
4491 if(pipe == 1)
4492 temp |= (1 << 21);
4493 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4494 }
a0c4da24
JB		 4495}
4496
eb1cbe48
DV		 4497static void i9xx_update_pll(struct drm_crtc *crtc,
4498 struct drm_display_mode *mode,
4499 struct drm_display_mode *adjusted_mode,
4500 intel_clock_t *clock, intel_clock_t *reduced_clock,
4501 int num_connectors)
4502{
4503 struct drm_device *dev = crtc->dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4506 int pipe = intel_crtc->pipe;
4507 u32 dpll;
4508 bool is_sdvo;
4509
2a8f64ca
VP		 4510 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4511
eb1cbe48
DV		 4512 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4513 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4514
4515 dpll = DPLL_VGA_MODE_DIS;
4516
4517 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4518 dpll |= DPLLB_MODE_LVDS;
4519 else
4520 dpll |= DPLLB_MODE_DAC_SERIAL;
4521 if (is_sdvo) {
4522 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4523 if (pixel_multiplier > 1) {
4524 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4525 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4526 }
4527 dpll |= DPLL_DVO_HIGH_SPEED;
4528 }
4529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4530 dpll |= DPLL_DVO_HIGH_SPEED;
4531
4532 /* compute bitmask from p1 value */
4533 if (IS_PINEVIEW(dev))
4534 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4535 else {
4536 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4537 if (IS_G4X(dev) && reduced_clock)
4538 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4539 }
4540 switch (clock->p2) {
4541 case 5:
4542 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4543 break;
4544 case 7:
4545 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4546 break;
4547 case 10:
4548 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4549 break;
4550 case 14:
4551 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4552 break;
4553 }
4554 if (INTEL_INFO(dev)->gen >= 4)
4555 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4556
4557 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4558 dpll |= PLL_REF_INPUT_TVCLKINBC;
4559 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4560 /* XXX: just matching BIOS for now */
4561 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4562 dpll |= 3;
4563 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4564 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4565 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4566 else
4567 dpll |= PLL_REF_INPUT_DREFCLK;
4568
4569 dpll |= DPLL_VCO_ENABLE;
4570 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4571 POSTING_READ(DPLL(pipe));
4572 udelay(150);
4573
4574 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4575 * This is an exception to the general rule that mode_set doesn't turn
4576 * things on.
4577 */
4578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4579 intel_update_lvds(crtc, clock, adjusted_mode);
4580
4581 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4582 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4583
4584 I915_WRITE(DPLL(pipe), dpll);
4585
4586 /* Wait for the clocks to stabilize. */
4587 POSTING_READ(DPLL(pipe));
4588 udelay(150);
4589
4590 if (INTEL_INFO(dev)->gen >= 4) {
4591 u32 temp = 0;
4592 if (is_sdvo) {
4593 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4594 if (temp > 1)
4595 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4596 else
4597 temp = 0;
4598 }
4599 I915_WRITE(DPLL_MD(pipe), temp);
4600 } else {
4601 /* The pixel multiplier can only be updated once the
4602 * DPLL is enabled and the clocks are stable.
4603 *
4604 * So write it again.
4605 */
4606 I915_WRITE(DPLL(pipe), dpll);
4607 }
4608}
4609
4610static void i8xx_update_pll(struct drm_crtc *crtc,
4611 struct drm_display_mode *adjusted_mode,
2a8f64ca 4612 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4613 int num_connectors)
4614{
4615 struct drm_device *dev = crtc->dev;
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4618 int pipe = intel_crtc->pipe;
4619 u32 dpll;
4620
2a8f64ca
VP		 4621 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4622
eb1cbe48
DV		 4623 dpll = DPLL_VGA_MODE_DIS;
4624
4625 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4626 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4627 } else {
4628 if (clock->p1 == 2)
4629 dpll |= PLL_P1_DIVIDE_BY_TWO;
4630 else
4631 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4632 if (clock->p2 == 4)
4633 dpll |= PLL_P2_DIVIDE_BY_4;
4634 }
4635
4636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4637 /* XXX: just matching BIOS for now */
4638 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4639 dpll |= 3;
4640 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4641 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4642 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4643 else
4644 dpll |= PLL_REF_INPUT_DREFCLK;
4645
4646 dpll |= DPLL_VCO_ENABLE;
4647 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4648 POSTING_READ(DPLL(pipe));
4649 udelay(150);
4650
eb1cbe48
DV		 4651 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4652 * This is an exception to the general rule that mode_set doesn't turn
4653 * things on.
4654 */
4655 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4656 intel_update_lvds(crtc, clock, adjusted_mode);
4657
5b5896e4
DV		 4658 I915_WRITE(DPLL(pipe), dpll);
4659
4660 /* Wait for the clocks to stabilize. */
4661 POSTING_READ(DPLL(pipe));
4662 udelay(150);
4663
eb1cbe48
DV		 4664 /* The pixel multiplier can only be updated once the
4665 * DPLL is enabled and the clocks are stable.
4666 *
4667 * So write it again.
4668 */
4669 I915_WRITE(DPLL(pipe), dpll);
4670}
4671
b0e77b9c
PZ		 4672static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4673 struct drm_display_mode *mode,
4674 struct drm_display_mode *adjusted_mode)
4675{
4676 struct drm_device *dev = intel_crtc->base.dev;
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4679 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4680 uint32_t vsyncshift;
4681
4682 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4683 /* the chip adds 2 halflines automatically */
4684 adjusted_mode->crtc_vtotal -= 1;
4685 adjusted_mode->crtc_vblank_end -= 1;
4686 vsyncshift = adjusted_mode->crtc_hsync_start
4687 - adjusted_mode->crtc_htotal / 2;
4688 } else {
4689 vsyncshift = 0;
4690 }
4691
4692 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4693 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4694
fe2b8f9d 4695 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4696 (adjusted_mode->crtc_hdisplay - 1) |
4697 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4698 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4699 (adjusted_mode->crtc_hblank_start - 1) |
4700 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4701 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4702 (adjusted_mode->crtc_hsync_start - 1) |
4703 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4704
fe2b8f9d 4705 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4706 (adjusted_mode->crtc_vdisplay - 1) |
4707 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4708 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4709 (adjusted_mode->crtc_vblank_start - 1) |
4710 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4711 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4712 (adjusted_mode->crtc_vsync_start - 1) |
4713 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4714
b5e508d4
PZ		 4715 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4716 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4717 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4718 * bits. */
4719 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4720 (pipe == PIPE_B || pipe == PIPE_C))
4721 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4722
b0e77b9c
PZ		 4723 /* pipesrc controls the size that is scaled from, which should
4724 * always be the user's requested size.
4725 */
4726 I915_WRITE(PIPESRC(pipe),
4727 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4728}
4729
f564048e
EA		 4730static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4731 struct drm_display_mode *mode,
4732 struct drm_display_mode *adjusted_mode,
4733 int x, int y,
94352cf9 4734 struct drm_framebuffer *fb)
79e53945
JB		 4735{
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
80824003 4740 int plane = intel_crtc->plane;
c751ce4f 4741 int refclk, num_connectors = 0;
652c393a 4742 intel_clock_t clock, reduced_clock;
b0e77b9c 4743 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4744 bool ok, has_reduced_clock = false, is_sdvo = false;
4745 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4746 struct intel_encoder *encoder;
d4906093 4747 const intel_limit_t *limit;
5c3b82e2 4748 int ret;
79e53945 4749
6c2b7c12 4750 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4751 switch (encoder->type) {
79e53945
JB		 4752 case INTEL_OUTPUT_LVDS:
4753 is_lvds = true;
4754 break;
4755 case INTEL_OUTPUT_SDVO:
7d57382e 4756 case INTEL_OUTPUT_HDMI:
79e53945 4757 is_sdvo = true;
5eddb70b 4758 if (encoder->needs_tv_clock)
e2f0ba97 4759 is_tv = true;
79e53945 4760 break;
79e53945
JB		 4761 case INTEL_OUTPUT_TVOUT:
4762 is_tv = true;
4763 break;
a4fc5ed6
KP		 4764 case INTEL_OUTPUT_DISPLAYPORT:
4765 is_dp = true;
4766 break;
79e53945 4767 }
43565a06 4768
c751ce4f 4769 num_connectors++;
79e53945
JB		 4770 }
4771
c65d77d8 4772 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4773
d4906093
ML		 4774 /*
4775 * Returns a set of divisors for the desired target clock with the given
4776 * refclk, or FALSE. The returned values represent the clock equation:
4777 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4778 */
1b894b59 4779 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4780 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4781 &clock);
79e53945
JB		 4782 if (!ok) {
4783 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4784 return -EINVAL;
79e53945
JB		 4785 }
4786
cda4b7d3 4787 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4788 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4789
ddc9003c 4790 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4791 /*
4792 * Ensure we match the reduced clock's P to the target clock.
4793 * If the clocks don't match, we can't switch the display clock
4794 * by using the FP0/FP1. In such case we will disable the LVDS
4795 * downclock feature.
4796 */
ddc9003c 4797 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4798 dev_priv->lvds_downclock,
4799 refclk,
cec2f356 4800 &clock,
5eddb70b 4801 &reduced_clock);
7026d4ac
ZW		 4802 }
4803
c65d77d8
JB		 4804 if (is_sdvo && is_tv)
4805 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4806
eb1cbe48 4807 if (IS_GEN2(dev))
2a8f64ca
VP		 4808 i8xx_update_pll(crtc, adjusted_mode, &clock,
4809 has_reduced_clock ? &reduced_clock : NULL,
4810 num_connectors);
a0c4da24 4811 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4812 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4813 has_reduced_clock ? &reduced_clock : NULL,
4814 num_connectors);
79e53945 4815 else
eb1cbe48
DV		 4816 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4817 has_reduced_clock ? &reduced_clock : NULL,
4818 num_connectors);
79e53945
JB		 4819
4820 /* setup pipeconf */
5eddb70b 4821 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4822
4823 /* Set up the display plane register */
4824 dspcntr = DISPPLANE_GAMMA_ENABLE;
4825
929c77fb
EA		 4826 if (pipe == 0)
4827 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4828 else
4829 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4830
a6c45cf0 4831 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4832 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4833 * core speed.
4834 *
4835 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4836 * pipe == 0 check?
4837 */
e70236a8
JB		 4838 if (mode->clock >
4839 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4840 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4841 else
5eddb70b 4842 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4843 }
4844
3b5c78a3
AJ		 4845 /* default to 8bpc */
4846 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4847 if (is_dp) {
0c96c65b 4848 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4849 pipeconf |= PIPECONF_BPP_6 |
4850 PIPECONF_DITHER_EN |
4851 PIPECONF_DITHER_TYPE_SP;
4852 }
4853 }
4854
19c03924
GB		 4855 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4856 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4857 pipeconf |= PIPECONF_BPP_6 |
4858 PIPECONF_ENABLE |
4859 I965_PIPECONF_ACTIVE;
4860 }
4861 }
4862
28c97730 4863 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4864 drm_mode_debug_printmodeline(mode);
4865
a7516a05
JB		 4866 if (HAS_PIPE_CXSR(dev)) {
4867 if (intel_crtc->lowfreq_avail) {
28c97730 4868 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4869 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4870 } else {
28c97730 4871 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4872 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4873 }
4874 }
4875
617cf884 4876 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4877 if (!IS_GEN2(dev) &&
b0e77b9c 4878 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4879 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4880 else
617cf884 4881 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4882
b0e77b9c 4883 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4884
4885 /* pipesrc and dspsize control the size that is scaled from,
4886 * which should always be the user's requested size.
79e53945 4887 */
929c77fb
EA		 4888 I915_WRITE(DSPSIZE(plane),
4889 ((mode->vdisplay - 1) << 16) |
4890 (mode->hdisplay - 1));
4891 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4892
f564048e
EA		 4893 I915_WRITE(PIPECONF(pipe), pipeconf);
4894 POSTING_READ(PIPECONF(pipe));
929c77fb 4895 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4896
4897 intel_wait_for_vblank(dev, pipe);
4898
f564048e
EA		 4899 I915_WRITE(DSPCNTR(plane), dspcntr);
4900 POSTING_READ(DSPCNTR(plane));
4901
94352cf9 4902 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4903
4904 intel_update_watermarks(dev);
4905
f564048e
EA		 4906 return ret;
4907}
4908
9fb526db
KP		 4909/*
4910 * Initialize reference clocks when the driver loads
4911 */
4912void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4913{
4914 struct drm_i915_private *dev_priv = dev->dev_private;
4915 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4916 struct intel_encoder *encoder;
13d83a67
JB		 4917 u32 temp;
4918 bool has_lvds = false;
199e5d79
KP		 4919 bool has_cpu_edp = false;
4920 bool has_pch_edp = false;
4921 bool has_panel = false;
99eb6a01
KP		 4922 bool has_ck505 = false;
4923 bool can_ssc = false;
13d83a67
JB		 4924
4925 /* We need to take the global config into account */
199e5d79
KP		 4926 list_for_each_entry(encoder, &mode_config->encoder_list,
4927 base.head) {
4928 switch (encoder->type) {
4929 case INTEL_OUTPUT_LVDS:
4930 has_panel = true;
4931 has_lvds = true;
4932 break;
4933 case INTEL_OUTPUT_EDP:
4934 has_panel = true;
4935 if (intel_encoder_is_pch_edp(&encoder->base))
4936 has_pch_edp = true;
4937 else
4938 has_cpu_edp = true;
4939 break;
13d83a67
JB		 4940 }
4941 }
4942
99eb6a01
KP		 4943 if (HAS_PCH_IBX(dev)) {
4944 has_ck505 = dev_priv->display_clock_mode;
4945 can_ssc = has_ck505;
4946 } else {
4947 has_ck505 = false;
4948 can_ssc = true;
4949 }
4950
4951 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4952 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4953 has_ck505);
13d83a67
JB		 4954
4955 /* Ironlake: try to setup display ref clock before DPLL
4956 * enabling. This is only under driver's control after
4957 * PCH B stepping, previous chipset stepping should be
4958 * ignoring this setting.
4959 */
4960 temp = I915_READ(PCH_DREF_CONTROL);
4961 /* Always enable nonspread source */
4962 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4963
99eb6a01
KP		 4964 if (has_ck505)
4965 temp |= DREF_NONSPREAD_CK505_ENABLE;
4966 else
4967 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4968
199e5d79
KP		 4969 if (has_panel) {
4970 temp &= ~DREF_SSC_SOURCE_MASK;
4971 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4972
199e5d79 4973 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4974 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4975 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4976 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4977 } else
4978 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4979
4980 /* Get SSC going before enabling the outputs */
4981 I915_WRITE(PCH_DREF_CONTROL, temp);
4982 POSTING_READ(PCH_DREF_CONTROL);
4983 udelay(200);
4984
13d83a67
JB		 4985 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4986
4987 /* Enable CPU source on CPU attached eDP */
199e5d79 4988 if (has_cpu_edp) {
99eb6a01 4989 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4990 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4991 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4992 }
13d83a67
JB		 4993 else
4994 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4995 } else
4996 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4997
4998 I915_WRITE(PCH_DREF_CONTROL, temp);
4999 POSTING_READ(PCH_DREF_CONTROL);
5000 udelay(200);
5001 } else {
5002 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5003
5004 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5005
5006 /* Turn off CPU output */
5007 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5008
5009 I915_WRITE(PCH_DREF_CONTROL, temp);
5010 POSTING_READ(PCH_DREF_CONTROL);
5011 udelay(200);
5012
5013 /* Turn off the SSC source */
5014 temp &= ~DREF_SSC_SOURCE_MASK;
5015 temp |= DREF_SSC_SOURCE_DISABLE;
5016
5017 /* Turn off SSC1 */
5018 temp &= ~ DREF_SSC1_ENABLE;
5019
13d83a67
JB		 5020 I915_WRITE(PCH_DREF_CONTROL, temp);
5021 POSTING_READ(PCH_DREF_CONTROL);
5022 udelay(200);
5023 }
5024}
5025
d9d444cb
JB		 5026static int ironlake_get_refclk(struct drm_crtc *crtc)
5027{
5028 struct drm_device *dev = crtc->dev;
5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 struct intel_encoder *encoder;
d9d444cb
JB		 5031 struct intel_encoder *edp_encoder = NULL;
5032 int num_connectors = 0;
5033 bool is_lvds = false;
5034
6c2b7c12 5035 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5036 switch (encoder->type) {
5037 case INTEL_OUTPUT_LVDS:
5038 is_lvds = true;
5039 break;
5040 case INTEL_OUTPUT_EDP:
5041 edp_encoder = encoder;
5042 break;
5043 }
5044 num_connectors++;
5045 }
5046
5047 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5048 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5049 dev_priv->lvds_ssc_freq);
5050 return dev_priv->lvds_ssc_freq * 1000;
5051 }
5052
5053 return 120000;
5054}
5055
c8203565
PZ		 5056static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5057 struct drm_display_mode *adjusted_mode,
5058 bool dither)
5059{
5060 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062 int pipe = intel_crtc->pipe;
5063 uint32_t val;
5064
5065 val = I915_READ(PIPECONF(pipe));
5066
5067 val &= ~PIPE_BPC_MASK;
5068 switch (intel_crtc->bpp) {
5069 case 18:
5070 val |= PIPE_6BPC;
5071 break;
5072 case 24:
5073 val |= PIPE_8BPC;
5074 break;
5075 case 30:
5076 val |= PIPE_10BPC;
5077 break;
5078 case 36:
5079 val |= PIPE_12BPC;
5080 break;
5081 default:
cc769b62
PZ		 5082 /* Case prevented by intel_choose_pipe_bpp_dither. */
5083 BUG();
c8203565
PZ		 5084 }
5085
5086 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5087 if (dither)
5088 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5089
5090 val &= ~PIPECONF_INTERLACE_MASK;
5091 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5092 val |= PIPECONF_INTERLACED_ILK;
5093 else
5094 val |= PIPECONF_PROGRESSIVE;
5095
5096 I915_WRITE(PIPECONF(pipe), val);
5097 POSTING_READ(PIPECONF(pipe));
5098}
5099
ee2b0b38
PZ		 5100static void haswell_set_pipeconf(struct drm_crtc *crtc,
5101 struct drm_display_mode *adjusted_mode,
5102 bool dither)
5103{
5104 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5106 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5107 uint32_t val;
5108
702e7a56 5109 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5110
5111 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5112 if (dither)
5113 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5114
5115 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5116 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5117 val |= PIPECONF_INTERLACED_ILK;
5118 else
5119 val |= PIPECONF_PROGRESSIVE;
5120
702e7a56
PZ		 5121 I915_WRITE(PIPECONF(cpu_transcoder), val);
5122 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5123}
5124
6591c6e4
PZ		 5125static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5126 struct drm_display_mode *adjusted_mode,
5127 intel_clock_t *clock,
5128 bool *has_reduced_clock,
5129 intel_clock_t *reduced_clock)
5130{
5131 struct drm_device *dev = crtc->dev;
5132 struct drm_i915_private *dev_priv = dev->dev_private;
5133 struct intel_encoder *intel_encoder;
5134 int refclk;
5135 const intel_limit_t *limit;
5136 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5137
5138 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5139 switch (intel_encoder->type) {
5140 case INTEL_OUTPUT_LVDS:
5141 is_lvds = true;
5142 break;
5143 case INTEL_OUTPUT_SDVO:
5144 case INTEL_OUTPUT_HDMI:
5145 is_sdvo = true;
5146 if (intel_encoder->needs_tv_clock)
5147 is_tv = true;
5148 break;
5149 case INTEL_OUTPUT_TVOUT:
5150 is_tv = true;
5151 break;
5152 }
5153 }
5154
5155 refclk = ironlake_get_refclk(crtc);
5156
5157 /*
5158 * Returns a set of divisors for the desired target clock with the given
5159 * refclk, or FALSE. The returned values represent the clock equation:
5160 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5161 */
5162 limit = intel_limit(crtc, refclk);
5163 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5164 clock);
5165 if (!ret)
5166 return false;
5167
5168 if (is_lvds && dev_priv->lvds_downclock_avail) {
5169 /*
5170 * Ensure we match the reduced clock's P to the target clock.
5171 * If the clocks don't match, we can't switch the display clock
5172 * by using the FP0/FP1. In such case we will disable the LVDS
5173 * downclock feature.
5174 */
5175 *has_reduced_clock = limit->find_pll(limit, crtc,
5176 dev_priv->lvds_downclock,
5177 refclk,
5178 clock,
5179 reduced_clock);
5180 }
5181
5182 if (is_sdvo && is_tv)
5183 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5184
5185 return true;
5186}
5187
01a415fd
DV		 5188static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5189{
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 uint32_t temp;
5192
5193 temp = I915_READ(SOUTH_CHICKEN1);
5194 if (temp & FDI_BC_BIFURCATION_SELECT)
5195 return;
5196
5197 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5198 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5199
5200 temp |= FDI_BC_BIFURCATION_SELECT;
5201 DRM_DEBUG_KMS("enabling fdi C rx\n");
5202 I915_WRITE(SOUTH_CHICKEN1, temp);
5203 POSTING_READ(SOUTH_CHICKEN1);
5204}
5205
5206static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5207{
5208 struct drm_device *dev = intel_crtc->base.dev;
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 struct intel_crtc *pipe_B_crtc =
5211 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5212
5213 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5214 intel_crtc->pipe, intel_crtc->fdi_lanes);
5215 if (intel_crtc->fdi_lanes > 4) {
5216 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5217 intel_crtc->pipe, intel_crtc->fdi_lanes);
5218 /* Clamp lanes to avoid programming the hw with bogus values. */
5219 intel_crtc->fdi_lanes = 4;
5220
5221 return false;
5222 }
5223
5224 if (dev_priv->num_pipe == 2)
5225 return true;
5226
5227 switch (intel_crtc->pipe) {
5228 case PIPE_A:
5229 return true;
5230 case PIPE_B:
5231 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5232 intel_crtc->fdi_lanes > 2) {
5233 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5234 intel_crtc->pipe, intel_crtc->fdi_lanes);
5235 /* Clamp lanes to avoid programming the hw with bogus values. */
5236 intel_crtc->fdi_lanes = 2;
5237
5238 return false;
5239 }
5240
5241 if (intel_crtc->fdi_lanes > 2)
5242 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5243 else
5244 cpt_enable_fdi_bc_bifurcation(dev);
5245
5246 return true;
5247 case PIPE_C:
5248 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5249 if (intel_crtc->fdi_lanes > 2) {
5250 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5251 intel_crtc->pipe, intel_crtc->fdi_lanes);
5252 /* Clamp lanes to avoid programming the hw with bogus values. */
5253 intel_crtc->fdi_lanes = 2;
5254
5255 return false;
5256 }
5257 } else {
5258 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5259 return false;
5260 }
5261
5262 cpt_enable_fdi_bc_bifurcation(dev);
5263
5264 return true;
5265 default:
5266 BUG();
5267 }
5268}
5269
f48d8f23
PZ		 5270static void ironlake_set_m_n(struct drm_crtc *crtc,
5271 struct drm_display_mode *mode,
5272 struct drm_display_mode *adjusted_mode)
5273{
5274 struct drm_device *dev = crtc->dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5277 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5278 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5279 struct fdi_m_n m_n = {0};
5280 int target_clock, pixel_multiplier, lane, link_bw;
5281 bool is_dp = false, is_cpu_edp = false;
5282
5283 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5284 switch (intel_encoder->type) {
5285 case INTEL_OUTPUT_DISPLAYPORT:
5286 is_dp = true;
5287 break;
5288 case INTEL_OUTPUT_EDP:
5289 is_dp = true;
5290 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5291 is_cpu_edp = true;
5292 edp_encoder = intel_encoder;
5293 break;
5294 }
5295 }
5296
5297 /* FDI link */
5298 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5299 lane = 0;
5300 /* CPU eDP doesn't require FDI link, so just set DP M/N
5301 according to current link config */
5302 if (is_cpu_edp) {
5303 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5304 } else {
5305 /* FDI is a binary signal running at ~2.7GHz, encoding
5306 * each output octet as 10 bits. The actual frequency
5307 * is stored as a divider into a 100MHz clock, and the
5308 * mode pixel clock is stored in units of 1KHz.
5309 * Hence the bw of each lane in terms of the mode signal
5310 * is:
5311 */
5312 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5313 }
5314
5315 /* [e]DP over FDI requires target mode clock instead of link clock. */
5316 if (edp_encoder)
5317 target_clock = intel_edp_target_clock(edp_encoder, mode);
5318 else if (is_dp)
5319 target_clock = mode->clock;
5320 else
5321 target_clock = adjusted_mode->clock;
5322
5323 if (!lane) {
5324 /*
5325 * Account for spread spectrum to avoid
5326 * oversubscribing the link. Max center spread
5327 * is 2.5%; use 5% for safety's sake.
5328 */
5329 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5330 lane = bps / (link_bw * 8) + 1;
5331 }
5332
5333 intel_crtc->fdi_lanes = lane;
5334
5335 if (pixel_multiplier > 1)
5336 link_bw *= pixel_multiplier;
5337 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5338 &m_n);
5339
afe2fcf5
PZ		 5340 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5341 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5342 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5343 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5344}
5345
de13a2e3
PZ		 5346static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5347 struct drm_display_mode *adjusted_mode,
5348 intel_clock_t *clock, u32 fp)
79e53945 5349{
de13a2e3 5350 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5351 struct drm_device *dev = crtc->dev;
5352 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5353 struct intel_encoder *intel_encoder;
5354 uint32_t dpll;
5355 int factor, pixel_multiplier, num_connectors = 0;
5356 bool is_lvds = false, is_sdvo = false, is_tv = false;
5357 bool is_dp = false, is_cpu_edp = false;
79e53945 5358
de13a2e3
PZ		 5359 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5360 switch (intel_encoder->type) {
79e53945
JB		 5361 case INTEL_OUTPUT_LVDS:
5362 is_lvds = true;
5363 break;
5364 case INTEL_OUTPUT_SDVO:
7d57382e 5365 case INTEL_OUTPUT_HDMI:
79e53945 5366 is_sdvo = true;
de13a2e3 5367 if (intel_encoder->needs_tv_clock)
e2f0ba97 5368 is_tv = true;
79e53945 5369 break;
79e53945
JB		 5370 case INTEL_OUTPUT_TVOUT:
5371 is_tv = true;
5372 break;
a4fc5ed6
KP		 5373 case INTEL_OUTPUT_DISPLAYPORT:
5374 is_dp = true;
5375 break;
32f9d658 5376 case INTEL_OUTPUT_EDP:
e3aef172 5377 is_dp = true;
de13a2e3 5378 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5379 is_cpu_edp = true;
32f9d658 5380 break;
79e53945 5381 }
43565a06 5382
c751ce4f 5383 num_connectors++;
79e53945
JB		 5384 }
5385
c1858123 5386 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5387 factor = 21;
5388 if (is_lvds) {
5389 if ((intel_panel_use_ssc(dev_priv) &&
5390 dev_priv->lvds_ssc_freq == 100) ||
5391 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5392 factor = 25;
5393 } else if (is_sdvo && is_tv)
5394 factor = 20;
c1858123 5395
de13a2e3 5396 if (clock->m < factor * clock->n)
8febb297 5397 fp |= FP_CB_TUNE;
2c07245f 5398
5eddb70b 5399 dpll = 0;
2c07245f 5400
a07d6787
EA		 5401 if (is_lvds)
5402 dpll |= DPLLB_MODE_LVDS;
5403 else
5404 dpll |= DPLLB_MODE_DAC_SERIAL;
5405 if (is_sdvo) {
de13a2e3 5406 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5407 if (pixel_multiplier > 1) {
5408 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5409 }
a07d6787
EA		 5410 dpll |= DPLL_DVO_HIGH_SPEED;
5411 }
e3aef172 5412 if (is_dp && !is_cpu_edp)
a07d6787 5413 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5414
a07d6787 5415 /* compute bitmask from p1 value */
de13a2e3 5416 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5417 /* also FPA1 */
de13a2e3 5418 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5419
de13a2e3 5420 switch (clock->p2) {
a07d6787
EA		 5421 case 5:
5422 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5423 break;
5424 case 7:
5425 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5426 break;
5427 case 10:
5428 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5429 break;
5430 case 14:
5431 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5432 break;
79e53945
JB		 5433 }
5434
43565a06
KH		 5435 if (is_sdvo && is_tv)
5436 dpll |= PLL_REF_INPUT_TVCLKINBC;
5437 else if (is_tv)
79e53945 5438 /* XXX: just matching BIOS for now */
43565a06 5439 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5440 dpll |= 3;
a7615030 5441 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5442 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5443 else
5444 dpll |= PLL_REF_INPUT_DREFCLK;
5445
de13a2e3
PZ		 5446 return dpll;
5447}
5448
5449static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5450 struct drm_display_mode *mode,
5451 struct drm_display_mode *adjusted_mode,
5452 int x, int y,
5453 struct drm_framebuffer *fb)
5454{
5455 struct drm_device *dev = crtc->dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5458 int pipe = intel_crtc->pipe;
5459 int plane = intel_crtc->plane;
5460 int num_connectors = 0;
5461 intel_clock_t clock, reduced_clock;
5462 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5463 bool ok, has_reduced_clock = false;
5464 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5465 struct intel_encoder *encoder;
5466 u32 temp;
5467 int ret;
01a415fd 5468 bool dither, fdi_config_ok;
de13a2e3
PZ		 5469
5470 for_each_encoder_on_crtc(dev, crtc, encoder) {
5471 switch (encoder->type) {
5472 case INTEL_OUTPUT_LVDS:
5473 is_lvds = true;
5474 break;
de13a2e3
PZ		 5475 case INTEL_OUTPUT_DISPLAYPORT:
5476 is_dp = true;
5477 break;
5478 case INTEL_OUTPUT_EDP:
5479 is_dp = true;
e2f12b07 5480 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5481 is_cpu_edp = true;
5482 break;
5483 }
5484
5485 num_connectors++;
5486 }
5487
5dc5298b
PZ		 5488 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5489 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5490
de13a2e3
PZ		 5491 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5492 &has_reduced_clock, &reduced_clock);
5493 if (!ok) {
5494 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5495 return -EINVAL;
5496 }
5497
5498 /* Ensure that the cursor is valid for the new mode before changing... */
5499 intel_crtc_update_cursor(crtc, true);
5500
5501 /* determine panel color depth */
c8241969
JN		 5502 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5503 adjusted_mode);
de13a2e3
PZ		 5504 if (is_lvds && dev_priv->lvds_dither)
5505 dither = true;
5506
5507 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5508 if (has_reduced_clock)
5509 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5510 reduced_clock.m2;
5511
5512 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5513
f7cb34d4 5514 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5515 drm_mode_debug_printmodeline(mode);
5516
5dc5298b
PZ		 5517 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5518 if (!is_cpu_edp) {
ee7b9f93 5519 struct intel_pch_pll *pll;
4b645f14 5520
ee7b9f93
JB		 5521 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5522 if (pll == NULL) {
5523 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5524 pipe);
4b645f14
JB		 5525 return -EINVAL;
5526 }
ee7b9f93
JB		 5527 } else
5528 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5529
5530 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5531 * This is an exception to the general rule that mode_set doesn't turn
5532 * things on.
5533 */
5534 if (is_lvds) {
fae14981 5535 temp = I915_READ(PCH_LVDS);
5eddb70b 5536 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5537 if (HAS_PCH_CPT(dev)) {
5538 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5539 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5540 } else {
5541 if (pipe == 1)
5542 temp |= LVDS_PIPEB_SELECT;
5543 else
5544 temp &= ~LVDS_PIPEB_SELECT;
5545 }
4b645f14 5546
a3e17eb8 5547 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5548 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5549 /* Set the B0-B3 data pairs corresponding to whether we're going to
5550 * set the DPLLs for dual-channel mode or not.
5551 */
5552 if (clock.p2 == 7)
5eddb70b 5553 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5554 else
5eddb70b 5555 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5556
5557 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5558 * appropriately here, but we need to look more thoroughly into how
5559 * panels behave in the two modes.
5560 */
284d5df5 5561 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5562 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5563 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5564 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5565 temp |= LVDS_VSYNC_POLARITY;
fae14981 5566 I915_WRITE(PCH_LVDS, temp);
79e53945 5567 }
434ed097 5568
e3aef172 5569 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5570 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5571 } else {
8db9d77b 5572 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5573 I915_WRITE(TRANSDATA_M1(pipe), 0);
5574 I915_WRITE(TRANSDATA_N1(pipe), 0);
5575 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5576 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5577 }
79e53945 5578
ee7b9f93
JB		 5579 if (intel_crtc->pch_pll) {
5580 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5581
32f9d658 5582 /* Wait for the clocks to stabilize. */
ee7b9f93 5583 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5584 udelay(150);
5585
8febb297
EA		 5586 /* The pixel multiplier can only be updated once the
5587 * DPLL is enabled and the clocks are stable.
5588 *
5589 * So write it again.
5590 */
ee7b9f93 5591 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5592 }
79e53945 5593
5eddb70b 5594 intel_crtc->lowfreq_avail = false;
ee7b9f93 5595 if (intel_crtc->pch_pll) {
4b645f14 5596 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5597 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5598 intel_crtc->lowfreq_avail = true;
4b645f14 5599 } else {
ee7b9f93 5600 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5601 }
5602 }
5603
b0e77b9c 5604 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5605
01a415fd
DV		 5606 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5607 * ironlake_check_fdi_lanes. */
f48d8f23 5608 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5609
01a415fd
DV		 5610 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5611
e3aef172 5612 if (is_cpu_edp)
8febb297 5613 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5614
c8203565 5615 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5616
9d0498a2 5617 intel_wait_for_vblank(dev, pipe);
79e53945 5618
a1f9e77e
PZ		 5619 /* Set up the display plane register */
5620 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5621 POSTING_READ(DSPCNTR(plane));
79e53945 5622
94352cf9 5623 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5624
5625 intel_update_watermarks(dev);
5626
1f8eeabf
ED		 5627 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5628
01a415fd 5629 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5630}
5631
09b4ddf9
PZ		 5632static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5633 struct drm_display_mode *mode,
5634 struct drm_display_mode *adjusted_mode,
5635 int x, int y,
5636 struct drm_framebuffer *fb)
5637{
5638 struct drm_device *dev = crtc->dev;
5639 struct drm_i915_private *dev_priv = dev->dev_private;
5640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5641 int pipe = intel_crtc->pipe;
5642 int plane = intel_crtc->plane;
5643 int num_connectors = 0;
5644 intel_clock_t clock, reduced_clock;
5dc5298b 5645 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5646 bool ok, has_reduced_clock = false;
5647 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5648 struct intel_encoder *encoder;
5649 u32 temp;
5650 int ret;
5651 bool dither;
5652
5653 for_each_encoder_on_crtc(dev, crtc, encoder) {
5654 switch (encoder->type) {
5655 case INTEL_OUTPUT_LVDS:
5656 is_lvds = true;
5657 break;
5658 case INTEL_OUTPUT_DISPLAYPORT:
5659 is_dp = true;
5660 break;
5661 case INTEL_OUTPUT_EDP:
5662 is_dp = true;
5663 if (!intel_encoder_is_pch_edp(&encoder->base))
5664 is_cpu_edp = true;
5665 break;
5666 }
5667
5668 num_connectors++;
5669 }
5670
a5c961d1
PZ		 5671 if (is_cpu_edp)
5672 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5673 else
5674 intel_crtc->cpu_transcoder = pipe;
5675
5dc5298b
PZ		 5676 /* We are not sure yet this won't happen. */
5677 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5678 INTEL_PCH_TYPE(dev));
5679
5680 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5681 num_connectors, pipe_name(pipe));
5682
702e7a56 5683 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5684 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5685
5686 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5687
6441ab5f
PZ		 5688 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5689 return -EINVAL;
5690
5dc5298b
PZ		 5691 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5692 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5693 &has_reduced_clock,
5694 &reduced_clock);
5695 if (!ok) {
5696 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5697 return -EINVAL;
5698 }
09b4ddf9
PZ		 5699 }
5700
5701 /* Ensure that the cursor is valid for the new mode before changing... */
5702 intel_crtc_update_cursor(crtc, true);
5703
5704 /* determine panel color depth */
c8241969
JN		 5705 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5706 adjusted_mode);
09b4ddf9
PZ		 5707 if (is_lvds && dev_priv->lvds_dither)
5708 dither = true;
5709
09b4ddf9
PZ		 5710 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5711 drm_mode_debug_printmodeline(mode);
5712
5dc5298b
PZ		 5713 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5714 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5715 if (has_reduced_clock)
5716 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5717 reduced_clock.m2;
5718
5719 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5720 fp);
5721
5722 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5723 * own on pre-Haswell/LPT generation */
5724 if (!is_cpu_edp) {
5725 struct intel_pch_pll *pll;
5726
5727 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5728 if (pll == NULL) {
5729 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5730 pipe);
5731 return -EINVAL;
5732 }
5733 } else
5734 intel_put_pch_pll(intel_crtc);
09b4ddf9 5735
5dc5298b
PZ		 5736 /* The LVDS pin pair needs to be on before the DPLLs are
5737 * enabled. This is an exception to the general rule that
5738 * mode_set doesn't turn things on.
5739 */
5740 if (is_lvds) {
5741 temp = I915_READ(PCH_LVDS);
5742 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5743 if (HAS_PCH_CPT(dev)) {
5744 temp &= ~PORT_TRANS_SEL_MASK;
5745 temp |= PORT_TRANS_SEL_CPT(pipe);
5746 } else {
5747 if (pipe == 1)
5748 temp |= LVDS_PIPEB_SELECT;
5749 else
5750 temp &= ~LVDS_PIPEB_SELECT;
5751 }
09b4ddf9 5752
5dc5298b
PZ		 5753 /* set the corresponsding LVDS_BORDER bit */
5754 temp |= dev_priv->lvds_border_bits;
5755 /* Set the B0-B3 data pairs corresponding to whether
5756 * we're going to set the DPLLs for dual-channel mode or
5757 * not.
5758 */
5759 if (clock.p2 == 7)
5760 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5761 else
5dc5298b
PZ		 5762 temp &= ~(LVDS_B0B3_POWER_UP |
5763 LVDS_CLKB_POWER_UP);
5764
5765 /* It would be nice to set 24 vs 18-bit mode
5766 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5767 * look more thoroughly into how panels behave in the
5768 * two modes.
5769 */
5770 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5771 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5772 temp |= LVDS_HSYNC_POLARITY;
5773 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5774 temp |= LVDS_VSYNC_POLARITY;
5775 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5776 }
09b4ddf9
PZ		 5777 }
5778
5779 if (is_dp && !is_cpu_edp) {
5780 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5781 } else {
5dc5298b
PZ		 5782 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5783 /* For non-DP output, clear any trans DP clock recovery
5784 * setting.*/
5785 I915_WRITE(TRANSDATA_M1(pipe), 0);
5786 I915_WRITE(TRANSDATA_N1(pipe), 0);
5787 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5788 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5789 }
09b4ddf9
PZ		 5790 }
5791
5792 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5793 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5794 if (intel_crtc->pch_pll) {
5795 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5796
5797 /* Wait for the clocks to stabilize. */
5798 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5799 udelay(150);
5800
5801 /* The pixel multiplier can only be updated once the
5802 * DPLL is enabled and the clocks are stable.
5803 *
5804 * So write it again.
5805 */
5806 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5807 }
5808
5809 if (intel_crtc->pch_pll) {
5810 if (is_lvds && has_reduced_clock && i915_powersave) {
5811 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5812 intel_crtc->lowfreq_avail = true;
5813 } else {
5814 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5815 }
09b4ddf9
PZ		 5816 }
5817 }
5818
5819 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5820
1eb8dfec
PZ		 5821 if (!is_dp || is_cpu_edp)
5822 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5823
5dc5298b
PZ		 5824 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5825 if (is_cpu_edp)
5826 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5827
ee2b0b38 5828 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5829
09b4ddf9
PZ		 5830 /* Set up the display plane register */
5831 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5832 POSTING_READ(DSPCNTR(plane));
5833
5834 ret = intel_pipe_set_base(crtc, x, y, fb);
5835
5836 intel_update_watermarks(dev);
5837
5838 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5839
5840 return ret;
5841}
5842
f564048e
EA		 5843static int intel_crtc_mode_set(struct drm_crtc *crtc,
5844 struct drm_display_mode *mode,
5845 struct drm_display_mode *adjusted_mode,
5846 int x, int y,
94352cf9 5847 struct drm_framebuffer *fb)
f564048e
EA		 5848{
5849 struct drm_device *dev = crtc->dev;
5850 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5851 struct drm_encoder_helper_funcs *encoder_funcs;
5852 struct intel_encoder *encoder;
0b701d27
EA		 5853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5854 int pipe = intel_crtc->pipe;
f564048e
EA		 5855 int ret;
5856
0b701d27 5857 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5858
f564048e 5859 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5860 x, y, fb);
79e53945 5861 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5862
9256aa19
DV		 5863 if (ret != 0)
5864 return ret;
5865
5866 for_each_encoder_on_crtc(dev, crtc, encoder) {
5867 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5868 encoder->base.base.id,
5869 drm_get_encoder_name(&encoder->base),
5870 mode->base.id, mode->name);
5871 encoder_funcs = encoder->base.helper_private;
5872 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5873 }
5874
5875 return 0;
79e53945
JB		 5876}
5877
3a9627f4
WF		 5878static bool intel_eld_uptodate(struct drm_connector *connector,
5879 int reg_eldv, uint32_t bits_eldv,
5880 int reg_elda, uint32_t bits_elda,
5881 int reg_edid)
5882{
5883 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5884 uint8_t *eld = connector->eld;
5885 uint32_t i;
5886
5887 i = I915_READ(reg_eldv);
5888 i &= bits_eldv;
5889
5890 if (!eld[0])
5891 return !i;
5892
5893 if (!i)
5894 return false;
5895
5896 i = I915_READ(reg_elda);
5897 i &= ~bits_elda;
5898 I915_WRITE(reg_elda, i);
5899
5900 for (i = 0; i < eld[2]; i++)
5901 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5902 return false;
5903
5904 return true;
5905}
5906
e0dac65e
WF		 5907static void g4x_write_eld(struct drm_connector *connector,
5908 struct drm_crtc *crtc)
5909{
5910 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5911 uint8_t *eld = connector->eld;
5912 uint32_t eldv;
5913 uint32_t len;
5914 uint32_t i;
5915
5916 i = I915_READ(G4X_AUD_VID_DID);
5917
5918 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5919 eldv = G4X_ELDV_DEVCL_DEVBLC;
5920 else
5921 eldv = G4X_ELDV_DEVCTG;
5922
3a9627f4
WF		 5923 if (intel_eld_uptodate(connector,
5924 G4X_AUD_CNTL_ST, eldv,
5925 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5926 G4X_HDMIW_HDMIEDID))
5927 return;
5928
e0dac65e
WF		 5929 i = I915_READ(G4X_AUD_CNTL_ST);
5930 i &= ~(eldv | G4X_ELD_ADDR);
5931 len = (i >> 9) & 0x1f; /* ELD buffer size */
5932 I915_WRITE(G4X_AUD_CNTL_ST, i);
5933
5934 if (!eld[0])
5935 return;
5936
5937 len = min_t(uint8_t, eld[2], len);
5938 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5939 for (i = 0; i < len; i++)
5940 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5941
5942 i = I915_READ(G4X_AUD_CNTL_ST);
5943 i |= eldv;
5944 I915_WRITE(G4X_AUD_CNTL_ST, i);
5945}
5946
83358c85
WX		 5947static void haswell_write_eld(struct drm_connector *connector,
5948 struct drm_crtc *crtc)
5949{
5950 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5951 uint8_t *eld = connector->eld;
5952 struct drm_device *dev = crtc->dev;
5953 uint32_t eldv;
5954 uint32_t i;
5955 int len;
5956 int pipe = to_intel_crtc(crtc)->pipe;
5957 int tmp;
5958
5959 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5960 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5961 int aud_config = HSW_AUD_CFG(pipe);
5962 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5963
5964
5965 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5966
5967 /* Audio output enable */
5968 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5969 tmp = I915_READ(aud_cntrl_st2);
5970 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5971 I915_WRITE(aud_cntrl_st2, tmp);
5972
5973 /* Wait for 1 vertical blank */
5974 intel_wait_for_vblank(dev, pipe);
5975
5976 /* Set ELD valid state */
5977 tmp = I915_READ(aud_cntrl_st2);
5978 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5979 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5980 I915_WRITE(aud_cntrl_st2, tmp);
5981 tmp = I915_READ(aud_cntrl_st2);
5982 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5983
5984 /* Enable HDMI mode */
5985 tmp = I915_READ(aud_config);
5986 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5987 /* clear N_programing_enable and N_value_index */
5988 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5989 I915_WRITE(aud_config, tmp);
5990
5991 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5992
5993 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5994
5995 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5996 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5997 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5998 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5999 } else
6000 I915_WRITE(aud_config, 0);
6001
6002 if (intel_eld_uptodate(connector,
6003 aud_cntrl_st2, eldv,
6004 aud_cntl_st, IBX_ELD_ADDRESS,
6005 hdmiw_hdmiedid))
6006 return;
6007
6008 i = I915_READ(aud_cntrl_st2);
6009 i &= ~eldv;
6010 I915_WRITE(aud_cntrl_st2, i);
6011
6012 if (!eld[0])
6013 return;
6014
6015 i = I915_READ(aud_cntl_st);
6016 i &= ~IBX_ELD_ADDRESS;
6017 I915_WRITE(aud_cntl_st, i);
6018 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6019 DRM_DEBUG_DRIVER("port num:%d\n", i);
6020
6021 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6022 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6023 for (i = 0; i < len; i++)
6024 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6025
6026 i = I915_READ(aud_cntrl_st2);
6027 i |= eldv;
6028 I915_WRITE(aud_cntrl_st2, i);
6029
6030}
6031
e0dac65e
WF		 6032static void ironlake_write_eld(struct drm_connector *connector,
6033 struct drm_crtc *crtc)
6034{
6035 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6036 uint8_t *eld = connector->eld;
6037 uint32_t eldv;
6038 uint32_t i;
6039 int len;
6040 int hdmiw_hdmiedid;
b6daa025 6041 int aud_config;
e0dac65e
WF		 6042 int aud_cntl_st;
6043 int aud_cntrl_st2;
9b138a83 6044 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6045
b3f33cbf 6046 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6047 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6048 aud_config = IBX_AUD_CFG(pipe);
6049 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6050 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6051 } else {
9b138a83
WX		 6052 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6053 aud_config = CPT_AUD_CFG(pipe);
6054 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6055 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6056 }
6057
9b138a83 6058 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6059
6060 i = I915_READ(aud_cntl_st);
9b138a83 6061 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6062 if (!i) {
6063 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6064 /* operate blindly on all ports */
1202b4c6
WF		 6065 eldv = IBX_ELD_VALIDB;
6066 eldv |= IBX_ELD_VALIDB << 4;
6067 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6068 } else {
6069 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6070 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6071 }
6072
3a9627f4
WF		 6073 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6074 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6075 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6076 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6077 } else
6078 I915_WRITE(aud_config, 0);
e0dac65e 6079
3a9627f4
WF		 6080 if (intel_eld_uptodate(connector,
6081 aud_cntrl_st2, eldv,
6082 aud_cntl_st, IBX_ELD_ADDRESS,
6083 hdmiw_hdmiedid))
6084 return;
6085
e0dac65e
WF		 6086 i = I915_READ(aud_cntrl_st2);
6087 i &= ~eldv;
6088 I915_WRITE(aud_cntrl_st2, i);
6089
6090 if (!eld[0])
6091 return;
6092
e0dac65e 6093 i = I915_READ(aud_cntl_st);
1202b4c6 6094 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6095 I915_WRITE(aud_cntl_st, i);
6096
6097 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6098 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6099 for (i = 0; i < len; i++)
6100 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6101
6102 i = I915_READ(aud_cntrl_st2);
6103 i |= eldv;
6104 I915_WRITE(aud_cntrl_st2, i);
6105}
6106
6107void intel_write_eld(struct drm_encoder *encoder,
6108 struct drm_display_mode *mode)
6109{
6110 struct drm_crtc *crtc = encoder->crtc;
6111 struct drm_connector *connector;
6112 struct drm_device *dev = encoder->dev;
6113 struct drm_i915_private *dev_priv = dev->dev_private;
6114
6115 connector = drm_select_eld(encoder, mode);
6116 if (!connector)
6117 return;
6118
6119 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6120 connector->base.id,
6121 drm_get_connector_name(connector),
6122 connector->encoder->base.id,
6123 drm_get_encoder_name(connector->encoder));
6124
6125 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6126
6127 if (dev_priv->display.write_eld)
6128 dev_priv->display.write_eld(connector, crtc);
6129}
6130
79e53945
JB		 6131/** Loads the palette/gamma unit for the CRTC with the prepared values */
6132void intel_crtc_load_lut(struct drm_crtc *crtc)
6133{
6134 struct drm_device *dev = crtc->dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6137 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6138 int i;
6139
6140 /* The clocks have to be on to load the palette. */
aed3f09d 6141 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6142 return;
6143
f2b115e6 6144 /* use legacy palette for Ironlake */
bad720ff 6145 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6146 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6147
79e53945
JB		 6148 for (i = 0; i < 256; i++) {
6149 I915_WRITE(palreg + 4 * i,
6150 (intel_crtc->lut_r[i] << 16) |
6151 (intel_crtc->lut_g[i] << 8) |
6152 intel_crtc->lut_b[i]);
6153 }
6154}
6155
560b85bb
CW		 6156static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6157{
6158 struct drm_device *dev = crtc->dev;
6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6161 bool visible = base != 0;
6162 u32 cntl;
6163
6164 if (intel_crtc->cursor_visible == visible)
6165 return;
6166
9db4a9c7 6167 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6168 if (visible) {
6169 /* On these chipsets we can only modify the base whilst
6170 * the cursor is disabled.
6171 */
9db4a9c7 6172 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6173
6174 cntl &= ~(CURSOR_FORMAT_MASK);
6175 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6176 cntl |= CURSOR_ENABLE |
6177 CURSOR_GAMMA_ENABLE |
6178 CURSOR_FORMAT_ARGB;
6179 } else
6180 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6181 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6182
6183 intel_crtc->cursor_visible = visible;
6184}
6185
6186static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6187{
6188 struct drm_device *dev = crtc->dev;
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191 int pipe = intel_crtc->pipe;
6192 bool visible = base != 0;
6193
6194 if (intel_crtc->cursor_visible != visible) {
548f245b 6195 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6196 if (base) {
6197 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6198 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6199 cntl |= pipe << 28; /* Connect to correct pipe */
6200 } else {
6201 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6202 cntl |= CURSOR_MODE_DISABLE;
6203 }
9db4a9c7 6204 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6205
6206 intel_crtc->cursor_visible = visible;
6207 }
6208 /* and commit changes on next vblank */
9db4a9c7 6209 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6210}
6211
65a21cd6
JB		 6212static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6213{
6214 struct drm_device *dev = crtc->dev;
6215 struct drm_i915_private *dev_priv = dev->dev_private;
6216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6217 int pipe = intel_crtc->pipe;
6218 bool visible = base != 0;
6219
6220 if (intel_crtc->cursor_visible != visible) {
6221 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6222 if (base) {
6223 cntl &= ~CURSOR_MODE;
6224 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6225 } else {
6226 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6227 cntl |= CURSOR_MODE_DISABLE;
6228 }
6229 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6230
6231 intel_crtc->cursor_visible = visible;
6232 }
6233 /* and commit changes on next vblank */
6234 I915_WRITE(CURBASE_IVB(pipe), base);
6235}
6236
cda4b7d3 6237/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6238static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6239 bool on)
cda4b7d3
CW		 6240{
6241 struct drm_device *dev = crtc->dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6244 int pipe = intel_crtc->pipe;
6245 int x = intel_crtc->cursor_x;
6246 int y = intel_crtc->cursor_y;
560b85bb 6247 u32 base, pos;
cda4b7d3
CW		 6248 bool visible;
6249
6250 pos = 0;
6251
6b383a7f 6252 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6253 base = intel_crtc->cursor_addr;
6254 if (x > (int) crtc->fb->width)
6255 base = 0;
6256
6257 if (y > (int) crtc->fb->height)
6258 base = 0;
6259 } else
6260 base = 0;
6261
6262 if (x < 0) {
6263 if (x + intel_crtc->cursor_width < 0)
6264 base = 0;
6265
6266 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6267 x = -x;
6268 }
6269 pos |= x << CURSOR_X_SHIFT;
6270
6271 if (y < 0) {
6272 if (y + intel_crtc->cursor_height < 0)
6273 base = 0;
6274
6275 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6276 y = -y;
6277 }
6278 pos |= y << CURSOR_Y_SHIFT;
6279
6280 visible = base != 0;
560b85bb 6281 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6282 return;
6283
0cd83aa9 6284 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6285 I915_WRITE(CURPOS_IVB(pipe), pos);
6286 ivb_update_cursor(crtc, base);
6287 } else {
6288 I915_WRITE(CURPOS(pipe), pos);
6289 if (IS_845G(dev) || IS_I865G(dev))
6290 i845_update_cursor(crtc, base);
6291 else
6292 i9xx_update_cursor(crtc, base);
6293 }
cda4b7d3
CW		 6294}
6295
79e53945 6296static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6297 struct drm_file *file,
79e53945
JB		 6298 uint32_t handle,
6299 uint32_t width, uint32_t height)
6300{
6301 struct drm_device *dev = crtc->dev;
6302 struct drm_i915_private *dev_priv = dev->dev_private;
6303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6304 struct drm_i915_gem_object *obj;
cda4b7d3 6305 uint32_t addr;
3f8bc370 6306 int ret;
79e53945 6307
79e53945
JB		 6308 /* if we want to turn off the cursor ignore width and height */
6309 if (!handle) {
28c97730 6310 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6311 addr = 0;
05394f39 6312 obj = NULL;
5004417d 6313 mutex_lock(&dev->struct_mutex);
3f8bc370 6314 goto finish;
79e53945
JB		 6315 }
6316
6317 /* Currently we only support 64x64 cursors */
6318 if (width != 64 || height != 64) {
6319 DRM_ERROR("we currently only support 64x64 cursors\n");
6320 return -EINVAL;
6321 }
6322
05394f39 6323 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6324 if (&obj->base == NULL)
79e53945
JB		 6325 return -ENOENT;
6326
05394f39 6327 if (obj->base.size < width * height * 4) {
79e53945 6328 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6329 ret = -ENOMEM;
6330 goto fail;
79e53945
JB		 6331 }
6332
71acb5eb 6333 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6334 mutex_lock(&dev->struct_mutex);
b295d1b6 6335 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6336 if (obj->tiling_mode) {
6337 DRM_ERROR("cursor cannot be tiled\n");
6338 ret = -EINVAL;
6339 goto fail_locked;
6340 }
6341
2da3b9b9 6342 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6343 if (ret) {
6344 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6345 goto fail_locked;
e7b526bb
CW		 6346 }
6347
d9e86c0e
CW		 6348 ret = i915_gem_object_put_fence(obj);
6349 if (ret) {
2da3b9b9 6350 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6351 goto fail_unpin;
6352 }
6353
05394f39 6354 addr = obj->gtt_offset;
71acb5eb 6355 } else {
6eeefaf3 6356 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6357 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6358 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6359 align);
71acb5eb
DA		 6360 if (ret) {
6361 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6362 goto fail_locked;
71acb5eb 6363 }
05394f39 6364 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6365 }
6366
a6c45cf0 6367 if (IS_GEN2(dev))
14b60391
JB		 6368 I915_WRITE(CURSIZE, (height << 12) | width);
6369
3f8bc370 6370 finish:
3f8bc370 6371 if (intel_crtc->cursor_bo) {
b295d1b6 6372 if (dev_priv->info->cursor_needs_physical) {
05394f39 6373 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6374 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6375 } else
6376 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6377 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6378 }
80824003 6379
7f9872e0 6380 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6381
6382 intel_crtc->cursor_addr = addr;
05394f39 6383 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6384 intel_crtc->cursor_width = width;
6385 intel_crtc->cursor_height = height;
6386
6b383a7f 6387 intel_crtc_update_cursor(crtc, true);
3f8bc370 6388
79e53945 6389 return 0;
e7b526bb 6390fail_unpin:
05394f39 6391 i915_gem_object_unpin(obj);
7f9872e0 6392fail_locked:
34b8686e 6393 mutex_unlock(&dev->struct_mutex);
bc9025bd 6394fail:
05394f39 6395 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6396 return ret;
79e53945
JB		 6397}
6398
6399static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6400{
79e53945 6401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6402
cda4b7d3
CW		 6403 intel_crtc->cursor_x = x;
6404 intel_crtc->cursor_y = y;
652c393a 6405
6b383a7f 6406 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6407
6408 return 0;
6409}
6410
6411/** Sets the color ramps on behalf of RandR */
6412void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6413 u16 blue, int regno)
6414{
6415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416
6417 intel_crtc->lut_r[regno] = red >> 8;
6418 intel_crtc->lut_g[regno] = green >> 8;
6419 intel_crtc->lut_b[regno] = blue >> 8;
6420}
6421
b8c00ac5
DA		 6422void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6423 u16 *blue, int regno)
6424{
6425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6426
6427 *red = intel_crtc->lut_r[regno] << 8;
6428 *green = intel_crtc->lut_g[regno] << 8;
6429 *blue = intel_crtc->lut_b[regno] << 8;
6430}
6431
79e53945 6432static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6433 u16 *blue, uint32_t start, uint32_t size)
79e53945 6434{
7203425a 6435 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6437
7203425a 6438 for (i = start; i < end; i++) {
79e53945
JB		 6439 intel_crtc->lut_r[i] = red[i] >> 8;
6440 intel_crtc->lut_g[i] = green[i] >> 8;
6441 intel_crtc->lut_b[i] = blue[i] >> 8;
6442 }
6443
6444 intel_crtc_load_lut(crtc);
6445}
6446
6447/**
6448 * Get a pipe with a simple mode set on it for doing load-based monitor
6449 * detection.
6450 *
6451 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6452 * its requirements. The pipe will be connected to no other encoders.
79e53945 6453 *
c751ce4f 6454 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6455 * configured for it. In the future, it could choose to temporarily disable
6456 * some outputs to free up a pipe for its use.
6457 *
6458 * \return crtc, or NULL if no pipes are available.
6459 */
6460
6461/* VESA 640x480x72Hz mode to set on the pipe */
6462static struct drm_display_mode load_detect_mode = {
6463 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6464 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6465};
6466
d2dff872
CW		 6467static struct drm_framebuffer *
6468intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6469 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6470 struct drm_i915_gem_object *obj)
6471{
6472 struct intel_framebuffer *intel_fb;
6473 int ret;
6474
6475 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6476 if (!intel_fb) {
6477 drm_gem_object_unreference_unlocked(&obj->base);
6478 return ERR_PTR(-ENOMEM);
6479 }
6480
6481 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6482 if (ret) {
6483 drm_gem_object_unreference_unlocked(&obj->base);
6484 kfree(intel_fb);
6485 return ERR_PTR(ret);
6486 }
6487
6488 return &intel_fb->base;
6489}
6490
6491static u32
6492intel_framebuffer_pitch_for_width(int width, int bpp)
6493{
6494 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6495 return ALIGN(pitch, 64);
6496}
6497
6498static u32
6499intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6500{
6501 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6502 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6503}
6504
6505static struct drm_framebuffer *
6506intel_framebuffer_create_for_mode(struct drm_device *dev,
6507 struct drm_display_mode *mode,
6508 int depth, int bpp)
6509{
6510 struct drm_i915_gem_object *obj;
308e5bcb 6511 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6512
6513 obj = i915_gem_alloc_object(dev,
6514 intel_framebuffer_size_for_mode(mode, bpp));
6515 if (obj == NULL)
6516 return ERR_PTR(-ENOMEM);
6517
6518 mode_cmd.width = mode->hdisplay;
6519 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6520 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6521 bpp);
5ca0c34a 6522 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6523
6524 return intel_framebuffer_create(dev, &mode_cmd, obj);
6525}
6526
6527static struct drm_framebuffer *
6528mode_fits_in_fbdev(struct drm_device *dev,
6529 struct drm_display_mode *mode)
6530{
6531 struct drm_i915_private *dev_priv = dev->dev_private;
6532 struct drm_i915_gem_object *obj;
6533 struct drm_framebuffer *fb;
6534
6535 if (dev_priv->fbdev == NULL)
6536 return NULL;
6537
6538 obj = dev_priv->fbdev->ifb.obj;
6539 if (obj == NULL)
6540 return NULL;
6541
6542 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6543 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6544 fb->bits_per_pixel))
d2dff872
CW		 6545 return NULL;
6546
01f2c773 6547 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6548 return NULL;
6549
6550 return fb;
6551}
6552
d2434ab7 6553bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6554 struct drm_display_mode *mode,
8261b191 6555 struct intel_load_detect_pipe *old)
79e53945
JB		 6556{
6557 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6558 struct intel_encoder *intel_encoder =
6559 intel_attached_encoder(connector);
79e53945 6560 struct drm_crtc *possible_crtc;
4ef69c7a 6561 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6562 struct drm_crtc *crtc = NULL;
6563 struct drm_device *dev = encoder->dev;
94352cf9 6564 struct drm_framebuffer *fb;
79e53945
JB		 6565 int i = -1;
6566
d2dff872
CW		 6567 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6568 connector->base.id, drm_get_connector_name(connector),
6569 encoder->base.id, drm_get_encoder_name(encoder));
6570
79e53945
JB		 6571 /*
6572 * Algorithm gets a little messy:
7a5e4805 6573 *
79e53945
JB		 6574 * - if the connector already has an assigned crtc, use it (but make
6575 * sure it's on first)
7a5e4805 6576 *
79e53945
JB		 6577 * - try to find the first unused crtc that can drive this connector,
6578 * and use that if we find one
79e53945
JB		 6579 */
6580
6581 /* See if we already have a CRTC for this connector */
6582 if (encoder->crtc) {
6583 crtc = encoder->crtc;
8261b191 6584
24218aac 6585 old->dpms_mode = connector->dpms;
8261b191
CW		 6586 old->load_detect_temp = false;
6587
6588 /* Make sure the crtc and connector are running */
24218aac
DV		 6589 if (connector->dpms != DRM_MODE_DPMS_ON)
6590 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6591
7173188d 6592 return true;
79e53945
JB		 6593 }
6594
6595 /* Find an unused one (if possible) */
6596 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6597 i++;
6598 if (!(encoder->possible_crtcs & (1 << i)))
6599 continue;
6600 if (!possible_crtc->enabled) {
6601 crtc = possible_crtc;
6602 break;
6603 }
79e53945
JB		 6604 }
6605
6606 /*
6607 * If we didn't find an unused CRTC, don't use any.
6608 */
6609 if (!crtc) {
7173188d
CW		 6610 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6611 return false;
79e53945
JB		 6612 }
6613
fc303101
DV		 6614 intel_encoder->new_crtc = to_intel_crtc(crtc);
6615 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6616
6617 intel_crtc = to_intel_crtc(crtc);
24218aac 6618 old->dpms_mode = connector->dpms;
8261b191 6619 old->load_detect_temp = true;
d2dff872 6620 old->release_fb = NULL;
79e53945 6621
6492711d
CW		 6622 if (!mode)
6623 mode = &load_detect_mode;
79e53945 6624
d2dff872
CW		 6625 /* We need a framebuffer large enough to accommodate all accesses
6626 * that the plane may generate whilst we perform load detection.
6627 * We can not rely on the fbcon either being present (we get called
6628 * during its initialisation to detect all boot displays, or it may
6629 * not even exist) or that it is large enough to satisfy the
6630 * requested mode.
6631 */
94352cf9
DV		 6632 fb = mode_fits_in_fbdev(dev, mode);
6633 if (fb == NULL) {
d2dff872 6634 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6635 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6636 old->release_fb = fb;
d2dff872
CW		 6637 } else
6638 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6639 if (IS_ERR(fb)) {
d2dff872 6640 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6641 goto fail;
79e53945 6642 }
79e53945 6643
94352cf9 6644 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6645 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6646 if (old->release_fb)
6647 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6648 goto fail;
79e53945 6649 }
7173188d 6650
79e53945 6651 /* let the connector get through one full cycle before testing */
9d0498a2 6652 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6653
7173188d 6654 return true;
24218aac
DV		 6655fail:
6656 connector->encoder = NULL;
6657 encoder->crtc = NULL;
24218aac 6658 return false;
79e53945
JB		 6659}
6660
d2434ab7 6661void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6662 struct intel_load_detect_pipe *old)
79e53945 6663{
d2434ab7
DV		 6664 struct intel_encoder *intel_encoder =
6665 intel_attached_encoder(connector);
4ef69c7a 6666 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6667
d2dff872
CW		 6668 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6669 connector->base.id, drm_get_connector_name(connector),
6670 encoder->base.id, drm_get_encoder_name(encoder));
6671
8261b191 6672 if (old->load_detect_temp) {
fc303101
DV		 6673 struct drm_crtc *crtc = encoder->crtc;
6674
6675 to_intel_connector(connector)->new_encoder = NULL;
6676 intel_encoder->new_crtc = NULL;
6677 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6678
6679 if (old->release_fb)
6680 old->release_fb->funcs->destroy(old->release_fb);
6681
0622a53c 6682 return;
79e53945
JB		 6683 }
6684
c751ce4f 6685 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6686 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6687 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6688}
6689
6690/* Returns the clock of the currently programmed mode of the given pipe. */
6691static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6692{
6693 struct drm_i915_private *dev_priv = dev->dev_private;
6694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6695 int pipe = intel_crtc->pipe;
548f245b 6696 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6697 u32 fp;
6698 intel_clock_t clock;
6699
6700 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6701 fp = I915_READ(FP0(pipe));
79e53945 6702 else
39adb7a5 6703 fp = I915_READ(FP1(pipe));
79e53945
JB		 6704
6705 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6706 if (IS_PINEVIEW(dev)) {
6707 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6708 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6709 } else {
6710 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6711 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6712 }
6713
a6c45cf0 6714 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6715 if (IS_PINEVIEW(dev))
6716 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6717 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6718 else
6719 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6720 DPLL_FPA01_P1_POST_DIV_SHIFT);
6721
6722 switch (dpll & DPLL_MODE_MASK) {
6723 case DPLLB_MODE_DAC_SERIAL:
6724 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6725 5 : 10;
6726 break;
6727 case DPLLB_MODE_LVDS:
6728 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6729 7 : 14;
6730 break;
6731 default:
28c97730 6732 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6733 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6734 return 0;
6735 }
6736
6737 /* XXX: Handle the 100Mhz refclk */
2177832f 6738 intel_clock(dev, 96000, &clock);
79e53945
JB		 6739 } else {
6740 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6741
6742 if (is_lvds) {
6743 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6744 DPLL_FPA01_P1_POST_DIV_SHIFT);
6745 clock.p2 = 14;
6746
6747 if ((dpll & PLL_REF_INPUT_MASK) ==
6748 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6749 /* XXX: might not be 66MHz */
2177832f 6750 intel_clock(dev, 66000, &clock);
79e53945 6751 } else
2177832f 6752 intel_clock(dev, 48000, &clock);
79e53945
JB		 6753 } else {
6754 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6755 clock.p1 = 2;
6756 else {
6757 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6758 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6759 }
6760 if (dpll & PLL_P2_DIVIDE_BY_4)
6761 clock.p2 = 4;
6762 else
6763 clock.p2 = 2;
6764
2177832f 6765 intel_clock(dev, 48000, &clock);
79e53945
JB		 6766 }
6767 }
6768
6769 /* XXX: It would be nice to validate the clocks, but we can't reuse
6770 * i830PllIsValid() because it relies on the xf86_config connector
6771 * configuration being accurate, which it isn't necessarily.
6772 */
6773
6774 return clock.dot;
6775}
6776
6777/** Returns the currently programmed mode of the given pipe. */
6778struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6779 struct drm_crtc *crtc)
6780{
548f245b 6781 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6783 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6784 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6785 int htot = I915_READ(HTOTAL(cpu_transcoder));
6786 int hsync = I915_READ(HSYNC(cpu_transcoder));
6787 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6788 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6789
6790 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6791 if (!mode)
6792 return NULL;
6793
6794 mode->clock = intel_crtc_clock_get(dev, crtc);
6795 mode->hdisplay = (htot & 0xffff) + 1;
6796 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6797 mode->hsync_start = (hsync & 0xffff) + 1;
6798 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6799 mode->vdisplay = (vtot & 0xffff) + 1;
6800 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6801 mode->vsync_start = (vsync & 0xffff) + 1;
6802 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6803
6804 drm_mode_set_name(mode);
79e53945
JB		 6805
6806 return mode;
6807}
6808
3dec0095 6809static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6810{
6811 struct drm_device *dev = crtc->dev;
6812 drm_i915_private_t *dev_priv = dev->dev_private;
6813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6815 int dpll_reg = DPLL(pipe);
6816 int dpll;
652c393a 6817
bad720ff 6818 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6819 return;
6820
6821 if (!dev_priv->lvds_downclock_avail)
6822 return;
6823
dbdc6479 6824 dpll = I915_READ(dpll_reg);
652c393a 6825 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6826 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6827
8ac5a6d5 6828 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6829
6830 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6831 I915_WRITE(dpll_reg, dpll);
9d0498a2 6832 intel_wait_for_vblank(dev, pipe);
dbdc6479 6833
652c393a
JB		 6834 dpll = I915_READ(dpll_reg);
6835 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6836 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6837 }
652c393a
JB		 6838}
6839
6840static void intel_decrease_pllclock(struct drm_crtc *crtc)
6841{
6842 struct drm_device *dev = crtc->dev;
6843 drm_i915_private_t *dev_priv = dev->dev_private;
6844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6845
bad720ff 6846 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6847 return;
6848
6849 if (!dev_priv->lvds_downclock_avail)
6850 return;
6851
6852 /*
6853 * Since this is called by a timer, we should never get here in
6854 * the manual case.
6855 */
6856 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6857 int pipe = intel_crtc->pipe;
6858 int dpll_reg = DPLL(pipe);
6859 int dpll;
f6e5b160 6860
44d98a61 6861 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6862
8ac5a6d5 6863 assert_panel_unlocked(dev_priv, pipe);
652c393a 6864
dc257cf1 6865 dpll = I915_READ(dpll_reg);
652c393a
JB		 6866 dpll |= DISPLAY_RATE_SELECT_FPA1;
6867 I915_WRITE(dpll_reg, dpll);
9d0498a2 6868 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6869 dpll = I915_READ(dpll_reg);
6870 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6871 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6872 }
6873
6874}
6875
f047e395
CW		 6876void intel_mark_busy(struct drm_device *dev)
6877{
f047e395
CW		 6878 i915_update_gfx_val(dev->dev_private);
6879}
6880
6881void intel_mark_idle(struct drm_device *dev)
652c393a 6882{
f047e395
CW		 6883}
6884
6885void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6886{
6887 struct drm_device *dev = obj->base.dev;
652c393a 6888 struct drm_crtc *crtc;
652c393a
JB		 6889
6890 if (!i915_powersave)
6891 return;
6892
652c393a 6893 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6894 if (!crtc->fb)
6895 continue;
6896
f047e395
CW		 6897 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6898 intel_increase_pllclock(crtc);
652c393a 6899 }
652c393a
JB		 6900}
6901
f047e395 6902void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6903{
f047e395
CW		 6904 struct drm_device *dev = obj->base.dev;
6905 struct drm_crtc *crtc;
652c393a 6906
f047e395 6907 if (!i915_powersave)
acb87dfb
CW		 6908 return;
6909
652c393a
JB		 6910 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6911 if (!crtc->fb)
6912 continue;
6913
f047e395
CW		 6914 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6915 intel_decrease_pllclock(crtc);
652c393a
JB		 6916 }
6917}
6918
79e53945
JB		 6919static void intel_crtc_destroy(struct drm_crtc *crtc)
6920{
6921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6922 struct drm_device *dev = crtc->dev;
6923 struct intel_unpin_work *work;
6924 unsigned long flags;
6925
6926 spin_lock_irqsave(&dev->event_lock, flags);
6927 work = intel_crtc->unpin_work;
6928 intel_crtc->unpin_work = NULL;
6929 spin_unlock_irqrestore(&dev->event_lock, flags);
6930
6931 if (work) {
6932 cancel_work_sync(&work->work);
6933 kfree(work);
6934 }
79e53945
JB		 6935
6936 drm_crtc_cleanup(crtc);
67e77c5a 6937
79e53945
JB		 6938 kfree(intel_crtc);
6939}
6940
6b95a207
KH		 6941static void intel_unpin_work_fn(struct work_struct *__work)
6942{
6943 struct intel_unpin_work *work =
6944 container_of(__work, struct intel_unpin_work, work);
6945
6946 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6947 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6948 drm_gem_object_unreference(&work->pending_flip_obj->base);
6949 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6950
7782de3b 6951 intel_update_fbc(work->dev);
6b95a207
KH		 6952 mutex_unlock(&work->dev->struct_mutex);
6953 kfree(work);
6954}
6955
1afe3e9d 6956static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6957 struct drm_crtc *crtc)
6b95a207
KH		 6958{
6959 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6961 struct intel_unpin_work *work;
05394f39 6962 struct drm_i915_gem_object *obj;
6b95a207 6963 struct drm_pending_vblank_event *e;
95cb1b02 6964 struct timeval tvbl;
6b95a207
KH		 6965 unsigned long flags;
6966
6967 /* Ignore early vblank irqs */
6968 if (intel_crtc == NULL)
6969 return;
6970
6971 spin_lock_irqsave(&dev->event_lock, flags);
6972 work = intel_crtc->unpin_work;
6973 if (work == NULL || !work->pending) {
6974 spin_unlock_irqrestore(&dev->event_lock, flags);
6975 return;
6976 }
6977
6978 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6979
6980 if (work->event) {
6981 e = work->event;
49b14a5c 6982 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6983
49b14a5c
MK		 6984 e->event.tv_sec = tvbl.tv_sec;
6985 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6986
6b95a207
KH		 6987 list_add_tail(&e->base.link,
6988 &e->base.file_priv->event_list);
6989 wake_up_interruptible(&e->base.file_priv->event_wait);
6990 }
6991
0af7e4df
MK		 6992 drm_vblank_put(dev, intel_crtc->pipe);
6993
6b95a207
KH		 6994 spin_unlock_irqrestore(&dev->event_lock, flags);
6995
05394f39 6996 obj = work->old_fb_obj;
d9e86c0e 6997
e59f2bac 6998 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6999 &obj->pending_flip.counter);
d9e86c0e 7000
5bb61643 7001 wake_up(&dev_priv->pending_flip_queue);
6b95a207 7002 schedule_work(&work->work);
e5510fac
JB		 7003
7004 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7005}
7006
1afe3e9d
JB		 7007void intel_finish_page_flip(struct drm_device *dev, int pipe)
7008{
7009 drm_i915_private_t *dev_priv = dev->dev_private;
7010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7011
49b14a5c 7012 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7013}
7014
7015void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7016{
7017 drm_i915_private_t *dev_priv = dev->dev_private;
7018 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7019
49b14a5c 7020 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7021}
7022
6b95a207
KH		 7023void intel_prepare_page_flip(struct drm_device *dev, int plane)
7024{
7025 drm_i915_private_t *dev_priv = dev->dev_private;
7026 struct intel_crtc *intel_crtc =
7027 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7028 unsigned long flags;
7029
7030 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7031 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7032 if ((++intel_crtc->unpin_work->pending) > 1)
7033 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7034 } else {
7035 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7036 }
6b95a207
KH		 7037 spin_unlock_irqrestore(&dev->event_lock, flags);
7038}
7039
8c9f3aaf
JB		 7040static int intel_gen2_queue_flip(struct drm_device *dev,
7041 struct drm_crtc *crtc,
7042 struct drm_framebuffer *fb,
7043 struct drm_i915_gem_object *obj)
7044{
7045 struct drm_i915_private *dev_priv = dev->dev_private;
7046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7047 u32 flip_mask;
6d90c952 7048 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7049 int ret;
7050
6d90c952 7051 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7052 if (ret)
83d4092b 7053 goto err;
8c9f3aaf 7054
6d90c952 7055 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7056 if (ret)
83d4092b 7057 goto err_unpin;
8c9f3aaf
JB		 7058
7059 /* Can't queue multiple flips, so wait for the previous
7060 * one to finish before executing the next.
7061 */
7062 if (intel_crtc->plane)
7063 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7064 else
7065 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7066 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7067 intel_ring_emit(ring, MI_NOOP);
7068 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7069 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7070 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7071 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7072 intel_ring_emit(ring, 0); /* aux display base address, unused */
7073 intel_ring_advance(ring);
83d4092b
CW		 7074 return 0;
7075
7076err_unpin:
7077 intel_unpin_fb_obj(obj);
7078err:
8c9f3aaf
JB		 7079 return ret;
7080}
7081
7082static int intel_gen3_queue_flip(struct drm_device *dev,
7083 struct drm_crtc *crtc,
7084 struct drm_framebuffer *fb,
7085 struct drm_i915_gem_object *obj)
7086{
7087 struct drm_i915_private *dev_priv = dev->dev_private;
7088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7089 u32 flip_mask;
6d90c952 7090 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7091 int ret;
7092
6d90c952 7093 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7094 if (ret)
83d4092b 7095 goto err;
8c9f3aaf 7096
6d90c952 7097 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7098 if (ret)
83d4092b 7099 goto err_unpin;
8c9f3aaf
JB		 7100
7101 if (intel_crtc->plane)
7102 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7103 else
7104 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7105 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7106 intel_ring_emit(ring, MI_NOOP);
7107 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7109 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7110 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7111 intel_ring_emit(ring, MI_NOOP);
7112
7113 intel_ring_advance(ring);
83d4092b
CW		 7114 return 0;
7115
7116err_unpin:
7117 intel_unpin_fb_obj(obj);
7118err:
8c9f3aaf
JB		 7119 return ret;
7120}
7121
7122static int intel_gen4_queue_flip(struct drm_device *dev,
7123 struct drm_crtc *crtc,
7124 struct drm_framebuffer *fb,
7125 struct drm_i915_gem_object *obj)
7126{
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7129 uint32_t pf, pipesrc;
6d90c952 7130 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7131 int ret;
7132
6d90c952 7133 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7134 if (ret)
83d4092b 7135 goto err;
8c9f3aaf 7136
6d90c952 7137 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7138 if (ret)
83d4092b 7139 goto err_unpin;
8c9f3aaf
JB		 7140
7141 /* i965+ uses the linear or tiled offsets from the
7142 * Display Registers (which do not change across a page-flip)
7143 * so we need only reprogram the base address.
7144 */
6d90c952
DV		 7145 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7146 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7147 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7148 intel_ring_emit(ring,
7149 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7150 obj->tiling_mode);
8c9f3aaf
JB		 7151
7152 /* XXX Enabling the panel-fitter across page-flip is so far
7153 * untested on non-native modes, so ignore it for now.
7154 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7155 */
7156 pf = 0;
7157 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7158 intel_ring_emit(ring, pf | pipesrc);
7159 intel_ring_advance(ring);
83d4092b
CW		 7160 return 0;
7161
7162err_unpin:
7163 intel_unpin_fb_obj(obj);
7164err:
8c9f3aaf
JB		 7165 return ret;
7166}
7167
7168static int intel_gen6_queue_flip(struct drm_device *dev,
7169 struct drm_crtc *crtc,
7170 struct drm_framebuffer *fb,
7171 struct drm_i915_gem_object *obj)
7172{
7173 struct drm_i915_private *dev_priv = dev->dev_private;
7174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7175 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7176 uint32_t pf, pipesrc;
7177 int ret;
7178
6d90c952 7179 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7180 if (ret)
83d4092b 7181 goto err;
8c9f3aaf 7182
6d90c952 7183 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7184 if (ret)
83d4092b 7185 goto err_unpin;
8c9f3aaf 7186
6d90c952
DV		 7187 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7188 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7189 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7190 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7191
dc257cf1
DV		 7192 /* Contrary to the suggestions in the documentation,
7193 * "Enable Panel Fitter" does not seem to be required when page
7194 * flipping with a non-native mode, and worse causes a normal
7195 * modeset to fail.
7196 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7197 */
7198 pf = 0;
8c9f3aaf 7199 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7200 intel_ring_emit(ring, pf | pipesrc);
7201 intel_ring_advance(ring);
83d4092b
CW		 7202 return 0;
7203
7204err_unpin:
7205 intel_unpin_fb_obj(obj);
7206err:
8c9f3aaf
JB		 7207 return ret;
7208}
7209
7c9017e5
JB		 7210/*
7211 * On gen7 we currently use the blit ring because (in early silicon at least)
7212 * the render ring doesn't give us interrpts for page flip completion, which
7213 * means clients will hang after the first flip is queued. Fortunately the
7214 * blit ring generates interrupts properly, so use it instead.
7215 */
7216static int intel_gen7_queue_flip(struct drm_device *dev,
7217 struct drm_crtc *crtc,
7218 struct drm_framebuffer *fb,
7219 struct drm_i915_gem_object *obj)
7220{
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7223 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7224 uint32_t plane_bit = 0;
7c9017e5
JB		 7225 int ret;
7226
7227 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7228 if (ret)
83d4092b 7229 goto err;
7c9017e5 7230
cb05d8de
DV		 7231 switch(intel_crtc->plane) {
7232 case PLANE_A:
7233 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7234 break;
7235 case PLANE_B:
7236 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7237 break;
7238 case PLANE_C:
7239 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7240 break;
7241 default:
7242 WARN_ONCE(1, "unknown plane in flip command\n");
7243 ret = -ENODEV;
ab3951eb 7244 goto err_unpin;
cb05d8de
DV		 7245 }
7246
7c9017e5
JB		 7247 ret = intel_ring_begin(ring, 4);
7248 if (ret)
83d4092b 7249 goto err_unpin;
7c9017e5 7250
cb05d8de 7251 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7252 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7253 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7254 intel_ring_emit(ring, (MI_NOOP));
7255 intel_ring_advance(ring);
83d4092b
CW		 7256 return 0;
7257
7258err_unpin:
7259 intel_unpin_fb_obj(obj);
7260err:
7c9017e5
JB		 7261 return ret;
7262}
7263
8c9f3aaf
JB		 7264static int intel_default_queue_flip(struct drm_device *dev,
7265 struct drm_crtc *crtc,
7266 struct drm_framebuffer *fb,
7267 struct drm_i915_gem_object *obj)
7268{
7269 return -ENODEV;
7270}
7271
6b95a207
KH		 7272static int intel_crtc_page_flip(struct drm_crtc *crtc,
7273 struct drm_framebuffer *fb,
7274 struct drm_pending_vblank_event *event)
7275{
7276 struct drm_device *dev = crtc->dev;
7277 struct drm_i915_private *dev_priv = dev->dev_private;
7278 struct intel_framebuffer *intel_fb;
05394f39 7279 struct drm_i915_gem_object *obj;
6b95a207
KH		 7280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7281 struct intel_unpin_work *work;
8c9f3aaf 7282 unsigned long flags;
52e68630 7283 int ret;
6b95a207 7284
e6a595d2
VS		 7285 /* Can't change pixel format via MI display flips. */
7286 if (fb->pixel_format != crtc->fb->pixel_format)
7287 return -EINVAL;
7288
7289 /*
7290 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7291 * Note that pitch changes could also affect these register.
7292 */
7293 if (INTEL_INFO(dev)->gen > 3 &&
7294 (fb->offsets[0] != crtc->fb->offsets[0] ||
7295 fb->pitches[0] != crtc->fb->pitches[0]))
7296 return -EINVAL;
7297
6b95a207
KH		 7298 work = kzalloc(sizeof *work, GFP_KERNEL);
7299 if (work == NULL)
7300 return -ENOMEM;
7301
6b95a207
KH		 7302 work->event = event;
7303 work->dev = crtc->dev;
7304 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7305 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7306 INIT_WORK(&work->work, intel_unpin_work_fn);
7307
7317c75e
JB		 7308 ret = drm_vblank_get(dev, intel_crtc->pipe);
7309 if (ret)
7310 goto free_work;
7311
6b95a207
KH		 7312 /* We borrow the event spin lock for protecting unpin_work */
7313 spin_lock_irqsave(&dev->event_lock, flags);
7314 if (intel_crtc->unpin_work) {
7315 spin_unlock_irqrestore(&dev->event_lock, flags);
7316 kfree(work);
7317c75e 7317 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7318
7319 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7320 return -EBUSY;
7321 }
7322 intel_crtc->unpin_work = work;
7323 spin_unlock_irqrestore(&dev->event_lock, flags);
7324
7325 intel_fb = to_intel_framebuffer(fb);
7326 obj = intel_fb->obj;
7327
79158103
CW		 7328 ret = i915_mutex_lock_interruptible(dev);
7329 if (ret)
7330 goto cleanup;
6b95a207 7331
75dfca80 7332 /* Reference the objects for the scheduled work. */
05394f39
CW		 7333 drm_gem_object_reference(&work->old_fb_obj->base);
7334 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7335
7336 crtc->fb = fb;
96b099fd 7337
e1f99ce6 7338 work->pending_flip_obj = obj;
e1f99ce6 7339
4e5359cd
SF		 7340 work->enable_stall_check = true;
7341
e1f99ce6
CW		 7342 /* Block clients from rendering to the new back buffer until
7343 * the flip occurs and the object is no longer visible.
7344 */
05394f39 7345 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7346
8c9f3aaf
JB		 7347 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7348 if (ret)
7349 goto cleanup_pending;
6b95a207 7350
7782de3b 7351 intel_disable_fbc(dev);
f047e395 7352 intel_mark_fb_busy(obj);
6b95a207
KH		 7353 mutex_unlock(&dev->struct_mutex);
7354
e5510fac
JB		 7355 trace_i915_flip_request(intel_crtc->plane, obj);
7356
6b95a207 7357 return 0;
96b099fd 7358
8c9f3aaf
JB		 7359cleanup_pending:
7360 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7361 drm_gem_object_unreference(&work->old_fb_obj->base);
7362 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7363 mutex_unlock(&dev->struct_mutex);
7364
79158103 7365cleanup:
96b099fd
CW		 7366 spin_lock_irqsave(&dev->event_lock, flags);
7367 intel_crtc->unpin_work = NULL;
7368 spin_unlock_irqrestore(&dev->event_lock, flags);
7369
7317c75e
JB		 7370 drm_vblank_put(dev, intel_crtc->pipe);
7371free_work:
96b099fd
CW		 7372 kfree(work);
7373
7374 return ret;
6b95a207
KH		 7375}
7376
f6e5b160 7377static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7378 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7379 .load_lut = intel_crtc_load_lut,
976f8a20 7380 .disable = intel_crtc_noop,
f6e5b160
CW		 7381};
7382
6ed0f796 7383bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7384{
6ed0f796
DV		 7385 struct intel_encoder *other_encoder;
7386 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7387
6ed0f796
DV		 7388 if (WARN_ON(!crtc))
7389 return false;
7390
7391 list_for_each_entry(other_encoder,
7392 &crtc->dev->mode_config.encoder_list,
7393 base.head) {
7394
7395 if (&other_encoder->new_crtc->base != crtc ||
7396 encoder == other_encoder)
7397 continue;
7398 else
7399 return true;
f47166d2
CW		 7400 }
7401
6ed0f796
DV		 7402 return false;
7403}
47f1c6c9 7404
50f56119
DV		 7405static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7406 struct drm_crtc *crtc)
7407{
7408 struct drm_device *dev;
7409 struct drm_crtc *tmp;
7410 int crtc_mask = 1;
47f1c6c9 7411
50f56119 7412 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7413
50f56119 7414 dev = crtc->dev;
47f1c6c9 7415
50f56119
DV		 7416 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7417 if (tmp == crtc)
7418 break;
7419 crtc_mask <<= 1;
7420 }
47f1c6c9 7421
50f56119
DV		 7422 if (encoder->possible_crtcs & crtc_mask)
7423 return true;
7424 return false;
47f1c6c9 7425}
79e53945 7426
9a935856
DV		 7427/**
7428 * intel_modeset_update_staged_output_state
7429 *
7430 * Updates the staged output configuration state, e.g. after we've read out the
7431 * current hw state.
7432 */
7433static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7434{
9a935856
DV		 7435 struct intel_encoder *encoder;
7436 struct intel_connector *connector;
f6e5b160 7437
9a935856
DV		 7438 list_for_each_entry(connector, &dev->mode_config.connector_list,
7439 base.head) {
7440 connector->new_encoder =
7441 to_intel_encoder(connector->base.encoder);
7442 }
f6e5b160 7443
9a935856
DV		 7444 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7445 base.head) {
7446 encoder->new_crtc =
7447 to_intel_crtc(encoder->base.crtc);
7448 }
f6e5b160
CW		 7449}
7450
9a935856
DV		 7451/**
7452 * intel_modeset_commit_output_state
7453 *
7454 * This function copies the stage display pipe configuration to the real one.
7455 */
7456static void intel_modeset_commit_output_state(struct drm_device *dev)
7457{
7458 struct intel_encoder *encoder;
7459 struct intel_connector *connector;
f6e5b160 7460
9a935856
DV		 7461 list_for_each_entry(connector, &dev->mode_config.connector_list,
7462 base.head) {
7463 connector->base.encoder = &connector->new_encoder->base;
7464 }
f6e5b160 7465
9a935856
DV		 7466 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7467 base.head) {
7468 encoder->base.crtc = &encoder->new_crtc->base;
7469 }
7470}
7471
7758a113
DV		 7472static struct drm_display_mode *
7473intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7474 struct drm_display_mode *mode)
ee7b9f93 7475{
7758a113
DV		 7476 struct drm_device *dev = crtc->dev;
7477 struct drm_display_mode *adjusted_mode;
7478 struct drm_encoder_helper_funcs *encoder_funcs;
7479 struct intel_encoder *encoder;
ee7b9f93 7480
7758a113
DV		 7481 adjusted_mode = drm_mode_duplicate(dev, mode);
7482 if (!adjusted_mode)
7483 return ERR_PTR(-ENOMEM);
7484
7485 /* Pass our mode to the connectors and the CRTC to give them a chance to
7486 * adjust it according to limitations or connector properties, and also
7487 * a chance to reject the mode entirely.
7488 */
7489 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7490 base.head) {
7491
7492 if (&encoder->new_crtc->base != crtc)
7493 continue;
7494 encoder_funcs = encoder->base.helper_private;
7495 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7496 adjusted_mode))) {
7497 DRM_DEBUG_KMS("Encoder fixup failed\n");
7498 goto fail;
7499 }
ee7b9f93
JB		 7500 }
7501
7758a113
DV		 7502 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7503 DRM_DEBUG_KMS("CRTC fixup failed\n");
7504 goto fail;
ee7b9f93 7505 }
7758a113
DV		 7506 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7507
7508 return adjusted_mode;
7509fail:
7510 drm_mode_destroy(dev, adjusted_mode);
7511 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7512}
7513
e2e1ed41
DV		 7514/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7515 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7516static void
7517intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7518 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7519{
7520 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7521 struct drm_device *dev = crtc->dev;
7522 struct intel_encoder *encoder;
7523 struct intel_connector *connector;
7524 struct drm_crtc *tmp_crtc;
79e53945 7525
e2e1ed41 7526 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7527
e2e1ed41
DV		 7528 /* Check which crtcs have changed outputs connected to them, these need
7529 * to be part of the prepare_pipes mask. We don't (yet) support global
7530 * modeset across multiple crtcs, so modeset_pipes will only have one
7531 * bit set at most. */
7532 list_for_each_entry(connector, &dev->mode_config.connector_list,
7533 base.head) {
7534 if (connector->base.encoder == &connector->new_encoder->base)
7535 continue;
79e53945 7536
e2e1ed41
DV		 7537 if (connector->base.encoder) {
7538 tmp_crtc = connector->base.encoder->crtc;
7539
7540 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7541 }
7542
7543 if (connector->new_encoder)
7544 *prepare_pipes |=
7545 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7546 }
7547
e2e1ed41
DV		 7548 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7549 base.head) {
7550 if (encoder->base.crtc == &encoder->new_crtc->base)
7551 continue;
7552
7553 if (encoder->base.crtc) {
7554 tmp_crtc = encoder->base.crtc;
7555
7556 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7557 }
7558
7559 if (encoder->new_crtc)
7560 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7561 }
7562
e2e1ed41
DV		 7563 /* Check for any pipes that will be fully disabled ... */
7564 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7565 base.head) {
7566 bool used = false;
22fd0fab 7567
e2e1ed41
DV		 7568 /* Don't try to disable disabled crtcs. */
7569 if (!intel_crtc->base.enabled)
7570 continue;
7e7d76c3 7571
e2e1ed41
DV		 7572 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7573 base.head) {
7574 if (encoder->new_crtc == intel_crtc)
7575 used = true;
7576 }
7577
7578 if (!used)
7579 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7580 }
7581
e2e1ed41
DV		 7582
7583 /* set_mode is also used to update properties on life display pipes. */
7584 intel_crtc = to_intel_crtc(crtc);
7585 if (crtc->enabled)
7586 *prepare_pipes |= 1 << intel_crtc->pipe;
7587
7588 /* We only support modeset on one single crtc, hence we need to do that
7589 * only for the passed in crtc iff we change anything else than just
7590 * disable crtcs.
7591 *
7592 * This is actually not true, to be fully compatible with the old crtc
7593 * helper we automatically disable _any_ output (i.e. doesn't need to be
7594 * connected to the crtc we're modesetting on) if it's disconnected.
7595 * Which is a rather nutty api (since changed the output configuration
7596 * without userspace's explicit request can lead to confusion), but
7597 * alas. Hence we currently need to modeset on all pipes we prepare. */
7598 if (*prepare_pipes)
7599 *modeset_pipes = *prepare_pipes;
7600
7601 /* ... and mask these out. */
7602 *modeset_pipes &= ~(*disable_pipes);
7603 *prepare_pipes &= ~(*disable_pipes);
7604}
7605
ea9d758d
DV		 7606static bool intel_crtc_in_use(struct drm_crtc *crtc)
7607{
7608 struct drm_encoder *encoder;
7609 struct drm_device *dev = crtc->dev;
7610
7611 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7612 if (encoder->crtc == crtc)
7613 return true;
7614
7615 return false;
7616}
7617
7618static void
7619intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7620{
7621 struct intel_encoder *intel_encoder;
7622 struct intel_crtc *intel_crtc;
7623 struct drm_connector *connector;
7624
7625 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7626 base.head) {
7627 if (!intel_encoder->base.crtc)
7628 continue;
7629
7630 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7631
7632 if (prepare_pipes & (1 << intel_crtc->pipe))
7633 intel_encoder->connectors_active = false;
7634 }
7635
7636 intel_modeset_commit_output_state(dev);
7637
7638 /* Update computed state. */
7639 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7640 base.head) {
7641 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7642 }
7643
7644 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7645 if (!connector->encoder || !connector->encoder->crtc)
7646 continue;
7647
7648 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7649
7650 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7651 struct drm_property *dpms_property =
7652 dev->mode_config.dpms_property;
7653
ea9d758d 7654 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7655 drm_connector_property_set_value(connector,
7656 dpms_property,
7657 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7658
7659 intel_encoder = to_intel_encoder(connector->encoder);
7660 intel_encoder->connectors_active = true;
7661 }
7662 }
7663
7664}
7665
25c5b266
DV		 7666#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7667 list_for_each_entry((intel_crtc), \
7668 &(dev)->mode_config.crtc_list, \
7669 base.head) \
7670 if (mask & (1 <<(intel_crtc)->pipe)) \
7671
b980514c 7672void
8af6cf88
DV		 7673intel_modeset_check_state(struct drm_device *dev)
7674{
7675 struct intel_crtc *crtc;
7676 struct intel_encoder *encoder;
7677 struct intel_connector *connector;
7678
7679 list_for_each_entry(connector, &dev->mode_config.connector_list,
7680 base.head) {
7681 /* This also checks the encoder/connector hw state with the
7682 * ->get_hw_state callbacks. */
7683 intel_connector_check_state(connector);
7684
7685 WARN(&connector->new_encoder->base != connector->base.encoder,
7686 "connector's staged encoder doesn't match current encoder\n");
7687 }
7688
7689 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7690 base.head) {
7691 bool enabled = false;
7692 bool active = false;
7693 enum pipe pipe, tracked_pipe;
7694
7695 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7696 encoder->base.base.id,
7697 drm_get_encoder_name(&encoder->base));
7698
7699 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7700 "encoder's stage crtc doesn't match current crtc\n");
7701 WARN(encoder->connectors_active && !encoder->base.crtc,
7702 "encoder's active_connectors set, but no crtc\n");
7703
7704 list_for_each_entry(connector, &dev->mode_config.connector_list,
7705 base.head) {
7706 if (connector->base.encoder != &encoder->base)
7707 continue;
7708 enabled = true;
7709 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7710 active = true;
7711 }
7712 WARN(!!encoder->base.crtc != enabled,
7713 "encoder's enabled state mismatch "
7714 "(expected %i, found %i)\n",
7715 !!encoder->base.crtc, enabled);
7716 WARN(active && !encoder->base.crtc,
7717 "active encoder with no crtc\n");
7718
7719 WARN(encoder->connectors_active != active,
7720 "encoder's computed active state doesn't match tracked active state "
7721 "(expected %i, found %i)\n", active, encoder->connectors_active);
7722
7723 active = encoder->get_hw_state(encoder, &pipe);
7724 WARN(active != encoder->connectors_active,
7725 "encoder's hw state doesn't match sw tracking "
7726 "(expected %i, found %i)\n",
7727 encoder->connectors_active, active);
7728
7729 if (!encoder->base.crtc)
7730 continue;
7731
7732 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7733 WARN(active && pipe != tracked_pipe,
7734 "active encoder's pipe doesn't match"
7735 "(expected %i, found %i)\n",
7736 tracked_pipe, pipe);
7737
7738 }
7739
7740 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7741 base.head) {
7742 bool enabled = false;
7743 bool active = false;
7744
7745 DRM_DEBUG_KMS("[CRTC:%d]\n",
7746 crtc->base.base.id);
7747
7748 WARN(crtc->active && !crtc->base.enabled,
7749 "active crtc, but not enabled in sw tracking\n");
7750
7751 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7752 base.head) {
7753 if (encoder->base.crtc != &crtc->base)
7754 continue;
7755 enabled = true;
7756 if (encoder->connectors_active)
7757 active = true;
7758 }
7759 WARN(active != crtc->active,
7760 "crtc's computed active state doesn't match tracked active state "
7761 "(expected %i, found %i)\n", active, crtc->active);
7762 WARN(enabled != crtc->base.enabled,
7763 "crtc's computed enabled state doesn't match tracked enabled state "
7764 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7765
7766 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7767 }
7768}
7769
a6778b3c
DV		 7770bool intel_set_mode(struct drm_crtc *crtc,
7771 struct drm_display_mode *mode,
94352cf9 7772 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7773{
7774 struct drm_device *dev = crtc->dev;
dbf2b54e 7775 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7776 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7777 struct intel_crtc *intel_crtc;
7778 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7779 bool ret = true;
7780
e2e1ed41 7781 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7782 &prepare_pipes, &disable_pipes);
7783
7784 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7785 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7786
976f8a20
DV		 7787 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7788 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7789
a6778b3c
DV		 7790 saved_hwmode = crtc->hwmode;
7791 saved_mode = crtc->mode;
a6778b3c 7792
25c5b266
DV		 7793 /* Hack: Because we don't (yet) support global modeset on multiple
7794 * crtcs, we don't keep track of the new mode for more than one crtc.
7795 * Hence simply check whether any bit is set in modeset_pipes in all the
7796 * pieces of code that are not yet converted to deal with mutliple crtcs
7797 * changing their mode at the same time. */
7798 adjusted_mode = NULL;
7799 if (modeset_pipes) {
7800 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7801 if (IS_ERR(adjusted_mode)) {
7802 return false;
7803 }
25c5b266 7804 }
a6778b3c 7805
ea9d758d
DV		 7806 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7807 if (intel_crtc->base.enabled)
7808 dev_priv->display.crtc_disable(&intel_crtc->base);
7809 }
a6778b3c 7810
6c4c86f5
DV		 7811 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7812 * to set it here already despite that we pass it down the callchain.
7813 */
7814 if (modeset_pipes)
25c5b266 7815 crtc->mode = *mode;
7758a113 7816
ea9d758d
DV		 7817 /* Only after disabling all output pipelines that will be changed can we
7818 * update the the output configuration. */
7819 intel_modeset_update_state(dev, prepare_pipes);
7820
47fab737
DV		 7821 if (dev_priv->display.modeset_global_resources)
7822 dev_priv->display.modeset_global_resources(dev);
7823
a6778b3c
DV		 7824 /* Set up the DPLL and any encoders state that needs to adjust or depend
7825 * on the DPLL.
7826 */
25c5b266
DV		 7827 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7828 ret = !intel_crtc_mode_set(&intel_crtc->base,
7829 mode, adjusted_mode,
7830 x, y, fb);
7831 if (!ret)
7832 goto done;
a6778b3c
DV		 7833 }
7834
7835 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7836 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7837 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7838
25c5b266
DV		 7839 if (modeset_pipes) {
7840 /* Store real post-adjustment hardware mode. */
7841 crtc->hwmode = *adjusted_mode;
a6778b3c 7842
25c5b266
DV		 7843 /* Calculate and store various constants which
7844 * are later needed by vblank and swap-completion
7845 * timestamping. They are derived from true hwmode.
7846 */
7847 drm_calc_timestamping_constants(crtc);
7848 }
a6778b3c
DV		 7849
7850 /* FIXME: add subpixel order */
7851done:
7852 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7853 if (!ret && crtc->enabled) {
a6778b3c
DV		 7854 crtc->hwmode = saved_hwmode;
7855 crtc->mode = saved_mode;
8af6cf88
DV		 7856 } else {
7857 intel_modeset_check_state(dev);
a6778b3c
DV		 7858 }
7859
7860 return ret;
7861}
7862
25c5b266
DV		 7863#undef for_each_intel_crtc_masked
7864
d9e55608
DV		 7865static void intel_set_config_free(struct intel_set_config *config)
7866{
7867 if (!config)
7868 return;
7869
1aa4b628
DV		 7870 kfree(config->save_connector_encoders);
7871 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7872 kfree(config);
7873}
7874
85f9eb71
DV		 7875static int intel_set_config_save_state(struct drm_device *dev,
7876 struct intel_set_config *config)
7877{
85f9eb71
DV		 7878 struct drm_encoder *encoder;
7879 struct drm_connector *connector;
7880 int count;
7881
1aa4b628
DV		 7882 config->save_encoder_crtcs =
7883 kcalloc(dev->mode_config.num_encoder,
7884 sizeof(struct drm_crtc *), GFP_KERNEL);
7885 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7886 return -ENOMEM;
7887
1aa4b628
DV		 7888 config->save_connector_encoders =
7889 kcalloc(dev->mode_config.num_connector,
7890 sizeof(struct drm_encoder *), GFP_KERNEL);
7891 if (!config->save_connector_encoders)
85f9eb71
DV		 7892 return -ENOMEM;
7893
7894 /* Copy data. Note that driver private data is not affected.
7895 * Should anything bad happen only the expected state is
7896 * restored, not the drivers personal bookkeeping.
7897 */
85f9eb71
DV		 7898 count = 0;
7899 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7900 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7901 }
7902
7903 count = 0;
7904 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7905 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7906 }
7907
7908 return 0;
7909}
7910
7911static void intel_set_config_restore_state(struct drm_device *dev,
7912 struct intel_set_config *config)
7913{
9a935856
DV		 7914 struct intel_encoder *encoder;
7915 struct intel_connector *connector;
85f9eb71
DV		 7916 int count;
7917
85f9eb71 7918 count = 0;
9a935856
DV		 7919 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7920 encoder->new_crtc =
7921 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7922 }
7923
7924 count = 0;
9a935856
DV		 7925 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7926 connector->new_encoder =
7927 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7928 }
7929}
7930
5e2b584e
DV		 7931static void
7932intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7933 struct intel_set_config *config)
7934{
7935
7936 /* We should be able to check here if the fb has the same properties
7937 * and then just flip_or_move it */
7938 if (set->crtc->fb != set->fb) {
7939 /* If we have no fb then treat it as a full mode set */
7940 if (set->crtc->fb == NULL) {
7941 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7942 config->mode_changed = true;
7943 } else if (set->fb == NULL) {
7944 config->mode_changed = true;
7945 } else if (set->fb->depth != set->crtc->fb->depth) {
7946 config->mode_changed = true;
7947 } else if (set->fb->bits_per_pixel !=
7948 set->crtc->fb->bits_per_pixel) {
7949 config->mode_changed = true;
7950 } else
7951 config->fb_changed = true;
7952 }
7953
835c5873 7954 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7955 config->fb_changed = true;
7956
7957 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7958 DRM_DEBUG_KMS("modes are different, full mode set\n");
7959 drm_mode_debug_printmodeline(&set->crtc->mode);
7960 drm_mode_debug_printmodeline(set->mode);
7961 config->mode_changed = true;
7962 }
7963}
7964
2e431051 7965static int
9a935856
DV		 7966intel_modeset_stage_output_state(struct drm_device *dev,
7967 struct drm_mode_set *set,
7968 struct intel_set_config *config)
50f56119 7969{
85f9eb71 7970 struct drm_crtc *new_crtc;
9a935856
DV		 7971 struct intel_connector *connector;
7972 struct intel_encoder *encoder;
2e431051 7973 int count, ro;
50f56119 7974
9a935856
DV		 7975 /* The upper layers ensure that we either disabl a crtc or have a list
7976 * of connectors. For paranoia, double-check this. */
7977 WARN_ON(!set->fb && (set->num_connectors != 0));
7978 WARN_ON(set->fb && (set->num_connectors == 0));
7979
50f56119 7980 count = 0;
9a935856
DV		 7981 list_for_each_entry(connector, &dev->mode_config.connector_list,
7982 base.head) {
7983 /* Otherwise traverse passed in connector list and get encoders
7984 * for them. */
50f56119 7985 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7986 if (set->connectors[ro] == &connector->base) {
7987 connector->new_encoder = connector->encoder;
50f56119
DV		 7988 break;
7989 }
7990 }
7991
9a935856
DV		 7992 /* If we disable the crtc, disable all its connectors. Also, if
7993 * the connector is on the changing crtc but not on the new
7994 * connector list, disable it. */
7995 if ((!set->fb || ro == set->num_connectors) &&
7996 connector->base.encoder &&
7997 connector->base.encoder->crtc == set->crtc) {
7998 connector->new_encoder = NULL;
7999
8000 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8001 connector->base.base.id,
8002 drm_get_connector_name(&connector->base));
8003 }
8004
8005
8006 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8007 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8008 config->mode_changed = true;
50f56119 8009 }
9a935856
DV		 8010
8011 /* Disable all disconnected encoders. */
8012 if (connector->base.status == connector_status_disconnected)
8013 connector->new_encoder = NULL;
50f56119 8014 }
9a935856 8015 /* connector->new_encoder is now updated for all connectors. */
50f56119 8016
9a935856 8017 /* Update crtc of enabled connectors. */
50f56119 8018 count = 0;
9a935856
DV		 8019 list_for_each_entry(connector, &dev->mode_config.connector_list,
8020 base.head) {
8021 if (!connector->new_encoder)
50f56119
DV		 8022 continue;
8023
9a935856 8024 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8025
8026 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8027 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8028 new_crtc = set->crtc;
8029 }
8030
8031 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8032 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8033 new_crtc)) {
5e2b584e 8034 return -EINVAL;
50f56119 8035 }
9a935856
DV		 8036 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8037
8038 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8039 connector->base.base.id,
8040 drm_get_connector_name(&connector->base),
8041 new_crtc->base.id);
8042 }
8043
8044 /* Check for any encoders that needs to be disabled. */
8045 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8046 base.head) {
8047 list_for_each_entry(connector,
8048 &dev->mode_config.connector_list,
8049 base.head) {
8050 if (connector->new_encoder == encoder) {
8051 WARN_ON(!connector->new_encoder->new_crtc);
8052
8053 goto next_encoder;
8054 }
8055 }
8056 encoder->new_crtc = NULL;
8057next_encoder:
8058 /* Only now check for crtc changes so we don't miss encoders
8059 * that will be disabled. */
8060 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8061 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8062 config->mode_changed = true;
50f56119
DV		 8063 }
8064 }
9a935856 8065 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8066
2e431051
DV		 8067 return 0;
8068}
8069
8070static int intel_crtc_set_config(struct drm_mode_set *set)
8071{
8072 struct drm_device *dev;
2e431051
DV		 8073 struct drm_mode_set save_set;
8074 struct intel_set_config *config;
8075 int ret;
2e431051 8076
8d3e375e
DV		 8077 BUG_ON(!set);
8078 BUG_ON(!set->crtc);
8079 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8080
8081 if (!set->mode)
8082 set->fb = NULL;
8083
431e50f7
DV		 8084 /* The fb helper likes to play gross jokes with ->mode_set_config.
8085 * Unfortunately the crtc helper doesn't do much at all for this case,
8086 * so we have to cope with this madness until the fb helper is fixed up. */
8087 if (set->fb && set->num_connectors == 0)
8088 return 0;
8089
2e431051
DV		 8090 if (set->fb) {
8091 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8092 set->crtc->base.id, set->fb->base.id,
8093 (int)set->num_connectors, set->x, set->y);
8094 } else {
8095 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8096 }
8097
8098 dev = set->crtc->dev;
8099
8100 ret = -ENOMEM;
8101 config = kzalloc(sizeof(*config), GFP_KERNEL);
8102 if (!config)
8103 goto out_config;
8104
8105 ret = intel_set_config_save_state(dev, config);
8106 if (ret)
8107 goto out_config;
8108
8109 save_set.crtc = set->crtc;
8110 save_set.mode = &set->crtc->mode;
8111 save_set.x = set->crtc->x;
8112 save_set.y = set->crtc->y;
8113 save_set.fb = set->crtc->fb;
8114
8115 /* Compute whether we need a full modeset, only an fb base update or no
8116 * change at all. In the future we might also check whether only the
8117 * mode changed, e.g. for LVDS where we only change the panel fitter in
8118 * such cases. */
8119 intel_set_config_compute_mode_changes(set, config);
8120
9a935856 8121 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8122 if (ret)
8123 goto fail;
8124
5e2b584e 8125 if (config->mode_changed) {
87f1faa6 8126 if (set->mode) {
50f56119
DV		 8127 DRM_DEBUG_KMS("attempting to set mode from"
8128 " userspace\n");
8129 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8130 }
8131
8132 if (!intel_set_mode(set->crtc, set->mode,
8133 set->x, set->y, set->fb)) {
8134 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8135 set->crtc->base.id);
8136 ret = -EINVAL;
8137 goto fail;
8138 }
5e2b584e 8139 } else if (config->fb_changed) {
4f660f49 8140 ret = intel_pipe_set_base(set->crtc,
94352cf9 8141 set->x, set->y, set->fb);
50f56119
DV		 8142 }
8143
d9e55608
DV		 8144 intel_set_config_free(config);
8145
50f56119
DV		 8146 return 0;
8147
8148fail:
85f9eb71 8149 intel_set_config_restore_state(dev, config);
50f56119
DV		 8150
8151 /* Try to restore the config */
5e2b584e 8152 if (config->mode_changed &&
a6778b3c
DV		 8153 !intel_set_mode(save_set.crtc, save_set.mode,
8154 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8155 DRM_ERROR("failed to restore config after modeset failure\n");
8156
d9e55608
DV		 8157out_config:
8158 intel_set_config_free(config);
50f56119
DV		 8159 return ret;
8160}
8161
f6e5b160 8162static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8163 .cursor_set = intel_crtc_cursor_set,
8164 .cursor_move = intel_crtc_cursor_move,
8165 .gamma_set = intel_crtc_gamma_set,
50f56119 8166 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8167 .destroy = intel_crtc_destroy,
8168 .page_flip = intel_crtc_page_flip,
8169};
8170
79f689aa
PZ		 8171static void intel_cpu_pll_init(struct drm_device *dev)
8172{
8173 if (IS_HASWELL(dev))
8174 intel_ddi_pll_init(dev);
8175}
8176
ee7b9f93
JB		 8177static void intel_pch_pll_init(struct drm_device *dev)
8178{
8179 drm_i915_private_t *dev_priv = dev->dev_private;
8180 int i;
8181
8182 if (dev_priv->num_pch_pll == 0) {
8183 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8184 return;
8185 }
8186
8187 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8188 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8189 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8190 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8191 }
8192}
8193
b358d0a6 8194static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8195{
22fd0fab 8196 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8197 struct intel_crtc *intel_crtc;
8198 int i;
8199
8200 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8201 if (intel_crtc == NULL)
8202 return;
8203
8204 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8205
8206 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8207 for (i = 0; i < 256; i++) {
8208 intel_crtc->lut_r[i] = i;
8209 intel_crtc->lut_g[i] = i;
8210 intel_crtc->lut_b[i] = i;
8211 }
8212
80824003
JB		 8213 /* Swap pipes & planes for FBC on pre-965 */
8214 intel_crtc->pipe = pipe;
8215 intel_crtc->plane = pipe;
a5c961d1 8216 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8217 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8218 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8219 intel_crtc->plane = !pipe;
80824003
JB		 8220 }
8221
22fd0fab
JB		 8222 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8223 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8224 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8225 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8226
5a354204 8227 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8228
79e53945 8229 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8230}
8231
08d7b3d1 8232int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8233 struct drm_file *file)
08d7b3d1 8234{
08d7b3d1 8235 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8236 struct drm_mode_object *drmmode_obj;
8237 struct intel_crtc *crtc;
08d7b3d1 8238
1cff8f6b
DV		 8239 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8240 return -ENODEV;
08d7b3d1 8241
c05422d5
DV		 8242 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8243 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8244
c05422d5 8245 if (!drmmode_obj) {
08d7b3d1
CW		 8246 DRM_ERROR("no such CRTC id\n");
8247 return -EINVAL;
8248 }
8249
c05422d5
DV		 8250 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8251 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8252
c05422d5 8253 return 0;
08d7b3d1
CW		 8254}
8255
66a9278e 8256static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8257{
66a9278e
DV		 8258 struct drm_device *dev = encoder->base.dev;
8259 struct intel_encoder *source_encoder;
79e53945 8260 int index_mask = 0;
79e53945
JB		 8261 int entry = 0;
8262
66a9278e
DV		 8263 list_for_each_entry(source_encoder,
8264 &dev->mode_config.encoder_list, base.head) {
8265
8266 if (encoder == source_encoder)
79e53945 8267 index_mask |= (1 << entry);
66a9278e
DV		 8268
8269 /* Intel hw has only one MUX where enocoders could be cloned. */
8270 if (encoder->cloneable && source_encoder->cloneable)
8271 index_mask |= (1 << entry);
8272
79e53945
JB		 8273 entry++;
8274 }
4ef69c7a 8275
79e53945
JB		 8276 return index_mask;
8277}
8278
4d302442
CW		 8279static bool has_edp_a(struct drm_device *dev)
8280{
8281 struct drm_i915_private *dev_priv = dev->dev_private;
8282
8283 if (!IS_MOBILE(dev))
8284 return false;
8285
8286 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8287 return false;
8288
8289 if (IS_GEN5(dev) &&
8290 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8291 return false;
8292
8293 return true;
8294}
8295
79e53945
JB		 8296static void intel_setup_outputs(struct drm_device *dev)
8297{
725e30ad 8298 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8299 struct intel_encoder *encoder;
cb0953d7 8300 bool dpd_is_edp = false;
f3cfcba6 8301 bool has_lvds;
79e53945 8302
f3cfcba6 8303 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8304 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8305 /* disable the panel fitter on everything but LVDS */
8306 I915_WRITE(PFIT_CONTROL, 0);
8307 }
79e53945 8308
bad720ff 8309 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8310 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8311
4d302442 8312 if (has_edp_a(dev))
ab9d7c30 8313 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8314
cb0953d7 8315 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8316 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8317 }
8318
8319 intel_crt_init(dev);
8320
0e72a5b5
ED		 8321 if (IS_HASWELL(dev)) {
8322 int found;
8323
8324 /* Haswell uses DDI functions to detect digital outputs */
8325 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8326 /* DDI A only supports eDP */
8327 if (found)
8328 intel_ddi_init(dev, PORT_A);
8329
8330 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8331 * register */
8332 found = I915_READ(SFUSE_STRAP);
8333
8334 if (found & SFUSE_STRAP_DDIB_DETECTED)
8335 intel_ddi_init(dev, PORT_B);
8336 if (found & SFUSE_STRAP_DDIC_DETECTED)
8337 intel_ddi_init(dev, PORT_C);
8338 if (found & SFUSE_STRAP_DDID_DETECTED)
8339 intel_ddi_init(dev, PORT_D);
8340 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8341 int found;
8342
30ad48b7 8343 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8344 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8345 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8346 if (!found)
08d644ad 8347 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8348 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8349 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8350 }
8351
8352 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8353 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8354
b708a1d5 8355 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8356 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8357
5eb08b69 8358 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8359 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8360
cb0953d7 8361 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8362 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8363 } else if (IS_VALLEYVIEW(dev)) {
8364 int found;
8365
19c03924
GB		 8366 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8367 if (I915_READ(DP_C) & DP_DETECTED)
8368 intel_dp_init(dev, DP_C, PORT_C);
8369
4a87d65d
JB		 8370 if (I915_READ(SDVOB) & PORT_DETECTED) {
8371 /* SDVOB multiplex with HDMIB */
8372 found = intel_sdvo_init(dev, SDVOB, true);
8373 if (!found)
08d644ad 8374 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8375 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8376 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8377 }
8378
8379 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8380 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8381
103a196f 8382 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8383 bool found = false;
7d57382e 8384
725e30ad 8385 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8386 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8387 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8388 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8389 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8390 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8391 }
27185ae1 8392
b01f2c3a
JB		 8393 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8394 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8395 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8396 }
725e30ad 8397 }
13520b05
KH		 8398
8399 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8400
b01f2c3a
JB		 8401 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8402 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8403 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8404 }
27185ae1
ML		 8405
8406 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8407
b01f2c3a
JB		 8408 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8409 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8410 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8411 }
8412 if (SUPPORTS_INTEGRATED_DP(dev)) {
8413 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8414 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8415 }
725e30ad 8416 }
27185ae1 8417
b01f2c3a
JB		 8418 if (SUPPORTS_INTEGRATED_DP(dev) &&
8419 (I915_READ(DP_D) & DP_DETECTED)) {
8420 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8421 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8422 }
bad720ff 8423 } else if (IS_GEN2(dev))
79e53945
JB		 8424 intel_dvo_init(dev);
8425
103a196f 8426 if (SUPPORTS_TV(dev))
79e53945
JB		 8427 intel_tv_init(dev);
8428
4ef69c7a
CW		 8429 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8430 encoder->base.possible_crtcs = encoder->crtc_mask;
8431 encoder->base.possible_clones =
66a9278e 8432 intel_encoder_clones(encoder);
79e53945 8433 }
47356eb6 8434
40579abe 8435 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8436 ironlake_init_pch_refclk(dev);
79e53945
JB		 8437}
8438
8439static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8440{
8441 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8442
8443 drm_framebuffer_cleanup(fb);
05394f39 8444 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8445
8446 kfree(intel_fb);
8447}
8448
8449static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8450 struct drm_file *file,
79e53945
JB		 8451 unsigned int *handle)
8452{
8453 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8454 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8455
05394f39 8456 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8457}
8458
8459static const struct drm_framebuffer_funcs intel_fb_funcs = {
8460 .destroy = intel_user_framebuffer_destroy,
8461 .create_handle = intel_user_framebuffer_create_handle,
8462};
8463
38651674
DA		 8464int intel_framebuffer_init(struct drm_device *dev,
8465 struct intel_framebuffer *intel_fb,
308e5bcb 8466 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8467 struct drm_i915_gem_object *obj)
79e53945 8468{
79e53945
JB		 8469 int ret;
8470
05394f39 8471 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8472 return -EINVAL;
8473
308e5bcb 8474 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8475 return -EINVAL;
8476
5d7bd705
VS		 8477 /* FIXME <= Gen4 stride limits are bit unclear */
8478 if (mode_cmd->pitches[0] > 32768)
8479 return -EINVAL;
8480
8481 if (obj->tiling_mode != I915_TILING_NONE &&
8482 mode_cmd->pitches[0] != obj->stride)
8483 return -EINVAL;
8484
57779d06 8485 /* Reject formats not supported by any plane early. */
308e5bcb 8486 switch (mode_cmd->pixel_format) {
57779d06 8487 case DRM_FORMAT_C8:
04b3924d
VS		 8488 case DRM_FORMAT_RGB565:
8489 case DRM_FORMAT_XRGB8888:
8490 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8491 break;
8492 case DRM_FORMAT_XRGB1555:
8493 case DRM_FORMAT_ARGB1555:
8494 if (INTEL_INFO(dev)->gen > 3)
8495 return -EINVAL;
8496 break;
8497 case DRM_FORMAT_XBGR8888:
8498 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8499 case DRM_FORMAT_XRGB2101010:
8500 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8501 case DRM_FORMAT_XBGR2101010:
8502 case DRM_FORMAT_ABGR2101010:
8503 if (INTEL_INFO(dev)->gen < 4)
8504 return -EINVAL;
b5626747 8505 break;
04b3924d
VS		 8506 case DRM_FORMAT_YUYV:
8507 case DRM_FORMAT_UYVY:
8508 case DRM_FORMAT_YVYU:
8509 case DRM_FORMAT_VYUY:
57779d06
VS		 8510 if (INTEL_INFO(dev)->gen < 6)
8511 return -EINVAL;
57cd6508
CW		 8512 break;
8513 default:
57779d06 8514 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8515 return -EINVAL;
8516 }
8517
90f9a336
VS		 8518 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8519 if (mode_cmd->offsets[0] != 0)
8520 return -EINVAL;
8521
79e53945
JB		 8522 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8523 if (ret) {
8524 DRM_ERROR("framebuffer init failed %d\n", ret);
8525 return ret;
8526 }
8527
8528 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8529 intel_fb->obj = obj;
79e53945
JB		 8530 return 0;
8531}
8532
79e53945
JB		 8533static struct drm_framebuffer *
8534intel_user_framebuffer_create(struct drm_device *dev,
8535 struct drm_file *filp,
308e5bcb 8536 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8537{
05394f39 8538 struct drm_i915_gem_object *obj;
79e53945 8539
308e5bcb
JB		 8540 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8541 mode_cmd->handles[0]));
c8725226 8542 if (&obj->base == NULL)
cce13ff7 8543 return ERR_PTR(-ENOENT);
79e53945 8544
d2dff872 8545 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8546}
8547
79e53945 8548static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8549 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8550 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8551};
8552
e70236a8
JB		 8553/* Set up chip specific display functions */
8554static void intel_init_display(struct drm_device *dev)
8555{
8556 struct drm_i915_private *dev_priv = dev->dev_private;
8557
8558 /* We always want a DPMS function */
09b4ddf9
PZ		 8559 if (IS_HASWELL(dev)) {
8560 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8561 dev_priv->display.crtc_enable = haswell_crtc_enable;
8562 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8563 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8564 dev_priv->display.update_plane = ironlake_update_plane;
8565 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8566 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8567 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8568 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8569 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8570 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8571 } else {
f564048e 8572 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8573 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8574 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8575 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8576 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8577 }
e70236a8 8578
e70236a8 8579 /* Returns the core display clock speed */
25eb05fc
JB		 8580 if (IS_VALLEYVIEW(dev))
8581 dev_priv->display.get_display_clock_speed =
8582 valleyview_get_display_clock_speed;
8583 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8584 dev_priv->display.get_display_clock_speed =
8585 i945_get_display_clock_speed;
8586 else if (IS_I915G(dev))
8587 dev_priv->display.get_display_clock_speed =
8588 i915_get_display_clock_speed;
f2b115e6 8589 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8590 dev_priv->display.get_display_clock_speed =
8591 i9xx_misc_get_display_clock_speed;
8592 else if (IS_I915GM(dev))
8593 dev_priv->display.get_display_clock_speed =
8594 i915gm_get_display_clock_speed;
8595 else if (IS_I865G(dev))
8596 dev_priv->display.get_display_clock_speed =
8597 i865_get_display_clock_speed;
f0f8a9ce 8598 else if (IS_I85X(dev))
e70236a8
JB		 8599 dev_priv->display.get_display_clock_speed =
8600 i855_get_display_clock_speed;
8601 else /* 852, 830 */
8602 dev_priv->display.get_display_clock_speed =
8603 i830_get_display_clock_speed;
8604
7f8a8569 8605 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8606 if (IS_GEN5(dev)) {
674cf967 8607 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8608 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8609 } else if (IS_GEN6(dev)) {
674cf967 8610 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8611 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8612 } else if (IS_IVYBRIDGE(dev)) {
8613 /* FIXME: detect B0+ stepping and use auto training */
8614 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8615 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8616 dev_priv->display.modeset_global_resources =
8617 ivb_modeset_global_resources;
c82e4d26
ED		 8618 } else if (IS_HASWELL(dev)) {
8619 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8620 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8621 } else
8622 dev_priv->display.update_wm = NULL;
6067aaea 8623 } else if (IS_G4X(dev)) {
e0dac65e 8624 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8625 }
8c9f3aaf
JB		 8626
8627 /* Default just returns -ENODEV to indicate unsupported */
8628 dev_priv->display.queue_flip = intel_default_queue_flip;
8629
8630 switch (INTEL_INFO(dev)->gen) {
8631 case 2:
8632 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8633 break;
8634
8635 case 3:
8636 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8637 break;
8638
8639 case 4:
8640 case 5:
8641 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8642 break;
8643
8644 case 6:
8645 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8646 break;
7c9017e5
JB		 8647 case 7:
8648 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8649 break;
8c9f3aaf 8650 }
e70236a8
JB		 8651}
8652
b690e96c
JB		 8653/*
8654 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8655 * resume, or other times. This quirk makes sure that's the case for
8656 * affected systems.
8657 */
0206e353 8658static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8659{
8660 struct drm_i915_private *dev_priv = dev->dev_private;
8661
8662 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8663 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8664}
8665
435793df
KP		 8666/*
8667 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8668 */
8669static void quirk_ssc_force_disable(struct drm_device *dev)
8670{
8671 struct drm_i915_private *dev_priv = dev->dev_private;
8672 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8673 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8674}
8675
4dca20ef 8676/*
5a15ab5b
CE		 8677 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8678 * brightness value
4dca20ef
CE		 8679 */
8680static void quirk_invert_brightness(struct drm_device *dev)
8681{
8682 struct drm_i915_private *dev_priv = dev->dev_private;
8683 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8684 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8685}
8686
b690e96c
JB		 8687struct intel_quirk {
8688 int device;
8689 int subsystem_vendor;
8690 int subsystem_device;
8691 void (*hook)(struct drm_device *dev);
8692};
8693
c43b5634 8694static struct intel_quirk intel_quirks[] = {
b690e96c 8695 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8696 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8697
b690e96c
JB		 8698 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8699 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8700
b690e96c
JB		 8701 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8702 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8703
ccd0d36e 8704 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8705 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8706 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8707
8708 /* Lenovo U160 cannot use SSC on LVDS */
8709 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8710
8711 /* Sony Vaio Y cannot use SSC on LVDS */
8712 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8713
8714 /* Acer Aspire 5734Z must invert backlight brightness */
8715 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8716};
8717
8718static void intel_init_quirks(struct drm_device *dev)
8719{
8720 struct pci_dev *d = dev->pdev;
8721 int i;
8722
8723 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8724 struct intel_quirk *q = &intel_quirks[i];
8725
8726 if (d->device == q->device &&
8727 (d->subsystem_vendor == q->subsystem_vendor ||
8728 q->subsystem_vendor == PCI_ANY_ID) &&
8729 (d->subsystem_device == q->subsystem_device ||
8730 q->subsystem_device == PCI_ANY_ID))
8731 q->hook(dev);
8732 }
8733}
8734
9cce37f4
JB		 8735/* Disable the VGA plane that we never use */
8736static void i915_disable_vga(struct drm_device *dev)
8737{
8738 struct drm_i915_private *dev_priv = dev->dev_private;
8739 u8 sr1;
8740 u32 vga_reg;
8741
8742 if (HAS_PCH_SPLIT(dev))
8743 vga_reg = CPU_VGACNTRL;
8744 else
8745 vga_reg = VGACNTRL;
8746
8747 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8748 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8749 sr1 = inb(VGA_SR_DATA);
8750 outb(sr1 | 1<<5, VGA_SR_DATA);
8751 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8752 udelay(300);
8753
8754 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8755 POSTING_READ(vga_reg);
8756}
8757
f817586c
DV		 8758void intel_modeset_init_hw(struct drm_device *dev)
8759{
0232e927
ED		 8760 /* We attempt to init the necessary power wells early in the initialization
8761 * time, so the subsystems that expect power to be enabled can work.
8762 */
8763 intel_init_power_wells(dev);
8764
a8f78b58
ED		 8765 intel_prepare_ddi(dev);
8766
f817586c
DV		 8767 intel_init_clock_gating(dev);
8768
79f5b2c7 8769 mutex_lock(&dev->struct_mutex);
8090c6b9 8770 intel_enable_gt_powersave(dev);
79f5b2c7 8771 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8772}
8773
79e53945
JB		 8774void intel_modeset_init(struct drm_device *dev)
8775{
652c393a 8776 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8777 int i, ret;
79e53945
JB		 8778
8779 drm_mode_config_init(dev);
8780
8781 dev->mode_config.min_width = 0;
8782 dev->mode_config.min_height = 0;
8783
019d96cb
DA		 8784 dev->mode_config.preferred_depth = 24;
8785 dev->mode_config.prefer_shadow = 1;
8786
e6ecefaa 8787 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8788
b690e96c
JB		 8789 intel_init_quirks(dev);
8790
1fa61106
ED		 8791 intel_init_pm(dev);
8792
e70236a8
JB		 8793 intel_init_display(dev);
8794
a6c45cf0
CW		 8795 if (IS_GEN2(dev)) {
8796 dev->mode_config.max_width = 2048;
8797 dev->mode_config.max_height = 2048;
8798 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8799 dev->mode_config.max_width = 4096;
8800 dev->mode_config.max_height = 4096;
79e53945 8801 } else {
a6c45cf0
CW		 8802 dev->mode_config.max_width = 8192;
8803 dev->mode_config.max_height = 8192;
79e53945 8804 }
dd2757f8 8805 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8806
28c97730 8807 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8808 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8809
a3524f1b 8810 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8811 intel_crtc_init(dev, i);
00c2064b
JB		 8812 ret = intel_plane_init(dev, i);
8813 if (ret)
8814 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8815 }
8816
79f689aa 8817 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8818 intel_pch_pll_init(dev);
8819
9cce37f4
JB		 8820 /* Just disable it once at startup */
8821 i915_disable_vga(dev);
79e53945 8822 intel_setup_outputs(dev);
2c7111db
CW		 8823}
8824
24929352
DV		 8825static void
8826intel_connector_break_all_links(struct intel_connector *connector)
8827{
8828 connector->base.dpms = DRM_MODE_DPMS_OFF;
8829 connector->base.encoder = NULL;
8830 connector->encoder->connectors_active = false;
8831 connector->encoder->base.crtc = NULL;
8832}
8833
7fad798e
DV		 8834static void intel_enable_pipe_a(struct drm_device *dev)
8835{
8836 struct intel_connector *connector;
8837 struct drm_connector *crt = NULL;
8838 struct intel_load_detect_pipe load_detect_temp;
8839
8840 /* We can't just switch on the pipe A, we need to set things up with a
8841 * proper mode and output configuration. As a gross hack, enable pipe A
8842 * by enabling the load detect pipe once. */
8843 list_for_each_entry(connector,
8844 &dev->mode_config.connector_list,
8845 base.head) {
8846 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8847 crt = &connector->base;
8848 break;
8849 }
8850 }
8851
8852 if (!crt)
8853 return;
8854
8855 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8856 intel_release_load_detect_pipe(crt, &load_detect_temp);
8857
8858
8859}
8860
fa555837
DV		 8861static bool
8862intel_check_plane_mapping(struct intel_crtc *crtc)
8863{
8864 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8865 u32 reg, val;
8866
8867 if (dev_priv->num_pipe == 1)
8868 return true;
8869
8870 reg = DSPCNTR(!crtc->plane);
8871 val = I915_READ(reg);
8872
8873 if ((val & DISPLAY_PLANE_ENABLE) &&
8874 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8875 return false;
8876
8877 return true;
8878}
8879
24929352
DV		 8880static void intel_sanitize_crtc(struct intel_crtc *crtc)
8881{
8882 struct drm_device *dev = crtc->base.dev;
8883 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8884 u32 reg;
24929352 8885
24929352 8886 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8887 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8888 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8889
8890 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8891 * disable the crtc (and hence change the state) if it is wrong. Note
8892 * that gen4+ has a fixed plane -> pipe mapping. */
8893 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8894 struct intel_connector *connector;
8895 bool plane;
8896
24929352
DV		 8897 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8898 crtc->base.base.id);
8899
8900 /* Pipe has the wrong plane attached and the plane is active.
8901 * Temporarily change the plane mapping and disable everything
8902 * ... */
8903 plane = crtc->plane;
8904 crtc->plane = !plane;
8905 dev_priv->display.crtc_disable(&crtc->base);
8906 crtc->plane = plane;
8907
8908 /* ... and break all links. */
8909 list_for_each_entry(connector, &dev->mode_config.connector_list,
8910 base.head) {
8911 if (connector->encoder->base.crtc != &crtc->base)
8912 continue;
8913
8914 intel_connector_break_all_links(connector);
8915 }
8916
8917 WARN_ON(crtc->active);
8918 crtc->base.enabled = false;
8919 }
24929352 8920
7fad798e
DV		 8921 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8922 crtc->pipe == PIPE_A && !crtc->active) {
8923 /* BIOS forgot to enable pipe A, this mostly happens after
8924 * resume. Force-enable the pipe to fix this, the update_dpms
8925 * call below we restore the pipe to the right state, but leave
8926 * the required bits on. */
8927 intel_enable_pipe_a(dev);
8928 }
8929
24929352
DV		 8930 /* Adjust the state of the output pipe according to whether we
8931 * have active connectors/encoders. */
8932 intel_crtc_update_dpms(&crtc->base);
8933
8934 if (crtc->active != crtc->base.enabled) {
8935 struct intel_encoder *encoder;
8936
8937 /* This can happen either due to bugs in the get_hw_state
8938 * functions or because the pipe is force-enabled due to the
8939 * pipe A quirk. */
8940 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8941 crtc->base.base.id,
8942 crtc->base.enabled ? "enabled" : "disabled",
8943 crtc->active ? "enabled" : "disabled");
8944
8945 crtc->base.enabled = crtc->active;
8946
8947 /* Because we only establish the connector -> encoder ->
8948 * crtc links if something is active, this means the
8949 * crtc is now deactivated. Break the links. connector
8950 * -> encoder links are only establish when things are
8951 * actually up, hence no need to break them. */
8952 WARN_ON(crtc->active);
8953
8954 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8955 WARN_ON(encoder->connectors_active);
8956 encoder->base.crtc = NULL;
8957 }
8958 }
8959}
8960
8961static void intel_sanitize_encoder(struct intel_encoder *encoder)
8962{
8963 struct intel_connector *connector;
8964 struct drm_device *dev = encoder->base.dev;
8965
8966 /* We need to check both for a crtc link (meaning that the
8967 * encoder is active and trying to read from a pipe) and the
8968 * pipe itself being active. */
8969 bool has_active_crtc = encoder->base.crtc &&
8970 to_intel_crtc(encoder->base.crtc)->active;
8971
8972 if (encoder->connectors_active && !has_active_crtc) {
8973 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8974 encoder->base.base.id,
8975 drm_get_encoder_name(&encoder->base));
8976
8977 /* Connector is active, but has no active pipe. This is
8978 * fallout from our resume register restoring. Disable
8979 * the encoder manually again. */
8980 if (encoder->base.crtc) {
8981 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8982 encoder->base.base.id,
8983 drm_get_encoder_name(&encoder->base));
8984 encoder->disable(encoder);
8985 }
8986
8987 /* Inconsistent output/port/pipe state happens presumably due to
8988 * a bug in one of the get_hw_state functions. Or someplace else
8989 * in our code, like the register restore mess on resume. Clamp
8990 * things to off as a safer default. */
8991 list_for_each_entry(connector,
8992 &dev->mode_config.connector_list,
8993 base.head) {
8994 if (connector->encoder != encoder)
8995 continue;
8996
8997 intel_connector_break_all_links(connector);
8998 }
8999 }
9000 /* Enabled encoders without active connectors will be fixed in
9001 * the crtc fixup. */
9002}
9003
9004/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9005 * and i915 state tracking structures. */
9006void intel_modeset_setup_hw_state(struct drm_device *dev)
9007{
9008 struct drm_i915_private *dev_priv = dev->dev_private;
9009 enum pipe pipe;
9010 u32 tmp;
9011 struct intel_crtc *crtc;
9012 struct intel_encoder *encoder;
9013 struct intel_connector *connector;
9014
e28d54cb
PZ		 9015 if (IS_HASWELL(dev)) {
9016 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9017
9018 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9019 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9020 case TRANS_DDI_EDP_INPUT_A_ON:
9021 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9022 pipe = PIPE_A;
9023 break;
9024 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9025 pipe = PIPE_B;
9026 break;
9027 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9028 pipe = PIPE_C;
9029 break;
9030 }
9031
9032 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9033 crtc->cpu_transcoder = TRANSCODER_EDP;
9034
9035 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9036 pipe_name(pipe));
9037 }
9038 }
9039
24929352
DV		 9040 for_each_pipe(pipe) {
9041 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9042
702e7a56 9043 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9044 if (tmp & PIPECONF_ENABLE)
9045 crtc->active = true;
9046 else
9047 crtc->active = false;
9048
9049 crtc->base.enabled = crtc->active;
9050
9051 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9052 crtc->base.base.id,
9053 crtc->active ? "enabled" : "disabled");
9054 }
9055
6441ab5f
PZ		 9056 if (IS_HASWELL(dev))
9057 intel_ddi_setup_hw_pll_state(dev);
9058
24929352
DV		 9059 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9060 base.head) {
9061 pipe = 0;
9062
9063 if (encoder->get_hw_state(encoder, &pipe)) {
9064 encoder->base.crtc =
9065 dev_priv->pipe_to_crtc_mapping[pipe];
9066 } else {
9067 encoder->base.crtc = NULL;
9068 }
9069
9070 encoder->connectors_active = false;
9071 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9072 encoder->base.base.id,
9073 drm_get_encoder_name(&encoder->base),
9074 encoder->base.crtc ? "enabled" : "disabled",
9075 pipe);
9076 }
9077
9078 list_for_each_entry(connector, &dev->mode_config.connector_list,
9079 base.head) {
9080 if (connector->get_hw_state(connector)) {
9081 connector->base.dpms = DRM_MODE_DPMS_ON;
9082 connector->encoder->connectors_active = true;
9083 connector->base.encoder = &connector->encoder->base;
9084 } else {
9085 connector->base.dpms = DRM_MODE_DPMS_OFF;
9086 connector->base.encoder = NULL;
9087 }
9088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9089 connector->base.base.id,
9090 drm_get_connector_name(&connector->base),
9091 connector->base.encoder ? "enabled" : "disabled");
9092 }
9093
9094 /* HW state is read out, now we need to sanitize this mess. */
9095 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9096 base.head) {
9097 intel_sanitize_encoder(encoder);
9098 }
9099
9100 for_each_pipe(pipe) {
9101 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9102 intel_sanitize_crtc(crtc);
9103 }
9a935856
DV		 9104
9105 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9106
9107 intel_modeset_check_state(dev);
2e938892
DV		 9108
9109 drm_mode_config_reset(dev);
24929352
DV		 9110}
9111
2c7111db
CW		 9112void intel_modeset_gem_init(struct drm_device *dev)
9113{
1833b134 9114 intel_modeset_init_hw(dev);
02e792fb
DV		 9115
9116 intel_setup_overlay(dev);
24929352
DV		 9117
9118 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9119}
9120
9121void intel_modeset_cleanup(struct drm_device *dev)
9122{
652c393a
JB		 9123 struct drm_i915_private *dev_priv = dev->dev_private;
9124 struct drm_crtc *crtc;
9125 struct intel_crtc *intel_crtc;
9126
f87ea761 9127 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9128 mutex_lock(&dev->struct_mutex);
9129
723bfd70
JB		 9130 intel_unregister_dsm_handler();
9131
9132
652c393a
JB		 9133 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9134 /* Skip inactive CRTCs */
9135 if (!crtc->fb)
9136 continue;
9137
9138 intel_crtc = to_intel_crtc(crtc);
3dec0095 9139 intel_increase_pllclock(crtc);
652c393a
JB		 9140 }
9141
973d04f9 9142 intel_disable_fbc(dev);
e70236a8 9143
8090c6b9 9144 intel_disable_gt_powersave(dev);
0cdab21f 9145
930ebb46
DV		 9146 ironlake_teardown_rc6(dev);
9147
57f350b6
JB		 9148 if (IS_VALLEYVIEW(dev))
9149 vlv_init_dpio(dev);
9150
69341a5e
KH		 9151 mutex_unlock(&dev->struct_mutex);
9152
6c0d9350
DV		 9153 /* Disable the irq before mode object teardown, for the irq might
9154 * enqueue unpin/hotplug work. */
9155 drm_irq_uninstall(dev);
9156 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9157 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9158
1630fe75
CW		 9159 /* flush any delayed tasks or pending work */
9160 flush_scheduled_work();
9161
79e53945
JB		 9162 drm_mode_config_cleanup(dev);
9163}
9164
f1c79df3
ZW		 9165/*
9166 * Return which encoder is currently attached for connector.
9167 */
df0e9248 9168struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9169{
df0e9248
CW		 9170 return &intel_attached_encoder(connector)->base;
9171}
f1c79df3 9172
df0e9248
CW		 9173void intel_connector_attach_encoder(struct intel_connector *connector,
9174 struct intel_encoder *encoder)
9175{
9176 connector->encoder = encoder;
9177 drm_mode_connector_attach_encoder(&connector->base,
9178 &encoder->base);
79e53945 9179}
28d52043
DA		 9180
9181/*
9182 * set vga decode state - true == enable VGA decode
9183 */
9184int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9185{
9186 struct drm_i915_private *dev_priv = dev->dev_private;
9187 u16 gmch_ctrl;
9188
9189 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9190 if (state)
9191 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9192 else
9193 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9194 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9195 return 0;
9196}
c4a1d9e4
CW		 9197
9198#ifdef CONFIG_DEBUG_FS
9199#include <linux/seq_file.h>
9200
9201struct intel_display_error_state {
9202 struct intel_cursor_error_state {
9203 u32 control;
9204 u32 position;
9205 u32 base;
9206 u32 size;
52331309 9207 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9208
9209 struct intel_pipe_error_state {
9210 u32 conf;
9211 u32 source;
9212
9213 u32 htotal;
9214 u32 hblank;
9215 u32 hsync;
9216 u32 vtotal;
9217 u32 vblank;
9218 u32 vsync;
52331309 9219 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9220
9221 struct intel_plane_error_state {
9222 u32 control;
9223 u32 stride;
9224 u32 size;
9225 u32 pos;
9226 u32 addr;
9227 u32 surface;
9228 u32 tile_offset;
52331309 9229 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9230};
9231
9232struct intel_display_error_state *
9233intel_display_capture_error_state(struct drm_device *dev)
9234{
0206e353 9235 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9236 struct intel_display_error_state *error;
702e7a56 9237 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9238 int i;
9239
9240 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9241 if (error == NULL)
9242 return NULL;
9243
52331309 9244 for_each_pipe(i) {
702e7a56
PZ		 9245 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9246
c4a1d9e4
CW		 9247 error->cursor[i].control = I915_READ(CURCNTR(i));
9248 error->cursor[i].position = I915_READ(CURPOS(i));
9249 error->cursor[i].base = I915_READ(CURBASE(i));
9250
9251 error->plane[i].control = I915_READ(DSPCNTR(i));
9252 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9253 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9254 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9255 error->plane[i].addr = I915_READ(DSPADDR(i));
9256 if (INTEL_INFO(dev)->gen >= 4) {
9257 error->plane[i].surface = I915_READ(DSPSURF(i));
9258 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9259 }
9260
702e7a56 9261 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9262 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9263 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9264 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9265 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9266 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9267 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9268 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9269 }
9270
9271 return error;
9272}
9273
9274void
9275intel_display_print_error_state(struct seq_file *m,
9276 struct drm_device *dev,
9277 struct intel_display_error_state *error)
9278{
52331309 9279 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9280 int i;
9281
52331309
DL		 9282 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9283 for_each_pipe(i) {
c4a1d9e4
CW		 9284 seq_printf(m, "Pipe [%d]:\n", i);
9285 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9286 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9287 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9288 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9289 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9290 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9291 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9292 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9293
9294 seq_printf(m, "Plane [%d]:\n", i);
9295 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9296 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9297 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9298 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9299 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9300 if (INTEL_INFO(dev)->gen >= 4) {
9301 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9302 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9303 }
9304
9305 seq_printf(m, "Cursor [%d]:\n", i);
9306 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9307 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9308 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9309 }
9310}
9311#endif
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