]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: don't call dpms funcs after set_mode
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
284637d9 1027 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
e9a851ed 1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
e9a851ed 1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
e9a851ed 1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
7434a255
TR		 1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1434 */
a37b9b34 1435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
a0c4da24 1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
a416edef
ED		 1491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
39fb50f6 1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
39fb50f6 1526 u32 value = 0;
a416edef
ED		 1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
39fb50f6 1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
92f2584a
JB		 1554/**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
ee7b9f93 1562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1563{
ee7b9f93 1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1565 struct intel_pch_pll *pll;
92f2584a
JB		 1566 int reg;
1567 u32 val;
1568
48da64a8 1569 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1570 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
ee7b9f93
JB		 1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
92f2584a
JB		 1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
ee7b9f93 1585 if (pll->active++ && pll->on) {
92b27b08 1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
92f2584a
JB		 1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
ee7b9f93
JB		 1598
1599 pll->on = true;
92f2584a
JB		 1600}
1601
ee7b9f93 1602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1603{
ee7b9f93
JB		 1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1606 int reg;
ee7b9f93 1607 u32 val;
4c609cb8 1608
92f2584a
JB		 1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1611 if (pll == NULL)
1612 return;
92f2584a 1613
48da64a8
CW		 1614 if (WARN_ON(pll->refcount == 0))
1615 return;
7a419866 1616
ee7b9f93
JB		 1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
7a419866 1620
48da64a8 1621 if (WARN_ON(pll->active == 0)) {
92b27b08 1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1623 return;
1624 }
1625
ee7b9f93 1626 if (--pll->active) {
92b27b08 1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1628 return;
ee7b9f93
JB		 1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1635
ee7b9f93 1636 reg = pll->pll_reg;
92f2584a
JB		 1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
ee7b9f93
JB		 1642
1643 pll->on = false;
92f2584a
JB		 1644}
1645
040484af
JB		 1646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
5f7f726d 1650 u32 val, pipeconf_val;
7c26e5c6 1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
040484af
JB		 1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
59c859d6
ED		 1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
040484af
JB		 1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
5f7f726d 1671 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
5f7f726d 1679 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1680 }
5f7f726d
PZ		 1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
040484af
JB		 1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
291906f1
JB		 1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
040484af
JB		 1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1717}
1718
b24e7179 1719/**
309cfea8 1720 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
040484af 1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
040484af
JB		 1733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
b24e7179
JB		 1735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
b24e7179
JB		 1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
00d70b15
CW		 1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
309cfea8 1765 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
00d70b15
CW		 1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
d74362c9
KP		 1801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
6f1d69b0 1805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
b24e7179
JB		 1812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
00d70b15
CW		 1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1835 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
b24e7179
JB		 1839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
127bd2ac 1863int
48b956c5 1864intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1865 struct drm_i915_gem_object *obj,
919926ae 1866 struct intel_ring_buffer *pipelined)
6b95a207 1867{
ce453d81 1868 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1869 u32 alignment;
1870 int ret;
1871
05394f39 1872 switch (obj->tiling_mode) {
6b95a207 1873 case I915_TILING_NONE:
534843da
CW		 1874 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1875 alignment = 128 * 1024;
a6c45cf0 1876 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1877 alignment = 4 * 1024;
1878 else
1879 alignment = 64 * 1024;
6b95a207
KH		 1880 break;
1881 case I915_TILING_X:
1882 /* pin() will align the object as required by fence */
1883 alignment = 0;
1884 break;
1885 case I915_TILING_Y:
1886 /* FIXME: Is this true? */
1887 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
ce453d81 1893 dev_priv->mm.interruptible = false;
2da3b9b9 1894 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1895 if (ret)
ce453d81 1896 goto err_interruptible;
6b95a207
KH		 1897
1898 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1899 * fence, whereas 965+ only requires a fence if using
1900 * framebuffer compression. For simplicity, we always install
1901 * a fence as the cost is not that onerous.
1902 */
06d98131 1903 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1904 if (ret)
1905 goto err_unpin;
1690e1eb 1906
9a5a53b3 1907 i915_gem_object_pin_fence(obj);
6b95a207 1908
ce453d81 1909 dev_priv->mm.interruptible = true;
6b95a207 1910 return 0;
48b956c5
CW		 1911
1912err_unpin:
1913 i915_gem_object_unpin(obj);
ce453d81
CW		 1914err_interruptible:
1915 dev_priv->mm.interruptible = true;
48b956c5 1916 return ret;
6b95a207
KH		 1917}
1918
1690e1eb
CW		 1919void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1920{
1921 i915_gem_object_unpin_fence(obj);
1922 i915_gem_object_unpin(obj);
1923}
1924
c2c75131
DV		 1925/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1926 * is assumed to be a power-of-two. */
1927static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1928 unsigned int bpp,
1929 unsigned int pitch)
1930{
1931 int tile_rows, tiles;
1932
1933 tile_rows = *y / 8;
1934 *y %= 8;
1935 tiles = *x / (512/bpp);
1936 *x %= 512/bpp;
1937
1938 return tile_rows * pitch * 8 + tiles * 4096;
1939}
1940
17638cd6
JB		 1941static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1942 int x, int y)
81255565
JB		 1943{
1944 struct drm_device *dev = crtc->dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1947 struct intel_framebuffer *intel_fb;
05394f39 1948 struct drm_i915_gem_object *obj;
81255565 1949 int plane = intel_crtc->plane;
e506a0c6 1950 unsigned long linear_offset;
81255565 1951 u32 dspcntr;
5eddb70b 1952 u32 reg;
81255565
JB		 1953
1954 switch (plane) {
1955 case 0:
1956 case 1:
1957 break;
1958 default:
1959 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1960 return -EINVAL;
1961 }
1962
1963 intel_fb = to_intel_framebuffer(fb);
1964 obj = intel_fb->obj;
81255565 1965
5eddb70b
CW		 1966 reg = DSPCNTR(plane);
1967 dspcntr = I915_READ(reg);
81255565
JB		 1968 /* Mask out pixel format bits in case we change it */
1969 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1970 switch (fb->bits_per_pixel) {
1971 case 8:
1972 dspcntr |= DISPPLANE_8BPP;
1973 break;
1974 case 16:
1975 if (fb->depth == 15)
1976 dspcntr |= DISPPLANE_15_16BPP;
1977 else
1978 dspcntr |= DISPPLANE_16BPP;
1979 break;
1980 case 24:
1981 case 32:
1982 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1983 break;
1984 default:
17638cd6 1985 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1986 return -EINVAL;
1987 }
a6c45cf0 1988 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1989 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1990 dspcntr |= DISPPLANE_TILED;
1991 else
1992 dspcntr &= ~DISPPLANE_TILED;
1993 }
1994
5eddb70b 1995 I915_WRITE(reg, dspcntr);
81255565 1996
e506a0c6 1997 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1998
c2c75131
DV		 1999 if (INTEL_INFO(dev)->gen >= 4) {
2000 intel_crtc->dspaddr_offset =
2001 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2002 fb->bits_per_pixel / 8,
2003 fb->pitches[0]);
2004 linear_offset -= intel_crtc->dspaddr_offset;
2005 } else {
e506a0c6 2006 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2007 }
e506a0c6
DV		 2008
2009 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2010 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2011 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2012 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2013 I915_MODIFY_DISPBASE(DSPSURF(plane),
2014 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2015 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2016 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2017 } else
e506a0c6 2018 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2019 POSTING_READ(reg);
81255565 2020
17638cd6
JB		 2021 return 0;
2022}
2023
2024static int ironlake_update_plane(struct drm_crtc *crtc,
2025 struct drm_framebuffer *fb, int x, int y)
2026{
2027 struct drm_device *dev = crtc->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030 struct intel_framebuffer *intel_fb;
2031 struct drm_i915_gem_object *obj;
2032 int plane = intel_crtc->plane;
e506a0c6 2033 unsigned long linear_offset;
17638cd6
JB		 2034 u32 dspcntr;
2035 u32 reg;
2036
2037 switch (plane) {
2038 case 0:
2039 case 1:
27f8227b 2040 case 2:
17638cd6
JB		 2041 break;
2042 default:
2043 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2044 return -EINVAL;
2045 }
2046
2047 intel_fb = to_intel_framebuffer(fb);
2048 obj = intel_fb->obj;
2049
2050 reg = DSPCNTR(plane);
2051 dspcntr = I915_READ(reg);
2052 /* Mask out pixel format bits in case we change it */
2053 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2054 switch (fb->bits_per_pixel) {
2055 case 8:
2056 dspcntr |= DISPPLANE_8BPP;
2057 break;
2058 case 16:
2059 if (fb->depth != 16)
2060 return -EINVAL;
2061
2062 dspcntr |= DISPPLANE_16BPP;
2063 break;
2064 case 24:
2065 case 32:
2066 if (fb->depth == 24)
2067 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2068 else if (fb->depth == 30)
2069 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2070 else
2071 return -EINVAL;
2072 break;
2073 default:
2074 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2075 return -EINVAL;
2076 }
2077
2078 if (obj->tiling_mode != I915_TILING_NONE)
2079 dspcntr |= DISPPLANE_TILED;
2080 else
2081 dspcntr &= ~DISPPLANE_TILED;
2082
2083 /* must disable */
2084 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2085
2086 I915_WRITE(reg, dspcntr);
2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2089 intel_crtc->dspaddr_offset =
2090 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2091 fb->bits_per_pixel / 8,
2092 fb->pitches[0]);
2093 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2094
e506a0c6
DV		 2095 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2096 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2097 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2098 I915_MODIFY_DISPBASE(DSPSURF(plane),
2099 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2100 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2101 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2102 POSTING_READ(reg);
2103
2104 return 0;
2105}
2106
2107/* Assume fb object is pinned & idle & fenced and just update base pointers */
2108static int
2109intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2110 int x, int y, enum mode_set_atomic state)
2111{
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2114
6b8e6ed0
CW		 2115 if (dev_priv->display.disable_fbc)
2116 dev_priv->display.disable_fbc(dev);
3dec0095 2117 intel_increase_pllclock(crtc);
81255565 2118
6b8e6ed0 2119 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2120}
2121
14667a4b
CW		 2122static int
2123intel_finish_fb(struct drm_framebuffer *old_fb)
2124{
2125 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2126 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2127 bool was_interruptible = dev_priv->mm.interruptible;
2128 int ret;
2129
2130 wait_event(dev_priv->pending_flip_queue,
2131 atomic_read(&dev_priv->mm.wedged) ||
2132 atomic_read(&obj->pending_flip) == 0);
2133
2134 /* Big Hammer, we also need to ensure that any pending
2135 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2136 * current scanout is retired before unpinning the old
2137 * framebuffer.
2138 *
2139 * This should only fail upon a hung GPU, in which case we
2140 * can safely continue.
2141 */
2142 dev_priv->mm.interruptible = false;
2143 ret = i915_gem_object_finish_gpu(obj);
2144 dev_priv->mm.interruptible = was_interruptible;
2145
2146 return ret;
2147}
2148
5c3b82e2 2149static int
3c4fdcfb 2150intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2151 struct drm_framebuffer *fb)
79e53945
JB		 2152{
2153 struct drm_device *dev = crtc->dev;
6b8e6ed0 2154 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2155 struct drm_i915_master_private *master_priv;
2156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2157 struct drm_framebuffer *old_fb;
5c3b82e2 2158 int ret;
79e53945
JB		 2159
2160 /* no fb bound */
94352cf9 2161 if (!fb) {
a5071c2f 2162 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2163 return 0;
2164 }
2165
5826eca5
ED		 2166 if(intel_crtc->plane > dev_priv->num_pipe) {
2167 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2168 intel_crtc->plane,
2169 dev_priv->num_pipe);
5c3b82e2 2170 return -EINVAL;
79e53945
JB		 2171 }
2172
5c3b82e2 2173 mutex_lock(&dev->struct_mutex);
265db958 2174 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2175 to_intel_framebuffer(fb)->obj,
919926ae 2176 NULL);
5c3b82e2
CW		 2177 if (ret != 0) {
2178 mutex_unlock(&dev->struct_mutex);
a5071c2f 2179 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2180 return ret;
2181 }
79e53945 2182
94352cf9
DV		 2183 if (crtc->fb)
2184 intel_finish_fb(crtc->fb);
265db958 2185
94352cf9 2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2187 if (ret) {
94352cf9 2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2189 mutex_unlock(&dev->struct_mutex);
a5071c2f 2190 DRM_ERROR("failed to update base address\n");
4e6cfefc 2191 return ret;
79e53945 2192 }
3c4fdcfb 2193
94352cf9
DV		 2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
6c4c86f5
DV		 2196 crtc->x = x;
2197 crtc->y = y;
94352cf9 2198
b7f1de28
CW		 2199 if (old_fb) {
2200 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2201 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2202 }
652c393a 2203
6b8e6ed0 2204 intel_update_fbc(dev);
5c3b82e2 2205 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2206
2207 if (!dev->primary->master)
5c3b82e2 2208 return 0;
79e53945
JB		 2209
2210 master_priv = dev->primary->master->driver_priv;
2211 if (!master_priv->sarea_priv)
5c3b82e2 2212 return 0;
79e53945 2213
265db958 2214 if (intel_crtc->pipe) {
79e53945
JB		 2215 master_priv->sarea_priv->pipeB_x = x;
2216 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2217 } else {
2218 master_priv->sarea_priv->pipeA_x = x;
2219 master_priv->sarea_priv->pipeA_y = y;
79e53945 2220 }
5c3b82e2
CW		 2221
2222 return 0;
79e53945
JB		 2223}
2224
5eddb70b 2225static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2226{
2227 struct drm_device *dev = crtc->dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 u32 dpa_ctl;
2230
28c97730 2231 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2232 dpa_ctl = I915_READ(DP_A);
2233 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2234
2235 if (clock < 200000) {
2236 u32 temp;
2237 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2238 /* workaround for 160Mhz:
2239 1) program 0x4600c bits 15:0 = 0x8124
2240 2) program 0x46010 bit 0 = 1
2241 3) program 0x46034 bit 24 = 1
2242 4) program 0x64000 bit 14 = 1
2243 */
2244 temp = I915_READ(0x4600c);
2245 temp &= 0xffff0000;
2246 I915_WRITE(0x4600c, temp | 0x8124);
2247
2248 temp = I915_READ(0x46010);
2249 I915_WRITE(0x46010, temp | 1);
2250
2251 temp = I915_READ(0x46034);
2252 I915_WRITE(0x46034, temp | (1 << 24));
2253 } else {
2254 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2255 }
2256 I915_WRITE(DP_A, dpa_ctl);
2257
5eddb70b 2258 POSTING_READ(DP_A);
32f9d658
ZW		 2259 udelay(500);
2260}
2261
5e84e1a4
ZW		 2262static void intel_fdi_normal_train(struct drm_crtc *crtc)
2263{
2264 struct drm_device *dev = crtc->dev;
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2267 int pipe = intel_crtc->pipe;
2268 u32 reg, temp;
2269
2270 /* enable normal train */
2271 reg = FDI_TX_CTL(pipe);
2272 temp = I915_READ(reg);
61e499bf 2273 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2274 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2275 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2276 } else {
2277 temp &= ~FDI_LINK_TRAIN_NONE;
2278 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2279 }
5e84e1a4
ZW		 2280 I915_WRITE(reg, temp);
2281
2282 reg = FDI_RX_CTL(pipe);
2283 temp = I915_READ(reg);
2284 if (HAS_PCH_CPT(dev)) {
2285 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2286 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2287 } else {
2288 temp &= ~FDI_LINK_TRAIN_NONE;
2289 temp |= FDI_LINK_TRAIN_NONE;
2290 }
2291 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2292
2293 /* wait one idle pattern time */
2294 POSTING_READ(reg);
2295 udelay(1000);
357555c0
JB		 2296
2297 /* IVB wants error correction enabled */
2298 if (IS_IVYBRIDGE(dev))
2299 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2300 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2301}
2302
291427f5
JB		 2303static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2304{
2305 struct drm_i915_private *dev_priv = dev->dev_private;
2306 u32 flags = I915_READ(SOUTH_CHICKEN1);
2307
2308 flags |= FDI_PHASE_SYNC_OVR(pipe);
2309 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2310 flags |= FDI_PHASE_SYNC_EN(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2312 POSTING_READ(SOUTH_CHICKEN1);
2313}
2314
8db9d77b
ZW		 2315/* The FDI link training functions for ILK/Ibexpeak. */
2316static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2317{
2318 struct drm_device *dev = crtc->dev;
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2321 int pipe = intel_crtc->pipe;
0fc932b8 2322 int plane = intel_crtc->plane;
5eddb70b 2323 u32 reg, temp, tries;
8db9d77b 2324
0fc932b8
JB		 2325 /* FDI needs bits from pipe & plane first */
2326 assert_pipe_enabled(dev_priv, pipe);
2327 assert_plane_enabled(dev_priv, plane);
2328
e1a44743
AJ		 2329 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2330 for train result */
5eddb70b
CW		 2331 reg = FDI_RX_IMR(pipe);
2332 temp = I915_READ(reg);
e1a44743
AJ		 2333 temp &= ~FDI_RX_SYMBOL_LOCK;
2334 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2335 I915_WRITE(reg, temp);
2336 I915_READ(reg);
e1a44743
AJ		 2337 udelay(150);
2338
8db9d77b 2339 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
77ffb597
AJ		 2342 temp &= ~(7 << 19);
2343 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2346 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2347
5eddb70b
CW		 2348 reg = FDI_RX_CTL(pipe);
2349 temp = I915_READ(reg);
8db9d77b
ZW		 2350 temp &= ~FDI_LINK_TRAIN_NONE;
2351 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2352 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2353
2354 POSTING_READ(reg);
8db9d77b
ZW		 2355 udelay(150);
2356
5b2adf89 2357 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2358 if (HAS_PCH_IBX(dev)) {
2359 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2360 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2361 FDI_RX_PHASE_SYNC_POINTER_EN);
2362 }
5b2adf89 2363
5eddb70b 2364 reg = FDI_RX_IIR(pipe);
e1a44743 2365 for (tries = 0; tries < 5; tries++) {
5eddb70b 2366 temp = I915_READ(reg);
8db9d77b
ZW		 2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368
2369 if ((temp & FDI_RX_BIT_LOCK)) {
2370 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2372 break;
2373 }
8db9d77b 2374 }
e1a44743 2375 if (tries == 5)
5eddb70b 2376 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2377
2378 /* Train 2 */
5eddb70b
CW		 2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
8db9d77b
ZW		 2381 temp &= ~FDI_LINK_TRAIN_NONE;
2382 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2383 I915_WRITE(reg, temp);
8db9d77b 2384
5eddb70b
CW		 2385 reg = FDI_RX_CTL(pipe);
2386 temp = I915_READ(reg);
8db9d77b
ZW		 2387 temp &= ~FDI_LINK_TRAIN_NONE;
2388 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2389 I915_WRITE(reg, temp);
8db9d77b 2390
5eddb70b
CW		 2391 POSTING_READ(reg);
2392 udelay(150);
8db9d77b 2393
5eddb70b 2394 reg = FDI_RX_IIR(pipe);
e1a44743 2395 for (tries = 0; tries < 5; tries++) {
5eddb70b 2396 temp = I915_READ(reg);
8db9d77b
ZW		 2397 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2398
2399 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2400 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2401 DRM_DEBUG_KMS("FDI train 2 done.\n");
2402 break;
2403 }
8db9d77b 2404 }
e1a44743 2405 if (tries == 5)
5eddb70b 2406 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2407
2408 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2409
8db9d77b
ZW		 2410}
2411
0206e353 2412static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2413 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2414 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2415 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2416 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2417};
2418
2419/* The FDI link training functions for SNB/Cougarpoint. */
2420static void gen6_fdi_link_train(struct drm_crtc *crtc)
2421{
2422 struct drm_device *dev = crtc->dev;
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2425 int pipe = intel_crtc->pipe;
fa37d39e 2426 u32 reg, temp, i, retry;
8db9d77b 2427
e1a44743
AJ		 2428 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2429 for train result */
5eddb70b
CW		 2430 reg = FDI_RX_IMR(pipe);
2431 temp = I915_READ(reg);
e1a44743
AJ		 2432 temp &= ~FDI_RX_SYMBOL_LOCK;
2433 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2434 I915_WRITE(reg, temp);
2435
2436 POSTING_READ(reg);
e1a44743
AJ		 2437 udelay(150);
2438
8db9d77b 2439 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2440 reg = FDI_TX_CTL(pipe);
2441 temp = I915_READ(reg);
77ffb597
AJ		 2442 temp &= ~(7 << 19);
2443 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2444 temp &= ~FDI_LINK_TRAIN_NONE;
2445 temp |= FDI_LINK_TRAIN_PATTERN_1;
2446 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447 /* SNB-B */
2448 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2449 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2450
5eddb70b
CW		 2451 reg = FDI_RX_CTL(pipe);
2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 if (HAS_PCH_CPT(dev)) {
2454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2455 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2456 } else {
2457 temp &= ~FDI_LINK_TRAIN_NONE;
2458 temp |= FDI_LINK_TRAIN_PATTERN_1;
2459 }
5eddb70b
CW		 2460 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2461
2462 POSTING_READ(reg);
8db9d77b
ZW		 2463 udelay(150);
2464
291427f5
JB		 2465 if (HAS_PCH_CPT(dev))
2466 cpt_phase_pointer_enable(dev, pipe);
2467
0206e353 2468 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2469 reg = FDI_TX_CTL(pipe);
2470 temp = I915_READ(reg);
8db9d77b
ZW		 2471 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2472 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2473 I915_WRITE(reg, temp);
2474
2475 POSTING_READ(reg);
8db9d77b
ZW		 2476 udelay(500);
2477
fa37d39e
SP		 2478 for (retry = 0; retry < 5; retry++) {
2479 reg = FDI_RX_IIR(pipe);
2480 temp = I915_READ(reg);
2481 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2482 if (temp & FDI_RX_BIT_LOCK) {
2483 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2484 DRM_DEBUG_KMS("FDI train 1 done.\n");
2485 break;
2486 }
2487 udelay(50);
8db9d77b 2488 }
fa37d39e
SP		 2489 if (retry < 5)
2490 break;
8db9d77b
ZW		 2491 }
2492 if (i == 4)
5eddb70b 2493 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2494
2495 /* Train 2 */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
8db9d77b
ZW		 2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_2;
2500 if (IS_GEN6(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2502 /* SNB-B */
2503 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2504 }
5eddb70b 2505 I915_WRITE(reg, temp);
8db9d77b 2506
5eddb70b
CW		 2507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 if (HAS_PCH_CPT(dev)) {
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2512 } else {
2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_2;
2515 }
5eddb70b
CW		 2516 I915_WRITE(reg, temp);
2517
2518 POSTING_READ(reg);
8db9d77b
ZW		 2519 udelay(150);
2520
0206e353 2521 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2522 reg = FDI_TX_CTL(pipe);
2523 temp = I915_READ(reg);
8db9d77b
ZW		 2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2526 I915_WRITE(reg, temp);
2527
2528 POSTING_READ(reg);
8db9d77b
ZW		 2529 udelay(500);
2530
fa37d39e
SP		 2531 for (retry = 0; retry < 5; retry++) {
2532 reg = FDI_RX_IIR(pipe);
2533 temp = I915_READ(reg);
2534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535 if (temp & FDI_RX_SYMBOL_LOCK) {
2536 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537 DRM_DEBUG_KMS("FDI train 2 done.\n");
2538 break;
2539 }
2540 udelay(50);
8db9d77b 2541 }
fa37d39e
SP		 2542 if (retry < 5)
2543 break;
8db9d77b
ZW		 2544 }
2545 if (i == 4)
5eddb70b 2546 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2547
2548 DRM_DEBUG_KMS("FDI train done.\n");
2549}
2550
357555c0
JB		 2551/* Manual link training for Ivy Bridge A0 parts */
2552static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2553{
2554 struct drm_device *dev = crtc->dev;
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2557 int pipe = intel_crtc->pipe;
2558 u32 reg, temp, i;
2559
2560 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2561 for train result */
2562 reg = FDI_RX_IMR(pipe);
2563 temp = I915_READ(reg);
2564 temp &= ~FDI_RX_SYMBOL_LOCK;
2565 temp &= ~FDI_RX_BIT_LOCK;
2566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
2569 udelay(150);
2570
2571 /* enable CPU FDI TX and PCH FDI RX */
2572 reg = FDI_TX_CTL(pipe);
2573 temp = I915_READ(reg);
2574 temp &= ~(7 << 19);
2575 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2576 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2577 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2579 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2580 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2581 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2582
2583 reg = FDI_RX_CTL(pipe);
2584 temp = I915_READ(reg);
2585 temp &= ~FDI_LINK_TRAIN_AUTO;
2586 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2587 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2588 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2589 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2590
2591 POSTING_READ(reg);
2592 udelay(150);
2593
291427f5
JB		 2594 if (HAS_PCH_CPT(dev))
2595 cpt_phase_pointer_enable(dev, pipe);
2596
0206e353 2597 for (i = 0; i < 4; i++) {
357555c0
JB		 2598 reg = FDI_TX_CTL(pipe);
2599 temp = I915_READ(reg);
2600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2601 temp |= snb_b_fdi_train_param[i];
2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
2605 udelay(500);
2606
2607 reg = FDI_RX_IIR(pipe);
2608 temp = I915_READ(reg);
2609 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2610
2611 if (temp & FDI_RX_BIT_LOCK ||
2612 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2613 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2614 DRM_DEBUG_KMS("FDI train 1 done.\n");
2615 break;
2616 }
2617 }
2618 if (i == 4)
2619 DRM_ERROR("FDI train 1 fail!\n");
2620
2621 /* Train 2 */
2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
2624 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2625 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2628 I915_WRITE(reg, temp);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2633 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2634 I915_WRITE(reg, temp);
2635
2636 POSTING_READ(reg);
2637 udelay(150);
2638
0206e353 2639 for (i = 0; i < 4; i++) {
357555c0
JB		 2640 reg = FDI_TX_CTL(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643 temp |= snb_b_fdi_train_param[i];
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(500);
2648
2649 reg = FDI_RX_IIR(pipe);
2650 temp = I915_READ(reg);
2651 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652
2653 if (temp & FDI_RX_SYMBOL_LOCK) {
2654 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2655 DRM_DEBUG_KMS("FDI train 2 done.\n");
2656 break;
2657 }
2658 }
2659 if (i == 4)
2660 DRM_ERROR("FDI train 2 fail!\n");
2661
2662 DRM_DEBUG_KMS("FDI train done.\n");
2663}
2664
88cefb6c 2665static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2666{
88cefb6c 2667 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2668 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2669 int pipe = intel_crtc->pipe;
5eddb70b 2670 u32 reg, temp;
79e53945 2671
c64e311e 2672 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2673 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2674 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2675
c98e9dcf 2676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2680 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2681 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2682 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2683
2684 POSTING_READ(reg);
c98e9dcf
JB		 2685 udelay(200);
2686
2687 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2688 temp = I915_READ(reg);
2689 I915_WRITE(reg, temp | FDI_PCDCLK);
2690
2691 POSTING_READ(reg);
c98e9dcf
JB		 2692 udelay(200);
2693
bf507ef7
ED		 2694 /* On Haswell, the PLL configuration for ports and pipes is handled
2695 * separately, as part of DDI setup */
2696 if (!IS_HASWELL(dev)) {
2697 /* Enable CPU FDI TX PLL, always on for Ironlake */
2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2701 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2702
bf507ef7
ED		 2703 POSTING_READ(reg);
2704 udelay(100);
2705 }
6be4a607 2706 }
0e23b99d
JB		 2707}
2708
88cefb6c
DV		 2709static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2710{
2711 struct drm_device *dev = intel_crtc->base.dev;
2712 struct drm_i915_private *dev_priv = dev->dev_private;
2713 int pipe = intel_crtc->pipe;
2714 u32 reg, temp;
2715
2716 /* Switch from PCDclk to Rawclk */
2717 reg = FDI_RX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2720
2721 /* Disable CPU FDI TX PLL */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2725
2726 POSTING_READ(reg);
2727 udelay(100);
2728
2729 reg = FDI_RX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2732
2733 /* Wait for the clocks to turn off. */
2734 POSTING_READ(reg);
2735 udelay(100);
2736}
2737
291427f5
JB		 2738static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2739{
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 u32 flags = I915_READ(SOUTH_CHICKEN1);
2742
2743 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2744 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2745 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2747 POSTING_READ(SOUTH_CHICKEN1);
2748}
0fc932b8
JB		 2749static void ironlake_fdi_disable(struct drm_crtc *crtc)
2750{
2751 struct drm_device *dev = crtc->dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2754 int pipe = intel_crtc->pipe;
2755 u32 reg, temp;
2756
2757 /* disable CPU FDI tx and PCH FDI rx */
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2761 POSTING_READ(reg);
2762
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~(0x7 << 16);
2766 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2767 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2768
2769 POSTING_READ(reg);
2770 udelay(100);
2771
2772 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2773 if (HAS_PCH_IBX(dev)) {
2774 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2775 I915_WRITE(FDI_RX_CHICKEN(pipe),
2776 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2777 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2778 } else if (HAS_PCH_CPT(dev)) {
2779 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2780 }
0fc932b8
JB		 2781
2782 /* still set train pattern 1 */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 temp &= ~FDI_LINK_TRAIN_NONE;
2786 temp |= FDI_LINK_TRAIN_PATTERN_1;
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if (HAS_PCH_CPT(dev)) {
2792 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2793 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2794 } else {
2795 temp &= ~FDI_LINK_TRAIN_NONE;
2796 temp |= FDI_LINK_TRAIN_PATTERN_1;
2797 }
2798 /* BPC in FDI rx is consistent with that in PIPECONF */
2799 temp &= ~(0x07 << 16);
2800 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805}
2806
e6c3a2a6
CW		 2807static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808{
0f91128d 2809 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2810
2811 if (crtc->fb == NULL)
2812 return;
2813
0f91128d
CW		 2814 mutex_lock(&dev->struct_mutex);
2815 intel_finish_fb(crtc->fb);
2816 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2817}
2818
040484af
JB		 2819static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2820{
2821 struct drm_device *dev = crtc->dev;
228d3e36 2822 struct intel_encoder *intel_encoder;
040484af
JB		 2823
2824 /*
2825 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2826 * must be driven by its own crtc; no sharing is possible.
2827 */
228d3e36 2828 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2829
6ee8bab0
ED		 2830 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2831 * CPU handles all others */
2832 if (IS_HASWELL(dev)) {
2833 /* It is still unclear how this will work on PPT, so throw up a warning */
2834 WARN_ON(!HAS_PCH_LPT(dev));
2835
228d3e36 2836 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2837 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2838 return true;
2839 } else {
2840 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2841 intel_encoder->type);
6ee8bab0
ED		 2842 return false;
2843 }
2844 }
2845
228d3e36 2846 switch (intel_encoder->type) {
040484af 2847 case INTEL_OUTPUT_EDP:
228d3e36 2848 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2849 return false;
2850 continue;
2851 }
2852 }
2853
2854 return true;
2855}
2856
e615efe4
ED		 2857/* Program iCLKIP clock to the desired frequency */
2858static void lpt_program_iclkip(struct drm_crtc *crtc)
2859{
2860 struct drm_device *dev = crtc->dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2863 u32 temp;
2864
2865 /* It is necessary to ungate the pixclk gate prior to programming
2866 * the divisors, and gate it back when it is done.
2867 */
2868 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2869
2870 /* Disable SSCCTL */
2871 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2872 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2873 SBI_SSCCTL_DISABLE);
2874
2875 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2876 if (crtc->mode.clock == 20000) {
2877 auxdiv = 1;
2878 divsel = 0x41;
2879 phaseinc = 0x20;
2880 } else {
2881 /* The iCLK virtual clock root frequency is in MHz,
2882 * but the crtc->mode.clock in in KHz. To get the divisors,
2883 * it is necessary to divide one by another, so we
2884 * convert the virtual clock precision to KHz here for higher
2885 * precision.
2886 */
2887 u32 iclk_virtual_root_freq = 172800 * 1000;
2888 u32 iclk_pi_range = 64;
2889 u32 desired_divisor, msb_divisor_value, pi_value;
2890
2891 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2892 msb_divisor_value = desired_divisor / iclk_pi_range;
2893 pi_value = desired_divisor % iclk_pi_range;
2894
2895 auxdiv = 0;
2896 divsel = msb_divisor_value - 2;
2897 phaseinc = pi_value;
2898 }
2899
2900 /* This should not happen with any sane values */
2901 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2902 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2904 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2905
2906 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2907 crtc->mode.clock,
2908 auxdiv,
2909 divsel,
2910 phasedir,
2911 phaseinc);
2912
2913 /* Program SSCDIVINTPHASE6 */
2914 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2915 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2916 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2917 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2918 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2919 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2920 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2921
2922 intel_sbi_write(dev_priv,
2923 SBI_SSCDIVINTPHASE6,
2924 temp);
2925
2926 /* Program SSCAUXDIV */
2927 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2928 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2929 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2930 intel_sbi_write(dev_priv,
2931 SBI_SSCAUXDIV6,
2932 temp);
2933
2934
2935 /* Enable modulator and associated divider */
2936 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2937 temp &= ~SBI_SSCCTL_DISABLE;
2938 intel_sbi_write(dev_priv,
2939 SBI_SSCCTL6,
2940 temp);
2941
2942 /* Wait for initialization time */
2943 udelay(24);
2944
2945 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2946}
2947
f67a559d
JB		 2948/*
2949 * Enable PCH resources required for PCH ports:
2950 * - PCH PLLs
2951 * - FDI training & RX/TX
2952 * - update transcoder timings
2953 * - DP transcoding bits
2954 * - transcoder
2955 */
2956static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2957{
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2961 int pipe = intel_crtc->pipe;
ee7b9f93 2962 u32 reg, temp;
2c07245f 2963
e7e164db
CW		 2964 assert_transcoder_disabled(dev_priv, pipe);
2965
c98e9dcf 2966 /* For PCH output, training FDI link */
674cf967 2967 dev_priv->display.fdi_link_train(crtc);
2c07245f 2968
6f13b7b5
CW		 2969 intel_enable_pch_pll(intel_crtc);
2970
e615efe4
ED		 2971 if (HAS_PCH_LPT(dev)) {
2972 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2973 lpt_program_iclkip(crtc);
2974 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2975 u32 sel;
4b645f14 2976
c98e9dcf 2977 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2978 switch (pipe) {
2979 default:
2980 case 0:
2981 temp |= TRANSA_DPLL_ENABLE;
2982 sel = TRANSA_DPLLB_SEL;
2983 break;
2984 case 1:
2985 temp |= TRANSB_DPLL_ENABLE;
2986 sel = TRANSB_DPLLB_SEL;
2987 break;
2988 case 2:
2989 temp |= TRANSC_DPLL_ENABLE;
2990 sel = TRANSC_DPLLB_SEL;
2991 break;
d64311ab 2992 }
ee7b9f93
JB		 2993 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2994 temp |= sel;
2995 else
2996 temp &= ~sel;
c98e9dcf 2997 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2998 }
5eddb70b 2999
d9b6cb56
JB		 3000 /* set transcoder timing, panel must allow it */
3001 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3002 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3003 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3004 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3005
5eddb70b
CW		 3006 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3007 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3008 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3009 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3010
f57e1e3a
ED		 3011 if (!IS_HASWELL(dev))
3012 intel_fdi_normal_train(crtc);
5e84e1a4 3013
c98e9dcf
JB		 3014 /* For PCH DP, enable TRANS_DP_CTL */
3015 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3016 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3017 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3018 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3019 reg = TRANS_DP_CTL(pipe);
3020 temp = I915_READ(reg);
3021 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3022 TRANS_DP_SYNC_MASK |
3023 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3024 temp |= (TRANS_DP_OUTPUT_ENABLE |
3025 TRANS_DP_ENH_FRAMING);
9325c9f0 3026 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3027
3028 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3029 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3030 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3031 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3032
3033 switch (intel_trans_dp_port_sel(crtc)) {
3034 case PCH_DP_B:
5eddb70b 3035 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3036 break;
3037 case PCH_DP_C:
5eddb70b 3038 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3039 break;
3040 case PCH_DP_D:
5eddb70b 3041 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3042 break;
3043 default:
3044 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3045 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3046 break;
32f9d658 3047 }
2c07245f 3048
5eddb70b 3049 I915_WRITE(reg, temp);
6be4a607 3050 }
b52eb4dc 3051
040484af 3052 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3053}
3054
ee7b9f93
JB		 3055static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3056{
3057 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3058
3059 if (pll == NULL)
3060 return;
3061
3062 if (pll->refcount == 0) {
3063 WARN(1, "bad PCH PLL refcount\n");
3064 return;
3065 }
3066
3067 --pll->refcount;
3068 intel_crtc->pch_pll = NULL;
3069}
3070
3071static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3072{
3073 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3074 struct intel_pch_pll *pll;
3075 int i;
3076
3077 pll = intel_crtc->pch_pll;
3078 if (pll) {
3079 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3080 intel_crtc->base.base.id, pll->pll_reg);
3081 goto prepare;
3082 }
3083
98b6bd99
DV		 3084 if (HAS_PCH_IBX(dev_priv->dev)) {
3085 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3086 i = intel_crtc->pipe;
3087 pll = &dev_priv->pch_plls[i];
3088
3089 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3090 intel_crtc->base.base.id, pll->pll_reg);
3091
3092 goto found;
3093 }
3094
ee7b9f93
JB		 3095 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3096 pll = &dev_priv->pch_plls[i];
3097
3098 /* Only want to check enabled timings first */
3099 if (pll->refcount == 0)
3100 continue;
3101
3102 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3103 fp == I915_READ(pll->fp0_reg)) {
3104 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3105 intel_crtc->base.base.id,
3106 pll->pll_reg, pll->refcount, pll->active);
3107
3108 goto found;
3109 }
3110 }
3111
3112 /* Ok no matching timings, maybe there's a free one? */
3113 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3114 pll = &dev_priv->pch_plls[i];
3115 if (pll->refcount == 0) {
3116 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3117 intel_crtc->base.base.id, pll->pll_reg);
3118 goto found;
3119 }
3120 }
3121
3122 return NULL;
3123
3124found:
3125 intel_crtc->pch_pll = pll;
3126 pll->refcount++;
3127 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3128prepare: /* separate function? */
3129 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3130
e04c7350
CW		 3131 /* Wait for the clocks to stabilize before rewriting the regs */
3132 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3133 POSTING_READ(pll->pll_reg);
3134 udelay(150);
e04c7350
CW		 3135
3136 I915_WRITE(pll->fp0_reg, fp);
3137 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3138 pll->on = false;
3139 return pll;
3140}
3141
d4270e57
JB		 3142void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3143{
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3146 u32 temp;
3147
3148 temp = I915_READ(dslreg);
3149 udelay(500);
3150 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3151 /* Without this, mode sets may fail silently on FDI */
3152 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3153 udelay(250);
3154 I915_WRITE(tc2reg, 0);
3155 if (wait_for(I915_READ(dslreg) != temp, 5))
3156 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3157 }
3158}
3159
f67a559d
JB		 3160static void ironlake_crtc_enable(struct drm_crtc *crtc)
3161{
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3165 struct intel_encoder *encoder;
f67a559d
JB		 3166 int pipe = intel_crtc->pipe;
3167 int plane = intel_crtc->plane;
3168 u32 temp;
3169 bool is_pch_port;
3170
08a48469
DV		 3171 WARN_ON(!crtc->enabled);
3172
f67a559d
JB		 3173 if (intel_crtc->active)
3174 return;
3175
3176 intel_crtc->active = true;
3177 intel_update_watermarks(dev);
3178
3179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3180 temp = I915_READ(PCH_LVDS);
3181 if ((temp & LVDS_PORT_EN) == 0)
3182 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3183 }
3184
3185 is_pch_port = intel_crtc_driving_pch(crtc);
3186
46b6f814 3187 if (is_pch_port) {
88cefb6c 3188 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3189 } else {
3190 assert_fdi_tx_disabled(dev_priv, pipe);
3191 assert_fdi_rx_disabled(dev_priv, pipe);
3192 }
f67a559d 3193
bf49ec8c
DV		 3194 for_each_encoder_on_crtc(dev, crtc, encoder)
3195 if (encoder->pre_enable)
3196 encoder->pre_enable(encoder);
3197
f67a559d
JB		 3198 /* Enable panel fitting for LVDS */
3199 if (dev_priv->pch_pf_size &&
3200 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3201 /* Force use of hard-coded filter coefficients
3202 * as some pre-programmed values are broken,
3203 * e.g. x201.
3204 */
9db4a9c7
JB		 3205 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3206 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3207 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3208 }
3209
9c54c0dd
JB		 3210 /*
3211 * On ILK+ LUT must be loaded before the pipe is running but with
3212 * clocks enabled
3213 */
3214 intel_crtc_load_lut(crtc);
3215
f67a559d
JB		 3216 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3217 intel_enable_plane(dev_priv, plane, pipe);
3218
3219 if (is_pch_port)
3220 ironlake_pch_enable(crtc);
c98e9dcf 3221
d1ebd816 3222 mutex_lock(&dev->struct_mutex);
bed4a673 3223 intel_update_fbc(dev);
d1ebd816
BW		 3224 mutex_unlock(&dev->struct_mutex);
3225
6b383a7f 3226 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3227
fa5c73b1
DV		 3228 for_each_encoder_on_crtc(dev, crtc, encoder)
3229 encoder->enable(encoder);
61b77ddd
DV		 3230
3231 if (HAS_PCH_CPT(dev))
3232 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3233}
3234
3235static void ironlake_crtc_disable(struct drm_crtc *crtc)
3236{
3237 struct drm_device *dev = crtc->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3240 struct intel_encoder *encoder;
6be4a607
JB		 3241 int pipe = intel_crtc->pipe;
3242 int plane = intel_crtc->plane;
5eddb70b 3243 u32 reg, temp;
b52eb4dc 3244
ef9c3aee 3245
f7abfe8b
CW		 3246 if (!intel_crtc->active)
3247 return;
3248
ea9d758d
DV		 3249 for_each_encoder_on_crtc(dev, crtc, encoder)
3250 encoder->disable(encoder);
3251
e6c3a2a6 3252 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3253 drm_vblank_off(dev, pipe);
6b383a7f 3254 intel_crtc_update_cursor(crtc, false);
5eddb70b 3255
b24e7179 3256 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3257
973d04f9
CW		 3258 if (dev_priv->cfb_plane == plane)
3259 intel_disable_fbc(dev);
2c07245f 3260
b24e7179 3261 intel_disable_pipe(dev_priv, pipe);
32f9d658 3262
6be4a607 3263 /* Disable PF */
9db4a9c7
JB		 3264 I915_WRITE(PF_CTL(pipe), 0);
3265 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3266
bf49ec8c
DV		 3267 for_each_encoder_on_crtc(dev, crtc, encoder)
3268 if (encoder->post_disable)
3269 encoder->post_disable(encoder);
3270
0fc932b8 3271 ironlake_fdi_disable(crtc);
2c07245f 3272
040484af 3273 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3274
6be4a607
JB		 3275 if (HAS_PCH_CPT(dev)) {
3276 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3277 reg = TRANS_DP_CTL(pipe);
3278 temp = I915_READ(reg);
3279 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3280 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3281 I915_WRITE(reg, temp);
6be4a607
JB		 3282
3283 /* disable DPLL_SEL */
3284 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3285 switch (pipe) {
3286 case 0:
d64311ab 3287 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3288 break;
3289 case 1:
6be4a607 3290 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3291 break;
3292 case 2:
4b645f14 3293 /* C shares PLL A or B */
d64311ab 3294 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3295 break;
3296 default:
3297 BUG(); /* wtf */
3298 }
6be4a607 3299 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3300 }
e3421a18 3301
6be4a607 3302 /* disable PCH DPLL */
ee7b9f93 3303 intel_disable_pch_pll(intel_crtc);
8db9d77b 3304
88cefb6c 3305 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3306
f7abfe8b 3307 intel_crtc->active = false;
6b383a7f 3308 intel_update_watermarks(dev);
d1ebd816
BW		 3309
3310 mutex_lock(&dev->struct_mutex);
6b383a7f 3311 intel_update_fbc(dev);
d1ebd816 3312 mutex_unlock(&dev->struct_mutex);
6be4a607 3313}
1b3c7a47 3314
ee7b9f93
JB		 3315static void ironlake_crtc_off(struct drm_crtc *crtc)
3316{
3317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3318 intel_put_pch_pll(intel_crtc);
3319}
3320
02e792fb
DV		 3321static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3322{
02e792fb 3323 if (!enable && intel_crtc->overlay) {
23f09ce3 3324 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3325 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3326
23f09ce3 3327 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3328 dev_priv->mm.interruptible = false;
3329 (void) intel_overlay_switch_off(intel_crtc->overlay);
3330 dev_priv->mm.interruptible = true;
23f09ce3 3331 mutex_unlock(&dev->struct_mutex);
02e792fb 3332 }
02e792fb 3333
5dcdbcb0
CW		 3334 /* Let userspace switch the overlay on again. In most cases userspace
3335 * has to recompute where to put it anyway.
3336 */
02e792fb
DV		 3337}
3338
0b8765c6 3339static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3340{
3341 struct drm_device *dev = crtc->dev;
79e53945
JB		 3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3344 struct intel_encoder *encoder;
79e53945 3345 int pipe = intel_crtc->pipe;
80824003 3346 int plane = intel_crtc->plane;
79e53945 3347
08a48469
DV		 3348 WARN_ON(!crtc->enabled);
3349
f7abfe8b
CW		 3350 if (intel_crtc->active)
3351 return;
3352
3353 intel_crtc->active = true;
6b383a7f
CW		 3354 intel_update_watermarks(dev);
3355
63d7bbe9 3356 intel_enable_pll(dev_priv, pipe);
040484af 3357 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3358 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3359
0b8765c6 3360 intel_crtc_load_lut(crtc);
bed4a673 3361 intel_update_fbc(dev);
79e53945 3362
0b8765c6
JB		 3363 /* Give the overlay scaler a chance to enable if it's on this pipe */
3364 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3365 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3366
fa5c73b1
DV		 3367 for_each_encoder_on_crtc(dev, crtc, encoder)
3368 encoder->enable(encoder);
0b8765c6 3369}
79e53945 3370
0b8765c6
JB		 3371static void i9xx_crtc_disable(struct drm_crtc *crtc)
3372{
3373 struct drm_device *dev = crtc->dev;
3374 struct drm_i915_private *dev_priv = dev->dev_private;
3375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3376 struct intel_encoder *encoder;
0b8765c6
JB		 3377 int pipe = intel_crtc->pipe;
3378 int plane = intel_crtc->plane;
b690e96c 3379
ef9c3aee 3380
f7abfe8b
CW		 3381 if (!intel_crtc->active)
3382 return;
3383
ea9d758d
DV		 3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 encoder->disable(encoder);
3386
0b8765c6 3387 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3388 intel_crtc_wait_for_pending_flips(crtc);
3389 drm_vblank_off(dev, pipe);
0b8765c6 3390 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3391 intel_crtc_update_cursor(crtc, false);
0b8765c6 3392
973d04f9
CW		 3393 if (dev_priv->cfb_plane == plane)
3394 intel_disable_fbc(dev);
79e53945 3395
b24e7179 3396 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3397 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3398 intel_disable_pll(dev_priv, pipe);
0b8765c6 3399
f7abfe8b 3400 intel_crtc->active = false;
6b383a7f
CW		 3401 intel_update_fbc(dev);
3402 intel_update_watermarks(dev);
0b8765c6
JB		 3403}
3404
ee7b9f93
JB		 3405static void i9xx_crtc_off(struct drm_crtc *crtc)
3406{
3407}
3408
976f8a20
DV		 3409static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3410 bool enabled)
2c07245f
ZW		 3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_master_private *master_priv;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415 int pipe = intel_crtc->pipe;
79e53945
JB		 3416
3417 if (!dev->primary->master)
3418 return;
3419
3420 master_priv = dev->primary->master->driver_priv;
3421 if (!master_priv->sarea_priv)
3422 return;
3423
79e53945
JB		 3424 switch (pipe) {
3425 case 0:
3426 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3427 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3428 break;
3429 case 1:
3430 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3431 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3432 break;
3433 default:
9db4a9c7 3434 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3435 break;
3436 }
79e53945
JB		 3437}
3438
976f8a20
DV		 3439/**
3440 * Sets the power management mode of the pipe and plane.
3441 */
3442void intel_crtc_update_dpms(struct drm_crtc *crtc)
3443{
3444 struct drm_device *dev = crtc->dev;
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 struct intel_encoder *intel_encoder;
3447 bool enable = false;
3448
3449 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3450 enable |= intel_encoder->connectors_active;
3451
3452 if (enable)
3453 dev_priv->display.crtc_enable(crtc);
3454 else
3455 dev_priv->display.crtc_disable(crtc);
3456
3457 intel_crtc_update_sarea(crtc, enable);
3458}
3459
3460static void intel_crtc_noop(struct drm_crtc *crtc)
3461{
3462}
3463
cdd59983
CW		 3464static void intel_crtc_disable(struct drm_crtc *crtc)
3465{
cdd59983 3466 struct drm_device *dev = crtc->dev;
976f8a20 3467 struct drm_connector *connector;
ee7b9f93 3468 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3469
976f8a20
DV		 3470 /* crtc should still be enabled when we disable it. */
3471 WARN_ON(!crtc->enabled);
3472
3473 dev_priv->display.crtc_disable(crtc);
3474 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3475 dev_priv->display.off(crtc);
3476
931872fc
CW		 3477 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3478 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3479
3480 if (crtc->fb) {
3481 mutex_lock(&dev->struct_mutex);
1690e1eb 3482 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3483 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3484 crtc->fb = NULL;
3485 }
3486
3487 /* Update computed state. */
3488 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3489 if (!connector->encoder || !connector->encoder->crtc)
3490 continue;
3491
3492 if (connector->encoder->crtc != crtc)
3493 continue;
3494
3495 connector->dpms = DRM_MODE_DPMS_OFF;
3496 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3497 }
3498}
3499
a261b246 3500void intel_modeset_disable(struct drm_device *dev)
79e53945 3501{
a261b246
DV		 3502 struct drm_crtc *crtc;
3503
3504 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3505 if (crtc->enabled)
3506 intel_crtc_disable(crtc);
3507 }
79e53945
JB		 3508}
3509
1f703855 3510void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3511{
7e7d76c3
JB		 3512}
3513
ea5b213a 3514void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3515{
4ef69c7a 3516 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3517
ea5b213a
CW		 3518 drm_encoder_cleanup(encoder);
3519 kfree(intel_encoder);
7e7d76c3
JB		 3520}
3521
5ab432ef
DV		 3522/* Simple dpms helper for encodres with just one connector, no cloning and only
3523 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3524 * state of the entire output pipe. */
3525void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3526{
5ab432ef
DV		 3527 if (mode == DRM_MODE_DPMS_ON) {
3528 encoder->connectors_active = true;
3529
b2cabb0e 3530 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3531 } else {
3532 encoder->connectors_active = false;
3533
b2cabb0e 3534 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3535 }
79e53945
JB		 3536}
3537
0a91ca29
DV		 3538/* Cross check the actual hw state with our own modeset state tracking (and it's
3539 * internal consistency). */
b980514c 3540static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3541{
0a91ca29
DV		 3542 if (connector->get_hw_state(connector)) {
3543 struct intel_encoder *encoder = connector->encoder;
3544 struct drm_crtc *crtc;
3545 bool encoder_enabled;
3546 enum pipe pipe;
3547
3548 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3549 connector->base.base.id,
3550 drm_get_connector_name(&connector->base));
3551
3552 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3553 "wrong connector dpms state\n");
3554 WARN(connector->base.encoder != &encoder->base,
3555 "active connector not linked to encoder\n");
3556 WARN(!encoder->connectors_active,
3557 "encoder->connectors_active not set\n");
3558
3559 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3560 WARN(!encoder_enabled, "encoder not enabled\n");
3561 if (WARN_ON(!encoder->base.crtc))
3562 return;
3563
3564 crtc = encoder->base.crtc;
3565
3566 WARN(!crtc->enabled, "crtc not enabled\n");
3567 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3568 WARN(pipe != to_intel_crtc(crtc)->pipe,
3569 "encoder active on the wrong pipe\n");
3570 }
79e53945
JB		 3571}
3572
5ab432ef
DV		 3573/* Even simpler default implementation, if there's really no special case to
3574 * consider. */
3575void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3576{
5ab432ef 3577 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3578
5ab432ef
DV		 3579 /* All the simple cases only support two dpms states. */
3580 if (mode != DRM_MODE_DPMS_ON)
3581 mode = DRM_MODE_DPMS_OFF;
d4270e57 3582
5ab432ef
DV		 3583 if (mode == connector->dpms)
3584 return;
3585
3586 connector->dpms = mode;
3587
3588 /* Only need to change hw state when actually enabled */
3589 if (encoder->base.crtc)
3590 intel_encoder_dpms(encoder, mode);
3591 else
8af6cf88 3592 WARN_ON(encoder->connectors_active != false);
0a91ca29 3593
b980514c 3594 intel_modeset_check_state(connector->dev);
79e53945
JB		 3595}
3596
f0947c37
DV		 3597/* Simple connector->get_hw_state implementation for encoders that support only
3598 * one connector and no cloning and hence the encoder state determines the state
3599 * of the connector. */
3600bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3601{
24929352 3602 enum pipe pipe = 0;
f0947c37 3603 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3604
f0947c37 3605 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3606}
3607
79e53945 3608static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3609 const struct drm_display_mode *mode,
79e53945
JB		 3610 struct drm_display_mode *adjusted_mode)
3611{
2c07245f 3612 struct drm_device *dev = crtc->dev;
89749350 3613
bad720ff 3614 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3615 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3616 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3617 return false;
2c07245f 3618 }
89749350 3619
f9bef081
DV		 3620 /* All interlaced capable intel hw wants timings in frames. Note though
3621 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3622 * timings, so we need to be careful not to clobber these.*/
3623 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3624 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3625
44f46b42
CW		 3626 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3627 * with a hsync front porch of 0.
3628 */
3629 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3630 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3631 return false;
3632
79e53945
JB		 3633 return true;
3634}
3635
25eb05fc
JB		 3636static int valleyview_get_display_clock_speed(struct drm_device *dev)
3637{
3638 return 400000; /* FIXME */
3639}
3640
e70236a8
JB		 3641static int i945_get_display_clock_speed(struct drm_device *dev)
3642{
3643 return 400000;
3644}
79e53945 3645
e70236a8 3646static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3647{
e70236a8
JB		 3648 return 333000;
3649}
79e53945 3650
e70236a8
JB		 3651static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3652{
3653 return 200000;
3654}
79e53945 3655
e70236a8
JB		 3656static int i915gm_get_display_clock_speed(struct drm_device *dev)
3657{
3658 u16 gcfgc = 0;
79e53945 3659
e70236a8
JB		 3660 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3661
3662 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3663 return 133000;
3664 else {
3665 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3666 case GC_DISPLAY_CLOCK_333_MHZ:
3667 return 333000;
3668 default:
3669 case GC_DISPLAY_CLOCK_190_200_MHZ:
3670 return 190000;
79e53945 3671 }
e70236a8
JB		 3672 }
3673}
3674
3675static int i865_get_display_clock_speed(struct drm_device *dev)
3676{
3677 return 266000;
3678}
3679
3680static int i855_get_display_clock_speed(struct drm_device *dev)
3681{
3682 u16 hpllcc = 0;
3683 /* Assume that the hardware is in the high speed state. This
3684 * should be the default.
3685 */
3686 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3687 case GC_CLOCK_133_200:
3688 case GC_CLOCK_100_200:
3689 return 200000;
3690 case GC_CLOCK_166_250:
3691 return 250000;
3692 case GC_CLOCK_100_133:
79e53945 3693 return 133000;
e70236a8 3694 }
79e53945 3695
e70236a8
JB		 3696 /* Shouldn't happen */
3697 return 0;
3698}
79e53945 3699
e70236a8
JB		 3700static int i830_get_display_clock_speed(struct drm_device *dev)
3701{
3702 return 133000;
79e53945
JB		 3703}
3704
2c07245f
ZW		 3705struct fdi_m_n {
3706 u32 tu;
3707 u32 gmch_m;
3708 u32 gmch_n;
3709 u32 link_m;
3710 u32 link_n;
3711};
3712
3713static void
3714fdi_reduce_ratio(u32 *num, u32 *den)
3715{
3716 while (*num > 0xffffff || *den > 0xffffff) {
3717 *num >>= 1;
3718 *den >>= 1;
3719 }
3720}
3721
2c07245f 3722static void
f2b115e6
AJ		 3723ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3724 int link_clock, struct fdi_m_n *m_n)
2c07245f 3725{
2c07245f
ZW		 3726 m_n->tu = 64; /* default size */
3727
22ed1113
CW		 3728 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3729 m_n->gmch_m = bits_per_pixel * pixel_clock;
3730 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3731 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3732
22ed1113
CW		 3733 m_n->link_m = pixel_clock;
3734 m_n->link_n = link_clock;
2c07245f
ZW		 3735 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3736}
3737
a7615030
CW		 3738static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3739{
72bbe58c
KP		 3740 if (i915_panel_use_ssc >= 0)
3741 return i915_panel_use_ssc != 0;
3742 return dev_priv->lvds_use_ssc
435793df 3743 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3744}
3745
5a354204
JB		 3746/**
3747 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3748 * @crtc: CRTC structure
3b5c78a3 3749 * @mode: requested mode
5a354204
JB		 3750 *
3751 * A pipe may be connected to one or more outputs. Based on the depth of the
3752 * attached framebuffer, choose a good color depth to use on the pipe.
3753 *
3754 * If possible, match the pipe depth to the fb depth. In some cases, this
3755 * isn't ideal, because the connected output supports a lesser or restricted
3756 * set of depths. Resolve that here:
3757 * LVDS typically supports only 6bpc, so clamp down in that case
3758 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3759 * Displays may support a restricted set as well, check EDID and clamp as
3760 * appropriate.
3b5c78a3 3761 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3762 *
3763 * RETURNS:
3764 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3765 * true if they don't match).
3766 */
3767static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3768 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3769 unsigned int *pipe_bpp,
3770 struct drm_display_mode *mode)
5a354204
JB		 3771{
3772 struct drm_device *dev = crtc->dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3774 struct drm_connector *connector;
6c2b7c12 3775 struct intel_encoder *intel_encoder;
5a354204
JB		 3776 unsigned int display_bpc = UINT_MAX, bpc;
3777
3778 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3779 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3780
3781 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3782 unsigned int lvds_bpc;
3783
3784 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3785 LVDS_A3_POWER_UP)
3786 lvds_bpc = 8;
3787 else
3788 lvds_bpc = 6;
3789
3790 if (lvds_bpc < display_bpc) {
82820490 3791 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3792 display_bpc = lvds_bpc;
3793 }
3794 continue;
3795 }
3796
5a354204
JB		 3797 /* Not one of the known troublemakers, check the EDID */
3798 list_for_each_entry(connector, &dev->mode_config.connector_list,
3799 head) {
6c2b7c12 3800 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3801 continue;
3802
62ac41a6
JB		 3803 /* Don't use an invalid EDID bpc value */
3804 if (connector->display_info.bpc &&
3805 connector->display_info.bpc < display_bpc) {
82820490 3806 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3807 display_bpc = connector->display_info.bpc;
3808 }
3809 }
3810
3811 /*
3812 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3813 * through, clamp it down. (Note: >12bpc will be caught below.)
3814 */
3815 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3816 if (display_bpc > 8 && display_bpc < 12) {
82820490 3817 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3818 display_bpc = 12;
3819 } else {
82820490 3820 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3821 display_bpc = 8;
3822 }
3823 }
3824 }
3825
3b5c78a3
AJ		 3826 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3827 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3828 display_bpc = 6;
3829 }
3830
5a354204
JB		 3831 /*
3832 * We could just drive the pipe at the highest bpc all the time and
3833 * enable dithering as needed, but that costs bandwidth. So choose
3834 * the minimum value that expresses the full color range of the fb but
3835 * also stays within the max display bpc discovered above.
3836 */
3837
94352cf9 3838 switch (fb->depth) {
5a354204
JB		 3839 case 8:
3840 bpc = 8; /* since we go through a colormap */
3841 break;
3842 case 15:
3843 case 16:
3844 bpc = 6; /* min is 18bpp */
3845 break;
3846 case 24:
578393cd 3847 bpc = 8;
5a354204
JB		 3848 break;
3849 case 30:
578393cd 3850 bpc = 10;
5a354204
JB		 3851 break;
3852 case 48:
578393cd 3853 bpc = 12;
5a354204
JB		 3854 break;
3855 default:
3856 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3857 bpc = min((unsigned int)8, display_bpc);
3858 break;
3859 }
3860
578393cd
KP		 3861 display_bpc = min(display_bpc, bpc);
3862
82820490
AJ		 3863 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3864 bpc, display_bpc);
5a354204 3865
578393cd 3866 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3867
3868 return display_bpc != bpc;
3869}
3870
a0c4da24
JB		 3871static int vlv_get_refclk(struct drm_crtc *crtc)
3872{
3873 struct drm_device *dev = crtc->dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875 int refclk = 27000; /* for DP & HDMI */
3876
3877 return 100000; /* only one validated so far */
3878
3879 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3880 refclk = 96000;
3881 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3882 if (intel_panel_use_ssc(dev_priv))
3883 refclk = 100000;
3884 else
3885 refclk = 96000;
3886 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3887 refclk = 100000;
3888 }
3889
3890 return refclk;
3891}
3892
c65d77d8
JB		 3893static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3894{
3895 struct drm_device *dev = crtc->dev;
3896 struct drm_i915_private *dev_priv = dev->dev_private;
3897 int refclk;
3898
a0c4da24
JB		 3899 if (IS_VALLEYVIEW(dev)) {
3900 refclk = vlv_get_refclk(crtc);
3901 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3902 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3903 refclk = dev_priv->lvds_ssc_freq * 1000;
3904 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3905 refclk / 1000);
3906 } else if (!IS_GEN2(dev)) {
3907 refclk = 96000;
3908 } else {
3909 refclk = 48000;
3910 }
3911
3912 return refclk;
3913}
3914
3915static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3916 intel_clock_t *clock)
3917{
3918 /* SDVO TV has fixed PLL values depend on its clock range,
3919 this mirrors vbios setting. */
3920 if (adjusted_mode->clock >= 100000
3921 && adjusted_mode->clock < 140500) {
3922 clock->p1 = 2;
3923 clock->p2 = 10;
3924 clock->n = 3;
3925 clock->m1 = 16;
3926 clock->m2 = 8;
3927 } else if (adjusted_mode->clock >= 140500
3928 && adjusted_mode->clock <= 200000) {
3929 clock->p1 = 1;
3930 clock->p2 = 10;
3931 clock->n = 6;
3932 clock->m1 = 12;
3933 clock->m2 = 8;
3934 }
3935}
3936
a7516a05
JB		 3937static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3938 intel_clock_t *clock,
3939 intel_clock_t *reduced_clock)
3940{
3941 struct drm_device *dev = crtc->dev;
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944 int pipe = intel_crtc->pipe;
3945 u32 fp, fp2 = 0;
3946
3947 if (IS_PINEVIEW(dev)) {
3948 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3949 if (reduced_clock)
3950 fp2 = (1 << reduced_clock->n) << 16 |
3951 reduced_clock->m1 << 8 | reduced_clock->m2;
3952 } else {
3953 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3954 if (reduced_clock)
3955 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3956 reduced_clock->m2;
3957 }
3958
3959 I915_WRITE(FP0(pipe), fp);
3960
3961 intel_crtc->lowfreq_avail = false;
3962 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3963 reduced_clock && i915_powersave) {
3964 I915_WRITE(FP1(pipe), fp2);
3965 intel_crtc->lowfreq_avail = true;
3966 } else {
3967 I915_WRITE(FP1(pipe), fp);
3968 }
3969}
3970
93e537a1
DV		 3971static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3972 struct drm_display_mode *adjusted_mode)
3973{
3974 struct drm_device *dev = crtc->dev;
3975 struct drm_i915_private *dev_priv = dev->dev_private;
3976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3977 int pipe = intel_crtc->pipe;
284d5df5 3978 u32 temp;
93e537a1
DV		 3979
3980 temp = I915_READ(LVDS);
3981 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3982 if (pipe == 1) {
3983 temp |= LVDS_PIPEB_SELECT;
3984 } else {
3985 temp &= ~LVDS_PIPEB_SELECT;
3986 }
3987 /* set the corresponsding LVDS_BORDER bit */
3988 temp |= dev_priv->lvds_border_bits;
3989 /* Set the B0-B3 data pairs corresponding to whether we're going to
3990 * set the DPLLs for dual-channel mode or not.
3991 */
3992 if (clock->p2 == 7)
3993 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3994 else
3995 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3996
3997 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3998 * appropriately here, but we need to look more thoroughly into how
3999 * panels behave in the two modes.
4000 */
4001 /* set the dithering flag on LVDS as needed */
4002 if (INTEL_INFO(dev)->gen >= 4) {
4003 if (dev_priv->lvds_dither)
4004 temp |= LVDS_ENABLE_DITHER;
4005 else
4006 temp &= ~LVDS_ENABLE_DITHER;
4007 }
284d5df5 4008 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4009 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4010 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4011 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4012 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4013 I915_WRITE(LVDS, temp);
4014}
4015
a0c4da24
JB		 4016static void vlv_update_pll(struct drm_crtc *crtc,
4017 struct drm_display_mode *mode,
4018 struct drm_display_mode *adjusted_mode,
4019 intel_clock_t *clock, intel_clock_t *reduced_clock,
4020 int refclk, int num_connectors)
4021{
4022 struct drm_device *dev = crtc->dev;
4023 struct drm_i915_private *dev_priv = dev->dev_private;
4024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4025 int pipe = intel_crtc->pipe;
4026 u32 dpll, mdiv, pdiv;
4027 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4028 bool is_hdmi;
4029
4030 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4031
4032 bestn = clock->n;
4033 bestm1 = clock->m1;
4034 bestm2 = clock->m2;
4035 bestp1 = clock->p1;
4036 bestp2 = clock->p2;
4037
4038 /* Enable DPIO clock input */
4039 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4040 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4041 I915_WRITE(DPLL(pipe), dpll);
4042 POSTING_READ(DPLL(pipe));
4043
4044 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4045 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4046 mdiv |= ((bestn << DPIO_N_SHIFT));
4047 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4048 mdiv |= (1 << DPIO_K_SHIFT);
4049 mdiv |= DPIO_ENABLE_CALIBRATION;
4050 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4051
4052 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4053
4054 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4055 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4056 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4057 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4058
4059 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4060
4061 dpll |= DPLL_VCO_ENABLE;
4062 I915_WRITE(DPLL(pipe), dpll);
4063 POSTING_READ(DPLL(pipe));
4064 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4065 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4066
4067 if (is_hdmi) {
4068 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4069
4070 if (temp > 1)
4071 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4072 else
4073 temp = 0;
4074
4075 I915_WRITE(DPLL_MD(pipe), temp);
4076 POSTING_READ(DPLL_MD(pipe));
4077 }
4078
4079 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4080}
4081
eb1cbe48
DV		 4082static void i9xx_update_pll(struct drm_crtc *crtc,
4083 struct drm_display_mode *mode,
4084 struct drm_display_mode *adjusted_mode,
4085 intel_clock_t *clock, intel_clock_t *reduced_clock,
4086 int num_connectors)
4087{
4088 struct drm_device *dev = crtc->dev;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4091 int pipe = intel_crtc->pipe;
4092 u32 dpll;
4093 bool is_sdvo;
4094
4095 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4096 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4097
4098 dpll = DPLL_VGA_MODE_DIS;
4099
4100 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4101 dpll |= DPLLB_MODE_LVDS;
4102 else
4103 dpll |= DPLLB_MODE_DAC_SERIAL;
4104 if (is_sdvo) {
4105 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4106 if (pixel_multiplier > 1) {
4107 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4108 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4109 }
4110 dpll |= DPLL_DVO_HIGH_SPEED;
4111 }
4112 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4113 dpll |= DPLL_DVO_HIGH_SPEED;
4114
4115 /* compute bitmask from p1 value */
4116 if (IS_PINEVIEW(dev))
4117 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4118 else {
4119 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4120 if (IS_G4X(dev) && reduced_clock)
4121 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4122 }
4123 switch (clock->p2) {
4124 case 5:
4125 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4126 break;
4127 case 7:
4128 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4129 break;
4130 case 10:
4131 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4132 break;
4133 case 14:
4134 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4135 break;
4136 }
4137 if (INTEL_INFO(dev)->gen >= 4)
4138 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4139
4140 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4141 dpll |= PLL_REF_INPUT_TVCLKINBC;
4142 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4143 /* XXX: just matching BIOS for now */
4144 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4145 dpll |= 3;
4146 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4147 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4148 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4149 else
4150 dpll |= PLL_REF_INPUT_DREFCLK;
4151
4152 dpll |= DPLL_VCO_ENABLE;
4153 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4154 POSTING_READ(DPLL(pipe));
4155 udelay(150);
4156
4157 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4158 * This is an exception to the general rule that mode_set doesn't turn
4159 * things on.
4160 */
4161 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4162 intel_update_lvds(crtc, clock, adjusted_mode);
4163
4164 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4165 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4166
4167 I915_WRITE(DPLL(pipe), dpll);
4168
4169 /* Wait for the clocks to stabilize. */
4170 POSTING_READ(DPLL(pipe));
4171 udelay(150);
4172
4173 if (INTEL_INFO(dev)->gen >= 4) {
4174 u32 temp = 0;
4175 if (is_sdvo) {
4176 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4177 if (temp > 1)
4178 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4179 else
4180 temp = 0;
4181 }
4182 I915_WRITE(DPLL_MD(pipe), temp);
4183 } else {
4184 /* The pixel multiplier can only be updated once the
4185 * DPLL is enabled and the clocks are stable.
4186 *
4187 * So write it again.
4188 */
4189 I915_WRITE(DPLL(pipe), dpll);
4190 }
4191}
4192
4193static void i8xx_update_pll(struct drm_crtc *crtc,
4194 struct drm_display_mode *adjusted_mode,
4195 intel_clock_t *clock,
4196 int num_connectors)
4197{
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4201 int pipe = intel_crtc->pipe;
4202 u32 dpll;
4203
4204 dpll = DPLL_VGA_MODE_DIS;
4205
4206 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4208 } else {
4209 if (clock->p1 == 2)
4210 dpll |= PLL_P1_DIVIDE_BY_TWO;
4211 else
4212 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4213 if (clock->p2 == 4)
4214 dpll |= PLL_P2_DIVIDE_BY_4;
4215 }
4216
4217 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4218 /* XXX: just matching BIOS for now */
4219 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4220 dpll |= 3;
4221 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4222 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4223 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4224 else
4225 dpll |= PLL_REF_INPUT_DREFCLK;
4226
4227 dpll |= DPLL_VCO_ENABLE;
4228 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4229 POSTING_READ(DPLL(pipe));
4230 udelay(150);
4231
4232 I915_WRITE(DPLL(pipe), dpll);
4233
4234 /* Wait for the clocks to stabilize. */
4235 POSTING_READ(DPLL(pipe));
4236 udelay(150);
4237
4238 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4239 * This is an exception to the general rule that mode_set doesn't turn
4240 * things on.
4241 */
4242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4243 intel_update_lvds(crtc, clock, adjusted_mode);
4244
4245 /* The pixel multiplier can only be updated once the
4246 * DPLL is enabled and the clocks are stable.
4247 *
4248 * So write it again.
4249 */
4250 I915_WRITE(DPLL(pipe), dpll);
4251}
4252
f564048e
EA		 4253static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4254 struct drm_display_mode *mode,
4255 struct drm_display_mode *adjusted_mode,
4256 int x, int y,
94352cf9 4257 struct drm_framebuffer *fb)
79e53945
JB		 4258{
4259 struct drm_device *dev = crtc->dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4262 int pipe = intel_crtc->pipe;
80824003 4263 int plane = intel_crtc->plane;
c751ce4f 4264 int refclk, num_connectors = 0;
652c393a 4265 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4266 u32 dspcntr, pipeconf, vsyncshift;
4267 bool ok, has_reduced_clock = false, is_sdvo = false;
4268 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4269 struct intel_encoder *encoder;
d4906093 4270 const intel_limit_t *limit;
5c3b82e2 4271 int ret;
79e53945 4272
6c2b7c12 4273 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4274 switch (encoder->type) {
79e53945
JB		 4275 case INTEL_OUTPUT_LVDS:
4276 is_lvds = true;
4277 break;
4278 case INTEL_OUTPUT_SDVO:
7d57382e 4279 case INTEL_OUTPUT_HDMI:
79e53945 4280 is_sdvo = true;
5eddb70b 4281 if (encoder->needs_tv_clock)
e2f0ba97 4282 is_tv = true;
79e53945 4283 break;
79e53945
JB		 4284 case INTEL_OUTPUT_TVOUT:
4285 is_tv = true;
4286 break;
a4fc5ed6
KP		 4287 case INTEL_OUTPUT_DISPLAYPORT:
4288 is_dp = true;
4289 break;
79e53945 4290 }
43565a06 4291
c751ce4f 4292 num_connectors++;
79e53945
JB		 4293 }
4294
c65d77d8 4295 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4296
d4906093
ML		 4297 /*
4298 * Returns a set of divisors for the desired target clock with the given
4299 * refclk, or FALSE. The returned values represent the clock equation:
4300 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4301 */
1b894b59 4302 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4303 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4304 &clock);
79e53945
JB		 4305 if (!ok) {
4306 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4307 return -EINVAL;
79e53945
JB		 4308 }
4309
cda4b7d3 4310 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4311 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4312
ddc9003c 4313 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4314 /*
4315 * Ensure we match the reduced clock's P to the target clock.
4316 * If the clocks don't match, we can't switch the display clock
4317 * by using the FP0/FP1. In such case we will disable the LVDS
4318 * downclock feature.
4319 */
ddc9003c 4320 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4321 dev_priv->lvds_downclock,
4322 refclk,
cec2f356 4323 &clock,
5eddb70b 4324 &reduced_clock);
7026d4ac
ZW		 4325 }
4326
c65d77d8
JB		 4327 if (is_sdvo && is_tv)
4328 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4329
a7516a05
JB		 4330 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4331 &reduced_clock : NULL);
79e53945 4332
eb1cbe48
DV		 4333 if (IS_GEN2(dev))
4334 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4335 else if (IS_VALLEYVIEW(dev))
4336 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4337 refclk, num_connectors);
79e53945 4338 else
eb1cbe48
DV		 4339 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4340 has_reduced_clock ? &reduced_clock : NULL,
4341 num_connectors);
79e53945
JB		 4342
4343 /* setup pipeconf */
5eddb70b 4344 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4345
4346 /* Set up the display plane register */
4347 dspcntr = DISPPLANE_GAMMA_ENABLE;
4348
929c77fb
EA		 4349 if (pipe == 0)
4350 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4351 else
4352 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4353
a6c45cf0 4354 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4355 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4356 * core speed.
4357 *
4358 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4359 * pipe == 0 check?
4360 */
e70236a8
JB		 4361 if (mode->clock >
4362 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4363 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4364 else
5eddb70b 4365 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4366 }
4367
3b5c78a3
AJ		 4368 /* default to 8bpc */
4369 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4370 if (is_dp) {
4371 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4372 pipeconf |= PIPECONF_BPP_6 |
4373 PIPECONF_DITHER_EN |
4374 PIPECONF_DITHER_TYPE_SP;
4375 }
4376 }
4377
28c97730 4378 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4379 drm_mode_debug_printmodeline(mode);
4380
a7516a05
JB		 4381 if (HAS_PIPE_CXSR(dev)) {
4382 if (intel_crtc->lowfreq_avail) {
28c97730 4383 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4384 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4385 } else {
28c97730 4386 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4387 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4388 }
4389 }
4390
617cf884 4391 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4392 if (!IS_GEN2(dev) &&
4393 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4394 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4395 /* the chip adds 2 halflines automatically */
734b4157 4396 adjusted_mode->crtc_vtotal -= 1;
734b4157 4397 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4398 vsyncshift = adjusted_mode->crtc_hsync_start
4399 - adjusted_mode->crtc_htotal/2;
4400 } else {
617cf884 4401 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4402 vsyncshift = 0;
4403 }
4404
4405 if (!IS_GEN3(dev))
4406 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4407
5eddb70b
CW		 4408 I915_WRITE(HTOTAL(pipe),
4409 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4410 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4411 I915_WRITE(HBLANK(pipe),
4412 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4413 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4414 I915_WRITE(HSYNC(pipe),
4415 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4416 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4417
4418 I915_WRITE(VTOTAL(pipe),
4419 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4420 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4421 I915_WRITE(VBLANK(pipe),
4422 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4423 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4424 I915_WRITE(VSYNC(pipe),
4425 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4426 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4427
4428 /* pipesrc and dspsize control the size that is scaled from,
4429 * which should always be the user's requested size.
79e53945 4430 */
929c77fb
EA		 4431 I915_WRITE(DSPSIZE(plane),
4432 ((mode->vdisplay - 1) << 16) |
4433 (mode->hdisplay - 1));
4434 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4435 I915_WRITE(PIPESRC(pipe),
4436 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4437
f564048e
EA		 4438 I915_WRITE(PIPECONF(pipe), pipeconf);
4439 POSTING_READ(PIPECONF(pipe));
929c77fb 4440 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4441
4442 intel_wait_for_vblank(dev, pipe);
4443
f564048e
EA		 4444 I915_WRITE(DSPCNTR(plane), dspcntr);
4445 POSTING_READ(DSPCNTR(plane));
4446
94352cf9 4447 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4448
4449 intel_update_watermarks(dev);
4450
f564048e
EA		 4451 return ret;
4452}
4453
9fb526db
KP		 4454/*
4455 * Initialize reference clocks when the driver loads
4456 */
4457void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4458{
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4461 struct intel_encoder *encoder;
13d83a67
JB		 4462 u32 temp;
4463 bool has_lvds = false;
199e5d79
KP		 4464 bool has_cpu_edp = false;
4465 bool has_pch_edp = false;
4466 bool has_panel = false;
99eb6a01
KP		 4467 bool has_ck505 = false;
4468 bool can_ssc = false;
13d83a67
JB		 4469
4470 /* We need to take the global config into account */
199e5d79
KP		 4471 list_for_each_entry(encoder, &mode_config->encoder_list,
4472 base.head) {
4473 switch (encoder->type) {
4474 case INTEL_OUTPUT_LVDS:
4475 has_panel = true;
4476 has_lvds = true;
4477 break;
4478 case INTEL_OUTPUT_EDP:
4479 has_panel = true;
4480 if (intel_encoder_is_pch_edp(&encoder->base))
4481 has_pch_edp = true;
4482 else
4483 has_cpu_edp = true;
4484 break;
13d83a67
JB		 4485 }
4486 }
4487
99eb6a01
KP		 4488 if (HAS_PCH_IBX(dev)) {
4489 has_ck505 = dev_priv->display_clock_mode;
4490 can_ssc = has_ck505;
4491 } else {
4492 has_ck505 = false;
4493 can_ssc = true;
4494 }
4495
4496 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4497 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4498 has_ck505);
13d83a67
JB		 4499
4500 /* Ironlake: try to setup display ref clock before DPLL
4501 * enabling. This is only under driver's control after
4502 * PCH B stepping, previous chipset stepping should be
4503 * ignoring this setting.
4504 */
4505 temp = I915_READ(PCH_DREF_CONTROL);
4506 /* Always enable nonspread source */
4507 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4508
99eb6a01
KP		 4509 if (has_ck505)
4510 temp |= DREF_NONSPREAD_CK505_ENABLE;
4511 else
4512 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4513
199e5d79
KP		 4514 if (has_panel) {
4515 temp &= ~DREF_SSC_SOURCE_MASK;
4516 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4517
199e5d79 4518 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4519 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4520 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4521 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4522 } else
4523 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4524
4525 /* Get SSC going before enabling the outputs */
4526 I915_WRITE(PCH_DREF_CONTROL, temp);
4527 POSTING_READ(PCH_DREF_CONTROL);
4528 udelay(200);
4529
13d83a67
JB		 4530 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4531
4532 /* Enable CPU source on CPU attached eDP */
199e5d79 4533 if (has_cpu_edp) {
99eb6a01 4534 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4535 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4536 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4537 }
13d83a67
JB		 4538 else
4539 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4540 } else
4541 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4542
4543 I915_WRITE(PCH_DREF_CONTROL, temp);
4544 POSTING_READ(PCH_DREF_CONTROL);
4545 udelay(200);
4546 } else {
4547 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4548
4549 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4550
4551 /* Turn off CPU output */
4552 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4553
4554 I915_WRITE(PCH_DREF_CONTROL, temp);
4555 POSTING_READ(PCH_DREF_CONTROL);
4556 udelay(200);
4557
4558 /* Turn off the SSC source */
4559 temp &= ~DREF_SSC_SOURCE_MASK;
4560 temp |= DREF_SSC_SOURCE_DISABLE;
4561
4562 /* Turn off SSC1 */
4563 temp &= ~ DREF_SSC1_ENABLE;
4564
13d83a67
JB		 4565 I915_WRITE(PCH_DREF_CONTROL, temp);
4566 POSTING_READ(PCH_DREF_CONTROL);
4567 udelay(200);
4568 }
4569}
4570
d9d444cb
JB		 4571static int ironlake_get_refclk(struct drm_crtc *crtc)
4572{
4573 struct drm_device *dev = crtc->dev;
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 struct intel_encoder *encoder;
d9d444cb
JB		 4576 struct intel_encoder *edp_encoder = NULL;
4577 int num_connectors = 0;
4578 bool is_lvds = false;
4579
6c2b7c12 4580 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4581 switch (encoder->type) {
4582 case INTEL_OUTPUT_LVDS:
4583 is_lvds = true;
4584 break;
4585 case INTEL_OUTPUT_EDP:
4586 edp_encoder = encoder;
4587 break;
4588 }
4589 num_connectors++;
4590 }
4591
4592 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4593 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4594 dev_priv->lvds_ssc_freq);
4595 return dev_priv->lvds_ssc_freq * 1000;
4596 }
4597
4598 return 120000;
4599}
4600
c8203565
PZ		 4601static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4602 struct drm_display_mode *adjusted_mode,
4603 bool dither)
4604{
4605 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4607 int pipe = intel_crtc->pipe;
4608 uint32_t val;
4609
4610 val = I915_READ(PIPECONF(pipe));
4611
4612 val &= ~PIPE_BPC_MASK;
4613 switch (intel_crtc->bpp) {
4614 case 18:
4615 val |= PIPE_6BPC;
4616 break;
4617 case 24:
4618 val |= PIPE_8BPC;
4619 break;
4620 case 30:
4621 val |= PIPE_10BPC;
4622 break;
4623 case 36:
4624 val |= PIPE_12BPC;
4625 break;
4626 default:
4627 val |= PIPE_8BPC;
4628 break;
4629 }
4630
4631 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4632 if (dither)
4633 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4634
4635 val &= ~PIPECONF_INTERLACE_MASK;
4636 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4637 val |= PIPECONF_INTERLACED_ILK;
4638 else
4639 val |= PIPECONF_PROGRESSIVE;
4640
4641 I915_WRITE(PIPECONF(pipe), val);
4642 POSTING_READ(PIPECONF(pipe));
4643}
4644
6591c6e4
PZ		 4645static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4646 struct drm_display_mode *adjusted_mode,
4647 intel_clock_t *clock,
4648 bool *has_reduced_clock,
4649 intel_clock_t *reduced_clock)
4650{
4651 struct drm_device *dev = crtc->dev;
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 struct intel_encoder *intel_encoder;
4654 int refclk;
4655 const intel_limit_t *limit;
4656 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4657
4658 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4659 switch (intel_encoder->type) {
4660 case INTEL_OUTPUT_LVDS:
4661 is_lvds = true;
4662 break;
4663 case INTEL_OUTPUT_SDVO:
4664 case INTEL_OUTPUT_HDMI:
4665 is_sdvo = true;
4666 if (intel_encoder->needs_tv_clock)
4667 is_tv = true;
4668 break;
4669 case INTEL_OUTPUT_TVOUT:
4670 is_tv = true;
4671 break;
4672 }
4673 }
4674
4675 refclk = ironlake_get_refclk(crtc);
4676
4677 /*
4678 * Returns a set of divisors for the desired target clock with the given
4679 * refclk, or FALSE. The returned values represent the clock equation:
4680 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4681 */
4682 limit = intel_limit(crtc, refclk);
4683 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4684 clock);
4685 if (!ret)
4686 return false;
4687
4688 if (is_lvds && dev_priv->lvds_downclock_avail) {
4689 /*
4690 * Ensure we match the reduced clock's P to the target clock.
4691 * If the clocks don't match, we can't switch the display clock
4692 * by using the FP0/FP1. In such case we will disable the LVDS
4693 * downclock feature.
4694 */
4695 *has_reduced_clock = limit->find_pll(limit, crtc,
4696 dev_priv->lvds_downclock,
4697 refclk,
4698 clock,
4699 reduced_clock);
4700 }
4701
4702 if (is_sdvo && is_tv)
4703 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4704
4705 return true;
4706}
4707
f564048e
EA		 4708static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4709 struct drm_display_mode *mode,
4710 struct drm_display_mode *adjusted_mode,
4711 int x, int y,
94352cf9 4712 struct drm_framebuffer *fb)
79e53945
JB		 4713{
4714 struct drm_device *dev = crtc->dev;
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717 int pipe = intel_crtc->pipe;
80824003 4718 int plane = intel_crtc->plane;
6591c6e4 4719 int num_connectors = 0;
652c393a 4720 intel_clock_t clock, reduced_clock;
a1f9e77e 4721 u32 dpll, fp = 0, fp2 = 0;
a07d6787 4722 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4723 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4724 struct intel_encoder *encoder, *edp_encoder = NULL;
5c3b82e2 4725 int ret;
2c07245f 4726 struct fdi_m_n m_n = {0};
fae14981 4727 u32 temp;
5a354204
JB		 4728 int target_clock, pixel_multiplier, lane, link_bw, factor;
4729 unsigned int pipe_bpp;
4730 bool dither;
e3aef172 4731 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4732
6c2b7c12 4733 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4734 switch (encoder->type) {
79e53945
JB		 4735 case INTEL_OUTPUT_LVDS:
4736 is_lvds = true;
4737 break;
4738 case INTEL_OUTPUT_SDVO:
7d57382e 4739 case INTEL_OUTPUT_HDMI:
79e53945 4740 is_sdvo = true;
5eddb70b 4741 if (encoder->needs_tv_clock)
e2f0ba97 4742 is_tv = true;
79e53945 4743 break;
79e53945
JB		 4744 case INTEL_OUTPUT_TVOUT:
4745 is_tv = true;
4746 break;
4747 case INTEL_OUTPUT_ANALOG:
4748 is_crt = true;
4749 break;
a4fc5ed6
KP		 4750 case INTEL_OUTPUT_DISPLAYPORT:
4751 is_dp = true;
4752 break;
32f9d658 4753 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4754 is_dp = true;
4755 if (intel_encoder_is_pch_edp(&encoder->base))
4756 is_pch_edp = true;
4757 else
4758 is_cpu_edp = true;
4759 edp_encoder = encoder;
32f9d658 4760 break;
79e53945 4761 }
43565a06 4762
c751ce4f 4763 num_connectors++;
79e53945
JB		 4764 }
4765
6591c6e4
PZ		 4766 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
4767 &has_reduced_clock, &reduced_clock);
79e53945
JB		 4768 if (!ok) {
4769 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4770 return -EINVAL;
79e53945
JB		 4771 }
4772
cda4b7d3 4773 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4774 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4775
2c07245f 4776 /* FDI link */
8febb297
EA		 4777 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4778 lane = 0;
4779 /* CPU eDP doesn't require FDI link, so just set DP M/N
4780 according to current link config */
e3aef172 4781 if (is_cpu_edp) {
e3aef172 4782 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4783 } else {
8febb297
EA		 4784 /* FDI is a binary signal running at ~2.7GHz, encoding
4785 * each output octet as 10 bits. The actual frequency
4786 * is stored as a divider into a 100MHz clock, and the
4787 * mode pixel clock is stored in units of 1KHz.
4788 * Hence the bw of each lane in terms of the mode signal
4789 * is:
4790 */
4791 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4792 }
58a27471 4793
94bf2ced
DV		 4794 /* [e]DP over FDI requires target mode clock instead of link clock. */
4795 if (edp_encoder)
4796 target_clock = intel_edp_target_clock(edp_encoder, mode);
4797 else if (is_dp)
4798 target_clock = mode->clock;
4799 else
4800 target_clock = adjusted_mode->clock;
4801
8febb297 4802 /* determine panel color depth */
94352cf9 4803 dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
c8203565
PZ		 4804 if (is_lvds && dev_priv->lvds_dither)
4805 dither = true;
4806
4807 if (pipe_bpp != 18 && pipe_bpp != 24 && pipe_bpp != 30 &&
4808 pipe_bpp != 36) {
62ac41a6 4809 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
c8203565 4810 pipe_bpp);
5a354204 4811 pipe_bpp = 24;
8febb297 4812 }
5a354204 4813 intel_crtc->bpp = pipe_bpp;
5a354204 4814
8febb297
EA		 4815 if (!lane) {
4816 /*
4817 * Account for spread spectrum to avoid
4818 * oversubscribing the link. Max center spread
4819 * is 2.5%; use 5% for safety's sake.
4820 */
5a354204 4821 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4822 lane = bps / (link_bw * 8) + 1;
5eb08b69 4823 }
2c07245f 4824
8febb297
EA		 4825 intel_crtc->fdi_lanes = lane;
4826
4827 if (pixel_multiplier > 1)
4828 link_bw *= pixel_multiplier;
5a354204
JB		 4829 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4830 &m_n);
8febb297 4831
a07d6787
EA		 4832 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4833 if (has_reduced_clock)
4834 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4835 reduced_clock.m2;
79e53945 4836
c1858123 4837 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4838 factor = 21;
4839 if (is_lvds) {
4840 if ((intel_panel_use_ssc(dev_priv) &&
4841 dev_priv->lvds_ssc_freq == 100) ||
4842 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4843 factor = 25;
4844 } else if (is_sdvo && is_tv)
4845 factor = 20;
c1858123 4846
cb0e0931 4847 if (clock.m < factor * clock.n)
8febb297 4848 fp |= FP_CB_TUNE;
2c07245f 4849
5eddb70b 4850 dpll = 0;
2c07245f 4851
a07d6787
EA		 4852 if (is_lvds)
4853 dpll |= DPLLB_MODE_LVDS;
4854 else
4855 dpll |= DPLLB_MODE_DAC_SERIAL;
4856 if (is_sdvo) {
4857 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4858 if (pixel_multiplier > 1) {
4859 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4860 }
a07d6787
EA		 4861 dpll |= DPLL_DVO_HIGH_SPEED;
4862 }
e3aef172 4863 if (is_dp && !is_cpu_edp)
a07d6787 4864 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4865
a07d6787
EA		 4866 /* compute bitmask from p1 value */
4867 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4868 /* also FPA1 */
4869 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4870
4871 switch (clock.p2) {
4872 case 5:
4873 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4874 break;
4875 case 7:
4876 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4877 break;
4878 case 10:
4879 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4880 break;
4881 case 14:
4882 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4883 break;
79e53945
JB		 4884 }
4885
43565a06
KH		 4886 if (is_sdvo && is_tv)
4887 dpll |= PLL_REF_INPUT_TVCLKINBC;
4888 else if (is_tv)
79e53945 4889 /* XXX: just matching BIOS for now */
43565a06 4890 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4891 dpll |= 3;
a7615030 4892 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4893 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4894 else
4895 dpll |= PLL_REF_INPUT_DREFCLK;
4896
f7cb34d4 4897 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4898 drm_mode_debug_printmodeline(mode);
4899
9d82aa17
ED		 4900 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4901 * pre-Haswell/LPT generation */
4902 if (HAS_PCH_LPT(dev)) {
4903 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4904 pipe);
4905 } else if (!is_cpu_edp) {
ee7b9f93 4906 struct intel_pch_pll *pll;
4b645f14 4907
ee7b9f93
JB		 4908 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4909 if (pll == NULL) {
4910 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4911 pipe);
4b645f14
JB		 4912 return -EINVAL;
4913 }
ee7b9f93
JB		 4914 } else
4915 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4916
4917 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4918 * This is an exception to the general rule that mode_set doesn't turn
4919 * things on.
4920 */
4921 if (is_lvds) {
fae14981 4922 temp = I915_READ(PCH_LVDS);
5eddb70b 4923 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4924 if (HAS_PCH_CPT(dev)) {
4925 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4926 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4927 } else {
4928 if (pipe == 1)
4929 temp |= LVDS_PIPEB_SELECT;
4930 else
4931 temp &= ~LVDS_PIPEB_SELECT;
4932 }
4b645f14 4933
a3e17eb8 4934 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4935 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4936 /* Set the B0-B3 data pairs corresponding to whether we're going to
4937 * set the DPLLs for dual-channel mode or not.
4938 */
4939 if (clock.p2 == 7)
5eddb70b 4940 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4941 else
5eddb70b 4942 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4943
4944 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4945 * appropriately here, but we need to look more thoroughly into how
4946 * panels behave in the two modes.
4947 */
284d5df5 4948 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4949 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4950 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4951 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4952 temp |= LVDS_VSYNC_POLARITY;
fae14981 4953 I915_WRITE(PCH_LVDS, temp);
79e53945 4954 }
434ed097 4955
e3aef172 4956 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4957 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4958 } else {
8db9d77b 4959 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4960 I915_WRITE(TRANSDATA_M1(pipe), 0);
4961 I915_WRITE(TRANSDATA_N1(pipe), 0);
4962 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4963 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4964 }
79e53945 4965
ee7b9f93
JB		 4966 if (intel_crtc->pch_pll) {
4967 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4968
32f9d658 4969 /* Wait for the clocks to stabilize. */
ee7b9f93 4970 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4971 udelay(150);
4972
8febb297
EA		 4973 /* The pixel multiplier can only be updated once the
4974 * DPLL is enabled and the clocks are stable.
4975 *
4976 * So write it again.
4977 */
ee7b9f93 4978 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4979 }
79e53945 4980
5eddb70b 4981 intel_crtc->lowfreq_avail = false;
ee7b9f93 4982 if (intel_crtc->pch_pll) {
4b645f14 4983 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4984 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4985 intel_crtc->lowfreq_avail = true;
4b645f14 4986 } else {
ee7b9f93 4987 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4988 }
4989 }
4990
734b4157 4991 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157 4992 /* the chip adds 2 halflines automatically */
734b4157 4993 adjusted_mode->crtc_vtotal -= 1;
734b4157 4994 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4995 I915_WRITE(VSYNCSHIFT(pipe),
4996 adjusted_mode->crtc_hsync_start
4997 - adjusted_mode->crtc_htotal/2);
4998 } else {
0529a0d9
DV		 4999 I915_WRITE(VSYNCSHIFT(pipe), 0);
5000 }
734b4157 5001
5eddb70b
CW		 5002 I915_WRITE(HTOTAL(pipe),
5003 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5004 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5005 I915_WRITE(HBLANK(pipe),
5006 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5007 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5008 I915_WRITE(HSYNC(pipe),
5009 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5010 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5011
5012 I915_WRITE(VTOTAL(pipe),
5013 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5014 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5015 I915_WRITE(VBLANK(pipe),
5016 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5017 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5018 I915_WRITE(VSYNC(pipe),
5019 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5020 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5021
8febb297
EA		 5022 /* pipesrc controls the size that is scaled from, which should
5023 * always be the user's requested size.
79e53945 5024 */
5eddb70b
CW		 5025 I915_WRITE(PIPESRC(pipe),
5026 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5027
8febb297
EA		 5028 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5029 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5030 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5031 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5032
e3aef172 5033 if (is_cpu_edp)
8febb297 5034 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5035
c8203565 5036 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5037
9d0498a2 5038 intel_wait_for_vblank(dev, pipe);
79e53945 5039
a1f9e77e
PZ		 5040 /* Set up the display plane register */
5041 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5042 POSTING_READ(DSPCNTR(plane));
79e53945 5043
94352cf9 5044 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5045
5046 intel_update_watermarks(dev);
5047
1f8eeabf
ED		 5048 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5049
1f803ee5 5050 return ret;
79e53945
JB		 5051}
5052
f564048e
EA		 5053static int intel_crtc_mode_set(struct drm_crtc *crtc,
5054 struct drm_display_mode *mode,
5055 struct drm_display_mode *adjusted_mode,
5056 int x, int y,
94352cf9 5057 struct drm_framebuffer *fb)
f564048e
EA		 5058{
5059 struct drm_device *dev = crtc->dev;
5060 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062 int pipe = intel_crtc->pipe;
f564048e
EA		 5063 int ret;
5064
0b701d27 5065 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5066
f564048e 5067 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5068 x, y, fb);
79e53945 5069 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5070
1f803ee5 5071 return ret;
79e53945
JB		 5072}
5073
3a9627f4
WF		 5074static bool intel_eld_uptodate(struct drm_connector *connector,
5075 int reg_eldv, uint32_t bits_eldv,
5076 int reg_elda, uint32_t bits_elda,
5077 int reg_edid)
5078{
5079 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5080 uint8_t *eld = connector->eld;
5081 uint32_t i;
5082
5083 i = I915_READ(reg_eldv);
5084 i &= bits_eldv;
5085
5086 if (!eld[0])
5087 return !i;
5088
5089 if (!i)
5090 return false;
5091
5092 i = I915_READ(reg_elda);
5093 i &= ~bits_elda;
5094 I915_WRITE(reg_elda, i);
5095
5096 for (i = 0; i < eld[2]; i++)
5097 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5098 return false;
5099
5100 return true;
5101}
5102
e0dac65e
WF		 5103static void g4x_write_eld(struct drm_connector *connector,
5104 struct drm_crtc *crtc)
5105{
5106 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5107 uint8_t *eld = connector->eld;
5108 uint32_t eldv;
5109 uint32_t len;
5110 uint32_t i;
5111
5112 i = I915_READ(G4X_AUD_VID_DID);
5113
5114 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5115 eldv = G4X_ELDV_DEVCL_DEVBLC;
5116 else
5117 eldv = G4X_ELDV_DEVCTG;
5118
3a9627f4
WF		 5119 if (intel_eld_uptodate(connector,
5120 G4X_AUD_CNTL_ST, eldv,
5121 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5122 G4X_HDMIW_HDMIEDID))
5123 return;
5124
e0dac65e
WF		 5125 i = I915_READ(G4X_AUD_CNTL_ST);
5126 i &= ~(eldv | G4X_ELD_ADDR);
5127 len = (i >> 9) & 0x1f; /* ELD buffer size */
5128 I915_WRITE(G4X_AUD_CNTL_ST, i);
5129
5130 if (!eld[0])
5131 return;
5132
5133 len = min_t(uint8_t, eld[2], len);
5134 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5135 for (i = 0; i < len; i++)
5136 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5137
5138 i = I915_READ(G4X_AUD_CNTL_ST);
5139 i |= eldv;
5140 I915_WRITE(G4X_AUD_CNTL_ST, i);
5141}
5142
83358c85
WX		 5143static void haswell_write_eld(struct drm_connector *connector,
5144 struct drm_crtc *crtc)
5145{
5146 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5147 uint8_t *eld = connector->eld;
5148 struct drm_device *dev = crtc->dev;
5149 uint32_t eldv;
5150 uint32_t i;
5151 int len;
5152 int pipe = to_intel_crtc(crtc)->pipe;
5153 int tmp;
5154
5155 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5156 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5157 int aud_config = HSW_AUD_CFG(pipe);
5158 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5159
5160
5161 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5162
5163 /* Audio output enable */
5164 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5165 tmp = I915_READ(aud_cntrl_st2);
5166 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5167 I915_WRITE(aud_cntrl_st2, tmp);
5168
5169 /* Wait for 1 vertical blank */
5170 intel_wait_for_vblank(dev, pipe);
5171
5172 /* Set ELD valid state */
5173 tmp = I915_READ(aud_cntrl_st2);
5174 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5175 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5176 I915_WRITE(aud_cntrl_st2, tmp);
5177 tmp = I915_READ(aud_cntrl_st2);
5178 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5179
5180 /* Enable HDMI mode */
5181 tmp = I915_READ(aud_config);
5182 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5183 /* clear N_programing_enable and N_value_index */
5184 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5185 I915_WRITE(aud_config, tmp);
5186
5187 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5188
5189 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5190
5191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5192 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5193 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5194 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5195 } else
5196 I915_WRITE(aud_config, 0);
5197
5198 if (intel_eld_uptodate(connector,
5199 aud_cntrl_st2, eldv,
5200 aud_cntl_st, IBX_ELD_ADDRESS,
5201 hdmiw_hdmiedid))
5202 return;
5203
5204 i = I915_READ(aud_cntrl_st2);
5205 i &= ~eldv;
5206 I915_WRITE(aud_cntrl_st2, i);
5207
5208 if (!eld[0])
5209 return;
5210
5211 i = I915_READ(aud_cntl_st);
5212 i &= ~IBX_ELD_ADDRESS;
5213 I915_WRITE(aud_cntl_st, i);
5214 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5215 DRM_DEBUG_DRIVER("port num:%d\n", i);
5216
5217 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5218 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5219 for (i = 0; i < len; i++)
5220 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5221
5222 i = I915_READ(aud_cntrl_st2);
5223 i |= eldv;
5224 I915_WRITE(aud_cntrl_st2, i);
5225
5226}
5227
e0dac65e
WF		 5228static void ironlake_write_eld(struct drm_connector *connector,
5229 struct drm_crtc *crtc)
5230{
5231 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5232 uint8_t *eld = connector->eld;
5233 uint32_t eldv;
5234 uint32_t i;
5235 int len;
5236 int hdmiw_hdmiedid;
b6daa025 5237 int aud_config;
e0dac65e
WF		 5238 int aud_cntl_st;
5239 int aud_cntrl_st2;
9b138a83 5240 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5241
b3f33cbf 5242 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5243 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5244 aud_config = IBX_AUD_CFG(pipe);
5245 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5246 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5247 } else {
9b138a83
WX		 5248 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5249 aud_config = CPT_AUD_CFG(pipe);
5250 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5251 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5252 }
5253
9b138a83 5254 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5255
5256 i = I915_READ(aud_cntl_st);
9b138a83 5257 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5258 if (!i) {
5259 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5260 /* operate blindly on all ports */
1202b4c6
WF		 5261 eldv = IBX_ELD_VALIDB;
5262 eldv |= IBX_ELD_VALIDB << 4;
5263 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5264 } else {
5265 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5266 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5267 }
5268
3a9627f4
WF		 5269 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5270 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5271 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5272 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5273 } else
5274 I915_WRITE(aud_config, 0);
e0dac65e 5275
3a9627f4
WF		 5276 if (intel_eld_uptodate(connector,
5277 aud_cntrl_st2, eldv,
5278 aud_cntl_st, IBX_ELD_ADDRESS,
5279 hdmiw_hdmiedid))
5280 return;
5281
e0dac65e
WF		 5282 i = I915_READ(aud_cntrl_st2);
5283 i &= ~eldv;
5284 I915_WRITE(aud_cntrl_st2, i);
5285
5286 if (!eld[0])
5287 return;
5288
e0dac65e 5289 i = I915_READ(aud_cntl_st);
1202b4c6 5290 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5291 I915_WRITE(aud_cntl_st, i);
5292
5293 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5294 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5295 for (i = 0; i < len; i++)
5296 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5297
5298 i = I915_READ(aud_cntrl_st2);
5299 i |= eldv;
5300 I915_WRITE(aud_cntrl_st2, i);
5301}
5302
5303void intel_write_eld(struct drm_encoder *encoder,
5304 struct drm_display_mode *mode)
5305{
5306 struct drm_crtc *crtc = encoder->crtc;
5307 struct drm_connector *connector;
5308 struct drm_device *dev = encoder->dev;
5309 struct drm_i915_private *dev_priv = dev->dev_private;
5310
5311 connector = drm_select_eld(encoder, mode);
5312 if (!connector)
5313 return;
5314
5315 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5316 connector->base.id,
5317 drm_get_connector_name(connector),
5318 connector->encoder->base.id,
5319 drm_get_encoder_name(connector->encoder));
5320
5321 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5322
5323 if (dev_priv->display.write_eld)
5324 dev_priv->display.write_eld(connector, crtc);
5325}
5326
79e53945
JB		 5327/** Loads the palette/gamma unit for the CRTC with the prepared values */
5328void intel_crtc_load_lut(struct drm_crtc *crtc)
5329{
5330 struct drm_device *dev = crtc->dev;
5331 struct drm_i915_private *dev_priv = dev->dev_private;
5332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5333 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5334 int i;
5335
5336 /* The clocks have to be on to load the palette. */
aed3f09d 5337 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5338 return;
5339
f2b115e6 5340 /* use legacy palette for Ironlake */
bad720ff 5341 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5342 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5343
79e53945
JB		 5344 for (i = 0; i < 256; i++) {
5345 I915_WRITE(palreg + 4 * i,
5346 (intel_crtc->lut_r[i] << 16) |
5347 (intel_crtc->lut_g[i] << 8) |
5348 intel_crtc->lut_b[i]);
5349 }
5350}
5351
560b85bb
CW		 5352static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5353{
5354 struct drm_device *dev = crtc->dev;
5355 struct drm_i915_private *dev_priv = dev->dev_private;
5356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5357 bool visible = base != 0;
5358 u32 cntl;
5359
5360 if (intel_crtc->cursor_visible == visible)
5361 return;
5362
9db4a9c7 5363 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5364 if (visible) {
5365 /* On these chipsets we can only modify the base whilst
5366 * the cursor is disabled.
5367 */
9db4a9c7 5368 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5369
5370 cntl &= ~(CURSOR_FORMAT_MASK);
5371 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5372 cntl |= CURSOR_ENABLE |
5373 CURSOR_GAMMA_ENABLE |
5374 CURSOR_FORMAT_ARGB;
5375 } else
5376 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5377 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5378
5379 intel_crtc->cursor_visible = visible;
5380}
5381
5382static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5383{
5384 struct drm_device *dev = crtc->dev;
5385 struct drm_i915_private *dev_priv = dev->dev_private;
5386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5387 int pipe = intel_crtc->pipe;
5388 bool visible = base != 0;
5389
5390 if (intel_crtc->cursor_visible != visible) {
548f245b 5391 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5392 if (base) {
5393 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5394 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5395 cntl |= pipe << 28; /* Connect to correct pipe */
5396 } else {
5397 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5398 cntl |= CURSOR_MODE_DISABLE;
5399 }
9db4a9c7 5400 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5401
5402 intel_crtc->cursor_visible = visible;
5403 }
5404 /* and commit changes on next vblank */
9db4a9c7 5405 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5406}
5407
65a21cd6
JB		 5408static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5409{
5410 struct drm_device *dev = crtc->dev;
5411 struct drm_i915_private *dev_priv = dev->dev_private;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413 int pipe = intel_crtc->pipe;
5414 bool visible = base != 0;
5415
5416 if (intel_crtc->cursor_visible != visible) {
5417 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5418 if (base) {
5419 cntl &= ~CURSOR_MODE;
5420 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5421 } else {
5422 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5423 cntl |= CURSOR_MODE_DISABLE;
5424 }
5425 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5426
5427 intel_crtc->cursor_visible = visible;
5428 }
5429 /* and commit changes on next vblank */
5430 I915_WRITE(CURBASE_IVB(pipe), base);
5431}
5432
cda4b7d3 5433/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5434static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5435 bool on)
cda4b7d3
CW		 5436{
5437 struct drm_device *dev = crtc->dev;
5438 struct drm_i915_private *dev_priv = dev->dev_private;
5439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5440 int pipe = intel_crtc->pipe;
5441 int x = intel_crtc->cursor_x;
5442 int y = intel_crtc->cursor_y;
560b85bb 5443 u32 base, pos;
cda4b7d3
CW		 5444 bool visible;
5445
5446 pos = 0;
5447
6b383a7f 5448 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5449 base = intel_crtc->cursor_addr;
5450 if (x > (int) crtc->fb->width)
5451 base = 0;
5452
5453 if (y > (int) crtc->fb->height)
5454 base = 0;
5455 } else
5456 base = 0;
5457
5458 if (x < 0) {
5459 if (x + intel_crtc->cursor_width < 0)
5460 base = 0;
5461
5462 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5463 x = -x;
5464 }
5465 pos |= x << CURSOR_X_SHIFT;
5466
5467 if (y < 0) {
5468 if (y + intel_crtc->cursor_height < 0)
5469 base = 0;
5470
5471 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5472 y = -y;
5473 }
5474 pos |= y << CURSOR_Y_SHIFT;
5475
5476 visible = base != 0;
560b85bb 5477 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5478 return;
5479
0cd83aa9 5480 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5481 I915_WRITE(CURPOS_IVB(pipe), pos);
5482 ivb_update_cursor(crtc, base);
5483 } else {
5484 I915_WRITE(CURPOS(pipe), pos);
5485 if (IS_845G(dev) || IS_I865G(dev))
5486 i845_update_cursor(crtc, base);
5487 else
5488 i9xx_update_cursor(crtc, base);
5489 }
cda4b7d3
CW		 5490}
5491
79e53945 5492static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5493 struct drm_file *file,
79e53945
JB		 5494 uint32_t handle,
5495 uint32_t width, uint32_t height)
5496{
5497 struct drm_device *dev = crtc->dev;
5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5500 struct drm_i915_gem_object *obj;
cda4b7d3 5501 uint32_t addr;
3f8bc370 5502 int ret;
79e53945 5503
79e53945
JB		 5504 /* if we want to turn off the cursor ignore width and height */
5505 if (!handle) {
28c97730 5506 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5507 addr = 0;
05394f39 5508 obj = NULL;
5004417d 5509 mutex_lock(&dev->struct_mutex);
3f8bc370 5510 goto finish;
79e53945
JB		 5511 }
5512
5513 /* Currently we only support 64x64 cursors */
5514 if (width != 64 || height != 64) {
5515 DRM_ERROR("we currently only support 64x64 cursors\n");
5516 return -EINVAL;
5517 }
5518
05394f39 5519 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5520 if (&obj->base == NULL)
79e53945
JB		 5521 return -ENOENT;
5522
05394f39 5523 if (obj->base.size < width * height * 4) {
79e53945 5524 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5525 ret = -ENOMEM;
5526 goto fail;
79e53945
JB		 5527 }
5528
71acb5eb 5529 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5530 mutex_lock(&dev->struct_mutex);
b295d1b6 5531 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5532 if (obj->tiling_mode) {
5533 DRM_ERROR("cursor cannot be tiled\n");
5534 ret = -EINVAL;
5535 goto fail_locked;
5536 }
5537
2da3b9b9 5538 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5539 if (ret) {
5540 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5541 goto fail_locked;
e7b526bb
CW		 5542 }
5543
d9e86c0e
CW		 5544 ret = i915_gem_object_put_fence(obj);
5545 if (ret) {
2da3b9b9 5546 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5547 goto fail_unpin;
5548 }
5549
05394f39 5550 addr = obj->gtt_offset;
71acb5eb 5551 } else {
6eeefaf3 5552 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5553 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5554 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5555 align);
71acb5eb
DA		 5556 if (ret) {
5557 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5558 goto fail_locked;
71acb5eb 5559 }
05394f39 5560 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5561 }
5562
a6c45cf0 5563 if (IS_GEN2(dev))
14b60391
JB		 5564 I915_WRITE(CURSIZE, (height << 12) | width);
5565
3f8bc370 5566 finish:
3f8bc370 5567 if (intel_crtc->cursor_bo) {
b295d1b6 5568 if (dev_priv->info->cursor_needs_physical) {
05394f39 5569 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5570 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5571 } else
5572 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5573 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5574 }
80824003 5575
7f9872e0 5576 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5577
5578 intel_crtc->cursor_addr = addr;
05394f39 5579 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5580 intel_crtc->cursor_width = width;
5581 intel_crtc->cursor_height = height;
5582
6b383a7f 5583 intel_crtc_update_cursor(crtc, true);
3f8bc370 5584
79e53945 5585 return 0;
e7b526bb 5586fail_unpin:
05394f39 5587 i915_gem_object_unpin(obj);
7f9872e0 5588fail_locked:
34b8686e 5589 mutex_unlock(&dev->struct_mutex);
bc9025bd 5590fail:
05394f39 5591 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5592 return ret;
79e53945
JB		 5593}
5594
5595static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5596{
79e53945 5597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5598
cda4b7d3
CW		 5599 intel_crtc->cursor_x = x;
5600 intel_crtc->cursor_y = y;
652c393a 5601
6b383a7f 5602 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5603
5604 return 0;
5605}
5606
5607/** Sets the color ramps on behalf of RandR */
5608void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5609 u16 blue, int regno)
5610{
5611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5612
5613 intel_crtc->lut_r[regno] = red >> 8;
5614 intel_crtc->lut_g[regno] = green >> 8;
5615 intel_crtc->lut_b[regno] = blue >> 8;
5616}
5617
b8c00ac5
DA		 5618void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5619 u16 *blue, int regno)
5620{
5621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5622
5623 *red = intel_crtc->lut_r[regno] << 8;
5624 *green = intel_crtc->lut_g[regno] << 8;
5625 *blue = intel_crtc->lut_b[regno] << 8;
5626}
5627
79e53945 5628static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5629 u16 *blue, uint32_t start, uint32_t size)
79e53945 5630{
7203425a 5631 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5633
7203425a 5634 for (i = start; i < end; i++) {
79e53945
JB		 5635 intel_crtc->lut_r[i] = red[i] >> 8;
5636 intel_crtc->lut_g[i] = green[i] >> 8;
5637 intel_crtc->lut_b[i] = blue[i] >> 8;
5638 }
5639
5640 intel_crtc_load_lut(crtc);
5641}
5642
5643/**
5644 * Get a pipe with a simple mode set on it for doing load-based monitor
5645 * detection.
5646 *
5647 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5648 * its requirements. The pipe will be connected to no other encoders.
79e53945 5649 *
c751ce4f 5650 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5651 * configured for it. In the future, it could choose to temporarily disable
5652 * some outputs to free up a pipe for its use.
5653 *
5654 * \return crtc, or NULL if no pipes are available.
5655 */
5656
5657/* VESA 640x480x72Hz mode to set on the pipe */
5658static struct drm_display_mode load_detect_mode = {
5659 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5660 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5661};
5662
d2dff872
CW		 5663static struct drm_framebuffer *
5664intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5665 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5666 struct drm_i915_gem_object *obj)
5667{
5668 struct intel_framebuffer *intel_fb;
5669 int ret;
5670
5671 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5672 if (!intel_fb) {
5673 drm_gem_object_unreference_unlocked(&obj->base);
5674 return ERR_PTR(-ENOMEM);
5675 }
5676
5677 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5678 if (ret) {
5679 drm_gem_object_unreference_unlocked(&obj->base);
5680 kfree(intel_fb);
5681 return ERR_PTR(ret);
5682 }
5683
5684 return &intel_fb->base;
5685}
5686
5687static u32
5688intel_framebuffer_pitch_for_width(int width, int bpp)
5689{
5690 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5691 return ALIGN(pitch, 64);
5692}
5693
5694static u32
5695intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5696{
5697 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5698 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5699}
5700
5701static struct drm_framebuffer *
5702intel_framebuffer_create_for_mode(struct drm_device *dev,
5703 struct drm_display_mode *mode,
5704 int depth, int bpp)
5705{
5706 struct drm_i915_gem_object *obj;
308e5bcb 5707 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5708
5709 obj = i915_gem_alloc_object(dev,
5710 intel_framebuffer_size_for_mode(mode, bpp));
5711 if (obj == NULL)
5712 return ERR_PTR(-ENOMEM);
5713
5714 mode_cmd.width = mode->hdisplay;
5715 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5716 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5717 bpp);
5ca0c34a 5718 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5719
5720 return intel_framebuffer_create(dev, &mode_cmd, obj);
5721}
5722
5723static struct drm_framebuffer *
5724mode_fits_in_fbdev(struct drm_device *dev,
5725 struct drm_display_mode *mode)
5726{
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5728 struct drm_i915_gem_object *obj;
5729 struct drm_framebuffer *fb;
5730
5731 if (dev_priv->fbdev == NULL)
5732 return NULL;
5733
5734 obj = dev_priv->fbdev->ifb.obj;
5735 if (obj == NULL)
5736 return NULL;
5737
5738 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5739 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5740 fb->bits_per_pixel))
d2dff872
CW		 5741 return NULL;
5742
01f2c773 5743 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5744 return NULL;
5745
5746 return fb;
5747}
5748
d2434ab7 5749bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5750 struct drm_display_mode *mode,
8261b191 5751 struct intel_load_detect_pipe *old)
79e53945
JB		 5752{
5753 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5754 struct intel_encoder *intel_encoder =
5755 intel_attached_encoder(connector);
79e53945 5756 struct drm_crtc *possible_crtc;
4ef69c7a 5757 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5758 struct drm_crtc *crtc = NULL;
5759 struct drm_device *dev = encoder->dev;
94352cf9 5760 struct drm_framebuffer *fb;
79e53945
JB		 5761 int i = -1;
5762
d2dff872
CW		 5763 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5764 connector->base.id, drm_get_connector_name(connector),
5765 encoder->base.id, drm_get_encoder_name(encoder));
5766
79e53945
JB		 5767 /*
5768 * Algorithm gets a little messy:
7a5e4805 5769 *
79e53945
JB		 5770 * - if the connector already has an assigned crtc, use it (but make
5771 * sure it's on first)
7a5e4805 5772 *
79e53945
JB		 5773 * - try to find the first unused crtc that can drive this connector,
5774 * and use that if we find one
79e53945
JB		 5775 */
5776
5777 /* See if we already have a CRTC for this connector */
5778 if (encoder->crtc) {
5779 crtc = encoder->crtc;
8261b191 5780
24218aac 5781 old->dpms_mode = connector->dpms;
8261b191
CW		 5782 old->load_detect_temp = false;
5783
5784 /* Make sure the crtc and connector are running */
24218aac
DV		 5785 if (connector->dpms != DRM_MODE_DPMS_ON)
5786 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5787
7173188d 5788 return true;
79e53945
JB		 5789 }
5790
5791 /* Find an unused one (if possible) */
5792 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5793 i++;
5794 if (!(encoder->possible_crtcs & (1 << i)))
5795 continue;
5796 if (!possible_crtc->enabled) {
5797 crtc = possible_crtc;
5798 break;
5799 }
79e53945
JB		 5800 }
5801
5802 /*
5803 * If we didn't find an unused CRTC, don't use any.
5804 */
5805 if (!crtc) {
7173188d
CW		 5806 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5807 return false;
79e53945
JB		 5808 }
5809
fc303101
DV		 5810 intel_encoder->new_crtc = to_intel_crtc(crtc);
5811 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 5812
5813 intel_crtc = to_intel_crtc(crtc);
24218aac 5814 old->dpms_mode = connector->dpms;
8261b191 5815 old->load_detect_temp = true;
d2dff872 5816 old->release_fb = NULL;
79e53945 5817
6492711d
CW		 5818 if (!mode)
5819 mode = &load_detect_mode;
79e53945 5820
d2dff872
CW		 5821 /* We need a framebuffer large enough to accommodate all accesses
5822 * that the plane may generate whilst we perform load detection.
5823 * We can not rely on the fbcon either being present (we get called
5824 * during its initialisation to detect all boot displays, or it may
5825 * not even exist) or that it is large enough to satisfy the
5826 * requested mode.
5827 */
94352cf9
DV		 5828 fb = mode_fits_in_fbdev(dev, mode);
5829 if (fb == NULL) {
d2dff872 5830 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 5831 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5832 old->release_fb = fb;
d2dff872
CW		 5833 } else
5834 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 5835 if (IS_ERR(fb)) {
d2dff872 5836 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5837 goto fail;
79e53945 5838 }
79e53945 5839
94352cf9 5840 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 5841 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5842 if (old->release_fb)
5843 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5844 goto fail;
79e53945 5845 }
7173188d 5846
79e53945 5847 /* let the connector get through one full cycle before testing */
9d0498a2 5848 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5849
7173188d 5850 return true;
24218aac
DV		 5851fail:
5852 connector->encoder = NULL;
5853 encoder->crtc = NULL;
24218aac 5854 return false;
79e53945
JB		 5855}
5856
d2434ab7 5857void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5858 struct intel_load_detect_pipe *old)
79e53945 5859{
d2434ab7
DV		 5860 struct intel_encoder *intel_encoder =
5861 intel_attached_encoder(connector);
4ef69c7a 5862 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5863
d2dff872
CW		 5864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5865 connector->base.id, drm_get_connector_name(connector),
5866 encoder->base.id, drm_get_encoder_name(encoder));
5867
8261b191 5868 if (old->load_detect_temp) {
fc303101
DV		 5869 struct drm_crtc *crtc = encoder->crtc;
5870
5871 to_intel_connector(connector)->new_encoder = NULL;
5872 intel_encoder->new_crtc = NULL;
5873 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 5874
5875 if (old->release_fb)
5876 old->release_fb->funcs->destroy(old->release_fb);
5877
0622a53c 5878 return;
79e53945
JB		 5879 }
5880
c751ce4f 5881 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5882 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5883 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5884}
5885
5886/* Returns the clock of the currently programmed mode of the given pipe. */
5887static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5888{
5889 struct drm_i915_private *dev_priv = dev->dev_private;
5890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5891 int pipe = intel_crtc->pipe;
548f245b 5892 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5893 u32 fp;
5894 intel_clock_t clock;
5895
5896 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5897 fp = I915_READ(FP0(pipe));
79e53945 5898 else
39adb7a5 5899 fp = I915_READ(FP1(pipe));
79e53945
JB		 5900
5901 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5902 if (IS_PINEVIEW(dev)) {
5903 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5904 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5905 } else {
5906 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5907 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5908 }
5909
a6c45cf0 5910 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5911 if (IS_PINEVIEW(dev))
5912 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5913 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5914 else
5915 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5916 DPLL_FPA01_P1_POST_DIV_SHIFT);
5917
5918 switch (dpll & DPLL_MODE_MASK) {
5919 case DPLLB_MODE_DAC_SERIAL:
5920 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5921 5 : 10;
5922 break;
5923 case DPLLB_MODE_LVDS:
5924 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5925 7 : 14;
5926 break;
5927 default:
28c97730 5928 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5929 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5930 return 0;
5931 }
5932
5933 /* XXX: Handle the 100Mhz refclk */
2177832f 5934 intel_clock(dev, 96000, &clock);
79e53945
JB		 5935 } else {
5936 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5937
5938 if (is_lvds) {
5939 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5940 DPLL_FPA01_P1_POST_DIV_SHIFT);
5941 clock.p2 = 14;
5942
5943 if ((dpll & PLL_REF_INPUT_MASK) ==
5944 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5945 /* XXX: might not be 66MHz */
2177832f 5946 intel_clock(dev, 66000, &clock);
79e53945 5947 } else
2177832f 5948 intel_clock(dev, 48000, &clock);
79e53945
JB		 5949 } else {
5950 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5951 clock.p1 = 2;
5952 else {
5953 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5954 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5955 }
5956 if (dpll & PLL_P2_DIVIDE_BY_4)
5957 clock.p2 = 4;
5958 else
5959 clock.p2 = 2;
5960
2177832f 5961 intel_clock(dev, 48000, &clock);
79e53945
JB		 5962 }
5963 }
5964
5965 /* XXX: It would be nice to validate the clocks, but we can't reuse
5966 * i830PllIsValid() because it relies on the xf86_config connector
5967 * configuration being accurate, which it isn't necessarily.
5968 */
5969
5970 return clock.dot;
5971}
5972
5973/** Returns the currently programmed mode of the given pipe. */
5974struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5975 struct drm_crtc *crtc)
5976{
548f245b 5977 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5979 int pipe = intel_crtc->pipe;
5980 struct drm_display_mode *mode;
548f245b
JB		 5981 int htot = I915_READ(HTOTAL(pipe));
5982 int hsync = I915_READ(HSYNC(pipe));
5983 int vtot = I915_READ(VTOTAL(pipe));
5984 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5985
5986 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5987 if (!mode)
5988 return NULL;
5989
5990 mode->clock = intel_crtc_clock_get(dev, crtc);
5991 mode->hdisplay = (htot & 0xffff) + 1;
5992 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5993 mode->hsync_start = (hsync & 0xffff) + 1;
5994 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5995 mode->vdisplay = (vtot & 0xffff) + 1;
5996 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5997 mode->vsync_start = (vsync & 0xffff) + 1;
5998 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5999
6000 drm_mode_set_name(mode);
79e53945
JB		 6001
6002 return mode;
6003}
6004
3dec0095 6005static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6006{
6007 struct drm_device *dev = crtc->dev;
6008 drm_i915_private_t *dev_priv = dev->dev_private;
6009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6010 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6011 int dpll_reg = DPLL(pipe);
6012 int dpll;
652c393a 6013
bad720ff 6014 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6015 return;
6016
6017 if (!dev_priv->lvds_downclock_avail)
6018 return;
6019
dbdc6479 6020 dpll = I915_READ(dpll_reg);
652c393a 6021 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6022 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6023
8ac5a6d5 6024 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6025
6026 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6027 I915_WRITE(dpll_reg, dpll);
9d0498a2 6028 intel_wait_for_vblank(dev, pipe);
dbdc6479 6029
652c393a
JB		 6030 dpll = I915_READ(dpll_reg);
6031 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6032 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6033 }
652c393a
JB		 6034}
6035
6036static void intel_decrease_pllclock(struct drm_crtc *crtc)
6037{
6038 struct drm_device *dev = crtc->dev;
6039 drm_i915_private_t *dev_priv = dev->dev_private;
6040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6041
bad720ff 6042 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6043 return;
6044
6045 if (!dev_priv->lvds_downclock_avail)
6046 return;
6047
6048 /*
6049 * Since this is called by a timer, we should never get here in
6050 * the manual case.
6051 */
6052 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6053 int pipe = intel_crtc->pipe;
6054 int dpll_reg = DPLL(pipe);
6055 int dpll;
f6e5b160 6056
44d98a61 6057 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6058
8ac5a6d5 6059 assert_panel_unlocked(dev_priv, pipe);
652c393a 6060
dc257cf1 6061 dpll = I915_READ(dpll_reg);
652c393a
JB		 6062 dpll |= DISPLAY_RATE_SELECT_FPA1;
6063 I915_WRITE(dpll_reg, dpll);
9d0498a2 6064 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6065 dpll = I915_READ(dpll_reg);
6066 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6067 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6068 }
6069
6070}
6071
f047e395
CW		 6072void intel_mark_busy(struct drm_device *dev)
6073{
f047e395
CW		 6074 i915_update_gfx_val(dev->dev_private);
6075}
6076
6077void intel_mark_idle(struct drm_device *dev)
652c393a 6078{
f047e395
CW		 6079}
6080
6081void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6082{
6083 struct drm_device *dev = obj->base.dev;
652c393a 6084 struct drm_crtc *crtc;
652c393a
JB		 6085
6086 if (!i915_powersave)
6087 return;
6088
652c393a 6089 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6090 if (!crtc->fb)
6091 continue;
6092
f047e395
CW		 6093 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6094 intel_increase_pllclock(crtc);
652c393a 6095 }
652c393a
JB		 6096}
6097
f047e395 6098void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6099{
f047e395
CW		 6100 struct drm_device *dev = obj->base.dev;
6101 struct drm_crtc *crtc;
652c393a 6102
f047e395 6103 if (!i915_powersave)
acb87dfb
CW		 6104 return;
6105
652c393a
JB		 6106 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6107 if (!crtc->fb)
6108 continue;
6109
f047e395
CW		 6110 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6111 intel_decrease_pllclock(crtc);
652c393a
JB		 6112 }
6113}
6114
79e53945
JB		 6115static void intel_crtc_destroy(struct drm_crtc *crtc)
6116{
6117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6118 struct drm_device *dev = crtc->dev;
6119 struct intel_unpin_work *work;
6120 unsigned long flags;
6121
6122 spin_lock_irqsave(&dev->event_lock, flags);
6123 work = intel_crtc->unpin_work;
6124 intel_crtc->unpin_work = NULL;
6125 spin_unlock_irqrestore(&dev->event_lock, flags);
6126
6127 if (work) {
6128 cancel_work_sync(&work->work);
6129 kfree(work);
6130 }
79e53945
JB		 6131
6132 drm_crtc_cleanup(crtc);
67e77c5a 6133
79e53945
JB		 6134 kfree(intel_crtc);
6135}
6136
6b95a207
KH		 6137static void intel_unpin_work_fn(struct work_struct *__work)
6138{
6139 struct intel_unpin_work *work =
6140 container_of(__work, struct intel_unpin_work, work);
6141
6142 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6143 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6144 drm_gem_object_unreference(&work->pending_flip_obj->base);
6145 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6146
7782de3b 6147 intel_update_fbc(work->dev);
6b95a207
KH		 6148 mutex_unlock(&work->dev->struct_mutex);
6149 kfree(work);
6150}
6151
1afe3e9d 6152static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6153 struct drm_crtc *crtc)
6b95a207
KH		 6154{
6155 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157 struct intel_unpin_work *work;
05394f39 6158 struct drm_i915_gem_object *obj;
6b95a207 6159 struct drm_pending_vblank_event *e;
49b14a5c 6160 struct timeval tnow, tvbl;
6b95a207
KH		 6161 unsigned long flags;
6162
6163 /* Ignore early vblank irqs */
6164 if (intel_crtc == NULL)
6165 return;
6166
49b14a5c
MK		 6167 do_gettimeofday(&tnow);
6168
6b95a207
KH		 6169 spin_lock_irqsave(&dev->event_lock, flags);
6170 work = intel_crtc->unpin_work;
6171 if (work == NULL || !work->pending) {
6172 spin_unlock_irqrestore(&dev->event_lock, flags);
6173 return;
6174 }
6175
6176 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6177
6178 if (work->event) {
6179 e = work->event;
49b14a5c 6180 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6181
6182 /* Called before vblank count and timestamps have
6183 * been updated for the vblank interval of flip
6184 * completion? Need to increment vblank count and
6185 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6186 * to account for this. We assume this happened if we
6187 * get called over 0.9 frame durations after the last
6188 * timestamped vblank.
6189 *
6190 * This calculation can not be used with vrefresh rates
6191 * below 5Hz (10Hz to be on the safe side) without
6192 * promoting to 64 integers.
0af7e4df 6193 */
49b14a5c
MK		 6194 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6195 9 * crtc->framedur_ns) {
0af7e4df 6196 e->event.sequence++;
49b14a5c
MK		 6197 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6198 crtc->framedur_ns);
0af7e4df
MK		 6199 }
6200
49b14a5c
MK		 6201 e->event.tv_sec = tvbl.tv_sec;
6202 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6203
6b95a207
KH		 6204 list_add_tail(&e->base.link,
6205 &e->base.file_priv->event_list);
6206 wake_up_interruptible(&e->base.file_priv->event_wait);
6207 }
6208
0af7e4df
MK		 6209 drm_vblank_put(dev, intel_crtc->pipe);
6210
6b95a207
KH		 6211 spin_unlock_irqrestore(&dev->event_lock, flags);
6212
05394f39 6213 obj = work->old_fb_obj;
d9e86c0e 6214
e59f2bac 6215 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6216 &obj->pending_flip.counter);
6217 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6218 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6219
6b95a207 6220 schedule_work(&work->work);
e5510fac
JB		 6221
6222 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6223}
6224
1afe3e9d
JB		 6225void intel_finish_page_flip(struct drm_device *dev, int pipe)
6226{
6227 drm_i915_private_t *dev_priv = dev->dev_private;
6228 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6229
49b14a5c 6230 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6231}
6232
6233void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6234{
6235 drm_i915_private_t *dev_priv = dev->dev_private;
6236 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6237
49b14a5c 6238 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6239}
6240
6b95a207
KH		 6241void intel_prepare_page_flip(struct drm_device *dev, int plane)
6242{
6243 drm_i915_private_t *dev_priv = dev->dev_private;
6244 struct intel_crtc *intel_crtc =
6245 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6246 unsigned long flags;
6247
6248 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6249 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6250 if ((++intel_crtc->unpin_work->pending) > 1)
6251 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6252 } else {
6253 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6254 }
6b95a207
KH		 6255 spin_unlock_irqrestore(&dev->event_lock, flags);
6256}
6257
8c9f3aaf
JB		 6258static int intel_gen2_queue_flip(struct drm_device *dev,
6259 struct drm_crtc *crtc,
6260 struct drm_framebuffer *fb,
6261 struct drm_i915_gem_object *obj)
6262{
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6265 u32 flip_mask;
6d90c952 6266 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6267 int ret;
6268
6d90c952 6269 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6270 if (ret)
83d4092b 6271 goto err;
8c9f3aaf 6272
6d90c952 6273 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6274 if (ret)
83d4092b 6275 goto err_unpin;
8c9f3aaf
JB		 6276
6277 /* Can't queue multiple flips, so wait for the previous
6278 * one to finish before executing the next.
6279 */
6280 if (intel_crtc->plane)
6281 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6282 else
6283 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6284 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6285 intel_ring_emit(ring, MI_NOOP);
6286 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6287 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6288 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6289 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6290 intel_ring_emit(ring, 0); /* aux display base address, unused */
6291 intel_ring_advance(ring);
83d4092b
CW		 6292 return 0;
6293
6294err_unpin:
6295 intel_unpin_fb_obj(obj);
6296err:
8c9f3aaf
JB		 6297 return ret;
6298}
6299
6300static int intel_gen3_queue_flip(struct drm_device *dev,
6301 struct drm_crtc *crtc,
6302 struct drm_framebuffer *fb,
6303 struct drm_i915_gem_object *obj)
6304{
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6307 u32 flip_mask;
6d90c952 6308 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6309 int ret;
6310
6d90c952 6311 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6312 if (ret)
83d4092b 6313 goto err;
8c9f3aaf 6314
6d90c952 6315 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6316 if (ret)
83d4092b 6317 goto err_unpin;
8c9f3aaf
JB		 6318
6319 if (intel_crtc->plane)
6320 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6321 else
6322 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6323 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6324 intel_ring_emit(ring, MI_NOOP);
6325 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6326 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6327 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6328 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6329 intel_ring_emit(ring, MI_NOOP);
6330
6331 intel_ring_advance(ring);
83d4092b
CW		 6332 return 0;
6333
6334err_unpin:
6335 intel_unpin_fb_obj(obj);
6336err:
8c9f3aaf
JB		 6337 return ret;
6338}
6339
6340static int intel_gen4_queue_flip(struct drm_device *dev,
6341 struct drm_crtc *crtc,
6342 struct drm_framebuffer *fb,
6343 struct drm_i915_gem_object *obj)
6344{
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 uint32_t pf, pipesrc;
6d90c952 6348 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6349 int ret;
6350
6d90c952 6351 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6352 if (ret)
83d4092b 6353 goto err;
8c9f3aaf 6354
6d90c952 6355 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6356 if (ret)
83d4092b 6357 goto err_unpin;
8c9f3aaf
JB		 6358
6359 /* i965+ uses the linear or tiled offsets from the
6360 * Display Registers (which do not change across a page-flip)
6361 * so we need only reprogram the base address.
6362 */
6d90c952
DV		 6363 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6364 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6365 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6366 intel_ring_emit(ring,
6367 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6368 obj->tiling_mode);
8c9f3aaf
JB		 6369
6370 /* XXX Enabling the panel-fitter across page-flip is so far
6371 * untested on non-native modes, so ignore it for now.
6372 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6373 */
6374 pf = 0;
6375 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6376 intel_ring_emit(ring, pf | pipesrc);
6377 intel_ring_advance(ring);
83d4092b
CW		 6378 return 0;
6379
6380err_unpin:
6381 intel_unpin_fb_obj(obj);
6382err:
8c9f3aaf
JB		 6383 return ret;
6384}
6385
6386static int intel_gen6_queue_flip(struct drm_device *dev,
6387 struct drm_crtc *crtc,
6388 struct drm_framebuffer *fb,
6389 struct drm_i915_gem_object *obj)
6390{
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6393 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6394 uint32_t pf, pipesrc;
6395 int ret;
6396
6d90c952 6397 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6398 if (ret)
83d4092b 6399 goto err;
8c9f3aaf 6400
6d90c952 6401 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6402 if (ret)
83d4092b 6403 goto err_unpin;
8c9f3aaf 6404
6d90c952
DV		 6405 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6406 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6407 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6408 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6409
dc257cf1
DV		 6410 /* Contrary to the suggestions in the documentation,
6411 * "Enable Panel Fitter" does not seem to be required when page
6412 * flipping with a non-native mode, and worse causes a normal
6413 * modeset to fail.
6414 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6415 */
6416 pf = 0;
8c9f3aaf 6417 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6418 intel_ring_emit(ring, pf | pipesrc);
6419 intel_ring_advance(ring);
83d4092b
CW		 6420 return 0;
6421
6422err_unpin:
6423 intel_unpin_fb_obj(obj);
6424err:
8c9f3aaf
JB		 6425 return ret;
6426}
6427
7c9017e5
JB		 6428/*
6429 * On gen7 we currently use the blit ring because (in early silicon at least)
6430 * the render ring doesn't give us interrpts for page flip completion, which
6431 * means clients will hang after the first flip is queued. Fortunately the
6432 * blit ring generates interrupts properly, so use it instead.
6433 */
6434static int intel_gen7_queue_flip(struct drm_device *dev,
6435 struct drm_crtc *crtc,
6436 struct drm_framebuffer *fb,
6437 struct drm_i915_gem_object *obj)
6438{
6439 struct drm_i915_private *dev_priv = dev->dev_private;
6440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6441 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6442 uint32_t plane_bit = 0;
7c9017e5
JB		 6443 int ret;
6444
6445 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6446 if (ret)
83d4092b 6447 goto err;
7c9017e5 6448
cb05d8de
DV		 6449 switch(intel_crtc->plane) {
6450 case PLANE_A:
6451 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6452 break;
6453 case PLANE_B:
6454 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6455 break;
6456 case PLANE_C:
6457 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6458 break;
6459 default:
6460 WARN_ONCE(1, "unknown plane in flip command\n");
6461 ret = -ENODEV;
ab3951eb 6462 goto err_unpin;
cb05d8de
DV		 6463 }
6464
7c9017e5
JB		 6465 ret = intel_ring_begin(ring, 4);
6466 if (ret)
83d4092b 6467 goto err_unpin;
7c9017e5 6468
cb05d8de 6469 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6470 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6471 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6472 intel_ring_emit(ring, (MI_NOOP));
6473 intel_ring_advance(ring);
83d4092b
CW		 6474 return 0;
6475
6476err_unpin:
6477 intel_unpin_fb_obj(obj);
6478err:
7c9017e5
JB		 6479 return ret;
6480}
6481
8c9f3aaf
JB		 6482static int intel_default_queue_flip(struct drm_device *dev,
6483 struct drm_crtc *crtc,
6484 struct drm_framebuffer *fb,
6485 struct drm_i915_gem_object *obj)
6486{
6487 return -ENODEV;
6488}
6489
6b95a207
KH		 6490static int intel_crtc_page_flip(struct drm_crtc *crtc,
6491 struct drm_framebuffer *fb,
6492 struct drm_pending_vblank_event *event)
6493{
6494 struct drm_device *dev = crtc->dev;
6495 struct drm_i915_private *dev_priv = dev->dev_private;
6496 struct intel_framebuffer *intel_fb;
05394f39 6497 struct drm_i915_gem_object *obj;
6b95a207
KH		 6498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6499 struct intel_unpin_work *work;
8c9f3aaf 6500 unsigned long flags;
52e68630 6501 int ret;
6b95a207 6502
e6a595d2
VS		 6503 /* Can't change pixel format via MI display flips. */
6504 if (fb->pixel_format != crtc->fb->pixel_format)
6505 return -EINVAL;
6506
6507 /*
6508 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6509 * Note that pitch changes could also affect these register.
6510 */
6511 if (INTEL_INFO(dev)->gen > 3 &&
6512 (fb->offsets[0] != crtc->fb->offsets[0] ||
6513 fb->pitches[0] != crtc->fb->pitches[0]))
6514 return -EINVAL;
6515
6b95a207
KH		 6516 work = kzalloc(sizeof *work, GFP_KERNEL);
6517 if (work == NULL)
6518 return -ENOMEM;
6519
6b95a207
KH		 6520 work->event = event;
6521 work->dev = crtc->dev;
6522 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6523 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6524 INIT_WORK(&work->work, intel_unpin_work_fn);
6525
7317c75e
JB		 6526 ret = drm_vblank_get(dev, intel_crtc->pipe);
6527 if (ret)
6528 goto free_work;
6529
6b95a207
KH		 6530 /* We borrow the event spin lock for protecting unpin_work */
6531 spin_lock_irqsave(&dev->event_lock, flags);
6532 if (intel_crtc->unpin_work) {
6533 spin_unlock_irqrestore(&dev->event_lock, flags);
6534 kfree(work);
7317c75e 6535 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6536
6537 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6538 return -EBUSY;
6539 }
6540 intel_crtc->unpin_work = work;
6541 spin_unlock_irqrestore(&dev->event_lock, flags);
6542
6543 intel_fb = to_intel_framebuffer(fb);
6544 obj = intel_fb->obj;
6545
79158103
CW		 6546 ret = i915_mutex_lock_interruptible(dev);
6547 if (ret)
6548 goto cleanup;
6b95a207 6549
75dfca80 6550 /* Reference the objects for the scheduled work. */
05394f39
CW		 6551 drm_gem_object_reference(&work->old_fb_obj->base);
6552 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6553
6554 crtc->fb = fb;
96b099fd 6555
e1f99ce6 6556 work->pending_flip_obj = obj;
e1f99ce6 6557
4e5359cd
SF		 6558 work->enable_stall_check = true;
6559
e1f99ce6
CW		 6560 /* Block clients from rendering to the new back buffer until
6561 * the flip occurs and the object is no longer visible.
6562 */
05394f39 6563 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6564
8c9f3aaf
JB		 6565 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6566 if (ret)
6567 goto cleanup_pending;
6b95a207 6568
7782de3b 6569 intel_disable_fbc(dev);
f047e395 6570 intel_mark_fb_busy(obj);
6b95a207
KH		 6571 mutex_unlock(&dev->struct_mutex);
6572
e5510fac
JB		 6573 trace_i915_flip_request(intel_crtc->plane, obj);
6574
6b95a207 6575 return 0;
96b099fd 6576
8c9f3aaf
JB		 6577cleanup_pending:
6578 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6579 drm_gem_object_unreference(&work->old_fb_obj->base);
6580 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6581 mutex_unlock(&dev->struct_mutex);
6582
79158103 6583cleanup:
96b099fd
CW		 6584 spin_lock_irqsave(&dev->event_lock, flags);
6585 intel_crtc->unpin_work = NULL;
6586 spin_unlock_irqrestore(&dev->event_lock, flags);
6587
7317c75e
JB		 6588 drm_vblank_put(dev, intel_crtc->pipe);
6589free_work:
96b099fd
CW		 6590 kfree(work);
6591
6592 return ret;
6b95a207
KH		 6593}
6594
f6e5b160 6595static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6596 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6597 .load_lut = intel_crtc_load_lut,
976f8a20 6598 .disable = intel_crtc_noop,
f6e5b160
CW		 6599};
6600
6ed0f796 6601bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 6602{
6ed0f796
DV		 6603 struct intel_encoder *other_encoder;
6604 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 6605
6ed0f796
DV		 6606 if (WARN_ON(!crtc))
6607 return false;
6608
6609 list_for_each_entry(other_encoder,
6610 &crtc->dev->mode_config.encoder_list,
6611 base.head) {
6612
6613 if (&other_encoder->new_crtc->base != crtc ||
6614 encoder == other_encoder)
6615 continue;
6616 else
6617 return true;
f47166d2
CW		 6618 }
6619
6ed0f796
DV		 6620 return false;
6621}
47f1c6c9 6622
50f56119
DV		 6623static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6624 struct drm_crtc *crtc)
6625{
6626 struct drm_device *dev;
6627 struct drm_crtc *tmp;
6628 int crtc_mask = 1;
47f1c6c9 6629
50f56119 6630 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 6631
50f56119 6632 dev = crtc->dev;
47f1c6c9 6633
50f56119
DV		 6634 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6635 if (tmp == crtc)
6636 break;
6637 crtc_mask <<= 1;
6638 }
47f1c6c9 6639
50f56119
DV		 6640 if (encoder->possible_crtcs & crtc_mask)
6641 return true;
6642 return false;
47f1c6c9 6643}
79e53945 6644
9a935856
DV		 6645/**
6646 * intel_modeset_update_staged_output_state
6647 *
6648 * Updates the staged output configuration state, e.g. after we've read out the
6649 * current hw state.
6650 */
6651static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 6652{
9a935856
DV		 6653 struct intel_encoder *encoder;
6654 struct intel_connector *connector;
f6e5b160 6655
9a935856
DV		 6656 list_for_each_entry(connector, &dev->mode_config.connector_list,
6657 base.head) {
6658 connector->new_encoder =
6659 to_intel_encoder(connector->base.encoder);
6660 }
f6e5b160 6661
9a935856
DV		 6662 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6663 base.head) {
6664 encoder->new_crtc =
6665 to_intel_crtc(encoder->base.crtc);
6666 }
f6e5b160
CW		 6667}
6668
9a935856
DV		 6669/**
6670 * intel_modeset_commit_output_state
6671 *
6672 * This function copies the stage display pipe configuration to the real one.
6673 */
6674static void intel_modeset_commit_output_state(struct drm_device *dev)
6675{
6676 struct intel_encoder *encoder;
6677 struct intel_connector *connector;
f6e5b160 6678
9a935856
DV		 6679 list_for_each_entry(connector, &dev->mode_config.connector_list,
6680 base.head) {
6681 connector->base.encoder = &connector->new_encoder->base;
6682 }
f6e5b160 6683
9a935856
DV		 6684 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6685 base.head) {
6686 encoder->base.crtc = &encoder->new_crtc->base;
6687 }
6688}
6689
7758a113
DV		 6690static struct drm_display_mode *
6691intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6692 struct drm_display_mode *mode)
ee7b9f93 6693{
7758a113
DV		 6694 struct drm_device *dev = crtc->dev;
6695 struct drm_display_mode *adjusted_mode;
6696 struct drm_encoder_helper_funcs *encoder_funcs;
6697 struct intel_encoder *encoder;
ee7b9f93 6698
7758a113
DV		 6699 adjusted_mode = drm_mode_duplicate(dev, mode);
6700 if (!adjusted_mode)
6701 return ERR_PTR(-ENOMEM);
6702
6703 /* Pass our mode to the connectors and the CRTC to give them a chance to
6704 * adjust it according to limitations or connector properties, and also
6705 * a chance to reject the mode entirely.
6706 */
6707 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6708 base.head) {
6709
6710 if (&encoder->new_crtc->base != crtc)
6711 continue;
6712 encoder_funcs = encoder->base.helper_private;
6713 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6714 adjusted_mode))) {
6715 DRM_DEBUG_KMS("Encoder fixup failed\n");
6716 goto fail;
6717 }
ee7b9f93
JB		 6718 }
6719
7758a113
DV		 6720 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6721 DRM_DEBUG_KMS("CRTC fixup failed\n");
6722 goto fail;
ee7b9f93 6723 }
7758a113
DV		 6724 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6725
6726 return adjusted_mode;
6727fail:
6728 drm_mode_destroy(dev, adjusted_mode);
6729 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 6730}
6731
e2e1ed41
DV		 6732/* Computes which crtcs are affected and sets the relevant bits in the mask. For
6733 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6734static void
6735intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6736 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 6737{
6738 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 6739 struct drm_device *dev = crtc->dev;
6740 struct intel_encoder *encoder;
6741 struct intel_connector *connector;
6742 struct drm_crtc *tmp_crtc;
79e53945 6743
e2e1ed41 6744 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 6745
e2e1ed41
DV		 6746 /* Check which crtcs have changed outputs connected to them, these need
6747 * to be part of the prepare_pipes mask. We don't (yet) support global
6748 * modeset across multiple crtcs, so modeset_pipes will only have one
6749 * bit set at most. */
6750 list_for_each_entry(connector, &dev->mode_config.connector_list,
6751 base.head) {
6752 if (connector->base.encoder == &connector->new_encoder->base)
6753 continue;
79e53945 6754
e2e1ed41
DV		 6755 if (connector->base.encoder) {
6756 tmp_crtc = connector->base.encoder->crtc;
6757
6758 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6759 }
6760
6761 if (connector->new_encoder)
6762 *prepare_pipes |=
6763 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 6764 }
6765
e2e1ed41
DV		 6766 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6767 base.head) {
6768 if (encoder->base.crtc == &encoder->new_crtc->base)
6769 continue;
6770
6771 if (encoder->base.crtc) {
6772 tmp_crtc = encoder->base.crtc;
6773
6774 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6775 }
6776
6777 if (encoder->new_crtc)
6778 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 6779 }
6780
e2e1ed41
DV		 6781 /* Check for any pipes that will be fully disabled ... */
6782 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6783 base.head) {
6784 bool used = false;
22fd0fab 6785
e2e1ed41
DV		 6786 /* Don't try to disable disabled crtcs. */
6787 if (!intel_crtc->base.enabled)
6788 continue;
7e7d76c3 6789
e2e1ed41
DV		 6790 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6791 base.head) {
6792 if (encoder->new_crtc == intel_crtc)
6793 used = true;
6794 }
6795
6796 if (!used)
6797 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 6798 }
6799
e2e1ed41
DV		 6800
6801 /* set_mode is also used to update properties on life display pipes. */
6802 intel_crtc = to_intel_crtc(crtc);
6803 if (crtc->enabled)
6804 *prepare_pipes |= 1 << intel_crtc->pipe;
6805
6806 /* We only support modeset on one single crtc, hence we need to do that
6807 * only for the passed in crtc iff we change anything else than just
6808 * disable crtcs.
6809 *
6810 * This is actually not true, to be fully compatible with the old crtc
6811 * helper we automatically disable _any_ output (i.e. doesn't need to be
6812 * connected to the crtc we're modesetting on) if it's disconnected.
6813 * Which is a rather nutty api (since changed the output configuration
6814 * without userspace's explicit request can lead to confusion), but
6815 * alas. Hence we currently need to modeset on all pipes we prepare. */
6816 if (*prepare_pipes)
6817 *modeset_pipes = *prepare_pipes;
6818
6819 /* ... and mask these out. */
6820 *modeset_pipes &= ~(*disable_pipes);
6821 *prepare_pipes &= ~(*disable_pipes);
6822}
6823
ea9d758d
DV		 6824static bool intel_crtc_in_use(struct drm_crtc *crtc)
6825{
6826 struct drm_encoder *encoder;
6827 struct drm_device *dev = crtc->dev;
6828
6829 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6830 if (encoder->crtc == crtc)
6831 return true;
6832
6833 return false;
6834}
6835
6836static void
6837intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6838{
6839 struct intel_encoder *intel_encoder;
6840 struct intel_crtc *intel_crtc;
6841 struct drm_connector *connector;
6842
6843 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6844 base.head) {
6845 if (!intel_encoder->base.crtc)
6846 continue;
6847
6848 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6849
6850 if (prepare_pipes & (1 << intel_crtc->pipe))
6851 intel_encoder->connectors_active = false;
6852 }
6853
6854 intel_modeset_commit_output_state(dev);
6855
6856 /* Update computed state. */
6857 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6858 base.head) {
6859 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6860 }
6861
6862 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6863 if (!connector->encoder || !connector->encoder->crtc)
6864 continue;
6865
6866 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6867
6868 if (prepare_pipes & (1 << intel_crtc->pipe)) {
6869 connector->dpms = DRM_MODE_DPMS_ON;
6870
6871 intel_encoder = to_intel_encoder(connector->encoder);
6872 intel_encoder->connectors_active = true;
6873 }
6874 }
6875
6876}
6877
25c5b266
DV		 6878#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6879 list_for_each_entry((intel_crtc), \
6880 &(dev)->mode_config.crtc_list, \
6881 base.head) \
6882 if (mask & (1 <<(intel_crtc)->pipe)) \
6883
b980514c 6884void
8af6cf88
DV		 6885intel_modeset_check_state(struct drm_device *dev)
6886{
6887 struct intel_crtc *crtc;
6888 struct intel_encoder *encoder;
6889 struct intel_connector *connector;
6890
6891 list_for_each_entry(connector, &dev->mode_config.connector_list,
6892 base.head) {
6893 /* This also checks the encoder/connector hw state with the
6894 * ->get_hw_state callbacks. */
6895 intel_connector_check_state(connector);
6896
6897 WARN(&connector->new_encoder->base != connector->base.encoder,
6898 "connector's staged encoder doesn't match current encoder\n");
6899 }
6900
6901 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6902 base.head) {
6903 bool enabled = false;
6904 bool active = false;
6905 enum pipe pipe, tracked_pipe;
6906
6907 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6908 encoder->base.base.id,
6909 drm_get_encoder_name(&encoder->base));
6910
6911 WARN(&encoder->new_crtc->base != encoder->base.crtc,
6912 "encoder's stage crtc doesn't match current crtc\n");
6913 WARN(encoder->connectors_active && !encoder->base.crtc,
6914 "encoder's active_connectors set, but no crtc\n");
6915
6916 list_for_each_entry(connector, &dev->mode_config.connector_list,
6917 base.head) {
6918 if (connector->base.encoder != &encoder->base)
6919 continue;
6920 enabled = true;
6921 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
6922 active = true;
6923 }
6924 WARN(!!encoder->base.crtc != enabled,
6925 "encoder's enabled state mismatch "
6926 "(expected %i, found %i)\n",
6927 !!encoder->base.crtc, enabled);
6928 WARN(active && !encoder->base.crtc,
6929 "active encoder with no crtc\n");
6930
6931 WARN(encoder->connectors_active != active,
6932 "encoder's computed active state doesn't match tracked active state "
6933 "(expected %i, found %i)\n", active, encoder->connectors_active);
6934
6935 active = encoder->get_hw_state(encoder, &pipe);
6936 WARN(active != encoder->connectors_active,
6937 "encoder's hw state doesn't match sw tracking "
6938 "(expected %i, found %i)\n",
6939 encoder->connectors_active, active);
6940
6941 if (!encoder->base.crtc)
6942 continue;
6943
6944 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
6945 WARN(active && pipe != tracked_pipe,
6946 "active encoder's pipe doesn't match"
6947 "(expected %i, found %i)\n",
6948 tracked_pipe, pipe);
6949
6950 }
6951
6952 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
6953 base.head) {
6954 bool enabled = false;
6955 bool active = false;
6956
6957 DRM_DEBUG_KMS("[CRTC:%d]\n",
6958 crtc->base.base.id);
6959
6960 WARN(crtc->active && !crtc->base.enabled,
6961 "active crtc, but not enabled in sw tracking\n");
6962
6963 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6964 base.head) {
6965 if (encoder->base.crtc != &crtc->base)
6966 continue;
6967 enabled = true;
6968 if (encoder->connectors_active)
6969 active = true;
6970 }
6971 WARN(active != crtc->active,
6972 "crtc's computed active state doesn't match tracked active state "
6973 "(expected %i, found %i)\n", active, crtc->active);
6974 WARN(enabled != crtc->base.enabled,
6975 "crtc's computed enabled state doesn't match tracked enabled state "
6976 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
6977
6978 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
6979 }
6980}
6981
a6778b3c
DV		 6982bool intel_set_mode(struct drm_crtc *crtc,
6983 struct drm_display_mode *mode,
94352cf9 6984 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 6985{
6986 struct drm_device *dev = crtc->dev;
dbf2b54e 6987 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 6988 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 6989 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 6990 struct drm_encoder *encoder;
25c5b266
DV		 6991 struct intel_crtc *intel_crtc;
6992 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 6993 bool ret = true;
6994
e2e1ed41 6995 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 6996 &prepare_pipes, &disable_pipes);
6997
6998 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
6999 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7000
976f8a20
DV		 7001 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7002 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7003
a6778b3c
DV		 7004 saved_hwmode = crtc->hwmode;
7005 saved_mode = crtc->mode;
a6778b3c 7006
25c5b266
DV		 7007 /* Hack: Because we don't (yet) support global modeset on multiple
7008 * crtcs, we don't keep track of the new mode for more than one crtc.
7009 * Hence simply check whether any bit is set in modeset_pipes in all the
7010 * pieces of code that are not yet converted to deal with mutliple crtcs
7011 * changing their mode at the same time. */
7012 adjusted_mode = NULL;
7013 if (modeset_pipes) {
7014 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7015 if (IS_ERR(adjusted_mode)) {
7016 return false;
7017 }
25c5b266 7018 }
a6778b3c 7019
ea9d758d
DV		 7020 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7021 if (intel_crtc->base.enabled)
7022 dev_priv->display.crtc_disable(&intel_crtc->base);
7023 }
a6778b3c 7024
6c4c86f5
DV		 7025 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7026 * to set it here already despite that we pass it down the callchain.
7027 */
7028 if (modeset_pipes)
25c5b266 7029 crtc->mode = *mode;
7758a113 7030
ea9d758d
DV		 7031 /* Only after disabling all output pipelines that will be changed can we
7032 * update the the output configuration. */
7033 intel_modeset_update_state(dev, prepare_pipes);
7034
a6778b3c
DV		 7035 /* Set up the DPLL and any encoders state that needs to adjust or depend
7036 * on the DPLL.
7037 */
25c5b266
DV		 7038 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7039 ret = !intel_crtc_mode_set(&intel_crtc->base,
7040 mode, adjusted_mode,
7041 x, y, fb);
7042 if (!ret)
7043 goto done;
a6778b3c 7044
25c5b266 7045 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7046
25c5b266
DV		 7047 if (encoder->crtc != &intel_crtc->base)
7048 continue;
a6778b3c 7049
25c5b266
DV		 7050 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7051 encoder->base.id, drm_get_encoder_name(encoder),
7052 mode->base.id, mode->name);
7053 encoder_funcs = encoder->helper_private;
7054 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7055 }
a6778b3c
DV		 7056 }
7057
7058 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7059 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7060 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7061
25c5b266
DV		 7062 if (modeset_pipes) {
7063 /* Store real post-adjustment hardware mode. */
7064 crtc->hwmode = *adjusted_mode;
a6778b3c 7065
25c5b266
DV		 7066 /* Calculate and store various constants which
7067 * are later needed by vblank and swap-completion
7068 * timestamping. They are derived from true hwmode.
7069 */
7070 drm_calc_timestamping_constants(crtc);
7071 }
a6778b3c
DV		 7072
7073 /* FIXME: add subpixel order */
7074done:
7075 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7076 if (!ret && crtc->enabled) {
a6778b3c
DV		 7077 crtc->hwmode = saved_hwmode;
7078 crtc->mode = saved_mode;
8af6cf88
DV		 7079 } else {
7080 intel_modeset_check_state(dev);
a6778b3c
DV		 7081 }
7082
7083 return ret;
7084}
7085
25c5b266
DV		 7086#undef for_each_intel_crtc_masked
7087
d9e55608
DV		 7088static void intel_set_config_free(struct intel_set_config *config)
7089{
7090 if (!config)
7091 return;
7092
1aa4b628
DV		 7093 kfree(config->save_connector_encoders);
7094 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7095 kfree(config);
7096}
7097
85f9eb71
DV		 7098static int intel_set_config_save_state(struct drm_device *dev,
7099 struct intel_set_config *config)
7100{
85f9eb71
DV		 7101 struct drm_encoder *encoder;
7102 struct drm_connector *connector;
7103 int count;
7104
1aa4b628
DV		 7105 config->save_encoder_crtcs =
7106 kcalloc(dev->mode_config.num_encoder,
7107 sizeof(struct drm_crtc *), GFP_KERNEL);
7108 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7109 return -ENOMEM;
7110
1aa4b628
DV		 7111 config->save_connector_encoders =
7112 kcalloc(dev->mode_config.num_connector,
7113 sizeof(struct drm_encoder *), GFP_KERNEL);
7114 if (!config->save_connector_encoders)
85f9eb71
DV		 7115 return -ENOMEM;
7116
7117 /* Copy data. Note that driver private data is not affected.
7118 * Should anything bad happen only the expected state is
7119 * restored, not the drivers personal bookkeeping.
7120 */
85f9eb71
DV		 7121 count = 0;
7122 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7123 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7124 }
7125
7126 count = 0;
7127 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7128 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7129 }
7130
7131 return 0;
7132}
7133
7134static void intel_set_config_restore_state(struct drm_device *dev,
7135 struct intel_set_config *config)
7136{
9a935856
DV		 7137 struct intel_encoder *encoder;
7138 struct intel_connector *connector;
85f9eb71
DV		 7139 int count;
7140
85f9eb71 7141 count = 0;
9a935856
DV		 7142 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7143 encoder->new_crtc =
7144 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7145 }
7146
7147 count = 0;
9a935856
DV		 7148 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7149 connector->new_encoder =
7150 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7151 }
7152}
7153
5e2b584e
DV		 7154static void
7155intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7156 struct intel_set_config *config)
7157{
7158
7159 /* We should be able to check here if the fb has the same properties
7160 * and then just flip_or_move it */
7161 if (set->crtc->fb != set->fb) {
7162 /* If we have no fb then treat it as a full mode set */
7163 if (set->crtc->fb == NULL) {
7164 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7165 config->mode_changed = true;
7166 } else if (set->fb == NULL) {
7167 config->mode_changed = true;
7168 } else if (set->fb->depth != set->crtc->fb->depth) {
7169 config->mode_changed = true;
7170 } else if (set->fb->bits_per_pixel !=
7171 set->crtc->fb->bits_per_pixel) {
7172 config->mode_changed = true;
7173 } else
7174 config->fb_changed = true;
7175 }
7176
835c5873 7177 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7178 config->fb_changed = true;
7179
7180 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7181 DRM_DEBUG_KMS("modes are different, full mode set\n");
7182 drm_mode_debug_printmodeline(&set->crtc->mode);
7183 drm_mode_debug_printmodeline(set->mode);
7184 config->mode_changed = true;
7185 }
7186}
7187
2e431051 7188static int
9a935856
DV		 7189intel_modeset_stage_output_state(struct drm_device *dev,
7190 struct drm_mode_set *set,
7191 struct intel_set_config *config)
50f56119 7192{
85f9eb71 7193 struct drm_crtc *new_crtc;
9a935856
DV		 7194 struct intel_connector *connector;
7195 struct intel_encoder *encoder;
2e431051 7196 int count, ro;
50f56119 7197
9a935856
DV		 7198 /* The upper layers ensure that we either disabl a crtc or have a list
7199 * of connectors. For paranoia, double-check this. */
7200 WARN_ON(!set->fb && (set->num_connectors != 0));
7201 WARN_ON(set->fb && (set->num_connectors == 0));
7202
50f56119 7203 count = 0;
9a935856
DV		 7204 list_for_each_entry(connector, &dev->mode_config.connector_list,
7205 base.head) {
7206 /* Otherwise traverse passed in connector list and get encoders
7207 * for them. */
50f56119 7208 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7209 if (set->connectors[ro] == &connector->base) {
7210 connector->new_encoder = connector->encoder;
50f56119
DV		 7211 break;
7212 }
7213 }
7214
9a935856
DV		 7215 /* If we disable the crtc, disable all its connectors. Also, if
7216 * the connector is on the changing crtc but not on the new
7217 * connector list, disable it. */
7218 if ((!set->fb || ro == set->num_connectors) &&
7219 connector->base.encoder &&
7220 connector->base.encoder->crtc == set->crtc) {
7221 connector->new_encoder = NULL;
7222
7223 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7224 connector->base.base.id,
7225 drm_get_connector_name(&connector->base));
7226 }
7227
7228
7229 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7230 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7231 config->mode_changed = true;
50f56119 7232 }
9a935856
DV		 7233
7234 /* Disable all disconnected encoders. */
7235 if (connector->base.status == connector_status_disconnected)
7236 connector->new_encoder = NULL;
50f56119 7237 }
9a935856 7238 /* connector->new_encoder is now updated for all connectors. */
50f56119 7239
9a935856 7240 /* Update crtc of enabled connectors. */
50f56119 7241 count = 0;
9a935856
DV		 7242 list_for_each_entry(connector, &dev->mode_config.connector_list,
7243 base.head) {
7244 if (!connector->new_encoder)
50f56119
DV		 7245 continue;
7246
9a935856 7247 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7248
7249 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7250 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7251 new_crtc = set->crtc;
7252 }
7253
7254 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7255 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7256 new_crtc)) {
5e2b584e 7257 return -EINVAL;
50f56119 7258 }
9a935856
DV		 7259 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7260
7261 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7262 connector->base.base.id,
7263 drm_get_connector_name(&connector->base),
7264 new_crtc->base.id);
7265 }
7266
7267 /* Check for any encoders that needs to be disabled. */
7268 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7269 base.head) {
7270 list_for_each_entry(connector,
7271 &dev->mode_config.connector_list,
7272 base.head) {
7273 if (connector->new_encoder == encoder) {
7274 WARN_ON(!connector->new_encoder->new_crtc);
7275
7276 goto next_encoder;
7277 }
7278 }
7279 encoder->new_crtc = NULL;
7280next_encoder:
7281 /* Only now check for crtc changes so we don't miss encoders
7282 * that will be disabled. */
7283 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7284 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7285 config->mode_changed = true;
50f56119
DV		 7286 }
7287 }
9a935856 7288 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7289
2e431051
DV		 7290 return 0;
7291}
7292
7293static int intel_crtc_set_config(struct drm_mode_set *set)
7294{
7295 struct drm_device *dev;
2e431051
DV		 7296 struct drm_mode_set save_set;
7297 struct intel_set_config *config;
7298 int ret;
2e431051 7299
8d3e375e
DV		 7300 BUG_ON(!set);
7301 BUG_ON(!set->crtc);
7302 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7303
7304 if (!set->mode)
7305 set->fb = NULL;
7306
431e50f7
DV		 7307 /* The fb helper likes to play gross jokes with ->mode_set_config.
7308 * Unfortunately the crtc helper doesn't do much at all for this case,
7309 * so we have to cope with this madness until the fb helper is fixed up. */
7310 if (set->fb && set->num_connectors == 0)
7311 return 0;
7312
2e431051
DV		 7313 if (set->fb) {
7314 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7315 set->crtc->base.id, set->fb->base.id,
7316 (int)set->num_connectors, set->x, set->y);
7317 } else {
7318 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7319 }
7320
7321 dev = set->crtc->dev;
7322
7323 ret = -ENOMEM;
7324 config = kzalloc(sizeof(*config), GFP_KERNEL);
7325 if (!config)
7326 goto out_config;
7327
7328 ret = intel_set_config_save_state(dev, config);
7329 if (ret)
7330 goto out_config;
7331
7332 save_set.crtc = set->crtc;
7333 save_set.mode = &set->crtc->mode;
7334 save_set.x = set->crtc->x;
7335 save_set.y = set->crtc->y;
7336 save_set.fb = set->crtc->fb;
7337
7338 /* Compute whether we need a full modeset, only an fb base update or no
7339 * change at all. In the future we might also check whether only the
7340 * mode changed, e.g. for LVDS where we only change the panel fitter in
7341 * such cases. */
7342 intel_set_config_compute_mode_changes(set, config);
7343
9a935856 7344 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7345 if (ret)
7346 goto fail;
7347
5e2b584e 7348 if (config->mode_changed) {
87f1faa6 7349 if (set->mode) {
50f56119
DV		 7350 DRM_DEBUG_KMS("attempting to set mode from"
7351 " userspace\n");
7352 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7353 }
7354
7355 if (!intel_set_mode(set->crtc, set->mode,
7356 set->x, set->y, set->fb)) {
7357 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7358 set->crtc->base.id);
7359 ret = -EINVAL;
7360 goto fail;
7361 }
5e2b584e 7362 } else if (config->fb_changed) {
4f660f49 7363 ret = intel_pipe_set_base(set->crtc,
94352cf9 7364 set->x, set->y, set->fb);
50f56119
DV		 7365 }
7366
d9e55608
DV		 7367 intel_set_config_free(config);
7368
50f56119
DV		 7369 return 0;
7370
7371fail:
85f9eb71 7372 intel_set_config_restore_state(dev, config);
50f56119
DV		 7373
7374 /* Try to restore the config */
5e2b584e 7375 if (config->mode_changed &&
a6778b3c
DV		 7376 !intel_set_mode(save_set.crtc, save_set.mode,
7377 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7378 DRM_ERROR("failed to restore config after modeset failure\n");
7379
d9e55608
DV		 7380out_config:
7381 intel_set_config_free(config);
50f56119
DV		 7382 return ret;
7383}
7384
f6e5b160 7385static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7386 .cursor_set = intel_crtc_cursor_set,
7387 .cursor_move = intel_crtc_cursor_move,
7388 .gamma_set = intel_crtc_gamma_set,
50f56119 7389 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7390 .destroy = intel_crtc_destroy,
7391 .page_flip = intel_crtc_page_flip,
7392};
7393
ee7b9f93
JB		 7394static void intel_pch_pll_init(struct drm_device *dev)
7395{
7396 drm_i915_private_t *dev_priv = dev->dev_private;
7397 int i;
7398
7399 if (dev_priv->num_pch_pll == 0) {
7400 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7401 return;
7402 }
7403
7404 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7405 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7406 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7407 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7408 }
7409}
7410
b358d0a6 7411static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7412{
22fd0fab 7413 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7414 struct intel_crtc *intel_crtc;
7415 int i;
7416
7417 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7418 if (intel_crtc == NULL)
7419 return;
7420
7421 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7422
7423 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7424 for (i = 0; i < 256; i++) {
7425 intel_crtc->lut_r[i] = i;
7426 intel_crtc->lut_g[i] = i;
7427 intel_crtc->lut_b[i] = i;
7428 }
7429
80824003
JB		 7430 /* Swap pipes & planes for FBC on pre-965 */
7431 intel_crtc->pipe = pipe;
7432 intel_crtc->plane = pipe;
e2e767ab 7433 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7434 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7435 intel_crtc->plane = !pipe;
80824003
JB		 7436 }
7437
22fd0fab
JB		 7438 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7439 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7440 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7441 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7442
5a354204 7443 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7444
79e53945 7445 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7446}
7447
08d7b3d1 7448int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7449 struct drm_file *file)
08d7b3d1 7450{
08d7b3d1 7451 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7452 struct drm_mode_object *drmmode_obj;
7453 struct intel_crtc *crtc;
08d7b3d1 7454
1cff8f6b
DV		 7455 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7456 return -ENODEV;
08d7b3d1 7457
c05422d5
DV		 7458 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7459 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7460
c05422d5 7461 if (!drmmode_obj) {
08d7b3d1
CW		 7462 DRM_ERROR("no such CRTC id\n");
7463 return -EINVAL;
7464 }
7465
c05422d5
DV		 7466 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7467 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7468
c05422d5 7469 return 0;
08d7b3d1
CW		 7470}
7471
66a9278e 7472static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7473{
66a9278e
DV		 7474 struct drm_device *dev = encoder->base.dev;
7475 struct intel_encoder *source_encoder;
79e53945 7476 int index_mask = 0;
79e53945
JB		 7477 int entry = 0;
7478
66a9278e
DV		 7479 list_for_each_entry(source_encoder,
7480 &dev->mode_config.encoder_list, base.head) {
7481
7482 if (encoder == source_encoder)
79e53945 7483 index_mask |= (1 << entry);
66a9278e
DV		 7484
7485 /* Intel hw has only one MUX where enocoders could be cloned. */
7486 if (encoder->cloneable && source_encoder->cloneable)
7487 index_mask |= (1 << entry);
7488
79e53945
JB		 7489 entry++;
7490 }
4ef69c7a 7491
79e53945
JB		 7492 return index_mask;
7493}
7494
4d302442
CW		 7495static bool has_edp_a(struct drm_device *dev)
7496{
7497 struct drm_i915_private *dev_priv = dev->dev_private;
7498
7499 if (!IS_MOBILE(dev))
7500 return false;
7501
7502 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7503 return false;
7504
7505 if (IS_GEN5(dev) &&
7506 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7507 return false;
7508
7509 return true;
7510}
7511
79e53945
JB		 7512static void intel_setup_outputs(struct drm_device *dev)
7513{
725e30ad 7514 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7515 struct intel_encoder *encoder;
cb0953d7 7516 bool dpd_is_edp = false;
f3cfcba6 7517 bool has_lvds;
79e53945 7518
f3cfcba6 7519 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7520 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7521 /* disable the panel fitter on everything but LVDS */
7522 I915_WRITE(PFIT_CONTROL, 0);
7523 }
79e53945 7524
bad720ff 7525 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7526 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7527
4d302442 7528 if (has_edp_a(dev))
ab9d7c30 7529 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7530
cb0953d7 7531 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7532 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7533 }
7534
7535 intel_crt_init(dev);
7536
0e72a5b5
ED		 7537 if (IS_HASWELL(dev)) {
7538 int found;
7539
7540 /* Haswell uses DDI functions to detect digital outputs */
7541 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7542 /* DDI A only supports eDP */
7543 if (found)
7544 intel_ddi_init(dev, PORT_A);
7545
7546 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7547 * register */
7548 found = I915_READ(SFUSE_STRAP);
7549
7550 if (found & SFUSE_STRAP_DDIB_DETECTED)
7551 intel_ddi_init(dev, PORT_B);
7552 if (found & SFUSE_STRAP_DDIC_DETECTED)
7553 intel_ddi_init(dev, PORT_C);
7554 if (found & SFUSE_STRAP_DDID_DETECTED)
7555 intel_ddi_init(dev, PORT_D);
7556 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7557 int found;
7558
30ad48b7 7559 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7560 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7561 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7562 if (!found)
08d644ad 7563 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7564 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7565 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7566 }
7567
7568 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7569 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7570
b708a1d5 7571 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7572 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7573
5eb08b69 7574 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7575 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7576
cb0953d7 7577 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7578 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7579 } else if (IS_VALLEYVIEW(dev)) {
7580 int found;
7581
7582 if (I915_READ(SDVOB) & PORT_DETECTED) {
7583 /* SDVOB multiplex with HDMIB */
7584 found = intel_sdvo_init(dev, SDVOB, true);
7585 if (!found)
08d644ad 7586 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7587 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7588 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7589 }
7590
7591 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7592 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7593
4a87d65d
JB		 7594 /* Shares lanes with HDMI on SDVOC */
7595 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 7596 intel_dp_init(dev, DP_C, PORT_C);
103a196f 7597 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7598 bool found = false;
7d57382e 7599
725e30ad 7600 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7601 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7602 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7603 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7604 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7605 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7606 }
27185ae1 7607
b01f2c3a
JB		 7608 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7609 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7610 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7611 }
725e30ad 7612 }
13520b05
KH		 7613
7614 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7615
b01f2c3a
JB		 7616 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7617 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7618 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7619 }
27185ae1
ML		 7620
7621 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7622
b01f2c3a
JB		 7623 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7624 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7625 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7626 }
7627 if (SUPPORTS_INTEGRATED_DP(dev)) {
7628 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7629 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7630 }
725e30ad 7631 }
27185ae1 7632
b01f2c3a
JB		 7633 if (SUPPORTS_INTEGRATED_DP(dev) &&
7634 (I915_READ(DP_D) & DP_DETECTED)) {
7635 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7636 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7637 }
bad720ff 7638 } else if (IS_GEN2(dev))
79e53945
JB		 7639 intel_dvo_init(dev);
7640
103a196f 7641 if (SUPPORTS_TV(dev))
79e53945
JB		 7642 intel_tv_init(dev);
7643
4ef69c7a
CW		 7644 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7645 encoder->base.possible_crtcs = encoder->crtc_mask;
7646 encoder->base.possible_clones =
66a9278e 7647 intel_encoder_clones(encoder);
79e53945 7648 }
47356eb6 7649
40579abe 7650 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7651 ironlake_init_pch_refclk(dev);
79e53945
JB		 7652}
7653
7654static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7655{
7656 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7657
7658 drm_framebuffer_cleanup(fb);
05394f39 7659 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7660
7661 kfree(intel_fb);
7662}
7663
7664static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7665 struct drm_file *file,
79e53945
JB		 7666 unsigned int *handle)
7667{
7668 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7669 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7670
05394f39 7671 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7672}
7673
7674static const struct drm_framebuffer_funcs intel_fb_funcs = {
7675 .destroy = intel_user_framebuffer_destroy,
7676 .create_handle = intel_user_framebuffer_create_handle,
7677};
7678
38651674
DA		 7679int intel_framebuffer_init(struct drm_device *dev,
7680 struct intel_framebuffer *intel_fb,
308e5bcb 7681 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7682 struct drm_i915_gem_object *obj)
79e53945 7683{
79e53945
JB		 7684 int ret;
7685
05394f39 7686 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7687 return -EINVAL;
7688
308e5bcb 7689 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7690 return -EINVAL;
7691
308e5bcb 7692 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7693 case DRM_FORMAT_RGB332:
7694 case DRM_FORMAT_RGB565:
7695 case DRM_FORMAT_XRGB8888:
b250da79 7696 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7697 case DRM_FORMAT_ARGB8888:
7698 case DRM_FORMAT_XRGB2101010:
7699 case DRM_FORMAT_ARGB2101010:
308e5bcb 7700 /* RGB formats are common across chipsets */
b5626747 7701 break;
04b3924d
VS		 7702 case DRM_FORMAT_YUYV:
7703 case DRM_FORMAT_UYVY:
7704 case DRM_FORMAT_YVYU:
7705 case DRM_FORMAT_VYUY:
57cd6508
CW		 7706 break;
7707 default:
aca25848
ED		 7708 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7709 mode_cmd->pixel_format);
57cd6508
CW		 7710 return -EINVAL;
7711 }
7712
79e53945
JB		 7713 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7714 if (ret) {
7715 DRM_ERROR("framebuffer init failed %d\n", ret);
7716 return ret;
7717 }
7718
7719 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7720 intel_fb->obj = obj;
79e53945
JB		 7721 return 0;
7722}
7723
79e53945
JB		 7724static struct drm_framebuffer *
7725intel_user_framebuffer_create(struct drm_device *dev,
7726 struct drm_file *filp,
308e5bcb 7727 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7728{
05394f39 7729 struct drm_i915_gem_object *obj;
79e53945 7730
308e5bcb
JB		 7731 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7732 mode_cmd->handles[0]));
c8725226 7733 if (&obj->base == NULL)
cce13ff7 7734 return ERR_PTR(-ENOENT);
79e53945 7735
d2dff872 7736 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7737}
7738
79e53945 7739static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7740 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7741 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7742};
7743
e70236a8
JB		 7744/* Set up chip specific display functions */
7745static void intel_init_display(struct drm_device *dev)
7746{
7747 struct drm_i915_private *dev_priv = dev->dev_private;
7748
7749 /* We always want a DPMS function */
f564048e 7750 if (HAS_PCH_SPLIT(dev)) {
f564048e 7751 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7752 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7753 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7754 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7755 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7756 } else {
f564048e 7757 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7758 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7759 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7760 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7761 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7762 }
e70236a8 7763
e70236a8 7764 /* Returns the core display clock speed */
25eb05fc
JB		 7765 if (IS_VALLEYVIEW(dev))
7766 dev_priv->display.get_display_clock_speed =
7767 valleyview_get_display_clock_speed;
7768 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7769 dev_priv->display.get_display_clock_speed =
7770 i945_get_display_clock_speed;
7771 else if (IS_I915G(dev))
7772 dev_priv->display.get_display_clock_speed =
7773 i915_get_display_clock_speed;
f2b115e6 7774 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7775 dev_priv->display.get_display_clock_speed =
7776 i9xx_misc_get_display_clock_speed;
7777 else if (IS_I915GM(dev))
7778 dev_priv->display.get_display_clock_speed =
7779 i915gm_get_display_clock_speed;
7780 else if (IS_I865G(dev))
7781 dev_priv->display.get_display_clock_speed =
7782 i865_get_display_clock_speed;
f0f8a9ce 7783 else if (IS_I85X(dev))
e70236a8
JB		 7784 dev_priv->display.get_display_clock_speed =
7785 i855_get_display_clock_speed;
7786 else /* 852, 830 */
7787 dev_priv->display.get_display_clock_speed =
7788 i830_get_display_clock_speed;
7789
7f8a8569 7790 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7791 if (IS_GEN5(dev)) {
674cf967 7792 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7793 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7794 } else if (IS_GEN6(dev)) {
674cf967 7795 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7796 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7797 } else if (IS_IVYBRIDGE(dev)) {
7798 /* FIXME: detect B0+ stepping and use auto training */
7799 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7800 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7801 } else if (IS_HASWELL(dev)) {
7802 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7803 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7804 } else
7805 dev_priv->display.update_wm = NULL;
6067aaea 7806 } else if (IS_G4X(dev)) {
e0dac65e 7807 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7808 }
8c9f3aaf
JB		 7809
7810 /* Default just returns -ENODEV to indicate unsupported */
7811 dev_priv->display.queue_flip = intel_default_queue_flip;
7812
7813 switch (INTEL_INFO(dev)->gen) {
7814 case 2:
7815 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7816 break;
7817
7818 case 3:
7819 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7820 break;
7821
7822 case 4:
7823 case 5:
7824 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7825 break;
7826
7827 case 6:
7828 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7829 break;
7c9017e5
JB		 7830 case 7:
7831 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7832 break;
8c9f3aaf 7833 }
e70236a8
JB		 7834}
7835
b690e96c
JB		 7836/*
7837 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7838 * resume, or other times. This quirk makes sure that's the case for
7839 * affected systems.
7840 */
0206e353 7841static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7842{
7843 struct drm_i915_private *dev_priv = dev->dev_private;
7844
7845 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7846 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7847}
7848
435793df
KP		 7849/*
7850 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7851 */
7852static void quirk_ssc_force_disable(struct drm_device *dev)
7853{
7854 struct drm_i915_private *dev_priv = dev->dev_private;
7855 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7856 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7857}
7858
4dca20ef 7859/*
5a15ab5b
CE		 7860 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7861 * brightness value
4dca20ef
CE		 7862 */
7863static void quirk_invert_brightness(struct drm_device *dev)
7864{
7865 struct drm_i915_private *dev_priv = dev->dev_private;
7866 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7867 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7868}
7869
b690e96c
JB		 7870struct intel_quirk {
7871 int device;
7872 int subsystem_vendor;
7873 int subsystem_device;
7874 void (*hook)(struct drm_device *dev);
7875};
7876
c43b5634 7877static struct intel_quirk intel_quirks[] = {
b690e96c 7878 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7879 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7880
b690e96c
JB		 7881 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7882 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7883
b690e96c
JB		 7884 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7885 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7886
7887 /* 855 & before need to leave pipe A & dpll A up */
7888 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7889 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7890 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7891
7892 /* Lenovo U160 cannot use SSC on LVDS */
7893 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7894
7895 /* Sony Vaio Y cannot use SSC on LVDS */
7896 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7897
7898 /* Acer Aspire 5734Z must invert backlight brightness */
7899 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7900};
7901
7902static void intel_init_quirks(struct drm_device *dev)
7903{
7904 struct pci_dev *d = dev->pdev;
7905 int i;
7906
7907 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7908 struct intel_quirk *q = &intel_quirks[i];
7909
7910 if (d->device == q->device &&
7911 (d->subsystem_vendor == q->subsystem_vendor ||
7912 q->subsystem_vendor == PCI_ANY_ID) &&
7913 (d->subsystem_device == q->subsystem_device ||
7914 q->subsystem_device == PCI_ANY_ID))
7915 q->hook(dev);
7916 }
7917}
7918
9cce37f4
JB		 7919/* Disable the VGA plane that we never use */
7920static void i915_disable_vga(struct drm_device *dev)
7921{
7922 struct drm_i915_private *dev_priv = dev->dev_private;
7923 u8 sr1;
7924 u32 vga_reg;
7925
7926 if (HAS_PCH_SPLIT(dev))
7927 vga_reg = CPU_VGACNTRL;
7928 else
7929 vga_reg = VGACNTRL;
7930
7931 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7932 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7933 sr1 = inb(VGA_SR_DATA);
7934 outb(sr1 | 1<<5, VGA_SR_DATA);
7935 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7936 udelay(300);
7937
7938 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7939 POSTING_READ(vga_reg);
7940}
7941
f817586c
DV		 7942void intel_modeset_init_hw(struct drm_device *dev)
7943{
0232e927
ED		 7944 /* We attempt to init the necessary power wells early in the initialization
7945 * time, so the subsystems that expect power to be enabled can work.
7946 */
7947 intel_init_power_wells(dev);
7948
a8f78b58
ED		 7949 intel_prepare_ddi(dev);
7950
f817586c
DV		 7951 intel_init_clock_gating(dev);
7952
79f5b2c7 7953 mutex_lock(&dev->struct_mutex);
8090c6b9 7954 intel_enable_gt_powersave(dev);
79f5b2c7 7955 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7956}
7957
79e53945
JB		 7958void intel_modeset_init(struct drm_device *dev)
7959{
652c393a 7960 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7961 int i, ret;
79e53945
JB		 7962
7963 drm_mode_config_init(dev);
7964
7965 dev->mode_config.min_width = 0;
7966 dev->mode_config.min_height = 0;
7967
019d96cb
DA		 7968 dev->mode_config.preferred_depth = 24;
7969 dev->mode_config.prefer_shadow = 1;
7970
e6ecefaa 7971 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7972
b690e96c
JB		 7973 intel_init_quirks(dev);
7974
1fa61106
ED		 7975 intel_init_pm(dev);
7976
e70236a8
JB		 7977 intel_init_display(dev);
7978
a6c45cf0
CW		 7979 if (IS_GEN2(dev)) {
7980 dev->mode_config.max_width = 2048;
7981 dev->mode_config.max_height = 2048;
7982 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7983 dev->mode_config.max_width = 4096;
7984 dev->mode_config.max_height = 4096;
79e53945 7985 } else {
a6c45cf0
CW		 7986 dev->mode_config.max_width = 8192;
7987 dev->mode_config.max_height = 8192;
79e53945 7988 }
dd2757f8 7989 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7990
28c97730 7991 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7992 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7993
a3524f1b 7994 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7995 intel_crtc_init(dev, i);
00c2064b
JB		 7996 ret = intel_plane_init(dev, i);
7997 if (ret)
7998 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7999 }
8000
ee7b9f93
JB		 8001 intel_pch_pll_init(dev);
8002
9cce37f4
JB		 8003 /* Just disable it once at startup */
8004 i915_disable_vga(dev);
79e53945 8005 intel_setup_outputs(dev);
2c7111db
CW		 8006}
8007
24929352
DV		 8008static void
8009intel_connector_break_all_links(struct intel_connector *connector)
8010{
8011 connector->base.dpms = DRM_MODE_DPMS_OFF;
8012 connector->base.encoder = NULL;
8013 connector->encoder->connectors_active = false;
8014 connector->encoder->base.crtc = NULL;
8015}
8016
7fad798e
DV		 8017static void intel_enable_pipe_a(struct drm_device *dev)
8018{
8019 struct intel_connector *connector;
8020 struct drm_connector *crt = NULL;
8021 struct intel_load_detect_pipe load_detect_temp;
8022
8023 /* We can't just switch on the pipe A, we need to set things up with a
8024 * proper mode and output configuration. As a gross hack, enable pipe A
8025 * by enabling the load detect pipe once. */
8026 list_for_each_entry(connector,
8027 &dev->mode_config.connector_list,
8028 base.head) {
8029 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8030 crt = &connector->base;
8031 break;
8032 }
8033 }
8034
8035 if (!crt)
8036 return;
8037
8038 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8039 intel_release_load_detect_pipe(crt, &load_detect_temp);
8040
8041
8042}
8043
24929352
DV		 8044static void intel_sanitize_crtc(struct intel_crtc *crtc)
8045{
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 u32 reg, val;
8049
24929352
DV		 8050 /* Clear any frame start delays used for debugging left by the BIOS */
8051 reg = PIPECONF(crtc->pipe);
8052 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8053
8054 /* We need to sanitize the plane -> pipe mapping first because this will
8055 * disable the crtc (and hence change the state) if it is wrong. */
8056 if (!HAS_PCH_SPLIT(dev)) {
8057 struct intel_connector *connector;
8058 bool plane;
8059
8060 reg = DSPCNTR(crtc->plane);
8061 val = I915_READ(reg);
8062
8063 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8064 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8065 goto ok;
8066
8067 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8068 crtc->base.base.id);
8069
8070 /* Pipe has the wrong plane attached and the plane is active.
8071 * Temporarily change the plane mapping and disable everything
8072 * ... */
8073 plane = crtc->plane;
8074 crtc->plane = !plane;
8075 dev_priv->display.crtc_disable(&crtc->base);
8076 crtc->plane = plane;
8077
8078 /* ... and break all links. */
8079 list_for_each_entry(connector, &dev->mode_config.connector_list,
8080 base.head) {
8081 if (connector->encoder->base.crtc != &crtc->base)
8082 continue;
8083
8084 intel_connector_break_all_links(connector);
8085 }
8086
8087 WARN_ON(crtc->active);
8088 crtc->base.enabled = false;
8089 }
8090ok:
8091
7fad798e
DV		 8092 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8093 crtc->pipe == PIPE_A && !crtc->active) {
8094 /* BIOS forgot to enable pipe A, this mostly happens after
8095 * resume. Force-enable the pipe to fix this, the update_dpms
8096 * call below we restore the pipe to the right state, but leave
8097 * the required bits on. */
8098 intel_enable_pipe_a(dev);
8099 }
8100
24929352
DV		 8101 /* Adjust the state of the output pipe according to whether we
8102 * have active connectors/encoders. */
8103 intel_crtc_update_dpms(&crtc->base);
8104
8105 if (crtc->active != crtc->base.enabled) {
8106 struct intel_encoder *encoder;
8107
8108 /* This can happen either due to bugs in the get_hw_state
8109 * functions or because the pipe is force-enabled due to the
8110 * pipe A quirk. */
8111 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8112 crtc->base.base.id,
8113 crtc->base.enabled ? "enabled" : "disabled",
8114 crtc->active ? "enabled" : "disabled");
8115
8116 crtc->base.enabled = crtc->active;
8117
8118 /* Because we only establish the connector -> encoder ->
8119 * crtc links if something is active, this means the
8120 * crtc is now deactivated. Break the links. connector
8121 * -> encoder links are only establish when things are
8122 * actually up, hence no need to break them. */
8123 WARN_ON(crtc->active);
8124
8125 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8126 WARN_ON(encoder->connectors_active);
8127 encoder->base.crtc = NULL;
8128 }
8129 }
8130}
8131
8132static void intel_sanitize_encoder(struct intel_encoder *encoder)
8133{
8134 struct intel_connector *connector;
8135 struct drm_device *dev = encoder->base.dev;
8136
8137 /* We need to check both for a crtc link (meaning that the
8138 * encoder is active and trying to read from a pipe) and the
8139 * pipe itself being active. */
8140 bool has_active_crtc = encoder->base.crtc &&
8141 to_intel_crtc(encoder->base.crtc)->active;
8142
8143 if (encoder->connectors_active && !has_active_crtc) {
8144 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8145 encoder->base.base.id,
8146 drm_get_encoder_name(&encoder->base));
8147
8148 /* Connector is active, but has no active pipe. This is
8149 * fallout from our resume register restoring. Disable
8150 * the encoder manually again. */
8151 if (encoder->base.crtc) {
8152 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8153 encoder->base.base.id,
8154 drm_get_encoder_name(&encoder->base));
8155 encoder->disable(encoder);
8156 }
8157
8158 /* Inconsistent output/port/pipe state happens presumably due to
8159 * a bug in one of the get_hw_state functions. Or someplace else
8160 * in our code, like the register restore mess on resume. Clamp
8161 * things to off as a safer default. */
8162 list_for_each_entry(connector,
8163 &dev->mode_config.connector_list,
8164 base.head) {
8165 if (connector->encoder != encoder)
8166 continue;
8167
8168 intel_connector_break_all_links(connector);
8169 }
8170 }
8171 /* Enabled encoders without active connectors will be fixed in
8172 * the crtc fixup. */
8173}
8174
8175/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8176 * and i915 state tracking structures. */
8177void intel_modeset_setup_hw_state(struct drm_device *dev)
8178{
8179 struct drm_i915_private *dev_priv = dev->dev_private;
8180 enum pipe pipe;
8181 u32 tmp;
8182 struct intel_crtc *crtc;
8183 struct intel_encoder *encoder;
8184 struct intel_connector *connector;
8185
8186 for_each_pipe(pipe) {
8187 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8188
8189 tmp = I915_READ(PIPECONF(pipe));
8190 if (tmp & PIPECONF_ENABLE)
8191 crtc->active = true;
8192 else
8193 crtc->active = false;
8194
8195 crtc->base.enabled = crtc->active;
8196
8197 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8198 crtc->base.base.id,
8199 crtc->active ? "enabled" : "disabled");
8200 }
8201
8202 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8203 base.head) {
8204 pipe = 0;
8205
8206 if (encoder->get_hw_state(encoder, &pipe)) {
8207 encoder->base.crtc =
8208 dev_priv->pipe_to_crtc_mapping[pipe];
8209 } else {
8210 encoder->base.crtc = NULL;
8211 }
8212
8213 encoder->connectors_active = false;
8214 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8215 encoder->base.base.id,
8216 drm_get_encoder_name(&encoder->base),
8217 encoder->base.crtc ? "enabled" : "disabled",
8218 pipe);
8219 }
8220
8221 list_for_each_entry(connector, &dev->mode_config.connector_list,
8222 base.head) {
8223 if (connector->get_hw_state(connector)) {
8224 connector->base.dpms = DRM_MODE_DPMS_ON;
8225 connector->encoder->connectors_active = true;
8226 connector->base.encoder = &connector->encoder->base;
8227 } else {
8228 connector->base.dpms = DRM_MODE_DPMS_OFF;
8229 connector->base.encoder = NULL;
8230 }
8231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8232 connector->base.base.id,
8233 drm_get_connector_name(&connector->base),
8234 connector->base.encoder ? "enabled" : "disabled");
8235 }
8236
8237 /* HW state is read out, now we need to sanitize this mess. */
8238 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8239 base.head) {
8240 intel_sanitize_encoder(encoder);
8241 }
8242
8243 for_each_pipe(pipe) {
8244 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8245 intel_sanitize_crtc(crtc);
8246 }
9a935856
DV		 8247
8248 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8249
8250 intel_modeset_check_state(dev);
24929352
DV		 8251}
8252
2c7111db
CW		 8253void intel_modeset_gem_init(struct drm_device *dev)
8254{
1833b134 8255 intel_modeset_init_hw(dev);
02e792fb
DV		 8256
8257 intel_setup_overlay(dev);
24929352
DV		 8258
8259 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8260}
8261
8262void intel_modeset_cleanup(struct drm_device *dev)
8263{
652c393a
JB		 8264 struct drm_i915_private *dev_priv = dev->dev_private;
8265 struct drm_crtc *crtc;
8266 struct intel_crtc *intel_crtc;
8267
f87ea761 8268 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8269 mutex_lock(&dev->struct_mutex);
8270
723bfd70
JB		 8271 intel_unregister_dsm_handler();
8272
8273
652c393a
JB		 8274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8275 /* Skip inactive CRTCs */
8276 if (!crtc->fb)
8277 continue;
8278
8279 intel_crtc = to_intel_crtc(crtc);
3dec0095 8280 intel_increase_pllclock(crtc);
652c393a
JB		 8281 }
8282
973d04f9 8283 intel_disable_fbc(dev);
e70236a8 8284
8090c6b9 8285 intel_disable_gt_powersave(dev);
0cdab21f 8286
930ebb46
DV		 8287 ironlake_teardown_rc6(dev);
8288
57f350b6
JB		 8289 if (IS_VALLEYVIEW(dev))
8290 vlv_init_dpio(dev);
8291
69341a5e
KH		 8292 mutex_unlock(&dev->struct_mutex);
8293
6c0d9350
DV		 8294 /* Disable the irq before mode object teardown, for the irq might
8295 * enqueue unpin/hotplug work. */
8296 drm_irq_uninstall(dev);
8297 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8298 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8299
1630fe75
CW		 8300 /* flush any delayed tasks or pending work */
8301 flush_scheduled_work();
8302
79e53945
JB		 8303 drm_mode_config_cleanup(dev);
8304}
8305
f1c79df3
ZW		 8306/*
8307 * Return which encoder is currently attached for connector.
8308 */
df0e9248 8309struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8310{
df0e9248
CW		 8311 return &intel_attached_encoder(connector)->base;
8312}
f1c79df3 8313
df0e9248
CW		 8314void intel_connector_attach_encoder(struct intel_connector *connector,
8315 struct intel_encoder *encoder)
8316{
8317 connector->encoder = encoder;
8318 drm_mode_connector_attach_encoder(&connector->base,
8319 &encoder->base);
79e53945 8320}
28d52043
DA		 8321
8322/*
8323 * set vga decode state - true == enable VGA decode
8324 */
8325int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8326{
8327 struct drm_i915_private *dev_priv = dev->dev_private;
8328 u16 gmch_ctrl;
8329
8330 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8331 if (state)
8332 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8333 else
8334 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8335 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8336 return 0;
8337}
c4a1d9e4
CW		 8338
8339#ifdef CONFIG_DEBUG_FS
8340#include <linux/seq_file.h>
8341
8342struct intel_display_error_state {
8343 struct intel_cursor_error_state {
8344 u32 control;
8345 u32 position;
8346 u32 base;
8347 u32 size;
52331309 8348 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8349
8350 struct intel_pipe_error_state {
8351 u32 conf;
8352 u32 source;
8353
8354 u32 htotal;
8355 u32 hblank;
8356 u32 hsync;
8357 u32 vtotal;
8358 u32 vblank;
8359 u32 vsync;
52331309 8360 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8361
8362 struct intel_plane_error_state {
8363 u32 control;
8364 u32 stride;
8365 u32 size;
8366 u32 pos;
8367 u32 addr;
8368 u32 surface;
8369 u32 tile_offset;
52331309 8370 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8371};
8372
8373struct intel_display_error_state *
8374intel_display_capture_error_state(struct drm_device *dev)
8375{
0206e353 8376 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8377 struct intel_display_error_state *error;
8378 int i;
8379
8380 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8381 if (error == NULL)
8382 return NULL;
8383
52331309 8384 for_each_pipe(i) {
c4a1d9e4
CW		 8385 error->cursor[i].control = I915_READ(CURCNTR(i));
8386 error->cursor[i].position = I915_READ(CURPOS(i));
8387 error->cursor[i].base = I915_READ(CURBASE(i));
8388
8389 error->plane[i].control = I915_READ(DSPCNTR(i));
8390 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8391 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8392 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8393 error->plane[i].addr = I915_READ(DSPADDR(i));
8394 if (INTEL_INFO(dev)->gen >= 4) {
8395 error->plane[i].surface = I915_READ(DSPSURF(i));
8396 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8397 }
8398
8399 error->pipe[i].conf = I915_READ(PIPECONF(i));
8400 error->pipe[i].source = I915_READ(PIPESRC(i));
8401 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8402 error->pipe[i].hblank = I915_READ(HBLANK(i));
8403 error->pipe[i].hsync = I915_READ(HSYNC(i));
8404 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8405 error->pipe[i].vblank = I915_READ(VBLANK(i));
8406 error->pipe[i].vsync = I915_READ(VSYNC(i));
8407 }
8408
8409 return error;
8410}
8411
8412void
8413intel_display_print_error_state(struct seq_file *m,
8414 struct drm_device *dev,
8415 struct intel_display_error_state *error)
8416{
52331309 8417 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8418 int i;
8419
52331309
DL		 8420 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8421 for_each_pipe(i) {
c4a1d9e4
CW		 8422 seq_printf(m, "Pipe [%d]:\n", i);
8423 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8424 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8425 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8426 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8427 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8428 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8429 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8430 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8431
8432 seq_printf(m, "Plane [%d]:\n", i);
8433 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8434 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8435 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8436 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8437 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8438 if (INTEL_INFO(dev)->gen >= 4) {
8439 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8440 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8441 }
8442
8443 seq_printf(m, "Cursor [%d]:\n", i);
8444 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8445 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8446 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8447 }
8448}
8449#endif
ubuntu-bionic-kernel mirror