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intel/iommu: force writebuffer-flush quirk on Gen 4 Chipsets
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 157 .m1 = { .min = 8, .max = 18 },
158 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 171 .m1 = { .min = 8, .max = 18 },
172 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
69310161
PZ		 1217 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219 cur_state = false;
1220 } else {
1221 reg = PIPECONF(cpu_transcoder);
1222 val = I915_READ(reg);
1223 cur_state = !!(val & PIPECONF_ENABLE);
1224 }
1225
63d7bbe9
JB		 1226 WARN(cur_state != state,
1227 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1228 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1229}
1230
931872fc
CW		 1231static void assert_plane(struct drm_i915_private *dev_priv,
1232 enum plane plane, bool state)
b24e7179
JB		 1233{
1234 int reg;
1235 u32 val;
931872fc 1236 bool cur_state;
b24e7179
JB		 1237
1238 reg = DSPCNTR(plane);
1239 val = I915_READ(reg);
931872fc
CW		 1240 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241 WARN(cur_state != state,
1242 "plane %c assertion failure (expected %s, current %s)\n",
1243 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1244}
1245
931872fc
CW		 1246#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
b24e7179
JB		 1249static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
1251{
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
19ec1358 1256 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1257 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN((val & DISPLAY_PLANE_ENABLE),
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
19ec1358 1263 return;
28c05794 1264 }
19ec1358 1265
b24e7179
JB		 1266 /* Need to check both planes against the pipe */
1267 for (i = 0; i < 2; i++) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1275 }
1276}
1277
92f2584a
JB		 1278static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279{
1280 u32 val;
1281 bool enabled;
1282
9d82aa17
ED		 1283 if (HAS_PCH_LPT(dev_priv->dev)) {
1284 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 return;
1286 }
1287
92f2584a
JB		 1288 val = I915_READ(PCH_DREF_CONTROL);
1289 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290 DREF_SUPERSPREAD_SOURCE_MASK));
1291 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292}
1293
1294static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296{
1297 int reg;
1298 u32 val;
1299 bool enabled;
1300
1301 reg = TRANSCONF(pipe);
1302 val = I915_READ(reg);
1303 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1304 WARN(enabled,
1305 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 pipe_name(pipe));
92f2584a
JB		 1307}
1308
4e634389
KP		 1309static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1311{
1312 if ((val & DP_PORT_EN) == 0)
1313 return false;
1314
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325}
1326
1519b995
KP		 1327static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329{
1330 if ((val & PORT_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv->dev)) {
1334 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335 return false;
1336 } else {
1337 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338 return false;
1339 }
1340 return true;
1341}
1342
1343static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1345{
1346 if ((val & LVDS_PORT_EN) == 0)
1347 return false;
1348
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351 return false;
1352 } else {
1353 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354 return false;
1355 }
1356 return true;
1357}
1358
1359static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
1362 if ((val & ADPA_DAC_ENABLE) == 0)
1363 return false;
1364 if (HAS_PCH_CPT(dev_priv->dev)) {
1365 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366 return false;
1367 } else {
1368 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369 return false;
1370 }
1371 return true;
1372}
1373
291906f1 1374static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1375 enum pipe pipe, int reg, u32 port_sel)
291906f1 1376{
47a05eca 1377 u32 val = I915_READ(reg);
4e634389 1378 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1379 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1380 reg, pipe_name(pipe));
de9a35ab 1381
75c5da27
DV		 1382 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383 && (val & DP_PIPEB_SELECT),
de9a35ab 1384 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1385}
1386
1387static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg)
1389{
47a05eca 1390 u32 val = I915_READ(reg);
b70ad586 1391 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1392 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1397 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402{
1403 int reg;
1404 u32 val;
291906f1 1405
f0575e92
KP		 1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1409
1410 reg = PCH_ADPA;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 reg = PCH_LVDS;
1417 val = I915_READ(reg);
b70ad586 1418 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1420 pipe_name(pipe));
291906f1
JB		 1421
1422 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425}
1426
63d7bbe9
JB		 1427/**
1428 * intel_enable_pll - enable a PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1433 * make sure the PLL reg is writable first though, since the panel write
1434 * protect mechanism may be enabled.
1435 *
1436 * Note! This is for pre-ILK only.
7434a255
TR		 1437 *
1438 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1439 */
1440static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441{
1442 int reg;
1443 u32 val;
1444
1445 /* No really, not for ILK+ */
a0c4da24 1446 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1447
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 reg = DPLL(pipe);
1453 val = I915_READ(reg);
1454 val |= DPLL_VCO_ENABLE;
1455
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1464 POSTING_READ(reg);
1465 udelay(150); /* wait for warmup */
1466}
1467
1468/**
1469 * intel_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1472 *
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1474 *
1475 * Note! This is for pre-ILK only.
1476 */
1477static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478{
1479 int reg;
1480 u32 val;
1481
1482 /* Don't disable pipe A or pipe A PLLs if needed */
1483 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484 return;
1485
1486 /* Make sure the pipe isn't still relying on us */
1487 assert_pipe_disabled(dev_priv, pipe);
1488
1489 reg = DPLL(pipe);
1490 val = I915_READ(reg);
1491 val &= ~DPLL_VCO_ENABLE;
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494}
1495
a416edef
ED		 1496/* SBI access */
1497static void
988d6ee8
PZ		 1498intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499 enum intel_sbi_destination destination)
a416edef 1500{
988d6ee8 1501 u32 tmp;
a416edef 1502
09153000 1503 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1504
39fb50f6 1505 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1506 100)) {
1507 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1508 return;
a416edef
ED		 1509 }
1510
988d6ee8
PZ		 1511 I915_WRITE(SBI_ADDR, (reg << 16));
1512 I915_WRITE(SBI_DATA, value);
1513
1514 if (destination == SBI_ICLK)
1515 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516 else
1517 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1519
39fb50f6 1520 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1521 100)) {
1522 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1523 return;
a416edef 1524 }
a416edef
ED		 1525}
1526
1527static u32
988d6ee8
PZ		 1528intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529 enum intel_sbi_destination destination)
a416edef 1530{
39fb50f6 1531 u32 value = 0;
09153000 1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1533
39fb50f6 1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1535 100)) {
1536 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1537 return 0;
a416edef
ED		 1538 }
1539
988d6ee8
PZ		 1540 I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542 if (destination == SBI_ICLK)
1543 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544 else
1545 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1547
39fb50f6 1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1549 100)) {
1550 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1551 return 0;
a416edef
ED		 1552 }
1553
09153000 1554 return I915_READ(SBI_DATA);
a416edef
ED		 1555}
1556
92f2584a 1557/**
b6b4e185 1558 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1559 * @dev_priv: i915 private structure
1560 * @pipe: pipe PLL to enable
1561 *
1562 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563 * drives the transcoder clock.
1564 */
b6b4e185 1565static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1566{
ee7b9f93 1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1568 struct intel_pch_pll *pll;
92f2584a
JB		 1569 int reg;
1570 u32 val;
1571
48da64a8 1572 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1573 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1574 pll = intel_crtc->pch_pll;
1575 if (pll == NULL)
1576 return;
1577
1578 if (WARN_ON(pll->refcount == 0))
1579 return;
ee7b9f93
JB		 1580
1581 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582 pll->pll_reg, pll->active, pll->on,
1583 intel_crtc->base.base.id);
92f2584a
JB		 1584
1585 /* PCH refclock must be enabled first */
1586 assert_pch_refclk_enabled(dev_priv);
1587
ee7b9f93 1588 if (pll->active++ && pll->on) {
92b27b08 1589 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1590 return;
1591 }
1592
1593 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595 reg = pll->pll_reg;
92f2584a
JB		 1596 val = I915_READ(reg);
1597 val |= DPLL_VCO_ENABLE;
1598 I915_WRITE(reg, val);
1599 POSTING_READ(reg);
1600 udelay(200);
ee7b9f93
JB		 1601
1602 pll->on = true;
92f2584a
JB		 1603}
1604
ee7b9f93 1605static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1606{
ee7b9f93
JB		 1607 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1609 int reg;
ee7b9f93 1610 u32 val;
4c609cb8 1611
92f2584a
JB		 1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1614 if (pll == NULL)
1615 return;
92f2584a 1616
48da64a8
CW		 1617 if (WARN_ON(pll->refcount == 0))
1618 return;
7a419866 1619
ee7b9f93
JB		 1620 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621 pll->pll_reg, pll->active, pll->on,
1622 intel_crtc->base.base.id);
7a419866 1623
48da64a8 1624 if (WARN_ON(pll->active == 0)) {
92b27b08 1625 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1626 return;
1627 }
1628
ee7b9f93 1629 if (--pll->active) {
92b27b08 1630 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1631 return;
ee7b9f93
JB		 1632 }
1633
1634 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636 /* Make sure transcoder isn't still depending on us */
1637 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1638
ee7b9f93 1639 reg = pll->pll_reg;
92f2584a
JB		 1640 val = I915_READ(reg);
1641 val &= ~DPLL_VCO_ENABLE;
1642 I915_WRITE(reg, val);
1643 POSTING_READ(reg);
1644 udelay(200);
ee7b9f93
JB		 1645
1646 pll->on = false;
92f2584a
JB		 1647}
1648
b8a4f404
PZ		 1649static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650 enum pipe pipe)
040484af 1651{
23670b32 1652 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1654 uint32_t reg, val, pipeconf_val;
040484af
JB		 1655
1656 /* PCH only available on ILK+ */
1657 BUG_ON(dev_priv->info->gen < 5);
1658
1659 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1660 assert_pch_pll_enabled(dev_priv,
1661 to_intel_crtc(crtc)->pch_pll,
1662 to_intel_crtc(crtc));
040484af
JB		 1663
1664 /* FDI must be feeding us bits for PCH ports */
1665 assert_fdi_tx_enabled(dev_priv, pipe);
1666 assert_fdi_rx_enabled(dev_priv, pipe);
1667
23670b32
DV		 1668 if (HAS_PCH_CPT(dev)) {
1669 /* Workaround: Set the timing override bit before enabling the
1670 * pch transcoder. */
1671 reg = TRANS_CHICKEN2(pipe);
1672 val = I915_READ(reg);
1673 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674 I915_WRITE(reg, val);
59c859d6 1675 }
23670b32 1676
040484af
JB		 1677 reg = TRANSCONF(pipe);
1678 val = I915_READ(reg);
5f7f726d 1679 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1680
1681 if (HAS_PCH_IBX(dev_priv->dev)) {
1682 /*
1683 * make the BPC in transcoder be consistent with
1684 * that in pipeconf reg.
1685 */
dfd07d72
DV		 1686 val &= ~PIPECONF_BPC_MASK;
1687 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1688 }
5f7f726d
PZ		 1689
1690 val &= ~TRANS_INTERLACE_MASK;
1691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1692 if (HAS_PCH_IBX(dev_priv->dev) &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694 val |= TRANS_LEGACY_INTERLACED_ILK;
1695 else
1696 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1697 else
1698 val |= TRANS_PROGRESSIVE;
1699
040484af
JB		 1700 I915_WRITE(reg, val | TRANS_ENABLE);
1701 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703}
1704
8fb033d7 1705static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1706 enum transcoder cpu_transcoder)
040484af 1707{
8fb033d7 1708 u32 val, pipeconf_val;
8fb033d7
PZ		 1709
1710 /* PCH only available on ILK+ */
1711 BUG_ON(dev_priv->info->gen < 5);
1712
8fb033d7 1713 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1714 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1715 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1716
223a6fdf
PZ		 1717 /* Workaround: set timing override bit. */
1718 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1719 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1720 I915_WRITE(_TRANSA_CHICKEN2, val);
1721
25f3ef11 1722 val = TRANS_ENABLE;
937bb610 1723 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1724
9a76b1c6
PZ		 1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726 PIPECONF_INTERLACED_ILK)
a35f2679 1727 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1728 else
1729 val |= TRANS_PROGRESSIVE;
1730
25f3ef11 1731 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1732 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1734}
1735
b8a4f404
PZ		 1736static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737 enum pipe pipe)
040484af 1738{
23670b32
DV		 1739 struct drm_device *dev = dev_priv->dev;
1740 uint32_t reg, val;
040484af
JB		 1741
1742 /* FDI relies on the transcoder */
1743 assert_fdi_tx_disabled(dev_priv, pipe);
1744 assert_fdi_rx_disabled(dev_priv, pipe);
1745
291906f1
JB		 1746 /* Ports must be off as well */
1747 assert_pch_ports_disabled(dev_priv, pipe);
1748
040484af
JB		 1749 reg = TRANSCONF(pipe);
1750 val = I915_READ(reg);
1751 val &= ~TRANS_ENABLE;
1752 I915_WRITE(reg, val);
1753 /* wait for PCH transcoder off, transcoder state */
1754 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1755 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1756
1757 if (!HAS_PCH_IBX(dev)) {
1758 /* Workaround: Clear the timing override chicken bit again. */
1759 reg = TRANS_CHICKEN2(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762 I915_WRITE(reg, val);
1763 }
040484af
JB		 1764}
1765
ab4d966c 1766static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1767{
8fb033d7
PZ		 1768 u32 val;
1769
8a52fd9f 1770 val = I915_READ(_TRANSACONF);
8fb033d7 1771 val &= ~TRANS_ENABLE;
8a52fd9f 1772 I915_WRITE(_TRANSACONF, val);
8fb033d7 1773 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1774 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1776
1777 /* Workaround: clear timing override bit. */
1778 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1779 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1780 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1781}
1782
b24e7179 1783/**
309cfea8 1784 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to enable
040484af 1787 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1788 *
1789 * Enable @pipe, making sure that various hardware specific requirements
1790 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791 *
1792 * @pipe should be %PIPE_A or %PIPE_B.
1793 *
1794 * Will wait until the pipe is actually running (i.e. first vblank) before
1795 * returning.
1796 */
040484af
JB		 1797static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798 bool pch_port)
b24e7179 1799{
702e7a56
PZ		 1800 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801 pipe);
1a240d4d 1802 enum pipe pch_transcoder;
b24e7179
JB		 1803 int reg;
1804 u32 val;
1805
681e5811 1806 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1807 pch_transcoder = TRANSCODER_A;
1808 else
1809 pch_transcoder = pipe;
1810
b24e7179
JB		 1811 /*
1812 * A pipe without a PLL won't actually be able to drive bits from
1813 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1814 * need the check.
1815 */
1816 if (!HAS_PCH_SPLIT(dev_priv->dev))
1817 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1818 else {
1819 if (pch_port) {
1820 /* if driving the PCH, we need FDI enabled */
cc391bbb 1821 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1822 assert_fdi_tx_pll_enabled(dev_priv,
1823 (enum pipe) cpu_transcoder);
040484af
JB		 1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
b24e7179 1827
702e7a56 1828 reg = PIPECONF(cpu_transcoder);
b24e7179 1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
1837/**
309cfea8 1838 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851{
702e7a56
PZ		 1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
b24e7179
JB		 1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874}
1875
d74362c9
KP		 1876/*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
6f1d69b0 1880void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1881 enum plane plane)
1882{
14f86147
DL		 1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1887}
1888
b24e7179
JB		 1889/**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899{
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
00d70b15
CW		 1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1912 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914}
1915
b24e7179
JB		 1916/**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926{
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
00d70b15
CW		 1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938}
1939
127bd2ac 1940int
48b956c5 1941intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1942 struct drm_i915_gem_object *obj,
919926ae 1943 struct intel_ring_buffer *pipelined)
6b95a207 1944{
ce453d81 1945 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1946 u32 alignment;
1947 int ret;
1948
05394f39 1949 switch (obj->tiling_mode) {
6b95a207 1950 case I915_TILING_NONE:
534843da
CW		 1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
a6c45cf0 1953 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
6b95a207
KH		 1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
ce453d81 1970 dev_priv->mm.interruptible = false;
2da3b9b9 1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1972 if (ret)
ce453d81 1973 goto err_interruptible;
6b95a207
KH		 1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
06d98131 1980 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1981 if (ret)
1982 goto err_unpin;
1690e1eb 1983
9a5a53b3 1984 i915_gem_object_pin_fence(obj);
6b95a207 1985
ce453d81 1986 dev_priv->mm.interruptible = true;
6b95a207 1987 return 0;
48b956c5
CW		 1988
1989err_unpin:
1990 i915_gem_object_unpin(obj);
ce453d81
CW		 1991err_interruptible:
1992 dev_priv->mm.interruptible = true;
48b956c5 1993 return ret;
6b95a207
KH		 1994}
1995
1690e1eb
CW		 1996void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997{
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000}
2001
c2c75131
DV		 2002/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
5a35e99e
DL		 2004unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005 unsigned int bpp,
2006 unsigned int pitch)
c2c75131
DV		 2007{
2008 int tile_rows, tiles;
2009
2010 tile_rows = *y / 8;
2011 *y %= 8;
2012 tiles = *x / (512/bpp);
2013 *x %= 512/bpp;
2014
2015 return tile_rows * pitch * 8 + tiles * 4096;
2016}
2017
17638cd6
JB		 2018static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019 int x, int y)
81255565
JB		 2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
05394f39 2025 struct drm_i915_gem_object *obj;
81255565 2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
81255565 2028 u32 dspcntr;
5eddb70b 2029 u32 reg;
81255565
JB		 2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
2034 break;
2035 default:
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037 return -EINVAL;
2038 }
2039
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
81255565 2042
5eddb70b
CW		 2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
81255565
JB		 2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2047 switch (fb->pixel_format) {
2048 case DRM_FORMAT_C8:
81255565
JB		 2049 dspcntr |= DISPPLANE_8BPP;
2050 break;
57779d06
VS		 2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
81255565 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2057 break;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2073 break;
2074 default:
57779d06 2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2076 return -EINVAL;
2077 }
57779d06 2078
a6c45cf0 2079 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2080 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084 }
2085
5eddb70b 2086 I915_WRITE(reg, dspcntr);
81255565 2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2089
c2c75131
DV		 2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131
DV		 2095 linear_offset -= intel_crtc->dspaddr_offset;
2096 } else {
e506a0c6 2097 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2098 }
e506a0c6
DV		 2099
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2108 } else
e506a0c6 2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2110 POSTING_READ(reg);
81255565 2111
17638cd6
JB		 2112 return 0;
2113}
2114
2115static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117{
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
e506a0c6 2124 unsigned long linear_offset;
17638cd6
JB		 2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
27f8227b 2131 case 2:
17638cd6
JB		 2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
17638cd6
JB		 2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
57779d06
VS		 2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2151 break;
57779d06
VS		 2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2167 break;
2168 default:
57779d06 2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
e506a0c6 2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2184 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2187 fb->pitches[0]);
c2c75131 2188 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2189
e506a0c6
DV		 2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197 } else {
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200 }
17638cd6
JB		 2201 POSTING_READ(reg);
2202
2203 return 0;
2204}
2205
2206/* Assume fb object is pinned & idle & fenced and just update base pointers */
2207static int
2208intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2210{
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2213
6b8e6ed0
CW		 2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
3dec0095 2216 intel_increase_pllclock(crtc);
81255565 2217
6b8e6ed0 2218 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2219}
2220
14667a4b
CW		 2221static int
2222intel_finish_fb(struct drm_framebuffer *old_fb)
2223{
2224 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226 bool was_interruptible = dev_priv->mm.interruptible;
2227 int ret;
2228
14667a4b
CW		 2229 /* Big Hammer, we also need to ensure that any pending
2230 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2231 * current scanout is retired before unpinning the old
2232 * framebuffer.
2233 *
2234 * This should only fail upon a hung GPU, in which case we
2235 * can safely continue.
2236 */
2237 dev_priv->mm.interruptible = false;
2238 ret = i915_gem_object_finish_gpu(obj);
2239 dev_priv->mm.interruptible = was_interruptible;
2240
2241 return ret;
2242}
2243
198598d0
VS		 2244static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2245{
2246 struct drm_device *dev = crtc->dev;
2247 struct drm_i915_master_private *master_priv;
2248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
2250 if (!dev->primary->master)
2251 return;
2252
2253 master_priv = dev->primary->master->driver_priv;
2254 if (!master_priv->sarea_priv)
2255 return;
2256
2257 switch (intel_crtc->pipe) {
2258 case 0:
2259 master_priv->sarea_priv->pipeA_x = x;
2260 master_priv->sarea_priv->pipeA_y = y;
2261 break;
2262 case 1:
2263 master_priv->sarea_priv->pipeB_x = x;
2264 master_priv->sarea_priv->pipeB_y = y;
2265 break;
2266 default:
2267 break;
2268 }
2269}
2270
5c3b82e2 2271static int
3c4fdcfb 2272intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2273 struct drm_framebuffer *fb)
79e53945
JB		 2274{
2275 struct drm_device *dev = crtc->dev;
6b8e6ed0 2276 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2278 struct drm_framebuffer *old_fb;
5c3b82e2 2279 int ret;
79e53945
JB		 2280
2281 /* no fb bound */
94352cf9 2282 if (!fb) {
a5071c2f 2283 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2284 return 0;
2285 }
2286
5826eca5
ED		 2287 if(intel_crtc->plane > dev_priv->num_pipe) {
2288 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2289 intel_crtc->plane,
2290 dev_priv->num_pipe);
5c3b82e2 2291 return -EINVAL;
79e53945
JB		 2292 }
2293
5c3b82e2 2294 mutex_lock(&dev->struct_mutex);
265db958 2295 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2296 to_intel_framebuffer(fb)->obj,
919926ae 2297 NULL);
5c3b82e2
CW		 2298 if (ret != 0) {
2299 mutex_unlock(&dev->struct_mutex);
a5071c2f 2300 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2301 return ret;
2302 }
79e53945 2303
94352cf9
DV		 2304 if (crtc->fb)
2305 intel_finish_fb(crtc->fb);
265db958 2306
94352cf9 2307 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2308 if (ret) {
94352cf9 2309 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2310 mutex_unlock(&dev->struct_mutex);
a5071c2f 2311 DRM_ERROR("failed to update base address\n");
4e6cfefc 2312 return ret;
79e53945 2313 }
3c4fdcfb 2314
94352cf9
DV		 2315 old_fb = crtc->fb;
2316 crtc->fb = fb;
6c4c86f5
DV		 2317 crtc->x = x;
2318 crtc->y = y;
94352cf9 2319
b7f1de28
CW		 2320 if (old_fb) {
2321 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2322 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2323 }
652c393a 2324
6b8e6ed0 2325 intel_update_fbc(dev);
5c3b82e2 2326 mutex_unlock(&dev->struct_mutex);
79e53945 2327
198598d0 2328 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2329
2330 return 0;
79e53945
JB		 2331}
2332
5e84e1a4
ZW		 2333static void intel_fdi_normal_train(struct drm_crtc *crtc)
2334{
2335 struct drm_device *dev = crtc->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338 int pipe = intel_crtc->pipe;
2339 u32 reg, temp;
2340
2341 /* enable normal train */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
61e499bf 2344 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2345 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2347 } else {
2348 temp &= ~FDI_LINK_TRAIN_NONE;
2349 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2350 }
5e84e1a4
ZW		 2351 I915_WRITE(reg, temp);
2352
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 if (HAS_PCH_CPT(dev)) {
2356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2358 } else {
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_NONE;
2361 }
2362 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2363
2364 /* wait one idle pattern time */
2365 POSTING_READ(reg);
2366 udelay(1000);
357555c0
JB		 2367
2368 /* IVB wants error correction enabled */
2369 if (IS_IVYBRIDGE(dev))
2370 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2372}
2373
01a415fd
DV		 2374static void ivb_modeset_global_resources(struct drm_device *dev)
2375{
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 struct intel_crtc *pipe_B_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2379 struct intel_crtc *pipe_C_crtc =
2380 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2381 uint32_t temp;
2382
2383 /* When everything is off disable fdi C so that we could enable fdi B
2384 * with all lanes. XXX: This misses the case where a pipe is not using
2385 * any pch resources and so doesn't need any fdi lanes. */
2386 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2394 }
2395}
2396
8db9d77b
ZW		 2397/* The FDI link training functions for ILK/Ibexpeak. */
2398static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399{
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
0fc932b8 2404 int plane = intel_crtc->plane;
5eddb70b 2405 u32 reg, temp, tries;
8db9d77b 2406
0fc932b8
JB		 2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2410
e1a44743
AJ		 2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
5eddb70b
CW		 2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
e1a44743
AJ		 2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2417 I915_WRITE(reg, temp);
2418 I915_READ(reg);
e1a44743
AJ		 2419 udelay(150);
2420
8db9d77b 2421 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
77ffb597
AJ		 2424 temp &= ~(7 << 19);
2425 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2429
5eddb70b
CW		 2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436 POSTING_READ(reg);
8db9d77b
ZW		 2437 udelay(150);
2438
5b2adf89 2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2443
5eddb70b 2444 reg = FDI_RX_IIR(pipe);
e1a44743 2445 for (tries = 0; tries < 5; tries++) {
5eddb70b 2446 temp = I915_READ(reg);
8db9d77b
ZW		 2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2452 break;
2453 }
8db9d77b 2454 }
e1a44743 2455 if (tries == 5)
5eddb70b 2456 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2457
2458 /* Train 2 */
5eddb70b
CW		 2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
8db9d77b
ZW		 2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2463 I915_WRITE(reg, temp);
8db9d77b 2464
5eddb70b
CW		 2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 POSTING_READ(reg);
2472 udelay(150);
8db9d77b 2473
5eddb70b 2474 reg = FDI_RX_IIR(pipe);
e1a44743 2475 for (tries = 0; tries < 5; tries++) {
5eddb70b 2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2482 break;
2483 }
8db9d77b 2484 }
e1a44743 2485 if (tries == 5)
5eddb70b 2486 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2487
2488 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2489
8db9d77b
ZW		 2490}
2491
0206e353 2492static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497};
2498
2499/* The FDI link training functions for SNB/Cougarpoint. */
2500static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501{
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
fa37d39e 2506 u32 reg, temp, i, retry;
8db9d77b 2507
e1a44743
AJ		 2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
5eddb70b
CW		 2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
e1a44743
AJ		 2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
e1a44743
AJ		 2517 udelay(150);
2518
8db9d77b 2519 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
77ffb597
AJ		 2522 temp &= ~(7 << 19);
2523 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 /* SNB-B */
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2530
d74cf324
DV		 2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
5eddb70b
CW		 2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
5eddb70b
CW		 2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
8db9d77b
ZW		 2546 udelay(150);
2547
0206e353 2548 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
8db9d77b
ZW		 2556 udelay(500);
2557
fa37d39e
SP		 2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565 break;
2566 }
2567 udelay(50);
8db9d77b 2568 }
fa37d39e
SP		 2569 if (retry < 5)
2570 break;
8db9d77b
ZW		 2571 }
2572 if (i == 4)
5eddb70b 2573 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2574
2575 /* Train 2 */
5eddb70b
CW		 2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 if (IS_GEN6(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 }
5eddb70b 2585 I915_WRITE(reg, temp);
8db9d77b 2586
5eddb70b
CW		 2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595 }
5eddb70b
CW		 2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
8db9d77b
ZW		 2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
8db9d77b
ZW		 2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
8db9d77b
ZW		 2609 udelay(500);
2610
fa37d39e
SP		 2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618 break;
2619 }
2620 udelay(50);
8db9d77b 2621 }
fa37d39e
SP		 2622 if (retry < 5)
2623 break;
8db9d77b
ZW		 2624 }
2625 if (i == 4)
5eddb70b 2626 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2627
2628 DRM_DEBUG_KMS("FDI train done.\n");
2629}
2630
357555c0
JB		 2631/* Manual link training for Ivy Bridge A0 parts */
2632static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2638 u32 reg, temp, i;
2639
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641 for train result */
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(150);
2650
01a415fd
DV		 2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2653
357555c0
JB		 2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~(7 << 19);
2658 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2663 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
d74cf324
DV		 2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
357555c0
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2674 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677 POSTING_READ(reg);
2678 udelay(150);
2679
0206e353 2680 for (i = 0; i < 4; i++) {
357555c0
JB		 2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(500);
2689
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2698 break;
2699 }
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 1 fail!\n");
2703
2704 /* Train 2 */
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2712
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2718
2719 POSTING_READ(reg);
2720 udelay(150);
2721
0206e353 2722 for (i = 0; i < 4; i++) {
357555c0
JB		 2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(500);
2731
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2739 break;
2740 }
2741 }
2742 if (i == 4)
2743 DRM_ERROR("FDI train 2 fail!\n");
2744
2745 DRM_DEBUG_KMS("FDI train done.\n");
2746}
2747
88cefb6c 2748static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2749{
88cefb6c 2750 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2751 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2752 int pipe = intel_crtc->pipe;
5eddb70b 2753 u32 reg, temp;
79e53945 2754
c64e311e 2755
c98e9dcf 2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2760 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764 POSTING_READ(reg);
c98e9dcf
JB		 2765 udelay(200);
2766
2767 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771 POSTING_READ(reg);
c98e9dcf
JB		 2772 udelay(200);
2773
20749730
PZ		 2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2779
20749730
PZ		 2780 POSTING_READ(reg);
2781 udelay(100);
6be4a607 2782 }
0e23b99d
JB		 2783}
2784
88cefb6c
DV		 2785static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786{
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp;
2791
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
2803 udelay(100);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809 /* Wait for the clocks to turn off. */
2810 POSTING_READ(reg);
2811 udelay(100);
2812}
2813
0fc932b8
JB		 2814static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815{
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 POSTING_READ(reg);
2827
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
dfd07d72 2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834 POSTING_READ(reg);
2835 udelay(100);
2836
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2840 }
0fc932b8
JB		 2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
dfd07d72 2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865}
2866
5bb61643
CW		 2867static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868{
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2872 unsigned long flags;
2873 bool pending;
2874
10d83730
VS		 2875 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2877 return false;
2878
2879 spin_lock_irqsave(&dev->event_lock, flags);
2880 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881 spin_unlock_irqrestore(&dev->event_lock, flags);
2882
2883 return pending;
2884}
2885
e6c3a2a6
CW		 2886static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2887{
0f91128d 2888 struct drm_device *dev = crtc->dev;
5bb61643 2889 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2890
2891 if (crtc->fb == NULL)
2892 return;
2893
2c10d571
DV		 2894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2895
5bb61643
CW		 2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2898
0f91128d
CW		 2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2902}
2903
fc316cbe 2904static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2905{
2906 struct drm_device *dev = crtc->dev;
228d3e36 2907 struct intel_encoder *intel_encoder;
040484af
JB		 2908
2909 /*
2910 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2911 * must be driven by its own crtc; no sharing is possible.
2912 */
228d3e36 2913 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2914 switch (intel_encoder->type) {
040484af 2915 case INTEL_OUTPUT_EDP:
228d3e36 2916 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2917 return false;
2918 continue;
2919 }
2920 }
2921
2922 return true;
2923}
2924
fc316cbe
PZ		 2925static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2926{
2927 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2928}
2929
e615efe4
ED		 2930/* Program iCLKIP clock to the desired frequency */
2931static void lpt_program_iclkip(struct drm_crtc *crtc)
2932{
2933 struct drm_device *dev = crtc->dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2936 u32 temp;
2937
09153000
DV		 2938 mutex_lock(&dev_priv->dpio_lock);
2939
e615efe4
ED		 2940 /* It is necessary to ungate the pixclk gate prior to programming
2941 * the divisors, and gate it back when it is done.
2942 */
2943 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2944
2945 /* Disable SSCCTL */
2946 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2947 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2948 SBI_SSCCTL_DISABLE,
2949 SBI_ICLK);
e615efe4
ED		 2950
2951 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2952 if (crtc->mode.clock == 20000) {
2953 auxdiv = 1;
2954 divsel = 0x41;
2955 phaseinc = 0x20;
2956 } else {
2957 /* The iCLK virtual clock root frequency is in MHz,
2958 * but the crtc->mode.clock in in KHz. To get the divisors,
2959 * it is necessary to divide one by another, so we
2960 * convert the virtual clock precision to KHz here for higher
2961 * precision.
2962 */
2963 u32 iclk_virtual_root_freq = 172800 * 1000;
2964 u32 iclk_pi_range = 64;
2965 u32 desired_divisor, msb_divisor_value, pi_value;
2966
2967 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2968 msb_divisor_value = desired_divisor / iclk_pi_range;
2969 pi_value = desired_divisor % iclk_pi_range;
2970
2971 auxdiv = 0;
2972 divsel = msb_divisor_value - 2;
2973 phaseinc = pi_value;
2974 }
2975
2976 /* This should not happen with any sane values */
2977 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2978 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2979 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2980 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2981
2982 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2983 crtc->mode.clock,
2984 auxdiv,
2985 divsel,
2986 phasedir,
2987 phaseinc);
2988
2989 /* Program SSCDIVINTPHASE6 */
988d6ee8 2990 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2991 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2992 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2993 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2994 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2995 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2996 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2997 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2998
2999 /* Program SSCAUXDIV */
988d6ee8 3000 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3001 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3002 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3003 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3004
3005 /* Enable modulator and associated divider */
988d6ee8 3006 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3007 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3008 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3009
3010 /* Wait for initialization time */
3011 udelay(24);
3012
3013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3014
3015 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3016}
3017
f67a559d
JB		 3018/*
3019 * Enable PCH resources required for PCH ports:
3020 * - PCH PLLs
3021 * - FDI training & RX/TX
3022 * - update transcoder timings
3023 * - DP transcoding bits
3024 * - transcoder
3025 */
3026static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3027{
3028 struct drm_device *dev = crtc->dev;
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 int pipe = intel_crtc->pipe;
ee7b9f93 3032 u32 reg, temp;
2c07245f 3033
e7e164db
CW		 3034 assert_transcoder_disabled(dev_priv, pipe);
3035
cd986abb
DV		 3036 /* Write the TU size bits before fdi link training, so that error
3037 * detection works. */
3038 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3039 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3040
c98e9dcf 3041 /* For PCH output, training FDI link */
674cf967 3042 dev_priv->display.fdi_link_train(crtc);
2c07245f 3043
572deb37
DV		 3044 /* XXX: pch pll's can be enabled any time before we enable the PCH
3045 * transcoder, and we actually should do this to not upset any PCH
3046 * transcoder that already use the clock when we share it.
3047 *
3048 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3049 * unconditionally resets the pll - we need that to have the right LVDS
3050 * enable sequence. */
b6b4e185 3051 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3052
303b81e0 3053 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3054 u32 sel;
4b645f14 3055
c98e9dcf 3056 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3057 switch (pipe) {
3058 default:
3059 case 0:
3060 temp |= TRANSA_DPLL_ENABLE;
3061 sel = TRANSA_DPLLB_SEL;
3062 break;
3063 case 1:
3064 temp |= TRANSB_DPLL_ENABLE;
3065 sel = TRANSB_DPLLB_SEL;
3066 break;
3067 case 2:
3068 temp |= TRANSC_DPLL_ENABLE;
3069 sel = TRANSC_DPLLB_SEL;
3070 break;
d64311ab 3071 }
ee7b9f93
JB		 3072 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3073 temp |= sel;
3074 else
3075 temp &= ~sel;
c98e9dcf 3076 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3077 }
5eddb70b 3078
d9b6cb56
JB		 3079 /* set transcoder timing, panel must allow it */
3080 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3081 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3082 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3083 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3084
5eddb70b
CW		 3085 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3086 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3087 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3088 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3089
303b81e0 3090 intel_fdi_normal_train(crtc);
5e84e1a4 3091
c98e9dcf
JB		 3092 /* For PCH DP, enable TRANS_DP_CTL */
3093 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3094 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3095 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3096 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3097 reg = TRANS_DP_CTL(pipe);
3098 temp = I915_READ(reg);
3099 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3100 TRANS_DP_SYNC_MASK |
3101 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3102 temp |= (TRANS_DP_OUTPUT_ENABLE |
3103 TRANS_DP_ENH_FRAMING);
9325c9f0 3104 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3105
3106 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3107 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3108 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3109 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3110
3111 switch (intel_trans_dp_port_sel(crtc)) {
3112 case PCH_DP_B:
5eddb70b 3113 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3114 break;
3115 case PCH_DP_C:
5eddb70b 3116 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3117 break;
3118 case PCH_DP_D:
5eddb70b 3119 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3120 break;
3121 default:
e95d41e1 3122 BUG();
32f9d658 3123 }
2c07245f 3124
5eddb70b 3125 I915_WRITE(reg, temp);
6be4a607 3126 }
b52eb4dc 3127
b8a4f404 3128 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3129}
3130
1507e5bd
PZ		 3131static void lpt_pch_enable(struct drm_crtc *crtc)
3132{
3133 struct drm_device *dev = crtc->dev;
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3136 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3137
daed2dbb 3138 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3139
8c52b5e8 3140 lpt_program_iclkip(crtc);
1507e5bd 3141
0540e488 3142 /* Set transcoder timing. */
daed2dbb
PZ		 3143 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3144 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3145 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3146
daed2dbb
PZ		 3147 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3148 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3149 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3150 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3151
937bb610 3152 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3153}
3154
ee7b9f93
JB		 3155static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3156{
3157 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3158
3159 if (pll == NULL)
3160 return;
3161
3162 if (pll->refcount == 0) {
3163 WARN(1, "bad PCH PLL refcount\n");
3164 return;
3165 }
3166
3167 --pll->refcount;
3168 intel_crtc->pch_pll = NULL;
3169}
3170
3171static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3172{
3173 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3174 struct intel_pch_pll *pll;
3175 int i;
3176
3177 pll = intel_crtc->pch_pll;
3178 if (pll) {
3179 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3180 intel_crtc->base.base.id, pll->pll_reg);
3181 goto prepare;
3182 }
3183
98b6bd99
DV		 3184 if (HAS_PCH_IBX(dev_priv->dev)) {
3185 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3186 i = intel_crtc->pipe;
3187 pll = &dev_priv->pch_plls[i];
3188
3189 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3190 intel_crtc->base.base.id, pll->pll_reg);
3191
3192 goto found;
3193 }
3194
ee7b9f93
JB		 3195 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3196 pll = &dev_priv->pch_plls[i];
3197
3198 /* Only want to check enabled timings first */
3199 if (pll->refcount == 0)
3200 continue;
3201
3202 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3203 fp == I915_READ(pll->fp0_reg)) {
3204 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3205 intel_crtc->base.base.id,
3206 pll->pll_reg, pll->refcount, pll->active);
3207
3208 goto found;
3209 }
3210 }
3211
3212 /* Ok no matching timings, maybe there's a free one? */
3213 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3214 pll = &dev_priv->pch_plls[i];
3215 if (pll->refcount == 0) {
3216 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3217 intel_crtc->base.base.id, pll->pll_reg);
3218 goto found;
3219 }
3220 }
3221
3222 return NULL;
3223
3224found:
3225 intel_crtc->pch_pll = pll;
3226 pll->refcount++;
3227 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3228prepare: /* separate function? */
3229 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3230
e04c7350
CW		 3231 /* Wait for the clocks to stabilize before rewriting the regs */
3232 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3233 POSTING_READ(pll->pll_reg);
3234 udelay(150);
e04c7350
CW		 3235
3236 I915_WRITE(pll->fp0_reg, fp);
3237 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3238 pll->on = false;
3239 return pll;
3240}
3241
d4270e57
JB		 3242void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3243{
3244 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3245 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3246 u32 temp;
3247
3248 temp = I915_READ(dslreg);
3249 udelay(500);
3250 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3251 if (wait_for(I915_READ(dslreg) != temp, 5))
3252 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3253 }
3254}
3255
f67a559d
JB		 3256static void ironlake_crtc_enable(struct drm_crtc *crtc)
3257{
3258 struct drm_device *dev = crtc->dev;
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3261 struct intel_encoder *encoder;
f67a559d
JB		 3262 int pipe = intel_crtc->pipe;
3263 int plane = intel_crtc->plane;
3264 u32 temp;
3265 bool is_pch_port;
3266
08a48469
DV		 3267 WARN_ON(!crtc->enabled);
3268
f67a559d
JB		 3269 if (intel_crtc->active)
3270 return;
3271
3272 intel_crtc->active = true;
3273 intel_update_watermarks(dev);
3274
3275 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3276 temp = I915_READ(PCH_LVDS);
3277 if ((temp & LVDS_PORT_EN) == 0)
3278 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3279 }
3280
fc316cbe 3281 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3282
46b6f814 3283 if (is_pch_port) {
fff367c7
DV		 3284 /* Note: FDI PLL enabling _must_ be done before we enable the
3285 * cpu pipes, hence this is separate from all the other fdi/pch
3286 * enabling. */
88cefb6c 3287 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3288 } else {
3289 assert_fdi_tx_disabled(dev_priv, pipe);
3290 assert_fdi_rx_disabled(dev_priv, pipe);
3291 }
f67a559d 3292
bf49ec8c
DV		 3293 for_each_encoder_on_crtc(dev, crtc, encoder)
3294 if (encoder->pre_enable)
3295 encoder->pre_enable(encoder);
f67a559d
JB		 3296
3297 /* Enable panel fitting for LVDS */
3298 if (dev_priv->pch_pf_size &&
547dc041
JN		 3299 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3300 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3301 /* Force use of hard-coded filter coefficients
3302 * as some pre-programmed values are broken,
3303 * e.g. x201.
3304 */
13888d78
PZ		 3305 if (IS_IVYBRIDGE(dev))
3306 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3307 PF_PIPE_SEL_IVB(pipe));
3308 else
3309 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3310 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3311 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3312 }
3313
9c54c0dd
JB		 3314 /*
3315 * On ILK+ LUT must be loaded before the pipe is running but with
3316 * clocks enabled
3317 */
3318 intel_crtc_load_lut(crtc);
3319
f67a559d
JB		 3320 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3321 intel_enable_plane(dev_priv, plane, pipe);
3322
3323 if (is_pch_port)
3324 ironlake_pch_enable(crtc);
c98e9dcf 3325
d1ebd816 3326 mutex_lock(&dev->struct_mutex);
bed4a673 3327 intel_update_fbc(dev);
d1ebd816
BW		 3328 mutex_unlock(&dev->struct_mutex);
3329
6b383a7f 3330 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3331
fa5c73b1
DV		 3332 for_each_encoder_on_crtc(dev, crtc, encoder)
3333 encoder->enable(encoder);
61b77ddd
DV		 3334
3335 if (HAS_PCH_CPT(dev))
3336 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3337
3338 /*
3339 * There seems to be a race in PCH platform hw (at least on some
3340 * outputs) where an enabled pipe still completes any pageflip right
3341 * away (as if the pipe is off) instead of waiting for vblank. As soon
3342 * as the first vblank happend, everything works as expected. Hence just
3343 * wait for one vblank before returning to avoid strange things
3344 * happening.
3345 */
3346 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3347}
3348
4f771f10
PZ		 3349static void haswell_crtc_enable(struct drm_crtc *crtc)
3350{
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 struct intel_encoder *encoder;
3355 int pipe = intel_crtc->pipe;
3356 int plane = intel_crtc->plane;
4f771f10
PZ		 3357 bool is_pch_port;
3358
3359 WARN_ON(!crtc->enabled);
3360
3361 if (intel_crtc->active)
3362 return;
3363
3364 intel_crtc->active = true;
3365 intel_update_watermarks(dev);
3366
fc316cbe 3367 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3368
83616634 3369 if (is_pch_port)
04945641 3370 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3371
3372 for_each_encoder_on_crtc(dev, crtc, encoder)
3373 if (encoder->pre_enable)
3374 encoder->pre_enable(encoder);
3375
1f544388 3376 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3377
1f544388 3378 /* Enable panel fitting for eDP */
547dc041
JN		 3379 if (dev_priv->pch_pf_size &&
3380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3381 /* Force use of hard-coded filter coefficients
3382 * as some pre-programmed values are broken,
3383 * e.g. x201.
3384 */
54075a7d
PZ		 3385 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3386 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3387 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3388 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3389 }
3390
3391 /*
3392 * On ILK+ LUT must be loaded before the pipe is running but with
3393 * clocks enabled
3394 */
3395 intel_crtc_load_lut(crtc);
3396
1f544388
PZ		 3397 intel_ddi_set_pipe_settings(crtc);
3398 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3399
3400 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3401 intel_enable_plane(dev_priv, plane, pipe);
3402
3403 if (is_pch_port)
1507e5bd 3404 lpt_pch_enable(crtc);
4f771f10
PZ		 3405
3406 mutex_lock(&dev->struct_mutex);
3407 intel_update_fbc(dev);
3408 mutex_unlock(&dev->struct_mutex);
3409
3410 intel_crtc_update_cursor(crtc, true);
3411
3412 for_each_encoder_on_crtc(dev, crtc, encoder)
3413 encoder->enable(encoder);
3414
4f771f10
PZ		 3415 /*
3416 * There seems to be a race in PCH platform hw (at least on some
3417 * outputs) where an enabled pipe still completes any pageflip right
3418 * away (as if the pipe is off) instead of waiting for vblank. As soon
3419 * as the first vblank happend, everything works as expected. Hence just
3420 * wait for one vblank before returning to avoid strange things
3421 * happening.
3422 */
3423 intel_wait_for_vblank(dev, intel_crtc->pipe);
3424}
3425
6be4a607
JB		 3426static void ironlake_crtc_disable(struct drm_crtc *crtc)
3427{
3428 struct drm_device *dev = crtc->dev;
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3431 struct intel_encoder *encoder;
6be4a607
JB		 3432 int pipe = intel_crtc->pipe;
3433 int plane = intel_crtc->plane;
5eddb70b 3434 u32 reg, temp;
b52eb4dc 3435
ef9c3aee 3436
f7abfe8b
CW		 3437 if (!intel_crtc->active)
3438 return;
3439
ea9d758d
DV		 3440 for_each_encoder_on_crtc(dev, crtc, encoder)
3441 encoder->disable(encoder);
3442
e6c3a2a6 3443 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3444 drm_vblank_off(dev, pipe);
6b383a7f 3445 intel_crtc_update_cursor(crtc, false);
5eddb70b 3446
b24e7179 3447 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3448
973d04f9
CW		 3449 if (dev_priv->cfb_plane == plane)
3450 intel_disable_fbc(dev);
2c07245f 3451
b24e7179 3452 intel_disable_pipe(dev_priv, pipe);
32f9d658 3453
6be4a607 3454 /* Disable PF */
9db4a9c7
JB		 3455 I915_WRITE(PF_CTL(pipe), 0);
3456 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3457
bf49ec8c
DV		 3458 for_each_encoder_on_crtc(dev, crtc, encoder)
3459 if (encoder->post_disable)
3460 encoder->post_disable(encoder);
2c07245f 3461
0fc932b8 3462 ironlake_fdi_disable(crtc);
249c0e64 3463
b8a4f404 3464 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3465
6be4a607
JB		 3466 if (HAS_PCH_CPT(dev)) {
3467 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3468 reg = TRANS_DP_CTL(pipe);
3469 temp = I915_READ(reg);
3470 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3471 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3472 I915_WRITE(reg, temp);
6be4a607
JB		 3473
3474 /* disable DPLL_SEL */
3475 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3476 switch (pipe) {
3477 case 0:
d64311ab 3478 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3479 break;
3480 case 1:
6be4a607 3481 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3482 break;
3483 case 2:
4b645f14 3484 /* C shares PLL A or B */
d64311ab 3485 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3486 break;
3487 default:
3488 BUG(); /* wtf */
3489 }
6be4a607 3490 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3491 }
e3421a18 3492
6be4a607 3493 /* disable PCH DPLL */
ee7b9f93 3494 intel_disable_pch_pll(intel_crtc);
8db9d77b 3495
88cefb6c 3496 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3497
f7abfe8b 3498 intel_crtc->active = false;
6b383a7f 3499 intel_update_watermarks(dev);
d1ebd816
BW		 3500
3501 mutex_lock(&dev->struct_mutex);
6b383a7f 3502 intel_update_fbc(dev);
d1ebd816 3503 mutex_unlock(&dev->struct_mutex);
6be4a607 3504}
1b3c7a47 3505
4f771f10 3506static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3507{
4f771f10
PZ		 3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3511 struct intel_encoder *encoder;
3512 int pipe = intel_crtc->pipe;
3513 int plane = intel_crtc->plane;
ad80a810 3514 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3515 bool is_pch_port;
ee7b9f93 3516
4f771f10
PZ		 3517 if (!intel_crtc->active)
3518 return;
3519
83616634
PZ		 3520 is_pch_port = haswell_crtc_driving_pch(crtc);
3521
4f771f10
PZ		 3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 encoder->disable(encoder);
3524
3525 intel_crtc_wait_for_pending_flips(crtc);
3526 drm_vblank_off(dev, pipe);
3527 intel_crtc_update_cursor(crtc, false);
3528
3529 intel_disable_plane(dev_priv, plane, pipe);
3530
3531 if (dev_priv->cfb_plane == plane)
3532 intel_disable_fbc(dev);
3533
3534 intel_disable_pipe(dev_priv, pipe);
3535
ad80a810 3536 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3537
3538 /* Disable PF */
3539 I915_WRITE(PF_CTL(pipe), 0);
3540 I915_WRITE(PF_WIN_SZ(pipe), 0);
3541
1f544388 3542 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3543
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
83616634 3548 if (is_pch_port) {
ab4d966c 3549 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3550 intel_ddi_fdi_disable(crtc);
83616634 3551 }
4f771f10
PZ		 3552
3553 intel_crtc->active = false;
3554 intel_update_watermarks(dev);
3555
3556 mutex_lock(&dev->struct_mutex);
3557 intel_update_fbc(dev);
3558 mutex_unlock(&dev->struct_mutex);
3559}
3560
ee7b9f93
JB		 3561static void ironlake_crtc_off(struct drm_crtc *crtc)
3562{
3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564 intel_put_pch_pll(intel_crtc);
3565}
3566
6441ab5f
PZ		 3567static void haswell_crtc_off(struct drm_crtc *crtc)
3568{
a5c961d1
PZ		 3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570
3571 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3572 * start using it. */
1a240d4d 3573 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3574
6441ab5f
PZ		 3575 intel_ddi_put_crtc_pll(crtc);
3576}
3577
02e792fb
DV		 3578static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3579{
02e792fb 3580 if (!enable && intel_crtc->overlay) {
23f09ce3 3581 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3582 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3583
23f09ce3 3584 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3585 dev_priv->mm.interruptible = false;
3586 (void) intel_overlay_switch_off(intel_crtc->overlay);
3587 dev_priv->mm.interruptible = true;
23f09ce3 3588 mutex_unlock(&dev->struct_mutex);
02e792fb 3589 }
02e792fb 3590
5dcdbcb0
CW		 3591 /* Let userspace switch the overlay on again. In most cases userspace
3592 * has to recompute where to put it anyway.
3593 */
02e792fb
DV		 3594}
3595
0b8765c6 3596static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3597{
3598 struct drm_device *dev = crtc->dev;
79e53945
JB		 3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3601 struct intel_encoder *encoder;
79e53945 3602 int pipe = intel_crtc->pipe;
80824003 3603 int plane = intel_crtc->plane;
79e53945 3604
08a48469
DV		 3605 WARN_ON(!crtc->enabled);
3606
f7abfe8b
CW		 3607 if (intel_crtc->active)
3608 return;
3609
3610 intel_crtc->active = true;
6b383a7f
CW		 3611 intel_update_watermarks(dev);
3612
63d7bbe9 3613 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3614
3615 for_each_encoder_on_crtc(dev, crtc, encoder)
3616 if (encoder->pre_enable)
3617 encoder->pre_enable(encoder);
3618
040484af 3619 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3620 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3621
0b8765c6 3622 intel_crtc_load_lut(crtc);
bed4a673 3623 intel_update_fbc(dev);
79e53945 3624
0b8765c6
JB		 3625 /* Give the overlay scaler a chance to enable if it's on this pipe */
3626 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3627 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3628
fa5c73b1
DV		 3629 for_each_encoder_on_crtc(dev, crtc, encoder)
3630 encoder->enable(encoder);
0b8765c6 3631}
79e53945 3632
0b8765c6
JB		 3633static void i9xx_crtc_disable(struct drm_crtc *crtc)
3634{
3635 struct drm_device *dev = crtc->dev;
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3638 struct intel_encoder *encoder;
0b8765c6
JB		 3639 int pipe = intel_crtc->pipe;
3640 int plane = intel_crtc->plane;
24a1f16d 3641 u32 pctl;
b690e96c 3642
ef9c3aee 3643
f7abfe8b
CW		 3644 if (!intel_crtc->active)
3645 return;
3646
ea9d758d
DV		 3647 for_each_encoder_on_crtc(dev, crtc, encoder)
3648 encoder->disable(encoder);
3649
0b8765c6 3650 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3651 intel_crtc_wait_for_pending_flips(crtc);
3652 drm_vblank_off(dev, pipe);
0b8765c6 3653 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3654 intel_crtc_update_cursor(crtc, false);
0b8765c6 3655
973d04f9
CW		 3656 if (dev_priv->cfb_plane == plane)
3657 intel_disable_fbc(dev);
79e53945 3658
b24e7179 3659 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3660 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3661
3662 /* Disable pannel fitter if it is on this pipe. */
3663 pctl = I915_READ(PFIT_CONTROL);
3664 if ((pctl & PFIT_ENABLE) &&
3665 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3666 I915_WRITE(PFIT_CONTROL, 0);
3667
63d7bbe9 3668 intel_disable_pll(dev_priv, pipe);
0b8765c6 3669
f7abfe8b 3670 intel_crtc->active = false;
6b383a7f
CW		 3671 intel_update_fbc(dev);
3672 intel_update_watermarks(dev);
0b8765c6
JB		 3673}
3674
ee7b9f93
JB		 3675static void i9xx_crtc_off(struct drm_crtc *crtc)
3676{
3677}
3678
976f8a20
DV		 3679static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3680 bool enabled)
2c07245f
ZW		 3681{
3682 struct drm_device *dev = crtc->dev;
3683 struct drm_i915_master_private *master_priv;
3684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685 int pipe = intel_crtc->pipe;
79e53945
JB		 3686
3687 if (!dev->primary->master)
3688 return;
3689
3690 master_priv = dev->primary->master->driver_priv;
3691 if (!master_priv->sarea_priv)
3692 return;
3693
79e53945
JB		 3694 switch (pipe) {
3695 case 0:
3696 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3697 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3698 break;
3699 case 1:
3700 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3701 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3702 break;
3703 default:
9db4a9c7 3704 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3705 break;
3706 }
79e53945
JB		 3707}
3708
976f8a20
DV		 3709/**
3710 * Sets the power management mode of the pipe and plane.
3711 */
3712void intel_crtc_update_dpms(struct drm_crtc *crtc)
3713{
3714 struct drm_device *dev = crtc->dev;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 struct intel_encoder *intel_encoder;
3717 bool enable = false;
3718
3719 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3720 enable |= intel_encoder->connectors_active;
3721
3722 if (enable)
3723 dev_priv->display.crtc_enable(crtc);
3724 else
3725 dev_priv->display.crtc_disable(crtc);
3726
3727 intel_crtc_update_sarea(crtc, enable);
3728}
3729
3730static void intel_crtc_noop(struct drm_crtc *crtc)
3731{
3732}
3733
cdd59983
CW		 3734static void intel_crtc_disable(struct drm_crtc *crtc)
3735{
cdd59983 3736 struct drm_device *dev = crtc->dev;
976f8a20 3737 struct drm_connector *connector;
ee7b9f93 3738 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3740
976f8a20
DV		 3741 /* crtc should still be enabled when we disable it. */
3742 WARN_ON(!crtc->enabled);
3743
7b9f35a6 3744 intel_crtc->eld_vld = false;
976f8a20
DV		 3745 dev_priv->display.crtc_disable(crtc);
3746 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3747 dev_priv->display.off(crtc);
3748
931872fc
CW		 3749 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3750 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3751
3752 if (crtc->fb) {
3753 mutex_lock(&dev->struct_mutex);
1690e1eb 3754 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3755 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3756 crtc->fb = NULL;
3757 }
3758
3759 /* Update computed state. */
3760 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3761 if (!connector->encoder || !connector->encoder->crtc)
3762 continue;
3763
3764 if (connector->encoder->crtc != crtc)
3765 continue;
3766
3767 connector->dpms = DRM_MODE_DPMS_OFF;
3768 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3769 }
3770}
3771
a261b246 3772void intel_modeset_disable(struct drm_device *dev)
79e53945 3773{
a261b246
DV		 3774 struct drm_crtc *crtc;
3775
3776 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3777 if (crtc->enabled)
3778 intel_crtc_disable(crtc);
3779 }
79e53945
JB		 3780}
3781
1f703855 3782void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3783{
7e7d76c3
JB		 3784}
3785
ea5b213a 3786void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3787{
4ef69c7a 3788 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3789
ea5b213a
CW		 3790 drm_encoder_cleanup(encoder);
3791 kfree(intel_encoder);
7e7d76c3
JB		 3792}
3793
5ab432ef
DV		 3794/* Simple dpms helper for encodres with just one connector, no cloning and only
3795 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3796 * state of the entire output pipe. */
3797void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3798{
5ab432ef
DV		 3799 if (mode == DRM_MODE_DPMS_ON) {
3800 encoder->connectors_active = true;
3801
b2cabb0e 3802 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3803 } else {
3804 encoder->connectors_active = false;
3805
b2cabb0e 3806 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3807 }
79e53945
JB		 3808}
3809
0a91ca29
DV		 3810/* Cross check the actual hw state with our own modeset state tracking (and it's
3811 * internal consistency). */
b980514c 3812static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3813{
0a91ca29
DV		 3814 if (connector->get_hw_state(connector)) {
3815 struct intel_encoder *encoder = connector->encoder;
3816 struct drm_crtc *crtc;
3817 bool encoder_enabled;
3818 enum pipe pipe;
3819
3820 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3821 connector->base.base.id,
3822 drm_get_connector_name(&connector->base));
3823
3824 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3825 "wrong connector dpms state\n");
3826 WARN(connector->base.encoder != &encoder->base,
3827 "active connector not linked to encoder\n");
3828 WARN(!encoder->connectors_active,
3829 "encoder->connectors_active not set\n");
3830
3831 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3832 WARN(!encoder_enabled, "encoder not enabled\n");
3833 if (WARN_ON(!encoder->base.crtc))
3834 return;
3835
3836 crtc = encoder->base.crtc;
3837
3838 WARN(!crtc->enabled, "crtc not enabled\n");
3839 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3840 WARN(pipe != to_intel_crtc(crtc)->pipe,
3841 "encoder active on the wrong pipe\n");
3842 }
79e53945
JB		 3843}
3844
5ab432ef
DV		 3845/* Even simpler default implementation, if there's really no special case to
3846 * consider. */
3847void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3848{
5ab432ef 3849 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3850
5ab432ef
DV		 3851 /* All the simple cases only support two dpms states. */
3852 if (mode != DRM_MODE_DPMS_ON)
3853 mode = DRM_MODE_DPMS_OFF;
d4270e57 3854
5ab432ef
DV		 3855 if (mode == connector->dpms)
3856 return;
3857
3858 connector->dpms = mode;
3859
3860 /* Only need to change hw state when actually enabled */
3861 if (encoder->base.crtc)
3862 intel_encoder_dpms(encoder, mode);
3863 else
8af6cf88 3864 WARN_ON(encoder->connectors_active != false);
0a91ca29 3865
b980514c 3866 intel_modeset_check_state(connector->dev);
79e53945
JB		 3867}
3868
f0947c37
DV		 3869/* Simple connector->get_hw_state implementation for encoders that support only
3870 * one connector and no cloning and hence the encoder state determines the state
3871 * of the connector. */
3872bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3873{
24929352 3874 enum pipe pipe = 0;
f0947c37 3875 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3876
f0947c37 3877 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3878}
3879
79e53945 3880static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3881 const struct drm_display_mode *mode,
79e53945
JB		 3882 struct drm_display_mode *adjusted_mode)
3883{
2c07245f 3884 struct drm_device *dev = crtc->dev;
89749350 3885
bad720ff 3886 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3887 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3888 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3889 return false;
2c07245f 3890 }
89749350 3891
f9bef081
DV		 3892 /* All interlaced capable intel hw wants timings in frames. Note though
3893 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3894 * timings, so we need to be careful not to clobber these.*/
3895 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3896 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3897
44f46b42
CW		 3898 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3899 * with a hsync front porch of 0.
3900 */
3901 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3902 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3903 return false;
3904
79e53945
JB		 3905 return true;
3906}
3907
25eb05fc
JB		 3908static int valleyview_get_display_clock_speed(struct drm_device *dev)
3909{
3910 return 400000; /* FIXME */
3911}
3912
e70236a8
JB		 3913static int i945_get_display_clock_speed(struct drm_device *dev)
3914{
3915 return 400000;
3916}
79e53945 3917
e70236a8 3918static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3919{
e70236a8
JB		 3920 return 333000;
3921}
79e53945 3922
e70236a8
JB		 3923static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3924{
3925 return 200000;
3926}
79e53945 3927
e70236a8
JB		 3928static int i915gm_get_display_clock_speed(struct drm_device *dev)
3929{
3930 u16 gcfgc = 0;
79e53945 3931
e70236a8
JB		 3932 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3933
3934 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3935 return 133000;
3936 else {
3937 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3938 case GC_DISPLAY_CLOCK_333_MHZ:
3939 return 333000;
3940 default:
3941 case GC_DISPLAY_CLOCK_190_200_MHZ:
3942 return 190000;
79e53945 3943 }
e70236a8
JB		 3944 }
3945}
3946
3947static int i865_get_display_clock_speed(struct drm_device *dev)
3948{
3949 return 266000;
3950}
3951
3952static int i855_get_display_clock_speed(struct drm_device *dev)
3953{
3954 u16 hpllcc = 0;
3955 /* Assume that the hardware is in the high speed state. This
3956 * should be the default.
3957 */
3958 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3959 case GC_CLOCK_133_200:
3960 case GC_CLOCK_100_200:
3961 return 200000;
3962 case GC_CLOCK_166_250:
3963 return 250000;
3964 case GC_CLOCK_100_133:
79e53945 3965 return 133000;
e70236a8 3966 }
79e53945 3967
e70236a8
JB		 3968 /* Shouldn't happen */
3969 return 0;
3970}
79e53945 3971
e70236a8
JB		 3972static int i830_get_display_clock_speed(struct drm_device *dev)
3973{
3974 return 133000;
79e53945
JB		 3975}
3976
2c07245f 3977static void
e69d0bc1 3978intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3979{
3980 while (*num > 0xffffff || *den > 0xffffff) {
3981 *num >>= 1;
3982 *den >>= 1;
3983 }
3984}
3985
e69d0bc1
DV		 3986void
3987intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3988 int pixel_clock, int link_clock,
3989 struct intel_link_m_n *m_n)
2c07245f 3990{
e69d0bc1 3991 m_n->tu = 64;
22ed1113
CW		 3992 m_n->gmch_m = bits_per_pixel * pixel_clock;
3993 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 3994 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 3995 m_n->link_m = pixel_clock;
3996 m_n->link_n = link_clock;
e69d0bc1 3997 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 3998}
3999
a7615030
CW		 4000static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4001{
72bbe58c
KP		 4002 if (i915_panel_use_ssc >= 0)
4003 return i915_panel_use_ssc != 0;
4004 return dev_priv->lvds_use_ssc
435793df 4005 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4006}
4007
5a354204
JB		 4008/**
4009 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4010 * @crtc: CRTC structure
3b5c78a3 4011 * @mode: requested mode
5a354204
JB		 4012 *
4013 * A pipe may be connected to one or more outputs. Based on the depth of the
4014 * attached framebuffer, choose a good color depth to use on the pipe.
4015 *
4016 * If possible, match the pipe depth to the fb depth. In some cases, this
4017 * isn't ideal, because the connected output supports a lesser or restricted
4018 * set of depths. Resolve that here:
4019 * LVDS typically supports only 6bpc, so clamp down in that case
4020 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4021 * Displays may support a restricted set as well, check EDID and clamp as
4022 * appropriate.
3b5c78a3 4023 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4024 *
4025 * RETURNS:
4026 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4027 * true if they don't match).
4028 */
4029static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4030 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4031 unsigned int *pipe_bpp,
4032 struct drm_display_mode *mode)
5a354204
JB		 4033{
4034 struct drm_device *dev = crtc->dev;
4035 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4036 struct drm_connector *connector;
6c2b7c12 4037 struct intel_encoder *intel_encoder;
5a354204
JB		 4038 unsigned int display_bpc = UINT_MAX, bpc;
4039
4040 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4041 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4042
4043 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4044 unsigned int lvds_bpc;
4045
4046 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4047 LVDS_A3_POWER_UP)
4048 lvds_bpc = 8;
4049 else
4050 lvds_bpc = 6;
4051
4052 if (lvds_bpc < display_bpc) {
82820490 4053 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4054 display_bpc = lvds_bpc;
4055 }
4056 continue;
4057 }
4058
5a354204
JB		 4059 /* Not one of the known troublemakers, check the EDID */
4060 list_for_each_entry(connector, &dev->mode_config.connector_list,
4061 head) {
6c2b7c12 4062 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4063 continue;
4064
62ac41a6
JB		 4065 /* Don't use an invalid EDID bpc value */
4066 if (connector->display_info.bpc &&
4067 connector->display_info.bpc < display_bpc) {
82820490 4068 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4069 display_bpc = connector->display_info.bpc;
4070 }
4071 }
4072
2f4f649a
JN		 4073 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4074 /* Use VBT settings if we have an eDP panel */
4075 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4076
9a30a61f 4077 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4078 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4079 display_bpc = edp_bpc;
4080 }
4081 continue;
4082 }
4083
5a354204
JB		 4084 /*
4085 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4086 * through, clamp it down. (Note: >12bpc will be caught below.)
4087 */
4088 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4089 if (display_bpc > 8 && display_bpc < 12) {
82820490 4090 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4091 display_bpc = 12;
4092 } else {
82820490 4093 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4094 display_bpc = 8;
4095 }
4096 }
4097 }
4098
3b5c78a3
AJ		 4099 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4100 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4101 display_bpc = 6;
4102 }
4103
5a354204
JB		 4104 /*
4105 * We could just drive the pipe at the highest bpc all the time and
4106 * enable dithering as needed, but that costs bandwidth. So choose
4107 * the minimum value that expresses the full color range of the fb but
4108 * also stays within the max display bpc discovered above.
4109 */
4110
94352cf9 4111 switch (fb->depth) {
5a354204
JB		 4112 case 8:
4113 bpc = 8; /* since we go through a colormap */
4114 break;
4115 case 15:
4116 case 16:
4117 bpc = 6; /* min is 18bpp */
4118 break;
4119 case 24:
578393cd 4120 bpc = 8;
5a354204
JB		 4121 break;
4122 case 30:
578393cd 4123 bpc = 10;
5a354204
JB		 4124 break;
4125 case 48:
578393cd 4126 bpc = 12;
5a354204
JB		 4127 break;
4128 default:
4129 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4130 bpc = min((unsigned int)8, display_bpc);
4131 break;
4132 }
4133
578393cd
KP		 4134 display_bpc = min(display_bpc, bpc);
4135
82820490
AJ		 4136 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4137 bpc, display_bpc);
5a354204 4138
578393cd 4139 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4140
4141 return display_bpc != bpc;
4142}
4143
a0c4da24
JB		 4144static int vlv_get_refclk(struct drm_crtc *crtc)
4145{
4146 struct drm_device *dev = crtc->dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int refclk = 27000; /* for DP & HDMI */
4149
4150 return 100000; /* only one validated so far */
4151
4152 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4153 refclk = 96000;
4154 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4155 if (intel_panel_use_ssc(dev_priv))
4156 refclk = 100000;
4157 else
4158 refclk = 96000;
4159 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4160 refclk = 100000;
4161 }
4162
4163 return refclk;
4164}
4165
c65d77d8
JB		 4166static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4167{
4168 struct drm_device *dev = crtc->dev;
4169 struct drm_i915_private *dev_priv = dev->dev_private;
4170 int refclk;
4171
a0c4da24
JB		 4172 if (IS_VALLEYVIEW(dev)) {
4173 refclk = vlv_get_refclk(crtc);
4174 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4175 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4176 refclk = dev_priv->lvds_ssc_freq * 1000;
4177 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4178 refclk / 1000);
4179 } else if (!IS_GEN2(dev)) {
4180 refclk = 96000;
4181 } else {
4182 refclk = 48000;
4183 }
4184
4185 return refclk;
4186}
4187
4188static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4189 intel_clock_t *clock)
4190{
4191 /* SDVO TV has fixed PLL values depend on its clock range,
4192 this mirrors vbios setting. */
4193 if (adjusted_mode->clock >= 100000
4194 && adjusted_mode->clock < 140500) {
4195 clock->p1 = 2;
4196 clock->p2 = 10;
4197 clock->n = 3;
4198 clock->m1 = 16;
4199 clock->m2 = 8;
4200 } else if (adjusted_mode->clock >= 140500
4201 && adjusted_mode->clock <= 200000) {
4202 clock->p1 = 1;
4203 clock->p2 = 10;
4204 clock->n = 6;
4205 clock->m1 = 12;
4206 clock->m2 = 8;
4207 }
4208}
4209
a7516a05
JB		 4210static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4211 intel_clock_t *clock,
4212 intel_clock_t *reduced_clock)
4213{
4214 struct drm_device *dev = crtc->dev;
4215 struct drm_i915_private *dev_priv = dev->dev_private;
4216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217 int pipe = intel_crtc->pipe;
4218 u32 fp, fp2 = 0;
4219
4220 if (IS_PINEVIEW(dev)) {
4221 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4222 if (reduced_clock)
4223 fp2 = (1 << reduced_clock->n) << 16 |
4224 reduced_clock->m1 << 8 | reduced_clock->m2;
4225 } else {
4226 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4227 if (reduced_clock)
4228 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4229 reduced_clock->m2;
4230 }
4231
4232 I915_WRITE(FP0(pipe), fp);
4233
4234 intel_crtc->lowfreq_avail = false;
4235 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4236 reduced_clock && i915_powersave) {
4237 I915_WRITE(FP1(pipe), fp2);
4238 intel_crtc->lowfreq_avail = true;
4239 } else {
4240 I915_WRITE(FP1(pipe), fp);
4241 }
4242}
4243
a0c4da24
JB		 4244static void vlv_update_pll(struct drm_crtc *crtc,
4245 struct drm_display_mode *mode,
4246 struct drm_display_mode *adjusted_mode,
4247 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4248 int num_connectors)
a0c4da24
JB		 4249{
4250 struct drm_device *dev = crtc->dev;
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253 int pipe = intel_crtc->pipe;
4254 u32 dpll, mdiv, pdiv;
4255 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4256 bool is_sdvo;
4257 u32 temp;
a0c4da24 4258
09153000
DV		 4259 mutex_lock(&dev_priv->dpio_lock);
4260
2a8f64ca
VP		 4261 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4262 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4263
2a8f64ca
VP		 4264 dpll = DPLL_VGA_MODE_DIS;
4265 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4266 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4267 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4268
4269 I915_WRITE(DPLL(pipe), dpll);
4270 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4271
4272 bestn = clock->n;
4273 bestm1 = clock->m1;
4274 bestm2 = clock->m2;
4275 bestp1 = clock->p1;
4276 bestp2 = clock->p2;
4277
2a8f64ca
VP		 4278 /*
4279 * In Valleyview PLL and program lane counter registers are exposed
4280 * through DPIO interface
4281 */
a0c4da24
JB		 4282 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4283 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4284 mdiv |= ((bestn << DPIO_N_SHIFT));
4285 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4286 mdiv |= (1 << DPIO_K_SHIFT);
4287 mdiv |= DPIO_ENABLE_CALIBRATION;
4288 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4289
4290 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4291
2a8f64ca 4292 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4293 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4294 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4295 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4296 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4297
2a8f64ca 4298 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4299
4300 dpll |= DPLL_VCO_ENABLE;
4301 I915_WRITE(DPLL(pipe), dpll);
4302 POSTING_READ(DPLL(pipe));
4303 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4304 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4305
2a8f64ca
VP		 4306 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4307
4308 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4309 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4310
4311 I915_WRITE(DPLL(pipe), dpll);
4312
4313 /* Wait for the clocks to stabilize. */
4314 POSTING_READ(DPLL(pipe));
4315 udelay(150);
a0c4da24 4316
2a8f64ca
VP		 4317 temp = 0;
4318 if (is_sdvo) {
4319 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4320 if (temp > 1)
4321 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4322 else
4323 temp = 0;
a0c4da24 4324 }
2a8f64ca
VP		 4325 I915_WRITE(DPLL_MD(pipe), temp);
4326 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4327
2a8f64ca
VP		 4328 /* Now program lane control registers */
4329 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4330 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4331 {
4332 temp = 0x1000C4;
4333 if(pipe == 1)
4334 temp |= (1 << 21);
4335 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4336 }
4337 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4338 {
4339 temp = 0x1000C4;
4340 if(pipe == 1)
4341 temp |= (1 << 21);
4342 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4343 }
09153000
DV		 4344
4345 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4346}
4347
eb1cbe48
DV		 4348static void i9xx_update_pll(struct drm_crtc *crtc,
4349 struct drm_display_mode *mode,
4350 struct drm_display_mode *adjusted_mode,
4351 intel_clock_t *clock, intel_clock_t *reduced_clock,
4352 int num_connectors)
4353{
4354 struct drm_device *dev = crtc->dev;
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4357 struct intel_encoder *encoder;
eb1cbe48
DV		 4358 int pipe = intel_crtc->pipe;
4359 u32 dpll;
4360 bool is_sdvo;
4361
2a8f64ca
VP		 4362 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4363
eb1cbe48
DV		 4364 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4365 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4366
4367 dpll = DPLL_VGA_MODE_DIS;
4368
4369 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4370 dpll |= DPLLB_MODE_LVDS;
4371 else
4372 dpll |= DPLLB_MODE_DAC_SERIAL;
4373 if (is_sdvo) {
4374 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4375 if (pixel_multiplier > 1) {
4376 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4377 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4378 }
4379 dpll |= DPLL_DVO_HIGH_SPEED;
4380 }
4381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4382 dpll |= DPLL_DVO_HIGH_SPEED;
4383
4384 /* compute bitmask from p1 value */
4385 if (IS_PINEVIEW(dev))
4386 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4387 else {
4388 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4389 if (IS_G4X(dev) && reduced_clock)
4390 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4391 }
4392 switch (clock->p2) {
4393 case 5:
4394 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4395 break;
4396 case 7:
4397 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4398 break;
4399 case 10:
4400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4401 break;
4402 case 14:
4403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4404 break;
4405 }
4406 if (INTEL_INFO(dev)->gen >= 4)
4407 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4408
4409 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4410 dpll |= PLL_REF_INPUT_TVCLKINBC;
4411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4412 /* XXX: just matching BIOS for now */
4413 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4414 dpll |= 3;
4415 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4416 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4417 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4418 else
4419 dpll |= PLL_REF_INPUT_DREFCLK;
4420
4421 dpll |= DPLL_VCO_ENABLE;
4422 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4423 POSTING_READ(DPLL(pipe));
4424 udelay(150);
4425
dafd226c
DV		 4426 for_each_encoder_on_crtc(dev, crtc, encoder)
4427 if (encoder->pre_pll_enable)
4428 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4429
4430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4431 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4432
4433 I915_WRITE(DPLL(pipe), dpll);
4434
4435 /* Wait for the clocks to stabilize. */
4436 POSTING_READ(DPLL(pipe));
4437 udelay(150);
4438
4439 if (INTEL_INFO(dev)->gen >= 4) {
4440 u32 temp = 0;
4441 if (is_sdvo) {
4442 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4443 if (temp > 1)
4444 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4445 else
4446 temp = 0;
4447 }
4448 I915_WRITE(DPLL_MD(pipe), temp);
4449 } else {
4450 /* The pixel multiplier can only be updated once the
4451 * DPLL is enabled and the clocks are stable.
4452 *
4453 * So write it again.
4454 */
4455 I915_WRITE(DPLL(pipe), dpll);
4456 }
4457}
4458
4459static void i8xx_update_pll(struct drm_crtc *crtc,
4460 struct drm_display_mode *adjusted_mode,
2a8f64ca 4461 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4462 int num_connectors)
4463{
4464 struct drm_device *dev = crtc->dev;
4465 struct drm_i915_private *dev_priv = dev->dev_private;
4466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4467 struct intel_encoder *encoder;
eb1cbe48
DV		 4468 int pipe = intel_crtc->pipe;
4469 u32 dpll;
4470
2a8f64ca
VP		 4471 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4472
eb1cbe48
DV		 4473 dpll = DPLL_VGA_MODE_DIS;
4474
4475 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4476 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4477 } else {
4478 if (clock->p1 == 2)
4479 dpll |= PLL_P1_DIVIDE_BY_TWO;
4480 else
4481 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4482 if (clock->p2 == 4)
4483 dpll |= PLL_P2_DIVIDE_BY_4;
4484 }
4485
4486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4487 /* XXX: just matching BIOS for now */
4488 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4489 dpll |= 3;
4490 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4491 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4492 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4493 else
4494 dpll |= PLL_REF_INPUT_DREFCLK;
4495
4496 dpll |= DPLL_VCO_ENABLE;
4497 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4498 POSTING_READ(DPLL(pipe));
4499 udelay(150);
4500
dafd226c
DV		 4501 for_each_encoder_on_crtc(dev, crtc, encoder)
4502 if (encoder->pre_pll_enable)
4503 encoder->pre_pll_enable(encoder);
eb1cbe48 4504
5b5896e4
DV		 4505 I915_WRITE(DPLL(pipe), dpll);
4506
4507 /* Wait for the clocks to stabilize. */
4508 POSTING_READ(DPLL(pipe));
4509 udelay(150);
4510
eb1cbe48
DV		 4511 /* The pixel multiplier can only be updated once the
4512 * DPLL is enabled and the clocks are stable.
4513 *
4514 * So write it again.
4515 */
4516 I915_WRITE(DPLL(pipe), dpll);
4517}
4518
b0e77b9c
PZ		 4519static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4520 struct drm_display_mode *mode,
4521 struct drm_display_mode *adjusted_mode)
4522{
4523 struct drm_device *dev = intel_crtc->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4526 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4527 uint32_t vsyncshift;
4528
4529 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4530 /* the chip adds 2 halflines automatically */
4531 adjusted_mode->crtc_vtotal -= 1;
4532 adjusted_mode->crtc_vblank_end -= 1;
4533 vsyncshift = adjusted_mode->crtc_hsync_start
4534 - adjusted_mode->crtc_htotal / 2;
4535 } else {
4536 vsyncshift = 0;
4537 }
4538
4539 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4540 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4541
fe2b8f9d 4542 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4543 (adjusted_mode->crtc_hdisplay - 1) |
4544 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4545 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4546 (adjusted_mode->crtc_hblank_start - 1) |
4547 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4548 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4549 (adjusted_mode->crtc_hsync_start - 1) |
4550 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4551
fe2b8f9d 4552 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4553 (adjusted_mode->crtc_vdisplay - 1) |
4554 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4555 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4556 (adjusted_mode->crtc_vblank_start - 1) |
4557 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4558 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4559 (adjusted_mode->crtc_vsync_start - 1) |
4560 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4561
b5e508d4
PZ		 4562 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4563 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4564 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4565 * bits. */
4566 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4567 (pipe == PIPE_B || pipe == PIPE_C))
4568 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4569
b0e77b9c
PZ		 4570 /* pipesrc controls the size that is scaled from, which should
4571 * always be the user's requested size.
4572 */
4573 I915_WRITE(PIPESRC(pipe),
4574 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4575}
4576
f564048e
EA		 4577static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4578 struct drm_display_mode *mode,
4579 struct drm_display_mode *adjusted_mode,
4580 int x, int y,
94352cf9 4581 struct drm_framebuffer *fb)
79e53945
JB		 4582{
4583 struct drm_device *dev = crtc->dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586 int pipe = intel_crtc->pipe;
80824003 4587 int plane = intel_crtc->plane;
c751ce4f 4588 int refclk, num_connectors = 0;
652c393a 4589 intel_clock_t clock, reduced_clock;
b0e77b9c 4590 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4591 bool ok, has_reduced_clock = false, is_sdvo = false;
4592 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4593 struct intel_encoder *encoder;
d4906093 4594 const intel_limit_t *limit;
5c3b82e2 4595 int ret;
79e53945 4596
6c2b7c12 4597 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4598 switch (encoder->type) {
79e53945
JB		 4599 case INTEL_OUTPUT_LVDS:
4600 is_lvds = true;
4601 break;
4602 case INTEL_OUTPUT_SDVO:
7d57382e 4603 case INTEL_OUTPUT_HDMI:
79e53945 4604 is_sdvo = true;
5eddb70b 4605 if (encoder->needs_tv_clock)
e2f0ba97 4606 is_tv = true;
79e53945 4607 break;
79e53945
JB		 4608 case INTEL_OUTPUT_TVOUT:
4609 is_tv = true;
4610 break;
a4fc5ed6
KP		 4611 case INTEL_OUTPUT_DISPLAYPORT:
4612 is_dp = true;
4613 break;
79e53945 4614 }
43565a06 4615
c751ce4f 4616 num_connectors++;
79e53945
JB		 4617 }
4618
c65d77d8 4619 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4620
d4906093
ML		 4621 /*
4622 * Returns a set of divisors for the desired target clock with the given
4623 * refclk, or FALSE. The returned values represent the clock equation:
4624 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4625 */
1b894b59 4626 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4627 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4628 &clock);
79e53945
JB		 4629 if (!ok) {
4630 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4631 return -EINVAL;
79e53945
JB		 4632 }
4633
cda4b7d3 4634 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4635 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4636
ddc9003c 4637 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4638 /*
4639 * Ensure we match the reduced clock's P to the target clock.
4640 * If the clocks don't match, we can't switch the display clock
4641 * by using the FP0/FP1. In such case we will disable the LVDS
4642 * downclock feature.
4643 */
ddc9003c 4644 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4645 dev_priv->lvds_downclock,
4646 refclk,
cec2f356 4647 &clock,
5eddb70b 4648 &reduced_clock);
7026d4ac
ZW		 4649 }
4650
c65d77d8
JB		 4651 if (is_sdvo && is_tv)
4652 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4653
eb1cbe48 4654 if (IS_GEN2(dev))
2a8f64ca
VP		 4655 i8xx_update_pll(crtc, adjusted_mode, &clock,
4656 has_reduced_clock ? &reduced_clock : NULL,
4657 num_connectors);
a0c4da24 4658 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4659 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4660 has_reduced_clock ? &reduced_clock : NULL,
4661 num_connectors);
79e53945 4662 else
eb1cbe48
DV		 4663 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4664 has_reduced_clock ? &reduced_clock : NULL,
4665 num_connectors);
79e53945
JB		 4666
4667 /* setup pipeconf */
5eddb70b 4668 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4669
4670 /* Set up the display plane register */
4671 dspcntr = DISPPLANE_GAMMA_ENABLE;
4672
929c77fb
EA		 4673 if (pipe == 0)
4674 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4675 else
4676 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4677
a6c45cf0 4678 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4679 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4680 * core speed.
4681 *
4682 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4683 * pipe == 0 check?
4684 */
e70236a8
JB		 4685 if (mode->clock >
4686 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4687 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4688 else
5eddb70b 4689 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4690 }
4691
3b5c78a3 4692 /* default to 8bpc */
dfd07d72 4693 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4694 if (is_dp) {
0c96c65b 4695 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4696 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4697 PIPECONF_DITHER_EN |
4698 PIPECONF_DITHER_TYPE_SP;
4699 }
4700 }
4701
19c03924
GB		 4702 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4703 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4704 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4705 PIPECONF_ENABLE |
4706 I965_PIPECONF_ACTIVE;
4707 }
4708 }
4709
28c97730 4710 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4711 drm_mode_debug_printmodeline(mode);
4712
a7516a05
JB		 4713 if (HAS_PIPE_CXSR(dev)) {
4714 if (intel_crtc->lowfreq_avail) {
28c97730 4715 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4716 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4717 } else {
28c97730 4718 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4719 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4720 }
4721 }
4722
617cf884 4723 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4724 if (!IS_GEN2(dev) &&
b0e77b9c 4725 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4726 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4727 else
617cf884 4728 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4729
b0e77b9c 4730 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4731
4732 /* pipesrc and dspsize control the size that is scaled from,
4733 * which should always be the user's requested size.
79e53945 4734 */
929c77fb
EA		 4735 I915_WRITE(DSPSIZE(plane),
4736 ((mode->vdisplay - 1) << 16) |
4737 (mode->hdisplay - 1));
4738 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4739
f564048e
EA		 4740 I915_WRITE(PIPECONF(pipe), pipeconf);
4741 POSTING_READ(PIPECONF(pipe));
929c77fb 4742 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4743
4744 intel_wait_for_vblank(dev, pipe);
4745
f564048e
EA		 4746 I915_WRITE(DSPCNTR(plane), dspcntr);
4747 POSTING_READ(DSPCNTR(plane));
4748
94352cf9 4749 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4750
4751 intel_update_watermarks(dev);
4752
f564048e
EA		 4753 return ret;
4754}
4755
dde86e2d 4756static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4757{
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4760 struct intel_encoder *encoder;
13d83a67
JB		 4761 u32 temp;
4762 bool has_lvds = false;
199e5d79
KP		 4763 bool has_cpu_edp = false;
4764 bool has_pch_edp = false;
4765 bool has_panel = false;
99eb6a01
KP		 4766 bool has_ck505 = false;
4767 bool can_ssc = false;
13d83a67
JB		 4768
4769 /* We need to take the global config into account */
199e5d79
KP		 4770 list_for_each_entry(encoder, &mode_config->encoder_list,
4771 base.head) {
4772 switch (encoder->type) {
4773 case INTEL_OUTPUT_LVDS:
4774 has_panel = true;
4775 has_lvds = true;
4776 break;
4777 case INTEL_OUTPUT_EDP:
4778 has_panel = true;
4779 if (intel_encoder_is_pch_edp(&encoder->base))
4780 has_pch_edp = true;
4781 else
4782 has_cpu_edp = true;
4783 break;
13d83a67
JB		 4784 }
4785 }
4786
99eb6a01
KP		 4787 if (HAS_PCH_IBX(dev)) {
4788 has_ck505 = dev_priv->display_clock_mode;
4789 can_ssc = has_ck505;
4790 } else {
4791 has_ck505 = false;
4792 can_ssc = true;
4793 }
4794
4795 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4796 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4797 has_ck505);
13d83a67
JB		 4798
4799 /* Ironlake: try to setup display ref clock before DPLL
4800 * enabling. This is only under driver's control after
4801 * PCH B stepping, previous chipset stepping should be
4802 * ignoring this setting.
4803 */
4804 temp = I915_READ(PCH_DREF_CONTROL);
4805 /* Always enable nonspread source */
4806 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4807
99eb6a01
KP		 4808 if (has_ck505)
4809 temp |= DREF_NONSPREAD_CK505_ENABLE;
4810 else
4811 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4812
199e5d79
KP		 4813 if (has_panel) {
4814 temp &= ~DREF_SSC_SOURCE_MASK;
4815 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4816
199e5d79 4817 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4818 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4819 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4820 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4821 } else
4822 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4823
4824 /* Get SSC going before enabling the outputs */
4825 I915_WRITE(PCH_DREF_CONTROL, temp);
4826 POSTING_READ(PCH_DREF_CONTROL);
4827 udelay(200);
4828
13d83a67
JB		 4829 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4830
4831 /* Enable CPU source on CPU attached eDP */
199e5d79 4832 if (has_cpu_edp) {
99eb6a01 4833 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4834 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4835 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4836 }
13d83a67
JB		 4837 else
4838 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4839 } else
4840 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4841
4842 I915_WRITE(PCH_DREF_CONTROL, temp);
4843 POSTING_READ(PCH_DREF_CONTROL);
4844 udelay(200);
4845 } else {
4846 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4847
4848 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4849
4850 /* Turn off CPU output */
4851 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4852
4853 I915_WRITE(PCH_DREF_CONTROL, temp);
4854 POSTING_READ(PCH_DREF_CONTROL);
4855 udelay(200);
4856
4857 /* Turn off the SSC source */
4858 temp &= ~DREF_SSC_SOURCE_MASK;
4859 temp |= DREF_SSC_SOURCE_DISABLE;
4860
4861 /* Turn off SSC1 */
4862 temp &= ~ DREF_SSC1_ENABLE;
4863
13d83a67
JB		 4864 I915_WRITE(PCH_DREF_CONTROL, temp);
4865 POSTING_READ(PCH_DREF_CONTROL);
4866 udelay(200);
4867 }
4868}
4869
dde86e2d
PZ		 4870/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4871static void lpt_init_pch_refclk(struct drm_device *dev)
4872{
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 struct drm_mode_config *mode_config = &dev->mode_config;
4875 struct intel_encoder *encoder;
4876 bool has_vga = false;
4877 bool is_sdv = false;
4878 u32 tmp;
4879
4880 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4881 switch (encoder->type) {
4882 case INTEL_OUTPUT_ANALOG:
4883 has_vga = true;
4884 break;
4885 }
4886 }
4887
4888 if (!has_vga)
4889 return;
4890
c00db246
DV		 4891 mutex_lock(&dev_priv->dpio_lock);
4892
dde86e2d
PZ		 4893 /* XXX: Rip out SDV support once Haswell ships for real. */
4894 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4895 is_sdv = true;
4896
4897 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4898 tmp &= ~SBI_SSCCTL_DISABLE;
4899 tmp |= SBI_SSCCTL_PATHALT;
4900 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4901
4902 udelay(24);
4903
4904 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4905 tmp &= ~SBI_SSCCTL_PATHALT;
4906 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4907
4908 if (!is_sdv) {
4909 tmp = I915_READ(SOUTH_CHICKEN2);
4910 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4911 I915_WRITE(SOUTH_CHICKEN2, tmp);
4912
4913 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4914 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4915 DRM_ERROR("FDI mPHY reset assert timeout\n");
4916
4917 tmp = I915_READ(SOUTH_CHICKEN2);
4918 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4919 I915_WRITE(SOUTH_CHICKEN2, tmp);
4920
4921 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4922 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4923 100))
4924 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4925 }
4926
4927 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4928 tmp &= ~(0xFF << 24);
4929 tmp |= (0x12 << 24);
4930 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4931
4932 if (!is_sdv) {
4933 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4934 tmp &= ~(0x3 << 6);
4935 tmp |= (1 << 6) | (1 << 0);
4936 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4937 }
4938
4939 if (is_sdv) {
4940 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4941 tmp |= 0x7FFF;
4942 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4943 }
4944
4945 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4946 tmp |= (1 << 11);
4947 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4948
4949 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4950 tmp |= (1 << 11);
4951 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4952
4953 if (is_sdv) {
4954 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4955 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4956 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4957
4958 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4959 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4960 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4961
4962 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4963 tmp |= (0x3F << 8);
4964 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4965
4966 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4967 tmp |= (0x3F << 8);
4968 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4969 }
4970
4971 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4972 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4973 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4974
4975 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4976 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4977 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4978
4979 if (!is_sdv) {
4980 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4981 tmp &= ~(7 << 13);
4982 tmp |= (5 << 13);
4983 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4984
4985 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4986 tmp &= ~(7 << 13);
4987 tmp |= (5 << 13);
4988 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4989 }
4990
4991 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4992 tmp &= ~0xFF;
4993 tmp |= 0x1C;
4994 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4995
4996 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4997 tmp &= ~0xFF;
4998 tmp |= 0x1C;
4999 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5000
5001 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5002 tmp &= ~(0xFF << 16);
5003 tmp |= (0x1C << 16);
5004 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5005
5006 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5007 tmp &= ~(0xFF << 16);
5008 tmp |= (0x1C << 16);
5009 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5010
5011 if (!is_sdv) {
5012 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5013 tmp |= (1 << 27);
5014 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5015
5016 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5017 tmp |= (1 << 27);
5018 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5019
5020 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5021 tmp &= ~(0xF << 28);
5022 tmp |= (4 << 28);
5023 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5024
5025 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5026 tmp &= ~(0xF << 28);
5027 tmp |= (4 << 28);
5028 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5029 }
5030
5031 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5032 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5033 tmp |= SBI_DBUFF0_ENABLE;
5034 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5035
5036 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5037}
5038
5039/*
5040 * Initialize reference clocks when the driver loads
5041 */
5042void intel_init_pch_refclk(struct drm_device *dev)
5043{
5044 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5045 ironlake_init_pch_refclk(dev);
5046 else if (HAS_PCH_LPT(dev))
5047 lpt_init_pch_refclk(dev);
5048}
5049
d9d444cb
JB		 5050static int ironlake_get_refclk(struct drm_crtc *crtc)
5051{
5052 struct drm_device *dev = crtc->dev;
5053 struct drm_i915_private *dev_priv = dev->dev_private;
5054 struct intel_encoder *encoder;
d9d444cb
JB		 5055 struct intel_encoder *edp_encoder = NULL;
5056 int num_connectors = 0;
5057 bool is_lvds = false;
5058
6c2b7c12 5059 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5060 switch (encoder->type) {
5061 case INTEL_OUTPUT_LVDS:
5062 is_lvds = true;
5063 break;
5064 case INTEL_OUTPUT_EDP:
5065 edp_encoder = encoder;
5066 break;
5067 }
5068 num_connectors++;
5069 }
5070
5071 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5072 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5073 dev_priv->lvds_ssc_freq);
5074 return dev_priv->lvds_ssc_freq * 1000;
5075 }
5076
5077 return 120000;
5078}
5079
c8203565 5080static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5081 struct drm_display_mode *adjusted_mode,
c8203565 5082 bool dither)
79e53945 5083{
c8203565 5084 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086 int pipe = intel_crtc->pipe;
c8203565
PZ		 5087 uint32_t val;
5088
5089 val = I915_READ(PIPECONF(pipe));
5090
dfd07d72 5091 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5092 switch (intel_crtc->bpp) {
5093 case 18:
dfd07d72 5094 val |= PIPECONF_6BPC;
c8203565
PZ		 5095 break;
5096 case 24:
dfd07d72 5097 val |= PIPECONF_8BPC;
c8203565
PZ		 5098 break;
5099 case 30:
dfd07d72 5100 val |= PIPECONF_10BPC;
c8203565
PZ		 5101 break;
5102 case 36:
dfd07d72 5103 val |= PIPECONF_12BPC;
c8203565
PZ		 5104 break;
5105 default:
cc769b62
PZ		 5106 /* Case prevented by intel_choose_pipe_bpp_dither. */
5107 BUG();
c8203565
PZ		 5108 }
5109
5110 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5111 if (dither)
5112 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5113
5114 val &= ~PIPECONF_INTERLACE_MASK;
5115 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5116 val |= PIPECONF_INTERLACED_ILK;
5117 else
5118 val |= PIPECONF_PROGRESSIVE;
5119
3685a8f3
VS		 5120 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5121 val |= PIPECONF_COLOR_RANGE_SELECT;
5122 else
5123 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5124
c8203565
PZ		 5125 I915_WRITE(PIPECONF(pipe), val);
5126 POSTING_READ(PIPECONF(pipe));
5127}
5128
86d3efce
VS		 5129/*
5130 * Set up the pipe CSC unit.
5131 *
5132 * Currently only full range RGB to limited range RGB conversion
5133 * is supported, but eventually this should handle various
5134 * RGB<->YCbCr scenarios as well.
5135 */
5136static void intel_set_pipe_csc(struct drm_crtc *crtc,
5137 const struct drm_display_mode *adjusted_mode)
5138{
5139 struct drm_device *dev = crtc->dev;
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5142 int pipe = intel_crtc->pipe;
5143 uint16_t coeff = 0x7800; /* 1.0 */
5144
5145 /*
5146 * TODO: Check what kind of values actually come out of the pipe
5147 * with these coeff/postoff values and adjust to get the best
5148 * accuracy. Perhaps we even need to take the bpc value into
5149 * consideration.
5150 */
5151
5152 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5153 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5154
5155 /*
5156 * GY/GU and RY/RU should be the other way around according
5157 * to BSpec, but reality doesn't agree. Just set them up in
5158 * a way that results in the correct picture.
5159 */
5160 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5161 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5162
5163 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5164 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5165
5166 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5167 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5168
5169 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5170 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5171 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5172
5173 if (INTEL_INFO(dev)->gen > 6) {
5174 uint16_t postoff = 0;
5175
5176 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5177 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5178
5179 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5180 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5181 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5182
5183 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5184 } else {
5185 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5186
5187 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5188 mode |= CSC_BLACK_SCREEN_OFFSET;
5189
5190 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5191 }
5192}
5193
ee2b0b38
PZ		 5194static void haswell_set_pipeconf(struct drm_crtc *crtc,
5195 struct drm_display_mode *adjusted_mode,
5196 bool dither)
5197{
5198 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5200 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5201 uint32_t val;
5202
702e7a56 5203 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5204
5205 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5206 if (dither)
5207 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5208
5209 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5210 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5211 val |= PIPECONF_INTERLACED_ILK;
5212 else
5213 val |= PIPECONF_PROGRESSIVE;
5214
702e7a56
PZ		 5215 I915_WRITE(PIPECONF(cpu_transcoder), val);
5216 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5217}
5218
6591c6e4
PZ		 5219static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5220 struct drm_display_mode *adjusted_mode,
5221 intel_clock_t *clock,
5222 bool *has_reduced_clock,
5223 intel_clock_t *reduced_clock)
5224{
5225 struct drm_device *dev = crtc->dev;
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227 struct intel_encoder *intel_encoder;
5228 int refclk;
d4906093 5229 const intel_limit_t *limit;
6591c6e4 5230 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5231
6591c6e4
PZ		 5232 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5233 switch (intel_encoder->type) {
79e53945
JB		 5234 case INTEL_OUTPUT_LVDS:
5235 is_lvds = true;
5236 break;
5237 case INTEL_OUTPUT_SDVO:
7d57382e 5238 case INTEL_OUTPUT_HDMI:
79e53945 5239 is_sdvo = true;
6591c6e4 5240 if (intel_encoder->needs_tv_clock)
e2f0ba97 5241 is_tv = true;
79e53945 5242 break;
79e53945
JB		 5243 case INTEL_OUTPUT_TVOUT:
5244 is_tv = true;
5245 break;
79e53945
JB		 5246 }
5247 }
5248
d9d444cb 5249 refclk = ironlake_get_refclk(crtc);
79e53945 5250
d4906093
ML		 5251 /*
5252 * Returns a set of divisors for the desired target clock with the given
5253 * refclk, or FALSE. The returned values represent the clock equation:
5254 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5255 */
1b894b59 5256 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5257 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5258 clock);
5259 if (!ret)
5260 return false;
cda4b7d3 5261
ddc9003c 5262 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5263 /*
5264 * Ensure we match the reduced clock's P to the target clock.
5265 * If the clocks don't match, we can't switch the display clock
5266 * by using the FP0/FP1. In such case we will disable the LVDS
5267 * downclock feature.
5268 */
6591c6e4
PZ		 5269 *has_reduced_clock = limit->find_pll(limit, crtc,
5270 dev_priv->lvds_downclock,
5271 refclk,
5272 clock,
5273 reduced_clock);
652c393a 5274 }
61e9653f
DV		 5275
5276 if (is_sdvo && is_tv)
6591c6e4
PZ		 5277 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5278
5279 return true;
5280}
5281
01a415fd
DV		 5282static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5283{
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 uint32_t temp;
5286
5287 temp = I915_READ(SOUTH_CHICKEN1);
5288 if (temp & FDI_BC_BIFURCATION_SELECT)
5289 return;
5290
5291 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5292 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5293
5294 temp |= FDI_BC_BIFURCATION_SELECT;
5295 DRM_DEBUG_KMS("enabling fdi C rx\n");
5296 I915_WRITE(SOUTH_CHICKEN1, temp);
5297 POSTING_READ(SOUTH_CHICKEN1);
5298}
5299
5300static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5301{
5302 struct drm_device *dev = intel_crtc->base.dev;
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 struct intel_crtc *pipe_B_crtc =
5305 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5306
5307 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5308 intel_crtc->pipe, intel_crtc->fdi_lanes);
5309 if (intel_crtc->fdi_lanes > 4) {
5310 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5311 intel_crtc->pipe, intel_crtc->fdi_lanes);
5312 /* Clamp lanes to avoid programming the hw with bogus values. */
5313 intel_crtc->fdi_lanes = 4;
5314
5315 return false;
5316 }
5317
5318 if (dev_priv->num_pipe == 2)
5319 return true;
5320
5321 switch (intel_crtc->pipe) {
5322 case PIPE_A:
5323 return true;
5324 case PIPE_B:
5325 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5326 intel_crtc->fdi_lanes > 2) {
5327 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5328 intel_crtc->pipe, intel_crtc->fdi_lanes);
5329 /* Clamp lanes to avoid programming the hw with bogus values. */
5330 intel_crtc->fdi_lanes = 2;
5331
5332 return false;
5333 }
5334
5335 if (intel_crtc->fdi_lanes > 2)
5336 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5337 else
5338 cpt_enable_fdi_bc_bifurcation(dev);
5339
5340 return true;
5341 case PIPE_C:
5342 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5343 if (intel_crtc->fdi_lanes > 2) {
5344 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5345 intel_crtc->pipe, intel_crtc->fdi_lanes);
5346 /* Clamp lanes to avoid programming the hw with bogus values. */
5347 intel_crtc->fdi_lanes = 2;
5348
5349 return false;
5350 }
5351 } else {
5352 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5353 return false;
5354 }
5355
5356 cpt_enable_fdi_bc_bifurcation(dev);
5357
5358 return true;
5359 default:
5360 BUG();
5361 }
5362}
5363
d4b1931c
PZ		 5364int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5365{
5366 /*
5367 * Account for spread spectrum to avoid
5368 * oversubscribing the link. Max center spread
5369 * is 2.5%; use 5% for safety's sake.
5370 */
5371 u32 bps = target_clock * bpp * 21 / 20;
5372 return bps / (link_bw * 8) + 1;
5373}
5374
f48d8f23
PZ		 5375static void ironlake_set_m_n(struct drm_crtc *crtc,
5376 struct drm_display_mode *mode,
5377 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5378{
5379 struct drm_device *dev = crtc->dev;
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5382 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5383 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5384 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5385 int target_clock, pixel_multiplier, lane, link_bw;
5386 bool is_dp = false, is_cpu_edp = false;
79e53945 5387
f48d8f23
PZ		 5388 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5389 switch (intel_encoder->type) {
a4fc5ed6
KP		 5390 case INTEL_OUTPUT_DISPLAYPORT:
5391 is_dp = true;
5392 break;
32f9d658 5393 case INTEL_OUTPUT_EDP:
e3aef172 5394 is_dp = true;
f48d8f23 5395 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5396 is_cpu_edp = true;
f48d8f23 5397 edp_encoder = intel_encoder;
32f9d658 5398 break;
79e53945 5399 }
79e53945 5400 }
61e9653f 5401
2c07245f 5402 /* FDI link */
8febb297
EA		 5403 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5404 lane = 0;
5405 /* CPU eDP doesn't require FDI link, so just set DP M/N
5406 according to current link config */
e3aef172 5407 if (is_cpu_edp) {
e3aef172 5408 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5409 } else {
8febb297
EA		 5410 /* FDI is a binary signal running at ~2.7GHz, encoding
5411 * each output octet as 10 bits. The actual frequency
5412 * is stored as a divider into a 100MHz clock, and the
5413 * mode pixel clock is stored in units of 1KHz.
5414 * Hence the bw of each lane in terms of the mode signal
5415 * is:
5416 */
5417 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5418 }
58a27471 5419
94bf2ced
DV		 5420 /* [e]DP over FDI requires target mode clock instead of link clock. */
5421 if (edp_encoder)
5422 target_clock = intel_edp_target_clock(edp_encoder, mode);
5423 else if (is_dp)
5424 target_clock = mode->clock;
5425 else
5426 target_clock = adjusted_mode->clock;
5427
d4b1931c
PZ		 5428 if (!lane)
5429 lane = ironlake_get_lanes_required(target_clock, link_bw,
5430 intel_crtc->bpp);
2c07245f 5431
8febb297
EA		 5432 intel_crtc->fdi_lanes = lane;
5433
5434 if (pixel_multiplier > 1)
5435 link_bw *= pixel_multiplier;
e69d0bc1 5436 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5437
afe2fcf5
PZ		 5438 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5439 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5440 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5441 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5442}
5443
de13a2e3
PZ		 5444static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5445 struct drm_display_mode *adjusted_mode,
5446 intel_clock_t *clock, u32 fp)
79e53945 5447{
de13a2e3 5448 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5451 struct intel_encoder *intel_encoder;
5452 uint32_t dpll;
5453 int factor, pixel_multiplier, num_connectors = 0;
5454 bool is_lvds = false, is_sdvo = false, is_tv = false;
5455 bool is_dp = false, is_cpu_edp = false;
79e53945 5456
de13a2e3
PZ		 5457 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5458 switch (intel_encoder->type) {
79e53945
JB		 5459 case INTEL_OUTPUT_LVDS:
5460 is_lvds = true;
5461 break;
5462 case INTEL_OUTPUT_SDVO:
7d57382e 5463 case INTEL_OUTPUT_HDMI:
79e53945 5464 is_sdvo = true;
de13a2e3 5465 if (intel_encoder->needs_tv_clock)
e2f0ba97 5466 is_tv = true;
79e53945 5467 break;
79e53945
JB		 5468 case INTEL_OUTPUT_TVOUT:
5469 is_tv = true;
5470 break;
a4fc5ed6
KP		 5471 case INTEL_OUTPUT_DISPLAYPORT:
5472 is_dp = true;
5473 break;
32f9d658 5474 case INTEL_OUTPUT_EDP:
e3aef172 5475 is_dp = true;
de13a2e3 5476 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5477 is_cpu_edp = true;
32f9d658 5478 break;
79e53945 5479 }
43565a06 5480
c751ce4f 5481 num_connectors++;
79e53945 5482 }
79e53945 5483
c1858123 5484 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5485 factor = 21;
5486 if (is_lvds) {
5487 if ((intel_panel_use_ssc(dev_priv) &&
5488 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5489 intel_is_dual_link_lvds(dev))
8febb297
EA		 5490 factor = 25;
5491 } else if (is_sdvo && is_tv)
5492 factor = 20;
c1858123 5493
de13a2e3 5494 if (clock->m < factor * clock->n)
8febb297 5495 fp |= FP_CB_TUNE;
2c07245f 5496
5eddb70b 5497 dpll = 0;
2c07245f 5498
a07d6787
EA		 5499 if (is_lvds)
5500 dpll |= DPLLB_MODE_LVDS;
5501 else
5502 dpll |= DPLLB_MODE_DAC_SERIAL;
5503 if (is_sdvo) {
de13a2e3 5504 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5505 if (pixel_multiplier > 1) {
5506 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5507 }
a07d6787
EA		 5508 dpll |= DPLL_DVO_HIGH_SPEED;
5509 }
e3aef172 5510 if (is_dp && !is_cpu_edp)
a07d6787 5511 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5512
a07d6787 5513 /* compute bitmask from p1 value */
de13a2e3 5514 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5515 /* also FPA1 */
de13a2e3 5516 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5517
de13a2e3 5518 switch (clock->p2) {
a07d6787
EA		 5519 case 5:
5520 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5521 break;
5522 case 7:
5523 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5524 break;
5525 case 10:
5526 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5527 break;
5528 case 14:
5529 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5530 break;
79e53945
JB		 5531 }
5532
43565a06
KH		 5533 if (is_sdvo && is_tv)
5534 dpll |= PLL_REF_INPUT_TVCLKINBC;
5535 else if (is_tv)
79e53945 5536 /* XXX: just matching BIOS for now */
43565a06 5537 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5538 dpll |= 3;
a7615030 5539 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5540 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5541 else
5542 dpll |= PLL_REF_INPUT_DREFCLK;
5543
de13a2e3
PZ		 5544 return dpll;
5545}
5546
5547static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5548 struct drm_display_mode *mode,
5549 struct drm_display_mode *adjusted_mode,
5550 int x, int y,
5551 struct drm_framebuffer *fb)
5552{
5553 struct drm_device *dev = crtc->dev;
5554 struct drm_i915_private *dev_priv = dev->dev_private;
5555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5556 int pipe = intel_crtc->pipe;
5557 int plane = intel_crtc->plane;
5558 int num_connectors = 0;
5559 intel_clock_t clock, reduced_clock;
5560 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5561 bool ok, has_reduced_clock = false;
5562 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5563 struct intel_encoder *encoder;
de13a2e3 5564 int ret;
01a415fd 5565 bool dither, fdi_config_ok;
de13a2e3
PZ		 5566
5567 for_each_encoder_on_crtc(dev, crtc, encoder) {
5568 switch (encoder->type) {
5569 case INTEL_OUTPUT_LVDS:
5570 is_lvds = true;
5571 break;
de13a2e3
PZ		 5572 case INTEL_OUTPUT_DISPLAYPORT:
5573 is_dp = true;
5574 break;
5575 case INTEL_OUTPUT_EDP:
5576 is_dp = true;
e2f12b07 5577 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5578 is_cpu_edp = true;
5579 break;
5580 }
5581
5582 num_connectors++;
a07d6787 5583 }
79e53945 5584
5dc5298b
PZ		 5585 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5586 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5587
de13a2e3
PZ		 5588 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5589 &has_reduced_clock, &reduced_clock);
5590 if (!ok) {
5591 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5592 return -EINVAL;
79e53945
JB		 5593 }
5594
de13a2e3
PZ		 5595 /* Ensure that the cursor is valid for the new mode before changing... */
5596 intel_crtc_update_cursor(crtc, true);
5597
5598 /* determine panel color depth */
c8241969
JN		 5599 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5600 adjusted_mode);
de13a2e3
PZ		 5601 if (is_lvds && dev_priv->lvds_dither)
5602 dither = true;
5603
5604 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5605 if (has_reduced_clock)
5606 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5607 reduced_clock.m2;
5608
5609 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5610
f7cb34d4 5611 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5612 drm_mode_debug_printmodeline(mode);
5613
5dc5298b
PZ		 5614 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5615 if (!is_cpu_edp) {
ee7b9f93 5616 struct intel_pch_pll *pll;
4b645f14 5617
ee7b9f93
JB		 5618 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5619 if (pll == NULL) {
5620 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5621 pipe);
4b645f14
JB		 5622 return -EINVAL;
5623 }
ee7b9f93
JB		 5624 } else
5625 intel_put_pch_pll(intel_crtc);
79e53945 5626
2f0c2ad1 5627 if (is_dp && !is_cpu_edp)
a4fc5ed6 5628 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5629
dafd226c
DV		 5630 for_each_encoder_on_crtc(dev, crtc, encoder)
5631 if (encoder->pre_pll_enable)
5632 encoder->pre_pll_enable(encoder);
79e53945 5633
ee7b9f93
JB		 5634 if (intel_crtc->pch_pll) {
5635 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5636
32f9d658 5637 /* Wait for the clocks to stabilize. */
ee7b9f93 5638 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5639 udelay(150);
5640
8febb297
EA		 5641 /* The pixel multiplier can only be updated once the
5642 * DPLL is enabled and the clocks are stable.
5643 *
5644 * So write it again.
5645 */
ee7b9f93 5646 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5647 }
79e53945 5648
5eddb70b 5649 intel_crtc->lowfreq_avail = false;
ee7b9f93 5650 if (intel_crtc->pch_pll) {
4b645f14 5651 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5652 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5653 intel_crtc->lowfreq_avail = true;
4b645f14 5654 } else {
ee7b9f93 5655 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5656 }
5657 }
5658
b0e77b9c 5659 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5660
01a415fd
DV		 5661 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5662 * ironlake_check_fdi_lanes. */
f48d8f23 5663 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5664
01a415fd 5665 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5666
c8203565 5667 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5668
9d0498a2 5669 intel_wait_for_vblank(dev, pipe);
79e53945 5670
a1f9e77e
PZ		 5671 /* Set up the display plane register */
5672 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5673 POSTING_READ(DSPCNTR(plane));
79e53945 5674
94352cf9 5675 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5676
5677 intel_update_watermarks(dev);
5678
1f8eeabf
ED		 5679 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5680
01a415fd 5681 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5682}
5683
d6dd9eb1
DV		 5684static void haswell_modeset_global_resources(struct drm_device *dev)
5685{
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 bool enable = false;
5688 struct intel_crtc *crtc;
5689 struct intel_encoder *encoder;
5690
5691 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5692 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5693 enable = true;
5694 /* XXX: Should check for edp transcoder here, but thanks to init
5695 * sequence that's not yet available. Just in case desktop eDP
5696 * on PORT D is possible on haswell, too. */
5697 }
5698
5699 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5700 base.head) {
5701 if (encoder->type != INTEL_OUTPUT_EDP &&
5702 encoder->connectors_active)
5703 enable = true;
5704 }
5705
5706 /* Even the eDP panel fitter is outside the always-on well. */
5707 if (dev_priv->pch_pf_size)
5708 enable = true;
5709
5710 intel_set_power_well(dev, enable);
5711}
5712
09b4ddf9
PZ		 5713static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5714 struct drm_display_mode *mode,
5715 struct drm_display_mode *adjusted_mode,
5716 int x, int y,
5717 struct drm_framebuffer *fb)
5718{
5719 struct drm_device *dev = crtc->dev;
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5722 int pipe = intel_crtc->pipe;
5723 int plane = intel_crtc->plane;
5724 int num_connectors = 0;
ed7ef439 5725 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5726 struct intel_encoder *encoder;
09b4ddf9
PZ		 5727 int ret;
5728 bool dither;
5729
5730 for_each_encoder_on_crtc(dev, crtc, encoder) {
5731 switch (encoder->type) {
09b4ddf9
PZ		 5732 case INTEL_OUTPUT_DISPLAYPORT:
5733 is_dp = true;
5734 break;
5735 case INTEL_OUTPUT_EDP:
5736 is_dp = true;
5737 if (!intel_encoder_is_pch_edp(&encoder->base))
5738 is_cpu_edp = true;
5739 break;
5740 }
5741
5742 num_connectors++;
5743 }
5744
5dc5298b
PZ		 5745 /* We are not sure yet this won't happen. */
5746 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5747 INTEL_PCH_TYPE(dev));
5748
5749 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5750 num_connectors, pipe_name(pipe));
5751
702e7a56 5752 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5753 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5754
5755 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5756
6441ab5f
PZ		 5757 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5758 return -EINVAL;
5759
09b4ddf9
PZ		 5760 /* Ensure that the cursor is valid for the new mode before changing... */
5761 intel_crtc_update_cursor(crtc, true);
5762
5763 /* determine panel color depth */
c8241969
JN		 5764 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5765 adjusted_mode);
09b4ddf9 5766
09b4ddf9
PZ		 5767 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5768 drm_mode_debug_printmodeline(mode);
5769
ed7ef439 5770 if (is_dp && !is_cpu_edp)
09b4ddf9 5771 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5772
5773 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5774
5775 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5776
1eb8dfec
PZ		 5777 if (!is_dp || is_cpu_edp)
5778 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5779
ee2b0b38 5780 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5781
86d3efce
VS		 5782 intel_set_pipe_csc(crtc, adjusted_mode);
5783
09b4ddf9 5784 /* Set up the display plane register */
86d3efce 5785 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5786 POSTING_READ(DSPCNTR(plane));
5787
5788 ret = intel_pipe_set_base(crtc, x, y, fb);
5789
5790 intel_update_watermarks(dev);
5791
5792 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5793
1f803ee5 5794 return ret;
79e53945
JB		 5795}
5796
f564048e
EA		 5797static int intel_crtc_mode_set(struct drm_crtc *crtc,
5798 struct drm_display_mode *mode,
5799 struct drm_display_mode *adjusted_mode,
5800 int x, int y,
94352cf9 5801 struct drm_framebuffer *fb)
f564048e
EA		 5802{
5803 struct drm_device *dev = crtc->dev;
5804 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5805 struct drm_encoder_helper_funcs *encoder_funcs;
5806 struct intel_encoder *encoder;
0b701d27
EA		 5807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5808 int pipe = intel_crtc->pipe;
f564048e
EA		 5809 int ret;
5810
cc464b2a
PZ		 5811 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5812 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5813 else
5814 intel_crtc->cpu_transcoder = pipe;
5815
0b701d27 5816 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5817
f564048e 5818 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5819 x, y, fb);
79e53945 5820 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5821
9256aa19
DV		 5822 if (ret != 0)
5823 return ret;
5824
5825 for_each_encoder_on_crtc(dev, crtc, encoder) {
5826 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5827 encoder->base.base.id,
5828 drm_get_encoder_name(&encoder->base),
5829 mode->base.id, mode->name);
5830 encoder_funcs = encoder->base.helper_private;
5831 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5832 }
5833
5834 return 0;
79e53945
JB		 5835}
5836
3a9627f4
WF		 5837static bool intel_eld_uptodate(struct drm_connector *connector,
5838 int reg_eldv, uint32_t bits_eldv,
5839 int reg_elda, uint32_t bits_elda,
5840 int reg_edid)
5841{
5842 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843 uint8_t *eld = connector->eld;
5844 uint32_t i;
5845
5846 i = I915_READ(reg_eldv);
5847 i &= bits_eldv;
5848
5849 if (!eld[0])
5850 return !i;
5851
5852 if (!i)
5853 return false;
5854
5855 i = I915_READ(reg_elda);
5856 i &= ~bits_elda;
5857 I915_WRITE(reg_elda, i);
5858
5859 for (i = 0; i < eld[2]; i++)
5860 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5861 return false;
5862
5863 return true;
5864}
5865
e0dac65e
WF		 5866static void g4x_write_eld(struct drm_connector *connector,
5867 struct drm_crtc *crtc)
5868{
5869 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5870 uint8_t *eld = connector->eld;
5871 uint32_t eldv;
5872 uint32_t len;
5873 uint32_t i;
5874
5875 i = I915_READ(G4X_AUD_VID_DID);
5876
5877 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5878 eldv = G4X_ELDV_DEVCL_DEVBLC;
5879 else
5880 eldv = G4X_ELDV_DEVCTG;
5881
3a9627f4
WF		 5882 if (intel_eld_uptodate(connector,
5883 G4X_AUD_CNTL_ST, eldv,
5884 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5885 G4X_HDMIW_HDMIEDID))
5886 return;
5887
e0dac65e
WF		 5888 i = I915_READ(G4X_AUD_CNTL_ST);
5889 i &= ~(eldv | G4X_ELD_ADDR);
5890 len = (i >> 9) & 0x1f; /* ELD buffer size */
5891 I915_WRITE(G4X_AUD_CNTL_ST, i);
5892
5893 if (!eld[0])
5894 return;
5895
5896 len = min_t(uint8_t, eld[2], len);
5897 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5898 for (i = 0; i < len; i++)
5899 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5900
5901 i = I915_READ(G4X_AUD_CNTL_ST);
5902 i |= eldv;
5903 I915_WRITE(G4X_AUD_CNTL_ST, i);
5904}
5905
83358c85
WX		 5906static void haswell_write_eld(struct drm_connector *connector,
5907 struct drm_crtc *crtc)
5908{
5909 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5910 uint8_t *eld = connector->eld;
5911 struct drm_device *dev = crtc->dev;
7b9f35a6 5912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5913 uint32_t eldv;
5914 uint32_t i;
5915 int len;
5916 int pipe = to_intel_crtc(crtc)->pipe;
5917 int tmp;
5918
5919 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5920 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5921 int aud_config = HSW_AUD_CFG(pipe);
5922 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5923
5924
5925 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5926
5927 /* Audio output enable */
5928 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5929 tmp = I915_READ(aud_cntrl_st2);
5930 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5931 I915_WRITE(aud_cntrl_st2, tmp);
5932
5933 /* Wait for 1 vertical blank */
5934 intel_wait_for_vblank(dev, pipe);
5935
5936 /* Set ELD valid state */
5937 tmp = I915_READ(aud_cntrl_st2);
5938 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5939 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5940 I915_WRITE(aud_cntrl_st2, tmp);
5941 tmp = I915_READ(aud_cntrl_st2);
5942 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5943
5944 /* Enable HDMI mode */
5945 tmp = I915_READ(aud_config);
5946 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5947 /* clear N_programing_enable and N_value_index */
5948 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5949 I915_WRITE(aud_config, tmp);
5950
5951 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5952
5953 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5954 intel_crtc->eld_vld = true;
83358c85
WX		 5955
5956 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5957 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5958 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5959 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5960 } else
5961 I915_WRITE(aud_config, 0);
5962
5963 if (intel_eld_uptodate(connector,
5964 aud_cntrl_st2, eldv,
5965 aud_cntl_st, IBX_ELD_ADDRESS,
5966 hdmiw_hdmiedid))
5967 return;
5968
5969 i = I915_READ(aud_cntrl_st2);
5970 i &= ~eldv;
5971 I915_WRITE(aud_cntrl_st2, i);
5972
5973 if (!eld[0])
5974 return;
5975
5976 i = I915_READ(aud_cntl_st);
5977 i &= ~IBX_ELD_ADDRESS;
5978 I915_WRITE(aud_cntl_st, i);
5979 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5980 DRM_DEBUG_DRIVER("port num:%d\n", i);
5981
5982 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5983 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5984 for (i = 0; i < len; i++)
5985 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5986
5987 i = I915_READ(aud_cntrl_st2);
5988 i |= eldv;
5989 I915_WRITE(aud_cntrl_st2, i);
5990
5991}
5992
e0dac65e
WF		 5993static void ironlake_write_eld(struct drm_connector *connector,
5994 struct drm_crtc *crtc)
5995{
5996 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5997 uint8_t *eld = connector->eld;
5998 uint32_t eldv;
5999 uint32_t i;
6000 int len;
6001 int hdmiw_hdmiedid;
b6daa025 6002 int aud_config;
e0dac65e
WF		 6003 int aud_cntl_st;
6004 int aud_cntrl_st2;
9b138a83 6005 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6006
b3f33cbf 6007 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6008 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6009 aud_config = IBX_AUD_CFG(pipe);
6010 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6011 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6012 } else {
9b138a83
WX		 6013 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6014 aud_config = CPT_AUD_CFG(pipe);
6015 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6016 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6017 }
6018
9b138a83 6019 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6020
6021 i = I915_READ(aud_cntl_st);
9b138a83 6022 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6023 if (!i) {
6024 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6025 /* operate blindly on all ports */
1202b4c6
WF		 6026 eldv = IBX_ELD_VALIDB;
6027 eldv |= IBX_ELD_VALIDB << 4;
6028 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6029 } else {
6030 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6031 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6032 }
6033
3a9627f4
WF		 6034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6035 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6036 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6037 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6038 } else
6039 I915_WRITE(aud_config, 0);
e0dac65e 6040
3a9627f4
WF		 6041 if (intel_eld_uptodate(connector,
6042 aud_cntrl_st2, eldv,
6043 aud_cntl_st, IBX_ELD_ADDRESS,
6044 hdmiw_hdmiedid))
6045 return;
6046
e0dac65e
WF		 6047 i = I915_READ(aud_cntrl_st2);
6048 i &= ~eldv;
6049 I915_WRITE(aud_cntrl_st2, i);
6050
6051 if (!eld[0])
6052 return;
6053
e0dac65e 6054 i = I915_READ(aud_cntl_st);
1202b4c6 6055 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6056 I915_WRITE(aud_cntl_st, i);
6057
6058 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6059 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6060 for (i = 0; i < len; i++)
6061 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6062
6063 i = I915_READ(aud_cntrl_st2);
6064 i |= eldv;
6065 I915_WRITE(aud_cntrl_st2, i);
6066}
6067
6068void intel_write_eld(struct drm_encoder *encoder,
6069 struct drm_display_mode *mode)
6070{
6071 struct drm_crtc *crtc = encoder->crtc;
6072 struct drm_connector *connector;
6073 struct drm_device *dev = encoder->dev;
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075
6076 connector = drm_select_eld(encoder, mode);
6077 if (!connector)
6078 return;
6079
6080 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6081 connector->base.id,
6082 drm_get_connector_name(connector),
6083 connector->encoder->base.id,
6084 drm_get_encoder_name(connector->encoder));
6085
6086 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6087
6088 if (dev_priv->display.write_eld)
6089 dev_priv->display.write_eld(connector, crtc);
6090}
6091
79e53945
JB		 6092/** Loads the palette/gamma unit for the CRTC with the prepared values */
6093void intel_crtc_load_lut(struct drm_crtc *crtc)
6094{
6095 struct drm_device *dev = crtc->dev;
6096 struct drm_i915_private *dev_priv = dev->dev_private;
6097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6098 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6099 int i;
6100
6101 /* The clocks have to be on to load the palette. */
aed3f09d 6102 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6103 return;
6104
f2b115e6 6105 /* use legacy palette for Ironlake */
bad720ff 6106 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6107 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6108
79e53945
JB		 6109 for (i = 0; i < 256; i++) {
6110 I915_WRITE(palreg + 4 * i,
6111 (intel_crtc->lut_r[i] << 16) |
6112 (intel_crtc->lut_g[i] << 8) |
6113 intel_crtc->lut_b[i]);
6114 }
6115}
6116
560b85bb
CW		 6117static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6118{
6119 struct drm_device *dev = crtc->dev;
6120 struct drm_i915_private *dev_priv = dev->dev_private;
6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122 bool visible = base != 0;
6123 u32 cntl;
6124
6125 if (intel_crtc->cursor_visible == visible)
6126 return;
6127
9db4a9c7 6128 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6129 if (visible) {
6130 /* On these chipsets we can only modify the base whilst
6131 * the cursor is disabled.
6132 */
9db4a9c7 6133 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6134
6135 cntl &= ~(CURSOR_FORMAT_MASK);
6136 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6137 cntl |= CURSOR_ENABLE |
6138 CURSOR_GAMMA_ENABLE |
6139 CURSOR_FORMAT_ARGB;
6140 } else
6141 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6142 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6143
6144 intel_crtc->cursor_visible = visible;
6145}
6146
6147static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6148{
6149 struct drm_device *dev = crtc->dev;
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 int pipe = intel_crtc->pipe;
6153 bool visible = base != 0;
6154
6155 if (intel_crtc->cursor_visible != visible) {
548f245b 6156 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6157 if (base) {
6158 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6159 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6160 cntl |= pipe << 28; /* Connect to correct pipe */
6161 } else {
6162 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6163 cntl |= CURSOR_MODE_DISABLE;
6164 }
9db4a9c7 6165 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6166
6167 intel_crtc->cursor_visible = visible;
6168 }
6169 /* and commit changes on next vblank */
9db4a9c7 6170 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6171}
6172
65a21cd6
JB		 6173static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6174{
6175 struct drm_device *dev = crtc->dev;
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178 int pipe = intel_crtc->pipe;
6179 bool visible = base != 0;
6180
6181 if (intel_crtc->cursor_visible != visible) {
6182 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6183 if (base) {
6184 cntl &= ~CURSOR_MODE;
6185 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6186 } else {
6187 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6188 cntl |= CURSOR_MODE_DISABLE;
6189 }
86d3efce
VS		 6190 if (IS_HASWELL(dev))
6191 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6192 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6193
6194 intel_crtc->cursor_visible = visible;
6195 }
6196 /* and commit changes on next vblank */
6197 I915_WRITE(CURBASE_IVB(pipe), base);
6198}
6199
cda4b7d3 6200/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6201static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6202 bool on)
cda4b7d3
CW		 6203{
6204 struct drm_device *dev = crtc->dev;
6205 struct drm_i915_private *dev_priv = dev->dev_private;
6206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207 int pipe = intel_crtc->pipe;
6208 int x = intel_crtc->cursor_x;
6209 int y = intel_crtc->cursor_y;
560b85bb 6210 u32 base, pos;
cda4b7d3
CW		 6211 bool visible;
6212
6213 pos = 0;
6214
6b383a7f 6215 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6216 base = intel_crtc->cursor_addr;
6217 if (x > (int) crtc->fb->width)
6218 base = 0;
6219
6220 if (y > (int) crtc->fb->height)
6221 base = 0;
6222 } else
6223 base = 0;
6224
6225 if (x < 0) {
6226 if (x + intel_crtc->cursor_width < 0)
6227 base = 0;
6228
6229 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6230 x = -x;
6231 }
6232 pos |= x << CURSOR_X_SHIFT;
6233
6234 if (y < 0) {
6235 if (y + intel_crtc->cursor_height < 0)
6236 base = 0;
6237
6238 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6239 y = -y;
6240 }
6241 pos |= y << CURSOR_Y_SHIFT;
6242
6243 visible = base != 0;
560b85bb 6244 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6245 return;
6246
0cd83aa9 6247 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6248 I915_WRITE(CURPOS_IVB(pipe), pos);
6249 ivb_update_cursor(crtc, base);
6250 } else {
6251 I915_WRITE(CURPOS(pipe), pos);
6252 if (IS_845G(dev) || IS_I865G(dev))
6253 i845_update_cursor(crtc, base);
6254 else
6255 i9xx_update_cursor(crtc, base);
6256 }
cda4b7d3
CW		 6257}
6258
79e53945 6259static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6260 struct drm_file *file,
79e53945
JB		 6261 uint32_t handle,
6262 uint32_t width, uint32_t height)
6263{
6264 struct drm_device *dev = crtc->dev;
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6267 struct drm_i915_gem_object *obj;
cda4b7d3 6268 uint32_t addr;
3f8bc370 6269 int ret;
79e53945 6270
79e53945
JB		 6271 /* if we want to turn off the cursor ignore width and height */
6272 if (!handle) {
28c97730 6273 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6274 addr = 0;
05394f39 6275 obj = NULL;
5004417d 6276 mutex_lock(&dev->struct_mutex);
3f8bc370 6277 goto finish;
79e53945
JB		 6278 }
6279
6280 /* Currently we only support 64x64 cursors */
6281 if (width != 64 || height != 64) {
6282 DRM_ERROR("we currently only support 64x64 cursors\n");
6283 return -EINVAL;
6284 }
6285
05394f39 6286 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6287 if (&obj->base == NULL)
79e53945
JB		 6288 return -ENOENT;
6289
05394f39 6290 if (obj->base.size < width * height * 4) {
79e53945 6291 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6292 ret = -ENOMEM;
6293 goto fail;
79e53945
JB		 6294 }
6295
71acb5eb 6296 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6297 mutex_lock(&dev->struct_mutex);
b295d1b6 6298 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6299 if (obj->tiling_mode) {
6300 DRM_ERROR("cursor cannot be tiled\n");
6301 ret = -EINVAL;
6302 goto fail_locked;
6303 }
6304
2da3b9b9 6305 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6306 if (ret) {
6307 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6308 goto fail_locked;
e7b526bb
CW		 6309 }
6310
d9e86c0e
CW		 6311 ret = i915_gem_object_put_fence(obj);
6312 if (ret) {
2da3b9b9 6313 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6314 goto fail_unpin;
6315 }
6316
05394f39 6317 addr = obj->gtt_offset;
71acb5eb 6318 } else {
6eeefaf3 6319 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6320 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6321 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6322 align);
71acb5eb
DA		 6323 if (ret) {
6324 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6325 goto fail_locked;
71acb5eb 6326 }
05394f39 6327 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6328 }
6329
a6c45cf0 6330 if (IS_GEN2(dev))
14b60391
JB		 6331 I915_WRITE(CURSIZE, (height << 12) | width);
6332
3f8bc370 6333 finish:
3f8bc370 6334 if (intel_crtc->cursor_bo) {
b295d1b6 6335 if (dev_priv->info->cursor_needs_physical) {
05394f39 6336 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6337 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6338 } else
6339 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6340 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6341 }
80824003 6342
7f9872e0 6343 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6344
6345 intel_crtc->cursor_addr = addr;
05394f39 6346 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6347 intel_crtc->cursor_width = width;
6348 intel_crtc->cursor_height = height;
6349
6b383a7f 6350 intel_crtc_update_cursor(crtc, true);
3f8bc370 6351
79e53945 6352 return 0;
e7b526bb 6353fail_unpin:
05394f39 6354 i915_gem_object_unpin(obj);
7f9872e0 6355fail_locked:
34b8686e 6356 mutex_unlock(&dev->struct_mutex);
bc9025bd 6357fail:
05394f39 6358 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6359 return ret;
79e53945
JB		 6360}
6361
6362static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6363{
79e53945 6364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6365
cda4b7d3
CW		 6366 intel_crtc->cursor_x = x;
6367 intel_crtc->cursor_y = y;
652c393a 6368
6b383a7f 6369 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6370
6371 return 0;
6372}
6373
6374/** Sets the color ramps on behalf of RandR */
6375void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6376 u16 blue, int regno)
6377{
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379
6380 intel_crtc->lut_r[regno] = red >> 8;
6381 intel_crtc->lut_g[regno] = green >> 8;
6382 intel_crtc->lut_b[regno] = blue >> 8;
6383}
6384
b8c00ac5
DA		 6385void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6386 u16 *blue, int regno)
6387{
6388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389
6390 *red = intel_crtc->lut_r[regno] << 8;
6391 *green = intel_crtc->lut_g[regno] << 8;
6392 *blue = intel_crtc->lut_b[regno] << 8;
6393}
6394
79e53945 6395static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6396 u16 *blue, uint32_t start, uint32_t size)
79e53945 6397{
7203425a 6398 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6400
7203425a 6401 for (i = start; i < end; i++) {
79e53945
JB		 6402 intel_crtc->lut_r[i] = red[i] >> 8;
6403 intel_crtc->lut_g[i] = green[i] >> 8;
6404 intel_crtc->lut_b[i] = blue[i] >> 8;
6405 }
6406
6407 intel_crtc_load_lut(crtc);
6408}
6409
6410/**
6411 * Get a pipe with a simple mode set on it for doing load-based monitor
6412 * detection.
6413 *
6414 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6415 * its requirements. The pipe will be connected to no other encoders.
79e53945 6416 *
c751ce4f 6417 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6418 * configured for it. In the future, it could choose to temporarily disable
6419 * some outputs to free up a pipe for its use.
6420 *
6421 * \return crtc, or NULL if no pipes are available.
6422 */
6423
6424/* VESA 640x480x72Hz mode to set on the pipe */
6425static struct drm_display_mode load_detect_mode = {
6426 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6427 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6428};
6429
d2dff872
CW		 6430static struct drm_framebuffer *
6431intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6432 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6433 struct drm_i915_gem_object *obj)
6434{
6435 struct intel_framebuffer *intel_fb;
6436 int ret;
6437
6438 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6439 if (!intel_fb) {
6440 drm_gem_object_unreference_unlocked(&obj->base);
6441 return ERR_PTR(-ENOMEM);
6442 }
6443
6444 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6445 if (ret) {
6446 drm_gem_object_unreference_unlocked(&obj->base);
6447 kfree(intel_fb);
6448 return ERR_PTR(ret);
6449 }
6450
6451 return &intel_fb->base;
6452}
6453
6454static u32
6455intel_framebuffer_pitch_for_width(int width, int bpp)
6456{
6457 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6458 return ALIGN(pitch, 64);
6459}
6460
6461static u32
6462intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6463{
6464 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6465 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6466}
6467
6468static struct drm_framebuffer *
6469intel_framebuffer_create_for_mode(struct drm_device *dev,
6470 struct drm_display_mode *mode,
6471 int depth, int bpp)
6472{
6473 struct drm_i915_gem_object *obj;
0fed39bd 6474 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6475
6476 obj = i915_gem_alloc_object(dev,
6477 intel_framebuffer_size_for_mode(mode, bpp));
6478 if (obj == NULL)
6479 return ERR_PTR(-ENOMEM);
6480
6481 mode_cmd.width = mode->hdisplay;
6482 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6483 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6484 bpp);
5ca0c34a 6485 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6486
6487 return intel_framebuffer_create(dev, &mode_cmd, obj);
6488}
6489
6490static struct drm_framebuffer *
6491mode_fits_in_fbdev(struct drm_device *dev,
6492 struct drm_display_mode *mode)
6493{
6494 struct drm_i915_private *dev_priv = dev->dev_private;
6495 struct drm_i915_gem_object *obj;
6496 struct drm_framebuffer *fb;
6497
6498 if (dev_priv->fbdev == NULL)
6499 return NULL;
6500
6501 obj = dev_priv->fbdev->ifb.obj;
6502 if (obj == NULL)
6503 return NULL;
6504
6505 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6506 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6507 fb->bits_per_pixel))
d2dff872
CW		 6508 return NULL;
6509
01f2c773 6510 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6511 return NULL;
6512
6513 return fb;
6514}
6515
d2434ab7 6516bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6517 struct drm_display_mode *mode,
8261b191 6518 struct intel_load_detect_pipe *old)
79e53945
JB		 6519{
6520 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6521 struct intel_encoder *intel_encoder =
6522 intel_attached_encoder(connector);
79e53945 6523 struct drm_crtc *possible_crtc;
4ef69c7a 6524 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6525 struct drm_crtc *crtc = NULL;
6526 struct drm_device *dev = encoder->dev;
94352cf9 6527 struct drm_framebuffer *fb;
79e53945
JB		 6528 int i = -1;
6529
d2dff872
CW		 6530 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6531 connector->base.id, drm_get_connector_name(connector),
6532 encoder->base.id, drm_get_encoder_name(encoder));
6533
79e53945
JB		 6534 /*
6535 * Algorithm gets a little messy:
7a5e4805 6536 *
79e53945
JB		 6537 * - if the connector already has an assigned crtc, use it (but make
6538 * sure it's on first)
7a5e4805 6539 *
79e53945
JB		 6540 * - try to find the first unused crtc that can drive this connector,
6541 * and use that if we find one
79e53945
JB		 6542 */
6543
6544 /* See if we already have a CRTC for this connector */
6545 if (encoder->crtc) {
6546 crtc = encoder->crtc;
8261b191 6547
7b24056b
DV		 6548 mutex_lock(&crtc->mutex);
6549
24218aac 6550 old->dpms_mode = connector->dpms;
8261b191
CW		 6551 old->load_detect_temp = false;
6552
6553 /* Make sure the crtc and connector are running */
24218aac
DV		 6554 if (connector->dpms != DRM_MODE_DPMS_ON)
6555 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6556
7173188d 6557 return true;
79e53945
JB		 6558 }
6559
6560 /* Find an unused one (if possible) */
6561 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6562 i++;
6563 if (!(encoder->possible_crtcs & (1 << i)))
6564 continue;
6565 if (!possible_crtc->enabled) {
6566 crtc = possible_crtc;
6567 break;
6568 }
79e53945
JB		 6569 }
6570
6571 /*
6572 * If we didn't find an unused CRTC, don't use any.
6573 */
6574 if (!crtc) {
7173188d
CW		 6575 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6576 return false;
79e53945
JB		 6577 }
6578
7b24056b 6579 mutex_lock(&crtc->mutex);
fc303101
DV		 6580 intel_encoder->new_crtc = to_intel_crtc(crtc);
6581 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6582
6583 intel_crtc = to_intel_crtc(crtc);
24218aac 6584 old->dpms_mode = connector->dpms;
8261b191 6585 old->load_detect_temp = true;
d2dff872 6586 old->release_fb = NULL;
79e53945 6587
6492711d
CW		 6588 if (!mode)
6589 mode = &load_detect_mode;
79e53945 6590
d2dff872
CW		 6591 /* We need a framebuffer large enough to accommodate all accesses
6592 * that the plane may generate whilst we perform load detection.
6593 * We can not rely on the fbcon either being present (we get called
6594 * during its initialisation to detect all boot displays, or it may
6595 * not even exist) or that it is large enough to satisfy the
6596 * requested mode.
6597 */
94352cf9
DV		 6598 fb = mode_fits_in_fbdev(dev, mode);
6599 if (fb == NULL) {
d2dff872 6600 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6601 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6602 old->release_fb = fb;
d2dff872
CW		 6603 } else
6604 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6605 if (IS_ERR(fb)) {
d2dff872 6606 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6607 mutex_unlock(&crtc->mutex);
0e8b3d3e 6608 return false;
79e53945 6609 }
79e53945 6610
c0c36b94 6611 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6612 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6613 if (old->release_fb)
6614 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6615 mutex_unlock(&crtc->mutex);
0e8b3d3e 6616 return false;
79e53945 6617 }
7173188d 6618
79e53945 6619 /* let the connector get through one full cycle before testing */
9d0498a2 6620 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6621 return true;
79e53945
JB		 6622}
6623
d2434ab7 6624void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6625 struct intel_load_detect_pipe *old)
79e53945 6626{
d2434ab7
DV		 6627 struct intel_encoder *intel_encoder =
6628 intel_attached_encoder(connector);
4ef69c7a 6629 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6630 struct drm_crtc *crtc = encoder->crtc;
79e53945 6631
d2dff872
CW		 6632 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6633 connector->base.id, drm_get_connector_name(connector),
6634 encoder->base.id, drm_get_encoder_name(encoder));
6635
8261b191 6636 if (old->load_detect_temp) {
fc303101
DV		 6637 to_intel_connector(connector)->new_encoder = NULL;
6638 intel_encoder->new_crtc = NULL;
6639 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6640
36206361
DV		 6641 if (old->release_fb) {
6642 drm_framebuffer_unregister_private(old->release_fb);
6643 drm_framebuffer_unreference(old->release_fb);
6644 }
d2dff872 6645
67c96400 6646 mutex_unlock(&crtc->mutex);
0622a53c 6647 return;
79e53945
JB		 6648 }
6649
c751ce4f 6650 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6651 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6652 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6653
6654 mutex_unlock(&crtc->mutex);
79e53945
JB		 6655}
6656
6657/* Returns the clock of the currently programmed mode of the given pipe. */
6658static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6659{
6660 struct drm_i915_private *dev_priv = dev->dev_private;
6661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6662 int pipe = intel_crtc->pipe;
548f245b 6663 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6664 u32 fp;
6665 intel_clock_t clock;
6666
6667 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6668 fp = I915_READ(FP0(pipe));
79e53945 6669 else
39adb7a5 6670 fp = I915_READ(FP1(pipe));
79e53945
JB		 6671
6672 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6673 if (IS_PINEVIEW(dev)) {
6674 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6675 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6676 } else {
6677 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6678 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6679 }
6680
a6c45cf0 6681 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6682 if (IS_PINEVIEW(dev))
6683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6684 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6685 else
6686 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6687 DPLL_FPA01_P1_POST_DIV_SHIFT);
6688
6689 switch (dpll & DPLL_MODE_MASK) {
6690 case DPLLB_MODE_DAC_SERIAL:
6691 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6692 5 : 10;
6693 break;
6694 case DPLLB_MODE_LVDS:
6695 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6696 7 : 14;
6697 break;
6698 default:
28c97730 6699 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6700 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6701 return 0;
6702 }
6703
6704 /* XXX: Handle the 100Mhz refclk */
2177832f 6705 intel_clock(dev, 96000, &clock);
79e53945
JB		 6706 } else {
6707 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6708
6709 if (is_lvds) {
6710 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6711 DPLL_FPA01_P1_POST_DIV_SHIFT);
6712 clock.p2 = 14;
6713
6714 if ((dpll & PLL_REF_INPUT_MASK) ==
6715 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6716 /* XXX: might not be 66MHz */
2177832f 6717 intel_clock(dev, 66000, &clock);
79e53945 6718 } else
2177832f 6719 intel_clock(dev, 48000, &clock);
79e53945
JB		 6720 } else {
6721 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6722 clock.p1 = 2;
6723 else {
6724 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6725 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6726 }
6727 if (dpll & PLL_P2_DIVIDE_BY_4)
6728 clock.p2 = 4;
6729 else
6730 clock.p2 = 2;
6731
2177832f 6732 intel_clock(dev, 48000, &clock);
79e53945
JB		 6733 }
6734 }
6735
6736 /* XXX: It would be nice to validate the clocks, but we can't reuse
6737 * i830PllIsValid() because it relies on the xf86_config connector
6738 * configuration being accurate, which it isn't necessarily.
6739 */
6740
6741 return clock.dot;
6742}
6743
6744/** Returns the currently programmed mode of the given pipe. */
6745struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6746 struct drm_crtc *crtc)
6747{
548f245b 6748 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6750 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6751 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6752 int htot = I915_READ(HTOTAL(cpu_transcoder));
6753 int hsync = I915_READ(HSYNC(cpu_transcoder));
6754 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6755 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6756
6757 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6758 if (!mode)
6759 return NULL;
6760
6761 mode->clock = intel_crtc_clock_get(dev, crtc);
6762 mode->hdisplay = (htot & 0xffff) + 1;
6763 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6764 mode->hsync_start = (hsync & 0xffff) + 1;
6765 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6766 mode->vdisplay = (vtot & 0xffff) + 1;
6767 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6768 mode->vsync_start = (vsync & 0xffff) + 1;
6769 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6770
6771 drm_mode_set_name(mode);
79e53945
JB		 6772
6773 return mode;
6774}
6775
3dec0095 6776static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6777{
6778 struct drm_device *dev = crtc->dev;
6779 drm_i915_private_t *dev_priv = dev->dev_private;
6780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6781 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6782 int dpll_reg = DPLL(pipe);
6783 int dpll;
652c393a 6784
bad720ff 6785 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6786 return;
6787
6788 if (!dev_priv->lvds_downclock_avail)
6789 return;
6790
dbdc6479 6791 dpll = I915_READ(dpll_reg);
652c393a 6792 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6793 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6794
8ac5a6d5 6795 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6796
6797 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6798 I915_WRITE(dpll_reg, dpll);
9d0498a2 6799 intel_wait_for_vblank(dev, pipe);
dbdc6479 6800
652c393a
JB		 6801 dpll = I915_READ(dpll_reg);
6802 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6803 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6804 }
652c393a
JB		 6805}
6806
6807static void intel_decrease_pllclock(struct drm_crtc *crtc)
6808{
6809 struct drm_device *dev = crtc->dev;
6810 drm_i915_private_t *dev_priv = dev->dev_private;
6811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6812
bad720ff 6813 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6814 return;
6815
6816 if (!dev_priv->lvds_downclock_avail)
6817 return;
6818
6819 /*
6820 * Since this is called by a timer, we should never get here in
6821 * the manual case.
6822 */
6823 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6824 int pipe = intel_crtc->pipe;
6825 int dpll_reg = DPLL(pipe);
6826 int dpll;
f6e5b160 6827
44d98a61 6828 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6829
8ac5a6d5 6830 assert_panel_unlocked(dev_priv, pipe);
652c393a 6831
dc257cf1 6832 dpll = I915_READ(dpll_reg);
652c393a
JB		 6833 dpll |= DISPLAY_RATE_SELECT_FPA1;
6834 I915_WRITE(dpll_reg, dpll);
9d0498a2 6835 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6836 dpll = I915_READ(dpll_reg);
6837 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6838 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6839 }
6840
6841}
6842
f047e395
CW		 6843void intel_mark_busy(struct drm_device *dev)
6844{
f047e395
CW		 6845 i915_update_gfx_val(dev->dev_private);
6846}
6847
6848void intel_mark_idle(struct drm_device *dev)
652c393a 6849{
652c393a 6850 struct drm_crtc *crtc;
652c393a
JB		 6851
6852 if (!i915_powersave)
6853 return;
6854
652c393a 6855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6856 if (!crtc->fb)
6857 continue;
6858
725a5b54 6859 intel_decrease_pllclock(crtc);
652c393a 6860 }
652c393a
JB		 6861}
6862
725a5b54 6863void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6864{
f047e395
CW		 6865 struct drm_device *dev = obj->base.dev;
6866 struct drm_crtc *crtc;
652c393a 6867
f047e395 6868 if (!i915_powersave)
acb87dfb
CW		 6869 return;
6870
652c393a
JB		 6871 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6872 if (!crtc->fb)
6873 continue;
6874
f047e395 6875 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6876 intel_increase_pllclock(crtc);
652c393a
JB		 6877 }
6878}
6879
79e53945
JB		 6880static void intel_crtc_destroy(struct drm_crtc *crtc)
6881{
6882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6883 struct drm_device *dev = crtc->dev;
6884 struct intel_unpin_work *work;
6885 unsigned long flags;
6886
6887 spin_lock_irqsave(&dev->event_lock, flags);
6888 work = intel_crtc->unpin_work;
6889 intel_crtc->unpin_work = NULL;
6890 spin_unlock_irqrestore(&dev->event_lock, flags);
6891
6892 if (work) {
6893 cancel_work_sync(&work->work);
6894 kfree(work);
6895 }
79e53945
JB		 6896
6897 drm_crtc_cleanup(crtc);
67e77c5a 6898
79e53945
JB		 6899 kfree(intel_crtc);
6900}
6901
6b95a207
KH		 6902static void intel_unpin_work_fn(struct work_struct *__work)
6903{
6904 struct intel_unpin_work *work =
6905 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6906 struct drm_device *dev = work->crtc->dev;
6b95a207 6907
b4a98e57 6908 mutex_lock(&dev->struct_mutex);
1690e1eb 6909 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6910 drm_gem_object_unreference(&work->pending_flip_obj->base);
6911 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6912
b4a98e57
CW		 6913 intel_update_fbc(dev);
6914 mutex_unlock(&dev->struct_mutex);
6915
6916 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6917 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6918
6b95a207
KH		 6919 kfree(work);
6920}
6921
1afe3e9d 6922static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6923 struct drm_crtc *crtc)
6b95a207
KH		 6924{
6925 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6927 struct intel_unpin_work *work;
05394f39 6928 struct drm_i915_gem_object *obj;
6b95a207
KH		 6929 unsigned long flags;
6930
6931 /* Ignore early vblank irqs */
6932 if (intel_crtc == NULL)
6933 return;
6934
6935 spin_lock_irqsave(&dev->event_lock, flags);
6936 work = intel_crtc->unpin_work;
e7d841ca
CW		 6937
6938 /* Ensure we don't miss a work->pending update ... */
6939 smp_rmb();
6940
6941 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6942 spin_unlock_irqrestore(&dev->event_lock, flags);
6943 return;
6944 }
6945
e7d841ca
CW		 6946 /* and that the unpin work is consistent wrt ->pending. */
6947 smp_rmb();
6948
6b95a207 6949 intel_crtc->unpin_work = NULL;
6b95a207 6950
45a066eb
RC		 6951 if (work->event)
6952 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6953
0af7e4df
MK		 6954 drm_vblank_put(dev, intel_crtc->pipe);
6955
6b95a207
KH		 6956 spin_unlock_irqrestore(&dev->event_lock, flags);
6957
05394f39 6958 obj = work->old_fb_obj;
d9e86c0e 6959
2c10d571 6960 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6961
6962 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6963
6964 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6965}
6966
1afe3e9d
JB		 6967void intel_finish_page_flip(struct drm_device *dev, int pipe)
6968{
6969 drm_i915_private_t *dev_priv = dev->dev_private;
6970 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6971
49b14a5c 6972 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6973}
6974
6975void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6976{
6977 drm_i915_private_t *dev_priv = dev->dev_private;
6978 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6979
49b14a5c 6980 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6981}
6982
6b95a207
KH		 6983void intel_prepare_page_flip(struct drm_device *dev, int plane)
6984{
6985 drm_i915_private_t *dev_priv = dev->dev_private;
6986 struct intel_crtc *intel_crtc =
6987 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6988 unsigned long flags;
6989
e7d841ca
CW		 6990 /* NB: An MMIO update of the plane base pointer will also
6991 * generate a page-flip completion irq, i.e. every modeset
6992 * is also accompanied by a spurious intel_prepare_page_flip().
6993 */
6b95a207 6994 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6995 if (intel_crtc->unpin_work)
6996 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6997 spin_unlock_irqrestore(&dev->event_lock, flags);
6998}
6999
e7d841ca
CW		 7000inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7001{
7002 /* Ensure that the work item is consistent when activating it ... */
7003 smp_wmb();
7004 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7005 /* and that it is marked active as soon as the irq could fire. */
7006 smp_wmb();
7007}
7008
8c9f3aaf
JB		 7009static int intel_gen2_queue_flip(struct drm_device *dev,
7010 struct drm_crtc *crtc,
7011 struct drm_framebuffer *fb,
7012 struct drm_i915_gem_object *obj)
7013{
7014 struct drm_i915_private *dev_priv = dev->dev_private;
7015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7016 u32 flip_mask;
6d90c952 7017 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7018 int ret;
7019
6d90c952 7020 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7021 if (ret)
83d4092b 7022 goto err;
8c9f3aaf 7023
6d90c952 7024 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7025 if (ret)
83d4092b 7026 goto err_unpin;
8c9f3aaf
JB		 7027
7028 /* Can't queue multiple flips, so wait for the previous
7029 * one to finish before executing the next.
7030 */
7031 if (intel_crtc->plane)
7032 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7033 else
7034 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7035 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7036 intel_ring_emit(ring, MI_NOOP);
7037 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7039 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7040 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7041 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7042
7043 intel_mark_page_flip_active(intel_crtc);
6d90c952 7044 intel_ring_advance(ring);
83d4092b
CW		 7045 return 0;
7046
7047err_unpin:
7048 intel_unpin_fb_obj(obj);
7049err:
8c9f3aaf
JB		 7050 return ret;
7051}
7052
7053static int intel_gen3_queue_flip(struct drm_device *dev,
7054 struct drm_crtc *crtc,
7055 struct drm_framebuffer *fb,
7056 struct drm_i915_gem_object *obj)
7057{
7058 struct drm_i915_private *dev_priv = dev->dev_private;
7059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7060 u32 flip_mask;
6d90c952 7061 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7062 int ret;
7063
6d90c952 7064 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7065 if (ret)
83d4092b 7066 goto err;
8c9f3aaf 7067
6d90c952 7068 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7069 if (ret)
83d4092b 7070 goto err_unpin;
8c9f3aaf
JB		 7071
7072 if (intel_crtc->plane)
7073 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7074 else
7075 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7076 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7077 intel_ring_emit(ring, MI_NOOP);
7078 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7079 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7080 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7081 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7082 intel_ring_emit(ring, MI_NOOP);
7083
e7d841ca 7084 intel_mark_page_flip_active(intel_crtc);
6d90c952 7085 intel_ring_advance(ring);
83d4092b
CW		 7086 return 0;
7087
7088err_unpin:
7089 intel_unpin_fb_obj(obj);
7090err:
8c9f3aaf
JB		 7091 return ret;
7092}
7093
7094static int intel_gen4_queue_flip(struct drm_device *dev,
7095 struct drm_crtc *crtc,
7096 struct drm_framebuffer *fb,
7097 struct drm_i915_gem_object *obj)
7098{
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101 uint32_t pf, pipesrc;
6d90c952 7102 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7103 int ret;
7104
6d90c952 7105 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7106 if (ret)
83d4092b 7107 goto err;
8c9f3aaf 7108
6d90c952 7109 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7110 if (ret)
83d4092b 7111 goto err_unpin;
8c9f3aaf
JB		 7112
7113 /* i965+ uses the linear or tiled offsets from the
7114 * Display Registers (which do not change across a page-flip)
7115 * so we need only reprogram the base address.
7116 */
6d90c952
DV		 7117 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7118 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7119 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7120 intel_ring_emit(ring,
7121 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7122 obj->tiling_mode);
8c9f3aaf
JB		 7123
7124 /* XXX Enabling the panel-fitter across page-flip is so far
7125 * untested on non-native modes, so ignore it for now.
7126 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7127 */
7128 pf = 0;
7129 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7130 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7131
7132 intel_mark_page_flip_active(intel_crtc);
6d90c952 7133 intel_ring_advance(ring);
83d4092b
CW		 7134 return 0;
7135
7136err_unpin:
7137 intel_unpin_fb_obj(obj);
7138err:
8c9f3aaf
JB		 7139 return ret;
7140}
7141
7142static int intel_gen6_queue_flip(struct drm_device *dev,
7143 struct drm_crtc *crtc,
7144 struct drm_framebuffer *fb,
7145 struct drm_i915_gem_object *obj)
7146{
7147 struct drm_i915_private *dev_priv = dev->dev_private;
7148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7149 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7150 uint32_t pf, pipesrc;
7151 int ret;
7152
6d90c952 7153 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7154 if (ret)
83d4092b 7155 goto err;
8c9f3aaf 7156
6d90c952 7157 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7158 if (ret)
83d4092b 7159 goto err_unpin;
8c9f3aaf 7160
6d90c952
DV		 7161 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7162 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7163 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7164 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7165
dc257cf1
DV		 7166 /* Contrary to the suggestions in the documentation,
7167 * "Enable Panel Fitter" does not seem to be required when page
7168 * flipping with a non-native mode, and worse causes a normal
7169 * modeset to fail.
7170 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7171 */
7172 pf = 0;
8c9f3aaf 7173 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7174 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7175
7176 intel_mark_page_flip_active(intel_crtc);
6d90c952 7177 intel_ring_advance(ring);
83d4092b
CW		 7178 return 0;
7179
7180err_unpin:
7181 intel_unpin_fb_obj(obj);
7182err:
8c9f3aaf
JB		 7183 return ret;
7184}
7185
7c9017e5
JB		 7186/*
7187 * On gen7 we currently use the blit ring because (in early silicon at least)
7188 * the render ring doesn't give us interrpts for page flip completion, which
7189 * means clients will hang after the first flip is queued. Fortunately the
7190 * blit ring generates interrupts properly, so use it instead.
7191 */
7192static int intel_gen7_queue_flip(struct drm_device *dev,
7193 struct drm_crtc *crtc,
7194 struct drm_framebuffer *fb,
7195 struct drm_i915_gem_object *obj)
7196{
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7200 uint32_t plane_bit = 0;
7c9017e5
JB		 7201 int ret;
7202
7203 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7204 if (ret)
83d4092b 7205 goto err;
7c9017e5 7206
cb05d8de
DV		 7207 switch(intel_crtc->plane) {
7208 case PLANE_A:
7209 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7210 break;
7211 case PLANE_B:
7212 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7213 break;
7214 case PLANE_C:
7215 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7216 break;
7217 default:
7218 WARN_ONCE(1, "unknown plane in flip command\n");
7219 ret = -ENODEV;
ab3951eb 7220 goto err_unpin;
cb05d8de
DV		 7221 }
7222
7c9017e5
JB		 7223 ret = intel_ring_begin(ring, 4);
7224 if (ret)
83d4092b 7225 goto err_unpin;
7c9017e5 7226
cb05d8de 7227 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7228 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7229 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7230 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7231
7232 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7233 intel_ring_advance(ring);
83d4092b
CW		 7234 return 0;
7235
7236err_unpin:
7237 intel_unpin_fb_obj(obj);
7238err:
7c9017e5
JB		 7239 return ret;
7240}
7241
8c9f3aaf
JB		 7242static int intel_default_queue_flip(struct drm_device *dev,
7243 struct drm_crtc *crtc,
7244 struct drm_framebuffer *fb,
7245 struct drm_i915_gem_object *obj)
7246{
7247 return -ENODEV;
7248}
7249
6b95a207
KH		 7250static int intel_crtc_page_flip(struct drm_crtc *crtc,
7251 struct drm_framebuffer *fb,
7252 struct drm_pending_vblank_event *event)
7253{
7254 struct drm_device *dev = crtc->dev;
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256 struct intel_framebuffer *intel_fb;
05394f39 7257 struct drm_i915_gem_object *obj;
6b95a207
KH		 7258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7259 struct intel_unpin_work *work;
8c9f3aaf 7260 unsigned long flags;
52e68630 7261 int ret;
6b95a207 7262
e6a595d2
VS		 7263 /* Can't change pixel format via MI display flips. */
7264 if (fb->pixel_format != crtc->fb->pixel_format)
7265 return -EINVAL;
7266
7267 /*
7268 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7269 * Note that pitch changes could also affect these register.
7270 */
7271 if (INTEL_INFO(dev)->gen > 3 &&
7272 (fb->offsets[0] != crtc->fb->offsets[0] ||
7273 fb->pitches[0] != crtc->fb->pitches[0]))
7274 return -EINVAL;
7275
6b95a207
KH		 7276 work = kzalloc(sizeof *work, GFP_KERNEL);
7277 if (work == NULL)
7278 return -ENOMEM;
7279
6b95a207 7280 work->event = event;
b4a98e57 7281 work->crtc = crtc;
6b95a207 7282 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7283 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7284 INIT_WORK(&work->work, intel_unpin_work_fn);
7285
7317c75e
JB		 7286 ret = drm_vblank_get(dev, intel_crtc->pipe);
7287 if (ret)
7288 goto free_work;
7289
6b95a207
KH		 7290 /* We borrow the event spin lock for protecting unpin_work */
7291 spin_lock_irqsave(&dev->event_lock, flags);
7292 if (intel_crtc->unpin_work) {
7293 spin_unlock_irqrestore(&dev->event_lock, flags);
7294 kfree(work);
7317c75e 7295 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7296
7297 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7298 return -EBUSY;
7299 }
7300 intel_crtc->unpin_work = work;
7301 spin_unlock_irqrestore(&dev->event_lock, flags);
7302
7303 intel_fb = to_intel_framebuffer(fb);
7304 obj = intel_fb->obj;
7305
b4a98e57
CW		 7306 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7307 flush_workqueue(dev_priv->wq);
7308
79158103
CW		 7309 ret = i915_mutex_lock_interruptible(dev);
7310 if (ret)
7311 goto cleanup;
6b95a207 7312
75dfca80 7313 /* Reference the objects for the scheduled work. */
05394f39
CW		 7314 drm_gem_object_reference(&work->old_fb_obj->base);
7315 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7316
7317 crtc->fb = fb;
96b099fd 7318
e1f99ce6 7319 work->pending_flip_obj = obj;
e1f99ce6 7320
4e5359cd
SF		 7321 work->enable_stall_check = true;
7322
b4a98e57 7323 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7324 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7325
8c9f3aaf
JB		 7326 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7327 if (ret)
7328 goto cleanup_pending;
6b95a207 7329
7782de3b 7330 intel_disable_fbc(dev);
f047e395 7331 intel_mark_fb_busy(obj);
6b95a207
KH		 7332 mutex_unlock(&dev->struct_mutex);
7333
e5510fac
JB		 7334 trace_i915_flip_request(intel_crtc->plane, obj);
7335
6b95a207 7336 return 0;
96b099fd 7337
8c9f3aaf 7338cleanup_pending:
b4a98e57 7339 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7340 drm_gem_object_unreference(&work->old_fb_obj->base);
7341 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7342 mutex_unlock(&dev->struct_mutex);
7343
79158103 7344cleanup:
96b099fd
CW		 7345 spin_lock_irqsave(&dev->event_lock, flags);
7346 intel_crtc->unpin_work = NULL;
7347 spin_unlock_irqrestore(&dev->event_lock, flags);
7348
7317c75e
JB		 7349 drm_vblank_put(dev, intel_crtc->pipe);
7350free_work:
96b099fd
CW		 7351 kfree(work);
7352
7353 return ret;
6b95a207
KH		 7354}
7355
f6e5b160 7356static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7357 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7358 .load_lut = intel_crtc_load_lut,
976f8a20 7359 .disable = intel_crtc_noop,
f6e5b160
CW		 7360};
7361
6ed0f796 7362bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7363{
6ed0f796
DV		 7364 struct intel_encoder *other_encoder;
7365 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7366
6ed0f796
DV		 7367 if (WARN_ON(!crtc))
7368 return false;
7369
7370 list_for_each_entry(other_encoder,
7371 &crtc->dev->mode_config.encoder_list,
7372 base.head) {
7373
7374 if (&other_encoder->new_crtc->base != crtc ||
7375 encoder == other_encoder)
7376 continue;
7377 else
7378 return true;
f47166d2
CW		 7379 }
7380
6ed0f796
DV		 7381 return false;
7382}
47f1c6c9 7383
50f56119
DV		 7384static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7385 struct drm_crtc *crtc)
7386{
7387 struct drm_device *dev;
7388 struct drm_crtc *tmp;
7389 int crtc_mask = 1;
47f1c6c9 7390
50f56119 7391 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7392
50f56119 7393 dev = crtc->dev;
47f1c6c9 7394
50f56119
DV		 7395 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7396 if (tmp == crtc)
7397 break;
7398 crtc_mask <<= 1;
7399 }
47f1c6c9 7400
50f56119
DV		 7401 if (encoder->possible_crtcs & crtc_mask)
7402 return true;
7403 return false;
47f1c6c9 7404}
79e53945 7405
9a935856
DV		 7406/**
7407 * intel_modeset_update_staged_output_state
7408 *
7409 * Updates the staged output configuration state, e.g. after we've read out the
7410 * current hw state.
7411 */
7412static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7413{
9a935856
DV		 7414 struct intel_encoder *encoder;
7415 struct intel_connector *connector;
f6e5b160 7416
9a935856
DV		 7417 list_for_each_entry(connector, &dev->mode_config.connector_list,
7418 base.head) {
7419 connector->new_encoder =
7420 to_intel_encoder(connector->base.encoder);
7421 }
f6e5b160 7422
9a935856
DV		 7423 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7424 base.head) {
7425 encoder->new_crtc =
7426 to_intel_crtc(encoder->base.crtc);
7427 }
f6e5b160
CW		 7428}
7429
9a935856
DV		 7430/**
7431 * intel_modeset_commit_output_state
7432 *
7433 * This function copies the stage display pipe configuration to the real one.
7434 */
7435static void intel_modeset_commit_output_state(struct drm_device *dev)
7436{
7437 struct intel_encoder *encoder;
7438 struct intel_connector *connector;
f6e5b160 7439
9a935856
DV		 7440 list_for_each_entry(connector, &dev->mode_config.connector_list,
7441 base.head) {
7442 connector->base.encoder = &connector->new_encoder->base;
7443 }
f6e5b160 7444
9a935856
DV		 7445 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7446 base.head) {
7447 encoder->base.crtc = &encoder->new_crtc->base;
7448 }
7449}
7450
7758a113
DV		 7451static struct drm_display_mode *
7452intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7453 struct drm_display_mode *mode)
ee7b9f93 7454{
7758a113
DV		 7455 struct drm_device *dev = crtc->dev;
7456 struct drm_display_mode *adjusted_mode;
7457 struct drm_encoder_helper_funcs *encoder_funcs;
7458 struct intel_encoder *encoder;
ee7b9f93 7459
7758a113
DV		 7460 adjusted_mode = drm_mode_duplicate(dev, mode);
7461 if (!adjusted_mode)
7462 return ERR_PTR(-ENOMEM);
7463
7464 /* Pass our mode to the connectors and the CRTC to give them a chance to
7465 * adjust it according to limitations or connector properties, and also
7466 * a chance to reject the mode entirely.
47f1c6c9 7467 */
7758a113
DV		 7468 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7469 base.head) {
47f1c6c9 7470
7758a113
DV		 7471 if (&encoder->new_crtc->base != crtc)
7472 continue;
7473 encoder_funcs = encoder->base.helper_private;
7474 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7475 adjusted_mode))) {
7476 DRM_DEBUG_KMS("Encoder fixup failed\n");
7477 goto fail;
7478 }
ee7b9f93 7479 }
47f1c6c9 7480
7758a113
DV		 7481 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7482 DRM_DEBUG_KMS("CRTC fixup failed\n");
7483 goto fail;
ee7b9f93 7484 }
7758a113 7485 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7486
7758a113
DV		 7487 return adjusted_mode;
7488fail:
7489 drm_mode_destroy(dev, adjusted_mode);
7490 return ERR_PTR(-EINVAL);
ee7b9f93 7491}
47f1c6c9 7492
e2e1ed41
DV		 7493/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7494 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7495static void
7496intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7497 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7498{
7499 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7500 struct drm_device *dev = crtc->dev;
7501 struct intel_encoder *encoder;
7502 struct intel_connector *connector;
7503 struct drm_crtc *tmp_crtc;
79e53945 7504
e2e1ed41 7505 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7506
e2e1ed41
DV		 7507 /* Check which crtcs have changed outputs connected to them, these need
7508 * to be part of the prepare_pipes mask. We don't (yet) support global
7509 * modeset across multiple crtcs, so modeset_pipes will only have one
7510 * bit set at most. */
7511 list_for_each_entry(connector, &dev->mode_config.connector_list,
7512 base.head) {
7513 if (connector->base.encoder == &connector->new_encoder->base)
7514 continue;
79e53945 7515
e2e1ed41
DV		 7516 if (connector->base.encoder) {
7517 tmp_crtc = connector->base.encoder->crtc;
7518
7519 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7520 }
7521
7522 if (connector->new_encoder)
7523 *prepare_pipes |=
7524 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7525 }
7526
e2e1ed41
DV		 7527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7528 base.head) {
7529 if (encoder->base.crtc == &encoder->new_crtc->base)
7530 continue;
7531
7532 if (encoder->base.crtc) {
7533 tmp_crtc = encoder->base.crtc;
7534
7535 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7536 }
7537
7538 if (encoder->new_crtc)
7539 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7540 }
7541
e2e1ed41
DV		 7542 /* Check for any pipes that will be fully disabled ... */
7543 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7544 base.head) {
7545 bool used = false;
22fd0fab 7546
e2e1ed41
DV		 7547 /* Don't try to disable disabled crtcs. */
7548 if (!intel_crtc->base.enabled)
7549 continue;
7e7d76c3 7550
e2e1ed41
DV		 7551 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7552 base.head) {
7553 if (encoder->new_crtc == intel_crtc)
7554 used = true;
7555 }
7556
7557 if (!used)
7558 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7559 }
7560
e2e1ed41
DV		 7561
7562 /* set_mode is also used to update properties on life display pipes. */
7563 intel_crtc = to_intel_crtc(crtc);
7564 if (crtc->enabled)
7565 *prepare_pipes |= 1 << intel_crtc->pipe;
7566
7567 /* We only support modeset on one single crtc, hence we need to do that
7568 * only for the passed in crtc iff we change anything else than just
7569 * disable crtcs.
7570 *
7571 * This is actually not true, to be fully compatible with the old crtc
7572 * helper we automatically disable _any_ output (i.e. doesn't need to be
7573 * connected to the crtc we're modesetting on) if it's disconnected.
7574 * Which is a rather nutty api (since changed the output configuration
7575 * without userspace's explicit request can lead to confusion), but
7576 * alas. Hence we currently need to modeset on all pipes we prepare. */
7577 if (*prepare_pipes)
7578 *modeset_pipes = *prepare_pipes;
7579
7580 /* ... and mask these out. */
7581 *modeset_pipes &= ~(*disable_pipes);
7582 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7583}
79e53945 7584
ea9d758d 7585static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7586{
ea9d758d 7587 struct drm_encoder *encoder;
f6e5b160 7588 struct drm_device *dev = crtc->dev;
f6e5b160 7589
ea9d758d
DV		 7590 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7591 if (encoder->crtc == crtc)
7592 return true;
7593
7594 return false;
7595}
7596
7597static void
7598intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7599{
7600 struct intel_encoder *intel_encoder;
7601 struct intel_crtc *intel_crtc;
7602 struct drm_connector *connector;
7603
7604 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7605 base.head) {
7606 if (!intel_encoder->base.crtc)
7607 continue;
7608
7609 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7610
7611 if (prepare_pipes & (1 << intel_crtc->pipe))
7612 intel_encoder->connectors_active = false;
7613 }
7614
7615 intel_modeset_commit_output_state(dev);
7616
7617 /* Update computed state. */
7618 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7619 base.head) {
7620 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7621 }
7622
7623 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7624 if (!connector->encoder || !connector->encoder->crtc)
7625 continue;
7626
7627 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7628
7629 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7630 struct drm_property *dpms_property =
7631 dev->mode_config.dpms_property;
7632
ea9d758d 7633 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7634 drm_object_property_set_value(&connector->base,
68d34720
DV		 7635 dpms_property,
7636 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7637
7638 intel_encoder = to_intel_encoder(connector->encoder);
7639 intel_encoder->connectors_active = true;
7640 }
7641 }
7642
7643}
7644
25c5b266
DV		 7645#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7646 list_for_each_entry((intel_crtc), \
7647 &(dev)->mode_config.crtc_list, \
7648 base.head) \
7649 if (mask & (1 <<(intel_crtc)->pipe)) \
7650
b980514c 7651void
8af6cf88
DV		 7652intel_modeset_check_state(struct drm_device *dev)
7653{
7654 struct intel_crtc *crtc;
7655 struct intel_encoder *encoder;
7656 struct intel_connector *connector;
7657
7658 list_for_each_entry(connector, &dev->mode_config.connector_list,
7659 base.head) {
7660 /* This also checks the encoder/connector hw state with the
7661 * ->get_hw_state callbacks. */
7662 intel_connector_check_state(connector);
7663
7664 WARN(&connector->new_encoder->base != connector->base.encoder,
7665 "connector's staged encoder doesn't match current encoder\n");
7666 }
7667
7668 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7669 base.head) {
7670 bool enabled = false;
7671 bool active = false;
7672 enum pipe pipe, tracked_pipe;
7673
7674 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7675 encoder->base.base.id,
7676 drm_get_encoder_name(&encoder->base));
7677
7678 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7679 "encoder's stage crtc doesn't match current crtc\n");
7680 WARN(encoder->connectors_active && !encoder->base.crtc,
7681 "encoder's active_connectors set, but no crtc\n");
7682
7683 list_for_each_entry(connector, &dev->mode_config.connector_list,
7684 base.head) {
7685 if (connector->base.encoder != &encoder->base)
7686 continue;
7687 enabled = true;
7688 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7689 active = true;
7690 }
7691 WARN(!!encoder->base.crtc != enabled,
7692 "encoder's enabled state mismatch "
7693 "(expected %i, found %i)\n",
7694 !!encoder->base.crtc, enabled);
7695 WARN(active && !encoder->base.crtc,
7696 "active encoder with no crtc\n");
7697
7698 WARN(encoder->connectors_active != active,
7699 "encoder's computed active state doesn't match tracked active state "
7700 "(expected %i, found %i)\n", active, encoder->connectors_active);
7701
7702 active = encoder->get_hw_state(encoder, &pipe);
7703 WARN(active != encoder->connectors_active,
7704 "encoder's hw state doesn't match sw tracking "
7705 "(expected %i, found %i)\n",
7706 encoder->connectors_active, active);
7707
7708 if (!encoder->base.crtc)
7709 continue;
7710
7711 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7712 WARN(active && pipe != tracked_pipe,
7713 "active encoder's pipe doesn't match"
7714 "(expected %i, found %i)\n",
7715 tracked_pipe, pipe);
7716
7717 }
7718
7719 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7720 base.head) {
7721 bool enabled = false;
7722 bool active = false;
7723
7724 DRM_DEBUG_KMS("[CRTC:%d]\n",
7725 crtc->base.base.id);
7726
7727 WARN(crtc->active && !crtc->base.enabled,
7728 "active crtc, but not enabled in sw tracking\n");
7729
7730 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7731 base.head) {
7732 if (encoder->base.crtc != &crtc->base)
7733 continue;
7734 enabled = true;
7735 if (encoder->connectors_active)
7736 active = true;
7737 }
7738 WARN(active != crtc->active,
7739 "crtc's computed active state doesn't match tracked active state "
7740 "(expected %i, found %i)\n", active, crtc->active);
7741 WARN(enabled != crtc->base.enabled,
7742 "crtc's computed enabled state doesn't match tracked enabled state "
7743 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7744
7745 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7746 }
7747}
7748
c0c36b94
CW		 7749int intel_set_mode(struct drm_crtc *crtc,
7750 struct drm_display_mode *mode,
7751 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7752{
7753 struct drm_device *dev = crtc->dev;
dbf2b54e 7754 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7755 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7756 struct intel_crtc *intel_crtc;
7757 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7758 int ret = 0;
a6778b3c 7759
3ac18232 7760 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7761 if (!saved_mode)
7762 return -ENOMEM;
3ac18232 7763 saved_hwmode = saved_mode + 1;
a6778b3c 7764
e2e1ed41 7765 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7766 &prepare_pipes, &disable_pipes);
7767
7768 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7769 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7770
976f8a20
DV		 7771 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7772 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7773
3ac18232
TG		 7774 *saved_hwmode = crtc->hwmode;
7775 *saved_mode = crtc->mode;
a6778b3c 7776
25c5b266
DV		 7777 /* Hack: Because we don't (yet) support global modeset on multiple
7778 * crtcs, we don't keep track of the new mode for more than one crtc.
7779 * Hence simply check whether any bit is set in modeset_pipes in all the
7780 * pieces of code that are not yet converted to deal with mutliple crtcs
7781 * changing their mode at the same time. */
7782 adjusted_mode = NULL;
7783 if (modeset_pipes) {
7784 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7785 if (IS_ERR(adjusted_mode)) {
c0c36b94 7786 ret = PTR_ERR(adjusted_mode);
3ac18232 7787 goto out;
25c5b266 7788 }
25c5b266 7789 }
a6778b3c 7790
ea9d758d
DV		 7791 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7792 if (intel_crtc->base.enabled)
7793 dev_priv->display.crtc_disable(&intel_crtc->base);
7794 }
a6778b3c 7795
6c4c86f5
DV		 7796 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7797 * to set it here already despite that we pass it down the callchain.
f6e5b160 7798 */
6c4c86f5 7799 if (modeset_pipes)
25c5b266 7800 crtc->mode = *mode;
7758a113 7801
ea9d758d
DV		 7802 /* Only after disabling all output pipelines that will be changed can we
7803 * update the the output configuration. */
7804 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7805
47fab737
DV		 7806 if (dev_priv->display.modeset_global_resources)
7807 dev_priv->display.modeset_global_resources(dev);
7808
a6778b3c
DV		 7809 /* Set up the DPLL and any encoders state that needs to adjust or depend
7810 * on the DPLL.
f6e5b160 7811 */
25c5b266 7812 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7813 ret = intel_crtc_mode_set(&intel_crtc->base,
7814 mode, adjusted_mode,
7815 x, y, fb);
7816 if (ret)
7817 goto done;
a6778b3c
DV		 7818 }
7819
7820 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7821 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7822 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7823
25c5b266
DV		 7824 if (modeset_pipes) {
7825 /* Store real post-adjustment hardware mode. */
7826 crtc->hwmode = *adjusted_mode;
a6778b3c 7827
25c5b266
DV		 7828 /* Calculate and store various constants which
7829 * are later needed by vblank and swap-completion
7830 * timestamping. They are derived from true hwmode.
7831 */
7832 drm_calc_timestamping_constants(crtc);
7833 }
a6778b3c
DV		 7834
7835 /* FIXME: add subpixel order */
7836done:
7837 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7838 if (ret && crtc->enabled) {
3ac18232
TG		 7839 crtc->hwmode = *saved_hwmode;
7840 crtc->mode = *saved_mode;
8af6cf88
DV		 7841 } else {
7842 intel_modeset_check_state(dev);
a6778b3c
DV		 7843 }
7844
3ac18232
TG		 7845out:
7846 kfree(saved_mode);
a6778b3c 7847 return ret;
f6e5b160
CW		 7848}
7849
c0c36b94
CW		 7850void intel_crtc_restore_mode(struct drm_crtc *crtc)
7851{
7852 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7853}
7854
25c5b266
DV		 7855#undef for_each_intel_crtc_masked
7856
d9e55608
DV		 7857static void intel_set_config_free(struct intel_set_config *config)
7858{
7859 if (!config)
7860 return;
7861
1aa4b628
DV		 7862 kfree(config->save_connector_encoders);
7863 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7864 kfree(config);
7865}
7866
85f9eb71
DV		 7867static int intel_set_config_save_state(struct drm_device *dev,
7868 struct intel_set_config *config)
7869{
85f9eb71
DV		 7870 struct drm_encoder *encoder;
7871 struct drm_connector *connector;
7872 int count;
7873
1aa4b628
DV		 7874 config->save_encoder_crtcs =
7875 kcalloc(dev->mode_config.num_encoder,
7876 sizeof(struct drm_crtc *), GFP_KERNEL);
7877 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7878 return -ENOMEM;
7879
1aa4b628
DV		 7880 config->save_connector_encoders =
7881 kcalloc(dev->mode_config.num_connector,
7882 sizeof(struct drm_encoder *), GFP_KERNEL);
7883 if (!config->save_connector_encoders)
85f9eb71
DV		 7884 return -ENOMEM;
7885
7886 /* Copy data. Note that driver private data is not affected.
7887 * Should anything bad happen only the expected state is
7888 * restored, not the drivers personal bookkeeping.
7889 */
85f9eb71
DV		 7890 count = 0;
7891 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7892 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7893 }
7894
7895 count = 0;
7896 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7897 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7898 }
7899
7900 return 0;
7901}
7902
7903static void intel_set_config_restore_state(struct drm_device *dev,
7904 struct intel_set_config *config)
7905{
9a935856
DV		 7906 struct intel_encoder *encoder;
7907 struct intel_connector *connector;
85f9eb71
DV		 7908 int count;
7909
85f9eb71 7910 count = 0;
9a935856
DV		 7911 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7912 encoder->new_crtc =
7913 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7914 }
7915
7916 count = 0;
9a935856
DV		 7917 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7918 connector->new_encoder =
7919 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7920 }
7921}
7922
5e2b584e
DV		 7923static void
7924intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7925 struct intel_set_config *config)
7926{
7927
7928 /* We should be able to check here if the fb has the same properties
7929 * and then just flip_or_move it */
7930 if (set->crtc->fb != set->fb) {
7931 /* If we have no fb then treat it as a full mode set */
7932 if (set->crtc->fb == NULL) {
7933 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7934 config->mode_changed = true;
7935 } else if (set->fb == NULL) {
7936 config->mode_changed = true;
7937 } else if (set->fb->depth != set->crtc->fb->depth) {
7938 config->mode_changed = true;
7939 } else if (set->fb->bits_per_pixel !=
7940 set->crtc->fb->bits_per_pixel) {
7941 config->mode_changed = true;
7942 } else
7943 config->fb_changed = true;
7944 }
7945
835c5873 7946 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7947 config->fb_changed = true;
7948
7949 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7950 DRM_DEBUG_KMS("modes are different, full mode set\n");
7951 drm_mode_debug_printmodeline(&set->crtc->mode);
7952 drm_mode_debug_printmodeline(set->mode);
7953 config->mode_changed = true;
7954 }
7955}
7956
2e431051 7957static int
9a935856
DV		 7958intel_modeset_stage_output_state(struct drm_device *dev,
7959 struct drm_mode_set *set,
7960 struct intel_set_config *config)
50f56119 7961{
85f9eb71 7962 struct drm_crtc *new_crtc;
9a935856
DV		 7963 struct intel_connector *connector;
7964 struct intel_encoder *encoder;
2e431051 7965 int count, ro;
50f56119 7966
9abdda74 7967 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7968 * of connectors. For paranoia, double-check this. */
7969 WARN_ON(!set->fb && (set->num_connectors != 0));
7970 WARN_ON(set->fb && (set->num_connectors == 0));
7971
50f56119 7972 count = 0;
9a935856
DV		 7973 list_for_each_entry(connector, &dev->mode_config.connector_list,
7974 base.head) {
7975 /* Otherwise traverse passed in connector list and get encoders
7976 * for them. */
50f56119 7977 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7978 if (set->connectors[ro] == &connector->base) {
7979 connector->new_encoder = connector->encoder;
50f56119
DV		 7980 break;
7981 }
7982 }
7983
9a935856
DV		 7984 /* If we disable the crtc, disable all its connectors. Also, if
7985 * the connector is on the changing crtc but not on the new
7986 * connector list, disable it. */
7987 if ((!set->fb || ro == set->num_connectors) &&
7988 connector->base.encoder &&
7989 connector->base.encoder->crtc == set->crtc) {
7990 connector->new_encoder = NULL;
7991
7992 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7993 connector->base.base.id,
7994 drm_get_connector_name(&connector->base));
7995 }
7996
7997
7998 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7999 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8000 config->mode_changed = true;
50f56119
DV		 8001 }
8002 }
9a935856 8003 /* connector->new_encoder is now updated for all connectors. */
50f56119 8004
9a935856 8005 /* Update crtc of enabled connectors. */
50f56119 8006 count = 0;
9a935856
DV		 8007 list_for_each_entry(connector, &dev->mode_config.connector_list,
8008 base.head) {
8009 if (!connector->new_encoder)
50f56119
DV		 8010 continue;
8011
9a935856 8012 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8013
8014 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8015 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8016 new_crtc = set->crtc;
8017 }
8018
8019 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8020 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8021 new_crtc)) {
5e2b584e 8022 return -EINVAL;
50f56119 8023 }
9a935856
DV		 8024 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8025
8026 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8027 connector->base.base.id,
8028 drm_get_connector_name(&connector->base),
8029 new_crtc->base.id);
8030 }
8031
8032 /* Check for any encoders that needs to be disabled. */
8033 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8034 base.head) {
8035 list_for_each_entry(connector,
8036 &dev->mode_config.connector_list,
8037 base.head) {
8038 if (connector->new_encoder == encoder) {
8039 WARN_ON(!connector->new_encoder->new_crtc);
8040
8041 goto next_encoder;
8042 }
8043 }
8044 encoder->new_crtc = NULL;
8045next_encoder:
8046 /* Only now check for crtc changes so we don't miss encoders
8047 * that will be disabled. */
8048 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8049 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8050 config->mode_changed = true;
50f56119
DV		 8051 }
8052 }
9a935856 8053 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8054
2e431051
DV		 8055 return 0;
8056}
8057
8058static int intel_crtc_set_config(struct drm_mode_set *set)
8059{
8060 struct drm_device *dev;
2e431051
DV		 8061 struct drm_mode_set save_set;
8062 struct intel_set_config *config;
8063 int ret;
2e431051 8064
8d3e375e
DV		 8065 BUG_ON(!set);
8066 BUG_ON(!set->crtc);
8067 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8068
8069 if (!set->mode)
8070 set->fb = NULL;
8071
431e50f7
DV		 8072 /* The fb helper likes to play gross jokes with ->mode_set_config.
8073 * Unfortunately the crtc helper doesn't do much at all for this case,
8074 * so we have to cope with this madness until the fb helper is fixed up. */
8075 if (set->fb && set->num_connectors == 0)
8076 return 0;
8077
2e431051
DV		 8078 if (set->fb) {
8079 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8080 set->crtc->base.id, set->fb->base.id,
8081 (int)set->num_connectors, set->x, set->y);
8082 } else {
8083 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8084 }
8085
8086 dev = set->crtc->dev;
8087
8088 ret = -ENOMEM;
8089 config = kzalloc(sizeof(*config), GFP_KERNEL);
8090 if (!config)
8091 goto out_config;
8092
8093 ret = intel_set_config_save_state(dev, config);
8094 if (ret)
8095 goto out_config;
8096
8097 save_set.crtc = set->crtc;
8098 save_set.mode = &set->crtc->mode;
8099 save_set.x = set->crtc->x;
8100 save_set.y = set->crtc->y;
8101 save_set.fb = set->crtc->fb;
8102
8103 /* Compute whether we need a full modeset, only an fb base update or no
8104 * change at all. In the future we might also check whether only the
8105 * mode changed, e.g. for LVDS where we only change the panel fitter in
8106 * such cases. */
8107 intel_set_config_compute_mode_changes(set, config);
8108
9a935856 8109 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8110 if (ret)
8111 goto fail;
8112
5e2b584e 8113 if (config->mode_changed) {
87f1faa6 8114 if (set->mode) {
50f56119
DV		 8115 DRM_DEBUG_KMS("attempting to set mode from"
8116 " userspace\n");
8117 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8118 }
8119
c0c36b94
CW		 8120 ret = intel_set_mode(set->crtc, set->mode,
8121 set->x, set->y, set->fb);
8122 if (ret) {
8123 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8124 set->crtc->base.id, ret);
87f1faa6
DV		 8125 goto fail;
8126 }
5e2b584e 8127 } else if (config->fb_changed) {
4f660f49 8128 ret = intel_pipe_set_base(set->crtc,
94352cf9 8129 set->x, set->y, set->fb);
50f56119
DV		 8130 }
8131
d9e55608
DV		 8132 intel_set_config_free(config);
8133
50f56119
DV		 8134 return 0;
8135
8136fail:
85f9eb71 8137 intel_set_config_restore_state(dev, config);
50f56119
DV		 8138
8139 /* Try to restore the config */
5e2b584e 8140 if (config->mode_changed &&
c0c36b94
CW		 8141 intel_set_mode(save_set.crtc, save_set.mode,
8142 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8143 DRM_ERROR("failed to restore config after modeset failure\n");
8144
d9e55608
DV		 8145out_config:
8146 intel_set_config_free(config);
50f56119
DV		 8147 return ret;
8148}
f6e5b160
CW		 8149
8150static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8151 .cursor_set = intel_crtc_cursor_set,
8152 .cursor_move = intel_crtc_cursor_move,
8153 .gamma_set = intel_crtc_gamma_set,
50f56119 8154 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8155 .destroy = intel_crtc_destroy,
8156 .page_flip = intel_crtc_page_flip,
8157};
8158
79f689aa
PZ		 8159static void intel_cpu_pll_init(struct drm_device *dev)
8160{
affa9354 8161 if (HAS_DDI(dev))
79f689aa
PZ		 8162 intel_ddi_pll_init(dev);
8163}
8164
ee7b9f93
JB		 8165static void intel_pch_pll_init(struct drm_device *dev)
8166{
8167 drm_i915_private_t *dev_priv = dev->dev_private;
8168 int i;
8169
8170 if (dev_priv->num_pch_pll == 0) {
8171 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8172 return;
8173 }
8174
8175 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8176 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8177 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8178 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8179 }
8180}
8181
b358d0a6 8182static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8183{
22fd0fab 8184 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8185 struct intel_crtc *intel_crtc;
8186 int i;
8187
8188 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8189 if (intel_crtc == NULL)
8190 return;
8191
8192 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8193
8194 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8195 for (i = 0; i < 256; i++) {
8196 intel_crtc->lut_r[i] = i;
8197 intel_crtc->lut_g[i] = i;
8198 intel_crtc->lut_b[i] = i;
8199 }
8200
80824003
JB		 8201 /* Swap pipes & planes for FBC on pre-965 */
8202 intel_crtc->pipe = pipe;
8203 intel_crtc->plane = pipe;
a5c961d1 8204 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8205 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8206 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8207 intel_crtc->plane = !pipe;
80824003
JB		 8208 }
8209
22fd0fab
JB		 8210 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8211 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8212 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8213 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8214
5a354204 8215 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8216
79e53945 8217 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8218}
8219
08d7b3d1 8220int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8221 struct drm_file *file)
08d7b3d1 8222{
08d7b3d1 8223 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8224 struct drm_mode_object *drmmode_obj;
8225 struct intel_crtc *crtc;
08d7b3d1 8226
1cff8f6b
DV		 8227 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8228 return -ENODEV;
08d7b3d1 8229
c05422d5
DV		 8230 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8231 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8232
c05422d5 8233 if (!drmmode_obj) {
08d7b3d1
CW		 8234 DRM_ERROR("no such CRTC id\n");
8235 return -EINVAL;
8236 }
8237
c05422d5
DV		 8238 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8239 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8240
c05422d5 8241 return 0;
08d7b3d1
CW		 8242}
8243
66a9278e 8244static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8245{
66a9278e
DV		 8246 struct drm_device *dev = encoder->base.dev;
8247 struct intel_encoder *source_encoder;
79e53945 8248 int index_mask = 0;
79e53945
JB		 8249 int entry = 0;
8250
66a9278e
DV		 8251 list_for_each_entry(source_encoder,
8252 &dev->mode_config.encoder_list, base.head) {
8253
8254 if (encoder == source_encoder)
79e53945 8255 index_mask |= (1 << entry);
66a9278e
DV		 8256
8257 /* Intel hw has only one MUX where enocoders could be cloned. */
8258 if (encoder->cloneable && source_encoder->cloneable)
8259 index_mask |= (1 << entry);
8260
79e53945
JB		 8261 entry++;
8262 }
4ef69c7a 8263
79e53945
JB		 8264 return index_mask;
8265}
8266
4d302442
CW		 8267static bool has_edp_a(struct drm_device *dev)
8268{
8269 struct drm_i915_private *dev_priv = dev->dev_private;
8270
8271 if (!IS_MOBILE(dev))
8272 return false;
8273
8274 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8275 return false;
8276
8277 if (IS_GEN5(dev) &&
8278 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8279 return false;
8280
8281 return true;
8282}
8283
79e53945
JB		 8284static void intel_setup_outputs(struct drm_device *dev)
8285{
725e30ad 8286 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8287 struct intel_encoder *encoder;
cb0953d7 8288 bool dpd_is_edp = false;
f3cfcba6 8289 bool has_lvds;
79e53945 8290
f3cfcba6 8291 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8292 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8293 /* disable the panel fitter on everything but LVDS */
8294 I915_WRITE(PFIT_CONTROL, 0);
8295 }
79e53945 8296
affa9354 8297 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8298 intel_crt_init(dev);
cb0953d7 8299
affa9354 8300 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8301 int found;
8302
8303 /* Haswell uses DDI functions to detect digital outputs */
8304 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8305 /* DDI A only supports eDP */
8306 if (found)
8307 intel_ddi_init(dev, PORT_A);
8308
8309 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8310 * register */
8311 found = I915_READ(SFUSE_STRAP);
8312
8313 if (found & SFUSE_STRAP_DDIB_DETECTED)
8314 intel_ddi_init(dev, PORT_B);
8315 if (found & SFUSE_STRAP_DDIC_DETECTED)
8316 intel_ddi_init(dev, PORT_C);
8317 if (found & SFUSE_STRAP_DDID_DETECTED)
8318 intel_ddi_init(dev, PORT_D);
8319 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8320 int found;
270b3042
DV		 8321 dpd_is_edp = intel_dpd_is_edp(dev);
8322
8323 if (has_edp_a(dev))
8324 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8325
30ad48b7 8326 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8327 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8328 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8329 if (!found)
08d644ad 8330 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8331 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8332 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8333 }
8334
8335 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8336 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8337
b708a1d5 8338 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8339 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8340
5eb08b69 8341 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8342 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8343
270b3042 8344 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8345 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8346 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8347 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8348 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8349 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8350
67cfc203
VS		 8351 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8352 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8353 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8354 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d
JB		 8355 }
8356
67cfc203
VS		 8357 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8358 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
5eb08b69 8359
103a196f 8360 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8361 bool found = false;
7d57382e 8362
725e30ad 8363 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8364 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8365 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8366 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8367 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8368 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8369 }
27185ae1 8370
b01f2c3a
JB		 8371 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8372 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8373 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8374 }
725e30ad 8375 }
13520b05
KH		 8376
8377 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8378
b01f2c3a
JB		 8379 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8380 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8381 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8382 }
27185ae1
ML		 8383
8384 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8385
b01f2c3a
JB		 8386 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8387 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8388 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8389 }
8390 if (SUPPORTS_INTEGRATED_DP(dev)) {
8391 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8392 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8393 }
725e30ad 8394 }
27185ae1 8395
b01f2c3a
JB		 8396 if (SUPPORTS_INTEGRATED_DP(dev) &&
8397 (I915_READ(DP_D) & DP_DETECTED)) {
8398 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8399 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8400 }
bad720ff 8401 } else if (IS_GEN2(dev))
79e53945
JB		 8402 intel_dvo_init(dev);
8403
103a196f 8404 if (SUPPORTS_TV(dev))
79e53945
JB		 8405 intel_tv_init(dev);
8406
4ef69c7a
CW		 8407 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8408 encoder->base.possible_crtcs = encoder->crtc_mask;
8409 encoder->base.possible_clones =
66a9278e 8410 intel_encoder_clones(encoder);
79e53945 8411 }
47356eb6 8412
dde86e2d 8413 intel_init_pch_refclk(dev);
270b3042
DV		 8414
8415 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8416}
8417
8418static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8419{
8420 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8421
8422 drm_framebuffer_cleanup(fb);
05394f39 8423 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8424
8425 kfree(intel_fb);
8426}
8427
8428static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8429 struct drm_file *file,
79e53945
JB		 8430 unsigned int *handle)
8431{
8432 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8433 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8434
05394f39 8435 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8436}
8437
8438static const struct drm_framebuffer_funcs intel_fb_funcs = {
8439 .destroy = intel_user_framebuffer_destroy,
8440 .create_handle = intel_user_framebuffer_create_handle,
8441};
8442
38651674
DA		 8443int intel_framebuffer_init(struct drm_device *dev,
8444 struct intel_framebuffer *intel_fb,
308e5bcb 8445 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8446 struct drm_i915_gem_object *obj)
79e53945 8447{
79e53945
JB		 8448 int ret;
8449
c16ed4be
CW		 8450 if (obj->tiling_mode == I915_TILING_Y) {
8451 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8452 return -EINVAL;
c16ed4be 8453 }
57cd6508 8454
c16ed4be
CW		 8455 if (mode_cmd->pitches[0] & 63) {
8456 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8457 mode_cmd->pitches[0]);
57cd6508 8458 return -EINVAL;
c16ed4be 8459 }
57cd6508 8460
5d7bd705 8461 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8462 if (mode_cmd->pitches[0] > 32768) {
8463 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8464 mode_cmd->pitches[0]);
5d7bd705 8465 return -EINVAL;
c16ed4be 8466 }
5d7bd705
VS		 8467
8468 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8469 mode_cmd->pitches[0] != obj->stride) {
8470 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8471 mode_cmd->pitches[0], obj->stride);
5d7bd705 8472 return -EINVAL;
c16ed4be 8473 }
5d7bd705 8474
57779d06 8475 /* Reject formats not supported by any plane early. */
308e5bcb 8476 switch (mode_cmd->pixel_format) {
57779d06 8477 case DRM_FORMAT_C8:
04b3924d
VS		 8478 case DRM_FORMAT_RGB565:
8479 case DRM_FORMAT_XRGB8888:
8480 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8481 break;
8482 case DRM_FORMAT_XRGB1555:
8483 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8484 if (INTEL_INFO(dev)->gen > 3) {
8485 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8486 return -EINVAL;
c16ed4be 8487 }
57779d06
VS		 8488 break;
8489 case DRM_FORMAT_XBGR8888:
8490 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8491 case DRM_FORMAT_XRGB2101010:
8492 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8493 case DRM_FORMAT_XBGR2101010:
8494 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8495 if (INTEL_INFO(dev)->gen < 4) {
8496 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8497 return -EINVAL;
c16ed4be 8498 }
b5626747 8499 break;
04b3924d
VS		 8500 case DRM_FORMAT_YUYV:
8501 case DRM_FORMAT_UYVY:
8502 case DRM_FORMAT_YVYU:
8503 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8504 if (INTEL_INFO(dev)->gen < 5) {
8505 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8506 return -EINVAL;
c16ed4be 8507 }
57cd6508
CW		 8508 break;
8509 default:
c16ed4be 8510 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8511 return -EINVAL;
8512 }
8513
90f9a336
VS		 8514 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8515 if (mode_cmd->offsets[0] != 0)
8516 return -EINVAL;
8517
c7d73f6a
DV		 8518 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8519 intel_fb->obj = obj;
8520
79e53945
JB		 8521 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8522 if (ret) {
8523 DRM_ERROR("framebuffer init failed %d\n", ret);
8524 return ret;
8525 }
8526
79e53945
JB		 8527 return 0;
8528}
8529
79e53945
JB		 8530static struct drm_framebuffer *
8531intel_user_framebuffer_create(struct drm_device *dev,
8532 struct drm_file *filp,
308e5bcb 8533 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8534{
05394f39 8535 struct drm_i915_gem_object *obj;
79e53945 8536
308e5bcb
JB		 8537 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8538 mode_cmd->handles[0]));
c8725226 8539 if (&obj->base == NULL)
cce13ff7 8540 return ERR_PTR(-ENOENT);
79e53945 8541
d2dff872 8542 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8543}
8544
79e53945 8545static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8546 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8547 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8548};
8549
e70236a8
JB		 8550/* Set up chip specific display functions */
8551static void intel_init_display(struct drm_device *dev)
8552{
8553 struct drm_i915_private *dev_priv = dev->dev_private;
8554
8555 /* We always want a DPMS function */
affa9354 8556 if (HAS_DDI(dev)) {
09b4ddf9 8557 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8558 dev_priv->display.crtc_enable = haswell_crtc_enable;
8559 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8560 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8561 dev_priv->display.update_plane = ironlake_update_plane;
8562 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8563 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8564 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8565 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8566 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8567 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8568 } else {
f564048e 8569 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8570 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8571 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8572 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8573 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8574 }
e70236a8 8575
e70236a8 8576 /* Returns the core display clock speed */
25eb05fc
JB		 8577 if (IS_VALLEYVIEW(dev))
8578 dev_priv->display.get_display_clock_speed =
8579 valleyview_get_display_clock_speed;
8580 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8581 dev_priv->display.get_display_clock_speed =
8582 i945_get_display_clock_speed;
8583 else if (IS_I915G(dev))
8584 dev_priv->display.get_display_clock_speed =
8585 i915_get_display_clock_speed;
f2b115e6 8586 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8587 dev_priv->display.get_display_clock_speed =
8588 i9xx_misc_get_display_clock_speed;
8589 else if (IS_I915GM(dev))
8590 dev_priv->display.get_display_clock_speed =
8591 i915gm_get_display_clock_speed;
8592 else if (IS_I865G(dev))
8593 dev_priv->display.get_display_clock_speed =
8594 i865_get_display_clock_speed;
f0f8a9ce 8595 else if (IS_I85X(dev))
e70236a8
JB		 8596 dev_priv->display.get_display_clock_speed =
8597 i855_get_display_clock_speed;
8598 else /* 852, 830 */
8599 dev_priv->display.get_display_clock_speed =
8600 i830_get_display_clock_speed;
8601
7f8a8569 8602 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8603 if (IS_GEN5(dev)) {
674cf967 8604 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8605 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8606 } else if (IS_GEN6(dev)) {
674cf967 8607 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8608 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8609 } else if (IS_IVYBRIDGE(dev)) {
8610 /* FIXME: detect B0+ stepping and use auto training */
8611 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8612 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8613 dev_priv->display.modeset_global_resources =
8614 ivb_modeset_global_resources;
c82e4d26
ED		 8615 } else if (IS_HASWELL(dev)) {
8616 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8617 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8618 dev_priv->display.modeset_global_resources =
8619 haswell_modeset_global_resources;
a0e63c22 8620 }
6067aaea 8621 } else if (IS_G4X(dev)) {
e0dac65e 8622 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8623 }
8c9f3aaf
JB		 8624
8625 /* Default just returns -ENODEV to indicate unsupported */
8626 dev_priv->display.queue_flip = intel_default_queue_flip;
8627
8628 switch (INTEL_INFO(dev)->gen) {
8629 case 2:
8630 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8631 break;
8632
8633 case 3:
8634 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8635 break;
8636
8637 case 4:
8638 case 5:
8639 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8640 break;
8641
8642 case 6:
8643 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8644 break;
7c9017e5
JB		 8645 case 7:
8646 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8647 break;
8c9f3aaf 8648 }
e70236a8
JB		 8649}
8650
b690e96c
JB		 8651/*
8652 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8653 * resume, or other times. This quirk makes sure that's the case for
8654 * affected systems.
8655 */
0206e353 8656static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8657{
8658 struct drm_i915_private *dev_priv = dev->dev_private;
8659
8660 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8661 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8662}
8663
435793df
KP		 8664/*
8665 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8666 */
8667static void quirk_ssc_force_disable(struct drm_device *dev)
8668{
8669 struct drm_i915_private *dev_priv = dev->dev_private;
8670 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8671 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8672}
8673
4dca20ef 8674/*
5a15ab5b
CE		 8675 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8676 * brightness value
4dca20ef
CE		 8677 */
8678static void quirk_invert_brightness(struct drm_device *dev)
8679{
8680 struct drm_i915_private *dev_priv = dev->dev_private;
8681 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8682 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8683}
8684
b690e96c
JB		 8685struct intel_quirk {
8686 int device;
8687 int subsystem_vendor;
8688 int subsystem_device;
8689 void (*hook)(struct drm_device *dev);
8690};
8691
5f85f176
EE		 8692/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8693struct intel_dmi_quirk {
8694 void (*hook)(struct drm_device *dev);
8695 const struct dmi_system_id (*dmi_id_list)[];
8696};
8697
8698static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8699{
8700 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8701 return 1;
8702}
8703
8704static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8705 {
8706 .dmi_id_list = &(const struct dmi_system_id[]) {
8707 {
8708 .callback = intel_dmi_reverse_brightness,
8709 .ident = "NCR Corporation",
8710 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8711 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8712 },
8713 },
8714 { } /* terminating entry */
8715 },
8716 .hook = quirk_invert_brightness,
8717 },
8718};
8719
c43b5634 8720static struct intel_quirk intel_quirks[] = {
b690e96c 8721 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8722 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8723
b690e96c
JB		 8724 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8725 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8726
b690e96c
JB		 8727 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8728 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8729
ccd0d36e 8730 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8731 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8732 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8733
8734 /* Lenovo U160 cannot use SSC on LVDS */
8735 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8736
8737 /* Sony Vaio Y cannot use SSC on LVDS */
8738 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8739
8740 /* Acer Aspire 5734Z must invert backlight brightness */
8741 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8742
8743 /* Acer/eMachines G725 */
8744 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8745
8746 /* Acer/eMachines e725 */
8747 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8748
8749 /* Acer/Packard Bell NCL20 */
8750 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8751
8752 /* Acer Aspire 4736Z */
8753 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8754};
8755
8756static void intel_init_quirks(struct drm_device *dev)
8757{
8758 struct pci_dev *d = dev->pdev;
8759 int i;
8760
8761 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8762 struct intel_quirk *q = &intel_quirks[i];
8763
8764 if (d->device == q->device &&
8765 (d->subsystem_vendor == q->subsystem_vendor ||
8766 q->subsystem_vendor == PCI_ANY_ID) &&
8767 (d->subsystem_device == q->subsystem_device ||
8768 q->subsystem_device == PCI_ANY_ID))
8769 q->hook(dev);
8770 }
5f85f176
EE		 8771 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8772 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8773 intel_dmi_quirks[i].hook(dev);
8774 }
b690e96c
JB		 8775}
8776
9cce37f4
JB		 8777/* Disable the VGA plane that we never use */
8778static void i915_disable_vga(struct drm_device *dev)
8779{
8780 struct drm_i915_private *dev_priv = dev->dev_private;
8781 u8 sr1;
766aa1c4 8782 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8783
8784 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8785 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8786 sr1 = inb(VGA_SR_DATA);
8787 outb(sr1 | 1<<5, VGA_SR_DATA);
8788 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8789 udelay(300);
8790
8791 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8792 POSTING_READ(vga_reg);
8793}
8794
f817586c
DV		 8795void intel_modeset_init_hw(struct drm_device *dev)
8796{
fa42e23c 8797 intel_init_power_well(dev);
0232e927 8798
a8f78b58
ED		 8799 intel_prepare_ddi(dev);
8800
f817586c
DV		 8801 intel_init_clock_gating(dev);
8802
79f5b2c7 8803 mutex_lock(&dev->struct_mutex);
8090c6b9 8804 intel_enable_gt_powersave(dev);
79f5b2c7 8805 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8806}
8807
79e53945
JB		 8808void intel_modeset_init(struct drm_device *dev)
8809{
652c393a 8810 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8811 int i, ret;
79e53945
JB		 8812
8813 drm_mode_config_init(dev);
8814
8815 dev->mode_config.min_width = 0;
8816 dev->mode_config.min_height = 0;
8817
019d96cb
DA		 8818 dev->mode_config.preferred_depth = 24;
8819 dev->mode_config.prefer_shadow = 1;
8820
e6ecefaa 8821 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8822
b690e96c
JB		 8823 intel_init_quirks(dev);
8824
1fa61106
ED		 8825 intel_init_pm(dev);
8826
e70236a8
JB		 8827 intel_init_display(dev);
8828
a6c45cf0
CW		 8829 if (IS_GEN2(dev)) {
8830 dev->mode_config.max_width = 2048;
8831 dev->mode_config.max_height = 2048;
8832 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8833 dev->mode_config.max_width = 4096;
8834 dev->mode_config.max_height = 4096;
79e53945 8835 } else {
a6c45cf0
CW		 8836 dev->mode_config.max_width = 8192;
8837 dev->mode_config.max_height = 8192;
79e53945 8838 }
5d4545ae 8839 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8840
28c97730 8841 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8842 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8843
a3524f1b 8844 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8845 intel_crtc_init(dev, i);
00c2064b
JB		 8846 ret = intel_plane_init(dev, i);
8847 if (ret)
8848 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8849 }
8850
79f689aa 8851 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8852 intel_pch_pll_init(dev);
8853
9cce37f4
JB		 8854 /* Just disable it once at startup */
8855 i915_disable_vga(dev);
79e53945 8856 intel_setup_outputs(dev);
11be49eb
CW		 8857
8858 /* Just in case the BIOS is doing something questionable. */
8859 intel_disable_fbc(dev);
2c7111db
CW		 8860}
8861
24929352
DV		 8862static void
8863intel_connector_break_all_links(struct intel_connector *connector)
8864{
8865 connector->base.dpms = DRM_MODE_DPMS_OFF;
8866 connector->base.encoder = NULL;
8867 connector->encoder->connectors_active = false;
8868 connector->encoder->base.crtc = NULL;
8869}
8870
7fad798e
DV		 8871static void intel_enable_pipe_a(struct drm_device *dev)
8872{
8873 struct intel_connector *connector;
8874 struct drm_connector *crt = NULL;
8875 struct intel_load_detect_pipe load_detect_temp;
8876
8877 /* We can't just switch on the pipe A, we need to set things up with a
8878 * proper mode and output configuration. As a gross hack, enable pipe A
8879 * by enabling the load detect pipe once. */
8880 list_for_each_entry(connector,
8881 &dev->mode_config.connector_list,
8882 base.head) {
8883 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8884 crt = &connector->base;
8885 break;
8886 }
8887 }
8888
8889 if (!crt)
8890 return;
8891
8892 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8893 intel_release_load_detect_pipe(crt, &load_detect_temp);
8894
652c393a 8895
7fad798e
DV		 8896}
8897
fa555837
DV		 8898static bool
8899intel_check_plane_mapping(struct intel_crtc *crtc)
8900{
8901 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8902 u32 reg, val;
8903
8904 if (dev_priv->num_pipe == 1)
8905 return true;
8906
8907 reg = DSPCNTR(!crtc->plane);
8908 val = I915_READ(reg);
8909
8910 if ((val & DISPLAY_PLANE_ENABLE) &&
8911 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8912 return false;
8913
8914 return true;
8915}
8916
24929352
DV		 8917static void intel_sanitize_crtc(struct intel_crtc *crtc)
8918{
8919 struct drm_device *dev = crtc->base.dev;
8920 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8921 u32 reg;
24929352 8922
24929352 8923 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8924 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8925 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8926
8927 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8928 * disable the crtc (and hence change the state) if it is wrong. Note
8929 * that gen4+ has a fixed plane -> pipe mapping. */
8930 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8931 struct intel_connector *connector;
8932 bool plane;
8933
24929352
DV		 8934 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8935 crtc->base.base.id);
8936
8937 /* Pipe has the wrong plane attached and the plane is active.
8938 * Temporarily change the plane mapping and disable everything
8939 * ... */
8940 plane = crtc->plane;
8941 crtc->plane = !plane;
8942 dev_priv->display.crtc_disable(&crtc->base);
8943 crtc->plane = plane;
8944
8945 /* ... and break all links. */
8946 list_for_each_entry(connector, &dev->mode_config.connector_list,
8947 base.head) {
8948 if (connector->encoder->base.crtc != &crtc->base)
8949 continue;
8950
8951 intel_connector_break_all_links(connector);
8952 }
8953
8954 WARN_ON(crtc->active);
8955 crtc->base.enabled = false;
8956 }
24929352 8957
7fad798e
DV		 8958 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8959 crtc->pipe == PIPE_A && !crtc->active) {
8960 /* BIOS forgot to enable pipe A, this mostly happens after
8961 * resume. Force-enable the pipe to fix this, the update_dpms
8962 * call below we restore the pipe to the right state, but leave
8963 * the required bits on. */
8964 intel_enable_pipe_a(dev);
8965 }
8966
24929352
DV		 8967 /* Adjust the state of the output pipe according to whether we
8968 * have active connectors/encoders. */
8969 intel_crtc_update_dpms(&crtc->base);
8970
8971 if (crtc->active != crtc->base.enabled) {
8972 struct intel_encoder *encoder;
8973
8974 /* This can happen either due to bugs in the get_hw_state
8975 * functions or because the pipe is force-enabled due to the
8976 * pipe A quirk. */
8977 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8978 crtc->base.base.id,
8979 crtc->base.enabled ? "enabled" : "disabled",
8980 crtc->active ? "enabled" : "disabled");
8981
8982 crtc->base.enabled = crtc->active;
8983
8984 /* Because we only establish the connector -> encoder ->
8985 * crtc links if something is active, this means the
8986 * crtc is now deactivated. Break the links. connector
8987 * -> encoder links are only establish when things are
8988 * actually up, hence no need to break them. */
8989 WARN_ON(crtc->active);
8990
8991 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8992 WARN_ON(encoder->connectors_active);
8993 encoder->base.crtc = NULL;
8994 }
8995 }
8996}
8997
8998static void intel_sanitize_encoder(struct intel_encoder *encoder)
8999{
9000 struct intel_connector *connector;
9001 struct drm_device *dev = encoder->base.dev;
9002
9003 /* We need to check both for a crtc link (meaning that the
9004 * encoder is active and trying to read from a pipe) and the
9005 * pipe itself being active. */
9006 bool has_active_crtc = encoder->base.crtc &&
9007 to_intel_crtc(encoder->base.crtc)->active;
9008
9009 if (encoder->connectors_active && !has_active_crtc) {
9010 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9011 encoder->base.base.id,
9012 drm_get_encoder_name(&encoder->base));
9013
9014 /* Connector is active, but has no active pipe. This is
9015 * fallout from our resume register restoring. Disable
9016 * the encoder manually again. */
9017 if (encoder->base.crtc) {
9018 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9019 encoder->base.base.id,
9020 drm_get_encoder_name(&encoder->base));
9021 encoder->disable(encoder);
9022 }
9023
9024 /* Inconsistent output/port/pipe state happens presumably due to
9025 * a bug in one of the get_hw_state functions. Or someplace else
9026 * in our code, like the register restore mess on resume. Clamp
9027 * things to off as a safer default. */
9028 list_for_each_entry(connector,
9029 &dev->mode_config.connector_list,
9030 base.head) {
9031 if (connector->encoder != encoder)
9032 continue;
9033
9034 intel_connector_break_all_links(connector);
9035 }
9036 }
9037 /* Enabled encoders without active connectors will be fixed in
9038 * the crtc fixup. */
9039}
9040
44cec740 9041void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9042{
9043 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9044 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9045
9046 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9047 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9048 i915_disable_vga(dev);
0fde901f
KM		 9049 }
9050}
9051
24929352
DV		 9052/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9053 * and i915 state tracking structures. */
45e2b5f6
DV		 9054void intel_modeset_setup_hw_state(struct drm_device *dev,
9055 bool force_restore)
24929352
DV		 9056{
9057 struct drm_i915_private *dev_priv = dev->dev_private;
9058 enum pipe pipe;
9059 u32 tmp;
9060 struct intel_crtc *crtc;
9061 struct intel_encoder *encoder;
9062 struct intel_connector *connector;
9063
affa9354 9064 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9065 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9066
9067 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9068 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9069 case TRANS_DDI_EDP_INPUT_A_ON:
9070 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9071 pipe = PIPE_A;
9072 break;
9073 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9074 pipe = PIPE_B;
9075 break;
9076 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9077 pipe = PIPE_C;
9078 break;
9079 }
9080
9081 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9082 crtc->cpu_transcoder = TRANSCODER_EDP;
9083
9084 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9085 pipe_name(pipe));
9086 }
9087 }
9088
24929352
DV		 9089 for_each_pipe(pipe) {
9090 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9091
702e7a56 9092 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9093 if (tmp & PIPECONF_ENABLE)
9094 crtc->active = true;
9095 else
9096 crtc->active = false;
9097
9098 crtc->base.enabled = crtc->active;
9099
9100 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9101 crtc->base.base.id,
9102 crtc->active ? "enabled" : "disabled");
9103 }
9104
affa9354 9105 if (HAS_DDI(dev))
6441ab5f
PZ		 9106 intel_ddi_setup_hw_pll_state(dev);
9107
24929352
DV		 9108 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9109 base.head) {
9110 pipe = 0;
9111
9112 if (encoder->get_hw_state(encoder, &pipe)) {
9113 encoder->base.crtc =
9114 dev_priv->pipe_to_crtc_mapping[pipe];
9115 } else {
9116 encoder->base.crtc = NULL;
9117 }
9118
9119 encoder->connectors_active = false;
9120 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9121 encoder->base.base.id,
9122 drm_get_encoder_name(&encoder->base),
9123 encoder->base.crtc ? "enabled" : "disabled",
9124 pipe);
9125 }
9126
9127 list_for_each_entry(connector, &dev->mode_config.connector_list,
9128 base.head) {
9129 if (connector->get_hw_state(connector)) {
9130 connector->base.dpms = DRM_MODE_DPMS_ON;
9131 connector->encoder->connectors_active = true;
9132 connector->base.encoder = &connector->encoder->base;
9133 } else {
9134 connector->base.dpms = DRM_MODE_DPMS_OFF;
9135 connector->base.encoder = NULL;
9136 }
9137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9138 connector->base.base.id,
9139 drm_get_connector_name(&connector->base),
9140 connector->base.encoder ? "enabled" : "disabled");
9141 }
9142
9143 /* HW state is read out, now we need to sanitize this mess. */
9144 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9145 base.head) {
9146 intel_sanitize_encoder(encoder);
9147 }
9148
9149 for_each_pipe(pipe) {
9150 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9151 intel_sanitize_crtc(crtc);
9152 }
9a935856 9153
45e2b5f6
DV		 9154 if (force_restore) {
9155 for_each_pipe(pipe) {
c0c36b94 9156 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9157 }
0fde901f
KM		 9158
9159 i915_redisable_vga(dev);
45e2b5f6
DV		 9160 } else {
9161 intel_modeset_update_staged_output_state(dev);
9162 }
8af6cf88
DV		 9163
9164 intel_modeset_check_state(dev);
2e938892
DV		 9165
9166 drm_mode_config_reset(dev);
2c7111db
CW		 9167}
9168
9169void intel_modeset_gem_init(struct drm_device *dev)
9170{
1833b134 9171 intel_modeset_init_hw(dev);
02e792fb
DV		 9172
9173 intel_setup_overlay(dev);
24929352 9174
45e2b5f6 9175 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9176}
9177
9178void intel_modeset_cleanup(struct drm_device *dev)
9179{
652c393a
JB		 9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 struct drm_crtc *crtc;
9182 struct intel_crtc *intel_crtc;
9183
f87ea761 9184 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9185 mutex_lock(&dev->struct_mutex);
9186
723bfd70
JB		 9187 intel_unregister_dsm_handler();
9188
9189
652c393a
JB		 9190 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9191 /* Skip inactive CRTCs */
9192 if (!crtc->fb)
9193 continue;
9194
9195 intel_crtc = to_intel_crtc(crtc);
3dec0095 9196 intel_increase_pllclock(crtc);
652c393a
JB		 9197 }
9198
973d04f9 9199 intel_disable_fbc(dev);
e70236a8 9200
8090c6b9 9201 intel_disable_gt_powersave(dev);
0cdab21f 9202
930ebb46
DV		 9203 ironlake_teardown_rc6(dev);
9204
57f350b6
JB		 9205 if (IS_VALLEYVIEW(dev))
9206 vlv_init_dpio(dev);
9207
69341a5e
KH		 9208 mutex_unlock(&dev->struct_mutex);
9209
6c0d9350
DV		 9210 /* Disable the irq before mode object teardown, for the irq might
9211 * enqueue unpin/hotplug work. */
9212 drm_irq_uninstall(dev);
9213 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9214 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9215
1630fe75
CW		 9216 /* flush any delayed tasks or pending work */
9217 flush_scheduled_work();
9218
79e53945 9219 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9220
9221 intel_cleanup_overlay(dev);
79e53945
JB		 9222}
9223
f1c79df3
ZW		 9224/*
9225 * Return which encoder is currently attached for connector.
9226 */
df0e9248 9227struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9228{
df0e9248
CW		 9229 return &intel_attached_encoder(connector)->base;
9230}
f1c79df3 9231
df0e9248
CW		 9232void intel_connector_attach_encoder(struct intel_connector *connector,
9233 struct intel_encoder *encoder)
9234{
9235 connector->encoder = encoder;
9236 drm_mode_connector_attach_encoder(&connector->base,
9237 &encoder->base);
79e53945 9238}
28d52043
DA		 9239
9240/*
9241 * set vga decode state - true == enable VGA decode
9242 */
9243int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9244{
9245 struct drm_i915_private *dev_priv = dev->dev_private;
9246 u16 gmch_ctrl;
9247
9248 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9249 if (state)
9250 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9251 else
9252 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9253 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9254 return 0;
9255}
c4a1d9e4
CW		 9256
9257#ifdef CONFIG_DEBUG_FS
9258#include <linux/seq_file.h>
9259
9260struct intel_display_error_state {
9261 struct intel_cursor_error_state {
9262 u32 control;
9263 u32 position;
9264 u32 base;
9265 u32 size;
52331309 9266 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9267
9268 struct intel_pipe_error_state {
9269 u32 conf;
9270 u32 source;
9271
9272 u32 htotal;
9273 u32 hblank;
9274 u32 hsync;
9275 u32 vtotal;
9276 u32 vblank;
9277 u32 vsync;
52331309 9278 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9279
9280 struct intel_plane_error_state {
9281 u32 control;
9282 u32 stride;
9283 u32 size;
9284 u32 pos;
9285 u32 addr;
9286 u32 surface;
9287 u32 tile_offset;
52331309 9288 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9289};
9290
9291struct intel_display_error_state *
9292intel_display_capture_error_state(struct drm_device *dev)
9293{
0206e353 9294 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9295 struct intel_display_error_state *error;
702e7a56 9296 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9297 int i;
9298
9299 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9300 if (error == NULL)
9301 return NULL;
9302
52331309 9303 for_each_pipe(i) {
702e7a56
PZ		 9304 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9305
c4a1d9e4
CW		 9306 error->cursor[i].control = I915_READ(CURCNTR(i));
9307 error->cursor[i].position = I915_READ(CURPOS(i));
9308 error->cursor[i].base = I915_READ(CURBASE(i));
9309
9310 error->plane[i].control = I915_READ(DSPCNTR(i));
9311 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9312 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9313 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9314 error->plane[i].addr = I915_READ(DSPADDR(i));
9315 if (INTEL_INFO(dev)->gen >= 4) {
9316 error->plane[i].surface = I915_READ(DSPSURF(i));
9317 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9318 }
9319
702e7a56 9320 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9321 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9322 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9323 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9324 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9325 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9326 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9327 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9328 }
9329
9330 return error;
9331}
9332
9333void
9334intel_display_print_error_state(struct seq_file *m,
9335 struct drm_device *dev,
9336 struct intel_display_error_state *error)
9337{
52331309 9338 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9339 int i;
9340
52331309
DL		 9341 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9342 for_each_pipe(i) {
c4a1d9e4
CW		 9343 seq_printf(m, "Pipe [%d]:\n", i);
9344 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9345 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9346 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9347 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9348 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9349 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9350 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9351 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9352
9353 seq_printf(m, "Plane [%d]:\n", i);
9354 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9355 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9356 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9357 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9358 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9359 if (INTEL_INFO(dev)->gen >= 4) {
9360 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9361 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9362 }
9363
9364 seq_printf(m, "Cursor [%d]:\n", i);
9365 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9366 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9367 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9368 }
9369}
9370#endif
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