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drm/i915: fix PLL assertions for DSI PLL
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
2377b741
JB		 72/* FDI */
73#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
74
d2acd215
DV		 75int
76intel_pch_rawclk(struct drm_device *dev)
77{
78 struct drm_i915_private *dev_priv = dev->dev_private;
79
80 WARN_ON(!HAS_PCH_SPLIT(dev));
81
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
83}
84
021357ac
CW		 85static inline u32 /* units of 100MHz */
86intel_fdi_link_freq(struct drm_device *dev)
87{
8b99e68c
CW		 88 if (IS_GEN5(dev)) {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 } else
92 return 27;
021357ac
CW		 93}
94
5d536e28 95static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 106};
107
5d536e28
DV		 108static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
119};
120
e4b36699 121static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 145};
146
147static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 158};
159
273e27ca 160
e4b36699 161static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
171 .p2_slow = 10,
172 .p2_fast = 10
044c7c41 173 },
e4b36699
KP		 174};
175
176static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
044c7c41 200 },
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
044c7c41 214 },
e4b36699
KP		 215};
216
f2b115e6 217static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 220 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
273e27ca 223 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 230};
231
f2b115e6 232static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 243};
244
273e27ca
EA		 245/* Ironlake / Sandybridge
246 *
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
249 */
b91ad0ec 250static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 261};
262
b91ad0ec 263static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 274};
275
276static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 287};
288
273e27ca 289/* LVDS 100mhz refclk limits. */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
0206e353 298 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 301};
302
303static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
0206e353 311 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 314};
315
a0c4da24
JB		 316static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
75e53986 324 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 327};
328
329static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 340};
341
342static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 345 .n = { .min = 1, .max = 7 },
74a4dd2e 346 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 353};
354
1b894b59
CW		 355static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 int refclk)
2c07245f 357{
b91ad0ec 358 struct drm_device *dev = crtc->dev;
2c07245f 359 const intel_limit_t *limit;
b91ad0ec
ZW		 360
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 362 if (intel_is_dual_link_lvds(dev)) {
1b894b59 363 if (refclk == 100000)
b91ad0ec
ZW		 364 limit = &intel_limits_ironlake_dual_lvds_100m;
365 else
366 limit = &intel_limits_ironlake_dual_lvds;
367 } else {
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_single_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_single_lvds;
372 }
c6bb3538 373 } else
b91ad0ec 374 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 375
376 return limit;
377}
378
044c7c41
ML		 379static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
380{
381 struct drm_device *dev = crtc->dev;
044c7c41
ML		 382 const intel_limit_t *limit;
383
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 385 if (intel_is_dual_link_lvds(dev))
e4b36699 386 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 387 else
e4b36699 388 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 391 limit = &intel_limits_g4x_hdmi;
044c7c41 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 393 limit = &intel_limits_g4x_sdvo;
044c7c41 394 } else /* The option is for other outputs */
e4b36699 395 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 396
397 return limit;
398}
399
1b894b59 400static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 401{
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
404
bad720ff 405 if (HAS_PCH_SPLIT(dev))
1b894b59 406 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 407 else if (IS_G4X(dev)) {
044c7c41 408 limit = intel_g4x_limit(crtc);
f2b115e6 409 } else if (IS_PINEVIEW(dev)) {
2177832f 410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 411 limit = &intel_limits_pineview_lvds;
2177832f 412 else
f2b115e6 413 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
419 else
420 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
424 else
425 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 426 } else {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 428 limit = &intel_limits_i8xx_lvds;
5d536e28 429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 430 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 431 else
432 limit = &intel_limits_i8xx_dac;
79e53945
JB		 433 }
434 return limit;
435}
436
f2b115e6
AJ		 437/* m1 is reserved as 0 in Pineview, n is a ring counter */
438static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 439{
2177832f
SL		 440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
444}
445
7429e9d4
DV		 446static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
447{
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449}
450
ac58c3f0 451static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 452{
7429e9d4 453 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
457}
458
79e53945
JB		 459/**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
4ef69c7a 462bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 463{
4ef69c7a 464 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 465 struct intel_encoder *encoder;
466
6c2b7c12
DV		 467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
4ef69c7a
CW		 469 return true;
470
471 return false;
79e53945
JB		 472}
473
7c04d1d9 474#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 475/**
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
478 */
479
1b894b59
CW		 480static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
79e53945 483{
79e53945 484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 485 INTELPllInvalid("p1 out of range\n");
79e53945 486 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 487 INTELPllInvalid("p out of range\n");
79e53945 488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 489 INTELPllInvalid("m2 out of range\n");
79e53945 490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 491 INTELPllInvalid("m1 out of range\n");
f2b115e6 492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 493 INTELPllInvalid("m1 <= m2\n");
79e53945 494 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 495 INTELPllInvalid("m out of range\n");
79e53945 496 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 497 INTELPllInvalid("n out of range\n");
79e53945 498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 499 INTELPllInvalid("vco out of range\n");
79e53945
JB		 500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
502 */
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 504 INTELPllInvalid("dot out of range\n");
79e53945
JB		 505
506 return true;
507}
508
d4906093 509static bool
ee9300bb 510i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
79e53945
JB		 513{
514 struct drm_device *dev = crtc->dev;
79e53945 515 intel_clock_t clock;
79e53945
JB		 516 int err = target;
517
a210b028 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 519 /*
a210b028
DV		 520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
79e53945 523 */
1974cad0 524 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 525 clock.p2 = limit->p2.p2_fast;
526 else
527 clock.p2 = limit->p2.p2_slow;
528 } else {
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
531 else
532 clock.p2 = limit->p2.p2_fast;
533 }
534
0206e353 535 memset(best_clock, 0, sizeof(*best_clock));
79e53945 536
42158660
ZY		 537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
538 clock.m1++) {
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 541 if (clock.m2 >= clock.m1)
42158660
ZY		 542 break;
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 547 int this_err;
548
ac58c3f0
DV		 549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
551 &clock))
552 continue;
553 if (match_clock &&
554 clock.p != match_clock->p)
555 continue;
556
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
559 *best_clock = clock;
560 err = this_err;
561 }
562 }
563 }
564 }
565 }
566
567 return (err != target);
568}
569
570static bool
ee9300bb
DV		 571pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
79e53945
JB		 574{
575 struct drm_device *dev = crtc->dev;
79e53945 576 intel_clock_t clock;
79e53945
JB		 577 int err = target;
578
a210b028 579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 580 /*
a210b028
DV		 581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
79e53945 584 */
1974cad0 585 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 586 clock.p2 = limit->p2.p2_fast;
587 else
588 clock.p2 = limit->p2.p2_slow;
589 } else {
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
592 else
593 clock.p2 = limit->p2.p2_fast;
594 }
595
0206e353 596 memset(best_clock, 0, sizeof(*best_clock));
79e53945 597
42158660
ZY		 598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
599 clock.m1++) {
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 606 int this_err;
607
ac58c3f0 608 pineview_clock(refclk, &clock);
1b894b59
CW		 609 if (!intel_PLL_is_valid(dev, limit,
610 &clock))
79e53945 611 continue;
cec2f356
SP		 612 if (match_clock &&
613 clock.p != match_clock->p)
614 continue;
79e53945
JB		 615
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
618 *best_clock = clock;
619 err = this_err;
620 }
621 }
622 }
623 }
624 }
625
626 return (err != target);
627}
628
d4906093 629static bool
ee9300bb
DV		 630g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
d4906093
ML		 633{
634 struct drm_device *dev = crtc->dev;
d4906093
ML		 635 intel_clock_t clock;
636 int max_n;
637 bool found;
6ba770dc
AJ		 638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 640 found = false;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 643 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 644 clock.p2 = limit->p2.p2_fast;
645 else
646 clock.p2 = limit->p2.p2_slow;
647 } else {
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
650 else
651 clock.p2 = limit->p2.p2_fast;
652 }
653
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
f77f13e2 656 /* based on hardware requirement, prefer smaller n to precision */
d4906093 657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 658 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
665 int this_err;
666
ac58c3f0 667 i9xx_clock(refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
d4906093 670 continue;
1b894b59
CW		 671
672 this_err = abs(clock.dot - target);
d4906093
ML		 673 if (this_err < err_most) {
674 *best_clock = clock;
675 err_most = this_err;
676 max_n = clock.n;
677 found = true;
678 }
679 }
680 }
681 }
682 }
2c07245f
ZW		 683 return found;
684}
685
a0c4da24 686static bool
ee9300bb
DV		 687vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
a0c4da24
JB		 690{
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
692 u32 m, n, fastclk;
f3f08572 693 u32 updrate, minupdate, p;
a0c4da24
JB		 694 unsigned long bestppm, ppm, absppm;
695 int dotclk, flag;
696
af447bd3 697 flag = 0;
a0c4da24
JB		 698 dotclk = target * 1000;
699 bestppm = 1000000;
700 ppm = absppm = 0;
701 fastclk = dotclk / (2*100);
702 updrate = 0;
703 minupdate = 19200;
a0c4da24
JB		 704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
706
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
712 if (p2 > 10)
713 p2 = p2 - 1;
714 p = p1 * p2;
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
719 m = m1 * m2;
720 vco = updrate * m;
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
725 bestppm = 0;
726 flag = 1;
727 }
728 if (absppm < bestppm - 10) {
729 bestppm = absppm;
730 flag = 1;
731 }
732 if (flag) {
733 bestn = n;
734 bestm1 = m1;
735 bestm2 = m2;
736 bestp1 = p1;
737 bestp2 = p2;
738 flag = 0;
739 }
740 }
741 }
742 }
743 }
744 }
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
750
751 return true;
752}
a4fc5ed6 753
a5c961d1
PZ		 754enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
755 enum pipe pipe)
756{
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759
3b117c8f 760 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 761}
762
a928d536
PZ		 763static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764{
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
767
768 frame = I915_READ(frame_reg);
769
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
772}
773
9d0498a2
JB		 774/**
775 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @dev: drm device
777 * @pipe: pipe to wait for
778 *
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 * mode setting code.
781 */
782void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 783{
9d0498a2 784 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 785 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 786
a928d536
PZ		 787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
789 return;
790 }
791
300387c0
CW		 792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
794 *
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
801 * vblanks...
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
804 */
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807
9d0498a2 808 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
811 50))
9d0498a2
JB		 812 DRM_DEBUG_KMS("vblank wait timed out\n");
813}
814
ab7ad7f6
KP		 815/*
816 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 817 * @dev: drm device
818 * @pipe: pipe to wait for
819 *
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
823 *
ab7ad7f6
KP		 824 * On Gen4 and above:
825 * wait for the pipe register state bit to turn off
826 *
827 * Otherwise:
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
58e10eb9 830 *
9d0498a2 831 */
58e10eb9 832void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
836 pipe);
ab7ad7f6
KP		 837
838 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 839 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 840
841 /* Wait for the Pipe State to go off */
58e10eb9
CW		 842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 100))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 } else {
837ba00f 846 u32 last_line, line_mask;
58e10eb9 847 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
849
837ba00f
PZ		 850 if (IS_GEN2(dev))
851 line_mask = DSL_LINEMASK_GEN2;
852 else
853 line_mask = DSL_LINEMASK_GEN3;
854
ab7ad7f6
KP		 855 /* Wait for the display line to settle */
856 do {
837ba00f 857 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 858 mdelay(5);
837ba00f 859 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 }
79e53945
JB		 864}
865
b0ea7d37
DL		 866/*
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
870 *
871 * Returns true if @port is connected, false otherwise.
872 */
873bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
875{
876 u32 bit;
877
c36346e3
DL		 878 if (HAS_PCH_IBX(dev_priv->dev)) {
879 switch(port->port) {
880 case PORT_B:
881 bit = SDE_PORTB_HOTPLUG;
882 break;
883 case PORT_C:
884 bit = SDE_PORTC_HOTPLUG;
885 break;
886 case PORT_D:
887 bit = SDE_PORTD_HOTPLUG;
888 break;
889 default:
890 return true;
891 }
892 } else {
893 switch(port->port) {
894 case PORT_B:
895 bit = SDE_PORTB_HOTPLUG_CPT;
896 break;
897 case PORT_C:
898 bit = SDE_PORTC_HOTPLUG_CPT;
899 break;
900 case PORT_D:
901 bit = SDE_PORTD_HOTPLUG_CPT;
902 break;
903 default:
904 return true;
905 }
b0ea7d37
DL		 906 }
907
908 return I915_READ(SDEISR) & bit;
909}
910
b24e7179
JB		 911static const char *state_string(bool enabled)
912{
913 return enabled ? "on" : "off";
914}
915
916/* Only for pre-ILK configs */
55607e8a
DV		 917void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
b24e7179
JB		 919{
920 int reg;
921 u32 val;
922 bool cur_state;
923
924 reg = DPLL(pipe);
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
930}
b24e7179 931
23538ef1
JN		 932/* XXX: the dsi pll is shared between MIPI DSI ports */
933static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
934{
935 u32 val;
936 bool cur_state;
937
938 mutex_lock(&dev_priv->dpio_lock);
939 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
940 mutex_unlock(&dev_priv->dpio_lock);
941
942 cur_state = val & DSI_PLL_VCO_EN;
943 WARN(cur_state != state,
944 "DSI PLL state assertion failure (expected %s, current %s)\n",
945 state_string(state), state_string(cur_state));
946}
947#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
948#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949
55607e8a 950struct intel_shared_dpll *
e2b78267
DV		 951intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952{
953 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954
a43f6e0f 955 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 956 return NULL;
957
a43f6e0f 958 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 959}
960
040484af 961/* For ILK+ */
55607e8a
DV		 962void assert_shared_dpll(struct drm_i915_private *dev_priv,
963 struct intel_shared_dpll *pll,
964 bool state)
040484af 965{
040484af 966 bool cur_state;
5358901f 967 struct intel_dpll_hw_state hw_state;
040484af 968
9d82aa17
ED		 969 if (HAS_PCH_LPT(dev_priv->dev)) {
970 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
971 return;
972 }
973
92b27b08 974 if (WARN (!pll,
46edb027 975 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 976 return;
ee7b9f93 977
5358901f 978 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 979 WARN(cur_state != state,
5358901f
DV		 980 "%s assertion failure (expected %s, current %s)\n",
981 pll->name, state_string(state), state_string(cur_state));
040484af 982}
040484af
JB		 983
984static void assert_fdi_tx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
ad80a810
PZ		 990 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
991 pipe);
040484af 992
affa9354
PZ		 993 if (HAS_DDI(dev_priv->dev)) {
994 /* DDI does not have a specific FDI_TX register */
ad80a810 995 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 996 val = I915_READ(reg);
ad80a810 997 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 998 } else {
999 reg = FDI_TX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_TX_ENABLE);
1002 }
040484af
JB		 1003 WARN(cur_state != state,
1004 "FDI TX state assertion failure (expected %s, current %s)\n",
1005 state_string(state), state_string(cur_state));
1006}
1007#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1008#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009
1010static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1011 enum pipe pipe, bool state)
1012{
1013 int reg;
1014 u32 val;
1015 bool cur_state;
1016
d63fa0dc
PZ		 1017 reg = FDI_RX_CTL(pipe);
1018 val = I915_READ(reg);
1019 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1020 WARN(cur_state != state,
1021 "FDI RX state assertion failure (expected %s, current %s)\n",
1022 state_string(state), state_string(cur_state));
1023}
1024#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1025#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026
1027static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029{
1030 int reg;
1031 u32 val;
1032
1033 /* ILK FDI PLL is always enabled */
1034 if (dev_priv->info->gen == 5)
1035 return;
1036
bf507ef7 1037 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1038 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1039 return;
1040
040484af
JB		 1041 reg = FDI_TX_CTL(pipe);
1042 val = I915_READ(reg);
1043 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1044}
1045
55607e8a
DV		 1046void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1047 enum pipe pipe, bool state)
040484af
JB		 1048{
1049 int reg;
1050 u32 val;
55607e8a 1051 bool cur_state;
040484af
JB		 1052
1053 reg = FDI_RX_CTL(pipe);
1054 val = I915_READ(reg);
55607e8a
DV		 1055 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1056 WARN(cur_state != state,
1057 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1058 state_string(state), state_string(cur_state));
040484af
JB		 1059}
1060
ea0760cf
JB		 1061static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1062 enum pipe pipe)
1063{
1064 int pp_reg, lvds_reg;
1065 u32 val;
1066 enum pipe panel_pipe = PIPE_A;
0de3b485 1067 bool locked = true;
ea0760cf
JB		 1068
1069 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1070 pp_reg = PCH_PP_CONTROL;
1071 lvds_reg = PCH_LVDS;
1072 } else {
1073 pp_reg = PP_CONTROL;
1074 lvds_reg = LVDS;
1075 }
1076
1077 val = I915_READ(pp_reg);
1078 if (!(val & PANEL_POWER_ON) ||
1079 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1080 locked = false;
1081
1082 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1083 panel_pipe = PIPE_B;
1084
1085 WARN(panel_pipe == pipe && locked,
1086 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1087 pipe_name(pipe));
ea0760cf
JB		 1088}
1089
b840d907
JB		 1090void assert_pipe(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, bool state)
b24e7179
JB		 1092{
1093 int reg;
1094 u32 val;
63d7bbe9 1095 bool cur_state;
702e7a56
PZ		 1096 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1097 pipe);
b24e7179 1098
8e636784
DV		 1099 /* if we need the pipe A quirk it must be always on */
1100 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1101 state = true;
1102
b97186f0
PZ		 1103 if (!intel_display_power_enabled(dev_priv->dev,
1104 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1105 cur_state = false;
1106 } else {
1107 reg = PIPECONF(cpu_transcoder);
1108 val = I915_READ(reg);
1109 cur_state = !!(val & PIPECONF_ENABLE);
1110 }
1111
63d7bbe9
JB		 1112 WARN(cur_state != state,
1113 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1114 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1115}
1116
931872fc
CW		 1117static void assert_plane(struct drm_i915_private *dev_priv,
1118 enum plane plane, bool state)
b24e7179
JB		 1119{
1120 int reg;
1121 u32 val;
931872fc 1122 bool cur_state;
b24e7179
JB		 1123
1124 reg = DSPCNTR(plane);
1125 val = I915_READ(reg);
931872fc
CW		 1126 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1127 WARN(cur_state != state,
1128 "plane %c assertion failure (expected %s, current %s)\n",
1129 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1130}
1131
931872fc
CW		 1132#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1133#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1134
b24e7179
JB		 1135static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1136 enum pipe pipe)
1137{
653e1026 1138 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1139 int reg, i;
1140 u32 val;
1141 int cur_pipe;
1142
653e1026
VS		 1143 /* Primary planes are fixed to pipes on gen4+ */
1144 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1145 reg = DSPCNTR(pipe);
1146 val = I915_READ(reg);
1147 WARN((val & DISPLAY_PLANE_ENABLE),
1148 "plane %c assertion failure, should be disabled but not\n",
1149 plane_name(pipe));
19ec1358 1150 return;
28c05794 1151 }
19ec1358 1152
b24e7179 1153 /* Need to check both planes against the pipe */
08e2a7de 1154 for_each_pipe(i) {
b24e7179
JB		 1155 reg = DSPCNTR(i);
1156 val = I915_READ(reg);
1157 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1158 DISPPLANE_SEL_PIPE_SHIFT;
1159 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1160 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1161 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1162 }
1163}
1164
19332d7a
JB		 1165static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
20674eef 1168 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1169 int reg, i;
1170 u32 val;
1171
20674eef
VS		 1172 if (IS_VALLEYVIEW(dev)) {
1173 for (i = 0; i < dev_priv->num_plane; i++) {
1174 reg = SPCNTR(pipe, i);
1175 val = I915_READ(reg);
1176 WARN((val & SP_ENABLE),
1177 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1178 sprite_name(pipe, i), pipe_name(pipe));
1179 }
1180 } else if (INTEL_INFO(dev)->gen >= 7) {
1181 reg = SPRCTL(pipe);
19332d7a 1182 val = I915_READ(reg);
20674eef 1183 WARN((val & SPRITE_ENABLE),
06da8da2 1184 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1185 plane_name(pipe), pipe_name(pipe));
1186 } else if (INTEL_INFO(dev)->gen >= 5) {
1187 reg = DVSCNTR(pipe);
19332d7a 1188 val = I915_READ(reg);
20674eef 1189 WARN((val & DVS_ENABLE),
06da8da2 1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1191 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1192 }
1193}
1194
92f2584a
JB		 1195static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1196{
1197 u32 val;
1198 bool enabled;
1199
9d82aa17
ED		 1200 if (HAS_PCH_LPT(dev_priv->dev)) {
1201 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1202 return;
1203 }
1204
92f2584a
JB		 1205 val = I915_READ(PCH_DREF_CONTROL);
1206 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1207 DREF_SUPERSPREAD_SOURCE_MASK));
1208 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1209}
1210
ab9412ba
DV		 1211static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1212 enum pipe pipe)
92f2584a
JB		 1213{
1214 int reg;
1215 u32 val;
1216 bool enabled;
1217
ab9412ba 1218 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1219 val = I915_READ(reg);
1220 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1221 WARN(enabled,
1222 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1223 pipe_name(pipe));
92f2584a
JB		 1224}
1225
4e634389
KP		 1226static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1228{
1229 if ((val & DP_PORT_EN) == 0)
1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
1233 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1234 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1235 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1236 return false;
1237 } else {
1238 if ((val & DP_PIPE_MASK) != (pipe << 30))
1239 return false;
1240 }
1241 return true;
1242}
1243
1519b995
KP		 1244static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1245 enum pipe pipe, u32 val)
1246{
dc0fa718 1247 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1248 return false;
1249
1250 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1251 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1252 return false;
1253 } else {
dc0fa718 1254 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1255 return false;
1256 }
1257 return true;
1258}
1259
1260static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe, u32 val)
1262{
1263 if ((val & LVDS_PORT_EN) == 0)
1264 return false;
1265
1266 if (HAS_PCH_CPT(dev_priv->dev)) {
1267 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1268 return false;
1269 } else {
1270 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1271 return false;
1272 }
1273 return true;
1274}
1275
1276static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, u32 val)
1278{
1279 if ((val & ADPA_DAC_ENABLE) == 0)
1280 return false;
1281 if (HAS_PCH_CPT(dev_priv->dev)) {
1282 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283 return false;
1284 } else {
1285 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1286 return false;
1287 }
1288 return true;
1289}
1290
291906f1 1291static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1292 enum pipe pipe, int reg, u32 port_sel)
291906f1 1293{
47a05eca 1294 u32 val = I915_READ(reg);
4e634389 1295 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1296 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 reg, pipe_name(pipe));
de9a35ab 1298
75c5da27
DV		 1299 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1300 && (val & DP_PIPEB_SELECT),
de9a35ab 1301 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1302}
1303
1304static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, int reg)
1306{
47a05eca 1307 u32 val = I915_READ(reg);
b70ad586 1308 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1309 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1310 reg, pipe_name(pipe));
de9a35ab 1311
dc0fa718 1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1313 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1314 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1315}
1316
1317static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe)
1319{
1320 int reg;
1321 u32 val;
291906f1 1322
f0575e92
KP		 1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1324 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1326
1327 reg = PCH_ADPA;
1328 val = I915_READ(reg);
b70ad586 1329 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1330 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1331 pipe_name(pipe));
291906f1
JB		 1332
1333 reg = PCH_LVDS;
1334 val = I915_READ(reg);
b70ad586 1335 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1336 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1337 pipe_name(pipe));
291906f1 1338
e2debe91
PZ		 1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1340 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1342}
1343
426115cf 1344static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1345{
426115cf
DV		 1346 struct drm_device *dev = crtc->base.dev;
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 int reg = DPLL(crtc->pipe);
1349 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1350
426115cf 1351 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1352
1353 /* No really, not for ILK+ */
1354 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1355
1356 /* PLL is protected by panel, make sure we can write it */
1357 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1358 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1359
426115cf
DV		 1360 I915_WRITE(reg, dpll);
1361 POSTING_READ(reg);
1362 udelay(150);
1363
1364 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1365 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1366
1367 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1368 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1369
1370 /* We do this three times for luck */
426115cf 1371 I915_WRITE(reg, dpll);
87442f73
DV		 1372 POSTING_READ(reg);
1373 udelay(150); /* wait for warmup */
426115cf 1374 I915_WRITE(reg, dpll);
87442f73
DV		 1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
426115cf 1377 I915_WRITE(reg, dpll);
87442f73
DV		 1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380}
1381
66e3d5c0 1382static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1383{
66e3d5c0
DV		 1384 struct drm_device *dev = crtc->base.dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 int reg = DPLL(crtc->pipe);
1387 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1388
66e3d5c0 1389 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1390
63d7bbe9 1391 /* No really, not for ILK+ */
87442f73 1392 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1393
1394 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1395 if (IS_MOBILE(dev) && !IS_I830(dev))
1396 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1397
66e3d5c0
DV		 1398 I915_WRITE(reg, dpll);
1399
1400 /* Wait for the clocks to stabilize. */
1401 POSTING_READ(reg);
1402 udelay(150);
1403
1404 if (INTEL_INFO(dev)->gen >= 4) {
1405 I915_WRITE(DPLL_MD(crtc->pipe),
1406 crtc->config.dpll_hw_state.dpll_md);
1407 } else {
1408 /* The pixel multiplier can only be updated once the
1409 * DPLL is enabled and the clocks are stable.
1410 *
1411 * So write it again.
1412 */
1413 I915_WRITE(reg, dpll);
1414 }
63d7bbe9
JB		 1415
1416 /* We do this three times for luck */
66e3d5c0 1417 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1418 POSTING_READ(reg);
1419 udelay(150); /* wait for warmup */
66e3d5c0 1420 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1421 POSTING_READ(reg);
1422 udelay(150); /* wait for warmup */
66e3d5c0 1423 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1424 POSTING_READ(reg);
1425 udelay(150); /* wait for warmup */
1426}
1427
1428/**
50b44a44 1429 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1430 * @dev_priv: i915 private structure
1431 * @pipe: pipe PLL to disable
1432 *
1433 * Disable the PLL for @pipe, making sure the pipe is off first.
1434 *
1435 * Note! This is for pre-ILK only.
1436 */
50b44a44 1437static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1438{
63d7bbe9
JB		 1439 /* Don't disable pipe A or pipe A PLLs if needed */
1440 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1441 return;
1442
1443 /* Make sure the pipe isn't still relying on us */
1444 assert_pipe_disabled(dev_priv, pipe);
1445
50b44a44
DV		 1446 I915_WRITE(DPLL(pipe), 0);
1447 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1448}
1449
89b667f8
JB		 1450void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1451{
1452 u32 port_mask;
1453
1454 if (!port)
1455 port_mask = DPLL_PORTB_READY_MASK;
1456 else
1457 port_mask = DPLL_PORTC_READY_MASK;
1458
1459 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1460 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1461 'B' + port, I915_READ(DPLL(0)));
1462}
1463
92f2584a 1464/**
e72f9fbf 1465 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1466 * @dev_priv: i915 private structure
1467 * @pipe: pipe PLL to enable
1468 *
1469 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1470 * drives the transcoder clock.
1471 */
e2b78267 1472static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1473{
e2b78267
DV		 1474 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1475 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1476
48da64a8 1477 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1478 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1479 if (WARN_ON(pll == NULL))
48da64a8
CW		 1480 return;
1481
1482 if (WARN_ON(pll->refcount == 0))
1483 return;
ee7b9f93 1484
46edb027
DV		 1485 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1486 pll->name, pll->active, pll->on,
e2b78267 1487 crtc->base.base.id);
92f2584a 1488
cdbd2316
DV		 1489 if (pll->active++) {
1490 WARN_ON(!pll->on);
e9d6944e 1491 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1492 return;
1493 }
f4a091c7 1494 WARN_ON(pll->on);
ee7b9f93 1495
46edb027 1496 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1497 pll->enable(dev_priv, pll);
ee7b9f93 1498 pll->on = true;
92f2584a
JB		 1499}
1500
e2b78267 1501static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1502{
e2b78267
DV		 1503 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1504 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1505
92f2584a
JB		 1506 /* PCH only available on ILK+ */
1507 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1508 if (WARN_ON(pll == NULL))
ee7b9f93 1509 return;
92f2584a 1510
48da64a8
CW		 1511 if (WARN_ON(pll->refcount == 0))
1512 return;
7a419866 1513
46edb027
DV		 1514 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1515 pll->name, pll->active, pll->on,
e2b78267 1516 crtc->base.base.id);
7a419866 1517
48da64a8 1518 if (WARN_ON(pll->active == 0)) {
e9d6944e 1519 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1520 return;
1521 }
1522
e9d6944e 1523 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1524 WARN_ON(!pll->on);
cdbd2316 1525 if (--pll->active)
7a419866 1526 return;
ee7b9f93 1527
46edb027 1528 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1529 pll->disable(dev_priv, pll);
ee7b9f93 1530 pll->on = false;
92f2584a
JB		 1531}
1532
b8a4f404
PZ		 1533static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1534 enum pipe pipe)
040484af 1535{
23670b32 1536 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1537 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1539 uint32_t reg, val, pipeconf_val;
040484af
JB		 1540
1541 /* PCH only available on ILK+ */
1542 BUG_ON(dev_priv->info->gen < 5);
1543
1544 /* Make sure PCH DPLL is enabled */
e72f9fbf 1545 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1546 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1547
1548 /* FDI must be feeding us bits for PCH ports */
1549 assert_fdi_tx_enabled(dev_priv, pipe);
1550 assert_fdi_rx_enabled(dev_priv, pipe);
1551
23670b32
DV		 1552 if (HAS_PCH_CPT(dev)) {
1553 /* Workaround: Set the timing override bit before enabling the
1554 * pch transcoder. */
1555 reg = TRANS_CHICKEN2(pipe);
1556 val = I915_READ(reg);
1557 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1558 I915_WRITE(reg, val);
59c859d6 1559 }
23670b32 1560
ab9412ba 1561 reg = PCH_TRANSCONF(pipe);
040484af 1562 val = I915_READ(reg);
5f7f726d 1563 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1564
1565 if (HAS_PCH_IBX(dev_priv->dev)) {
1566 /*
1567 * make the BPC in transcoder be consistent with
1568 * that in pipeconf reg.
1569 */
dfd07d72
DV		 1570 val &= ~PIPECONF_BPC_MASK;
1571 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1572 }
5f7f726d
PZ		 1573
1574 val &= ~TRANS_INTERLACE_MASK;
1575 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1576 if (HAS_PCH_IBX(dev_priv->dev) &&
1577 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1578 val |= TRANS_LEGACY_INTERLACED_ILK;
1579 else
1580 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1581 else
1582 val |= TRANS_PROGRESSIVE;
1583
040484af
JB		 1584 I915_WRITE(reg, val | TRANS_ENABLE);
1585 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1586 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1587}
1588
8fb033d7 1589static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1590 enum transcoder cpu_transcoder)
040484af 1591{
8fb033d7 1592 u32 val, pipeconf_val;
8fb033d7
PZ		 1593
1594 /* PCH only available on ILK+ */
1595 BUG_ON(dev_priv->info->gen < 5);
1596
8fb033d7 1597 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1598 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1599 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1600
223a6fdf
PZ		 1601 /* Workaround: set timing override bit. */
1602 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1603 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1604 I915_WRITE(_TRANSA_CHICKEN2, val);
1605
25f3ef11 1606 val = TRANS_ENABLE;
937bb610 1607 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1608
9a76b1c6
PZ		 1609 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1610 PIPECONF_INTERLACED_ILK)
a35f2679 1611 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1612 else
1613 val |= TRANS_PROGRESSIVE;
1614
ab9412ba
DV		 1615 I915_WRITE(LPT_TRANSCONF, val);
1616 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1617 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1618}
1619
b8a4f404
PZ		 1620static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1621 enum pipe pipe)
040484af 1622{
23670b32
DV		 1623 struct drm_device *dev = dev_priv->dev;
1624 uint32_t reg, val;
040484af
JB		 1625
1626 /* FDI relies on the transcoder */
1627 assert_fdi_tx_disabled(dev_priv, pipe);
1628 assert_fdi_rx_disabled(dev_priv, pipe);
1629
291906f1
JB		 1630 /* Ports must be off as well */
1631 assert_pch_ports_disabled(dev_priv, pipe);
1632
ab9412ba 1633 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1634 val = I915_READ(reg);
1635 val &= ~TRANS_ENABLE;
1636 I915_WRITE(reg, val);
1637 /* wait for PCH transcoder off, transcoder state */
1638 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1639 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1640
1641 if (!HAS_PCH_IBX(dev)) {
1642 /* Workaround: Clear the timing override chicken bit again. */
1643 reg = TRANS_CHICKEN2(pipe);
1644 val = I915_READ(reg);
1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646 I915_WRITE(reg, val);
1647 }
040484af
JB		 1648}
1649
ab4d966c 1650static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1651{
8fb033d7
PZ		 1652 u32 val;
1653
ab9412ba 1654 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1655 val &= ~TRANS_ENABLE;
ab9412ba 1656 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1657 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1658 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1659 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1660
1661 /* Workaround: clear timing override bit. */
1662 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1663 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1664 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1665}
1666
b24e7179 1667/**
309cfea8 1668 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1669 * @dev_priv: i915 private structure
1670 * @pipe: pipe to enable
040484af 1671 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1672 *
1673 * Enable @pipe, making sure that various hardware specific requirements
1674 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1675 *
1676 * @pipe should be %PIPE_A or %PIPE_B.
1677 *
1678 * Will wait until the pipe is actually running (i.e. first vblank) before
1679 * returning.
1680 */
040484af 1681static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1682 bool pch_port, bool dsi)
b24e7179 1683{
702e7a56
PZ		 1684 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1685 pipe);
1a240d4d 1686 enum pipe pch_transcoder;
b24e7179
JB		 1687 int reg;
1688 u32 val;
1689
58c6eaa2
DV		 1690 assert_planes_disabled(dev_priv, pipe);
1691 assert_sprites_disabled(dev_priv, pipe);
1692
681e5811 1693 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1694 pch_transcoder = TRANSCODER_A;
1695 else
1696 pch_transcoder = pipe;
1697
b24e7179
JB		 1698 /*
1699 * A pipe without a PLL won't actually be able to drive bits from
1700 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1701 * need the check.
1702 */
1703 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1704 if (dsi)
1705 assert_dsi_pll_enabled(dev_priv);
1706 else
1707 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1708 else {
1709 if (pch_port) {
1710 /* if driving the PCH, we need FDI enabled */
cc391bbb 1711 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1712 assert_fdi_tx_pll_enabled(dev_priv,
1713 (enum pipe) cpu_transcoder);
040484af
JB		 1714 }
1715 /* FIXME: assert CPU port conditions for SNB+ */
1716 }
b24e7179 1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW		 1720 if (val & PIPECONF_ENABLE)
1721 return;
1722
1723 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1724 intel_wait_for_vblank(dev_priv->dev, pipe);
1725}
1726
1727/**
309cfea8 1728 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe to disable
1731 *
1732 * Disable @pipe, making sure that various hardware specific requirements
1733 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1734 *
1735 * @pipe should be %PIPE_A or %PIPE_B.
1736 *
1737 * Will wait until the pipe has shut down before returning.
1738 */
1739static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1740 enum pipe pipe)
1741{
702e7a56
PZ		 1742 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1743 pipe);
b24e7179
JB		 1744 int reg;
1745 u32 val;
1746
1747 /*
1748 * Make sure planes won't keep trying to pump pixels to us,
1749 * or we might hang the display.
1750 */
1751 assert_planes_disabled(dev_priv, pipe);
19332d7a 1752 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1753
1754 /* Don't disable pipe A or pipe A PLLs if needed */
1755 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1756 return;
1757
702e7a56 1758 reg = PIPECONF(cpu_transcoder);
b24e7179 1759 val = I915_READ(reg);
00d70b15
CW		 1760 if ((val & PIPECONF_ENABLE) == 0)
1761 return;
1762
1763 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1764 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1765}
1766
d74362c9
KP		 1767/*
1768 * Plane regs are double buffered, going from enabled->disabled needs a
1769 * trigger in order to latch. The display address reg provides this.
1770 */
6f1d69b0 1771void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1772 enum plane plane)
1773{
14f86147
DL		 1774 if (dev_priv->info->gen >= 4)
1775 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1776 else
1777 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1778}
1779
b24e7179
JB		 1780/**
1781 * intel_enable_plane - enable a display plane on a given pipe
1782 * @dev_priv: i915 private structure
1783 * @plane: plane to enable
1784 * @pipe: pipe being fed
1785 *
1786 * Enable @plane on @pipe, making sure that @pipe is running first.
1787 */
1788static void intel_enable_plane(struct drm_i915_private *dev_priv,
1789 enum plane plane, enum pipe pipe)
1790{
1791 int reg;
1792 u32 val;
1793
1794 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1795 assert_pipe_enabled(dev_priv, pipe);
1796
1797 reg = DSPCNTR(plane);
1798 val = I915_READ(reg);
00d70b15
CW		 1799 if (val & DISPLAY_PLANE_ENABLE)
1800 return;
1801
1802 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1803 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1804 intel_wait_for_vblank(dev_priv->dev, pipe);
1805}
1806
b24e7179
JB		 1807/**
1808 * intel_disable_plane - disable a display plane
1809 * @dev_priv: i915 private structure
1810 * @plane: plane to disable
1811 * @pipe: pipe consuming the data
1812 *
1813 * Disable @plane; should be an independent operation.
1814 */
1815static void intel_disable_plane(struct drm_i915_private *dev_priv,
1816 enum plane plane, enum pipe pipe)
1817{
1818 int reg;
1819 u32 val;
1820
1821 reg = DSPCNTR(plane);
1822 val = I915_READ(reg);
00d70b15
CW		 1823 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1824 return;
1825
1826 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1827 intel_flush_display_plane(dev_priv, plane);
1828 intel_wait_for_vblank(dev_priv->dev, pipe);
1829}
1830
693db184
CW		 1831static bool need_vtd_wa(struct drm_device *dev)
1832{
1833#ifdef CONFIG_INTEL_IOMMU
1834 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1835 return true;
1836#endif
1837 return false;
1838}
1839
127bd2ac 1840int
48b956c5 1841intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1842 struct drm_i915_gem_object *obj,
919926ae 1843 struct intel_ring_buffer *pipelined)
6b95a207 1844{
ce453d81 1845 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1846 u32 alignment;
1847 int ret;
1848
05394f39 1849 switch (obj->tiling_mode) {
6b95a207 1850 case I915_TILING_NONE:
534843da
CW		 1851 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1852 alignment = 128 * 1024;
a6c45cf0 1853 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1854 alignment = 4 * 1024;
1855 else
1856 alignment = 64 * 1024;
6b95a207
KH		 1857 break;
1858 case I915_TILING_X:
1859 /* pin() will align the object as required by fence */
1860 alignment = 0;
1861 break;
1862 case I915_TILING_Y:
8bb6e959
DV		 1863 /* Despite that we check this in framebuffer_init userspace can
1864 * screw us over and change the tiling after the fact. Only
1865 * pinned buffers can't change their tiling. */
1866 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1867 return -EINVAL;
1868 default:
1869 BUG();
1870 }
1871
693db184
CW		 1872 /* Note that the w/a also requires 64 PTE of padding following the
1873 * bo. We currently fill all unused PTE with the shadow page and so
1874 * we should always have valid PTE following the scanout preventing
1875 * the VT-d warning.
1876 */
1877 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1878 alignment = 256 * 1024;
1879
ce453d81 1880 dev_priv->mm.interruptible = false;
2da3b9b9 1881 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1882 if (ret)
ce453d81 1883 goto err_interruptible;
6b95a207
KH		 1884
1885 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1886 * fence, whereas 965+ only requires a fence if using
1887 * framebuffer compression. For simplicity, we always install
1888 * a fence as the cost is not that onerous.
1889 */
06d98131 1890 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1891 if (ret)
1892 goto err_unpin;
1690e1eb 1893
9a5a53b3 1894 i915_gem_object_pin_fence(obj);
6b95a207 1895
ce453d81 1896 dev_priv->mm.interruptible = true;
6b95a207 1897 return 0;
48b956c5
CW		 1898
1899err_unpin:
cc98b413 1900 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1901err_interruptible:
1902 dev_priv->mm.interruptible = true;
48b956c5 1903 return ret;
6b95a207
KH		 1904}
1905
1690e1eb
CW		 1906void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1907{
1908 i915_gem_object_unpin_fence(obj);
cc98b413 1909 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1910}
1911
c2c75131
DV		 1912/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1913 * is assumed to be a power-of-two. */
bc752862
CW		 1914unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1915 unsigned int tiling_mode,
1916 unsigned int cpp,
1917 unsigned int pitch)
c2c75131 1918{
bc752862
CW		 1919 if (tiling_mode != I915_TILING_NONE) {
1920 unsigned int tile_rows, tiles;
c2c75131 1921
bc752862
CW		 1922 tile_rows = *y / 8;
1923 *y %= 8;
c2c75131 1924
bc752862
CW		 1925 tiles = *x / (512/cpp);
1926 *x %= 512/cpp;
1927
1928 return tile_rows * pitch * 8 + tiles * 4096;
1929 } else {
1930 unsigned int offset;
1931
1932 offset = *y * pitch + *x * cpp;
1933 *y = 0;
1934 *x = (offset & 4095) / cpp;
1935 return offset & -4096;
1936 }
c2c75131
DV		 1937}
1938
17638cd6
JB		 1939static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1940 int x, int y)
81255565
JB		 1941{
1942 struct drm_device *dev = crtc->dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1945 struct intel_framebuffer *intel_fb;
05394f39 1946 struct drm_i915_gem_object *obj;
81255565 1947 int plane = intel_crtc->plane;
e506a0c6 1948 unsigned long linear_offset;
81255565 1949 u32 dspcntr;
5eddb70b 1950 u32 reg;
81255565
JB		 1951
1952 switch (plane) {
1953 case 0:
1954 case 1:
1955 break;
1956 default:
84f44ce7 1957 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1958 return -EINVAL;
1959 }
1960
1961 intel_fb = to_intel_framebuffer(fb);
1962 obj = intel_fb->obj;
81255565 1963
5eddb70b
CW		 1964 reg = DSPCNTR(plane);
1965 dspcntr = I915_READ(reg);
81255565
JB		 1966 /* Mask out pixel format bits in case we change it */
1967 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1968 switch (fb->pixel_format) {
1969 case DRM_FORMAT_C8:
81255565
JB		 1970 dspcntr |= DISPPLANE_8BPP;
1971 break;
57779d06
VS		 1972 case DRM_FORMAT_XRGB1555:
1973 case DRM_FORMAT_ARGB1555:
1974 dspcntr |= DISPPLANE_BGRX555;
81255565 1975 break;
57779d06
VS		 1976 case DRM_FORMAT_RGB565:
1977 dspcntr |= DISPPLANE_BGRX565;
1978 break;
1979 case DRM_FORMAT_XRGB8888:
1980 case DRM_FORMAT_ARGB8888:
1981 dspcntr |= DISPPLANE_BGRX888;
1982 break;
1983 case DRM_FORMAT_XBGR8888:
1984 case DRM_FORMAT_ABGR8888:
1985 dspcntr |= DISPPLANE_RGBX888;
1986 break;
1987 case DRM_FORMAT_XRGB2101010:
1988 case DRM_FORMAT_ARGB2101010:
1989 dspcntr |= DISPPLANE_BGRX101010;
1990 break;
1991 case DRM_FORMAT_XBGR2101010:
1992 case DRM_FORMAT_ABGR2101010:
1993 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1994 break;
1995 default:
baba133a 1996 BUG();
81255565 1997 }
57779d06 1998
a6c45cf0 1999 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2000 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2001 dspcntr |= DISPPLANE_TILED;
2002 else
2003 dspcntr &= ~DISPPLANE_TILED;
2004 }
2005
de1aa629
VS		 2006 if (IS_G4X(dev))
2007 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2008
5eddb70b 2009 I915_WRITE(reg, dspcntr);
81255565 2010
e506a0c6 2011 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2012
c2c75131
DV		 2013 if (INTEL_INFO(dev)->gen >= 4) {
2014 intel_crtc->dspaddr_offset =
bc752862
CW		 2015 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2016 fb->bits_per_pixel / 8,
2017 fb->pitches[0]);
c2c75131
DV		 2018 linear_offset -= intel_crtc->dspaddr_offset;
2019 } else {
e506a0c6 2020 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2021 }
e506a0c6 2022
f343c5f6
BW		 2023 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2024 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2025 fb->pitches[0]);
01f2c773 2026 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2027 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2028 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2029 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2030 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2031 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2032 } else
f343c5f6 2033 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2034 POSTING_READ(reg);
81255565 2035
17638cd6
JB		 2036 return 0;
2037}
2038
2039static int ironlake_update_plane(struct drm_crtc *crtc,
2040 struct drm_framebuffer *fb, int x, int y)
2041{
2042 struct drm_device *dev = crtc->dev;
2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2045 struct intel_framebuffer *intel_fb;
2046 struct drm_i915_gem_object *obj;
2047 int plane = intel_crtc->plane;
e506a0c6 2048 unsigned long linear_offset;
17638cd6
JB		 2049 u32 dspcntr;
2050 u32 reg;
2051
2052 switch (plane) {
2053 case 0:
2054 case 1:
27f8227b 2055 case 2:
17638cd6
JB		 2056 break;
2057 default:
84f44ce7 2058 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2059 return -EINVAL;
2060 }
2061
2062 intel_fb = to_intel_framebuffer(fb);
2063 obj = intel_fb->obj;
2064
2065 reg = DSPCNTR(plane);
2066 dspcntr = I915_READ(reg);
2067 /* Mask out pixel format bits in case we change it */
2068 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2069 switch (fb->pixel_format) {
2070 case DRM_FORMAT_C8:
17638cd6
JB		 2071 dspcntr |= DISPPLANE_8BPP;
2072 break;
57779d06
VS		 2073 case DRM_FORMAT_RGB565:
2074 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2075 break;
57779d06
VS		 2076 case DRM_FORMAT_XRGB8888:
2077 case DRM_FORMAT_ARGB8888:
2078 dspcntr |= DISPPLANE_BGRX888;
2079 break;
2080 case DRM_FORMAT_XBGR8888:
2081 case DRM_FORMAT_ABGR8888:
2082 dspcntr |= DISPPLANE_RGBX888;
2083 break;
2084 case DRM_FORMAT_XRGB2101010:
2085 case DRM_FORMAT_ARGB2101010:
2086 dspcntr |= DISPPLANE_BGRX101010;
2087 break;
2088 case DRM_FORMAT_XBGR2101010:
2089 case DRM_FORMAT_ABGR2101010:
2090 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2091 break;
2092 default:
baba133a 2093 BUG();
17638cd6
JB		 2094 }
2095
2096 if (obj->tiling_mode != I915_TILING_NONE)
2097 dspcntr |= DISPPLANE_TILED;
2098 else
2099 dspcntr &= ~DISPPLANE_TILED;
2100
1f5d76db
PZ		 2101 if (IS_HASWELL(dev))
2102 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2103 else
2104 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2105
2106 I915_WRITE(reg, dspcntr);
2107
e506a0c6 2108 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2109 intel_crtc->dspaddr_offset =
bc752862
CW		 2110 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2111 fb->bits_per_pixel / 8,
2112 fb->pitches[0]);
c2c75131 2113 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2114
f343c5f6
BW		 2115 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2116 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2117 fb->pitches[0]);
01f2c773 2118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2119 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2120 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2121 if (IS_HASWELL(dev)) {
2122 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2123 } else {
2124 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2125 I915_WRITE(DSPLINOFF(plane), linear_offset);
2126 }
17638cd6
JB		 2127 POSTING_READ(reg);
2128
2129 return 0;
2130}
2131
2132/* Assume fb object is pinned & idle & fenced and just update base pointers */
2133static int
2134intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2135 int x, int y, enum mode_set_atomic state)
2136{
2137 struct drm_device *dev = crtc->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2139
6b8e6ed0
CW		 2140 if (dev_priv->display.disable_fbc)
2141 dev_priv->display.disable_fbc(dev);
3dec0095 2142 intel_increase_pllclock(crtc);
81255565 2143
6b8e6ed0 2144 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2145}
2146
96a02917
VS		 2147void intel_display_handle_reset(struct drm_device *dev)
2148{
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 struct drm_crtc *crtc;
2151
2152 /*
2153 * Flips in the rings have been nuked by the reset,
2154 * so complete all pending flips so that user space
2155 * will get its events and not get stuck.
2156 *
2157 * Also update the base address of all primary
2158 * planes to the the last fb to make sure we're
2159 * showing the correct fb after a reset.
2160 *
2161 * Need to make two loops over the crtcs so that we
2162 * don't try to grab a crtc mutex before the
2163 * pending_flip_queue really got woken up.
2164 */
2165
2166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168 enum plane plane = intel_crtc->plane;
2169
2170 intel_prepare_page_flip(dev, plane);
2171 intel_finish_page_flip_plane(dev, plane);
2172 }
2173
2174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176
2177 mutex_lock(&crtc->mutex);
2178 if (intel_crtc->active)
2179 dev_priv->display.update_plane(crtc, crtc->fb,
2180 crtc->x, crtc->y);
2181 mutex_unlock(&crtc->mutex);
2182 }
2183}
2184
14667a4b
CW		 2185static int
2186intel_finish_fb(struct drm_framebuffer *old_fb)
2187{
2188 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2189 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2190 bool was_interruptible = dev_priv->mm.interruptible;
2191 int ret;
2192
14667a4b
CW		 2193 /* Big Hammer, we also need to ensure that any pending
2194 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2195 * current scanout is retired before unpinning the old
2196 * framebuffer.
2197 *
2198 * This should only fail upon a hung GPU, in which case we
2199 * can safely continue.
2200 */
2201 dev_priv->mm.interruptible = false;
2202 ret = i915_gem_object_finish_gpu(obj);
2203 dev_priv->mm.interruptible = was_interruptible;
2204
2205 return ret;
2206}
2207
198598d0
VS		 2208static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2209{
2210 struct drm_device *dev = crtc->dev;
2211 struct drm_i915_master_private *master_priv;
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 if (!dev->primary->master)
2215 return;
2216
2217 master_priv = dev->primary->master->driver_priv;
2218 if (!master_priv->sarea_priv)
2219 return;
2220
2221 switch (intel_crtc->pipe) {
2222 case 0:
2223 master_priv->sarea_priv->pipeA_x = x;
2224 master_priv->sarea_priv->pipeA_y = y;
2225 break;
2226 case 1:
2227 master_priv->sarea_priv->pipeB_x = x;
2228 master_priv->sarea_priv->pipeB_y = y;
2229 break;
2230 default:
2231 break;
2232 }
2233}
2234
5c3b82e2 2235static int
3c4fdcfb 2236intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2237 struct drm_framebuffer *fb)
79e53945
JB		 2238{
2239 struct drm_device *dev = crtc->dev;
6b8e6ed0 2240 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2242 struct drm_framebuffer *old_fb;
5c3b82e2 2243 int ret;
79e53945
JB		 2244
2245 /* no fb bound */
94352cf9 2246 if (!fb) {
a5071c2f 2247 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2248 return 0;
2249 }
2250
7eb552ae 2251 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2252 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2253 plane_name(intel_crtc->plane),
2254 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2255 return -EINVAL;
79e53945
JB		 2256 }
2257
5c3b82e2 2258 mutex_lock(&dev->struct_mutex);
265db958 2259 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2260 to_intel_framebuffer(fb)->obj,
919926ae 2261 NULL);
5c3b82e2
CW		 2262 if (ret != 0) {
2263 mutex_unlock(&dev->struct_mutex);
a5071c2f 2264 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2265 return ret;
2266 }
79e53945 2267
4d6a3e63
JB		 2268 /* Update pipe size and adjust fitter if needed */
2269 if (i915_fastboot) {
2270 I915_WRITE(PIPESRC(intel_crtc->pipe),
2271 ((crtc->mode.hdisplay - 1) << 16) |
2272 (crtc->mode.vdisplay - 1));
2273 if (!intel_crtc->config.pch_pfit.size &&
2274 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2275 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2276 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2277 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2278 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2279 }
2280 }
2281
94352cf9 2282 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2283 if (ret) {
94352cf9 2284 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2285 mutex_unlock(&dev->struct_mutex);
a5071c2f 2286 DRM_ERROR("failed to update base address\n");
4e6cfefc 2287 return ret;
79e53945 2288 }
3c4fdcfb 2289
94352cf9
DV		 2290 old_fb = crtc->fb;
2291 crtc->fb = fb;
6c4c86f5
DV		 2292 crtc->x = x;
2293 crtc->y = y;
94352cf9 2294
b7f1de28 2295 if (old_fb) {
d7697eea
DV		 2296 if (intel_crtc->active && old_fb != fb)
2297 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2298 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2299 }
652c393a 2300
6b8e6ed0 2301 intel_update_fbc(dev);
4906557e 2302 intel_edp_psr_update(dev);
5c3b82e2 2303 mutex_unlock(&dev->struct_mutex);
79e53945 2304
198598d0 2305 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2306
2307 return 0;
79e53945
JB		 2308}
2309
5e84e1a4
ZW		 2310static void intel_fdi_normal_train(struct drm_crtc *crtc)
2311{
2312 struct drm_device *dev = crtc->dev;
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2315 int pipe = intel_crtc->pipe;
2316 u32 reg, temp;
2317
2318 /* enable normal train */
2319 reg = FDI_TX_CTL(pipe);
2320 temp = I915_READ(reg);
61e499bf 2321 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2322 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2323 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2324 } else {
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2327 }
5e84e1a4
ZW		 2328 I915_WRITE(reg, temp);
2329
2330 reg = FDI_RX_CTL(pipe);
2331 temp = I915_READ(reg);
2332 if (HAS_PCH_CPT(dev)) {
2333 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2334 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2335 } else {
2336 temp &= ~FDI_LINK_TRAIN_NONE;
2337 temp |= FDI_LINK_TRAIN_NONE;
2338 }
2339 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2340
2341 /* wait one idle pattern time */
2342 POSTING_READ(reg);
2343 udelay(1000);
357555c0
JB		 2344
2345 /* IVB wants error correction enabled */
2346 if (IS_IVYBRIDGE(dev))
2347 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2348 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2349}
2350
1e833f40
DV		 2351static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2352{
2353 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2354}
2355
01a415fd
DV		 2356static void ivb_modeset_global_resources(struct drm_device *dev)
2357{
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *pipe_B_crtc =
2360 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2361 struct intel_crtc *pipe_C_crtc =
2362 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2363 uint32_t temp;
2364
1e833f40
DV		 2365 /*
2366 * When everything is off disable fdi C so that we could enable fdi B
2367 * with all lanes. Note that we don't care about enabled pipes without
2368 * an enabled pch encoder.
2369 */
2370 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2371 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2372 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2373 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2374
2375 temp = I915_READ(SOUTH_CHICKEN1);
2376 temp &= ~FDI_BC_BIFURCATION_SELECT;
2377 DRM_DEBUG_KMS("disabling fdi C rx\n");
2378 I915_WRITE(SOUTH_CHICKEN1, temp);
2379 }
2380}
2381
8db9d77b
ZW		 2382/* The FDI link training functions for ILK/Ibexpeak. */
2383static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
0fc932b8 2389 int plane = intel_crtc->plane;
5eddb70b 2390 u32 reg, temp, tries;
8db9d77b 2391
0fc932b8
JB		 2392 /* FDI needs bits from pipe & plane first */
2393 assert_pipe_enabled(dev_priv, pipe);
2394 assert_plane_enabled(dev_priv, plane);
2395
e1a44743
AJ		 2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
5eddb70b
CW		 2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
e1a44743
AJ		 2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2402 I915_WRITE(reg, temp);
2403 I915_READ(reg);
e1a44743
AJ		 2404 udelay(150);
2405
8db9d77b 2406 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2407 reg = FDI_TX_CTL(pipe);
2408 temp = I915_READ(reg);
627eb5a3
DV		 2409 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2410 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2411 temp &= ~FDI_LINK_TRAIN_NONE;
2412 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2413 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2414
5eddb70b
CW		 2415 reg = FDI_RX_CTL(pipe);
2416 temp = I915_READ(reg);
8db9d77b
ZW		 2417 temp &= ~FDI_LINK_TRAIN_NONE;
2418 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2419 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2420
2421 POSTING_READ(reg);
8db9d77b
ZW		 2422 udelay(150);
2423
5b2adf89 2424 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2425 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2426 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2427 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2428
5eddb70b 2429 reg = FDI_RX_IIR(pipe);
e1a44743 2430 for (tries = 0; tries < 5; tries++) {
5eddb70b 2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433
2434 if ((temp & FDI_RX_BIT_LOCK)) {
2435 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2436 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2437 break;
2438 }
8db9d77b 2439 }
e1a44743 2440 if (tries == 5)
5eddb70b 2441 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2442
2443 /* Train 2 */
5eddb70b
CW		 2444 reg = FDI_TX_CTL(pipe);
2445 temp = I915_READ(reg);
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2448 I915_WRITE(reg, temp);
8db9d77b 2449
5eddb70b
CW		 2450 reg = FDI_RX_CTL(pipe);
2451 temp = I915_READ(reg);
8db9d77b
ZW		 2452 temp &= ~FDI_LINK_TRAIN_NONE;
2453 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2454 I915_WRITE(reg, temp);
8db9d77b 2455
5eddb70b
CW		 2456 POSTING_READ(reg);
2457 udelay(150);
8db9d77b 2458
5eddb70b 2459 reg = FDI_RX_IIR(pipe);
e1a44743 2460 for (tries = 0; tries < 5; tries++) {
5eddb70b 2461 temp = I915_READ(reg);
8db9d77b
ZW		 2462 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2463
2464 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2465 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2466 DRM_DEBUG_KMS("FDI train 2 done.\n");
2467 break;
2468 }
8db9d77b 2469 }
e1a44743 2470 if (tries == 5)
5eddb70b 2471 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2472
2473 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2474
8db9d77b
ZW		 2475}
2476
0206e353 2477static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2478 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2479 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2480 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2481 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2482};
2483
2484/* The FDI link training functions for SNB/Cougarpoint. */
2485static void gen6_fdi_link_train(struct drm_crtc *crtc)
2486{
2487 struct drm_device *dev = crtc->dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490 int pipe = intel_crtc->pipe;
fa37d39e 2491 u32 reg, temp, i, retry;
8db9d77b 2492
e1a44743
AJ		 2493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2494 for train result */
5eddb70b
CW		 2495 reg = FDI_RX_IMR(pipe);
2496 temp = I915_READ(reg);
e1a44743
AJ		 2497 temp &= ~FDI_RX_SYMBOL_LOCK;
2498 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2499 I915_WRITE(reg, temp);
2500
2501 POSTING_READ(reg);
e1a44743
AJ		 2502 udelay(150);
2503
8db9d77b 2504 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
627eb5a3
DV		 2507 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2508 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2509 temp &= ~FDI_LINK_TRAIN_NONE;
2510 temp |= FDI_LINK_TRAIN_PATTERN_1;
2511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512 /* SNB-B */
2513 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2514 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2515
d74cf324
DV		 2516 I915_WRITE(FDI_RX_MISC(pipe),
2517 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2518
5eddb70b
CW		 2519 reg = FDI_RX_CTL(pipe);
2520 temp = I915_READ(reg);
8db9d77b
ZW		 2521 if (HAS_PCH_CPT(dev)) {
2522 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2524 } else {
2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_1;
2527 }
5eddb70b
CW		 2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(150);
2532
0206e353 2533 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2534 reg = FDI_TX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2538 I915_WRITE(reg, temp);
2539
2540 POSTING_READ(reg);
8db9d77b
ZW		 2541 udelay(500);
2542
fa37d39e
SP		 2543 for (retry = 0; retry < 5; retry++) {
2544 reg = FDI_RX_IIR(pipe);
2545 temp = I915_READ(reg);
2546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547 if (temp & FDI_RX_BIT_LOCK) {
2548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549 DRM_DEBUG_KMS("FDI train 1 done.\n");
2550 break;
2551 }
2552 udelay(50);
8db9d77b 2553 }
fa37d39e
SP		 2554 if (retry < 5)
2555 break;
8db9d77b
ZW		 2556 }
2557 if (i == 4)
5eddb70b 2558 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2559
2560 /* Train 2 */
5eddb70b
CW		 2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
8db9d77b
ZW		 2563 temp &= ~FDI_LINK_TRAIN_NONE;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2;
2565 if (IS_GEN6(dev)) {
2566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567 /* SNB-B */
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2569 }
5eddb70b 2570 I915_WRITE(reg, temp);
8db9d77b 2571
5eddb70b
CW		 2572 reg = FDI_RX_CTL(pipe);
2573 temp = I915_READ(reg);
8db9d77b
ZW		 2574 if (HAS_PCH_CPT(dev)) {
2575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2576 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2577 } else {
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 }
5eddb70b
CW		 2581 I915_WRITE(reg, temp);
2582
2583 POSTING_READ(reg);
8db9d77b
ZW		 2584 udelay(150);
2585
0206e353 2586 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
8db9d77b
ZW		 2594 udelay(500);
2595
fa37d39e
SP		 2596 for (retry = 0; retry < 5; retry++) {
2597 reg = FDI_RX_IIR(pipe);
2598 temp = I915_READ(reg);
2599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2600 if (temp & FDI_RX_SYMBOL_LOCK) {
2601 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2602 DRM_DEBUG_KMS("FDI train 2 done.\n");
2603 break;
2604 }
2605 udelay(50);
8db9d77b 2606 }
fa37d39e
SP		 2607 if (retry < 5)
2608 break;
8db9d77b
ZW		 2609 }
2610 if (i == 4)
5eddb70b 2611 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2612
2613 DRM_DEBUG_KMS("FDI train done.\n");
2614}
2615
357555c0
JB		 2616/* Manual link training for Ivy Bridge A0 parts */
2617static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2618{
2619 struct drm_device *dev = crtc->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622 int pipe = intel_crtc->pipe;
139ccd3f 2623 u32 reg, temp, i, j;
357555c0
JB		 2624
2625 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2626 for train result */
2627 reg = FDI_RX_IMR(pipe);
2628 temp = I915_READ(reg);
2629 temp &= ~FDI_RX_SYMBOL_LOCK;
2630 temp &= ~FDI_RX_BIT_LOCK;
2631 I915_WRITE(reg, temp);
2632
2633 POSTING_READ(reg);
2634 udelay(150);
2635
01a415fd
DV		 2636 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2637 I915_READ(FDI_RX_IIR(pipe)));
2638
139ccd3f
JB		 2639 /* Try each vswing and preemphasis setting twice before moving on */
2640 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2641 /* disable first in case we need to retry */
2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2645 temp &= ~FDI_TX_ENABLE;
2646 I915_WRITE(reg, temp);
357555c0 2647
139ccd3f
JB		 2648 reg = FDI_RX_CTL(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_LINK_TRAIN_AUTO;
2651 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2652 temp &= ~FDI_RX_ENABLE;
2653 I915_WRITE(reg, temp);
357555c0 2654
139ccd3f 2655 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2656 reg = FDI_TX_CTL(pipe);
2657 temp = I915_READ(reg);
139ccd3f
JB		 2658 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2659 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2662 temp |= snb_b_fdi_train_param[j/2];
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2665
139ccd3f
JB		 2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2668
139ccd3f 2669 reg = FDI_RX_CTL(pipe);
357555c0 2670 temp = I915_READ(reg);
139ccd3f
JB		 2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2672 temp |= FDI_COMPOSITE_SYNC;
2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2674
139ccd3f
JB		 2675 POSTING_READ(reg);
2676 udelay(1); /* should be 0.5us */
357555c0 2677
139ccd3f
JB		 2678 for (i = 0; i < 4; i++) {
2679 reg = FDI_RX_IIR(pipe);
2680 temp = I915_READ(reg);
2681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2682
139ccd3f
JB		 2683 if (temp & FDI_RX_BIT_LOCK ||
2684 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2685 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2686 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2687 i);
2688 break;
2689 }
2690 udelay(1); /* should be 0.5us */
2691 }
2692 if (i == 4) {
2693 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2694 continue;
2695 }
357555c0 2696
139ccd3f 2697 /* Train 2 */
357555c0
JB		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
139ccd3f
JB		 2700 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2701 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2702 I915_WRITE(reg, temp);
2703
2704 reg = FDI_RX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2707 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2708 I915_WRITE(reg, temp);
2709
2710 POSTING_READ(reg);
139ccd3f 2711 udelay(2); /* should be 1.5us */
357555c0 2712
139ccd3f
JB		 2713 for (i = 0; i < 4; i++) {
2714 reg = FDI_RX_IIR(pipe);
2715 temp = I915_READ(reg);
2716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2717
139ccd3f
JB		 2718 if (temp & FDI_RX_SYMBOL_LOCK ||
2719 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2720 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2721 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2722 i);
2723 goto train_done;
2724 }
2725 udelay(2); /* should be 1.5us */
357555c0 2726 }
139ccd3f
JB		 2727 if (i == 4)
2728 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2729 }
357555c0 2730
139ccd3f 2731train_done:
357555c0
JB		 2732 DRM_DEBUG_KMS("FDI train done.\n");
2733}
2734
88cefb6c 2735static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2736{
88cefb6c 2737 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2738 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2739 int pipe = intel_crtc->pipe;
5eddb70b 2740 u32 reg, temp;
79e53945 2741
c64e311e 2742
c98e9dcf 2743 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2744 reg = FDI_RX_CTL(pipe);
2745 temp = I915_READ(reg);
627eb5a3
DV		 2746 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2747 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2749 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2750
2751 POSTING_READ(reg);
c98e9dcf
JB		 2752 udelay(200);
2753
2754 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2755 temp = I915_READ(reg);
2756 I915_WRITE(reg, temp | FDI_PCDCLK);
2757
2758 POSTING_READ(reg);
c98e9dcf
JB		 2759 udelay(200);
2760
20749730
PZ		 2761 /* Enable CPU FDI TX PLL, always on for Ironlake */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2765 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2766
20749730
PZ		 2767 POSTING_READ(reg);
2768 udelay(100);
6be4a607 2769 }
0e23b99d
JB		 2770}
2771
88cefb6c
DV		 2772static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2773{
2774 struct drm_device *dev = intel_crtc->base.dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 int pipe = intel_crtc->pipe;
2777 u32 reg, temp;
2778
2779 /* Switch from PCDclk to Rawclk */
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2783
2784 /* Disable CPU FDI TX PLL */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2788
2789 POSTING_READ(reg);
2790 udelay(100);
2791
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2795
2796 /* Wait for the clocks to turn off. */
2797 POSTING_READ(reg);
2798 udelay(100);
2799}
2800
0fc932b8
JB		 2801static void ironlake_fdi_disable(struct drm_crtc *crtc)
2802{
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806 int pipe = intel_crtc->pipe;
2807 u32 reg, temp;
2808
2809 /* disable CPU FDI tx and PCH FDI rx */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2813 POSTING_READ(reg);
2814
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 temp &= ~(0x7 << 16);
dfd07d72 2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2819 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2820
2821 POSTING_READ(reg);
2822 udelay(100);
2823
2824 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2825 if (HAS_PCH_IBX(dev)) {
2826 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2827 }
0fc932b8
JB		 2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
dfd07d72 2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852}
2853
5bb61643
CW		 2854static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2855{
2856 struct drm_device *dev = crtc->dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2859 unsigned long flags;
2860 bool pending;
2861
10d83730
VS		 2862 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2863 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2864 return false;
2865
2866 spin_lock_irqsave(&dev->event_lock, flags);
2867 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2868 spin_unlock_irqrestore(&dev->event_lock, flags);
2869
2870 return pending;
2871}
2872
e6c3a2a6
CW		 2873static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2874{
0f91128d 2875 struct drm_device *dev = crtc->dev;
5bb61643 2876 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2877
2878 if (crtc->fb == NULL)
2879 return;
2880
2c10d571
DV		 2881 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2882
5bb61643
CW		 2883 wait_event(dev_priv->pending_flip_queue,
2884 !intel_crtc_has_pending_flip(crtc));
2885
0f91128d
CW		 2886 mutex_lock(&dev->struct_mutex);
2887 intel_finish_fb(crtc->fb);
2888 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2889}
2890
e615efe4
ED		 2891/* Program iCLKIP clock to the desired frequency */
2892static void lpt_program_iclkip(struct drm_crtc *crtc)
2893{
2894 struct drm_device *dev = crtc->dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2897 u32 temp;
2898
09153000
DV		 2899 mutex_lock(&dev_priv->dpio_lock);
2900
e615efe4
ED		 2901 /* It is necessary to ungate the pixclk gate prior to programming
2902 * the divisors, and gate it back when it is done.
2903 */
2904 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2905
2906 /* Disable SSCCTL */
2907 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2908 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2909 SBI_SSCCTL_DISABLE,
2910 SBI_ICLK);
e615efe4
ED		 2911
2912 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2913 if (crtc->mode.clock == 20000) {
2914 auxdiv = 1;
2915 divsel = 0x41;
2916 phaseinc = 0x20;
2917 } else {
2918 /* The iCLK virtual clock root frequency is in MHz,
2919 * but the crtc->mode.clock in in KHz. To get the divisors,
2920 * it is necessary to divide one by another, so we
2921 * convert the virtual clock precision to KHz here for higher
2922 * precision.
2923 */
2924 u32 iclk_virtual_root_freq = 172800 * 1000;
2925 u32 iclk_pi_range = 64;
2926 u32 desired_divisor, msb_divisor_value, pi_value;
2927
2928 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2929 msb_divisor_value = desired_divisor / iclk_pi_range;
2930 pi_value = desired_divisor % iclk_pi_range;
2931
2932 auxdiv = 0;
2933 divsel = msb_divisor_value - 2;
2934 phaseinc = pi_value;
2935 }
2936
2937 /* This should not happen with any sane values */
2938 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2939 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2940 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2941 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2942
2943 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2944 crtc->mode.clock,
2945 auxdiv,
2946 divsel,
2947 phasedir,
2948 phaseinc);
2949
2950 /* Program SSCDIVINTPHASE6 */
988d6ee8 2951 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2952 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2953 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2954 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2955 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2956 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2957 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2958 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2959
2960 /* Program SSCAUXDIV */
988d6ee8 2961 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2962 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2963 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2964 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2965
2966 /* Enable modulator and associated divider */
988d6ee8 2967 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2968 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2969 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2970
2971 /* Wait for initialization time */
2972 udelay(24);
2973
2974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2975
2976 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2977}
2978
275f01b2
DV		 2979static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2980 enum pipe pch_transcoder)
2981{
2982 struct drm_device *dev = crtc->base.dev;
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2985
2986 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2987 I915_READ(HTOTAL(cpu_transcoder)));
2988 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2989 I915_READ(HBLANK(cpu_transcoder)));
2990 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2991 I915_READ(HSYNC(cpu_transcoder)));
2992
2993 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2994 I915_READ(VTOTAL(cpu_transcoder)));
2995 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2996 I915_READ(VBLANK(cpu_transcoder)));
2997 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2998 I915_READ(VSYNC(cpu_transcoder)));
2999 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3000 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3001}
3002
f67a559d
JB		 3003/*
3004 * Enable PCH resources required for PCH ports:
3005 * - PCH PLLs
3006 * - FDI training & RX/TX
3007 * - update transcoder timings
3008 * - DP transcoding bits
3009 * - transcoder
3010 */
3011static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3012{
3013 struct drm_device *dev = crtc->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3016 int pipe = intel_crtc->pipe;
ee7b9f93 3017 u32 reg, temp;
2c07245f 3018
ab9412ba 3019 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3020
cd986abb
DV		 3021 /* Write the TU size bits before fdi link training, so that error
3022 * detection works. */
3023 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3024 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3025
c98e9dcf 3026 /* For PCH output, training FDI link */
674cf967 3027 dev_priv->display.fdi_link_train(crtc);
2c07245f 3028
3ad8a208
DV		 3029 /* We need to program the right clock selection before writing the pixel
3030 * mutliplier into the DPLL. */
303b81e0 3031 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3032 u32 sel;
4b645f14 3033
c98e9dcf 3034 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3035 temp |= TRANS_DPLL_ENABLE(pipe);
3036 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3037 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3038 temp |= sel;
3039 else
3040 temp &= ~sel;
c98e9dcf 3041 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3042 }
5eddb70b 3043
3ad8a208
DV		 3044 /* XXX: pch pll's can be enabled any time before we enable the PCH
3045 * transcoder, and we actually should do this to not upset any PCH
3046 * transcoder that already use the clock when we share it.
3047 *
3048 * Note that enable_shared_dpll tries to do the right thing, but
3049 * get_shared_dpll unconditionally resets the pll - we need that to have
3050 * the right LVDS enable sequence. */
3051 ironlake_enable_shared_dpll(intel_crtc);
3052
d9b6cb56
JB		 3053 /* set transcoder timing, panel must allow it */
3054 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3056
303b81e0 3057 intel_fdi_normal_train(crtc);
5e84e1a4 3058
c98e9dcf
JB		 3059 /* For PCH DP, enable TRANS_DP_CTL */
3060 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3061 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3062 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3063 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3064 reg = TRANS_DP_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3067 TRANS_DP_SYNC_MASK |
3068 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3069 temp |= (TRANS_DP_OUTPUT_ENABLE |
3070 TRANS_DP_ENH_FRAMING);
9325c9f0 3071 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3072
3073 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3074 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3075 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3076 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3077
3078 switch (intel_trans_dp_port_sel(crtc)) {
3079 case PCH_DP_B:
5eddb70b 3080 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3081 break;
3082 case PCH_DP_C:
5eddb70b 3083 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3084 break;
3085 case PCH_DP_D:
5eddb70b 3086 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3087 break;
3088 default:
e95d41e1 3089 BUG();
32f9d658 3090 }
2c07245f 3091
5eddb70b 3092 I915_WRITE(reg, temp);
6be4a607 3093 }
b52eb4dc 3094
b8a4f404 3095 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3096}
3097
1507e5bd
PZ		 3098static void lpt_pch_enable(struct drm_crtc *crtc)
3099{
3100 struct drm_device *dev = crtc->dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3103 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3104
ab9412ba 3105 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3106
8c52b5e8 3107 lpt_program_iclkip(crtc);
1507e5bd 3108
0540e488 3109 /* Set transcoder timing. */
275f01b2 3110 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3111
937bb610 3112 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3113}
3114
e2b78267 3115static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3116{
e2b78267 3117 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3118
3119 if (pll == NULL)
3120 return;
3121
3122 if (pll->refcount == 0) {
46edb027 3123 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3124 return;
3125 }
3126
f4a091c7
DV		 3127 if (--pll->refcount == 0) {
3128 WARN_ON(pll->on);
3129 WARN_ON(pll->active);
3130 }
3131
a43f6e0f 3132 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3133}
3134
b89a1d39 3135static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3136{
e2b78267
DV		 3137 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3138 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3139 enum intel_dpll_id i;
ee7b9f93 3140
ee7b9f93 3141 if (pll) {
46edb027
DV		 3142 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3143 crtc->base.base.id, pll->name);
e2b78267 3144 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3145 }
3146
98b6bd99
DV		 3147 if (HAS_PCH_IBX(dev_priv->dev)) {
3148 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3149 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3150 pll = &dev_priv->shared_dplls[i];
98b6bd99 3151
46edb027
DV		 3152 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3153 crtc->base.base.id, pll->name);
98b6bd99
DV		 3154
3155 goto found;
3156 }
3157
e72f9fbf
DV		 3158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3159 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3160
3161 /* Only want to check enabled timings first */
3162 if (pll->refcount == 0)
3163 continue;
3164
b89a1d39
DV		 3165 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3166 sizeof(pll->hw_state)) == 0) {
46edb027 3167 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3168 crtc->base.base.id,
46edb027 3169 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3170
3171 goto found;
3172 }
3173 }
3174
3175 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3176 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3177 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3178 if (pll->refcount == 0) {
46edb027
DV		 3179 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3180 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3181 goto found;
3182 }
3183 }
3184
3185 return NULL;
3186
3187found:
a43f6e0f 3188 crtc->config.shared_dpll = i;
46edb027
DV		 3189 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3190 pipe_name(crtc->pipe));
ee7b9f93 3191
cdbd2316 3192 if (pll->active == 0) {
66e985c0
DV		 3193 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3194 sizeof(pll->hw_state));
3195
46edb027 3196 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3197 WARN_ON(pll->on);
e9d6944e 3198 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3199
15bdd4cf 3200 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3201 }
3202 pll->refcount++;
e04c7350 3203
ee7b9f93
JB		 3204 return pll;
3205}
3206
a1520318 3207static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3208{
3209 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3210 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3211 u32 temp;
3212
3213 temp = I915_READ(dslreg);
3214 udelay(500);
3215 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3216 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3217 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3218 }
3219}
3220
b074cec8
JB		 3221static void ironlake_pfit_enable(struct intel_crtc *crtc)
3222{
3223 struct drm_device *dev = crtc->base.dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 int pipe = crtc->pipe;
3226
0ef37f3f 3227 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3228 /* Force use of hard-coded filter coefficients
3229 * as some pre-programmed values are broken,
3230 * e.g. x201.
3231 */
3232 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3233 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3234 PF_PIPE_SEL_IVB(pipe));
3235 else
3236 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3237 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3238 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3239 }
3240}
3241
bb53d4ae
VS		 3242static void intel_enable_planes(struct drm_crtc *crtc)
3243{
3244 struct drm_device *dev = crtc->dev;
3245 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3246 struct intel_plane *intel_plane;
3247
3248 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3249 if (intel_plane->pipe == pipe)
3250 intel_plane_restore(&intel_plane->base);
3251}
3252
3253static void intel_disable_planes(struct drm_crtc *crtc)
3254{
3255 struct drm_device *dev = crtc->dev;
3256 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3257 struct intel_plane *intel_plane;
3258
3259 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3260 if (intel_plane->pipe == pipe)
3261 intel_plane_disable(&intel_plane->base);
3262}
3263
f67a559d
JB		 3264static void ironlake_crtc_enable(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3269 struct intel_encoder *encoder;
f67a559d
JB		 3270 int pipe = intel_crtc->pipe;
3271 int plane = intel_crtc->plane;
f67a559d 3272
08a48469
DV		 3273 WARN_ON(!crtc->enabled);
3274
f67a559d
JB		 3275 if (intel_crtc->active)
3276 return;
3277
3278 intel_crtc->active = true;
8664281b
PZ		 3279
3280 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3281 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3282
f67a559d
JB		 3283 intel_update_watermarks(dev);
3284
f6736a1a 3285 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3286 if (encoder->pre_enable)
3287 encoder->pre_enable(encoder);
f67a559d 3288
5bfe2ac0 3289 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3290 /* Note: FDI PLL enabling _must_ be done before we enable the
3291 * cpu pipes, hence this is separate from all the other fdi/pch
3292 * enabling. */
88cefb6c 3293 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3294 } else {
3295 assert_fdi_tx_disabled(dev_priv, pipe);
3296 assert_fdi_rx_disabled(dev_priv, pipe);
3297 }
f67a559d 3298
b074cec8 3299 ironlake_pfit_enable(intel_crtc);
f67a559d 3300
9c54c0dd
JB		 3301 /*
3302 * On ILK+ LUT must be loaded before the pipe is running but with
3303 * clocks enabled
3304 */
3305 intel_crtc_load_lut(crtc);
3306
5bfe2ac0 3307 intel_enable_pipe(dev_priv, pipe,
23538ef1 3308 intel_crtc->config.has_pch_encoder, false);
f67a559d 3309 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3310 intel_enable_planes(crtc);
5c38d48c 3311 intel_crtc_update_cursor(crtc, true);
f67a559d 3312
5bfe2ac0 3313 if (intel_crtc->config.has_pch_encoder)
f67a559d 3314 ironlake_pch_enable(crtc);
c98e9dcf 3315
d1ebd816 3316 mutex_lock(&dev->struct_mutex);
bed4a673 3317 intel_update_fbc(dev);
d1ebd816
BW		 3318 mutex_unlock(&dev->struct_mutex);
3319
fa5c73b1
DV		 3320 for_each_encoder_on_crtc(dev, crtc, encoder)
3321 encoder->enable(encoder);
61b77ddd
DV		 3322
3323 if (HAS_PCH_CPT(dev))
a1520318 3324 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3325
3326 /*
3327 * There seems to be a race in PCH platform hw (at least on some
3328 * outputs) where an enabled pipe still completes any pageflip right
3329 * away (as if the pipe is off) instead of waiting for vblank. As soon
3330 * as the first vblank happend, everything works as expected. Hence just
3331 * wait for one vblank before returning to avoid strange things
3332 * happening.
3333 */
3334 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3335}
3336
42db64ef
PZ		 3337/* IPS only exists on ULT machines and is tied to pipe A. */
3338static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3339{
f5adf94e 3340 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3341}
3342
3343static void hsw_enable_ips(struct intel_crtc *crtc)
3344{
3345 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3346
3347 if (!crtc->config.ips_enabled)
3348 return;
3349
3350 /* We can only enable IPS after we enable a plane and wait for a vblank.
3351 * We guarantee that the plane is enabled by calling intel_enable_ips
3352 * only after intel_enable_plane. And intel_enable_plane already waits
3353 * for a vblank, so all we need to do here is to enable the IPS bit. */
3354 assert_plane_enabled(dev_priv, crtc->plane);
3355 I915_WRITE(IPS_CTL, IPS_ENABLE);
3356}
3357
3358static void hsw_disable_ips(struct intel_crtc *crtc)
3359{
3360 struct drm_device *dev = crtc->base.dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362
3363 if (!crtc->config.ips_enabled)
3364 return;
3365
3366 assert_plane_enabled(dev_priv, crtc->plane);
3367 I915_WRITE(IPS_CTL, 0);
3368
3369 /* We need to wait for a vblank before we can disable the plane. */
3370 intel_wait_for_vblank(dev, crtc->pipe);
3371}
3372
4f771f10
PZ		 3373static void haswell_crtc_enable(struct drm_crtc *crtc)
3374{
3375 struct drm_device *dev = crtc->dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3378 struct intel_encoder *encoder;
3379 int pipe = intel_crtc->pipe;
3380 int plane = intel_crtc->plane;
4f771f10
PZ		 3381
3382 WARN_ON(!crtc->enabled);
3383
3384 if (intel_crtc->active)
3385 return;
3386
3387 intel_crtc->active = true;
8664281b
PZ		 3388
3389 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3390 if (intel_crtc->config.has_pch_encoder)
3391 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3392
4f771f10
PZ		 3393 intel_update_watermarks(dev);
3394
5bfe2ac0 3395 if (intel_crtc->config.has_pch_encoder)
04945641 3396 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3397
3398 for_each_encoder_on_crtc(dev, crtc, encoder)
3399 if (encoder->pre_enable)
3400 encoder->pre_enable(encoder);
3401
1f544388 3402 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3403
b074cec8 3404 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3405
3406 /*
3407 * On ILK+ LUT must be loaded before the pipe is running but with
3408 * clocks enabled
3409 */
3410 intel_crtc_load_lut(crtc);
3411
1f544388 3412 intel_ddi_set_pipe_settings(crtc);
8228c251 3413 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3414
5bfe2ac0 3415 intel_enable_pipe(dev_priv, pipe,
23538ef1 3416 intel_crtc->config.has_pch_encoder, false);
4f771f10 3417 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3418 intel_enable_planes(crtc);
5c38d48c 3419 intel_crtc_update_cursor(crtc, true);
4f771f10 3420
42db64ef
PZ		 3421 hsw_enable_ips(intel_crtc);
3422
5bfe2ac0 3423 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3424 lpt_pch_enable(crtc);
4f771f10
PZ		 3425
3426 mutex_lock(&dev->struct_mutex);
3427 intel_update_fbc(dev);
3428 mutex_unlock(&dev->struct_mutex);
3429
4f771f10
PZ		 3430 for_each_encoder_on_crtc(dev, crtc, encoder)
3431 encoder->enable(encoder);
3432
4f771f10
PZ		 3433 /*
3434 * There seems to be a race in PCH platform hw (at least on some
3435 * outputs) where an enabled pipe still completes any pageflip right
3436 * away (as if the pipe is off) instead of waiting for vblank. As soon
3437 * as the first vblank happend, everything works as expected. Hence just
3438 * wait for one vblank before returning to avoid strange things
3439 * happening.
3440 */
3441 intel_wait_for_vblank(dev, intel_crtc->pipe);
3442}
3443
3f8dce3a
DV		 3444static void ironlake_pfit_disable(struct intel_crtc *crtc)
3445{
3446 struct drm_device *dev = crtc->base.dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448 int pipe = crtc->pipe;
3449
3450 /* To avoid upsetting the power well on haswell only disable the pfit if
3451 * it's in use. The hw state code will make sure we get this right. */
3452 if (crtc->config.pch_pfit.size) {
3453 I915_WRITE(PF_CTL(pipe), 0);
3454 I915_WRITE(PF_WIN_POS(pipe), 0);
3455 I915_WRITE(PF_WIN_SZ(pipe), 0);
3456 }
3457}
3458
6be4a607
JB		 3459static void ironlake_crtc_disable(struct drm_crtc *crtc)
3460{
3461 struct drm_device *dev = crtc->dev;
3462 struct drm_i915_private *dev_priv = dev->dev_private;
3463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3464 struct intel_encoder *encoder;
6be4a607
JB		 3465 int pipe = intel_crtc->pipe;
3466 int plane = intel_crtc->plane;
5eddb70b 3467 u32 reg, temp;
b52eb4dc 3468
ef9c3aee 3469
f7abfe8b
CW		 3470 if (!intel_crtc->active)
3471 return;
3472
ea9d758d
DV		 3473 for_each_encoder_on_crtc(dev, crtc, encoder)
3474 encoder->disable(encoder);
3475
e6c3a2a6 3476 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3477 drm_vblank_off(dev, pipe);
913d8d11 3478
5c3fe8b0 3479 if (dev_priv->fbc.plane == plane)
973d04f9 3480 intel_disable_fbc(dev);
2c07245f 3481
0d5b8c61 3482 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3483 intel_disable_planes(crtc);
0d5b8c61
VS		 3484 intel_disable_plane(dev_priv, plane, pipe);
3485
d925c59a
DV		 3486 if (intel_crtc->config.has_pch_encoder)
3487 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3488
b24e7179 3489 intel_disable_pipe(dev_priv, pipe);
32f9d658 3490
3f8dce3a 3491 ironlake_pfit_disable(intel_crtc);
2c07245f 3492
bf49ec8c
DV		 3493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 if (encoder->post_disable)
3495 encoder->post_disable(encoder);
2c07245f 3496
d925c59a
DV		 3497 if (intel_crtc->config.has_pch_encoder) {
3498 ironlake_fdi_disable(crtc);
913d8d11 3499
d925c59a
DV		 3500 ironlake_disable_pch_transcoder(dev_priv, pipe);
3501 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3502
d925c59a
DV		 3503 if (HAS_PCH_CPT(dev)) {
3504 /* disable TRANS_DP_CTL */
3505 reg = TRANS_DP_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3508 TRANS_DP_PORT_SEL_MASK);
3509 temp |= TRANS_DP_PORT_SEL_NONE;
3510 I915_WRITE(reg, temp);
3511
3512 /* disable DPLL_SEL */
3513 temp = I915_READ(PCH_DPLL_SEL);
11887397 3514 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3515 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3516 }
e3421a18 3517
d925c59a 3518 /* disable PCH DPLL */
e72f9fbf 3519 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3520
d925c59a
DV		 3521 ironlake_fdi_pll_disable(intel_crtc);
3522 }
6b383a7f 3523
f7abfe8b 3524 intel_crtc->active = false;
6b383a7f 3525 intel_update_watermarks(dev);
d1ebd816
BW		 3526
3527 mutex_lock(&dev->struct_mutex);
6b383a7f 3528 intel_update_fbc(dev);
d1ebd816 3529 mutex_unlock(&dev->struct_mutex);
6be4a607 3530}
1b3c7a47 3531
4f771f10 3532static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3533{
4f771f10
PZ		 3534 struct drm_device *dev = crtc->dev;
3535 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3537 struct intel_encoder *encoder;
3538 int pipe = intel_crtc->pipe;
3539 int plane = intel_crtc->plane;
3b117c8f 3540 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3541
4f771f10
PZ		 3542 if (!intel_crtc->active)
3543 return;
3544
3545 for_each_encoder_on_crtc(dev, crtc, encoder)
3546 encoder->disable(encoder);
3547
3548 intel_crtc_wait_for_pending_flips(crtc);
3549 drm_vblank_off(dev, pipe);
4f771f10 3550
891348b2 3551 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3552 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3553 intel_disable_fbc(dev);
3554
42db64ef
PZ		 3555 hsw_disable_ips(intel_crtc);
3556
0d5b8c61 3557 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3558 intel_disable_planes(crtc);
891348b2
RV		 3559 intel_disable_plane(dev_priv, plane, pipe);
3560
8664281b
PZ		 3561 if (intel_crtc->config.has_pch_encoder)
3562 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3563 intel_disable_pipe(dev_priv, pipe);
3564
ad80a810 3565 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3566
3f8dce3a 3567 ironlake_pfit_disable(intel_crtc);
4f771f10 3568
1f544388 3569 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3570
3571 for_each_encoder_on_crtc(dev, crtc, encoder)
3572 if (encoder->post_disable)
3573 encoder->post_disable(encoder);
3574
88adfff1 3575 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3576 lpt_disable_pch_transcoder(dev_priv);
8664281b 3577 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3578 intel_ddi_fdi_disable(crtc);
83616634 3579 }
4f771f10
PZ		 3580
3581 intel_crtc->active = false;
3582 intel_update_watermarks(dev);
3583
3584 mutex_lock(&dev->struct_mutex);
3585 intel_update_fbc(dev);
3586 mutex_unlock(&dev->struct_mutex);
3587}
3588
ee7b9f93
JB		 3589static void ironlake_crtc_off(struct drm_crtc *crtc)
3590{
3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3592 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3593}
3594
6441ab5f
PZ		 3595static void haswell_crtc_off(struct drm_crtc *crtc)
3596{
3597 intel_ddi_put_crtc_pll(crtc);
3598}
3599
02e792fb
DV		 3600static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3601{
02e792fb 3602 if (!enable && intel_crtc->overlay) {
23f09ce3 3603 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3604 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3605
23f09ce3 3606 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3607 dev_priv->mm.interruptible = false;
3608 (void) intel_overlay_switch_off(intel_crtc->overlay);
3609 dev_priv->mm.interruptible = true;
23f09ce3 3610 mutex_unlock(&dev->struct_mutex);
02e792fb 3611 }
02e792fb 3612
5dcdbcb0
CW		 3613 /* Let userspace switch the overlay on again. In most cases userspace
3614 * has to recompute where to put it anyway.
3615 */
02e792fb
DV		 3616}
3617
61bc95c1
EE		 3618/**
3619 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3620 * cursor plane briefly if not already running after enabling the display
3621 * plane.
3622 * This workaround avoids occasional blank screens when self refresh is
3623 * enabled.
3624 */
3625static void
3626g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3627{
3628 u32 cntl = I915_READ(CURCNTR(pipe));
3629
3630 if ((cntl & CURSOR_MODE) == 0) {
3631 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3632
3633 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3634 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3635 intel_wait_for_vblank(dev_priv->dev, pipe);
3636 I915_WRITE(CURCNTR(pipe), cntl);
3637 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3638 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3639 }
3640}
3641
2dd24552
JB		 3642static void i9xx_pfit_enable(struct intel_crtc *crtc)
3643{
3644 struct drm_device *dev = crtc->base.dev;
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 struct intel_crtc_config *pipe_config = &crtc->config;
3647
328d8e82 3648 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3649 return;
3650
2dd24552 3651 /*
c0b03411
DV		 3652 * The panel fitter should only be adjusted whilst the pipe is disabled,
3653 * according to register description and PRM.
2dd24552 3654 */
c0b03411
DV		 3655 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3656 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3657
b074cec8
JB		 3658 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3659 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3660
3661 /* Border color in case we don't scale up to the full screen. Black by
3662 * default, change to something else for debugging. */
3663 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3664}
3665
89b667f8
JB		 3666static void valleyview_crtc_enable(struct drm_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671 struct intel_encoder *encoder;
3672 int pipe = intel_crtc->pipe;
3673 int plane = intel_crtc->plane;
23538ef1 3674 bool is_dsi;
89b667f8
JB		 3675
3676 WARN_ON(!crtc->enabled);
3677
3678 if (intel_crtc->active)
3679 return;
3680
3681 intel_crtc->active = true;
3682 intel_update_watermarks(dev);
3683
89b667f8
JB		 3684 for_each_encoder_on_crtc(dev, crtc, encoder)
3685 if (encoder->pre_pll_enable)
3686 encoder->pre_pll_enable(encoder);
3687
23538ef1
JN		 3688 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3689
426115cf 3690 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3691
3692 for_each_encoder_on_crtc(dev, crtc, encoder)
3693 if (encoder->pre_enable)
3694 encoder->pre_enable(encoder);
3695
2dd24552
JB		 3696 i9xx_pfit_enable(intel_crtc);
3697
63cbb074
VS		 3698 intel_crtc_load_lut(crtc);
3699
23538ef1 3700 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3701 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3702 intel_enable_planes(crtc);
5c38d48c 3703 intel_crtc_update_cursor(crtc, true);
89b667f8 3704
89b667f8 3705 intel_update_fbc(dev);
5004945f
JN		 3706
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 encoder->enable(encoder);
89b667f8
JB		 3709}
3710
0b8765c6 3711static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3712{
3713 struct drm_device *dev = crtc->dev;
79e53945
JB		 3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3716 struct intel_encoder *encoder;
79e53945 3717 int pipe = intel_crtc->pipe;
80824003 3718 int plane = intel_crtc->plane;
79e53945 3719
08a48469
DV		 3720 WARN_ON(!crtc->enabled);
3721
f7abfe8b
CW		 3722 if (intel_crtc->active)
3723 return;
3724
3725 intel_crtc->active = true;
6b383a7f
CW		 3726 intel_update_watermarks(dev);
3727
9d6d9f19
MK		 3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 if (encoder->pre_enable)
3730 encoder->pre_enable(encoder);
3731
f6736a1a
DV		 3732 i9xx_enable_pll(intel_crtc);
3733
2dd24552
JB		 3734 i9xx_pfit_enable(intel_crtc);
3735
63cbb074
VS		 3736 intel_crtc_load_lut(crtc);
3737
23538ef1 3738 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3739 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3740 intel_enable_planes(crtc);
22e407d7 3741 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3742 if (IS_G4X(dev))
3743 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3744 intel_crtc_update_cursor(crtc, true);
79e53945 3745
0b8765c6
JB		 3746 /* Give the overlay scaler a chance to enable if it's on this pipe */
3747 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3748
f440eb13 3749 intel_update_fbc(dev);
ef9c3aee 3750
fa5c73b1
DV		 3751 for_each_encoder_on_crtc(dev, crtc, encoder)
3752 encoder->enable(encoder);
0b8765c6 3753}
79e53945 3754
87476d63
DV		 3755static void i9xx_pfit_disable(struct intel_crtc *crtc)
3756{
3757 struct drm_device *dev = crtc->base.dev;
3758 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3759
328d8e82
DV		 3760 if (!crtc->config.gmch_pfit.control)
3761 return;
87476d63 3762
328d8e82 3763 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3764
328d8e82
DV		 3765 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3766 I915_READ(PFIT_CONTROL));
3767 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3768}
3769
0b8765c6
JB		 3770static void i9xx_crtc_disable(struct drm_crtc *crtc)
3771{
3772 struct drm_device *dev = crtc->dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3775 struct intel_encoder *encoder;
0b8765c6
JB		 3776 int pipe = intel_crtc->pipe;
3777 int plane = intel_crtc->plane;
ef9c3aee 3778
f7abfe8b
CW		 3779 if (!intel_crtc->active)
3780 return;
3781
ea9d758d
DV		 3782 for_each_encoder_on_crtc(dev, crtc, encoder)
3783 encoder->disable(encoder);
3784
0b8765c6 3785 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3786 intel_crtc_wait_for_pending_flips(crtc);
3787 drm_vblank_off(dev, pipe);
0b8765c6 3788
5c3fe8b0 3789 if (dev_priv->fbc.plane == plane)
973d04f9 3790 intel_disable_fbc(dev);
79e53945 3791
0d5b8c61
VS		 3792 intel_crtc_dpms_overlay(intel_crtc, false);
3793 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3794 intel_disable_planes(crtc);
b24e7179 3795 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3796
b24e7179 3797 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3798
87476d63 3799 i9xx_pfit_disable(intel_crtc);
24a1f16d 3800
89b667f8
JB		 3801 for_each_encoder_on_crtc(dev, crtc, encoder)
3802 if (encoder->post_disable)
3803 encoder->post_disable(encoder);
3804
50b44a44 3805 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3806
f7abfe8b 3807 intel_crtc->active = false;
6b383a7f
CW		 3808 intel_update_fbc(dev);
3809 intel_update_watermarks(dev);
0b8765c6
JB		 3810}
3811
ee7b9f93
JB		 3812static void i9xx_crtc_off(struct drm_crtc *crtc)
3813{
3814}
3815
976f8a20
DV		 3816static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3817 bool enabled)
2c07245f
ZW		 3818{
3819 struct drm_device *dev = crtc->dev;
3820 struct drm_i915_master_private *master_priv;
3821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3822 int pipe = intel_crtc->pipe;
79e53945
JB		 3823
3824 if (!dev->primary->master)
3825 return;
3826
3827 master_priv = dev->primary->master->driver_priv;
3828 if (!master_priv->sarea_priv)
3829 return;
3830
79e53945
JB		 3831 switch (pipe) {
3832 case 0:
3833 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3834 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3835 break;
3836 case 1:
3837 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3838 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3839 break;
3840 default:
9db4a9c7 3841 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3842 break;
3843 }
79e53945
JB		 3844}
3845
976f8a20
DV		 3846/**
3847 * Sets the power management mode of the pipe and plane.
3848 */
3849void intel_crtc_update_dpms(struct drm_crtc *crtc)
3850{
3851 struct drm_device *dev = crtc->dev;
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 struct intel_encoder *intel_encoder;
3854 bool enable = false;
3855
3856 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3857 enable |= intel_encoder->connectors_active;
3858
3859 if (enable)
3860 dev_priv->display.crtc_enable(crtc);
3861 else
3862 dev_priv->display.crtc_disable(crtc);
3863
3864 intel_crtc_update_sarea(crtc, enable);
3865}
3866
cdd59983
CW		 3867static void intel_crtc_disable(struct drm_crtc *crtc)
3868{
cdd59983 3869 struct drm_device *dev = crtc->dev;
976f8a20 3870 struct drm_connector *connector;
ee7b9f93 3871 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3873
976f8a20
DV		 3874 /* crtc should still be enabled when we disable it. */
3875 WARN_ON(!crtc->enabled);
3876
3877 dev_priv->display.crtc_disable(crtc);
c77bf565 3878 intel_crtc->eld_vld = false;
976f8a20 3879 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3880 dev_priv->display.off(crtc);
3881
931872fc
CW		 3882 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3883 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3884
3885 if (crtc->fb) {
3886 mutex_lock(&dev->struct_mutex);
1690e1eb 3887 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3888 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3889 crtc->fb = NULL;
3890 }
3891
3892 /* Update computed state. */
3893 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3894 if (!connector->encoder || !connector->encoder->crtc)
3895 continue;
3896
3897 if (connector->encoder->crtc != crtc)
3898 continue;
3899
3900 connector->dpms = DRM_MODE_DPMS_OFF;
3901 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3902 }
3903}
3904
ea5b213a 3905void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3906{
4ef69c7a 3907 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3908
ea5b213a
CW		 3909 drm_encoder_cleanup(encoder);
3910 kfree(intel_encoder);
7e7d76c3
JB		 3911}
3912
9237329d 3913/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3914 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3915 * state of the entire output pipe. */
9237329d 3916static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3917{
5ab432ef
DV		 3918 if (mode == DRM_MODE_DPMS_ON) {
3919 encoder->connectors_active = true;
3920
b2cabb0e 3921 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3922 } else {
3923 encoder->connectors_active = false;
3924
b2cabb0e 3925 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3926 }
79e53945
JB		 3927}
3928
0a91ca29
DV		 3929/* Cross check the actual hw state with our own modeset state tracking (and it's
3930 * internal consistency). */
b980514c 3931static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3932{
0a91ca29
DV		 3933 if (connector->get_hw_state(connector)) {
3934 struct intel_encoder *encoder = connector->encoder;
3935 struct drm_crtc *crtc;
3936 bool encoder_enabled;
3937 enum pipe pipe;
3938
3939 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3940 connector->base.base.id,
3941 drm_get_connector_name(&connector->base));
3942
3943 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3944 "wrong connector dpms state\n");
3945 WARN(connector->base.encoder != &encoder->base,
3946 "active connector not linked to encoder\n");
3947 WARN(!encoder->connectors_active,
3948 "encoder->connectors_active not set\n");
3949
3950 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3951 WARN(!encoder_enabled, "encoder not enabled\n");
3952 if (WARN_ON(!encoder->base.crtc))
3953 return;
3954
3955 crtc = encoder->base.crtc;
3956
3957 WARN(!crtc->enabled, "crtc not enabled\n");
3958 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3959 WARN(pipe != to_intel_crtc(crtc)->pipe,
3960 "encoder active on the wrong pipe\n");
3961 }
79e53945
JB		 3962}
3963
5ab432ef
DV		 3964/* Even simpler default implementation, if there's really no special case to
3965 * consider. */
3966void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3967{
5ab432ef 3968 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3969
5ab432ef
DV		 3970 /* All the simple cases only support two dpms states. */
3971 if (mode != DRM_MODE_DPMS_ON)
3972 mode = DRM_MODE_DPMS_OFF;
d4270e57 3973
5ab432ef
DV		 3974 if (mode == connector->dpms)
3975 return;
3976
3977 connector->dpms = mode;
3978
3979 /* Only need to change hw state when actually enabled */
3980 if (encoder->base.crtc)
3981 intel_encoder_dpms(encoder, mode);
3982 else
8af6cf88 3983 WARN_ON(encoder->connectors_active != false);
0a91ca29 3984
b980514c 3985 intel_modeset_check_state(connector->dev);
79e53945
JB		 3986}
3987
f0947c37
DV		 3988/* Simple connector->get_hw_state implementation for encoders that support only
3989 * one connector and no cloning and hence the encoder state determines the state
3990 * of the connector. */
3991bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3992{
24929352 3993 enum pipe pipe = 0;
f0947c37 3994 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3995
f0947c37 3996 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3997}
3998
1857e1da
DV		 3999static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4000 struct intel_crtc_config *pipe_config)
4001{
4002 struct drm_i915_private *dev_priv = dev->dev_private;
4003 struct intel_crtc *pipe_B_crtc =
4004 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4005
4006 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4008 if (pipe_config->fdi_lanes > 4) {
4009 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4010 pipe_name(pipe), pipe_config->fdi_lanes);
4011 return false;
4012 }
4013
4014 if (IS_HASWELL(dev)) {
4015 if (pipe_config->fdi_lanes > 2) {
4016 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4017 pipe_config->fdi_lanes);
4018 return false;
4019 } else {
4020 return true;
4021 }
4022 }
4023
4024 if (INTEL_INFO(dev)->num_pipes == 2)
4025 return true;
4026
4027 /* Ivybridge 3 pipe is really complicated */
4028 switch (pipe) {
4029 case PIPE_A:
4030 return true;
4031 case PIPE_B:
4032 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4033 pipe_config->fdi_lanes > 2) {
4034 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 return false;
4037 }
4038 return true;
4039 case PIPE_C:
1e833f40 4040 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4041 pipe_B_crtc->config.fdi_lanes <= 2) {
4042 if (pipe_config->fdi_lanes > 2) {
4043 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4044 pipe_name(pipe), pipe_config->fdi_lanes);
4045 return false;
4046 }
4047 } else {
4048 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4049 return false;
4050 }
4051 return true;
4052 default:
4053 BUG();
4054 }
4055}
4056
e29c22c0
DV		 4057#define RETRY 1
4058static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4059 struct intel_crtc_config *pipe_config)
877d48d5 4060{
1857e1da 4061 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4062 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4063 int lane, link_bw, fdi_dotclock;
e29c22c0 4064 bool setup_ok, needs_recompute = false;
877d48d5 4065
e29c22c0 4066retry:
877d48d5
DV		 4067 /* FDI is a binary signal running at ~2.7GHz, encoding
4068 * each output octet as 10 bits. The actual frequency
4069 * is stored as a divider into a 100MHz clock, and the
4070 * mode pixel clock is stored in units of 1KHz.
4071 * Hence the bw of each lane in terms of the mode signal
4072 * is:
4073 */
4074 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4075
ff9a6750 4076 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4077 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4078
2bd89a07 4079 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4080 pipe_config->pipe_bpp);
4081
4082 pipe_config->fdi_lanes = lane;
4083
2bd89a07 4084 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4085 link_bw, &pipe_config->fdi_m_n);
1857e1da 4086
e29c22c0
DV		 4087 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4088 intel_crtc->pipe, pipe_config);
4089 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4090 pipe_config->pipe_bpp -= 2*3;
4091 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4092 pipe_config->pipe_bpp);
4093 needs_recompute = true;
4094 pipe_config->bw_constrained = true;
4095
4096 goto retry;
4097 }
4098
4099 if (needs_recompute)
4100 return RETRY;
4101
4102 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4103}
4104
42db64ef
PZ		 4105static void hsw_compute_ips_config(struct intel_crtc *crtc,
4106 struct intel_crtc_config *pipe_config)
4107{
3c4ca58c
PZ		 4108 pipe_config->ips_enabled = i915_enable_ips &&
4109 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4110 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4111}
4112
a43f6e0f 4113static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4114 struct intel_crtc_config *pipe_config)
79e53945 4115{
a43f6e0f 4116 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4117 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4118
bad720ff 4119 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4120 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4121 if (pipe_config->requested_mode.clock * 3
4122 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4123 return -EINVAL;
2c07245f 4124 }
89749350 4125
8693a824
DL		 4126 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4127 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4128 */
4129 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4130 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4131 return -EINVAL;
44f46b42 4132
bd080ee5 4133 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4134 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4135 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4136 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4137 * for lvds. */
4138 pipe_config->pipe_bpp = 8*3;
4139 }
4140
f5adf94e 4141 if (HAS_IPS(dev))
a43f6e0f
DV		 4142 hsw_compute_ips_config(crtc, pipe_config);
4143
4144 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4145 * clock survives for now. */
4146 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4147 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4148
877d48d5 4149 if (pipe_config->has_pch_encoder)
a43f6e0f 4150 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4151
e29c22c0 4152 return 0;
79e53945
JB		 4153}
4154
25eb05fc
JB		 4155static int valleyview_get_display_clock_speed(struct drm_device *dev)
4156{
4157 return 400000; /* FIXME */
4158}
4159
e70236a8
JB		 4160static int i945_get_display_clock_speed(struct drm_device *dev)
4161{
4162 return 400000;
4163}
79e53945 4164
e70236a8 4165static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4166{
e70236a8
JB		 4167 return 333000;
4168}
79e53945 4169
e70236a8
JB		 4170static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4171{
4172 return 200000;
4173}
79e53945 4174
257a7ffc
DV		 4175static int pnv_get_display_clock_speed(struct drm_device *dev)
4176{
4177 u16 gcfgc = 0;
4178
4179 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4180
4181 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4182 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4183 return 267000;
4184 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4185 return 333000;
4186 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4187 return 444000;
4188 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4189 return 200000;
4190 default:
4191 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4192 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4193 return 133000;
4194 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4195 return 167000;
4196 }
4197}
4198
e70236a8
JB		 4199static int i915gm_get_display_clock_speed(struct drm_device *dev)
4200{
4201 u16 gcfgc = 0;
79e53945 4202
e70236a8
JB		 4203 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4204
4205 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4206 return 133000;
4207 else {
4208 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4209 case GC_DISPLAY_CLOCK_333_MHZ:
4210 return 333000;
4211 default:
4212 case GC_DISPLAY_CLOCK_190_200_MHZ:
4213 return 190000;
79e53945 4214 }
e70236a8
JB		 4215 }
4216}
4217
4218static int i865_get_display_clock_speed(struct drm_device *dev)
4219{
4220 return 266000;
4221}
4222
4223static int i855_get_display_clock_speed(struct drm_device *dev)
4224{
4225 u16 hpllcc = 0;
4226 /* Assume that the hardware is in the high speed state. This
4227 * should be the default.
4228 */
4229 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4230 case GC_CLOCK_133_200:
4231 case GC_CLOCK_100_200:
4232 return 200000;
4233 case GC_CLOCK_166_250:
4234 return 250000;
4235 case GC_CLOCK_100_133:
79e53945 4236 return 133000;
e70236a8 4237 }
79e53945 4238
e70236a8
JB		 4239 /* Shouldn't happen */
4240 return 0;
4241}
79e53945 4242
e70236a8
JB		 4243static int i830_get_display_clock_speed(struct drm_device *dev)
4244{
4245 return 133000;
79e53945
JB		 4246}
4247
2c07245f 4248static void
a65851af 4249intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4250{
a65851af
VS		 4251 while (*num > DATA_LINK_M_N_MASK ||
4252 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4253 *num >>= 1;
4254 *den >>= 1;
4255 }
4256}
4257
a65851af
VS		 4258static void compute_m_n(unsigned int m, unsigned int n,
4259 uint32_t *ret_m, uint32_t *ret_n)
4260{
4261 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4262 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4263 intel_reduce_m_n_ratio(ret_m, ret_n);
4264}
4265
e69d0bc1
DV		 4266void
4267intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4268 int pixel_clock, int link_clock,
4269 struct intel_link_m_n *m_n)
2c07245f 4270{
e69d0bc1 4271 m_n->tu = 64;
a65851af
VS		 4272
4273 compute_m_n(bits_per_pixel * pixel_clock,
4274 link_clock * nlanes * 8,
4275 &m_n->gmch_m, &m_n->gmch_n);
4276
4277 compute_m_n(pixel_clock, link_clock,
4278 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4279}
4280
a7615030
CW		 4281static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4282{
72bbe58c
KP		 4283 if (i915_panel_use_ssc >= 0)
4284 return i915_panel_use_ssc != 0;
41aa3448 4285 return dev_priv->vbt.lvds_use_ssc
435793df 4286 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4287}
4288
a0c4da24
JB		 4289static int vlv_get_refclk(struct drm_crtc *crtc)
4290{
4291 struct drm_device *dev = crtc->dev;
4292 struct drm_i915_private *dev_priv = dev->dev_private;
4293 int refclk = 27000; /* for DP & HDMI */
4294
4295 return 100000; /* only one validated so far */
4296
4297 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4298 refclk = 96000;
4299 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4300 if (intel_panel_use_ssc(dev_priv))
4301 refclk = 100000;
4302 else
4303 refclk = 96000;
4304 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4305 refclk = 100000;
4306 }
4307
4308 return refclk;
4309}
4310
c65d77d8
JB		 4311static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4312{
4313 struct drm_device *dev = crtc->dev;
4314 struct drm_i915_private *dev_priv = dev->dev_private;
4315 int refclk;
4316
a0c4da24
JB		 4317 if (IS_VALLEYVIEW(dev)) {
4318 refclk = vlv_get_refclk(crtc);
4319 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4320 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4321 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4322 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4323 refclk / 1000);
4324 } else if (!IS_GEN2(dev)) {
4325 refclk = 96000;
4326 } else {
4327 refclk = 48000;
4328 }
4329
4330 return refclk;
4331}
4332
7429e9d4 4333static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4334{
7df00d7a 4335 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4336}
f47709a9 4337
7429e9d4
DV		 4338static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4339{
4340 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4341}
4342
f47709a9 4343static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4344 intel_clock_t *reduced_clock)
4345{
f47709a9 4346 struct drm_device *dev = crtc->base.dev;
a7516a05 4347 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4348 int pipe = crtc->pipe;
a7516a05
JB		 4349 u32 fp, fp2 = 0;
4350
4351 if (IS_PINEVIEW(dev)) {
7429e9d4 4352 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4353 if (reduced_clock)
7429e9d4 4354 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4355 } else {
7429e9d4 4356 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4357 if (reduced_clock)
7429e9d4 4358 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4359 }
4360
4361 I915_WRITE(FP0(pipe), fp);
8bcc2795 4362 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4363
f47709a9
DV		 4364 crtc->lowfreq_avail = false;
4365 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4366 reduced_clock && i915_powersave) {
4367 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4368 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4369 crtc->lowfreq_avail = true;
a7516a05
JB		 4370 } else {
4371 I915_WRITE(FP1(pipe), fp);
8bcc2795 4372 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4373 }
4374}
4375
89b667f8
JB		 4376static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4377{
4378 u32 reg_val;
4379
4380 /*
4381 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4382 * and set it to a reasonable value instead.
4383 */
ae99258f 4384 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4385 reg_val &= 0xffffff00;
4386 reg_val |= 0x00000030;
ae99258f 4387 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4388
ae99258f 4389 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4390 reg_val &= 0x8cffffff;
4391 reg_val = 0x8c000000;
ae99258f 4392 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4393
ae99258f 4394 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4395 reg_val &= 0xffffff00;
ae99258f 4396 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4397
ae99258f 4398 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4399 reg_val &= 0x00ffffff;
4400 reg_val |= 0xb0000000;
ae99258f 4401 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4402}
4403
b551842d
DV		 4404static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4405 struct intel_link_m_n *m_n)
4406{
4407 struct drm_device *dev = crtc->base.dev;
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409 int pipe = crtc->pipe;
4410
e3b95f1e
DV		 4411 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4412 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4413 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4414 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4415}
4416
4417static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4418 struct intel_link_m_n *m_n)
4419{
4420 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 int pipe = crtc->pipe;
4423 enum transcoder transcoder = crtc->config.cpu_transcoder;
4424
4425 if (INTEL_INFO(dev)->gen >= 5) {
4426 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4427 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4428 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4429 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4430 } else {
e3b95f1e
DV		 4431 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4432 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4433 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4434 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4435 }
4436}
4437
03afc4a2
DV		 4438static void intel_dp_set_m_n(struct intel_crtc *crtc)
4439{
4440 if (crtc->config.has_pch_encoder)
4441 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4442 else
4443 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4444}
4445
f47709a9 4446static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4447{
f47709a9 4448 struct drm_device *dev = crtc->base.dev;
a0c4da24 4449 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4450 int pipe = crtc->pipe;
89b667f8 4451 u32 dpll, mdiv;
a0c4da24 4452 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4453 u32 coreclk, reg_val, dpll_md;
a0c4da24 4454
09153000
DV		 4455 mutex_lock(&dev_priv->dpio_lock);
4456
f47709a9
DV		 4457 bestn = crtc->config.dpll.n;
4458 bestm1 = crtc->config.dpll.m1;
4459 bestm2 = crtc->config.dpll.m2;
4460 bestp1 = crtc->config.dpll.p1;
4461 bestp2 = crtc->config.dpll.p2;
a0c4da24 4462
89b667f8
JB		 4463 /* See eDP HDMI DPIO driver vbios notes doc */
4464
4465 /* PLL B needs special handling */
4466 if (pipe)
4467 vlv_pllb_recal_opamp(dev_priv);
4468
4469 /* Set up Tx target for periodic Rcomp update */
ae99258f 4470 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4471
4472 /* Disable target IRef on PLL */
ae99258f 4473 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4474 reg_val &= 0x00ffffff;
ae99258f 4475 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4476
4477 /* Disable fast lock */
ae99258f 4478 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4479
4480 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4481 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4482 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4483 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4484 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4485
4486 /*
4487 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4488 * but we don't support that).
4489 * Note: don't use the DAC post divider as it seems unstable.
4490 */
4491 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4492 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4493
a0c4da24 4494 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4495 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4496
89b667f8 4497 /* Set HBR and RBR LPF coefficients */
ff9a6750 4498 if (crtc->config.port_clock == 162000 ||
99750bd4 4499 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4500 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4501 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4502 0x009f0003);
89b667f8 4503 else
4abb2c39 4504 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4505 0x00d0000f);
4506
4507 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4508 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4509 /* Use SSC source */
4510 if (!pipe)
ae99258f 4511 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4512 0x0df40000);
4513 else
ae99258f 4514 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4515 0x0df70000);
4516 } else { /* HDMI or VGA */
4517 /* Use bend source */
4518 if (!pipe)
ae99258f 4519 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4520 0x0df70000);
4521 else
ae99258f 4522 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4523 0x0df40000);
4524 }
a0c4da24 4525
ae99258f 4526 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4527 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4528 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4529 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4530 coreclk |= 0x01000000;
ae99258f 4531 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4532
ae99258f 4533 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4534
89b667f8
JB		 4535 /* Enable DPIO clock input */
4536 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4537 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4538 if (pipe)
4539 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4540
4541 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4542 crtc->config.dpll_hw_state.dpll = dpll;
4543
ef1b460d
DV		 4544 dpll_md = (crtc->config.pixel_multiplier - 1)
4545 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4546 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4547
89b667f8
JB		 4548 if (crtc->config.has_dp_encoder)
4549 intel_dp_set_m_n(crtc);
09153000
DV		 4550
4551 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4552}
4553
f47709a9
DV		 4554static void i9xx_update_pll(struct intel_crtc *crtc,
4555 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4556 int num_connectors)
4557{
f47709a9 4558 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4559 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4560 u32 dpll;
4561 bool is_sdvo;
f47709a9 4562 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4563
f47709a9 4564 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4565
f47709a9
DV		 4566 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4567 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4568
4569 dpll = DPLL_VGA_MODE_DIS;
4570
f47709a9 4571 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4572 dpll |= DPLLB_MODE_LVDS;
4573 else
4574 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4575
ef1b460d 4576 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4577 dpll |= (crtc->config.pixel_multiplier - 1)
4578 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4579 }
198a037f
DV		 4580
4581 if (is_sdvo)
4a33e48d 4582 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4583
f47709a9 4584 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4585 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4586
4587 /* compute bitmask from p1 value */
4588 if (IS_PINEVIEW(dev))
4589 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4590 else {
4591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592 if (IS_G4X(dev) && reduced_clock)
4593 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4594 }
4595 switch (clock->p2) {
4596 case 5:
4597 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4598 break;
4599 case 7:
4600 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4601 break;
4602 case 10:
4603 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4604 break;
4605 case 14:
4606 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4607 break;
4608 }
4609 if (INTEL_INFO(dev)->gen >= 4)
4610 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4611
09ede541 4612 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4613 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4614 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4615 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4616 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4617 else
4618 dpll |= PLL_REF_INPUT_DREFCLK;
4619
4620 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4621 crtc->config.dpll_hw_state.dpll = dpll;
4622
eb1cbe48 4623 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4624 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4625 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4626 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4627 }
66e3d5c0
DV		 4628
4629 if (crtc->config.has_dp_encoder)
4630 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4631}
4632
f47709a9 4633static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4634 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4635 int num_connectors)
4636{
f47709a9 4637 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4638 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4639 u32 dpll;
f47709a9 4640 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4641
f47709a9 4642 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4643
eb1cbe48
DV		 4644 dpll = DPLL_VGA_MODE_DIS;
4645
f47709a9 4646 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4647 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4648 } else {
4649 if (clock->p1 == 2)
4650 dpll |= PLL_P1_DIVIDE_BY_TWO;
4651 else
4652 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4653 if (clock->p2 == 4)
4654 dpll |= PLL_P2_DIVIDE_BY_4;
4655 }
4656
4a33e48d
DV		 4657 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4658 dpll |= DPLL_DVO_2X_MODE;
4659
f47709a9 4660 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4661 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4662 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4663 else
4664 dpll |= PLL_REF_INPUT_DREFCLK;
4665
4666 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4667 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4668}
4669
8a654f3b 4670static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4671{
4672 struct drm_device *dev = intel_crtc->base.dev;
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4675 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4676 struct drm_display_mode *adjusted_mode =
4677 &intel_crtc->config.adjusted_mode;
4678 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4679 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4680
4681 /* We need to be careful not to changed the adjusted mode, for otherwise
4682 * the hw state checker will get angry at the mismatch. */
4683 crtc_vtotal = adjusted_mode->crtc_vtotal;
4684 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4685
4686 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4687 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4688 crtc_vtotal -= 1;
4689 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4690 vsyncshift = adjusted_mode->crtc_hsync_start
4691 - adjusted_mode->crtc_htotal / 2;
4692 } else {
4693 vsyncshift = 0;
4694 }
4695
4696 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4697 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4698
fe2b8f9d 4699 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4700 (adjusted_mode->crtc_hdisplay - 1) |
4701 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4702 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4703 (adjusted_mode->crtc_hblank_start - 1) |
4704 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4705 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4706 (adjusted_mode->crtc_hsync_start - 1) |
4707 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4708
fe2b8f9d 4709 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4710 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4711 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4712 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4713 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4714 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4715 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4716 (adjusted_mode->crtc_vsync_start - 1) |
4717 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4718
b5e508d4
PZ		 4719 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4720 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4721 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4722 * bits. */
4723 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4724 (pipe == PIPE_B || pipe == PIPE_C))
4725 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4726
b0e77b9c
PZ		 4727 /* pipesrc controls the size that is scaled from, which should
4728 * always be the user's requested size.
4729 */
4730 I915_WRITE(PIPESRC(pipe),
4731 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4732}
4733
1bd1bd80
DV		 4734static void intel_get_pipe_timings(struct intel_crtc *crtc,
4735 struct intel_crtc_config *pipe_config)
4736{
4737 struct drm_device *dev = crtc->base.dev;
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4740 uint32_t tmp;
4741
4742 tmp = I915_READ(HTOTAL(cpu_transcoder));
4743 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4744 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4745 tmp = I915_READ(HBLANK(cpu_transcoder));
4746 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4747 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4748 tmp = I915_READ(HSYNC(cpu_transcoder));
4749 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4750 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4751
4752 tmp = I915_READ(VTOTAL(cpu_transcoder));
4753 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4754 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4755 tmp = I915_READ(VBLANK(cpu_transcoder));
4756 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4757 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4758 tmp = I915_READ(VSYNC(cpu_transcoder));
4759 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4760 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4761
4762 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4763 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4764 pipe_config->adjusted_mode.crtc_vtotal += 1;
4765 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4766 }
4767
4768 tmp = I915_READ(PIPESRC(crtc->pipe));
4769 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4770 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4771}
4772
babea61d
JB		 4773static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4774 struct intel_crtc_config *pipe_config)
4775{
4776 struct drm_crtc *crtc = &intel_crtc->base;
4777
4778 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4779 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4780 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4781 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4782
4783 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4784 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4785 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4786 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4787
4788 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4789
4790 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4791 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4792}
4793
84b046f3
DV		 4794static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4795{
4796 struct drm_device *dev = intel_crtc->base.dev;
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 uint32_t pipeconf;
4799
9f11a9e4 4800 pipeconf = 0;
84b046f3
DV		 4801
4802 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4803 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4804 * core speed.
4805 *
4806 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4807 * pipe == 0 check?
4808 */
4809 if (intel_crtc->config.requested_mode.clock >
4810 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4811 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4812 }
4813
ff9ce46e
DV		 4814 /* only g4x and later have fancy bpc/dither controls */
4815 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4816 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4817 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4818 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4819 PIPECONF_DITHER_TYPE_SP;
84b046f3 4820
ff9ce46e
DV		 4821 switch (intel_crtc->config.pipe_bpp) {
4822 case 18:
4823 pipeconf |= PIPECONF_6BPC;
4824 break;
4825 case 24:
4826 pipeconf |= PIPECONF_8BPC;
4827 break;
4828 case 30:
4829 pipeconf |= PIPECONF_10BPC;
4830 break;
4831 default:
4832 /* Case prevented by intel_choose_pipe_bpp_dither. */
4833 BUG();
84b046f3
DV		 4834 }
4835 }
4836
4837 if (HAS_PIPE_CXSR(dev)) {
4838 if (intel_crtc->lowfreq_avail) {
4839 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4840 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4841 } else {
4842 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4843 }
4844 }
4845
84b046f3
DV		 4846 if (!IS_GEN2(dev) &&
4847 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4848 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4849 else
4850 pipeconf |= PIPECONF_PROGRESSIVE;
4851
9f11a9e4
DV		 4852 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4853 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4854
84b046f3
DV		 4855 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4856 POSTING_READ(PIPECONF(intel_crtc->pipe));
4857}
4858
f564048e 4859static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4860 int x, int y,
94352cf9 4861 struct drm_framebuffer *fb)
79e53945
JB		 4862{
4863 struct drm_device *dev = crtc->dev;
4864 struct drm_i915_private *dev_priv = dev->dev_private;
4865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4866 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4867 int pipe = intel_crtc->pipe;
80824003 4868 int plane = intel_crtc->plane;
c751ce4f 4869 int refclk, num_connectors = 0;
652c393a 4870 intel_clock_t clock, reduced_clock;
84b046f3 4871 u32 dspcntr;
a16af721
DV		 4872 bool ok, has_reduced_clock = false;
4873 bool is_lvds = false;
5eddb70b 4874 struct intel_encoder *encoder;
d4906093 4875 const intel_limit_t *limit;
5c3b82e2 4876 int ret;
79e53945 4877
6c2b7c12 4878 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4879 switch (encoder->type) {
79e53945
JB		 4880 case INTEL_OUTPUT_LVDS:
4881 is_lvds = true;
4882 break;
79e53945 4883 }
43565a06 4884
c751ce4f 4885 num_connectors++;
79e53945
JB		 4886 }
4887
c65d77d8 4888 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4889
d4906093
ML		 4890 /*
4891 * Returns a set of divisors for the desired target clock with the given
4892 * refclk, or FALSE. The returned values represent the clock equation:
4893 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4894 */
1b894b59 4895 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4896 ok = dev_priv->display.find_dpll(limit, crtc,
4897 intel_crtc->config.port_clock,
ee9300bb
DV		 4898 refclk, NULL, &clock);
4899 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4900 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4901 return -EINVAL;
79e53945
JB		 4902 }
4903
cda4b7d3 4904 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4905 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4906
ddc9003c 4907 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4908 /*
4909 * Ensure we match the reduced clock's P to the target clock.
4910 * If the clocks don't match, we can't switch the display clock
4911 * by using the FP0/FP1. In such case we will disable the LVDS
4912 * downclock feature.
4913 */
ee9300bb
DV		 4914 has_reduced_clock =
4915 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4916 dev_priv->lvds_downclock,
ee9300bb 4917 refclk, &clock,
5eddb70b 4918 &reduced_clock);
7026d4ac 4919 }
f47709a9
DV		 4920 /* Compat-code for transition, will disappear. */
4921 if (!intel_crtc->config.clock_set) {
4922 intel_crtc->config.dpll.n = clock.n;
4923 intel_crtc->config.dpll.m1 = clock.m1;
4924 intel_crtc->config.dpll.m2 = clock.m2;
4925 intel_crtc->config.dpll.p1 = clock.p1;
4926 intel_crtc->config.dpll.p2 = clock.p2;
4927 }
7026d4ac 4928
eb1cbe48 4929 if (IS_GEN2(dev))
8a654f3b 4930 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4931 has_reduced_clock ? &reduced_clock : NULL,
4932 num_connectors);
a0c4da24 4933 else if (IS_VALLEYVIEW(dev))
f47709a9 4934 vlv_update_pll(intel_crtc);
79e53945 4935 else
f47709a9 4936 i9xx_update_pll(intel_crtc,
eb1cbe48 4937 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4938 num_connectors);
79e53945 4939
79e53945
JB		 4940 /* Set up the display plane register */
4941 dspcntr = DISPPLANE_GAMMA_ENABLE;
4942
da6ecc5d
JB		 4943 if (!IS_VALLEYVIEW(dev)) {
4944 if (pipe == 0)
4945 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4946 else
4947 dspcntr |= DISPPLANE_SEL_PIPE_B;
4948 }
79e53945 4949
8a654f3b 4950 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4951
4952 /* pipesrc and dspsize control the size that is scaled from,
4953 * which should always be the user's requested size.
79e53945 4954 */
929c77fb
EA		 4955 I915_WRITE(DSPSIZE(plane),
4956 ((mode->vdisplay - 1) << 16) |
4957 (mode->hdisplay - 1));
4958 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4959
84b046f3
DV		 4960 i9xx_set_pipeconf(intel_crtc);
4961
f564048e
EA		 4962 I915_WRITE(DSPCNTR(plane), dspcntr);
4963 POSTING_READ(DSPCNTR(plane));
4964
94352cf9 4965 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4966
4967 intel_update_watermarks(dev);
4968
f564048e
EA		 4969 return ret;
4970}
4971
2fa2fe9a
DV		 4972static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4973 struct intel_crtc_config *pipe_config)
4974{
4975 struct drm_device *dev = crtc->base.dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 uint32_t tmp;
4978
4979 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4980 if (!(tmp & PFIT_ENABLE))
4981 return;
2fa2fe9a 4982
06922821 4983 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4984 if (INTEL_INFO(dev)->gen < 4) {
4985 if (crtc->pipe != PIPE_B)
4986 return;
2fa2fe9a
DV		 4987 } else {
4988 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4989 return;
4990 }
4991
06922821 4992 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 4993 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4994 if (INTEL_INFO(dev)->gen < 5)
4995 pipe_config->gmch_pfit.lvds_border_bits =
4996 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4997}
4998
0e8ffe1b
DV		 4999static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5000 struct intel_crtc_config *pipe_config)
5001{
5002 struct drm_device *dev = crtc->base.dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 uint32_t tmp;
5005
e143a21c 5006 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5007 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5008
0e8ffe1b
DV		 5009 tmp = I915_READ(PIPECONF(crtc->pipe));
5010 if (!(tmp & PIPECONF_ENABLE))
5011 return false;
5012
1bd1bd80
DV		 5013 intel_get_pipe_timings(crtc, pipe_config);
5014
2fa2fe9a
DV		 5015 i9xx_get_pfit_config(crtc, pipe_config);
5016
6c49f241
DV		 5017 if (INTEL_INFO(dev)->gen >= 4) {
5018 tmp = I915_READ(DPLL_MD(crtc->pipe));
5019 pipe_config->pixel_multiplier =
5020 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5021 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5022 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5023 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5024 tmp = I915_READ(DPLL(crtc->pipe));
5025 pipe_config->pixel_multiplier =
5026 ((tmp & SDVO_MULTIPLIER_MASK)
5027 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5028 } else {
5029 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5030 * port and will be fixed up in the encoder->get_config
5031 * function. */
5032 pipe_config->pixel_multiplier = 1;
5033 }
8bcc2795
DV		 5034 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5035 if (!IS_VALLEYVIEW(dev)) {
5036 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5037 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5038 } else {
5039 /* Mask out read-only status bits. */
5040 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5041 DPLL_PORTC_READY_MASK |
5042 DPLL_PORTB_READY_MASK);
8bcc2795 5043 }
6c49f241 5044
0e8ffe1b
DV		 5045 return true;
5046}
5047
dde86e2d 5048static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5049{
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5051 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5052 struct intel_encoder *encoder;
74cfd7ac 5053 u32 val, final;
13d83a67 5054 bool has_lvds = false;
199e5d79 5055 bool has_cpu_edp = false;
199e5d79 5056 bool has_panel = false;
99eb6a01
KP		 5057 bool has_ck505 = false;
5058 bool can_ssc = false;
13d83a67
JB		 5059
5060 /* We need to take the global config into account */
199e5d79
KP		 5061 list_for_each_entry(encoder, &mode_config->encoder_list,
5062 base.head) {
5063 switch (encoder->type) {
5064 case INTEL_OUTPUT_LVDS:
5065 has_panel = true;
5066 has_lvds = true;
5067 break;
5068 case INTEL_OUTPUT_EDP:
5069 has_panel = true;
2de6905f 5070 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5071 has_cpu_edp = true;
5072 break;
13d83a67
JB		 5073 }
5074 }
5075
99eb6a01 5076 if (HAS_PCH_IBX(dev)) {
41aa3448 5077 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5078 can_ssc = has_ck505;
5079 } else {
5080 has_ck505 = false;
5081 can_ssc = true;
5082 }
5083
2de6905f
ID		 5084 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5085 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5086
5087 /* Ironlake: try to setup display ref clock before DPLL
5088 * enabling. This is only under driver's control after
5089 * PCH B stepping, previous chipset stepping should be
5090 * ignoring this setting.
5091 */
74cfd7ac
CW		 5092 val = I915_READ(PCH_DREF_CONTROL);
5093
5094 /* As we must carefully and slowly disable/enable each source in turn,
5095 * compute the final state we want first and check if we need to
5096 * make any changes at all.
5097 */
5098 final = val;
5099 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5100 if (has_ck505)
5101 final |= DREF_NONSPREAD_CK505_ENABLE;
5102 else
5103 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5104
5105 final &= ~DREF_SSC_SOURCE_MASK;
5106 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5107 final &= ~DREF_SSC1_ENABLE;
5108
5109 if (has_panel) {
5110 final |= DREF_SSC_SOURCE_ENABLE;
5111
5112 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5113 final |= DREF_SSC1_ENABLE;
5114
5115 if (has_cpu_edp) {
5116 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5117 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5118 else
5119 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5120 } else
5121 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5122 } else {
5123 final |= DREF_SSC_SOURCE_DISABLE;
5124 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5125 }
5126
5127 if (final == val)
5128 return;
5129
13d83a67 5130 /* Always enable nonspread source */
74cfd7ac 5131 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5132
99eb6a01 5133 if (has_ck505)
74cfd7ac 5134 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5135 else
74cfd7ac 5136 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5137
199e5d79 5138 if (has_panel) {
74cfd7ac
CW		 5139 val &= ~DREF_SSC_SOURCE_MASK;
5140 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5141
199e5d79 5142 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5143 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5144 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5145 val |= DREF_SSC1_ENABLE;
e77166b5 5146 } else
74cfd7ac 5147 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5148
5149 /* Get SSC going before enabling the outputs */
74cfd7ac 5150 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5151 POSTING_READ(PCH_DREF_CONTROL);
5152 udelay(200);
5153
74cfd7ac 5154 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5155
5156 /* Enable CPU source on CPU attached eDP */
199e5d79 5157 if (has_cpu_edp) {
99eb6a01 5158 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5159 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5160 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5161 }
13d83a67 5162 else
74cfd7ac 5163 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5164 } else
74cfd7ac 5165 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5166
74cfd7ac 5167 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5168 POSTING_READ(PCH_DREF_CONTROL);
5169 udelay(200);
5170 } else {
5171 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5172
74cfd7ac 5173 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5174
5175 /* Turn off CPU output */
74cfd7ac 5176 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5177
74cfd7ac 5178 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5179 POSTING_READ(PCH_DREF_CONTROL);
5180 udelay(200);
5181
5182 /* Turn off the SSC source */
74cfd7ac
CW		 5183 val &= ~DREF_SSC_SOURCE_MASK;
5184 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5185
5186 /* Turn off SSC1 */
74cfd7ac 5187 val &= ~DREF_SSC1_ENABLE;
199e5d79 5188
74cfd7ac 5189 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5190 POSTING_READ(PCH_DREF_CONTROL);
5191 udelay(200);
5192 }
74cfd7ac
CW		 5193
5194 BUG_ON(val != final);
13d83a67
JB		 5195}
5196
f31f2d55 5197static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5198{
f31f2d55 5199 uint32_t tmp;
dde86e2d 5200
0ff066a9
PZ		 5201 tmp = I915_READ(SOUTH_CHICKEN2);
5202 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5203 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5204
0ff066a9
PZ		 5205 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5206 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5207 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5208
0ff066a9
PZ		 5209 tmp = I915_READ(SOUTH_CHICKEN2);
5210 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5211 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5212
0ff066a9
PZ		 5213 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5214 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5215 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5216}
5217
5218/* WaMPhyProgramming:hsw */
5219static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5220{
5221 uint32_t tmp;
dde86e2d
PZ		 5222
5223 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5224 tmp &= ~(0xFF << 24);
5225 tmp |= (0x12 << 24);
5226 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5227
dde86e2d
PZ		 5228 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5229 tmp |= (1 << 11);
5230 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5231
5232 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5233 tmp |= (1 << 11);
5234 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5235
dde86e2d
PZ		 5236 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5237 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5238 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5239
5240 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5241 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5242 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5243
0ff066a9
PZ		 5244 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5245 tmp &= ~(7 << 13);
5246 tmp |= (5 << 13);
5247 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5248
0ff066a9
PZ		 5249 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5250 tmp &= ~(7 << 13);
5251 tmp |= (5 << 13);
5252 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5253
5254 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5255 tmp &= ~0xFF;
5256 tmp |= 0x1C;
5257 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5258
5259 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5260 tmp &= ~0xFF;
5261 tmp |= 0x1C;
5262 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5263
5264 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5265 tmp &= ~(0xFF << 16);
5266 tmp |= (0x1C << 16);
5267 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5270 tmp &= ~(0xFF << 16);
5271 tmp |= (0x1C << 16);
5272 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5273
0ff066a9
PZ		 5274 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5275 tmp |= (1 << 27);
5276 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5277
0ff066a9
PZ		 5278 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5279 tmp |= (1 << 27);
5280 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5281
0ff066a9
PZ		 5282 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5283 tmp &= ~(0xF << 28);
5284 tmp |= (4 << 28);
5285 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5286
0ff066a9
PZ		 5287 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5288 tmp &= ~(0xF << 28);
5289 tmp |= (4 << 28);
5290 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5291}
5292
2fa86a1f
PZ		 5293/* Implements 3 different sequences from BSpec chapter "Display iCLK
5294 * Programming" based on the parameters passed:
5295 * - Sequence to enable CLKOUT_DP
5296 * - Sequence to enable CLKOUT_DP without spread
5297 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5298 */
5299static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5300 bool with_fdi)
f31f2d55
PZ		 5301{
5302 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5303 uint32_t reg, tmp;
5304
5305 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5306 with_spread = true;
5307 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5308 with_fdi, "LP PCH doesn't have FDI\n"))
5309 with_fdi = false;
f31f2d55
PZ		 5310
5311 mutex_lock(&dev_priv->dpio_lock);
5312
5313 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5314 tmp &= ~SBI_SSCCTL_DISABLE;
5315 tmp |= SBI_SSCCTL_PATHALT;
5316 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5317
5318 udelay(24);
5319
2fa86a1f
PZ		 5320 if (with_spread) {
5321 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5322 tmp &= ~SBI_SSCCTL_PATHALT;
5323 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5324
2fa86a1f
PZ		 5325 if (with_fdi) {
5326 lpt_reset_fdi_mphy(dev_priv);
5327 lpt_program_fdi_mphy(dev_priv);
5328 }
5329 }
dde86e2d 5330
2fa86a1f
PZ		 5331 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5332 SBI_GEN0 : SBI_DBUFF0;
5333 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5334 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5335 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5336
5337 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5338}
5339
47701c3b
PZ		 5340/* Sequence to disable CLKOUT_DP */
5341static void lpt_disable_clkout_dp(struct drm_device *dev)
5342{
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344 uint32_t reg, tmp;
5345
5346 mutex_lock(&dev_priv->dpio_lock);
5347
5348 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5349 SBI_GEN0 : SBI_DBUFF0;
5350 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5351 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5352 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5353
5354 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5355 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5356 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5357 tmp |= SBI_SSCCTL_PATHALT;
5358 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5359 udelay(32);
5360 }
5361 tmp |= SBI_SSCCTL_DISABLE;
5362 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5363 }
5364
5365 mutex_unlock(&dev_priv->dpio_lock);
5366}
5367
bf8fa3d3
PZ		 5368static void lpt_init_pch_refclk(struct drm_device *dev)
5369{
5370 struct drm_mode_config *mode_config = &dev->mode_config;
5371 struct intel_encoder *encoder;
5372 bool has_vga = false;
5373
5374 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5375 switch (encoder->type) {
5376 case INTEL_OUTPUT_ANALOG:
5377 has_vga = true;
5378 break;
5379 }
5380 }
5381
47701c3b
PZ		 5382 if (has_vga)
5383 lpt_enable_clkout_dp(dev, true, true);
5384 else
5385 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5386}
5387
dde86e2d
PZ		 5388/*
5389 * Initialize reference clocks when the driver loads
5390 */
5391void intel_init_pch_refclk(struct drm_device *dev)
5392{
5393 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5394 ironlake_init_pch_refclk(dev);
5395 else if (HAS_PCH_LPT(dev))
5396 lpt_init_pch_refclk(dev);
5397}
5398
d9d444cb
JB		 5399static int ironlake_get_refclk(struct drm_crtc *crtc)
5400{
5401 struct drm_device *dev = crtc->dev;
5402 struct drm_i915_private *dev_priv = dev->dev_private;
5403 struct intel_encoder *encoder;
d9d444cb
JB		 5404 int num_connectors = 0;
5405 bool is_lvds = false;
5406
6c2b7c12 5407 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5408 switch (encoder->type) {
5409 case INTEL_OUTPUT_LVDS:
5410 is_lvds = true;
5411 break;
d9d444cb
JB		 5412 }
5413 num_connectors++;
5414 }
5415
5416 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5417 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5418 dev_priv->vbt.lvds_ssc_freq);
5419 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5420 }
5421
5422 return 120000;
5423}
5424
6ff93609 5425static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5426{
c8203565 5427 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5429 int pipe = intel_crtc->pipe;
c8203565
PZ		 5430 uint32_t val;
5431
78114071 5432 val = 0;
c8203565 5433
965e0c48 5434 switch (intel_crtc->config.pipe_bpp) {
c8203565 5435 case 18:
dfd07d72 5436 val |= PIPECONF_6BPC;
c8203565
PZ		 5437 break;
5438 case 24:
dfd07d72 5439 val |= PIPECONF_8BPC;
c8203565
PZ		 5440 break;
5441 case 30:
dfd07d72 5442 val |= PIPECONF_10BPC;
c8203565
PZ		 5443 break;
5444 case 36:
dfd07d72 5445 val |= PIPECONF_12BPC;
c8203565
PZ		 5446 break;
5447 default:
cc769b62
PZ		 5448 /* Case prevented by intel_choose_pipe_bpp_dither. */
5449 BUG();
c8203565
PZ		 5450 }
5451
d8b32247 5452 if (intel_crtc->config.dither)
c8203565
PZ		 5453 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5454
6ff93609 5455 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5456 val |= PIPECONF_INTERLACED_ILK;
5457 else
5458 val |= PIPECONF_PROGRESSIVE;
5459
50f3b016 5460 if (intel_crtc->config.limited_color_range)
3685a8f3 5461 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5462
c8203565
PZ		 5463 I915_WRITE(PIPECONF(pipe), val);
5464 POSTING_READ(PIPECONF(pipe));
5465}
5466
86d3efce
VS		 5467/*
5468 * Set up the pipe CSC unit.
5469 *
5470 * Currently only full range RGB to limited range RGB conversion
5471 * is supported, but eventually this should handle various
5472 * RGB<->YCbCr scenarios as well.
5473 */
50f3b016 5474static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5475{
5476 struct drm_device *dev = crtc->dev;
5477 struct drm_i915_private *dev_priv = dev->dev_private;
5478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5479 int pipe = intel_crtc->pipe;
5480 uint16_t coeff = 0x7800; /* 1.0 */
5481
5482 /*
5483 * TODO: Check what kind of values actually come out of the pipe
5484 * with these coeff/postoff values and adjust to get the best
5485 * accuracy. Perhaps we even need to take the bpc value into
5486 * consideration.
5487 */
5488
50f3b016 5489 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5490 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5491
5492 /*
5493 * GY/GU and RY/RU should be the other way around according
5494 * to BSpec, but reality doesn't agree. Just set them up in
5495 * a way that results in the correct picture.
5496 */
5497 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5498 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5499
5500 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5501 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5502
5503 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5504 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5505
5506 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5507 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5508 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5509
5510 if (INTEL_INFO(dev)->gen > 6) {
5511 uint16_t postoff = 0;
5512
50f3b016 5513 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5514 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5515
5516 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5517 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5518 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5519
5520 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5521 } else {
5522 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5523
50f3b016 5524 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5525 mode |= CSC_BLACK_SCREEN_OFFSET;
5526
5527 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5528 }
5529}
5530
6ff93609 5531static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5532{
5533 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5535 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5536 uint32_t val;
5537
3eff4faa 5538 val = 0;
ee2b0b38 5539
d8b32247 5540 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5541 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5542
6ff93609 5543 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5544 val |= PIPECONF_INTERLACED_ILK;
5545 else
5546 val |= PIPECONF_PROGRESSIVE;
5547
702e7a56
PZ		 5548 I915_WRITE(PIPECONF(cpu_transcoder), val);
5549 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5550
5551 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5552 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5553}
5554
6591c6e4 5555static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5556 intel_clock_t *clock,
5557 bool *has_reduced_clock,
5558 intel_clock_t *reduced_clock)
5559{
5560 struct drm_device *dev = crtc->dev;
5561 struct drm_i915_private *dev_priv = dev->dev_private;
5562 struct intel_encoder *intel_encoder;
5563 int refclk;
d4906093 5564 const intel_limit_t *limit;
a16af721 5565 bool ret, is_lvds = false;
79e53945 5566
6591c6e4
PZ		 5567 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5568 switch (intel_encoder->type) {
79e53945
JB		 5569 case INTEL_OUTPUT_LVDS:
5570 is_lvds = true;
5571 break;
79e53945
JB		 5572 }
5573 }
5574
d9d444cb 5575 refclk = ironlake_get_refclk(crtc);
79e53945 5576
d4906093
ML		 5577 /*
5578 * Returns a set of divisors for the desired target clock with the given
5579 * refclk, or FALSE. The returned values represent the clock equation:
5580 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5581 */
1b894b59 5582 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5583 ret = dev_priv->display.find_dpll(limit, crtc,
5584 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5585 refclk, NULL, clock);
6591c6e4
PZ		 5586 if (!ret)
5587 return false;
cda4b7d3 5588
ddc9003c 5589 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5590 /*
5591 * Ensure we match the reduced clock's P to the target clock.
5592 * If the clocks don't match, we can't switch the display clock
5593 * by using the FP0/FP1. In such case we will disable the LVDS
5594 * downclock feature.
5595 */
ee9300bb
DV		 5596 *has_reduced_clock =
5597 dev_priv->display.find_dpll(limit, crtc,
5598 dev_priv->lvds_downclock,
5599 refclk, clock,
5600 reduced_clock);
652c393a 5601 }
61e9653f 5602
6591c6e4
PZ		 5603 return true;
5604}
5605
01a415fd
DV		 5606static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5607{
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609 uint32_t temp;
5610
5611 temp = I915_READ(SOUTH_CHICKEN1);
5612 if (temp & FDI_BC_BIFURCATION_SELECT)
5613 return;
5614
5615 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5616 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5617
5618 temp |= FDI_BC_BIFURCATION_SELECT;
5619 DRM_DEBUG_KMS("enabling fdi C rx\n");
5620 I915_WRITE(SOUTH_CHICKEN1, temp);
5621 POSTING_READ(SOUTH_CHICKEN1);
5622}
5623
ebfd86fd 5624static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5625{
5626 struct drm_device *dev = intel_crtc->base.dev;
5627 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5628
5629 switch (intel_crtc->pipe) {
5630 case PIPE_A:
ebfd86fd 5631 break;
01a415fd 5632 case PIPE_B:
ebfd86fd 5633 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5634 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5635 else
5636 cpt_enable_fdi_bc_bifurcation(dev);
5637
ebfd86fd 5638 break;
01a415fd 5639 case PIPE_C:
01a415fd
DV		 5640 cpt_enable_fdi_bc_bifurcation(dev);
5641
ebfd86fd 5642 break;
01a415fd
DV		 5643 default:
5644 BUG();
5645 }
5646}
5647
d4b1931c
PZ		 5648int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5649{
5650 /*
5651 * Account for spread spectrum to avoid
5652 * oversubscribing the link. Max center spread
5653 * is 2.5%; use 5% for safety's sake.
5654 */
5655 u32 bps = target_clock * bpp * 21 / 20;
5656 return bps / (link_bw * 8) + 1;
5657}
5658
7429e9d4 5659static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5660{
7429e9d4 5661 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5662}
5663
de13a2e3 5664static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5665 u32 *fp,
9a7c7890 5666 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5667{
de13a2e3 5668 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5669 struct drm_device *dev = crtc->dev;
5670 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5671 struct intel_encoder *intel_encoder;
5672 uint32_t dpll;
6cc5f341 5673 int factor, num_connectors = 0;
09ede541 5674 bool is_lvds = false, is_sdvo = false;
79e53945 5675
de13a2e3
PZ		 5676 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5677 switch (intel_encoder->type) {
79e53945
JB		 5678 case INTEL_OUTPUT_LVDS:
5679 is_lvds = true;
5680 break;
5681 case INTEL_OUTPUT_SDVO:
7d57382e 5682 case INTEL_OUTPUT_HDMI:
79e53945 5683 is_sdvo = true;
79e53945 5684 break;
79e53945 5685 }
43565a06 5686
c751ce4f 5687 num_connectors++;
79e53945 5688 }
79e53945 5689
c1858123 5690 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5691 factor = 21;
5692 if (is_lvds) {
5693 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5694 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5695 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5696 factor = 25;
09ede541 5697 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5698 factor = 20;
c1858123 5699
7429e9d4 5700 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5701 *fp |= FP_CB_TUNE;
2c07245f 5702
9a7c7890
DV		 5703 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5704 *fp2 |= FP_CB_TUNE;
5705
5eddb70b 5706 dpll = 0;
2c07245f 5707
a07d6787
EA		 5708 if (is_lvds)
5709 dpll |= DPLLB_MODE_LVDS;
5710 else
5711 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5712
ef1b460d
DV		 5713 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5714 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5715
5716 if (is_sdvo)
4a33e48d 5717 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5718 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5719 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5720
a07d6787 5721 /* compute bitmask from p1 value */
7429e9d4 5722 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5723 /* also FPA1 */
7429e9d4 5724 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5725
7429e9d4 5726 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5727 case 5:
5728 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5729 break;
5730 case 7:
5731 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5732 break;
5733 case 10:
5734 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5735 break;
5736 case 14:
5737 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5738 break;
79e53945
JB		 5739 }
5740
b4c09f3b 5741 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5742 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5743 else
5744 dpll |= PLL_REF_INPUT_DREFCLK;
5745
959e16d6 5746 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5747}
5748
5749static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5750 int x, int y,
5751 struct drm_framebuffer *fb)
5752{
5753 struct drm_device *dev = crtc->dev;
5754 struct drm_i915_private *dev_priv = dev->dev_private;
5755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5756 int pipe = intel_crtc->pipe;
5757 int plane = intel_crtc->plane;
5758 int num_connectors = 0;
5759 intel_clock_t clock, reduced_clock;
cbbab5bd 5760 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5761 bool ok, has_reduced_clock = false;
8b47047b 5762 bool is_lvds = false;
de13a2e3 5763 struct intel_encoder *encoder;
e2b78267 5764 struct intel_shared_dpll *pll;
de13a2e3 5765 int ret;
de13a2e3
PZ		 5766
5767 for_each_encoder_on_crtc(dev, crtc, encoder) {
5768 switch (encoder->type) {
5769 case INTEL_OUTPUT_LVDS:
5770 is_lvds = true;
5771 break;
de13a2e3
PZ		 5772 }
5773
5774 num_connectors++;
a07d6787 5775 }
79e53945 5776
5dc5298b
PZ		 5777 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5778 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5779
ff9a6750 5780 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5781 &has_reduced_clock, &reduced_clock);
ee9300bb 5782 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5783 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5784 return -EINVAL;
79e53945 5785 }
f47709a9
DV		 5786 /* Compat-code for transition, will disappear. */
5787 if (!intel_crtc->config.clock_set) {
5788 intel_crtc->config.dpll.n = clock.n;
5789 intel_crtc->config.dpll.m1 = clock.m1;
5790 intel_crtc->config.dpll.m2 = clock.m2;
5791 intel_crtc->config.dpll.p1 = clock.p1;
5792 intel_crtc->config.dpll.p2 = clock.p2;
5793 }
79e53945 5794
de13a2e3
PZ		 5795 /* Ensure that the cursor is valid for the new mode before changing... */
5796 intel_crtc_update_cursor(crtc, true);
5797
5dc5298b 5798 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5799 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5800 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5801 if (has_reduced_clock)
7429e9d4 5802 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5803
7429e9d4 5804 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5805 &fp, &reduced_clock,
5806 has_reduced_clock ? &fp2 : NULL);
5807
959e16d6 5808 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5809 intel_crtc->config.dpll_hw_state.fp0 = fp;
5810 if (has_reduced_clock)
5811 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5812 else
5813 intel_crtc->config.dpll_hw_state.fp1 = fp;
5814
b89a1d39 5815 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5816 if (pll == NULL) {
84f44ce7
VS		 5817 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5818 pipe_name(pipe));
4b645f14
JB		 5819 return -EINVAL;
5820 }
ee7b9f93 5821 } else
e72f9fbf 5822 intel_put_shared_dpll(intel_crtc);
79e53945 5823
03afc4a2
DV		 5824 if (intel_crtc->config.has_dp_encoder)
5825 intel_dp_set_m_n(intel_crtc);
79e53945 5826
bcd644e0
DV		 5827 if (is_lvds && has_reduced_clock && i915_powersave)
5828 intel_crtc->lowfreq_avail = true;
5829 else
5830 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5831
5832 if (intel_crtc->config.has_pch_encoder) {
5833 pll = intel_crtc_to_shared_dpll(intel_crtc);
5834
652c393a
JB		 5835 }
5836
8a654f3b 5837 intel_set_pipe_timings(intel_crtc);
5eddb70b 5838
ca3a0ff8 5839 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5840 intel_cpu_transcoder_set_m_n(intel_crtc,
5841 &intel_crtc->config.fdi_m_n);
5842 }
2c07245f 5843
ebfd86fd
DV		 5844 if (IS_IVYBRIDGE(dev))
5845 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5846
6ff93609 5847 ironlake_set_pipeconf(crtc);
79e53945 5848
a1f9e77e
PZ		 5849 /* Set up the display plane register */
5850 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5851 POSTING_READ(DSPCNTR(plane));
79e53945 5852
94352cf9 5853 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5854
5855 intel_update_watermarks(dev);
5856
1857e1da 5857 return ret;
79e53945
JB		 5858}
5859
72419203
DV		 5860static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5861 struct intel_crtc_config *pipe_config)
5862{
5863 struct drm_device *dev = crtc->base.dev;
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 enum transcoder transcoder = pipe_config->cpu_transcoder;
5866
5867 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5868 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5869 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5870 & ~TU_SIZE_MASK;
5871 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5872 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5873 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5874}
5875
2fa2fe9a
DV		 5876static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5877 struct intel_crtc_config *pipe_config)
5878{
5879 struct drm_device *dev = crtc->base.dev;
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 uint32_t tmp;
5882
5883 tmp = I915_READ(PF_CTL(crtc->pipe));
5884
5885 if (tmp & PF_ENABLE) {
5886 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5887 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5888
5889 /* We currently do not free assignements of panel fitters on
5890 * ivb/hsw (since we don't use the higher upscaling modes which
5891 * differentiates them) so just WARN about this case for now. */
5892 if (IS_GEN7(dev)) {
5893 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5894 PF_PIPE_SEL_IVB(crtc->pipe));
5895 }
2fa2fe9a 5896 }
79e53945
JB		 5897}
5898
0e8ffe1b
DV		 5899static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5900 struct intel_crtc_config *pipe_config)
5901{
5902 struct drm_device *dev = crtc->base.dev;
5903 struct drm_i915_private *dev_priv = dev->dev_private;
5904 uint32_t tmp;
5905
e143a21c 5906 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5907 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5908
0e8ffe1b
DV		 5909 tmp = I915_READ(PIPECONF(crtc->pipe));
5910 if (!(tmp & PIPECONF_ENABLE))
5911 return false;
5912
ab9412ba 5913 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5914 struct intel_shared_dpll *pll;
5915
88adfff1
DV		 5916 pipe_config->has_pch_encoder = true;
5917
627eb5a3
DV		 5918 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5919 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5920 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5921
5922 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5923
c0d43d62 5924 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5925 pipe_config->shared_dpll =
5926 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5927 } else {
5928 tmp = I915_READ(PCH_DPLL_SEL);
5929 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5930 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5931 else
5932 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5933 }
66e985c0
DV		 5934
5935 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5936
5937 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5938 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5939
5940 tmp = pipe_config->dpll_hw_state.dpll;
5941 pipe_config->pixel_multiplier =
5942 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5943 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5944 } else {
5945 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5946 }
5947
1bd1bd80
DV		 5948 intel_get_pipe_timings(crtc, pipe_config);
5949
2fa2fe9a
DV		 5950 ironlake_get_pfit_config(crtc, pipe_config);
5951
0e8ffe1b
DV		 5952 return true;
5953}
5954
be256dc7
PZ		 5955static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5956{
5957 struct drm_device *dev = dev_priv->dev;
5958 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5959 struct intel_crtc *crtc;
5960 unsigned long irqflags;
bd633a7c 5961 uint32_t val;
be256dc7
PZ		 5962
5963 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5964 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5965 pipe_name(crtc->pipe));
5966
5967 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5968 WARN(plls->spll_refcount, "SPLL enabled\n");
5969 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5970 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5971 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5972 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5973 "CPU PWM1 enabled\n");
5974 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5975 "CPU PWM2 enabled\n");
5976 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5977 "PCH PWM1 enabled\n");
5978 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5979 "Utility pin enabled\n");
5980 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5981
5982 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5983 val = I915_READ(DEIMR);
5984 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5985 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5986 val = I915_READ(SDEIMR);
bd633a7c 5987 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 5988 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5989 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5990}
5991
5992/*
5993 * This function implements pieces of two sequences from BSpec:
5994 * - Sequence for display software to disable LCPLL
5995 * - Sequence for display software to allow package C8+
5996 * The steps implemented here are just the steps that actually touch the LCPLL
5997 * register. Callers should take care of disabling all the display engine
5998 * functions, doing the mode unset, fixing interrupts, etc.
5999 */
6000void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6001 bool switch_to_fclk, bool allow_power_down)
6002{
6003 uint32_t val;
6004
6005 assert_can_disable_lcpll(dev_priv);
6006
6007 val = I915_READ(LCPLL_CTL);
6008
6009 if (switch_to_fclk) {
6010 val |= LCPLL_CD_SOURCE_FCLK;
6011 I915_WRITE(LCPLL_CTL, val);
6012
6013 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6014 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6015 DRM_ERROR("Switching to FCLK failed\n");
6016
6017 val = I915_READ(LCPLL_CTL);
6018 }
6019
6020 val |= LCPLL_PLL_DISABLE;
6021 I915_WRITE(LCPLL_CTL, val);
6022 POSTING_READ(LCPLL_CTL);
6023
6024 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6025 DRM_ERROR("LCPLL still locked\n");
6026
6027 val = I915_READ(D_COMP);
6028 val |= D_COMP_COMP_DISABLE;
6029 I915_WRITE(D_COMP, val);
6030 POSTING_READ(D_COMP);
6031 ndelay(100);
6032
6033 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6034 DRM_ERROR("D_COMP RCOMP still in progress\n");
6035
6036 if (allow_power_down) {
6037 val = I915_READ(LCPLL_CTL);
6038 val |= LCPLL_POWER_DOWN_ALLOW;
6039 I915_WRITE(LCPLL_CTL, val);
6040 POSTING_READ(LCPLL_CTL);
6041 }
6042}
6043
6044/*
6045 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6046 * source.
6047 */
6048void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6049{
6050 uint32_t val;
6051
6052 val = I915_READ(LCPLL_CTL);
6053
6054 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6055 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6056 return;
6057
215733fa
PZ		 6058 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6059 * we'll hang the machine! */
6060 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6061
be256dc7
PZ		 6062 if (val & LCPLL_POWER_DOWN_ALLOW) {
6063 val &= ~LCPLL_POWER_DOWN_ALLOW;
6064 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6065 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6066 }
6067
6068 val = I915_READ(D_COMP);
6069 val |= D_COMP_COMP_FORCE;
6070 val &= ~D_COMP_COMP_DISABLE;
6071 I915_WRITE(D_COMP, val);
35d8f2eb 6072 POSTING_READ(D_COMP);
be256dc7
PZ		 6073
6074 val = I915_READ(LCPLL_CTL);
6075 val &= ~LCPLL_PLL_DISABLE;
6076 I915_WRITE(LCPLL_CTL, val);
6077
6078 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6079 DRM_ERROR("LCPLL not locked yet\n");
6080
6081 if (val & LCPLL_CD_SOURCE_FCLK) {
6082 val = I915_READ(LCPLL_CTL);
6083 val &= ~LCPLL_CD_SOURCE_FCLK;
6084 I915_WRITE(LCPLL_CTL, val);
6085
6086 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6087 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6088 DRM_ERROR("Switching back to LCPLL failed\n");
6089 }
215733fa
PZ		 6090
6091 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6092}
6093
c67a470b
PZ		 6094void hsw_enable_pc8_work(struct work_struct *__work)
6095{
6096 struct drm_i915_private *dev_priv =
6097 container_of(to_delayed_work(__work), struct drm_i915_private,
6098 pc8.enable_work);
6099 struct drm_device *dev = dev_priv->dev;
6100 uint32_t val;
6101
6102 if (dev_priv->pc8.enabled)
6103 return;
6104
6105 DRM_DEBUG_KMS("Enabling package C8+\n");
6106
6107 dev_priv->pc8.enabled = true;
6108
6109 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6110 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6111 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6112 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6113 }
6114
6115 lpt_disable_clkout_dp(dev);
6116 hsw_pc8_disable_interrupts(dev);
6117 hsw_disable_lcpll(dev_priv, true, true);
6118}
6119
6120static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6121{
6122 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6123 WARN(dev_priv->pc8.disable_count < 1,
6124 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6125
6126 dev_priv->pc8.disable_count--;
6127 if (dev_priv->pc8.disable_count != 0)
6128 return;
6129
6130 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6131 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6132}
6133
6134static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6135{
6136 struct drm_device *dev = dev_priv->dev;
6137 uint32_t val;
6138
6139 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6140 WARN(dev_priv->pc8.disable_count < 0,
6141 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6142
6143 dev_priv->pc8.disable_count++;
6144 if (dev_priv->pc8.disable_count != 1)
6145 return;
6146
6147 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6148 if (!dev_priv->pc8.enabled)
6149 return;
6150
6151 DRM_DEBUG_KMS("Disabling package C8+\n");
6152
6153 hsw_restore_lcpll(dev_priv);
6154 hsw_pc8_restore_interrupts(dev);
6155 lpt_init_pch_refclk(dev);
6156
6157 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6158 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6159 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6160 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6161 }
6162
6163 intel_prepare_ddi(dev);
6164 i915_gem_init_swizzling(dev);
6165 mutex_lock(&dev_priv->rps.hw_lock);
6166 gen6_update_ring_freq(dev);
6167 mutex_unlock(&dev_priv->rps.hw_lock);
6168 dev_priv->pc8.enabled = false;
6169}
6170
6171void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6172{
6173 mutex_lock(&dev_priv->pc8.lock);
6174 __hsw_enable_package_c8(dev_priv);
6175 mutex_unlock(&dev_priv->pc8.lock);
6176}
6177
6178void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6179{
6180 mutex_lock(&dev_priv->pc8.lock);
6181 __hsw_disable_package_c8(dev_priv);
6182 mutex_unlock(&dev_priv->pc8.lock);
6183}
6184
6185static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6186{
6187 struct drm_device *dev = dev_priv->dev;
6188 struct intel_crtc *crtc;
6189 uint32_t val;
6190
6191 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6192 if (crtc->base.enabled)
6193 return false;
6194
6195 /* This case is still possible since we have the i915.disable_power_well
6196 * parameter and also the KVMr or something else might be requesting the
6197 * power well. */
6198 val = I915_READ(HSW_PWR_WELL_DRIVER);
6199 if (val != 0) {
6200 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6201 return false;
6202 }
6203
6204 return true;
6205}
6206
6207/* Since we're called from modeset_global_resources there's no way to
6208 * symmetrically increase and decrease the refcount, so we use
6209 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6210 * or not.
6211 */
6212static void hsw_update_package_c8(struct drm_device *dev)
6213{
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215 bool allow;
6216
6217 if (!i915_enable_pc8)
6218 return;
6219
6220 mutex_lock(&dev_priv->pc8.lock);
6221
6222 allow = hsw_can_enable_package_c8(dev_priv);
6223
6224 if (allow == dev_priv->pc8.requirements_met)
6225 goto done;
6226
6227 dev_priv->pc8.requirements_met = allow;
6228
6229 if (allow)
6230 __hsw_enable_package_c8(dev_priv);
6231 else
6232 __hsw_disable_package_c8(dev_priv);
6233
6234done:
6235 mutex_unlock(&dev_priv->pc8.lock);
6236}
6237
6238static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6239{
6240 if (!dev_priv->pc8.gpu_idle) {
6241 dev_priv->pc8.gpu_idle = true;
6242 hsw_enable_package_c8(dev_priv);
6243 }
6244}
6245
6246static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6247{
6248 if (dev_priv->pc8.gpu_idle) {
6249 dev_priv->pc8.gpu_idle = false;
6250 hsw_disable_package_c8(dev_priv);
6251 }
be256dc7
PZ		 6252}
6253
d6dd9eb1
DV		 6254static void haswell_modeset_global_resources(struct drm_device *dev)
6255{
d6dd9eb1
DV		 6256 bool enable = false;
6257 struct intel_crtc *crtc;
d6dd9eb1
DV		 6258
6259 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6260 if (!crtc->base.enabled)
6261 continue;
d6dd9eb1 6262
e7a639c4
DV		 6263 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6264 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6265 enable = true;
6266 }
6267
d6dd9eb1 6268 intel_set_power_well(dev, enable);
c67a470b
PZ		 6269
6270 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6271}
6272
09b4ddf9 6273static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6274 int x, int y,
6275 struct drm_framebuffer *fb)
6276{
6277 struct drm_device *dev = crtc->dev;
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6280 int plane = intel_crtc->plane;
09b4ddf9 6281 int ret;
09b4ddf9 6282
ff9a6750 6283 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6284 return -EINVAL;
6285
09b4ddf9
PZ		 6286 /* Ensure that the cursor is valid for the new mode before changing... */
6287 intel_crtc_update_cursor(crtc, true);
6288
03afc4a2
DV		 6289 if (intel_crtc->config.has_dp_encoder)
6290 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6291
6292 intel_crtc->lowfreq_avail = false;
09b4ddf9 6293
8a654f3b 6294 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6295
ca3a0ff8 6296 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6297 intel_cpu_transcoder_set_m_n(intel_crtc,
6298 &intel_crtc->config.fdi_m_n);
6299 }
09b4ddf9 6300
6ff93609 6301 haswell_set_pipeconf(crtc);
09b4ddf9 6302
50f3b016 6303 intel_set_pipe_csc(crtc);
86d3efce 6304
09b4ddf9 6305 /* Set up the display plane register */
86d3efce 6306 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6307 POSTING_READ(DSPCNTR(plane));
6308
6309 ret = intel_pipe_set_base(crtc, x, y, fb);
6310
6311 intel_update_watermarks(dev);
6312
1f803ee5 6313 return ret;
79e53945
JB		 6314}
6315
0e8ffe1b
DV		 6316static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6317 struct intel_crtc_config *pipe_config)
6318{
6319 struct drm_device *dev = crtc->base.dev;
6320 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6321 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6322 uint32_t tmp;
6323
e143a21c 6324 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6325 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6326
eccb140b
DV		 6327 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6328 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6329 enum pipe trans_edp_pipe;
6330 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6331 default:
6332 WARN(1, "unknown pipe linked to edp transcoder\n");
6333 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6334 case TRANS_DDI_EDP_INPUT_A_ON:
6335 trans_edp_pipe = PIPE_A;
6336 break;
6337 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6338 trans_edp_pipe = PIPE_B;
6339 break;
6340 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6341 trans_edp_pipe = PIPE_C;
6342 break;
6343 }
6344
6345 if (trans_edp_pipe == crtc->pipe)
6346 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6347 }
6348
b97186f0 6349 if (!intel_display_power_enabled(dev,
eccb140b 6350 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6351 return false;
6352
eccb140b 6353 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6354 if (!(tmp & PIPECONF_ENABLE))
6355 return false;
6356
88adfff1 6357 /*
f196e6be 6358 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6359 * DDI E. So just check whether this pipe is wired to DDI E and whether
6360 * the PCH transcoder is on.
6361 */
eccb140b 6362 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6363 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6364 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6365 pipe_config->has_pch_encoder = true;
6366
627eb5a3
DV		 6367 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6368 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6369 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6370
6371 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6372 }
6373
1bd1bd80
DV		 6374 intel_get_pipe_timings(crtc, pipe_config);
6375
2fa2fe9a
DV		 6376 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6377 if (intel_display_power_enabled(dev, pfit_domain))
6378 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6379
42db64ef
PZ		 6380 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6381 (I915_READ(IPS_CTL) & IPS_ENABLE);
6382
6c49f241
DV		 6383 pipe_config->pixel_multiplier = 1;
6384
0e8ffe1b
DV		 6385 return true;
6386}
6387
f564048e 6388static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6389 int x, int y,
94352cf9 6390 struct drm_framebuffer *fb)
f564048e
EA		 6391{
6392 struct drm_device *dev = crtc->dev;
6393 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6394 struct intel_encoder *encoder;
0b701d27 6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6396 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6397 int pipe = intel_crtc->pipe;
f564048e
EA		 6398 int ret;
6399
0b701d27 6400 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6401
b8cecdf5
DV		 6402 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6403
79e53945 6404 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6405
9256aa19
DV		 6406 if (ret != 0)
6407 return ret;
6408
6409 for_each_encoder_on_crtc(dev, crtc, encoder) {
6410 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6411 encoder->base.base.id,
6412 drm_get_encoder_name(&encoder->base),
6413 mode->base.id, mode->name);
36f2d1f1 6414 encoder->mode_set(encoder);
9256aa19
DV		 6415 }
6416
6417 return 0;
79e53945
JB		 6418}
6419
3a9627f4
WF		 6420static bool intel_eld_uptodate(struct drm_connector *connector,
6421 int reg_eldv, uint32_t bits_eldv,
6422 int reg_elda, uint32_t bits_elda,
6423 int reg_edid)
6424{
6425 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6426 uint8_t *eld = connector->eld;
6427 uint32_t i;
6428
6429 i = I915_READ(reg_eldv);
6430 i &= bits_eldv;
6431
6432 if (!eld[0])
6433 return !i;
6434
6435 if (!i)
6436 return false;
6437
6438 i = I915_READ(reg_elda);
6439 i &= ~bits_elda;
6440 I915_WRITE(reg_elda, i);
6441
6442 for (i = 0; i < eld[2]; i++)
6443 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6444 return false;
6445
6446 return true;
6447}
6448
e0dac65e
WF		 6449static void g4x_write_eld(struct drm_connector *connector,
6450 struct drm_crtc *crtc)
6451{
6452 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6453 uint8_t *eld = connector->eld;
6454 uint32_t eldv;
6455 uint32_t len;
6456 uint32_t i;
6457
6458 i = I915_READ(G4X_AUD_VID_DID);
6459
6460 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6461 eldv = G4X_ELDV_DEVCL_DEVBLC;
6462 else
6463 eldv = G4X_ELDV_DEVCTG;
6464
3a9627f4
WF		 6465 if (intel_eld_uptodate(connector,
6466 G4X_AUD_CNTL_ST, eldv,
6467 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6468 G4X_HDMIW_HDMIEDID))
6469 return;
6470
e0dac65e
WF		 6471 i = I915_READ(G4X_AUD_CNTL_ST);
6472 i &= ~(eldv | G4X_ELD_ADDR);
6473 len = (i >> 9) & 0x1f; /* ELD buffer size */
6474 I915_WRITE(G4X_AUD_CNTL_ST, i);
6475
6476 if (!eld[0])
6477 return;
6478
6479 len = min_t(uint8_t, eld[2], len);
6480 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6481 for (i = 0; i < len; i++)
6482 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6483
6484 i = I915_READ(G4X_AUD_CNTL_ST);
6485 i |= eldv;
6486 I915_WRITE(G4X_AUD_CNTL_ST, i);
6487}
6488
83358c85
WX		 6489static void haswell_write_eld(struct drm_connector *connector,
6490 struct drm_crtc *crtc)
6491{
6492 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6493 uint8_t *eld = connector->eld;
6494 struct drm_device *dev = crtc->dev;
7b9f35a6 6495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6496 uint32_t eldv;
6497 uint32_t i;
6498 int len;
6499 int pipe = to_intel_crtc(crtc)->pipe;
6500 int tmp;
6501
6502 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6503 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6504 int aud_config = HSW_AUD_CFG(pipe);
6505 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6506
6507
6508 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6509
6510 /* Audio output enable */
6511 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6512 tmp = I915_READ(aud_cntrl_st2);
6513 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6514 I915_WRITE(aud_cntrl_st2, tmp);
6515
6516 /* Wait for 1 vertical blank */
6517 intel_wait_for_vblank(dev, pipe);
6518
6519 /* Set ELD valid state */
6520 tmp = I915_READ(aud_cntrl_st2);
6521 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6522 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6523 I915_WRITE(aud_cntrl_st2, tmp);
6524 tmp = I915_READ(aud_cntrl_st2);
6525 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6526
6527 /* Enable HDMI mode */
6528 tmp = I915_READ(aud_config);
6529 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6530 /* clear N_programing_enable and N_value_index */
6531 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6532 I915_WRITE(aud_config, tmp);
6533
6534 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6535
6536 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6537 intel_crtc->eld_vld = true;
83358c85
WX		 6538
6539 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6540 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6541 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6542 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6543 } else
6544 I915_WRITE(aud_config, 0);
6545
6546 if (intel_eld_uptodate(connector,
6547 aud_cntrl_st2, eldv,
6548 aud_cntl_st, IBX_ELD_ADDRESS,
6549 hdmiw_hdmiedid))
6550 return;
6551
6552 i = I915_READ(aud_cntrl_st2);
6553 i &= ~eldv;
6554 I915_WRITE(aud_cntrl_st2, i);
6555
6556 if (!eld[0])
6557 return;
6558
6559 i = I915_READ(aud_cntl_st);
6560 i &= ~IBX_ELD_ADDRESS;
6561 I915_WRITE(aud_cntl_st, i);
6562 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6563 DRM_DEBUG_DRIVER("port num:%d\n", i);
6564
6565 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6566 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6567 for (i = 0; i < len; i++)
6568 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6569
6570 i = I915_READ(aud_cntrl_st2);
6571 i |= eldv;
6572 I915_WRITE(aud_cntrl_st2, i);
6573
6574}
6575
e0dac65e
WF		 6576static void ironlake_write_eld(struct drm_connector *connector,
6577 struct drm_crtc *crtc)
6578{
6579 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6580 uint8_t *eld = connector->eld;
6581 uint32_t eldv;
6582 uint32_t i;
6583 int len;
6584 int hdmiw_hdmiedid;
b6daa025 6585 int aud_config;
e0dac65e
WF		 6586 int aud_cntl_st;
6587 int aud_cntrl_st2;
9b138a83 6588 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6589
b3f33cbf 6590 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6591 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6592 aud_config = IBX_AUD_CFG(pipe);
6593 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6594 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6595 } else {
9b138a83
WX		 6596 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6597 aud_config = CPT_AUD_CFG(pipe);
6598 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6599 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6600 }
6601
9b138a83 6602 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6603
6604 i = I915_READ(aud_cntl_st);
9b138a83 6605 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6606 if (!i) {
6607 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6608 /* operate blindly on all ports */
1202b4c6
WF		 6609 eldv = IBX_ELD_VALIDB;
6610 eldv |= IBX_ELD_VALIDB << 4;
6611 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6612 } else {
2582a850 6613 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6614 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6615 }
6616
3a9627f4
WF		 6617 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6618 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6619 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6620 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6621 } else
6622 I915_WRITE(aud_config, 0);
e0dac65e 6623
3a9627f4
WF		 6624 if (intel_eld_uptodate(connector,
6625 aud_cntrl_st2, eldv,
6626 aud_cntl_st, IBX_ELD_ADDRESS,
6627 hdmiw_hdmiedid))
6628 return;
6629
e0dac65e
WF		 6630 i = I915_READ(aud_cntrl_st2);
6631 i &= ~eldv;
6632 I915_WRITE(aud_cntrl_st2, i);
6633
6634 if (!eld[0])
6635 return;
6636
e0dac65e 6637 i = I915_READ(aud_cntl_st);
1202b4c6 6638 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6639 I915_WRITE(aud_cntl_st, i);
6640
6641 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6642 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6643 for (i = 0; i < len; i++)
6644 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6645
6646 i = I915_READ(aud_cntrl_st2);
6647 i |= eldv;
6648 I915_WRITE(aud_cntrl_st2, i);
6649}
6650
6651void intel_write_eld(struct drm_encoder *encoder,
6652 struct drm_display_mode *mode)
6653{
6654 struct drm_crtc *crtc = encoder->crtc;
6655 struct drm_connector *connector;
6656 struct drm_device *dev = encoder->dev;
6657 struct drm_i915_private *dev_priv = dev->dev_private;
6658
6659 connector = drm_select_eld(encoder, mode);
6660 if (!connector)
6661 return;
6662
6663 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6664 connector->base.id,
6665 drm_get_connector_name(connector),
6666 connector->encoder->base.id,
6667 drm_get_encoder_name(connector->encoder));
6668
6669 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6670
6671 if (dev_priv->display.write_eld)
6672 dev_priv->display.write_eld(connector, crtc);
6673}
6674
79e53945
JB		 6675/** Loads the palette/gamma unit for the CRTC with the prepared values */
6676void intel_crtc_load_lut(struct drm_crtc *crtc)
6677{
6678 struct drm_device *dev = crtc->dev;
6679 struct drm_i915_private *dev_priv = dev->dev_private;
6680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6681 enum pipe pipe = intel_crtc->pipe;
6682 int palreg = PALETTE(pipe);
79e53945 6683 int i;
42db64ef 6684 bool reenable_ips = false;
79e53945
JB		 6685
6686 /* The clocks have to be on to load the palette. */
aed3f09d 6687 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6688 return;
6689
23538ef1
JN		 6690 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6691 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6692 assert_dsi_pll_enabled(dev_priv);
6693 else
6694 assert_pll_enabled(dev_priv, pipe);
6695 }
14420bd0 6696
f2b115e6 6697 /* use legacy palette for Ironlake */
bad720ff 6698 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6699 palreg = LGC_PALETTE(pipe);
6700
6701 /* Workaround : Do not read or write the pipe palette/gamma data while
6702 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6703 */
6704 if (intel_crtc->config.ips_enabled &&
6705 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6706 GAMMA_MODE_MODE_SPLIT)) {
6707 hsw_disable_ips(intel_crtc);
6708 reenable_ips = true;
6709 }
2c07245f 6710
79e53945
JB		 6711 for (i = 0; i < 256; i++) {
6712 I915_WRITE(palreg + 4 * i,
6713 (intel_crtc->lut_r[i] << 16) |
6714 (intel_crtc->lut_g[i] << 8) |
6715 intel_crtc->lut_b[i]);
6716 }
42db64ef
PZ		 6717
6718 if (reenable_ips)
6719 hsw_enable_ips(intel_crtc);
79e53945
JB		 6720}
6721
560b85bb
CW		 6722static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6723{
6724 struct drm_device *dev = crtc->dev;
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6727 bool visible = base != 0;
6728 u32 cntl;
6729
6730 if (intel_crtc->cursor_visible == visible)
6731 return;
6732
9db4a9c7 6733 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6734 if (visible) {
6735 /* On these chipsets we can only modify the base whilst
6736 * the cursor is disabled.
6737 */
9db4a9c7 6738 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6739
6740 cntl &= ~(CURSOR_FORMAT_MASK);
6741 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6742 cntl |= CURSOR_ENABLE |
6743 CURSOR_GAMMA_ENABLE |
6744 CURSOR_FORMAT_ARGB;
6745 } else
6746 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6747 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6748
6749 intel_crtc->cursor_visible = visible;
6750}
6751
6752static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6753{
6754 struct drm_device *dev = crtc->dev;
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6757 int pipe = intel_crtc->pipe;
6758 bool visible = base != 0;
6759
6760 if (intel_crtc->cursor_visible != visible) {
548f245b 6761 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6762 if (base) {
6763 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6764 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6765 cntl |= pipe << 28; /* Connect to correct pipe */
6766 } else {
6767 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6768 cntl |= CURSOR_MODE_DISABLE;
6769 }
9db4a9c7 6770 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6771
6772 intel_crtc->cursor_visible = visible;
6773 }
6774 /* and commit changes on next vblank */
9db4a9c7 6775 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6776}
6777
65a21cd6
JB		 6778static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6779{
6780 struct drm_device *dev = crtc->dev;
6781 struct drm_i915_private *dev_priv = dev->dev_private;
6782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6783 int pipe = intel_crtc->pipe;
6784 bool visible = base != 0;
6785
6786 if (intel_crtc->cursor_visible != visible) {
6787 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6788 if (base) {
6789 cntl &= ~CURSOR_MODE;
6790 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6791 } else {
6792 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6793 cntl |= CURSOR_MODE_DISABLE;
6794 }
1f5d76db 6795 if (IS_HASWELL(dev)) {
86d3efce 6796 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6797 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6798 }
65a21cd6
JB		 6799 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6800
6801 intel_crtc->cursor_visible = visible;
6802 }
6803 /* and commit changes on next vblank */
6804 I915_WRITE(CURBASE_IVB(pipe), base);
6805}
6806
cda4b7d3 6807/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6808static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6809 bool on)
cda4b7d3
CW		 6810{
6811 struct drm_device *dev = crtc->dev;
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814 int pipe = intel_crtc->pipe;
6815 int x = intel_crtc->cursor_x;
6816 int y = intel_crtc->cursor_y;
560b85bb 6817 u32 base, pos;
cda4b7d3
CW		 6818 bool visible;
6819
6820 pos = 0;
6821
6b383a7f 6822 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6823 base = intel_crtc->cursor_addr;
6824 if (x > (int) crtc->fb->width)
6825 base = 0;
6826
6827 if (y > (int) crtc->fb->height)
6828 base = 0;
6829 } else
6830 base = 0;
6831
6832 if (x < 0) {
6833 if (x + intel_crtc->cursor_width < 0)
6834 base = 0;
6835
6836 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6837 x = -x;
6838 }
6839 pos |= x << CURSOR_X_SHIFT;
6840
6841 if (y < 0) {
6842 if (y + intel_crtc->cursor_height < 0)
6843 base = 0;
6844
6845 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6846 y = -y;
6847 }
6848 pos |= y << CURSOR_Y_SHIFT;
6849
6850 visible = base != 0;
560b85bb 6851 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6852 return;
6853
0cd83aa9 6854 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6855 I915_WRITE(CURPOS_IVB(pipe), pos);
6856 ivb_update_cursor(crtc, base);
6857 } else {
6858 I915_WRITE(CURPOS(pipe), pos);
6859 if (IS_845G(dev) || IS_I865G(dev))
6860 i845_update_cursor(crtc, base);
6861 else
6862 i9xx_update_cursor(crtc, base);
6863 }
cda4b7d3
CW		 6864}
6865
79e53945 6866static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6867 struct drm_file *file,
79e53945
JB		 6868 uint32_t handle,
6869 uint32_t width, uint32_t height)
6870{
6871 struct drm_device *dev = crtc->dev;
6872 struct drm_i915_private *dev_priv = dev->dev_private;
6873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6874 struct drm_i915_gem_object *obj;
cda4b7d3 6875 uint32_t addr;
3f8bc370 6876 int ret;
79e53945 6877
79e53945
JB		 6878 /* if we want to turn off the cursor ignore width and height */
6879 if (!handle) {
28c97730 6880 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6881 addr = 0;
05394f39 6882 obj = NULL;
5004417d 6883 mutex_lock(&dev->struct_mutex);
3f8bc370 6884 goto finish;
79e53945
JB		 6885 }
6886
6887 /* Currently we only support 64x64 cursors */
6888 if (width != 64 || height != 64) {
6889 DRM_ERROR("we currently only support 64x64 cursors\n");
6890 return -EINVAL;
6891 }
6892
05394f39 6893 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6894 if (&obj->base == NULL)
79e53945
JB		 6895 return -ENOENT;
6896
05394f39 6897 if (obj->base.size < width * height * 4) {
79e53945 6898 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6899 ret = -ENOMEM;
6900 goto fail;
79e53945
JB		 6901 }
6902
71acb5eb 6903 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6904 mutex_lock(&dev->struct_mutex);
b295d1b6 6905 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6906 unsigned alignment;
6907
d9e86c0e
CW		 6908 if (obj->tiling_mode) {
6909 DRM_ERROR("cursor cannot be tiled\n");
6910 ret = -EINVAL;
6911 goto fail_locked;
6912 }
6913
693db184
CW		 6914 /* Note that the w/a also requires 2 PTE of padding following
6915 * the bo. We currently fill all unused PTE with the shadow
6916 * page and so we should always have valid PTE following the
6917 * cursor preventing the VT-d warning.
6918 */
6919 alignment = 0;
6920 if (need_vtd_wa(dev))
6921 alignment = 64*1024;
6922
6923 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6924 if (ret) {
6925 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6926 goto fail_locked;
e7b526bb
CW		 6927 }
6928
d9e86c0e
CW		 6929 ret = i915_gem_object_put_fence(obj);
6930 if (ret) {
2da3b9b9 6931 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6932 goto fail_unpin;
6933 }
6934
f343c5f6 6935 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6936 } else {
6eeefaf3 6937 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6938 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6939 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6940 align);
71acb5eb
DA		 6941 if (ret) {
6942 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6943 goto fail_locked;
71acb5eb 6944 }
05394f39 6945 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6946 }
6947
a6c45cf0 6948 if (IS_GEN2(dev))
14b60391
JB		 6949 I915_WRITE(CURSIZE, (height << 12) | width);
6950
3f8bc370 6951 finish:
3f8bc370 6952 if (intel_crtc->cursor_bo) {
b295d1b6 6953 if (dev_priv->info->cursor_needs_physical) {
05394f39 6954 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6955 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6956 } else
cc98b413 6957 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 6958 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6959 }
80824003 6960
7f9872e0 6961 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6962
6963 intel_crtc->cursor_addr = addr;
05394f39 6964 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6965 intel_crtc->cursor_width = width;
6966 intel_crtc->cursor_height = height;
6967
40ccc72b 6968 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6969
79e53945 6970 return 0;
e7b526bb 6971fail_unpin:
cc98b413 6972 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 6973fail_locked:
34b8686e 6974 mutex_unlock(&dev->struct_mutex);
bc9025bd 6975fail:
05394f39 6976 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6977 return ret;
79e53945
JB		 6978}
6979
6980static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6981{
79e53945 6982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6983
cda4b7d3
CW		 6984 intel_crtc->cursor_x = x;
6985 intel_crtc->cursor_y = y;
652c393a 6986
40ccc72b 6987 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6988
6989 return 0;
6990}
6991
6992/** Sets the color ramps on behalf of RandR */
6993void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6994 u16 blue, int regno)
6995{
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6997
6998 intel_crtc->lut_r[regno] = red >> 8;
6999 intel_crtc->lut_g[regno] = green >> 8;
7000 intel_crtc->lut_b[regno] = blue >> 8;
7001}
7002
b8c00ac5
DA		 7003void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7004 u16 *blue, int regno)
7005{
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007
7008 *red = intel_crtc->lut_r[regno] << 8;
7009 *green = intel_crtc->lut_g[regno] << 8;
7010 *blue = intel_crtc->lut_b[regno] << 8;
7011}
7012
79e53945 7013static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7014 u16 *blue, uint32_t start, uint32_t size)
79e53945 7015{
7203425a 7016 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7018
7203425a 7019 for (i = start; i < end; i++) {
79e53945
JB		 7020 intel_crtc->lut_r[i] = red[i] >> 8;
7021 intel_crtc->lut_g[i] = green[i] >> 8;
7022 intel_crtc->lut_b[i] = blue[i] >> 8;
7023 }
7024
7025 intel_crtc_load_lut(crtc);
7026}
7027
79e53945
JB		 7028/* VESA 640x480x72Hz mode to set on the pipe */
7029static struct drm_display_mode load_detect_mode = {
7030 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7031 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7032};
7033
d2dff872
CW		 7034static struct drm_framebuffer *
7035intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7036 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7037 struct drm_i915_gem_object *obj)
7038{
7039 struct intel_framebuffer *intel_fb;
7040 int ret;
7041
7042 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7043 if (!intel_fb) {
7044 drm_gem_object_unreference_unlocked(&obj->base);
7045 return ERR_PTR(-ENOMEM);
7046 }
7047
7048 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7049 if (ret) {
7050 drm_gem_object_unreference_unlocked(&obj->base);
7051 kfree(intel_fb);
7052 return ERR_PTR(ret);
7053 }
7054
7055 return &intel_fb->base;
7056}
7057
7058static u32
7059intel_framebuffer_pitch_for_width(int width, int bpp)
7060{
7061 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7062 return ALIGN(pitch, 64);
7063}
7064
7065static u32
7066intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7067{
7068 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7069 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7070}
7071
7072static struct drm_framebuffer *
7073intel_framebuffer_create_for_mode(struct drm_device *dev,
7074 struct drm_display_mode *mode,
7075 int depth, int bpp)
7076{
7077 struct drm_i915_gem_object *obj;
0fed39bd 7078 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7079
7080 obj = i915_gem_alloc_object(dev,
7081 intel_framebuffer_size_for_mode(mode, bpp));
7082 if (obj == NULL)
7083 return ERR_PTR(-ENOMEM);
7084
7085 mode_cmd.width = mode->hdisplay;
7086 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7087 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7088 bpp);
5ca0c34a 7089 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7090
7091 return intel_framebuffer_create(dev, &mode_cmd, obj);
7092}
7093
7094static struct drm_framebuffer *
7095mode_fits_in_fbdev(struct drm_device *dev,
7096 struct drm_display_mode *mode)
7097{
7098 struct drm_i915_private *dev_priv = dev->dev_private;
7099 struct drm_i915_gem_object *obj;
7100 struct drm_framebuffer *fb;
7101
7102 if (dev_priv->fbdev == NULL)
7103 return NULL;
7104
7105 obj = dev_priv->fbdev->ifb.obj;
7106 if (obj == NULL)
7107 return NULL;
7108
7109 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7110 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7111 fb->bits_per_pixel))
d2dff872
CW		 7112 return NULL;
7113
01f2c773 7114 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7115 return NULL;
7116
7117 return fb;
7118}
7119
d2434ab7 7120bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7121 struct drm_display_mode *mode,
8261b191 7122 struct intel_load_detect_pipe *old)
79e53945
JB		 7123{
7124 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7125 struct intel_encoder *intel_encoder =
7126 intel_attached_encoder(connector);
79e53945 7127 struct drm_crtc *possible_crtc;
4ef69c7a 7128 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7129 struct drm_crtc *crtc = NULL;
7130 struct drm_device *dev = encoder->dev;
94352cf9 7131 struct drm_framebuffer *fb;
79e53945
JB		 7132 int i = -1;
7133
d2dff872
CW		 7134 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7135 connector->base.id, drm_get_connector_name(connector),
7136 encoder->base.id, drm_get_encoder_name(encoder));
7137
79e53945
JB		 7138 /*
7139 * Algorithm gets a little messy:
7a5e4805 7140 *
79e53945
JB		 7141 * - if the connector already has an assigned crtc, use it (but make
7142 * sure it's on first)
7a5e4805 7143 *
79e53945
JB		 7144 * - try to find the first unused crtc that can drive this connector,
7145 * and use that if we find one
79e53945
JB		 7146 */
7147
7148 /* See if we already have a CRTC for this connector */
7149 if (encoder->crtc) {
7150 crtc = encoder->crtc;
8261b191 7151
7b24056b
DV		 7152 mutex_lock(&crtc->mutex);
7153
24218aac 7154 old->dpms_mode = connector->dpms;
8261b191
CW		 7155 old->load_detect_temp = false;
7156
7157 /* Make sure the crtc and connector are running */
24218aac
DV		 7158 if (connector->dpms != DRM_MODE_DPMS_ON)
7159 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7160
7173188d 7161 return true;
79e53945
JB		 7162 }
7163
7164 /* Find an unused one (if possible) */
7165 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7166 i++;
7167 if (!(encoder->possible_crtcs & (1 << i)))
7168 continue;
7169 if (!possible_crtc->enabled) {
7170 crtc = possible_crtc;
7171 break;
7172 }
79e53945
JB		 7173 }
7174
7175 /*
7176 * If we didn't find an unused CRTC, don't use any.
7177 */
7178 if (!crtc) {
7173188d
CW		 7179 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7180 return false;
79e53945
JB		 7181 }
7182
7b24056b 7183 mutex_lock(&crtc->mutex);
fc303101
DV		 7184 intel_encoder->new_crtc = to_intel_crtc(crtc);
7185 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7186
7187 intel_crtc = to_intel_crtc(crtc);
24218aac 7188 old->dpms_mode = connector->dpms;
8261b191 7189 old->load_detect_temp = true;
d2dff872 7190 old->release_fb = NULL;
79e53945 7191
6492711d
CW		 7192 if (!mode)
7193 mode = &load_detect_mode;
79e53945 7194
d2dff872
CW		 7195 /* We need a framebuffer large enough to accommodate all accesses
7196 * that the plane may generate whilst we perform load detection.
7197 * We can not rely on the fbcon either being present (we get called
7198 * during its initialisation to detect all boot displays, or it may
7199 * not even exist) or that it is large enough to satisfy the
7200 * requested mode.
7201 */
94352cf9
DV		 7202 fb = mode_fits_in_fbdev(dev, mode);
7203 if (fb == NULL) {
d2dff872 7204 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7205 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7206 old->release_fb = fb;
d2dff872
CW		 7207 } else
7208 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7209 if (IS_ERR(fb)) {
d2dff872 7210 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7211 mutex_unlock(&crtc->mutex);
0e8b3d3e 7212 return false;
79e53945 7213 }
79e53945 7214
c0c36b94 7215 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7216 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7217 if (old->release_fb)
7218 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7219 mutex_unlock(&crtc->mutex);
0e8b3d3e 7220 return false;
79e53945 7221 }
7173188d 7222
79e53945 7223 /* let the connector get through one full cycle before testing */
9d0498a2 7224 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7225 return true;
79e53945
JB		 7226}
7227
d2434ab7 7228void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7229 struct intel_load_detect_pipe *old)
79e53945 7230{
d2434ab7
DV		 7231 struct intel_encoder *intel_encoder =
7232 intel_attached_encoder(connector);
4ef69c7a 7233 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7234 struct drm_crtc *crtc = encoder->crtc;
79e53945 7235
d2dff872
CW		 7236 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7237 connector->base.id, drm_get_connector_name(connector),
7238 encoder->base.id, drm_get_encoder_name(encoder));
7239
8261b191 7240 if (old->load_detect_temp) {
fc303101
DV		 7241 to_intel_connector(connector)->new_encoder = NULL;
7242 intel_encoder->new_crtc = NULL;
7243 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7244
36206361
DV		 7245 if (old->release_fb) {
7246 drm_framebuffer_unregister_private(old->release_fb);
7247 drm_framebuffer_unreference(old->release_fb);
7248 }
d2dff872 7249
67c96400 7250 mutex_unlock(&crtc->mutex);
0622a53c 7251 return;
79e53945
JB		 7252 }
7253
c751ce4f 7254 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7255 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7256 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7257
7258 mutex_unlock(&crtc->mutex);
79e53945
JB		 7259}
7260
7261/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7262static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7263 struct intel_crtc_config *pipe_config)
79e53945 7264{
f1f644dc 7265 struct drm_device *dev = crtc->base.dev;
79e53945 7266 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7267 int pipe = pipe_config->cpu_transcoder;
548f245b 7268 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7269 u32 fp;
7270 intel_clock_t clock;
7271
7272 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7273 fp = I915_READ(FP0(pipe));
79e53945 7274 else
39adb7a5 7275 fp = I915_READ(FP1(pipe));
79e53945
JB		 7276
7277 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7278 if (IS_PINEVIEW(dev)) {
7279 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7280 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7281 } else {
7282 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7283 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7284 }
7285
a6c45cf0 7286 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7287 if (IS_PINEVIEW(dev))
7288 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7289 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7290 else
7291 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7292 DPLL_FPA01_P1_POST_DIV_SHIFT);
7293
7294 switch (dpll & DPLL_MODE_MASK) {
7295 case DPLLB_MODE_DAC_SERIAL:
7296 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7297 5 : 10;
7298 break;
7299 case DPLLB_MODE_LVDS:
7300 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7301 7 : 14;
7302 break;
7303 default:
28c97730 7304 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7305 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 7306 pipe_config->adjusted_mode.clock = 0;
7307 return;
79e53945
JB		 7308 }
7309
ac58c3f0
DV		 7310 if (IS_PINEVIEW(dev))
7311 pineview_clock(96000, &clock);
7312 else
7313 i9xx_clock(96000, &clock);
79e53945
JB		 7314 } else {
7315 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7316
7317 if (is_lvds) {
7318 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7319 DPLL_FPA01_P1_POST_DIV_SHIFT);
7320 clock.p2 = 14;
7321
7322 if ((dpll & PLL_REF_INPUT_MASK) ==
7323 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7324 /* XXX: might not be 66MHz */
ac58c3f0 7325 i9xx_clock(66000, &clock);
79e53945 7326 } else
ac58c3f0 7327 i9xx_clock(48000, &clock);
79e53945
JB		 7328 } else {
7329 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7330 clock.p1 = 2;
7331 else {
7332 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7333 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7334 }
7335 if (dpll & PLL_P2_DIVIDE_BY_4)
7336 clock.p2 = 4;
7337 else
7338 clock.p2 = 2;
7339
ac58c3f0 7340 i9xx_clock(48000, &clock);
79e53945
JB		 7341 }
7342 }
7343
a2dc53e7 7344 pipe_config->adjusted_mode.clock = clock.dot;
f1f644dc
JB		 7345}
7346
7347static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7348 struct intel_crtc_config *pipe_config)
7349{
7350 struct drm_device *dev = crtc->base.dev;
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7353 int link_freq, repeat;
7354 u64 clock;
7355 u32 link_m, link_n;
7356
7357 repeat = pipe_config->pixel_multiplier;
7358
7359 /*
7360 * The calculation for the data clock is:
7361 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7362 * But we want to avoid losing precison if possible, so:
7363 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7364 *
7365 * and the link clock is simpler:
7366 * link_clock = (m * link_clock * repeat) / n
7367 */
7368
7369 /*
7370 * We need to get the FDI or DP link clock here to derive
7371 * the M/N dividers.
7372 *
7373 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7374 * For DP, it's either 1.62GHz or 2.7GHz.
7375 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7376 */
f1f644dc
JB		 7377 if (pipe_config->has_pch_encoder)
7378 link_freq = intel_fdi_link_freq(dev) * 10000;
7379 else
7380 link_freq = pipe_config->port_clock;
7381
7382 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7383 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7384
7385 if (!link_m || !link_n)
7386 return;
79e53945 7387
f1f644dc
JB		 7388 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7389 do_div(clock, link_n);
7390
7391 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7392}
7393
7394/** Returns the currently programmed mode of the given pipe. */
7395struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7396 struct drm_crtc *crtc)
7397{
548f245b 7398 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7400 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7401 struct drm_display_mode *mode;
f1f644dc 7402 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7403 int htot = I915_READ(HTOTAL(cpu_transcoder));
7404 int hsync = I915_READ(HSYNC(cpu_transcoder));
7405 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7406 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7407
7408 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7409 if (!mode)
7410 return NULL;
7411
f1f644dc
JB		 7412 /*
7413 * Construct a pipe_config sufficient for getting the clock info
7414 * back out of crtc_clock_get.
7415 *
7416 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7417 * to use a real value here instead.
7418 */
e143a21c 7419 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7420 pipe_config.pixel_multiplier = 1;
7421 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7422
7423 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7424 mode->hdisplay = (htot & 0xffff) + 1;
7425 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7426 mode->hsync_start = (hsync & 0xffff) + 1;
7427 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7428 mode->vdisplay = (vtot & 0xffff) + 1;
7429 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7430 mode->vsync_start = (vsync & 0xffff) + 1;
7431 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7432
7433 drm_mode_set_name(mode);
79e53945
JB		 7434
7435 return mode;
7436}
7437
3dec0095 7438static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7439{
7440 struct drm_device *dev = crtc->dev;
7441 drm_i915_private_t *dev_priv = dev->dev_private;
7442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7443 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7444 int dpll_reg = DPLL(pipe);
7445 int dpll;
652c393a 7446
bad720ff 7447 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7448 return;
7449
7450 if (!dev_priv->lvds_downclock_avail)
7451 return;
7452
dbdc6479 7453 dpll = I915_READ(dpll_reg);
652c393a 7454 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7455 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7456
8ac5a6d5 7457 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7458
7459 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7460 I915_WRITE(dpll_reg, dpll);
9d0498a2 7461 intel_wait_for_vblank(dev, pipe);
dbdc6479 7462
652c393a
JB		 7463 dpll = I915_READ(dpll_reg);
7464 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7465 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7466 }
652c393a
JB		 7467}
7468
7469static void intel_decrease_pllclock(struct drm_crtc *crtc)
7470{
7471 struct drm_device *dev = crtc->dev;
7472 drm_i915_private_t *dev_priv = dev->dev_private;
7473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7474
bad720ff 7475 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7476 return;
7477
7478 if (!dev_priv->lvds_downclock_avail)
7479 return;
7480
7481 /*
7482 * Since this is called by a timer, we should never get here in
7483 * the manual case.
7484 */
7485 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7486 int pipe = intel_crtc->pipe;
7487 int dpll_reg = DPLL(pipe);
7488 int dpll;
f6e5b160 7489
44d98a61 7490 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7491
8ac5a6d5 7492 assert_panel_unlocked(dev_priv, pipe);
652c393a 7493
dc257cf1 7494 dpll = I915_READ(dpll_reg);
652c393a
JB		 7495 dpll |= DISPLAY_RATE_SELECT_FPA1;
7496 I915_WRITE(dpll_reg, dpll);
9d0498a2 7497 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7498 dpll = I915_READ(dpll_reg);
7499 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7500 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7501 }
7502
7503}
7504
f047e395
CW		 7505void intel_mark_busy(struct drm_device *dev)
7506{
c67a470b
PZ		 7507 struct drm_i915_private *dev_priv = dev->dev_private;
7508
7509 hsw_package_c8_gpu_busy(dev_priv);
7510 i915_update_gfx_val(dev_priv);
f047e395
CW		 7511}
7512
7513void intel_mark_idle(struct drm_device *dev)
652c393a 7514{
c67a470b 7515 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7516 struct drm_crtc *crtc;
652c393a 7517
c67a470b
PZ		 7518 hsw_package_c8_gpu_idle(dev_priv);
7519
652c393a
JB		 7520 if (!i915_powersave)
7521 return;
7522
652c393a 7523 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7524 if (!crtc->fb)
7525 continue;
7526
725a5b54 7527 intel_decrease_pllclock(crtc);
652c393a 7528 }
652c393a
JB		 7529}
7530
c65355bb
CW		 7531void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7532 struct intel_ring_buffer *ring)
652c393a 7533{
f047e395
CW		 7534 struct drm_device *dev = obj->base.dev;
7535 struct drm_crtc *crtc;
652c393a 7536
f047e395 7537 if (!i915_powersave)
acb87dfb
CW		 7538 return;
7539
652c393a
JB		 7540 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7541 if (!crtc->fb)
7542 continue;
7543
c65355bb
CW		 7544 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7545 continue;
7546
7547 intel_increase_pllclock(crtc);
7548 if (ring && intel_fbc_enabled(dev))
7549 ring->fbc_dirty = true;
652c393a
JB		 7550 }
7551}
7552
79e53945
JB		 7553static void intel_crtc_destroy(struct drm_crtc *crtc)
7554{
7555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7556 struct drm_device *dev = crtc->dev;
7557 struct intel_unpin_work *work;
7558 unsigned long flags;
7559
7560 spin_lock_irqsave(&dev->event_lock, flags);
7561 work = intel_crtc->unpin_work;
7562 intel_crtc->unpin_work = NULL;
7563 spin_unlock_irqrestore(&dev->event_lock, flags);
7564
7565 if (work) {
7566 cancel_work_sync(&work->work);
7567 kfree(work);
7568 }
79e53945 7569
40ccc72b
MK		 7570 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7571
79e53945 7572 drm_crtc_cleanup(crtc);
67e77c5a 7573
79e53945
JB		 7574 kfree(intel_crtc);
7575}
7576
6b95a207
KH		 7577static void intel_unpin_work_fn(struct work_struct *__work)
7578{
7579 struct intel_unpin_work *work =
7580 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7581 struct drm_device *dev = work->crtc->dev;
6b95a207 7582
b4a98e57 7583 mutex_lock(&dev->struct_mutex);
1690e1eb 7584 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7585 drm_gem_object_unreference(&work->pending_flip_obj->base);
7586 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7587
b4a98e57
CW		 7588 intel_update_fbc(dev);
7589 mutex_unlock(&dev->struct_mutex);
7590
7591 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7592 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7593
6b95a207
KH		 7594 kfree(work);
7595}
7596
1afe3e9d 7597static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7598 struct drm_crtc *crtc)
6b95a207
KH		 7599{
7600 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7602 struct intel_unpin_work *work;
6b95a207
KH		 7603 unsigned long flags;
7604
7605 /* Ignore early vblank irqs */
7606 if (intel_crtc == NULL)
7607 return;
7608
7609 spin_lock_irqsave(&dev->event_lock, flags);
7610 work = intel_crtc->unpin_work;
e7d841ca
CW		 7611
7612 /* Ensure we don't miss a work->pending update ... */
7613 smp_rmb();
7614
7615 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7616 spin_unlock_irqrestore(&dev->event_lock, flags);
7617 return;
7618 }
7619
e7d841ca
CW		 7620 /* and that the unpin work is consistent wrt ->pending. */
7621 smp_rmb();
7622
6b95a207 7623 intel_crtc->unpin_work = NULL;
6b95a207 7624
45a066eb
RC		 7625 if (work->event)
7626 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7627
0af7e4df
MK		 7628 drm_vblank_put(dev, intel_crtc->pipe);
7629
6b95a207
KH		 7630 spin_unlock_irqrestore(&dev->event_lock, flags);
7631
2c10d571 7632 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7633
7634 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7635
7636 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7637}
7638
1afe3e9d
JB		 7639void intel_finish_page_flip(struct drm_device *dev, int pipe)
7640{
7641 drm_i915_private_t *dev_priv = dev->dev_private;
7642 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7643
49b14a5c 7644 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7645}
7646
7647void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7648{
7649 drm_i915_private_t *dev_priv = dev->dev_private;
7650 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7651
49b14a5c 7652 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7653}
7654
6b95a207
KH		 7655void intel_prepare_page_flip(struct drm_device *dev, int plane)
7656{
7657 drm_i915_private_t *dev_priv = dev->dev_private;
7658 struct intel_crtc *intel_crtc =
7659 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7660 unsigned long flags;
7661
e7d841ca
CW		 7662 /* NB: An MMIO update of the plane base pointer will also
7663 * generate a page-flip completion irq, i.e. every modeset
7664 * is also accompanied by a spurious intel_prepare_page_flip().
7665 */
6b95a207 7666 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7667 if (intel_crtc->unpin_work)
7668 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7669 spin_unlock_irqrestore(&dev->event_lock, flags);
7670}
7671
e7d841ca
CW		 7672inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7673{
7674 /* Ensure that the work item is consistent when activating it ... */
7675 smp_wmb();
7676 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7677 /* and that it is marked active as soon as the irq could fire. */
7678 smp_wmb();
7679}
7680
8c9f3aaf
JB		 7681static int intel_gen2_queue_flip(struct drm_device *dev,
7682 struct drm_crtc *crtc,
7683 struct drm_framebuffer *fb,
ed8d1975
KP		 7684 struct drm_i915_gem_object *obj,
7685 uint32_t flags)
8c9f3aaf
JB		 7686{
7687 struct drm_i915_private *dev_priv = dev->dev_private;
7688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7689 u32 flip_mask;
6d90c952 7690 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7691 int ret;
7692
6d90c952 7693 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7694 if (ret)
83d4092b 7695 goto err;
8c9f3aaf 7696
6d90c952 7697 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7698 if (ret)
83d4092b 7699 goto err_unpin;
8c9f3aaf
JB		 7700
7701 /* Can't queue multiple flips, so wait for the previous
7702 * one to finish before executing the next.
7703 */
7704 if (intel_crtc->plane)
7705 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7706 else
7707 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7708 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7709 intel_ring_emit(ring, MI_NOOP);
7710 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7711 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7712 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7713 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7714 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7715
7716 intel_mark_page_flip_active(intel_crtc);
6d90c952 7717 intel_ring_advance(ring);
83d4092b
CW		 7718 return 0;
7719
7720err_unpin:
7721 intel_unpin_fb_obj(obj);
7722err:
8c9f3aaf
JB		 7723 return ret;
7724}
7725
7726static int intel_gen3_queue_flip(struct drm_device *dev,
7727 struct drm_crtc *crtc,
7728 struct drm_framebuffer *fb,
ed8d1975
KP		 7729 struct drm_i915_gem_object *obj,
7730 uint32_t flags)
8c9f3aaf
JB		 7731{
7732 struct drm_i915_private *dev_priv = dev->dev_private;
7733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7734 u32 flip_mask;
6d90c952 7735 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7736 int ret;
7737
6d90c952 7738 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7739 if (ret)
83d4092b 7740 goto err;
8c9f3aaf 7741
6d90c952 7742 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7743 if (ret)
83d4092b 7744 goto err_unpin;
8c9f3aaf
JB		 7745
7746 if (intel_crtc->plane)
7747 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7748 else
7749 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7750 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7751 intel_ring_emit(ring, MI_NOOP);
7752 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7753 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7754 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7755 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7756 intel_ring_emit(ring, MI_NOOP);
7757
e7d841ca 7758 intel_mark_page_flip_active(intel_crtc);
6d90c952 7759 intel_ring_advance(ring);
83d4092b
CW		 7760 return 0;
7761
7762err_unpin:
7763 intel_unpin_fb_obj(obj);
7764err:
8c9f3aaf
JB		 7765 return ret;
7766}
7767
7768static int intel_gen4_queue_flip(struct drm_device *dev,
7769 struct drm_crtc *crtc,
7770 struct drm_framebuffer *fb,
ed8d1975
KP		 7771 struct drm_i915_gem_object *obj,
7772 uint32_t flags)
8c9f3aaf
JB		 7773{
7774 struct drm_i915_private *dev_priv = dev->dev_private;
7775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7776 uint32_t pf, pipesrc;
6d90c952 7777 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7778 int ret;
7779
6d90c952 7780 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7781 if (ret)
83d4092b 7782 goto err;
8c9f3aaf 7783
6d90c952 7784 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7785 if (ret)
83d4092b 7786 goto err_unpin;
8c9f3aaf
JB		 7787
7788 /* i965+ uses the linear or tiled offsets from the
7789 * Display Registers (which do not change across a page-flip)
7790 * so we need only reprogram the base address.
7791 */
6d90c952
DV		 7792 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7793 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7794 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7795 intel_ring_emit(ring,
f343c5f6 7796 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7797 obj->tiling_mode);
8c9f3aaf
JB		 7798
7799 /* XXX Enabling the panel-fitter across page-flip is so far
7800 * untested on non-native modes, so ignore it for now.
7801 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7802 */
7803 pf = 0;
7804 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7805 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7806
7807 intel_mark_page_flip_active(intel_crtc);
6d90c952 7808 intel_ring_advance(ring);
83d4092b
CW		 7809 return 0;
7810
7811err_unpin:
7812 intel_unpin_fb_obj(obj);
7813err:
8c9f3aaf
JB		 7814 return ret;
7815}
7816
7817static int intel_gen6_queue_flip(struct drm_device *dev,
7818 struct drm_crtc *crtc,
7819 struct drm_framebuffer *fb,
ed8d1975
KP		 7820 struct drm_i915_gem_object *obj,
7821 uint32_t flags)
8c9f3aaf
JB		 7822{
7823 struct drm_i915_private *dev_priv = dev->dev_private;
7824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7825 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7826 uint32_t pf, pipesrc;
7827 int ret;
7828
6d90c952 7829 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7830 if (ret)
83d4092b 7831 goto err;
8c9f3aaf 7832
6d90c952 7833 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7834 if (ret)
83d4092b 7835 goto err_unpin;
8c9f3aaf 7836
6d90c952
DV		 7837 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7838 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7839 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7840 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7841
dc257cf1
DV		 7842 /* Contrary to the suggestions in the documentation,
7843 * "Enable Panel Fitter" does not seem to be required when page
7844 * flipping with a non-native mode, and worse causes a normal
7845 * modeset to fail.
7846 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7847 */
7848 pf = 0;
8c9f3aaf 7849 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7850 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7851
7852 intel_mark_page_flip_active(intel_crtc);
6d90c952 7853 intel_ring_advance(ring);
83d4092b
CW		 7854 return 0;
7855
7856err_unpin:
7857 intel_unpin_fb_obj(obj);
7858err:
8c9f3aaf
JB		 7859 return ret;
7860}
7861
7c9017e5
JB		 7862static int intel_gen7_queue_flip(struct drm_device *dev,
7863 struct drm_crtc *crtc,
7864 struct drm_framebuffer *fb,
ed8d1975
KP		 7865 struct drm_i915_gem_object *obj,
7866 uint32_t flags)
7c9017e5
JB		 7867{
7868 struct drm_i915_private *dev_priv = dev->dev_private;
7869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7870 struct intel_ring_buffer *ring;
cb05d8de 7871 uint32_t plane_bit = 0;
ffe74d75
CW		 7872 int len, ret;
7873
7874 ring = obj->ring;
7875 if (ring == NULL || ring->id != RCS)
7876 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7877
7878 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7879 if (ret)
83d4092b 7880 goto err;
7c9017e5 7881
cb05d8de
DV		 7882 switch(intel_crtc->plane) {
7883 case PLANE_A:
7884 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7885 break;
7886 case PLANE_B:
7887 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7888 break;
7889 case PLANE_C:
7890 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7891 break;
7892 default:
7893 WARN_ONCE(1, "unknown plane in flip command\n");
7894 ret = -ENODEV;
ab3951eb 7895 goto err_unpin;
cb05d8de
DV		 7896 }
7897
ffe74d75
CW		 7898 len = 4;
7899 if (ring->id == RCS)
7900 len += 6;
7901
7902 ret = intel_ring_begin(ring, len);
7c9017e5 7903 if (ret)
83d4092b 7904 goto err_unpin;
7c9017e5 7905
ffe74d75
CW		 7906 /* Unmask the flip-done completion message. Note that the bspec says that
7907 * we should do this for both the BCS and RCS, and that we must not unmask
7908 * more than one flip event at any time (or ensure that one flip message
7909 * can be sent by waiting for flip-done prior to queueing new flips).
7910 * Experimentation says that BCS works despite DERRMR masking all
7911 * flip-done completion events and that unmasking all planes at once
7912 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7913 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7914 */
7915 if (ring->id == RCS) {
7916 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7917 intel_ring_emit(ring, DERRMR);
7918 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7919 DERRMR_PIPEB_PRI_FLIP_DONE |
7920 DERRMR_PIPEC_PRI_FLIP_DONE));
7921 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7922 intel_ring_emit(ring, DERRMR);
7923 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7924 }
7925
cb05d8de 7926 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7927 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7928 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7929 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7930
7931 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7932 intel_ring_advance(ring);
83d4092b
CW		 7933 return 0;
7934
7935err_unpin:
7936 intel_unpin_fb_obj(obj);
7937err:
7c9017e5
JB		 7938 return ret;
7939}
7940
8c9f3aaf
JB		 7941static int intel_default_queue_flip(struct drm_device *dev,
7942 struct drm_crtc *crtc,
7943 struct drm_framebuffer *fb,
ed8d1975
KP		 7944 struct drm_i915_gem_object *obj,
7945 uint32_t flags)
8c9f3aaf
JB		 7946{
7947 return -ENODEV;
7948}
7949
6b95a207
KH		 7950static int intel_crtc_page_flip(struct drm_crtc *crtc,
7951 struct drm_framebuffer *fb,
ed8d1975
KP		 7952 struct drm_pending_vblank_event *event,
7953 uint32_t page_flip_flags)
6b95a207
KH		 7954{
7955 struct drm_device *dev = crtc->dev;
7956 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7957 struct drm_framebuffer *old_fb = crtc->fb;
7958 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7960 struct intel_unpin_work *work;
8c9f3aaf 7961 unsigned long flags;
52e68630 7962 int ret;
6b95a207 7963
e6a595d2
VS		 7964 /* Can't change pixel format via MI display flips. */
7965 if (fb->pixel_format != crtc->fb->pixel_format)
7966 return -EINVAL;
7967
7968 /*
7969 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7970 * Note that pitch changes could also affect these register.
7971 */
7972 if (INTEL_INFO(dev)->gen > 3 &&
7973 (fb->offsets[0] != crtc->fb->offsets[0] ||
7974 fb->pitches[0] != crtc->fb->pitches[0]))
7975 return -EINVAL;
7976
6b95a207
KH		 7977 work = kzalloc(sizeof *work, GFP_KERNEL);
7978 if (work == NULL)
7979 return -ENOMEM;
7980
6b95a207 7981 work->event = event;
b4a98e57 7982 work->crtc = crtc;
4a35f83b 7983 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7984 INIT_WORK(&work->work, intel_unpin_work_fn);
7985
7317c75e
JB		 7986 ret = drm_vblank_get(dev, intel_crtc->pipe);
7987 if (ret)
7988 goto free_work;
7989
6b95a207
KH		 7990 /* We borrow the event spin lock for protecting unpin_work */
7991 spin_lock_irqsave(&dev->event_lock, flags);
7992 if (intel_crtc->unpin_work) {
7993 spin_unlock_irqrestore(&dev->event_lock, flags);
7994 kfree(work);
7317c75e 7995 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7996
7997 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7998 return -EBUSY;
7999 }
8000 intel_crtc->unpin_work = work;
8001 spin_unlock_irqrestore(&dev->event_lock, flags);
8002
b4a98e57
CW		 8003 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8004 flush_workqueue(dev_priv->wq);
8005
79158103
CW		 8006 ret = i915_mutex_lock_interruptible(dev);
8007 if (ret)
8008 goto cleanup;
6b95a207 8009
75dfca80 8010 /* Reference the objects for the scheduled work. */
05394f39
CW		 8011 drm_gem_object_reference(&work->old_fb_obj->base);
8012 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8013
8014 crtc->fb = fb;
96b099fd 8015
e1f99ce6 8016 work->pending_flip_obj = obj;
e1f99ce6 8017
4e5359cd
SF		 8018 work->enable_stall_check = true;
8019
b4a98e57 8020 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8021 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8022
ed8d1975 8023 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8024 if (ret)
8025 goto cleanup_pending;
6b95a207 8026
7782de3b 8027 intel_disable_fbc(dev);
c65355bb 8028 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8029 mutex_unlock(&dev->struct_mutex);
8030
e5510fac
JB		 8031 trace_i915_flip_request(intel_crtc->plane, obj);
8032
6b95a207 8033 return 0;
96b099fd 8034
8c9f3aaf 8035cleanup_pending:
b4a98e57 8036 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8037 crtc->fb = old_fb;
05394f39
CW		 8038 drm_gem_object_unreference(&work->old_fb_obj->base);
8039 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8040 mutex_unlock(&dev->struct_mutex);
8041
79158103 8042cleanup:
96b099fd
CW		 8043 spin_lock_irqsave(&dev->event_lock, flags);
8044 intel_crtc->unpin_work = NULL;
8045 spin_unlock_irqrestore(&dev->event_lock, flags);
8046
7317c75e
JB		 8047 drm_vblank_put(dev, intel_crtc->pipe);
8048free_work:
96b099fd
CW		 8049 kfree(work);
8050
8051 return ret;
6b95a207
KH		 8052}
8053
f6e5b160 8054static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8055 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8056 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8057};
8058
50f56119
DV		 8059static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8060 struct drm_crtc *crtc)
8061{
8062 struct drm_device *dev;
8063 struct drm_crtc *tmp;
8064 int crtc_mask = 1;
47f1c6c9 8065
50f56119 8066 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8067
50f56119 8068 dev = crtc->dev;
47f1c6c9 8069
50f56119
DV		 8070 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8071 if (tmp == crtc)
8072 break;
8073 crtc_mask <<= 1;
8074 }
47f1c6c9 8075
50f56119
DV		 8076 if (encoder->possible_crtcs & crtc_mask)
8077 return true;
8078 return false;
47f1c6c9 8079}
79e53945 8080
9a935856
DV		 8081/**
8082 * intel_modeset_update_staged_output_state
8083 *
8084 * Updates the staged output configuration state, e.g. after we've read out the
8085 * current hw state.
8086 */
8087static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8088{
9a935856
DV		 8089 struct intel_encoder *encoder;
8090 struct intel_connector *connector;
f6e5b160 8091
9a935856
DV		 8092 list_for_each_entry(connector, &dev->mode_config.connector_list,
8093 base.head) {
8094 connector->new_encoder =
8095 to_intel_encoder(connector->base.encoder);
8096 }
f6e5b160 8097
9a935856
DV		 8098 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8099 base.head) {
8100 encoder->new_crtc =
8101 to_intel_crtc(encoder->base.crtc);
8102 }
f6e5b160
CW		 8103}
8104
9a935856
DV		 8105/**
8106 * intel_modeset_commit_output_state
8107 *
8108 * This function copies the stage display pipe configuration to the real one.
8109 */
8110static void intel_modeset_commit_output_state(struct drm_device *dev)
8111{
8112 struct intel_encoder *encoder;
8113 struct intel_connector *connector;
f6e5b160 8114
9a935856
DV		 8115 list_for_each_entry(connector, &dev->mode_config.connector_list,
8116 base.head) {
8117 connector->base.encoder = &connector->new_encoder->base;
8118 }
f6e5b160 8119
9a935856
DV		 8120 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8121 base.head) {
8122 encoder->base.crtc = &encoder->new_crtc->base;
8123 }
8124}
8125
050f7aeb
DV		 8126static void
8127connected_sink_compute_bpp(struct intel_connector * connector,
8128 struct intel_crtc_config *pipe_config)
8129{
8130 int bpp = pipe_config->pipe_bpp;
8131
8132 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8133 connector->base.base.id,
8134 drm_get_connector_name(&connector->base));
8135
8136 /* Don't use an invalid EDID bpc value */
8137 if (connector->base.display_info.bpc &&
8138 connector->base.display_info.bpc * 3 < bpp) {
8139 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8140 bpp, connector->base.display_info.bpc*3);
8141 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8142 }
8143
8144 /* Clamp bpp to 8 on screens without EDID 1.4 */
8145 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8146 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8147 bpp);
8148 pipe_config->pipe_bpp = 24;
8149 }
8150}
8151
4e53c2e0 8152static int
050f7aeb
DV		 8153compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8154 struct drm_framebuffer *fb,
8155 struct intel_crtc_config *pipe_config)
4e53c2e0 8156{
050f7aeb
DV		 8157 struct drm_device *dev = crtc->base.dev;
8158 struct intel_connector *connector;
4e53c2e0
DV		 8159 int bpp;
8160
d42264b1
DV		 8161 switch (fb->pixel_format) {
8162 case DRM_FORMAT_C8:
4e53c2e0
DV		 8163 bpp = 8*3; /* since we go through a colormap */
8164 break;
d42264b1
DV		 8165 case DRM_FORMAT_XRGB1555:
8166 case DRM_FORMAT_ARGB1555:
8167 /* checked in intel_framebuffer_init already */
8168 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8169 return -EINVAL;
8170 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8171 bpp = 6*3; /* min is 18bpp */
8172 break;
d42264b1
DV		 8173 case DRM_FORMAT_XBGR8888:
8174 case DRM_FORMAT_ABGR8888:
8175 /* checked in intel_framebuffer_init already */
8176 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8177 return -EINVAL;
8178 case DRM_FORMAT_XRGB8888:
8179 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8180 bpp = 8*3;
8181 break;
d42264b1
DV		 8182 case DRM_FORMAT_XRGB2101010:
8183 case DRM_FORMAT_ARGB2101010:
8184 case DRM_FORMAT_XBGR2101010:
8185 case DRM_FORMAT_ABGR2101010:
8186 /* checked in intel_framebuffer_init already */
8187 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8188 return -EINVAL;
4e53c2e0
DV		 8189 bpp = 10*3;
8190 break;
baba133a 8191 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8192 default:
8193 DRM_DEBUG_KMS("unsupported depth\n");
8194 return -EINVAL;
8195 }
8196
4e53c2e0
DV		 8197 pipe_config->pipe_bpp = bpp;
8198
8199 /* Clamp display bpp to EDID value */
8200 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8201 base.head) {
1b829e05
DV		 8202 if (!connector->new_encoder ||
8203 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8204 continue;
8205
050f7aeb 8206 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8207 }
8208
8209 return bpp;
8210}
8211
c0b03411
DV		 8212static void intel_dump_pipe_config(struct intel_crtc *crtc,
8213 struct intel_crtc_config *pipe_config,
8214 const char *context)
8215{
8216 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8217 context, pipe_name(crtc->pipe));
8218
8219 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8220 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8221 pipe_config->pipe_bpp, pipe_config->dither);
8222 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8223 pipe_config->has_pch_encoder,
8224 pipe_config->fdi_lanes,
8225 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8226 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8227 pipe_config->fdi_m_n.tu);
8228 DRM_DEBUG_KMS("requested mode:\n");
8229 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8230 DRM_DEBUG_KMS("adjusted mode:\n");
8231 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8232 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8233 pipe_config->gmch_pfit.control,
8234 pipe_config->gmch_pfit.pgm_ratios,
8235 pipe_config->gmch_pfit.lvds_border_bits);
8236 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8237 pipe_config->pch_pfit.pos,
8238 pipe_config->pch_pfit.size);
42db64ef 8239 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8240}
8241
accfc0c5
DV		 8242static bool check_encoder_cloning(struct drm_crtc *crtc)
8243{
8244 int num_encoders = 0;
8245 bool uncloneable_encoders = false;
8246 struct intel_encoder *encoder;
8247
8248 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8249 base.head) {
8250 if (&encoder->new_crtc->base != crtc)
8251 continue;
8252
8253 num_encoders++;
8254 if (!encoder->cloneable)
8255 uncloneable_encoders = true;
8256 }
8257
8258 return !(num_encoders > 1 && uncloneable_encoders);
8259}
8260
b8cecdf5
DV		 8261static struct intel_crtc_config *
8262intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8263 struct drm_framebuffer *fb,
b8cecdf5 8264 struct drm_display_mode *mode)
ee7b9f93 8265{
7758a113 8266 struct drm_device *dev = crtc->dev;
7758a113 8267 struct intel_encoder *encoder;
b8cecdf5 8268 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8269 int plane_bpp, ret = -EINVAL;
8270 bool retry = true;
ee7b9f93 8271
accfc0c5
DV		 8272 if (!check_encoder_cloning(crtc)) {
8273 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8274 return ERR_PTR(-EINVAL);
8275 }
8276
b8cecdf5
DV		 8277 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8278 if (!pipe_config)
7758a113
DV		 8279 return ERR_PTR(-ENOMEM);
8280
b8cecdf5
DV		 8281 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8282 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8283 pipe_config->cpu_transcoder =
8284 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8285 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8286
2960bc9c
ID		 8287 /*
8288 * Sanitize sync polarity flags based on requested ones. If neither
8289 * positive or negative polarity is requested, treat this as meaning
8290 * negative polarity.
8291 */
8292 if (!(pipe_config->adjusted_mode.flags &
8293 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8294 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8295
8296 if (!(pipe_config->adjusted_mode.flags &
8297 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8298 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8299
050f7aeb
DV		 8300 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8301 * plane pixel format and any sink constraints into account. Returns the
8302 * source plane bpp so that dithering can be selected on mismatches
8303 * after encoders and crtc also have had their say. */
8304 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8305 fb, pipe_config);
4e53c2e0
DV		 8306 if (plane_bpp < 0)
8307 goto fail;
8308
e29c22c0 8309encoder_retry:
ef1b460d 8310 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8311 pipe_config->port_clock = 0;
ef1b460d 8312 pipe_config->pixel_multiplier = 1;
ff9a6750 8313
135c81b8
DV		 8314 /* Fill in default crtc timings, allow encoders to overwrite them. */
8315 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8316
7758a113
DV		 8317 /* Pass our mode to the connectors and the CRTC to give them a chance to
8318 * adjust it according to limitations or connector properties, and also
8319 * a chance to reject the mode entirely.
47f1c6c9 8320 */
7758a113
DV		 8321 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8322 base.head) {
47f1c6c9 8323
7758a113
DV		 8324 if (&encoder->new_crtc->base != crtc)
8325 continue;
7ae89233 8326
efea6e8e
DV		 8327 if (!(encoder->compute_config(encoder, pipe_config))) {
8328 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8329 goto fail;
8330 }
ee7b9f93 8331 }
47f1c6c9 8332
ff9a6750
DV		 8333 /* Set default port clock if not overwritten by the encoder. Needs to be
8334 * done afterwards in case the encoder adjusts the mode. */
8335 if (!pipe_config->port_clock)
8336 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8337
a43f6e0f 8338 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8339 if (ret < 0) {
7758a113
DV		 8340 DRM_DEBUG_KMS("CRTC fixup failed\n");
8341 goto fail;
ee7b9f93 8342 }
e29c22c0
DV		 8343
8344 if (ret == RETRY) {
8345 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8346 ret = -EINVAL;
8347 goto fail;
8348 }
8349
8350 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8351 retry = false;
8352 goto encoder_retry;
8353 }
8354
4e53c2e0
DV		 8355 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8356 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8357 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8358
b8cecdf5 8359 return pipe_config;
7758a113 8360fail:
b8cecdf5 8361 kfree(pipe_config);
e29c22c0 8362 return ERR_PTR(ret);
ee7b9f93 8363}
47f1c6c9 8364
e2e1ed41
DV		 8365/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8366 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8367static void
8368intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8369 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8370{
8371 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8372 struct drm_device *dev = crtc->dev;
8373 struct intel_encoder *encoder;
8374 struct intel_connector *connector;
8375 struct drm_crtc *tmp_crtc;
79e53945 8376
e2e1ed41 8377 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8378
e2e1ed41
DV		 8379 /* Check which crtcs have changed outputs connected to them, these need
8380 * to be part of the prepare_pipes mask. We don't (yet) support global
8381 * modeset across multiple crtcs, so modeset_pipes will only have one
8382 * bit set at most. */
8383 list_for_each_entry(connector, &dev->mode_config.connector_list,
8384 base.head) {
8385 if (connector->base.encoder == &connector->new_encoder->base)
8386 continue;
79e53945 8387
e2e1ed41
DV		 8388 if (connector->base.encoder) {
8389 tmp_crtc = connector->base.encoder->crtc;
8390
8391 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8392 }
8393
8394 if (connector->new_encoder)
8395 *prepare_pipes |=
8396 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8397 }
8398
e2e1ed41
DV		 8399 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8400 base.head) {
8401 if (encoder->base.crtc == &encoder->new_crtc->base)
8402 continue;
8403
8404 if (encoder->base.crtc) {
8405 tmp_crtc = encoder->base.crtc;
8406
8407 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8408 }
8409
8410 if (encoder->new_crtc)
8411 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8412 }
8413
e2e1ed41
DV		 8414 /* Check for any pipes that will be fully disabled ... */
8415 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8416 base.head) {
8417 bool used = false;
22fd0fab 8418
e2e1ed41
DV		 8419 /* Don't try to disable disabled crtcs. */
8420 if (!intel_crtc->base.enabled)
8421 continue;
7e7d76c3 8422
e2e1ed41
DV		 8423 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8424 base.head) {
8425 if (encoder->new_crtc == intel_crtc)
8426 used = true;
8427 }
8428
8429 if (!used)
8430 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8431 }
8432
e2e1ed41
DV		 8433
8434 /* set_mode is also used to update properties on life display pipes. */
8435 intel_crtc = to_intel_crtc(crtc);
8436 if (crtc->enabled)
8437 *prepare_pipes |= 1 << intel_crtc->pipe;
8438
b6c5164d
DV		 8439 /*
8440 * For simplicity do a full modeset on any pipe where the output routing
8441 * changed. We could be more clever, but that would require us to be
8442 * more careful with calling the relevant encoder->mode_set functions.
8443 */
e2e1ed41
DV		 8444 if (*prepare_pipes)
8445 *modeset_pipes = *prepare_pipes;
8446
8447 /* ... and mask these out. */
8448 *modeset_pipes &= ~(*disable_pipes);
8449 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8450
8451 /*
8452 * HACK: We don't (yet) fully support global modesets. intel_set_config
8453 * obies this rule, but the modeset restore mode of
8454 * intel_modeset_setup_hw_state does not.
8455 */
8456 *modeset_pipes &= 1 << intel_crtc->pipe;
8457 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8458
8459 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8460 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8461}
79e53945 8462
ea9d758d 8463static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8464{
ea9d758d 8465 struct drm_encoder *encoder;
f6e5b160 8466 struct drm_device *dev = crtc->dev;
f6e5b160 8467
ea9d758d
DV		 8468 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8469 if (encoder->crtc == crtc)
8470 return true;
8471
8472 return false;
8473}
8474
8475static void
8476intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8477{
8478 struct intel_encoder *intel_encoder;
8479 struct intel_crtc *intel_crtc;
8480 struct drm_connector *connector;
8481
8482 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8483 base.head) {
8484 if (!intel_encoder->base.crtc)
8485 continue;
8486
8487 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8488
8489 if (prepare_pipes & (1 << intel_crtc->pipe))
8490 intel_encoder->connectors_active = false;
8491 }
8492
8493 intel_modeset_commit_output_state(dev);
8494
8495 /* Update computed state. */
8496 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8497 base.head) {
8498 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8499 }
8500
8501 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8502 if (!connector->encoder || !connector->encoder->crtc)
8503 continue;
8504
8505 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8506
8507 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8508 struct drm_property *dpms_property =
8509 dev->mode_config.dpms_property;
8510
ea9d758d 8511 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8512 drm_object_property_set_value(&connector->base,
68d34720
DV		 8513 dpms_property,
8514 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8515
8516 intel_encoder = to_intel_encoder(connector->encoder);
8517 intel_encoder->connectors_active = true;
8518 }
8519 }
8520
8521}
8522
f1f644dc
JB		 8523static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8524 struct intel_crtc_config *new)
8525{
8526 int clock1, clock2, diff;
8527
8528 clock1 = cur->adjusted_mode.clock;
8529 clock2 = new->adjusted_mode.clock;
8530
8531 if (clock1 == clock2)
8532 return true;
8533
8534 if (!clock1 || !clock2)
8535 return false;
8536
8537 diff = abs(clock1 - clock2);
8538
8539 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8540 return true;
8541
8542 return false;
8543}
8544
25c5b266
DV		 8545#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8546 list_for_each_entry((intel_crtc), \
8547 &(dev)->mode_config.crtc_list, \
8548 base.head) \
0973f18f 8549 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8550
0e8ffe1b 8551static bool
2fa2fe9a
DV		 8552intel_pipe_config_compare(struct drm_device *dev,
8553 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8554 struct intel_crtc_config *pipe_config)
8555{
66e985c0
DV		 8556#define PIPE_CONF_CHECK_X(name) \
8557 if (current_config->name != pipe_config->name) { \
8558 DRM_ERROR("mismatch in " #name " " \
8559 "(expected 0x%08x, found 0x%08x)\n", \
8560 current_config->name, \
8561 pipe_config->name); \
8562 return false; \
8563 }
8564
08a24034
DV		 8565#define PIPE_CONF_CHECK_I(name) \
8566 if (current_config->name != pipe_config->name) { \
8567 DRM_ERROR("mismatch in " #name " " \
8568 "(expected %i, found %i)\n", \
8569 current_config->name, \
8570 pipe_config->name); \
8571 return false; \
88adfff1
DV		 8572 }
8573
1bd1bd80
DV		 8574#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8575 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8576 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8577 "(expected %i, found %i)\n", \
8578 current_config->name & (mask), \
8579 pipe_config->name & (mask)); \
8580 return false; \
8581 }
8582
bb760063
DV		 8583#define PIPE_CONF_QUIRK(quirk) \
8584 ((current_config->quirks | pipe_config->quirks) & (quirk))
8585
eccb140b
DV		 8586 PIPE_CONF_CHECK_I(cpu_transcoder);
8587
08a24034
DV		 8588 PIPE_CONF_CHECK_I(has_pch_encoder);
8589 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8590 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8591 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8592 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8593 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8594 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8595
1bd1bd80
DV		 8596 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8597 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8598 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8599 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8600 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8601 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8602
8603 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8604 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8605 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8606 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8607 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8608 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8609
c93f54cf 8610 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8611
1bd1bd80
DV		 8612 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8613 DRM_MODE_FLAG_INTERLACE);
8614
bb760063
DV		 8615 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8616 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8617 DRM_MODE_FLAG_PHSYNC);
8618 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8619 DRM_MODE_FLAG_NHSYNC);
8620 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8621 DRM_MODE_FLAG_PVSYNC);
8622 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8623 DRM_MODE_FLAG_NVSYNC);
8624 }
045ac3b5 8625
1bd1bd80
DV		 8626 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8627 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8628
2fa2fe9a
DV		 8629 PIPE_CONF_CHECK_I(gmch_pfit.control);
8630 /* pfit ratios are autocomputed by the hw on gen4+ */
8631 if (INTEL_INFO(dev)->gen < 4)
8632 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8633 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8634 PIPE_CONF_CHECK_I(pch_pfit.pos);
8635 PIPE_CONF_CHECK_I(pch_pfit.size);
8636
42db64ef
PZ		 8637 PIPE_CONF_CHECK_I(ips_enabled);
8638
c0d43d62 8639 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8640 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8641 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8642 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8643 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8644
66e985c0 8645#undef PIPE_CONF_CHECK_X
08a24034 8646#undef PIPE_CONF_CHECK_I
1bd1bd80 8647#undef PIPE_CONF_CHECK_FLAGS
bb760063 8648#undef PIPE_CONF_QUIRK
88adfff1 8649
f1f644dc
JB		 8650 if (!IS_HASWELL(dev)) {
8651 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8652 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8653 current_config->adjusted_mode.clock,
8654 pipe_config->adjusted_mode.clock);
8655 return false;
8656 }
8657 }
8658
0e8ffe1b
DV		 8659 return true;
8660}
8661
91d1b4bd
DV		 8662static void
8663check_connector_state(struct drm_device *dev)
8af6cf88 8664{
8af6cf88
DV		 8665 struct intel_connector *connector;
8666
8667 list_for_each_entry(connector, &dev->mode_config.connector_list,
8668 base.head) {
8669 /* This also checks the encoder/connector hw state with the
8670 * ->get_hw_state callbacks. */
8671 intel_connector_check_state(connector);
8672
8673 WARN(&connector->new_encoder->base != connector->base.encoder,
8674 "connector's staged encoder doesn't match current encoder\n");
8675 }
91d1b4bd
DV		 8676}
8677
8678static void
8679check_encoder_state(struct drm_device *dev)
8680{
8681 struct intel_encoder *encoder;
8682 struct intel_connector *connector;
8af6cf88
DV		 8683
8684 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8685 base.head) {
8686 bool enabled = false;
8687 bool active = false;
8688 enum pipe pipe, tracked_pipe;
8689
8690 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8691 encoder->base.base.id,
8692 drm_get_encoder_name(&encoder->base));
8693
8694 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8695 "encoder's stage crtc doesn't match current crtc\n");
8696 WARN(encoder->connectors_active && !encoder->base.crtc,
8697 "encoder's active_connectors set, but no crtc\n");
8698
8699 list_for_each_entry(connector, &dev->mode_config.connector_list,
8700 base.head) {
8701 if (connector->base.encoder != &encoder->base)
8702 continue;
8703 enabled = true;
8704 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8705 active = true;
8706 }
8707 WARN(!!encoder->base.crtc != enabled,
8708 "encoder's enabled state mismatch "
8709 "(expected %i, found %i)\n",
8710 !!encoder->base.crtc, enabled);
8711 WARN(active && !encoder->base.crtc,
8712 "active encoder with no crtc\n");
8713
8714 WARN(encoder->connectors_active != active,
8715 "encoder's computed active state doesn't match tracked active state "
8716 "(expected %i, found %i)\n", active, encoder->connectors_active);
8717
8718 active = encoder->get_hw_state(encoder, &pipe);
8719 WARN(active != encoder->connectors_active,
8720 "encoder's hw state doesn't match sw tracking "
8721 "(expected %i, found %i)\n",
8722 encoder->connectors_active, active);
8723
8724 if (!encoder->base.crtc)
8725 continue;
8726
8727 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8728 WARN(active && pipe != tracked_pipe,
8729 "active encoder's pipe doesn't match"
8730 "(expected %i, found %i)\n",
8731 tracked_pipe, pipe);
8732
8733 }
91d1b4bd
DV		 8734}
8735
8736static void
8737check_crtc_state(struct drm_device *dev)
8738{
8739 drm_i915_private_t *dev_priv = dev->dev_private;
8740 struct intel_crtc *crtc;
8741 struct intel_encoder *encoder;
8742 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8743
8744 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8745 base.head) {
8746 bool enabled = false;
8747 bool active = false;
8748
045ac3b5
JB		 8749 memset(&pipe_config, 0, sizeof(pipe_config));
8750
8af6cf88
DV		 8751 DRM_DEBUG_KMS("[CRTC:%d]\n",
8752 crtc->base.base.id);
8753
8754 WARN(crtc->active && !crtc->base.enabled,
8755 "active crtc, but not enabled in sw tracking\n");
8756
8757 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8758 base.head) {
8759 if (encoder->base.crtc != &crtc->base)
8760 continue;
8761 enabled = true;
8762 if (encoder->connectors_active)
8763 active = true;
8764 }
6c49f241 8765
8af6cf88
DV		 8766 WARN(active != crtc->active,
8767 "crtc's computed active state doesn't match tracked active state "
8768 "(expected %i, found %i)\n", active, crtc->active);
8769 WARN(enabled != crtc->base.enabled,
8770 "crtc's computed enabled state doesn't match tracked enabled state "
8771 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8772
0e8ffe1b
DV		 8773 active = dev_priv->display.get_pipe_config(crtc,
8774 &pipe_config);
d62cf62a
DV		 8775
8776 /* hw state is inconsistent with the pipe A quirk */
8777 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8778 active = crtc->active;
8779
6c49f241
DV		 8780 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8781 base.head) {
3eaba51c 8782 enum pipe pipe;
6c49f241
DV		 8783 if (encoder->base.crtc != &crtc->base)
8784 continue;
3eaba51c
VS		 8785 if (encoder->get_config &&
8786 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8787 encoder->get_config(encoder, &pipe_config);
8788 }
8789
510d5f2f
JB		 8790 if (dev_priv->display.get_clock)
8791 dev_priv->display.get_clock(crtc, &pipe_config);
8792
0e8ffe1b
DV		 8793 WARN(crtc->active != active,
8794 "crtc active state doesn't match with hw state "
8795 "(expected %i, found %i)\n", crtc->active, active);
8796
c0b03411
DV		 8797 if (active &&
8798 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8799 WARN(1, "pipe state doesn't match!\n");
8800 intel_dump_pipe_config(crtc, &pipe_config,
8801 "[hw state]");
8802 intel_dump_pipe_config(crtc, &crtc->config,
8803 "[sw state]");
8804 }
8af6cf88
DV		 8805 }
8806}
8807
91d1b4bd
DV		 8808static void
8809check_shared_dpll_state(struct drm_device *dev)
8810{
8811 drm_i915_private_t *dev_priv = dev->dev_private;
8812 struct intel_crtc *crtc;
8813 struct intel_dpll_hw_state dpll_hw_state;
8814 int i;
5358901f
DV		 8815
8816 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8817 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8818 int enabled_crtcs = 0, active_crtcs = 0;
8819 bool active;
8820
8821 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8822
8823 DRM_DEBUG_KMS("%s\n", pll->name);
8824
8825 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8826
8827 WARN(pll->active > pll->refcount,
8828 "more active pll users than references: %i vs %i\n",
8829 pll->active, pll->refcount);
8830 WARN(pll->active && !pll->on,
8831 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8832 WARN(pll->on && !pll->active,
8833 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8834 WARN(pll->on != active,
8835 "pll on state mismatch (expected %i, found %i)\n",
8836 pll->on, active);
8837
8838 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8839 base.head) {
8840 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8841 enabled_crtcs++;
8842 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8843 active_crtcs++;
8844 }
8845 WARN(pll->active != active_crtcs,
8846 "pll active crtcs mismatch (expected %i, found %i)\n",
8847 pll->active, active_crtcs);
8848 WARN(pll->refcount != enabled_crtcs,
8849 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8850 pll->refcount, enabled_crtcs);
66e985c0
DV		 8851
8852 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8853 sizeof(dpll_hw_state)),
8854 "pll hw state mismatch\n");
5358901f 8855 }
8af6cf88
DV		 8856}
8857
91d1b4bd
DV		 8858void
8859intel_modeset_check_state(struct drm_device *dev)
8860{
8861 check_connector_state(dev);
8862 check_encoder_state(dev);
8863 check_crtc_state(dev);
8864 check_shared_dpll_state(dev);
8865}
8866
f30da187
DV		 8867static int __intel_set_mode(struct drm_crtc *crtc,
8868 struct drm_display_mode *mode,
8869 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8870{
8871 struct drm_device *dev = crtc->dev;
dbf2b54e 8872 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8873 struct drm_display_mode *saved_mode, *saved_hwmode;
8874 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8875 struct intel_crtc *intel_crtc;
8876 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8877 int ret = 0;
a6778b3c 8878
3ac18232 8879 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8880 if (!saved_mode)
8881 return -ENOMEM;
3ac18232 8882 saved_hwmode = saved_mode + 1;
a6778b3c 8883
e2e1ed41 8884 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8885 &prepare_pipes, &disable_pipes);
8886
3ac18232
TG		 8887 *saved_hwmode = crtc->hwmode;
8888 *saved_mode = crtc->mode;
a6778b3c 8889
25c5b266
DV		 8890 /* Hack: Because we don't (yet) support global modeset on multiple
8891 * crtcs, we don't keep track of the new mode for more than one crtc.
8892 * Hence simply check whether any bit is set in modeset_pipes in all the
8893 * pieces of code that are not yet converted to deal with mutliple crtcs
8894 * changing their mode at the same time. */
25c5b266 8895 if (modeset_pipes) {
4e53c2e0 8896 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8897 if (IS_ERR(pipe_config)) {
8898 ret = PTR_ERR(pipe_config);
8899 pipe_config = NULL;
8900
3ac18232 8901 goto out;
25c5b266 8902 }
c0b03411
DV		 8903 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8904 "[modeset]");
25c5b266 8905 }
a6778b3c 8906
460da916
DV		 8907 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8908 intel_crtc_disable(&intel_crtc->base);
8909
ea9d758d
DV		 8910 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8911 if (intel_crtc->base.enabled)
8912 dev_priv->display.crtc_disable(&intel_crtc->base);
8913 }
a6778b3c 8914
6c4c86f5
DV		 8915 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8916 * to set it here already despite that we pass it down the callchain.
f6e5b160 8917 */
b8cecdf5 8918 if (modeset_pipes) {
25c5b266 8919 crtc->mode = *mode;
b8cecdf5
DV		 8920 /* mode_set/enable/disable functions rely on a correct pipe
8921 * config. */
8922 to_intel_crtc(crtc)->config = *pipe_config;
8923 }
7758a113 8924
ea9d758d
DV		 8925 /* Only after disabling all output pipelines that will be changed can we
8926 * update the the output configuration. */
8927 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8928
47fab737
DV		 8929 if (dev_priv->display.modeset_global_resources)
8930 dev_priv->display.modeset_global_resources(dev);
8931
a6778b3c
DV		 8932 /* Set up the DPLL and any encoders state that needs to adjust or depend
8933 * on the DPLL.
f6e5b160 8934 */
25c5b266 8935 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8936 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8937 x, y, fb);
8938 if (ret)
8939 goto done;
a6778b3c
DV		 8940 }
8941
8942 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8943 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8944 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8945
25c5b266
DV		 8946 if (modeset_pipes) {
8947 /* Store real post-adjustment hardware mode. */
b8cecdf5 8948 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8949
25c5b266
DV		 8950 /* Calculate and store various constants which
8951 * are later needed by vblank and swap-completion
8952 * timestamping. They are derived from true hwmode.
8953 */
8954 drm_calc_timestamping_constants(crtc);
8955 }
a6778b3c
DV		 8956
8957 /* FIXME: add subpixel order */
8958done:
c0c36b94 8959 if (ret && crtc->enabled) {
3ac18232
TG		 8960 crtc->hwmode = *saved_hwmode;
8961 crtc->mode = *saved_mode;
a6778b3c
DV		 8962 }
8963
3ac18232 8964out:
b8cecdf5 8965 kfree(pipe_config);
3ac18232 8966 kfree(saved_mode);
a6778b3c 8967 return ret;
f6e5b160
CW		 8968}
8969
e7457a9a
DL		 8970static int intel_set_mode(struct drm_crtc *crtc,
8971 struct drm_display_mode *mode,
8972 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 8973{
8974 int ret;
8975
8976 ret = __intel_set_mode(crtc, mode, x, y, fb);
8977
8978 if (ret == 0)
8979 intel_modeset_check_state(crtc->dev);
8980
8981 return ret;
8982}
8983
c0c36b94
CW		 8984void intel_crtc_restore_mode(struct drm_crtc *crtc)
8985{
8986 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8987}
8988
25c5b266
DV		 8989#undef for_each_intel_crtc_masked
8990
d9e55608
DV		 8991static void intel_set_config_free(struct intel_set_config *config)
8992{
8993 if (!config)
8994 return;
8995
1aa4b628
DV		 8996 kfree(config->save_connector_encoders);
8997 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8998 kfree(config);
8999}
9000
85f9eb71
DV		 9001static int intel_set_config_save_state(struct drm_device *dev,
9002 struct intel_set_config *config)
9003{
85f9eb71
DV		 9004 struct drm_encoder *encoder;
9005 struct drm_connector *connector;
9006 int count;
9007
1aa4b628
DV		 9008 config->save_encoder_crtcs =
9009 kcalloc(dev->mode_config.num_encoder,
9010 sizeof(struct drm_crtc *), GFP_KERNEL);
9011 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9012 return -ENOMEM;
9013
1aa4b628
DV		 9014 config->save_connector_encoders =
9015 kcalloc(dev->mode_config.num_connector,
9016 sizeof(struct drm_encoder *), GFP_KERNEL);
9017 if (!config->save_connector_encoders)
85f9eb71
DV		 9018 return -ENOMEM;
9019
9020 /* Copy data. Note that driver private data is not affected.
9021 * Should anything bad happen only the expected state is
9022 * restored, not the drivers personal bookkeeping.
9023 */
85f9eb71
DV		 9024 count = 0;
9025 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9026 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9027 }
9028
9029 count = 0;
9030 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9031 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9032 }
9033
9034 return 0;
9035}
9036
9037static void intel_set_config_restore_state(struct drm_device *dev,
9038 struct intel_set_config *config)
9039{
9a935856
DV		 9040 struct intel_encoder *encoder;
9041 struct intel_connector *connector;
85f9eb71
DV		 9042 int count;
9043
85f9eb71 9044 count = 0;
9a935856
DV		 9045 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9046 encoder->new_crtc =
9047 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9048 }
9049
9050 count = 0;
9a935856
DV		 9051 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9052 connector->new_encoder =
9053 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9054 }
9055}
9056
e3de42b6 9057static bool
2e57f47d 9058is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9059{
9060 int i;
9061
2e57f47d
CW		 9062 if (set->num_connectors == 0)
9063 return false;
9064
9065 if (WARN_ON(set->connectors == NULL))
9066 return false;
9067
9068 for (i = 0; i < set->num_connectors; i++)
9069 if (set->connectors[i]->encoder &&
9070 set->connectors[i]->encoder->crtc == set->crtc &&
9071 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9072 return true;
9073
9074 return false;
9075}
9076
5e2b584e
DV		 9077static void
9078intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9079 struct intel_set_config *config)
9080{
9081
9082 /* We should be able to check here if the fb has the same properties
9083 * and then just flip_or_move it */
2e57f47d
CW		 9084 if (is_crtc_connector_off(set)) {
9085 config->mode_changed = true;
e3de42b6 9086 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9087 /* If we have no fb then treat it as a full mode set */
9088 if (set->crtc->fb == NULL) {
319d9827
JB		 9089 struct intel_crtc *intel_crtc =
9090 to_intel_crtc(set->crtc);
9091
9092 if (intel_crtc->active && i915_fastboot) {
9093 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9094 config->fb_changed = true;
9095 } else {
9096 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9097 config->mode_changed = true;
9098 }
5e2b584e
DV		 9099 } else if (set->fb == NULL) {
9100 config->mode_changed = true;
72f4901e
DV		 9101 } else if (set->fb->pixel_format !=
9102 set->crtc->fb->pixel_format) {
5e2b584e 9103 config->mode_changed = true;
e3de42b6 9104 } else {
5e2b584e 9105 config->fb_changed = true;
e3de42b6 9106 }
5e2b584e
DV		 9107 }
9108
835c5873 9109 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9110 config->fb_changed = true;
9111
9112 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9113 DRM_DEBUG_KMS("modes are different, full mode set\n");
9114 drm_mode_debug_printmodeline(&set->crtc->mode);
9115 drm_mode_debug_printmodeline(set->mode);
9116 config->mode_changed = true;
9117 }
a1d95703
CW		 9118
9119 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9120 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9121}
9122
2e431051 9123static int
9a935856
DV		 9124intel_modeset_stage_output_state(struct drm_device *dev,
9125 struct drm_mode_set *set,
9126 struct intel_set_config *config)
50f56119 9127{
85f9eb71 9128 struct drm_crtc *new_crtc;
9a935856
DV		 9129 struct intel_connector *connector;
9130 struct intel_encoder *encoder;
f3f08572 9131 int ro;
50f56119 9132
9abdda74 9133 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9134 * of connectors. For paranoia, double-check this. */
9135 WARN_ON(!set->fb && (set->num_connectors != 0));
9136 WARN_ON(set->fb && (set->num_connectors == 0));
9137
9a935856
DV		 9138 list_for_each_entry(connector, &dev->mode_config.connector_list,
9139 base.head) {
9140 /* Otherwise traverse passed in connector list and get encoders
9141 * for them. */
50f56119 9142 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9143 if (set->connectors[ro] == &connector->base) {
9144 connector->new_encoder = connector->encoder;
50f56119
DV		 9145 break;
9146 }
9147 }
9148
9a935856
DV		 9149 /* If we disable the crtc, disable all its connectors. Also, if
9150 * the connector is on the changing crtc but not on the new
9151 * connector list, disable it. */
9152 if ((!set->fb || ro == set->num_connectors) &&
9153 connector->base.encoder &&
9154 connector->base.encoder->crtc == set->crtc) {
9155 connector->new_encoder = NULL;
9156
9157 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9158 connector->base.base.id,
9159 drm_get_connector_name(&connector->base));
9160 }
9161
9162
9163 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9164 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9165 config->mode_changed = true;
50f56119
DV		 9166 }
9167 }
9a935856 9168 /* connector->new_encoder is now updated for all connectors. */
50f56119 9169
9a935856 9170 /* Update crtc of enabled connectors. */
9a935856
DV		 9171 list_for_each_entry(connector, &dev->mode_config.connector_list,
9172 base.head) {
9173 if (!connector->new_encoder)
50f56119
DV		 9174 continue;
9175
9a935856 9176 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9177
9178 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9179 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9180 new_crtc = set->crtc;
9181 }
9182
9183 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9184 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9185 new_crtc)) {
5e2b584e 9186 return -EINVAL;
50f56119 9187 }
9a935856
DV		 9188 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9189
9190 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9191 connector->base.base.id,
9192 drm_get_connector_name(&connector->base),
9193 new_crtc->base.id);
9194 }
9195
9196 /* Check for any encoders that needs to be disabled. */
9197 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9198 base.head) {
9199 list_for_each_entry(connector,
9200 &dev->mode_config.connector_list,
9201 base.head) {
9202 if (connector->new_encoder == encoder) {
9203 WARN_ON(!connector->new_encoder->new_crtc);
9204
9205 goto next_encoder;
9206 }
9207 }
9208 encoder->new_crtc = NULL;
9209next_encoder:
9210 /* Only now check for crtc changes so we don't miss encoders
9211 * that will be disabled. */
9212 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9213 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9214 config->mode_changed = true;
50f56119
DV		 9215 }
9216 }
9a935856 9217 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9218
2e431051
DV		 9219 return 0;
9220}
9221
9222static int intel_crtc_set_config(struct drm_mode_set *set)
9223{
9224 struct drm_device *dev;
2e431051
DV		 9225 struct drm_mode_set save_set;
9226 struct intel_set_config *config;
9227 int ret;
2e431051 9228
8d3e375e
DV		 9229 BUG_ON(!set);
9230 BUG_ON(!set->crtc);
9231 BUG_ON(!set->crtc->helper_private);
2e431051 9232
7e53f3a4
DV		 9233 /* Enforce sane interface api - has been abused by the fb helper. */
9234 BUG_ON(!set->mode && set->fb);
9235 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9236
2e431051
DV		 9237 if (set->fb) {
9238 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9239 set->crtc->base.id, set->fb->base.id,
9240 (int)set->num_connectors, set->x, set->y);
9241 } else {
9242 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9243 }
9244
9245 dev = set->crtc->dev;
9246
9247 ret = -ENOMEM;
9248 config = kzalloc(sizeof(*config), GFP_KERNEL);
9249 if (!config)
9250 goto out_config;
9251
9252 ret = intel_set_config_save_state(dev, config);
9253 if (ret)
9254 goto out_config;
9255
9256 save_set.crtc = set->crtc;
9257 save_set.mode = &set->crtc->mode;
9258 save_set.x = set->crtc->x;
9259 save_set.y = set->crtc->y;
9260 save_set.fb = set->crtc->fb;
9261
9262 /* Compute whether we need a full modeset, only an fb base update or no
9263 * change at all. In the future we might also check whether only the
9264 * mode changed, e.g. for LVDS where we only change the panel fitter in
9265 * such cases. */
9266 intel_set_config_compute_mode_changes(set, config);
9267
9a935856 9268 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9269 if (ret)
9270 goto fail;
9271
5e2b584e 9272 if (config->mode_changed) {
c0c36b94
CW		 9273 ret = intel_set_mode(set->crtc, set->mode,
9274 set->x, set->y, set->fb);
5e2b584e 9275 } else if (config->fb_changed) {
4878cae2
VS		 9276 intel_crtc_wait_for_pending_flips(set->crtc);
9277
4f660f49 9278 ret = intel_pipe_set_base(set->crtc,
94352cf9 9279 set->x, set->y, set->fb);
50f56119
DV		 9280 }
9281
2d05eae1 9282 if (ret) {
bf67dfeb
DV		 9283 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9284 set->crtc->base.id, ret);
50f56119 9285fail:
2d05eae1 9286 intel_set_config_restore_state(dev, config);
50f56119 9287
2d05eae1
CW		 9288 /* Try to restore the config */
9289 if (config->mode_changed &&
9290 intel_set_mode(save_set.crtc, save_set.mode,
9291 save_set.x, save_set.y, save_set.fb))
9292 DRM_ERROR("failed to restore config after modeset failure\n");
9293 }
50f56119 9294
d9e55608
DV		 9295out_config:
9296 intel_set_config_free(config);
50f56119
DV		 9297 return ret;
9298}
f6e5b160
CW		 9299
9300static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9301 .cursor_set = intel_crtc_cursor_set,
9302 .cursor_move = intel_crtc_cursor_move,
9303 .gamma_set = intel_crtc_gamma_set,
50f56119 9304 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9305 .destroy = intel_crtc_destroy,
9306 .page_flip = intel_crtc_page_flip,
9307};
9308
79f689aa
PZ		 9309static void intel_cpu_pll_init(struct drm_device *dev)
9310{
affa9354 9311 if (HAS_DDI(dev))
79f689aa
PZ		 9312 intel_ddi_pll_init(dev);
9313}
9314
5358901f
DV		 9315static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9316 struct intel_shared_dpll *pll,
9317 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9318{
5358901f 9319 uint32_t val;
ee7b9f93 9320
5358901f 9321 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9322 hw_state->dpll = val;
9323 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9324 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9325
9326 return val & DPLL_VCO_ENABLE;
9327}
9328
15bdd4cf
DV		 9329static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9330 struct intel_shared_dpll *pll)
9331{
9332 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9333 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9334}
9335
e7b903d2
DV		 9336static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9337 struct intel_shared_dpll *pll)
9338{
e7b903d2
DV		 9339 /* PCH refclock must be enabled first */
9340 assert_pch_refclk_enabled(dev_priv);
9341
15bdd4cf
DV		 9342 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9343
9344 /* Wait for the clocks to stabilize. */
9345 POSTING_READ(PCH_DPLL(pll->id));
9346 udelay(150);
9347
9348 /* The pixel multiplier can only be updated once the
9349 * DPLL is enabled and the clocks are stable.
9350 *
9351 * So write it again.
9352 */
9353 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9354 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9355 udelay(200);
9356}
9357
9358static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9359 struct intel_shared_dpll *pll)
9360{
9361 struct drm_device *dev = dev_priv->dev;
9362 struct intel_crtc *crtc;
e7b903d2
DV		 9363
9364 /* Make sure no transcoder isn't still depending on us. */
9365 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9366 if (intel_crtc_to_shared_dpll(crtc) == pll)
9367 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9368 }
9369
15bdd4cf
DV		 9370 I915_WRITE(PCH_DPLL(pll->id), 0);
9371 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9372 udelay(200);
9373}
9374
46edb027
DV		 9375static char *ibx_pch_dpll_names[] = {
9376 "PCH DPLL A",
9377 "PCH DPLL B",
9378};
9379
7c74ade1 9380static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9381{
e7b903d2 9382 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9383 int i;
9384
7c74ade1 9385 dev_priv->num_shared_dpll = 2;
ee7b9f93 9386
e72f9fbf 9387 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9388 dev_priv->shared_dplls[i].id = i;
9389 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9390 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9391 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9392 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9393 dev_priv->shared_dplls[i].get_hw_state =
9394 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9395 }
9396}
9397
7c74ade1
DV		 9398static void intel_shared_dpll_init(struct drm_device *dev)
9399{
e7b903d2 9400 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9401
9402 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9403 ibx_pch_dpll_init(dev);
9404 else
9405 dev_priv->num_shared_dpll = 0;
9406
9407 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9408 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9409 dev_priv->num_shared_dpll);
9410}
9411
b358d0a6 9412static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9413{
22fd0fab 9414 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9415 struct intel_crtc *intel_crtc;
9416 int i;
9417
9418 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9419 if (intel_crtc == NULL)
9420 return;
9421
9422 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9423
9424 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9425 for (i = 0; i < 256; i++) {
9426 intel_crtc->lut_r[i] = i;
9427 intel_crtc->lut_g[i] = i;
9428 intel_crtc->lut_b[i] = i;
9429 }
9430
80824003
JB		 9431 /* Swap pipes & planes for FBC on pre-965 */
9432 intel_crtc->pipe = pipe;
9433 intel_crtc->plane = pipe;
e2e767ab 9434 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9435 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9436 intel_crtc->plane = !pipe;
80824003
JB		 9437 }
9438
22fd0fab
JB		 9439 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9440 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9441 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9442 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9443
79e53945 9444 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9445}
9446
08d7b3d1 9447int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9448 struct drm_file *file)
08d7b3d1 9449{
08d7b3d1 9450 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9451 struct drm_mode_object *drmmode_obj;
9452 struct intel_crtc *crtc;
08d7b3d1 9453
1cff8f6b
DV		 9454 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9455 return -ENODEV;
08d7b3d1 9456
c05422d5
DV		 9457 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9458 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9459
c05422d5 9460 if (!drmmode_obj) {
08d7b3d1
CW		 9461 DRM_ERROR("no such CRTC id\n");
9462 return -EINVAL;
9463 }
9464
c05422d5
DV		 9465 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9466 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9467
c05422d5 9468 return 0;
08d7b3d1
CW		 9469}
9470
66a9278e 9471static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9472{
66a9278e
DV		 9473 struct drm_device *dev = encoder->base.dev;
9474 struct intel_encoder *source_encoder;
79e53945 9475 int index_mask = 0;
79e53945
JB		 9476 int entry = 0;
9477
66a9278e
DV		 9478 list_for_each_entry(source_encoder,
9479 &dev->mode_config.encoder_list, base.head) {
9480
9481 if (encoder == source_encoder)
79e53945 9482 index_mask |= (1 << entry);
66a9278e
DV		 9483
9484 /* Intel hw has only one MUX where enocoders could be cloned. */
9485 if (encoder->cloneable && source_encoder->cloneable)
9486 index_mask |= (1 << entry);
9487
79e53945
JB		 9488 entry++;
9489 }
4ef69c7a 9490
79e53945
JB		 9491 return index_mask;
9492}
9493
4d302442
CW		 9494static bool has_edp_a(struct drm_device *dev)
9495{
9496 struct drm_i915_private *dev_priv = dev->dev_private;
9497
9498 if (!IS_MOBILE(dev))
9499 return false;
9500
9501 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9502 return false;
9503
9504 if (IS_GEN5(dev) &&
9505 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9506 return false;
9507
9508 return true;
9509}
9510
79e53945
JB		 9511static void intel_setup_outputs(struct drm_device *dev)
9512{
725e30ad 9513 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9514 struct intel_encoder *encoder;
cb0953d7 9515 bool dpd_is_edp = false;
79e53945 9516
c9093354 9517 intel_lvds_init(dev);
79e53945 9518
c40c0f5b 9519 if (!IS_ULT(dev))
79935fca 9520 intel_crt_init(dev);
cb0953d7 9521
affa9354 9522 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9523 int found;
9524
9525 /* Haswell uses DDI functions to detect digital outputs */
9526 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9527 /* DDI A only supports eDP */
9528 if (found)
9529 intel_ddi_init(dev, PORT_A);
9530
9531 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9532 * register */
9533 found = I915_READ(SFUSE_STRAP);
9534
9535 if (found & SFUSE_STRAP_DDIB_DETECTED)
9536 intel_ddi_init(dev, PORT_B);
9537 if (found & SFUSE_STRAP_DDIC_DETECTED)
9538 intel_ddi_init(dev, PORT_C);
9539 if (found & SFUSE_STRAP_DDID_DETECTED)
9540 intel_ddi_init(dev, PORT_D);
9541 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9542 int found;
270b3042
DV		 9543 dpd_is_edp = intel_dpd_is_edp(dev);
9544
9545 if (has_edp_a(dev))
9546 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9547
dc0fa718 9548 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9549 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9550 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9551 if (!found)
e2debe91 9552 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9553 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9554 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9555 }
9556
dc0fa718 9557 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9558 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9559
dc0fa718 9560 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9561 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9562
5eb08b69 9563 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9564 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9565
270b3042 9566 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9567 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9568 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9569 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9570 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9571 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9572 PORT_C);
9573 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9574 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9575 PORT_C);
9576 }
19c03924 9577
dc0fa718 9578 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9579 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9580 PORT_B);
67cfc203
VS		 9581 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9582 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9583 }
103a196f 9584 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9585 bool found = false;
7d57382e 9586
e2debe91 9587 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9588 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9589 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9590 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9591 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9592 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9593 }
27185ae1 9594
e7281eab 9595 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9596 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9597 }
13520b05
KH		 9598
9599 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9600
e2debe91 9601 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9602 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9603 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9604 }
27185ae1 9605
e2debe91 9606 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9607
b01f2c3a
JB		 9608 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9609 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9610 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9611 }
e7281eab 9612 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9613 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9614 }
27185ae1 9615
b01f2c3a 9616 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9617 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9618 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9619 } else if (IS_GEN2(dev))
79e53945
JB		 9620 intel_dvo_init(dev);
9621
103a196f 9622 if (SUPPORTS_TV(dev))
79e53945
JB		 9623 intel_tv_init(dev);
9624
4ef69c7a
CW		 9625 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9626 encoder->base.possible_crtcs = encoder->crtc_mask;
9627 encoder->base.possible_clones =
66a9278e 9628 intel_encoder_clones(encoder);
79e53945 9629 }
47356eb6 9630
dde86e2d 9631 intel_init_pch_refclk(dev);
270b3042
DV		 9632
9633 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9634}
9635
ddfe1567
CW		 9636void intel_framebuffer_fini(struct intel_framebuffer *fb)
9637{
9638 drm_framebuffer_cleanup(&fb->base);
9639 drm_gem_object_unreference_unlocked(&fb->obj->base);
9640}
9641
79e53945
JB		 9642static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9643{
9644 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9645
ddfe1567 9646 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9647 kfree(intel_fb);
9648}
9649
9650static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9651 struct drm_file *file,
79e53945
JB		 9652 unsigned int *handle)
9653{
9654 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9655 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9656
05394f39 9657 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9658}
9659
9660static const struct drm_framebuffer_funcs intel_fb_funcs = {
9661 .destroy = intel_user_framebuffer_destroy,
9662 .create_handle = intel_user_framebuffer_create_handle,
9663};
9664
38651674
DA		 9665int intel_framebuffer_init(struct drm_device *dev,
9666 struct intel_framebuffer *intel_fb,
308e5bcb 9667 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9668 struct drm_i915_gem_object *obj)
79e53945 9669{
a35cdaa0 9670 int pitch_limit;
79e53945
JB		 9671 int ret;
9672
c16ed4be
CW		 9673 if (obj->tiling_mode == I915_TILING_Y) {
9674 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9675 return -EINVAL;
c16ed4be 9676 }
57cd6508 9677
c16ed4be
CW		 9678 if (mode_cmd->pitches[0] & 63) {
9679 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9680 mode_cmd->pitches[0]);
57cd6508 9681 return -EINVAL;
c16ed4be 9682 }
57cd6508 9683
a35cdaa0
CW		 9684 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9685 pitch_limit = 32*1024;
9686 } else if (INTEL_INFO(dev)->gen >= 4) {
9687 if (obj->tiling_mode)
9688 pitch_limit = 16*1024;
9689 else
9690 pitch_limit = 32*1024;
9691 } else if (INTEL_INFO(dev)->gen >= 3) {
9692 if (obj->tiling_mode)
9693 pitch_limit = 8*1024;
9694 else
9695 pitch_limit = 16*1024;
9696 } else
9697 /* XXX DSPC is limited to 4k tiled */
9698 pitch_limit = 8*1024;
9699
9700 if (mode_cmd->pitches[0] > pitch_limit) {
9701 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9702 obj->tiling_mode ? "tiled" : "linear",
9703 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9704 return -EINVAL;
c16ed4be 9705 }
5d7bd705
VS		 9706
9707 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9708 mode_cmd->pitches[0] != obj->stride) {
9709 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9710 mode_cmd->pitches[0], obj->stride);
5d7bd705 9711 return -EINVAL;
c16ed4be 9712 }
5d7bd705 9713
57779d06 9714 /* Reject formats not supported by any plane early. */
308e5bcb 9715 switch (mode_cmd->pixel_format) {
57779d06 9716 case DRM_FORMAT_C8:
04b3924d
VS		 9717 case DRM_FORMAT_RGB565:
9718 case DRM_FORMAT_XRGB8888:
9719 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9720 break;
9721 case DRM_FORMAT_XRGB1555:
9722 case DRM_FORMAT_ARGB1555:
c16ed4be 9723 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9724 DRM_DEBUG("unsupported pixel format: %s\n",
9725 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9726 return -EINVAL;
c16ed4be 9727 }
57779d06
VS		 9728 break;
9729 case DRM_FORMAT_XBGR8888:
9730 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9731 case DRM_FORMAT_XRGB2101010:
9732 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9733 case DRM_FORMAT_XBGR2101010:
9734 case DRM_FORMAT_ABGR2101010:
c16ed4be 9735 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9736 DRM_DEBUG("unsupported pixel format: %s\n",
9737 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9738 return -EINVAL;
c16ed4be 9739 }
b5626747 9740 break;
04b3924d
VS		 9741 case DRM_FORMAT_YUYV:
9742 case DRM_FORMAT_UYVY:
9743 case DRM_FORMAT_YVYU:
9744 case DRM_FORMAT_VYUY:
c16ed4be 9745 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9746 DRM_DEBUG("unsupported pixel format: %s\n",
9747 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9748 return -EINVAL;
c16ed4be 9749 }
57cd6508
CW		 9750 break;
9751 default:
4ee62c76
VS		 9752 DRM_DEBUG("unsupported pixel format: %s\n",
9753 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9754 return -EINVAL;
9755 }
9756
90f9a336
VS		 9757 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9758 if (mode_cmd->offsets[0] != 0)
9759 return -EINVAL;
9760
c7d73f6a
DV		 9761 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9762 intel_fb->obj = obj;
9763
79e53945
JB		 9764 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9765 if (ret) {
9766 DRM_ERROR("framebuffer init failed %d\n", ret);
9767 return ret;
9768 }
9769
79e53945
JB		 9770 return 0;
9771}
9772
79e53945
JB		 9773static struct drm_framebuffer *
9774intel_user_framebuffer_create(struct drm_device *dev,
9775 struct drm_file *filp,
308e5bcb 9776 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9777{
05394f39 9778 struct drm_i915_gem_object *obj;
79e53945 9779
308e5bcb
JB		 9780 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9781 mode_cmd->handles[0]));
c8725226 9782 if (&obj->base == NULL)
cce13ff7 9783 return ERR_PTR(-ENOENT);
79e53945 9784
d2dff872 9785 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9786}
9787
79e53945 9788static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9789 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9790 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9791};
9792
e70236a8
JB		 9793/* Set up chip specific display functions */
9794static void intel_init_display(struct drm_device *dev)
9795{
9796 struct drm_i915_private *dev_priv = dev->dev_private;
9797
ee9300bb
DV		 9798 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9799 dev_priv->display.find_dpll = g4x_find_best_dpll;
9800 else if (IS_VALLEYVIEW(dev))
9801 dev_priv->display.find_dpll = vlv_find_best_dpll;
9802 else if (IS_PINEVIEW(dev))
9803 dev_priv->display.find_dpll = pnv_find_best_dpll;
9804 else
9805 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9806
affa9354 9807 if (HAS_DDI(dev)) {
0e8ffe1b 9808 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9809 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9810 dev_priv->display.crtc_enable = haswell_crtc_enable;
9811 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9812 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9813 dev_priv->display.update_plane = ironlake_update_plane;
9814 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9815 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9816 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9817 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9818 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9819 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9820 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9821 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9822 } else if (IS_VALLEYVIEW(dev)) {
9823 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9824 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9825 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9826 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9827 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9828 dev_priv->display.off = i9xx_crtc_off;
9829 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9830 } else {
0e8ffe1b 9831 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9832 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9833 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9834 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9835 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9836 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9837 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9838 }
e70236a8 9839
e70236a8 9840 /* Returns the core display clock speed */
25eb05fc
JB		 9841 if (IS_VALLEYVIEW(dev))
9842 dev_priv->display.get_display_clock_speed =
9843 valleyview_get_display_clock_speed;
9844 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9845 dev_priv->display.get_display_clock_speed =
9846 i945_get_display_clock_speed;
9847 else if (IS_I915G(dev))
9848 dev_priv->display.get_display_clock_speed =
9849 i915_get_display_clock_speed;
257a7ffc 9850 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9851 dev_priv->display.get_display_clock_speed =
9852 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9853 else if (IS_PINEVIEW(dev))
9854 dev_priv->display.get_display_clock_speed =
9855 pnv_get_display_clock_speed;
e70236a8
JB		 9856 else if (IS_I915GM(dev))
9857 dev_priv->display.get_display_clock_speed =
9858 i915gm_get_display_clock_speed;
9859 else if (IS_I865G(dev))
9860 dev_priv->display.get_display_clock_speed =
9861 i865_get_display_clock_speed;
f0f8a9ce 9862 else if (IS_I85X(dev))
e70236a8
JB		 9863 dev_priv->display.get_display_clock_speed =
9864 i855_get_display_clock_speed;
9865 else /* 852, 830 */
9866 dev_priv->display.get_display_clock_speed =
9867 i830_get_display_clock_speed;
9868
7f8a8569 9869 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9870 if (IS_GEN5(dev)) {
674cf967 9871 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9872 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9873 } else if (IS_GEN6(dev)) {
674cf967 9874 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9875 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9876 } else if (IS_IVYBRIDGE(dev)) {
9877 /* FIXME: detect B0+ stepping and use auto training */
9878 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9879 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9880 dev_priv->display.modeset_global_resources =
9881 ivb_modeset_global_resources;
c82e4d26
ED		 9882 } else if (IS_HASWELL(dev)) {
9883 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9884 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9885 dev_priv->display.modeset_global_resources =
9886 haswell_modeset_global_resources;
a0e63c22 9887 }
6067aaea 9888 } else if (IS_G4X(dev)) {
e0dac65e 9889 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9890 }
8c9f3aaf
JB		 9891
9892 /* Default just returns -ENODEV to indicate unsupported */
9893 dev_priv->display.queue_flip = intel_default_queue_flip;
9894
9895 switch (INTEL_INFO(dev)->gen) {
9896 case 2:
9897 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9898 break;
9899
9900 case 3:
9901 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9902 break;
9903
9904 case 4:
9905 case 5:
9906 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9907 break;
9908
9909 case 6:
9910 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9911 break;
7c9017e5
JB		 9912 case 7:
9913 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9914 break;
8c9f3aaf 9915 }
e70236a8
JB		 9916}
9917
b690e96c
JB		 9918/*
9919 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9920 * resume, or other times. This quirk makes sure that's the case for
9921 * affected systems.
9922 */
0206e353 9923static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9924{
9925 struct drm_i915_private *dev_priv = dev->dev_private;
9926
9927 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9928 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9929}
9930
435793df
KP		 9931/*
9932 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9933 */
9934static void quirk_ssc_force_disable(struct drm_device *dev)
9935{
9936 struct drm_i915_private *dev_priv = dev->dev_private;
9937 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9938 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9939}
9940
4dca20ef 9941/*
5a15ab5b
CE		 9942 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9943 * brightness value
4dca20ef
CE		 9944 */
9945static void quirk_invert_brightness(struct drm_device *dev)
9946{
9947 struct drm_i915_private *dev_priv = dev->dev_private;
9948 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9949 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9950}
9951
e85843be
KM		 9952/*
9953 * Some machines (Dell XPS13) suffer broken backlight controls if
9954 * BLM_PCH_PWM_ENABLE is set.
9955 */
9956static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9957{
9958 struct drm_i915_private *dev_priv = dev->dev_private;
9959 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9960 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9961}
9962
b690e96c
JB		 9963struct intel_quirk {
9964 int device;
9965 int subsystem_vendor;
9966 int subsystem_device;
9967 void (*hook)(struct drm_device *dev);
9968};
9969
5f85f176
EE		 9970/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9971struct intel_dmi_quirk {
9972 void (*hook)(struct drm_device *dev);
9973 const struct dmi_system_id (*dmi_id_list)[];
9974};
9975
9976static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9977{
9978 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9979 return 1;
9980}
9981
9982static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9983 {
9984 .dmi_id_list = &(const struct dmi_system_id[]) {
9985 {
9986 .callback = intel_dmi_reverse_brightness,
9987 .ident = "NCR Corporation",
9988 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9989 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9990 },
9991 },
9992 { } /* terminating entry */
9993 },
9994 .hook = quirk_invert_brightness,
9995 },
9996};
9997
c43b5634 9998static struct intel_quirk intel_quirks[] = {
b690e96c 9999 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10000 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10001
b690e96c
JB		 10002 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10003 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10004
b690e96c
JB		 10005 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10006 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10007
ccd0d36e 10008 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10009 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10010 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10011
10012 /* Lenovo U160 cannot use SSC on LVDS */
10013 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10014
10015 /* Sony Vaio Y cannot use SSC on LVDS */
10016 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10017
10018 /* Acer Aspire 5734Z must invert backlight brightness */
10019 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10020
10021 /* Acer/eMachines G725 */
10022 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10023
10024 /* Acer/eMachines e725 */
10025 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10026
10027 /* Acer/Packard Bell NCL20 */
10028 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10029
10030 /* Acer Aspire 4736Z */
10031 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10032
10033 /* Dell XPS13 HD Sandy Bridge */
10034 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10035 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10036 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10037};
10038
10039static void intel_init_quirks(struct drm_device *dev)
10040{
10041 struct pci_dev *d = dev->pdev;
10042 int i;
10043
10044 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10045 struct intel_quirk *q = &intel_quirks[i];
10046
10047 if (d->device == q->device &&
10048 (d->subsystem_vendor == q->subsystem_vendor ||
10049 q->subsystem_vendor == PCI_ANY_ID) &&
10050 (d->subsystem_device == q->subsystem_device ||
10051 q->subsystem_device == PCI_ANY_ID))
10052 q->hook(dev);
10053 }
5f85f176
EE		 10054 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10055 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10056 intel_dmi_quirks[i].hook(dev);
10057 }
b690e96c
JB		 10058}
10059
9cce37f4
JB		 10060/* Disable the VGA plane that we never use */
10061static void i915_disable_vga(struct drm_device *dev)
10062{
10063 struct drm_i915_private *dev_priv = dev->dev_private;
10064 u8 sr1;
766aa1c4 10065 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10066
10067 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10068 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10069 sr1 = inb(VGA_SR_DATA);
10070 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10071
10072 /* Disable VGA memory on Intel HD */
10073 if (HAS_PCH_SPLIT(dev)) {
10074 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10075 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10076 VGA_RSRC_NORMAL_IO |
10077 VGA_RSRC_NORMAL_MEM);
10078 }
10079
9cce37f4
JB		 10080 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10081 udelay(300);
10082
10083 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10084 POSTING_READ(vga_reg);
10085}
10086
81b5c7bc
AW		 10087static void i915_enable_vga(struct drm_device *dev)
10088{
10089 /* Enable VGA memory on Intel HD */
10090 if (HAS_PCH_SPLIT(dev)) {
10091 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10092 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10093 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10094 VGA_RSRC_LEGACY_MEM |
10095 VGA_RSRC_NORMAL_IO |
10096 VGA_RSRC_NORMAL_MEM);
10097 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10098 }
10099}
10100
f817586c
DV		 10101void intel_modeset_init_hw(struct drm_device *dev)
10102{
fa42e23c 10103 intel_init_power_well(dev);
0232e927 10104
a8f78b58
ED		 10105 intel_prepare_ddi(dev);
10106
f817586c
DV		 10107 intel_init_clock_gating(dev);
10108
79f5b2c7 10109 mutex_lock(&dev->struct_mutex);
8090c6b9 10110 intel_enable_gt_powersave(dev);
79f5b2c7 10111 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10112}
10113
7d708ee4
ID		 10114void intel_modeset_suspend_hw(struct drm_device *dev)
10115{
10116 intel_suspend_hw(dev);
10117}
10118
79e53945
JB		 10119void intel_modeset_init(struct drm_device *dev)
10120{
652c393a 10121 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10122 int i, j, ret;
79e53945
JB		 10123
10124 drm_mode_config_init(dev);
10125
10126 dev->mode_config.min_width = 0;
10127 dev->mode_config.min_height = 0;
10128
019d96cb
DA		 10129 dev->mode_config.preferred_depth = 24;
10130 dev->mode_config.prefer_shadow = 1;
10131
e6ecefaa 10132 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10133
b690e96c
JB		 10134 intel_init_quirks(dev);
10135
1fa61106
ED		 10136 intel_init_pm(dev);
10137
e3c74757
BW		 10138 if (INTEL_INFO(dev)->num_pipes == 0)
10139 return;
10140
e70236a8
JB		 10141 intel_init_display(dev);
10142
a6c45cf0
CW		 10143 if (IS_GEN2(dev)) {
10144 dev->mode_config.max_width = 2048;
10145 dev->mode_config.max_height = 2048;
10146 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10147 dev->mode_config.max_width = 4096;
10148 dev->mode_config.max_height = 4096;
79e53945 10149 } else {
a6c45cf0
CW		 10150 dev->mode_config.max_width = 8192;
10151 dev->mode_config.max_height = 8192;
79e53945 10152 }
5d4545ae 10153 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10154
28c97730 10155 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10156 INTEL_INFO(dev)->num_pipes,
10157 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10158
08e2a7de 10159 for_each_pipe(i) {
79e53945 10160 intel_crtc_init(dev, i);
7f1f3851
JB		 10161 for (j = 0; j < dev_priv->num_plane; j++) {
10162 ret = intel_plane_init(dev, i, j);
10163 if (ret)
06da8da2
VS		 10164 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10165 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10166 }
79e53945
JB		 10167 }
10168
79f689aa 10169 intel_cpu_pll_init(dev);
e72f9fbf 10170 intel_shared_dpll_init(dev);
ee7b9f93 10171
9cce37f4
JB		 10172 /* Just disable it once at startup */
10173 i915_disable_vga(dev);
79e53945 10174 intel_setup_outputs(dev);
11be49eb
CW		 10175
10176 /* Just in case the BIOS is doing something questionable. */
10177 intel_disable_fbc(dev);
2c7111db
CW		 10178}
10179
24929352
DV		 10180static void
10181intel_connector_break_all_links(struct intel_connector *connector)
10182{
10183 connector->base.dpms = DRM_MODE_DPMS_OFF;
10184 connector->base.encoder = NULL;
10185 connector->encoder->connectors_active = false;
10186 connector->encoder->base.crtc = NULL;
10187}
10188
7fad798e
DV		 10189static void intel_enable_pipe_a(struct drm_device *dev)
10190{
10191 struct intel_connector *connector;
10192 struct drm_connector *crt = NULL;
10193 struct intel_load_detect_pipe load_detect_temp;
10194
10195 /* We can't just switch on the pipe A, we need to set things up with a
10196 * proper mode and output configuration. As a gross hack, enable pipe A
10197 * by enabling the load detect pipe once. */
10198 list_for_each_entry(connector,
10199 &dev->mode_config.connector_list,
10200 base.head) {
10201 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10202 crt = &connector->base;
10203 break;
10204 }
10205 }
10206
10207 if (!crt)
10208 return;
10209
10210 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10211 intel_release_load_detect_pipe(crt, &load_detect_temp);
10212
652c393a 10213
7fad798e
DV		 10214}
10215
fa555837
DV		 10216static bool
10217intel_check_plane_mapping(struct intel_crtc *crtc)
10218{
7eb552ae
BW		 10219 struct drm_device *dev = crtc->base.dev;
10220 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10221 u32 reg, val;
10222
7eb552ae 10223 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10224 return true;
10225
10226 reg = DSPCNTR(!crtc->plane);
10227 val = I915_READ(reg);
10228
10229 if ((val & DISPLAY_PLANE_ENABLE) &&
10230 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10231 return false;
10232
10233 return true;
10234}
10235
24929352
DV		 10236static void intel_sanitize_crtc(struct intel_crtc *crtc)
10237{
10238 struct drm_device *dev = crtc->base.dev;
10239 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10240 u32 reg;
24929352 10241
24929352 10242 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10243 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10244 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10245
10246 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10247 * disable the crtc (and hence change the state) if it is wrong. Note
10248 * that gen4+ has a fixed plane -> pipe mapping. */
10249 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10250 struct intel_connector *connector;
10251 bool plane;
10252
24929352
DV		 10253 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10254 crtc->base.base.id);
10255
10256 /* Pipe has the wrong plane attached and the plane is active.
10257 * Temporarily change the plane mapping and disable everything
10258 * ... */
10259 plane = crtc->plane;
10260 crtc->plane = !plane;
10261 dev_priv->display.crtc_disable(&crtc->base);
10262 crtc->plane = plane;
10263
10264 /* ... and break all links. */
10265 list_for_each_entry(connector, &dev->mode_config.connector_list,
10266 base.head) {
10267 if (connector->encoder->base.crtc != &crtc->base)
10268 continue;
10269
10270 intel_connector_break_all_links(connector);
10271 }
10272
10273 WARN_ON(crtc->active);
10274 crtc->base.enabled = false;
10275 }
24929352 10276
7fad798e
DV		 10277 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10278 crtc->pipe == PIPE_A && !crtc->active) {
10279 /* BIOS forgot to enable pipe A, this mostly happens after
10280 * resume. Force-enable the pipe to fix this, the update_dpms
10281 * call below we restore the pipe to the right state, but leave
10282 * the required bits on. */
10283 intel_enable_pipe_a(dev);
10284 }
10285
24929352
DV		 10286 /* Adjust the state of the output pipe according to whether we
10287 * have active connectors/encoders. */
10288 intel_crtc_update_dpms(&crtc->base);
10289
10290 if (crtc->active != crtc->base.enabled) {
10291 struct intel_encoder *encoder;
10292
10293 /* This can happen either due to bugs in the get_hw_state
10294 * functions or because the pipe is force-enabled due to the
10295 * pipe A quirk. */
10296 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10297 crtc->base.base.id,
10298 crtc->base.enabled ? "enabled" : "disabled",
10299 crtc->active ? "enabled" : "disabled");
10300
10301 crtc->base.enabled = crtc->active;
10302
10303 /* Because we only establish the connector -> encoder ->
10304 * crtc links if something is active, this means the
10305 * crtc is now deactivated. Break the links. connector
10306 * -> encoder links are only establish when things are
10307 * actually up, hence no need to break them. */
10308 WARN_ON(crtc->active);
10309
10310 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10311 WARN_ON(encoder->connectors_active);
10312 encoder->base.crtc = NULL;
10313 }
10314 }
10315}
10316
10317static void intel_sanitize_encoder(struct intel_encoder *encoder)
10318{
10319 struct intel_connector *connector;
10320 struct drm_device *dev = encoder->base.dev;
10321
10322 /* We need to check both for a crtc link (meaning that the
10323 * encoder is active and trying to read from a pipe) and the
10324 * pipe itself being active. */
10325 bool has_active_crtc = encoder->base.crtc &&
10326 to_intel_crtc(encoder->base.crtc)->active;
10327
10328 if (encoder->connectors_active && !has_active_crtc) {
10329 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10330 encoder->base.base.id,
10331 drm_get_encoder_name(&encoder->base));
10332
10333 /* Connector is active, but has no active pipe. This is
10334 * fallout from our resume register restoring. Disable
10335 * the encoder manually again. */
10336 if (encoder->base.crtc) {
10337 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10338 encoder->base.base.id,
10339 drm_get_encoder_name(&encoder->base));
10340 encoder->disable(encoder);
10341 }
10342
10343 /* Inconsistent output/port/pipe state happens presumably due to
10344 * a bug in one of the get_hw_state functions. Or someplace else
10345 * in our code, like the register restore mess on resume. Clamp
10346 * things to off as a safer default. */
10347 list_for_each_entry(connector,
10348 &dev->mode_config.connector_list,
10349 base.head) {
10350 if (connector->encoder != encoder)
10351 continue;
10352
10353 intel_connector_break_all_links(connector);
10354 }
10355 }
10356 /* Enabled encoders without active connectors will be fixed in
10357 * the crtc fixup. */
10358}
10359
44cec740 10360void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10361{
10362 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10363 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10364
8dc8a27c
PZ		 10365 /* This function can be called both from intel_modeset_setup_hw_state or
10366 * at a very early point in our resume sequence, where the power well
10367 * structures are not yet restored. Since this function is at a very
10368 * paranoid "someone might have enabled VGA while we were not looking"
10369 * level, just check if the power well is enabled instead of trying to
10370 * follow the "don't touch the power well if we don't need it" policy
10371 * the rest of the driver uses. */
10372 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10373 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10374 return;
10375
0fde901f
KM		 10376 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10377 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10378 i915_disable_vga(dev);
0fde901f
KM		 10379 }
10380}
10381
30e984df 10382static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10383{
10384 struct drm_i915_private *dev_priv = dev->dev_private;
10385 enum pipe pipe;
24929352
DV		 10386 struct intel_crtc *crtc;
10387 struct intel_encoder *encoder;
10388 struct intel_connector *connector;
5358901f 10389 int i;
24929352 10390
0e8ffe1b
DV		 10391 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10392 base.head) {
88adfff1 10393 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10394
0e8ffe1b
DV		 10395 crtc->active = dev_priv->display.get_pipe_config(crtc,
10396 &crtc->config);
24929352
DV		 10397
10398 crtc->base.enabled = crtc->active;
10399
10400 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10401 crtc->base.base.id,
10402 crtc->active ? "enabled" : "disabled");
10403 }
10404
5358901f 10405 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10406 if (HAS_DDI(dev))
6441ab5f
PZ		 10407 intel_ddi_setup_hw_pll_state(dev);
10408
5358901f
DV		 10409 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10410 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10411
10412 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10413 pll->active = 0;
10414 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10415 base.head) {
10416 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10417 pll->active++;
10418 }
10419 pll->refcount = pll->active;
10420
35c95375
DV		 10421 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10422 pll->name, pll->refcount, pll->on);
5358901f
DV		 10423 }
10424
24929352
DV		 10425 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10426 base.head) {
10427 pipe = 0;
10428
10429 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10430 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10431 encoder->base.crtc = &crtc->base;
510d5f2f 10432 if (encoder->get_config)
045ac3b5 10433 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10434 } else {
10435 encoder->base.crtc = NULL;
10436 }
10437
10438 encoder->connectors_active = false;
10439 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10440 encoder->base.base.id,
10441 drm_get_encoder_name(&encoder->base),
10442 encoder->base.crtc ? "enabled" : "disabled",
10443 pipe);
10444 }
10445
510d5f2f
JB		 10446 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10447 base.head) {
10448 if (!crtc->active)
10449 continue;
10450 if (dev_priv->display.get_clock)
10451 dev_priv->display.get_clock(crtc,
10452 &crtc->config);
10453 }
10454
24929352
DV		 10455 list_for_each_entry(connector, &dev->mode_config.connector_list,
10456 base.head) {
10457 if (connector->get_hw_state(connector)) {
10458 connector->base.dpms = DRM_MODE_DPMS_ON;
10459 connector->encoder->connectors_active = true;
10460 connector->base.encoder = &connector->encoder->base;
10461 } else {
10462 connector->base.dpms = DRM_MODE_DPMS_OFF;
10463 connector->base.encoder = NULL;
10464 }
10465 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10466 connector->base.base.id,
10467 drm_get_connector_name(&connector->base),
10468 connector->base.encoder ? "enabled" : "disabled");
10469 }
30e984df
DV		 10470}
10471
10472/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10473 * and i915 state tracking structures. */
10474void intel_modeset_setup_hw_state(struct drm_device *dev,
10475 bool force_restore)
10476{
10477 struct drm_i915_private *dev_priv = dev->dev_private;
10478 enum pipe pipe;
10479 struct drm_plane *plane;
10480 struct intel_crtc *crtc;
10481 struct intel_encoder *encoder;
35c95375 10482 int i;
30e984df
DV		 10483
10484 intel_modeset_readout_hw_state(dev);
24929352 10485
babea61d
JB		 10486 /*
10487 * Now that we have the config, copy it to each CRTC struct
10488 * Note that this could go away if we move to using crtc_config
10489 * checking everywhere.
10490 */
10491 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10492 base.head) {
10493 if (crtc->active && i915_fastboot) {
10494 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10495
10496 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10497 crtc->base.base.id);
10498 drm_mode_debug_printmodeline(&crtc->base.mode);
10499 }
10500 }
10501
24929352
DV		 10502 /* HW state is read out, now we need to sanitize this mess. */
10503 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10504 base.head) {
10505 intel_sanitize_encoder(encoder);
10506 }
10507
10508 for_each_pipe(pipe) {
10509 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10510 intel_sanitize_crtc(crtc);
c0b03411 10511 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10512 }
9a935856 10513
35c95375
DV		 10514 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10515 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10516
10517 if (!pll->on || pll->active)
10518 continue;
10519
10520 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10521
10522 pll->disable(dev_priv, pll);
10523 pll->on = false;
10524 }
10525
45e2b5f6 10526 if (force_restore) {
f30da187
DV		 10527 /*
10528 * We need to use raw interfaces for restoring state to avoid
10529 * checking (bogus) intermediate states.
10530 */
45e2b5f6 10531 for_each_pipe(pipe) {
b5644d05
JB		 10532 struct drm_crtc *crtc =
10533 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10534
10535 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10536 crtc->fb);
45e2b5f6 10537 }
b5644d05
JB		 10538 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10539 intel_plane_restore(plane);
0fde901f
KM		 10540
10541 i915_redisable_vga(dev);
45e2b5f6
DV		 10542 } else {
10543 intel_modeset_update_staged_output_state(dev);
10544 }
8af6cf88
DV		 10545
10546 intel_modeset_check_state(dev);
2e938892
DV		 10547
10548 drm_mode_config_reset(dev);
2c7111db
CW		 10549}
10550
10551void intel_modeset_gem_init(struct drm_device *dev)
10552{
1833b134 10553 intel_modeset_init_hw(dev);
02e792fb
DV		 10554
10555 intel_setup_overlay(dev);
24929352 10556
45e2b5f6 10557 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10558}
10559
10560void intel_modeset_cleanup(struct drm_device *dev)
10561{
652c393a
JB		 10562 struct drm_i915_private *dev_priv = dev->dev_private;
10563 struct drm_crtc *crtc;
652c393a 10564
fd0c0642
DV		 10565 /*
10566 * Interrupts and polling as the first thing to avoid creating havoc.
10567 * Too much stuff here (turning of rps, connectors, ...) would
10568 * experience fancy races otherwise.
10569 */
10570 drm_irq_uninstall(dev);
10571 cancel_work_sync(&dev_priv->hotplug_work);
10572 /*
10573 * Due to the hpd irq storm handling the hotplug work can re-arm the
10574 * poll handlers. Hence disable polling after hpd handling is shut down.
10575 */
f87ea761 10576 drm_kms_helper_poll_fini(dev);
fd0c0642 10577
652c393a
JB		 10578 mutex_lock(&dev->struct_mutex);
10579
723bfd70
JB		 10580 intel_unregister_dsm_handler();
10581
652c393a
JB		 10582 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10583 /* Skip inactive CRTCs */
10584 if (!crtc->fb)
10585 continue;
10586
3dec0095 10587 intel_increase_pllclock(crtc);
652c393a
JB		 10588 }
10589
973d04f9 10590 intel_disable_fbc(dev);
e70236a8 10591
81b5c7bc
AW		 10592 i915_enable_vga(dev);
10593
8090c6b9 10594 intel_disable_gt_powersave(dev);
0cdab21f 10595
930ebb46
DV		 10596 ironlake_teardown_rc6(dev);
10597
69341a5e
KH		 10598 mutex_unlock(&dev->struct_mutex);
10599
1630fe75
CW		 10600 /* flush any delayed tasks or pending work */
10601 flush_scheduled_work();
10602
dc652f90
JN		 10603 /* destroy backlight, if any, before the connectors */
10604 intel_panel_destroy_backlight(dev);
10605
79e53945 10606 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10607
10608 intel_cleanup_overlay(dev);
79e53945
JB		 10609}
10610
f1c79df3
ZW		 10611/*
10612 * Return which encoder is currently attached for connector.
10613 */
df0e9248 10614struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10615{
df0e9248
CW		 10616 return &intel_attached_encoder(connector)->base;
10617}
f1c79df3 10618
df0e9248
CW		 10619void intel_connector_attach_encoder(struct intel_connector *connector,
10620 struct intel_encoder *encoder)
10621{
10622 connector->encoder = encoder;
10623 drm_mode_connector_attach_encoder(&connector->base,
10624 &encoder->base);
79e53945 10625}
28d52043
DA		 10626
10627/*
10628 * set vga decode state - true == enable VGA decode
10629 */
10630int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10631{
10632 struct drm_i915_private *dev_priv = dev->dev_private;
10633 u16 gmch_ctrl;
10634
10635 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10636 if (state)
10637 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10638 else
10639 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10640 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10641 return 0;
10642}
c4a1d9e4 10643
c4a1d9e4 10644struct intel_display_error_state {
ff57f1b0
PZ		 10645
10646 u32 power_well_driver;
10647
63b66e5b
CW		 10648 int num_transcoders;
10649
c4a1d9e4
CW		 10650 struct intel_cursor_error_state {
10651 u32 control;
10652 u32 position;
10653 u32 base;
10654 u32 size;
52331309 10655 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10656
10657 struct intel_pipe_error_state {
c4a1d9e4 10658 u32 source;
52331309 10659 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10660
10661 struct intel_plane_error_state {
10662 u32 control;
10663 u32 stride;
10664 u32 size;
10665 u32 pos;
10666 u32 addr;
10667 u32 surface;
10668 u32 tile_offset;
52331309 10669 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10670
10671 struct intel_transcoder_error_state {
10672 enum transcoder cpu_transcoder;
10673
10674 u32 conf;
10675
10676 u32 htotal;
10677 u32 hblank;
10678 u32 hsync;
10679 u32 vtotal;
10680 u32 vblank;
10681 u32 vsync;
10682 } transcoder[4];
c4a1d9e4
CW		 10683};
10684
10685struct intel_display_error_state *
10686intel_display_capture_error_state(struct drm_device *dev)
10687{
0206e353 10688 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10689 struct intel_display_error_state *error;
63b66e5b
CW		 10690 int transcoders[] = {
10691 TRANSCODER_A,
10692 TRANSCODER_B,
10693 TRANSCODER_C,
10694 TRANSCODER_EDP,
10695 };
c4a1d9e4
CW		 10696 int i;
10697
63b66e5b
CW		 10698 if (INTEL_INFO(dev)->num_pipes == 0)
10699 return NULL;
10700
c4a1d9e4
CW		 10701 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10702 if (error == NULL)
10703 return NULL;
10704
ff57f1b0
PZ		 10705 if (HAS_POWER_WELL(dev))
10706 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10707
52331309 10708 for_each_pipe(i) {
a18c4c3d
PZ		 10709 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10710 error->cursor[i].control = I915_READ(CURCNTR(i));
10711 error->cursor[i].position = I915_READ(CURPOS(i));
10712 error->cursor[i].base = I915_READ(CURBASE(i));
10713 } else {
10714 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10715 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10716 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10717 }
c4a1d9e4
CW		 10718
10719 error->plane[i].control = I915_READ(DSPCNTR(i));
10720 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10721 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10722 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10723 error->plane[i].pos = I915_READ(DSPPOS(i));
10724 }
ca291363
PZ		 10725 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10726 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10727 if (INTEL_INFO(dev)->gen >= 4) {
10728 error->plane[i].surface = I915_READ(DSPSURF(i));
10729 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10730 }
10731
c4a1d9e4 10732 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10733 }
10734
10735 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10736 if (HAS_DDI(dev_priv->dev))
10737 error->num_transcoders++; /* Account for eDP. */
10738
10739 for (i = 0; i < error->num_transcoders; i++) {
10740 enum transcoder cpu_transcoder = transcoders[i];
10741
10742 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10743
10744 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10745 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10746 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10747 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10748 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10749 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10750 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10751 }
10752
12d217c7
PZ		 10753 /* In the code above we read the registers without checking if the power
10754 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10755 * prevent the next I915_WRITE from detecting it and printing an error
10756 * message. */
907b28c5 10757 intel_uncore_clear_errors(dev);
12d217c7 10758
c4a1d9e4
CW		 10759 return error;
10760}
10761
edc3d884
MK		 10762#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10763
c4a1d9e4 10764void
edc3d884 10765intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10766 struct drm_device *dev,
10767 struct intel_display_error_state *error)
10768{
10769 int i;
10770
63b66e5b
CW		 10771 if (!error)
10772 return;
10773
edc3d884 10774 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10775 if (HAS_POWER_WELL(dev))
edc3d884 10776 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10777 error->power_well_driver);
52331309 10778 for_each_pipe(i) {
edc3d884 10779 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10780 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10781
10782 err_printf(m, "Plane [%d]:\n", i);
10783 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10784 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10785 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10786 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10787 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10788 }
4b71a570 10789 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10790 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10791 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10792 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10793 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10794 }
10795
edc3d884
MK		 10796 err_printf(m, "Cursor [%d]:\n", i);
10797 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10798 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10799 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10800 }
63b66e5b
CW		 10801
10802 for (i = 0; i < error->num_transcoders; i++) {
10803 err_printf(m, " CPU transcoder: %c\n",
10804 transcoder_name(error->transcoder[i].cpu_transcoder));
10805 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10806 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10807 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10808 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10809 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10810 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10811 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10812 }
c4a1d9e4 10813}
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