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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
ef9348c8 CML |
44 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
45 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) | |
46 | ||
3dec0095 | 47 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 48 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 49 | |
f1f644dc JB |
50 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
51 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
52 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
53 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 54 | |
e7457a9a DL |
55 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
56 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
57 | static int intel_framebuffer_init(struct drm_device *dev, |
58 | struct intel_framebuffer *ifb, | |
59 | struct drm_mode_fb_cmd2 *mode_cmd, | |
60 | struct drm_i915_gem_object *obj); | |
e7457a9a | 61 | |
79e53945 | 62 | typedef struct { |
0206e353 | 63 | int min, max; |
79e53945 JB |
64 | } intel_range_t; |
65 | ||
66 | typedef struct { | |
0206e353 AJ |
67 | int dot_limit; |
68 | int p2_slow, p2_fast; | |
79e53945 JB |
69 | } intel_p2_t; |
70 | ||
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
0206e353 AJ |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 | 75 | }; |
79e53945 | 76 | |
d2acd215 DV |
77 | int |
78 | intel_pch_rawclk(struct drm_device *dev) | |
79 | { | |
80 | struct drm_i915_private *dev_priv = dev->dev_private; | |
81 | ||
82 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
83 | ||
84 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
85 | } | |
86 | ||
021357ac CW |
87 | static inline u32 /* units of 100MHz */ |
88 | intel_fdi_link_freq(struct drm_device *dev) | |
89 | { | |
8b99e68c CW |
90 | if (IS_GEN5(dev)) { |
91 | struct drm_i915_private *dev_priv = dev->dev_private; | |
92 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
93 | } else | |
94 | return 27; | |
021357ac CW |
95 | } |
96 | ||
5d536e28 | 97 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 98 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 99 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 100 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
101 | .m = { .min = 96, .max = 140 }, |
102 | .m1 = { .min = 18, .max = 26 }, | |
103 | .m2 = { .min = 6, .max = 16 }, | |
104 | .p = { .min = 4, .max = 128 }, | |
105 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
106 | .p2 = { .dot_limit = 165000, |
107 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
108 | }; |
109 | ||
5d536e28 DV |
110 | static const intel_limit_t intel_limits_i8xx_dvo = { |
111 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 112 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 113 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
114 | .m = { .min = 96, .max = 140 }, |
115 | .m1 = { .min = 18, .max = 26 }, | |
116 | .m2 = { .min = 6, .max = 16 }, | |
117 | .p = { .min = 4, .max = 128 }, | |
118 | .p1 = { .min = 2, .max = 33 }, | |
119 | .p2 = { .dot_limit = 165000, | |
120 | .p2_slow = 4, .p2_fast = 4 }, | |
121 | }; | |
122 | ||
e4b36699 | 123 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 124 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 125 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 126 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
127 | .m = { .min = 96, .max = 140 }, |
128 | .m1 = { .min = 18, .max = 26 }, | |
129 | .m2 = { .min = 6, .max = 16 }, | |
130 | .p = { .min = 4, .max = 128 }, | |
131 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
132 | .p2 = { .dot_limit = 165000, |
133 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 134 | }; |
273e27ca | 135 | |
e4b36699 | 136 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
137 | .dot = { .min = 20000, .max = 400000 }, |
138 | .vco = { .min = 1400000, .max = 2800000 }, | |
139 | .n = { .min = 1, .max = 6 }, | |
140 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
141 | .m1 = { .min = 8, .max = 18 }, |
142 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
143 | .p = { .min = 5, .max = 80 }, |
144 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
145 | .p2 = { .dot_limit = 200000, |
146 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
147 | }; |
148 | ||
149 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
150 | .dot = { .min = 20000, .max = 400000 }, |
151 | .vco = { .min = 1400000, .max = 2800000 }, | |
152 | .n = { .min = 1, .max = 6 }, | |
153 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
154 | .m1 = { .min = 8, .max = 18 }, |
155 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
156 | .p = { .min = 7, .max = 98 }, |
157 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
158 | .p2 = { .dot_limit = 112000, |
159 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
160 | }; |
161 | ||
273e27ca | 162 | |
e4b36699 | 163 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
164 | .dot = { .min = 25000, .max = 270000 }, |
165 | .vco = { .min = 1750000, .max = 3500000}, | |
166 | .n = { .min = 1, .max = 4 }, | |
167 | .m = { .min = 104, .max = 138 }, | |
168 | .m1 = { .min = 17, .max = 23 }, | |
169 | .m2 = { .min = 5, .max = 11 }, | |
170 | .p = { .min = 10, .max = 30 }, | |
171 | .p1 = { .min = 1, .max = 3}, | |
172 | .p2 = { .dot_limit = 270000, | |
173 | .p2_slow = 10, | |
174 | .p2_fast = 10 | |
044c7c41 | 175 | }, |
e4b36699 KP |
176 | }; |
177 | ||
178 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
179 | .dot = { .min = 22000, .max = 400000 }, |
180 | .vco = { .min = 1750000, .max = 3500000}, | |
181 | .n = { .min = 1, .max = 4 }, | |
182 | .m = { .min = 104, .max = 138 }, | |
183 | .m1 = { .min = 16, .max = 23 }, | |
184 | .m2 = { .min = 5, .max = 11 }, | |
185 | .p = { .min = 5, .max = 80 }, | |
186 | .p1 = { .min = 1, .max = 8}, | |
187 | .p2 = { .dot_limit = 165000, | |
188 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
189 | }; |
190 | ||
191 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
192 | .dot = { .min = 20000, .max = 115000 }, |
193 | .vco = { .min = 1750000, .max = 3500000 }, | |
194 | .n = { .min = 1, .max = 3 }, | |
195 | .m = { .min = 104, .max = 138 }, | |
196 | .m1 = { .min = 17, .max = 23 }, | |
197 | .m2 = { .min = 5, .max = 11 }, | |
198 | .p = { .min = 28, .max = 112 }, | |
199 | .p1 = { .min = 2, .max = 8 }, | |
200 | .p2 = { .dot_limit = 0, | |
201 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 202 | }, |
e4b36699 KP |
203 | }; |
204 | ||
205 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
206 | .dot = { .min = 80000, .max = 224000 }, |
207 | .vco = { .min = 1750000, .max = 3500000 }, | |
208 | .n = { .min = 1, .max = 3 }, | |
209 | .m = { .min = 104, .max = 138 }, | |
210 | .m1 = { .min = 17, .max = 23 }, | |
211 | .m2 = { .min = 5, .max = 11 }, | |
212 | .p = { .min = 14, .max = 42 }, | |
213 | .p1 = { .min = 2, .max = 6 }, | |
214 | .p2 = { .dot_limit = 0, | |
215 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 216 | }, |
e4b36699 KP |
217 | }; |
218 | ||
f2b115e6 | 219 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
220 | .dot = { .min = 20000, .max = 400000}, |
221 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 222 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
223 | .n = { .min = 3, .max = 6 }, |
224 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 225 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
226 | .m1 = { .min = 0, .max = 0 }, |
227 | .m2 = { .min = 0, .max = 254 }, | |
228 | .p = { .min = 5, .max = 80 }, | |
229 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
230 | .p2 = { .dot_limit = 200000, |
231 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
232 | }; |
233 | ||
f2b115e6 | 234 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
235 | .dot = { .min = 20000, .max = 400000 }, |
236 | .vco = { .min = 1700000, .max = 3500000 }, | |
237 | .n = { .min = 3, .max = 6 }, | |
238 | .m = { .min = 2, .max = 256 }, | |
239 | .m1 = { .min = 0, .max = 0 }, | |
240 | .m2 = { .min = 0, .max = 254 }, | |
241 | .p = { .min = 7, .max = 112 }, | |
242 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
243 | .p2 = { .dot_limit = 112000, |
244 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
245 | }; |
246 | ||
273e27ca EA |
247 | /* Ironlake / Sandybridge |
248 | * | |
249 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
250 | * the range value for them is (actual_value - 2). | |
251 | */ | |
b91ad0ec | 252 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
253 | .dot = { .min = 25000, .max = 350000 }, |
254 | .vco = { .min = 1760000, .max = 3510000 }, | |
255 | .n = { .min = 1, .max = 5 }, | |
256 | .m = { .min = 79, .max = 127 }, | |
257 | .m1 = { .min = 12, .max = 22 }, | |
258 | .m2 = { .min = 5, .max = 9 }, | |
259 | .p = { .min = 5, .max = 80 }, | |
260 | .p1 = { .min = 1, .max = 8 }, | |
261 | .p2 = { .dot_limit = 225000, | |
262 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
263 | }; |
264 | ||
b91ad0ec | 265 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
266 | .dot = { .min = 25000, .max = 350000 }, |
267 | .vco = { .min = 1760000, .max = 3510000 }, | |
268 | .n = { .min = 1, .max = 3 }, | |
269 | .m = { .min = 79, .max = 118 }, | |
270 | .m1 = { .min = 12, .max = 22 }, | |
271 | .m2 = { .min = 5, .max = 9 }, | |
272 | .p = { .min = 28, .max = 112 }, | |
273 | .p1 = { .min = 2, .max = 8 }, | |
274 | .p2 = { .dot_limit = 225000, | |
275 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
276 | }; |
277 | ||
278 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
279 | .dot = { .min = 25000, .max = 350000 }, |
280 | .vco = { .min = 1760000, .max = 3510000 }, | |
281 | .n = { .min = 1, .max = 3 }, | |
282 | .m = { .min = 79, .max = 127 }, | |
283 | .m1 = { .min = 12, .max = 22 }, | |
284 | .m2 = { .min = 5, .max = 9 }, | |
285 | .p = { .min = 14, .max = 56 }, | |
286 | .p1 = { .min = 2, .max = 8 }, | |
287 | .p2 = { .dot_limit = 225000, | |
288 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
289 | }; |
290 | ||
273e27ca | 291 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 292 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
293 | .dot = { .min = 25000, .max = 350000 }, |
294 | .vco = { .min = 1760000, .max = 3510000 }, | |
295 | .n = { .min = 1, .max = 2 }, | |
296 | .m = { .min = 79, .max = 126 }, | |
297 | .m1 = { .min = 12, .max = 22 }, | |
298 | .m2 = { .min = 5, .max = 9 }, | |
299 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 300 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
301 | .p2 = { .dot_limit = 225000, |
302 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
303 | }; |
304 | ||
305 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
306 | .dot = { .min = 25000, .max = 350000 }, |
307 | .vco = { .min = 1760000, .max = 3510000 }, | |
308 | .n = { .min = 1, .max = 3 }, | |
309 | .m = { .min = 79, .max = 126 }, | |
310 | .m1 = { .min = 12, .max = 22 }, | |
311 | .m2 = { .min = 5, .max = 9 }, | |
312 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 313 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
314 | .p2 = { .dot_limit = 225000, |
315 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
316 | }; |
317 | ||
dc730512 | 318 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
319 | /* |
320 | * These are the data rate limits (measured in fast clocks) | |
321 | * since those are the strictest limits we have. The fast | |
322 | * clock and actual rate limits are more relaxed, so checking | |
323 | * them would make no difference. | |
324 | */ | |
325 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 326 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 327 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
328 | .m1 = { .min = 2, .max = 3 }, |
329 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 330 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 331 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
332 | }; |
333 | ||
ef9348c8 CML |
334 | static const intel_limit_t intel_limits_chv = { |
335 | /* | |
336 | * These are the data rate limits (measured in fast clocks) | |
337 | * since those are the strictest limits we have. The fast | |
338 | * clock and actual rate limits are more relaxed, so checking | |
339 | * them would make no difference. | |
340 | */ | |
341 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
342 | .vco = { .min = 4860000, .max = 6700000 }, | |
343 | .n = { .min = 1, .max = 1 }, | |
344 | .m1 = { .min = 2, .max = 2 }, | |
345 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
346 | .p1 = { .min = 2, .max = 4 }, | |
347 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
348 | }; | |
349 | ||
6b4bf1c4 VS |
350 | static void vlv_clock(int refclk, intel_clock_t *clock) |
351 | { | |
352 | clock->m = clock->m1 * clock->m2; | |
353 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
354 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
355 | return; | |
fb03ac01 VS |
356 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
357 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
358 | } |
359 | ||
e0638cdf PZ |
360 | /** |
361 | * Returns whether any output on the specified pipe is of the specified type | |
362 | */ | |
363 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
364 | { | |
365 | struct drm_device *dev = crtc->dev; | |
366 | struct intel_encoder *encoder; | |
367 | ||
368 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
369 | if (encoder->type == type) | |
370 | return true; | |
371 | ||
372 | return false; | |
373 | } | |
374 | ||
1b894b59 CW |
375 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
376 | int refclk) | |
2c07245f | 377 | { |
b91ad0ec | 378 | struct drm_device *dev = crtc->dev; |
2c07245f | 379 | const intel_limit_t *limit; |
b91ad0ec ZW |
380 | |
381 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 382 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 383 | if (refclk == 100000) |
b91ad0ec ZW |
384 | limit = &intel_limits_ironlake_dual_lvds_100m; |
385 | else | |
386 | limit = &intel_limits_ironlake_dual_lvds; | |
387 | } else { | |
1b894b59 | 388 | if (refclk == 100000) |
b91ad0ec ZW |
389 | limit = &intel_limits_ironlake_single_lvds_100m; |
390 | else | |
391 | limit = &intel_limits_ironlake_single_lvds; | |
392 | } | |
c6bb3538 | 393 | } else |
b91ad0ec | 394 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
395 | |
396 | return limit; | |
397 | } | |
398 | ||
044c7c41 ML |
399 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
400 | { | |
401 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
402 | const intel_limit_t *limit; |
403 | ||
404 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 405 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 406 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 407 | else |
e4b36699 | 408 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
409 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
410 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 411 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 412 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 413 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 414 | } else /* The option is for other outputs */ |
e4b36699 | 415 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
416 | |
417 | return limit; | |
418 | } | |
419 | ||
1b894b59 | 420 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
421 | { |
422 | struct drm_device *dev = crtc->dev; | |
423 | const intel_limit_t *limit; | |
424 | ||
bad720ff | 425 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 426 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 427 | else if (IS_G4X(dev)) { |
044c7c41 | 428 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 429 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 431 | limit = &intel_limits_pineview_lvds; |
2177832f | 432 | else |
f2b115e6 | 433 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
434 | } else if (IS_CHERRYVIEW(dev)) { |
435 | limit = &intel_limits_chv; | |
a0c4da24 | 436 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 437 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
438 | } else if (!IS_GEN2(dev)) { |
439 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
440 | limit = &intel_limits_i9xx_lvds; | |
441 | else | |
442 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
443 | } else { |
444 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 445 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 446 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 447 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
448 | else |
449 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
450 | } |
451 | return limit; | |
452 | } | |
453 | ||
f2b115e6 AJ |
454 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
455 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 456 | { |
2177832f SL |
457 | clock->m = clock->m2 + 2; |
458 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
459 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
460 | return; | |
fb03ac01 VS |
461 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
462 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
463 | } |
464 | ||
7429e9d4 DV |
465 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
466 | { | |
467 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
468 | } | |
469 | ||
ac58c3f0 | 470 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 471 | { |
7429e9d4 | 472 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 473 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
474 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
475 | return; | |
fb03ac01 VS |
476 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
477 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
478 | } |
479 | ||
ef9348c8 CML |
480 | static void chv_clock(int refclk, intel_clock_t *clock) |
481 | { | |
482 | clock->m = clock->m1 * clock->m2; | |
483 | clock->p = clock->p1 * clock->p2; | |
484 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
485 | return; | |
486 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
487 | clock->n << 22); | |
488 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
489 | } | |
490 | ||
7c04d1d9 | 491 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
492 | /** |
493 | * Returns whether the given set of divisors are valid for a given refclk with | |
494 | * the given connectors. | |
495 | */ | |
496 | ||
1b894b59 CW |
497 | static bool intel_PLL_is_valid(struct drm_device *dev, |
498 | const intel_limit_t *limit, | |
499 | const intel_clock_t *clock) | |
79e53945 | 500 | { |
f01b7962 VS |
501 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
502 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 503 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 504 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 505 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 506 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 507 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 508 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
509 | |
510 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
511 | if (clock->m1 <= clock->m2) | |
512 | INTELPllInvalid("m1 <= m2\n"); | |
513 | ||
514 | if (!IS_VALLEYVIEW(dev)) { | |
515 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
516 | INTELPllInvalid("p out of range\n"); | |
517 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
518 | INTELPllInvalid("m out of range\n"); | |
519 | } | |
520 | ||
79e53945 | 521 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 522 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
523 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
524 | * connector, etc., rather than just a single range. | |
525 | */ | |
526 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 527 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
528 | |
529 | return true; | |
530 | } | |
531 | ||
d4906093 | 532 | static bool |
ee9300bb | 533 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
534 | int target, int refclk, intel_clock_t *match_clock, |
535 | intel_clock_t *best_clock) | |
79e53945 JB |
536 | { |
537 | struct drm_device *dev = crtc->dev; | |
79e53945 | 538 | intel_clock_t clock; |
79e53945 JB |
539 | int err = target; |
540 | ||
a210b028 | 541 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 542 | /* |
a210b028 DV |
543 | * For LVDS just rely on its current settings for dual-channel. |
544 | * We haven't figured out how to reliably set up different | |
545 | * single/dual channel state, if we even can. | |
79e53945 | 546 | */ |
1974cad0 | 547 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
548 | clock.p2 = limit->p2.p2_fast; |
549 | else | |
550 | clock.p2 = limit->p2.p2_slow; | |
551 | } else { | |
552 | if (target < limit->p2.dot_limit) | |
553 | clock.p2 = limit->p2.p2_slow; | |
554 | else | |
555 | clock.p2 = limit->p2.p2_fast; | |
556 | } | |
557 | ||
0206e353 | 558 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 559 | |
42158660 ZY |
560 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
561 | clock.m1++) { | |
562 | for (clock.m2 = limit->m2.min; | |
563 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 564 | if (clock.m2 >= clock.m1) |
42158660 ZY |
565 | break; |
566 | for (clock.n = limit->n.min; | |
567 | clock.n <= limit->n.max; clock.n++) { | |
568 | for (clock.p1 = limit->p1.min; | |
569 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
570 | int this_err; |
571 | ||
ac58c3f0 DV |
572 | i9xx_clock(refclk, &clock); |
573 | if (!intel_PLL_is_valid(dev, limit, | |
574 | &clock)) | |
575 | continue; | |
576 | if (match_clock && | |
577 | clock.p != match_clock->p) | |
578 | continue; | |
579 | ||
580 | this_err = abs(clock.dot - target); | |
581 | if (this_err < err) { | |
582 | *best_clock = clock; | |
583 | err = this_err; | |
584 | } | |
585 | } | |
586 | } | |
587 | } | |
588 | } | |
589 | ||
590 | return (err != target); | |
591 | } | |
592 | ||
593 | static bool | |
ee9300bb DV |
594 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
595 | int target, int refclk, intel_clock_t *match_clock, | |
596 | intel_clock_t *best_clock) | |
79e53945 JB |
597 | { |
598 | struct drm_device *dev = crtc->dev; | |
79e53945 | 599 | intel_clock_t clock; |
79e53945 JB |
600 | int err = target; |
601 | ||
a210b028 | 602 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 603 | /* |
a210b028 DV |
604 | * For LVDS just rely on its current settings for dual-channel. |
605 | * We haven't figured out how to reliably set up different | |
606 | * single/dual channel state, if we even can. | |
79e53945 | 607 | */ |
1974cad0 | 608 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
609 | clock.p2 = limit->p2.p2_fast; |
610 | else | |
611 | clock.p2 = limit->p2.p2_slow; | |
612 | } else { | |
613 | if (target < limit->p2.dot_limit) | |
614 | clock.p2 = limit->p2.p2_slow; | |
615 | else | |
616 | clock.p2 = limit->p2.p2_fast; | |
617 | } | |
618 | ||
0206e353 | 619 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 620 | |
42158660 ZY |
621 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
622 | clock.m1++) { | |
623 | for (clock.m2 = limit->m2.min; | |
624 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
625 | for (clock.n = limit->n.min; |
626 | clock.n <= limit->n.max; clock.n++) { | |
627 | for (clock.p1 = limit->p1.min; | |
628 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
629 | int this_err; |
630 | ||
ac58c3f0 | 631 | pineview_clock(refclk, &clock); |
1b894b59 CW |
632 | if (!intel_PLL_is_valid(dev, limit, |
633 | &clock)) | |
79e53945 | 634 | continue; |
cec2f356 SP |
635 | if (match_clock && |
636 | clock.p != match_clock->p) | |
637 | continue; | |
79e53945 JB |
638 | |
639 | this_err = abs(clock.dot - target); | |
640 | if (this_err < err) { | |
641 | *best_clock = clock; | |
642 | err = this_err; | |
643 | } | |
644 | } | |
645 | } | |
646 | } | |
647 | } | |
648 | ||
649 | return (err != target); | |
650 | } | |
651 | ||
d4906093 | 652 | static bool |
ee9300bb DV |
653 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
654 | int target, int refclk, intel_clock_t *match_clock, | |
655 | intel_clock_t *best_clock) | |
d4906093 ML |
656 | { |
657 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
658 | intel_clock_t clock; |
659 | int max_n; | |
660 | bool found; | |
6ba770dc AJ |
661 | /* approximately equals target * 0.00585 */ |
662 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
663 | found = false; |
664 | ||
665 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 666 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
667 | clock.p2 = limit->p2.p2_fast; |
668 | else | |
669 | clock.p2 = limit->p2.p2_slow; | |
670 | } else { | |
671 | if (target < limit->p2.dot_limit) | |
672 | clock.p2 = limit->p2.p2_slow; | |
673 | else | |
674 | clock.p2 = limit->p2.p2_fast; | |
675 | } | |
676 | ||
677 | memset(best_clock, 0, sizeof(*best_clock)); | |
678 | max_n = limit->n.max; | |
f77f13e2 | 679 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 680 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 681 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
682 | for (clock.m1 = limit->m1.max; |
683 | clock.m1 >= limit->m1.min; clock.m1--) { | |
684 | for (clock.m2 = limit->m2.max; | |
685 | clock.m2 >= limit->m2.min; clock.m2--) { | |
686 | for (clock.p1 = limit->p1.max; | |
687 | clock.p1 >= limit->p1.min; clock.p1--) { | |
688 | int this_err; | |
689 | ||
ac58c3f0 | 690 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
691 | if (!intel_PLL_is_valid(dev, limit, |
692 | &clock)) | |
d4906093 | 693 | continue; |
1b894b59 CW |
694 | |
695 | this_err = abs(clock.dot - target); | |
d4906093 ML |
696 | if (this_err < err_most) { |
697 | *best_clock = clock; | |
698 | err_most = this_err; | |
699 | max_n = clock.n; | |
700 | found = true; | |
701 | } | |
702 | } | |
703 | } | |
704 | } | |
705 | } | |
2c07245f ZW |
706 | return found; |
707 | } | |
708 | ||
a0c4da24 | 709 | static bool |
ee9300bb DV |
710 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
711 | int target, int refclk, intel_clock_t *match_clock, | |
712 | intel_clock_t *best_clock) | |
a0c4da24 | 713 | { |
f01b7962 | 714 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 715 | intel_clock_t clock; |
69e4f900 | 716 | unsigned int bestppm = 1000000; |
27e639bf VS |
717 | /* min update 19.2 MHz */ |
718 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 719 | bool found = false; |
a0c4da24 | 720 | |
6b4bf1c4 VS |
721 | target *= 5; /* fast clock */ |
722 | ||
723 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
724 | |
725 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 726 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 727 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 728 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 729 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 730 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 731 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 732 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
733 | unsigned int ppm, diff; |
734 | ||
6b4bf1c4 VS |
735 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
736 | refclk * clock.m1); | |
737 | ||
738 | vlv_clock(refclk, &clock); | |
43b0ac53 | 739 | |
f01b7962 VS |
740 | if (!intel_PLL_is_valid(dev, limit, |
741 | &clock)) | |
43b0ac53 VS |
742 | continue; |
743 | ||
6b4bf1c4 VS |
744 | diff = abs(clock.dot - target); |
745 | ppm = div_u64(1000000ULL * diff, target); | |
746 | ||
747 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 748 | bestppm = 0; |
6b4bf1c4 | 749 | *best_clock = clock; |
49e497ef | 750 | found = true; |
43b0ac53 | 751 | } |
6b4bf1c4 | 752 | |
c686122c | 753 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 754 | bestppm = ppm; |
6b4bf1c4 | 755 | *best_clock = clock; |
49e497ef | 756 | found = true; |
a0c4da24 JB |
757 | } |
758 | } | |
759 | } | |
760 | } | |
761 | } | |
a0c4da24 | 762 | |
49e497ef | 763 | return found; |
a0c4da24 | 764 | } |
a4fc5ed6 | 765 | |
ef9348c8 CML |
766 | static bool |
767 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
768 | int target, int refclk, intel_clock_t *match_clock, | |
769 | intel_clock_t *best_clock) | |
770 | { | |
771 | struct drm_device *dev = crtc->dev; | |
772 | intel_clock_t clock; | |
773 | uint64_t m2; | |
774 | int found = false; | |
775 | ||
776 | memset(best_clock, 0, sizeof(*best_clock)); | |
777 | ||
778 | /* | |
779 | * Based on hardware doc, the n always set to 1, and m1 always | |
780 | * set to 2. If requires to support 200Mhz refclk, we need to | |
781 | * revisit this because n may not 1 anymore. | |
782 | */ | |
783 | clock.n = 1, clock.m1 = 2; | |
784 | target *= 5; /* fast clock */ | |
785 | ||
786 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
787 | for (clock.p2 = limit->p2.p2_fast; | |
788 | clock.p2 >= limit->p2.p2_slow; | |
789 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
790 | ||
791 | clock.p = clock.p1 * clock.p2; | |
792 | ||
793 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
794 | clock.n) << 22, refclk * clock.m1); | |
795 | ||
796 | if (m2 > INT_MAX/clock.m1) | |
797 | continue; | |
798 | ||
799 | clock.m2 = m2; | |
800 | ||
801 | chv_clock(refclk, &clock); | |
802 | ||
803 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
804 | continue; | |
805 | ||
806 | /* based on hardware requirement, prefer bigger p | |
807 | */ | |
808 | if (clock.p > best_clock->p) { | |
809 | *best_clock = clock; | |
810 | found = true; | |
811 | } | |
812 | } | |
813 | } | |
814 | ||
815 | return found; | |
816 | } | |
817 | ||
20ddf665 VS |
818 | bool intel_crtc_active(struct drm_crtc *crtc) |
819 | { | |
820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
821 | ||
822 | /* Be paranoid as we can arrive here with only partial | |
823 | * state retrieved from the hardware during setup. | |
824 | * | |
241bfc38 | 825 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
826 | * as Haswell has gained clock readout/fastboot support. |
827 | * | |
66e514c1 | 828 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
829 | * properly reconstruct framebuffers. |
830 | */ | |
f4510a27 | 831 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 832 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
833 | } |
834 | ||
a5c961d1 PZ |
835 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
836 | enum pipe pipe) | |
837 | { | |
838 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
840 | ||
3b117c8f | 841 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
842 | } |
843 | ||
57e22f4a | 844 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
845 | { |
846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 847 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
848 | |
849 | frame = I915_READ(frame_reg); | |
850 | ||
851 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 852 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
853 | } |
854 | ||
9d0498a2 JB |
855 | /** |
856 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
857 | * @dev: drm device | |
858 | * @pipe: pipe to wait for | |
859 | * | |
860 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
861 | * mode setting code. | |
862 | */ | |
863 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 864 | { |
9d0498a2 | 865 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 866 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 867 | |
57e22f4a VS |
868 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
869 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
870 | return; |
871 | } | |
872 | ||
300387c0 CW |
873 | /* Clear existing vblank status. Note this will clear any other |
874 | * sticky status fields as well. | |
875 | * | |
876 | * This races with i915_driver_irq_handler() with the result | |
877 | * that either function could miss a vblank event. Here it is not | |
878 | * fatal, as we will either wait upon the next vblank interrupt or | |
879 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
880 | * called during modeset at which time the GPU should be idle and | |
881 | * should *not* be performing page flips and thus not waiting on | |
882 | * vblanks... | |
883 | * Currently, the result of us stealing a vblank from the irq | |
884 | * handler is that a single frame will be skipped during swapbuffers. | |
885 | */ | |
886 | I915_WRITE(pipestat_reg, | |
887 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
888 | ||
9d0498a2 | 889 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
890 | if (wait_for(I915_READ(pipestat_reg) & |
891 | PIPE_VBLANK_INTERRUPT_STATUS, | |
892 | 50)) | |
9d0498a2 JB |
893 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
894 | } | |
895 | ||
fbf49ea2 VS |
896 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
897 | { | |
898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
899 | u32 reg = PIPEDSL(pipe); | |
900 | u32 line1, line2; | |
901 | u32 line_mask; | |
902 | ||
903 | if (IS_GEN2(dev)) | |
904 | line_mask = DSL_LINEMASK_GEN2; | |
905 | else | |
906 | line_mask = DSL_LINEMASK_GEN3; | |
907 | ||
908 | line1 = I915_READ(reg) & line_mask; | |
909 | mdelay(5); | |
910 | line2 = I915_READ(reg) & line_mask; | |
911 | ||
912 | return line1 == line2; | |
913 | } | |
914 | ||
ab7ad7f6 KP |
915 | /* |
916 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
917 | * @dev: drm device |
918 | * @pipe: pipe to wait for | |
919 | * | |
920 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
921 | * spinning on the vblank interrupt status bit, since we won't actually | |
922 | * see an interrupt when the pipe is disabled. | |
923 | * | |
ab7ad7f6 KP |
924 | * On Gen4 and above: |
925 | * wait for the pipe register state bit to turn off | |
926 | * | |
927 | * Otherwise: | |
928 | * wait for the display line value to settle (it usually | |
929 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 930 | * |
9d0498a2 | 931 | */ |
58e10eb9 | 932 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
933 | { |
934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
935 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
936 | pipe); | |
ab7ad7f6 KP |
937 | |
938 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 939 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
940 | |
941 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
942 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
943 | 100)) | |
284637d9 | 944 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 945 | } else { |
ab7ad7f6 | 946 | /* Wait for the display line to settle */ |
fbf49ea2 | 947 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 948 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 949 | } |
79e53945 JB |
950 | } |
951 | ||
b0ea7d37 DL |
952 | /* |
953 | * ibx_digital_port_connected - is the specified port connected? | |
954 | * @dev_priv: i915 private structure | |
955 | * @port: the port to test | |
956 | * | |
957 | * Returns true if @port is connected, false otherwise. | |
958 | */ | |
959 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
960 | struct intel_digital_port *port) | |
961 | { | |
962 | u32 bit; | |
963 | ||
c36346e3 DL |
964 | if (HAS_PCH_IBX(dev_priv->dev)) { |
965 | switch(port->port) { | |
966 | case PORT_B: | |
967 | bit = SDE_PORTB_HOTPLUG; | |
968 | break; | |
969 | case PORT_C: | |
970 | bit = SDE_PORTC_HOTPLUG; | |
971 | break; | |
972 | case PORT_D: | |
973 | bit = SDE_PORTD_HOTPLUG; | |
974 | break; | |
975 | default: | |
976 | return true; | |
977 | } | |
978 | } else { | |
979 | switch(port->port) { | |
980 | case PORT_B: | |
981 | bit = SDE_PORTB_HOTPLUG_CPT; | |
982 | break; | |
983 | case PORT_C: | |
984 | bit = SDE_PORTC_HOTPLUG_CPT; | |
985 | break; | |
986 | case PORT_D: | |
987 | bit = SDE_PORTD_HOTPLUG_CPT; | |
988 | break; | |
989 | default: | |
990 | return true; | |
991 | } | |
b0ea7d37 DL |
992 | } |
993 | ||
994 | return I915_READ(SDEISR) & bit; | |
995 | } | |
996 | ||
b24e7179 JB |
997 | static const char *state_string(bool enabled) |
998 | { | |
999 | return enabled ? "on" : "off"; | |
1000 | } | |
1001 | ||
1002 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1003 | void assert_pll(struct drm_i915_private *dev_priv, |
1004 | enum pipe pipe, bool state) | |
b24e7179 JB |
1005 | { |
1006 | int reg; | |
1007 | u32 val; | |
1008 | bool cur_state; | |
1009 | ||
1010 | reg = DPLL(pipe); | |
1011 | val = I915_READ(reg); | |
1012 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1013 | WARN(cur_state != state, | |
1014 | "PLL state assertion failure (expected %s, current %s)\n", | |
1015 | state_string(state), state_string(cur_state)); | |
1016 | } | |
b24e7179 | 1017 | |
23538ef1 JN |
1018 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1019 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1020 | { | |
1021 | u32 val; | |
1022 | bool cur_state; | |
1023 | ||
1024 | mutex_lock(&dev_priv->dpio_lock); | |
1025 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1026 | mutex_unlock(&dev_priv->dpio_lock); | |
1027 | ||
1028 | cur_state = val & DSI_PLL_VCO_EN; | |
1029 | WARN(cur_state != state, | |
1030 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1031 | state_string(state), state_string(cur_state)); | |
1032 | } | |
1033 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1034 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1035 | ||
55607e8a | 1036 | struct intel_shared_dpll * |
e2b78267 DV |
1037 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1038 | { | |
1039 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1040 | ||
a43f6e0f | 1041 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1042 | return NULL; |
1043 | ||
a43f6e0f | 1044 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1045 | } |
1046 | ||
040484af | 1047 | /* For ILK+ */ |
55607e8a DV |
1048 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1049 | struct intel_shared_dpll *pll, | |
1050 | bool state) | |
040484af | 1051 | { |
040484af | 1052 | bool cur_state; |
5358901f | 1053 | struct intel_dpll_hw_state hw_state; |
040484af | 1054 | |
9d82aa17 ED |
1055 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1056 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1057 | return; | |
1058 | } | |
1059 | ||
92b27b08 | 1060 | if (WARN (!pll, |
46edb027 | 1061 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1062 | return; |
ee7b9f93 | 1063 | |
5358901f | 1064 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1065 | WARN(cur_state != state, |
5358901f DV |
1066 | "%s assertion failure (expected %s, current %s)\n", |
1067 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1068 | } |
040484af JB |
1069 | |
1070 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1071 | enum pipe pipe, bool state) | |
1072 | { | |
1073 | int reg; | |
1074 | u32 val; | |
1075 | bool cur_state; | |
ad80a810 PZ |
1076 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1077 | pipe); | |
040484af | 1078 | |
affa9354 PZ |
1079 | if (HAS_DDI(dev_priv->dev)) { |
1080 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1081 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1082 | val = I915_READ(reg); |
ad80a810 | 1083 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1084 | } else { |
1085 | reg = FDI_TX_CTL(pipe); | |
1086 | val = I915_READ(reg); | |
1087 | cur_state = !!(val & FDI_TX_ENABLE); | |
1088 | } | |
040484af JB |
1089 | WARN(cur_state != state, |
1090 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1091 | state_string(state), state_string(cur_state)); | |
1092 | } | |
1093 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1094 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1095 | ||
1096 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1097 | enum pipe pipe, bool state) | |
1098 | { | |
1099 | int reg; | |
1100 | u32 val; | |
1101 | bool cur_state; | |
1102 | ||
d63fa0dc PZ |
1103 | reg = FDI_RX_CTL(pipe); |
1104 | val = I915_READ(reg); | |
1105 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1106 | WARN(cur_state != state, |
1107 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1108 | state_string(state), state_string(cur_state)); | |
1109 | } | |
1110 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1111 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1112 | ||
1113 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1114 | enum pipe pipe) | |
1115 | { | |
1116 | int reg; | |
1117 | u32 val; | |
1118 | ||
1119 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1120 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1121 | return; |
1122 | ||
bf507ef7 | 1123 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1124 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1125 | return; |
1126 | ||
040484af JB |
1127 | reg = FDI_TX_CTL(pipe); |
1128 | val = I915_READ(reg); | |
1129 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1130 | } | |
1131 | ||
55607e8a DV |
1132 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1133 | enum pipe pipe, bool state) | |
040484af JB |
1134 | { |
1135 | int reg; | |
1136 | u32 val; | |
55607e8a | 1137 | bool cur_state; |
040484af JB |
1138 | |
1139 | reg = FDI_RX_CTL(pipe); | |
1140 | val = I915_READ(reg); | |
55607e8a DV |
1141 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1142 | WARN(cur_state != state, | |
1143 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1144 | state_string(state), state_string(cur_state)); | |
040484af JB |
1145 | } |
1146 | ||
ea0760cf JB |
1147 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1148 | enum pipe pipe) | |
1149 | { | |
1150 | int pp_reg, lvds_reg; | |
1151 | u32 val; | |
1152 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1153 | bool locked = true; |
ea0760cf JB |
1154 | |
1155 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1156 | pp_reg = PCH_PP_CONTROL; | |
1157 | lvds_reg = PCH_LVDS; | |
1158 | } else { | |
1159 | pp_reg = PP_CONTROL; | |
1160 | lvds_reg = LVDS; | |
1161 | } | |
1162 | ||
1163 | val = I915_READ(pp_reg); | |
1164 | if (!(val & PANEL_POWER_ON) || | |
1165 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1166 | locked = false; | |
1167 | ||
1168 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1169 | panel_pipe = PIPE_B; | |
1170 | ||
1171 | WARN(panel_pipe == pipe && locked, | |
1172 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1173 | pipe_name(pipe)); |
ea0760cf JB |
1174 | } |
1175 | ||
93ce0ba6 JN |
1176 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1177 | enum pipe pipe, bool state) | |
1178 | { | |
1179 | struct drm_device *dev = dev_priv->dev; | |
1180 | bool cur_state; | |
1181 | ||
d9d82081 | 1182 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1183 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1184 | else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) |
93ce0ba6 | 1185 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
d9d82081 PZ |
1186 | else |
1187 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
93ce0ba6 JN |
1188 | |
1189 | WARN(cur_state != state, | |
1190 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1191 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1192 | } | |
1193 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1194 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1195 | ||
b840d907 JB |
1196 | void assert_pipe(struct drm_i915_private *dev_priv, |
1197 | enum pipe pipe, bool state) | |
b24e7179 JB |
1198 | { |
1199 | int reg; | |
1200 | u32 val; | |
63d7bbe9 | 1201 | bool cur_state; |
702e7a56 PZ |
1202 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1203 | pipe); | |
b24e7179 | 1204 | |
8e636784 DV |
1205 | /* if we need the pipe A quirk it must be always on */ |
1206 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1207 | state = true; | |
1208 | ||
da7e29bd | 1209 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1210 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1211 | cur_state = false; |
1212 | } else { | |
1213 | reg = PIPECONF(cpu_transcoder); | |
1214 | val = I915_READ(reg); | |
1215 | cur_state = !!(val & PIPECONF_ENABLE); | |
1216 | } | |
1217 | ||
63d7bbe9 JB |
1218 | WARN(cur_state != state, |
1219 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1220 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1221 | } |
1222 | ||
931872fc CW |
1223 | static void assert_plane(struct drm_i915_private *dev_priv, |
1224 | enum plane plane, bool state) | |
b24e7179 JB |
1225 | { |
1226 | int reg; | |
1227 | u32 val; | |
931872fc | 1228 | bool cur_state; |
b24e7179 JB |
1229 | |
1230 | reg = DSPCNTR(plane); | |
1231 | val = I915_READ(reg); | |
931872fc CW |
1232 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1233 | WARN(cur_state != state, | |
1234 | "plane %c assertion failure (expected %s, current %s)\n", | |
1235 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1236 | } |
1237 | ||
931872fc CW |
1238 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1239 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1240 | ||
b24e7179 JB |
1241 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1242 | enum pipe pipe) | |
1243 | { | |
653e1026 | 1244 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1245 | int reg, i; |
1246 | u32 val; | |
1247 | int cur_pipe; | |
1248 | ||
653e1026 VS |
1249 | /* Primary planes are fixed to pipes on gen4+ */ |
1250 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1251 | reg = DSPCNTR(pipe); |
1252 | val = I915_READ(reg); | |
83f26f16 | 1253 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1254 | "plane %c assertion failure, should be disabled but not\n", |
1255 | plane_name(pipe)); | |
19ec1358 | 1256 | return; |
28c05794 | 1257 | } |
19ec1358 | 1258 | |
b24e7179 | 1259 | /* Need to check both planes against the pipe */ |
08e2a7de | 1260 | for_each_pipe(i) { |
b24e7179 JB |
1261 | reg = DSPCNTR(i); |
1262 | val = I915_READ(reg); | |
1263 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1264 | DISPPLANE_SEL_PIPE_SHIFT; | |
1265 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1266 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1267 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1268 | } |
1269 | } | |
1270 | ||
19332d7a JB |
1271 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1272 | enum pipe pipe) | |
1273 | { | |
20674eef | 1274 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1275 | int reg, sprite; |
19332d7a JB |
1276 | u32 val; |
1277 | ||
20674eef | 1278 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1279 | for_each_sprite(pipe, sprite) { |
1280 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1281 | val = I915_READ(reg); |
83f26f16 | 1282 | WARN(val & SP_ENABLE, |
20674eef | 1283 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1284 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1285 | } |
1286 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1287 | reg = SPRCTL(pipe); | |
19332d7a | 1288 | val = I915_READ(reg); |
83f26f16 | 1289 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1290 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1291 | plane_name(pipe), pipe_name(pipe)); |
1292 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1293 | reg = DVSCNTR(pipe); | |
19332d7a | 1294 | val = I915_READ(reg); |
83f26f16 | 1295 | WARN(val & DVS_ENABLE, |
06da8da2 | 1296 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1297 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1298 | } |
1299 | } | |
1300 | ||
89eff4be | 1301 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1302 | { |
1303 | u32 val; | |
1304 | bool enabled; | |
1305 | ||
89eff4be | 1306 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1307 | |
92f2584a JB |
1308 | val = I915_READ(PCH_DREF_CONTROL); |
1309 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1310 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1311 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1312 | } | |
1313 | ||
ab9412ba DV |
1314 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1315 | enum pipe pipe) | |
92f2584a JB |
1316 | { |
1317 | int reg; | |
1318 | u32 val; | |
1319 | bool enabled; | |
1320 | ||
ab9412ba | 1321 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1322 | val = I915_READ(reg); |
1323 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1324 | WARN(enabled, |
1325 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1326 | pipe_name(pipe)); | |
92f2584a JB |
1327 | } |
1328 | ||
4e634389 KP |
1329 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1330 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1331 | { |
1332 | if ((val & DP_PORT_EN) == 0) | |
1333 | return false; | |
1334 | ||
1335 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1336 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1337 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1338 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1339 | return false; | |
44f37d1f CML |
1340 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1341 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1342 | return false; | |
f0575e92 KP |
1343 | } else { |
1344 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1345 | return false; | |
1346 | } | |
1347 | return true; | |
1348 | } | |
1349 | ||
1519b995 KP |
1350 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1351 | enum pipe pipe, u32 val) | |
1352 | { | |
dc0fa718 | 1353 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1354 | return false; |
1355 | ||
1356 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1357 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1358 | return false; |
44f37d1f CML |
1359 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1360 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1361 | return false; | |
1519b995 | 1362 | } else { |
dc0fa718 | 1363 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1364 | return false; |
1365 | } | |
1366 | return true; | |
1367 | } | |
1368 | ||
1369 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1370 | enum pipe pipe, u32 val) | |
1371 | { | |
1372 | if ((val & LVDS_PORT_EN) == 0) | |
1373 | return false; | |
1374 | ||
1375 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1376 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1377 | return false; | |
1378 | } else { | |
1379 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1380 | return false; | |
1381 | } | |
1382 | return true; | |
1383 | } | |
1384 | ||
1385 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1386 | enum pipe pipe, u32 val) | |
1387 | { | |
1388 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1389 | return false; | |
1390 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1391 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1392 | return false; | |
1393 | } else { | |
1394 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1395 | return false; | |
1396 | } | |
1397 | return true; | |
1398 | } | |
1399 | ||
291906f1 | 1400 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1401 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1402 | { |
47a05eca | 1403 | u32 val = I915_READ(reg); |
4e634389 | 1404 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1405 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1406 | reg, pipe_name(pipe)); |
de9a35ab | 1407 | |
75c5da27 DV |
1408 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1409 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1410 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1411 | } |
1412 | ||
1413 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1414 | enum pipe pipe, int reg) | |
1415 | { | |
47a05eca | 1416 | u32 val = I915_READ(reg); |
b70ad586 | 1417 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1418 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1419 | reg, pipe_name(pipe)); |
de9a35ab | 1420 | |
dc0fa718 | 1421 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1422 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1423 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1424 | } |
1425 | ||
1426 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1427 | enum pipe pipe) | |
1428 | { | |
1429 | int reg; | |
1430 | u32 val; | |
291906f1 | 1431 | |
f0575e92 KP |
1432 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1433 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1434 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1435 | |
1436 | reg = PCH_ADPA; | |
1437 | val = I915_READ(reg); | |
b70ad586 | 1438 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1439 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | pipe_name(pipe)); |
291906f1 JB |
1441 | |
1442 | reg = PCH_LVDS; | |
1443 | val = I915_READ(reg); | |
b70ad586 | 1444 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1445 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1446 | pipe_name(pipe)); |
291906f1 | 1447 | |
e2debe91 PZ |
1448 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1449 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1450 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1451 | } |
1452 | ||
40e9cf64 JB |
1453 | static void intel_init_dpio(struct drm_device *dev) |
1454 | { | |
1455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1456 | ||
1457 | if (!IS_VALLEYVIEW(dev)) | |
1458 | return; | |
1459 | ||
a09caddd CML |
1460 | /* |
1461 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1462 | * CHV x1 PHY (DP/HDMI D) | |
1463 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1464 | */ | |
1465 | if (IS_CHERRYVIEW(dev)) { | |
1466 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1467 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1468 | } else { | |
1469 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1470 | } | |
5382f5f3 JB |
1471 | } |
1472 | ||
1473 | static void intel_reset_dpio(struct drm_device *dev) | |
1474 | { | |
1475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1476 | ||
1477 | if (!IS_VALLEYVIEW(dev)) | |
1478 | return; | |
1479 | ||
e5cbfbfb ID |
1480 | /* |
1481 | * Enable the CRI clock source so we can get at the display and the | |
1482 | * reference clock for VGA hotplug / manual detection. | |
1483 | */ | |
404faabc | 1484 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1485 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1486 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1487 | ||
076ed3b2 CML |
1488 | if (IS_CHERRYVIEW(dev)) { |
1489 | enum dpio_phy phy; | |
1490 | u32 val; | |
1491 | ||
1492 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { | |
1493 | /* Poll for phypwrgood signal */ | |
1494 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & | |
1495 | PHY_POWERGOOD(phy), 1)) | |
1496 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1497 | ||
1498 | /* | |
1499 | * Deassert common lane reset for PHY. | |
1500 | * | |
1501 | * This should only be done on init and resume from S3 | |
1502 | * with both PLLs disabled, or we risk losing DPIO and | |
1503 | * PLL synchronization. | |
1504 | */ | |
1505 | val = I915_READ(DISPLAY_PHY_CONTROL); | |
1506 | I915_WRITE(DISPLAY_PHY_CONTROL, | |
1507 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); | |
1508 | } | |
1509 | ||
1510 | } else { | |
1511 | /* | |
1512 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1513 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1514 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1515 | * b. The other bits such as sfr settings / modesel may all | |
1516 | * be set to 0. | |
1517 | * | |
1518 | * This should only be done on init and resume from S3 with | |
1519 | * both PLLs disabled, or we risk losing DPIO and PLL | |
1520 | * synchronization. | |
1521 | */ | |
1522 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1523 | } | |
40e9cf64 JB |
1524 | } |
1525 | ||
426115cf | 1526 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1527 | { |
426115cf DV |
1528 | struct drm_device *dev = crtc->base.dev; |
1529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1530 | int reg = DPLL(crtc->pipe); | |
1531 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1532 | |
426115cf | 1533 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1534 | |
1535 | /* No really, not for ILK+ */ | |
1536 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1537 | ||
1538 | /* PLL is protected by panel, make sure we can write it */ | |
1539 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1540 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1541 | |
426115cf DV |
1542 | I915_WRITE(reg, dpll); |
1543 | POSTING_READ(reg); | |
1544 | udelay(150); | |
1545 | ||
1546 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1547 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1548 | ||
1549 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1550 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1551 | |
1552 | /* We do this three times for luck */ | |
426115cf | 1553 | I915_WRITE(reg, dpll); |
87442f73 DV |
1554 | POSTING_READ(reg); |
1555 | udelay(150); /* wait for warmup */ | |
426115cf | 1556 | I915_WRITE(reg, dpll); |
87442f73 DV |
1557 | POSTING_READ(reg); |
1558 | udelay(150); /* wait for warmup */ | |
426115cf | 1559 | I915_WRITE(reg, dpll); |
87442f73 DV |
1560 | POSTING_READ(reg); |
1561 | udelay(150); /* wait for warmup */ | |
1562 | } | |
1563 | ||
9d556c99 CML |
1564 | static void chv_enable_pll(struct intel_crtc *crtc) |
1565 | { | |
1566 | struct drm_device *dev = crtc->base.dev; | |
1567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1568 | int pipe = crtc->pipe; | |
1569 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
1570 | int dpll = DPLL(crtc->pipe); | |
1571 | u32 tmp; | |
1572 | ||
1573 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1574 | ||
1575 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1576 | ||
1577 | mutex_lock(&dev_priv->dpio_lock); | |
1578 | ||
1579 | /* Enable back the 10bit clock to display controller */ | |
1580 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1581 | tmp |= DPIO_DCLKP_EN; | |
1582 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1583 | ||
1584 | /* | |
1585 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1586 | */ | |
1587 | udelay(1); | |
1588 | ||
1589 | /* Enable PLL */ | |
1590 | tmp = I915_READ(dpll); | |
1591 | tmp |= DPLL_VCO_ENABLE; | |
1592 | I915_WRITE(dpll, tmp); | |
1593 | ||
1594 | /* Check PLL is locked */ | |
1595 | if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1596 | DRM_ERROR("PLL %d failed to lock\n", pipe); | |
1597 | ||
1598 | /* Deassert soft data lane reset*/ | |
1599 | tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port)); | |
1600 | tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1601 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp); | |
1602 | ||
1603 | ||
1604 | mutex_unlock(&dev_priv->dpio_lock); | |
1605 | } | |
1606 | ||
66e3d5c0 | 1607 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1608 | { |
66e3d5c0 DV |
1609 | struct drm_device *dev = crtc->base.dev; |
1610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1611 | int reg = DPLL(crtc->pipe); | |
1612 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1613 | |
66e3d5c0 | 1614 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1615 | |
63d7bbe9 | 1616 | /* No really, not for ILK+ */ |
3d13ef2e | 1617 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1618 | |
1619 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1620 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1621 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1622 | |
66e3d5c0 DV |
1623 | I915_WRITE(reg, dpll); |
1624 | ||
1625 | /* Wait for the clocks to stabilize. */ | |
1626 | POSTING_READ(reg); | |
1627 | udelay(150); | |
1628 | ||
1629 | if (INTEL_INFO(dev)->gen >= 4) { | |
1630 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1631 | crtc->config.dpll_hw_state.dpll_md); | |
1632 | } else { | |
1633 | /* The pixel multiplier can only be updated once the | |
1634 | * DPLL is enabled and the clocks are stable. | |
1635 | * | |
1636 | * So write it again. | |
1637 | */ | |
1638 | I915_WRITE(reg, dpll); | |
1639 | } | |
63d7bbe9 JB |
1640 | |
1641 | /* We do this three times for luck */ | |
66e3d5c0 | 1642 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1643 | POSTING_READ(reg); |
1644 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1645 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1646 | POSTING_READ(reg); |
1647 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1648 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1649 | POSTING_READ(reg); |
1650 | udelay(150); /* wait for warmup */ | |
1651 | } | |
1652 | ||
1653 | /** | |
50b44a44 | 1654 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1655 | * @dev_priv: i915 private structure |
1656 | * @pipe: pipe PLL to disable | |
1657 | * | |
1658 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1659 | * | |
1660 | * Note! This is for pre-ILK only. | |
1661 | */ | |
50b44a44 | 1662 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1663 | { |
63d7bbe9 JB |
1664 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1665 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1666 | return; | |
1667 | ||
1668 | /* Make sure the pipe isn't still relying on us */ | |
1669 | assert_pipe_disabled(dev_priv, pipe); | |
1670 | ||
50b44a44 DV |
1671 | I915_WRITE(DPLL(pipe), 0); |
1672 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1673 | } |
1674 | ||
f6071166 JB |
1675 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1676 | { | |
1677 | u32 val = 0; | |
1678 | ||
1679 | /* Make sure the pipe isn't still relying on us */ | |
1680 | assert_pipe_disabled(dev_priv, pipe); | |
1681 | ||
e5cbfbfb ID |
1682 | /* |
1683 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1684 | * The latter is needed for VGA hotplug / manual detection. | |
1685 | */ | |
f6071166 | 1686 | if (pipe == PIPE_B) |
e5cbfbfb | 1687 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1688 | I915_WRITE(DPLL(pipe), val); |
1689 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1690 | |
1691 | } | |
1692 | ||
1693 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1694 | { | |
1695 | int dpll = DPLL(pipe); | |
1696 | u32 val; | |
1697 | ||
1698 | /* Set PLL en = 0 */ | |
1699 | val = I915_READ(dpll); | |
1700 | val &= ~DPLL_VCO_ENABLE; | |
1701 | I915_WRITE(dpll, val); | |
1702 | ||
f6071166 JB |
1703 | } |
1704 | ||
e4607fcf CML |
1705 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1706 | struct intel_digital_port *dport) | |
89b667f8 JB |
1707 | { |
1708 | u32 port_mask; | |
00fc31b7 | 1709 | int dpll_reg; |
89b667f8 | 1710 | |
e4607fcf CML |
1711 | switch (dport->port) { |
1712 | case PORT_B: | |
89b667f8 | 1713 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1714 | dpll_reg = DPLL(0); |
e4607fcf CML |
1715 | break; |
1716 | case PORT_C: | |
89b667f8 | 1717 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1718 | dpll_reg = DPLL(0); |
1719 | break; | |
1720 | case PORT_D: | |
1721 | port_mask = DPLL_PORTD_READY_MASK; | |
1722 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1723 | break; |
1724 | default: | |
1725 | BUG(); | |
1726 | } | |
89b667f8 | 1727 | |
00fc31b7 | 1728 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1729 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1730 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1731 | } |
1732 | ||
92f2584a | 1733 | /** |
e72f9fbf | 1734 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1735 | * @dev_priv: i915 private structure |
1736 | * @pipe: pipe PLL to enable | |
1737 | * | |
1738 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1739 | * drives the transcoder clock. | |
1740 | */ | |
e2b78267 | 1741 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1742 | { |
3d13ef2e DL |
1743 | struct drm_device *dev = crtc->base.dev; |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1745 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1746 | |
48da64a8 | 1747 | /* PCH PLLs only available on ILK, SNB and IVB */ |
3d13ef2e | 1748 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1749 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1750 | return; |
1751 | ||
1752 | if (WARN_ON(pll->refcount == 0)) | |
1753 | return; | |
ee7b9f93 | 1754 | |
46edb027 DV |
1755 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1756 | pll->name, pll->active, pll->on, | |
e2b78267 | 1757 | crtc->base.base.id); |
92f2584a | 1758 | |
cdbd2316 DV |
1759 | if (pll->active++) { |
1760 | WARN_ON(!pll->on); | |
e9d6944e | 1761 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1762 | return; |
1763 | } | |
f4a091c7 | 1764 | WARN_ON(pll->on); |
ee7b9f93 | 1765 | |
46edb027 | 1766 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1767 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1768 | pll->on = true; |
92f2584a JB |
1769 | } |
1770 | ||
e2b78267 | 1771 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1772 | { |
3d13ef2e DL |
1773 | struct drm_device *dev = crtc->base.dev; |
1774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1775 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1776 | |
92f2584a | 1777 | /* PCH only available on ILK+ */ |
3d13ef2e | 1778 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1779 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1780 | return; |
92f2584a | 1781 | |
48da64a8 CW |
1782 | if (WARN_ON(pll->refcount == 0)) |
1783 | return; | |
7a419866 | 1784 | |
46edb027 DV |
1785 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1786 | pll->name, pll->active, pll->on, | |
e2b78267 | 1787 | crtc->base.base.id); |
7a419866 | 1788 | |
48da64a8 | 1789 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1790 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1791 | return; |
1792 | } | |
1793 | ||
e9d6944e | 1794 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1795 | WARN_ON(!pll->on); |
cdbd2316 | 1796 | if (--pll->active) |
7a419866 | 1797 | return; |
ee7b9f93 | 1798 | |
46edb027 | 1799 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1800 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1801 | pll->on = false; |
92f2584a JB |
1802 | } |
1803 | ||
b8a4f404 PZ |
1804 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1805 | enum pipe pipe) | |
040484af | 1806 | { |
23670b32 | 1807 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1808 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1810 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1811 | |
1812 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1813 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1814 | |
1815 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1816 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1817 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1818 | |
1819 | /* FDI must be feeding us bits for PCH ports */ | |
1820 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1821 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1822 | ||
23670b32 DV |
1823 | if (HAS_PCH_CPT(dev)) { |
1824 | /* Workaround: Set the timing override bit before enabling the | |
1825 | * pch transcoder. */ | |
1826 | reg = TRANS_CHICKEN2(pipe); | |
1827 | val = I915_READ(reg); | |
1828 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1829 | I915_WRITE(reg, val); | |
59c859d6 | 1830 | } |
23670b32 | 1831 | |
ab9412ba | 1832 | reg = PCH_TRANSCONF(pipe); |
040484af | 1833 | val = I915_READ(reg); |
5f7f726d | 1834 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1835 | |
1836 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1837 | /* | |
1838 | * make the BPC in transcoder be consistent with | |
1839 | * that in pipeconf reg. | |
1840 | */ | |
dfd07d72 DV |
1841 | val &= ~PIPECONF_BPC_MASK; |
1842 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1843 | } |
5f7f726d PZ |
1844 | |
1845 | val &= ~TRANS_INTERLACE_MASK; | |
1846 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1847 | if (HAS_PCH_IBX(dev_priv->dev) && |
1848 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1849 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1850 | else | |
1851 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1852 | else |
1853 | val |= TRANS_PROGRESSIVE; | |
1854 | ||
040484af JB |
1855 | I915_WRITE(reg, val | TRANS_ENABLE); |
1856 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1857 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1858 | } |
1859 | ||
8fb033d7 | 1860 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1861 | enum transcoder cpu_transcoder) |
040484af | 1862 | { |
8fb033d7 | 1863 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1864 | |
1865 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1866 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1867 | |
8fb033d7 | 1868 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1869 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1870 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1871 | |
223a6fdf PZ |
1872 | /* Workaround: set timing override bit. */ |
1873 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1874 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1875 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1876 | ||
25f3ef11 | 1877 | val = TRANS_ENABLE; |
937bb610 | 1878 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1879 | |
9a76b1c6 PZ |
1880 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1881 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1882 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1883 | else |
1884 | val |= TRANS_PROGRESSIVE; | |
1885 | ||
ab9412ba DV |
1886 | I915_WRITE(LPT_TRANSCONF, val); |
1887 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1888 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1889 | } |
1890 | ||
b8a4f404 PZ |
1891 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1892 | enum pipe pipe) | |
040484af | 1893 | { |
23670b32 DV |
1894 | struct drm_device *dev = dev_priv->dev; |
1895 | uint32_t reg, val; | |
040484af JB |
1896 | |
1897 | /* FDI relies on the transcoder */ | |
1898 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1899 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1900 | ||
291906f1 JB |
1901 | /* Ports must be off as well */ |
1902 | assert_pch_ports_disabled(dev_priv, pipe); | |
1903 | ||
ab9412ba | 1904 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1905 | val = I915_READ(reg); |
1906 | val &= ~TRANS_ENABLE; | |
1907 | I915_WRITE(reg, val); | |
1908 | /* wait for PCH transcoder off, transcoder state */ | |
1909 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1910 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1911 | |
1912 | if (!HAS_PCH_IBX(dev)) { | |
1913 | /* Workaround: Clear the timing override chicken bit again. */ | |
1914 | reg = TRANS_CHICKEN2(pipe); | |
1915 | val = I915_READ(reg); | |
1916 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1917 | I915_WRITE(reg, val); | |
1918 | } | |
040484af JB |
1919 | } |
1920 | ||
ab4d966c | 1921 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1922 | { |
8fb033d7 PZ |
1923 | u32 val; |
1924 | ||
ab9412ba | 1925 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1926 | val &= ~TRANS_ENABLE; |
ab9412ba | 1927 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1928 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1929 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1930 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1931 | |
1932 | /* Workaround: clear timing override bit. */ | |
1933 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1934 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1935 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1936 | } |
1937 | ||
b24e7179 | 1938 | /** |
309cfea8 | 1939 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1940 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1941 | * |
0372264a | 1942 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1943 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1944 | */ |
e1fdc473 | 1945 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1946 | { |
0372264a PZ |
1947 | struct drm_device *dev = crtc->base.dev; |
1948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1949 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1950 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1951 | pipe); | |
1a240d4d | 1952 | enum pipe pch_transcoder; |
b24e7179 JB |
1953 | int reg; |
1954 | u32 val; | |
1955 | ||
58c6eaa2 | 1956 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1957 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1958 | assert_sprites_disabled(dev_priv, pipe); |
1959 | ||
681e5811 | 1960 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1961 | pch_transcoder = TRANSCODER_A; |
1962 | else | |
1963 | pch_transcoder = pipe; | |
1964 | ||
b24e7179 JB |
1965 | /* |
1966 | * A pipe without a PLL won't actually be able to drive bits from | |
1967 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1968 | * need the check. | |
1969 | */ | |
1970 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 1971 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1972 | assert_dsi_pll_enabled(dev_priv); |
1973 | else | |
1974 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1975 | else { |
30421c4f | 1976 | if (crtc->config.has_pch_encoder) { |
040484af | 1977 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1978 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1979 | assert_fdi_tx_pll_enabled(dev_priv, |
1980 | (enum pipe) cpu_transcoder); | |
040484af JB |
1981 | } |
1982 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1983 | } | |
b24e7179 | 1984 | |
702e7a56 | 1985 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1986 | val = I915_READ(reg); |
7ad25d48 PZ |
1987 | if (val & PIPECONF_ENABLE) { |
1988 | WARN_ON(!(pipe == PIPE_A && | |
1989 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 1990 | return; |
7ad25d48 | 1991 | } |
00d70b15 CW |
1992 | |
1993 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1994 | POSTING_READ(reg); |
b24e7179 JB |
1995 | } |
1996 | ||
1997 | /** | |
309cfea8 | 1998 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1999 | * @dev_priv: i915 private structure |
2000 | * @pipe: pipe to disable | |
2001 | * | |
2002 | * Disable @pipe, making sure that various hardware specific requirements | |
2003 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2004 | * | |
2005 | * @pipe should be %PIPE_A or %PIPE_B. | |
2006 | * | |
2007 | * Will wait until the pipe has shut down before returning. | |
2008 | */ | |
2009 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2010 | enum pipe pipe) | |
2011 | { | |
702e7a56 PZ |
2012 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2013 | pipe); | |
b24e7179 JB |
2014 | int reg; |
2015 | u32 val; | |
2016 | ||
2017 | /* | |
2018 | * Make sure planes won't keep trying to pump pixels to us, | |
2019 | * or we might hang the display. | |
2020 | */ | |
2021 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2022 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2023 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2024 | |
2025 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2026 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2027 | return; | |
2028 | ||
702e7a56 | 2029 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2030 | val = I915_READ(reg); |
00d70b15 CW |
2031 | if ((val & PIPECONF_ENABLE) == 0) |
2032 | return; | |
2033 | ||
2034 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2035 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2036 | } | |
2037 | ||
d74362c9 KP |
2038 | /* |
2039 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2040 | * trigger in order to latch. The display address reg provides this. | |
2041 | */ | |
1dba99f4 VS |
2042 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2043 | enum plane plane) | |
d74362c9 | 2044 | { |
3d13ef2e DL |
2045 | struct drm_device *dev = dev_priv->dev; |
2046 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2047 | |
2048 | I915_WRITE(reg, I915_READ(reg)); | |
2049 | POSTING_READ(reg); | |
d74362c9 KP |
2050 | } |
2051 | ||
b24e7179 | 2052 | /** |
262ca2b0 | 2053 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2054 | * @dev_priv: i915 private structure |
2055 | * @plane: plane to enable | |
2056 | * @pipe: pipe being fed | |
2057 | * | |
2058 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2059 | */ | |
262ca2b0 MR |
2060 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2061 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2062 | { |
939c2fe8 VS |
2063 | struct intel_crtc *intel_crtc = |
2064 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2065 | int reg; |
2066 | u32 val; | |
2067 | ||
2068 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2069 | assert_pipe_enabled(dev_priv, pipe); | |
2070 | ||
98ec7739 VS |
2071 | if (intel_crtc->primary_enabled) |
2072 | return; | |
0037f71c | 2073 | |
4c445e0e | 2074 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2075 | |
b24e7179 JB |
2076 | reg = DSPCNTR(plane); |
2077 | val = I915_READ(reg); | |
10efa932 | 2078 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2079 | |
2080 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2081 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2082 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2083 | } | |
2084 | ||
b24e7179 | 2085 | /** |
262ca2b0 | 2086 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2087 | * @dev_priv: i915 private structure |
2088 | * @plane: plane to disable | |
2089 | * @pipe: pipe consuming the data | |
2090 | * | |
2091 | * Disable @plane; should be an independent operation. | |
2092 | */ | |
262ca2b0 MR |
2093 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2094 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2095 | { |
939c2fe8 VS |
2096 | struct intel_crtc *intel_crtc = |
2097 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2098 | int reg; |
2099 | u32 val; | |
2100 | ||
98ec7739 VS |
2101 | if (!intel_crtc->primary_enabled) |
2102 | return; | |
0037f71c | 2103 | |
4c445e0e | 2104 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2105 | |
b24e7179 JB |
2106 | reg = DSPCNTR(plane); |
2107 | val = I915_READ(reg); | |
10efa932 | 2108 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2109 | |
2110 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2111 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2112 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2113 | } | |
2114 | ||
693db184 CW |
2115 | static bool need_vtd_wa(struct drm_device *dev) |
2116 | { | |
2117 | #ifdef CONFIG_INTEL_IOMMU | |
2118 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2119 | return true; | |
2120 | #endif | |
2121 | return false; | |
2122 | } | |
2123 | ||
a57ce0b2 JB |
2124 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2125 | { | |
2126 | int tile_height; | |
2127 | ||
2128 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2129 | return ALIGN(height, tile_height); | |
2130 | } | |
2131 | ||
127bd2ac | 2132 | int |
48b956c5 | 2133 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2134 | struct drm_i915_gem_object *obj, |
919926ae | 2135 | struct intel_ring_buffer *pipelined) |
6b95a207 | 2136 | { |
ce453d81 | 2137 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2138 | u32 alignment; |
2139 | int ret; | |
2140 | ||
05394f39 | 2141 | switch (obj->tiling_mode) { |
6b95a207 | 2142 | case I915_TILING_NONE: |
534843da CW |
2143 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2144 | alignment = 128 * 1024; | |
a6c45cf0 | 2145 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2146 | alignment = 4 * 1024; |
2147 | else | |
2148 | alignment = 64 * 1024; | |
6b95a207 KH |
2149 | break; |
2150 | case I915_TILING_X: | |
2151 | /* pin() will align the object as required by fence */ | |
2152 | alignment = 0; | |
2153 | break; | |
2154 | case I915_TILING_Y: | |
80075d49 | 2155 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2156 | return -EINVAL; |
2157 | default: | |
2158 | BUG(); | |
2159 | } | |
2160 | ||
693db184 CW |
2161 | /* Note that the w/a also requires 64 PTE of padding following the |
2162 | * bo. We currently fill all unused PTE with the shadow page and so | |
2163 | * we should always have valid PTE following the scanout preventing | |
2164 | * the VT-d warning. | |
2165 | */ | |
2166 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2167 | alignment = 256 * 1024; | |
2168 | ||
ce453d81 | 2169 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2170 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2171 | if (ret) |
ce453d81 | 2172 | goto err_interruptible; |
6b95a207 KH |
2173 | |
2174 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2175 | * fence, whereas 965+ only requires a fence if using | |
2176 | * framebuffer compression. For simplicity, we always install | |
2177 | * a fence as the cost is not that onerous. | |
2178 | */ | |
06d98131 | 2179 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2180 | if (ret) |
2181 | goto err_unpin; | |
1690e1eb | 2182 | |
9a5a53b3 | 2183 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2184 | |
ce453d81 | 2185 | dev_priv->mm.interruptible = true; |
6b95a207 | 2186 | return 0; |
48b956c5 CW |
2187 | |
2188 | err_unpin: | |
cc98b413 | 2189 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2190 | err_interruptible: |
2191 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2192 | return ret; |
6b95a207 KH |
2193 | } |
2194 | ||
1690e1eb CW |
2195 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2196 | { | |
2197 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2198 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2199 | } |
2200 | ||
c2c75131 DV |
2201 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2202 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2203 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2204 | unsigned int tiling_mode, | |
2205 | unsigned int cpp, | |
2206 | unsigned int pitch) | |
c2c75131 | 2207 | { |
bc752862 CW |
2208 | if (tiling_mode != I915_TILING_NONE) { |
2209 | unsigned int tile_rows, tiles; | |
c2c75131 | 2210 | |
bc752862 CW |
2211 | tile_rows = *y / 8; |
2212 | *y %= 8; | |
c2c75131 | 2213 | |
bc752862 CW |
2214 | tiles = *x / (512/cpp); |
2215 | *x %= 512/cpp; | |
2216 | ||
2217 | return tile_rows * pitch * 8 + tiles * 4096; | |
2218 | } else { | |
2219 | unsigned int offset; | |
2220 | ||
2221 | offset = *y * pitch + *x * cpp; | |
2222 | *y = 0; | |
2223 | *x = (offset & 4095) / cpp; | |
2224 | return offset & -4096; | |
2225 | } | |
c2c75131 DV |
2226 | } |
2227 | ||
46f297fb JB |
2228 | int intel_format_to_fourcc(int format) |
2229 | { | |
2230 | switch (format) { | |
2231 | case DISPPLANE_8BPP: | |
2232 | return DRM_FORMAT_C8; | |
2233 | case DISPPLANE_BGRX555: | |
2234 | return DRM_FORMAT_XRGB1555; | |
2235 | case DISPPLANE_BGRX565: | |
2236 | return DRM_FORMAT_RGB565; | |
2237 | default: | |
2238 | case DISPPLANE_BGRX888: | |
2239 | return DRM_FORMAT_XRGB8888; | |
2240 | case DISPPLANE_RGBX888: | |
2241 | return DRM_FORMAT_XBGR8888; | |
2242 | case DISPPLANE_BGRX101010: | |
2243 | return DRM_FORMAT_XRGB2101010; | |
2244 | case DISPPLANE_RGBX101010: | |
2245 | return DRM_FORMAT_XBGR2101010; | |
2246 | } | |
2247 | } | |
2248 | ||
484b41dd | 2249 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2250 | struct intel_plane_config *plane_config) |
2251 | { | |
2252 | struct drm_device *dev = crtc->base.dev; | |
2253 | struct drm_i915_gem_object *obj = NULL; | |
2254 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2255 | u32 base = plane_config->base; | |
2256 | ||
ff2652ea CW |
2257 | if (plane_config->size == 0) |
2258 | return false; | |
2259 | ||
46f297fb JB |
2260 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2261 | plane_config->size); | |
2262 | if (!obj) | |
484b41dd | 2263 | return false; |
46f297fb JB |
2264 | |
2265 | if (plane_config->tiled) { | |
2266 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2267 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2268 | } |
2269 | ||
66e514c1 DA |
2270 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2271 | mode_cmd.width = crtc->base.primary->fb->width; | |
2272 | mode_cmd.height = crtc->base.primary->fb->height; | |
2273 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2274 | |
2275 | mutex_lock(&dev->struct_mutex); | |
2276 | ||
66e514c1 | 2277 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2278 | &mode_cmd, obj)) { |
46f297fb JB |
2279 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2280 | goto out_unref_obj; | |
2281 | } | |
2282 | ||
2283 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2284 | |
2285 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2286 | return true; | |
46f297fb JB |
2287 | |
2288 | out_unref_obj: | |
2289 | drm_gem_object_unreference(&obj->base); | |
2290 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2291 | return false; |
2292 | } | |
2293 | ||
2294 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2295 | struct intel_plane_config *plane_config) | |
2296 | { | |
2297 | struct drm_device *dev = intel_crtc->base.dev; | |
2298 | struct drm_crtc *c; | |
2299 | struct intel_crtc *i; | |
2300 | struct intel_framebuffer *fb; | |
2301 | ||
66e514c1 | 2302 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2303 | return; |
2304 | ||
2305 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2306 | return; | |
2307 | ||
66e514c1 DA |
2308 | kfree(intel_crtc->base.primary->fb); |
2309 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2310 | |
2311 | /* | |
2312 | * Failed to alloc the obj, check to see if we should share | |
2313 | * an fb with another CRTC instead | |
2314 | */ | |
70e1e0ec | 2315 | for_each_crtc(dev, c) { |
484b41dd JB |
2316 | i = to_intel_crtc(c); |
2317 | ||
2318 | if (c == &intel_crtc->base) | |
2319 | continue; | |
2320 | ||
66e514c1 | 2321 | if (!i->active || !c->primary->fb) |
484b41dd JB |
2322 | continue; |
2323 | ||
66e514c1 | 2324 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd | 2325 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
66e514c1 DA |
2326 | drm_framebuffer_reference(c->primary->fb); |
2327 | intel_crtc->base.primary->fb = c->primary->fb; | |
484b41dd JB |
2328 | break; |
2329 | } | |
2330 | } | |
46f297fb JB |
2331 | } |
2332 | ||
29b9bde6 DV |
2333 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2334 | struct drm_framebuffer *fb, | |
2335 | int x, int y) | |
81255565 JB |
2336 | { |
2337 | struct drm_device *dev = crtc->dev; | |
2338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2340 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2341 | struct drm_i915_gem_object *obj; |
81255565 | 2342 | int plane = intel_crtc->plane; |
e506a0c6 | 2343 | unsigned long linear_offset; |
81255565 | 2344 | u32 dspcntr; |
5eddb70b | 2345 | u32 reg; |
81255565 | 2346 | |
81255565 JB |
2347 | intel_fb = to_intel_framebuffer(fb); |
2348 | obj = intel_fb->obj; | |
81255565 | 2349 | |
5eddb70b CW |
2350 | reg = DSPCNTR(plane); |
2351 | dspcntr = I915_READ(reg); | |
81255565 JB |
2352 | /* Mask out pixel format bits in case we change it */ |
2353 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2354 | switch (fb->pixel_format) { |
2355 | case DRM_FORMAT_C8: | |
81255565 JB |
2356 | dspcntr |= DISPPLANE_8BPP; |
2357 | break; | |
57779d06 VS |
2358 | case DRM_FORMAT_XRGB1555: |
2359 | case DRM_FORMAT_ARGB1555: | |
2360 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2361 | break; |
57779d06 VS |
2362 | case DRM_FORMAT_RGB565: |
2363 | dspcntr |= DISPPLANE_BGRX565; | |
2364 | break; | |
2365 | case DRM_FORMAT_XRGB8888: | |
2366 | case DRM_FORMAT_ARGB8888: | |
2367 | dspcntr |= DISPPLANE_BGRX888; | |
2368 | break; | |
2369 | case DRM_FORMAT_XBGR8888: | |
2370 | case DRM_FORMAT_ABGR8888: | |
2371 | dspcntr |= DISPPLANE_RGBX888; | |
2372 | break; | |
2373 | case DRM_FORMAT_XRGB2101010: | |
2374 | case DRM_FORMAT_ARGB2101010: | |
2375 | dspcntr |= DISPPLANE_BGRX101010; | |
2376 | break; | |
2377 | case DRM_FORMAT_XBGR2101010: | |
2378 | case DRM_FORMAT_ABGR2101010: | |
2379 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2380 | break; |
2381 | default: | |
baba133a | 2382 | BUG(); |
81255565 | 2383 | } |
57779d06 | 2384 | |
a6c45cf0 | 2385 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2386 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2387 | dspcntr |= DISPPLANE_TILED; |
2388 | else | |
2389 | dspcntr &= ~DISPPLANE_TILED; | |
2390 | } | |
2391 | ||
de1aa629 VS |
2392 | if (IS_G4X(dev)) |
2393 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2394 | ||
5eddb70b | 2395 | I915_WRITE(reg, dspcntr); |
81255565 | 2396 | |
e506a0c6 | 2397 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2398 | |
c2c75131 DV |
2399 | if (INTEL_INFO(dev)->gen >= 4) { |
2400 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2401 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2402 | fb->bits_per_pixel / 8, | |
2403 | fb->pitches[0]); | |
c2c75131 DV |
2404 | linear_offset -= intel_crtc->dspaddr_offset; |
2405 | } else { | |
e506a0c6 | 2406 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2407 | } |
e506a0c6 | 2408 | |
f343c5f6 BW |
2409 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2410 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2411 | fb->pitches[0]); | |
01f2c773 | 2412 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2413 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2414 | I915_WRITE(DSPSURF(plane), |
2415 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2416 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2417 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2418 | } else |
f343c5f6 | 2419 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2420 | POSTING_READ(reg); |
17638cd6 JB |
2421 | } |
2422 | ||
29b9bde6 DV |
2423 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2424 | struct drm_framebuffer *fb, | |
2425 | int x, int y) | |
17638cd6 JB |
2426 | { |
2427 | struct drm_device *dev = crtc->dev; | |
2428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2429 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2430 | struct intel_framebuffer *intel_fb; | |
2431 | struct drm_i915_gem_object *obj; | |
2432 | int plane = intel_crtc->plane; | |
e506a0c6 | 2433 | unsigned long linear_offset; |
17638cd6 JB |
2434 | u32 dspcntr; |
2435 | u32 reg; | |
2436 | ||
17638cd6 JB |
2437 | intel_fb = to_intel_framebuffer(fb); |
2438 | obj = intel_fb->obj; | |
2439 | ||
2440 | reg = DSPCNTR(plane); | |
2441 | dspcntr = I915_READ(reg); | |
2442 | /* Mask out pixel format bits in case we change it */ | |
2443 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2444 | switch (fb->pixel_format) { |
2445 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2446 | dspcntr |= DISPPLANE_8BPP; |
2447 | break; | |
57779d06 VS |
2448 | case DRM_FORMAT_RGB565: |
2449 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2450 | break; |
57779d06 VS |
2451 | case DRM_FORMAT_XRGB8888: |
2452 | case DRM_FORMAT_ARGB8888: | |
2453 | dspcntr |= DISPPLANE_BGRX888; | |
2454 | break; | |
2455 | case DRM_FORMAT_XBGR8888: | |
2456 | case DRM_FORMAT_ABGR8888: | |
2457 | dspcntr |= DISPPLANE_RGBX888; | |
2458 | break; | |
2459 | case DRM_FORMAT_XRGB2101010: | |
2460 | case DRM_FORMAT_ARGB2101010: | |
2461 | dspcntr |= DISPPLANE_BGRX101010; | |
2462 | break; | |
2463 | case DRM_FORMAT_XBGR2101010: | |
2464 | case DRM_FORMAT_ABGR2101010: | |
2465 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2466 | break; |
2467 | default: | |
baba133a | 2468 | BUG(); |
17638cd6 JB |
2469 | } |
2470 | ||
2471 | if (obj->tiling_mode != I915_TILING_NONE) | |
2472 | dspcntr |= DISPPLANE_TILED; | |
2473 | else | |
2474 | dspcntr &= ~DISPPLANE_TILED; | |
2475 | ||
b42c6009 | 2476 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2477 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2478 | else | |
2479 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2480 | |
2481 | I915_WRITE(reg, dspcntr); | |
2482 | ||
e506a0c6 | 2483 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2484 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2485 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2486 | fb->bits_per_pixel / 8, | |
2487 | fb->pitches[0]); | |
c2c75131 | 2488 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2489 | |
f343c5f6 BW |
2490 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2491 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2492 | fb->pitches[0]); | |
01f2c773 | 2493 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2494 | I915_WRITE(DSPSURF(plane), |
2495 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2496 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2497 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2498 | } else { | |
2499 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2500 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2501 | } | |
17638cd6 | 2502 | POSTING_READ(reg); |
17638cd6 JB |
2503 | } |
2504 | ||
2505 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2506 | static int | |
2507 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2508 | int x, int y, enum mode_set_atomic state) | |
2509 | { | |
2510 | struct drm_device *dev = crtc->dev; | |
2511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2512 | |
6b8e6ed0 CW |
2513 | if (dev_priv->display.disable_fbc) |
2514 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2515 | intel_increase_pllclock(crtc); |
81255565 | 2516 | |
29b9bde6 DV |
2517 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2518 | ||
2519 | return 0; | |
81255565 JB |
2520 | } |
2521 | ||
96a02917 VS |
2522 | void intel_display_handle_reset(struct drm_device *dev) |
2523 | { | |
2524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2525 | struct drm_crtc *crtc; | |
2526 | ||
2527 | /* | |
2528 | * Flips in the rings have been nuked by the reset, | |
2529 | * so complete all pending flips so that user space | |
2530 | * will get its events and not get stuck. | |
2531 | * | |
2532 | * Also update the base address of all primary | |
2533 | * planes to the the last fb to make sure we're | |
2534 | * showing the correct fb after a reset. | |
2535 | * | |
2536 | * Need to make two loops over the crtcs so that we | |
2537 | * don't try to grab a crtc mutex before the | |
2538 | * pending_flip_queue really got woken up. | |
2539 | */ | |
2540 | ||
70e1e0ec | 2541 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2542 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2543 | enum plane plane = intel_crtc->plane; | |
2544 | ||
2545 | intel_prepare_page_flip(dev, plane); | |
2546 | intel_finish_page_flip_plane(dev, plane); | |
2547 | } | |
2548 | ||
70e1e0ec | 2549 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2551 | ||
2552 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2553 | /* |
2554 | * FIXME: Once we have proper support for primary planes (and | |
2555 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2556 | * a NULL crtc->primary->fb. |
947fdaad | 2557 | */ |
f4510a27 | 2558 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2559 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2560 | crtc->primary->fb, |
262ca2b0 MR |
2561 | crtc->x, |
2562 | crtc->y); | |
96a02917 VS |
2563 | mutex_unlock(&crtc->mutex); |
2564 | } | |
2565 | } | |
2566 | ||
14667a4b CW |
2567 | static int |
2568 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2569 | { | |
2570 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2571 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2572 | bool was_interruptible = dev_priv->mm.interruptible; | |
2573 | int ret; | |
2574 | ||
14667a4b CW |
2575 | /* Big Hammer, we also need to ensure that any pending |
2576 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2577 | * current scanout is retired before unpinning the old | |
2578 | * framebuffer. | |
2579 | * | |
2580 | * This should only fail upon a hung GPU, in which case we | |
2581 | * can safely continue. | |
2582 | */ | |
2583 | dev_priv->mm.interruptible = false; | |
2584 | ret = i915_gem_object_finish_gpu(obj); | |
2585 | dev_priv->mm.interruptible = was_interruptible; | |
2586 | ||
2587 | return ret; | |
2588 | } | |
2589 | ||
7d5e3799 CW |
2590 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2591 | { | |
2592 | struct drm_device *dev = crtc->dev; | |
2593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2594 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2595 | unsigned long flags; | |
2596 | bool pending; | |
2597 | ||
2598 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2599 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2600 | return false; | |
2601 | ||
2602 | spin_lock_irqsave(&dev->event_lock, flags); | |
2603 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2604 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2605 | ||
2606 | return pending; | |
2607 | } | |
2608 | ||
5c3b82e2 | 2609 | static int |
3c4fdcfb | 2610 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2611 | struct drm_framebuffer *fb) |
79e53945 JB |
2612 | { |
2613 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2614 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2615 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2616 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2617 | int ret; |
79e53945 | 2618 | |
7d5e3799 CW |
2619 | if (intel_crtc_has_pending_flip(crtc)) { |
2620 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2621 | return -EBUSY; | |
2622 | } | |
2623 | ||
79e53945 | 2624 | /* no fb bound */ |
94352cf9 | 2625 | if (!fb) { |
a5071c2f | 2626 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2627 | return 0; |
2628 | } | |
2629 | ||
7eb552ae | 2630 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2631 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2632 | plane_name(intel_crtc->plane), | |
2633 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2634 | return -EINVAL; |
79e53945 JB |
2635 | } |
2636 | ||
5c3b82e2 | 2637 | mutex_lock(&dev->struct_mutex); |
265db958 | 2638 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2639 | to_intel_framebuffer(fb)->obj, |
919926ae | 2640 | NULL); |
8ac36ec1 | 2641 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2642 | if (ret != 0) { |
a5071c2f | 2643 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2644 | return ret; |
2645 | } | |
79e53945 | 2646 | |
bb2043de DL |
2647 | /* |
2648 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2649 | * that in compute_mode_changes we check the native mode (not the pfit | |
2650 | * mode) to see if we can flip rather than do a full mode set. In the | |
2651 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2652 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2653 | * sized surface. | |
2654 | * | |
2655 | * To fix this properly, we need to hoist the checks up into | |
2656 | * compute_mode_changes (or above), check the actual pfit state and | |
2657 | * whether the platform allows pfit disable with pipe active, and only | |
2658 | * then update the pipesrc and pfit state, even on the flip path. | |
2659 | */ | |
d330a953 | 2660 | if (i915.fastboot) { |
d7bf63f2 DL |
2661 | const struct drm_display_mode *adjusted_mode = |
2662 | &intel_crtc->config.adjusted_mode; | |
2663 | ||
4d6a3e63 | 2664 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2665 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2666 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2667 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2668 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2669 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2670 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2671 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2672 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2673 | } | |
0637d60d JB |
2674 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2675 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2676 | } |
2677 | ||
29b9bde6 | 2678 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2679 | |
f4510a27 MR |
2680 | old_fb = crtc->primary->fb; |
2681 | crtc->primary->fb = fb; | |
6c4c86f5 DV |
2682 | crtc->x = x; |
2683 | crtc->y = y; | |
94352cf9 | 2684 | |
b7f1de28 | 2685 | if (old_fb) { |
d7697eea DV |
2686 | if (intel_crtc->active && old_fb != fb) |
2687 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2688 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 2689 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
8ac36ec1 | 2690 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2691 | } |
652c393a | 2692 | |
8ac36ec1 | 2693 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2694 | intel_update_fbc(dev); |
4906557e | 2695 | intel_edp_psr_update(dev); |
5c3b82e2 | 2696 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2697 | |
5c3b82e2 | 2698 | return 0; |
79e53945 JB |
2699 | } |
2700 | ||
5e84e1a4 ZW |
2701 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2702 | { | |
2703 | struct drm_device *dev = crtc->dev; | |
2704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2706 | int pipe = intel_crtc->pipe; | |
2707 | u32 reg, temp; | |
2708 | ||
2709 | /* enable normal train */ | |
2710 | reg = FDI_TX_CTL(pipe); | |
2711 | temp = I915_READ(reg); | |
61e499bf | 2712 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2713 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2714 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2715 | } else { |
2716 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2717 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2718 | } |
5e84e1a4 ZW |
2719 | I915_WRITE(reg, temp); |
2720 | ||
2721 | reg = FDI_RX_CTL(pipe); | |
2722 | temp = I915_READ(reg); | |
2723 | if (HAS_PCH_CPT(dev)) { | |
2724 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2725 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2726 | } else { | |
2727 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2728 | temp |= FDI_LINK_TRAIN_NONE; | |
2729 | } | |
2730 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2731 | ||
2732 | /* wait one idle pattern time */ | |
2733 | POSTING_READ(reg); | |
2734 | udelay(1000); | |
357555c0 JB |
2735 | |
2736 | /* IVB wants error correction enabled */ | |
2737 | if (IS_IVYBRIDGE(dev)) | |
2738 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2739 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2740 | } |
2741 | ||
1fbc0d78 | 2742 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2743 | { |
1fbc0d78 DV |
2744 | return crtc->base.enabled && crtc->active && |
2745 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2746 | } |
2747 | ||
01a415fd DV |
2748 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2749 | { | |
2750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2751 | struct intel_crtc *pipe_B_crtc = | |
2752 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2753 | struct intel_crtc *pipe_C_crtc = | |
2754 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2755 | uint32_t temp; | |
2756 | ||
1e833f40 DV |
2757 | /* |
2758 | * When everything is off disable fdi C so that we could enable fdi B | |
2759 | * with all lanes. Note that we don't care about enabled pipes without | |
2760 | * an enabled pch encoder. | |
2761 | */ | |
2762 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2763 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2764 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2765 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2766 | ||
2767 | temp = I915_READ(SOUTH_CHICKEN1); | |
2768 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2769 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2770 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2771 | } | |
2772 | } | |
2773 | ||
8db9d77b ZW |
2774 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2775 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2776 | { | |
2777 | struct drm_device *dev = crtc->dev; | |
2778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2780 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2781 | u32 reg, temp, tries; |
8db9d77b | 2782 | |
1c8562f6 | 2783 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2784 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2785 | |
e1a44743 AJ |
2786 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2787 | for train result */ | |
5eddb70b CW |
2788 | reg = FDI_RX_IMR(pipe); |
2789 | temp = I915_READ(reg); | |
e1a44743 AJ |
2790 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2791 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2792 | I915_WRITE(reg, temp); |
2793 | I915_READ(reg); | |
e1a44743 AJ |
2794 | udelay(150); |
2795 | ||
8db9d77b | 2796 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2797 | reg = FDI_TX_CTL(pipe); |
2798 | temp = I915_READ(reg); | |
627eb5a3 DV |
2799 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2800 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2801 | temp &= ~FDI_LINK_TRAIN_NONE; |
2802 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2803 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2804 | |
5eddb70b CW |
2805 | reg = FDI_RX_CTL(pipe); |
2806 | temp = I915_READ(reg); | |
8db9d77b ZW |
2807 | temp &= ~FDI_LINK_TRAIN_NONE; |
2808 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2809 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2810 | ||
2811 | POSTING_READ(reg); | |
8db9d77b ZW |
2812 | udelay(150); |
2813 | ||
5b2adf89 | 2814 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2815 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2816 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2817 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2818 | |
5eddb70b | 2819 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2820 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2821 | temp = I915_READ(reg); |
8db9d77b ZW |
2822 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2823 | ||
2824 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2825 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2826 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2827 | break; |
2828 | } | |
8db9d77b | 2829 | } |
e1a44743 | 2830 | if (tries == 5) |
5eddb70b | 2831 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2832 | |
2833 | /* Train 2 */ | |
5eddb70b CW |
2834 | reg = FDI_TX_CTL(pipe); |
2835 | temp = I915_READ(reg); | |
8db9d77b ZW |
2836 | temp &= ~FDI_LINK_TRAIN_NONE; |
2837 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2838 | I915_WRITE(reg, temp); |
8db9d77b | 2839 | |
5eddb70b CW |
2840 | reg = FDI_RX_CTL(pipe); |
2841 | temp = I915_READ(reg); | |
8db9d77b ZW |
2842 | temp &= ~FDI_LINK_TRAIN_NONE; |
2843 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2844 | I915_WRITE(reg, temp); |
8db9d77b | 2845 | |
5eddb70b CW |
2846 | POSTING_READ(reg); |
2847 | udelay(150); | |
8db9d77b | 2848 | |
5eddb70b | 2849 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2850 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2851 | temp = I915_READ(reg); |
8db9d77b ZW |
2852 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2853 | ||
2854 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2855 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2856 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2857 | break; | |
2858 | } | |
8db9d77b | 2859 | } |
e1a44743 | 2860 | if (tries == 5) |
5eddb70b | 2861 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2862 | |
2863 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2864 | |
8db9d77b ZW |
2865 | } |
2866 | ||
0206e353 | 2867 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2868 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2869 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2870 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2871 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2872 | }; | |
2873 | ||
2874 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2875 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2876 | { | |
2877 | struct drm_device *dev = crtc->dev; | |
2878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2879 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2880 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2881 | u32 reg, temp, i, retry; |
8db9d77b | 2882 | |
e1a44743 AJ |
2883 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2884 | for train result */ | |
5eddb70b CW |
2885 | reg = FDI_RX_IMR(pipe); |
2886 | temp = I915_READ(reg); | |
e1a44743 AJ |
2887 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2888 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2889 | I915_WRITE(reg, temp); |
2890 | ||
2891 | POSTING_READ(reg); | |
e1a44743 AJ |
2892 | udelay(150); |
2893 | ||
8db9d77b | 2894 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2895 | reg = FDI_TX_CTL(pipe); |
2896 | temp = I915_READ(reg); | |
627eb5a3 DV |
2897 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2898 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2899 | temp &= ~FDI_LINK_TRAIN_NONE; |
2900 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2901 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2902 | /* SNB-B */ | |
2903 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2904 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2905 | |
d74cf324 DV |
2906 | I915_WRITE(FDI_RX_MISC(pipe), |
2907 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2908 | ||
5eddb70b CW |
2909 | reg = FDI_RX_CTL(pipe); |
2910 | temp = I915_READ(reg); | |
8db9d77b ZW |
2911 | if (HAS_PCH_CPT(dev)) { |
2912 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2913 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2914 | } else { | |
2915 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2916 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2917 | } | |
5eddb70b CW |
2918 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2919 | ||
2920 | POSTING_READ(reg); | |
8db9d77b ZW |
2921 | udelay(150); |
2922 | ||
0206e353 | 2923 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2924 | reg = FDI_TX_CTL(pipe); |
2925 | temp = I915_READ(reg); | |
8db9d77b ZW |
2926 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2927 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2928 | I915_WRITE(reg, temp); |
2929 | ||
2930 | POSTING_READ(reg); | |
8db9d77b ZW |
2931 | udelay(500); |
2932 | ||
fa37d39e SP |
2933 | for (retry = 0; retry < 5; retry++) { |
2934 | reg = FDI_RX_IIR(pipe); | |
2935 | temp = I915_READ(reg); | |
2936 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2937 | if (temp & FDI_RX_BIT_LOCK) { | |
2938 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2939 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2940 | break; | |
2941 | } | |
2942 | udelay(50); | |
8db9d77b | 2943 | } |
fa37d39e SP |
2944 | if (retry < 5) |
2945 | break; | |
8db9d77b ZW |
2946 | } |
2947 | if (i == 4) | |
5eddb70b | 2948 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2949 | |
2950 | /* Train 2 */ | |
5eddb70b CW |
2951 | reg = FDI_TX_CTL(pipe); |
2952 | temp = I915_READ(reg); | |
8db9d77b ZW |
2953 | temp &= ~FDI_LINK_TRAIN_NONE; |
2954 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2955 | if (IS_GEN6(dev)) { | |
2956 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2957 | /* SNB-B */ | |
2958 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2959 | } | |
5eddb70b | 2960 | I915_WRITE(reg, temp); |
8db9d77b | 2961 | |
5eddb70b CW |
2962 | reg = FDI_RX_CTL(pipe); |
2963 | temp = I915_READ(reg); | |
8db9d77b ZW |
2964 | if (HAS_PCH_CPT(dev)) { |
2965 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2966 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2967 | } else { | |
2968 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2969 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2970 | } | |
5eddb70b CW |
2971 | I915_WRITE(reg, temp); |
2972 | ||
2973 | POSTING_READ(reg); | |
8db9d77b ZW |
2974 | udelay(150); |
2975 | ||
0206e353 | 2976 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2977 | reg = FDI_TX_CTL(pipe); |
2978 | temp = I915_READ(reg); | |
8db9d77b ZW |
2979 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2980 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2981 | I915_WRITE(reg, temp); |
2982 | ||
2983 | POSTING_READ(reg); | |
8db9d77b ZW |
2984 | udelay(500); |
2985 | ||
fa37d39e SP |
2986 | for (retry = 0; retry < 5; retry++) { |
2987 | reg = FDI_RX_IIR(pipe); | |
2988 | temp = I915_READ(reg); | |
2989 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2990 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2991 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2992 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2993 | break; | |
2994 | } | |
2995 | udelay(50); | |
8db9d77b | 2996 | } |
fa37d39e SP |
2997 | if (retry < 5) |
2998 | break; | |
8db9d77b ZW |
2999 | } |
3000 | if (i == 4) | |
5eddb70b | 3001 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3002 | |
3003 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3004 | } | |
3005 | ||
357555c0 JB |
3006 | /* Manual link training for Ivy Bridge A0 parts */ |
3007 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3008 | { | |
3009 | struct drm_device *dev = crtc->dev; | |
3010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3012 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3013 | u32 reg, temp, i, j; |
357555c0 JB |
3014 | |
3015 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3016 | for train result */ | |
3017 | reg = FDI_RX_IMR(pipe); | |
3018 | temp = I915_READ(reg); | |
3019 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3020 | temp &= ~FDI_RX_BIT_LOCK; | |
3021 | I915_WRITE(reg, temp); | |
3022 | ||
3023 | POSTING_READ(reg); | |
3024 | udelay(150); | |
3025 | ||
01a415fd DV |
3026 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3027 | I915_READ(FDI_RX_IIR(pipe))); | |
3028 | ||
139ccd3f JB |
3029 | /* Try each vswing and preemphasis setting twice before moving on */ |
3030 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3031 | /* disable first in case we need to retry */ | |
3032 | reg = FDI_TX_CTL(pipe); | |
3033 | temp = I915_READ(reg); | |
3034 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3035 | temp &= ~FDI_TX_ENABLE; | |
3036 | I915_WRITE(reg, temp); | |
357555c0 | 3037 | |
139ccd3f JB |
3038 | reg = FDI_RX_CTL(pipe); |
3039 | temp = I915_READ(reg); | |
3040 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3041 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3042 | temp &= ~FDI_RX_ENABLE; | |
3043 | I915_WRITE(reg, temp); | |
357555c0 | 3044 | |
139ccd3f | 3045 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3046 | reg = FDI_TX_CTL(pipe); |
3047 | temp = I915_READ(reg); | |
139ccd3f JB |
3048 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3049 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3050 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3051 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3052 | temp |= snb_b_fdi_train_param[j/2]; |
3053 | temp |= FDI_COMPOSITE_SYNC; | |
3054 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3055 | |
139ccd3f JB |
3056 | I915_WRITE(FDI_RX_MISC(pipe), |
3057 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3058 | |
139ccd3f | 3059 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3060 | temp = I915_READ(reg); |
139ccd3f JB |
3061 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3062 | temp |= FDI_COMPOSITE_SYNC; | |
3063 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3064 | |
139ccd3f JB |
3065 | POSTING_READ(reg); |
3066 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3067 | |
139ccd3f JB |
3068 | for (i = 0; i < 4; i++) { |
3069 | reg = FDI_RX_IIR(pipe); | |
3070 | temp = I915_READ(reg); | |
3071 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3072 | |
139ccd3f JB |
3073 | if (temp & FDI_RX_BIT_LOCK || |
3074 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3075 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3076 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3077 | i); | |
3078 | break; | |
3079 | } | |
3080 | udelay(1); /* should be 0.5us */ | |
3081 | } | |
3082 | if (i == 4) { | |
3083 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3084 | continue; | |
3085 | } | |
357555c0 | 3086 | |
139ccd3f | 3087 | /* Train 2 */ |
357555c0 JB |
3088 | reg = FDI_TX_CTL(pipe); |
3089 | temp = I915_READ(reg); | |
139ccd3f JB |
3090 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3091 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3092 | I915_WRITE(reg, temp); | |
3093 | ||
3094 | reg = FDI_RX_CTL(pipe); | |
3095 | temp = I915_READ(reg); | |
3096 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3097 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3098 | I915_WRITE(reg, temp); |
3099 | ||
3100 | POSTING_READ(reg); | |
139ccd3f | 3101 | udelay(2); /* should be 1.5us */ |
357555c0 | 3102 | |
139ccd3f JB |
3103 | for (i = 0; i < 4; i++) { |
3104 | reg = FDI_RX_IIR(pipe); | |
3105 | temp = I915_READ(reg); | |
3106 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3107 | |
139ccd3f JB |
3108 | if (temp & FDI_RX_SYMBOL_LOCK || |
3109 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3110 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3111 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3112 | i); | |
3113 | goto train_done; | |
3114 | } | |
3115 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3116 | } |
139ccd3f JB |
3117 | if (i == 4) |
3118 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3119 | } |
357555c0 | 3120 | |
139ccd3f | 3121 | train_done: |
357555c0 JB |
3122 | DRM_DEBUG_KMS("FDI train done.\n"); |
3123 | } | |
3124 | ||
88cefb6c | 3125 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3126 | { |
88cefb6c | 3127 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3128 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3129 | int pipe = intel_crtc->pipe; |
5eddb70b | 3130 | u32 reg, temp; |
79e53945 | 3131 | |
c64e311e | 3132 | |
c98e9dcf | 3133 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3134 | reg = FDI_RX_CTL(pipe); |
3135 | temp = I915_READ(reg); | |
627eb5a3 DV |
3136 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3137 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3138 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3139 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3140 | ||
3141 | POSTING_READ(reg); | |
c98e9dcf JB |
3142 | udelay(200); |
3143 | ||
3144 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3145 | temp = I915_READ(reg); |
3146 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3147 | ||
3148 | POSTING_READ(reg); | |
c98e9dcf JB |
3149 | udelay(200); |
3150 | ||
20749730 PZ |
3151 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3152 | reg = FDI_TX_CTL(pipe); | |
3153 | temp = I915_READ(reg); | |
3154 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3155 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3156 | |
20749730 PZ |
3157 | POSTING_READ(reg); |
3158 | udelay(100); | |
6be4a607 | 3159 | } |
0e23b99d JB |
3160 | } |
3161 | ||
88cefb6c DV |
3162 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3163 | { | |
3164 | struct drm_device *dev = intel_crtc->base.dev; | |
3165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3166 | int pipe = intel_crtc->pipe; | |
3167 | u32 reg, temp; | |
3168 | ||
3169 | /* Switch from PCDclk to Rawclk */ | |
3170 | reg = FDI_RX_CTL(pipe); | |
3171 | temp = I915_READ(reg); | |
3172 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3173 | ||
3174 | /* Disable CPU FDI TX PLL */ | |
3175 | reg = FDI_TX_CTL(pipe); | |
3176 | temp = I915_READ(reg); | |
3177 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3178 | ||
3179 | POSTING_READ(reg); | |
3180 | udelay(100); | |
3181 | ||
3182 | reg = FDI_RX_CTL(pipe); | |
3183 | temp = I915_READ(reg); | |
3184 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3185 | ||
3186 | /* Wait for the clocks to turn off. */ | |
3187 | POSTING_READ(reg); | |
3188 | udelay(100); | |
3189 | } | |
3190 | ||
0fc932b8 JB |
3191 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3192 | { | |
3193 | struct drm_device *dev = crtc->dev; | |
3194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3196 | int pipe = intel_crtc->pipe; | |
3197 | u32 reg, temp; | |
3198 | ||
3199 | /* disable CPU FDI tx and PCH FDI rx */ | |
3200 | reg = FDI_TX_CTL(pipe); | |
3201 | temp = I915_READ(reg); | |
3202 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3203 | POSTING_READ(reg); | |
3204 | ||
3205 | reg = FDI_RX_CTL(pipe); | |
3206 | temp = I915_READ(reg); | |
3207 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3208 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3209 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3210 | ||
3211 | POSTING_READ(reg); | |
3212 | udelay(100); | |
3213 | ||
3214 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
3215 | if (HAS_PCH_IBX(dev)) { |
3216 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 3217 | } |
0fc932b8 JB |
3218 | |
3219 | /* still set train pattern 1 */ | |
3220 | reg = FDI_TX_CTL(pipe); | |
3221 | temp = I915_READ(reg); | |
3222 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3223 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3224 | I915_WRITE(reg, temp); | |
3225 | ||
3226 | reg = FDI_RX_CTL(pipe); | |
3227 | temp = I915_READ(reg); | |
3228 | if (HAS_PCH_CPT(dev)) { | |
3229 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3230 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3231 | } else { | |
3232 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3233 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3234 | } | |
3235 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3236 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3237 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3238 | I915_WRITE(reg, temp); |
3239 | ||
3240 | POSTING_READ(reg); | |
3241 | udelay(100); | |
3242 | } | |
3243 | ||
5dce5b93 CW |
3244 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3245 | { | |
3246 | struct intel_crtc *crtc; | |
3247 | ||
3248 | /* Note that we don't need to be called with mode_config.lock here | |
3249 | * as our list of CRTC objects is static for the lifetime of the | |
3250 | * device and so cannot disappear as we iterate. Similarly, we can | |
3251 | * happily treat the predicates as racy, atomic checks as userspace | |
3252 | * cannot claim and pin a new fb without at least acquring the | |
3253 | * struct_mutex and so serialising with us. | |
3254 | */ | |
d3fcc808 | 3255 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3256 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3257 | continue; | |
3258 | ||
3259 | if (crtc->unpin_work) | |
3260 | intel_wait_for_vblank(dev, crtc->pipe); | |
3261 | ||
3262 | return true; | |
3263 | } | |
3264 | ||
3265 | return false; | |
3266 | } | |
3267 | ||
e6c3a2a6 CW |
3268 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3269 | { | |
0f91128d | 3270 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3271 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3272 | |
f4510a27 | 3273 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3274 | return; |
3275 | ||
2c10d571 DV |
3276 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3277 | ||
5bb61643 CW |
3278 | wait_event(dev_priv->pending_flip_queue, |
3279 | !intel_crtc_has_pending_flip(crtc)); | |
3280 | ||
0f91128d | 3281 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3282 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3283 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3284 | } |
3285 | ||
e615efe4 ED |
3286 | /* Program iCLKIP clock to the desired frequency */ |
3287 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3288 | { | |
3289 | struct drm_device *dev = crtc->dev; | |
3290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3291 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3292 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3293 | u32 temp; | |
3294 | ||
09153000 DV |
3295 | mutex_lock(&dev_priv->dpio_lock); |
3296 | ||
e615efe4 ED |
3297 | /* It is necessary to ungate the pixclk gate prior to programming |
3298 | * the divisors, and gate it back when it is done. | |
3299 | */ | |
3300 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3301 | ||
3302 | /* Disable SSCCTL */ | |
3303 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3304 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3305 | SBI_SSCCTL_DISABLE, | |
3306 | SBI_ICLK); | |
e615efe4 ED |
3307 | |
3308 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3309 | if (clock == 20000) { |
e615efe4 ED |
3310 | auxdiv = 1; |
3311 | divsel = 0x41; | |
3312 | phaseinc = 0x20; | |
3313 | } else { | |
3314 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3315 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3316 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3317 | * convert the virtual clock precision to KHz here for higher |
3318 | * precision. | |
3319 | */ | |
3320 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3321 | u32 iclk_pi_range = 64; | |
3322 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3323 | ||
12d7ceed | 3324 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3325 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3326 | pi_value = desired_divisor % iclk_pi_range; | |
3327 | ||
3328 | auxdiv = 0; | |
3329 | divsel = msb_divisor_value - 2; | |
3330 | phaseinc = pi_value; | |
3331 | } | |
3332 | ||
3333 | /* This should not happen with any sane values */ | |
3334 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3335 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3336 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3337 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3338 | ||
3339 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3340 | clock, |
e615efe4 ED |
3341 | auxdiv, |
3342 | divsel, | |
3343 | phasedir, | |
3344 | phaseinc); | |
3345 | ||
3346 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3347 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3348 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3349 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3350 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3351 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3352 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3353 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3354 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3355 | |
3356 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3357 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3358 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3359 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3360 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3361 | |
3362 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3363 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3364 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3365 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3366 | |
3367 | /* Wait for initialization time */ | |
3368 | udelay(24); | |
3369 | ||
3370 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3371 | |
3372 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3373 | } |
3374 | ||
275f01b2 DV |
3375 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3376 | enum pipe pch_transcoder) | |
3377 | { | |
3378 | struct drm_device *dev = crtc->base.dev; | |
3379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3380 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3381 | ||
3382 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3383 | I915_READ(HTOTAL(cpu_transcoder))); | |
3384 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3385 | I915_READ(HBLANK(cpu_transcoder))); | |
3386 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3387 | I915_READ(HSYNC(cpu_transcoder))); | |
3388 | ||
3389 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3390 | I915_READ(VTOTAL(cpu_transcoder))); | |
3391 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3392 | I915_READ(VBLANK(cpu_transcoder))); | |
3393 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3394 | I915_READ(VSYNC(cpu_transcoder))); | |
3395 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3396 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3397 | } | |
3398 | ||
1fbc0d78 DV |
3399 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3400 | { | |
3401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3402 | uint32_t temp; | |
3403 | ||
3404 | temp = I915_READ(SOUTH_CHICKEN1); | |
3405 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3406 | return; | |
3407 | ||
3408 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3409 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3410 | ||
3411 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3412 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3413 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3414 | POSTING_READ(SOUTH_CHICKEN1); | |
3415 | } | |
3416 | ||
3417 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3418 | { | |
3419 | struct drm_device *dev = intel_crtc->base.dev; | |
3420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3421 | ||
3422 | switch (intel_crtc->pipe) { | |
3423 | case PIPE_A: | |
3424 | break; | |
3425 | case PIPE_B: | |
3426 | if (intel_crtc->config.fdi_lanes > 2) | |
3427 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3428 | else | |
3429 | cpt_enable_fdi_bc_bifurcation(dev); | |
3430 | ||
3431 | break; | |
3432 | case PIPE_C: | |
3433 | cpt_enable_fdi_bc_bifurcation(dev); | |
3434 | ||
3435 | break; | |
3436 | default: | |
3437 | BUG(); | |
3438 | } | |
3439 | } | |
3440 | ||
f67a559d JB |
3441 | /* |
3442 | * Enable PCH resources required for PCH ports: | |
3443 | * - PCH PLLs | |
3444 | * - FDI training & RX/TX | |
3445 | * - update transcoder timings | |
3446 | * - DP transcoding bits | |
3447 | * - transcoder | |
3448 | */ | |
3449 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3450 | { |
3451 | struct drm_device *dev = crtc->dev; | |
3452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3454 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3455 | u32 reg, temp; |
2c07245f | 3456 | |
ab9412ba | 3457 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3458 | |
1fbc0d78 DV |
3459 | if (IS_IVYBRIDGE(dev)) |
3460 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3461 | ||
cd986abb DV |
3462 | /* Write the TU size bits before fdi link training, so that error |
3463 | * detection works. */ | |
3464 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3465 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3466 | ||
c98e9dcf | 3467 | /* For PCH output, training FDI link */ |
674cf967 | 3468 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3469 | |
3ad8a208 DV |
3470 | /* We need to program the right clock selection before writing the pixel |
3471 | * mutliplier into the DPLL. */ | |
303b81e0 | 3472 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3473 | u32 sel; |
4b645f14 | 3474 | |
c98e9dcf | 3475 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3476 | temp |= TRANS_DPLL_ENABLE(pipe); |
3477 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3478 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3479 | temp |= sel; |
3480 | else | |
3481 | temp &= ~sel; | |
c98e9dcf | 3482 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3483 | } |
5eddb70b | 3484 | |
3ad8a208 DV |
3485 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3486 | * transcoder, and we actually should do this to not upset any PCH | |
3487 | * transcoder that already use the clock when we share it. | |
3488 | * | |
3489 | * Note that enable_shared_dpll tries to do the right thing, but | |
3490 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3491 | * the right LVDS enable sequence. */ | |
3492 | ironlake_enable_shared_dpll(intel_crtc); | |
3493 | ||
d9b6cb56 JB |
3494 | /* set transcoder timing, panel must allow it */ |
3495 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3496 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3497 | |
303b81e0 | 3498 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3499 | |
c98e9dcf JB |
3500 | /* For PCH DP, enable TRANS_DP_CTL */ |
3501 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3502 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3503 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3504 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3505 | reg = TRANS_DP_CTL(pipe); |
3506 | temp = I915_READ(reg); | |
3507 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3508 | TRANS_DP_SYNC_MASK | |
3509 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3510 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3511 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3512 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3513 | |
3514 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3515 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3516 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3517 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3518 | |
3519 | switch (intel_trans_dp_port_sel(crtc)) { | |
3520 | case PCH_DP_B: | |
5eddb70b | 3521 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3522 | break; |
3523 | case PCH_DP_C: | |
5eddb70b | 3524 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3525 | break; |
3526 | case PCH_DP_D: | |
5eddb70b | 3527 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3528 | break; |
3529 | default: | |
e95d41e1 | 3530 | BUG(); |
32f9d658 | 3531 | } |
2c07245f | 3532 | |
5eddb70b | 3533 | I915_WRITE(reg, temp); |
6be4a607 | 3534 | } |
b52eb4dc | 3535 | |
b8a4f404 | 3536 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3537 | } |
3538 | ||
1507e5bd PZ |
3539 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3540 | { | |
3541 | struct drm_device *dev = crtc->dev; | |
3542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3543 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3544 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3545 | |
ab9412ba | 3546 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3547 | |
8c52b5e8 | 3548 | lpt_program_iclkip(crtc); |
1507e5bd | 3549 | |
0540e488 | 3550 | /* Set transcoder timing. */ |
275f01b2 | 3551 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3552 | |
937bb610 | 3553 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3554 | } |
3555 | ||
e2b78267 | 3556 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3557 | { |
e2b78267 | 3558 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3559 | |
3560 | if (pll == NULL) | |
3561 | return; | |
3562 | ||
3563 | if (pll->refcount == 0) { | |
46edb027 | 3564 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3565 | return; |
3566 | } | |
3567 | ||
f4a091c7 DV |
3568 | if (--pll->refcount == 0) { |
3569 | WARN_ON(pll->on); | |
3570 | WARN_ON(pll->active); | |
3571 | } | |
3572 | ||
a43f6e0f | 3573 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3574 | } |
3575 | ||
b89a1d39 | 3576 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3577 | { |
e2b78267 DV |
3578 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3579 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3580 | enum intel_dpll_id i; | |
ee7b9f93 | 3581 | |
ee7b9f93 | 3582 | if (pll) { |
46edb027 DV |
3583 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3584 | crtc->base.base.id, pll->name); | |
e2b78267 | 3585 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3586 | } |
3587 | ||
98b6bd99 DV |
3588 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3589 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3590 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3591 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3592 | |
46edb027 DV |
3593 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3594 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3595 | |
3596 | goto found; | |
3597 | } | |
3598 | ||
e72f9fbf DV |
3599 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3600 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3601 | |
3602 | /* Only want to check enabled timings first */ | |
3603 | if (pll->refcount == 0) | |
3604 | continue; | |
3605 | ||
b89a1d39 DV |
3606 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3607 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3608 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3609 | crtc->base.base.id, |
46edb027 | 3610 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3611 | |
3612 | goto found; | |
3613 | } | |
3614 | } | |
3615 | ||
3616 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3617 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3618 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3619 | if (pll->refcount == 0) { |
46edb027 DV |
3620 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3621 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3622 | goto found; |
3623 | } | |
3624 | } | |
3625 | ||
3626 | return NULL; | |
3627 | ||
3628 | found: | |
a43f6e0f | 3629 | crtc->config.shared_dpll = i; |
46edb027 DV |
3630 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3631 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3632 | |
cdbd2316 | 3633 | if (pll->active == 0) { |
66e985c0 DV |
3634 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3635 | sizeof(pll->hw_state)); | |
3636 | ||
46edb027 | 3637 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3638 | WARN_ON(pll->on); |
e9d6944e | 3639 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3640 | |
15bdd4cf | 3641 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3642 | } |
3643 | pll->refcount++; | |
e04c7350 | 3644 | |
ee7b9f93 JB |
3645 | return pll; |
3646 | } | |
3647 | ||
a1520318 | 3648 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3649 | { |
3650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3651 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3652 | u32 temp; |
3653 | ||
3654 | temp = I915_READ(dslreg); | |
3655 | udelay(500); | |
3656 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3657 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3658 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3659 | } |
3660 | } | |
3661 | ||
b074cec8 JB |
3662 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3663 | { | |
3664 | struct drm_device *dev = crtc->base.dev; | |
3665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3666 | int pipe = crtc->pipe; | |
3667 | ||
fd4daa9c | 3668 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3669 | /* Force use of hard-coded filter coefficients |
3670 | * as some pre-programmed values are broken, | |
3671 | * e.g. x201. | |
3672 | */ | |
3673 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3674 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3675 | PF_PIPE_SEL_IVB(pipe)); | |
3676 | else | |
3677 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3678 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3679 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3680 | } |
3681 | } | |
3682 | ||
bb53d4ae VS |
3683 | static void intel_enable_planes(struct drm_crtc *crtc) |
3684 | { | |
3685 | struct drm_device *dev = crtc->dev; | |
3686 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3687 | struct drm_plane *plane; |
bb53d4ae VS |
3688 | struct intel_plane *intel_plane; |
3689 | ||
af2b653b MR |
3690 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3691 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3692 | if (intel_plane->pipe == pipe) |
3693 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3694 | } |
bb53d4ae VS |
3695 | } |
3696 | ||
3697 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3698 | { | |
3699 | struct drm_device *dev = crtc->dev; | |
3700 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3701 | struct drm_plane *plane; |
bb53d4ae VS |
3702 | struct intel_plane *intel_plane; |
3703 | ||
af2b653b MR |
3704 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3705 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3706 | if (intel_plane->pipe == pipe) |
3707 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3708 | } |
bb53d4ae VS |
3709 | } |
3710 | ||
20bc8673 | 3711 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3712 | { |
3713 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3714 | ||
3715 | if (!crtc->config.ips_enabled) | |
3716 | return; | |
3717 | ||
3718 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3719 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3720 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3721 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3722 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3723 | if (IS_BROADWELL(crtc->base.dev)) { |
3724 | mutex_lock(&dev_priv->rps.hw_lock); | |
3725 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3726 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3727 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3728 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3729 | * mailbox." Moreover, the mailbox may return a bogus state, |
3730 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3731 | */ |
3732 | } else { | |
3733 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3734 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3735 | * is essentially intel_wait_for_vblank. If we don't have this | |
3736 | * and don't wait for vblanks until the end of crtc_enable, then | |
3737 | * the HW state readout code will complain that the expected | |
3738 | * IPS_CTL value is not the one we read. */ | |
3739 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3740 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3741 | } | |
d77e4531 PZ |
3742 | } |
3743 | ||
20bc8673 | 3744 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3745 | { |
3746 | struct drm_device *dev = crtc->base.dev; | |
3747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3748 | ||
3749 | if (!crtc->config.ips_enabled) | |
3750 | return; | |
3751 | ||
3752 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3753 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3754 | mutex_lock(&dev_priv->rps.hw_lock); |
3755 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3756 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3757 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3758 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3759 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3760 | } else { |
2a114cc1 | 3761 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3762 | POSTING_READ(IPS_CTL); |
3763 | } | |
d77e4531 PZ |
3764 | |
3765 | /* We need to wait for a vblank before we can disable the plane. */ | |
3766 | intel_wait_for_vblank(dev, crtc->pipe); | |
3767 | } | |
3768 | ||
3769 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3770 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3771 | { | |
3772 | struct drm_device *dev = crtc->dev; | |
3773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3775 | enum pipe pipe = intel_crtc->pipe; | |
3776 | int palreg = PALETTE(pipe); | |
3777 | int i; | |
3778 | bool reenable_ips = false; | |
3779 | ||
3780 | /* The clocks have to be on to load the palette. */ | |
3781 | if (!crtc->enabled || !intel_crtc->active) | |
3782 | return; | |
3783 | ||
3784 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3785 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3786 | assert_dsi_pll_enabled(dev_priv); | |
3787 | else | |
3788 | assert_pll_enabled(dev_priv, pipe); | |
3789 | } | |
3790 | ||
3791 | /* use legacy palette for Ironlake */ | |
3792 | if (HAS_PCH_SPLIT(dev)) | |
3793 | palreg = LGC_PALETTE(pipe); | |
3794 | ||
3795 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3796 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3797 | */ | |
41e6fc4c | 3798 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3799 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3800 | GAMMA_MODE_MODE_SPLIT)) { | |
3801 | hsw_disable_ips(intel_crtc); | |
3802 | reenable_ips = true; | |
3803 | } | |
3804 | ||
3805 | for (i = 0; i < 256; i++) { | |
3806 | I915_WRITE(palreg + 4 * i, | |
3807 | (intel_crtc->lut_r[i] << 16) | | |
3808 | (intel_crtc->lut_g[i] << 8) | | |
3809 | intel_crtc->lut_b[i]); | |
3810 | } | |
3811 | ||
3812 | if (reenable_ips) | |
3813 | hsw_enable_ips(intel_crtc); | |
3814 | } | |
3815 | ||
d3eedb1a VS |
3816 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3817 | { | |
3818 | if (!enable && intel_crtc->overlay) { | |
3819 | struct drm_device *dev = intel_crtc->base.dev; | |
3820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3821 | ||
3822 | mutex_lock(&dev->struct_mutex); | |
3823 | dev_priv->mm.interruptible = false; | |
3824 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3825 | dev_priv->mm.interruptible = true; | |
3826 | mutex_unlock(&dev->struct_mutex); | |
3827 | } | |
3828 | ||
3829 | /* Let userspace switch the overlay on again. In most cases userspace | |
3830 | * has to recompute where to put it anyway. | |
3831 | */ | |
3832 | } | |
3833 | ||
3834 | /** | |
3835 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3836 | * cursor plane briefly if not already running after enabling the display | |
3837 | * plane. | |
3838 | * This workaround avoids occasional blank screens when self refresh is | |
3839 | * enabled. | |
3840 | */ | |
3841 | static void | |
3842 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3843 | { | |
3844 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3845 | ||
3846 | if ((cntl & CURSOR_MODE) == 0) { | |
3847 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3848 | ||
3849 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3850 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3851 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3852 | I915_WRITE(CURCNTR(pipe), cntl); | |
3853 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3854 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3855 | } | |
3856 | } | |
3857 | ||
3858 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
a5c4d7bc VS |
3859 | { |
3860 | struct drm_device *dev = crtc->dev; | |
3861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3863 | int pipe = intel_crtc->pipe; | |
3864 | int plane = intel_crtc->plane; | |
3865 | ||
3866 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); | |
3867 | intel_enable_planes(crtc); | |
d3eedb1a VS |
3868 | /* The fixup needs to happen before cursor is enabled */ |
3869 | if (IS_G4X(dev)) | |
3870 | g4x_fixup_plane(dev_priv, pipe); | |
a5c4d7bc | 3871 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 3872 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3873 | |
3874 | hsw_enable_ips(intel_crtc); | |
3875 | ||
3876 | mutex_lock(&dev->struct_mutex); | |
3877 | intel_update_fbc(dev); | |
3878 | mutex_unlock(&dev->struct_mutex); | |
3879 | } | |
3880 | ||
d3eedb1a | 3881 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3882 | { |
3883 | struct drm_device *dev = crtc->dev; | |
3884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3885 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3886 | int pipe = intel_crtc->pipe; | |
3887 | int plane = intel_crtc->plane; | |
3888 | ||
3889 | intel_crtc_wait_for_pending_flips(crtc); | |
3890 | drm_vblank_off(dev, pipe); | |
3891 | ||
3892 | if (dev_priv->fbc.plane == plane) | |
3893 | intel_disable_fbc(dev); | |
3894 | ||
3895 | hsw_disable_ips(intel_crtc); | |
3896 | ||
d3eedb1a | 3897 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3898 | intel_crtc_update_cursor(crtc, false); |
3899 | intel_disable_planes(crtc); | |
3900 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
3901 | } | |
3902 | ||
f67a559d JB |
3903 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3904 | { | |
3905 | struct drm_device *dev = crtc->dev; | |
3906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3908 | struct intel_encoder *encoder; |
f67a559d | 3909 | int pipe = intel_crtc->pipe; |
f67a559d | 3910 | |
08a48469 DV |
3911 | WARN_ON(!crtc->enabled); |
3912 | ||
f67a559d JB |
3913 | if (intel_crtc->active) |
3914 | return; | |
3915 | ||
3916 | intel_crtc->active = true; | |
8664281b PZ |
3917 | |
3918 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3919 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3920 | ||
f6736a1a | 3921 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3922 | if (encoder->pre_enable) |
3923 | encoder->pre_enable(encoder); | |
f67a559d | 3924 | |
5bfe2ac0 | 3925 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3926 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3927 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3928 | * enabling. */ | |
88cefb6c | 3929 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3930 | } else { |
3931 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3932 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3933 | } | |
f67a559d | 3934 | |
b074cec8 | 3935 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3936 | |
9c54c0dd JB |
3937 | /* |
3938 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3939 | * clocks enabled | |
3940 | */ | |
3941 | intel_crtc_load_lut(crtc); | |
3942 | ||
f37fcc2a | 3943 | intel_update_watermarks(crtc); |
e1fdc473 | 3944 | intel_enable_pipe(intel_crtc); |
f67a559d | 3945 | |
5bfe2ac0 | 3946 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3947 | ironlake_pch_enable(crtc); |
c98e9dcf | 3948 | |
fa5c73b1 DV |
3949 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3950 | encoder->enable(encoder); | |
61b77ddd DV |
3951 | |
3952 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3953 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 3954 | |
d3eedb1a | 3955 | intel_crtc_enable_planes(crtc); |
a5c4d7bc | 3956 | |
6ce94100 DV |
3957 | /* |
3958 | * There seems to be a race in PCH platform hw (at least on some | |
3959 | * outputs) where an enabled pipe still completes any pageflip right | |
3960 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3961 | * as the first vblank happend, everything works as expected. Hence just | |
3962 | * wait for one vblank before returning to avoid strange things | |
3963 | * happening. | |
3964 | */ | |
3965 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3966 | } |
3967 | ||
42db64ef PZ |
3968 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3969 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3970 | { | |
f5adf94e | 3971 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3972 | } |
3973 | ||
e4916946 PZ |
3974 | /* |
3975 | * This implements the workaround described in the "notes" section of the mode | |
3976 | * set sequence documentation. When going from no pipes or single pipe to | |
3977 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3978 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3979 | */ | |
3980 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3981 | { | |
3982 | struct drm_device *dev = crtc->base.dev; | |
3983 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3984 | ||
3985 | /* We want to get the other_active_crtc only if there's only 1 other | |
3986 | * active crtc. */ | |
d3fcc808 | 3987 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
3988 | if (!crtc_it->active || crtc_it == crtc) |
3989 | continue; | |
3990 | ||
3991 | if (other_active_crtc) | |
3992 | return; | |
3993 | ||
3994 | other_active_crtc = crtc_it; | |
3995 | } | |
3996 | if (!other_active_crtc) | |
3997 | return; | |
3998 | ||
3999 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4000 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4001 | } | |
4002 | ||
4f771f10 PZ |
4003 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4004 | { | |
4005 | struct drm_device *dev = crtc->dev; | |
4006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4008 | struct intel_encoder *encoder; | |
4009 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
4010 | |
4011 | WARN_ON(!crtc->enabled); | |
4012 | ||
4013 | if (intel_crtc->active) | |
4014 | return; | |
4015 | ||
4016 | intel_crtc->active = true; | |
8664281b PZ |
4017 | |
4018 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4019 | if (intel_crtc->config.has_pch_encoder) | |
4020 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4021 | ||
5bfe2ac0 | 4022 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 4023 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
4024 | |
4025 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4026 | if (encoder->pre_enable) | |
4027 | encoder->pre_enable(encoder); | |
4028 | ||
1f544388 | 4029 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4030 | |
b074cec8 | 4031 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4032 | |
4033 | /* | |
4034 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4035 | * clocks enabled | |
4036 | */ | |
4037 | intel_crtc_load_lut(crtc); | |
4038 | ||
1f544388 | 4039 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4040 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4041 | |
f37fcc2a | 4042 | intel_update_watermarks(crtc); |
e1fdc473 | 4043 | intel_enable_pipe(intel_crtc); |
42db64ef | 4044 | |
5bfe2ac0 | 4045 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4046 | lpt_pch_enable(crtc); |
4f771f10 | 4047 | |
8807e55b | 4048 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4049 | encoder->enable(encoder); |
8807e55b JN |
4050 | intel_opregion_notify_encoder(encoder, true); |
4051 | } | |
4f771f10 | 4052 | |
e4916946 PZ |
4053 | /* If we change the relative order between pipe/planes enabling, we need |
4054 | * to change the workaround. */ | |
4055 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4056 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4057 | } |
4058 | ||
3f8dce3a DV |
4059 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4060 | { | |
4061 | struct drm_device *dev = crtc->base.dev; | |
4062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4063 | int pipe = crtc->pipe; | |
4064 | ||
4065 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4066 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4067 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4068 | I915_WRITE(PF_CTL(pipe), 0); |
4069 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4070 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4071 | } | |
4072 | } | |
4073 | ||
6be4a607 JB |
4074 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4075 | { | |
4076 | struct drm_device *dev = crtc->dev; | |
4077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4079 | struct intel_encoder *encoder; |
6be4a607 | 4080 | int pipe = intel_crtc->pipe; |
5eddb70b | 4081 | u32 reg, temp; |
b52eb4dc | 4082 | |
f7abfe8b CW |
4083 | if (!intel_crtc->active) |
4084 | return; | |
4085 | ||
d3eedb1a | 4086 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4087 | |
ea9d758d DV |
4088 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4089 | encoder->disable(encoder); | |
4090 | ||
d925c59a DV |
4091 | if (intel_crtc->config.has_pch_encoder) |
4092 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4093 | ||
b24e7179 | 4094 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4095 | |
3f8dce3a | 4096 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4097 | |
bf49ec8c DV |
4098 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4099 | if (encoder->post_disable) | |
4100 | encoder->post_disable(encoder); | |
2c07245f | 4101 | |
d925c59a DV |
4102 | if (intel_crtc->config.has_pch_encoder) { |
4103 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4104 | |
d925c59a DV |
4105 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4106 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4107 | |
d925c59a DV |
4108 | if (HAS_PCH_CPT(dev)) { |
4109 | /* disable TRANS_DP_CTL */ | |
4110 | reg = TRANS_DP_CTL(pipe); | |
4111 | temp = I915_READ(reg); | |
4112 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4113 | TRANS_DP_PORT_SEL_MASK); | |
4114 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4115 | I915_WRITE(reg, temp); | |
4116 | ||
4117 | /* disable DPLL_SEL */ | |
4118 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4119 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4120 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4121 | } |
e3421a18 | 4122 | |
d925c59a | 4123 | /* disable PCH DPLL */ |
e72f9fbf | 4124 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4125 | |
d925c59a DV |
4126 | ironlake_fdi_pll_disable(intel_crtc); |
4127 | } | |
6b383a7f | 4128 | |
f7abfe8b | 4129 | intel_crtc->active = false; |
46ba614c | 4130 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4131 | |
4132 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4133 | intel_update_fbc(dev); |
d1ebd816 | 4134 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4135 | } |
1b3c7a47 | 4136 | |
4f771f10 | 4137 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4138 | { |
4f771f10 PZ |
4139 | struct drm_device *dev = crtc->dev; |
4140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4142 | struct intel_encoder *encoder; |
4143 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4144 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4145 | |
4f771f10 PZ |
4146 | if (!intel_crtc->active) |
4147 | return; | |
4148 | ||
d3eedb1a | 4149 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4150 | |
8807e55b JN |
4151 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4152 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4153 | encoder->disable(encoder); |
8807e55b | 4154 | } |
4f771f10 | 4155 | |
8664281b PZ |
4156 | if (intel_crtc->config.has_pch_encoder) |
4157 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4158 | intel_disable_pipe(dev_priv, pipe); |
4159 | ||
ad80a810 | 4160 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4161 | |
3f8dce3a | 4162 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4163 | |
1f544388 | 4164 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
4165 | |
4166 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4167 | if (encoder->post_disable) | |
4168 | encoder->post_disable(encoder); | |
4169 | ||
88adfff1 | 4170 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4171 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4172 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4173 | intel_ddi_fdi_disable(crtc); |
83616634 | 4174 | } |
4f771f10 PZ |
4175 | |
4176 | intel_crtc->active = false; | |
46ba614c | 4177 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4178 | |
4179 | mutex_lock(&dev->struct_mutex); | |
4180 | intel_update_fbc(dev); | |
4181 | mutex_unlock(&dev->struct_mutex); | |
4182 | } | |
4183 | ||
ee7b9f93 JB |
4184 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4185 | { | |
4186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4187 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4188 | } |
4189 | ||
6441ab5f PZ |
4190 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4191 | { | |
4192 | intel_ddi_put_crtc_pll(crtc); | |
4193 | } | |
4194 | ||
2dd24552 JB |
4195 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4196 | { | |
4197 | struct drm_device *dev = crtc->base.dev; | |
4198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4199 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4200 | ||
328d8e82 | 4201 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4202 | return; |
4203 | ||
2dd24552 | 4204 | /* |
c0b03411 DV |
4205 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4206 | * according to register description and PRM. | |
2dd24552 | 4207 | */ |
c0b03411 DV |
4208 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4209 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4210 | |
b074cec8 JB |
4211 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4212 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4213 | |
4214 | /* Border color in case we don't scale up to the full screen. Black by | |
4215 | * default, change to something else for debugging. */ | |
4216 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4217 | } |
4218 | ||
77d22dca ID |
4219 | #define for_each_power_domain(domain, mask) \ |
4220 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4221 | if ((1 << (domain)) & (mask)) | |
4222 | ||
319be8ae ID |
4223 | enum intel_display_power_domain |
4224 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4225 | { | |
4226 | struct drm_device *dev = intel_encoder->base.dev; | |
4227 | struct intel_digital_port *intel_dig_port; | |
4228 | ||
4229 | switch (intel_encoder->type) { | |
4230 | case INTEL_OUTPUT_UNKNOWN: | |
4231 | /* Only DDI platforms should ever use this output type */ | |
4232 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4233 | case INTEL_OUTPUT_DISPLAYPORT: | |
4234 | case INTEL_OUTPUT_HDMI: | |
4235 | case INTEL_OUTPUT_EDP: | |
4236 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4237 | switch (intel_dig_port->port) { | |
4238 | case PORT_A: | |
4239 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4240 | case PORT_B: | |
4241 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4242 | case PORT_C: | |
4243 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4244 | case PORT_D: | |
4245 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4246 | default: | |
4247 | WARN_ON_ONCE(1); | |
4248 | return POWER_DOMAIN_PORT_OTHER; | |
4249 | } | |
4250 | case INTEL_OUTPUT_ANALOG: | |
4251 | return POWER_DOMAIN_PORT_CRT; | |
4252 | case INTEL_OUTPUT_DSI: | |
4253 | return POWER_DOMAIN_PORT_DSI; | |
4254 | default: | |
4255 | return POWER_DOMAIN_PORT_OTHER; | |
4256 | } | |
4257 | } | |
4258 | ||
4259 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4260 | { |
319be8ae ID |
4261 | struct drm_device *dev = crtc->dev; |
4262 | struct intel_encoder *intel_encoder; | |
4263 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4264 | enum pipe pipe = intel_crtc->pipe; | |
4265 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4266 | unsigned long mask; |
4267 | enum transcoder transcoder; | |
4268 | ||
4269 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4270 | ||
4271 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4272 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4273 | if (pfit_enabled) | |
4274 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4275 | ||
319be8ae ID |
4276 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4277 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4278 | ||
77d22dca ID |
4279 | return mask; |
4280 | } | |
4281 | ||
4282 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4283 | bool enable) | |
4284 | { | |
4285 | if (dev_priv->power_domains.init_power_on == enable) | |
4286 | return; | |
4287 | ||
4288 | if (enable) | |
4289 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4290 | else | |
4291 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4292 | ||
4293 | dev_priv->power_domains.init_power_on = enable; | |
4294 | } | |
4295 | ||
4296 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4297 | { | |
4298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4299 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4300 | struct intel_crtc *crtc; | |
4301 | ||
4302 | /* | |
4303 | * First get all needed power domains, then put all unneeded, to avoid | |
4304 | * any unnecessary toggling of the power wells. | |
4305 | */ | |
d3fcc808 | 4306 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4307 | enum intel_display_power_domain domain; |
4308 | ||
4309 | if (!crtc->base.enabled) | |
4310 | continue; | |
4311 | ||
319be8ae | 4312 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4313 | |
4314 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4315 | intel_display_power_get(dev_priv, domain); | |
4316 | } | |
4317 | ||
d3fcc808 | 4318 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4319 | enum intel_display_power_domain domain; |
4320 | ||
4321 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4322 | intel_display_power_put(dev_priv, domain); | |
4323 | ||
4324 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4325 | } | |
4326 | ||
4327 | intel_display_set_init_power(dev_priv, false); | |
4328 | } | |
4329 | ||
586f49dc | 4330 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4331 | { |
586f49dc | 4332 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4333 | |
586f49dc JB |
4334 | /* Obtain SKU information */ |
4335 | mutex_lock(&dev_priv->dpio_lock); | |
4336 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4337 | CCK_FUSE_HPLL_FREQ_MASK; | |
4338 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4339 | |
586f49dc | 4340 | return vco_freq[hpll_freq]; |
30a970c6 JB |
4341 | } |
4342 | ||
4343 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4344 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4345 | { | |
4346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4347 | u32 val, cmd; | |
4348 | ||
d60c4473 ID |
4349 | WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq); |
4350 | dev_priv->vlv_cdclk_freq = cdclk; | |
4351 | ||
30a970c6 JB |
4352 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4353 | cmd = 2; | |
4354 | else if (cdclk == 266) | |
4355 | cmd = 1; | |
4356 | else | |
4357 | cmd = 0; | |
4358 | ||
4359 | mutex_lock(&dev_priv->rps.hw_lock); | |
4360 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4361 | val &= ~DSPFREQGUAR_MASK; | |
4362 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4363 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4364 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4365 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4366 | 50)) { | |
4367 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4368 | } | |
4369 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4370 | ||
4371 | if (cdclk == 400) { | |
4372 | u32 divider, vco; | |
4373 | ||
4374 | vco = valleyview_get_vco(dev_priv); | |
4375 | divider = ((vco << 1) / cdclk) - 1; | |
4376 | ||
4377 | mutex_lock(&dev_priv->dpio_lock); | |
4378 | /* adjust cdclk divider */ | |
4379 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4380 | val &= ~0xf; | |
4381 | val |= divider; | |
4382 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4383 | mutex_unlock(&dev_priv->dpio_lock); | |
4384 | } | |
4385 | ||
4386 | mutex_lock(&dev_priv->dpio_lock); | |
4387 | /* adjust self-refresh exit latency value */ | |
4388 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4389 | val &= ~0x7f; | |
4390 | ||
4391 | /* | |
4392 | * For high bandwidth configs, we set a higher latency in the bunit | |
4393 | * so that the core display fetch happens in time to avoid underruns. | |
4394 | */ | |
4395 | if (cdclk == 400) | |
4396 | val |= 4500 / 250; /* 4.5 usec */ | |
4397 | else | |
4398 | val |= 3000 / 250; /* 3.0 usec */ | |
4399 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4400 | mutex_unlock(&dev_priv->dpio_lock); | |
4401 | ||
4402 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4403 | intel_i2c_reset(dev); | |
4404 | } | |
4405 | ||
d60c4473 | 4406 | int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
30a970c6 JB |
4407 | { |
4408 | int cur_cdclk, vco; | |
4409 | int divider; | |
4410 | ||
4411 | vco = valleyview_get_vco(dev_priv); | |
4412 | ||
4413 | mutex_lock(&dev_priv->dpio_lock); | |
4414 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4415 | mutex_unlock(&dev_priv->dpio_lock); | |
4416 | ||
4417 | divider &= 0xf; | |
4418 | ||
4419 | cur_cdclk = (vco << 1) / (divider + 1); | |
4420 | ||
4421 | return cur_cdclk; | |
4422 | } | |
4423 | ||
4424 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4425 | int max_pixclk) | |
4426 | { | |
30a970c6 JB |
4427 | /* |
4428 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4429 | * 200MHz | |
4430 | * 267MHz | |
4431 | * 320MHz | |
4432 | * 400MHz | |
4433 | * So we check to see whether we're above 90% of the lower bin and | |
4434 | * adjust if needed. | |
4435 | */ | |
4436 | if (max_pixclk > 288000) { | |
4437 | return 400; | |
4438 | } else if (max_pixclk > 240000) { | |
4439 | return 320; | |
4440 | } else | |
4441 | return 266; | |
4442 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4443 | } | |
4444 | ||
2f2d7aa1 VS |
4445 | /* compute the max pixel clock for new configuration */ |
4446 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4447 | { |
4448 | struct drm_device *dev = dev_priv->dev; | |
4449 | struct intel_crtc *intel_crtc; | |
4450 | int max_pixclk = 0; | |
4451 | ||
d3fcc808 | 4452 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4453 | if (intel_crtc->new_enabled) |
30a970c6 | 4454 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4455 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4456 | } |
4457 | ||
4458 | return max_pixclk; | |
4459 | } | |
4460 | ||
4461 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4462 | unsigned *prepare_pipes) |
30a970c6 JB |
4463 | { |
4464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4465 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4466 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4467 | |
d60c4473 ID |
4468 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4469 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4470 | return; |
4471 | ||
2f2d7aa1 | 4472 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4473 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4474 | if (intel_crtc->base.enabled) |
4475 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4476 | } | |
4477 | ||
4478 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4479 | { | |
4480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4481 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4482 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4483 | ||
d60c4473 | 4484 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
30a970c6 | 4485 | valleyview_set_cdclk(dev, req_cdclk); |
77961eb9 | 4486 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4487 | } |
4488 | ||
89b667f8 JB |
4489 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4490 | { | |
4491 | struct drm_device *dev = crtc->dev; | |
89b667f8 JB |
4492 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4493 | struct intel_encoder *encoder; | |
4494 | int pipe = intel_crtc->pipe; | |
23538ef1 | 4495 | bool is_dsi; |
89b667f8 JB |
4496 | |
4497 | WARN_ON(!crtc->enabled); | |
4498 | ||
4499 | if (intel_crtc->active) | |
4500 | return; | |
4501 | ||
4502 | intel_crtc->active = true; | |
89b667f8 | 4503 | |
89b667f8 JB |
4504 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4505 | if (encoder->pre_pll_enable) | |
4506 | encoder->pre_pll_enable(encoder); | |
4507 | ||
23538ef1 JN |
4508 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4509 | ||
9d556c99 CML |
4510 | if (!is_dsi) { |
4511 | if (IS_CHERRYVIEW(dev)) | |
4512 | chv_enable_pll(intel_crtc); | |
4513 | else | |
4514 | vlv_enable_pll(intel_crtc); | |
4515 | } | |
89b667f8 JB |
4516 | |
4517 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4518 | if (encoder->pre_enable) | |
4519 | encoder->pre_enable(encoder); | |
4520 | ||
2dd24552 JB |
4521 | i9xx_pfit_enable(intel_crtc); |
4522 | ||
63cbb074 VS |
4523 | intel_crtc_load_lut(crtc); |
4524 | ||
f37fcc2a | 4525 | intel_update_watermarks(crtc); |
e1fdc473 | 4526 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4527 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
be6a6f8e | 4528 | |
5004945f JN |
4529 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4530 | encoder->enable(encoder); | |
9ab0460b VS |
4531 | |
4532 | intel_crtc_enable_planes(crtc); | |
89b667f8 JB |
4533 | } |
4534 | ||
0b8765c6 | 4535 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4536 | { |
4537 | struct drm_device *dev = crtc->dev; | |
79e53945 | 4538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4539 | struct intel_encoder *encoder; |
79e53945 | 4540 | int pipe = intel_crtc->pipe; |
79e53945 | 4541 | |
08a48469 DV |
4542 | WARN_ON(!crtc->enabled); |
4543 | ||
f7abfe8b CW |
4544 | if (intel_crtc->active) |
4545 | return; | |
4546 | ||
4547 | intel_crtc->active = true; | |
6b383a7f | 4548 | |
9d6d9f19 MK |
4549 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4550 | if (encoder->pre_enable) | |
4551 | encoder->pre_enable(encoder); | |
4552 | ||
f6736a1a DV |
4553 | i9xx_enable_pll(intel_crtc); |
4554 | ||
2dd24552 JB |
4555 | i9xx_pfit_enable(intel_crtc); |
4556 | ||
63cbb074 VS |
4557 | intel_crtc_load_lut(crtc); |
4558 | ||
f37fcc2a | 4559 | intel_update_watermarks(crtc); |
e1fdc473 | 4560 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4561 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
be6a6f8e | 4562 | |
fa5c73b1 DV |
4563 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4564 | encoder->enable(encoder); | |
9ab0460b VS |
4565 | |
4566 | intel_crtc_enable_planes(crtc); | |
0b8765c6 | 4567 | } |
79e53945 | 4568 | |
87476d63 DV |
4569 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4570 | { | |
4571 | struct drm_device *dev = crtc->base.dev; | |
4572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4573 | |
328d8e82 DV |
4574 | if (!crtc->config.gmch_pfit.control) |
4575 | return; | |
87476d63 | 4576 | |
328d8e82 | 4577 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4578 | |
328d8e82 DV |
4579 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4580 | I915_READ(PFIT_CONTROL)); | |
4581 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4582 | } |
4583 | ||
0b8765c6 JB |
4584 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4585 | { | |
4586 | struct drm_device *dev = crtc->dev; | |
4587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4589 | struct intel_encoder *encoder; |
0b8765c6 | 4590 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4591 | |
f7abfe8b CW |
4592 | if (!intel_crtc->active) |
4593 | return; | |
4594 | ||
9ab0460b VS |
4595 | intel_crtc_disable_planes(crtc); |
4596 | ||
ea9d758d DV |
4597 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4598 | encoder->disable(encoder); | |
4599 | ||
2d9d2b0b | 4600 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 4601 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4602 | |
87476d63 | 4603 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4604 | |
89b667f8 JB |
4605 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4606 | if (encoder->post_disable) | |
4607 | encoder->post_disable(encoder); | |
4608 | ||
076ed3b2 CML |
4609 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4610 | if (IS_CHERRYVIEW(dev)) | |
4611 | chv_disable_pll(dev_priv, pipe); | |
4612 | else if (IS_VALLEYVIEW(dev)) | |
4613 | vlv_disable_pll(dev_priv, pipe); | |
4614 | else | |
4615 | i9xx_disable_pll(dev_priv, pipe); | |
4616 | } | |
0b8765c6 | 4617 | |
f7abfe8b | 4618 | intel_crtc->active = false; |
46ba614c | 4619 | intel_update_watermarks(crtc); |
f37fcc2a | 4620 | |
6b383a7f | 4621 | intel_update_fbc(dev); |
0b8765c6 JB |
4622 | } |
4623 | ||
ee7b9f93 JB |
4624 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4625 | { | |
4626 | } | |
4627 | ||
976f8a20 DV |
4628 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4629 | bool enabled) | |
2c07245f ZW |
4630 | { |
4631 | struct drm_device *dev = crtc->dev; | |
4632 | struct drm_i915_master_private *master_priv; | |
4633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4634 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4635 | |
4636 | if (!dev->primary->master) | |
4637 | return; | |
4638 | ||
4639 | master_priv = dev->primary->master->driver_priv; | |
4640 | if (!master_priv->sarea_priv) | |
4641 | return; | |
4642 | ||
79e53945 JB |
4643 | switch (pipe) { |
4644 | case 0: | |
4645 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4646 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4647 | break; | |
4648 | case 1: | |
4649 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4650 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4651 | break; | |
4652 | default: | |
9db4a9c7 | 4653 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4654 | break; |
4655 | } | |
79e53945 JB |
4656 | } |
4657 | ||
976f8a20 DV |
4658 | /** |
4659 | * Sets the power management mode of the pipe and plane. | |
4660 | */ | |
4661 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4662 | { | |
4663 | struct drm_device *dev = crtc->dev; | |
4664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4665 | struct intel_encoder *intel_encoder; | |
4666 | bool enable = false; | |
4667 | ||
4668 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4669 | enable |= intel_encoder->connectors_active; | |
4670 | ||
4671 | if (enable) | |
4672 | dev_priv->display.crtc_enable(crtc); | |
4673 | else | |
4674 | dev_priv->display.crtc_disable(crtc); | |
4675 | ||
4676 | intel_crtc_update_sarea(crtc, enable); | |
4677 | } | |
4678 | ||
cdd59983 CW |
4679 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4680 | { | |
cdd59983 | 4681 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4682 | struct drm_connector *connector; |
ee7b9f93 | 4683 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 4684 | |
976f8a20 DV |
4685 | /* crtc should still be enabled when we disable it. */ |
4686 | WARN_ON(!crtc->enabled); | |
4687 | ||
4688 | dev_priv->display.crtc_disable(crtc); | |
4689 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4690 | dev_priv->display.off(crtc); |
4691 | ||
931872fc | 4692 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4693 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4694 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 | 4695 | |
f4510a27 | 4696 | if (crtc->primary->fb) { |
cdd59983 | 4697 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 4698 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj); |
cdd59983 | 4699 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4700 | crtc->primary->fb = NULL; |
976f8a20 DV |
4701 | } |
4702 | ||
4703 | /* Update computed state. */ | |
4704 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4705 | if (!connector->encoder || !connector->encoder->crtc) | |
4706 | continue; | |
4707 | ||
4708 | if (connector->encoder->crtc != crtc) | |
4709 | continue; | |
4710 | ||
4711 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4712 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4713 | } |
4714 | } | |
4715 | ||
ea5b213a | 4716 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4717 | { |
4ef69c7a | 4718 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4719 | |
ea5b213a CW |
4720 | drm_encoder_cleanup(encoder); |
4721 | kfree(intel_encoder); | |
7e7d76c3 JB |
4722 | } |
4723 | ||
9237329d | 4724 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4725 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4726 | * state of the entire output pipe. */ | |
9237329d | 4727 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4728 | { |
5ab432ef DV |
4729 | if (mode == DRM_MODE_DPMS_ON) { |
4730 | encoder->connectors_active = true; | |
4731 | ||
b2cabb0e | 4732 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4733 | } else { |
4734 | encoder->connectors_active = false; | |
4735 | ||
b2cabb0e | 4736 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4737 | } |
79e53945 JB |
4738 | } |
4739 | ||
0a91ca29 DV |
4740 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4741 | * internal consistency). */ | |
b980514c | 4742 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4743 | { |
0a91ca29 DV |
4744 | if (connector->get_hw_state(connector)) { |
4745 | struct intel_encoder *encoder = connector->encoder; | |
4746 | struct drm_crtc *crtc; | |
4747 | bool encoder_enabled; | |
4748 | enum pipe pipe; | |
4749 | ||
4750 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4751 | connector->base.base.id, | |
4752 | drm_get_connector_name(&connector->base)); | |
4753 | ||
4754 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4755 | "wrong connector dpms state\n"); | |
4756 | WARN(connector->base.encoder != &encoder->base, | |
4757 | "active connector not linked to encoder\n"); | |
4758 | WARN(!encoder->connectors_active, | |
4759 | "encoder->connectors_active not set\n"); | |
4760 | ||
4761 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4762 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4763 | if (WARN_ON(!encoder->base.crtc)) | |
4764 | return; | |
4765 | ||
4766 | crtc = encoder->base.crtc; | |
4767 | ||
4768 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4769 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4770 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4771 | "encoder active on the wrong pipe\n"); | |
4772 | } | |
79e53945 JB |
4773 | } |
4774 | ||
5ab432ef DV |
4775 | /* Even simpler default implementation, if there's really no special case to |
4776 | * consider. */ | |
4777 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4778 | { |
5ab432ef DV |
4779 | /* All the simple cases only support two dpms states. */ |
4780 | if (mode != DRM_MODE_DPMS_ON) | |
4781 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4782 | |
5ab432ef DV |
4783 | if (mode == connector->dpms) |
4784 | return; | |
4785 | ||
4786 | connector->dpms = mode; | |
4787 | ||
4788 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4789 | if (connector->encoder) |
4790 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4791 | |
b980514c | 4792 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4793 | } |
4794 | ||
f0947c37 DV |
4795 | /* Simple connector->get_hw_state implementation for encoders that support only |
4796 | * one connector and no cloning and hence the encoder state determines the state | |
4797 | * of the connector. */ | |
4798 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4799 | { |
24929352 | 4800 | enum pipe pipe = 0; |
f0947c37 | 4801 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4802 | |
f0947c37 | 4803 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4804 | } |
4805 | ||
1857e1da DV |
4806 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4807 | struct intel_crtc_config *pipe_config) | |
4808 | { | |
4809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4810 | struct intel_crtc *pipe_B_crtc = | |
4811 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4812 | ||
4813 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4814 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4815 | if (pipe_config->fdi_lanes > 4) { | |
4816 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4817 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4818 | return false; | |
4819 | } | |
4820 | ||
bafb6553 | 4821 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4822 | if (pipe_config->fdi_lanes > 2) { |
4823 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4824 | pipe_config->fdi_lanes); | |
4825 | return false; | |
4826 | } else { | |
4827 | return true; | |
4828 | } | |
4829 | } | |
4830 | ||
4831 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4832 | return true; | |
4833 | ||
4834 | /* Ivybridge 3 pipe is really complicated */ | |
4835 | switch (pipe) { | |
4836 | case PIPE_A: | |
4837 | return true; | |
4838 | case PIPE_B: | |
4839 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4840 | pipe_config->fdi_lanes > 2) { | |
4841 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4842 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4843 | return false; | |
4844 | } | |
4845 | return true; | |
4846 | case PIPE_C: | |
1e833f40 | 4847 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4848 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4849 | if (pipe_config->fdi_lanes > 2) { | |
4850 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4851 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4852 | return false; | |
4853 | } | |
4854 | } else { | |
4855 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4856 | return false; | |
4857 | } | |
4858 | return true; | |
4859 | default: | |
4860 | BUG(); | |
4861 | } | |
4862 | } | |
4863 | ||
e29c22c0 DV |
4864 | #define RETRY 1 |
4865 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4866 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4867 | { |
1857e1da | 4868 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4869 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4870 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4871 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4872 | |
e29c22c0 | 4873 | retry: |
877d48d5 DV |
4874 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4875 | * each output octet as 10 bits. The actual frequency | |
4876 | * is stored as a divider into a 100MHz clock, and the | |
4877 | * mode pixel clock is stored in units of 1KHz. | |
4878 | * Hence the bw of each lane in terms of the mode signal | |
4879 | * is: | |
4880 | */ | |
4881 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4882 | ||
241bfc38 | 4883 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4884 | |
2bd89a07 | 4885 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4886 | pipe_config->pipe_bpp); |
4887 | ||
4888 | pipe_config->fdi_lanes = lane; | |
4889 | ||
2bd89a07 | 4890 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4891 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4892 | |
e29c22c0 DV |
4893 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4894 | intel_crtc->pipe, pipe_config); | |
4895 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4896 | pipe_config->pipe_bpp -= 2*3; | |
4897 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4898 | pipe_config->pipe_bpp); | |
4899 | needs_recompute = true; | |
4900 | pipe_config->bw_constrained = true; | |
4901 | ||
4902 | goto retry; | |
4903 | } | |
4904 | ||
4905 | if (needs_recompute) | |
4906 | return RETRY; | |
4907 | ||
4908 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4909 | } |
4910 | ||
42db64ef PZ |
4911 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4912 | struct intel_crtc_config *pipe_config) | |
4913 | { | |
d330a953 | 4914 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 4915 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 4916 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4917 | } |
4918 | ||
a43f6e0f | 4919 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4920 | struct intel_crtc_config *pipe_config) |
79e53945 | 4921 | { |
a43f6e0f | 4922 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4923 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4924 | |
ad3a4479 | 4925 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4926 | if (INTEL_INFO(dev)->gen < 4) { |
4927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4928 | int clock_limit = | |
4929 | dev_priv->display.get_display_clock_speed(dev); | |
4930 | ||
4931 | /* | |
4932 | * Enable pixel doubling when the dot clock | |
4933 | * is > 90% of the (display) core speed. | |
4934 | * | |
b397c96b VS |
4935 | * GDG double wide on either pipe, |
4936 | * otherwise pipe A only. | |
cf532bb2 | 4937 | */ |
b397c96b | 4938 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4939 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4940 | clock_limit *= 2; |
cf532bb2 | 4941 | pipe_config->double_wide = true; |
ad3a4479 VS |
4942 | } |
4943 | ||
241bfc38 | 4944 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4945 | return -EINVAL; |
2c07245f | 4946 | } |
89749350 | 4947 | |
1d1d0e27 VS |
4948 | /* |
4949 | * Pipe horizontal size must be even in: | |
4950 | * - DVO ganged mode | |
4951 | * - LVDS dual channel mode | |
4952 | * - Double wide pipe | |
4953 | */ | |
4954 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4955 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4956 | pipe_config->pipe_src_w &= ~1; | |
4957 | ||
8693a824 DL |
4958 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4959 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4960 | */ |
4961 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4962 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4963 | return -EINVAL; |
44f46b42 | 4964 | |
bd080ee5 | 4965 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4966 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4967 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4968 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4969 | * for lvds. */ | |
4970 | pipe_config->pipe_bpp = 8*3; | |
4971 | } | |
4972 | ||
f5adf94e | 4973 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4974 | hsw_compute_ips_config(crtc, pipe_config); |
4975 | ||
4976 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4977 | * clock survives for now. */ | |
4978 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4979 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4980 | |
877d48d5 | 4981 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4982 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4983 | |
e29c22c0 | 4984 | return 0; |
79e53945 JB |
4985 | } |
4986 | ||
25eb05fc JB |
4987 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4988 | { | |
4989 | return 400000; /* FIXME */ | |
4990 | } | |
4991 | ||
e70236a8 JB |
4992 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4993 | { | |
4994 | return 400000; | |
4995 | } | |
79e53945 | 4996 | |
e70236a8 | 4997 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4998 | { |
e70236a8 JB |
4999 | return 333000; |
5000 | } | |
79e53945 | 5001 | |
e70236a8 JB |
5002 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5003 | { | |
5004 | return 200000; | |
5005 | } | |
79e53945 | 5006 | |
257a7ffc DV |
5007 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5008 | { | |
5009 | u16 gcfgc = 0; | |
5010 | ||
5011 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5012 | ||
5013 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5014 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5015 | return 267000; | |
5016 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5017 | return 333000; | |
5018 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5019 | return 444000; | |
5020 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5021 | return 200000; | |
5022 | default: | |
5023 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5024 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5025 | return 133000; | |
5026 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5027 | return 167000; | |
5028 | } | |
5029 | } | |
5030 | ||
e70236a8 JB |
5031 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5032 | { | |
5033 | u16 gcfgc = 0; | |
79e53945 | 5034 | |
e70236a8 JB |
5035 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5036 | ||
5037 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5038 | return 133000; | |
5039 | else { | |
5040 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5041 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5042 | return 333000; | |
5043 | default: | |
5044 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5045 | return 190000; | |
79e53945 | 5046 | } |
e70236a8 JB |
5047 | } |
5048 | } | |
5049 | ||
5050 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5051 | { | |
5052 | return 266000; | |
5053 | } | |
5054 | ||
5055 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5056 | { | |
5057 | u16 hpllcc = 0; | |
5058 | /* Assume that the hardware is in the high speed state. This | |
5059 | * should be the default. | |
5060 | */ | |
5061 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5062 | case GC_CLOCK_133_200: | |
5063 | case GC_CLOCK_100_200: | |
5064 | return 200000; | |
5065 | case GC_CLOCK_166_250: | |
5066 | return 250000; | |
5067 | case GC_CLOCK_100_133: | |
79e53945 | 5068 | return 133000; |
e70236a8 | 5069 | } |
79e53945 | 5070 | |
e70236a8 JB |
5071 | /* Shouldn't happen */ |
5072 | return 0; | |
5073 | } | |
79e53945 | 5074 | |
e70236a8 JB |
5075 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5076 | { | |
5077 | return 133000; | |
79e53945 JB |
5078 | } |
5079 | ||
2c07245f | 5080 | static void |
a65851af | 5081 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5082 | { |
a65851af VS |
5083 | while (*num > DATA_LINK_M_N_MASK || |
5084 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5085 | *num >>= 1; |
5086 | *den >>= 1; | |
5087 | } | |
5088 | } | |
5089 | ||
a65851af VS |
5090 | static void compute_m_n(unsigned int m, unsigned int n, |
5091 | uint32_t *ret_m, uint32_t *ret_n) | |
5092 | { | |
5093 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5094 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5095 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5096 | } | |
5097 | ||
e69d0bc1 DV |
5098 | void |
5099 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5100 | int pixel_clock, int link_clock, | |
5101 | struct intel_link_m_n *m_n) | |
2c07245f | 5102 | { |
e69d0bc1 | 5103 | m_n->tu = 64; |
a65851af VS |
5104 | |
5105 | compute_m_n(bits_per_pixel * pixel_clock, | |
5106 | link_clock * nlanes * 8, | |
5107 | &m_n->gmch_m, &m_n->gmch_n); | |
5108 | ||
5109 | compute_m_n(pixel_clock, link_clock, | |
5110 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5111 | } |
5112 | ||
a7615030 CW |
5113 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5114 | { | |
d330a953 JN |
5115 | if (i915.panel_use_ssc >= 0) |
5116 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5117 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5118 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5119 | } |
5120 | ||
c65d77d8 JB |
5121 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5122 | { | |
5123 | struct drm_device *dev = crtc->dev; | |
5124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5125 | int refclk; | |
5126 | ||
a0c4da24 | 5127 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5128 | refclk = 100000; |
a0c4da24 | 5129 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5130 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5131 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5132 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5133 | } else if (!IS_GEN2(dev)) { |
5134 | refclk = 96000; | |
5135 | } else { | |
5136 | refclk = 48000; | |
5137 | } | |
5138 | ||
5139 | return refclk; | |
5140 | } | |
5141 | ||
7429e9d4 | 5142 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5143 | { |
7df00d7a | 5144 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5145 | } |
f47709a9 | 5146 | |
7429e9d4 DV |
5147 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5148 | { | |
5149 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5150 | } |
5151 | ||
f47709a9 | 5152 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5153 | intel_clock_t *reduced_clock) |
5154 | { | |
f47709a9 | 5155 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 5156 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5157 | int pipe = crtc->pipe; |
a7516a05 JB |
5158 | u32 fp, fp2 = 0; |
5159 | ||
5160 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5161 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5162 | if (reduced_clock) |
7429e9d4 | 5163 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5164 | } else { |
7429e9d4 | 5165 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5166 | if (reduced_clock) |
7429e9d4 | 5167 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5168 | } |
5169 | ||
5170 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 5171 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5172 | |
f47709a9 DV |
5173 | crtc->lowfreq_avail = false; |
5174 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5175 | reduced_clock && i915.powersave) { |
a7516a05 | 5176 | I915_WRITE(FP1(pipe), fp2); |
8bcc2795 | 5177 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5178 | crtc->lowfreq_avail = true; |
a7516a05 JB |
5179 | } else { |
5180 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 5181 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5182 | } |
5183 | } | |
5184 | ||
5e69f97f CML |
5185 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5186 | pipe) | |
89b667f8 JB |
5187 | { |
5188 | u32 reg_val; | |
5189 | ||
5190 | /* | |
5191 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5192 | * and set it to a reasonable value instead. | |
5193 | */ | |
ab3c759a | 5194 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5195 | reg_val &= 0xffffff00; |
5196 | reg_val |= 0x00000030; | |
ab3c759a | 5197 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5198 | |
ab3c759a | 5199 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5200 | reg_val &= 0x8cffffff; |
5201 | reg_val = 0x8c000000; | |
ab3c759a | 5202 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5203 | |
ab3c759a | 5204 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5205 | reg_val &= 0xffffff00; |
ab3c759a | 5206 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5207 | |
ab3c759a | 5208 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5209 | reg_val &= 0x00ffffff; |
5210 | reg_val |= 0xb0000000; | |
ab3c759a | 5211 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5212 | } |
5213 | ||
b551842d DV |
5214 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5215 | struct intel_link_m_n *m_n) | |
5216 | { | |
5217 | struct drm_device *dev = crtc->base.dev; | |
5218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5219 | int pipe = crtc->pipe; | |
5220 | ||
e3b95f1e DV |
5221 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5222 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5223 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5224 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5225 | } |
5226 | ||
5227 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5228 | struct intel_link_m_n *m_n) | |
5229 | { | |
5230 | struct drm_device *dev = crtc->base.dev; | |
5231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5232 | int pipe = crtc->pipe; | |
5233 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5234 | ||
5235 | if (INTEL_INFO(dev)->gen >= 5) { | |
5236 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5237 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5238 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5239 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5240 | } else { | |
e3b95f1e DV |
5241 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5242 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5243 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5244 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5245 | } |
5246 | } | |
5247 | ||
03afc4a2 DV |
5248 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5249 | { | |
5250 | if (crtc->config.has_pch_encoder) | |
5251 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5252 | else | |
5253 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5254 | } | |
5255 | ||
f47709a9 | 5256 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 5257 | { |
f47709a9 | 5258 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5259 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5260 | int pipe = crtc->pipe; |
89b667f8 | 5261 | u32 dpll, mdiv; |
a0c4da24 | 5262 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 5263 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 5264 | |
09153000 DV |
5265 | mutex_lock(&dev_priv->dpio_lock); |
5266 | ||
f47709a9 DV |
5267 | bestn = crtc->config.dpll.n; |
5268 | bestm1 = crtc->config.dpll.m1; | |
5269 | bestm2 = crtc->config.dpll.m2; | |
5270 | bestp1 = crtc->config.dpll.p1; | |
5271 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5272 | |
89b667f8 JB |
5273 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5274 | ||
5275 | /* PLL B needs special handling */ | |
5276 | if (pipe) | |
5e69f97f | 5277 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5278 | |
5279 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5280 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5281 | |
5282 | /* Disable target IRef on PLL */ | |
ab3c759a | 5283 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5284 | reg_val &= 0x00ffffff; |
ab3c759a | 5285 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5286 | |
5287 | /* Disable fast lock */ | |
ab3c759a | 5288 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5289 | |
5290 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5291 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5292 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5293 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5294 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5295 | |
5296 | /* | |
5297 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5298 | * but we don't support that). | |
5299 | * Note: don't use the DAC post divider as it seems unstable. | |
5300 | */ | |
5301 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5302 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5303 | |
a0c4da24 | 5304 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5305 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5306 | |
89b667f8 | 5307 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5308 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5309 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5310 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5311 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5312 | 0x009f0003); |
89b667f8 | 5313 | else |
ab3c759a | 5314 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5315 | 0x00d0000f); |
5316 | ||
5317 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5318 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5319 | /* Use SSC source */ | |
5320 | if (!pipe) | |
ab3c759a | 5321 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5322 | 0x0df40000); |
5323 | else | |
ab3c759a | 5324 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5325 | 0x0df70000); |
5326 | } else { /* HDMI or VGA */ | |
5327 | /* Use bend source */ | |
5328 | if (!pipe) | |
ab3c759a | 5329 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5330 | 0x0df70000); |
5331 | else | |
ab3c759a | 5332 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5333 | 0x0df40000); |
5334 | } | |
a0c4da24 | 5335 | |
ab3c759a | 5336 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5337 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5338 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5339 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5340 | coreclk |= 0x01000000; | |
ab3c759a | 5341 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5342 | |
ab3c759a | 5343 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 5344 | |
e5cbfbfb ID |
5345 | /* |
5346 | * Enable DPIO clock input. We should never disable the reference | |
5347 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5348 | * on it. | |
5349 | */ | |
89b667f8 JB |
5350 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
5351 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
5352 | /* We should never disable this, set it here for state tracking */ |
5353 | if (pipe == PIPE_B) | |
89b667f8 | 5354 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 5355 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
5356 | crtc->config.dpll_hw_state.dpll = dpll; |
5357 | ||
ef1b460d DV |
5358 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5359 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
5360 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5361 | ||
09153000 | 5362 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5363 | } |
5364 | ||
9d556c99 CML |
5365 | static void chv_update_pll(struct intel_crtc *crtc) |
5366 | { | |
5367 | struct drm_device *dev = crtc->base.dev; | |
5368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5369 | int pipe = crtc->pipe; | |
5370 | int dpll_reg = DPLL(crtc->pipe); | |
5371 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
5372 | u32 val, loopfilter, intcoeff; | |
5373 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; | |
5374 | int refclk; | |
5375 | ||
5376 | mutex_lock(&dev_priv->dpio_lock); | |
5377 | ||
5378 | bestn = crtc->config.dpll.n; | |
5379 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5380 | bestm1 = crtc->config.dpll.m1; | |
5381 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5382 | bestp1 = crtc->config.dpll.p1; | |
5383 | bestp2 = crtc->config.dpll.p2; | |
5384 | ||
5385 | /* | |
5386 | * Enable Refclk and SSC | |
5387 | */ | |
5388 | val = I915_READ(dpll_reg); | |
5389 | val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV); | |
5390 | I915_WRITE(dpll_reg, val); | |
5391 | ||
5392 | /* Propagate soft reset to data lane reset */ | |
5393 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port)); | |
5394 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
5395 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val); | |
5396 | ||
5397 | /* Disable 10bit clock to display controller */ | |
5398 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
5399 | val &= ~DPIO_DCLKP_EN; | |
5400 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
5401 | ||
5402 | /* p1 and p2 divider */ | |
5403 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5404 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5405 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5406 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5407 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5408 | ||
5409 | /* Feedback post-divider - m2 */ | |
5410 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5411 | ||
5412 | /* Feedback refclk divider - n and m1 */ | |
5413 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5414 | DPIO_CHV_M1_DIV_BY_2 | | |
5415 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5416 | ||
5417 | /* M2 fraction division */ | |
5418 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5419 | ||
5420 | /* M2 fraction division enable */ | |
5421 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5422 | DPIO_CHV_FRAC_DIV_EN | | |
5423 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5424 | ||
5425 | /* Loop filter */ | |
5426 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5427 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5428 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5429 | if (refclk == 100000) | |
5430 | intcoeff = 11; | |
5431 | else if (refclk == 38400) | |
5432 | intcoeff = 10; | |
5433 | else | |
5434 | intcoeff = 9; | |
5435 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5436 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5437 | ||
5438 | /* AFC Recal */ | |
5439 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5440 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5441 | DPIO_AFC_RECAL); | |
5442 | ||
5443 | mutex_unlock(&dev_priv->dpio_lock); | |
5444 | } | |
5445 | ||
f47709a9 DV |
5446 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5447 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5448 | int num_connectors) |
5449 | { | |
f47709a9 | 5450 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5451 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5452 | u32 dpll; |
5453 | bool is_sdvo; | |
f47709a9 | 5454 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5455 | |
f47709a9 | 5456 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5457 | |
f47709a9 DV |
5458 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5459 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5460 | |
5461 | dpll = DPLL_VGA_MODE_DIS; | |
5462 | ||
f47709a9 | 5463 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5464 | dpll |= DPLLB_MODE_LVDS; |
5465 | else | |
5466 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5467 | |
ef1b460d | 5468 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5469 | dpll |= (crtc->config.pixel_multiplier - 1) |
5470 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5471 | } |
198a037f DV |
5472 | |
5473 | if (is_sdvo) | |
4a33e48d | 5474 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5475 | |
f47709a9 | 5476 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5477 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5478 | |
5479 | /* compute bitmask from p1 value */ | |
5480 | if (IS_PINEVIEW(dev)) | |
5481 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5482 | else { | |
5483 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5484 | if (IS_G4X(dev) && reduced_clock) | |
5485 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5486 | } | |
5487 | switch (clock->p2) { | |
5488 | case 5: | |
5489 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5490 | break; | |
5491 | case 7: | |
5492 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5493 | break; | |
5494 | case 10: | |
5495 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5496 | break; | |
5497 | case 14: | |
5498 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5499 | break; | |
5500 | } | |
5501 | if (INTEL_INFO(dev)->gen >= 4) | |
5502 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5503 | ||
09ede541 | 5504 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5505 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5506 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5507 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5508 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5509 | else | |
5510 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5511 | ||
5512 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5513 | crtc->config.dpll_hw_state.dpll = dpll; |
5514 | ||
eb1cbe48 | 5515 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5516 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5517 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5518 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5519 | } |
5520 | } | |
5521 | ||
f47709a9 | 5522 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5523 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5524 | int num_connectors) |
5525 | { | |
f47709a9 | 5526 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5527 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5528 | u32 dpll; |
f47709a9 | 5529 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5530 | |
f47709a9 | 5531 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5532 | |
eb1cbe48 DV |
5533 | dpll = DPLL_VGA_MODE_DIS; |
5534 | ||
f47709a9 | 5535 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5536 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5537 | } else { | |
5538 | if (clock->p1 == 2) | |
5539 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5540 | else | |
5541 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5542 | if (clock->p2 == 4) | |
5543 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5544 | } | |
5545 | ||
4a33e48d DV |
5546 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5547 | dpll |= DPLL_DVO_2X_MODE; | |
5548 | ||
f47709a9 | 5549 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5550 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5551 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5552 | else | |
5553 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5554 | ||
5555 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5556 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5557 | } |
5558 | ||
8a654f3b | 5559 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5560 | { |
5561 | struct drm_device *dev = intel_crtc->base.dev; | |
5562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5563 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5564 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5565 | struct drm_display_mode *adjusted_mode = |
5566 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5567 | uint32_t crtc_vtotal, crtc_vblank_end; |
5568 | int vsyncshift = 0; | |
4d8a62ea DV |
5569 | |
5570 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5571 | * the hw state checker will get angry at the mismatch. */ | |
5572 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5573 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5574 | |
609aeaca | 5575 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5576 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5577 | crtc_vtotal -= 1; |
5578 | crtc_vblank_end -= 1; | |
609aeaca VS |
5579 | |
5580 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5581 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5582 | else | |
5583 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5584 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5585 | if (vsyncshift < 0) |
5586 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5587 | } |
5588 | ||
5589 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5590 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5591 | |
fe2b8f9d | 5592 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5593 | (adjusted_mode->crtc_hdisplay - 1) | |
5594 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5595 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5596 | (adjusted_mode->crtc_hblank_start - 1) | |
5597 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5598 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5599 | (adjusted_mode->crtc_hsync_start - 1) | |
5600 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5601 | ||
fe2b8f9d | 5602 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5603 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5604 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5605 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5606 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5607 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5608 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5609 | (adjusted_mode->crtc_vsync_start - 1) | |
5610 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5611 | ||
b5e508d4 PZ |
5612 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5613 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5614 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5615 | * bits. */ | |
5616 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5617 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5618 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5619 | ||
b0e77b9c PZ |
5620 | /* pipesrc controls the size that is scaled from, which should |
5621 | * always be the user's requested size. | |
5622 | */ | |
5623 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5624 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5625 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5626 | } |
5627 | ||
1bd1bd80 DV |
5628 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5629 | struct intel_crtc_config *pipe_config) | |
5630 | { | |
5631 | struct drm_device *dev = crtc->base.dev; | |
5632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5633 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5634 | uint32_t tmp; | |
5635 | ||
5636 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5637 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5638 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5639 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5640 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5641 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5642 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5643 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5644 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5645 | ||
5646 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5647 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5648 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5649 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5650 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5651 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5652 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5653 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5654 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5655 | ||
5656 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5657 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5658 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5659 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5660 | } | |
5661 | ||
5662 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5663 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5664 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5665 | ||
5666 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5667 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5668 | } |
5669 | ||
f6a83288 DV |
5670 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5671 | struct intel_crtc_config *pipe_config) | |
babea61d | 5672 | { |
f6a83288 DV |
5673 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5674 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5675 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5676 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5677 | |
f6a83288 DV |
5678 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5679 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5680 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5681 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5682 | |
f6a83288 | 5683 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5684 | |
f6a83288 DV |
5685 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5686 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5687 | } |
5688 | ||
84b046f3 DV |
5689 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5690 | { | |
5691 | struct drm_device *dev = intel_crtc->base.dev; | |
5692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5693 | uint32_t pipeconf; | |
5694 | ||
9f11a9e4 | 5695 | pipeconf = 0; |
84b046f3 | 5696 | |
67c72a12 DV |
5697 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5698 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5699 | pipeconf |= PIPECONF_ENABLE; | |
5700 | ||
cf532bb2 VS |
5701 | if (intel_crtc->config.double_wide) |
5702 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5703 | |
ff9ce46e DV |
5704 | /* only g4x and later have fancy bpc/dither controls */ |
5705 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5706 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5707 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5708 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5709 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5710 | |
ff9ce46e DV |
5711 | switch (intel_crtc->config.pipe_bpp) { |
5712 | case 18: | |
5713 | pipeconf |= PIPECONF_6BPC; | |
5714 | break; | |
5715 | case 24: | |
5716 | pipeconf |= PIPECONF_8BPC; | |
5717 | break; | |
5718 | case 30: | |
5719 | pipeconf |= PIPECONF_10BPC; | |
5720 | break; | |
5721 | default: | |
5722 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5723 | BUG(); | |
84b046f3 DV |
5724 | } |
5725 | } | |
5726 | ||
5727 | if (HAS_PIPE_CXSR(dev)) { | |
5728 | if (intel_crtc->lowfreq_avail) { | |
5729 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5730 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5731 | } else { | |
5732 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5733 | } |
5734 | } | |
5735 | ||
efc2cfff VS |
5736 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
5737 | if (INTEL_INFO(dev)->gen < 4 || | |
5738 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5739 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5740 | else | |
5741 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
5742 | } else | |
84b046f3 DV |
5743 | pipeconf |= PIPECONF_PROGRESSIVE; |
5744 | ||
9f11a9e4 DV |
5745 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5746 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5747 | |
84b046f3 DV |
5748 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5749 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5750 | } | |
5751 | ||
f564048e | 5752 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5753 | int x, int y, |
94352cf9 | 5754 | struct drm_framebuffer *fb) |
79e53945 JB |
5755 | { |
5756 | struct drm_device *dev = crtc->dev; | |
5757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5758 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5759 | int pipe = intel_crtc->pipe; | |
80824003 | 5760 | int plane = intel_crtc->plane; |
c751ce4f | 5761 | int refclk, num_connectors = 0; |
652c393a | 5762 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5763 | u32 dspcntr; |
a16af721 | 5764 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5765 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5766 | struct intel_encoder *encoder; |
d4906093 | 5767 | const intel_limit_t *limit; |
5c3b82e2 | 5768 | int ret; |
79e53945 | 5769 | |
6c2b7c12 | 5770 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5771 | switch (encoder->type) { |
79e53945 JB |
5772 | case INTEL_OUTPUT_LVDS: |
5773 | is_lvds = true; | |
5774 | break; | |
e9fd1c02 JN |
5775 | case INTEL_OUTPUT_DSI: |
5776 | is_dsi = true; | |
5777 | break; | |
79e53945 | 5778 | } |
43565a06 | 5779 | |
c751ce4f | 5780 | num_connectors++; |
79e53945 JB |
5781 | } |
5782 | ||
f2335330 JN |
5783 | if (is_dsi) |
5784 | goto skip_dpll; | |
5785 | ||
5786 | if (!intel_crtc->config.clock_set) { | |
5787 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5788 | |
e9fd1c02 JN |
5789 | /* |
5790 | * Returns a set of divisors for the desired target clock with | |
5791 | * the given refclk, or FALSE. The returned values represent | |
5792 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5793 | * 2) / p1 / p2. | |
5794 | */ | |
5795 | limit = intel_limit(crtc, refclk); | |
5796 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5797 | intel_crtc->config.port_clock, | |
5798 | refclk, NULL, &clock); | |
f2335330 | 5799 | if (!ok) { |
e9fd1c02 JN |
5800 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5801 | return -EINVAL; | |
5802 | } | |
79e53945 | 5803 | |
f2335330 JN |
5804 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5805 | /* | |
5806 | * Ensure we match the reduced clock's P to the target | |
5807 | * clock. If the clocks don't match, we can't switch | |
5808 | * the display clock by using the FP0/FP1. In such case | |
5809 | * we will disable the LVDS downclock feature. | |
5810 | */ | |
5811 | has_reduced_clock = | |
5812 | dev_priv->display.find_dpll(limit, crtc, | |
5813 | dev_priv->lvds_downclock, | |
5814 | refclk, &clock, | |
5815 | &reduced_clock); | |
5816 | } | |
5817 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5818 | intel_crtc->config.dpll.n = clock.n; |
5819 | intel_crtc->config.dpll.m1 = clock.m1; | |
5820 | intel_crtc->config.dpll.m2 = clock.m2; | |
5821 | intel_crtc->config.dpll.p1 = clock.p1; | |
5822 | intel_crtc->config.dpll.p2 = clock.p2; | |
5823 | } | |
7026d4ac | 5824 | |
e9fd1c02 | 5825 | if (IS_GEN2(dev)) { |
8a654f3b | 5826 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5827 | has_reduced_clock ? &reduced_clock : NULL, |
5828 | num_connectors); | |
9d556c99 CML |
5829 | } else if (IS_CHERRYVIEW(dev)) { |
5830 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 5831 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5832 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5833 | } else { |
f47709a9 | 5834 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5835 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5836 | num_connectors); |
e9fd1c02 | 5837 | } |
79e53945 | 5838 | |
f2335330 | 5839 | skip_dpll: |
79e53945 JB |
5840 | /* Set up the display plane register */ |
5841 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5842 | ||
da6ecc5d JB |
5843 | if (!IS_VALLEYVIEW(dev)) { |
5844 | if (pipe == 0) | |
5845 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5846 | else | |
5847 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5848 | } | |
79e53945 | 5849 | |
2070f00c VS |
5850 | if (intel_crtc->config.has_dp_encoder) |
5851 | intel_dp_set_m_n(intel_crtc); | |
5852 | ||
8a654f3b | 5853 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5854 | |
5855 | /* pipesrc and dspsize control the size that is scaled from, | |
5856 | * which should always be the user's requested size. | |
79e53945 | 5857 | */ |
929c77fb | 5858 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5859 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5860 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5861 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5862 | |
84b046f3 DV |
5863 | i9xx_set_pipeconf(intel_crtc); |
5864 | ||
f564048e EA |
5865 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5866 | POSTING_READ(DSPCNTR(plane)); | |
5867 | ||
94352cf9 | 5868 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5869 | |
f564048e EA |
5870 | return ret; |
5871 | } | |
5872 | ||
2fa2fe9a DV |
5873 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5874 | struct intel_crtc_config *pipe_config) | |
5875 | { | |
5876 | struct drm_device *dev = crtc->base.dev; | |
5877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5878 | uint32_t tmp; | |
5879 | ||
dc9e7dec VS |
5880 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5881 | return; | |
5882 | ||
2fa2fe9a | 5883 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
5884 | if (!(tmp & PFIT_ENABLE)) |
5885 | return; | |
2fa2fe9a | 5886 | |
06922821 | 5887 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5888 | if (INTEL_INFO(dev)->gen < 4) { |
5889 | if (crtc->pipe != PIPE_B) | |
5890 | return; | |
2fa2fe9a DV |
5891 | } else { |
5892 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5893 | return; | |
5894 | } | |
5895 | ||
06922821 | 5896 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5897 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5898 | if (INTEL_INFO(dev)->gen < 5) | |
5899 | pipe_config->gmch_pfit.lvds_border_bits = | |
5900 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5901 | } | |
5902 | ||
acbec814 JB |
5903 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5904 | struct intel_crtc_config *pipe_config) | |
5905 | { | |
5906 | struct drm_device *dev = crtc->base.dev; | |
5907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5908 | int pipe = pipe_config->cpu_transcoder; | |
5909 | intel_clock_t clock; | |
5910 | u32 mdiv; | |
662c6ecb | 5911 | int refclk = 100000; |
acbec814 JB |
5912 | |
5913 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5914 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5915 | mutex_unlock(&dev_priv->dpio_lock); |
5916 | ||
5917 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5918 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5919 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5920 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5921 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5922 | ||
f646628b | 5923 | vlv_clock(refclk, &clock); |
acbec814 | 5924 | |
f646628b VS |
5925 | /* clock.dot is the fast clock */ |
5926 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5927 | } |
5928 | ||
1ad292b5 JB |
5929 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
5930 | struct intel_plane_config *plane_config) | |
5931 | { | |
5932 | struct drm_device *dev = crtc->base.dev; | |
5933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5934 | u32 val, base, offset; | |
5935 | int pipe = crtc->pipe, plane = crtc->plane; | |
5936 | int fourcc, pixel_format; | |
5937 | int aligned_height; | |
5938 | ||
66e514c1 DA |
5939 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
5940 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
5941 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
5942 | return; | |
5943 | } | |
5944 | ||
5945 | val = I915_READ(DSPCNTR(plane)); | |
5946 | ||
5947 | if (INTEL_INFO(dev)->gen >= 4) | |
5948 | if (val & DISPPLANE_TILED) | |
5949 | plane_config->tiled = true; | |
5950 | ||
5951 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
5952 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
5953 | crtc->base.primary->fb->pixel_format = fourcc; |
5954 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
5955 | drm_format_plane_cpp(fourcc, 0) * 8; |
5956 | ||
5957 | if (INTEL_INFO(dev)->gen >= 4) { | |
5958 | if (plane_config->tiled) | |
5959 | offset = I915_READ(DSPTILEOFF(plane)); | |
5960 | else | |
5961 | offset = I915_READ(DSPLINOFF(plane)); | |
5962 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
5963 | } else { | |
5964 | base = I915_READ(DSPADDR(plane)); | |
5965 | } | |
5966 | plane_config->base = base; | |
5967 | ||
5968 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
5969 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
5970 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
5971 | |
5972 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 5973 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
1ad292b5 | 5974 | |
66e514c1 | 5975 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
5976 | plane_config->tiled); |
5977 | ||
66e514c1 | 5978 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
1ad292b5 JB |
5979 | aligned_height, PAGE_SIZE); |
5980 | ||
5981 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
5982 | pipe, plane, crtc->base.primary->fb->width, |
5983 | crtc->base.primary->fb->height, | |
5984 | crtc->base.primary->fb->bits_per_pixel, base, | |
5985 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
5986 | plane_config->size); |
5987 | ||
5988 | } | |
5989 | ||
70b23a98 VS |
5990 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5991 | struct intel_crtc_config *pipe_config) | |
5992 | { | |
5993 | struct drm_device *dev = crtc->base.dev; | |
5994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5995 | int pipe = pipe_config->cpu_transcoder; | |
5996 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
5997 | intel_clock_t clock; | |
5998 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
5999 | int refclk = 100000; | |
6000 | ||
6001 | mutex_lock(&dev_priv->dpio_lock); | |
6002 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6003 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6004 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6005 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6006 | mutex_unlock(&dev_priv->dpio_lock); | |
6007 | ||
6008 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6009 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6010 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6011 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6012 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6013 | ||
6014 | chv_clock(refclk, &clock); | |
6015 | ||
6016 | /* clock.dot is the fast clock */ | |
6017 | pipe_config->port_clock = clock.dot / 5; | |
6018 | } | |
6019 | ||
0e8ffe1b DV |
6020 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6021 | struct intel_crtc_config *pipe_config) | |
6022 | { | |
6023 | struct drm_device *dev = crtc->base.dev; | |
6024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6025 | uint32_t tmp; | |
6026 | ||
b5482bd0 ID |
6027 | if (!intel_display_power_enabled(dev_priv, |
6028 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6029 | return false; | |
6030 | ||
e143a21c | 6031 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6032 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6033 | |
0e8ffe1b DV |
6034 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6035 | if (!(tmp & PIPECONF_ENABLE)) | |
6036 | return false; | |
6037 | ||
42571aef VS |
6038 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6039 | switch (tmp & PIPECONF_BPC_MASK) { | |
6040 | case PIPECONF_6BPC: | |
6041 | pipe_config->pipe_bpp = 18; | |
6042 | break; | |
6043 | case PIPECONF_8BPC: | |
6044 | pipe_config->pipe_bpp = 24; | |
6045 | break; | |
6046 | case PIPECONF_10BPC: | |
6047 | pipe_config->pipe_bpp = 30; | |
6048 | break; | |
6049 | default: | |
6050 | break; | |
6051 | } | |
6052 | } | |
6053 | ||
b5a9fa09 DV |
6054 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6055 | pipe_config->limited_color_range = true; | |
6056 | ||
282740f7 VS |
6057 | if (INTEL_INFO(dev)->gen < 4) |
6058 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6059 | ||
1bd1bd80 DV |
6060 | intel_get_pipe_timings(crtc, pipe_config); |
6061 | ||
2fa2fe9a DV |
6062 | i9xx_get_pfit_config(crtc, pipe_config); |
6063 | ||
6c49f241 DV |
6064 | if (INTEL_INFO(dev)->gen >= 4) { |
6065 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6066 | pipe_config->pixel_multiplier = | |
6067 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6068 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6069 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6070 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6071 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6072 | pipe_config->pixel_multiplier = | |
6073 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6074 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6075 | } else { | |
6076 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6077 | * port and will be fixed up in the encoder->get_config | |
6078 | * function. */ | |
6079 | pipe_config->pixel_multiplier = 1; | |
6080 | } | |
8bcc2795 DV |
6081 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6082 | if (!IS_VALLEYVIEW(dev)) { | |
6083 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6084 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6085 | } else { |
6086 | /* Mask out read-only status bits. */ | |
6087 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6088 | DPLL_PORTC_READY_MASK | | |
6089 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6090 | } |
6c49f241 | 6091 | |
70b23a98 VS |
6092 | if (IS_CHERRYVIEW(dev)) |
6093 | chv_crtc_clock_get(crtc, pipe_config); | |
6094 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6095 | vlv_crtc_clock_get(crtc, pipe_config); |
6096 | else | |
6097 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6098 | |
0e8ffe1b DV |
6099 | return true; |
6100 | } | |
6101 | ||
dde86e2d | 6102 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6103 | { |
6104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6105 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6106 | struct intel_encoder *encoder; |
74cfd7ac | 6107 | u32 val, final; |
13d83a67 | 6108 | bool has_lvds = false; |
199e5d79 | 6109 | bool has_cpu_edp = false; |
199e5d79 | 6110 | bool has_panel = false; |
99eb6a01 KP |
6111 | bool has_ck505 = false; |
6112 | bool can_ssc = false; | |
13d83a67 JB |
6113 | |
6114 | /* We need to take the global config into account */ | |
199e5d79 KP |
6115 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6116 | base.head) { | |
6117 | switch (encoder->type) { | |
6118 | case INTEL_OUTPUT_LVDS: | |
6119 | has_panel = true; | |
6120 | has_lvds = true; | |
6121 | break; | |
6122 | case INTEL_OUTPUT_EDP: | |
6123 | has_panel = true; | |
2de6905f | 6124 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6125 | has_cpu_edp = true; |
6126 | break; | |
13d83a67 JB |
6127 | } |
6128 | } | |
6129 | ||
99eb6a01 | 6130 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6131 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6132 | can_ssc = has_ck505; |
6133 | } else { | |
6134 | has_ck505 = false; | |
6135 | can_ssc = true; | |
6136 | } | |
6137 | ||
2de6905f ID |
6138 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6139 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6140 | |
6141 | /* Ironlake: try to setup display ref clock before DPLL | |
6142 | * enabling. This is only under driver's control after | |
6143 | * PCH B stepping, previous chipset stepping should be | |
6144 | * ignoring this setting. | |
6145 | */ | |
74cfd7ac CW |
6146 | val = I915_READ(PCH_DREF_CONTROL); |
6147 | ||
6148 | /* As we must carefully and slowly disable/enable each source in turn, | |
6149 | * compute the final state we want first and check if we need to | |
6150 | * make any changes at all. | |
6151 | */ | |
6152 | final = val; | |
6153 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6154 | if (has_ck505) | |
6155 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6156 | else | |
6157 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6158 | ||
6159 | final &= ~DREF_SSC_SOURCE_MASK; | |
6160 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6161 | final &= ~DREF_SSC1_ENABLE; | |
6162 | ||
6163 | if (has_panel) { | |
6164 | final |= DREF_SSC_SOURCE_ENABLE; | |
6165 | ||
6166 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6167 | final |= DREF_SSC1_ENABLE; | |
6168 | ||
6169 | if (has_cpu_edp) { | |
6170 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6171 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6172 | else | |
6173 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6174 | } else | |
6175 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6176 | } else { | |
6177 | final |= DREF_SSC_SOURCE_DISABLE; | |
6178 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6179 | } | |
6180 | ||
6181 | if (final == val) | |
6182 | return; | |
6183 | ||
13d83a67 | 6184 | /* Always enable nonspread source */ |
74cfd7ac | 6185 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6186 | |
99eb6a01 | 6187 | if (has_ck505) |
74cfd7ac | 6188 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6189 | else |
74cfd7ac | 6190 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6191 | |
199e5d79 | 6192 | if (has_panel) { |
74cfd7ac CW |
6193 | val &= ~DREF_SSC_SOURCE_MASK; |
6194 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6195 | |
199e5d79 | 6196 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6197 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6198 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6199 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6200 | } else |
74cfd7ac | 6201 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6202 | |
6203 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6204 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6205 | POSTING_READ(PCH_DREF_CONTROL); |
6206 | udelay(200); | |
6207 | ||
74cfd7ac | 6208 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6209 | |
6210 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6211 | if (has_cpu_edp) { |
99eb6a01 | 6212 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6213 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6214 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 6215 | } |
13d83a67 | 6216 | else |
74cfd7ac | 6217 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6218 | } else |
74cfd7ac | 6219 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6220 | |
74cfd7ac | 6221 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6222 | POSTING_READ(PCH_DREF_CONTROL); |
6223 | udelay(200); | |
6224 | } else { | |
6225 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6226 | ||
74cfd7ac | 6227 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6228 | |
6229 | /* Turn off CPU output */ | |
74cfd7ac | 6230 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6231 | |
74cfd7ac | 6232 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6233 | POSTING_READ(PCH_DREF_CONTROL); |
6234 | udelay(200); | |
6235 | ||
6236 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6237 | val &= ~DREF_SSC_SOURCE_MASK; |
6238 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6239 | |
6240 | /* Turn off SSC1 */ | |
74cfd7ac | 6241 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6242 | |
74cfd7ac | 6243 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6244 | POSTING_READ(PCH_DREF_CONTROL); |
6245 | udelay(200); | |
6246 | } | |
74cfd7ac CW |
6247 | |
6248 | BUG_ON(val != final); | |
13d83a67 JB |
6249 | } |
6250 | ||
f31f2d55 | 6251 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6252 | { |
f31f2d55 | 6253 | uint32_t tmp; |
dde86e2d | 6254 | |
0ff066a9 PZ |
6255 | tmp = I915_READ(SOUTH_CHICKEN2); |
6256 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6257 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6258 | |
0ff066a9 PZ |
6259 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6260 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6261 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6262 | |
0ff066a9 PZ |
6263 | tmp = I915_READ(SOUTH_CHICKEN2); |
6264 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6265 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6266 | |
0ff066a9 PZ |
6267 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6268 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6269 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6270 | } |
6271 | ||
6272 | /* WaMPhyProgramming:hsw */ | |
6273 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6274 | { | |
6275 | uint32_t tmp; | |
dde86e2d PZ |
6276 | |
6277 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6278 | tmp &= ~(0xFF << 24); | |
6279 | tmp |= (0x12 << 24); | |
6280 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6281 | ||
dde86e2d PZ |
6282 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6283 | tmp |= (1 << 11); | |
6284 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6285 | ||
6286 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6287 | tmp |= (1 << 11); | |
6288 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6289 | ||
dde86e2d PZ |
6290 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6291 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6292 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6293 | ||
6294 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6295 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6296 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6297 | ||
0ff066a9 PZ |
6298 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6299 | tmp &= ~(7 << 13); | |
6300 | tmp |= (5 << 13); | |
6301 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6302 | |
0ff066a9 PZ |
6303 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6304 | tmp &= ~(7 << 13); | |
6305 | tmp |= (5 << 13); | |
6306 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6307 | |
6308 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6309 | tmp &= ~0xFF; | |
6310 | tmp |= 0x1C; | |
6311 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6312 | ||
6313 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6314 | tmp &= ~0xFF; | |
6315 | tmp |= 0x1C; | |
6316 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6317 | ||
6318 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6319 | tmp &= ~(0xFF << 16); | |
6320 | tmp |= (0x1C << 16); | |
6321 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6322 | ||
6323 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6324 | tmp &= ~(0xFF << 16); | |
6325 | tmp |= (0x1C << 16); | |
6326 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6327 | ||
0ff066a9 PZ |
6328 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6329 | tmp |= (1 << 27); | |
6330 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6331 | |
0ff066a9 PZ |
6332 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6333 | tmp |= (1 << 27); | |
6334 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6335 | |
0ff066a9 PZ |
6336 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6337 | tmp &= ~(0xF << 28); | |
6338 | tmp |= (4 << 28); | |
6339 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6340 | |
0ff066a9 PZ |
6341 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6342 | tmp &= ~(0xF << 28); | |
6343 | tmp |= (4 << 28); | |
6344 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6345 | } |
6346 | ||
2fa86a1f PZ |
6347 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6348 | * Programming" based on the parameters passed: | |
6349 | * - Sequence to enable CLKOUT_DP | |
6350 | * - Sequence to enable CLKOUT_DP without spread | |
6351 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6352 | */ | |
6353 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6354 | bool with_fdi) | |
f31f2d55 PZ |
6355 | { |
6356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6357 | uint32_t reg, tmp; |
6358 | ||
6359 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6360 | with_spread = true; | |
6361 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6362 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6363 | with_fdi = false; | |
f31f2d55 PZ |
6364 | |
6365 | mutex_lock(&dev_priv->dpio_lock); | |
6366 | ||
6367 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6368 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6369 | tmp |= SBI_SSCCTL_PATHALT; | |
6370 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6371 | ||
6372 | udelay(24); | |
6373 | ||
2fa86a1f PZ |
6374 | if (with_spread) { |
6375 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6376 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6377 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6378 | |
2fa86a1f PZ |
6379 | if (with_fdi) { |
6380 | lpt_reset_fdi_mphy(dev_priv); | |
6381 | lpt_program_fdi_mphy(dev_priv); | |
6382 | } | |
6383 | } | |
dde86e2d | 6384 | |
2fa86a1f PZ |
6385 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6386 | SBI_GEN0 : SBI_DBUFF0; | |
6387 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6388 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6389 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6390 | |
6391 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6392 | } |
6393 | ||
47701c3b PZ |
6394 | /* Sequence to disable CLKOUT_DP */ |
6395 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6396 | { | |
6397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6398 | uint32_t reg, tmp; | |
6399 | ||
6400 | mutex_lock(&dev_priv->dpio_lock); | |
6401 | ||
6402 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6403 | SBI_GEN0 : SBI_DBUFF0; | |
6404 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6405 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6406 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6407 | ||
6408 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6409 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6410 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6411 | tmp |= SBI_SSCCTL_PATHALT; | |
6412 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6413 | udelay(32); | |
6414 | } | |
6415 | tmp |= SBI_SSCCTL_DISABLE; | |
6416 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6417 | } | |
6418 | ||
6419 | mutex_unlock(&dev_priv->dpio_lock); | |
6420 | } | |
6421 | ||
bf8fa3d3 PZ |
6422 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6423 | { | |
6424 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6425 | struct intel_encoder *encoder; | |
6426 | bool has_vga = false; | |
6427 | ||
6428 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6429 | switch (encoder->type) { | |
6430 | case INTEL_OUTPUT_ANALOG: | |
6431 | has_vga = true; | |
6432 | break; | |
6433 | } | |
6434 | } | |
6435 | ||
47701c3b PZ |
6436 | if (has_vga) |
6437 | lpt_enable_clkout_dp(dev, true, true); | |
6438 | else | |
6439 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6440 | } |
6441 | ||
dde86e2d PZ |
6442 | /* |
6443 | * Initialize reference clocks when the driver loads | |
6444 | */ | |
6445 | void intel_init_pch_refclk(struct drm_device *dev) | |
6446 | { | |
6447 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6448 | ironlake_init_pch_refclk(dev); | |
6449 | else if (HAS_PCH_LPT(dev)) | |
6450 | lpt_init_pch_refclk(dev); | |
6451 | } | |
6452 | ||
d9d444cb JB |
6453 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6454 | { | |
6455 | struct drm_device *dev = crtc->dev; | |
6456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6457 | struct intel_encoder *encoder; | |
d9d444cb JB |
6458 | int num_connectors = 0; |
6459 | bool is_lvds = false; | |
6460 | ||
6c2b7c12 | 6461 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6462 | switch (encoder->type) { |
6463 | case INTEL_OUTPUT_LVDS: | |
6464 | is_lvds = true; | |
6465 | break; | |
d9d444cb JB |
6466 | } |
6467 | num_connectors++; | |
6468 | } | |
6469 | ||
6470 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6471 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6472 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6473 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6474 | } |
6475 | ||
6476 | return 120000; | |
6477 | } | |
6478 | ||
6ff93609 | 6479 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6480 | { |
c8203565 | 6481 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6483 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6484 | uint32_t val; |
6485 | ||
78114071 | 6486 | val = 0; |
c8203565 | 6487 | |
965e0c48 | 6488 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6489 | case 18: |
dfd07d72 | 6490 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6491 | break; |
6492 | case 24: | |
dfd07d72 | 6493 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6494 | break; |
6495 | case 30: | |
dfd07d72 | 6496 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6497 | break; |
6498 | case 36: | |
dfd07d72 | 6499 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6500 | break; |
6501 | default: | |
cc769b62 PZ |
6502 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6503 | BUG(); | |
c8203565 PZ |
6504 | } |
6505 | ||
d8b32247 | 6506 | if (intel_crtc->config.dither) |
c8203565 PZ |
6507 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6508 | ||
6ff93609 | 6509 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6510 | val |= PIPECONF_INTERLACED_ILK; |
6511 | else | |
6512 | val |= PIPECONF_PROGRESSIVE; | |
6513 | ||
50f3b016 | 6514 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6515 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6516 | |
c8203565 PZ |
6517 | I915_WRITE(PIPECONF(pipe), val); |
6518 | POSTING_READ(PIPECONF(pipe)); | |
6519 | } | |
6520 | ||
86d3efce VS |
6521 | /* |
6522 | * Set up the pipe CSC unit. | |
6523 | * | |
6524 | * Currently only full range RGB to limited range RGB conversion | |
6525 | * is supported, but eventually this should handle various | |
6526 | * RGB<->YCbCr scenarios as well. | |
6527 | */ | |
50f3b016 | 6528 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6529 | { |
6530 | struct drm_device *dev = crtc->dev; | |
6531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6533 | int pipe = intel_crtc->pipe; | |
6534 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6535 | ||
6536 | /* | |
6537 | * TODO: Check what kind of values actually come out of the pipe | |
6538 | * with these coeff/postoff values and adjust to get the best | |
6539 | * accuracy. Perhaps we even need to take the bpc value into | |
6540 | * consideration. | |
6541 | */ | |
6542 | ||
50f3b016 | 6543 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6544 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6545 | ||
6546 | /* | |
6547 | * GY/GU and RY/RU should be the other way around according | |
6548 | * to BSpec, but reality doesn't agree. Just set them up in | |
6549 | * a way that results in the correct picture. | |
6550 | */ | |
6551 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6552 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6553 | ||
6554 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6555 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6556 | ||
6557 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6558 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6559 | ||
6560 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6561 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6562 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6563 | ||
6564 | if (INTEL_INFO(dev)->gen > 6) { | |
6565 | uint16_t postoff = 0; | |
6566 | ||
50f3b016 | 6567 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6568 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6569 | |
6570 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6571 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6572 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6573 | ||
6574 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6575 | } else { | |
6576 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6577 | ||
50f3b016 | 6578 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6579 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6580 | ||
6581 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6582 | } | |
6583 | } | |
6584 | ||
6ff93609 | 6585 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6586 | { |
756f85cf PZ |
6587 | struct drm_device *dev = crtc->dev; |
6588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6589 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6590 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6591 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6592 | uint32_t val; |
6593 | ||
3eff4faa | 6594 | val = 0; |
ee2b0b38 | 6595 | |
756f85cf | 6596 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6597 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6598 | ||
6ff93609 | 6599 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6600 | val |= PIPECONF_INTERLACED_ILK; |
6601 | else | |
6602 | val |= PIPECONF_PROGRESSIVE; | |
6603 | ||
702e7a56 PZ |
6604 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6605 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6606 | |
6607 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6608 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6609 | |
6610 | if (IS_BROADWELL(dev)) { | |
6611 | val = 0; | |
6612 | ||
6613 | switch (intel_crtc->config.pipe_bpp) { | |
6614 | case 18: | |
6615 | val |= PIPEMISC_DITHER_6_BPC; | |
6616 | break; | |
6617 | case 24: | |
6618 | val |= PIPEMISC_DITHER_8_BPC; | |
6619 | break; | |
6620 | case 30: | |
6621 | val |= PIPEMISC_DITHER_10_BPC; | |
6622 | break; | |
6623 | case 36: | |
6624 | val |= PIPEMISC_DITHER_12_BPC; | |
6625 | break; | |
6626 | default: | |
6627 | /* Case prevented by pipe_config_set_bpp. */ | |
6628 | BUG(); | |
6629 | } | |
6630 | ||
6631 | if (intel_crtc->config.dither) | |
6632 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6633 | ||
6634 | I915_WRITE(PIPEMISC(pipe), val); | |
6635 | } | |
ee2b0b38 PZ |
6636 | } |
6637 | ||
6591c6e4 | 6638 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6639 | intel_clock_t *clock, |
6640 | bool *has_reduced_clock, | |
6641 | intel_clock_t *reduced_clock) | |
6642 | { | |
6643 | struct drm_device *dev = crtc->dev; | |
6644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6645 | struct intel_encoder *intel_encoder; | |
6646 | int refclk; | |
d4906093 | 6647 | const intel_limit_t *limit; |
a16af721 | 6648 | bool ret, is_lvds = false; |
79e53945 | 6649 | |
6591c6e4 PZ |
6650 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6651 | switch (intel_encoder->type) { | |
79e53945 JB |
6652 | case INTEL_OUTPUT_LVDS: |
6653 | is_lvds = true; | |
6654 | break; | |
79e53945 JB |
6655 | } |
6656 | } | |
6657 | ||
d9d444cb | 6658 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6659 | |
d4906093 ML |
6660 | /* |
6661 | * Returns a set of divisors for the desired target clock with the given | |
6662 | * refclk, or FALSE. The returned values represent the clock equation: | |
6663 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6664 | */ | |
1b894b59 | 6665 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6666 | ret = dev_priv->display.find_dpll(limit, crtc, |
6667 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6668 | refclk, NULL, clock); |
6591c6e4 PZ |
6669 | if (!ret) |
6670 | return false; | |
cda4b7d3 | 6671 | |
ddc9003c | 6672 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6673 | /* |
6674 | * Ensure we match the reduced clock's P to the target clock. | |
6675 | * If the clocks don't match, we can't switch the display clock | |
6676 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6677 | * downclock feature. | |
6678 | */ | |
ee9300bb DV |
6679 | *has_reduced_clock = |
6680 | dev_priv->display.find_dpll(limit, crtc, | |
6681 | dev_priv->lvds_downclock, | |
6682 | refclk, clock, | |
6683 | reduced_clock); | |
652c393a | 6684 | } |
61e9653f | 6685 | |
6591c6e4 PZ |
6686 | return true; |
6687 | } | |
6688 | ||
d4b1931c PZ |
6689 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6690 | { | |
6691 | /* | |
6692 | * Account for spread spectrum to avoid | |
6693 | * oversubscribing the link. Max center spread | |
6694 | * is 2.5%; use 5% for safety's sake. | |
6695 | */ | |
6696 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6697 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6698 | } |
6699 | ||
7429e9d4 | 6700 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6701 | { |
7429e9d4 | 6702 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6703 | } |
6704 | ||
de13a2e3 | 6705 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6706 | u32 *fp, |
9a7c7890 | 6707 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6708 | { |
de13a2e3 | 6709 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6710 | struct drm_device *dev = crtc->dev; |
6711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6712 | struct intel_encoder *intel_encoder; |
6713 | uint32_t dpll; | |
6cc5f341 | 6714 | int factor, num_connectors = 0; |
09ede541 | 6715 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6716 | |
de13a2e3 PZ |
6717 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6718 | switch (intel_encoder->type) { | |
79e53945 JB |
6719 | case INTEL_OUTPUT_LVDS: |
6720 | is_lvds = true; | |
6721 | break; | |
6722 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6723 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6724 | is_sdvo = true; |
79e53945 | 6725 | break; |
79e53945 | 6726 | } |
43565a06 | 6727 | |
c751ce4f | 6728 | num_connectors++; |
79e53945 | 6729 | } |
79e53945 | 6730 | |
c1858123 | 6731 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6732 | factor = 21; |
6733 | if (is_lvds) { | |
6734 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6735 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6736 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6737 | factor = 25; |
09ede541 | 6738 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6739 | factor = 20; |
c1858123 | 6740 | |
7429e9d4 | 6741 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6742 | *fp |= FP_CB_TUNE; |
2c07245f | 6743 | |
9a7c7890 DV |
6744 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6745 | *fp2 |= FP_CB_TUNE; | |
6746 | ||
5eddb70b | 6747 | dpll = 0; |
2c07245f | 6748 | |
a07d6787 EA |
6749 | if (is_lvds) |
6750 | dpll |= DPLLB_MODE_LVDS; | |
6751 | else | |
6752 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6753 | |
ef1b460d DV |
6754 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6755 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6756 | |
6757 | if (is_sdvo) | |
4a33e48d | 6758 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6759 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6760 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6761 | |
a07d6787 | 6762 | /* compute bitmask from p1 value */ |
7429e9d4 | 6763 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6764 | /* also FPA1 */ |
7429e9d4 | 6765 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6766 | |
7429e9d4 | 6767 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6768 | case 5: |
6769 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6770 | break; | |
6771 | case 7: | |
6772 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6773 | break; | |
6774 | case 10: | |
6775 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6776 | break; | |
6777 | case 14: | |
6778 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6779 | break; | |
79e53945 JB |
6780 | } |
6781 | ||
b4c09f3b | 6782 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6783 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6784 | else |
6785 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6786 | ||
959e16d6 | 6787 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6788 | } |
6789 | ||
6790 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6791 | int x, int y, |
6792 | struct drm_framebuffer *fb) | |
6793 | { | |
6794 | struct drm_device *dev = crtc->dev; | |
6795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6797 | int pipe = intel_crtc->pipe; | |
6798 | int plane = intel_crtc->plane; | |
6799 | int num_connectors = 0; | |
6800 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6801 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6802 | bool ok, has_reduced_clock = false; |
8b47047b | 6803 | bool is_lvds = false; |
de13a2e3 | 6804 | struct intel_encoder *encoder; |
e2b78267 | 6805 | struct intel_shared_dpll *pll; |
de13a2e3 | 6806 | int ret; |
de13a2e3 PZ |
6807 | |
6808 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6809 | switch (encoder->type) { | |
6810 | case INTEL_OUTPUT_LVDS: | |
6811 | is_lvds = true; | |
6812 | break; | |
de13a2e3 PZ |
6813 | } |
6814 | ||
6815 | num_connectors++; | |
a07d6787 | 6816 | } |
79e53945 | 6817 | |
5dc5298b PZ |
6818 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6819 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6820 | |
ff9a6750 | 6821 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6822 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6823 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6824 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6825 | return -EINVAL; | |
79e53945 | 6826 | } |
f47709a9 DV |
6827 | /* Compat-code for transition, will disappear. */ |
6828 | if (!intel_crtc->config.clock_set) { | |
6829 | intel_crtc->config.dpll.n = clock.n; | |
6830 | intel_crtc->config.dpll.m1 = clock.m1; | |
6831 | intel_crtc->config.dpll.m2 = clock.m2; | |
6832 | intel_crtc->config.dpll.p1 = clock.p1; | |
6833 | intel_crtc->config.dpll.p2 = clock.p2; | |
6834 | } | |
79e53945 | 6835 | |
5dc5298b | 6836 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6837 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6838 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6839 | if (has_reduced_clock) |
7429e9d4 | 6840 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6841 | |
7429e9d4 | 6842 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6843 | &fp, &reduced_clock, |
6844 | has_reduced_clock ? &fp2 : NULL); | |
6845 | ||
959e16d6 | 6846 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6847 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6848 | if (has_reduced_clock) | |
6849 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6850 | else | |
6851 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6852 | ||
b89a1d39 | 6853 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6854 | if (pll == NULL) { |
84f44ce7 VS |
6855 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6856 | pipe_name(pipe)); | |
4b645f14 JB |
6857 | return -EINVAL; |
6858 | } | |
ee7b9f93 | 6859 | } else |
e72f9fbf | 6860 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6861 | |
03afc4a2 DV |
6862 | if (intel_crtc->config.has_dp_encoder) |
6863 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6864 | |
d330a953 | 6865 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
6866 | intel_crtc->lowfreq_avail = true; |
6867 | else | |
6868 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6869 | |
8a654f3b | 6870 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6871 | |
ca3a0ff8 | 6872 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6873 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6874 | &intel_crtc->config.fdi_m_n); | |
6875 | } | |
2c07245f | 6876 | |
6ff93609 | 6877 | ironlake_set_pipeconf(crtc); |
79e53945 | 6878 | |
a1f9e77e PZ |
6879 | /* Set up the display plane register */ |
6880 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6881 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6882 | |
94352cf9 | 6883 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6884 | |
1857e1da | 6885 | return ret; |
79e53945 JB |
6886 | } |
6887 | ||
eb14cb74 VS |
6888 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6889 | struct intel_link_m_n *m_n) | |
6890 | { | |
6891 | struct drm_device *dev = crtc->base.dev; | |
6892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6893 | enum pipe pipe = crtc->pipe; | |
6894 | ||
6895 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6896 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6897 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6898 | & ~TU_SIZE_MASK; | |
6899 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6900 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6901 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6902 | } | |
6903 | ||
6904 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6905 | enum transcoder transcoder, | |
6906 | struct intel_link_m_n *m_n) | |
72419203 DV |
6907 | { |
6908 | struct drm_device *dev = crtc->base.dev; | |
6909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6910 | enum pipe pipe = crtc->pipe; |
72419203 | 6911 | |
eb14cb74 VS |
6912 | if (INTEL_INFO(dev)->gen >= 5) { |
6913 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6914 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6915 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6916 | & ~TU_SIZE_MASK; | |
6917 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6918 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6919 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6920 | } else { | |
6921 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6922 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6923 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6924 | & ~TU_SIZE_MASK; | |
6925 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6926 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6927 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6928 | } | |
6929 | } | |
6930 | ||
6931 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6932 | struct intel_crtc_config *pipe_config) | |
6933 | { | |
6934 | if (crtc->config.has_pch_encoder) | |
6935 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6936 | else | |
6937 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6938 | &pipe_config->dp_m_n); | |
6939 | } | |
72419203 | 6940 | |
eb14cb74 VS |
6941 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6942 | struct intel_crtc_config *pipe_config) | |
6943 | { | |
6944 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6945 | &pipe_config->fdi_m_n); | |
72419203 DV |
6946 | } |
6947 | ||
2fa2fe9a DV |
6948 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6949 | struct intel_crtc_config *pipe_config) | |
6950 | { | |
6951 | struct drm_device *dev = crtc->base.dev; | |
6952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6953 | uint32_t tmp; | |
6954 | ||
6955 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6956 | ||
6957 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6958 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6959 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6960 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6961 | |
6962 | /* We currently do not free assignements of panel fitters on | |
6963 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6964 | * differentiates them) so just WARN about this case for now. */ | |
6965 | if (IS_GEN7(dev)) { | |
6966 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6967 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6968 | } | |
2fa2fe9a | 6969 | } |
79e53945 JB |
6970 | } |
6971 | ||
4c6baa59 JB |
6972 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
6973 | struct intel_plane_config *plane_config) | |
6974 | { | |
6975 | struct drm_device *dev = crtc->base.dev; | |
6976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6977 | u32 val, base, offset; | |
6978 | int pipe = crtc->pipe, plane = crtc->plane; | |
6979 | int fourcc, pixel_format; | |
6980 | int aligned_height; | |
6981 | ||
66e514c1 DA |
6982 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6983 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
6984 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6985 | return; | |
6986 | } | |
6987 | ||
6988 | val = I915_READ(DSPCNTR(plane)); | |
6989 | ||
6990 | if (INTEL_INFO(dev)->gen >= 4) | |
6991 | if (val & DISPPLANE_TILED) | |
6992 | plane_config->tiled = true; | |
6993 | ||
6994 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6995 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6996 | crtc->base.primary->fb->pixel_format = fourcc; |
6997 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
6998 | drm_format_plane_cpp(fourcc, 0) * 8; |
6999 | ||
7000 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7001 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7002 | offset = I915_READ(DSPOFFSET(plane)); | |
7003 | } else { | |
7004 | if (plane_config->tiled) | |
7005 | offset = I915_READ(DSPTILEOFF(plane)); | |
7006 | else | |
7007 | offset = I915_READ(DSPLINOFF(plane)); | |
7008 | } | |
7009 | plane_config->base = base; | |
7010 | ||
7011 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7012 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7013 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7014 | |
7015 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 7016 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
4c6baa59 | 7017 | |
66e514c1 | 7018 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7019 | plane_config->tiled); |
7020 | ||
66e514c1 | 7021 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
4c6baa59 JB |
7022 | aligned_height, PAGE_SIZE); |
7023 | ||
7024 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7025 | pipe, plane, crtc->base.primary->fb->width, |
7026 | crtc->base.primary->fb->height, | |
7027 | crtc->base.primary->fb->bits_per_pixel, base, | |
7028 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7029 | plane_config->size); |
7030 | } | |
7031 | ||
0e8ffe1b DV |
7032 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7033 | struct intel_crtc_config *pipe_config) | |
7034 | { | |
7035 | struct drm_device *dev = crtc->base.dev; | |
7036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7037 | uint32_t tmp; | |
7038 | ||
e143a21c | 7039 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7040 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7041 | |
0e8ffe1b DV |
7042 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7043 | if (!(tmp & PIPECONF_ENABLE)) | |
7044 | return false; | |
7045 | ||
42571aef VS |
7046 | switch (tmp & PIPECONF_BPC_MASK) { |
7047 | case PIPECONF_6BPC: | |
7048 | pipe_config->pipe_bpp = 18; | |
7049 | break; | |
7050 | case PIPECONF_8BPC: | |
7051 | pipe_config->pipe_bpp = 24; | |
7052 | break; | |
7053 | case PIPECONF_10BPC: | |
7054 | pipe_config->pipe_bpp = 30; | |
7055 | break; | |
7056 | case PIPECONF_12BPC: | |
7057 | pipe_config->pipe_bpp = 36; | |
7058 | break; | |
7059 | default: | |
7060 | break; | |
7061 | } | |
7062 | ||
b5a9fa09 DV |
7063 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7064 | pipe_config->limited_color_range = true; | |
7065 | ||
ab9412ba | 7066 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7067 | struct intel_shared_dpll *pll; |
7068 | ||
88adfff1 DV |
7069 | pipe_config->has_pch_encoder = true; |
7070 | ||
627eb5a3 DV |
7071 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7072 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7073 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7074 | |
7075 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7076 | |
c0d43d62 | 7077 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7078 | pipe_config->shared_dpll = |
7079 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7080 | } else { |
7081 | tmp = I915_READ(PCH_DPLL_SEL); | |
7082 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7083 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7084 | else | |
7085 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7086 | } | |
66e985c0 DV |
7087 | |
7088 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7089 | ||
7090 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7091 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7092 | |
7093 | tmp = pipe_config->dpll_hw_state.dpll; | |
7094 | pipe_config->pixel_multiplier = | |
7095 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7096 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7097 | |
7098 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7099 | } else { |
7100 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7101 | } |
7102 | ||
1bd1bd80 DV |
7103 | intel_get_pipe_timings(crtc, pipe_config); |
7104 | ||
2fa2fe9a DV |
7105 | ironlake_get_pfit_config(crtc, pipe_config); |
7106 | ||
0e8ffe1b DV |
7107 | return true; |
7108 | } | |
7109 | ||
be256dc7 PZ |
7110 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7111 | { | |
7112 | struct drm_device *dev = dev_priv->dev; | |
7113 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
7114 | struct intel_crtc *crtc; | |
be256dc7 | 7115 | |
d3fcc808 | 7116 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7117 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7118 | pipe_name(crtc->pipe)); |
7119 | ||
7120 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
7121 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
7122 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
7123 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
7124 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7125 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7126 | "CPU PWM1 enabled\n"); | |
7127 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7128 | "CPU PWM2 enabled\n"); | |
7129 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
7130 | "PCH PWM1 enabled\n"); | |
7131 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7132 | "Utility pin enabled\n"); | |
7133 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7134 | ||
9926ada1 PZ |
7135 | /* |
7136 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7137 | * interrupts remain enabled. We used to check for that, but since it's | |
7138 | * gen-specific and since we only disable LCPLL after we fully disable | |
7139 | * the interrupts, the check below should be enough. | |
7140 | */ | |
7141 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | |
be256dc7 PZ |
7142 | } |
7143 | ||
3c4c9b81 PZ |
7144 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7145 | { | |
7146 | struct drm_device *dev = dev_priv->dev; | |
7147 | ||
7148 | if (IS_HASWELL(dev)) { | |
7149 | mutex_lock(&dev_priv->rps.hw_lock); | |
7150 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7151 | val)) | |
7152 | DRM_ERROR("Failed to disable D_COMP\n"); | |
7153 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7154 | } else { | |
7155 | I915_WRITE(D_COMP, val); | |
7156 | } | |
7157 | POSTING_READ(D_COMP); | |
be256dc7 PZ |
7158 | } |
7159 | ||
7160 | /* | |
7161 | * This function implements pieces of two sequences from BSpec: | |
7162 | * - Sequence for display software to disable LCPLL | |
7163 | * - Sequence for display software to allow package C8+ | |
7164 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7165 | * register. Callers should take care of disabling all the display engine | |
7166 | * functions, doing the mode unset, fixing interrupts, etc. | |
7167 | */ | |
6ff58d53 PZ |
7168 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7169 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7170 | { |
7171 | uint32_t val; | |
7172 | ||
7173 | assert_can_disable_lcpll(dev_priv); | |
7174 | ||
7175 | val = I915_READ(LCPLL_CTL); | |
7176 | ||
7177 | if (switch_to_fclk) { | |
7178 | val |= LCPLL_CD_SOURCE_FCLK; | |
7179 | I915_WRITE(LCPLL_CTL, val); | |
7180 | ||
7181 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7182 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7183 | DRM_ERROR("Switching to FCLK failed\n"); | |
7184 | ||
7185 | val = I915_READ(LCPLL_CTL); | |
7186 | } | |
7187 | ||
7188 | val |= LCPLL_PLL_DISABLE; | |
7189 | I915_WRITE(LCPLL_CTL, val); | |
7190 | POSTING_READ(LCPLL_CTL); | |
7191 | ||
7192 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7193 | DRM_ERROR("LCPLL still locked\n"); | |
7194 | ||
7195 | val = I915_READ(D_COMP); | |
7196 | val |= D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7197 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7198 | ndelay(100); |
7199 | ||
7200 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
7201 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
7202 | ||
7203 | if (allow_power_down) { | |
7204 | val = I915_READ(LCPLL_CTL); | |
7205 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7206 | I915_WRITE(LCPLL_CTL, val); | |
7207 | POSTING_READ(LCPLL_CTL); | |
7208 | } | |
7209 | } | |
7210 | ||
7211 | /* | |
7212 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7213 | * source. | |
7214 | */ | |
6ff58d53 | 7215 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7216 | { |
7217 | uint32_t val; | |
a8a8bd54 | 7218 | unsigned long irqflags; |
be256dc7 PZ |
7219 | |
7220 | val = I915_READ(LCPLL_CTL); | |
7221 | ||
7222 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7223 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7224 | return; | |
7225 | ||
a8a8bd54 PZ |
7226 | /* |
7227 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7228 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7229 | * | |
7230 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7231 | * the runtime PM resume sequence, so we can't just call | |
7232 | * gen6_gt_force_wake_get() because that function calls | |
7233 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7234 | * while we are on the resume sequence. So to solve this problem we have | |
7235 | * to call special forcewake code that doesn't touch runtime PM and | |
7236 | * doesn't enable the forcewake delayed work. | |
7237 | */ | |
7238 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7239 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7240 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7241 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7242 | |
be256dc7 PZ |
7243 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7244 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7245 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7246 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7247 | } |
7248 | ||
7249 | val = I915_READ(D_COMP); | |
7250 | val |= D_COMP_COMP_FORCE; | |
7251 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7252 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7253 | |
7254 | val = I915_READ(LCPLL_CTL); | |
7255 | val &= ~LCPLL_PLL_DISABLE; | |
7256 | I915_WRITE(LCPLL_CTL, val); | |
7257 | ||
7258 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7259 | DRM_ERROR("LCPLL not locked yet\n"); | |
7260 | ||
7261 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7262 | val = I915_READ(LCPLL_CTL); | |
7263 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7264 | I915_WRITE(LCPLL_CTL, val); | |
7265 | ||
7266 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7267 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7268 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7269 | } | |
215733fa | 7270 | |
a8a8bd54 PZ |
7271 | /* See the big comment above. */ |
7272 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7273 | if (--dev_priv->uncore.forcewake_count == 0) | |
7274 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7275 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7276 | } |
7277 | ||
765dab67 PZ |
7278 | /* |
7279 | * Package states C8 and deeper are really deep PC states that can only be | |
7280 | * reached when all the devices on the system allow it, so even if the graphics | |
7281 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7282 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7283 | * | |
7284 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7285 | * well is disabled and most interrupts are disabled, and these are also | |
7286 | * requirements for runtime PM. When these conditions are met, we manually do | |
7287 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7288 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7289 | * hang the machine. | |
7290 | * | |
7291 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7292 | * the state of some registers, so when we come back from PC8+ we need to | |
7293 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7294 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7295 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7296 | * because of the runtime PM support). | |
7297 | * | |
7298 | * For more, read "Display Sequences for Package C8" on the hardware | |
7299 | * documentation. | |
7300 | */ | |
a14cb6fc | 7301 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7302 | { |
c67a470b PZ |
7303 | struct drm_device *dev = dev_priv->dev; |
7304 | uint32_t val; | |
7305 | ||
c67a470b PZ |
7306 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7307 | ||
c67a470b PZ |
7308 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7309 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7310 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7311 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7312 | } | |
7313 | ||
7314 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7315 | hsw_disable_lcpll(dev_priv, true, true); |
7316 | } | |
7317 | ||
a14cb6fc | 7318 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7319 | { |
7320 | struct drm_device *dev = dev_priv->dev; | |
7321 | uint32_t val; | |
7322 | ||
c67a470b PZ |
7323 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7324 | ||
7325 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7326 | lpt_init_pch_refclk(dev); |
7327 | ||
7328 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7329 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7330 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7331 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7332 | } | |
7333 | ||
7334 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7335 | } |
7336 | ||
9a952a0d PZ |
7337 | static void snb_modeset_global_resources(struct drm_device *dev) |
7338 | { | |
7339 | modeset_update_crtc_power_domains(dev); | |
7340 | } | |
7341 | ||
4f074129 ID |
7342 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7343 | { | |
da723569 | 7344 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7345 | } |
7346 | ||
09b4ddf9 | 7347 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7348 | int x, int y, |
7349 | struct drm_framebuffer *fb) | |
7350 | { | |
7351 | struct drm_device *dev = crtc->dev; | |
7352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7353 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 7354 | int plane = intel_crtc->plane; |
09b4ddf9 | 7355 | int ret; |
09b4ddf9 | 7356 | |
566b734a | 7357 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7358 | return -EINVAL; |
566b734a | 7359 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7360 | |
03afc4a2 DV |
7361 | if (intel_crtc->config.has_dp_encoder) |
7362 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
7363 | |
7364 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 7365 | |
8a654f3b | 7366 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 7367 | |
ca3a0ff8 | 7368 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
7369 | intel_cpu_transcoder_set_m_n(intel_crtc, |
7370 | &intel_crtc->config.fdi_m_n); | |
7371 | } | |
09b4ddf9 | 7372 | |
6ff93609 | 7373 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 7374 | |
50f3b016 | 7375 | intel_set_pipe_csc(crtc); |
86d3efce | 7376 | |
09b4ddf9 | 7377 | /* Set up the display plane register */ |
86d3efce | 7378 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
7379 | POSTING_READ(DSPCNTR(plane)); |
7380 | ||
7381 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
7382 | ||
1f803ee5 | 7383 | return ret; |
79e53945 JB |
7384 | } |
7385 | ||
0e8ffe1b DV |
7386 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7387 | struct intel_crtc_config *pipe_config) | |
7388 | { | |
7389 | struct drm_device *dev = crtc->base.dev; | |
7390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7391 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7392 | uint32_t tmp; |
7393 | ||
b5482bd0 ID |
7394 | if (!intel_display_power_enabled(dev_priv, |
7395 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7396 | return false; | |
7397 | ||
e143a21c | 7398 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7399 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7400 | ||
eccb140b DV |
7401 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7402 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7403 | enum pipe trans_edp_pipe; | |
7404 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7405 | default: | |
7406 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7407 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7408 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7409 | trans_edp_pipe = PIPE_A; | |
7410 | break; | |
7411 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7412 | trans_edp_pipe = PIPE_B; | |
7413 | break; | |
7414 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7415 | trans_edp_pipe = PIPE_C; | |
7416 | break; | |
7417 | } | |
7418 | ||
7419 | if (trans_edp_pipe == crtc->pipe) | |
7420 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7421 | } | |
7422 | ||
da7e29bd | 7423 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7424 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7425 | return false; |
7426 | ||
eccb140b | 7427 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7428 | if (!(tmp & PIPECONF_ENABLE)) |
7429 | return false; | |
7430 | ||
88adfff1 | 7431 | /* |
f196e6be | 7432 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7433 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7434 | * the PCH transcoder is on. | |
7435 | */ | |
eccb140b | 7436 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7437 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7438 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7439 | pipe_config->has_pch_encoder = true; |
7440 | ||
627eb5a3 DV |
7441 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7442 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7443 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7444 | |
7445 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7446 | } |
7447 | ||
1bd1bd80 DV |
7448 | intel_get_pipe_timings(crtc, pipe_config); |
7449 | ||
2fa2fe9a | 7450 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7451 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7452 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7453 | |
e59150dc JB |
7454 | if (IS_HASWELL(dev)) |
7455 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7456 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7457 | |
6c49f241 DV |
7458 | pipe_config->pixel_multiplier = 1; |
7459 | ||
0e8ffe1b DV |
7460 | return true; |
7461 | } | |
7462 | ||
1a91510d JN |
7463 | static struct { |
7464 | int clock; | |
7465 | u32 config; | |
7466 | } hdmi_audio_clock[] = { | |
7467 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7468 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7469 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7470 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7471 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7472 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7473 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7474 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7475 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7476 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7477 | }; | |
7478 | ||
7479 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7480 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7481 | { | |
7482 | int i; | |
7483 | ||
7484 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7485 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7486 | break; | |
7487 | } | |
7488 | ||
7489 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7490 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7491 | i = 1; | |
7492 | } | |
7493 | ||
7494 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7495 | hdmi_audio_clock[i].clock, | |
7496 | hdmi_audio_clock[i].config); | |
7497 | ||
7498 | return hdmi_audio_clock[i].config; | |
7499 | } | |
7500 | ||
3a9627f4 WF |
7501 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7502 | int reg_eldv, uint32_t bits_eldv, | |
7503 | int reg_elda, uint32_t bits_elda, | |
7504 | int reg_edid) | |
7505 | { | |
7506 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7507 | uint8_t *eld = connector->eld; | |
7508 | uint32_t i; | |
7509 | ||
7510 | i = I915_READ(reg_eldv); | |
7511 | i &= bits_eldv; | |
7512 | ||
7513 | if (!eld[0]) | |
7514 | return !i; | |
7515 | ||
7516 | if (!i) | |
7517 | return false; | |
7518 | ||
7519 | i = I915_READ(reg_elda); | |
7520 | i &= ~bits_elda; | |
7521 | I915_WRITE(reg_elda, i); | |
7522 | ||
7523 | for (i = 0; i < eld[2]; i++) | |
7524 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7525 | return false; | |
7526 | ||
7527 | return true; | |
7528 | } | |
7529 | ||
e0dac65e | 7530 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7531 | struct drm_crtc *crtc, |
7532 | struct drm_display_mode *mode) | |
e0dac65e WF |
7533 | { |
7534 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7535 | uint8_t *eld = connector->eld; | |
7536 | uint32_t eldv; | |
7537 | uint32_t len; | |
7538 | uint32_t i; | |
7539 | ||
7540 | i = I915_READ(G4X_AUD_VID_DID); | |
7541 | ||
7542 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7543 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7544 | else | |
7545 | eldv = G4X_ELDV_DEVCTG; | |
7546 | ||
3a9627f4 WF |
7547 | if (intel_eld_uptodate(connector, |
7548 | G4X_AUD_CNTL_ST, eldv, | |
7549 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7550 | G4X_HDMIW_HDMIEDID)) | |
7551 | return; | |
7552 | ||
e0dac65e WF |
7553 | i = I915_READ(G4X_AUD_CNTL_ST); |
7554 | i &= ~(eldv | G4X_ELD_ADDR); | |
7555 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7556 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7557 | ||
7558 | if (!eld[0]) | |
7559 | return; | |
7560 | ||
7561 | len = min_t(uint8_t, eld[2], len); | |
7562 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7563 | for (i = 0; i < len; i++) | |
7564 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7565 | ||
7566 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7567 | i |= eldv; | |
7568 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7569 | } | |
7570 | ||
83358c85 | 7571 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7572 | struct drm_crtc *crtc, |
7573 | struct drm_display_mode *mode) | |
83358c85 WX |
7574 | { |
7575 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7576 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7577 | uint32_t eldv; |
7578 | uint32_t i; | |
7579 | int len; | |
7580 | int pipe = to_intel_crtc(crtc)->pipe; | |
7581 | int tmp; | |
7582 | ||
7583 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7584 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7585 | int aud_config = HSW_AUD_CFG(pipe); | |
7586 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7587 | ||
83358c85 WX |
7588 | /* Audio output enable */ |
7589 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7590 | tmp = I915_READ(aud_cntrl_st2); | |
7591 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7592 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7593 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7594 | |
c7905792 | 7595 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7596 | |
7597 | /* Set ELD valid state */ | |
7598 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7599 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7600 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7601 | I915_WRITE(aud_cntrl_st2, tmp); | |
7602 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7603 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7604 | |
7605 | /* Enable HDMI mode */ | |
7606 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7607 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7608 | /* clear N_programing_enable and N_value_index */ |
7609 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7610 | I915_WRITE(aud_config, tmp); | |
7611 | ||
7612 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7613 | ||
7614 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7615 | ||
7616 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7617 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7618 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7619 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7620 | } else { |
7621 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7622 | } | |
83358c85 WX |
7623 | |
7624 | if (intel_eld_uptodate(connector, | |
7625 | aud_cntrl_st2, eldv, | |
7626 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7627 | hdmiw_hdmiedid)) | |
7628 | return; | |
7629 | ||
7630 | i = I915_READ(aud_cntrl_st2); | |
7631 | i &= ~eldv; | |
7632 | I915_WRITE(aud_cntrl_st2, i); | |
7633 | ||
7634 | if (!eld[0]) | |
7635 | return; | |
7636 | ||
7637 | i = I915_READ(aud_cntl_st); | |
7638 | i &= ~IBX_ELD_ADDRESS; | |
7639 | I915_WRITE(aud_cntl_st, i); | |
7640 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7641 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7642 | ||
7643 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7644 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7645 | for (i = 0; i < len; i++) | |
7646 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7647 | ||
7648 | i = I915_READ(aud_cntrl_st2); | |
7649 | i |= eldv; | |
7650 | I915_WRITE(aud_cntrl_st2, i); | |
7651 | ||
7652 | } | |
7653 | ||
e0dac65e | 7654 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7655 | struct drm_crtc *crtc, |
7656 | struct drm_display_mode *mode) | |
e0dac65e WF |
7657 | { |
7658 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7659 | uint8_t *eld = connector->eld; | |
7660 | uint32_t eldv; | |
7661 | uint32_t i; | |
7662 | int len; | |
7663 | int hdmiw_hdmiedid; | |
b6daa025 | 7664 | int aud_config; |
e0dac65e WF |
7665 | int aud_cntl_st; |
7666 | int aud_cntrl_st2; | |
9b138a83 | 7667 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7668 | |
b3f33cbf | 7669 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7670 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7671 | aud_config = IBX_AUD_CFG(pipe); | |
7672 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7673 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7674 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7675 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7676 | aud_config = VLV_AUD_CFG(pipe); | |
7677 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7678 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7679 | } else { |
9b138a83 WX |
7680 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7681 | aud_config = CPT_AUD_CFG(pipe); | |
7682 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7683 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7684 | } |
7685 | ||
9b138a83 | 7686 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7687 | |
9ca2fe73 ML |
7688 | if (IS_VALLEYVIEW(connector->dev)) { |
7689 | struct intel_encoder *intel_encoder; | |
7690 | struct intel_digital_port *intel_dig_port; | |
7691 | ||
7692 | intel_encoder = intel_attached_encoder(connector); | |
7693 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7694 | i = intel_dig_port->port; | |
7695 | } else { | |
7696 | i = I915_READ(aud_cntl_st); | |
7697 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7698 | /* DIP_Port_Select, 0x1 = PortB */ | |
7699 | } | |
7700 | ||
e0dac65e WF |
7701 | if (!i) { |
7702 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7703 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7704 | eldv = IBX_ELD_VALIDB; |
7705 | eldv |= IBX_ELD_VALIDB << 4; | |
7706 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7707 | } else { |
2582a850 | 7708 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7709 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7710 | } |
7711 | ||
3a9627f4 WF |
7712 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7713 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7714 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7715 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7716 | } else { |
7717 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7718 | } | |
e0dac65e | 7719 | |
3a9627f4 WF |
7720 | if (intel_eld_uptodate(connector, |
7721 | aud_cntrl_st2, eldv, | |
7722 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7723 | hdmiw_hdmiedid)) | |
7724 | return; | |
7725 | ||
e0dac65e WF |
7726 | i = I915_READ(aud_cntrl_st2); |
7727 | i &= ~eldv; | |
7728 | I915_WRITE(aud_cntrl_st2, i); | |
7729 | ||
7730 | if (!eld[0]) | |
7731 | return; | |
7732 | ||
e0dac65e | 7733 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7734 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7735 | I915_WRITE(aud_cntl_st, i); |
7736 | ||
7737 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7738 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7739 | for (i = 0; i < len; i++) | |
7740 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7741 | ||
7742 | i = I915_READ(aud_cntrl_st2); | |
7743 | i |= eldv; | |
7744 | I915_WRITE(aud_cntrl_st2, i); | |
7745 | } | |
7746 | ||
7747 | void intel_write_eld(struct drm_encoder *encoder, | |
7748 | struct drm_display_mode *mode) | |
7749 | { | |
7750 | struct drm_crtc *crtc = encoder->crtc; | |
7751 | struct drm_connector *connector; | |
7752 | struct drm_device *dev = encoder->dev; | |
7753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7754 | ||
7755 | connector = drm_select_eld(encoder, mode); | |
7756 | if (!connector) | |
7757 | return; | |
7758 | ||
7759 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7760 | connector->base.id, | |
7761 | drm_get_connector_name(connector), | |
7762 | connector->encoder->base.id, | |
7763 | drm_get_encoder_name(connector->encoder)); | |
7764 | ||
7765 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7766 | ||
7767 | if (dev_priv->display.write_eld) | |
34427052 | 7768 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7769 | } |
7770 | ||
560b85bb CW |
7771 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7772 | { | |
7773 | struct drm_device *dev = crtc->dev; | |
7774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7776 | bool visible = base != 0; | |
7777 | u32 cntl; | |
7778 | ||
7779 | if (intel_crtc->cursor_visible == visible) | |
7780 | return; | |
7781 | ||
9db4a9c7 | 7782 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7783 | if (visible) { |
7784 | /* On these chipsets we can only modify the base whilst | |
7785 | * the cursor is disabled. | |
7786 | */ | |
9db4a9c7 | 7787 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7788 | |
7789 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7790 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7791 | cntl |= CURSOR_ENABLE | | |
7792 | CURSOR_GAMMA_ENABLE | | |
7793 | CURSOR_FORMAT_ARGB; | |
7794 | } else | |
7795 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7796 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7797 | |
7798 | intel_crtc->cursor_visible = visible; | |
7799 | } | |
7800 | ||
7801 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7802 | { | |
7803 | struct drm_device *dev = crtc->dev; | |
7804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7806 | int pipe = intel_crtc->pipe; | |
7807 | bool visible = base != 0; | |
7808 | ||
7809 | if (intel_crtc->cursor_visible != visible) { | |
4726e0b0 | 7810 | int16_t width = intel_crtc->cursor_width; |
548f245b | 7811 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7812 | if (base) { |
7813 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4726e0b0 SK |
7814 | cntl |= MCURSOR_GAMMA_ENABLE; |
7815 | ||
7816 | switch (width) { | |
7817 | case 64: | |
7818 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7819 | break; | |
7820 | case 128: | |
7821 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7822 | break; | |
7823 | case 256: | |
7824 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7825 | break; | |
7826 | default: | |
7827 | WARN_ON(1); | |
7828 | return; | |
7829 | } | |
560b85bb CW |
7830 | cntl |= pipe << 28; /* Connect to correct pipe */ |
7831 | } else { | |
7832 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7833 | cntl |= CURSOR_MODE_DISABLE; | |
7834 | } | |
9db4a9c7 | 7835 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7836 | |
7837 | intel_crtc->cursor_visible = visible; | |
7838 | } | |
7839 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7840 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7841 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7842 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7843 | } |
7844 | ||
65a21cd6 JB |
7845 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7846 | { | |
7847 | struct drm_device *dev = crtc->dev; | |
7848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7850 | int pipe = intel_crtc->pipe; | |
7851 | bool visible = base != 0; | |
7852 | ||
7853 | if (intel_crtc->cursor_visible != visible) { | |
4726e0b0 | 7854 | int16_t width = intel_crtc->cursor_width; |
65a21cd6 JB |
7855 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
7856 | if (base) { | |
7857 | cntl &= ~CURSOR_MODE; | |
4726e0b0 SK |
7858 | cntl |= MCURSOR_GAMMA_ENABLE; |
7859 | switch (width) { | |
7860 | case 64: | |
7861 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7862 | break; | |
7863 | case 128: | |
7864 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7865 | break; | |
7866 | case 256: | |
7867 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7868 | break; | |
7869 | default: | |
7870 | WARN_ON(1); | |
7871 | return; | |
7872 | } | |
65a21cd6 JB |
7873 | } else { |
7874 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7875 | cntl |= CURSOR_MODE_DISABLE; | |
7876 | } | |
6bbfa1c5 | 7877 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7878 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7879 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7880 | } | |
65a21cd6 JB |
7881 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7882 | ||
7883 | intel_crtc->cursor_visible = visible; | |
7884 | } | |
7885 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7886 | POSTING_READ(CURCNTR_IVB(pipe)); |
65a21cd6 | 7887 | I915_WRITE(CURBASE_IVB(pipe), base); |
b2ea8ef5 | 7888 | POSTING_READ(CURBASE_IVB(pipe)); |
65a21cd6 JB |
7889 | } |
7890 | ||
cda4b7d3 | 7891 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7892 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7893 | bool on) | |
cda4b7d3 CW |
7894 | { |
7895 | struct drm_device *dev = crtc->dev; | |
7896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7898 | int pipe = intel_crtc->pipe; | |
7899 | int x = intel_crtc->cursor_x; | |
7900 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7901 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7902 | bool visible; |
7903 | ||
d6e4db15 | 7904 | if (on) |
cda4b7d3 | 7905 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7906 | |
d6e4db15 VS |
7907 | if (x >= intel_crtc->config.pipe_src_w) |
7908 | base = 0; | |
7909 | ||
7910 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7911 | base = 0; |
7912 | ||
7913 | if (x < 0) { | |
efc9064e | 7914 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7915 | base = 0; |
7916 | ||
7917 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7918 | x = -x; | |
7919 | } | |
7920 | pos |= x << CURSOR_X_SHIFT; | |
7921 | ||
7922 | if (y < 0) { | |
efc9064e | 7923 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7924 | base = 0; |
7925 | ||
7926 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7927 | y = -y; | |
7928 | } | |
7929 | pos |= y << CURSOR_Y_SHIFT; | |
7930 | ||
7931 | visible = base != 0; | |
560b85bb | 7932 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7933 | return; |
7934 | ||
b3dc685e | 7935 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7936 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7937 | ivb_update_cursor(crtc, base); | |
7938 | } else { | |
7939 | I915_WRITE(CURPOS(pipe), pos); | |
7940 | if (IS_845G(dev) || IS_I865G(dev)) | |
7941 | i845_update_cursor(crtc, base); | |
7942 | else | |
7943 | i9xx_update_cursor(crtc, base); | |
7944 | } | |
cda4b7d3 CW |
7945 | } |
7946 | ||
79e53945 | 7947 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7948 | struct drm_file *file, |
79e53945 JB |
7949 | uint32_t handle, |
7950 | uint32_t width, uint32_t height) | |
7951 | { | |
7952 | struct drm_device *dev = crtc->dev; | |
7953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7955 | struct drm_i915_gem_object *obj; |
64f962e3 | 7956 | unsigned old_width; |
cda4b7d3 | 7957 | uint32_t addr; |
3f8bc370 | 7958 | int ret; |
79e53945 | 7959 | |
79e53945 JB |
7960 | /* if we want to turn off the cursor ignore width and height */ |
7961 | if (!handle) { | |
28c97730 | 7962 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7963 | addr = 0; |
05394f39 | 7964 | obj = NULL; |
5004417d | 7965 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7966 | goto finish; |
79e53945 JB |
7967 | } |
7968 | ||
4726e0b0 SK |
7969 | /* Check for which cursor types we support */ |
7970 | if (!((width == 64 && height == 64) || | |
7971 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
7972 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
7973 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
7974 | return -EINVAL; |
7975 | } | |
7976 | ||
05394f39 | 7977 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7978 | if (&obj->base == NULL) |
79e53945 JB |
7979 | return -ENOENT; |
7980 | ||
05394f39 | 7981 | if (obj->base.size < width * height * 4) { |
3b25b31f | 7982 | DRM_DEBUG_KMS("buffer is to small\n"); |
34b8686e DA |
7983 | ret = -ENOMEM; |
7984 | goto fail; | |
79e53945 JB |
7985 | } |
7986 | ||
71acb5eb | 7987 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7988 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 7989 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
7990 | unsigned alignment; |
7991 | ||
d9e86c0e | 7992 | if (obj->tiling_mode) { |
3b25b31f | 7993 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
7994 | ret = -EINVAL; |
7995 | goto fail_locked; | |
7996 | } | |
7997 | ||
693db184 CW |
7998 | /* Note that the w/a also requires 2 PTE of padding following |
7999 | * the bo. We currently fill all unused PTE with the shadow | |
8000 | * page and so we should always have valid PTE following the | |
8001 | * cursor preventing the VT-d warning. | |
8002 | */ | |
8003 | alignment = 0; | |
8004 | if (need_vtd_wa(dev)) | |
8005 | alignment = 64*1024; | |
8006 | ||
8007 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8008 | if (ret) { |
3b25b31f | 8009 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8010 | goto fail_locked; |
e7b526bb CW |
8011 | } |
8012 | ||
d9e86c0e CW |
8013 | ret = i915_gem_object_put_fence(obj); |
8014 | if (ret) { | |
3b25b31f | 8015 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8016 | goto fail_unpin; |
8017 | } | |
8018 | ||
f343c5f6 | 8019 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8020 | } else { |
6eeefaf3 | 8021 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 8022 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
8023 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
8024 | align); | |
71acb5eb | 8025 | if (ret) { |
3b25b31f | 8026 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8027 | goto fail_locked; |
71acb5eb | 8028 | } |
05394f39 | 8029 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
8030 | } |
8031 | ||
a6c45cf0 | 8032 | if (IS_GEN2(dev)) |
14b60391 JB |
8033 | I915_WRITE(CURSIZE, (height << 12) | width); |
8034 | ||
3f8bc370 | 8035 | finish: |
3f8bc370 | 8036 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 8037 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 8038 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
8039 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
8040 | } else | |
cc98b413 | 8041 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 8042 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 8043 | } |
80824003 | 8044 | |
7f9872e0 | 8045 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8046 | |
64f962e3 CW |
8047 | old_width = intel_crtc->cursor_width; |
8048 | ||
3f8bc370 | 8049 | intel_crtc->cursor_addr = addr; |
05394f39 | 8050 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8051 | intel_crtc->cursor_width = width; |
8052 | intel_crtc->cursor_height = height; | |
8053 | ||
64f962e3 CW |
8054 | if (intel_crtc->active) { |
8055 | if (old_width != width) | |
8056 | intel_update_watermarks(crtc); | |
f2f5f771 | 8057 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8058 | } |
3f8bc370 | 8059 | |
79e53945 | 8060 | return 0; |
e7b526bb | 8061 | fail_unpin: |
cc98b413 | 8062 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8063 | fail_locked: |
34b8686e | 8064 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8065 | fail: |
05394f39 | 8066 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8067 | return ret; |
79e53945 JB |
8068 | } |
8069 | ||
8070 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
8071 | { | |
79e53945 | 8072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8073 | |
92e76c8c VS |
8074 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
8075 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 8076 | |
f2f5f771 VS |
8077 | if (intel_crtc->active) |
8078 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
8079 | |
8080 | return 0; | |
b8c00ac5 DA |
8081 | } |
8082 | ||
79e53945 | 8083 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8084 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8085 | { |
7203425a | 8086 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8087 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8088 | |
7203425a | 8089 | for (i = start; i < end; i++) { |
79e53945 JB |
8090 | intel_crtc->lut_r[i] = red[i] >> 8; |
8091 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8092 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8093 | } | |
8094 | ||
8095 | intel_crtc_load_lut(crtc); | |
8096 | } | |
8097 | ||
79e53945 JB |
8098 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8099 | static struct drm_display_mode load_detect_mode = { | |
8100 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8101 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8102 | }; | |
8103 | ||
a8bb6818 DV |
8104 | struct drm_framebuffer * |
8105 | __intel_framebuffer_create(struct drm_device *dev, | |
8106 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8107 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8108 | { |
8109 | struct intel_framebuffer *intel_fb; | |
8110 | int ret; | |
8111 | ||
8112 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8113 | if (!intel_fb) { | |
8114 | drm_gem_object_unreference_unlocked(&obj->base); | |
8115 | return ERR_PTR(-ENOMEM); | |
8116 | } | |
8117 | ||
8118 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8119 | if (ret) |
8120 | goto err; | |
d2dff872 CW |
8121 | |
8122 | return &intel_fb->base; | |
dd4916c5 DV |
8123 | err: |
8124 | drm_gem_object_unreference_unlocked(&obj->base); | |
8125 | kfree(intel_fb); | |
8126 | ||
8127 | return ERR_PTR(ret); | |
d2dff872 CW |
8128 | } |
8129 | ||
b5ea642a | 8130 | static struct drm_framebuffer * |
a8bb6818 DV |
8131 | intel_framebuffer_create(struct drm_device *dev, |
8132 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8133 | struct drm_i915_gem_object *obj) | |
8134 | { | |
8135 | struct drm_framebuffer *fb; | |
8136 | int ret; | |
8137 | ||
8138 | ret = i915_mutex_lock_interruptible(dev); | |
8139 | if (ret) | |
8140 | return ERR_PTR(ret); | |
8141 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8142 | mutex_unlock(&dev->struct_mutex); | |
8143 | ||
8144 | return fb; | |
8145 | } | |
8146 | ||
d2dff872 CW |
8147 | static u32 |
8148 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8149 | { | |
8150 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8151 | return ALIGN(pitch, 64); | |
8152 | } | |
8153 | ||
8154 | static u32 | |
8155 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8156 | { | |
8157 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
8158 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
8159 | } | |
8160 | ||
8161 | static struct drm_framebuffer * | |
8162 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8163 | struct drm_display_mode *mode, | |
8164 | int depth, int bpp) | |
8165 | { | |
8166 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8167 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8168 | |
8169 | obj = i915_gem_alloc_object(dev, | |
8170 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8171 | if (obj == NULL) | |
8172 | return ERR_PTR(-ENOMEM); | |
8173 | ||
8174 | mode_cmd.width = mode->hdisplay; | |
8175 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8176 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8177 | bpp); | |
5ca0c34a | 8178 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8179 | |
8180 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8181 | } | |
8182 | ||
8183 | static struct drm_framebuffer * | |
8184 | mode_fits_in_fbdev(struct drm_device *dev, | |
8185 | struct drm_display_mode *mode) | |
8186 | { | |
4520f53a | 8187 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8188 | struct drm_i915_private *dev_priv = dev->dev_private; |
8189 | struct drm_i915_gem_object *obj; | |
8190 | struct drm_framebuffer *fb; | |
8191 | ||
4c0e5528 | 8192 | if (!dev_priv->fbdev) |
d2dff872 CW |
8193 | return NULL; |
8194 | ||
4c0e5528 | 8195 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8196 | return NULL; |
8197 | ||
4c0e5528 DV |
8198 | obj = dev_priv->fbdev->fb->obj; |
8199 | BUG_ON(!obj); | |
8200 | ||
8bcd4553 | 8201 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8202 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8203 | fb->bits_per_pixel)) | |
d2dff872 CW |
8204 | return NULL; |
8205 | ||
01f2c773 | 8206 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8207 | return NULL; |
8208 | ||
8209 | return fb; | |
4520f53a DV |
8210 | #else |
8211 | return NULL; | |
8212 | #endif | |
d2dff872 CW |
8213 | } |
8214 | ||
d2434ab7 | 8215 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8216 | struct drm_display_mode *mode, |
8261b191 | 8217 | struct intel_load_detect_pipe *old) |
79e53945 JB |
8218 | { |
8219 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8220 | struct intel_encoder *intel_encoder = |
8221 | intel_attached_encoder(connector); | |
79e53945 | 8222 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8223 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8224 | struct drm_crtc *crtc = NULL; |
8225 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8226 | struct drm_framebuffer *fb; |
79e53945 JB |
8227 | int i = -1; |
8228 | ||
d2dff872 CW |
8229 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8230 | connector->base.id, drm_get_connector_name(connector), | |
8231 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8232 | ||
79e53945 JB |
8233 | /* |
8234 | * Algorithm gets a little messy: | |
7a5e4805 | 8235 | * |
79e53945 JB |
8236 | * - if the connector already has an assigned crtc, use it (but make |
8237 | * sure it's on first) | |
7a5e4805 | 8238 | * |
79e53945 JB |
8239 | * - try to find the first unused crtc that can drive this connector, |
8240 | * and use that if we find one | |
79e53945 JB |
8241 | */ |
8242 | ||
8243 | /* See if we already have a CRTC for this connector */ | |
8244 | if (encoder->crtc) { | |
8245 | crtc = encoder->crtc; | |
8261b191 | 8246 | |
7b24056b DV |
8247 | mutex_lock(&crtc->mutex); |
8248 | ||
24218aac | 8249 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8250 | old->load_detect_temp = false; |
8251 | ||
8252 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8253 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8254 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8255 | |
7173188d | 8256 | return true; |
79e53945 JB |
8257 | } |
8258 | ||
8259 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8260 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8261 | i++; |
8262 | if (!(encoder->possible_crtcs & (1 << i))) | |
8263 | continue; | |
8264 | if (!possible_crtc->enabled) { | |
8265 | crtc = possible_crtc; | |
8266 | break; | |
8267 | } | |
79e53945 JB |
8268 | } |
8269 | ||
8270 | /* | |
8271 | * If we didn't find an unused CRTC, don't use any. | |
8272 | */ | |
8273 | if (!crtc) { | |
7173188d CW |
8274 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
8275 | return false; | |
79e53945 JB |
8276 | } |
8277 | ||
7b24056b | 8278 | mutex_lock(&crtc->mutex); |
fc303101 DV |
8279 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8280 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8281 | |
8282 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8283 | intel_crtc->new_enabled = true; |
8284 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8285 | old->dpms_mode = connector->dpms; |
8261b191 | 8286 | old->load_detect_temp = true; |
d2dff872 | 8287 | old->release_fb = NULL; |
79e53945 | 8288 | |
6492711d CW |
8289 | if (!mode) |
8290 | mode = &load_detect_mode; | |
79e53945 | 8291 | |
d2dff872 CW |
8292 | /* We need a framebuffer large enough to accommodate all accesses |
8293 | * that the plane may generate whilst we perform load detection. | |
8294 | * We can not rely on the fbcon either being present (we get called | |
8295 | * during its initialisation to detect all boot displays, or it may | |
8296 | * not even exist) or that it is large enough to satisfy the | |
8297 | * requested mode. | |
8298 | */ | |
94352cf9 DV |
8299 | fb = mode_fits_in_fbdev(dev, mode); |
8300 | if (fb == NULL) { | |
d2dff872 | 8301 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8302 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8303 | old->release_fb = fb; | |
d2dff872 CW |
8304 | } else |
8305 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8306 | if (IS_ERR(fb)) { |
d2dff872 | 8307 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8308 | goto fail; |
79e53945 | 8309 | } |
79e53945 | 8310 | |
c0c36b94 | 8311 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8312 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8313 | if (old->release_fb) |
8314 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8315 | goto fail; |
79e53945 | 8316 | } |
7173188d | 8317 | |
79e53945 | 8318 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8319 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8320 | return true; |
412b61d8 VS |
8321 | |
8322 | fail: | |
8323 | intel_crtc->new_enabled = crtc->enabled; | |
8324 | if (intel_crtc->new_enabled) | |
8325 | intel_crtc->new_config = &intel_crtc->config; | |
8326 | else | |
8327 | intel_crtc->new_config = NULL; | |
8328 | mutex_unlock(&crtc->mutex); | |
8329 | return false; | |
79e53945 JB |
8330 | } |
8331 | ||
d2434ab7 | 8332 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 8333 | struct intel_load_detect_pipe *old) |
79e53945 | 8334 | { |
d2434ab7 DV |
8335 | struct intel_encoder *intel_encoder = |
8336 | intel_attached_encoder(connector); | |
4ef69c7a | 8337 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8338 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8340 | |
d2dff872 CW |
8341 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8342 | connector->base.id, drm_get_connector_name(connector), | |
8343 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8344 | ||
8261b191 | 8345 | if (old->load_detect_temp) { |
fc303101 DV |
8346 | to_intel_connector(connector)->new_encoder = NULL; |
8347 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8348 | intel_crtc->new_enabled = false; |
8349 | intel_crtc->new_config = NULL; | |
fc303101 | 8350 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8351 | |
36206361 DV |
8352 | if (old->release_fb) { |
8353 | drm_framebuffer_unregister_private(old->release_fb); | |
8354 | drm_framebuffer_unreference(old->release_fb); | |
8355 | } | |
d2dff872 | 8356 | |
67c96400 | 8357 | mutex_unlock(&crtc->mutex); |
0622a53c | 8358 | return; |
79e53945 JB |
8359 | } |
8360 | ||
c751ce4f | 8361 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8362 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8363 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
8364 | |
8365 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
8366 | } |
8367 | ||
da4a1efa VS |
8368 | static int i9xx_pll_refclk(struct drm_device *dev, |
8369 | const struct intel_crtc_config *pipe_config) | |
8370 | { | |
8371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8372 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8373 | ||
8374 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8375 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8376 | else if (HAS_PCH_SPLIT(dev)) |
8377 | return 120000; | |
8378 | else if (!IS_GEN2(dev)) | |
8379 | return 96000; | |
8380 | else | |
8381 | return 48000; | |
8382 | } | |
8383 | ||
79e53945 | 8384 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8385 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8386 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8387 | { |
f1f644dc | 8388 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8389 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8390 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8391 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8392 | u32 fp; |
8393 | intel_clock_t clock; | |
da4a1efa | 8394 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8395 | |
8396 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8397 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8398 | else |
293623f7 | 8399 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8400 | |
8401 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8402 | if (IS_PINEVIEW(dev)) { |
8403 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8404 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8405 | } else { |
8406 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8407 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8408 | } | |
8409 | ||
a6c45cf0 | 8410 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8411 | if (IS_PINEVIEW(dev)) |
8412 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8413 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8414 | else |
8415 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8416 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8417 | ||
8418 | switch (dpll & DPLL_MODE_MASK) { | |
8419 | case DPLLB_MODE_DAC_SERIAL: | |
8420 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8421 | 5 : 10; | |
8422 | break; | |
8423 | case DPLLB_MODE_LVDS: | |
8424 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8425 | 7 : 14; | |
8426 | break; | |
8427 | default: | |
28c97730 | 8428 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8429 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8430 | return; |
79e53945 JB |
8431 | } |
8432 | ||
ac58c3f0 | 8433 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8434 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8435 | else |
da4a1efa | 8436 | i9xx_clock(refclk, &clock); |
79e53945 | 8437 | } else { |
0fb58223 | 8438 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8439 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8440 | |
8441 | if (is_lvds) { | |
8442 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8443 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8444 | |
8445 | if (lvds & LVDS_CLKB_POWER_UP) | |
8446 | clock.p2 = 7; | |
8447 | else | |
8448 | clock.p2 = 14; | |
79e53945 JB |
8449 | } else { |
8450 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8451 | clock.p1 = 2; | |
8452 | else { | |
8453 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8454 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8455 | } | |
8456 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8457 | clock.p2 = 4; | |
8458 | else | |
8459 | clock.p2 = 2; | |
79e53945 | 8460 | } |
da4a1efa VS |
8461 | |
8462 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8463 | } |
8464 | ||
18442d08 VS |
8465 | /* |
8466 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8467 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8468 | * encoder's get_config() function. |
8469 | */ | |
8470 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8471 | } |
8472 | ||
6878da05 VS |
8473 | int intel_dotclock_calculate(int link_freq, |
8474 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8475 | { |
f1f644dc JB |
8476 | /* |
8477 | * The calculation for the data clock is: | |
1041a02f | 8478 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8479 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8480 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8481 | * |
8482 | * and the link clock is simpler: | |
1041a02f | 8483 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8484 | */ |
8485 | ||
6878da05 VS |
8486 | if (!m_n->link_n) |
8487 | return 0; | |
f1f644dc | 8488 | |
6878da05 VS |
8489 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8490 | } | |
f1f644dc | 8491 | |
18442d08 VS |
8492 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8493 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8494 | { |
8495 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8496 | |
18442d08 VS |
8497 | /* read out port_clock from the DPLL */ |
8498 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8499 | |
f1f644dc | 8500 | /* |
18442d08 | 8501 | * This value does not include pixel_multiplier. |
241bfc38 | 8502 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8503 | * agree once we know their relationship in the encoder's |
8504 | * get_config() function. | |
79e53945 | 8505 | */ |
241bfc38 | 8506 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8507 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8508 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8509 | } |
8510 | ||
8511 | /** Returns the currently programmed mode of the given pipe. */ | |
8512 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8513 | struct drm_crtc *crtc) | |
8514 | { | |
548f245b | 8515 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8516 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8517 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8518 | struct drm_display_mode *mode; |
f1f644dc | 8519 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8520 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8521 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8522 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8523 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8524 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8525 | |
8526 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8527 | if (!mode) | |
8528 | return NULL; | |
8529 | ||
f1f644dc JB |
8530 | /* |
8531 | * Construct a pipe_config sufficient for getting the clock info | |
8532 | * back out of crtc_clock_get. | |
8533 | * | |
8534 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8535 | * to use a real value here instead. | |
8536 | */ | |
293623f7 | 8537 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8538 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8539 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8540 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8541 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8542 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8543 | ||
773ae034 | 8544 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8545 | mode->hdisplay = (htot & 0xffff) + 1; |
8546 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8547 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8548 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8549 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8550 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8551 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8552 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8553 | ||
8554 | drm_mode_set_name(mode); | |
79e53945 JB |
8555 | |
8556 | return mode; | |
8557 | } | |
8558 | ||
3dec0095 | 8559 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8560 | { |
8561 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8562 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a JB |
8563 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8564 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8565 | int dpll_reg = DPLL(pipe); |
8566 | int dpll; | |
652c393a | 8567 | |
bad720ff | 8568 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8569 | return; |
8570 | ||
8571 | if (!dev_priv->lvds_downclock_avail) | |
8572 | return; | |
8573 | ||
dbdc6479 | 8574 | dpll = I915_READ(dpll_reg); |
652c393a | 8575 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8576 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8577 | |
8ac5a6d5 | 8578 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8579 | |
8580 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8581 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8582 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8583 | |
652c393a JB |
8584 | dpll = I915_READ(dpll_reg); |
8585 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8586 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8587 | } |
652c393a JB |
8588 | } |
8589 | ||
8590 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8591 | { | |
8592 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8593 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8594 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8595 | |
bad720ff | 8596 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8597 | return; |
8598 | ||
8599 | if (!dev_priv->lvds_downclock_avail) | |
8600 | return; | |
8601 | ||
8602 | /* | |
8603 | * Since this is called by a timer, we should never get here in | |
8604 | * the manual case. | |
8605 | */ | |
8606 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8607 | int pipe = intel_crtc->pipe; |
8608 | int dpll_reg = DPLL(pipe); | |
8609 | int dpll; | |
f6e5b160 | 8610 | |
44d98a61 | 8611 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8612 | |
8ac5a6d5 | 8613 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8614 | |
dc257cf1 | 8615 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8616 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8617 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8618 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8619 | dpll = I915_READ(dpll_reg); |
8620 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8621 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8622 | } |
8623 | ||
8624 | } | |
8625 | ||
f047e395 CW |
8626 | void intel_mark_busy(struct drm_device *dev) |
8627 | { | |
c67a470b PZ |
8628 | struct drm_i915_private *dev_priv = dev->dev_private; |
8629 | ||
f62a0076 CW |
8630 | if (dev_priv->mm.busy) |
8631 | return; | |
8632 | ||
43694d69 | 8633 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8634 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8635 | dev_priv->mm.busy = true; |
f047e395 CW |
8636 | } |
8637 | ||
8638 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8639 | { |
c67a470b | 8640 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8641 | struct drm_crtc *crtc; |
652c393a | 8642 | |
f62a0076 CW |
8643 | if (!dev_priv->mm.busy) |
8644 | return; | |
8645 | ||
8646 | dev_priv->mm.busy = false; | |
8647 | ||
d330a953 | 8648 | if (!i915.powersave) |
bb4cdd53 | 8649 | goto out; |
652c393a | 8650 | |
70e1e0ec | 8651 | for_each_crtc(dev, crtc) { |
f4510a27 | 8652 | if (!crtc->primary->fb) |
652c393a JB |
8653 | continue; |
8654 | ||
725a5b54 | 8655 | intel_decrease_pllclock(crtc); |
652c393a | 8656 | } |
b29c19b6 | 8657 | |
3d13ef2e | 8658 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8659 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8660 | |
8661 | out: | |
43694d69 | 8662 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8663 | } |
8664 | ||
c65355bb CW |
8665 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8666 | struct intel_ring_buffer *ring) | |
652c393a | 8667 | { |
f047e395 CW |
8668 | struct drm_device *dev = obj->base.dev; |
8669 | struct drm_crtc *crtc; | |
652c393a | 8670 | |
d330a953 | 8671 | if (!i915.powersave) |
acb87dfb CW |
8672 | return; |
8673 | ||
70e1e0ec | 8674 | for_each_crtc(dev, crtc) { |
f4510a27 | 8675 | if (!crtc->primary->fb) |
652c393a JB |
8676 | continue; |
8677 | ||
f4510a27 | 8678 | if (to_intel_framebuffer(crtc->primary->fb)->obj != obj) |
c65355bb CW |
8679 | continue; |
8680 | ||
8681 | intel_increase_pllclock(crtc); | |
8682 | if (ring && intel_fbc_enabled(dev)) | |
8683 | ring->fbc_dirty = true; | |
652c393a JB |
8684 | } |
8685 | } | |
8686 | ||
79e53945 JB |
8687 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8688 | { | |
8689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8690 | struct drm_device *dev = crtc->dev; |
8691 | struct intel_unpin_work *work; | |
8692 | unsigned long flags; | |
8693 | ||
8694 | spin_lock_irqsave(&dev->event_lock, flags); | |
8695 | work = intel_crtc->unpin_work; | |
8696 | intel_crtc->unpin_work = NULL; | |
8697 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8698 | ||
8699 | if (work) { | |
8700 | cancel_work_sync(&work->work); | |
8701 | kfree(work); | |
8702 | } | |
79e53945 | 8703 | |
40ccc72b MK |
8704 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8705 | ||
79e53945 | 8706 | drm_crtc_cleanup(crtc); |
67e77c5a | 8707 | |
79e53945 JB |
8708 | kfree(intel_crtc); |
8709 | } | |
8710 | ||
6b95a207 KH |
8711 | static void intel_unpin_work_fn(struct work_struct *__work) |
8712 | { | |
8713 | struct intel_unpin_work *work = | |
8714 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8715 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8716 | |
b4a98e57 | 8717 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8718 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8719 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8720 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8721 | |
b4a98e57 CW |
8722 | intel_update_fbc(dev); |
8723 | mutex_unlock(&dev->struct_mutex); | |
8724 | ||
8725 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8726 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8727 | ||
6b95a207 KH |
8728 | kfree(work); |
8729 | } | |
8730 | ||
1afe3e9d | 8731 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8732 | struct drm_crtc *crtc) |
6b95a207 | 8733 | { |
fbee40df | 8734 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8735 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8736 | struct intel_unpin_work *work; | |
6b95a207 KH |
8737 | unsigned long flags; |
8738 | ||
8739 | /* Ignore early vblank irqs */ | |
8740 | if (intel_crtc == NULL) | |
8741 | return; | |
8742 | ||
8743 | spin_lock_irqsave(&dev->event_lock, flags); | |
8744 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8745 | |
8746 | /* Ensure we don't miss a work->pending update ... */ | |
8747 | smp_rmb(); | |
8748 | ||
8749 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8750 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8751 | return; | |
8752 | } | |
8753 | ||
e7d841ca CW |
8754 | /* and that the unpin work is consistent wrt ->pending. */ |
8755 | smp_rmb(); | |
8756 | ||
6b95a207 | 8757 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8758 | |
45a066eb RC |
8759 | if (work->event) |
8760 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8761 | |
0af7e4df MK |
8762 | drm_vblank_put(dev, intel_crtc->pipe); |
8763 | ||
6b95a207 KH |
8764 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8765 | ||
2c10d571 | 8766 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8767 | |
8768 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8769 | |
8770 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8771 | } |
8772 | ||
1afe3e9d JB |
8773 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8774 | { | |
fbee40df | 8775 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8776 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8777 | ||
49b14a5c | 8778 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8779 | } |
8780 | ||
8781 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8782 | { | |
fbee40df | 8783 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8784 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
8785 | ||
49b14a5c | 8786 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8787 | } |
8788 | ||
6b95a207 KH |
8789 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8790 | { | |
fbee40df | 8791 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8792 | struct intel_crtc *intel_crtc = |
8793 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8794 | unsigned long flags; | |
8795 | ||
e7d841ca CW |
8796 | /* NB: An MMIO update of the plane base pointer will also |
8797 | * generate a page-flip completion irq, i.e. every modeset | |
8798 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8799 | */ | |
6b95a207 | 8800 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8801 | if (intel_crtc->unpin_work) |
8802 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8803 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8804 | } | |
8805 | ||
e7d841ca CW |
8806 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8807 | { | |
8808 | /* Ensure that the work item is consistent when activating it ... */ | |
8809 | smp_wmb(); | |
8810 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8811 | /* and that it is marked active as soon as the irq could fire. */ | |
8812 | smp_wmb(); | |
8813 | } | |
8814 | ||
8c9f3aaf JB |
8815 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8816 | struct drm_crtc *crtc, | |
8817 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8818 | struct drm_i915_gem_object *obj, |
8819 | uint32_t flags) | |
8c9f3aaf JB |
8820 | { |
8821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8823 | u32 flip_mask; |
6d90c952 | 8824 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8825 | int ret; |
8826 | ||
6d90c952 | 8827 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8828 | if (ret) |
83d4092b | 8829 | goto err; |
8c9f3aaf | 8830 | |
6d90c952 | 8831 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8832 | if (ret) |
83d4092b | 8833 | goto err_unpin; |
8c9f3aaf JB |
8834 | |
8835 | /* Can't queue multiple flips, so wait for the previous | |
8836 | * one to finish before executing the next. | |
8837 | */ | |
8838 | if (intel_crtc->plane) | |
8839 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8840 | else | |
8841 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8842 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8843 | intel_ring_emit(ring, MI_NOOP); | |
8844 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8845 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8846 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8847 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8848 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8849 | |
8850 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8851 | __intel_ring_advance(ring); |
83d4092b CW |
8852 | return 0; |
8853 | ||
8854 | err_unpin: | |
8855 | intel_unpin_fb_obj(obj); | |
8856 | err: | |
8c9f3aaf JB |
8857 | return ret; |
8858 | } | |
8859 | ||
8860 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8861 | struct drm_crtc *crtc, | |
8862 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8863 | struct drm_i915_gem_object *obj, |
8864 | uint32_t flags) | |
8c9f3aaf JB |
8865 | { |
8866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8867 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8868 | u32 flip_mask; |
6d90c952 | 8869 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8870 | int ret; |
8871 | ||
6d90c952 | 8872 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8873 | if (ret) |
83d4092b | 8874 | goto err; |
8c9f3aaf | 8875 | |
6d90c952 | 8876 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8877 | if (ret) |
83d4092b | 8878 | goto err_unpin; |
8c9f3aaf JB |
8879 | |
8880 | if (intel_crtc->plane) | |
8881 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8882 | else | |
8883 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8884 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8885 | intel_ring_emit(ring, MI_NOOP); | |
8886 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8887 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8888 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8889 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8890 | intel_ring_emit(ring, MI_NOOP); |
8891 | ||
e7d841ca | 8892 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8893 | __intel_ring_advance(ring); |
83d4092b CW |
8894 | return 0; |
8895 | ||
8896 | err_unpin: | |
8897 | intel_unpin_fb_obj(obj); | |
8898 | err: | |
8c9f3aaf JB |
8899 | return ret; |
8900 | } | |
8901 | ||
8902 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8903 | struct drm_crtc *crtc, | |
8904 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8905 | struct drm_i915_gem_object *obj, |
8906 | uint32_t flags) | |
8c9f3aaf JB |
8907 | { |
8908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8910 | uint32_t pf, pipesrc; | |
6d90c952 | 8911 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8912 | int ret; |
8913 | ||
6d90c952 | 8914 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8915 | if (ret) |
83d4092b | 8916 | goto err; |
8c9f3aaf | 8917 | |
6d90c952 | 8918 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8919 | if (ret) |
83d4092b | 8920 | goto err_unpin; |
8c9f3aaf JB |
8921 | |
8922 | /* i965+ uses the linear or tiled offsets from the | |
8923 | * Display Registers (which do not change across a page-flip) | |
8924 | * so we need only reprogram the base address. | |
8925 | */ | |
6d90c952 DV |
8926 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8927 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8928 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8929 | intel_ring_emit(ring, |
f343c5f6 | 8930 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8931 | obj->tiling_mode); |
8c9f3aaf JB |
8932 | |
8933 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8934 | * untested on non-native modes, so ignore it for now. | |
8935 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8936 | */ | |
8937 | pf = 0; | |
8938 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8939 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8940 | |
8941 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8942 | __intel_ring_advance(ring); |
83d4092b CW |
8943 | return 0; |
8944 | ||
8945 | err_unpin: | |
8946 | intel_unpin_fb_obj(obj); | |
8947 | err: | |
8c9f3aaf JB |
8948 | return ret; |
8949 | } | |
8950 | ||
8951 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8952 | struct drm_crtc *crtc, | |
8953 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8954 | struct drm_i915_gem_object *obj, |
8955 | uint32_t flags) | |
8c9f3aaf JB |
8956 | { |
8957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8959 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8960 | uint32_t pf, pipesrc; |
8961 | int ret; | |
8962 | ||
6d90c952 | 8963 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8964 | if (ret) |
83d4092b | 8965 | goto err; |
8c9f3aaf | 8966 | |
6d90c952 | 8967 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8968 | if (ret) |
83d4092b | 8969 | goto err_unpin; |
8c9f3aaf | 8970 | |
6d90c952 DV |
8971 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8972 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8973 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8974 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8975 | |
dc257cf1 DV |
8976 | /* Contrary to the suggestions in the documentation, |
8977 | * "Enable Panel Fitter" does not seem to be required when page | |
8978 | * flipping with a non-native mode, and worse causes a normal | |
8979 | * modeset to fail. | |
8980 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8981 | */ | |
8982 | pf = 0; | |
8c9f3aaf | 8983 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8984 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8985 | |
8986 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8987 | __intel_ring_advance(ring); |
83d4092b CW |
8988 | return 0; |
8989 | ||
8990 | err_unpin: | |
8991 | intel_unpin_fb_obj(obj); | |
8992 | err: | |
8c9f3aaf JB |
8993 | return ret; |
8994 | } | |
8995 | ||
7c9017e5 JB |
8996 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8997 | struct drm_crtc *crtc, | |
8998 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8999 | struct drm_i915_gem_object *obj, |
9000 | uint32_t flags) | |
7c9017e5 JB |
9001 | { |
9002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 9004 | struct intel_ring_buffer *ring; |
cb05d8de | 9005 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9006 | int len, ret; |
9007 | ||
9008 | ring = obj->ring; | |
1c5fd085 | 9009 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 9010 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
9011 | |
9012 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
9013 | if (ret) | |
83d4092b | 9014 | goto err; |
7c9017e5 | 9015 | |
cb05d8de DV |
9016 | switch(intel_crtc->plane) { |
9017 | case PLANE_A: | |
9018 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9019 | break; | |
9020 | case PLANE_B: | |
9021 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9022 | break; | |
9023 | case PLANE_C: | |
9024 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9025 | break; | |
9026 | default: | |
9027 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
9028 | ret = -ENODEV; | |
ab3951eb | 9029 | goto err_unpin; |
cb05d8de DV |
9030 | } |
9031 | ||
ffe74d75 | 9032 | len = 4; |
f476828a | 9033 | if (ring->id == RCS) { |
ffe74d75 | 9034 | len += 6; |
f476828a DL |
9035 | /* |
9036 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9037 | * 48bits addresses, and we need a NOOP for the batch size to | |
9038 | * stay even. | |
9039 | */ | |
9040 | if (IS_GEN8(dev)) | |
9041 | len += 2; | |
9042 | } | |
ffe74d75 | 9043 | |
f66fab8e VS |
9044 | /* |
9045 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9046 | * "The full packet must be contained within the same cache line." | |
9047 | * | |
9048 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9049 | * cacheline, if we ever start emitting more commands before | |
9050 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9051 | * then do the cacheline alignment, and finally emit the | |
9052 | * MI_DISPLAY_FLIP. | |
9053 | */ | |
9054 | ret = intel_ring_cacheline_align(ring); | |
9055 | if (ret) | |
9056 | goto err_unpin; | |
9057 | ||
ffe74d75 | 9058 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9059 | if (ret) |
83d4092b | 9060 | goto err_unpin; |
7c9017e5 | 9061 | |
ffe74d75 CW |
9062 | /* Unmask the flip-done completion message. Note that the bspec says that |
9063 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9064 | * more than one flip event at any time (or ensure that one flip message | |
9065 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9066 | * Experimentation says that BCS works despite DERRMR masking all | |
9067 | * flip-done completion events and that unmasking all planes at once | |
9068 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9069 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9070 | */ | |
9071 | if (ring->id == RCS) { | |
9072 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9073 | intel_ring_emit(ring, DERRMR); | |
9074 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9075 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9076 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9077 | if (IS_GEN8(dev)) |
9078 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9079 | MI_SRM_LRM_GLOBAL_GTT); | |
9080 | else | |
9081 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9082 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9083 | intel_ring_emit(ring, DERRMR); |
9084 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9085 | if (IS_GEN8(dev)) { |
9086 | intel_ring_emit(ring, 0); | |
9087 | intel_ring_emit(ring, MI_NOOP); | |
9088 | } | |
ffe74d75 CW |
9089 | } |
9090 | ||
cb05d8de | 9091 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9092 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 9093 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 9094 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9095 | |
9096 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9097 | __intel_ring_advance(ring); |
83d4092b CW |
9098 | return 0; |
9099 | ||
9100 | err_unpin: | |
9101 | intel_unpin_fb_obj(obj); | |
9102 | err: | |
7c9017e5 JB |
9103 | return ret; |
9104 | } | |
9105 | ||
8c9f3aaf JB |
9106 | static int intel_default_queue_flip(struct drm_device *dev, |
9107 | struct drm_crtc *crtc, | |
9108 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9109 | struct drm_i915_gem_object *obj, |
9110 | uint32_t flags) | |
8c9f3aaf JB |
9111 | { |
9112 | return -ENODEV; | |
9113 | } | |
9114 | ||
6b95a207 KH |
9115 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9116 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9117 | struct drm_pending_vblank_event *event, |
9118 | uint32_t page_flip_flags) | |
6b95a207 KH |
9119 | { |
9120 | struct drm_device *dev = crtc->dev; | |
9121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9122 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
4a35f83b | 9123 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
6b95a207 KH |
9124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9125 | struct intel_unpin_work *work; | |
8c9f3aaf | 9126 | unsigned long flags; |
52e68630 | 9127 | int ret; |
6b95a207 | 9128 | |
e6a595d2 | 9129 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9130 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9131 | return -EINVAL; |
9132 | ||
9133 | /* | |
9134 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9135 | * Note that pitch changes could also affect these register. | |
9136 | */ | |
9137 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9138 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9139 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9140 | return -EINVAL; |
9141 | ||
f900db47 CW |
9142 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9143 | goto out_hang; | |
9144 | ||
b14c5679 | 9145 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9146 | if (work == NULL) |
9147 | return -ENOMEM; | |
9148 | ||
6b95a207 | 9149 | work->event = event; |
b4a98e57 | 9150 | work->crtc = crtc; |
4a35f83b | 9151 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
9152 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9153 | ||
7317c75e JB |
9154 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
9155 | if (ret) | |
9156 | goto free_work; | |
9157 | ||
6b95a207 KH |
9158 | /* We borrow the event spin lock for protecting unpin_work */ |
9159 | spin_lock_irqsave(&dev->event_lock, flags); | |
9160 | if (intel_crtc->unpin_work) { | |
9161 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9162 | kfree(work); | |
7317c75e | 9163 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
9164 | |
9165 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9166 | return -EBUSY; |
9167 | } | |
9168 | intel_crtc->unpin_work = work; | |
9169 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9170 | ||
b4a98e57 CW |
9171 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9172 | flush_workqueue(dev_priv->wq); | |
9173 | ||
79158103 CW |
9174 | ret = i915_mutex_lock_interruptible(dev); |
9175 | if (ret) | |
9176 | goto cleanup; | |
6b95a207 | 9177 | |
75dfca80 | 9178 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9179 | drm_gem_object_reference(&work->old_fb_obj->base); |
9180 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9181 | |
f4510a27 | 9182 | crtc->primary->fb = fb; |
96b099fd | 9183 | |
e1f99ce6 | 9184 | work->pending_flip_obj = obj; |
e1f99ce6 | 9185 | |
4e5359cd SF |
9186 | work->enable_stall_check = true; |
9187 | ||
b4a98e57 | 9188 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9189 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9190 | |
ed8d1975 | 9191 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
9192 | if (ret) |
9193 | goto cleanup_pending; | |
6b95a207 | 9194 | |
7782de3b | 9195 | intel_disable_fbc(dev); |
c65355bb | 9196 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
9197 | mutex_unlock(&dev->struct_mutex); |
9198 | ||
e5510fac JB |
9199 | trace_i915_flip_request(intel_crtc->plane, obj); |
9200 | ||
6b95a207 | 9201 | return 0; |
96b099fd | 9202 | |
8c9f3aaf | 9203 | cleanup_pending: |
b4a98e57 | 9204 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9205 | crtc->primary->fb = old_fb; |
05394f39 CW |
9206 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9207 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9208 | mutex_unlock(&dev->struct_mutex); |
9209 | ||
79158103 | 9210 | cleanup: |
96b099fd CW |
9211 | spin_lock_irqsave(&dev->event_lock, flags); |
9212 | intel_crtc->unpin_work = NULL; | |
9213 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9214 | ||
7317c75e JB |
9215 | drm_vblank_put(dev, intel_crtc->pipe); |
9216 | free_work: | |
96b099fd CW |
9217 | kfree(work); |
9218 | ||
f900db47 CW |
9219 | if (ret == -EIO) { |
9220 | out_hang: | |
9221 | intel_crtc_wait_for_pending_flips(crtc); | |
9222 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9223 | if (ret == 0 && event) | |
9224 | drm_send_vblank_event(dev, intel_crtc->pipe, event); | |
9225 | } | |
96b099fd | 9226 | return ret; |
6b95a207 KH |
9227 | } |
9228 | ||
f6e5b160 | 9229 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9230 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9231 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9232 | }; |
9233 | ||
9a935856 DV |
9234 | /** |
9235 | * intel_modeset_update_staged_output_state | |
9236 | * | |
9237 | * Updates the staged output configuration state, e.g. after we've read out the | |
9238 | * current hw state. | |
9239 | */ | |
9240 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9241 | { |
7668851f | 9242 | struct intel_crtc *crtc; |
9a935856 DV |
9243 | struct intel_encoder *encoder; |
9244 | struct intel_connector *connector; | |
f6e5b160 | 9245 | |
9a935856 DV |
9246 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9247 | base.head) { | |
9248 | connector->new_encoder = | |
9249 | to_intel_encoder(connector->base.encoder); | |
9250 | } | |
f6e5b160 | 9251 | |
9a935856 DV |
9252 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9253 | base.head) { | |
9254 | encoder->new_crtc = | |
9255 | to_intel_crtc(encoder->base.crtc); | |
9256 | } | |
7668851f | 9257 | |
d3fcc808 | 9258 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9259 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9260 | |
9261 | if (crtc->new_enabled) | |
9262 | crtc->new_config = &crtc->config; | |
9263 | else | |
9264 | crtc->new_config = NULL; | |
7668851f | 9265 | } |
f6e5b160 CW |
9266 | } |
9267 | ||
9a935856 DV |
9268 | /** |
9269 | * intel_modeset_commit_output_state | |
9270 | * | |
9271 | * This function copies the stage display pipe configuration to the real one. | |
9272 | */ | |
9273 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9274 | { | |
7668851f | 9275 | struct intel_crtc *crtc; |
9a935856 DV |
9276 | struct intel_encoder *encoder; |
9277 | struct intel_connector *connector; | |
f6e5b160 | 9278 | |
9a935856 DV |
9279 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9280 | base.head) { | |
9281 | connector->base.encoder = &connector->new_encoder->base; | |
9282 | } | |
f6e5b160 | 9283 | |
9a935856 DV |
9284 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9285 | base.head) { | |
9286 | encoder->base.crtc = &encoder->new_crtc->base; | |
9287 | } | |
7668851f | 9288 | |
d3fcc808 | 9289 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9290 | crtc->base.enabled = crtc->new_enabled; |
9291 | } | |
9a935856 DV |
9292 | } |
9293 | ||
050f7aeb DV |
9294 | static void |
9295 | connected_sink_compute_bpp(struct intel_connector * connector, | |
9296 | struct intel_crtc_config *pipe_config) | |
9297 | { | |
9298 | int bpp = pipe_config->pipe_bpp; | |
9299 | ||
9300 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9301 | connector->base.base.id, | |
9302 | drm_get_connector_name(&connector->base)); | |
9303 | ||
9304 | /* Don't use an invalid EDID bpc value */ | |
9305 | if (connector->base.display_info.bpc && | |
9306 | connector->base.display_info.bpc * 3 < bpp) { | |
9307 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9308 | bpp, connector->base.display_info.bpc*3); | |
9309 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9310 | } | |
9311 | ||
9312 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9313 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9314 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9315 | bpp); | |
9316 | pipe_config->pipe_bpp = 24; | |
9317 | } | |
9318 | } | |
9319 | ||
4e53c2e0 | 9320 | static int |
050f7aeb DV |
9321 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9322 | struct drm_framebuffer *fb, | |
9323 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9324 | { |
050f7aeb DV |
9325 | struct drm_device *dev = crtc->base.dev; |
9326 | struct intel_connector *connector; | |
4e53c2e0 DV |
9327 | int bpp; |
9328 | ||
d42264b1 DV |
9329 | switch (fb->pixel_format) { |
9330 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9331 | bpp = 8*3; /* since we go through a colormap */ |
9332 | break; | |
d42264b1 DV |
9333 | case DRM_FORMAT_XRGB1555: |
9334 | case DRM_FORMAT_ARGB1555: | |
9335 | /* checked in intel_framebuffer_init already */ | |
9336 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9337 | return -EINVAL; | |
9338 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9339 | bpp = 6*3; /* min is 18bpp */ |
9340 | break; | |
d42264b1 DV |
9341 | case DRM_FORMAT_XBGR8888: |
9342 | case DRM_FORMAT_ABGR8888: | |
9343 | /* checked in intel_framebuffer_init already */ | |
9344 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9345 | return -EINVAL; | |
9346 | case DRM_FORMAT_XRGB8888: | |
9347 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9348 | bpp = 8*3; |
9349 | break; | |
d42264b1 DV |
9350 | case DRM_FORMAT_XRGB2101010: |
9351 | case DRM_FORMAT_ARGB2101010: | |
9352 | case DRM_FORMAT_XBGR2101010: | |
9353 | case DRM_FORMAT_ABGR2101010: | |
9354 | /* checked in intel_framebuffer_init already */ | |
9355 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9356 | return -EINVAL; |
4e53c2e0 DV |
9357 | bpp = 10*3; |
9358 | break; | |
baba133a | 9359 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9360 | default: |
9361 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9362 | return -EINVAL; | |
9363 | } | |
9364 | ||
4e53c2e0 DV |
9365 | pipe_config->pipe_bpp = bpp; |
9366 | ||
9367 | /* Clamp display bpp to EDID value */ | |
9368 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9369 | base.head) { |
1b829e05 DV |
9370 | if (!connector->new_encoder || |
9371 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9372 | continue; |
9373 | ||
050f7aeb | 9374 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9375 | } |
9376 | ||
9377 | return bpp; | |
9378 | } | |
9379 | ||
644db711 DV |
9380 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9381 | { | |
9382 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9383 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9384 | mode->crtc_clock, |
644db711 DV |
9385 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9386 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9387 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9388 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9389 | } | |
9390 | ||
c0b03411 DV |
9391 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9392 | struct intel_crtc_config *pipe_config, | |
9393 | const char *context) | |
9394 | { | |
9395 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9396 | context, pipe_name(crtc->pipe)); | |
9397 | ||
9398 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9399 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9400 | pipe_config->pipe_bpp, pipe_config->dither); | |
9401 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9402 | pipe_config->has_pch_encoder, | |
9403 | pipe_config->fdi_lanes, | |
9404 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9405 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9406 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9407 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9408 | pipe_config->has_dp_encoder, | |
9409 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9410 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9411 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9412 | DRM_DEBUG_KMS("requested mode:\n"); |
9413 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9414 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9415 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9416 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9417 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9418 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9419 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9420 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9421 | pipe_config->gmch_pfit.control, | |
9422 | pipe_config->gmch_pfit.pgm_ratios, | |
9423 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9424 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9425 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9426 | pipe_config->pch_pfit.size, |
9427 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9428 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9429 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9430 | } |
9431 | ||
bc079e8b VS |
9432 | static bool encoders_cloneable(const struct intel_encoder *a, |
9433 | const struct intel_encoder *b) | |
accfc0c5 | 9434 | { |
bc079e8b VS |
9435 | /* masks could be asymmetric, so check both ways */ |
9436 | return a == b || (a->cloneable & (1 << b->type) && | |
9437 | b->cloneable & (1 << a->type)); | |
9438 | } | |
9439 | ||
9440 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
9441 | struct intel_encoder *encoder) | |
9442 | { | |
9443 | struct drm_device *dev = crtc->base.dev; | |
9444 | struct intel_encoder *source_encoder; | |
9445 | ||
9446 | list_for_each_entry(source_encoder, | |
9447 | &dev->mode_config.encoder_list, base.head) { | |
9448 | if (source_encoder->new_crtc != crtc) | |
9449 | continue; | |
9450 | ||
9451 | if (!encoders_cloneable(encoder, source_encoder)) | |
9452 | return false; | |
9453 | } | |
9454 | ||
9455 | return true; | |
9456 | } | |
9457 | ||
9458 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
9459 | { | |
9460 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
9461 | struct intel_encoder *encoder; |
9462 | ||
bc079e8b VS |
9463 | list_for_each_entry(encoder, |
9464 | &dev->mode_config.encoder_list, base.head) { | |
9465 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
9466 | continue; |
9467 | ||
bc079e8b VS |
9468 | if (!check_single_encoder_cloning(crtc, encoder)) |
9469 | return false; | |
accfc0c5 DV |
9470 | } |
9471 | ||
bc079e8b | 9472 | return true; |
accfc0c5 DV |
9473 | } |
9474 | ||
b8cecdf5 DV |
9475 | static struct intel_crtc_config * |
9476 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9477 | struct drm_framebuffer *fb, |
b8cecdf5 | 9478 | struct drm_display_mode *mode) |
ee7b9f93 | 9479 | { |
7758a113 | 9480 | struct drm_device *dev = crtc->dev; |
7758a113 | 9481 | struct intel_encoder *encoder; |
b8cecdf5 | 9482 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9483 | int plane_bpp, ret = -EINVAL; |
9484 | bool retry = true; | |
ee7b9f93 | 9485 | |
bc079e8b | 9486 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
9487 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9488 | return ERR_PTR(-EINVAL); | |
9489 | } | |
9490 | ||
b8cecdf5 DV |
9491 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9492 | if (!pipe_config) | |
7758a113 DV |
9493 | return ERR_PTR(-ENOMEM); |
9494 | ||
b8cecdf5 DV |
9495 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9496 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9497 | |
e143a21c DV |
9498 | pipe_config->cpu_transcoder = |
9499 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9500 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9501 | |
2960bc9c ID |
9502 | /* |
9503 | * Sanitize sync polarity flags based on requested ones. If neither | |
9504 | * positive or negative polarity is requested, treat this as meaning | |
9505 | * negative polarity. | |
9506 | */ | |
9507 | if (!(pipe_config->adjusted_mode.flags & | |
9508 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9509 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9510 | ||
9511 | if (!(pipe_config->adjusted_mode.flags & | |
9512 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9513 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9514 | ||
050f7aeb DV |
9515 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9516 | * plane pixel format and any sink constraints into account. Returns the | |
9517 | * source plane bpp so that dithering can be selected on mismatches | |
9518 | * after encoders and crtc also have had their say. */ | |
9519 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9520 | fb, pipe_config); | |
4e53c2e0 DV |
9521 | if (plane_bpp < 0) |
9522 | goto fail; | |
9523 | ||
e41a56be VS |
9524 | /* |
9525 | * Determine the real pipe dimensions. Note that stereo modes can | |
9526 | * increase the actual pipe size due to the frame doubling and | |
9527 | * insertion of additional space for blanks between the frame. This | |
9528 | * is stored in the crtc timings. We use the requested mode to do this | |
9529 | * computation to clearly distinguish it from the adjusted mode, which | |
9530 | * can be changed by the connectors in the below retry loop. | |
9531 | */ | |
9532 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9533 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9534 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9535 | ||
e29c22c0 | 9536 | encoder_retry: |
ef1b460d | 9537 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9538 | pipe_config->port_clock = 0; |
ef1b460d | 9539 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9540 | |
135c81b8 | 9541 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9542 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9543 | |
7758a113 DV |
9544 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9545 | * adjust it according to limitations or connector properties, and also | |
9546 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9547 | */ |
7758a113 DV |
9548 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9549 | base.head) { | |
47f1c6c9 | 9550 | |
7758a113 DV |
9551 | if (&encoder->new_crtc->base != crtc) |
9552 | continue; | |
7ae89233 | 9553 | |
efea6e8e DV |
9554 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9555 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9556 | goto fail; |
9557 | } | |
ee7b9f93 | 9558 | } |
47f1c6c9 | 9559 | |
ff9a6750 DV |
9560 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9561 | * done afterwards in case the encoder adjusts the mode. */ | |
9562 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9563 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9564 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9565 | |
a43f6e0f | 9566 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9567 | if (ret < 0) { |
7758a113 DV |
9568 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9569 | goto fail; | |
ee7b9f93 | 9570 | } |
e29c22c0 DV |
9571 | |
9572 | if (ret == RETRY) { | |
9573 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9574 | ret = -EINVAL; | |
9575 | goto fail; | |
9576 | } | |
9577 | ||
9578 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9579 | retry = false; | |
9580 | goto encoder_retry; | |
9581 | } | |
9582 | ||
4e53c2e0 DV |
9583 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9584 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9585 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9586 | ||
b8cecdf5 | 9587 | return pipe_config; |
7758a113 | 9588 | fail: |
b8cecdf5 | 9589 | kfree(pipe_config); |
e29c22c0 | 9590 | return ERR_PTR(ret); |
ee7b9f93 | 9591 | } |
47f1c6c9 | 9592 | |
e2e1ed41 DV |
9593 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9594 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9595 | static void | |
9596 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9597 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9598 | { |
9599 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9600 | struct drm_device *dev = crtc->dev; |
9601 | struct intel_encoder *encoder; | |
9602 | struct intel_connector *connector; | |
9603 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9604 | |
e2e1ed41 | 9605 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9606 | |
e2e1ed41 DV |
9607 | /* Check which crtcs have changed outputs connected to them, these need |
9608 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9609 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9610 | * bit set at most. */ | |
9611 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9612 | base.head) { | |
9613 | if (connector->base.encoder == &connector->new_encoder->base) | |
9614 | continue; | |
79e53945 | 9615 | |
e2e1ed41 DV |
9616 | if (connector->base.encoder) { |
9617 | tmp_crtc = connector->base.encoder->crtc; | |
9618 | ||
9619 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9620 | } | |
9621 | ||
9622 | if (connector->new_encoder) | |
9623 | *prepare_pipes |= | |
9624 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9625 | } |
9626 | ||
e2e1ed41 DV |
9627 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9628 | base.head) { | |
9629 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9630 | continue; | |
9631 | ||
9632 | if (encoder->base.crtc) { | |
9633 | tmp_crtc = encoder->base.crtc; | |
9634 | ||
9635 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9636 | } | |
9637 | ||
9638 | if (encoder->new_crtc) | |
9639 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9640 | } |
9641 | ||
7668851f | 9642 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 9643 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9644 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9645 | continue; |
7e7d76c3 | 9646 | |
7668851f | 9647 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9648 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9649 | else |
9650 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9651 | } |
9652 | ||
e2e1ed41 DV |
9653 | |
9654 | /* set_mode is also used to update properties on life display pipes. */ | |
9655 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9656 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9657 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9658 | ||
b6c5164d DV |
9659 | /* |
9660 | * For simplicity do a full modeset on any pipe where the output routing | |
9661 | * changed. We could be more clever, but that would require us to be | |
9662 | * more careful with calling the relevant encoder->mode_set functions. | |
9663 | */ | |
e2e1ed41 DV |
9664 | if (*prepare_pipes) |
9665 | *modeset_pipes = *prepare_pipes; | |
9666 | ||
9667 | /* ... and mask these out. */ | |
9668 | *modeset_pipes &= ~(*disable_pipes); | |
9669 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9670 | |
9671 | /* | |
9672 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9673 | * obies this rule, but the modeset restore mode of | |
9674 | * intel_modeset_setup_hw_state does not. | |
9675 | */ | |
9676 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9677 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9678 | |
9679 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9680 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9681 | } |
79e53945 | 9682 | |
ea9d758d | 9683 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9684 | { |
ea9d758d | 9685 | struct drm_encoder *encoder; |
f6e5b160 | 9686 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9687 | |
ea9d758d DV |
9688 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9689 | if (encoder->crtc == crtc) | |
9690 | return true; | |
9691 | ||
9692 | return false; | |
9693 | } | |
9694 | ||
9695 | static void | |
9696 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9697 | { | |
9698 | struct intel_encoder *intel_encoder; | |
9699 | struct intel_crtc *intel_crtc; | |
9700 | struct drm_connector *connector; | |
9701 | ||
9702 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9703 | base.head) { | |
9704 | if (!intel_encoder->base.crtc) | |
9705 | continue; | |
9706 | ||
9707 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9708 | ||
9709 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9710 | intel_encoder->connectors_active = false; | |
9711 | } | |
9712 | ||
9713 | intel_modeset_commit_output_state(dev); | |
9714 | ||
7668851f | 9715 | /* Double check state. */ |
d3fcc808 | 9716 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9717 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9718 | WARN_ON(intel_crtc->new_config && |
9719 | intel_crtc->new_config != &intel_crtc->config); | |
9720 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9721 | } |
9722 | ||
9723 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9724 | if (!connector->encoder || !connector->encoder->crtc) | |
9725 | continue; | |
9726 | ||
9727 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9728 | ||
9729 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9730 | struct drm_property *dpms_property = |
9731 | dev->mode_config.dpms_property; | |
9732 | ||
ea9d758d | 9733 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9734 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9735 | dpms_property, |
9736 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9737 | |
9738 | intel_encoder = to_intel_encoder(connector->encoder); | |
9739 | intel_encoder->connectors_active = true; | |
9740 | } | |
9741 | } | |
9742 | ||
9743 | } | |
9744 | ||
3bd26263 | 9745 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9746 | { |
3bd26263 | 9747 | int diff; |
f1f644dc JB |
9748 | |
9749 | if (clock1 == clock2) | |
9750 | return true; | |
9751 | ||
9752 | if (!clock1 || !clock2) | |
9753 | return false; | |
9754 | ||
9755 | diff = abs(clock1 - clock2); | |
9756 | ||
9757 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9758 | return true; | |
9759 | ||
9760 | return false; | |
9761 | } | |
9762 | ||
25c5b266 DV |
9763 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9764 | list_for_each_entry((intel_crtc), \ | |
9765 | &(dev)->mode_config.crtc_list, \ | |
9766 | base.head) \ | |
0973f18f | 9767 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9768 | |
0e8ffe1b | 9769 | static bool |
2fa2fe9a DV |
9770 | intel_pipe_config_compare(struct drm_device *dev, |
9771 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9772 | struct intel_crtc_config *pipe_config) |
9773 | { | |
66e985c0 DV |
9774 | #define PIPE_CONF_CHECK_X(name) \ |
9775 | if (current_config->name != pipe_config->name) { \ | |
9776 | DRM_ERROR("mismatch in " #name " " \ | |
9777 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9778 | current_config->name, \ | |
9779 | pipe_config->name); \ | |
9780 | return false; \ | |
9781 | } | |
9782 | ||
08a24034 DV |
9783 | #define PIPE_CONF_CHECK_I(name) \ |
9784 | if (current_config->name != pipe_config->name) { \ | |
9785 | DRM_ERROR("mismatch in " #name " " \ | |
9786 | "(expected %i, found %i)\n", \ | |
9787 | current_config->name, \ | |
9788 | pipe_config->name); \ | |
9789 | return false; \ | |
88adfff1 DV |
9790 | } |
9791 | ||
1bd1bd80 DV |
9792 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9793 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9794 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9795 | "(expected %i, found %i)\n", \ |
9796 | current_config->name & (mask), \ | |
9797 | pipe_config->name & (mask)); \ | |
9798 | return false; \ | |
9799 | } | |
9800 | ||
5e550656 VS |
9801 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9802 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9803 | DRM_ERROR("mismatch in " #name " " \ | |
9804 | "(expected %i, found %i)\n", \ | |
9805 | current_config->name, \ | |
9806 | pipe_config->name); \ | |
9807 | return false; \ | |
9808 | } | |
9809 | ||
bb760063 DV |
9810 | #define PIPE_CONF_QUIRK(quirk) \ |
9811 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9812 | ||
eccb140b DV |
9813 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9814 | ||
08a24034 DV |
9815 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9816 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9817 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9818 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9819 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9820 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9821 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9822 | |
eb14cb74 VS |
9823 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9824 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9825 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9826 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9827 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9828 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9829 | ||
1bd1bd80 DV |
9830 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9831 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9832 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9833 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9834 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9835 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9836 | ||
9837 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9838 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9839 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9840 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9841 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9842 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9843 | ||
c93f54cf | 9844 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 9845 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
9846 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
9847 | IS_VALLEYVIEW(dev)) | |
9848 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 9849 | |
9ed109a7 DV |
9850 | PIPE_CONF_CHECK_I(has_audio); |
9851 | ||
1bd1bd80 DV |
9852 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9853 | DRM_MODE_FLAG_INTERLACE); | |
9854 | ||
bb760063 DV |
9855 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9856 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9857 | DRM_MODE_FLAG_PHSYNC); | |
9858 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9859 | DRM_MODE_FLAG_NHSYNC); | |
9860 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9861 | DRM_MODE_FLAG_PVSYNC); | |
9862 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9863 | DRM_MODE_FLAG_NVSYNC); | |
9864 | } | |
045ac3b5 | 9865 | |
37327abd VS |
9866 | PIPE_CONF_CHECK_I(pipe_src_w); |
9867 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9868 | |
9953599b DV |
9869 | /* |
9870 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
9871 | * screen. Since we don't yet re-compute the pipe config when moving | |
9872 | * just the lvds port away to another pipe the sw tracking won't match. | |
9873 | * | |
9874 | * Proper atomic modesets with recomputed global state will fix this. | |
9875 | * Until then just don't check gmch state for inherited modes. | |
9876 | */ | |
9877 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
9878 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
9879 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9880 | if (INTEL_INFO(dev)->gen < 4) | |
9881 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9882 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
9883 | } | |
9884 | ||
fd4daa9c CW |
9885 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9886 | if (current_config->pch_pfit.enabled) { | |
9887 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9888 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9889 | } | |
2fa2fe9a | 9890 | |
e59150dc JB |
9891 | /* BDW+ don't expose a synchronous way to read the state */ |
9892 | if (IS_HASWELL(dev)) | |
9893 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9894 | |
282740f7 VS |
9895 | PIPE_CONF_CHECK_I(double_wide); |
9896 | ||
c0d43d62 | 9897 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9898 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9899 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9900 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9901 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9902 | |
42571aef VS |
9903 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9904 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9905 | ||
a9a7e98a JB |
9906 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9907 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 9908 | |
66e985c0 | 9909 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9910 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9911 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9912 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9913 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9914 | |
0e8ffe1b DV |
9915 | return true; |
9916 | } | |
9917 | ||
91d1b4bd DV |
9918 | static void |
9919 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9920 | { |
8af6cf88 DV |
9921 | struct intel_connector *connector; |
9922 | ||
9923 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9924 | base.head) { | |
9925 | /* This also checks the encoder/connector hw state with the | |
9926 | * ->get_hw_state callbacks. */ | |
9927 | intel_connector_check_state(connector); | |
9928 | ||
9929 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9930 | "connector's staged encoder doesn't match current encoder\n"); | |
9931 | } | |
91d1b4bd DV |
9932 | } |
9933 | ||
9934 | static void | |
9935 | check_encoder_state(struct drm_device *dev) | |
9936 | { | |
9937 | struct intel_encoder *encoder; | |
9938 | struct intel_connector *connector; | |
8af6cf88 DV |
9939 | |
9940 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9941 | base.head) { | |
9942 | bool enabled = false; | |
9943 | bool active = false; | |
9944 | enum pipe pipe, tracked_pipe; | |
9945 | ||
9946 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9947 | encoder->base.base.id, | |
9948 | drm_get_encoder_name(&encoder->base)); | |
9949 | ||
9950 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9951 | "encoder's stage crtc doesn't match current crtc\n"); | |
9952 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9953 | "encoder's active_connectors set, but no crtc\n"); | |
9954 | ||
9955 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9956 | base.head) { | |
9957 | if (connector->base.encoder != &encoder->base) | |
9958 | continue; | |
9959 | enabled = true; | |
9960 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9961 | active = true; | |
9962 | } | |
9963 | WARN(!!encoder->base.crtc != enabled, | |
9964 | "encoder's enabled state mismatch " | |
9965 | "(expected %i, found %i)\n", | |
9966 | !!encoder->base.crtc, enabled); | |
9967 | WARN(active && !encoder->base.crtc, | |
9968 | "active encoder with no crtc\n"); | |
9969 | ||
9970 | WARN(encoder->connectors_active != active, | |
9971 | "encoder's computed active state doesn't match tracked active state " | |
9972 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9973 | ||
9974 | active = encoder->get_hw_state(encoder, &pipe); | |
9975 | WARN(active != encoder->connectors_active, | |
9976 | "encoder's hw state doesn't match sw tracking " | |
9977 | "(expected %i, found %i)\n", | |
9978 | encoder->connectors_active, active); | |
9979 | ||
9980 | if (!encoder->base.crtc) | |
9981 | continue; | |
9982 | ||
9983 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9984 | WARN(active && pipe != tracked_pipe, | |
9985 | "active encoder's pipe doesn't match" | |
9986 | "(expected %i, found %i)\n", | |
9987 | tracked_pipe, pipe); | |
9988 | ||
9989 | } | |
91d1b4bd DV |
9990 | } |
9991 | ||
9992 | static void | |
9993 | check_crtc_state(struct drm_device *dev) | |
9994 | { | |
fbee40df | 9995 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
9996 | struct intel_crtc *crtc; |
9997 | struct intel_encoder *encoder; | |
9998 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 9999 | |
d3fcc808 | 10000 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10001 | bool enabled = false; |
10002 | bool active = false; | |
10003 | ||
045ac3b5 JB |
10004 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10005 | ||
8af6cf88 DV |
10006 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10007 | crtc->base.base.id); | |
10008 | ||
10009 | WARN(crtc->active && !crtc->base.enabled, | |
10010 | "active crtc, but not enabled in sw tracking\n"); | |
10011 | ||
10012 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10013 | base.head) { | |
10014 | if (encoder->base.crtc != &crtc->base) | |
10015 | continue; | |
10016 | enabled = true; | |
10017 | if (encoder->connectors_active) | |
10018 | active = true; | |
10019 | } | |
6c49f241 | 10020 | |
8af6cf88 DV |
10021 | WARN(active != crtc->active, |
10022 | "crtc's computed active state doesn't match tracked active state " | |
10023 | "(expected %i, found %i)\n", active, crtc->active); | |
10024 | WARN(enabled != crtc->base.enabled, | |
10025 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10026 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10027 | ||
0e8ffe1b DV |
10028 | active = dev_priv->display.get_pipe_config(crtc, |
10029 | &pipe_config); | |
d62cf62a DV |
10030 | |
10031 | /* hw state is inconsistent with the pipe A quirk */ | |
10032 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10033 | active = crtc->active; | |
10034 | ||
6c49f241 DV |
10035 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10036 | base.head) { | |
3eaba51c | 10037 | enum pipe pipe; |
6c49f241 DV |
10038 | if (encoder->base.crtc != &crtc->base) |
10039 | continue; | |
1d37b689 | 10040 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10041 | encoder->get_config(encoder, &pipe_config); |
10042 | } | |
10043 | ||
0e8ffe1b DV |
10044 | WARN(crtc->active != active, |
10045 | "crtc active state doesn't match with hw state " | |
10046 | "(expected %i, found %i)\n", crtc->active, active); | |
10047 | ||
c0b03411 DV |
10048 | if (active && |
10049 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10050 | WARN(1, "pipe state doesn't match!\n"); | |
10051 | intel_dump_pipe_config(crtc, &pipe_config, | |
10052 | "[hw state]"); | |
10053 | intel_dump_pipe_config(crtc, &crtc->config, | |
10054 | "[sw state]"); | |
10055 | } | |
8af6cf88 DV |
10056 | } |
10057 | } | |
10058 | ||
91d1b4bd DV |
10059 | static void |
10060 | check_shared_dpll_state(struct drm_device *dev) | |
10061 | { | |
fbee40df | 10062 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10063 | struct intel_crtc *crtc; |
10064 | struct intel_dpll_hw_state dpll_hw_state; | |
10065 | int i; | |
5358901f DV |
10066 | |
10067 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10068 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10069 | int enabled_crtcs = 0, active_crtcs = 0; | |
10070 | bool active; | |
10071 | ||
10072 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10073 | ||
10074 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10075 | ||
10076 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10077 | ||
10078 | WARN(pll->active > pll->refcount, | |
10079 | "more active pll users than references: %i vs %i\n", | |
10080 | pll->active, pll->refcount); | |
10081 | WARN(pll->active && !pll->on, | |
10082 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10083 | WARN(pll->on && !pll->active, |
10084 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10085 | WARN(pll->on != active, |
10086 | "pll on state mismatch (expected %i, found %i)\n", | |
10087 | pll->on, active); | |
10088 | ||
d3fcc808 | 10089 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10090 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10091 | enabled_crtcs++; | |
10092 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10093 | active_crtcs++; | |
10094 | } | |
10095 | WARN(pll->active != active_crtcs, | |
10096 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10097 | pll->active, active_crtcs); | |
10098 | WARN(pll->refcount != enabled_crtcs, | |
10099 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10100 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10101 | |
10102 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10103 | sizeof(dpll_hw_state)), | |
10104 | "pll hw state mismatch\n"); | |
5358901f | 10105 | } |
8af6cf88 DV |
10106 | } |
10107 | ||
91d1b4bd DV |
10108 | void |
10109 | intel_modeset_check_state(struct drm_device *dev) | |
10110 | { | |
10111 | check_connector_state(dev); | |
10112 | check_encoder_state(dev); | |
10113 | check_crtc_state(dev); | |
10114 | check_shared_dpll_state(dev); | |
10115 | } | |
10116 | ||
18442d08 VS |
10117 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10118 | int dotclock) | |
10119 | { | |
10120 | /* | |
10121 | * FDI already provided one idea for the dotclock. | |
10122 | * Yell if the encoder disagrees. | |
10123 | */ | |
241bfc38 | 10124 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10125 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10126 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10127 | } |
10128 | ||
f30da187 DV |
10129 | static int __intel_set_mode(struct drm_crtc *crtc, |
10130 | struct drm_display_mode *mode, | |
10131 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10132 | { |
10133 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10134 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10135 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10136 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10137 | struct intel_crtc *intel_crtc; |
10138 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10139 | int ret = 0; |
a6778b3c | 10140 | |
4b4b9238 | 10141 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10142 | if (!saved_mode) |
10143 | return -ENOMEM; | |
a6778b3c | 10144 | |
e2e1ed41 | 10145 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10146 | &prepare_pipes, &disable_pipes); |
10147 | ||
3ac18232 | 10148 | *saved_mode = crtc->mode; |
a6778b3c | 10149 | |
25c5b266 DV |
10150 | /* Hack: Because we don't (yet) support global modeset on multiple |
10151 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10152 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10153 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10154 | * changing their mode at the same time. */ | |
25c5b266 | 10155 | if (modeset_pipes) { |
4e53c2e0 | 10156 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10157 | if (IS_ERR(pipe_config)) { |
10158 | ret = PTR_ERR(pipe_config); | |
10159 | pipe_config = NULL; | |
10160 | ||
3ac18232 | 10161 | goto out; |
25c5b266 | 10162 | } |
c0b03411 DV |
10163 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10164 | "[modeset]"); | |
50741abc | 10165 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10166 | } |
a6778b3c | 10167 | |
30a970c6 JB |
10168 | /* |
10169 | * See if the config requires any additional preparation, e.g. | |
10170 | * to adjust global state with pipes off. We need to do this | |
10171 | * here so we can get the modeset_pipe updated config for the new | |
10172 | * mode set on this crtc. For other crtcs we need to use the | |
10173 | * adjusted_mode bits in the crtc directly. | |
10174 | */ | |
c164f833 | 10175 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10176 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10177 | |
c164f833 VS |
10178 | /* may have added more to prepare_pipes than we should */ |
10179 | prepare_pipes &= ~disable_pipes; | |
10180 | } | |
10181 | ||
460da916 DV |
10182 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10183 | intel_crtc_disable(&intel_crtc->base); | |
10184 | ||
ea9d758d DV |
10185 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10186 | if (intel_crtc->base.enabled) | |
10187 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10188 | } | |
a6778b3c | 10189 | |
6c4c86f5 DV |
10190 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10191 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10192 | */ |
b8cecdf5 | 10193 | if (modeset_pipes) { |
25c5b266 | 10194 | crtc->mode = *mode; |
b8cecdf5 DV |
10195 | /* mode_set/enable/disable functions rely on a correct pipe |
10196 | * config. */ | |
10197 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10198 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10199 | |
10200 | /* | |
10201 | * Calculate and store various constants which | |
10202 | * are later needed by vblank and swap-completion | |
10203 | * timestamping. They are derived from true hwmode. | |
10204 | */ | |
10205 | drm_calc_timestamping_constants(crtc, | |
10206 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10207 | } |
7758a113 | 10208 | |
ea9d758d DV |
10209 | /* Only after disabling all output pipelines that will be changed can we |
10210 | * update the the output configuration. */ | |
10211 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10212 | |
47fab737 DV |
10213 | if (dev_priv->display.modeset_global_resources) |
10214 | dev_priv->display.modeset_global_resources(dev); | |
10215 | ||
a6778b3c DV |
10216 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10217 | * on the DPLL. | |
f6e5b160 | 10218 | */ |
25c5b266 | 10219 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
4271b753 DV |
10220 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10221 | x, y, fb); | |
c0c36b94 CW |
10222 | if (ret) |
10223 | goto done; | |
a6778b3c DV |
10224 | } |
10225 | ||
10226 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
10227 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
10228 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 10229 | |
a6778b3c DV |
10230 | /* FIXME: add subpixel order */ |
10231 | done: | |
4b4b9238 | 10232 | if (ret && crtc->enabled) |
3ac18232 | 10233 | crtc->mode = *saved_mode; |
a6778b3c | 10234 | |
3ac18232 | 10235 | out: |
b8cecdf5 | 10236 | kfree(pipe_config); |
3ac18232 | 10237 | kfree(saved_mode); |
a6778b3c | 10238 | return ret; |
f6e5b160 CW |
10239 | } |
10240 | ||
e7457a9a DL |
10241 | static int intel_set_mode(struct drm_crtc *crtc, |
10242 | struct drm_display_mode *mode, | |
10243 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
10244 | { |
10245 | int ret; | |
10246 | ||
10247 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
10248 | ||
10249 | if (ret == 0) | |
10250 | intel_modeset_check_state(crtc->dev); | |
10251 | ||
10252 | return ret; | |
10253 | } | |
10254 | ||
c0c36b94 CW |
10255 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10256 | { | |
f4510a27 | 10257 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
10258 | } |
10259 | ||
25c5b266 DV |
10260 | #undef for_each_intel_crtc_masked |
10261 | ||
d9e55608 DV |
10262 | static void intel_set_config_free(struct intel_set_config *config) |
10263 | { | |
10264 | if (!config) | |
10265 | return; | |
10266 | ||
1aa4b628 DV |
10267 | kfree(config->save_connector_encoders); |
10268 | kfree(config->save_encoder_crtcs); | |
7668851f | 10269 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
10270 | kfree(config); |
10271 | } | |
10272 | ||
85f9eb71 DV |
10273 | static int intel_set_config_save_state(struct drm_device *dev, |
10274 | struct intel_set_config *config) | |
10275 | { | |
7668851f | 10276 | struct drm_crtc *crtc; |
85f9eb71 DV |
10277 | struct drm_encoder *encoder; |
10278 | struct drm_connector *connector; | |
10279 | int count; | |
10280 | ||
7668851f VS |
10281 | config->save_crtc_enabled = |
10282 | kcalloc(dev->mode_config.num_crtc, | |
10283 | sizeof(bool), GFP_KERNEL); | |
10284 | if (!config->save_crtc_enabled) | |
10285 | return -ENOMEM; | |
10286 | ||
1aa4b628 DV |
10287 | config->save_encoder_crtcs = |
10288 | kcalloc(dev->mode_config.num_encoder, | |
10289 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10290 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10291 | return -ENOMEM; |
10292 | ||
1aa4b628 DV |
10293 | config->save_connector_encoders = |
10294 | kcalloc(dev->mode_config.num_connector, | |
10295 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10296 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10297 | return -ENOMEM; |
10298 | ||
10299 | /* Copy data. Note that driver private data is not affected. | |
10300 | * Should anything bad happen only the expected state is | |
10301 | * restored, not the drivers personal bookkeeping. | |
10302 | */ | |
7668851f | 10303 | count = 0; |
70e1e0ec | 10304 | for_each_crtc(dev, crtc) { |
7668851f VS |
10305 | config->save_crtc_enabled[count++] = crtc->enabled; |
10306 | } | |
10307 | ||
85f9eb71 DV |
10308 | count = 0; |
10309 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10310 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10311 | } |
10312 | ||
10313 | count = 0; | |
10314 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10315 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10316 | } |
10317 | ||
10318 | return 0; | |
10319 | } | |
10320 | ||
10321 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10322 | struct intel_set_config *config) | |
10323 | { | |
7668851f | 10324 | struct intel_crtc *crtc; |
9a935856 DV |
10325 | struct intel_encoder *encoder; |
10326 | struct intel_connector *connector; | |
85f9eb71 DV |
10327 | int count; |
10328 | ||
7668851f | 10329 | count = 0; |
d3fcc808 | 10330 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10331 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
10332 | |
10333 | if (crtc->new_enabled) | |
10334 | crtc->new_config = &crtc->config; | |
10335 | else | |
10336 | crtc->new_config = NULL; | |
7668851f VS |
10337 | } |
10338 | ||
85f9eb71 | 10339 | count = 0; |
9a935856 DV |
10340 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10341 | encoder->new_crtc = | |
10342 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10343 | } |
10344 | ||
10345 | count = 0; | |
9a935856 DV |
10346 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10347 | connector->new_encoder = | |
10348 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10349 | } |
10350 | } | |
10351 | ||
e3de42b6 | 10352 | static bool |
2e57f47d | 10353 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10354 | { |
10355 | int i; | |
10356 | ||
2e57f47d CW |
10357 | if (set->num_connectors == 0) |
10358 | return false; | |
10359 | ||
10360 | if (WARN_ON(set->connectors == NULL)) | |
10361 | return false; | |
10362 | ||
10363 | for (i = 0; i < set->num_connectors; i++) | |
10364 | if (set->connectors[i]->encoder && | |
10365 | set->connectors[i]->encoder->crtc == set->crtc && | |
10366 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10367 | return true; |
10368 | ||
10369 | return false; | |
10370 | } | |
10371 | ||
5e2b584e DV |
10372 | static void |
10373 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10374 | struct intel_set_config *config) | |
10375 | { | |
10376 | ||
10377 | /* We should be able to check here if the fb has the same properties | |
10378 | * and then just flip_or_move it */ | |
2e57f47d CW |
10379 | if (is_crtc_connector_off(set)) { |
10380 | config->mode_changed = true; | |
f4510a27 | 10381 | } else if (set->crtc->primary->fb != set->fb) { |
5e2b584e | 10382 | /* If we have no fb then treat it as a full mode set */ |
f4510a27 | 10383 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
10384 | struct intel_crtc *intel_crtc = |
10385 | to_intel_crtc(set->crtc); | |
10386 | ||
d330a953 | 10387 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
10388 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10389 | config->fb_changed = true; | |
10390 | } else { | |
10391 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10392 | config->mode_changed = true; | |
10393 | } | |
5e2b584e DV |
10394 | } else if (set->fb == NULL) { |
10395 | config->mode_changed = true; | |
72f4901e | 10396 | } else if (set->fb->pixel_format != |
f4510a27 | 10397 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 10398 | config->mode_changed = true; |
e3de42b6 | 10399 | } else { |
5e2b584e | 10400 | config->fb_changed = true; |
e3de42b6 | 10401 | } |
5e2b584e DV |
10402 | } |
10403 | ||
835c5873 | 10404 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10405 | config->fb_changed = true; |
10406 | ||
10407 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10408 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10409 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10410 | drm_mode_debug_printmodeline(set->mode); | |
10411 | config->mode_changed = true; | |
10412 | } | |
a1d95703 CW |
10413 | |
10414 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10415 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10416 | } |
10417 | ||
2e431051 | 10418 | static int |
9a935856 DV |
10419 | intel_modeset_stage_output_state(struct drm_device *dev, |
10420 | struct drm_mode_set *set, | |
10421 | struct intel_set_config *config) | |
50f56119 | 10422 | { |
9a935856 DV |
10423 | struct intel_connector *connector; |
10424 | struct intel_encoder *encoder; | |
7668851f | 10425 | struct intel_crtc *crtc; |
f3f08572 | 10426 | int ro; |
50f56119 | 10427 | |
9abdda74 | 10428 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
10429 | * of connectors. For paranoia, double-check this. */ |
10430 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
10431 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
10432 | ||
9a935856 DV |
10433 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10434 | base.head) { | |
10435 | /* Otherwise traverse passed in connector list and get encoders | |
10436 | * for them. */ | |
50f56119 | 10437 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
10438 | if (set->connectors[ro] == &connector->base) { |
10439 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
10440 | break; |
10441 | } | |
10442 | } | |
10443 | ||
9a935856 DV |
10444 | /* If we disable the crtc, disable all its connectors. Also, if |
10445 | * the connector is on the changing crtc but not on the new | |
10446 | * connector list, disable it. */ | |
10447 | if ((!set->fb || ro == set->num_connectors) && | |
10448 | connector->base.encoder && | |
10449 | connector->base.encoder->crtc == set->crtc) { | |
10450 | connector->new_encoder = NULL; | |
10451 | ||
10452 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
10453 | connector->base.base.id, | |
10454 | drm_get_connector_name(&connector->base)); | |
10455 | } | |
10456 | ||
10457 | ||
10458 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 10459 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 10460 | config->mode_changed = true; |
50f56119 DV |
10461 | } |
10462 | } | |
9a935856 | 10463 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 10464 | |
9a935856 | 10465 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
10466 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10467 | base.head) { | |
7668851f VS |
10468 | struct drm_crtc *new_crtc; |
10469 | ||
9a935856 | 10470 | if (!connector->new_encoder) |
50f56119 DV |
10471 | continue; |
10472 | ||
9a935856 | 10473 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
10474 | |
10475 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 10476 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
10477 | new_crtc = set->crtc; |
10478 | } | |
10479 | ||
10480 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
10481 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10482 | new_crtc)) { | |
5e2b584e | 10483 | return -EINVAL; |
50f56119 | 10484 | } |
9a935856 DV |
10485 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10486 | ||
10487 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10488 | connector->base.base.id, | |
10489 | drm_get_connector_name(&connector->base), | |
10490 | new_crtc->base.id); | |
10491 | } | |
10492 | ||
10493 | /* Check for any encoders that needs to be disabled. */ | |
10494 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10495 | base.head) { | |
5a65f358 | 10496 | int num_connectors = 0; |
9a935856 DV |
10497 | list_for_each_entry(connector, |
10498 | &dev->mode_config.connector_list, | |
10499 | base.head) { | |
10500 | if (connector->new_encoder == encoder) { | |
10501 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10502 | num_connectors++; |
9a935856 DV |
10503 | } |
10504 | } | |
5a65f358 PZ |
10505 | |
10506 | if (num_connectors == 0) | |
10507 | encoder->new_crtc = NULL; | |
10508 | else if (num_connectors > 1) | |
10509 | return -EINVAL; | |
10510 | ||
9a935856 DV |
10511 | /* Only now check for crtc changes so we don't miss encoders |
10512 | * that will be disabled. */ | |
10513 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10514 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10515 | config->mode_changed = true; |
50f56119 DV |
10516 | } |
10517 | } | |
9a935856 | 10518 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10519 | |
d3fcc808 | 10520 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
10521 | crtc->new_enabled = false; |
10522 | ||
10523 | list_for_each_entry(encoder, | |
10524 | &dev->mode_config.encoder_list, | |
10525 | base.head) { | |
10526 | if (encoder->new_crtc == crtc) { | |
10527 | crtc->new_enabled = true; | |
10528 | break; | |
10529 | } | |
10530 | } | |
10531 | ||
10532 | if (crtc->new_enabled != crtc->base.enabled) { | |
10533 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10534 | crtc->new_enabled ? "en" : "dis"); | |
10535 | config->mode_changed = true; | |
10536 | } | |
7bd0a8e7 VS |
10537 | |
10538 | if (crtc->new_enabled) | |
10539 | crtc->new_config = &crtc->config; | |
10540 | else | |
10541 | crtc->new_config = NULL; | |
7668851f VS |
10542 | } |
10543 | ||
2e431051 DV |
10544 | return 0; |
10545 | } | |
10546 | ||
7d00a1f5 VS |
10547 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10548 | { | |
10549 | struct drm_device *dev = crtc->base.dev; | |
10550 | struct intel_encoder *encoder; | |
10551 | struct intel_connector *connector; | |
10552 | ||
10553 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10554 | pipe_name(crtc->pipe)); | |
10555 | ||
10556 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10557 | if (connector->new_encoder && | |
10558 | connector->new_encoder->new_crtc == crtc) | |
10559 | connector->new_encoder = NULL; | |
10560 | } | |
10561 | ||
10562 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10563 | if (encoder->new_crtc == crtc) | |
10564 | encoder->new_crtc = NULL; | |
10565 | } | |
10566 | ||
10567 | crtc->new_enabled = false; | |
7bd0a8e7 | 10568 | crtc->new_config = NULL; |
7d00a1f5 VS |
10569 | } |
10570 | ||
2e431051 DV |
10571 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10572 | { | |
10573 | struct drm_device *dev; | |
2e431051 DV |
10574 | struct drm_mode_set save_set; |
10575 | struct intel_set_config *config; | |
10576 | int ret; | |
2e431051 | 10577 | |
8d3e375e DV |
10578 | BUG_ON(!set); |
10579 | BUG_ON(!set->crtc); | |
10580 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10581 | |
7e53f3a4 DV |
10582 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10583 | BUG_ON(!set->mode && set->fb); | |
10584 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10585 | |
2e431051 DV |
10586 | if (set->fb) { |
10587 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10588 | set->crtc->base.id, set->fb->base.id, | |
10589 | (int)set->num_connectors, set->x, set->y); | |
10590 | } else { | |
10591 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10592 | } |
10593 | ||
10594 | dev = set->crtc->dev; | |
10595 | ||
10596 | ret = -ENOMEM; | |
10597 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10598 | if (!config) | |
10599 | goto out_config; | |
10600 | ||
10601 | ret = intel_set_config_save_state(dev, config); | |
10602 | if (ret) | |
10603 | goto out_config; | |
10604 | ||
10605 | save_set.crtc = set->crtc; | |
10606 | save_set.mode = &set->crtc->mode; | |
10607 | save_set.x = set->crtc->x; | |
10608 | save_set.y = set->crtc->y; | |
f4510a27 | 10609 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
10610 | |
10611 | /* Compute whether we need a full modeset, only an fb base update or no | |
10612 | * change at all. In the future we might also check whether only the | |
10613 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10614 | * such cases. */ | |
10615 | intel_set_config_compute_mode_changes(set, config); | |
10616 | ||
9a935856 | 10617 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10618 | if (ret) |
10619 | goto fail; | |
10620 | ||
5e2b584e | 10621 | if (config->mode_changed) { |
c0c36b94 CW |
10622 | ret = intel_set_mode(set->crtc, set->mode, |
10623 | set->x, set->y, set->fb); | |
5e2b584e | 10624 | } else if (config->fb_changed) { |
4878cae2 VS |
10625 | intel_crtc_wait_for_pending_flips(set->crtc); |
10626 | ||
4f660f49 | 10627 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10628 | set->x, set->y, set->fb); |
7ca51a3a JB |
10629 | /* |
10630 | * In the fastboot case this may be our only check of the | |
10631 | * state after boot. It would be better to only do it on | |
10632 | * the first update, but we don't have a nice way of doing that | |
10633 | * (and really, set_config isn't used much for high freq page | |
10634 | * flipping, so increasing its cost here shouldn't be a big | |
10635 | * deal). | |
10636 | */ | |
d330a953 | 10637 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10638 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10639 | } |
10640 | ||
2d05eae1 | 10641 | if (ret) { |
bf67dfeb DV |
10642 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10643 | set->crtc->base.id, ret); | |
50f56119 | 10644 | fail: |
2d05eae1 | 10645 | intel_set_config_restore_state(dev, config); |
50f56119 | 10646 | |
7d00a1f5 VS |
10647 | /* |
10648 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10649 | * force the pipe off to avoid oopsing in the modeset code | |
10650 | * due to fb==NULL. This should only happen during boot since | |
10651 | * we don't yet reconstruct the FB from the hardware state. | |
10652 | */ | |
10653 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10654 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10655 | ||
2d05eae1 CW |
10656 | /* Try to restore the config */ |
10657 | if (config->mode_changed && | |
10658 | intel_set_mode(save_set.crtc, save_set.mode, | |
10659 | save_set.x, save_set.y, save_set.fb)) | |
10660 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10661 | } | |
50f56119 | 10662 | |
d9e55608 DV |
10663 | out_config: |
10664 | intel_set_config_free(config); | |
50f56119 DV |
10665 | return ret; |
10666 | } | |
f6e5b160 CW |
10667 | |
10668 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10669 | .cursor_set = intel_crtc_cursor_set, |
10670 | .cursor_move = intel_crtc_cursor_move, | |
10671 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10672 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10673 | .destroy = intel_crtc_destroy, |
10674 | .page_flip = intel_crtc_page_flip, | |
10675 | }; | |
10676 | ||
79f689aa PZ |
10677 | static void intel_cpu_pll_init(struct drm_device *dev) |
10678 | { | |
affa9354 | 10679 | if (HAS_DDI(dev)) |
79f689aa PZ |
10680 | intel_ddi_pll_init(dev); |
10681 | } | |
10682 | ||
5358901f DV |
10683 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10684 | struct intel_shared_dpll *pll, | |
10685 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10686 | { |
5358901f | 10687 | uint32_t val; |
ee7b9f93 | 10688 | |
5358901f | 10689 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10690 | hw_state->dpll = val; |
10691 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10692 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10693 | |
10694 | return val & DPLL_VCO_ENABLE; | |
10695 | } | |
10696 | ||
15bdd4cf DV |
10697 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10698 | struct intel_shared_dpll *pll) | |
10699 | { | |
10700 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10701 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10702 | } | |
10703 | ||
e7b903d2 DV |
10704 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10705 | struct intel_shared_dpll *pll) | |
10706 | { | |
e7b903d2 | 10707 | /* PCH refclock must be enabled first */ |
89eff4be | 10708 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10709 | |
15bdd4cf DV |
10710 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10711 | ||
10712 | /* Wait for the clocks to stabilize. */ | |
10713 | POSTING_READ(PCH_DPLL(pll->id)); | |
10714 | udelay(150); | |
10715 | ||
10716 | /* The pixel multiplier can only be updated once the | |
10717 | * DPLL is enabled and the clocks are stable. | |
10718 | * | |
10719 | * So write it again. | |
10720 | */ | |
10721 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10722 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10723 | udelay(200); |
10724 | } | |
10725 | ||
10726 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10727 | struct intel_shared_dpll *pll) | |
10728 | { | |
10729 | struct drm_device *dev = dev_priv->dev; | |
10730 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10731 | |
10732 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 10733 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
10734 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
10735 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10736 | } |
10737 | ||
15bdd4cf DV |
10738 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10739 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10740 | udelay(200); |
10741 | } | |
10742 | ||
46edb027 DV |
10743 | static char *ibx_pch_dpll_names[] = { |
10744 | "PCH DPLL A", | |
10745 | "PCH DPLL B", | |
10746 | }; | |
10747 | ||
7c74ade1 | 10748 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10749 | { |
e7b903d2 | 10750 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10751 | int i; |
10752 | ||
7c74ade1 | 10753 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10754 | |
e72f9fbf | 10755 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10756 | dev_priv->shared_dplls[i].id = i; |
10757 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10758 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10759 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10760 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10761 | dev_priv->shared_dplls[i].get_hw_state = |
10762 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10763 | } |
10764 | } | |
10765 | ||
7c74ade1 DV |
10766 | static void intel_shared_dpll_init(struct drm_device *dev) |
10767 | { | |
e7b903d2 | 10768 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10769 | |
10770 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10771 | ibx_pch_dpll_init(dev); | |
10772 | else | |
10773 | dev_priv->num_shared_dpll = 0; | |
10774 | ||
10775 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10776 | } |
10777 | ||
b358d0a6 | 10778 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10779 | { |
fbee40df | 10780 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
10781 | struct intel_crtc *intel_crtc; |
10782 | int i; | |
10783 | ||
955382f3 | 10784 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10785 | if (intel_crtc == NULL) |
10786 | return; | |
10787 | ||
10788 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10789 | ||
10790 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10791 | for (i = 0; i < 256; i++) { |
10792 | intel_crtc->lut_r[i] = i; | |
10793 | intel_crtc->lut_g[i] = i; | |
10794 | intel_crtc->lut_b[i] = i; | |
10795 | } | |
10796 | ||
1f1c2e24 VS |
10797 | /* |
10798 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10799 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10800 | */ | |
80824003 JB |
10801 | intel_crtc->pipe = pipe; |
10802 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10803 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10804 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10805 | intel_crtc->plane = !pipe; |
80824003 JB |
10806 | } |
10807 | ||
8d7849db VS |
10808 | init_waitqueue_head(&intel_crtc->vbl_wait); |
10809 | ||
22fd0fab JB |
10810 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10811 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10812 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10813 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10814 | ||
79e53945 | 10815 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10816 | } |
10817 | ||
752aa88a JB |
10818 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10819 | { | |
10820 | struct drm_encoder *encoder = connector->base.encoder; | |
10821 | ||
10822 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10823 | ||
10824 | if (!encoder) | |
10825 | return INVALID_PIPE; | |
10826 | ||
10827 | return to_intel_crtc(encoder->crtc)->pipe; | |
10828 | } | |
10829 | ||
08d7b3d1 | 10830 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10831 | struct drm_file *file) |
08d7b3d1 | 10832 | { |
08d7b3d1 | 10833 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10834 | struct drm_mode_object *drmmode_obj; |
10835 | struct intel_crtc *crtc; | |
08d7b3d1 | 10836 | |
1cff8f6b DV |
10837 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10838 | return -ENODEV; | |
08d7b3d1 | 10839 | |
c05422d5 DV |
10840 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10841 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10842 | |
c05422d5 | 10843 | if (!drmmode_obj) { |
08d7b3d1 | 10844 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10845 | return -ENOENT; |
08d7b3d1 CW |
10846 | } |
10847 | ||
c05422d5 DV |
10848 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10849 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10850 | |
c05422d5 | 10851 | return 0; |
08d7b3d1 CW |
10852 | } |
10853 | ||
66a9278e | 10854 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10855 | { |
66a9278e DV |
10856 | struct drm_device *dev = encoder->base.dev; |
10857 | struct intel_encoder *source_encoder; | |
79e53945 | 10858 | int index_mask = 0; |
79e53945 JB |
10859 | int entry = 0; |
10860 | ||
66a9278e DV |
10861 | list_for_each_entry(source_encoder, |
10862 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 10863 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
10864 | index_mask |= (1 << entry); |
10865 | ||
79e53945 JB |
10866 | entry++; |
10867 | } | |
4ef69c7a | 10868 | |
79e53945 JB |
10869 | return index_mask; |
10870 | } | |
10871 | ||
4d302442 CW |
10872 | static bool has_edp_a(struct drm_device *dev) |
10873 | { | |
10874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10875 | ||
10876 | if (!IS_MOBILE(dev)) | |
10877 | return false; | |
10878 | ||
10879 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10880 | return false; | |
10881 | ||
e3589908 | 10882 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
10883 | return false; |
10884 | ||
10885 | return true; | |
10886 | } | |
10887 | ||
ba0fbca4 DL |
10888 | const char *intel_output_name(int output) |
10889 | { | |
10890 | static const char *names[] = { | |
10891 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
10892 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
10893 | [INTEL_OUTPUT_DVO] = "DVO", | |
10894 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
10895 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
10896 | [INTEL_OUTPUT_TVOUT] = "TV", | |
10897 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
10898 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
10899 | [INTEL_OUTPUT_EDP] = "eDP", | |
10900 | [INTEL_OUTPUT_DSI] = "DSI", | |
10901 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
10902 | }; | |
10903 | ||
10904 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
10905 | return "Invalid"; | |
10906 | ||
10907 | return names[output]; | |
10908 | } | |
10909 | ||
79e53945 JB |
10910 | static void intel_setup_outputs(struct drm_device *dev) |
10911 | { | |
725e30ad | 10912 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10913 | struct intel_encoder *encoder; |
cb0953d7 | 10914 | bool dpd_is_edp = false; |
79e53945 | 10915 | |
c9093354 | 10916 | intel_lvds_init(dev); |
79e53945 | 10917 | |
7895a81d | 10918 | if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev)) |
79935fca | 10919 | intel_crt_init(dev); |
cb0953d7 | 10920 | |
affa9354 | 10921 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10922 | int found; |
10923 | ||
10924 | /* Haswell uses DDI functions to detect digital outputs */ | |
10925 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10926 | /* DDI A only supports eDP */ | |
10927 | if (found) | |
10928 | intel_ddi_init(dev, PORT_A); | |
10929 | ||
10930 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10931 | * register */ | |
10932 | found = I915_READ(SFUSE_STRAP); | |
10933 | ||
10934 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10935 | intel_ddi_init(dev, PORT_B); | |
10936 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10937 | intel_ddi_init(dev, PORT_C); | |
10938 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10939 | intel_ddi_init(dev, PORT_D); | |
10940 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10941 | int found; |
5d8a7752 | 10942 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
10943 | |
10944 | if (has_edp_a(dev)) | |
10945 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10946 | |
dc0fa718 | 10947 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10948 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10949 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10950 | if (!found) |
e2debe91 | 10951 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10952 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10953 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10954 | } |
10955 | ||
dc0fa718 | 10956 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10957 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10958 | |
dc0fa718 | 10959 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10960 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10961 | |
5eb08b69 | 10962 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10963 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10964 | |
270b3042 | 10965 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10966 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10967 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10968 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10969 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10970 | PORT_B); | |
10971 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10972 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10973 | } | |
10974 | ||
6f6005a5 JB |
10975 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10976 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10977 | PORT_C); | |
10978 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 10979 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 10980 | } |
19c03924 | 10981 | |
3cfca973 | 10982 | intel_dsi_init(dev); |
103a196f | 10983 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10984 | bool found = false; |
7d57382e | 10985 | |
e2debe91 | 10986 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10987 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10988 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10989 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10990 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10991 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10992 | } |
27185ae1 | 10993 | |
e7281eab | 10994 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10995 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10996 | } |
13520b05 KH |
10997 | |
10998 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10999 | |
e2debe91 | 11000 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11001 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 11002 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 11003 | } |
27185ae1 | 11004 | |
e2debe91 | 11005 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 11006 | |
b01f2c3a JB |
11007 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11008 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 11009 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 11010 | } |
e7281eab | 11011 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11012 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 11013 | } |
27185ae1 | 11014 | |
b01f2c3a | 11015 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 11016 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 11017 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 11018 | } else if (IS_GEN2(dev)) |
79e53945 JB |
11019 | intel_dvo_init(dev); |
11020 | ||
103a196f | 11021 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
11022 | intel_tv_init(dev); |
11023 | ||
4ef69c7a CW |
11024 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11025 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
11026 | encoder->base.possible_clones = | |
66a9278e | 11027 | intel_encoder_clones(encoder); |
79e53945 | 11028 | } |
47356eb6 | 11029 | |
dde86e2d | 11030 | intel_init_pch_refclk(dev); |
270b3042 DV |
11031 | |
11032 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
11033 | } |
11034 | ||
11035 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
11036 | { | |
11037 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 11038 | |
ef2d633e DV |
11039 | drm_framebuffer_cleanup(fb); |
11040 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
11041 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
11042 | kfree(intel_fb); |
11043 | } | |
11044 | ||
11045 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 11046 | struct drm_file *file, |
79e53945 JB |
11047 | unsigned int *handle) |
11048 | { | |
11049 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 11050 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 11051 | |
05394f39 | 11052 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
11053 | } |
11054 | ||
11055 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
11056 | .destroy = intel_user_framebuffer_destroy, | |
11057 | .create_handle = intel_user_framebuffer_create_handle, | |
11058 | }; | |
11059 | ||
b5ea642a DV |
11060 | static int intel_framebuffer_init(struct drm_device *dev, |
11061 | struct intel_framebuffer *intel_fb, | |
11062 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11063 | struct drm_i915_gem_object *obj) | |
79e53945 | 11064 | { |
a57ce0b2 | 11065 | int aligned_height; |
a35cdaa0 | 11066 | int pitch_limit; |
79e53945 JB |
11067 | int ret; |
11068 | ||
dd4916c5 DV |
11069 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
11070 | ||
c16ed4be CW |
11071 | if (obj->tiling_mode == I915_TILING_Y) { |
11072 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 11073 | return -EINVAL; |
c16ed4be | 11074 | } |
57cd6508 | 11075 | |
c16ed4be CW |
11076 | if (mode_cmd->pitches[0] & 63) { |
11077 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
11078 | mode_cmd->pitches[0]); | |
57cd6508 | 11079 | return -EINVAL; |
c16ed4be | 11080 | } |
57cd6508 | 11081 | |
a35cdaa0 CW |
11082 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
11083 | pitch_limit = 32*1024; | |
11084 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
11085 | if (obj->tiling_mode) | |
11086 | pitch_limit = 16*1024; | |
11087 | else | |
11088 | pitch_limit = 32*1024; | |
11089 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
11090 | if (obj->tiling_mode) | |
11091 | pitch_limit = 8*1024; | |
11092 | else | |
11093 | pitch_limit = 16*1024; | |
11094 | } else | |
11095 | /* XXX DSPC is limited to 4k tiled */ | |
11096 | pitch_limit = 8*1024; | |
11097 | ||
11098 | if (mode_cmd->pitches[0] > pitch_limit) { | |
11099 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
11100 | obj->tiling_mode ? "tiled" : "linear", | |
11101 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 11102 | return -EINVAL; |
c16ed4be | 11103 | } |
5d7bd705 VS |
11104 | |
11105 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
11106 | mode_cmd->pitches[0] != obj->stride) { |
11107 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
11108 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 11109 | return -EINVAL; |
c16ed4be | 11110 | } |
5d7bd705 | 11111 | |
57779d06 | 11112 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 11113 | switch (mode_cmd->pixel_format) { |
57779d06 | 11114 | case DRM_FORMAT_C8: |
04b3924d VS |
11115 | case DRM_FORMAT_RGB565: |
11116 | case DRM_FORMAT_XRGB8888: | |
11117 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
11118 | break; |
11119 | case DRM_FORMAT_XRGB1555: | |
11120 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 11121 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
11122 | DRM_DEBUG("unsupported pixel format: %s\n", |
11123 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11124 | return -EINVAL; |
c16ed4be | 11125 | } |
57779d06 VS |
11126 | break; |
11127 | case DRM_FORMAT_XBGR8888: | |
11128 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
11129 | case DRM_FORMAT_XRGB2101010: |
11130 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
11131 | case DRM_FORMAT_XBGR2101010: |
11132 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 11133 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
11134 | DRM_DEBUG("unsupported pixel format: %s\n", |
11135 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11136 | return -EINVAL; |
c16ed4be | 11137 | } |
b5626747 | 11138 | break; |
04b3924d VS |
11139 | case DRM_FORMAT_YUYV: |
11140 | case DRM_FORMAT_UYVY: | |
11141 | case DRM_FORMAT_YVYU: | |
11142 | case DRM_FORMAT_VYUY: | |
c16ed4be | 11143 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
11144 | DRM_DEBUG("unsupported pixel format: %s\n", |
11145 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11146 | return -EINVAL; |
c16ed4be | 11147 | } |
57cd6508 CW |
11148 | break; |
11149 | default: | |
4ee62c76 VS |
11150 | DRM_DEBUG("unsupported pixel format: %s\n", |
11151 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
11152 | return -EINVAL; |
11153 | } | |
11154 | ||
90f9a336 VS |
11155 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11156 | if (mode_cmd->offsets[0] != 0) | |
11157 | return -EINVAL; | |
11158 | ||
a57ce0b2 JB |
11159 | aligned_height = intel_align_height(dev, mode_cmd->height, |
11160 | obj->tiling_mode); | |
53155c0a DV |
11161 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11162 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
11163 | return -EINVAL; | |
11164 | ||
c7d73f6a DV |
11165 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
11166 | intel_fb->obj = obj; | |
80075d49 | 11167 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 11168 | |
79e53945 JB |
11169 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
11170 | if (ret) { | |
11171 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
11172 | return ret; | |
11173 | } | |
11174 | ||
79e53945 JB |
11175 | return 0; |
11176 | } | |
11177 | ||
79e53945 JB |
11178 | static struct drm_framebuffer * |
11179 | intel_user_framebuffer_create(struct drm_device *dev, | |
11180 | struct drm_file *filp, | |
308e5bcb | 11181 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 11182 | { |
05394f39 | 11183 | struct drm_i915_gem_object *obj; |
79e53945 | 11184 | |
308e5bcb JB |
11185 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
11186 | mode_cmd->handles[0])); | |
c8725226 | 11187 | if (&obj->base == NULL) |
cce13ff7 | 11188 | return ERR_PTR(-ENOENT); |
79e53945 | 11189 | |
d2dff872 | 11190 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
11191 | } |
11192 | ||
4520f53a | 11193 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 11194 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
11195 | { |
11196 | } | |
11197 | #endif | |
11198 | ||
79e53945 | 11199 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 11200 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 11201 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
11202 | }; |
11203 | ||
e70236a8 JB |
11204 | /* Set up chip specific display functions */ |
11205 | static void intel_init_display(struct drm_device *dev) | |
11206 | { | |
11207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11208 | ||
ee9300bb DV |
11209 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11210 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
11211 | else if (IS_CHERRYVIEW(dev)) |
11212 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
11213 | else if (IS_VALLEYVIEW(dev)) |
11214 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
11215 | else if (IS_PINEVIEW(dev)) | |
11216 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
11217 | else | |
11218 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
11219 | ||
affa9354 | 11220 | if (HAS_DDI(dev)) { |
0e8ffe1b | 11221 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 11222 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 11223 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
11224 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11225 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 11226 | dev_priv->display.off = haswell_crtc_off; |
262ca2b0 MR |
11227 | dev_priv->display.update_primary_plane = |
11228 | ironlake_update_primary_plane; | |
09b4ddf9 | 11229 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 11230 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 11231 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 11232 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
11233 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11234 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 11235 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
11236 | dev_priv->display.update_primary_plane = |
11237 | ironlake_update_primary_plane; | |
89b667f8 JB |
11238 | } else if (IS_VALLEYVIEW(dev)) { |
11239 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 11240 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
11241 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11242 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
11243 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
11244 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
11245 | dev_priv->display.update_primary_plane = |
11246 | i9xx_update_primary_plane; | |
f564048e | 11247 | } else { |
0e8ffe1b | 11248 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 11249 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 11250 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
11251 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
11252 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 11253 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
11254 | dev_priv->display.update_primary_plane = |
11255 | i9xx_update_primary_plane; | |
f564048e | 11256 | } |
e70236a8 | 11257 | |
e70236a8 | 11258 | /* Returns the core display clock speed */ |
25eb05fc JB |
11259 | if (IS_VALLEYVIEW(dev)) |
11260 | dev_priv->display.get_display_clock_speed = | |
11261 | valleyview_get_display_clock_speed; | |
11262 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
11263 | dev_priv->display.get_display_clock_speed = |
11264 | i945_get_display_clock_speed; | |
11265 | else if (IS_I915G(dev)) | |
11266 | dev_priv->display.get_display_clock_speed = | |
11267 | i915_get_display_clock_speed; | |
257a7ffc | 11268 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
11269 | dev_priv->display.get_display_clock_speed = |
11270 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
11271 | else if (IS_PINEVIEW(dev)) |
11272 | dev_priv->display.get_display_clock_speed = | |
11273 | pnv_get_display_clock_speed; | |
e70236a8 JB |
11274 | else if (IS_I915GM(dev)) |
11275 | dev_priv->display.get_display_clock_speed = | |
11276 | i915gm_get_display_clock_speed; | |
11277 | else if (IS_I865G(dev)) | |
11278 | dev_priv->display.get_display_clock_speed = | |
11279 | i865_get_display_clock_speed; | |
f0f8a9ce | 11280 | else if (IS_I85X(dev)) |
e70236a8 JB |
11281 | dev_priv->display.get_display_clock_speed = |
11282 | i855_get_display_clock_speed; | |
11283 | else /* 852, 830 */ | |
11284 | dev_priv->display.get_display_clock_speed = | |
11285 | i830_get_display_clock_speed; | |
11286 | ||
7f8a8569 | 11287 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 11288 | if (IS_GEN5(dev)) { |
674cf967 | 11289 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 11290 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 11291 | } else if (IS_GEN6(dev)) { |
674cf967 | 11292 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 11293 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
11294 | dev_priv->display.modeset_global_resources = |
11295 | snb_modeset_global_resources; | |
357555c0 JB |
11296 | } else if (IS_IVYBRIDGE(dev)) { |
11297 | /* FIXME: detect B0+ stepping and use auto training */ | |
11298 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 11299 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
11300 | dev_priv->display.modeset_global_resources = |
11301 | ivb_modeset_global_resources; | |
4e0bbc31 | 11302 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 11303 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 11304 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
11305 | dev_priv->display.modeset_global_resources = |
11306 | haswell_modeset_global_resources; | |
a0e63c22 | 11307 | } |
6067aaea | 11308 | } else if (IS_G4X(dev)) { |
e0dac65e | 11309 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
11310 | } else if (IS_VALLEYVIEW(dev)) { |
11311 | dev_priv->display.modeset_global_resources = | |
11312 | valleyview_modeset_global_resources; | |
9ca2fe73 | 11313 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 11314 | } |
8c9f3aaf JB |
11315 | |
11316 | /* Default just returns -ENODEV to indicate unsupported */ | |
11317 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
11318 | ||
11319 | switch (INTEL_INFO(dev)->gen) { | |
11320 | case 2: | |
11321 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
11322 | break; | |
11323 | ||
11324 | case 3: | |
11325 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
11326 | break; | |
11327 | ||
11328 | case 4: | |
11329 | case 5: | |
11330 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
11331 | break; | |
11332 | ||
11333 | case 6: | |
11334 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
11335 | break; | |
7c9017e5 | 11336 | case 7: |
4e0bbc31 | 11337 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
11338 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
11339 | break; | |
8c9f3aaf | 11340 | } |
7bd688cd JN |
11341 | |
11342 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
11343 | } |
11344 | ||
b690e96c JB |
11345 | /* |
11346 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
11347 | * resume, or other times. This quirk makes sure that's the case for | |
11348 | * affected systems. | |
11349 | */ | |
0206e353 | 11350 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
11351 | { |
11352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11353 | ||
11354 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 11355 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
11356 | } |
11357 | ||
435793df KP |
11358 | /* |
11359 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
11360 | */ | |
11361 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
11362 | { | |
11363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11364 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 11365 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
11366 | } |
11367 | ||
4dca20ef | 11368 | /* |
5a15ab5b CE |
11369 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
11370 | * brightness value | |
4dca20ef CE |
11371 | */ |
11372 | static void quirk_invert_brightness(struct drm_device *dev) | |
11373 | { | |
11374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11375 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 11376 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
11377 | } |
11378 | ||
b690e96c JB |
11379 | struct intel_quirk { |
11380 | int device; | |
11381 | int subsystem_vendor; | |
11382 | int subsystem_device; | |
11383 | void (*hook)(struct drm_device *dev); | |
11384 | }; | |
11385 | ||
5f85f176 EE |
11386 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
11387 | struct intel_dmi_quirk { | |
11388 | void (*hook)(struct drm_device *dev); | |
11389 | const struct dmi_system_id (*dmi_id_list)[]; | |
11390 | }; | |
11391 | ||
11392 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
11393 | { | |
11394 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
11395 | return 1; | |
11396 | } | |
11397 | ||
11398 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
11399 | { | |
11400 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
11401 | { | |
11402 | .callback = intel_dmi_reverse_brightness, | |
11403 | .ident = "NCR Corporation", | |
11404 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
11405 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
11406 | }, | |
11407 | }, | |
11408 | { } /* terminating entry */ | |
11409 | }, | |
11410 | .hook = quirk_invert_brightness, | |
11411 | }, | |
11412 | }; | |
11413 | ||
c43b5634 | 11414 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 11415 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 11416 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 11417 | |
b690e96c JB |
11418 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
11419 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
11420 | ||
b690e96c JB |
11421 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
11422 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
11423 | ||
a4945f95 | 11424 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 11425 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
11426 | |
11427 | /* Lenovo U160 cannot use SSC on LVDS */ | |
11428 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
11429 | |
11430 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
11431 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 11432 | |
be505f64 AH |
11433 | /* Acer Aspire 5734Z must invert backlight brightness */ |
11434 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
11435 | ||
11436 | /* Acer/eMachines G725 */ | |
11437 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
11438 | ||
11439 | /* Acer/eMachines e725 */ | |
11440 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
11441 | ||
11442 | /* Acer/Packard Bell NCL20 */ | |
11443 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
11444 | ||
11445 | /* Acer Aspire 4736Z */ | |
11446 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
11447 | |
11448 | /* Acer Aspire 5336 */ | |
11449 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
11450 | }; |
11451 | ||
11452 | static void intel_init_quirks(struct drm_device *dev) | |
11453 | { | |
11454 | struct pci_dev *d = dev->pdev; | |
11455 | int i; | |
11456 | ||
11457 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
11458 | struct intel_quirk *q = &intel_quirks[i]; | |
11459 | ||
11460 | if (d->device == q->device && | |
11461 | (d->subsystem_vendor == q->subsystem_vendor || | |
11462 | q->subsystem_vendor == PCI_ANY_ID) && | |
11463 | (d->subsystem_device == q->subsystem_device || | |
11464 | q->subsystem_device == PCI_ANY_ID)) | |
11465 | q->hook(dev); | |
11466 | } | |
5f85f176 EE |
11467 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
11468 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
11469 | intel_dmi_quirks[i].hook(dev); | |
11470 | } | |
b690e96c JB |
11471 | } |
11472 | ||
9cce37f4 JB |
11473 | /* Disable the VGA plane that we never use */ |
11474 | static void i915_disable_vga(struct drm_device *dev) | |
11475 | { | |
11476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11477 | u8 sr1; | |
766aa1c4 | 11478 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 11479 | |
2b37c616 | 11480 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 11481 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 11482 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
11483 | sr1 = inb(VGA_SR_DATA); |
11484 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
11485 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
11486 | udelay(300); | |
11487 | ||
11488 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
11489 | POSTING_READ(vga_reg); | |
11490 | } | |
11491 | ||
f817586c DV |
11492 | void intel_modeset_init_hw(struct drm_device *dev) |
11493 | { | |
a8f78b58 ED |
11494 | intel_prepare_ddi(dev); |
11495 | ||
f817586c DV |
11496 | intel_init_clock_gating(dev); |
11497 | ||
5382f5f3 | 11498 | intel_reset_dpio(dev); |
40e9cf64 | 11499 | |
8090c6b9 | 11500 | intel_enable_gt_powersave(dev); |
f817586c DV |
11501 | } |
11502 | ||
7d708ee4 ID |
11503 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11504 | { | |
11505 | intel_suspend_hw(dev); | |
11506 | } | |
11507 | ||
79e53945 JB |
11508 | void intel_modeset_init(struct drm_device *dev) |
11509 | { | |
652c393a | 11510 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 11511 | int sprite, ret; |
8cc87b75 | 11512 | enum pipe pipe; |
46f297fb | 11513 | struct intel_crtc *crtc; |
79e53945 JB |
11514 | |
11515 | drm_mode_config_init(dev); | |
11516 | ||
11517 | dev->mode_config.min_width = 0; | |
11518 | dev->mode_config.min_height = 0; | |
11519 | ||
019d96cb DA |
11520 | dev->mode_config.preferred_depth = 24; |
11521 | dev->mode_config.prefer_shadow = 1; | |
11522 | ||
e6ecefaa | 11523 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11524 | |
b690e96c JB |
11525 | intel_init_quirks(dev); |
11526 | ||
1fa61106 ED |
11527 | intel_init_pm(dev); |
11528 | ||
e3c74757 BW |
11529 | if (INTEL_INFO(dev)->num_pipes == 0) |
11530 | return; | |
11531 | ||
e70236a8 JB |
11532 | intel_init_display(dev); |
11533 | ||
a6c45cf0 CW |
11534 | if (IS_GEN2(dev)) { |
11535 | dev->mode_config.max_width = 2048; | |
11536 | dev->mode_config.max_height = 2048; | |
11537 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11538 | dev->mode_config.max_width = 4096; |
11539 | dev->mode_config.max_height = 4096; | |
79e53945 | 11540 | } else { |
a6c45cf0 CW |
11541 | dev->mode_config.max_width = 8192; |
11542 | dev->mode_config.max_height = 8192; | |
79e53945 | 11543 | } |
068be561 DL |
11544 | |
11545 | if (IS_GEN2(dev)) { | |
11546 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
11547 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
11548 | } else { | |
11549 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
11550 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
11551 | } | |
11552 | ||
5d4545ae | 11553 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11554 | |
28c97730 | 11555 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11556 | INTEL_INFO(dev)->num_pipes, |
11557 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11558 | |
8cc87b75 DL |
11559 | for_each_pipe(pipe) { |
11560 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
11561 | for_each_sprite(pipe, sprite) { |
11562 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 11563 | if (ret) |
06da8da2 | 11564 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 11565 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 11566 | } |
79e53945 JB |
11567 | } |
11568 | ||
f42bb70d | 11569 | intel_init_dpio(dev); |
5382f5f3 | 11570 | intel_reset_dpio(dev); |
f42bb70d | 11571 | |
79f689aa | 11572 | intel_cpu_pll_init(dev); |
e72f9fbf | 11573 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11574 | |
9cce37f4 JB |
11575 | /* Just disable it once at startup */ |
11576 | i915_disable_vga(dev); | |
79e53945 | 11577 | intel_setup_outputs(dev); |
11be49eb CW |
11578 | |
11579 | /* Just in case the BIOS is doing something questionable. */ | |
11580 | intel_disable_fbc(dev); | |
fa9fa083 | 11581 | |
8b687df4 | 11582 | mutex_lock(&dev->mode_config.mutex); |
fa9fa083 | 11583 | intel_modeset_setup_hw_state(dev, false); |
8b687df4 | 11584 | mutex_unlock(&dev->mode_config.mutex); |
46f297fb | 11585 | |
d3fcc808 | 11586 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
11587 | if (!crtc->active) |
11588 | continue; | |
11589 | ||
46f297fb | 11590 | /* |
46f297fb JB |
11591 | * Note that reserving the BIOS fb up front prevents us |
11592 | * from stuffing other stolen allocations like the ring | |
11593 | * on top. This prevents some ugliness at boot time, and | |
11594 | * can even allow for smooth boot transitions if the BIOS | |
11595 | * fb is large enough for the active pipe configuration. | |
11596 | */ | |
11597 | if (dev_priv->display.get_plane_config) { | |
11598 | dev_priv->display.get_plane_config(crtc, | |
11599 | &crtc->plane_config); | |
11600 | /* | |
11601 | * If the fb is shared between multiple heads, we'll | |
11602 | * just get the first one. | |
11603 | */ | |
484b41dd | 11604 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 11605 | } |
46f297fb | 11606 | } |
2c7111db CW |
11607 | } |
11608 | ||
24929352 DV |
11609 | static void |
11610 | intel_connector_break_all_links(struct intel_connector *connector) | |
11611 | { | |
11612 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11613 | connector->base.encoder = NULL; | |
11614 | connector->encoder->connectors_active = false; | |
11615 | connector->encoder->base.crtc = NULL; | |
11616 | } | |
11617 | ||
7fad798e DV |
11618 | static void intel_enable_pipe_a(struct drm_device *dev) |
11619 | { | |
11620 | struct intel_connector *connector; | |
11621 | struct drm_connector *crt = NULL; | |
11622 | struct intel_load_detect_pipe load_detect_temp; | |
11623 | ||
11624 | /* We can't just switch on the pipe A, we need to set things up with a | |
11625 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11626 | * by enabling the load detect pipe once. */ | |
11627 | list_for_each_entry(connector, | |
11628 | &dev->mode_config.connector_list, | |
11629 | base.head) { | |
11630 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11631 | crt = &connector->base; | |
11632 | break; | |
11633 | } | |
11634 | } | |
11635 | ||
11636 | if (!crt) | |
11637 | return; | |
11638 | ||
11639 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11640 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11641 | ||
652c393a | 11642 | |
7fad798e DV |
11643 | } |
11644 | ||
fa555837 DV |
11645 | static bool |
11646 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11647 | { | |
7eb552ae BW |
11648 | struct drm_device *dev = crtc->base.dev; |
11649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11650 | u32 reg, val; |
11651 | ||
7eb552ae | 11652 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11653 | return true; |
11654 | ||
11655 | reg = DSPCNTR(!crtc->plane); | |
11656 | val = I915_READ(reg); | |
11657 | ||
11658 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11659 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11660 | return false; | |
11661 | ||
11662 | return true; | |
11663 | } | |
11664 | ||
24929352 DV |
11665 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11666 | { | |
11667 | struct drm_device *dev = crtc->base.dev; | |
11668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11669 | u32 reg; |
24929352 | 11670 | |
24929352 | 11671 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11672 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11673 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11674 | ||
11675 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
11676 | * disable the crtc (and hence change the state) if it is wrong. Note |
11677 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11678 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11679 | struct intel_connector *connector; |
11680 | bool plane; | |
11681 | ||
24929352 DV |
11682 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11683 | crtc->base.base.id); | |
11684 | ||
11685 | /* Pipe has the wrong plane attached and the plane is active. | |
11686 | * Temporarily change the plane mapping and disable everything | |
11687 | * ... */ | |
11688 | plane = crtc->plane; | |
11689 | crtc->plane = !plane; | |
11690 | dev_priv->display.crtc_disable(&crtc->base); | |
11691 | crtc->plane = plane; | |
11692 | ||
11693 | /* ... and break all links. */ | |
11694 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11695 | base.head) { | |
11696 | if (connector->encoder->base.crtc != &crtc->base) | |
11697 | continue; | |
11698 | ||
11699 | intel_connector_break_all_links(connector); | |
11700 | } | |
11701 | ||
11702 | WARN_ON(crtc->active); | |
11703 | crtc->base.enabled = false; | |
11704 | } | |
24929352 | 11705 | |
7fad798e DV |
11706 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11707 | crtc->pipe == PIPE_A && !crtc->active) { | |
11708 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11709 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11710 | * call below we restore the pipe to the right state, but leave | |
11711 | * the required bits on. */ | |
11712 | intel_enable_pipe_a(dev); | |
11713 | } | |
11714 | ||
24929352 DV |
11715 | /* Adjust the state of the output pipe according to whether we |
11716 | * have active connectors/encoders. */ | |
11717 | intel_crtc_update_dpms(&crtc->base); | |
11718 | ||
11719 | if (crtc->active != crtc->base.enabled) { | |
11720 | struct intel_encoder *encoder; | |
11721 | ||
11722 | /* This can happen either due to bugs in the get_hw_state | |
11723 | * functions or because the pipe is force-enabled due to the | |
11724 | * pipe A quirk. */ | |
11725 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11726 | crtc->base.base.id, | |
11727 | crtc->base.enabled ? "enabled" : "disabled", | |
11728 | crtc->active ? "enabled" : "disabled"); | |
11729 | ||
11730 | crtc->base.enabled = crtc->active; | |
11731 | ||
11732 | /* Because we only establish the connector -> encoder -> | |
11733 | * crtc links if something is active, this means the | |
11734 | * crtc is now deactivated. Break the links. connector | |
11735 | * -> encoder links are only establish when things are | |
11736 | * actually up, hence no need to break them. */ | |
11737 | WARN_ON(crtc->active); | |
11738 | ||
11739 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11740 | WARN_ON(encoder->connectors_active); | |
11741 | encoder->base.crtc = NULL; | |
11742 | } | |
11743 | } | |
4cc31489 DV |
11744 | if (crtc->active) { |
11745 | /* | |
11746 | * We start out with underrun reporting disabled to avoid races. | |
11747 | * For correct bookkeeping mark this on active crtcs. | |
11748 | * | |
11749 | * No protection against concurrent access is required - at | |
11750 | * worst a fifo underrun happens which also sets this to false. | |
11751 | */ | |
11752 | crtc->cpu_fifo_underrun_disabled = true; | |
11753 | crtc->pch_fifo_underrun_disabled = true; | |
11754 | } | |
24929352 DV |
11755 | } |
11756 | ||
11757 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11758 | { | |
11759 | struct intel_connector *connector; | |
11760 | struct drm_device *dev = encoder->base.dev; | |
11761 | ||
11762 | /* We need to check both for a crtc link (meaning that the | |
11763 | * encoder is active and trying to read from a pipe) and the | |
11764 | * pipe itself being active. */ | |
11765 | bool has_active_crtc = encoder->base.crtc && | |
11766 | to_intel_crtc(encoder->base.crtc)->active; | |
11767 | ||
11768 | if (encoder->connectors_active && !has_active_crtc) { | |
11769 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11770 | encoder->base.base.id, | |
11771 | drm_get_encoder_name(&encoder->base)); | |
11772 | ||
11773 | /* Connector is active, but has no active pipe. This is | |
11774 | * fallout from our resume register restoring. Disable | |
11775 | * the encoder manually again. */ | |
11776 | if (encoder->base.crtc) { | |
11777 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11778 | encoder->base.base.id, | |
11779 | drm_get_encoder_name(&encoder->base)); | |
11780 | encoder->disable(encoder); | |
11781 | } | |
11782 | ||
11783 | /* Inconsistent output/port/pipe state happens presumably due to | |
11784 | * a bug in one of the get_hw_state functions. Or someplace else | |
11785 | * in our code, like the register restore mess on resume. Clamp | |
11786 | * things to off as a safer default. */ | |
11787 | list_for_each_entry(connector, | |
11788 | &dev->mode_config.connector_list, | |
11789 | base.head) { | |
11790 | if (connector->encoder != encoder) | |
11791 | continue; | |
11792 | ||
11793 | intel_connector_break_all_links(connector); | |
11794 | } | |
11795 | } | |
11796 | /* Enabled encoders without active connectors will be fixed in | |
11797 | * the crtc fixup. */ | |
11798 | } | |
11799 | ||
04098753 | 11800 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
11801 | { |
11802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11803 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11804 | |
04098753 ID |
11805 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
11806 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
11807 | i915_disable_vga(dev); | |
11808 | } | |
11809 | } | |
11810 | ||
11811 | void i915_redisable_vga(struct drm_device *dev) | |
11812 | { | |
11813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11814 | ||
8dc8a27c PZ |
11815 | /* This function can be called both from intel_modeset_setup_hw_state or |
11816 | * at a very early point in our resume sequence, where the power well | |
11817 | * structures are not yet restored. Since this function is at a very | |
11818 | * paranoid "someone might have enabled VGA while we were not looking" | |
11819 | * level, just check if the power well is enabled instead of trying to | |
11820 | * follow the "don't touch the power well if we don't need it" policy | |
11821 | * the rest of the driver uses. */ | |
04098753 | 11822 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
11823 | return; |
11824 | ||
04098753 | 11825 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
11826 | } |
11827 | ||
98ec7739 VS |
11828 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
11829 | { | |
11830 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
11831 | ||
11832 | if (!crtc->active) | |
11833 | return false; | |
11834 | ||
11835 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
11836 | } | |
11837 | ||
30e984df | 11838 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11839 | { |
11840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11841 | enum pipe pipe; | |
24929352 DV |
11842 | struct intel_crtc *crtc; |
11843 | struct intel_encoder *encoder; | |
11844 | struct intel_connector *connector; | |
5358901f | 11845 | int i; |
24929352 | 11846 | |
d3fcc808 | 11847 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 11848 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11849 | |
9953599b DV |
11850 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
11851 | ||
0e8ffe1b DV |
11852 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11853 | &crtc->config); | |
24929352 DV |
11854 | |
11855 | crtc->base.enabled = crtc->active; | |
98ec7739 | 11856 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
11857 | |
11858 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11859 | crtc->base.base.id, | |
11860 | crtc->active ? "enabled" : "disabled"); | |
11861 | } | |
11862 | ||
5358901f | 11863 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11864 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11865 | intel_ddi_setup_hw_pll_state(dev); |
11866 | ||
5358901f DV |
11867 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11868 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11869 | ||
11870 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11871 | pll->active = 0; | |
d3fcc808 | 11872 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
11873 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
11874 | pll->active++; | |
11875 | } | |
11876 | pll->refcount = pll->active; | |
11877 | ||
35c95375 DV |
11878 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11879 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11880 | } |
11881 | ||
24929352 DV |
11882 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11883 | base.head) { | |
11884 | pipe = 0; | |
11885 | ||
11886 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11887 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11888 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11889 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11890 | } else { |
11891 | encoder->base.crtc = NULL; | |
11892 | } | |
11893 | ||
11894 | encoder->connectors_active = false; | |
6f2bcceb | 11895 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11896 | encoder->base.base.id, |
11897 | drm_get_encoder_name(&encoder->base), | |
11898 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11899 | pipe_name(pipe)); |
24929352 DV |
11900 | } |
11901 | ||
11902 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11903 | base.head) { | |
11904 | if (connector->get_hw_state(connector)) { | |
11905 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11906 | connector->encoder->connectors_active = true; | |
11907 | connector->base.encoder = &connector->encoder->base; | |
11908 | } else { | |
11909 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11910 | connector->base.encoder = NULL; | |
11911 | } | |
11912 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11913 | connector->base.base.id, | |
11914 | drm_get_connector_name(&connector->base), | |
11915 | connector->base.encoder ? "enabled" : "disabled"); | |
11916 | } | |
30e984df DV |
11917 | } |
11918 | ||
11919 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11920 | * and i915 state tracking structures. */ | |
11921 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11922 | bool force_restore) | |
11923 | { | |
11924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11925 | enum pipe pipe; | |
30e984df DV |
11926 | struct intel_crtc *crtc; |
11927 | struct intel_encoder *encoder; | |
35c95375 | 11928 | int i; |
30e984df DV |
11929 | |
11930 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11931 | |
babea61d JB |
11932 | /* |
11933 | * Now that we have the config, copy it to each CRTC struct | |
11934 | * Note that this could go away if we move to using crtc_config | |
11935 | * checking everywhere. | |
11936 | */ | |
d3fcc808 | 11937 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 11938 | if (crtc->active && i915.fastboot) { |
f6a83288 | 11939 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
11940 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
11941 | crtc->base.base.id); | |
11942 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11943 | } | |
11944 | } | |
11945 | ||
24929352 DV |
11946 | /* HW state is read out, now we need to sanitize this mess. */ |
11947 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11948 | base.head) { | |
11949 | intel_sanitize_encoder(encoder); | |
11950 | } | |
11951 | ||
11952 | for_each_pipe(pipe) { | |
11953 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11954 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11955 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11956 | } |
9a935856 | 11957 | |
35c95375 DV |
11958 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11959 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11960 | ||
11961 | if (!pll->on || pll->active) | |
11962 | continue; | |
11963 | ||
11964 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11965 | ||
11966 | pll->disable(dev_priv, pll); | |
11967 | pll->on = false; | |
11968 | } | |
11969 | ||
96f90c54 | 11970 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
11971 | ilk_wm_get_hw_state(dev); |
11972 | ||
45e2b5f6 | 11973 | if (force_restore) { |
7d0bc1ea VS |
11974 | i915_redisable_vga(dev); |
11975 | ||
f30da187 DV |
11976 | /* |
11977 | * We need to use raw interfaces for restoring state to avoid | |
11978 | * checking (bogus) intermediate states. | |
11979 | */ | |
45e2b5f6 | 11980 | for_each_pipe(pipe) { |
b5644d05 JB |
11981 | struct drm_crtc *crtc = |
11982 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11983 | |
11984 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 11985 | crtc->primary->fb); |
45e2b5f6 DV |
11986 | } |
11987 | } else { | |
11988 | intel_modeset_update_staged_output_state(dev); | |
11989 | } | |
8af6cf88 DV |
11990 | |
11991 | intel_modeset_check_state(dev); | |
2c7111db CW |
11992 | } |
11993 | ||
11994 | void intel_modeset_gem_init(struct drm_device *dev) | |
11995 | { | |
484b41dd JB |
11996 | struct drm_crtc *c; |
11997 | struct intel_framebuffer *fb; | |
11998 | ||
ae48434c ID |
11999 | mutex_lock(&dev->struct_mutex); |
12000 | intel_init_gt_powersave(dev); | |
12001 | mutex_unlock(&dev->struct_mutex); | |
12002 | ||
1833b134 | 12003 | intel_modeset_init_hw(dev); |
02e792fb DV |
12004 | |
12005 | intel_setup_overlay(dev); | |
484b41dd JB |
12006 | |
12007 | /* | |
12008 | * Make sure any fbs we allocated at startup are properly | |
12009 | * pinned & fenced. When we do the allocation it's too early | |
12010 | * for this. | |
12011 | */ | |
12012 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 12013 | for_each_crtc(dev, c) { |
66e514c1 | 12014 | if (!c->primary->fb) |
484b41dd JB |
12015 | continue; |
12016 | ||
66e514c1 | 12017 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd JB |
12018 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
12019 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
12020 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
12021 | drm_framebuffer_unreference(c->primary->fb); |
12022 | c->primary->fb = NULL; | |
484b41dd JB |
12023 | } |
12024 | } | |
12025 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12026 | } |
12027 | ||
4932e2c3 ID |
12028 | void intel_connector_unregister(struct intel_connector *intel_connector) |
12029 | { | |
12030 | struct drm_connector *connector = &intel_connector->base; | |
12031 | ||
12032 | intel_panel_destroy_backlight(connector); | |
12033 | drm_sysfs_connector_remove(connector); | |
12034 | } | |
12035 | ||
79e53945 JB |
12036 | void intel_modeset_cleanup(struct drm_device *dev) |
12037 | { | |
652c393a JB |
12038 | struct drm_i915_private *dev_priv = dev->dev_private; |
12039 | struct drm_crtc *crtc; | |
d9255d57 | 12040 | struct drm_connector *connector; |
652c393a | 12041 | |
fd0c0642 DV |
12042 | /* |
12043 | * Interrupts and polling as the first thing to avoid creating havoc. | |
12044 | * Too much stuff here (turning of rps, connectors, ...) would | |
12045 | * experience fancy races otherwise. | |
12046 | */ | |
12047 | drm_irq_uninstall(dev); | |
12048 | cancel_work_sync(&dev_priv->hotplug_work); | |
12049 | /* | |
12050 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
12051 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
12052 | */ | |
f87ea761 | 12053 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 12054 | |
652c393a JB |
12055 | mutex_lock(&dev->struct_mutex); |
12056 | ||
723bfd70 JB |
12057 | intel_unregister_dsm_handler(); |
12058 | ||
70e1e0ec | 12059 | for_each_crtc(dev, crtc) { |
652c393a | 12060 | /* Skip inactive CRTCs */ |
f4510a27 | 12061 | if (!crtc->primary->fb) |
652c393a JB |
12062 | continue; |
12063 | ||
3dec0095 | 12064 | intel_increase_pllclock(crtc); |
652c393a JB |
12065 | } |
12066 | ||
973d04f9 | 12067 | intel_disable_fbc(dev); |
e70236a8 | 12068 | |
8090c6b9 | 12069 | intel_disable_gt_powersave(dev); |
0cdab21f | 12070 | |
930ebb46 DV |
12071 | ironlake_teardown_rc6(dev); |
12072 | ||
69341a5e KH |
12073 | mutex_unlock(&dev->struct_mutex); |
12074 | ||
1630fe75 CW |
12075 | /* flush any delayed tasks or pending work */ |
12076 | flush_scheduled_work(); | |
12077 | ||
db31af1d JN |
12078 | /* destroy the backlight and sysfs files before encoders/connectors */ |
12079 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
12080 | struct intel_connector *intel_connector; |
12081 | ||
12082 | intel_connector = to_intel_connector(connector); | |
12083 | intel_connector->unregister(intel_connector); | |
db31af1d | 12084 | } |
d9255d57 | 12085 | |
79e53945 | 12086 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
12087 | |
12088 | intel_cleanup_overlay(dev); | |
ae48434c ID |
12089 | |
12090 | mutex_lock(&dev->struct_mutex); | |
12091 | intel_cleanup_gt_powersave(dev); | |
12092 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12093 | } |
12094 | ||
f1c79df3 ZW |
12095 | /* |
12096 | * Return which encoder is currently attached for connector. | |
12097 | */ | |
df0e9248 | 12098 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 12099 | { |
df0e9248 CW |
12100 | return &intel_attached_encoder(connector)->base; |
12101 | } | |
f1c79df3 | 12102 | |
df0e9248 CW |
12103 | void intel_connector_attach_encoder(struct intel_connector *connector, |
12104 | struct intel_encoder *encoder) | |
12105 | { | |
12106 | connector->encoder = encoder; | |
12107 | drm_mode_connector_attach_encoder(&connector->base, | |
12108 | &encoder->base); | |
79e53945 | 12109 | } |
28d52043 DA |
12110 | |
12111 | /* | |
12112 | * set vga decode state - true == enable VGA decode | |
12113 | */ | |
12114 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
12115 | { | |
12116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 12117 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
12118 | u16 gmch_ctrl; |
12119 | ||
75fa041d CW |
12120 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
12121 | DRM_ERROR("failed to read control word\n"); | |
12122 | return -EIO; | |
12123 | } | |
12124 | ||
c0cc8a55 CW |
12125 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
12126 | return 0; | |
12127 | ||
28d52043 DA |
12128 | if (state) |
12129 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
12130 | else | |
12131 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
12132 | |
12133 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
12134 | DRM_ERROR("failed to write control word\n"); | |
12135 | return -EIO; | |
12136 | } | |
12137 | ||
28d52043 DA |
12138 | return 0; |
12139 | } | |
c4a1d9e4 | 12140 | |
c4a1d9e4 | 12141 | struct intel_display_error_state { |
ff57f1b0 PZ |
12142 | |
12143 | u32 power_well_driver; | |
12144 | ||
63b66e5b CW |
12145 | int num_transcoders; |
12146 | ||
c4a1d9e4 CW |
12147 | struct intel_cursor_error_state { |
12148 | u32 control; | |
12149 | u32 position; | |
12150 | u32 base; | |
12151 | u32 size; | |
52331309 | 12152 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12153 | |
12154 | struct intel_pipe_error_state { | |
ddf9c536 | 12155 | bool power_domain_on; |
c4a1d9e4 | 12156 | u32 source; |
f301b1e1 | 12157 | u32 stat; |
52331309 | 12158 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12159 | |
12160 | struct intel_plane_error_state { | |
12161 | u32 control; | |
12162 | u32 stride; | |
12163 | u32 size; | |
12164 | u32 pos; | |
12165 | u32 addr; | |
12166 | u32 surface; | |
12167 | u32 tile_offset; | |
52331309 | 12168 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
12169 | |
12170 | struct intel_transcoder_error_state { | |
ddf9c536 | 12171 | bool power_domain_on; |
63b66e5b CW |
12172 | enum transcoder cpu_transcoder; |
12173 | ||
12174 | u32 conf; | |
12175 | ||
12176 | u32 htotal; | |
12177 | u32 hblank; | |
12178 | u32 hsync; | |
12179 | u32 vtotal; | |
12180 | u32 vblank; | |
12181 | u32 vsync; | |
12182 | } transcoder[4]; | |
c4a1d9e4 CW |
12183 | }; |
12184 | ||
12185 | struct intel_display_error_state * | |
12186 | intel_display_capture_error_state(struct drm_device *dev) | |
12187 | { | |
fbee40df | 12188 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 12189 | struct intel_display_error_state *error; |
63b66e5b CW |
12190 | int transcoders[] = { |
12191 | TRANSCODER_A, | |
12192 | TRANSCODER_B, | |
12193 | TRANSCODER_C, | |
12194 | TRANSCODER_EDP, | |
12195 | }; | |
c4a1d9e4 CW |
12196 | int i; |
12197 | ||
63b66e5b CW |
12198 | if (INTEL_INFO(dev)->num_pipes == 0) |
12199 | return NULL; | |
12200 | ||
9d1cb914 | 12201 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
12202 | if (error == NULL) |
12203 | return NULL; | |
12204 | ||
190be112 | 12205 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
12206 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12207 | ||
52331309 | 12208 | for_each_pipe(i) { |
ddf9c536 | 12209 | error->pipe[i].power_domain_on = |
da7e29bd ID |
12210 | intel_display_power_enabled_sw(dev_priv, |
12211 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 12212 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
12213 | continue; |
12214 | ||
a18c4c3d PZ |
12215 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
12216 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
12217 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
12218 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
12219 | } else { | |
12220 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
12221 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
12222 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
12223 | } | |
c4a1d9e4 CW |
12224 | |
12225 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
12226 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 12227 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 12228 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
12229 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
12230 | } | |
ca291363 PZ |
12231 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12232 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
12233 | if (INTEL_INFO(dev)->gen >= 4) { |
12234 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
12235 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
12236 | } | |
12237 | ||
c4a1d9e4 | 12238 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 ID |
12239 | |
12240 | if (!HAS_PCH_SPLIT(dev)) | |
12241 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
63b66e5b CW |
12242 | } |
12243 | ||
12244 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
12245 | if (HAS_DDI(dev_priv->dev)) | |
12246 | error->num_transcoders++; /* Account for eDP. */ | |
12247 | ||
12248 | for (i = 0; i < error->num_transcoders; i++) { | |
12249 | enum transcoder cpu_transcoder = transcoders[i]; | |
12250 | ||
ddf9c536 | 12251 | error->transcoder[i].power_domain_on = |
da7e29bd | 12252 | intel_display_power_enabled_sw(dev_priv, |
38cc1daf | 12253 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 12254 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
12255 | continue; |
12256 | ||
63b66e5b CW |
12257 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
12258 | ||
12259 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
12260 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
12261 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
12262 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
12263 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
12264 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
12265 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
12266 | } |
12267 | ||
12268 | return error; | |
12269 | } | |
12270 | ||
edc3d884 MK |
12271 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
12272 | ||
c4a1d9e4 | 12273 | void |
edc3d884 | 12274 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
12275 | struct drm_device *dev, |
12276 | struct intel_display_error_state *error) | |
12277 | { | |
12278 | int i; | |
12279 | ||
63b66e5b CW |
12280 | if (!error) |
12281 | return; | |
12282 | ||
edc3d884 | 12283 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 12284 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 12285 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 12286 | error->power_well_driver); |
52331309 | 12287 | for_each_pipe(i) { |
edc3d884 | 12288 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
12289 | err_printf(m, " Power: %s\n", |
12290 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 12291 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 12292 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
12293 | |
12294 | err_printf(m, "Plane [%d]:\n", i); | |
12295 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
12296 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 12297 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
12298 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
12299 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 12300 | } |
4b71a570 | 12301 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 12302 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 12303 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
12304 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
12305 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
12306 | } |
12307 | ||
edc3d884 MK |
12308 | err_printf(m, "Cursor [%d]:\n", i); |
12309 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
12310 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
12311 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 12312 | } |
63b66e5b CW |
12313 | |
12314 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 12315 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 12316 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
12317 | err_printf(m, " Power: %s\n", |
12318 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
12319 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
12320 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
12321 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
12322 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
12323 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
12324 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
12325 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
12326 | } | |
c4a1d9e4 | 12327 | } |