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drm/i915: clear up the fdi dotclock semantics for M/N computation
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
1108 int reg, i;
1109 u32 val;
1110 int cur_pipe;
1111
19ec1358 1112 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1113 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1114 reg = DSPCNTR(pipe);
1115 val = I915_READ(reg);
1116 WARN((val & DISPLAY_PLANE_ENABLE),
1117 "plane %c assertion failure, should be disabled but not\n",
1118 plane_name(pipe));
19ec1358 1119 return;
28c05794 1120 }
19ec1358 1121
b24e7179
JB		 1122 /* Need to check both planes against the pipe */
1123 for (i = 0; i < 2; i++) {
1124 reg = DSPCNTR(i);
1125 val = I915_READ(reg);
1126 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1127 DISPPLANE_SEL_PIPE_SHIFT;
1128 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1129 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1130 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1131 }
1132}
1133
19332d7a
JB		 1134static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1135 enum pipe pipe)
1136{
1137 int reg, i;
1138 u32 val;
1139
1140 if (!IS_VALLEYVIEW(dev_priv->dev))
1141 return;
1142
1143 /* Need to check both planes against the pipe */
1144 for (i = 0; i < dev_priv->num_plane; i++) {
1145 reg = SPCNTR(pipe, i);
1146 val = I915_READ(reg);
1147 WARN((val & SP_ENABLE),
06da8da2
VS		 1148 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1150 }
1151}
1152
92f2584a
JB		 1153static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1154{
1155 u32 val;
1156 bool enabled;
1157
9d82aa17
ED		 1158 if (HAS_PCH_LPT(dev_priv->dev)) {
1159 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1160 return;
1161 }
1162
92f2584a
JB		 1163 val = I915_READ(PCH_DREF_CONTROL);
1164 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1165 DREF_SUPERSPREAD_SOURCE_MASK));
1166 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1167}
1168
ab9412ba
DV		 1169static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
92f2584a
JB		 1171{
1172 int reg;
1173 u32 val;
1174 bool enabled;
1175
ab9412ba 1176 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1177 val = I915_READ(reg);
1178 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1179 WARN(enabled,
1180 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1181 pipe_name(pipe));
92f2584a
JB		 1182}
1183
4e634389
KP		 1184static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1186{
1187 if ((val & DP_PORT_EN) == 0)
1188 return false;
1189
1190 if (HAS_PCH_CPT(dev_priv->dev)) {
1191 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1192 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1193 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1194 return false;
1195 } else {
1196 if ((val & DP_PIPE_MASK) != (pipe << 30))
1197 return false;
1198 }
1199 return true;
1200}
1201
1519b995
KP		 1202static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1203 enum pipe pipe, u32 val)
1204{
dc0fa718 1205 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1206 return false;
1207
1208 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1209 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1210 return false;
1211 } else {
dc0fa718 1212 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1213 return false;
1214 }
1215 return true;
1216}
1217
1218static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 val)
1220{
1221 if ((val & LVDS_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1226 return false;
1227 } else {
1228 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1229 return false;
1230 }
1231 return true;
1232}
1233
1234static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 val)
1236{
1237 if ((val & ADPA_DAC_ENABLE) == 0)
1238 return false;
1239 if (HAS_PCH_CPT(dev_priv->dev)) {
1240 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1241 return false;
1242 } else {
1243 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1244 return false;
1245 }
1246 return true;
1247}
1248
291906f1 1249static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1250 enum pipe pipe, int reg, u32 port_sel)
291906f1 1251{
47a05eca 1252 u32 val = I915_READ(reg);
4e634389 1253 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1254 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1255 reg, pipe_name(pipe));
de9a35ab 1256
75c5da27
DV		 1257 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1258 && (val & DP_PIPEB_SELECT),
de9a35ab 1259 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1260}
1261
1262static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, int reg)
1264{
47a05eca 1265 u32 val = I915_READ(reg);
b70ad586 1266 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1267 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1268 reg, pipe_name(pipe));
de9a35ab 1269
dc0fa718 1270 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1271 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1272 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1273}
1274
1275static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1276 enum pipe pipe)
1277{
1278 int reg;
1279 u32 val;
291906f1 1280
f0575e92
KP		 1281 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1282 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1284
1285 reg = PCH_ADPA;
1286 val = I915_READ(reg);
b70ad586 1287 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1288 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1289 pipe_name(pipe));
291906f1
JB		 1290
1291 reg = PCH_LVDS;
1292 val = I915_READ(reg);
b70ad586 1293 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1294 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 pipe_name(pipe));
291906f1 1296
e2debe91
PZ		 1297 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1298 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1300}
1301
63d7bbe9
JB		 1302/**
1303 * intel_enable_pll - enable a PLL
1304 * @dev_priv: i915 private structure
1305 * @pipe: pipe PLL to enable
1306 *
1307 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1308 * make sure the PLL reg is writable first though, since the panel write
1309 * protect mechanism may be enabled.
1310 *
1311 * Note! This is for pre-ILK only.
7434a255
TR		 1312 *
1313 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1314 */
1315static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1316{
1317 int reg;
1318 u32 val;
1319
58c6eaa2
DV		 1320 assert_pipe_disabled(dev_priv, pipe);
1321
63d7bbe9 1322 /* No really, not for ILK+ */
a0c4da24 1323 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1324
1325 /* PLL is protected by panel, make sure we can write it */
1326 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1327 assert_panel_unlocked(dev_priv, pipe);
1328
1329 reg = DPLL(pipe);
1330 val = I915_READ(reg);
1331 val |= DPLL_VCO_ENABLE;
1332
1333 /* We do this three times for luck */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340 I915_WRITE(reg, val);
1341 POSTING_READ(reg);
1342 udelay(150); /* wait for warmup */
1343}
1344
1345/**
1346 * intel_disable_pll - disable a PLL
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe PLL to disable
1349 *
1350 * Disable the PLL for @pipe, making sure the pipe is off first.
1351 *
1352 * Note! This is for pre-ILK only.
1353 */
1354static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1355{
1356 int reg;
1357 u32 val;
1358
1359 /* Don't disable pipe A or pipe A PLLs if needed */
1360 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361 return;
1362
1363 /* Make sure the pipe isn't still relying on us */
1364 assert_pipe_disabled(dev_priv, pipe);
1365
1366 reg = DPLL(pipe);
1367 val = I915_READ(reg);
1368 val &= ~DPLL_VCO_ENABLE;
1369 I915_WRITE(reg, val);
1370 POSTING_READ(reg);
1371}
1372
89b667f8
JB		 1373void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1374{
1375 u32 port_mask;
1376
1377 if (!port)
1378 port_mask = DPLL_PORTB_READY_MASK;
1379 else
1380 port_mask = DPLL_PORTC_READY_MASK;
1381
1382 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1383 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1384 'B' + port, I915_READ(DPLL(0)));
1385}
1386
92f2584a 1387/**
b6b4e185 1388 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1389 * @dev_priv: i915 private structure
1390 * @pipe: pipe PLL to enable
1391 *
1392 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1393 * drives the transcoder clock.
1394 */
b6b4e185 1395static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1396{
ee7b9f93 1397 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1398 struct intel_pch_pll *pll;
92f2584a
JB		 1399 int reg;
1400 u32 val;
1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1404 pll = intel_crtc->pch_pll;
1405 if (pll == NULL)
1406 return;
1407
1408 if (WARN_ON(pll->refcount == 0))
1409 return;
ee7b9f93
JB		 1410
1411 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1412 pll->pll_reg, pll->active, pll->on,
1413 intel_crtc->base.base.id);
92f2584a
JB		 1414
1415 /* PCH refclock must be enabled first */
1416 assert_pch_refclk_enabled(dev_priv);
1417
ee7b9f93 1418 if (pll->active++ && pll->on) {
92b27b08 1419 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1420 return;
1421 }
1422
1423 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1424
1425 reg = pll->pll_reg;
92f2584a
JB		 1426 val = I915_READ(reg);
1427 val |= DPLL_VCO_ENABLE;
1428 I915_WRITE(reg, val);
1429 POSTING_READ(reg);
1430 udelay(200);
ee7b9f93
JB		 1431
1432 pll->on = true;
92f2584a
JB		 1433}
1434
ee7b9f93 1435static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1436{
ee7b9f93
JB		 1437 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1438 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1439 int reg;
ee7b9f93 1440 u32 val;
4c609cb8 1441
92f2584a
JB		 1442 /* PCH only available on ILK+ */
1443 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1444 if (pll == NULL)
1445 return;
92f2584a 1446
48da64a8
CW		 1447 if (WARN_ON(pll->refcount == 0))
1448 return;
7a419866 1449
ee7b9f93
JB		 1450 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1451 pll->pll_reg, pll->active, pll->on,
1452 intel_crtc->base.base.id);
7a419866 1453
48da64a8 1454 if (WARN_ON(pll->active == 0)) {
92b27b08 1455 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1456 return;
1457 }
1458
ee7b9f93 1459 if (--pll->active) {
92b27b08 1460 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1461 return;
ee7b9f93
JB		 1462 }
1463
1464 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1465
1466 /* Make sure transcoder isn't still depending on us */
ab9412ba 1467 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1468
ee7b9f93 1469 reg = pll->pll_reg;
92f2584a
JB		 1470 val = I915_READ(reg);
1471 val &= ~DPLL_VCO_ENABLE;
1472 I915_WRITE(reg, val);
1473 POSTING_READ(reg);
1474 udelay(200);
ee7b9f93
JB		 1475
1476 pll->on = false;
92f2584a
JB		 1477}
1478
b8a4f404
PZ		 1479static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1480 enum pipe pipe)
040484af 1481{
23670b32 1482 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1484 uint32_t reg, val, pipeconf_val;
040484af
JB		 1485
1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv->info->gen < 5);
1488
1489 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1490 assert_pch_pll_enabled(dev_priv,
1491 to_intel_crtc(crtc)->pch_pll,
1492 to_intel_crtc(crtc));
040484af
JB		 1493
1494 /* FDI must be feeding us bits for PCH ports */
1495 assert_fdi_tx_enabled(dev_priv, pipe);
1496 assert_fdi_rx_enabled(dev_priv, pipe);
1497
23670b32
DV		 1498 if (HAS_PCH_CPT(dev)) {
1499 /* Workaround: Set the timing override bit before enabling the
1500 * pch transcoder. */
1501 reg = TRANS_CHICKEN2(pipe);
1502 val = I915_READ(reg);
1503 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1504 I915_WRITE(reg, val);
59c859d6 1505 }
23670b32 1506
ab9412ba 1507 reg = PCH_TRANSCONF(pipe);
040484af 1508 val = I915_READ(reg);
5f7f726d 1509 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1510
1511 if (HAS_PCH_IBX(dev_priv->dev)) {
1512 /*
1513 * make the BPC in transcoder be consistent with
1514 * that in pipeconf reg.
1515 */
dfd07d72
DV		 1516 val &= ~PIPECONF_BPC_MASK;
1517 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1518 }
5f7f726d
PZ		 1519
1520 val &= ~TRANS_INTERLACE_MASK;
1521 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1522 if (HAS_PCH_IBX(dev_priv->dev) &&
1523 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1524 val |= TRANS_LEGACY_INTERLACED_ILK;
1525 else
1526 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1527 else
1528 val |= TRANS_PROGRESSIVE;
1529
040484af
JB		 1530 I915_WRITE(reg, val | TRANS_ENABLE);
1531 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1532 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1533}
1534
8fb033d7 1535static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1536 enum transcoder cpu_transcoder)
040484af 1537{
8fb033d7 1538 u32 val, pipeconf_val;
8fb033d7
PZ		 1539
1540 /* PCH only available on ILK+ */
1541 BUG_ON(dev_priv->info->gen < 5);
1542
8fb033d7 1543 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1544 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1545 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1546
223a6fdf
PZ		 1547 /* Workaround: set timing override bit. */
1548 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1549 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1550 I915_WRITE(_TRANSA_CHICKEN2, val);
1551
25f3ef11 1552 val = TRANS_ENABLE;
937bb610 1553 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1554
9a76b1c6
PZ		 1555 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1556 PIPECONF_INTERLACED_ILK)
a35f2679 1557 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1558 else
1559 val |= TRANS_PROGRESSIVE;
1560
ab9412ba
DV		 1561 I915_WRITE(LPT_TRANSCONF, val);
1562 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1563 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1564}
1565
b8a4f404
PZ		 1566static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
040484af 1568{
23670b32
DV		 1569 struct drm_device *dev = dev_priv->dev;
1570 uint32_t reg, val;
040484af
JB		 1571
1572 /* FDI relies on the transcoder */
1573 assert_fdi_tx_disabled(dev_priv, pipe);
1574 assert_fdi_rx_disabled(dev_priv, pipe);
1575
291906f1
JB		 1576 /* Ports must be off as well */
1577 assert_pch_ports_disabled(dev_priv, pipe);
1578
ab9412ba 1579 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1580 val = I915_READ(reg);
1581 val &= ~TRANS_ENABLE;
1582 I915_WRITE(reg, val);
1583 /* wait for PCH transcoder off, transcoder state */
1584 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1585 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1586
1587 if (!HAS_PCH_IBX(dev)) {
1588 /* Workaround: Clear the timing override chicken bit again. */
1589 reg = TRANS_CHICKEN2(pipe);
1590 val = I915_READ(reg);
1591 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1592 I915_WRITE(reg, val);
1593 }
040484af
JB		 1594}
1595
ab4d966c 1596static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1597{
8fb033d7
PZ		 1598 u32 val;
1599
ab9412ba 1600 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1601 val &= ~TRANS_ENABLE;
ab9412ba 1602 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1603 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1604 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1605 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1606
1607 /* Workaround: clear timing override bit. */
1608 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1609 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1610 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1611}
1612
b24e7179 1613/**
309cfea8 1614 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1615 * @dev_priv: i915 private structure
1616 * @pipe: pipe to enable
040484af 1617 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1618 *
1619 * Enable @pipe, making sure that various hardware specific requirements
1620 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1621 *
1622 * @pipe should be %PIPE_A or %PIPE_B.
1623 *
1624 * Will wait until the pipe is actually running (i.e. first vblank) before
1625 * returning.
1626 */
040484af
JB		 1627static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1628 bool pch_port)
b24e7179 1629{
702e7a56
PZ		 1630 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1631 pipe);
1a240d4d 1632 enum pipe pch_transcoder;
b24e7179
JB		 1633 int reg;
1634 u32 val;
1635
58c6eaa2
DV		 1636 assert_planes_disabled(dev_priv, pipe);
1637 assert_sprites_disabled(dev_priv, pipe);
1638
681e5811 1639 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1640 pch_transcoder = TRANSCODER_A;
1641 else
1642 pch_transcoder = pipe;
1643
b24e7179
JB		 1644 /*
1645 * A pipe without a PLL won't actually be able to drive bits from
1646 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1647 * need the check.
1648 */
1649 if (!HAS_PCH_SPLIT(dev_priv->dev))
1650 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1651 else {
1652 if (pch_port) {
1653 /* if driving the PCH, we need FDI enabled */
cc391bbb 1654 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1655 assert_fdi_tx_pll_enabled(dev_priv,
1656 (enum pipe) cpu_transcoder);
040484af
JB		 1657 }
1658 /* FIXME: assert CPU port conditions for SNB+ */
1659 }
b24e7179 1660
702e7a56 1661 reg = PIPECONF(cpu_transcoder);
b24e7179 1662 val = I915_READ(reg);
00d70b15
CW		 1663 if (val & PIPECONF_ENABLE)
1664 return;
1665
1666 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1667 intel_wait_for_vblank(dev_priv->dev, pipe);
1668}
1669
1670/**
309cfea8 1671 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1672 * @dev_priv: i915 private structure
1673 * @pipe: pipe to disable
1674 *
1675 * Disable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe has shut down before returning.
1681 */
1682static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1683 enum pipe pipe)
1684{
702e7a56
PZ		 1685 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1686 pipe);
b24e7179
JB		 1687 int reg;
1688 u32 val;
1689
1690 /*
1691 * Make sure planes won't keep trying to pump pixels to us,
1692 * or we might hang the display.
1693 */
1694 assert_planes_disabled(dev_priv, pipe);
19332d7a 1695 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1696
1697 /* Don't disable pipe A or pipe A PLLs if needed */
1698 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699 return;
1700
702e7a56 1701 reg = PIPECONF(cpu_transcoder);
b24e7179 1702 val = I915_READ(reg);
00d70b15
CW		 1703 if ((val & PIPECONF_ENABLE) == 0)
1704 return;
1705
1706 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1707 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1708}
1709
d74362c9
KP		 1710/*
1711 * Plane regs are double buffered, going from enabled->disabled needs a
1712 * trigger in order to latch. The display address reg provides this.
1713 */
6f1d69b0 1714void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1715 enum plane plane)
1716{
14f86147
DL		 1717 if (dev_priv->info->gen >= 4)
1718 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1719 else
1720 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1721}
1722
b24e7179
JB		 1723/**
1724 * intel_enable_plane - enable a display plane on a given pipe
1725 * @dev_priv: i915 private structure
1726 * @plane: plane to enable
1727 * @pipe: pipe being fed
1728 *
1729 * Enable @plane on @pipe, making sure that @pipe is running first.
1730 */
1731static void intel_enable_plane(struct drm_i915_private *dev_priv,
1732 enum plane plane, enum pipe pipe)
1733{
1734 int reg;
1735 u32 val;
1736
1737 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1738 assert_pipe_enabled(dev_priv, pipe);
1739
1740 reg = DSPCNTR(plane);
1741 val = I915_READ(reg);
00d70b15
CW		 1742 if (val & DISPLAY_PLANE_ENABLE)
1743 return;
1744
1745 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1746 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1747 intel_wait_for_vblank(dev_priv->dev, pipe);
1748}
1749
b24e7179
JB		 1750/**
1751 * intel_disable_plane - disable a display plane
1752 * @dev_priv: i915 private structure
1753 * @plane: plane to disable
1754 * @pipe: pipe consuming the data
1755 *
1756 * Disable @plane; should be an independent operation.
1757 */
1758static void intel_disable_plane(struct drm_i915_private *dev_priv,
1759 enum plane plane, enum pipe pipe)
1760{
1761 int reg;
1762 u32 val;
1763
1764 reg = DSPCNTR(plane);
1765 val = I915_READ(reg);
00d70b15
CW		 1766 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1767 return;
1768
1769 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1770 intel_flush_display_plane(dev_priv, plane);
1771 intel_wait_for_vblank(dev_priv->dev, pipe);
1772}
1773
693db184
CW		 1774static bool need_vtd_wa(struct drm_device *dev)
1775{
1776#ifdef CONFIG_INTEL_IOMMU
1777 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1778 return true;
1779#endif
1780 return false;
1781}
1782
127bd2ac 1783int
48b956c5 1784intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1785 struct drm_i915_gem_object *obj,
919926ae 1786 struct intel_ring_buffer *pipelined)
6b95a207 1787{
ce453d81 1788 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1789 u32 alignment;
1790 int ret;
1791
05394f39 1792 switch (obj->tiling_mode) {
6b95a207 1793 case I915_TILING_NONE:
534843da
CW		 1794 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1795 alignment = 128 * 1024;
a6c45cf0 1796 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1797 alignment = 4 * 1024;
1798 else
1799 alignment = 64 * 1024;
6b95a207
KH		 1800 break;
1801 case I915_TILING_X:
1802 /* pin() will align the object as required by fence */
1803 alignment = 0;
1804 break;
1805 case I915_TILING_Y:
8bb6e959
DV		 1806 /* Despite that we check this in framebuffer_init userspace can
1807 * screw us over and change the tiling after the fact. Only
1808 * pinned buffers can't change their tiling. */
1809 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1810 return -EINVAL;
1811 default:
1812 BUG();
1813 }
1814
693db184
CW		 1815 /* Note that the w/a also requires 64 PTE of padding following the
1816 * bo. We currently fill all unused PTE with the shadow page and so
1817 * we should always have valid PTE following the scanout preventing
1818 * the VT-d warning.
1819 */
1820 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1821 alignment = 256 * 1024;
1822
ce453d81 1823 dev_priv->mm.interruptible = false;
2da3b9b9 1824 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1825 if (ret)
ce453d81 1826 goto err_interruptible;
6b95a207
KH		 1827
1828 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1829 * fence, whereas 965+ only requires a fence if using
1830 * framebuffer compression. For simplicity, we always install
1831 * a fence as the cost is not that onerous.
1832 */
06d98131 1833 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1834 if (ret)
1835 goto err_unpin;
1690e1eb 1836
9a5a53b3 1837 i915_gem_object_pin_fence(obj);
6b95a207 1838
ce453d81 1839 dev_priv->mm.interruptible = true;
6b95a207 1840 return 0;
48b956c5
CW		 1841
1842err_unpin:
1843 i915_gem_object_unpin(obj);
ce453d81
CW		 1844err_interruptible:
1845 dev_priv->mm.interruptible = true;
48b956c5 1846 return ret;
6b95a207
KH		 1847}
1848
1690e1eb
CW		 1849void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1850{
1851 i915_gem_object_unpin_fence(obj);
1852 i915_gem_object_unpin(obj);
1853}
1854
c2c75131
DV		 1855/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1856 * is assumed to be a power-of-two. */
bc752862
CW		 1857unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1858 unsigned int tiling_mode,
1859 unsigned int cpp,
1860 unsigned int pitch)
c2c75131 1861{
bc752862
CW		 1862 if (tiling_mode != I915_TILING_NONE) {
1863 unsigned int tile_rows, tiles;
c2c75131 1864
bc752862
CW		 1865 tile_rows = *y / 8;
1866 *y %= 8;
c2c75131 1867
bc752862
CW		 1868 tiles = *x / (512/cpp);
1869 *x %= 512/cpp;
1870
1871 return tile_rows * pitch * 8 + tiles * 4096;
1872 } else {
1873 unsigned int offset;
1874
1875 offset = *y * pitch + *x * cpp;
1876 *y = 0;
1877 *x = (offset & 4095) / cpp;
1878 return offset & -4096;
1879 }
c2c75131
DV		 1880}
1881
17638cd6
JB		 1882static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1883 int x, int y)
81255565
JB		 1884{
1885 struct drm_device *dev = crtc->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888 struct intel_framebuffer *intel_fb;
05394f39 1889 struct drm_i915_gem_object *obj;
81255565 1890 int plane = intel_crtc->plane;
e506a0c6 1891 unsigned long linear_offset;
81255565 1892 u32 dspcntr;
5eddb70b 1893 u32 reg;
81255565
JB		 1894
1895 switch (plane) {
1896 case 0:
1897 case 1:
1898 break;
1899 default:
84f44ce7 1900 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1901 return -EINVAL;
1902 }
1903
1904 intel_fb = to_intel_framebuffer(fb);
1905 obj = intel_fb->obj;
81255565 1906
5eddb70b
CW		 1907 reg = DSPCNTR(plane);
1908 dspcntr = I915_READ(reg);
81255565
JB		 1909 /* Mask out pixel format bits in case we change it */
1910 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1911 switch (fb->pixel_format) {
1912 case DRM_FORMAT_C8:
81255565
JB		 1913 dspcntr |= DISPPLANE_8BPP;
1914 break;
57779d06
VS		 1915 case DRM_FORMAT_XRGB1555:
1916 case DRM_FORMAT_ARGB1555:
1917 dspcntr |= DISPPLANE_BGRX555;
81255565 1918 break;
57779d06
VS		 1919 case DRM_FORMAT_RGB565:
1920 dspcntr |= DISPPLANE_BGRX565;
1921 break;
1922 case DRM_FORMAT_XRGB8888:
1923 case DRM_FORMAT_ARGB8888:
1924 dspcntr |= DISPPLANE_BGRX888;
1925 break;
1926 case DRM_FORMAT_XBGR8888:
1927 case DRM_FORMAT_ABGR8888:
1928 dspcntr |= DISPPLANE_RGBX888;
1929 break;
1930 case DRM_FORMAT_XRGB2101010:
1931 case DRM_FORMAT_ARGB2101010:
1932 dspcntr |= DISPPLANE_BGRX101010;
1933 break;
1934 case DRM_FORMAT_XBGR2101010:
1935 case DRM_FORMAT_ABGR2101010:
1936 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1937 break;
1938 default:
baba133a 1939 BUG();
81255565 1940 }
57779d06 1941
a6c45cf0 1942 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1943 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1944 dspcntr |= DISPPLANE_TILED;
1945 else
1946 dspcntr &= ~DISPPLANE_TILED;
1947 }
1948
5eddb70b 1949 I915_WRITE(reg, dspcntr);
81255565 1950
e506a0c6 1951 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1952
c2c75131
DV		 1953 if (INTEL_INFO(dev)->gen >= 4) {
1954 intel_crtc->dspaddr_offset =
bc752862
CW		 1955 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1956 fb->bits_per_pixel / 8,
1957 fb->pitches[0]);
c2c75131
DV		 1958 linear_offset -= intel_crtc->dspaddr_offset;
1959 } else {
e506a0c6 1960 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1961 }
e506a0c6
DV		 1962
1963 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1964 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1965 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1966 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1967 I915_MODIFY_DISPBASE(DSPSURF(plane),
1968 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1969 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1970 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1971 } else
e506a0c6 1972 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1973 POSTING_READ(reg);
81255565 1974
17638cd6
JB		 1975 return 0;
1976}
1977
1978static int ironlake_update_plane(struct drm_crtc *crtc,
1979 struct drm_framebuffer *fb, int x, int y)
1980{
1981 struct drm_device *dev = crtc->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984 struct intel_framebuffer *intel_fb;
1985 struct drm_i915_gem_object *obj;
1986 int plane = intel_crtc->plane;
e506a0c6 1987 unsigned long linear_offset;
17638cd6
JB		 1988 u32 dspcntr;
1989 u32 reg;
1990
1991 switch (plane) {
1992 case 0:
1993 case 1:
27f8227b 1994 case 2:
17638cd6
JB		 1995 break;
1996 default:
84f44ce7 1997 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1998 return -EINVAL;
1999 }
2000
2001 intel_fb = to_intel_framebuffer(fb);
2002 obj = intel_fb->obj;
2003
2004 reg = DSPCNTR(plane);
2005 dspcntr = I915_READ(reg);
2006 /* Mask out pixel format bits in case we change it */
2007 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2008 switch (fb->pixel_format) {
2009 case DRM_FORMAT_C8:
17638cd6
JB		 2010 dspcntr |= DISPPLANE_8BPP;
2011 break;
57779d06
VS		 2012 case DRM_FORMAT_RGB565:
2013 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2014 break;
57779d06
VS		 2015 case DRM_FORMAT_XRGB8888:
2016 case DRM_FORMAT_ARGB8888:
2017 dspcntr |= DISPPLANE_BGRX888;
2018 break;
2019 case DRM_FORMAT_XBGR8888:
2020 case DRM_FORMAT_ABGR8888:
2021 dspcntr |= DISPPLANE_RGBX888;
2022 break;
2023 case DRM_FORMAT_XRGB2101010:
2024 case DRM_FORMAT_ARGB2101010:
2025 dspcntr |= DISPPLANE_BGRX101010;
2026 break;
2027 case DRM_FORMAT_XBGR2101010:
2028 case DRM_FORMAT_ABGR2101010:
2029 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2030 break;
2031 default:
baba133a 2032 BUG();
17638cd6
JB		 2033 }
2034
2035 if (obj->tiling_mode != I915_TILING_NONE)
2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039
2040 /* must disable */
2041 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2042
2043 I915_WRITE(reg, dspcntr);
2044
e506a0c6 2045 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2046 intel_crtc->dspaddr_offset =
bc752862
CW		 2047 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2048 fb->bits_per_pixel / 8,
2049 fb->pitches[0]);
c2c75131 2050 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2051
e506a0c6
DV		 2052 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2053 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2054 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2055 I915_MODIFY_DISPBASE(DSPSURF(plane),
2056 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2057 if (IS_HASWELL(dev)) {
2058 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2059 } else {
2060 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2061 I915_WRITE(DSPLINOFF(plane), linear_offset);
2062 }
17638cd6
JB		 2063 POSTING_READ(reg);
2064
2065 return 0;
2066}
2067
2068/* Assume fb object is pinned & idle & fenced and just update base pointers */
2069static int
2070intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2071 int x, int y, enum mode_set_atomic state)
2072{
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2075
6b8e6ed0
CW		 2076 if (dev_priv->display.disable_fbc)
2077 dev_priv->display.disable_fbc(dev);
3dec0095 2078 intel_increase_pllclock(crtc);
81255565 2079
6b8e6ed0 2080 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2081}
2082
96a02917
VS		 2083void intel_display_handle_reset(struct drm_device *dev)
2084{
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct drm_crtc *crtc;
2087
2088 /*
2089 * Flips in the rings have been nuked by the reset,
2090 * so complete all pending flips so that user space
2091 * will get its events and not get stuck.
2092 *
2093 * Also update the base address of all primary
2094 * planes to the the last fb to make sure we're
2095 * showing the correct fb after a reset.
2096 *
2097 * Need to make two loops over the crtcs so that we
2098 * don't try to grab a crtc mutex before the
2099 * pending_flip_queue really got woken up.
2100 */
2101
2102 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104 enum plane plane = intel_crtc->plane;
2105
2106 intel_prepare_page_flip(dev, plane);
2107 intel_finish_page_flip_plane(dev, plane);
2108 }
2109
2110 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112
2113 mutex_lock(&crtc->mutex);
2114 if (intel_crtc->active)
2115 dev_priv->display.update_plane(crtc, crtc->fb,
2116 crtc->x, crtc->y);
2117 mutex_unlock(&crtc->mutex);
2118 }
2119}
2120
14667a4b
CW		 2121static int
2122intel_finish_fb(struct drm_framebuffer *old_fb)
2123{
2124 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2126 bool was_interruptible = dev_priv->mm.interruptible;
2127 int ret;
2128
14667a4b
CW		 2129 /* Big Hammer, we also need to ensure that any pending
2130 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2131 * current scanout is retired before unpinning the old
2132 * framebuffer.
2133 *
2134 * This should only fail upon a hung GPU, in which case we
2135 * can safely continue.
2136 */
2137 dev_priv->mm.interruptible = false;
2138 ret = i915_gem_object_finish_gpu(obj);
2139 dev_priv->mm.interruptible = was_interruptible;
2140
2141 return ret;
2142}
2143
198598d0
VS		 2144static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2145{
2146 struct drm_device *dev = crtc->dev;
2147 struct drm_i915_master_private *master_priv;
2148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150 if (!dev->primary->master)
2151 return;
2152
2153 master_priv = dev->primary->master->driver_priv;
2154 if (!master_priv->sarea_priv)
2155 return;
2156
2157 switch (intel_crtc->pipe) {
2158 case 0:
2159 master_priv->sarea_priv->pipeA_x = x;
2160 master_priv->sarea_priv->pipeA_y = y;
2161 break;
2162 case 1:
2163 master_priv->sarea_priv->pipeB_x = x;
2164 master_priv->sarea_priv->pipeB_y = y;
2165 break;
2166 default:
2167 break;
2168 }
2169}
2170
5c3b82e2 2171static int
3c4fdcfb 2172intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2173 struct drm_framebuffer *fb)
79e53945
JB		 2174{
2175 struct drm_device *dev = crtc->dev;
6b8e6ed0 2176 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2178 struct drm_framebuffer *old_fb;
5c3b82e2 2179 int ret;
79e53945
JB		 2180
2181 /* no fb bound */
94352cf9 2182 if (!fb) {
a5071c2f 2183 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2184 return 0;
2185 }
2186
7eb552ae 2187 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2188 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2189 plane_name(intel_crtc->plane),
2190 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2191 return -EINVAL;
79e53945
JB		 2192 }
2193
5c3b82e2 2194 mutex_lock(&dev->struct_mutex);
265db958 2195 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2196 to_intel_framebuffer(fb)->obj,
919926ae 2197 NULL);
5c3b82e2
CW		 2198 if (ret != 0) {
2199 mutex_unlock(&dev->struct_mutex);
a5071c2f 2200 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2201 return ret;
2202 }
79e53945 2203
94352cf9 2204 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2205 if (ret) {
94352cf9 2206 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
a5071c2f 2208 DRM_ERROR("failed to update base address\n");
4e6cfefc 2209 return ret;
79e53945 2210 }
3c4fdcfb 2211
94352cf9
DV		 2212 old_fb = crtc->fb;
2213 crtc->fb = fb;
6c4c86f5
DV		 2214 crtc->x = x;
2215 crtc->y = y;
94352cf9 2216
b7f1de28 2217 if (old_fb) {
d7697eea
DV		 2218 if (intel_crtc->active && old_fb != fb)
2219 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2220 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2221 }
652c393a 2222
6b8e6ed0 2223 intel_update_fbc(dev);
5c3b82e2 2224 mutex_unlock(&dev->struct_mutex);
79e53945 2225
198598d0 2226 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2227
2228 return 0;
79e53945
JB		 2229}
2230
5e84e1a4
ZW		 2231static void intel_fdi_normal_train(struct drm_crtc *crtc)
2232{
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236 int pipe = intel_crtc->pipe;
2237 u32 reg, temp;
2238
2239 /* enable normal train */
2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
61e499bf 2242 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2243 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2244 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2245 } else {
2246 temp &= ~FDI_LINK_TRAIN_NONE;
2247 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2248 }
5e84e1a4
ZW		 2249 I915_WRITE(reg, temp);
2250
2251 reg = FDI_RX_CTL(pipe);
2252 temp = I915_READ(reg);
2253 if (HAS_PCH_CPT(dev)) {
2254 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2255 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2256 } else {
2257 temp &= ~FDI_LINK_TRAIN_NONE;
2258 temp |= FDI_LINK_TRAIN_NONE;
2259 }
2260 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2261
2262 /* wait one idle pattern time */
2263 POSTING_READ(reg);
2264 udelay(1000);
357555c0
JB		 2265
2266 /* IVB wants error correction enabled */
2267 if (IS_IVYBRIDGE(dev))
2268 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2269 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2270}
2271
1e833f40
DV		 2272static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2273{
2274 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2275}
2276
01a415fd
DV		 2277static void ivb_modeset_global_resources(struct drm_device *dev)
2278{
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 struct intel_crtc *pipe_B_crtc =
2281 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2282 struct intel_crtc *pipe_C_crtc =
2283 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2284 uint32_t temp;
2285
1e833f40
DV		 2286 /*
2287 * When everything is off disable fdi C so that we could enable fdi B
2288 * with all lanes. Note that we don't care about enabled pipes without
2289 * an enabled pch encoder.
2290 */
2291 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2292 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2293 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2294 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2295
2296 temp = I915_READ(SOUTH_CHICKEN1);
2297 temp &= ~FDI_BC_BIFURCATION_SELECT;
2298 DRM_DEBUG_KMS("disabling fdi C rx\n");
2299 I915_WRITE(SOUTH_CHICKEN1, temp);
2300 }
2301}
2302
8db9d77b
ZW		 2303/* The FDI link training functions for ILK/Ibexpeak. */
2304static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2305{
2306 struct drm_device *dev = crtc->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309 int pipe = intel_crtc->pipe;
0fc932b8 2310 int plane = intel_crtc->plane;
5eddb70b 2311 u32 reg, temp, tries;
8db9d77b 2312
0fc932b8
JB		 2313 /* FDI needs bits from pipe & plane first */
2314 assert_pipe_enabled(dev_priv, pipe);
2315 assert_plane_enabled(dev_priv, plane);
2316
e1a44743
AJ		 2317 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318 for train result */
5eddb70b
CW		 2319 reg = FDI_RX_IMR(pipe);
2320 temp = I915_READ(reg);
e1a44743
AJ		 2321 temp &= ~FDI_RX_SYMBOL_LOCK;
2322 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2323 I915_WRITE(reg, temp);
2324 I915_READ(reg);
e1a44743
AJ		 2325 udelay(150);
2326
8db9d77b 2327 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2328 reg = FDI_TX_CTL(pipe);
2329 temp = I915_READ(reg);
627eb5a3
DV		 2330 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2331 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2332 temp &= ~FDI_LINK_TRAIN_NONE;
2333 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2334 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2335
5eddb70b
CW		 2336 reg = FDI_RX_CTL(pipe);
2337 temp = I915_READ(reg);
8db9d77b
ZW		 2338 temp &= ~FDI_LINK_TRAIN_NONE;
2339 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2340 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2341
2342 POSTING_READ(reg);
8db9d77b
ZW		 2343 udelay(150);
2344
5b2adf89 2345 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2346 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2347 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2348 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2349
5eddb70b 2350 reg = FDI_RX_IIR(pipe);
e1a44743 2351 for (tries = 0; tries < 5; tries++) {
5eddb70b 2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2354
2355 if ((temp & FDI_RX_BIT_LOCK)) {
2356 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2357 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2358 break;
2359 }
8db9d77b 2360 }
e1a44743 2361 if (tries == 5)
5eddb70b 2362 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2363
2364 /* Train 2 */
5eddb70b
CW		 2365 reg = FDI_TX_CTL(pipe);
2366 temp = I915_READ(reg);
8db9d77b
ZW		 2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2369 I915_WRITE(reg, temp);
8db9d77b 2370
5eddb70b
CW		 2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
8db9d77b
ZW		 2373 temp &= ~FDI_LINK_TRAIN_NONE;
2374 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2375 I915_WRITE(reg, temp);
8db9d77b 2376
5eddb70b
CW		 2377 POSTING_READ(reg);
2378 udelay(150);
8db9d77b 2379
5eddb70b 2380 reg = FDI_RX_IIR(pipe);
e1a44743 2381 for (tries = 0; tries < 5; tries++) {
5eddb70b 2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2387 DRM_DEBUG_KMS("FDI train 2 done.\n");
2388 break;
2389 }
8db9d77b 2390 }
e1a44743 2391 if (tries == 5)
5eddb70b 2392 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2393
2394 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2395
8db9d77b
ZW		 2396}
2397
0206e353 2398static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2399 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2400 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2401 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2402 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2403};
2404
2405/* The FDI link training functions for SNB/Cougarpoint. */
2406static void gen6_fdi_link_train(struct drm_crtc *crtc)
2407{
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 int pipe = intel_crtc->pipe;
fa37d39e 2412 u32 reg, temp, i, retry;
8db9d77b 2413
e1a44743
AJ		 2414 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2415 for train result */
5eddb70b
CW		 2416 reg = FDI_RX_IMR(pipe);
2417 temp = I915_READ(reg);
e1a44743
AJ		 2418 temp &= ~FDI_RX_SYMBOL_LOCK;
2419 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2420 I915_WRITE(reg, temp);
2421
2422 POSTING_READ(reg);
e1a44743
AJ		 2423 udelay(150);
2424
8db9d77b 2425 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
627eb5a3
DV		 2428 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2429 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
2432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2433 /* SNB-B */
2434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2436
d74cf324
DV		 2437 I915_WRITE(FDI_RX_MISC(pipe),
2438 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2439
5eddb70b
CW		 2440 reg = FDI_RX_CTL(pipe);
2441 temp = I915_READ(reg);
8db9d77b
ZW		 2442 if (HAS_PCH_CPT(dev)) {
2443 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2445 } else {
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 }
5eddb70b
CW		 2449 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2450
2451 POSTING_READ(reg);
8db9d77b
ZW		 2452 udelay(150);
2453
0206e353 2454 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2455 reg = FDI_TX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2458 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2459 I915_WRITE(reg, temp);
2460
2461 POSTING_READ(reg);
8db9d77b
ZW		 2462 udelay(500);
2463
fa37d39e
SP		 2464 for (retry = 0; retry < 5; retry++) {
2465 reg = FDI_RX_IIR(pipe);
2466 temp = I915_READ(reg);
2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468 if (temp & FDI_RX_BIT_LOCK) {
2469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
2471 break;
2472 }
2473 udelay(50);
8db9d77b 2474 }
fa37d39e
SP		 2475 if (retry < 5)
2476 break;
8db9d77b
ZW		 2477 }
2478 if (i == 4)
5eddb70b 2479 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2480
2481 /* Train 2 */
5eddb70b
CW		 2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_2;
2486 if (IS_GEN6(dev)) {
2487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488 /* SNB-B */
2489 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2490 }
5eddb70b 2491 I915_WRITE(reg, temp);
8db9d77b 2492
5eddb70b
CW		 2493 reg = FDI_RX_CTL(pipe);
2494 temp = I915_READ(reg);
8db9d77b
ZW		 2495 if (HAS_PCH_CPT(dev)) {
2496 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2498 } else {
2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 }
5eddb70b
CW		 2502 I915_WRITE(reg, temp);
2503
2504 POSTING_READ(reg);
8db9d77b
ZW		 2505 udelay(150);
2506
0206e353 2507 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
8db9d77b
ZW		 2515 udelay(500);
2516
fa37d39e
SP		 2517 for (retry = 0; retry < 5; retry++) {
2518 reg = FDI_RX_IIR(pipe);
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521 if (temp & FDI_RX_SYMBOL_LOCK) {
2522 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2523 DRM_DEBUG_KMS("FDI train 2 done.\n");
2524 break;
2525 }
2526 udelay(50);
8db9d77b 2527 }
fa37d39e
SP		 2528 if (retry < 5)
2529 break;
8db9d77b
ZW		 2530 }
2531 if (i == 4)
5eddb70b 2532 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2533
2534 DRM_DEBUG_KMS("FDI train done.\n");
2535}
2536
357555c0
JB		 2537/* Manual link training for Ivy Bridge A0 parts */
2538static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2539{
2540 struct drm_device *dev = crtc->dev;
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543 int pipe = intel_crtc->pipe;
2544 u32 reg, temp, i;
2545
2546 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2547 for train result */
2548 reg = FDI_RX_IMR(pipe);
2549 temp = I915_READ(reg);
2550 temp &= ~FDI_RX_SYMBOL_LOCK;
2551 temp &= ~FDI_RX_BIT_LOCK;
2552 I915_WRITE(reg, temp);
2553
2554 POSTING_READ(reg);
2555 udelay(150);
2556
01a415fd
DV		 2557 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2558 I915_READ(FDI_RX_IIR(pipe)));
2559
357555c0
JB		 2560 /* enable CPU FDI TX and PCH FDI RX */
2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
627eb5a3
DV		 2563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2565 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2566 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2569 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2571
d74cf324
DV		 2572 I915_WRITE(FDI_RX_MISC(pipe),
2573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2574
357555c0
JB		 2575 reg = FDI_RX_CTL(pipe);
2576 temp = I915_READ(reg);
2577 temp &= ~FDI_LINK_TRAIN_AUTO;
2578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2580 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2581 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2582
2583 POSTING_READ(reg);
2584 udelay(150);
2585
0206e353 2586 for (i = 0; i < 4; i++) {
357555c0
JB		 2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
2594 udelay(500);
2595
2596 reg = FDI_RX_IIR(pipe);
2597 temp = I915_READ(reg);
2598 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2599
2600 if (temp & FDI_RX_BIT_LOCK ||
2601 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2602 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2603 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2604 break;
2605 }
2606 }
2607 if (i == 4)
2608 DRM_ERROR("FDI train 1 fail!\n");
2609
2610 /* Train 2 */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2617 I915_WRITE(reg, temp);
2618
2619 reg = FDI_RX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(150);
2627
0206e353 2628 for (i = 0; i < 4; i++) {
357555c0
JB		 2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632 temp |= snb_b_fdi_train_param[i];
2633 I915_WRITE(reg, temp);
2634
2635 POSTING_READ(reg);
2636 udelay(500);
2637
2638 reg = FDI_RX_IIR(pipe);
2639 temp = I915_READ(reg);
2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642 if (temp & FDI_RX_SYMBOL_LOCK) {
2643 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2644 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2645 break;
2646 }
2647 }
2648 if (i == 4)
2649 DRM_ERROR("FDI train 2 fail!\n");
2650
2651 DRM_DEBUG_KMS("FDI train done.\n");
2652}
2653
88cefb6c 2654static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2655{
88cefb6c 2656 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2657 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2658 int pipe = intel_crtc->pipe;
5eddb70b 2659 u32 reg, temp;
79e53945 2660
c64e311e 2661
c98e9dcf 2662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
627eb5a3
DV		 2665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2669
2670 POSTING_READ(reg);
c98e9dcf
JB		 2671 udelay(200);
2672
2673 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2674 temp = I915_READ(reg);
2675 I915_WRITE(reg, temp | FDI_PCDCLK);
2676
2677 POSTING_READ(reg);
c98e9dcf
JB		 2678 udelay(200);
2679
20749730
PZ		 2680 /* Enable CPU FDI TX PLL, always on for Ironlake */
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2685
20749730
PZ		 2686 POSTING_READ(reg);
2687 udelay(100);
6be4a607 2688 }
0e23b99d
JB		 2689}
2690
88cefb6c
DV		 2691static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2692{
2693 struct drm_device *dev = intel_crtc->base.dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 int pipe = intel_crtc->pipe;
2696 u32 reg, temp;
2697
2698 /* Switch from PCDclk to Rawclk */
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2702
2703 /* Disable CPU FDI TX PLL */
2704 reg = FDI_TX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2707
2708 POSTING_READ(reg);
2709 udelay(100);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2714
2715 /* Wait for the clocks to turn off. */
2716 POSTING_READ(reg);
2717 udelay(100);
2718}
2719
0fc932b8
JB		 2720static void ironlake_fdi_disable(struct drm_crtc *crtc)
2721{
2722 struct drm_device *dev = crtc->dev;
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725 int pipe = intel_crtc->pipe;
2726 u32 reg, temp;
2727
2728 /* disable CPU FDI tx and PCH FDI rx */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2732 POSTING_READ(reg);
2733
2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~(0x7 << 16);
dfd07d72 2737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2738 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2739
2740 POSTING_READ(reg);
2741 udelay(100);
2742
2743 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2744 if (HAS_PCH_IBX(dev)) {
2745 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2746 }
0fc932b8
JB		 2747
2748 /* still set train pattern 1 */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~FDI_LINK_TRAIN_NONE;
2752 temp |= FDI_LINK_TRAIN_PATTERN_1;
2753 I915_WRITE(reg, temp);
2754
2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 if (HAS_PCH_CPT(dev)) {
2758 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2760 } else {
2761 temp &= ~FDI_LINK_TRAIN_NONE;
2762 temp |= FDI_LINK_TRAIN_PATTERN_1;
2763 }
2764 /* BPC in FDI rx is consistent with that in PIPECONF */
2765 temp &= ~(0x07 << 16);
dfd07d72 2766 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2767 I915_WRITE(reg, temp);
2768
2769 POSTING_READ(reg);
2770 udelay(100);
2771}
2772
5bb61643
CW		 2773static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2774{
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2778 unsigned long flags;
2779 bool pending;
2780
10d83730
VS		 2781 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2782 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2783 return false;
2784
2785 spin_lock_irqsave(&dev->event_lock, flags);
2786 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2787 spin_unlock_irqrestore(&dev->event_lock, flags);
2788
2789 return pending;
2790}
2791
e6c3a2a6
CW		 2792static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2793{
0f91128d 2794 struct drm_device *dev = crtc->dev;
5bb61643 2795 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2796
2797 if (crtc->fb == NULL)
2798 return;
2799
2c10d571
DV		 2800 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2801
5bb61643
CW		 2802 wait_event(dev_priv->pending_flip_queue,
2803 !intel_crtc_has_pending_flip(crtc));
2804
0f91128d
CW		 2805 mutex_lock(&dev->struct_mutex);
2806 intel_finish_fb(crtc->fb);
2807 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2808}
2809
e615efe4
ED		 2810/* Program iCLKIP clock to the desired frequency */
2811static void lpt_program_iclkip(struct drm_crtc *crtc)
2812{
2813 struct drm_device *dev = crtc->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2816 u32 temp;
2817
09153000
DV		 2818 mutex_lock(&dev_priv->dpio_lock);
2819
e615efe4
ED		 2820 /* It is necessary to ungate the pixclk gate prior to programming
2821 * the divisors, and gate it back when it is done.
2822 */
2823 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2824
2825 /* Disable SSCCTL */
2826 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2827 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2828 SBI_SSCCTL_DISABLE,
2829 SBI_ICLK);
e615efe4
ED		 2830
2831 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2832 if (crtc->mode.clock == 20000) {
2833 auxdiv = 1;
2834 divsel = 0x41;
2835 phaseinc = 0x20;
2836 } else {
2837 /* The iCLK virtual clock root frequency is in MHz,
2838 * but the crtc->mode.clock in in KHz. To get the divisors,
2839 * it is necessary to divide one by another, so we
2840 * convert the virtual clock precision to KHz here for higher
2841 * precision.
2842 */
2843 u32 iclk_virtual_root_freq = 172800 * 1000;
2844 u32 iclk_pi_range = 64;
2845 u32 desired_divisor, msb_divisor_value, pi_value;
2846
2847 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2848 msb_divisor_value = desired_divisor / iclk_pi_range;
2849 pi_value = desired_divisor % iclk_pi_range;
2850
2851 auxdiv = 0;
2852 divsel = msb_divisor_value - 2;
2853 phaseinc = pi_value;
2854 }
2855
2856 /* This should not happen with any sane values */
2857 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2858 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2859 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2860 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2861
2862 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2863 crtc->mode.clock,
2864 auxdiv,
2865 divsel,
2866 phasedir,
2867 phaseinc);
2868
2869 /* Program SSCDIVINTPHASE6 */
988d6ee8 2870 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2871 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2872 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2873 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2874 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2875 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2876 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2877 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2878
2879 /* Program SSCAUXDIV */
988d6ee8 2880 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2881 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2882 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2883 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2884
2885 /* Enable modulator and associated divider */
988d6ee8 2886 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2887 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2888 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2889
2890 /* Wait for initialization time */
2891 udelay(24);
2892
2893 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2894
2895 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2896}
2897
275f01b2
DV		 2898static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2899 enum pipe pch_transcoder)
2900{
2901 struct drm_device *dev = crtc->base.dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2904
2905 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2906 I915_READ(HTOTAL(cpu_transcoder)));
2907 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2908 I915_READ(HBLANK(cpu_transcoder)));
2909 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2910 I915_READ(HSYNC(cpu_transcoder)));
2911
2912 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2913 I915_READ(VTOTAL(cpu_transcoder)));
2914 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2915 I915_READ(VBLANK(cpu_transcoder)));
2916 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2917 I915_READ(VSYNC(cpu_transcoder)));
2918 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2919 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2920}
2921
f67a559d
JB		 2922/*
2923 * Enable PCH resources required for PCH ports:
2924 * - PCH PLLs
2925 * - FDI training & RX/TX
2926 * - update transcoder timings
2927 * - DP transcoding bits
2928 * - transcoder
2929 */
2930static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2931{
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 int pipe = intel_crtc->pipe;
ee7b9f93 2936 u32 reg, temp;
2c07245f 2937
ab9412ba 2938 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2939
cd986abb
DV		 2940 /* Write the TU size bits before fdi link training, so that error
2941 * detection works. */
2942 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2943 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2944
c98e9dcf 2945 /* For PCH output, training FDI link */
674cf967 2946 dev_priv->display.fdi_link_train(crtc);
2c07245f 2947
572deb37
DV		 2948 /* XXX: pch pll's can be enabled any time before we enable the PCH
2949 * transcoder, and we actually should do this to not upset any PCH
2950 * transcoder that already use the clock when we share it.
2951 *
2952 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2953 * unconditionally resets the pll - we need that to have the right LVDS
2954 * enable sequence. */
b6b4e185 2955 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2956
303b81e0 2957 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2958 u32 sel;
4b645f14 2959
c98e9dcf 2960 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2961 switch (pipe) {
2962 default:
2963 case 0:
2964 temp |= TRANSA_DPLL_ENABLE;
2965 sel = TRANSA_DPLLB_SEL;
2966 break;
2967 case 1:
2968 temp |= TRANSB_DPLL_ENABLE;
2969 sel = TRANSB_DPLLB_SEL;
2970 break;
2971 case 2:
2972 temp |= TRANSC_DPLL_ENABLE;
2973 sel = TRANSC_DPLLB_SEL;
2974 break;
d64311ab 2975 }
ee7b9f93
JB		 2976 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2977 temp |= sel;
2978 else
2979 temp &= ~sel;
c98e9dcf 2980 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2981 }
5eddb70b 2982
d9b6cb56
JB		 2983 /* set transcoder timing, panel must allow it */
2984 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2985 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2986
303b81e0 2987 intel_fdi_normal_train(crtc);
5e84e1a4 2988
c98e9dcf
JB		 2989 /* For PCH DP, enable TRANS_DP_CTL */
2990 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2991 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2992 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2993 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2994 reg = TRANS_DP_CTL(pipe);
2995 temp = I915_READ(reg);
2996 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2997 TRANS_DP_SYNC_MASK |
2998 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2999 temp |= (TRANS_DP_OUTPUT_ENABLE |
3000 TRANS_DP_ENH_FRAMING);
9325c9f0 3001 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3002
3003 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3004 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3005 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3006 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3007
3008 switch (intel_trans_dp_port_sel(crtc)) {
3009 case PCH_DP_B:
5eddb70b 3010 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3011 break;
3012 case PCH_DP_C:
5eddb70b 3013 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3014 break;
3015 case PCH_DP_D:
5eddb70b 3016 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3017 break;
3018 default:
e95d41e1 3019 BUG();
32f9d658 3020 }
2c07245f 3021
5eddb70b 3022 I915_WRITE(reg, temp);
6be4a607 3023 }
b52eb4dc 3024
b8a4f404 3025 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3026}
3027
1507e5bd
PZ		 3028static void lpt_pch_enable(struct drm_crtc *crtc)
3029{
3030 struct drm_device *dev = crtc->dev;
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3033 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3034
ab9412ba 3035 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3036
8c52b5e8 3037 lpt_program_iclkip(crtc);
1507e5bd 3038
0540e488 3039 /* Set transcoder timing. */
275f01b2 3040 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3041
937bb610 3042 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3043}
3044
ee7b9f93
JB		 3045static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3046{
3047 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3048
3049 if (pll == NULL)
3050 return;
3051
3052 if (pll->refcount == 0) {
3053 WARN(1, "bad PCH PLL refcount\n");
3054 return;
3055 }
3056
3057 --pll->refcount;
3058 intel_crtc->pch_pll = NULL;
3059}
3060
3061static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3062{
3063 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3064 struct intel_pch_pll *pll;
3065 int i;
3066
3067 pll = intel_crtc->pch_pll;
3068 if (pll) {
3069 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3070 intel_crtc->base.base.id, pll->pll_reg);
3071 goto prepare;
3072 }
3073
98b6bd99
DV		 3074 if (HAS_PCH_IBX(dev_priv->dev)) {
3075 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3076 i = intel_crtc->pipe;
3077 pll = &dev_priv->pch_plls[i];
3078
3079 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3080 intel_crtc->base.base.id, pll->pll_reg);
3081
3082 goto found;
3083 }
3084
ee7b9f93
JB		 3085 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3086 pll = &dev_priv->pch_plls[i];
3087
3088 /* Only want to check enabled timings first */
3089 if (pll->refcount == 0)
3090 continue;
3091
3092 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3093 fp == I915_READ(pll->fp0_reg)) {
3094 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3095 intel_crtc->base.base.id,
3096 pll->pll_reg, pll->refcount, pll->active);
3097
3098 goto found;
3099 }
3100 }
3101
3102 /* Ok no matching timings, maybe there's a free one? */
3103 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3104 pll = &dev_priv->pch_plls[i];
3105 if (pll->refcount == 0) {
3106 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3107 intel_crtc->base.base.id, pll->pll_reg);
3108 goto found;
3109 }
3110 }
3111
3112 return NULL;
3113
3114found:
3115 intel_crtc->pch_pll = pll;
3116 pll->refcount++;
84f44ce7 3117 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3118prepare: /* separate function? */
3119 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3120
e04c7350
CW		 3121 /* Wait for the clocks to stabilize before rewriting the regs */
3122 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3123 POSTING_READ(pll->pll_reg);
3124 udelay(150);
e04c7350
CW		 3125
3126 I915_WRITE(pll->fp0_reg, fp);
3127 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3128 pll->on = false;
3129 return pll;
3130}
3131
a1520318 3132static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3133{
3134 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3135 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3136 u32 temp;
3137
3138 temp = I915_READ(dslreg);
3139 udelay(500);
3140 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3141 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3142 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3143 }
3144}
3145
b074cec8
JB		 3146static void ironlake_pfit_enable(struct intel_crtc *crtc)
3147{
3148 struct drm_device *dev = crtc->base.dev;
3149 struct drm_i915_private *dev_priv = dev->dev_private;
3150 int pipe = crtc->pipe;
3151
0ef37f3f 3152 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3153 /* Force use of hard-coded filter coefficients
3154 * as some pre-programmed values are broken,
3155 * e.g. x201.
3156 */
3157 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3158 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3159 PF_PIPE_SEL_IVB(pipe));
3160 else
3161 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3162 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3163 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3164 }
3165}
3166
f67a559d
JB		 3167static void ironlake_crtc_enable(struct drm_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3172 struct intel_encoder *encoder;
f67a559d
JB		 3173 int pipe = intel_crtc->pipe;
3174 int plane = intel_crtc->plane;
3175 u32 temp;
f67a559d 3176
08a48469
DV		 3177 WARN_ON(!crtc->enabled);
3178
f67a559d
JB		 3179 if (intel_crtc->active)
3180 return;
3181
3182 intel_crtc->active = true;
8664281b
PZ		 3183
3184 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3185 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3186
f67a559d
JB		 3187 intel_update_watermarks(dev);
3188
3189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3190 temp = I915_READ(PCH_LVDS);
3191 if ((temp & LVDS_PORT_EN) == 0)
3192 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3193 }
3194
f67a559d 3195
5bfe2ac0 3196 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3197 /* Note: FDI PLL enabling _must_ be done before we enable the
3198 * cpu pipes, hence this is separate from all the other fdi/pch
3199 * enabling. */
88cefb6c 3200 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3201 } else {
3202 assert_fdi_tx_disabled(dev_priv, pipe);
3203 assert_fdi_rx_disabled(dev_priv, pipe);
3204 }
f67a559d 3205
bf49ec8c
DV		 3206 for_each_encoder_on_crtc(dev, crtc, encoder)
3207 if (encoder->pre_enable)
3208 encoder->pre_enable(encoder);
f67a559d
JB		 3209
3210 /* Enable panel fitting for LVDS */
b074cec8 3211 ironlake_pfit_enable(intel_crtc);
f67a559d 3212
9c54c0dd
JB		 3213 /*
3214 * On ILK+ LUT must be loaded before the pipe is running but with
3215 * clocks enabled
3216 */
3217 intel_crtc_load_lut(crtc);
3218
5bfe2ac0
DV		 3219 intel_enable_pipe(dev_priv, pipe,
3220 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3221 intel_enable_plane(dev_priv, plane, pipe);
3222
5bfe2ac0 3223 if (intel_crtc->config.has_pch_encoder)
f67a559d 3224 ironlake_pch_enable(crtc);
c98e9dcf 3225
d1ebd816 3226 mutex_lock(&dev->struct_mutex);
bed4a673 3227 intel_update_fbc(dev);
d1ebd816
BW		 3228 mutex_unlock(&dev->struct_mutex);
3229
6b383a7f 3230 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3231
fa5c73b1
DV		 3232 for_each_encoder_on_crtc(dev, crtc, encoder)
3233 encoder->enable(encoder);
61b77ddd
DV		 3234
3235 if (HAS_PCH_CPT(dev))
a1520318 3236 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3237
3238 /*
3239 * There seems to be a race in PCH platform hw (at least on some
3240 * outputs) where an enabled pipe still completes any pageflip right
3241 * away (as if the pipe is off) instead of waiting for vblank. As soon
3242 * as the first vblank happend, everything works as expected. Hence just
3243 * wait for one vblank before returning to avoid strange things
3244 * happening.
3245 */
3246 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3247}
3248
42db64ef
PZ		 3249/* IPS only exists on ULT machines and is tied to pipe A. */
3250static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3251{
3252 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3253}
3254
3255static void hsw_enable_ips(struct intel_crtc *crtc)
3256{
3257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258
3259 if (!crtc->config.ips_enabled)
3260 return;
3261
3262 /* We can only enable IPS after we enable a plane and wait for a vblank.
3263 * We guarantee that the plane is enabled by calling intel_enable_ips
3264 * only after intel_enable_plane. And intel_enable_plane already waits
3265 * for a vblank, so all we need to do here is to enable the IPS bit. */
3266 assert_plane_enabled(dev_priv, crtc->plane);
3267 I915_WRITE(IPS_CTL, IPS_ENABLE);
3268}
3269
3270static void hsw_disable_ips(struct intel_crtc *crtc)
3271{
3272 struct drm_device *dev = crtc->base.dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274
3275 if (!crtc->config.ips_enabled)
3276 return;
3277
3278 assert_plane_enabled(dev_priv, crtc->plane);
3279 I915_WRITE(IPS_CTL, 0);
3280
3281 /* We need to wait for a vblank before we can disable the plane. */
3282 intel_wait_for_vblank(dev, crtc->pipe);
3283}
3284
4f771f10
PZ		 3285static void haswell_crtc_enable(struct drm_crtc *crtc)
3286{
3287 struct drm_device *dev = crtc->dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290 struct intel_encoder *encoder;
3291 int pipe = intel_crtc->pipe;
3292 int plane = intel_crtc->plane;
4f771f10
PZ		 3293
3294 WARN_ON(!crtc->enabled);
3295
3296 if (intel_crtc->active)
3297 return;
3298
3299 intel_crtc->active = true;
8664281b
PZ		 3300
3301 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3302 if (intel_crtc->config.has_pch_encoder)
3303 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3304
4f771f10
PZ		 3305 intel_update_watermarks(dev);
3306
5bfe2ac0 3307 if (intel_crtc->config.has_pch_encoder)
04945641 3308 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3309
3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 if (encoder->pre_enable)
3312 encoder->pre_enable(encoder);
3313
1f544388 3314 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3315
1f544388 3316 /* Enable panel fitting for eDP */
b074cec8 3317 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3318
3319 /*
3320 * On ILK+ LUT must be loaded before the pipe is running but with
3321 * clocks enabled
3322 */
3323 intel_crtc_load_lut(crtc);
3324
1f544388 3325 intel_ddi_set_pipe_settings(crtc);
8228c251 3326 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3327
5bfe2ac0
DV		 3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3330 intel_enable_plane(dev_priv, plane, pipe);
3331
42db64ef
PZ		 3332 hsw_enable_ips(intel_crtc);
3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3335 lpt_pch_enable(crtc);
4f771f10
PZ		 3336
3337 mutex_lock(&dev->struct_mutex);
3338 intel_update_fbc(dev);
3339 mutex_unlock(&dev->struct_mutex);
3340
3341 intel_crtc_update_cursor(crtc, true);
3342
3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
3345
4f771f10
PZ		 3346 /*
3347 * There seems to be a race in PCH platform hw (at least on some
3348 * outputs) where an enabled pipe still completes any pageflip right
3349 * away (as if the pipe is off) instead of waiting for vblank. As soon
3350 * as the first vblank happend, everything works as expected. Hence just
3351 * wait for one vblank before returning to avoid strange things
3352 * happening.
3353 */
3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3355}
3356
3f8dce3a
DV		 3357static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358{
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3362
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369 }
3370}
3371
6be4a607
JB		 3372static void ironlake_crtc_disable(struct drm_crtc *crtc)
3373{
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3377 struct intel_encoder *encoder;
6be4a607
JB		 3378 int pipe = intel_crtc->pipe;
3379 int plane = intel_crtc->plane;
5eddb70b 3380 u32 reg, temp;
b52eb4dc 3381
ef9c3aee 3382
f7abfe8b
CW		 3383 if (!intel_crtc->active)
3384 return;
3385
ea9d758d
DV		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3388
e6c3a2a6 3389 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3390 drm_vblank_off(dev, pipe);
6b383a7f 3391 intel_crtc_update_cursor(crtc, false);
5eddb70b 3392
b24e7179 3393 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3394
973d04f9
CW		 3395 if (dev_priv->cfb_plane == plane)
3396 intel_disable_fbc(dev);
2c07245f 3397
8664281b 3398 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3399 intel_disable_pipe(dev_priv, pipe);
32f9d658 3400
3f8dce3a 3401 ironlake_pfit_disable(intel_crtc);
2c07245f 3402
bf49ec8c
DV		 3403 for_each_encoder_on_crtc(dev, crtc, encoder)
3404 if (encoder->post_disable)
3405 encoder->post_disable(encoder);
2c07245f 3406
0fc932b8 3407 ironlake_fdi_disable(crtc);
249c0e64 3408
b8a4f404 3409 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3410 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3411
6be4a607
JB		 3412 if (HAS_PCH_CPT(dev)) {
3413 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3414 reg = TRANS_DP_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3417 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3418 I915_WRITE(reg, temp);
6be4a607
JB		 3419
3420 /* disable DPLL_SEL */
3421 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3422 switch (pipe) {
3423 case 0:
d64311ab 3424 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3425 break;
3426 case 1:
6be4a607 3427 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3428 break;
3429 case 2:
4b645f14 3430 /* C shares PLL A or B */
d64311ab 3431 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3432 break;
3433 default:
3434 BUG(); /* wtf */
3435 }
6be4a607 3436 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3437 }
e3421a18 3438
6be4a607 3439 /* disable PCH DPLL */
ee7b9f93 3440 intel_disable_pch_pll(intel_crtc);
8db9d77b 3441
88cefb6c 3442 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3443
f7abfe8b 3444 intel_crtc->active = false;
6b383a7f 3445 intel_update_watermarks(dev);
d1ebd816
BW		 3446
3447 mutex_lock(&dev->struct_mutex);
6b383a7f 3448 intel_update_fbc(dev);
d1ebd816 3449 mutex_unlock(&dev->struct_mutex);
6be4a607 3450}
1b3c7a47 3451
4f771f10 3452static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3453{
4f771f10
PZ		 3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3457 struct intel_encoder *encoder;
3458 int pipe = intel_crtc->pipe;
3459 int plane = intel_crtc->plane;
3b117c8f 3460 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3461
4f771f10
PZ		 3462 if (!intel_crtc->active)
3463 return;
3464
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->disable(encoder);
3467
3468 intel_crtc_wait_for_pending_flips(crtc);
3469 drm_vblank_off(dev, pipe);
3470 intel_crtc_update_cursor(crtc, false);
3471
891348b2 3472 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3473 if (dev_priv->cfb_plane == plane)
3474 intel_disable_fbc(dev);
3475
42db64ef
PZ		 3476 hsw_disable_ips(intel_crtc);
3477
891348b2
RV		 3478 intel_disable_plane(dev_priv, plane, pipe);
3479
8664281b
PZ		 3480 if (intel_crtc->config.has_pch_encoder)
3481 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3482 intel_disable_pipe(dev_priv, pipe);
3483
ad80a810 3484 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3485
3f8dce3a 3486 ironlake_pfit_disable(intel_crtc);
4f771f10 3487
1f544388 3488 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3489
3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 if (encoder->post_disable)
3492 encoder->post_disable(encoder);
3493
88adfff1 3494 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3495 lpt_disable_pch_transcoder(dev_priv);
8664281b 3496 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3497 intel_ddi_fdi_disable(crtc);
83616634 3498 }
4f771f10
PZ		 3499
3500 intel_crtc->active = false;
3501 intel_update_watermarks(dev);
3502
3503 mutex_lock(&dev->struct_mutex);
3504 intel_update_fbc(dev);
3505 mutex_unlock(&dev->struct_mutex);
3506}
3507
ee7b9f93
JB		 3508static void ironlake_crtc_off(struct drm_crtc *crtc)
3509{
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 intel_put_pch_pll(intel_crtc);
3512}
3513
6441ab5f
PZ		 3514static void haswell_crtc_off(struct drm_crtc *crtc)
3515{
3516 intel_ddi_put_crtc_pll(crtc);
3517}
3518
02e792fb
DV		 3519static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3520{
02e792fb 3521 if (!enable && intel_crtc->overlay) {
23f09ce3 3522 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3523 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3524
23f09ce3 3525 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3526 dev_priv->mm.interruptible = false;
3527 (void) intel_overlay_switch_off(intel_crtc->overlay);
3528 dev_priv->mm.interruptible = true;
23f09ce3 3529 mutex_unlock(&dev->struct_mutex);
02e792fb 3530 }
02e792fb 3531
5dcdbcb0
CW		 3532 /* Let userspace switch the overlay on again. In most cases userspace
3533 * has to recompute where to put it anyway.
3534 */
02e792fb
DV		 3535}
3536
61bc95c1
EE		 3537/**
3538 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3539 * cursor plane briefly if not already running after enabling the display
3540 * plane.
3541 * This workaround avoids occasional blank screens when self refresh is
3542 * enabled.
3543 */
3544static void
3545g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3546{
3547 u32 cntl = I915_READ(CURCNTR(pipe));
3548
3549 if ((cntl & CURSOR_MODE) == 0) {
3550 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3551
3552 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3553 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3554 intel_wait_for_vblank(dev_priv->dev, pipe);
3555 I915_WRITE(CURCNTR(pipe), cntl);
3556 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3557 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3558 }
3559}
3560
2dd24552
JB		 3561static void i9xx_pfit_enable(struct intel_crtc *crtc)
3562{
3563 struct drm_device *dev = crtc->base.dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct intel_crtc_config *pipe_config = &crtc->config;
3566
328d8e82 3567 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3568 return;
3569
2dd24552 3570 /*
c0b03411
DV		 3571 * The panel fitter should only be adjusted whilst the pipe is disabled,
3572 * according to register description and PRM.
2dd24552 3573 */
c0b03411
DV		 3574 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3575 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3576
b074cec8
JB		 3577 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3578 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3579
3580 /* Border color in case we don't scale up to the full screen. Black by
3581 * default, change to something else for debugging. */
3582 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3583}
3584
89b667f8
JB		 3585static void valleyview_crtc_enable(struct drm_crtc *crtc)
3586{
3587 struct drm_device *dev = crtc->dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3590 struct intel_encoder *encoder;
3591 int pipe = intel_crtc->pipe;
3592 int plane = intel_crtc->plane;
3593
3594 WARN_ON(!crtc->enabled);
3595
3596 if (intel_crtc->active)
3597 return;
3598
3599 intel_crtc->active = true;
3600 intel_update_watermarks(dev);
3601
3602 mutex_lock(&dev_priv->dpio_lock);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_pll_enable)
3606 encoder->pre_pll_enable(encoder);
3607
3608 intel_enable_pll(dev_priv, pipe);
3609
3610 for_each_encoder_on_crtc(dev, crtc, encoder)
3611 if (encoder->pre_enable)
3612 encoder->pre_enable(encoder);
3613
3614 /* VLV wants encoder enabling _before_ the pipe is up. */
3615 for_each_encoder_on_crtc(dev, crtc, encoder)
3616 encoder->enable(encoder);
3617
2dd24552
JB		 3618 /* Enable panel fitting for eDP */
3619 i9xx_pfit_enable(intel_crtc);
3620
89b667f8
JB		 3621 intel_enable_pipe(dev_priv, pipe, false);
3622 intel_enable_plane(dev_priv, plane, pipe);
3623
3624 intel_crtc_load_lut(crtc);
3625 intel_update_fbc(dev);
3626
3627 /* Give the overlay scaler a chance to enable if it's on this pipe */
3628 intel_crtc_dpms_overlay(intel_crtc, true);
3629 intel_crtc_update_cursor(crtc, true);
3630
3631 mutex_unlock(&dev_priv->dpio_lock);
3632}
3633
0b8765c6 3634static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3635{
3636 struct drm_device *dev = crtc->dev;
79e53945
JB		 3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3639 struct intel_encoder *encoder;
79e53945 3640 int pipe = intel_crtc->pipe;
80824003 3641 int plane = intel_crtc->plane;
79e53945 3642
08a48469
DV		 3643 WARN_ON(!crtc->enabled);
3644
f7abfe8b
CW		 3645 if (intel_crtc->active)
3646 return;
3647
3648 intel_crtc->active = true;
6b383a7f
CW		 3649 intel_update_watermarks(dev);
3650
63d7bbe9 3651 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3652
3653 for_each_encoder_on_crtc(dev, crtc, encoder)
3654 if (encoder->pre_enable)
3655 encoder->pre_enable(encoder);
3656
2dd24552
JB		 3657 /* Enable panel fitting for LVDS */
3658 i9xx_pfit_enable(intel_crtc);
3659
040484af 3660 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3661 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3662 if (IS_G4X(dev))
3663 g4x_fixup_plane(dev_priv, pipe);
79e53945 3664
0b8765c6 3665 intel_crtc_load_lut(crtc);
bed4a673 3666 intel_update_fbc(dev);
79e53945 3667
0b8765c6
JB		 3668 /* Give the overlay scaler a chance to enable if it's on this pipe */
3669 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3670 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3671
fa5c73b1
DV		 3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 encoder->enable(encoder);
0b8765c6 3674}
79e53945 3675
87476d63
DV		 3676static void i9xx_pfit_disable(struct intel_crtc *crtc)
3677{
3678 struct drm_device *dev = crtc->base.dev;
3679 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3680
328d8e82
DV		 3681 if (!crtc->config.gmch_pfit.control)
3682 return;
87476d63 3683
328d8e82 3684 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3685
328d8e82
DV		 3686 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3687 I915_READ(PFIT_CONTROL));
3688 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3689}
3690
0b8765c6
JB		 3691static void i9xx_crtc_disable(struct drm_crtc *crtc)
3692{
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3696 struct intel_encoder *encoder;
0b8765c6
JB		 3697 int pipe = intel_crtc->pipe;
3698 int plane = intel_crtc->plane;
ef9c3aee 3699
f7abfe8b
CW		 3700 if (!intel_crtc->active)
3701 return;
3702
ea9d758d
DV		 3703 for_each_encoder_on_crtc(dev, crtc, encoder)
3704 encoder->disable(encoder);
3705
0b8765c6 3706 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3707 intel_crtc_wait_for_pending_flips(crtc);
3708 drm_vblank_off(dev, pipe);
0b8765c6 3709 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3710 intel_crtc_update_cursor(crtc, false);
0b8765c6 3711
973d04f9
CW		 3712 if (dev_priv->cfb_plane == plane)
3713 intel_disable_fbc(dev);
79e53945 3714
b24e7179 3715 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3716 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3717
87476d63 3718 i9xx_pfit_disable(intel_crtc);
24a1f16d 3719
89b667f8
JB		 3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->post_disable)
3722 encoder->post_disable(encoder);
3723
63d7bbe9 3724 intel_disable_pll(dev_priv, pipe);
0b8765c6 3725
f7abfe8b 3726 intel_crtc->active = false;
6b383a7f
CW		 3727 intel_update_fbc(dev);
3728 intel_update_watermarks(dev);
0b8765c6
JB		 3729}
3730
ee7b9f93
JB		 3731static void i9xx_crtc_off(struct drm_crtc *crtc)
3732{
3733}
3734
976f8a20
DV		 3735static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736 bool enabled)
2c07245f
ZW		 3737{
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_master_private *master_priv;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
79e53945
JB		 3742
3743 if (!dev->primary->master)
3744 return;
3745
3746 master_priv = dev->primary->master->driver_priv;
3747 if (!master_priv->sarea_priv)
3748 return;
3749
79e53945
JB		 3750 switch (pipe) {
3751 case 0:
3752 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 case 1:
3756 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758 break;
3759 default:
9db4a9c7 3760 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3761 break;
3762 }
79e53945
JB		 3763}
3764
976f8a20
DV		 3765/**
3766 * Sets the power management mode of the pipe and plane.
3767 */
3768void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_encoder *intel_encoder;
3773 bool enable = false;
3774
3775 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776 enable |= intel_encoder->connectors_active;
3777
3778 if (enable)
3779 dev_priv->display.crtc_enable(crtc);
3780 else
3781 dev_priv->display.crtc_disable(crtc);
3782
3783 intel_crtc_update_sarea(crtc, enable);
3784}
3785
cdd59983
CW		 3786static void intel_crtc_disable(struct drm_crtc *crtc)
3787{
cdd59983 3788 struct drm_device *dev = crtc->dev;
976f8a20 3789 struct drm_connector *connector;
ee7b9f93 3790 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3792
976f8a20
DV		 3793 /* crtc should still be enabled when we disable it. */
3794 WARN_ON(!crtc->enabled);
3795
3796 dev_priv->display.crtc_disable(crtc);
c77bf565 3797 intel_crtc->eld_vld = false;
976f8a20 3798 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3799 dev_priv->display.off(crtc);
3800
931872fc
CW		 3801 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3803
3804 if (crtc->fb) {
3805 mutex_lock(&dev->struct_mutex);
1690e1eb 3806 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3807 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3808 crtc->fb = NULL;
3809 }
3810
3811 /* Update computed state. */
3812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813 if (!connector->encoder || !connector->encoder->crtc)
3814 continue;
3815
3816 if (connector->encoder->crtc != crtc)
3817 continue;
3818
3819 connector->dpms = DRM_MODE_DPMS_OFF;
3820 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3821 }
3822}
3823
a261b246 3824void intel_modeset_disable(struct drm_device *dev)
79e53945 3825{
a261b246
DV		 3826 struct drm_crtc *crtc;
3827
3828 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829 if (crtc->enabled)
3830 intel_crtc_disable(crtc);
3831 }
79e53945
JB		 3832}
3833
ea5b213a 3834void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3835{
4ef69c7a 3836 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3837
ea5b213a
CW		 3838 drm_encoder_cleanup(encoder);
3839 kfree(intel_encoder);
7e7d76c3
JB		 3840}
3841
5ab432ef
DV		 3842/* Simple dpms helper for encodres with just one connector, no cloning and only
3843 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844 * state of the entire output pipe. */
3845void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3846{
5ab432ef
DV		 3847 if (mode == DRM_MODE_DPMS_ON) {
3848 encoder->connectors_active = true;
3849
b2cabb0e 3850 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3851 } else {
3852 encoder->connectors_active = false;
3853
b2cabb0e 3854 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3855 }
79e53945
JB		 3856}
3857
0a91ca29
DV		 3858/* Cross check the actual hw state with our own modeset state tracking (and it's
3859 * internal consistency). */
b980514c 3860static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3861{
0a91ca29
DV		 3862 if (connector->get_hw_state(connector)) {
3863 struct intel_encoder *encoder = connector->encoder;
3864 struct drm_crtc *crtc;
3865 bool encoder_enabled;
3866 enum pipe pipe;
3867
3868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869 connector->base.base.id,
3870 drm_get_connector_name(&connector->base));
3871
3872 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873 "wrong connector dpms state\n");
3874 WARN(connector->base.encoder != &encoder->base,
3875 "active connector not linked to encoder\n");
3876 WARN(!encoder->connectors_active,
3877 "encoder->connectors_active not set\n");
3878
3879 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880 WARN(!encoder_enabled, "encoder not enabled\n");
3881 if (WARN_ON(!encoder->base.crtc))
3882 return;
3883
3884 crtc = encoder->base.crtc;
3885
3886 WARN(!crtc->enabled, "crtc not enabled\n");
3887 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889 "encoder active on the wrong pipe\n");
3890 }
79e53945
JB		 3891}
3892
5ab432ef
DV		 3893/* Even simpler default implementation, if there's really no special case to
3894 * consider. */
3895void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3896{
5ab432ef 3897 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3898
5ab432ef
DV		 3899 /* All the simple cases only support two dpms states. */
3900 if (mode != DRM_MODE_DPMS_ON)
3901 mode = DRM_MODE_DPMS_OFF;
d4270e57 3902
5ab432ef
DV		 3903 if (mode == connector->dpms)
3904 return;
3905
3906 connector->dpms = mode;
3907
3908 /* Only need to change hw state when actually enabled */
3909 if (encoder->base.crtc)
3910 intel_encoder_dpms(encoder, mode);
3911 else
8af6cf88 3912 WARN_ON(encoder->connectors_active != false);
0a91ca29 3913
b980514c 3914 intel_modeset_check_state(connector->dev);
79e53945
JB		 3915}
3916
f0947c37
DV		 3917/* Simple connector->get_hw_state implementation for encoders that support only
3918 * one connector and no cloning and hence the encoder state determines the state
3919 * of the connector. */
3920bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3921{
24929352 3922 enum pipe pipe = 0;
f0947c37 3923 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3924
f0947c37 3925 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3926}
3927
1857e1da
DV		 3928static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929 struct intel_crtc_config *pipe_config)
3930{
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932 struct intel_crtc *pipe_B_crtc =
3933 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 if (pipe_config->fdi_lanes > 4) {
3938 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939 pipe_name(pipe), pipe_config->fdi_lanes);
3940 return false;
3941 }
3942
3943 if (IS_HASWELL(dev)) {
3944 if (pipe_config->fdi_lanes > 2) {
3945 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946 pipe_config->fdi_lanes);
3947 return false;
3948 } else {
3949 return true;
3950 }
3951 }
3952
3953 if (INTEL_INFO(dev)->num_pipes == 2)
3954 return true;
3955
3956 /* Ivybridge 3 pipe is really complicated */
3957 switch (pipe) {
3958 case PIPE_A:
3959 return true;
3960 case PIPE_B:
3961 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962 pipe_config->fdi_lanes > 2) {
3963 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964 pipe_name(pipe), pipe_config->fdi_lanes);
3965 return false;
3966 }
3967 return true;
3968 case PIPE_C:
1e833f40 3969 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3970 pipe_B_crtc->config.fdi_lanes <= 2) {
3971 if (pipe_config->fdi_lanes > 2) {
3972 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3974 return false;
3975 }
3976 } else {
3977 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978 return false;
3979 }
3980 return true;
3981 default:
3982 BUG();
3983 }
3984}
3985
e29c22c0
DV		 3986#define RETRY 1
3987static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988 struct intel_crtc_config *pipe_config)
877d48d5 3989{
1857e1da 3990 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3991 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
2bd89a07 3992 int target_clock, lane, link_bw, fdi_dotclock;
e29c22c0 3993 bool setup_ok, needs_recompute = false;
877d48d5 3994
e29c22c0 3995retry:
877d48d5
DV		 3996 /* FDI is a binary signal running at ~2.7GHz, encoding
3997 * each output octet as 10 bits. The actual frequency
3998 * is stored as a divider into a 100MHz clock, and the
3999 * mode pixel clock is stored in units of 1KHz.
4000 * Hence the bw of each lane in terms of the mode signal
4001 * is:
4002 */
4003 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
4005 if (pipe_config->pixel_target_clock)
4006 target_clock = pipe_config->pixel_target_clock;
4007 else
4008 target_clock = adjusted_mode->clock;
4009
2bd89a07
DV		 4010 fdi_dotclock = target_clock;
4011 if (pipe_config->pixel_multiplier > 1)
4012 fdi_dotclock /= pipe_config->pixel_multiplier;
4013
4014 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4015 pipe_config->pipe_bpp);
4016
4017 pipe_config->fdi_lanes = lane;
4018
2bd89a07 4019 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4020 link_bw, &pipe_config->fdi_m_n);
1857e1da 4021
e29c22c0
DV		 4022 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4023 intel_crtc->pipe, pipe_config);
4024 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4025 pipe_config->pipe_bpp -= 2*3;
4026 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4027 pipe_config->pipe_bpp);
4028 needs_recompute = true;
4029 pipe_config->bw_constrained = true;
4030
4031 goto retry;
4032 }
4033
4034 if (needs_recompute)
4035 return RETRY;
4036
4037 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4038}
4039
42db64ef
PZ		 4040static void hsw_compute_ips_config(struct intel_crtc *crtc,
4041 struct intel_crtc_config *pipe_config)
4042{
3c4ca58c
PZ		 4043 pipe_config->ips_enabled = i915_enable_ips &&
4044 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4045 pipe_config->pipe_bpp == 24;
4046}
4047
e29c22c0
DV		 4048static int intel_crtc_compute_config(struct drm_crtc *crtc,
4049 struct intel_crtc_config *pipe_config)
79e53945 4050{
2c07245f 4051 struct drm_device *dev = crtc->dev;
b8cecdf5 4052 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4054
bad720ff 4055 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4056 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4057 if (pipe_config->requested_mode.clock * 3
4058 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4059 return -EINVAL;
2c07245f 4060 }
89749350 4061
f9bef081
DV		 4062 /* All interlaced capable intel hw wants timings in frames. Note though
4063 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4064 * timings, so we need to be careful not to clobber these.*/
7ae89233 4065 if (!pipe_config->timings_set)
f9bef081 4066 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4067
8693a824
DL		 4068 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4069 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4070 */
4071 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4072 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4073 return -EINVAL;
44f46b42 4074
bd080ee5 4075 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4076 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4077 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4078 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4079 * for lvds. */
4080 pipe_config->pipe_bpp = 8*3;
4081 }
4082
42db64ef
PZ		 4083 if (IS_HASWELL(dev))
4084 hsw_compute_ips_config(intel_crtc, pipe_config);
4085
877d48d5 4086 if (pipe_config->has_pch_encoder)
42db64ef 4087 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4088
e29c22c0 4089 return 0;
79e53945
JB		 4090}
4091
25eb05fc
JB		 4092static int valleyview_get_display_clock_speed(struct drm_device *dev)
4093{
4094 return 400000; /* FIXME */
4095}
4096
e70236a8
JB		 4097static int i945_get_display_clock_speed(struct drm_device *dev)
4098{
4099 return 400000;
4100}
79e53945 4101
e70236a8 4102static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4103{
e70236a8
JB		 4104 return 333000;
4105}
79e53945 4106
e70236a8
JB		 4107static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4108{
4109 return 200000;
4110}
79e53945 4111
e70236a8
JB		 4112static int i915gm_get_display_clock_speed(struct drm_device *dev)
4113{
4114 u16 gcfgc = 0;
79e53945 4115
e70236a8
JB		 4116 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4117
4118 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4119 return 133000;
4120 else {
4121 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4122 case GC_DISPLAY_CLOCK_333_MHZ:
4123 return 333000;
4124 default:
4125 case GC_DISPLAY_CLOCK_190_200_MHZ:
4126 return 190000;
79e53945 4127 }
e70236a8
JB		 4128 }
4129}
4130
4131static int i865_get_display_clock_speed(struct drm_device *dev)
4132{
4133 return 266000;
4134}
4135
4136static int i855_get_display_clock_speed(struct drm_device *dev)
4137{
4138 u16 hpllcc = 0;
4139 /* Assume that the hardware is in the high speed state. This
4140 * should be the default.
4141 */
4142 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4143 case GC_CLOCK_133_200:
4144 case GC_CLOCK_100_200:
4145 return 200000;
4146 case GC_CLOCK_166_250:
4147 return 250000;
4148 case GC_CLOCK_100_133:
79e53945 4149 return 133000;
e70236a8 4150 }
79e53945 4151
e70236a8
JB		 4152 /* Shouldn't happen */
4153 return 0;
4154}
79e53945 4155
e70236a8
JB		 4156static int i830_get_display_clock_speed(struct drm_device *dev)
4157{
4158 return 133000;
79e53945
JB		 4159}
4160
2c07245f 4161static void
a65851af 4162intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4163{
a65851af
VS		 4164 while (*num > DATA_LINK_M_N_MASK ||
4165 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4166 *num >>= 1;
4167 *den >>= 1;
4168 }
4169}
4170
a65851af
VS		 4171static void compute_m_n(unsigned int m, unsigned int n,
4172 uint32_t *ret_m, uint32_t *ret_n)
4173{
4174 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4175 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4176 intel_reduce_m_n_ratio(ret_m, ret_n);
4177}
4178
e69d0bc1
DV		 4179void
4180intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4181 int pixel_clock, int link_clock,
4182 struct intel_link_m_n *m_n)
2c07245f 4183{
e69d0bc1 4184 m_n->tu = 64;
a65851af
VS		 4185
4186 compute_m_n(bits_per_pixel * pixel_clock,
4187 link_clock * nlanes * 8,
4188 &m_n->gmch_m, &m_n->gmch_n);
4189
4190 compute_m_n(pixel_clock, link_clock,
4191 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4192}
4193
a7615030
CW		 4194static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4195{
72bbe58c
KP		 4196 if (i915_panel_use_ssc >= 0)
4197 return i915_panel_use_ssc != 0;
41aa3448 4198 return dev_priv->vbt.lvds_use_ssc
435793df 4199 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4200}
4201
a0c4da24
JB		 4202static int vlv_get_refclk(struct drm_crtc *crtc)
4203{
4204 struct drm_device *dev = crtc->dev;
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206 int refclk = 27000; /* for DP & HDMI */
4207
4208 return 100000; /* only one validated so far */
4209
4210 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4211 refclk = 96000;
4212 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4213 if (intel_panel_use_ssc(dev_priv))
4214 refclk = 100000;
4215 else
4216 refclk = 96000;
4217 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4218 refclk = 100000;
4219 }
4220
4221 return refclk;
4222}
4223
c65d77d8
JB		 4224static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4225{
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 int refclk;
4229
a0c4da24
JB		 4230 if (IS_VALLEYVIEW(dev)) {
4231 refclk = vlv_get_refclk(crtc);
4232 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4233 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4234 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4235 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4236 refclk / 1000);
4237 } else if (!IS_GEN2(dev)) {
4238 refclk = 96000;
4239 } else {
4240 refclk = 48000;
4241 }
4242
4243 return refclk;
4244}
4245
7429e9d4
DV		 4246static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4247{
4248 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4249}
4250
4251static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4252{
4253 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4254}
4255
f47709a9 4256static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4257 intel_clock_t *reduced_clock)
4258{
f47709a9 4259 struct drm_device *dev = crtc->base.dev;
a7516a05 4260 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4261 int pipe = crtc->pipe;
a7516a05
JB		 4262 u32 fp, fp2 = 0;
4263
4264 if (IS_PINEVIEW(dev)) {
7429e9d4 4265 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4266 if (reduced_clock)
7429e9d4 4267 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4268 } else {
7429e9d4 4269 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4270 if (reduced_clock)
7429e9d4 4271 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4272 }
4273
4274 I915_WRITE(FP0(pipe), fp);
4275
f47709a9
DV		 4276 crtc->lowfreq_avail = false;
4277 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4278 reduced_clock && i915_powersave) {
4279 I915_WRITE(FP1(pipe), fp2);
f47709a9 4280 crtc->lowfreq_avail = true;
a7516a05
JB		 4281 } else {
4282 I915_WRITE(FP1(pipe), fp);
4283 }
4284}
4285
89b667f8
JB		 4286static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4287{
4288 u32 reg_val;
4289
4290 /*
4291 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4292 * and set it to a reasonable value instead.
4293 */
ae99258f 4294 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4295 reg_val &= 0xffffff00;
4296 reg_val |= 0x00000030;
ae99258f 4297 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4298
ae99258f 4299 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4300 reg_val &= 0x8cffffff;
4301 reg_val = 0x8c000000;
ae99258f 4302 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4303
ae99258f 4304 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4305 reg_val &= 0xffffff00;
ae99258f 4306 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4307
ae99258f 4308 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4309 reg_val &= 0x00ffffff;
4310 reg_val |= 0xb0000000;
ae99258f 4311 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4312}
4313
b551842d
DV		 4314static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4315 struct intel_link_m_n *m_n)
4316{
4317 struct drm_device *dev = crtc->base.dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 int pipe = crtc->pipe;
4320
e3b95f1e
DV		 4321 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4322 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4323 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4324 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4325}
4326
4327static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4328 struct intel_link_m_n *m_n)
4329{
4330 struct drm_device *dev = crtc->base.dev;
4331 struct drm_i915_private *dev_priv = dev->dev_private;
4332 int pipe = crtc->pipe;
4333 enum transcoder transcoder = crtc->config.cpu_transcoder;
4334
4335 if (INTEL_INFO(dev)->gen >= 5) {
4336 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4337 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4338 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4339 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4340 } else {
e3b95f1e
DV		 4341 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4342 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4343 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4344 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4345 }
4346}
4347
03afc4a2
DV		 4348static void intel_dp_set_m_n(struct intel_crtc *crtc)
4349{
4350 if (crtc->config.has_pch_encoder)
4351 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4352 else
4353 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4354}
4355
f47709a9 4356static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4357{
f47709a9 4358 struct drm_device *dev = crtc->base.dev;
a0c4da24 4359 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4360 struct drm_display_mode *adjusted_mode =
4361 &crtc->config.adjusted_mode;
4362 struct intel_encoder *encoder;
f47709a9 4363 int pipe = crtc->pipe;
89b667f8 4364 u32 dpll, mdiv;
a0c4da24 4365 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4366 bool is_hdmi;
198a037f 4367 u32 coreclk, reg_val, dpll_md;
a0c4da24 4368
09153000
DV		 4369 mutex_lock(&dev_priv->dpio_lock);
4370
89b667f8 4371 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4372
f47709a9
DV		 4373 bestn = crtc->config.dpll.n;
4374 bestm1 = crtc->config.dpll.m1;
4375 bestm2 = crtc->config.dpll.m2;
4376 bestp1 = crtc->config.dpll.p1;
4377 bestp2 = crtc->config.dpll.p2;
a0c4da24 4378
89b667f8
JB		 4379 /* See eDP HDMI DPIO driver vbios notes doc */
4380
4381 /* PLL B needs special handling */
4382 if (pipe)
4383 vlv_pllb_recal_opamp(dev_priv);
4384
4385 /* Set up Tx target for periodic Rcomp update */
ae99258f 4386 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4387
4388 /* Disable target IRef on PLL */
ae99258f 4389 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4390 reg_val &= 0x00ffffff;
ae99258f 4391 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4392
4393 /* Disable fast lock */
ae99258f 4394 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4395
4396 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4397 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4398 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4399 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4400 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4401
4402 /*
4403 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4404 * but we don't support that).
4405 * Note: don't use the DAC post divider as it seems unstable.
4406 */
4407 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4408 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4409
89b667f8 4410 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4411 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4412
89b667f8
JB		 4413 /* Set HBR and RBR LPF coefficients */
4414 if (adjusted_mode->clock == 162000 ||
4415 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4416 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4417 0x005f0021);
4418 else
ae99258f 4419 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4420 0x00d0000f);
4421
4422 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4423 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4424 /* Use SSC source */
4425 if (!pipe)
ae99258f 4426 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4427 0x0df40000);
4428 else
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4430 0x0df70000);
4431 } else { /* HDMI or VGA */
4432 /* Use bend source */
4433 if (!pipe)
ae99258f 4434 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4435 0x0df70000);
4436 else
ae99258f 4437 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4438 0x0df40000);
4439 }
a0c4da24 4440
ae99258f 4441 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4442 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4443 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4444 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4445 coreclk |= 0x01000000;
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4447
ae99258f 4448 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4449
89b667f8
JB		 4450 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4451 if (encoder->pre_pll_enable)
4452 encoder->pre_pll_enable(encoder);
2a8f64ca 4453
89b667f8
JB		 4454 /* Enable DPIO clock input */
4455 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4456 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4457 if (pipe)
4458 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4459
89b667f8 4460 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4461 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4462 POSTING_READ(DPLL(pipe));
4463 udelay(150);
a0c4da24 4464
89b667f8
JB		 4465 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4466 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4467
198a037f
DV		 4468 dpll_md = 0;
4469 if (crtc->config.pixel_multiplier > 1) {
4470 dpll_md = (crtc->config.pixel_multiplier - 1)
4471 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4472 }
198a037f
DV		 4473 I915_WRITE(DPLL_MD(pipe), dpll_md);
4474 POSTING_READ(DPLL_MD(pipe));
f47709a9 4475
89b667f8
JB		 4476 if (crtc->config.has_dp_encoder)
4477 intel_dp_set_m_n(crtc);
09153000
DV		 4478
4479 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4480}
4481
f47709a9
DV		 4482static void i9xx_update_pll(struct intel_crtc *crtc,
4483 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4484 int num_connectors)
4485{
f47709a9 4486 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4487 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4488 struct intel_encoder *encoder;
f47709a9 4489 int pipe = crtc->pipe;
eb1cbe48
DV		 4490 u32 dpll;
4491 bool is_sdvo;
f47709a9 4492 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4493
f47709a9 4494 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4495
f47709a9
DV		 4496 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4497 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4498
4499 dpll = DPLL_VGA_MODE_DIS;
4500
f47709a9 4501 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4502 dpll |= DPLLB_MODE_LVDS;
4503 else
4504 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4505
198a037f
DV		 4506 if ((crtc->config.pixel_multiplier > 1) &&
4507 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4508 dpll |= (crtc->config.pixel_multiplier - 1)
4509 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4510 }
198a037f
DV		 4511
4512 if (is_sdvo)
4513 dpll |= DPLL_DVO_HIGH_SPEED;
4514
f47709a9 4515 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4516 dpll |= DPLL_DVO_HIGH_SPEED;
4517
4518 /* compute bitmask from p1 value */
4519 if (IS_PINEVIEW(dev))
4520 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4521 else {
4522 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4523 if (IS_G4X(dev) && reduced_clock)
4524 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4525 }
4526 switch (clock->p2) {
4527 case 5:
4528 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4529 break;
4530 case 7:
4531 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4532 break;
4533 case 10:
4534 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4535 break;
4536 case 14:
4537 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4538 break;
4539 }
4540 if (INTEL_INFO(dev)->gen >= 4)
4541 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4542
09ede541 4543 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4544 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4545 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4546 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4547 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4548 else
4549 dpll |= PLL_REF_INPUT_DREFCLK;
4550
4551 dpll |= DPLL_VCO_ENABLE;
4552 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4553 POSTING_READ(DPLL(pipe));
4554 udelay(150);
4555
f47709a9 4556 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4557 if (encoder->pre_pll_enable)
4558 encoder->pre_pll_enable(encoder);
eb1cbe48 4559
f47709a9
DV		 4560 if (crtc->config.has_dp_encoder)
4561 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4562
4563 I915_WRITE(DPLL(pipe), dpll);
4564
4565 /* Wait for the clocks to stabilize. */
4566 POSTING_READ(DPLL(pipe));
4567 udelay(150);
4568
4569 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4570 u32 dpll_md = 0;
4571 if (crtc->config.pixel_multiplier > 1) {
4572 dpll_md = (crtc->config.pixel_multiplier - 1)
4573 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4574 }
198a037f 4575 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4576 } else {
4577 /* The pixel multiplier can only be updated once the
4578 * DPLL is enabled and the clocks are stable.
4579 *
4580 * So write it again.
4581 */
4582 I915_WRITE(DPLL(pipe), dpll);
4583 }
4584}
4585
f47709a9 4586static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4587 struct drm_display_mode *adjusted_mode,
f47709a9 4588 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4589 int num_connectors)
4590{
f47709a9 4591 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4592 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4593 struct intel_encoder *encoder;
f47709a9 4594 int pipe = crtc->pipe;
eb1cbe48 4595 u32 dpll;
f47709a9 4596 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4597
f47709a9 4598 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4599
eb1cbe48
DV		 4600 dpll = DPLL_VGA_MODE_DIS;
4601
f47709a9 4602 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4603 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4604 } else {
4605 if (clock->p1 == 2)
4606 dpll |= PLL_P1_DIVIDE_BY_TWO;
4607 else
4608 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4609 if (clock->p2 == 4)
4610 dpll |= PLL_P2_DIVIDE_BY_4;
4611 }
4612
f47709a9 4613 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4614 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4615 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4616 else
4617 dpll |= PLL_REF_INPUT_DREFCLK;
4618
4619 dpll |= DPLL_VCO_ENABLE;
4620 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4621 POSTING_READ(DPLL(pipe));
4622 udelay(150);
4623
f47709a9 4624 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4625 if (encoder->pre_pll_enable)
4626 encoder->pre_pll_enable(encoder);
eb1cbe48 4627
5b5896e4
DV		 4628 I915_WRITE(DPLL(pipe), dpll);
4629
4630 /* Wait for the clocks to stabilize. */
4631 POSTING_READ(DPLL(pipe));
4632 udelay(150);
4633
eb1cbe48
DV		 4634 /* The pixel multiplier can only be updated once the
4635 * DPLL is enabled and the clocks are stable.
4636 *
4637 * So write it again.
4638 */
4639 I915_WRITE(DPLL(pipe), dpll);
4640}
4641
b0e77b9c
PZ		 4642static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4643 struct drm_display_mode *mode,
4644 struct drm_display_mode *adjusted_mode)
4645{
4646 struct drm_device *dev = intel_crtc->base.dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4649 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4650 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4651
4652 /* We need to be careful not to changed the adjusted mode, for otherwise
4653 * the hw state checker will get angry at the mismatch. */
4654 crtc_vtotal = adjusted_mode->crtc_vtotal;
4655 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4656
4657 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4658 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4659 crtc_vtotal -= 1;
4660 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4661 vsyncshift = adjusted_mode->crtc_hsync_start
4662 - adjusted_mode->crtc_htotal / 2;
4663 } else {
4664 vsyncshift = 0;
4665 }
4666
4667 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4668 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4669
fe2b8f9d 4670 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4671 (adjusted_mode->crtc_hdisplay - 1) |
4672 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4673 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4674 (adjusted_mode->crtc_hblank_start - 1) |
4675 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4676 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4677 (adjusted_mode->crtc_hsync_start - 1) |
4678 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4679
fe2b8f9d 4680 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4681 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4682 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4683 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4684 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4685 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4686 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4687 (adjusted_mode->crtc_vsync_start - 1) |
4688 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4689
b5e508d4
PZ		 4690 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4691 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4692 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4693 * bits. */
4694 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4695 (pipe == PIPE_B || pipe == PIPE_C))
4696 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4697
b0e77b9c
PZ		 4698 /* pipesrc controls the size that is scaled from, which should
4699 * always be the user's requested size.
4700 */
4701 I915_WRITE(PIPESRC(pipe),
4702 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4703}
4704
1bd1bd80
DV		 4705static void intel_get_pipe_timings(struct intel_crtc *crtc,
4706 struct intel_crtc_config *pipe_config)
4707{
4708 struct drm_device *dev = crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4711 uint32_t tmp;
4712
4713 tmp = I915_READ(HTOTAL(cpu_transcoder));
4714 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4715 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4716 tmp = I915_READ(HBLANK(cpu_transcoder));
4717 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4718 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4719 tmp = I915_READ(HSYNC(cpu_transcoder));
4720 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4721 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4722
4723 tmp = I915_READ(VTOTAL(cpu_transcoder));
4724 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4725 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4726 tmp = I915_READ(VBLANK(cpu_transcoder));
4727 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4728 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4729 tmp = I915_READ(VSYNC(cpu_transcoder));
4730 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4731 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4732
4733 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4734 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4735 pipe_config->adjusted_mode.crtc_vtotal += 1;
4736 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4737 }
4738
4739 tmp = I915_READ(PIPESRC(crtc->pipe));
4740 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4741 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4742}
4743
84b046f3
DV		 4744static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4745{
4746 struct drm_device *dev = intel_crtc->base.dev;
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748 uint32_t pipeconf;
4749
4750 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4751
4752 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4753 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4754 * core speed.
4755 *
4756 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4757 * pipe == 0 check?
4758 */
4759 if (intel_crtc->config.requested_mode.clock >
4760 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4761 pipeconf |= PIPECONF_DOUBLE_WIDE;
4762 else
4763 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4764 }
4765
ff9ce46e
DV		 4766 /* only g4x and later have fancy bpc/dither controls */
4767 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4768 pipeconf &= ~(PIPECONF_BPC_MASK |
4769 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4770
4771 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4772 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4773 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4774 PIPECONF_DITHER_TYPE_SP;
84b046f3 4775
ff9ce46e
DV		 4776 switch (intel_crtc->config.pipe_bpp) {
4777 case 18:
4778 pipeconf |= PIPECONF_6BPC;
4779 break;
4780 case 24:
4781 pipeconf |= PIPECONF_8BPC;
4782 break;
4783 case 30:
4784 pipeconf |= PIPECONF_10BPC;
4785 break;
4786 default:
4787 /* Case prevented by intel_choose_pipe_bpp_dither. */
4788 BUG();
84b046f3
DV		 4789 }
4790 }
4791
4792 if (HAS_PIPE_CXSR(dev)) {
4793 if (intel_crtc->lowfreq_avail) {
4794 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4795 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4796 } else {
4797 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4798 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4799 }
4800 }
4801
4802 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4803 if (!IS_GEN2(dev) &&
4804 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4805 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4806 else
4807 pipeconf |= PIPECONF_PROGRESSIVE;
4808
9c8e09b7
VS		 4809 if (IS_VALLEYVIEW(dev)) {
4810 if (intel_crtc->config.limited_color_range)
4811 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4812 else
4813 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4814 }
4815
84b046f3
DV		 4816 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4817 POSTING_READ(PIPECONF(intel_crtc->pipe));
4818}
4819
f564048e 4820static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4821 int x, int y,
94352cf9 4822 struct drm_framebuffer *fb)
79e53945
JB		 4823{
4824 struct drm_device *dev = crtc->dev;
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4827 struct drm_display_mode *adjusted_mode =
4828 &intel_crtc->config.adjusted_mode;
4829 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4830 int pipe = intel_crtc->pipe;
80824003 4831 int plane = intel_crtc->plane;
c751ce4f 4832 int refclk, num_connectors = 0;
652c393a 4833 intel_clock_t clock, reduced_clock;
84b046f3 4834 u32 dspcntr;
a16af721
DV		 4835 bool ok, has_reduced_clock = false;
4836 bool is_lvds = false;
5eddb70b 4837 struct intel_encoder *encoder;
d4906093 4838 const intel_limit_t *limit;
5c3b82e2 4839 int ret;
79e53945 4840
6c2b7c12 4841 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4842 switch (encoder->type) {
79e53945
JB		 4843 case INTEL_OUTPUT_LVDS:
4844 is_lvds = true;
4845 break;
79e53945 4846 }
43565a06 4847
c751ce4f 4848 num_connectors++;
79e53945
JB		 4849 }
4850
c65d77d8 4851 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4852
d4906093
ML		 4853 /*
4854 * Returns a set of divisors for the desired target clock with the given
4855 * refclk, or FALSE. The returned values represent the clock equation:
4856 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4857 */
1b894b59 4858 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4859 ok = dev_priv->display.find_dpll(limit, crtc, adjusted_mode->clock,
4860 refclk, NULL, &clock);
4861 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4862 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4863 return -EINVAL;
79e53945
JB		 4864 }
4865
cda4b7d3 4866 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4867 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4868
ddc9003c 4869 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4870 /*
4871 * Ensure we match the reduced clock's P to the target clock.
4872 * If the clocks don't match, we can't switch the display clock
4873 * by using the FP0/FP1. In such case we will disable the LVDS
4874 * downclock feature.
4875 */
ee9300bb
DV		 4876 has_reduced_clock =
4877 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4878 dev_priv->lvds_downclock,
ee9300bb 4879 refclk, &clock,
5eddb70b 4880 &reduced_clock);
7026d4ac 4881 }
f47709a9
DV		 4882 /* Compat-code for transition, will disappear. */
4883 if (!intel_crtc->config.clock_set) {
4884 intel_crtc->config.dpll.n = clock.n;
4885 intel_crtc->config.dpll.m1 = clock.m1;
4886 intel_crtc->config.dpll.m2 = clock.m2;
4887 intel_crtc->config.dpll.p1 = clock.p1;
4888 intel_crtc->config.dpll.p2 = clock.p2;
4889 }
7026d4ac 4890
eb1cbe48 4891 if (IS_GEN2(dev))
f47709a9 4892 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4893 has_reduced_clock ? &reduced_clock : NULL,
4894 num_connectors);
a0c4da24 4895 else if (IS_VALLEYVIEW(dev))
f47709a9 4896 vlv_update_pll(intel_crtc);
79e53945 4897 else
f47709a9 4898 i9xx_update_pll(intel_crtc,
eb1cbe48 4899 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4900 num_connectors);
79e53945 4901
79e53945
JB		 4902 /* Set up the display plane register */
4903 dspcntr = DISPPLANE_GAMMA_ENABLE;
4904
da6ecc5d
JB		 4905 if (!IS_VALLEYVIEW(dev)) {
4906 if (pipe == 0)
4907 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4908 else
4909 dspcntr |= DISPPLANE_SEL_PIPE_B;
4910 }
79e53945 4911
b0e77b9c 4912 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4913
4914 /* pipesrc and dspsize control the size that is scaled from,
4915 * which should always be the user's requested size.
79e53945 4916 */
929c77fb
EA		 4917 I915_WRITE(DSPSIZE(plane),
4918 ((mode->vdisplay - 1) << 16) |
4919 (mode->hdisplay - 1));
4920 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4921
84b046f3
DV		 4922 i9xx_set_pipeconf(intel_crtc);
4923
f564048e
EA		 4924 I915_WRITE(DSPCNTR(plane), dspcntr);
4925 POSTING_READ(DSPCNTR(plane));
4926
94352cf9 4927 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4928
4929 intel_update_watermarks(dev);
4930
f564048e
EA		 4931 return ret;
4932}
4933
2fa2fe9a
DV		 4934static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4935 struct intel_crtc_config *pipe_config)
4936{
4937 struct drm_device *dev = crtc->base.dev;
4938 struct drm_i915_private *dev_priv = dev->dev_private;
4939 uint32_t tmp;
4940
4941 tmp = I915_READ(PFIT_CONTROL);
4942
4943 if (INTEL_INFO(dev)->gen < 4) {
4944 if (crtc->pipe != PIPE_B)
4945 return;
4946
4947 /* gen2/3 store dither state in pfit control, needs to match */
4948 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4949 } else {
4950 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4951 return;
4952 }
4953
4954 if (!(tmp & PFIT_ENABLE))
4955 return;
4956
4957 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4958 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4959 if (INTEL_INFO(dev)->gen < 5)
4960 pipe_config->gmch_pfit.lvds_border_bits =
4961 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4962}
4963
0e8ffe1b
DV		 4964static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4965 struct intel_crtc_config *pipe_config)
4966{
4967 struct drm_device *dev = crtc->base.dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 uint32_t tmp;
4970
eccb140b
DV		 4971 pipe_config->cpu_transcoder = crtc->pipe;
4972
0e8ffe1b
DV		 4973 tmp = I915_READ(PIPECONF(crtc->pipe));
4974 if (!(tmp & PIPECONF_ENABLE))
4975 return false;
4976
1bd1bd80
DV		 4977 intel_get_pipe_timings(crtc, pipe_config);
4978
2fa2fe9a
DV		 4979 i9xx_get_pfit_config(crtc, pipe_config);
4980
0e8ffe1b
DV		 4981 return true;
4982}
4983
dde86e2d 4984static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4985{
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4988 struct intel_encoder *encoder;
74cfd7ac 4989 u32 val, final;
13d83a67 4990 bool has_lvds = false;
199e5d79 4991 bool has_cpu_edp = false;
199e5d79 4992 bool has_panel = false;
99eb6a01
KP		 4993 bool has_ck505 = false;
4994 bool can_ssc = false;
13d83a67
JB		 4995
4996 /* We need to take the global config into account */
199e5d79
KP		 4997 list_for_each_entry(encoder, &mode_config->encoder_list,
4998 base.head) {
4999 switch (encoder->type) {
5000 case INTEL_OUTPUT_LVDS:
5001 has_panel = true;
5002 has_lvds = true;
5003 break;
5004 case INTEL_OUTPUT_EDP:
5005 has_panel = true;
2de6905f 5006 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5007 has_cpu_edp = true;
5008 break;
13d83a67
JB		 5009 }
5010 }
5011
99eb6a01 5012 if (HAS_PCH_IBX(dev)) {
41aa3448 5013 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5014 can_ssc = has_ck505;
5015 } else {
5016 has_ck505 = false;
5017 can_ssc = true;
5018 }
5019
2de6905f
ID		 5020 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5021 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5022
5023 /* Ironlake: try to setup display ref clock before DPLL
5024 * enabling. This is only under driver's control after
5025 * PCH B stepping, previous chipset stepping should be
5026 * ignoring this setting.
5027 */
74cfd7ac
CW		 5028 val = I915_READ(PCH_DREF_CONTROL);
5029
5030 /* As we must carefully and slowly disable/enable each source in turn,
5031 * compute the final state we want first and check if we need to
5032 * make any changes at all.
5033 */
5034 final = val;
5035 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5036 if (has_ck505)
5037 final |= DREF_NONSPREAD_CK505_ENABLE;
5038 else
5039 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5040
5041 final &= ~DREF_SSC_SOURCE_MASK;
5042 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5043 final &= ~DREF_SSC1_ENABLE;
5044
5045 if (has_panel) {
5046 final |= DREF_SSC_SOURCE_ENABLE;
5047
5048 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5049 final |= DREF_SSC1_ENABLE;
5050
5051 if (has_cpu_edp) {
5052 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5053 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5054 else
5055 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5056 } else
5057 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5058 } else {
5059 final |= DREF_SSC_SOURCE_DISABLE;
5060 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5061 }
5062
5063 if (final == val)
5064 return;
5065
13d83a67 5066 /* Always enable nonspread source */
74cfd7ac 5067 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5068
99eb6a01 5069 if (has_ck505)
74cfd7ac 5070 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5071 else
74cfd7ac 5072 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5073
199e5d79 5074 if (has_panel) {
74cfd7ac
CW		 5075 val &= ~DREF_SSC_SOURCE_MASK;
5076 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5077
199e5d79 5078 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5079 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5080 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5081 val |= DREF_SSC1_ENABLE;
e77166b5 5082 } else
74cfd7ac 5083 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5084
5085 /* Get SSC going before enabling the outputs */
74cfd7ac 5086 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5087 POSTING_READ(PCH_DREF_CONTROL);
5088 udelay(200);
5089
74cfd7ac 5090 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5091
5092 /* Enable CPU source on CPU attached eDP */
199e5d79 5093 if (has_cpu_edp) {
99eb6a01 5094 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5095 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5096 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5097 }
13d83a67 5098 else
74cfd7ac 5099 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5100 } else
74cfd7ac 5101 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5102
74cfd7ac 5103 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5104 POSTING_READ(PCH_DREF_CONTROL);
5105 udelay(200);
5106 } else {
5107 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5108
74cfd7ac 5109 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5110
5111 /* Turn off CPU output */
74cfd7ac 5112 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5113
74cfd7ac 5114 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5115 POSTING_READ(PCH_DREF_CONTROL);
5116 udelay(200);
5117
5118 /* Turn off the SSC source */
74cfd7ac
CW		 5119 val &= ~DREF_SSC_SOURCE_MASK;
5120 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5121
5122 /* Turn off SSC1 */
74cfd7ac 5123 val &= ~DREF_SSC1_ENABLE;
199e5d79 5124
74cfd7ac 5125 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5126 POSTING_READ(PCH_DREF_CONTROL);
5127 udelay(200);
5128 }
74cfd7ac
CW		 5129
5130 BUG_ON(val != final);
13d83a67
JB		 5131}
5132
dde86e2d
PZ		 5133/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5134static void lpt_init_pch_refclk(struct drm_device *dev)
5135{
5136 struct drm_i915_private *dev_priv = dev->dev_private;
5137 struct drm_mode_config *mode_config = &dev->mode_config;
5138 struct intel_encoder *encoder;
5139 bool has_vga = false;
5140 bool is_sdv = false;
5141 u32 tmp;
5142
5143 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5144 switch (encoder->type) {
5145 case INTEL_OUTPUT_ANALOG:
5146 has_vga = true;
5147 break;
5148 }
5149 }
5150
5151 if (!has_vga)
5152 return;
5153
c00db246
DV		 5154 mutex_lock(&dev_priv->dpio_lock);
5155
dde86e2d
PZ		 5156 /* XXX: Rip out SDV support once Haswell ships for real. */
5157 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5158 is_sdv = true;
5159
5160 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5161 tmp &= ~SBI_SSCCTL_DISABLE;
5162 tmp |= SBI_SSCCTL_PATHALT;
5163 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5164
5165 udelay(24);
5166
5167 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5168 tmp &= ~SBI_SSCCTL_PATHALT;
5169 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5170
5171 if (!is_sdv) {
5172 tmp = I915_READ(SOUTH_CHICKEN2);
5173 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5174 I915_WRITE(SOUTH_CHICKEN2, tmp);
5175
5176 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5177 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5178 DRM_ERROR("FDI mPHY reset assert timeout\n");
5179
5180 tmp = I915_READ(SOUTH_CHICKEN2);
5181 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5182 I915_WRITE(SOUTH_CHICKEN2, tmp);
5183
5184 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5185 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5186 100))
5187 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5188 }
5189
5190 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5191 tmp &= ~(0xFF << 24);
5192 tmp |= (0x12 << 24);
5193 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5194
dde86e2d
PZ		 5195 if (is_sdv) {
5196 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5197 tmp |= 0x7FFF;
5198 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5199 }
5200
5201 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5202 tmp |= (1 << 11);
5203 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5204
5205 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5206 tmp |= (1 << 11);
5207 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5208
5209 if (is_sdv) {
5210 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5211 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5212 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5213
5214 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5215 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5216 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5217
5218 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5219 tmp |= (0x3F << 8);
5220 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5221
5222 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5223 tmp |= (0x3F << 8);
5224 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5225 }
5226
5227 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5228 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5229 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5230
5231 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5232 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5233 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5234
5235 if (!is_sdv) {
5236 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5237 tmp &= ~(7 << 13);
5238 tmp |= (5 << 13);
5239 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5240
5241 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5242 tmp &= ~(7 << 13);
5243 tmp |= (5 << 13);
5244 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5245 }
5246
5247 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5248 tmp &= ~0xFF;
5249 tmp |= 0x1C;
5250 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5253 tmp &= ~0xFF;
5254 tmp |= 0x1C;
5255 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5258 tmp &= ~(0xFF << 16);
5259 tmp |= (0x1C << 16);
5260 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5261
5262 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5263 tmp &= ~(0xFF << 16);
5264 tmp |= (0x1C << 16);
5265 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5266
5267 if (!is_sdv) {
5268 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5269 tmp |= (1 << 27);
5270 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5271
5272 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5273 tmp |= (1 << 27);
5274 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5275
5276 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5277 tmp &= ~(0xF << 28);
5278 tmp |= (4 << 28);
5279 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5280
5281 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5282 tmp &= ~(0xF << 28);
5283 tmp |= (4 << 28);
5284 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5285 }
5286
5287 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5288 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5289 tmp |= SBI_DBUFF0_ENABLE;
5290 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5291
5292 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5293}
5294
5295/*
5296 * Initialize reference clocks when the driver loads
5297 */
5298void intel_init_pch_refclk(struct drm_device *dev)
5299{
5300 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5301 ironlake_init_pch_refclk(dev);
5302 else if (HAS_PCH_LPT(dev))
5303 lpt_init_pch_refclk(dev);
5304}
5305
d9d444cb
JB		 5306static int ironlake_get_refclk(struct drm_crtc *crtc)
5307{
5308 struct drm_device *dev = crtc->dev;
5309 struct drm_i915_private *dev_priv = dev->dev_private;
5310 struct intel_encoder *encoder;
d9d444cb
JB		 5311 int num_connectors = 0;
5312 bool is_lvds = false;
5313
6c2b7c12 5314 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5315 switch (encoder->type) {
5316 case INTEL_OUTPUT_LVDS:
5317 is_lvds = true;
5318 break;
d9d444cb
JB		 5319 }
5320 num_connectors++;
5321 }
5322
5323 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5324 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5325 dev_priv->vbt.lvds_ssc_freq);
5326 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5327 }
5328
5329 return 120000;
5330}
5331
6ff93609 5332static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5333{
c8203565 5334 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5336 int pipe = intel_crtc->pipe;
c8203565
PZ		 5337 uint32_t val;
5338
5339 val = I915_READ(PIPECONF(pipe));
5340
dfd07d72 5341 val &= ~PIPECONF_BPC_MASK;
965e0c48 5342 switch (intel_crtc->config.pipe_bpp) {
c8203565 5343 case 18:
dfd07d72 5344 val |= PIPECONF_6BPC;
c8203565
PZ		 5345 break;
5346 case 24:
dfd07d72 5347 val |= PIPECONF_8BPC;
c8203565
PZ		 5348 break;
5349 case 30:
dfd07d72 5350 val |= PIPECONF_10BPC;
c8203565
PZ		 5351 break;
5352 case 36:
dfd07d72 5353 val |= PIPECONF_12BPC;
c8203565
PZ		 5354 break;
5355 default:
cc769b62
PZ		 5356 /* Case prevented by intel_choose_pipe_bpp_dither. */
5357 BUG();
c8203565
PZ		 5358 }
5359
5360 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5361 if (intel_crtc->config.dither)
c8203565
PZ		 5362 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5363
5364 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5365 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5366 val |= PIPECONF_INTERLACED_ILK;
5367 else
5368 val |= PIPECONF_PROGRESSIVE;
5369
50f3b016 5370 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5371 val |= PIPECONF_COLOR_RANGE_SELECT;
5372 else
5373 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5374
c8203565
PZ		 5375 I915_WRITE(PIPECONF(pipe), val);
5376 POSTING_READ(PIPECONF(pipe));
5377}
5378
86d3efce
VS		 5379/*
5380 * Set up the pipe CSC unit.
5381 *
5382 * Currently only full range RGB to limited range RGB conversion
5383 * is supported, but eventually this should handle various
5384 * RGB<->YCbCr scenarios as well.
5385 */
50f3b016 5386static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5387{
5388 struct drm_device *dev = crtc->dev;
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5391 int pipe = intel_crtc->pipe;
5392 uint16_t coeff = 0x7800; /* 1.0 */
5393
5394 /*
5395 * TODO: Check what kind of values actually come out of the pipe
5396 * with these coeff/postoff values and adjust to get the best
5397 * accuracy. Perhaps we even need to take the bpc value into
5398 * consideration.
5399 */
5400
50f3b016 5401 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5402 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5403
5404 /*
5405 * GY/GU and RY/RU should be the other way around according
5406 * to BSpec, but reality doesn't agree. Just set them up in
5407 * a way that results in the correct picture.
5408 */
5409 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5410 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5411
5412 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5413 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5414
5415 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5416 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5417
5418 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5419 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5420 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5421
5422 if (INTEL_INFO(dev)->gen > 6) {
5423 uint16_t postoff = 0;
5424
50f3b016 5425 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5426 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5427
5428 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5429 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5430 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5431
5432 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5433 } else {
5434 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5435
50f3b016 5436 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5437 mode |= CSC_BLACK_SCREEN_OFFSET;
5438
5439 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5440 }
5441}
5442
6ff93609 5443static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5444{
5445 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5447 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5448 uint32_t val;
5449
702e7a56 5450 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5451
5452 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5453 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5454 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5455
5456 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5457 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5458 val |= PIPECONF_INTERLACED_ILK;
5459 else
5460 val |= PIPECONF_PROGRESSIVE;
5461
702e7a56
PZ		 5462 I915_WRITE(PIPECONF(cpu_transcoder), val);
5463 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5464}
5465
6591c6e4
PZ		 5466static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5467 struct drm_display_mode *adjusted_mode,
5468 intel_clock_t *clock,
5469 bool *has_reduced_clock,
5470 intel_clock_t *reduced_clock)
5471{
5472 struct drm_device *dev = crtc->dev;
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 struct intel_encoder *intel_encoder;
5475 int refclk;
d4906093 5476 const intel_limit_t *limit;
a16af721 5477 bool ret, is_lvds = false;
79e53945 5478
6591c6e4
PZ		 5479 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5480 switch (intel_encoder->type) {
79e53945
JB		 5481 case INTEL_OUTPUT_LVDS:
5482 is_lvds = true;
5483 break;
79e53945
JB		 5484 }
5485 }
5486
d9d444cb 5487 refclk = ironlake_get_refclk(crtc);
79e53945 5488
d4906093
ML		 5489 /*
5490 * Returns a set of divisors for the desired target clock with the given
5491 * refclk, or FALSE. The returned values represent the clock equation:
5492 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5493 */
1b894b59 5494 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 5495 ret = dev_priv->display.find_dpll(limit, crtc, adjusted_mode->clock,
5496 refclk, NULL, clock);
6591c6e4
PZ		 5497 if (!ret)
5498 return false;
cda4b7d3 5499
ddc9003c 5500 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5501 /*
5502 * Ensure we match the reduced clock's P to the target clock.
5503 * If the clocks don't match, we can't switch the display clock
5504 * by using the FP0/FP1. In such case we will disable the LVDS
5505 * downclock feature.
5506 */
ee9300bb
DV		 5507 *has_reduced_clock =
5508 dev_priv->display.find_dpll(limit, crtc,
5509 dev_priv->lvds_downclock,
5510 refclk, clock,
5511 reduced_clock);
652c393a 5512 }
61e9653f 5513
6591c6e4
PZ		 5514 return true;
5515}
5516
01a415fd
DV		 5517static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5518{
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 uint32_t temp;
5521
5522 temp = I915_READ(SOUTH_CHICKEN1);
5523 if (temp & FDI_BC_BIFURCATION_SELECT)
5524 return;
5525
5526 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5527 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5528
5529 temp |= FDI_BC_BIFURCATION_SELECT;
5530 DRM_DEBUG_KMS("enabling fdi C rx\n");
5531 I915_WRITE(SOUTH_CHICKEN1, temp);
5532 POSTING_READ(SOUTH_CHICKEN1);
5533}
5534
ebfd86fd
DV		 5535static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5536{
5537 struct drm_device *dev = intel_crtc->base.dev;
5538 struct drm_i915_private *dev_priv = dev->dev_private;
5539
5540 switch (intel_crtc->pipe) {
5541 case PIPE_A:
5542 break;
5543 case PIPE_B:
5544 if (intel_crtc->config.fdi_lanes > 2)
5545 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5546 else
5547 cpt_enable_fdi_bc_bifurcation(dev);
5548
5549 break;
5550 case PIPE_C:
01a415fd
DV		 5551 cpt_enable_fdi_bc_bifurcation(dev);
5552
ebfd86fd 5553 break;
01a415fd
DV		 5554 default:
5555 BUG();
5556 }
5557}
5558
d4b1931c
PZ		 5559int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5560{
5561 /*
5562 * Account for spread spectrum to avoid
5563 * oversubscribing the link. Max center spread
5564 * is 2.5%; use 5% for safety's sake.
5565 */
5566 u32 bps = target_clock * bpp * 21 / 20;
5567 return bps / (link_bw * 8) + 1;
5568}
5569
7429e9d4
DV		 5570static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5571{
5572 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5573}
5574
de13a2e3 5575static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5576 u32 *fp,
9a7c7890 5577 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5578{
de13a2e3 5579 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5580 struct drm_device *dev = crtc->dev;
5581 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5582 struct intel_encoder *intel_encoder;
5583 uint32_t dpll;
6cc5f341 5584 int factor, num_connectors = 0;
09ede541 5585 bool is_lvds = false, is_sdvo = false;
79e53945 5586
de13a2e3
PZ		 5587 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5588 switch (intel_encoder->type) {
79e53945
JB		 5589 case INTEL_OUTPUT_LVDS:
5590 is_lvds = true;
5591 break;
5592 case INTEL_OUTPUT_SDVO:
7d57382e 5593 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5594 is_sdvo = true;
5595 break;
79e53945 5596 }
43565a06 5597
c751ce4f 5598 num_connectors++;
79e53945 5599 }
79e53945 5600
c1858123 5601 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5602 factor = 21;
5603 if (is_lvds) {
5604 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5605 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5606 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5607 factor = 25;
09ede541 5608 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5609 factor = 20;
c1858123 5610
7429e9d4 5611 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5612 *fp |= FP_CB_TUNE;
2c07245f 5613
9a7c7890
DV		 5614 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5615 *fp2 |= FP_CB_TUNE;
5616
5eddb70b 5617 dpll = 0;
2c07245f 5618
a07d6787
EA		 5619 if (is_lvds)
5620 dpll |= DPLLB_MODE_LVDS;
5621 else
5622 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5623
5624 if (intel_crtc->config.pixel_multiplier > 1) {
5625 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5626 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5627 }
198a037f
DV		 5628
5629 if (is_sdvo)
5630 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5631 if (intel_crtc->config.has_dp_encoder)
a07d6787 5632 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5633
a07d6787 5634 /* compute bitmask from p1 value */
7429e9d4 5635 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5636 /* also FPA1 */
7429e9d4 5637 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5638
7429e9d4 5639 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5640 case 5:
5641 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5642 break;
5643 case 7:
5644 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5645 break;
5646 case 10:
5647 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5648 break;
5649 case 14:
5650 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5651 break;
79e53945
JB		 5652 }
5653
b4c09f3b 5654 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5655 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5656 else
5657 dpll |= PLL_REF_INPUT_DREFCLK;
5658
de13a2e3
PZ		 5659 return dpll;
5660}
5661
5662static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5663 int x, int y,
5664 struct drm_framebuffer *fb)
5665{
5666 struct drm_device *dev = crtc->dev;
5667 struct drm_i915_private *dev_priv = dev->dev_private;
5668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5669 struct drm_display_mode *adjusted_mode =
5670 &intel_crtc->config.adjusted_mode;
5671 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5672 int pipe = intel_crtc->pipe;
5673 int plane = intel_crtc->plane;
5674 int num_connectors = 0;
5675 intel_clock_t clock, reduced_clock;
cbbab5bd 5676 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5677 bool ok, has_reduced_clock = false;
8b47047b 5678 bool is_lvds = false;
de13a2e3 5679 struct intel_encoder *encoder;
de13a2e3 5680 int ret;
de13a2e3
PZ		 5681
5682 for_each_encoder_on_crtc(dev, crtc, encoder) {
5683 switch (encoder->type) {
5684 case INTEL_OUTPUT_LVDS:
5685 is_lvds = true;
5686 break;
de13a2e3
PZ		 5687 }
5688
5689 num_connectors++;
a07d6787 5690 }
79e53945 5691
5dc5298b
PZ		 5692 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5693 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5694
de13a2e3
PZ		 5695 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5696 &has_reduced_clock, &reduced_clock);
ee9300bb 5697 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5698 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5699 return -EINVAL;
79e53945 5700 }
f47709a9
DV		 5701 /* Compat-code for transition, will disappear. */
5702 if (!intel_crtc->config.clock_set) {
5703 intel_crtc->config.dpll.n = clock.n;
5704 intel_crtc->config.dpll.m1 = clock.m1;
5705 intel_crtc->config.dpll.m2 = clock.m2;
5706 intel_crtc->config.dpll.p1 = clock.p1;
5707 intel_crtc->config.dpll.p2 = clock.p2;
5708 }
79e53945 5709
de13a2e3
PZ		 5710 /* Ensure that the cursor is valid for the new mode before changing... */
5711 intel_crtc_update_cursor(crtc, true);
5712
5dc5298b 5713 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5714 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5715 struct intel_pch_pll *pll;
4b645f14 5716
7429e9d4 5717 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5718 if (has_reduced_clock)
7429e9d4 5719 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5720
7429e9d4 5721 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5722 &fp, &reduced_clock,
5723 has_reduced_clock ? &fp2 : NULL);
5724
ee7b9f93
JB		 5725 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5726 if (pll == NULL) {
84f44ce7
VS		 5727 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5728 pipe_name(pipe));
4b645f14
JB		 5729 return -EINVAL;
5730 }
ee7b9f93
JB		 5731 } else
5732 intel_put_pch_pll(intel_crtc);
79e53945 5733
03afc4a2
DV		 5734 if (intel_crtc->config.has_dp_encoder)
5735 intel_dp_set_m_n(intel_crtc);
79e53945 5736
dafd226c
DV		 5737 for_each_encoder_on_crtc(dev, crtc, encoder)
5738 if (encoder->pre_pll_enable)
5739 encoder->pre_pll_enable(encoder);
79e53945 5740
ee7b9f93
JB		 5741 if (intel_crtc->pch_pll) {
5742 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5743
32f9d658 5744 /* Wait for the clocks to stabilize. */
ee7b9f93 5745 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5746 udelay(150);
5747
8febb297
EA		 5748 /* The pixel multiplier can only be updated once the
5749 * DPLL is enabled and the clocks are stable.
5750 *
5751 * So write it again.
5752 */
ee7b9f93 5753 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5754 }
79e53945 5755
5eddb70b 5756 intel_crtc->lowfreq_avail = false;
ee7b9f93 5757 if (intel_crtc->pch_pll) {
4b645f14 5758 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5759 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5760 intel_crtc->lowfreq_avail = true;
4b645f14 5761 } else {
ee7b9f93 5762 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5763 }
5764 }
5765
b0e77b9c 5766 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5767
ca3a0ff8 5768 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5769 intel_cpu_transcoder_set_m_n(intel_crtc,
5770 &intel_crtc->config.fdi_m_n);
5771 }
2c07245f 5772
ebfd86fd
DV		 5773 if (IS_IVYBRIDGE(dev))
5774 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5775
6ff93609 5776 ironlake_set_pipeconf(crtc);
79e53945 5777
a1f9e77e
PZ		 5778 /* Set up the display plane register */
5779 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5780 POSTING_READ(DSPCNTR(plane));
79e53945 5781
94352cf9 5782 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5783
5784 intel_update_watermarks(dev);
5785
1857e1da 5786 return ret;
79e53945
JB		 5787}
5788
72419203
DV		 5789static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5790 struct intel_crtc_config *pipe_config)
5791{
5792 struct drm_device *dev = crtc->base.dev;
5793 struct drm_i915_private *dev_priv = dev->dev_private;
5794 enum transcoder transcoder = pipe_config->cpu_transcoder;
5795
5796 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5797 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5798 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5799 & ~TU_SIZE_MASK;
5800 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5801 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5802 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5803}
5804
2fa2fe9a
DV		 5805static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5806 struct intel_crtc_config *pipe_config)
5807{
5808 struct drm_device *dev = crtc->base.dev;
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 uint32_t tmp;
5811
5812 tmp = I915_READ(PF_CTL(crtc->pipe));
5813
5814 if (tmp & PF_ENABLE) {
5815 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5816 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5817 }
5818}
5819
0e8ffe1b
DV		 5820static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5821 struct intel_crtc_config *pipe_config)
5822{
5823 struct drm_device *dev = crtc->base.dev;
5824 struct drm_i915_private *dev_priv = dev->dev_private;
5825 uint32_t tmp;
5826
eccb140b
DV		 5827 pipe_config->cpu_transcoder = crtc->pipe;
5828
0e8ffe1b
DV		 5829 tmp = I915_READ(PIPECONF(crtc->pipe));
5830 if (!(tmp & PIPECONF_ENABLE))
5831 return false;
5832
ab9412ba 5833 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5834 pipe_config->has_pch_encoder = true;
5835
627eb5a3
DV		 5836 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5837 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5838 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5839
5840 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5841 }
5842
1bd1bd80
DV		 5843 intel_get_pipe_timings(crtc, pipe_config);
5844
2fa2fe9a
DV		 5845 ironlake_get_pfit_config(crtc, pipe_config);
5846
0e8ffe1b
DV		 5847 return true;
5848}
5849
d6dd9eb1
DV		 5850static void haswell_modeset_global_resources(struct drm_device *dev)
5851{
d6dd9eb1
DV		 5852 bool enable = false;
5853 struct intel_crtc *crtc;
d6dd9eb1
DV		 5854
5855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5856 if (!crtc->base.enabled)
5857 continue;
d6dd9eb1 5858
e7a639c4
DV		 5859 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5860 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5861 enable = true;
5862 }
5863
d6dd9eb1
DV		 5864 intel_set_power_well(dev, enable);
5865}
5866
09b4ddf9 5867static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5868 int x, int y,
5869 struct drm_framebuffer *fb)
5870{
5871 struct drm_device *dev = crtc->dev;
5872 struct drm_i915_private *dev_priv = dev->dev_private;
5873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5874 struct drm_display_mode *adjusted_mode =
5875 &intel_crtc->config.adjusted_mode;
5876 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5877 int pipe = intel_crtc->pipe;
5878 int plane = intel_crtc->plane;
5879 int num_connectors = 0;
8b47047b 5880 bool is_cpu_edp = false;
09b4ddf9 5881 struct intel_encoder *encoder;
09b4ddf9 5882 int ret;
09b4ddf9
PZ		 5883
5884 for_each_encoder_on_crtc(dev, crtc, encoder) {
5885 switch (encoder->type) {
09b4ddf9 5886 case INTEL_OUTPUT_EDP:
d8e8b582 5887 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5888 is_cpu_edp = true;
5889 break;
5890 }
5891
5892 num_connectors++;
5893 }
5894
5dc5298b
PZ		 5895 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5896 num_connectors, pipe_name(pipe));
5897
6441ab5f
PZ		 5898 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5899 return -EINVAL;
5900
09b4ddf9
PZ		 5901 /* Ensure that the cursor is valid for the new mode before changing... */
5902 intel_crtc_update_cursor(crtc, true);
5903
03afc4a2
DV		 5904 if (intel_crtc->config.has_dp_encoder)
5905 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5906
5907 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5908
5909 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5910
ca3a0ff8 5911 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5912 intel_cpu_transcoder_set_m_n(intel_crtc,
5913 &intel_crtc->config.fdi_m_n);
5914 }
09b4ddf9 5915
6ff93609 5916 haswell_set_pipeconf(crtc);
09b4ddf9 5917
50f3b016 5918 intel_set_pipe_csc(crtc);
86d3efce 5919
09b4ddf9 5920 /* Set up the display plane register */
86d3efce 5921 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5922 POSTING_READ(DSPCNTR(plane));
5923
5924 ret = intel_pipe_set_base(crtc, x, y, fb);
5925
5926 intel_update_watermarks(dev);
5927
1f803ee5 5928 return ret;
79e53945
JB		 5929}
5930
0e8ffe1b
DV		 5931static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5932 struct intel_crtc_config *pipe_config)
5933{
5934 struct drm_device *dev = crtc->base.dev;
5935 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5936 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5937 uint32_t tmp;
5938
eccb140b
DV		 5939 pipe_config->cpu_transcoder = crtc->pipe;
5940 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5941 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5942 enum pipe trans_edp_pipe;
5943 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5944 default:
5945 WARN(1, "unknown pipe linked to edp transcoder\n");
5946 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5947 case TRANS_DDI_EDP_INPUT_A_ON:
5948 trans_edp_pipe = PIPE_A;
5949 break;
5950 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5951 trans_edp_pipe = PIPE_B;
5952 break;
5953 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5954 trans_edp_pipe = PIPE_C;
5955 break;
5956 }
5957
5958 if (trans_edp_pipe == crtc->pipe)
5959 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5960 }
5961
b97186f0 5962 if (!intel_display_power_enabled(dev,
eccb140b 5963 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5964 return false;
5965
eccb140b 5966 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5967 if (!(tmp & PIPECONF_ENABLE))
5968 return false;
5969
88adfff1 5970 /*
f196e6be 5971 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5972 * DDI E. So just check whether this pipe is wired to DDI E and whether
5973 * the PCH transcoder is on.
5974 */
eccb140b 5975 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5976 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5977 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5978 pipe_config->has_pch_encoder = true;
5979
627eb5a3
DV		 5980 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5981 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5982 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5983
5984 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5985 }
5986
1bd1bd80
DV		 5987 intel_get_pipe_timings(crtc, pipe_config);
5988
2fa2fe9a
DV		 5989 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5990 if (intel_display_power_enabled(dev, pfit_domain))
5991 ironlake_get_pfit_config(crtc, pipe_config);
5992
42db64ef
PZ		 5993 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5994 (I915_READ(IPS_CTL) & IPS_ENABLE);
5995
0e8ffe1b
DV		 5996 return true;
5997}
5998
f564048e 5999static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6000 int x, int y,
94352cf9 6001 struct drm_framebuffer *fb)
f564048e
EA		 6002{
6003 struct drm_device *dev = crtc->dev;
6004 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6005 struct drm_encoder_helper_funcs *encoder_funcs;
6006 struct intel_encoder *encoder;
0b701d27 6007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6008 struct drm_display_mode *adjusted_mode =
6009 &intel_crtc->config.adjusted_mode;
6010 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6011 int pipe = intel_crtc->pipe;
f564048e
EA		 6012 int ret;
6013
0b701d27 6014 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6015
b8cecdf5
DV		 6016 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6017
79e53945 6018 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6019
9256aa19
DV		 6020 if (ret != 0)
6021 return ret;
6022
6023 for_each_encoder_on_crtc(dev, crtc, encoder) {
6024 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6025 encoder->base.base.id,
6026 drm_get_encoder_name(&encoder->base),
6027 mode->base.id, mode->name);
6cc5f341
DV		 6028 if (encoder->mode_set) {
6029 encoder->mode_set(encoder);
6030 } else {
6031 encoder_funcs = encoder->base.helper_private;
6032 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6033 }
9256aa19
DV		 6034 }
6035
6036 return 0;
79e53945
JB		 6037}
6038
3a9627f4
WF		 6039static bool intel_eld_uptodate(struct drm_connector *connector,
6040 int reg_eldv, uint32_t bits_eldv,
6041 int reg_elda, uint32_t bits_elda,
6042 int reg_edid)
6043{
6044 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6045 uint8_t *eld = connector->eld;
6046 uint32_t i;
6047
6048 i = I915_READ(reg_eldv);
6049 i &= bits_eldv;
6050
6051 if (!eld[0])
6052 return !i;
6053
6054 if (!i)
6055 return false;
6056
6057 i = I915_READ(reg_elda);
6058 i &= ~bits_elda;
6059 I915_WRITE(reg_elda, i);
6060
6061 for (i = 0; i < eld[2]; i++)
6062 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6063 return false;
6064
6065 return true;
6066}
6067
e0dac65e
WF		 6068static void g4x_write_eld(struct drm_connector *connector,
6069 struct drm_crtc *crtc)
6070{
6071 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6072 uint8_t *eld = connector->eld;
6073 uint32_t eldv;
6074 uint32_t len;
6075 uint32_t i;
6076
6077 i = I915_READ(G4X_AUD_VID_DID);
6078
6079 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6080 eldv = G4X_ELDV_DEVCL_DEVBLC;
6081 else
6082 eldv = G4X_ELDV_DEVCTG;
6083
3a9627f4
WF		 6084 if (intel_eld_uptodate(connector,
6085 G4X_AUD_CNTL_ST, eldv,
6086 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6087 G4X_HDMIW_HDMIEDID))
6088 return;
6089
e0dac65e
WF		 6090 i = I915_READ(G4X_AUD_CNTL_ST);
6091 i &= ~(eldv | G4X_ELD_ADDR);
6092 len = (i >> 9) & 0x1f; /* ELD buffer size */
6093 I915_WRITE(G4X_AUD_CNTL_ST, i);
6094
6095 if (!eld[0])
6096 return;
6097
6098 len = min_t(uint8_t, eld[2], len);
6099 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6100 for (i = 0; i < len; i++)
6101 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6102
6103 i = I915_READ(G4X_AUD_CNTL_ST);
6104 i |= eldv;
6105 I915_WRITE(G4X_AUD_CNTL_ST, i);
6106}
6107
83358c85
WX		 6108static void haswell_write_eld(struct drm_connector *connector,
6109 struct drm_crtc *crtc)
6110{
6111 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6112 uint8_t *eld = connector->eld;
6113 struct drm_device *dev = crtc->dev;
7b9f35a6 6114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6115 uint32_t eldv;
6116 uint32_t i;
6117 int len;
6118 int pipe = to_intel_crtc(crtc)->pipe;
6119 int tmp;
6120
6121 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6122 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6123 int aud_config = HSW_AUD_CFG(pipe);
6124 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6125
6126
6127 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6128
6129 /* Audio output enable */
6130 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6131 tmp = I915_READ(aud_cntrl_st2);
6132 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6133 I915_WRITE(aud_cntrl_st2, tmp);
6134
6135 /* Wait for 1 vertical blank */
6136 intel_wait_for_vblank(dev, pipe);
6137
6138 /* Set ELD valid state */
6139 tmp = I915_READ(aud_cntrl_st2);
6140 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6141 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6142 I915_WRITE(aud_cntrl_st2, tmp);
6143 tmp = I915_READ(aud_cntrl_st2);
6144 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6145
6146 /* Enable HDMI mode */
6147 tmp = I915_READ(aud_config);
6148 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6149 /* clear N_programing_enable and N_value_index */
6150 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6151 I915_WRITE(aud_config, tmp);
6152
6153 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6154
6155 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6156 intel_crtc->eld_vld = true;
83358c85
WX		 6157
6158 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6159 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6160 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6161 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6162 } else
6163 I915_WRITE(aud_config, 0);
6164
6165 if (intel_eld_uptodate(connector,
6166 aud_cntrl_st2, eldv,
6167 aud_cntl_st, IBX_ELD_ADDRESS,
6168 hdmiw_hdmiedid))
6169 return;
6170
6171 i = I915_READ(aud_cntrl_st2);
6172 i &= ~eldv;
6173 I915_WRITE(aud_cntrl_st2, i);
6174
6175 if (!eld[0])
6176 return;
6177
6178 i = I915_READ(aud_cntl_st);
6179 i &= ~IBX_ELD_ADDRESS;
6180 I915_WRITE(aud_cntl_st, i);
6181 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6182 DRM_DEBUG_DRIVER("port num:%d\n", i);
6183
6184 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6185 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6186 for (i = 0; i < len; i++)
6187 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6188
6189 i = I915_READ(aud_cntrl_st2);
6190 i |= eldv;
6191 I915_WRITE(aud_cntrl_st2, i);
6192
6193}
6194
e0dac65e
WF		 6195static void ironlake_write_eld(struct drm_connector *connector,
6196 struct drm_crtc *crtc)
6197{
6198 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6199 uint8_t *eld = connector->eld;
6200 uint32_t eldv;
6201 uint32_t i;
6202 int len;
6203 int hdmiw_hdmiedid;
b6daa025 6204 int aud_config;
e0dac65e
WF		 6205 int aud_cntl_st;
6206 int aud_cntrl_st2;
9b138a83 6207 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6208
b3f33cbf 6209 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6210 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6211 aud_config = IBX_AUD_CFG(pipe);
6212 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6213 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6214 } else {
9b138a83
WX		 6215 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6216 aud_config = CPT_AUD_CFG(pipe);
6217 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6218 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6219 }
6220
9b138a83 6221 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6222
6223 i = I915_READ(aud_cntl_st);
9b138a83 6224 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6225 if (!i) {
6226 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6227 /* operate blindly on all ports */
1202b4c6
WF		 6228 eldv = IBX_ELD_VALIDB;
6229 eldv |= IBX_ELD_VALIDB << 4;
6230 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6231 } else {
2582a850 6232 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6233 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6234 }
6235
3a9627f4
WF		 6236 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6237 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6238 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6239 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6240 } else
6241 I915_WRITE(aud_config, 0);
e0dac65e 6242
3a9627f4
WF		 6243 if (intel_eld_uptodate(connector,
6244 aud_cntrl_st2, eldv,
6245 aud_cntl_st, IBX_ELD_ADDRESS,
6246 hdmiw_hdmiedid))
6247 return;
6248
e0dac65e
WF		 6249 i = I915_READ(aud_cntrl_st2);
6250 i &= ~eldv;
6251 I915_WRITE(aud_cntrl_st2, i);
6252
6253 if (!eld[0])
6254 return;
6255
e0dac65e 6256 i = I915_READ(aud_cntl_st);
1202b4c6 6257 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6258 I915_WRITE(aud_cntl_st, i);
6259
6260 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6261 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6262 for (i = 0; i < len; i++)
6263 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6264
6265 i = I915_READ(aud_cntrl_st2);
6266 i |= eldv;
6267 I915_WRITE(aud_cntrl_st2, i);
6268}
6269
6270void intel_write_eld(struct drm_encoder *encoder,
6271 struct drm_display_mode *mode)
6272{
6273 struct drm_crtc *crtc = encoder->crtc;
6274 struct drm_connector *connector;
6275 struct drm_device *dev = encoder->dev;
6276 struct drm_i915_private *dev_priv = dev->dev_private;
6277
6278 connector = drm_select_eld(encoder, mode);
6279 if (!connector)
6280 return;
6281
6282 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6283 connector->base.id,
6284 drm_get_connector_name(connector),
6285 connector->encoder->base.id,
6286 drm_get_encoder_name(connector->encoder));
6287
6288 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6289
6290 if (dev_priv->display.write_eld)
6291 dev_priv->display.write_eld(connector, crtc);
6292}
6293
79e53945
JB		 6294/** Loads the palette/gamma unit for the CRTC with the prepared values */
6295void intel_crtc_load_lut(struct drm_crtc *crtc)
6296{
6297 struct drm_device *dev = crtc->dev;
6298 struct drm_i915_private *dev_priv = dev->dev_private;
6299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6300 enum pipe pipe = intel_crtc->pipe;
6301 int palreg = PALETTE(pipe);
79e53945 6302 int i;
42db64ef 6303 bool reenable_ips = false;
79e53945
JB		 6304
6305 /* The clocks have to be on to load the palette. */
aed3f09d 6306 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6307 return;
6308
f2b115e6 6309 /* use legacy palette for Ironlake */
bad720ff 6310 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6311 palreg = LGC_PALETTE(pipe);
6312
6313 /* Workaround : Do not read or write the pipe palette/gamma data while
6314 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6315 */
6316 if (intel_crtc->config.ips_enabled &&
6317 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6318 GAMMA_MODE_MODE_SPLIT)) {
6319 hsw_disable_ips(intel_crtc);
6320 reenable_ips = true;
6321 }
2c07245f 6322
79e53945
JB		 6323 for (i = 0; i < 256; i++) {
6324 I915_WRITE(palreg + 4 * i,
6325 (intel_crtc->lut_r[i] << 16) |
6326 (intel_crtc->lut_g[i] << 8) |
6327 intel_crtc->lut_b[i]);
6328 }
42db64ef
PZ		 6329
6330 if (reenable_ips)
6331 hsw_enable_ips(intel_crtc);
79e53945
JB		 6332}
6333
560b85bb
CW		 6334static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6335{
6336 struct drm_device *dev = crtc->dev;
6337 struct drm_i915_private *dev_priv = dev->dev_private;
6338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6339 bool visible = base != 0;
6340 u32 cntl;
6341
6342 if (intel_crtc->cursor_visible == visible)
6343 return;
6344
9db4a9c7 6345 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6346 if (visible) {
6347 /* On these chipsets we can only modify the base whilst
6348 * the cursor is disabled.
6349 */
9db4a9c7 6350 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6351
6352 cntl &= ~(CURSOR_FORMAT_MASK);
6353 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6354 cntl |= CURSOR_ENABLE |
6355 CURSOR_GAMMA_ENABLE |
6356 CURSOR_FORMAT_ARGB;
6357 } else
6358 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6359 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6360
6361 intel_crtc->cursor_visible = visible;
6362}
6363
6364static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6365{
6366 struct drm_device *dev = crtc->dev;
6367 struct drm_i915_private *dev_priv = dev->dev_private;
6368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6369 int pipe = intel_crtc->pipe;
6370 bool visible = base != 0;
6371
6372 if (intel_crtc->cursor_visible != visible) {
548f245b 6373 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6374 if (base) {
6375 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6376 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6377 cntl |= pipe << 28; /* Connect to correct pipe */
6378 } else {
6379 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6380 cntl |= CURSOR_MODE_DISABLE;
6381 }
9db4a9c7 6382 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6383
6384 intel_crtc->cursor_visible = visible;
6385 }
6386 /* and commit changes on next vblank */
9db4a9c7 6387 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6388}
6389
65a21cd6
JB		 6390static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6391{
6392 struct drm_device *dev = crtc->dev;
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6395 int pipe = intel_crtc->pipe;
6396 bool visible = base != 0;
6397
6398 if (intel_crtc->cursor_visible != visible) {
6399 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6400 if (base) {
6401 cntl &= ~CURSOR_MODE;
6402 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6403 } else {
6404 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6405 cntl |= CURSOR_MODE_DISABLE;
6406 }
86d3efce
VS		 6407 if (IS_HASWELL(dev))
6408 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6409 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6410
6411 intel_crtc->cursor_visible = visible;
6412 }
6413 /* and commit changes on next vblank */
6414 I915_WRITE(CURBASE_IVB(pipe), base);
6415}
6416
cda4b7d3 6417/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6418static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6419 bool on)
cda4b7d3
CW		 6420{
6421 struct drm_device *dev = crtc->dev;
6422 struct drm_i915_private *dev_priv = dev->dev_private;
6423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6424 int pipe = intel_crtc->pipe;
6425 int x = intel_crtc->cursor_x;
6426 int y = intel_crtc->cursor_y;
560b85bb 6427 u32 base, pos;
cda4b7d3
CW		 6428 bool visible;
6429
6430 pos = 0;
6431
6b383a7f 6432 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6433 base = intel_crtc->cursor_addr;
6434 if (x > (int) crtc->fb->width)
6435 base = 0;
6436
6437 if (y > (int) crtc->fb->height)
6438 base = 0;
6439 } else
6440 base = 0;
6441
6442 if (x < 0) {
6443 if (x + intel_crtc->cursor_width < 0)
6444 base = 0;
6445
6446 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6447 x = -x;
6448 }
6449 pos |= x << CURSOR_X_SHIFT;
6450
6451 if (y < 0) {
6452 if (y + intel_crtc->cursor_height < 0)
6453 base = 0;
6454
6455 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6456 y = -y;
6457 }
6458 pos |= y << CURSOR_Y_SHIFT;
6459
6460 visible = base != 0;
560b85bb 6461 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6462 return;
6463
0cd83aa9 6464 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6465 I915_WRITE(CURPOS_IVB(pipe), pos);
6466 ivb_update_cursor(crtc, base);
6467 } else {
6468 I915_WRITE(CURPOS(pipe), pos);
6469 if (IS_845G(dev) || IS_I865G(dev))
6470 i845_update_cursor(crtc, base);
6471 else
6472 i9xx_update_cursor(crtc, base);
6473 }
cda4b7d3
CW		 6474}
6475
79e53945 6476static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6477 struct drm_file *file,
79e53945
JB		 6478 uint32_t handle,
6479 uint32_t width, uint32_t height)
6480{
6481 struct drm_device *dev = crtc->dev;
6482 struct drm_i915_private *dev_priv = dev->dev_private;
6483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6484 struct drm_i915_gem_object *obj;
cda4b7d3 6485 uint32_t addr;
3f8bc370 6486 int ret;
79e53945 6487
79e53945
JB		 6488 /* if we want to turn off the cursor ignore width and height */
6489 if (!handle) {
28c97730 6490 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6491 addr = 0;
05394f39 6492 obj = NULL;
5004417d 6493 mutex_lock(&dev->struct_mutex);
3f8bc370 6494 goto finish;
79e53945
JB		 6495 }
6496
6497 /* Currently we only support 64x64 cursors */
6498 if (width != 64 || height != 64) {
6499 DRM_ERROR("we currently only support 64x64 cursors\n");
6500 return -EINVAL;
6501 }
6502
05394f39 6503 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6504 if (&obj->base == NULL)
79e53945
JB		 6505 return -ENOENT;
6506
05394f39 6507 if (obj->base.size < width * height * 4) {
79e53945 6508 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6509 ret = -ENOMEM;
6510 goto fail;
79e53945
JB		 6511 }
6512
71acb5eb 6513 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6514 mutex_lock(&dev->struct_mutex);
b295d1b6 6515 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6516 unsigned alignment;
6517
d9e86c0e
CW		 6518 if (obj->tiling_mode) {
6519 DRM_ERROR("cursor cannot be tiled\n");
6520 ret = -EINVAL;
6521 goto fail_locked;
6522 }
6523
693db184
CW		 6524 /* Note that the w/a also requires 2 PTE of padding following
6525 * the bo. We currently fill all unused PTE with the shadow
6526 * page and so we should always have valid PTE following the
6527 * cursor preventing the VT-d warning.
6528 */
6529 alignment = 0;
6530 if (need_vtd_wa(dev))
6531 alignment = 64*1024;
6532
6533 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6534 if (ret) {
6535 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6536 goto fail_locked;
e7b526bb
CW		 6537 }
6538
d9e86c0e
CW		 6539 ret = i915_gem_object_put_fence(obj);
6540 if (ret) {
2da3b9b9 6541 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6542 goto fail_unpin;
6543 }
6544
05394f39 6545 addr = obj->gtt_offset;
71acb5eb 6546 } else {
6eeefaf3 6547 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6548 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6549 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6550 align);
71acb5eb
DA		 6551 if (ret) {
6552 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6553 goto fail_locked;
71acb5eb 6554 }
05394f39 6555 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6556 }
6557
a6c45cf0 6558 if (IS_GEN2(dev))
14b60391
JB		 6559 I915_WRITE(CURSIZE, (height << 12) | width);
6560
3f8bc370 6561 finish:
3f8bc370 6562 if (intel_crtc->cursor_bo) {
b295d1b6 6563 if (dev_priv->info->cursor_needs_physical) {
05394f39 6564 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6565 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6566 } else
6567 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6568 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6569 }
80824003 6570
7f9872e0 6571 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6572
6573 intel_crtc->cursor_addr = addr;
05394f39 6574 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6575 intel_crtc->cursor_width = width;
6576 intel_crtc->cursor_height = height;
6577
40ccc72b 6578 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6579
79e53945 6580 return 0;
e7b526bb 6581fail_unpin:
05394f39 6582 i915_gem_object_unpin(obj);
7f9872e0 6583fail_locked:
34b8686e 6584 mutex_unlock(&dev->struct_mutex);
bc9025bd 6585fail:
05394f39 6586 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6587 return ret;
79e53945
JB		 6588}
6589
6590static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6591{
79e53945 6592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6593
cda4b7d3
CW		 6594 intel_crtc->cursor_x = x;
6595 intel_crtc->cursor_y = y;
652c393a 6596
40ccc72b 6597 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6598
6599 return 0;
6600}
6601
6602/** Sets the color ramps on behalf of RandR */
6603void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6604 u16 blue, int regno)
6605{
6606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6607
6608 intel_crtc->lut_r[regno] = red >> 8;
6609 intel_crtc->lut_g[regno] = green >> 8;
6610 intel_crtc->lut_b[regno] = blue >> 8;
6611}
6612
b8c00ac5
DA		 6613void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6614 u16 *blue, int regno)
6615{
6616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6617
6618 *red = intel_crtc->lut_r[regno] << 8;
6619 *green = intel_crtc->lut_g[regno] << 8;
6620 *blue = intel_crtc->lut_b[regno] << 8;
6621}
6622
79e53945 6623static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6624 u16 *blue, uint32_t start, uint32_t size)
79e53945 6625{
7203425a 6626 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6628
7203425a 6629 for (i = start; i < end; i++) {
79e53945
JB		 6630 intel_crtc->lut_r[i] = red[i] >> 8;
6631 intel_crtc->lut_g[i] = green[i] >> 8;
6632 intel_crtc->lut_b[i] = blue[i] >> 8;
6633 }
6634
6635 intel_crtc_load_lut(crtc);
6636}
6637
79e53945
JB		 6638/* VESA 640x480x72Hz mode to set on the pipe */
6639static struct drm_display_mode load_detect_mode = {
6640 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6641 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6642};
6643
d2dff872
CW		 6644static struct drm_framebuffer *
6645intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6646 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6647 struct drm_i915_gem_object *obj)
6648{
6649 struct intel_framebuffer *intel_fb;
6650 int ret;
6651
6652 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6653 if (!intel_fb) {
6654 drm_gem_object_unreference_unlocked(&obj->base);
6655 return ERR_PTR(-ENOMEM);
6656 }
6657
6658 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6659 if (ret) {
6660 drm_gem_object_unreference_unlocked(&obj->base);
6661 kfree(intel_fb);
6662 return ERR_PTR(ret);
6663 }
6664
6665 return &intel_fb->base;
6666}
6667
6668static u32
6669intel_framebuffer_pitch_for_width(int width, int bpp)
6670{
6671 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6672 return ALIGN(pitch, 64);
6673}
6674
6675static u32
6676intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6677{
6678 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6679 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6680}
6681
6682static struct drm_framebuffer *
6683intel_framebuffer_create_for_mode(struct drm_device *dev,
6684 struct drm_display_mode *mode,
6685 int depth, int bpp)
6686{
6687 struct drm_i915_gem_object *obj;
0fed39bd 6688 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6689
6690 obj = i915_gem_alloc_object(dev,
6691 intel_framebuffer_size_for_mode(mode, bpp));
6692 if (obj == NULL)
6693 return ERR_PTR(-ENOMEM);
6694
6695 mode_cmd.width = mode->hdisplay;
6696 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6697 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6698 bpp);
5ca0c34a 6699 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6700
6701 return intel_framebuffer_create(dev, &mode_cmd, obj);
6702}
6703
6704static struct drm_framebuffer *
6705mode_fits_in_fbdev(struct drm_device *dev,
6706 struct drm_display_mode *mode)
6707{
6708 struct drm_i915_private *dev_priv = dev->dev_private;
6709 struct drm_i915_gem_object *obj;
6710 struct drm_framebuffer *fb;
6711
6712 if (dev_priv->fbdev == NULL)
6713 return NULL;
6714
6715 obj = dev_priv->fbdev->ifb.obj;
6716 if (obj == NULL)
6717 return NULL;
6718
6719 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6720 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6721 fb->bits_per_pixel))
d2dff872
CW		 6722 return NULL;
6723
01f2c773 6724 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6725 return NULL;
6726
6727 return fb;
6728}
6729
d2434ab7 6730bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6731 struct drm_display_mode *mode,
8261b191 6732 struct intel_load_detect_pipe *old)
79e53945
JB		 6733{
6734 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6735 struct intel_encoder *intel_encoder =
6736 intel_attached_encoder(connector);
79e53945 6737 struct drm_crtc *possible_crtc;
4ef69c7a 6738 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6739 struct drm_crtc *crtc = NULL;
6740 struct drm_device *dev = encoder->dev;
94352cf9 6741 struct drm_framebuffer *fb;
79e53945
JB		 6742 int i = -1;
6743
d2dff872
CW		 6744 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6745 connector->base.id, drm_get_connector_name(connector),
6746 encoder->base.id, drm_get_encoder_name(encoder));
6747
79e53945
JB		 6748 /*
6749 * Algorithm gets a little messy:
7a5e4805 6750 *
79e53945
JB		 6751 * - if the connector already has an assigned crtc, use it (but make
6752 * sure it's on first)
7a5e4805 6753 *
79e53945
JB		 6754 * - try to find the first unused crtc that can drive this connector,
6755 * and use that if we find one
79e53945
JB		 6756 */
6757
6758 /* See if we already have a CRTC for this connector */
6759 if (encoder->crtc) {
6760 crtc = encoder->crtc;
8261b191 6761
7b24056b
DV		 6762 mutex_lock(&crtc->mutex);
6763
24218aac 6764 old->dpms_mode = connector->dpms;
8261b191
CW		 6765 old->load_detect_temp = false;
6766
6767 /* Make sure the crtc and connector are running */
24218aac
DV		 6768 if (connector->dpms != DRM_MODE_DPMS_ON)
6769 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6770
7173188d 6771 return true;
79e53945
JB		 6772 }
6773
6774 /* Find an unused one (if possible) */
6775 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6776 i++;
6777 if (!(encoder->possible_crtcs & (1 << i)))
6778 continue;
6779 if (!possible_crtc->enabled) {
6780 crtc = possible_crtc;
6781 break;
6782 }
79e53945
JB		 6783 }
6784
6785 /*
6786 * If we didn't find an unused CRTC, don't use any.
6787 */
6788 if (!crtc) {
7173188d
CW		 6789 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6790 return false;
79e53945
JB		 6791 }
6792
7b24056b 6793 mutex_lock(&crtc->mutex);
fc303101
DV		 6794 intel_encoder->new_crtc = to_intel_crtc(crtc);
6795 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6796
6797 intel_crtc = to_intel_crtc(crtc);
24218aac 6798 old->dpms_mode = connector->dpms;
8261b191 6799 old->load_detect_temp = true;
d2dff872 6800 old->release_fb = NULL;
79e53945 6801
6492711d
CW		 6802 if (!mode)
6803 mode = &load_detect_mode;
79e53945 6804
d2dff872
CW		 6805 /* We need a framebuffer large enough to accommodate all accesses
6806 * that the plane may generate whilst we perform load detection.
6807 * We can not rely on the fbcon either being present (we get called
6808 * during its initialisation to detect all boot displays, or it may
6809 * not even exist) or that it is large enough to satisfy the
6810 * requested mode.
6811 */
94352cf9
DV		 6812 fb = mode_fits_in_fbdev(dev, mode);
6813 if (fb == NULL) {
d2dff872 6814 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6815 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6816 old->release_fb = fb;
d2dff872
CW		 6817 } else
6818 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6819 if (IS_ERR(fb)) {
d2dff872 6820 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6821 mutex_unlock(&crtc->mutex);
0e8b3d3e 6822 return false;
79e53945 6823 }
79e53945 6824
c0c36b94 6825 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6826 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6827 if (old->release_fb)
6828 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6829 mutex_unlock(&crtc->mutex);
0e8b3d3e 6830 return false;
79e53945 6831 }
7173188d 6832
79e53945 6833 /* let the connector get through one full cycle before testing */
9d0498a2 6834 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6835 return true;
79e53945
JB		 6836}
6837
d2434ab7 6838void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6839 struct intel_load_detect_pipe *old)
79e53945 6840{
d2434ab7
DV		 6841 struct intel_encoder *intel_encoder =
6842 intel_attached_encoder(connector);
4ef69c7a 6843 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6844 struct drm_crtc *crtc = encoder->crtc;
79e53945 6845
d2dff872
CW		 6846 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6847 connector->base.id, drm_get_connector_name(connector),
6848 encoder->base.id, drm_get_encoder_name(encoder));
6849
8261b191 6850 if (old->load_detect_temp) {
fc303101
DV		 6851 to_intel_connector(connector)->new_encoder = NULL;
6852 intel_encoder->new_crtc = NULL;
6853 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6854
36206361
DV		 6855 if (old->release_fb) {
6856 drm_framebuffer_unregister_private(old->release_fb);
6857 drm_framebuffer_unreference(old->release_fb);
6858 }
d2dff872 6859
67c96400 6860 mutex_unlock(&crtc->mutex);
0622a53c 6861 return;
79e53945
JB		 6862 }
6863
c751ce4f 6864 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6865 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6866 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6867
6868 mutex_unlock(&crtc->mutex);
79e53945
JB		 6869}
6870
6871/* Returns the clock of the currently programmed mode of the given pipe. */
6872static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6873{
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6876 int pipe = intel_crtc->pipe;
548f245b 6877 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6878 u32 fp;
6879 intel_clock_t clock;
6880
6881 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6882 fp = I915_READ(FP0(pipe));
79e53945 6883 else
39adb7a5 6884 fp = I915_READ(FP1(pipe));
79e53945
JB		 6885
6886 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6887 if (IS_PINEVIEW(dev)) {
6888 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6889 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6890 } else {
6891 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6892 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6893 }
6894
a6c45cf0 6895 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6896 if (IS_PINEVIEW(dev))
6897 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6898 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6899 else
6900 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6901 DPLL_FPA01_P1_POST_DIV_SHIFT);
6902
6903 switch (dpll & DPLL_MODE_MASK) {
6904 case DPLLB_MODE_DAC_SERIAL:
6905 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6906 5 : 10;
6907 break;
6908 case DPLLB_MODE_LVDS:
6909 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6910 7 : 14;
6911 break;
6912 default:
28c97730 6913 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6914 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6915 return 0;
6916 }
6917
ac58c3f0
DV		 6918 if (IS_PINEVIEW(dev))
6919 pineview_clock(96000, &clock);
6920 else
6921 i9xx_clock(96000, &clock);
79e53945
JB		 6922 } else {
6923 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6924
6925 if (is_lvds) {
6926 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6927 DPLL_FPA01_P1_POST_DIV_SHIFT);
6928 clock.p2 = 14;
6929
6930 if ((dpll & PLL_REF_INPUT_MASK) ==
6931 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6932 /* XXX: might not be 66MHz */
ac58c3f0 6933 i9xx_clock(66000, &clock);
79e53945 6934 } else
ac58c3f0 6935 i9xx_clock(48000, &clock);
79e53945
JB		 6936 } else {
6937 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6938 clock.p1 = 2;
6939 else {
6940 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6941 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6942 }
6943 if (dpll & PLL_P2_DIVIDE_BY_4)
6944 clock.p2 = 4;
6945 else
6946 clock.p2 = 2;
6947
ac58c3f0 6948 i9xx_clock(48000, &clock);
79e53945
JB		 6949 }
6950 }
6951
6952 /* XXX: It would be nice to validate the clocks, but we can't reuse
6953 * i830PllIsValid() because it relies on the xf86_config connector
6954 * configuration being accurate, which it isn't necessarily.
6955 */
6956
6957 return clock.dot;
6958}
6959
6960/** Returns the currently programmed mode of the given pipe. */
6961struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6962 struct drm_crtc *crtc)
6963{
548f245b 6964 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6966 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6967 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6968 int htot = I915_READ(HTOTAL(cpu_transcoder));
6969 int hsync = I915_READ(HSYNC(cpu_transcoder));
6970 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6971 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6972
6973 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6974 if (!mode)
6975 return NULL;
6976
6977 mode->clock = intel_crtc_clock_get(dev, crtc);
6978 mode->hdisplay = (htot & 0xffff) + 1;
6979 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6980 mode->hsync_start = (hsync & 0xffff) + 1;
6981 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6982 mode->vdisplay = (vtot & 0xffff) + 1;
6983 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6984 mode->vsync_start = (vsync & 0xffff) + 1;
6985 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6986
6987 drm_mode_set_name(mode);
79e53945
JB		 6988
6989 return mode;
6990}
6991
3dec0095 6992static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6993{
6994 struct drm_device *dev = crtc->dev;
6995 drm_i915_private_t *dev_priv = dev->dev_private;
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6997 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6998 int dpll_reg = DPLL(pipe);
6999 int dpll;
652c393a 7000
bad720ff 7001 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7002 return;
7003
7004 if (!dev_priv->lvds_downclock_avail)
7005 return;
7006
dbdc6479 7007 dpll = I915_READ(dpll_reg);
652c393a 7008 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7009 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7010
8ac5a6d5 7011 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7012
7013 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7014 I915_WRITE(dpll_reg, dpll);
9d0498a2 7015 intel_wait_for_vblank(dev, pipe);
dbdc6479 7016
652c393a
JB		 7017 dpll = I915_READ(dpll_reg);
7018 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7019 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7020 }
652c393a
JB		 7021}
7022
7023static void intel_decrease_pllclock(struct drm_crtc *crtc)
7024{
7025 struct drm_device *dev = crtc->dev;
7026 drm_i915_private_t *dev_priv = dev->dev_private;
7027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7028
bad720ff 7029 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7030 return;
7031
7032 if (!dev_priv->lvds_downclock_avail)
7033 return;
7034
7035 /*
7036 * Since this is called by a timer, we should never get here in
7037 * the manual case.
7038 */
7039 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7040 int pipe = intel_crtc->pipe;
7041 int dpll_reg = DPLL(pipe);
7042 int dpll;
f6e5b160 7043
44d98a61 7044 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7045
8ac5a6d5 7046 assert_panel_unlocked(dev_priv, pipe);
652c393a 7047
dc257cf1 7048 dpll = I915_READ(dpll_reg);
652c393a
JB		 7049 dpll |= DISPLAY_RATE_SELECT_FPA1;
7050 I915_WRITE(dpll_reg, dpll);
9d0498a2 7051 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7052 dpll = I915_READ(dpll_reg);
7053 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7054 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7055 }
7056
7057}
7058
f047e395
CW		 7059void intel_mark_busy(struct drm_device *dev)
7060{
f047e395
CW		 7061 i915_update_gfx_val(dev->dev_private);
7062}
7063
7064void intel_mark_idle(struct drm_device *dev)
652c393a 7065{
652c393a 7066 struct drm_crtc *crtc;
652c393a
JB		 7067
7068 if (!i915_powersave)
7069 return;
7070
652c393a 7071 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7072 if (!crtc->fb)
7073 continue;
7074
725a5b54 7075 intel_decrease_pllclock(crtc);
652c393a 7076 }
652c393a
JB		 7077}
7078
725a5b54 7079void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7080{
f047e395
CW		 7081 struct drm_device *dev = obj->base.dev;
7082 struct drm_crtc *crtc;
652c393a 7083
f047e395 7084 if (!i915_powersave)
acb87dfb
CW		 7085 return;
7086
652c393a
JB		 7087 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7088 if (!crtc->fb)
7089 continue;
7090
f047e395 7091 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7092 intel_increase_pllclock(crtc);
652c393a
JB		 7093 }
7094}
7095
79e53945
JB		 7096static void intel_crtc_destroy(struct drm_crtc *crtc)
7097{
7098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7099 struct drm_device *dev = crtc->dev;
7100 struct intel_unpin_work *work;
7101 unsigned long flags;
7102
7103 spin_lock_irqsave(&dev->event_lock, flags);
7104 work = intel_crtc->unpin_work;
7105 intel_crtc->unpin_work = NULL;
7106 spin_unlock_irqrestore(&dev->event_lock, flags);
7107
7108 if (work) {
7109 cancel_work_sync(&work->work);
7110 kfree(work);
7111 }
79e53945 7112
40ccc72b
MK		 7113 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7114
79e53945 7115 drm_crtc_cleanup(crtc);
67e77c5a 7116
79e53945
JB		 7117 kfree(intel_crtc);
7118}
7119
6b95a207
KH		 7120static void intel_unpin_work_fn(struct work_struct *__work)
7121{
7122 struct intel_unpin_work *work =
7123 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7124 struct drm_device *dev = work->crtc->dev;
6b95a207 7125
b4a98e57 7126 mutex_lock(&dev->struct_mutex);
1690e1eb 7127 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7128 drm_gem_object_unreference(&work->pending_flip_obj->base);
7129 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7130
b4a98e57
CW		 7131 intel_update_fbc(dev);
7132 mutex_unlock(&dev->struct_mutex);
7133
7134 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7135 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7136
6b95a207
KH		 7137 kfree(work);
7138}
7139
1afe3e9d 7140static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7141 struct drm_crtc *crtc)
6b95a207
KH		 7142{
7143 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7145 struct intel_unpin_work *work;
6b95a207
KH		 7146 unsigned long flags;
7147
7148 /* Ignore early vblank irqs */
7149 if (intel_crtc == NULL)
7150 return;
7151
7152 spin_lock_irqsave(&dev->event_lock, flags);
7153 work = intel_crtc->unpin_work;
e7d841ca
CW		 7154
7155 /* Ensure we don't miss a work->pending update ... */
7156 smp_rmb();
7157
7158 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7159 spin_unlock_irqrestore(&dev->event_lock, flags);
7160 return;
7161 }
7162
e7d841ca
CW		 7163 /* and that the unpin work is consistent wrt ->pending. */
7164 smp_rmb();
7165
6b95a207 7166 intel_crtc->unpin_work = NULL;
6b95a207 7167
45a066eb
RC		 7168 if (work->event)
7169 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7170
0af7e4df
MK		 7171 drm_vblank_put(dev, intel_crtc->pipe);
7172
6b95a207
KH		 7173 spin_unlock_irqrestore(&dev->event_lock, flags);
7174
2c10d571 7175 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7176
7177 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7178
7179 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7180}
7181
1afe3e9d
JB		 7182void intel_finish_page_flip(struct drm_device *dev, int pipe)
7183{
7184 drm_i915_private_t *dev_priv = dev->dev_private;
7185 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7186
49b14a5c 7187 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7188}
7189
7190void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7191{
7192 drm_i915_private_t *dev_priv = dev->dev_private;
7193 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7194
49b14a5c 7195 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7196}
7197
6b95a207
KH		 7198void intel_prepare_page_flip(struct drm_device *dev, int plane)
7199{
7200 drm_i915_private_t *dev_priv = dev->dev_private;
7201 struct intel_crtc *intel_crtc =
7202 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7203 unsigned long flags;
7204
e7d841ca
CW		 7205 /* NB: An MMIO update of the plane base pointer will also
7206 * generate a page-flip completion irq, i.e. every modeset
7207 * is also accompanied by a spurious intel_prepare_page_flip().
7208 */
6b95a207 7209 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7210 if (intel_crtc->unpin_work)
7211 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7212 spin_unlock_irqrestore(&dev->event_lock, flags);
7213}
7214
e7d841ca
CW		 7215inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7216{
7217 /* Ensure that the work item is consistent when activating it ... */
7218 smp_wmb();
7219 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7220 /* and that it is marked active as soon as the irq could fire. */
7221 smp_wmb();
7222}
7223
8c9f3aaf
JB		 7224static int intel_gen2_queue_flip(struct drm_device *dev,
7225 struct drm_crtc *crtc,
7226 struct drm_framebuffer *fb,
7227 struct drm_i915_gem_object *obj)
7228{
7229 struct drm_i915_private *dev_priv = dev->dev_private;
7230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7231 u32 flip_mask;
6d90c952 7232 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7233 int ret;
7234
6d90c952 7235 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7236 if (ret)
83d4092b 7237 goto err;
8c9f3aaf 7238
6d90c952 7239 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7240 if (ret)
83d4092b 7241 goto err_unpin;
8c9f3aaf
JB		 7242
7243 /* Can't queue multiple flips, so wait for the previous
7244 * one to finish before executing the next.
7245 */
7246 if (intel_crtc->plane)
7247 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7248 else
7249 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7250 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7251 intel_ring_emit(ring, MI_NOOP);
7252 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7253 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7254 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7255 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7256 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7257
7258 intel_mark_page_flip_active(intel_crtc);
6d90c952 7259 intel_ring_advance(ring);
83d4092b
CW		 7260 return 0;
7261
7262err_unpin:
7263 intel_unpin_fb_obj(obj);
7264err:
8c9f3aaf
JB		 7265 return ret;
7266}
7267
7268static int intel_gen3_queue_flip(struct drm_device *dev,
7269 struct drm_crtc *crtc,
7270 struct drm_framebuffer *fb,
7271 struct drm_i915_gem_object *obj)
7272{
7273 struct drm_i915_private *dev_priv = dev->dev_private;
7274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7275 u32 flip_mask;
6d90c952 7276 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7277 int ret;
7278
6d90c952 7279 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7280 if (ret)
83d4092b 7281 goto err;
8c9f3aaf 7282
6d90c952 7283 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7284 if (ret)
83d4092b 7285 goto err_unpin;
8c9f3aaf
JB		 7286
7287 if (intel_crtc->plane)
7288 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7289 else
7290 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7291 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7292 intel_ring_emit(ring, MI_NOOP);
7293 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7294 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7295 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7296 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7297 intel_ring_emit(ring, MI_NOOP);
7298
e7d841ca 7299 intel_mark_page_flip_active(intel_crtc);
6d90c952 7300 intel_ring_advance(ring);
83d4092b
CW		 7301 return 0;
7302
7303err_unpin:
7304 intel_unpin_fb_obj(obj);
7305err:
8c9f3aaf
JB		 7306 return ret;
7307}
7308
7309static int intel_gen4_queue_flip(struct drm_device *dev,
7310 struct drm_crtc *crtc,
7311 struct drm_framebuffer *fb,
7312 struct drm_i915_gem_object *obj)
7313{
7314 struct drm_i915_private *dev_priv = dev->dev_private;
7315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7316 uint32_t pf, pipesrc;
6d90c952 7317 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7318 int ret;
7319
6d90c952 7320 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7321 if (ret)
83d4092b 7322 goto err;
8c9f3aaf 7323
6d90c952 7324 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7325 if (ret)
83d4092b 7326 goto err_unpin;
8c9f3aaf
JB		 7327
7328 /* i965+ uses the linear or tiled offsets from the
7329 * Display Registers (which do not change across a page-flip)
7330 * so we need only reprogram the base address.
7331 */
6d90c952
DV		 7332 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7333 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7334 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7335 intel_ring_emit(ring,
7336 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7337 obj->tiling_mode);
8c9f3aaf
JB		 7338
7339 /* XXX Enabling the panel-fitter across page-flip is so far
7340 * untested on non-native modes, so ignore it for now.
7341 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7342 */
7343 pf = 0;
7344 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7345 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7346
7347 intel_mark_page_flip_active(intel_crtc);
6d90c952 7348 intel_ring_advance(ring);
83d4092b
CW		 7349 return 0;
7350
7351err_unpin:
7352 intel_unpin_fb_obj(obj);
7353err:
8c9f3aaf
JB		 7354 return ret;
7355}
7356
7357static int intel_gen6_queue_flip(struct drm_device *dev,
7358 struct drm_crtc *crtc,
7359 struct drm_framebuffer *fb,
7360 struct drm_i915_gem_object *obj)
7361{
7362 struct drm_i915_private *dev_priv = dev->dev_private;
7363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7364 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7365 uint32_t pf, pipesrc;
7366 int ret;
7367
6d90c952 7368 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7369 if (ret)
83d4092b 7370 goto err;
8c9f3aaf 7371
6d90c952 7372 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7373 if (ret)
83d4092b 7374 goto err_unpin;
8c9f3aaf 7375
6d90c952
DV		 7376 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7377 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7378 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7379 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7380
dc257cf1
DV		 7381 /* Contrary to the suggestions in the documentation,
7382 * "Enable Panel Fitter" does not seem to be required when page
7383 * flipping with a non-native mode, and worse causes a normal
7384 * modeset to fail.
7385 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7386 */
7387 pf = 0;
8c9f3aaf 7388 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7389 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7390
7391 intel_mark_page_flip_active(intel_crtc);
6d90c952 7392 intel_ring_advance(ring);
83d4092b
CW		 7393 return 0;
7394
7395err_unpin:
7396 intel_unpin_fb_obj(obj);
7397err:
8c9f3aaf
JB		 7398 return ret;
7399}
7400
7c9017e5
JB		 7401/*
7402 * On gen7 we currently use the blit ring because (in early silicon at least)
7403 * the render ring doesn't give us interrpts for page flip completion, which
7404 * means clients will hang after the first flip is queued. Fortunately the
7405 * blit ring generates interrupts properly, so use it instead.
7406 */
7407static int intel_gen7_queue_flip(struct drm_device *dev,
7408 struct drm_crtc *crtc,
7409 struct drm_framebuffer *fb,
7410 struct drm_i915_gem_object *obj)
7411{
7412 struct drm_i915_private *dev_priv = dev->dev_private;
7413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7414 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7415 uint32_t plane_bit = 0;
7c9017e5
JB		 7416 int ret;
7417
7418 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7419 if (ret)
83d4092b 7420 goto err;
7c9017e5 7421
cb05d8de
DV		 7422 switch(intel_crtc->plane) {
7423 case PLANE_A:
7424 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7425 break;
7426 case PLANE_B:
7427 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7428 break;
7429 case PLANE_C:
7430 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7431 break;
7432 default:
7433 WARN_ONCE(1, "unknown plane in flip command\n");
7434 ret = -ENODEV;
ab3951eb 7435 goto err_unpin;
cb05d8de
DV		 7436 }
7437
7c9017e5
JB		 7438 ret = intel_ring_begin(ring, 4);
7439 if (ret)
83d4092b 7440 goto err_unpin;
7c9017e5 7441
cb05d8de 7442 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7443 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7444 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7445 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7446
7447 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7448 intel_ring_advance(ring);
83d4092b
CW		 7449 return 0;
7450
7451err_unpin:
7452 intel_unpin_fb_obj(obj);
7453err:
7c9017e5
JB		 7454 return ret;
7455}
7456
8c9f3aaf
JB		 7457static int intel_default_queue_flip(struct drm_device *dev,
7458 struct drm_crtc *crtc,
7459 struct drm_framebuffer *fb,
7460 struct drm_i915_gem_object *obj)
7461{
7462 return -ENODEV;
7463}
7464
6b95a207
KH		 7465static int intel_crtc_page_flip(struct drm_crtc *crtc,
7466 struct drm_framebuffer *fb,
7467 struct drm_pending_vblank_event *event)
7468{
7469 struct drm_device *dev = crtc->dev;
7470 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7471 struct drm_framebuffer *old_fb = crtc->fb;
7472 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7474 struct intel_unpin_work *work;
8c9f3aaf 7475 unsigned long flags;
52e68630 7476 int ret;
6b95a207 7477
e6a595d2
VS		 7478 /* Can't change pixel format via MI display flips. */
7479 if (fb->pixel_format != crtc->fb->pixel_format)
7480 return -EINVAL;
7481
7482 /*
7483 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7484 * Note that pitch changes could also affect these register.
7485 */
7486 if (INTEL_INFO(dev)->gen > 3 &&
7487 (fb->offsets[0] != crtc->fb->offsets[0] ||
7488 fb->pitches[0] != crtc->fb->pitches[0]))
7489 return -EINVAL;
7490
6b95a207
KH		 7491 work = kzalloc(sizeof *work, GFP_KERNEL);
7492 if (work == NULL)
7493 return -ENOMEM;
7494
6b95a207 7495 work->event = event;
b4a98e57 7496 work->crtc = crtc;
4a35f83b 7497 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7498 INIT_WORK(&work->work, intel_unpin_work_fn);
7499
7317c75e
JB		 7500 ret = drm_vblank_get(dev, intel_crtc->pipe);
7501 if (ret)
7502 goto free_work;
7503
6b95a207
KH		 7504 /* We borrow the event spin lock for protecting unpin_work */
7505 spin_lock_irqsave(&dev->event_lock, flags);
7506 if (intel_crtc->unpin_work) {
7507 spin_unlock_irqrestore(&dev->event_lock, flags);
7508 kfree(work);
7317c75e 7509 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7510
7511 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7512 return -EBUSY;
7513 }
7514 intel_crtc->unpin_work = work;
7515 spin_unlock_irqrestore(&dev->event_lock, flags);
7516
b4a98e57
CW		 7517 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7518 flush_workqueue(dev_priv->wq);
7519
79158103
CW		 7520 ret = i915_mutex_lock_interruptible(dev);
7521 if (ret)
7522 goto cleanup;
6b95a207 7523
75dfca80 7524 /* Reference the objects for the scheduled work. */
05394f39
CW		 7525 drm_gem_object_reference(&work->old_fb_obj->base);
7526 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7527
7528 crtc->fb = fb;
96b099fd 7529
e1f99ce6 7530 work->pending_flip_obj = obj;
e1f99ce6 7531
4e5359cd
SF		 7532 work->enable_stall_check = true;
7533
b4a98e57 7534 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7535 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7536
8c9f3aaf
JB		 7537 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7538 if (ret)
7539 goto cleanup_pending;
6b95a207 7540
7782de3b 7541 intel_disable_fbc(dev);
f047e395 7542 intel_mark_fb_busy(obj);
6b95a207
KH		 7543 mutex_unlock(&dev->struct_mutex);
7544
e5510fac
JB		 7545 trace_i915_flip_request(intel_crtc->plane, obj);
7546
6b95a207 7547 return 0;
96b099fd 7548
8c9f3aaf 7549cleanup_pending:
b4a98e57 7550 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7551 crtc->fb = old_fb;
05394f39
CW		 7552 drm_gem_object_unreference(&work->old_fb_obj->base);
7553 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7554 mutex_unlock(&dev->struct_mutex);
7555
79158103 7556cleanup:
96b099fd
CW		 7557 spin_lock_irqsave(&dev->event_lock, flags);
7558 intel_crtc->unpin_work = NULL;
7559 spin_unlock_irqrestore(&dev->event_lock, flags);
7560
7317c75e
JB		 7561 drm_vblank_put(dev, intel_crtc->pipe);
7562free_work:
96b099fd
CW		 7563 kfree(work);
7564
7565 return ret;
6b95a207
KH		 7566}
7567
f6e5b160 7568static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7569 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7570 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7571};
7572
6ed0f796 7573bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7574{
6ed0f796
DV		 7575 struct intel_encoder *other_encoder;
7576 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7577
6ed0f796
DV		 7578 if (WARN_ON(!crtc))
7579 return false;
7580
7581 list_for_each_entry(other_encoder,
7582 &crtc->dev->mode_config.encoder_list,
7583 base.head) {
7584
7585 if (&other_encoder->new_crtc->base != crtc ||
7586 encoder == other_encoder)
7587 continue;
7588 else
7589 return true;
f47166d2
CW		 7590 }
7591
6ed0f796
DV		 7592 return false;
7593}
47f1c6c9 7594
50f56119
DV		 7595static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7596 struct drm_crtc *crtc)
7597{
7598 struct drm_device *dev;
7599 struct drm_crtc *tmp;
7600 int crtc_mask = 1;
47f1c6c9 7601
50f56119 7602 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7603
50f56119 7604 dev = crtc->dev;
47f1c6c9 7605
50f56119
DV		 7606 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7607 if (tmp == crtc)
7608 break;
7609 crtc_mask <<= 1;
7610 }
47f1c6c9 7611
50f56119
DV		 7612 if (encoder->possible_crtcs & crtc_mask)
7613 return true;
7614 return false;
47f1c6c9 7615}
79e53945 7616
9a935856
DV		 7617/**
7618 * intel_modeset_update_staged_output_state
7619 *
7620 * Updates the staged output configuration state, e.g. after we've read out the
7621 * current hw state.
7622 */
7623static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7624{
9a935856
DV		 7625 struct intel_encoder *encoder;
7626 struct intel_connector *connector;
f6e5b160 7627
9a935856
DV		 7628 list_for_each_entry(connector, &dev->mode_config.connector_list,
7629 base.head) {
7630 connector->new_encoder =
7631 to_intel_encoder(connector->base.encoder);
7632 }
f6e5b160 7633
9a935856
DV		 7634 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7635 base.head) {
7636 encoder->new_crtc =
7637 to_intel_crtc(encoder->base.crtc);
7638 }
f6e5b160
CW		 7639}
7640
9a935856
DV		 7641/**
7642 * intel_modeset_commit_output_state
7643 *
7644 * This function copies the stage display pipe configuration to the real one.
7645 */
7646static void intel_modeset_commit_output_state(struct drm_device *dev)
7647{
7648 struct intel_encoder *encoder;
7649 struct intel_connector *connector;
f6e5b160 7650
9a935856
DV		 7651 list_for_each_entry(connector, &dev->mode_config.connector_list,
7652 base.head) {
7653 connector->base.encoder = &connector->new_encoder->base;
7654 }
f6e5b160 7655
9a935856
DV		 7656 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7657 base.head) {
7658 encoder->base.crtc = &encoder->new_crtc->base;
7659 }
7660}
7661
050f7aeb
DV		 7662static void
7663connected_sink_compute_bpp(struct intel_connector * connector,
7664 struct intel_crtc_config *pipe_config)
7665{
7666 int bpp = pipe_config->pipe_bpp;
7667
7668 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7669 connector->base.base.id,
7670 drm_get_connector_name(&connector->base));
7671
7672 /* Don't use an invalid EDID bpc value */
7673 if (connector->base.display_info.bpc &&
7674 connector->base.display_info.bpc * 3 < bpp) {
7675 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7676 bpp, connector->base.display_info.bpc*3);
7677 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7678 }
7679
7680 /* Clamp bpp to 8 on screens without EDID 1.4 */
7681 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7682 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7683 bpp);
7684 pipe_config->pipe_bpp = 24;
7685 }
7686}
7687
4e53c2e0 7688static int
050f7aeb
DV		 7689compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7690 struct drm_framebuffer *fb,
7691 struct intel_crtc_config *pipe_config)
4e53c2e0 7692{
050f7aeb
DV		 7693 struct drm_device *dev = crtc->base.dev;
7694 struct intel_connector *connector;
4e53c2e0
DV		 7695 int bpp;
7696
d42264b1
DV		 7697 switch (fb->pixel_format) {
7698 case DRM_FORMAT_C8:
4e53c2e0
DV		 7699 bpp = 8*3; /* since we go through a colormap */
7700 break;
d42264b1
DV		 7701 case DRM_FORMAT_XRGB1555:
7702 case DRM_FORMAT_ARGB1555:
7703 /* checked in intel_framebuffer_init already */
7704 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7705 return -EINVAL;
7706 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7707 bpp = 6*3; /* min is 18bpp */
7708 break;
d42264b1
DV		 7709 case DRM_FORMAT_XBGR8888:
7710 case DRM_FORMAT_ABGR8888:
7711 /* checked in intel_framebuffer_init already */
7712 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7713 return -EINVAL;
7714 case DRM_FORMAT_XRGB8888:
7715 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7716 bpp = 8*3;
7717 break;
d42264b1
DV		 7718 case DRM_FORMAT_XRGB2101010:
7719 case DRM_FORMAT_ARGB2101010:
7720 case DRM_FORMAT_XBGR2101010:
7721 case DRM_FORMAT_ABGR2101010:
7722 /* checked in intel_framebuffer_init already */
7723 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7724 return -EINVAL;
4e53c2e0
DV		 7725 bpp = 10*3;
7726 break;
baba133a 7727 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7728 default:
7729 DRM_DEBUG_KMS("unsupported depth\n");
7730 return -EINVAL;
7731 }
7732
4e53c2e0
DV		 7733 pipe_config->pipe_bpp = bpp;
7734
7735 /* Clamp display bpp to EDID value */
7736 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7737 base.head) {
1b829e05
DV		 7738 if (!connector->new_encoder ||
7739 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7740 continue;
7741
050f7aeb 7742 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7743 }
7744
7745 return bpp;
7746}
7747
c0b03411
DV		 7748static void intel_dump_pipe_config(struct intel_crtc *crtc,
7749 struct intel_crtc_config *pipe_config,
7750 const char *context)
7751{
7752 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7753 context, pipe_name(crtc->pipe));
7754
7755 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7756 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7757 pipe_config->pipe_bpp, pipe_config->dither);
7758 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7759 pipe_config->has_pch_encoder,
7760 pipe_config->fdi_lanes,
7761 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7762 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7763 pipe_config->fdi_m_n.tu);
7764 DRM_DEBUG_KMS("requested mode:\n");
7765 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7766 DRM_DEBUG_KMS("adjusted mode:\n");
7767 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7768 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7769 pipe_config->gmch_pfit.control,
7770 pipe_config->gmch_pfit.pgm_ratios,
7771 pipe_config->gmch_pfit.lvds_border_bits);
7772 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7773 pipe_config->pch_pfit.pos,
7774 pipe_config->pch_pfit.size);
42db64ef 7775 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7776}
7777
b8cecdf5
DV		 7778static struct intel_crtc_config *
7779intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7780 struct drm_framebuffer *fb,
b8cecdf5 7781 struct drm_display_mode *mode)
ee7b9f93 7782{
7758a113 7783 struct drm_device *dev = crtc->dev;
7758a113
DV		 7784 struct drm_encoder_helper_funcs *encoder_funcs;
7785 struct intel_encoder *encoder;
b8cecdf5 7786 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7787 int plane_bpp, ret = -EINVAL;
7788 bool retry = true;
ee7b9f93 7789
b8cecdf5
DV		 7790 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7791 if (!pipe_config)
7758a113
DV		 7792 return ERR_PTR(-ENOMEM);
7793
b8cecdf5
DV		 7794 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7795 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7796 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7797
050f7aeb
DV		 7798 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7799 * plane pixel format and any sink constraints into account. Returns the
7800 * source plane bpp so that dithering can be selected on mismatches
7801 * after encoders and crtc also have had their say. */
7802 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7803 fb, pipe_config);
4e53c2e0
DV		 7804 if (plane_bpp < 0)
7805 goto fail;
7806
e29c22c0 7807encoder_retry:
7758a113
DV		 7808 /* Pass our mode to the connectors and the CRTC to give them a chance to
7809 * adjust it according to limitations or connector properties, and also
7810 * a chance to reject the mode entirely.
47f1c6c9 7811 */
7758a113
DV		 7812 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7813 base.head) {
47f1c6c9 7814
7758a113
DV		 7815 if (&encoder->new_crtc->base != crtc)
7816 continue;
7ae89233
DV		 7817
7818 if (encoder->compute_config) {
7819 if (!(encoder->compute_config(encoder, pipe_config))) {
7820 DRM_DEBUG_KMS("Encoder config failure\n");
7821 goto fail;
7822 }
7823
7824 continue;
7825 }
7826
7758a113 7827 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7828 if (!(encoder_funcs->mode_fixup(&encoder->base,
7829 &pipe_config->requested_mode,
7830 &pipe_config->adjusted_mode))) {
7758a113
DV		 7831 DRM_DEBUG_KMS("Encoder fixup failed\n");
7832 goto fail;
7833 }
ee7b9f93 7834 }
47f1c6c9 7835
e29c22c0
DV		 7836 ret = intel_crtc_compute_config(crtc, pipe_config);
7837 if (ret < 0) {
7758a113
DV		 7838 DRM_DEBUG_KMS("CRTC fixup failed\n");
7839 goto fail;
ee7b9f93 7840 }
e29c22c0
DV		 7841
7842 if (ret == RETRY) {
7843 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7844 ret = -EINVAL;
7845 goto fail;
7846 }
7847
7848 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7849 retry = false;
7850 goto encoder_retry;
7851 }
7852
4e53c2e0
DV		 7853 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7854 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7855 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7856
b8cecdf5 7857 return pipe_config;
7758a113 7858fail:
b8cecdf5 7859 kfree(pipe_config);
e29c22c0 7860 return ERR_PTR(ret);
ee7b9f93 7861}
47f1c6c9 7862
e2e1ed41
DV		 7863/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7864 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7865static void
7866intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7867 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7868{
7869 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7870 struct drm_device *dev = crtc->dev;
7871 struct intel_encoder *encoder;
7872 struct intel_connector *connector;
7873 struct drm_crtc *tmp_crtc;
79e53945 7874
e2e1ed41 7875 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7876
e2e1ed41
DV		 7877 /* Check which crtcs have changed outputs connected to them, these need
7878 * to be part of the prepare_pipes mask. We don't (yet) support global
7879 * modeset across multiple crtcs, so modeset_pipes will only have one
7880 * bit set at most. */
7881 list_for_each_entry(connector, &dev->mode_config.connector_list,
7882 base.head) {
7883 if (connector->base.encoder == &connector->new_encoder->base)
7884 continue;
79e53945 7885
e2e1ed41
DV		 7886 if (connector->base.encoder) {
7887 tmp_crtc = connector->base.encoder->crtc;
7888
7889 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7890 }
7891
7892 if (connector->new_encoder)
7893 *prepare_pipes |=
7894 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7895 }
7896
e2e1ed41
DV		 7897 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7898 base.head) {
7899 if (encoder->base.crtc == &encoder->new_crtc->base)
7900 continue;
7901
7902 if (encoder->base.crtc) {
7903 tmp_crtc = encoder->base.crtc;
7904
7905 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7906 }
7907
7908 if (encoder->new_crtc)
7909 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7910 }
7911
e2e1ed41
DV		 7912 /* Check for any pipes that will be fully disabled ... */
7913 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7914 base.head) {
7915 bool used = false;
22fd0fab 7916
e2e1ed41
DV		 7917 /* Don't try to disable disabled crtcs. */
7918 if (!intel_crtc->base.enabled)
7919 continue;
7e7d76c3 7920
e2e1ed41
DV		 7921 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7922 base.head) {
7923 if (encoder->new_crtc == intel_crtc)
7924 used = true;
7925 }
7926
7927 if (!used)
7928 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7929 }
7930
e2e1ed41
DV		 7931
7932 /* set_mode is also used to update properties on life display pipes. */
7933 intel_crtc = to_intel_crtc(crtc);
7934 if (crtc->enabled)
7935 *prepare_pipes |= 1 << intel_crtc->pipe;
7936
b6c5164d
DV		 7937 /*
7938 * For simplicity do a full modeset on any pipe where the output routing
7939 * changed. We could be more clever, but that would require us to be
7940 * more careful with calling the relevant encoder->mode_set functions.
7941 */
e2e1ed41
DV		 7942 if (*prepare_pipes)
7943 *modeset_pipes = *prepare_pipes;
7944
7945 /* ... and mask these out. */
7946 *modeset_pipes &= ~(*disable_pipes);
7947 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7948
7949 /*
7950 * HACK: We don't (yet) fully support global modesets. intel_set_config
7951 * obies this rule, but the modeset restore mode of
7952 * intel_modeset_setup_hw_state does not.
7953 */
7954 *modeset_pipes &= 1 << intel_crtc->pipe;
7955 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7956
7957 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7958 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7959}
79e53945 7960
ea9d758d 7961static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7962{
ea9d758d 7963 struct drm_encoder *encoder;
f6e5b160 7964 struct drm_device *dev = crtc->dev;
f6e5b160 7965
ea9d758d
DV		 7966 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7967 if (encoder->crtc == crtc)
7968 return true;
7969
7970 return false;
7971}
7972
7973static void
7974intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7975{
7976 struct intel_encoder *intel_encoder;
7977 struct intel_crtc *intel_crtc;
7978 struct drm_connector *connector;
7979
7980 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7981 base.head) {
7982 if (!intel_encoder->base.crtc)
7983 continue;
7984
7985 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7986
7987 if (prepare_pipes & (1 << intel_crtc->pipe))
7988 intel_encoder->connectors_active = false;
7989 }
7990
7991 intel_modeset_commit_output_state(dev);
7992
7993 /* Update computed state. */
7994 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7995 base.head) {
7996 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7997 }
7998
7999 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8000 if (!connector->encoder || !connector->encoder->crtc)
8001 continue;
8002
8003 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8004
8005 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8006 struct drm_property *dpms_property =
8007 dev->mode_config.dpms_property;
8008
ea9d758d 8009 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8010 drm_object_property_set_value(&connector->base,
68d34720
DV		 8011 dpms_property,
8012 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8013
8014 intel_encoder = to_intel_encoder(connector->encoder);
8015 intel_encoder->connectors_active = true;
8016 }
8017 }
8018
8019}
8020
25c5b266
DV		 8021#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8022 list_for_each_entry((intel_crtc), \
8023 &(dev)->mode_config.crtc_list, \
8024 base.head) \
0973f18f 8025 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8026
0e8ffe1b 8027static bool
2fa2fe9a
DV		 8028intel_pipe_config_compare(struct drm_device *dev,
8029 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8030 struct intel_crtc_config *pipe_config)
8031{
08a24034
DV		 8032#define PIPE_CONF_CHECK_I(name) \
8033 if (current_config->name != pipe_config->name) { \
8034 DRM_ERROR("mismatch in " #name " " \
8035 "(expected %i, found %i)\n", \
8036 current_config->name, \
8037 pipe_config->name); \
8038 return false; \
88adfff1
DV		 8039 }
8040
1bd1bd80
DV		 8041#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8042 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8043 DRM_ERROR("mismatch in " #name " " \
8044 "(expected %i, found %i)\n", \
8045 current_config->name & (mask), \
8046 pipe_config->name & (mask)); \
8047 return false; \
8048 }
8049
eccb140b
DV		 8050 PIPE_CONF_CHECK_I(cpu_transcoder);
8051
08a24034
DV		 8052 PIPE_CONF_CHECK_I(has_pch_encoder);
8053 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8054 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8055 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8056 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8057 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8058 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8059
1bd1bd80
DV		 8060 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8061 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8062 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8063 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8064 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8065 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8066
8067 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8068 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8069 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8070 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8071 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8072 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8073
8074 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8075 DRM_MODE_FLAG_INTERLACE);
8076
045ac3b5
JB		 8077 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8078 DRM_MODE_FLAG_PHSYNC);
8079 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8080 DRM_MODE_FLAG_NHSYNC);
8081 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8082 DRM_MODE_FLAG_PVSYNC);
8083 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8084 DRM_MODE_FLAG_NVSYNC);
8085
1bd1bd80
DV		 8086 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8087 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8088
2fa2fe9a
DV		 8089 PIPE_CONF_CHECK_I(gmch_pfit.control);
8090 /* pfit ratios are autocomputed by the hw on gen4+ */
8091 if (INTEL_INFO(dev)->gen < 4)
8092 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8093 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8094 PIPE_CONF_CHECK_I(pch_pfit.pos);
8095 PIPE_CONF_CHECK_I(pch_pfit.size);
8096
42db64ef
PZ		 8097 PIPE_CONF_CHECK_I(ips_enabled);
8098
08a24034 8099#undef PIPE_CONF_CHECK_I
1bd1bd80 8100#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8101
0e8ffe1b
DV		 8102 return true;
8103}
8104
b980514c 8105void
8af6cf88
DV		 8106intel_modeset_check_state(struct drm_device *dev)
8107{
0e8ffe1b 8108 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8109 struct intel_crtc *crtc;
8110 struct intel_encoder *encoder;
8111 struct intel_connector *connector;
0e8ffe1b 8112 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8113
8114 list_for_each_entry(connector, &dev->mode_config.connector_list,
8115 base.head) {
8116 /* This also checks the encoder/connector hw state with the
8117 * ->get_hw_state callbacks. */
8118 intel_connector_check_state(connector);
8119
8120 WARN(&connector->new_encoder->base != connector->base.encoder,
8121 "connector's staged encoder doesn't match current encoder\n");
8122 }
8123
8124 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8125 base.head) {
8126 bool enabled = false;
8127 bool active = false;
8128 enum pipe pipe, tracked_pipe;
8129
8130 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8131 encoder->base.base.id,
8132 drm_get_encoder_name(&encoder->base));
8133
8134 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8135 "encoder's stage crtc doesn't match current crtc\n");
8136 WARN(encoder->connectors_active && !encoder->base.crtc,
8137 "encoder's active_connectors set, but no crtc\n");
8138
8139 list_for_each_entry(connector, &dev->mode_config.connector_list,
8140 base.head) {
8141 if (connector->base.encoder != &encoder->base)
8142 continue;
8143 enabled = true;
8144 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8145 active = true;
8146 }
8147 WARN(!!encoder->base.crtc != enabled,
8148 "encoder's enabled state mismatch "
8149 "(expected %i, found %i)\n",
8150 !!encoder->base.crtc, enabled);
8151 WARN(active && !encoder->base.crtc,
8152 "active encoder with no crtc\n");
8153
8154 WARN(encoder->connectors_active != active,
8155 "encoder's computed active state doesn't match tracked active state "
8156 "(expected %i, found %i)\n", active, encoder->connectors_active);
8157
8158 active = encoder->get_hw_state(encoder, &pipe);
8159 WARN(active != encoder->connectors_active,
8160 "encoder's hw state doesn't match sw tracking "
8161 "(expected %i, found %i)\n",
8162 encoder->connectors_active, active);
8163
8164 if (!encoder->base.crtc)
8165 continue;
8166
8167 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8168 WARN(active && pipe != tracked_pipe,
8169 "active encoder's pipe doesn't match"
8170 "(expected %i, found %i)\n",
8171 tracked_pipe, pipe);
8172
8173 }
8174
8175 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8176 base.head) {
8177 bool enabled = false;
8178 bool active = false;
8179
045ac3b5
JB		 8180 memset(&pipe_config, 0, sizeof(pipe_config));
8181
8af6cf88
DV		 8182 DRM_DEBUG_KMS("[CRTC:%d]\n",
8183 crtc->base.base.id);
8184
8185 WARN(crtc->active && !crtc->base.enabled,
8186 "active crtc, but not enabled in sw tracking\n");
8187
8188 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8189 base.head) {
8190 if (encoder->base.crtc != &crtc->base)
8191 continue;
8192 enabled = true;
8193 if (encoder->connectors_active)
8194 active = true;
045ac3b5
JB		 8195 if (encoder->get_config)
8196 encoder->get_config(encoder, &pipe_config);
8af6cf88
DV		 8197 }
8198 WARN(active != crtc->active,
8199 "crtc's computed active state doesn't match tracked active state "
8200 "(expected %i, found %i)\n", active, crtc->active);
8201 WARN(enabled != crtc->base.enabled,
8202 "crtc's computed enabled state doesn't match tracked enabled state "
8203 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8204
0e8ffe1b
DV		 8205 active = dev_priv->display.get_pipe_config(crtc,
8206 &pipe_config);
8207 WARN(crtc->active != active,
8208 "crtc active state doesn't match with hw state "
8209 "(expected %i, found %i)\n", crtc->active, active);
8210
c0b03411
DV		 8211 if (active &&
8212 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8213 WARN(1, "pipe state doesn't match!\n");
8214 intel_dump_pipe_config(crtc, &pipe_config,
8215 "[hw state]");
8216 intel_dump_pipe_config(crtc, &crtc->config,
8217 "[sw state]");
8218 }
8af6cf88
DV		 8219 }
8220}
8221
f30da187
DV		 8222static int __intel_set_mode(struct drm_crtc *crtc,
8223 struct drm_display_mode *mode,
8224 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8225{
8226 struct drm_device *dev = crtc->dev;
dbf2b54e 8227 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8228 struct drm_display_mode *saved_mode, *saved_hwmode;
8229 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8230 struct intel_crtc *intel_crtc;
8231 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8232 int ret = 0;
a6778b3c 8233
3ac18232 8234 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8235 if (!saved_mode)
8236 return -ENOMEM;
3ac18232 8237 saved_hwmode = saved_mode + 1;
a6778b3c 8238
e2e1ed41 8239 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8240 &prepare_pipes, &disable_pipes);
8241
3ac18232
TG		 8242 *saved_hwmode = crtc->hwmode;
8243 *saved_mode = crtc->mode;
a6778b3c 8244
25c5b266
DV		 8245 /* Hack: Because we don't (yet) support global modeset on multiple
8246 * crtcs, we don't keep track of the new mode for more than one crtc.
8247 * Hence simply check whether any bit is set in modeset_pipes in all the
8248 * pieces of code that are not yet converted to deal with mutliple crtcs
8249 * changing their mode at the same time. */
25c5b266 8250 if (modeset_pipes) {
4e53c2e0 8251 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8252 if (IS_ERR(pipe_config)) {
8253 ret = PTR_ERR(pipe_config);
8254 pipe_config = NULL;
8255
3ac18232 8256 goto out;
25c5b266 8257 }
c0b03411
DV		 8258 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8259 "[modeset]");
25c5b266 8260 }
a6778b3c 8261
460da916
DV		 8262 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8263 intel_crtc_disable(&intel_crtc->base);
8264
ea9d758d
DV		 8265 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8266 if (intel_crtc->base.enabled)
8267 dev_priv->display.crtc_disable(&intel_crtc->base);
8268 }
a6778b3c 8269
6c4c86f5
DV		 8270 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8271 * to set it here already despite that we pass it down the callchain.
f6e5b160 8272 */
b8cecdf5 8273 if (modeset_pipes) {
25c5b266 8274 crtc->mode = *mode;
b8cecdf5
DV		 8275 /* mode_set/enable/disable functions rely on a correct pipe
8276 * config. */
8277 to_intel_crtc(crtc)->config = *pipe_config;
8278 }
7758a113 8279
ea9d758d
DV		 8280 /* Only after disabling all output pipelines that will be changed can we
8281 * update the the output configuration. */
8282 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8283
47fab737
DV		 8284 if (dev_priv->display.modeset_global_resources)
8285 dev_priv->display.modeset_global_resources(dev);
8286
a6778b3c
DV		 8287 /* Set up the DPLL and any encoders state that needs to adjust or depend
8288 * on the DPLL.
f6e5b160 8289 */
25c5b266 8290 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8291 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8292 x, y, fb);
8293 if (ret)
8294 goto done;
a6778b3c
DV		 8295 }
8296
8297 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8298 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8299 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8300
25c5b266
DV		 8301 if (modeset_pipes) {
8302 /* Store real post-adjustment hardware mode. */
b8cecdf5 8303 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8304
25c5b266
DV		 8305 /* Calculate and store various constants which
8306 * are later needed by vblank and swap-completion
8307 * timestamping. They are derived from true hwmode.
8308 */
8309 drm_calc_timestamping_constants(crtc);
8310 }
a6778b3c
DV		 8311
8312 /* FIXME: add subpixel order */
8313done:
c0c36b94 8314 if (ret && crtc->enabled) {
3ac18232
TG		 8315 crtc->hwmode = *saved_hwmode;
8316 crtc->mode = *saved_mode;
a6778b3c
DV		 8317 }
8318
3ac18232 8319out:
b8cecdf5 8320 kfree(pipe_config);
3ac18232 8321 kfree(saved_mode);
a6778b3c 8322 return ret;
f6e5b160
CW		 8323}
8324
f30da187
DV		 8325int intel_set_mode(struct drm_crtc *crtc,
8326 struct drm_display_mode *mode,
8327 int x, int y, struct drm_framebuffer *fb)
8328{
8329 int ret;
8330
8331 ret = __intel_set_mode(crtc, mode, x, y, fb);
8332
8333 if (ret == 0)
8334 intel_modeset_check_state(crtc->dev);
8335
8336 return ret;
8337}
8338
c0c36b94
CW		 8339void intel_crtc_restore_mode(struct drm_crtc *crtc)
8340{
8341 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8342}
8343
25c5b266
DV		 8344#undef for_each_intel_crtc_masked
8345
d9e55608
DV		 8346static void intel_set_config_free(struct intel_set_config *config)
8347{
8348 if (!config)
8349 return;
8350
1aa4b628
DV		 8351 kfree(config->save_connector_encoders);
8352 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8353 kfree(config);
8354}
8355
85f9eb71
DV		 8356static int intel_set_config_save_state(struct drm_device *dev,
8357 struct intel_set_config *config)
8358{
85f9eb71
DV		 8359 struct drm_encoder *encoder;
8360 struct drm_connector *connector;
8361 int count;
8362
1aa4b628
DV		 8363 config->save_encoder_crtcs =
8364 kcalloc(dev->mode_config.num_encoder,
8365 sizeof(struct drm_crtc *), GFP_KERNEL);
8366 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8367 return -ENOMEM;
8368
1aa4b628
DV		 8369 config->save_connector_encoders =
8370 kcalloc(dev->mode_config.num_connector,
8371 sizeof(struct drm_encoder *), GFP_KERNEL);
8372 if (!config->save_connector_encoders)
85f9eb71
DV		 8373 return -ENOMEM;
8374
8375 /* Copy data. Note that driver private data is not affected.
8376 * Should anything bad happen only the expected state is
8377 * restored, not the drivers personal bookkeeping.
8378 */
85f9eb71
DV		 8379 count = 0;
8380 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8381 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8382 }
8383
8384 count = 0;
8385 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8386 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8387 }
8388
8389 return 0;
8390}
8391
8392static void intel_set_config_restore_state(struct drm_device *dev,
8393 struct intel_set_config *config)
8394{
9a935856
DV		 8395 struct intel_encoder *encoder;
8396 struct intel_connector *connector;
85f9eb71
DV		 8397 int count;
8398
85f9eb71 8399 count = 0;
9a935856
DV		 8400 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8401 encoder->new_crtc =
8402 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8403 }
8404
8405 count = 0;
9a935856
DV		 8406 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8407 connector->new_encoder =
8408 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8409 }
8410}
8411
5e2b584e
DV		 8412static void
8413intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8414 struct intel_set_config *config)
8415{
8416
8417 /* We should be able to check here if the fb has the same properties
8418 * and then just flip_or_move it */
8419 if (set->crtc->fb != set->fb) {
8420 /* If we have no fb then treat it as a full mode set */
8421 if (set->crtc->fb == NULL) {
8422 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8423 config->mode_changed = true;
8424 } else if (set->fb == NULL) {
8425 config->mode_changed = true;
72f4901e
DV		 8426 } else if (set->fb->pixel_format !=
8427 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8428 config->mode_changed = true;
8429 } else
8430 config->fb_changed = true;
8431 }
8432
835c5873 8433 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8434 config->fb_changed = true;
8435
8436 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8437 DRM_DEBUG_KMS("modes are different, full mode set\n");
8438 drm_mode_debug_printmodeline(&set->crtc->mode);
8439 drm_mode_debug_printmodeline(set->mode);
8440 config->mode_changed = true;
8441 }
8442}
8443
2e431051 8444static int
9a935856
DV		 8445intel_modeset_stage_output_state(struct drm_device *dev,
8446 struct drm_mode_set *set,
8447 struct intel_set_config *config)
50f56119 8448{
85f9eb71 8449 struct drm_crtc *new_crtc;
9a935856
DV		 8450 struct intel_connector *connector;
8451 struct intel_encoder *encoder;
2e431051 8452 int count, ro;
50f56119 8453
9abdda74 8454 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8455 * of connectors. For paranoia, double-check this. */
8456 WARN_ON(!set->fb && (set->num_connectors != 0));
8457 WARN_ON(set->fb && (set->num_connectors == 0));
8458
50f56119 8459 count = 0;
9a935856
DV		 8460 list_for_each_entry(connector, &dev->mode_config.connector_list,
8461 base.head) {
8462 /* Otherwise traverse passed in connector list and get encoders
8463 * for them. */
50f56119 8464 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8465 if (set->connectors[ro] == &connector->base) {
8466 connector->new_encoder = connector->encoder;
50f56119
DV		 8467 break;
8468 }
8469 }
8470
9a935856
DV		 8471 /* If we disable the crtc, disable all its connectors. Also, if
8472 * the connector is on the changing crtc but not on the new
8473 * connector list, disable it. */
8474 if ((!set->fb || ro == set->num_connectors) &&
8475 connector->base.encoder &&
8476 connector->base.encoder->crtc == set->crtc) {
8477 connector->new_encoder = NULL;
8478
8479 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8480 connector->base.base.id,
8481 drm_get_connector_name(&connector->base));
8482 }
8483
8484
8485 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8486 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8487 config->mode_changed = true;
50f56119
DV		 8488 }
8489 }
9a935856 8490 /* connector->new_encoder is now updated for all connectors. */
50f56119 8491
9a935856 8492 /* Update crtc of enabled connectors. */
50f56119 8493 count = 0;
9a935856
DV		 8494 list_for_each_entry(connector, &dev->mode_config.connector_list,
8495 base.head) {
8496 if (!connector->new_encoder)
50f56119
DV		 8497 continue;
8498
9a935856 8499 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8500
8501 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8502 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8503 new_crtc = set->crtc;
8504 }
8505
8506 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8507 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8508 new_crtc)) {
5e2b584e 8509 return -EINVAL;
50f56119 8510 }
9a935856
DV		 8511 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8512
8513 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8514 connector->base.base.id,
8515 drm_get_connector_name(&connector->base),
8516 new_crtc->base.id);
8517 }
8518
8519 /* Check for any encoders that needs to be disabled. */
8520 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8521 base.head) {
8522 list_for_each_entry(connector,
8523 &dev->mode_config.connector_list,
8524 base.head) {
8525 if (connector->new_encoder == encoder) {
8526 WARN_ON(!connector->new_encoder->new_crtc);
8527
8528 goto next_encoder;
8529 }
8530 }
8531 encoder->new_crtc = NULL;
8532next_encoder:
8533 /* Only now check for crtc changes so we don't miss encoders
8534 * that will be disabled. */
8535 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8536 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8537 config->mode_changed = true;
50f56119
DV		 8538 }
8539 }
9a935856 8540 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8541
2e431051
DV		 8542 return 0;
8543}
8544
8545static int intel_crtc_set_config(struct drm_mode_set *set)
8546{
8547 struct drm_device *dev;
2e431051
DV		 8548 struct drm_mode_set save_set;
8549 struct intel_set_config *config;
8550 int ret;
2e431051 8551
8d3e375e
DV		 8552 BUG_ON(!set);
8553 BUG_ON(!set->crtc);
8554 BUG_ON(!set->crtc->helper_private);
2e431051 8555
7e53f3a4
DV		 8556 /* Enforce sane interface api - has been abused by the fb helper. */
8557 BUG_ON(!set->mode && set->fb);
8558 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8559
2e431051
DV		 8560 if (set->fb) {
8561 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8562 set->crtc->base.id, set->fb->base.id,
8563 (int)set->num_connectors, set->x, set->y);
8564 } else {
8565 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8566 }
8567
8568 dev = set->crtc->dev;
8569
8570 ret = -ENOMEM;
8571 config = kzalloc(sizeof(*config), GFP_KERNEL);
8572 if (!config)
8573 goto out_config;
8574
8575 ret = intel_set_config_save_state(dev, config);
8576 if (ret)
8577 goto out_config;
8578
8579 save_set.crtc = set->crtc;
8580 save_set.mode = &set->crtc->mode;
8581 save_set.x = set->crtc->x;
8582 save_set.y = set->crtc->y;
8583 save_set.fb = set->crtc->fb;
8584
8585 /* Compute whether we need a full modeset, only an fb base update or no
8586 * change at all. In the future we might also check whether only the
8587 * mode changed, e.g. for LVDS where we only change the panel fitter in
8588 * such cases. */
8589 intel_set_config_compute_mode_changes(set, config);
8590
9a935856 8591 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8592 if (ret)
8593 goto fail;
8594
5e2b584e 8595 if (config->mode_changed) {
c0c36b94
CW		 8596 ret = intel_set_mode(set->crtc, set->mode,
8597 set->x, set->y, set->fb);
8598 if (ret) {
8599 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8600 set->crtc->base.id, ret);
87f1faa6
DV		 8601 goto fail;
8602 }
5e2b584e 8603 } else if (config->fb_changed) {
4878cae2
VS		 8604 intel_crtc_wait_for_pending_flips(set->crtc);
8605
4f660f49 8606 ret = intel_pipe_set_base(set->crtc,
94352cf9 8607 set->x, set->y, set->fb);
50f56119
DV		 8608 }
8609
d9e55608
DV		 8610 intel_set_config_free(config);
8611
50f56119
DV		 8612 return 0;
8613
8614fail:
85f9eb71 8615 intel_set_config_restore_state(dev, config);
50f56119
DV		 8616
8617 /* Try to restore the config */
5e2b584e 8618 if (config->mode_changed &&
c0c36b94
CW		 8619 intel_set_mode(save_set.crtc, save_set.mode,
8620 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8621 DRM_ERROR("failed to restore config after modeset failure\n");
8622
d9e55608
DV		 8623out_config:
8624 intel_set_config_free(config);
50f56119
DV		 8625 return ret;
8626}
f6e5b160
CW		 8627
8628static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8629 .cursor_set = intel_crtc_cursor_set,
8630 .cursor_move = intel_crtc_cursor_move,
8631 .gamma_set = intel_crtc_gamma_set,
50f56119 8632 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8633 .destroy = intel_crtc_destroy,
8634 .page_flip = intel_crtc_page_flip,
8635};
8636
79f689aa
PZ		 8637static void intel_cpu_pll_init(struct drm_device *dev)
8638{
affa9354 8639 if (HAS_DDI(dev))
79f689aa
PZ		 8640 intel_ddi_pll_init(dev);
8641}
8642
ee7b9f93
JB		 8643static void intel_pch_pll_init(struct drm_device *dev)
8644{
8645 drm_i915_private_t *dev_priv = dev->dev_private;
8646 int i;
8647
8648 if (dev_priv->num_pch_pll == 0) {
8649 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8650 return;
8651 }
8652
8653 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8654 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8655 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8656 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8657 }
8658}
8659
b358d0a6 8660static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8661{
22fd0fab 8662 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8663 struct intel_crtc *intel_crtc;
8664 int i;
8665
8666 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8667 if (intel_crtc == NULL)
8668 return;
8669
8670 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8671
8672 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8673 for (i = 0; i < 256; i++) {
8674 intel_crtc->lut_r[i] = i;
8675 intel_crtc->lut_g[i] = i;
8676 intel_crtc->lut_b[i] = i;
8677 }
8678
80824003
JB		 8679 /* Swap pipes & planes for FBC on pre-965 */
8680 intel_crtc->pipe = pipe;
8681 intel_crtc->plane = pipe;
e2e767ab 8682 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8683 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8684 intel_crtc->plane = !pipe;
80824003
JB		 8685 }
8686
22fd0fab
JB		 8687 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8688 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8689 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8690 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8691
79e53945 8692 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8693}
8694
08d7b3d1 8695int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8696 struct drm_file *file)
08d7b3d1 8697{
08d7b3d1 8698 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8699 struct drm_mode_object *drmmode_obj;
8700 struct intel_crtc *crtc;
08d7b3d1 8701
1cff8f6b
DV		 8702 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8703 return -ENODEV;
08d7b3d1 8704
c05422d5
DV		 8705 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8706 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8707
c05422d5 8708 if (!drmmode_obj) {
08d7b3d1
CW		 8709 DRM_ERROR("no such CRTC id\n");
8710 return -EINVAL;
8711 }
8712
c05422d5
DV		 8713 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8714 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8715
c05422d5 8716 return 0;
08d7b3d1
CW		 8717}
8718
66a9278e 8719static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8720{
66a9278e
DV		 8721 struct drm_device *dev = encoder->base.dev;
8722 struct intel_encoder *source_encoder;
79e53945 8723 int index_mask = 0;
79e53945
JB		 8724 int entry = 0;
8725
66a9278e
DV		 8726 list_for_each_entry(source_encoder,
8727 &dev->mode_config.encoder_list, base.head) {
8728
8729 if (encoder == source_encoder)
79e53945 8730 index_mask |= (1 << entry);
66a9278e
DV		 8731
8732 /* Intel hw has only one MUX where enocoders could be cloned. */
8733 if (encoder->cloneable && source_encoder->cloneable)
8734 index_mask |= (1 << entry);
8735
79e53945
JB		 8736 entry++;
8737 }
4ef69c7a 8738
79e53945
JB		 8739 return index_mask;
8740}
8741
4d302442
CW		 8742static bool has_edp_a(struct drm_device *dev)
8743{
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745
8746 if (!IS_MOBILE(dev))
8747 return false;
8748
8749 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8750 return false;
8751
8752 if (IS_GEN5(dev) &&
8753 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8754 return false;
8755
8756 return true;
8757}
8758
79e53945
JB		 8759static void intel_setup_outputs(struct drm_device *dev)
8760{
725e30ad 8761 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8762 struct intel_encoder *encoder;
cb0953d7 8763 bool dpd_is_edp = false;
f3cfcba6 8764 bool has_lvds;
79e53945 8765
f3cfcba6 8766 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8767 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8768 /* disable the panel fitter on everything but LVDS */
8769 I915_WRITE(PFIT_CONTROL, 0);
8770 }
79e53945 8771
c40c0f5b 8772 if (!IS_ULT(dev))
79935fca 8773 intel_crt_init(dev);
cb0953d7 8774
affa9354 8775 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8776 int found;
8777
8778 /* Haswell uses DDI functions to detect digital outputs */
8779 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8780 /* DDI A only supports eDP */
8781 if (found)
8782 intel_ddi_init(dev, PORT_A);
8783
8784 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8785 * register */
8786 found = I915_READ(SFUSE_STRAP);
8787
8788 if (found & SFUSE_STRAP_DDIB_DETECTED)
8789 intel_ddi_init(dev, PORT_B);
8790 if (found & SFUSE_STRAP_DDIC_DETECTED)
8791 intel_ddi_init(dev, PORT_C);
8792 if (found & SFUSE_STRAP_DDID_DETECTED)
8793 intel_ddi_init(dev, PORT_D);
8794 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8795 int found;
270b3042
DV		 8796 dpd_is_edp = intel_dpd_is_edp(dev);
8797
8798 if (has_edp_a(dev))
8799 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8800
dc0fa718 8801 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8802 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8803 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8804 if (!found)
e2debe91 8805 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8806 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8807 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8808 }
8809
dc0fa718 8810 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8811 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8812
dc0fa718 8813 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8814 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8815
5eb08b69 8816 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8817 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8818
270b3042 8819 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8820 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8821 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8822 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8823 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8824 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8825
dc0fa718 8826 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8827 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8828 PORT_B);
67cfc203
VS		 8829 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8830 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8831 }
103a196f 8832 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8833 bool found = false;
7d57382e 8834
e2debe91 8835 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8836 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8837 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8838 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8839 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8840 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8841 }
27185ae1 8842
e7281eab 8843 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8844 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8845 }
13520b05
KH		 8846
8847 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8848
e2debe91 8849 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8850 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8851 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8852 }
27185ae1 8853
e2debe91 8854 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8855
b01f2c3a
JB		 8856 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8857 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8858 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8859 }
e7281eab 8860 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8861 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8862 }
27185ae1 8863
b01f2c3a 8864 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8865 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8866 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8867 } else if (IS_GEN2(dev))
79e53945
JB		 8868 intel_dvo_init(dev);
8869
103a196f 8870 if (SUPPORTS_TV(dev))
79e53945
JB		 8871 intel_tv_init(dev);
8872
4ef69c7a
CW		 8873 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8874 encoder->base.possible_crtcs = encoder->crtc_mask;
8875 encoder->base.possible_clones =
66a9278e 8876 intel_encoder_clones(encoder);
79e53945 8877 }
47356eb6 8878
dde86e2d 8879 intel_init_pch_refclk(dev);
270b3042
DV		 8880
8881 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8882}
8883
8884static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8885{
8886 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8887
8888 drm_framebuffer_cleanup(fb);
05394f39 8889 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8890
8891 kfree(intel_fb);
8892}
8893
8894static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8895 struct drm_file *file,
79e53945
JB		 8896 unsigned int *handle)
8897{
8898 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8899 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8900
05394f39 8901 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8902}
8903
8904static const struct drm_framebuffer_funcs intel_fb_funcs = {
8905 .destroy = intel_user_framebuffer_destroy,
8906 .create_handle = intel_user_framebuffer_create_handle,
8907};
8908
38651674
DA		 8909int intel_framebuffer_init(struct drm_device *dev,
8910 struct intel_framebuffer *intel_fb,
308e5bcb 8911 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8912 struct drm_i915_gem_object *obj)
79e53945 8913{
79e53945
JB		 8914 int ret;
8915
c16ed4be
CW		 8916 if (obj->tiling_mode == I915_TILING_Y) {
8917 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8918 return -EINVAL;
c16ed4be 8919 }
57cd6508 8920
c16ed4be
CW		 8921 if (mode_cmd->pitches[0] & 63) {
8922 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8923 mode_cmd->pitches[0]);
57cd6508 8924 return -EINVAL;
c16ed4be 8925 }
57cd6508 8926
5d7bd705 8927 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8928 if (mode_cmd->pitches[0] > 32768) {
8929 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8930 mode_cmd->pitches[0]);
5d7bd705 8931 return -EINVAL;
c16ed4be 8932 }
5d7bd705
VS		 8933
8934 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8935 mode_cmd->pitches[0] != obj->stride) {
8936 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8937 mode_cmd->pitches[0], obj->stride);
5d7bd705 8938 return -EINVAL;
c16ed4be 8939 }
5d7bd705 8940
57779d06 8941 /* Reject formats not supported by any plane early. */
308e5bcb 8942 switch (mode_cmd->pixel_format) {
57779d06 8943 case DRM_FORMAT_C8:
04b3924d
VS		 8944 case DRM_FORMAT_RGB565:
8945 case DRM_FORMAT_XRGB8888:
8946 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8947 break;
8948 case DRM_FORMAT_XRGB1555:
8949 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8950 if (INTEL_INFO(dev)->gen > 3) {
8951 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8952 return -EINVAL;
c16ed4be 8953 }
57779d06
VS		 8954 break;
8955 case DRM_FORMAT_XBGR8888:
8956 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8957 case DRM_FORMAT_XRGB2101010:
8958 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8959 case DRM_FORMAT_XBGR2101010:
8960 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8961 if (INTEL_INFO(dev)->gen < 4) {
8962 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8963 return -EINVAL;
c16ed4be 8964 }
b5626747 8965 break;
04b3924d
VS		 8966 case DRM_FORMAT_YUYV:
8967 case DRM_FORMAT_UYVY:
8968 case DRM_FORMAT_YVYU:
8969 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8970 if (INTEL_INFO(dev)->gen < 5) {
8971 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8972 return -EINVAL;
c16ed4be 8973 }
57cd6508
CW		 8974 break;
8975 default:
c16ed4be 8976 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8977 return -EINVAL;
8978 }
8979
90f9a336
VS		 8980 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8981 if (mode_cmd->offsets[0] != 0)
8982 return -EINVAL;
8983
c7d73f6a
DV		 8984 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8985 intel_fb->obj = obj;
8986
79e53945
JB		 8987 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8988 if (ret) {
8989 DRM_ERROR("framebuffer init failed %d\n", ret);
8990 return ret;
8991 }
8992
79e53945
JB		 8993 return 0;
8994}
8995
79e53945
JB		 8996static struct drm_framebuffer *
8997intel_user_framebuffer_create(struct drm_device *dev,
8998 struct drm_file *filp,
308e5bcb 8999 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9000{
05394f39 9001 struct drm_i915_gem_object *obj;
79e53945 9002
308e5bcb
JB		 9003 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9004 mode_cmd->handles[0]));
c8725226 9005 if (&obj->base == NULL)
cce13ff7 9006 return ERR_PTR(-ENOENT);
79e53945 9007
d2dff872 9008 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9009}
9010
79e53945 9011static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9012 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9013 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9014};
9015
e70236a8
JB		 9016/* Set up chip specific display functions */
9017static void intel_init_display(struct drm_device *dev)
9018{
9019 struct drm_i915_private *dev_priv = dev->dev_private;
9020
ee9300bb
DV		 9021 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9022 dev_priv->display.find_dpll = g4x_find_best_dpll;
9023 else if (IS_VALLEYVIEW(dev))
9024 dev_priv->display.find_dpll = vlv_find_best_dpll;
9025 else if (IS_PINEVIEW(dev))
9026 dev_priv->display.find_dpll = pnv_find_best_dpll;
9027 else
9028 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9029
affa9354 9030 if (HAS_DDI(dev)) {
0e8ffe1b 9031 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9032 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9033 dev_priv->display.crtc_enable = haswell_crtc_enable;
9034 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9035 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9036 dev_priv->display.update_plane = ironlake_update_plane;
9037 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9038 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9039 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9040 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9041 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9042 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9043 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9044 } else if (IS_VALLEYVIEW(dev)) {
9045 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9046 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9047 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9048 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9049 dev_priv->display.off = i9xx_crtc_off;
9050 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9051 } else {
0e8ffe1b 9052 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9053 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9054 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9055 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9056 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9057 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9058 }
e70236a8 9059
e70236a8 9060 /* Returns the core display clock speed */
25eb05fc
JB		 9061 if (IS_VALLEYVIEW(dev))
9062 dev_priv->display.get_display_clock_speed =
9063 valleyview_get_display_clock_speed;
9064 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9065 dev_priv->display.get_display_clock_speed =
9066 i945_get_display_clock_speed;
9067 else if (IS_I915G(dev))
9068 dev_priv->display.get_display_clock_speed =
9069 i915_get_display_clock_speed;
f2b115e6 9070 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9071 dev_priv->display.get_display_clock_speed =
9072 i9xx_misc_get_display_clock_speed;
9073 else if (IS_I915GM(dev))
9074 dev_priv->display.get_display_clock_speed =
9075 i915gm_get_display_clock_speed;
9076 else if (IS_I865G(dev))
9077 dev_priv->display.get_display_clock_speed =
9078 i865_get_display_clock_speed;
f0f8a9ce 9079 else if (IS_I85X(dev))
e70236a8
JB		 9080 dev_priv->display.get_display_clock_speed =
9081 i855_get_display_clock_speed;
9082 else /* 852, 830 */
9083 dev_priv->display.get_display_clock_speed =
9084 i830_get_display_clock_speed;
9085
7f8a8569 9086 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9087 if (IS_GEN5(dev)) {
674cf967 9088 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9089 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9090 } else if (IS_GEN6(dev)) {
674cf967 9091 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9092 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9093 } else if (IS_IVYBRIDGE(dev)) {
9094 /* FIXME: detect B0+ stepping and use auto training */
9095 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9096 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9097 dev_priv->display.modeset_global_resources =
9098 ivb_modeset_global_resources;
c82e4d26
ED		 9099 } else if (IS_HASWELL(dev)) {
9100 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9101 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9102 dev_priv->display.modeset_global_resources =
9103 haswell_modeset_global_resources;
a0e63c22 9104 }
6067aaea 9105 } else if (IS_G4X(dev)) {
e0dac65e 9106 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9107 }
8c9f3aaf
JB		 9108
9109 /* Default just returns -ENODEV to indicate unsupported */
9110 dev_priv->display.queue_flip = intel_default_queue_flip;
9111
9112 switch (INTEL_INFO(dev)->gen) {
9113 case 2:
9114 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9115 break;
9116
9117 case 3:
9118 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9119 break;
9120
9121 case 4:
9122 case 5:
9123 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9124 break;
9125
9126 case 6:
9127 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9128 break;
7c9017e5
JB		 9129 case 7:
9130 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9131 break;
8c9f3aaf 9132 }
e70236a8
JB		 9133}
9134
b690e96c
JB		 9135/*
9136 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9137 * resume, or other times. This quirk makes sure that's the case for
9138 * affected systems.
9139 */
0206e353 9140static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9141{
9142 struct drm_i915_private *dev_priv = dev->dev_private;
9143
9144 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9145 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9146}
9147
435793df
KP		 9148/*
9149 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9150 */
9151static void quirk_ssc_force_disable(struct drm_device *dev)
9152{
9153 struct drm_i915_private *dev_priv = dev->dev_private;
9154 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9155 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9156}
9157
4dca20ef 9158/*
5a15ab5b
CE		 9159 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9160 * brightness value
4dca20ef
CE		 9161 */
9162static void quirk_invert_brightness(struct drm_device *dev)
9163{
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9166 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9167}
9168
b690e96c
JB		 9169struct intel_quirk {
9170 int device;
9171 int subsystem_vendor;
9172 int subsystem_device;
9173 void (*hook)(struct drm_device *dev);
9174};
9175
5f85f176
EE		 9176/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9177struct intel_dmi_quirk {
9178 void (*hook)(struct drm_device *dev);
9179 const struct dmi_system_id (*dmi_id_list)[];
9180};
9181
9182static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9183{
9184 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9185 return 1;
9186}
9187
9188static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9189 {
9190 .dmi_id_list = &(const struct dmi_system_id[]) {
9191 {
9192 .callback = intel_dmi_reverse_brightness,
9193 .ident = "NCR Corporation",
9194 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9195 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9196 },
9197 },
9198 { } /* terminating entry */
9199 },
9200 .hook = quirk_invert_brightness,
9201 },
9202};
9203
c43b5634 9204static struct intel_quirk intel_quirks[] = {
b690e96c 9205 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9206 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9207
b690e96c
JB		 9208 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9209 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9210
b690e96c
JB		 9211 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9212 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9213
ccd0d36e 9214 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9215 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9216 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9217
9218 /* Lenovo U160 cannot use SSC on LVDS */
9219 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9220
9221 /* Sony Vaio Y cannot use SSC on LVDS */
9222 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9223
9224 /* Acer Aspire 5734Z must invert backlight brightness */
9225 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9226
9227 /* Acer/eMachines G725 */
9228 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9229
9230 /* Acer/eMachines e725 */
9231 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9232
9233 /* Acer/Packard Bell NCL20 */
9234 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9235
9236 /* Acer Aspire 4736Z */
9237 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9238};
9239
9240static void intel_init_quirks(struct drm_device *dev)
9241{
9242 struct pci_dev *d = dev->pdev;
9243 int i;
9244
9245 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9246 struct intel_quirk *q = &intel_quirks[i];
9247
9248 if (d->device == q->device &&
9249 (d->subsystem_vendor == q->subsystem_vendor ||
9250 q->subsystem_vendor == PCI_ANY_ID) &&
9251 (d->subsystem_device == q->subsystem_device ||
9252 q->subsystem_device == PCI_ANY_ID))
9253 q->hook(dev);
9254 }
5f85f176
EE		 9255 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9256 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9257 intel_dmi_quirks[i].hook(dev);
9258 }
b690e96c
JB		 9259}
9260
9cce37f4
JB		 9261/* Disable the VGA plane that we never use */
9262static void i915_disable_vga(struct drm_device *dev)
9263{
9264 struct drm_i915_private *dev_priv = dev->dev_private;
9265 u8 sr1;
766aa1c4 9266 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9267
9268 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9269 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9270 sr1 = inb(VGA_SR_DATA);
9271 outb(sr1 | 1<<5, VGA_SR_DATA);
9272 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9273 udelay(300);
9274
9275 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9276 POSTING_READ(vga_reg);
9277}
9278
f817586c
DV		 9279void intel_modeset_init_hw(struct drm_device *dev)
9280{
fa42e23c 9281 intel_init_power_well(dev);
0232e927 9282
a8f78b58
ED		 9283 intel_prepare_ddi(dev);
9284
f817586c
DV		 9285 intel_init_clock_gating(dev);
9286
79f5b2c7 9287 mutex_lock(&dev->struct_mutex);
8090c6b9 9288 intel_enable_gt_powersave(dev);
79f5b2c7 9289 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9290}
9291
7d708ee4
ID		 9292void intel_modeset_suspend_hw(struct drm_device *dev)
9293{
9294 intel_suspend_hw(dev);
9295}
9296
79e53945
JB		 9297void intel_modeset_init(struct drm_device *dev)
9298{
652c393a 9299 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9300 int i, j, ret;
79e53945
JB		 9301
9302 drm_mode_config_init(dev);
9303
9304 dev->mode_config.min_width = 0;
9305 dev->mode_config.min_height = 0;
9306
019d96cb
DA		 9307 dev->mode_config.preferred_depth = 24;
9308 dev->mode_config.prefer_shadow = 1;
9309
e6ecefaa 9310 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9311
b690e96c
JB		 9312 intel_init_quirks(dev);
9313
1fa61106
ED		 9314 intel_init_pm(dev);
9315
e3c74757
BW		 9316 if (INTEL_INFO(dev)->num_pipes == 0)
9317 return;
9318
e70236a8
JB		 9319 intel_init_display(dev);
9320
a6c45cf0
CW		 9321 if (IS_GEN2(dev)) {
9322 dev->mode_config.max_width = 2048;
9323 dev->mode_config.max_height = 2048;
9324 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9325 dev->mode_config.max_width = 4096;
9326 dev->mode_config.max_height = 4096;
79e53945 9327 } else {
a6c45cf0
CW		 9328 dev->mode_config.max_width = 8192;
9329 dev->mode_config.max_height = 8192;
79e53945 9330 }
5d4545ae 9331 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9332
28c97730 9333 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9334 INTEL_INFO(dev)->num_pipes,
9335 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9336
7eb552ae 9337 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9338 intel_crtc_init(dev, i);
7f1f3851
JB		 9339 for (j = 0; j < dev_priv->num_plane; j++) {
9340 ret = intel_plane_init(dev, i, j);
9341 if (ret)
06da8da2
VS		 9342 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9343 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9344 }
79e53945
JB		 9345 }
9346
79f689aa 9347 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9348 intel_pch_pll_init(dev);
9349
9cce37f4
JB		 9350 /* Just disable it once at startup */
9351 i915_disable_vga(dev);
79e53945 9352 intel_setup_outputs(dev);
11be49eb
CW		 9353
9354 /* Just in case the BIOS is doing something questionable. */
9355 intel_disable_fbc(dev);
2c7111db
CW		 9356}
9357
24929352
DV		 9358static void
9359intel_connector_break_all_links(struct intel_connector *connector)
9360{
9361 connector->base.dpms = DRM_MODE_DPMS_OFF;
9362 connector->base.encoder = NULL;
9363 connector->encoder->connectors_active = false;
9364 connector->encoder->base.crtc = NULL;
9365}
9366
7fad798e
DV		 9367static void intel_enable_pipe_a(struct drm_device *dev)
9368{
9369 struct intel_connector *connector;
9370 struct drm_connector *crt = NULL;
9371 struct intel_load_detect_pipe load_detect_temp;
9372
9373 /* We can't just switch on the pipe A, we need to set things up with a
9374 * proper mode and output configuration. As a gross hack, enable pipe A
9375 * by enabling the load detect pipe once. */
9376 list_for_each_entry(connector,
9377 &dev->mode_config.connector_list,
9378 base.head) {
9379 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9380 crt = &connector->base;
9381 break;
9382 }
9383 }
9384
9385 if (!crt)
9386 return;
9387
9388 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9389 intel_release_load_detect_pipe(crt, &load_detect_temp);
9390
652c393a 9391
7fad798e
DV		 9392}
9393
fa555837
DV		 9394static bool
9395intel_check_plane_mapping(struct intel_crtc *crtc)
9396{
7eb552ae
BW		 9397 struct drm_device *dev = crtc->base.dev;
9398 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9399 u32 reg, val;
9400
7eb552ae 9401 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9402 return true;
9403
9404 reg = DSPCNTR(!crtc->plane);
9405 val = I915_READ(reg);
9406
9407 if ((val & DISPLAY_PLANE_ENABLE) &&
9408 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9409 return false;
9410
9411 return true;
9412}
9413
24929352
DV		 9414static void intel_sanitize_crtc(struct intel_crtc *crtc)
9415{
9416 struct drm_device *dev = crtc->base.dev;
9417 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9418 u32 reg;
24929352 9419
24929352 9420 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9421 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9422 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9423
9424 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9425 * disable the crtc (and hence change the state) if it is wrong. Note
9426 * that gen4+ has a fixed plane -> pipe mapping. */
9427 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9428 struct intel_connector *connector;
9429 bool plane;
9430
24929352
DV		 9431 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9432 crtc->base.base.id);
9433
9434 /* Pipe has the wrong plane attached and the plane is active.
9435 * Temporarily change the plane mapping and disable everything
9436 * ... */
9437 plane = crtc->plane;
9438 crtc->plane = !plane;
9439 dev_priv->display.crtc_disable(&crtc->base);
9440 crtc->plane = plane;
9441
9442 /* ... and break all links. */
9443 list_for_each_entry(connector, &dev->mode_config.connector_list,
9444 base.head) {
9445 if (connector->encoder->base.crtc != &crtc->base)
9446 continue;
9447
9448 intel_connector_break_all_links(connector);
9449 }
9450
9451 WARN_ON(crtc->active);
9452 crtc->base.enabled = false;
9453 }
24929352 9454
7fad798e
DV		 9455 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9456 crtc->pipe == PIPE_A && !crtc->active) {
9457 /* BIOS forgot to enable pipe A, this mostly happens after
9458 * resume. Force-enable the pipe to fix this, the update_dpms
9459 * call below we restore the pipe to the right state, but leave
9460 * the required bits on. */
9461 intel_enable_pipe_a(dev);
9462 }
9463
24929352
DV		 9464 /* Adjust the state of the output pipe according to whether we
9465 * have active connectors/encoders. */
9466 intel_crtc_update_dpms(&crtc->base);
9467
9468 if (crtc->active != crtc->base.enabled) {
9469 struct intel_encoder *encoder;
9470
9471 /* This can happen either due to bugs in the get_hw_state
9472 * functions or because the pipe is force-enabled due to the
9473 * pipe A quirk. */
9474 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9475 crtc->base.base.id,
9476 crtc->base.enabled ? "enabled" : "disabled",
9477 crtc->active ? "enabled" : "disabled");
9478
9479 crtc->base.enabled = crtc->active;
9480
9481 /* Because we only establish the connector -> encoder ->
9482 * crtc links if something is active, this means the
9483 * crtc is now deactivated. Break the links. connector
9484 * -> encoder links are only establish when things are
9485 * actually up, hence no need to break them. */
9486 WARN_ON(crtc->active);
9487
9488 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9489 WARN_ON(encoder->connectors_active);
9490 encoder->base.crtc = NULL;
9491 }
9492 }
9493}
9494
9495static void intel_sanitize_encoder(struct intel_encoder *encoder)
9496{
9497 struct intel_connector *connector;
9498 struct drm_device *dev = encoder->base.dev;
9499
9500 /* We need to check both for a crtc link (meaning that the
9501 * encoder is active and trying to read from a pipe) and the
9502 * pipe itself being active. */
9503 bool has_active_crtc = encoder->base.crtc &&
9504 to_intel_crtc(encoder->base.crtc)->active;
9505
9506 if (encoder->connectors_active && !has_active_crtc) {
9507 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9508 encoder->base.base.id,
9509 drm_get_encoder_name(&encoder->base));
9510
9511 /* Connector is active, but has no active pipe. This is
9512 * fallout from our resume register restoring. Disable
9513 * the encoder manually again. */
9514 if (encoder->base.crtc) {
9515 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9516 encoder->base.base.id,
9517 drm_get_encoder_name(&encoder->base));
9518 encoder->disable(encoder);
9519 }
9520
9521 /* Inconsistent output/port/pipe state happens presumably due to
9522 * a bug in one of the get_hw_state functions. Or someplace else
9523 * in our code, like the register restore mess on resume. Clamp
9524 * things to off as a safer default. */
9525 list_for_each_entry(connector,
9526 &dev->mode_config.connector_list,
9527 base.head) {
9528 if (connector->encoder != encoder)
9529 continue;
9530
9531 intel_connector_break_all_links(connector);
9532 }
9533 }
9534 /* Enabled encoders without active connectors will be fixed in
9535 * the crtc fixup. */
9536}
9537
44cec740 9538void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9539{
9540 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9541 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9542
9543 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9544 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9545 i915_disable_vga(dev);
0fde901f
KM		 9546 }
9547}
9548
24929352
DV		 9549/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9550 * and i915 state tracking structures. */
45e2b5f6
DV		 9551void intel_modeset_setup_hw_state(struct drm_device *dev,
9552 bool force_restore)
24929352
DV		 9553{
9554 struct drm_i915_private *dev_priv = dev->dev_private;
9555 enum pipe pipe;
b5644d05 9556 struct drm_plane *plane;
24929352
DV		 9557 struct intel_crtc *crtc;
9558 struct intel_encoder *encoder;
9559 struct intel_connector *connector;
9560
0e8ffe1b
DV		 9561 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9562 base.head) {
88adfff1 9563 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9564
0e8ffe1b
DV		 9565 crtc->active = dev_priv->display.get_pipe_config(crtc,
9566 &crtc->config);
24929352
DV		 9567
9568 crtc->base.enabled = crtc->active;
9569
9570 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9571 crtc->base.base.id,
9572 crtc->active ? "enabled" : "disabled");
9573 }
9574
affa9354 9575 if (HAS_DDI(dev))
6441ab5f
PZ		 9576 intel_ddi_setup_hw_pll_state(dev);
9577
24929352
DV		 9578 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9579 base.head) {
9580 pipe = 0;
9581
9582 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9583 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9584 encoder->base.crtc = &crtc->base;
9585 if (encoder->get_config)
9586 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9587 } else {
9588 encoder->base.crtc = NULL;
9589 }
9590
9591 encoder->connectors_active = false;
9592 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9593 encoder->base.base.id,
9594 drm_get_encoder_name(&encoder->base),
9595 encoder->base.crtc ? "enabled" : "disabled",
9596 pipe);
9597 }
9598
9599 list_for_each_entry(connector, &dev->mode_config.connector_list,
9600 base.head) {
9601 if (connector->get_hw_state(connector)) {
9602 connector->base.dpms = DRM_MODE_DPMS_ON;
9603 connector->encoder->connectors_active = true;
9604 connector->base.encoder = &connector->encoder->base;
9605 } else {
9606 connector->base.dpms = DRM_MODE_DPMS_OFF;
9607 connector->base.encoder = NULL;
9608 }
9609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9610 connector->base.base.id,
9611 drm_get_connector_name(&connector->base),
9612 connector->base.encoder ? "enabled" : "disabled");
9613 }
9614
9615 /* HW state is read out, now we need to sanitize this mess. */
9616 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9617 base.head) {
9618 intel_sanitize_encoder(encoder);
9619 }
9620
9621 for_each_pipe(pipe) {
9622 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9623 intel_sanitize_crtc(crtc);
c0b03411 9624 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9625 }
9a935856 9626
45e2b5f6 9627 if (force_restore) {
f30da187
DV		 9628 /*
9629 * We need to use raw interfaces for restoring state to avoid
9630 * checking (bogus) intermediate states.
9631 */
45e2b5f6 9632 for_each_pipe(pipe) {
b5644d05
JB		 9633 struct drm_crtc *crtc =
9634 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9635
9636 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9637 crtc->fb);
45e2b5f6 9638 }
b5644d05
JB		 9639 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9640 intel_plane_restore(plane);
0fde901f
KM		 9641
9642 i915_redisable_vga(dev);
45e2b5f6
DV		 9643 } else {
9644 intel_modeset_update_staged_output_state(dev);
9645 }
8af6cf88
DV		 9646
9647 intel_modeset_check_state(dev);
2e938892
DV		 9648
9649 drm_mode_config_reset(dev);
2c7111db
CW		 9650}
9651
9652void intel_modeset_gem_init(struct drm_device *dev)
9653{
1833b134 9654 intel_modeset_init_hw(dev);
02e792fb
DV		 9655
9656 intel_setup_overlay(dev);
24929352 9657
45e2b5f6 9658 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9659}
9660
9661void intel_modeset_cleanup(struct drm_device *dev)
9662{
652c393a
JB		 9663 struct drm_i915_private *dev_priv = dev->dev_private;
9664 struct drm_crtc *crtc;
9665 struct intel_crtc *intel_crtc;
9666
fd0c0642
DV		 9667 /*
9668 * Interrupts and polling as the first thing to avoid creating havoc.
9669 * Too much stuff here (turning of rps, connectors, ...) would
9670 * experience fancy races otherwise.
9671 */
9672 drm_irq_uninstall(dev);
9673 cancel_work_sync(&dev_priv->hotplug_work);
9674 /*
9675 * Due to the hpd irq storm handling the hotplug work can re-arm the
9676 * poll handlers. Hence disable polling after hpd handling is shut down.
9677 */
f87ea761 9678 drm_kms_helper_poll_fini(dev);
fd0c0642 9679
652c393a
JB		 9680 mutex_lock(&dev->struct_mutex);
9681
723bfd70
JB		 9682 intel_unregister_dsm_handler();
9683
652c393a
JB		 9684 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9685 /* Skip inactive CRTCs */
9686 if (!crtc->fb)
9687 continue;
9688
9689 intel_crtc = to_intel_crtc(crtc);
3dec0095 9690 intel_increase_pllclock(crtc);
652c393a
JB		 9691 }
9692
973d04f9 9693 intel_disable_fbc(dev);
e70236a8 9694
8090c6b9 9695 intel_disable_gt_powersave(dev);
0cdab21f 9696
930ebb46
DV		 9697 ironlake_teardown_rc6(dev);
9698
69341a5e
KH		 9699 mutex_unlock(&dev->struct_mutex);
9700
1630fe75
CW		 9701 /* flush any delayed tasks or pending work */
9702 flush_scheduled_work();
9703
dc652f90
JN		 9704 /* destroy backlight, if any, before the connectors */
9705 intel_panel_destroy_backlight(dev);
9706
79e53945 9707 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9708
9709 intel_cleanup_overlay(dev);
79e53945
JB		 9710}
9711
f1c79df3
ZW		 9712/*
9713 * Return which encoder is currently attached for connector.
9714 */
df0e9248 9715struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9716{
df0e9248
CW		 9717 return &intel_attached_encoder(connector)->base;
9718}
f1c79df3 9719
df0e9248
CW		 9720void intel_connector_attach_encoder(struct intel_connector *connector,
9721 struct intel_encoder *encoder)
9722{
9723 connector->encoder = encoder;
9724 drm_mode_connector_attach_encoder(&connector->base,
9725 &encoder->base);
79e53945 9726}
28d52043
DA		 9727
9728/*
9729 * set vga decode state - true == enable VGA decode
9730 */
9731int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9732{
9733 struct drm_i915_private *dev_priv = dev->dev_private;
9734 u16 gmch_ctrl;
9735
9736 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9737 if (state)
9738 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9739 else
9740 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9741 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9742 return 0;
9743}
c4a1d9e4
CW		 9744
9745#ifdef CONFIG_DEBUG_FS
9746#include <linux/seq_file.h>
9747
9748struct intel_display_error_state {
ff57f1b0
PZ		 9749
9750 u32 power_well_driver;
9751
c4a1d9e4
CW		 9752 struct intel_cursor_error_state {
9753 u32 control;
9754 u32 position;
9755 u32 base;
9756 u32 size;
52331309 9757 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9758
9759 struct intel_pipe_error_state {
ff57f1b0 9760 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9761 u32 conf;
9762 u32 source;
9763
9764 u32 htotal;
9765 u32 hblank;
9766 u32 hsync;
9767 u32 vtotal;
9768 u32 vblank;
9769 u32 vsync;
52331309 9770 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9771
9772 struct intel_plane_error_state {
9773 u32 control;
9774 u32 stride;
9775 u32 size;
9776 u32 pos;
9777 u32 addr;
9778 u32 surface;
9779 u32 tile_offset;
52331309 9780 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9781};
9782
9783struct intel_display_error_state *
9784intel_display_capture_error_state(struct drm_device *dev)
9785{
0206e353 9786 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9787 struct intel_display_error_state *error;
702e7a56 9788 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9789 int i;
9790
9791 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9792 if (error == NULL)
9793 return NULL;
9794
ff57f1b0
PZ		 9795 if (HAS_POWER_WELL(dev))
9796 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9797
52331309 9798 for_each_pipe(i) {
702e7a56 9799 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9800 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9801
a18c4c3d
PZ		 9802 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9803 error->cursor[i].control = I915_READ(CURCNTR(i));
9804 error->cursor[i].position = I915_READ(CURPOS(i));
9805 error->cursor[i].base = I915_READ(CURBASE(i));
9806 } else {
9807 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9808 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9809 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9810 }
c4a1d9e4
CW		 9811
9812 error->plane[i].control = I915_READ(DSPCNTR(i));
9813 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9814 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9815 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9816 error->plane[i].pos = I915_READ(DSPPOS(i));
9817 }
ca291363
PZ		 9818 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9819 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9820 if (INTEL_INFO(dev)->gen >= 4) {
9821 error->plane[i].surface = I915_READ(DSPSURF(i));
9822 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9823 }
9824
702e7a56 9825 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9826 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9827 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9828 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9829 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9830 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9831 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9832 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9833 }
9834
12d217c7
PZ		 9835 /* In the code above we read the registers without checking if the power
9836 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9837 * prevent the next I915_WRITE from detecting it and printing an error
9838 * message. */
9839 if (HAS_POWER_WELL(dev))
9840 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9841
c4a1d9e4
CW		 9842 return error;
9843}
9844
edc3d884
MK		 9845#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9846
c4a1d9e4 9847void
edc3d884 9848intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9849 struct drm_device *dev,
9850 struct intel_display_error_state *error)
9851{
9852 int i;
9853
edc3d884 9854 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9855 if (HAS_POWER_WELL(dev))
edc3d884 9856 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9857 error->power_well_driver);
52331309 9858 for_each_pipe(i) {
edc3d884
MK		 9859 err_printf(m, "Pipe [%d]:\n", i);
9860 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9861 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9862 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9863 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9864 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9865 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9866 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9867 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9868 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9869 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9870
9871 err_printf(m, "Plane [%d]:\n", i);
9872 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9873 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9874 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9875 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9876 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9877 }
4b71a570 9878 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9879 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9880 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9881 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9882 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9883 }
9884
edc3d884
MK		 9885 err_printf(m, "Cursor [%d]:\n", i);
9886 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9887 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9888 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9889 }
9890}
9891#endif
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