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drm/i915: enable 30bpp for DP outputs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
653e1026 1108 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1109 int reg, i;
1110 u32 val;
1111 int cur_pipe;
1112
653e1026
VS		 1113 /* Primary planes are fixed to pipes on gen4+ */
1114 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1115 reg = DSPCNTR(pipe);
1116 val = I915_READ(reg);
1117 WARN((val & DISPLAY_PLANE_ENABLE),
1118 "plane %c assertion failure, should be disabled but not\n",
1119 plane_name(pipe));
19ec1358 1120 return;
28c05794 1121 }
19ec1358 1122
b24e7179 1123 /* Need to check both planes against the pipe */
653e1026 1124 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1125 reg = DSPCNTR(i);
1126 val = I915_READ(reg);
1127 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1128 DISPPLANE_SEL_PIPE_SHIFT;
1129 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1130 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1131 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1132 }
1133}
1134
19332d7a
JB		 1135static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1136 enum pipe pipe)
1137{
20674eef 1138 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1139 int reg, i;
1140 u32 val;
1141
20674eef
VS		 1142 if (IS_VALLEYVIEW(dev)) {
1143 for (i = 0; i < dev_priv->num_plane; i++) {
1144 reg = SPCNTR(pipe, i);
1145 val = I915_READ(reg);
1146 WARN((val & SP_ENABLE),
1147 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1148 sprite_name(pipe, i), pipe_name(pipe));
1149 }
1150 } else if (INTEL_INFO(dev)->gen >= 7) {
1151 reg = SPRCTL(pipe);
1152 val = I915_READ(reg);
1153 WARN((val & SPRITE_ENABLE),
1154 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1155 plane_name(pipe), pipe_name(pipe));
1156 } else if (INTEL_INFO(dev)->gen >= 5) {
1157 reg = DVSCNTR(pipe);
19332d7a 1158 val = I915_READ(reg);
20674eef 1159 WARN((val & DVS_ENABLE),
06da8da2 1160 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1161 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1162 }
1163}
1164
92f2584a
JB		 1165static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1166{
1167 u32 val;
1168 bool enabled;
1169
9d82aa17
ED		 1170 if (HAS_PCH_LPT(dev_priv->dev)) {
1171 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1172 return;
1173 }
1174
92f2584a
JB		 1175 val = I915_READ(PCH_DREF_CONTROL);
1176 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1177 DREF_SUPERSPREAD_SOURCE_MASK));
1178 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1179}
1180
ab9412ba
DV		 1181static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
92f2584a
JB		 1183{
1184 int reg;
1185 u32 val;
1186 bool enabled;
1187
ab9412ba 1188 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1189 val = I915_READ(reg);
1190 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1191 WARN(enabled,
1192 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1193 pipe_name(pipe));
92f2584a
JB		 1194}
1195
4e634389
KP		 1196static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1198{
1199 if ((val & DP_PORT_EN) == 0)
1200 return false;
1201
1202 if (HAS_PCH_CPT(dev_priv->dev)) {
1203 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1204 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1205 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1206 return false;
1207 } else {
1208 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209 return false;
1210 }
1211 return true;
1212}
1213
1519b995
KP		 1214static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1215 enum pipe pipe, u32 val)
1216{
dc0fa718 1217 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1218 return false;
1219
1220 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1221 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1222 return false;
1223 } else {
dc0fa718 1224 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1225 return false;
1226 }
1227 return true;
1228}
1229
1230static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, u32 val)
1232{
1233 if ((val & LVDS_PORT_EN) == 0)
1234 return false;
1235
1236 if (HAS_PCH_CPT(dev_priv->dev)) {
1237 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238 return false;
1239 } else {
1240 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241 return false;
1242 }
1243 return true;
1244}
1245
1246static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 val)
1248{
1249 if ((val & ADPA_DAC_ENABLE) == 0)
1250 return false;
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1253 return false;
1254 } else {
1255 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256 return false;
1257 }
1258 return true;
1259}
1260
291906f1 1261static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1262 enum pipe pipe, int reg, u32 port_sel)
291906f1 1263{
47a05eca 1264 u32 val = I915_READ(reg);
4e634389 1265 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1266 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1267 reg, pipe_name(pipe));
de9a35ab 1268
75c5da27
DV		 1269 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1270 && (val & DP_PIPEB_SELECT),
de9a35ab 1271 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1272}
1273
1274static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, int reg)
1276{
47a05eca 1277 u32 val = I915_READ(reg);
b70ad586 1278 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1279 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1280 reg, pipe_name(pipe));
de9a35ab 1281
dc0fa718 1282 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1283 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1284 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1285}
1286
1287static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288 enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
291906f1 1292
f0575e92
KP		 1293 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1296
1297 reg = PCH_ADPA;
1298 val = I915_READ(reg);
b70ad586 1299 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1300 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1301 pipe_name(pipe));
291906f1
JB		 1302
1303 reg = PCH_LVDS;
1304 val = I915_READ(reg);
b70ad586 1305 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1306 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1307 pipe_name(pipe));
291906f1 1308
e2debe91
PZ		 1309 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1310 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1312}
1313
63d7bbe9
JB		 1314/**
1315 * intel_enable_pll - enable a PLL
1316 * @dev_priv: i915 private structure
1317 * @pipe: pipe PLL to enable
1318 *
1319 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1320 * make sure the PLL reg is writable first though, since the panel write
1321 * protect mechanism may be enabled.
1322 *
1323 * Note! This is for pre-ILK only.
7434a255
TR		 1324 *
1325 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1326 */
1327static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331
58c6eaa2
DV		 1332 assert_pipe_disabled(dev_priv, pipe);
1333
63d7bbe9 1334 /* No really, not for ILK+ */
a0c4da24 1335 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1336
1337 /* PLL is protected by panel, make sure we can write it */
1338 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1339 assert_panel_unlocked(dev_priv, pipe);
1340
1341 reg = DPLL(pipe);
1342 val = I915_READ(reg);
1343 val |= DPLL_VCO_ENABLE;
1344
1345 /* We do this three times for luck */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352 I915_WRITE(reg, val);
1353 POSTING_READ(reg);
1354 udelay(150); /* wait for warmup */
1355}
1356
1357/**
1358 * intel_disable_pll - disable a PLL
1359 * @dev_priv: i915 private structure
1360 * @pipe: pipe PLL to disable
1361 *
1362 * Disable the PLL for @pipe, making sure the pipe is off first.
1363 *
1364 * Note! This is for pre-ILK only.
1365 */
1366static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1367{
1368 int reg;
1369 u32 val;
1370
1371 /* Don't disable pipe A or pipe A PLLs if needed */
1372 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373 return;
1374
1375 /* Make sure the pipe isn't still relying on us */
1376 assert_pipe_disabled(dev_priv, pipe);
1377
1378 reg = DPLL(pipe);
1379 val = I915_READ(reg);
1380 val &= ~DPLL_VCO_ENABLE;
1381 I915_WRITE(reg, val);
1382 POSTING_READ(reg);
1383}
1384
89b667f8
JB		 1385void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1386{
1387 u32 port_mask;
1388
1389 if (!port)
1390 port_mask = DPLL_PORTB_READY_MASK;
1391 else
1392 port_mask = DPLL_PORTC_READY_MASK;
1393
1394 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1395 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1396 'B' + port, I915_READ(DPLL(0)));
1397}
1398
92f2584a 1399/**
b6b4e185 1400 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1401 * @dev_priv: i915 private structure
1402 * @pipe: pipe PLL to enable
1403 *
1404 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1405 * drives the transcoder clock.
1406 */
b6b4e185 1407static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1408{
ee7b9f93 1409 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1410 struct intel_pch_pll *pll;
92f2584a
JB		 1411 int reg;
1412 u32 val;
1413
48da64a8 1414 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1415 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1416 pll = intel_crtc->pch_pll;
1417 if (pll == NULL)
1418 return;
1419
1420 if (WARN_ON(pll->refcount == 0))
1421 return;
ee7b9f93
JB		 1422
1423 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1424 pll->pll_reg, pll->active, pll->on,
1425 intel_crtc->base.base.id);
92f2584a
JB		 1426
1427 /* PCH refclock must be enabled first */
1428 assert_pch_refclk_enabled(dev_priv);
1429
ee7b9f93 1430 if (pll->active++ && pll->on) {
92b27b08 1431 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1432 return;
1433 }
1434
1435 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1436
1437 reg = pll->pll_reg;
92f2584a
JB		 1438 val = I915_READ(reg);
1439 val |= DPLL_VCO_ENABLE;
1440 I915_WRITE(reg, val);
1441 POSTING_READ(reg);
1442 udelay(200);
ee7b9f93
JB		 1443
1444 pll->on = true;
92f2584a
JB		 1445}
1446
ee7b9f93 1447static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1448{
ee7b9f93
JB		 1449 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1450 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1451 int reg;
ee7b9f93 1452 u32 val;
4c609cb8 1453
92f2584a
JB		 1454 /* PCH only available on ILK+ */
1455 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1456 if (pll == NULL)
1457 return;
92f2584a 1458
48da64a8
CW		 1459 if (WARN_ON(pll->refcount == 0))
1460 return;
7a419866 1461
ee7b9f93
JB		 1462 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1463 pll->pll_reg, pll->active, pll->on,
1464 intel_crtc->base.base.id);
7a419866 1465
48da64a8 1466 if (WARN_ON(pll->active == 0)) {
92b27b08 1467 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1468 return;
1469 }
1470
ee7b9f93 1471 if (--pll->active) {
92b27b08 1472 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1473 return;
ee7b9f93
JB		 1474 }
1475
1476 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1477
1478 /* Make sure transcoder isn't still depending on us */
ab9412ba 1479 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1480
ee7b9f93 1481 reg = pll->pll_reg;
92f2584a
JB		 1482 val = I915_READ(reg);
1483 val &= ~DPLL_VCO_ENABLE;
1484 I915_WRITE(reg, val);
1485 POSTING_READ(reg);
1486 udelay(200);
ee7b9f93
JB		 1487
1488 pll->on = false;
92f2584a
JB		 1489}
1490
b8a4f404
PZ		 1491static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492 enum pipe pipe)
040484af 1493{
23670b32 1494 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1496 uint32_t reg, val, pipeconf_val;
040484af
JB		 1497
1498 /* PCH only available on ILK+ */
1499 BUG_ON(dev_priv->info->gen < 5);
1500
1501 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1502 assert_pch_pll_enabled(dev_priv,
1503 to_intel_crtc(crtc)->pch_pll,
1504 to_intel_crtc(crtc));
040484af
JB		 1505
1506 /* FDI must be feeding us bits for PCH ports */
1507 assert_fdi_tx_enabled(dev_priv, pipe);
1508 assert_fdi_rx_enabled(dev_priv, pipe);
1509
23670b32
DV		 1510 if (HAS_PCH_CPT(dev)) {
1511 /* Workaround: Set the timing override bit before enabling the
1512 * pch transcoder. */
1513 reg = TRANS_CHICKEN2(pipe);
1514 val = I915_READ(reg);
1515 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516 I915_WRITE(reg, val);
59c859d6 1517 }
23670b32 1518
ab9412ba 1519 reg = PCH_TRANSCONF(pipe);
040484af 1520 val = I915_READ(reg);
5f7f726d 1521 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1522
1523 if (HAS_PCH_IBX(dev_priv->dev)) {
1524 /*
1525 * make the BPC in transcoder be consistent with
1526 * that in pipeconf reg.
1527 */
dfd07d72
DV		 1528 val &= ~PIPECONF_BPC_MASK;
1529 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1530 }
5f7f726d
PZ		 1531
1532 val &= ~TRANS_INTERLACE_MASK;
1533 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1534 if (HAS_PCH_IBX(dev_priv->dev) &&
1535 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536 val |= TRANS_LEGACY_INTERLACED_ILK;
1537 else
1538 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1539 else
1540 val |= TRANS_PROGRESSIVE;
1541
040484af
JB		 1542 I915_WRITE(reg, val | TRANS_ENABLE);
1543 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1544 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1545}
1546
8fb033d7 1547static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1548 enum transcoder cpu_transcoder)
040484af 1549{
8fb033d7 1550 u32 val, pipeconf_val;
8fb033d7
PZ		 1551
1552 /* PCH only available on ILK+ */
1553 BUG_ON(dev_priv->info->gen < 5);
1554
8fb033d7 1555 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1556 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1557 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1558
223a6fdf
PZ		 1559 /* Workaround: set timing override bit. */
1560 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1561 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1562 I915_WRITE(_TRANSA_CHICKEN2, val);
1563
25f3ef11 1564 val = TRANS_ENABLE;
937bb610 1565 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1566
9a76b1c6
PZ		 1567 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568 PIPECONF_INTERLACED_ILK)
a35f2679 1569 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1570 else
1571 val |= TRANS_PROGRESSIVE;
1572
ab9412ba
DV		 1573 I915_WRITE(LPT_TRANSCONF, val);
1574 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1575 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1576}
1577
b8a4f404
PZ		 1578static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579 enum pipe pipe)
040484af 1580{
23670b32
DV		 1581 struct drm_device *dev = dev_priv->dev;
1582 uint32_t reg, val;
040484af
JB		 1583
1584 /* FDI relies on the transcoder */
1585 assert_fdi_tx_disabled(dev_priv, pipe);
1586 assert_fdi_rx_disabled(dev_priv, pipe);
1587
291906f1
JB		 1588 /* Ports must be off as well */
1589 assert_pch_ports_disabled(dev_priv, pipe);
1590
ab9412ba 1591 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1592 val = I915_READ(reg);
1593 val &= ~TRANS_ENABLE;
1594 I915_WRITE(reg, val);
1595 /* wait for PCH transcoder off, transcoder state */
1596 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1597 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1598
1599 if (!HAS_PCH_IBX(dev)) {
1600 /* Workaround: Clear the timing override chicken bit again. */
1601 reg = TRANS_CHICKEN2(pipe);
1602 val = I915_READ(reg);
1603 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604 I915_WRITE(reg, val);
1605 }
040484af
JB		 1606}
1607
ab4d966c 1608static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1609{
8fb033d7
PZ		 1610 u32 val;
1611
ab9412ba 1612 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1613 val &= ~TRANS_ENABLE;
ab9412ba 1614 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1615 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1616 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1617 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1618
1619 /* Workaround: clear timing override bit. */
1620 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1621 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1622 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1623}
1624
b24e7179 1625/**
309cfea8 1626 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1627 * @dev_priv: i915 private structure
1628 * @pipe: pipe to enable
040484af 1629 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1630 *
1631 * Enable @pipe, making sure that various hardware specific requirements
1632 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633 *
1634 * @pipe should be %PIPE_A or %PIPE_B.
1635 *
1636 * Will wait until the pipe is actually running (i.e. first vblank) before
1637 * returning.
1638 */
040484af
JB		 1639static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640 bool pch_port)
b24e7179 1641{
702e7a56
PZ		 1642 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643 pipe);
1a240d4d 1644 enum pipe pch_transcoder;
b24e7179
JB		 1645 int reg;
1646 u32 val;
1647
58c6eaa2
DV		 1648 assert_planes_disabled(dev_priv, pipe);
1649 assert_sprites_disabled(dev_priv, pipe);
1650
681e5811 1651 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1652 pch_transcoder = TRANSCODER_A;
1653 else
1654 pch_transcoder = pipe;
1655
b24e7179
JB		 1656 /*
1657 * A pipe without a PLL won't actually be able to drive bits from
1658 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1659 * need the check.
1660 */
1661 if (!HAS_PCH_SPLIT(dev_priv->dev))
1662 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1663 else {
1664 if (pch_port) {
1665 /* if driving the PCH, we need FDI enabled */
cc391bbb 1666 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1667 assert_fdi_tx_pll_enabled(dev_priv,
1668 (enum pipe) cpu_transcoder);
040484af
JB		 1669 }
1670 /* FIXME: assert CPU port conditions for SNB+ */
1671 }
b24e7179 1672
702e7a56 1673 reg = PIPECONF(cpu_transcoder);
b24e7179 1674 val = I915_READ(reg);
00d70b15
CW		 1675 if (val & PIPECONF_ENABLE)
1676 return;
1677
1678 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1679 intel_wait_for_vblank(dev_priv->dev, pipe);
1680}
1681
1682/**
309cfea8 1683 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1684 * @dev_priv: i915 private structure
1685 * @pipe: pipe to disable
1686 *
1687 * Disable @pipe, making sure that various hardware specific requirements
1688 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689 *
1690 * @pipe should be %PIPE_A or %PIPE_B.
1691 *
1692 * Will wait until the pipe has shut down before returning.
1693 */
1694static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
1696{
702e7a56
PZ		 1697 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698 pipe);
b24e7179
JB		 1699 int reg;
1700 u32 val;
1701
1702 /*
1703 * Make sure planes won't keep trying to pump pixels to us,
1704 * or we might hang the display.
1705 */
1706 assert_planes_disabled(dev_priv, pipe);
19332d7a 1707 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1708
1709 /* Don't disable pipe A or pipe A PLLs if needed */
1710 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711 return;
1712
702e7a56 1713 reg = PIPECONF(cpu_transcoder);
b24e7179 1714 val = I915_READ(reg);
00d70b15
CW		 1715 if ((val & PIPECONF_ENABLE) == 0)
1716 return;
1717
1718 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1719 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720}
1721
d74362c9
KP		 1722/*
1723 * Plane regs are double buffered, going from enabled->disabled needs a
1724 * trigger in order to latch. The display address reg provides this.
1725 */
6f1d69b0 1726void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1727 enum plane plane)
1728{
14f86147
DL		 1729 if (dev_priv->info->gen >= 4)
1730 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731 else
1732 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1733}
1734
b24e7179
JB		 1735/**
1736 * intel_enable_plane - enable a display plane on a given pipe
1737 * @dev_priv: i915 private structure
1738 * @plane: plane to enable
1739 * @pipe: pipe being fed
1740 *
1741 * Enable @plane on @pipe, making sure that @pipe is running first.
1742 */
1743static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744 enum plane plane, enum pipe pipe)
1745{
1746 int reg;
1747 u32 val;
1748
1749 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750 assert_pipe_enabled(dev_priv, pipe);
1751
1752 reg = DSPCNTR(plane);
1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & DISPLAY_PLANE_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1758 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
b24e7179
JB		 1762/**
1763 * intel_disable_plane - disable a display plane
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to disable
1766 * @pipe: pipe consuming the data
1767 *
1768 * Disable @plane; should be an independent operation.
1769 */
1770static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
00d70b15
CW		 1778 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779 return;
1780
1781 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
693db184
CW		 1786static bool need_vtd_wa(struct drm_device *dev)
1787{
1788#ifdef CONFIG_INTEL_IOMMU
1789 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790 return true;
1791#endif
1792 return false;
1793}
1794
127bd2ac 1795int
48b956c5 1796intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1797 struct drm_i915_gem_object *obj,
919926ae 1798 struct intel_ring_buffer *pipelined)
6b95a207 1799{
ce453d81 1800 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1801 u32 alignment;
1802 int ret;
1803
05394f39 1804 switch (obj->tiling_mode) {
6b95a207 1805 case I915_TILING_NONE:
534843da
CW		 1806 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807 alignment = 128 * 1024;
a6c45cf0 1808 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1809 alignment = 4 * 1024;
1810 else
1811 alignment = 64 * 1024;
6b95a207
KH		 1812 break;
1813 case I915_TILING_X:
1814 /* pin() will align the object as required by fence */
1815 alignment = 0;
1816 break;
1817 case I915_TILING_Y:
8bb6e959
DV		 1818 /* Despite that we check this in framebuffer_init userspace can
1819 * screw us over and change the tiling after the fact. Only
1820 * pinned buffers can't change their tiling. */
1821 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1822 return -EINVAL;
1823 default:
1824 BUG();
1825 }
1826
693db184
CW		 1827 /* Note that the w/a also requires 64 PTE of padding following the
1828 * bo. We currently fill all unused PTE with the shadow page and so
1829 * we should always have valid PTE following the scanout preventing
1830 * the VT-d warning.
1831 */
1832 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833 alignment = 256 * 1024;
1834
ce453d81 1835 dev_priv->mm.interruptible = false;
2da3b9b9 1836 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1837 if (ret)
ce453d81 1838 goto err_interruptible;
6b95a207
KH		 1839
1840 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841 * fence, whereas 965+ only requires a fence if using
1842 * framebuffer compression. For simplicity, we always install
1843 * a fence as the cost is not that onerous.
1844 */
06d98131 1845 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1846 if (ret)
1847 goto err_unpin;
1690e1eb 1848
9a5a53b3 1849 i915_gem_object_pin_fence(obj);
6b95a207 1850
ce453d81 1851 dev_priv->mm.interruptible = true;
6b95a207 1852 return 0;
48b956c5
CW		 1853
1854err_unpin:
1855 i915_gem_object_unpin(obj);
ce453d81
CW		 1856err_interruptible:
1857 dev_priv->mm.interruptible = true;
48b956c5 1858 return ret;
6b95a207
KH		 1859}
1860
1690e1eb
CW		 1861void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862{
1863 i915_gem_object_unpin_fence(obj);
1864 i915_gem_object_unpin(obj);
1865}
1866
c2c75131
DV		 1867/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868 * is assumed to be a power-of-two. */
bc752862
CW		 1869unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870 unsigned int tiling_mode,
1871 unsigned int cpp,
1872 unsigned int pitch)
c2c75131 1873{
bc752862
CW		 1874 if (tiling_mode != I915_TILING_NONE) {
1875 unsigned int tile_rows, tiles;
c2c75131 1876
bc752862
CW		 1877 tile_rows = *y / 8;
1878 *y %= 8;
c2c75131 1879
bc752862
CW		 1880 tiles = *x / (512/cpp);
1881 *x %= 512/cpp;
1882
1883 return tile_rows * pitch * 8 + tiles * 4096;
1884 } else {
1885 unsigned int offset;
1886
1887 offset = *y * pitch + *x * cpp;
1888 *y = 0;
1889 *x = (offset & 4095) / cpp;
1890 return offset & -4096;
1891 }
c2c75131
DV		 1892}
1893
17638cd6
JB		 1894static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895 int x, int y)
81255565
JB		 1896{
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900 struct intel_framebuffer *intel_fb;
05394f39 1901 struct drm_i915_gem_object *obj;
81255565 1902 int plane = intel_crtc->plane;
e506a0c6 1903 unsigned long linear_offset;
81255565 1904 u32 dspcntr;
5eddb70b 1905 u32 reg;
81255565
JB		 1906
1907 switch (plane) {
1908 case 0:
1909 case 1:
1910 break;
1911 default:
84f44ce7 1912 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1913 return -EINVAL;
1914 }
1915
1916 intel_fb = to_intel_framebuffer(fb);
1917 obj = intel_fb->obj;
81255565 1918
5eddb70b
CW		 1919 reg = DSPCNTR(plane);
1920 dspcntr = I915_READ(reg);
81255565
JB		 1921 /* Mask out pixel format bits in case we change it */
1922 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1923 switch (fb->pixel_format) {
1924 case DRM_FORMAT_C8:
81255565
JB		 1925 dspcntr |= DISPPLANE_8BPP;
1926 break;
57779d06
VS		 1927 case DRM_FORMAT_XRGB1555:
1928 case DRM_FORMAT_ARGB1555:
1929 dspcntr |= DISPPLANE_BGRX555;
81255565 1930 break;
57779d06
VS		 1931 case DRM_FORMAT_RGB565:
1932 dspcntr |= DISPPLANE_BGRX565;
1933 break;
1934 case DRM_FORMAT_XRGB8888:
1935 case DRM_FORMAT_ARGB8888:
1936 dspcntr |= DISPPLANE_BGRX888;
1937 break;
1938 case DRM_FORMAT_XBGR8888:
1939 case DRM_FORMAT_ABGR8888:
1940 dspcntr |= DISPPLANE_RGBX888;
1941 break;
1942 case DRM_FORMAT_XRGB2101010:
1943 case DRM_FORMAT_ARGB2101010:
1944 dspcntr |= DISPPLANE_BGRX101010;
1945 break;
1946 case DRM_FORMAT_XBGR2101010:
1947 case DRM_FORMAT_ABGR2101010:
1948 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1949 break;
1950 default:
baba133a 1951 BUG();
81255565 1952 }
57779d06 1953
a6c45cf0 1954 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1955 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1956 dspcntr |= DISPPLANE_TILED;
1957 else
1958 dspcntr &= ~DISPPLANE_TILED;
1959 }
1960
5eddb70b 1961 I915_WRITE(reg, dspcntr);
81255565 1962
e506a0c6 1963 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1964
c2c75131
DV		 1965 if (INTEL_INFO(dev)->gen >= 4) {
1966 intel_crtc->dspaddr_offset =
bc752862
CW		 1967 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1968 fb->bits_per_pixel / 8,
1969 fb->pitches[0]);
c2c75131
DV		 1970 linear_offset -= intel_crtc->dspaddr_offset;
1971 } else {
e506a0c6 1972 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1973 }
e506a0c6
DV		 1974
1975 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1976 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1977 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1978 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1979 I915_MODIFY_DISPBASE(DSPSURF(plane),
1980 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1981 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1982 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1983 } else
e506a0c6 1984 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1985 POSTING_READ(reg);
81255565 1986
17638cd6
JB		 1987 return 0;
1988}
1989
1990static int ironlake_update_plane(struct drm_crtc *crtc,
1991 struct drm_framebuffer *fb, int x, int y)
1992{
1993 struct drm_device *dev = crtc->dev;
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1996 struct intel_framebuffer *intel_fb;
1997 struct drm_i915_gem_object *obj;
1998 int plane = intel_crtc->plane;
e506a0c6 1999 unsigned long linear_offset;
17638cd6
JB		 2000 u32 dspcntr;
2001 u32 reg;
2002
2003 switch (plane) {
2004 case 0:
2005 case 1:
27f8227b 2006 case 2:
17638cd6
JB		 2007 break;
2008 default:
84f44ce7 2009 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2010 return -EINVAL;
2011 }
2012
2013 intel_fb = to_intel_framebuffer(fb);
2014 obj = intel_fb->obj;
2015
2016 reg = DSPCNTR(plane);
2017 dspcntr = I915_READ(reg);
2018 /* Mask out pixel format bits in case we change it */
2019 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2020 switch (fb->pixel_format) {
2021 case DRM_FORMAT_C8:
17638cd6
JB		 2022 dspcntr |= DISPPLANE_8BPP;
2023 break;
57779d06
VS		 2024 case DRM_FORMAT_RGB565:
2025 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2026 break;
57779d06
VS		 2027 case DRM_FORMAT_XRGB8888:
2028 case DRM_FORMAT_ARGB8888:
2029 dspcntr |= DISPPLANE_BGRX888;
2030 break;
2031 case DRM_FORMAT_XBGR8888:
2032 case DRM_FORMAT_ABGR8888:
2033 dspcntr |= DISPPLANE_RGBX888;
2034 break;
2035 case DRM_FORMAT_XRGB2101010:
2036 case DRM_FORMAT_ARGB2101010:
2037 dspcntr |= DISPPLANE_BGRX101010;
2038 break;
2039 case DRM_FORMAT_XBGR2101010:
2040 case DRM_FORMAT_ABGR2101010:
2041 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2042 break;
2043 default:
baba133a 2044 BUG();
17638cd6
JB		 2045 }
2046
2047 if (obj->tiling_mode != I915_TILING_NONE)
2048 dspcntr |= DISPPLANE_TILED;
2049 else
2050 dspcntr &= ~DISPPLANE_TILED;
2051
2052 /* must disable */
2053 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2054
2055 I915_WRITE(reg, dspcntr);
2056
e506a0c6 2057 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2058 intel_crtc->dspaddr_offset =
bc752862
CW		 2059 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2060 fb->bits_per_pixel / 8,
2061 fb->pitches[0]);
c2c75131 2062 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2063
e506a0c6
DV		 2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2067 I915_MODIFY_DISPBASE(DSPSURF(plane),
2068 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2069 if (IS_HASWELL(dev)) {
2070 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2071 } else {
2072 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2073 I915_WRITE(DSPLINOFF(plane), linear_offset);
2074 }
17638cd6
JB		 2075 POSTING_READ(reg);
2076
2077 return 0;
2078}
2079
2080/* Assume fb object is pinned & idle & fenced and just update base pointers */
2081static int
2082intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2083 int x, int y, enum mode_set_atomic state)
2084{
2085 struct drm_device *dev = crtc->dev;
2086 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2087
6b8e6ed0
CW		 2088 if (dev_priv->display.disable_fbc)
2089 dev_priv->display.disable_fbc(dev);
3dec0095 2090 intel_increase_pllclock(crtc);
81255565 2091
6b8e6ed0 2092 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2093}
2094
96a02917
VS		 2095void intel_display_handle_reset(struct drm_device *dev)
2096{
2097 struct drm_i915_private *dev_priv = dev->dev_private;
2098 struct drm_crtc *crtc;
2099
2100 /*
2101 * Flips in the rings have been nuked by the reset,
2102 * so complete all pending flips so that user space
2103 * will get its events and not get stuck.
2104 *
2105 * Also update the base address of all primary
2106 * planes to the the last fb to make sure we're
2107 * showing the correct fb after a reset.
2108 *
2109 * Need to make two loops over the crtcs so that we
2110 * don't try to grab a crtc mutex before the
2111 * pending_flip_queue really got woken up.
2112 */
2113
2114 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2116 enum plane plane = intel_crtc->plane;
2117
2118 intel_prepare_page_flip(dev, plane);
2119 intel_finish_page_flip_plane(dev, plane);
2120 }
2121
2122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124
2125 mutex_lock(&crtc->mutex);
2126 if (intel_crtc->active)
2127 dev_priv->display.update_plane(crtc, crtc->fb,
2128 crtc->x, crtc->y);
2129 mutex_unlock(&crtc->mutex);
2130 }
2131}
2132
14667a4b
CW		 2133static int
2134intel_finish_fb(struct drm_framebuffer *old_fb)
2135{
2136 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2137 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2138 bool was_interruptible = dev_priv->mm.interruptible;
2139 int ret;
2140
14667a4b
CW		 2141 /* Big Hammer, we also need to ensure that any pending
2142 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2143 * current scanout is retired before unpinning the old
2144 * framebuffer.
2145 *
2146 * This should only fail upon a hung GPU, in which case we
2147 * can safely continue.
2148 */
2149 dev_priv->mm.interruptible = false;
2150 ret = i915_gem_object_finish_gpu(obj);
2151 dev_priv->mm.interruptible = was_interruptible;
2152
2153 return ret;
2154}
2155
198598d0
VS		 2156static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_master_private *master_priv;
2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161
2162 if (!dev->primary->master)
2163 return;
2164
2165 master_priv = dev->primary->master->driver_priv;
2166 if (!master_priv->sarea_priv)
2167 return;
2168
2169 switch (intel_crtc->pipe) {
2170 case 0:
2171 master_priv->sarea_priv->pipeA_x = x;
2172 master_priv->sarea_priv->pipeA_y = y;
2173 break;
2174 case 1:
2175 master_priv->sarea_priv->pipeB_x = x;
2176 master_priv->sarea_priv->pipeB_y = y;
2177 break;
2178 default:
2179 break;
2180 }
2181}
2182
5c3b82e2 2183static int
3c4fdcfb 2184intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2185 struct drm_framebuffer *fb)
79e53945
JB		 2186{
2187 struct drm_device *dev = crtc->dev;
6b8e6ed0 2188 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2190 struct drm_framebuffer *old_fb;
5c3b82e2 2191 int ret;
79e53945
JB		 2192
2193 /* no fb bound */
94352cf9 2194 if (!fb) {
a5071c2f 2195 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2196 return 0;
2197 }
2198
7eb552ae 2199 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2200 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2201 plane_name(intel_crtc->plane),
2202 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2203 return -EINVAL;
79e53945
JB		 2204 }
2205
5c3b82e2 2206 mutex_lock(&dev->struct_mutex);
265db958 2207 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2208 to_intel_framebuffer(fb)->obj,
919926ae 2209 NULL);
5c3b82e2
CW		 2210 if (ret != 0) {
2211 mutex_unlock(&dev->struct_mutex);
a5071c2f 2212 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2213 return ret;
2214 }
79e53945 2215
94352cf9 2216 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2217 if (ret) {
94352cf9 2218 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2219 mutex_unlock(&dev->struct_mutex);
a5071c2f 2220 DRM_ERROR("failed to update base address\n");
4e6cfefc 2221 return ret;
79e53945 2222 }
3c4fdcfb 2223
94352cf9
DV		 2224 old_fb = crtc->fb;
2225 crtc->fb = fb;
6c4c86f5
DV		 2226 crtc->x = x;
2227 crtc->y = y;
94352cf9 2228
b7f1de28 2229 if (old_fb) {
d7697eea
DV		 2230 if (intel_crtc->active && old_fb != fb)
2231 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2232 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2233 }
652c393a 2234
6b8e6ed0 2235 intel_update_fbc(dev);
5c3b82e2 2236 mutex_unlock(&dev->struct_mutex);
79e53945 2237
198598d0 2238 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2239
2240 return 0;
79e53945
JB		 2241}
2242
5e84e1a4
ZW		 2243static void intel_fdi_normal_train(struct drm_crtc *crtc)
2244{
2245 struct drm_device *dev = crtc->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2248 int pipe = intel_crtc->pipe;
2249 u32 reg, temp;
2250
2251 /* enable normal train */
2252 reg = FDI_TX_CTL(pipe);
2253 temp = I915_READ(reg);
61e499bf 2254 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2255 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2256 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2257 } else {
2258 temp &= ~FDI_LINK_TRAIN_NONE;
2259 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2260 }
5e84e1a4
ZW		 2261 I915_WRITE(reg, temp);
2262
2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2268 } else {
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_NONE;
2271 }
2272 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2273
2274 /* wait one idle pattern time */
2275 POSTING_READ(reg);
2276 udelay(1000);
357555c0
JB		 2277
2278 /* IVB wants error correction enabled */
2279 if (IS_IVYBRIDGE(dev))
2280 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2281 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2282}
2283
1e833f40
DV		 2284static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2285{
2286 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2287}
2288
01a415fd
DV		 2289static void ivb_modeset_global_resources(struct drm_device *dev)
2290{
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292 struct intel_crtc *pipe_B_crtc =
2293 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2294 struct intel_crtc *pipe_C_crtc =
2295 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2296 uint32_t temp;
2297
1e833f40
DV		 2298 /*
2299 * When everything is off disable fdi C so that we could enable fdi B
2300 * with all lanes. Note that we don't care about enabled pipes without
2301 * an enabled pch encoder.
2302 */
2303 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2304 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2305 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2306 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2307
2308 temp = I915_READ(SOUTH_CHICKEN1);
2309 temp &= ~FDI_BC_BIFURCATION_SELECT;
2310 DRM_DEBUG_KMS("disabling fdi C rx\n");
2311 I915_WRITE(SOUTH_CHICKEN1, temp);
2312 }
2313}
2314
8db9d77b
ZW		 2315/* The FDI link training functions for ILK/Ibexpeak. */
2316static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2317{
2318 struct drm_device *dev = crtc->dev;
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2321 int pipe = intel_crtc->pipe;
0fc932b8 2322 int plane = intel_crtc->plane;
5eddb70b 2323 u32 reg, temp, tries;
8db9d77b 2324
0fc932b8
JB		 2325 /* FDI needs bits from pipe & plane first */
2326 assert_pipe_enabled(dev_priv, pipe);
2327 assert_plane_enabled(dev_priv, plane);
2328
e1a44743
AJ		 2329 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2330 for train result */
5eddb70b
CW		 2331 reg = FDI_RX_IMR(pipe);
2332 temp = I915_READ(reg);
e1a44743
AJ		 2333 temp &= ~FDI_RX_SYMBOL_LOCK;
2334 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2335 I915_WRITE(reg, temp);
2336 I915_READ(reg);
e1a44743
AJ		 2337 udelay(150);
2338
8db9d77b 2339 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
627eb5a3
DV		 2342 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2343 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2346 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2347
5eddb70b
CW		 2348 reg = FDI_RX_CTL(pipe);
2349 temp = I915_READ(reg);
8db9d77b
ZW		 2350 temp &= ~FDI_LINK_TRAIN_NONE;
2351 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2352 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2353
2354 POSTING_READ(reg);
8db9d77b
ZW		 2355 udelay(150);
2356
5b2adf89 2357 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2358 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2359 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2360 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2361
5eddb70b 2362 reg = FDI_RX_IIR(pipe);
e1a44743 2363 for (tries = 0; tries < 5; tries++) {
5eddb70b 2364 temp = I915_READ(reg);
8db9d77b
ZW		 2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if ((temp & FDI_RX_BIT_LOCK)) {
2368 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2369 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2370 break;
2371 }
8db9d77b 2372 }
e1a44743 2373 if (tries == 5)
5eddb70b 2374 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2375
2376 /* Train 2 */
5eddb70b
CW		 2377 reg = FDI_TX_CTL(pipe);
2378 temp = I915_READ(reg);
8db9d77b
ZW		 2379 temp &= ~FDI_LINK_TRAIN_NONE;
2380 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2381 I915_WRITE(reg, temp);
8db9d77b 2382
5eddb70b
CW		 2383 reg = FDI_RX_CTL(pipe);
2384 temp = I915_READ(reg);
8db9d77b
ZW		 2385 temp &= ~FDI_LINK_TRAIN_NONE;
2386 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2387 I915_WRITE(reg, temp);
8db9d77b 2388
5eddb70b
CW		 2389 POSTING_READ(reg);
2390 udelay(150);
8db9d77b 2391
5eddb70b 2392 reg = FDI_RX_IIR(pipe);
e1a44743 2393 for (tries = 0; tries < 5; tries++) {
5eddb70b 2394 temp = I915_READ(reg);
8db9d77b
ZW		 2395 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2396
2397 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2398 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2399 DRM_DEBUG_KMS("FDI train 2 done.\n");
2400 break;
2401 }
8db9d77b 2402 }
e1a44743 2403 if (tries == 5)
5eddb70b 2404 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2405
2406 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2407
8db9d77b
ZW		 2408}
2409
0206e353 2410static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2411 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2412 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2413 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2414 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2415};
2416
2417/* The FDI link training functions for SNB/Cougarpoint. */
2418static void gen6_fdi_link_train(struct drm_crtc *crtc)
2419{
2420 struct drm_device *dev = crtc->dev;
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423 int pipe = intel_crtc->pipe;
fa37d39e 2424 u32 reg, temp, i, retry;
8db9d77b 2425
e1a44743
AJ		 2426 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2427 for train result */
5eddb70b
CW		 2428 reg = FDI_RX_IMR(pipe);
2429 temp = I915_READ(reg);
e1a44743
AJ		 2430 temp &= ~FDI_RX_SYMBOL_LOCK;
2431 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2432 I915_WRITE(reg, temp);
2433
2434 POSTING_READ(reg);
e1a44743
AJ		 2435 udelay(150);
2436
8db9d77b 2437 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2438 reg = FDI_TX_CTL(pipe);
2439 temp = I915_READ(reg);
627eb5a3
DV		 2440 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2441 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_PATTERN_1;
2444 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2445 /* SNB-B */
2446 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2447 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2448
d74cf324
DV		 2449 I915_WRITE(FDI_RX_MISC(pipe),
2450 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2451
5eddb70b
CW		 2452 reg = FDI_RX_CTL(pipe);
2453 temp = I915_READ(reg);
8db9d77b
ZW		 2454 if (HAS_PCH_CPT(dev)) {
2455 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2456 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2457 } else {
2458 temp &= ~FDI_LINK_TRAIN_NONE;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1;
2460 }
5eddb70b
CW		 2461 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2462
2463 POSTING_READ(reg);
8db9d77b
ZW		 2464 udelay(150);
2465
0206e353 2466 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2467 reg = FDI_TX_CTL(pipe);
2468 temp = I915_READ(reg);
8db9d77b
ZW		 2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2471 I915_WRITE(reg, temp);
2472
2473 POSTING_READ(reg);
8db9d77b
ZW		 2474 udelay(500);
2475
fa37d39e
SP		 2476 for (retry = 0; retry < 5; retry++) {
2477 reg = FDI_RX_IIR(pipe);
2478 temp = I915_READ(reg);
2479 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2480 if (temp & FDI_RX_BIT_LOCK) {
2481 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2482 DRM_DEBUG_KMS("FDI train 1 done.\n");
2483 break;
2484 }
2485 udelay(50);
8db9d77b 2486 }
fa37d39e
SP		 2487 if (retry < 5)
2488 break;
8db9d77b
ZW		 2489 }
2490 if (i == 4)
5eddb70b 2491 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2492
2493 /* Train 2 */
5eddb70b
CW		 2494 reg = FDI_TX_CTL(pipe);
2495 temp = I915_READ(reg);
8db9d77b
ZW		 2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2;
2498 if (IS_GEN6(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2500 /* SNB-B */
2501 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2502 }
5eddb70b 2503 I915_WRITE(reg, temp);
8db9d77b 2504
5eddb70b
CW		 2505 reg = FDI_RX_CTL(pipe);
2506 temp = I915_READ(reg);
8db9d77b
ZW		 2507 if (HAS_PCH_CPT(dev)) {
2508 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2509 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2510 } else {
2511 temp &= ~FDI_LINK_TRAIN_NONE;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2;
2513 }
5eddb70b
CW		 2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
8db9d77b
ZW		 2517 udelay(150);
2518
0206e353 2519 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2524 I915_WRITE(reg, temp);
2525
2526 POSTING_READ(reg);
8db9d77b
ZW		 2527 udelay(500);
2528
fa37d39e
SP		 2529 for (retry = 0; retry < 5; retry++) {
2530 reg = FDI_RX_IIR(pipe);
2531 temp = I915_READ(reg);
2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533 if (temp & FDI_RX_SYMBOL_LOCK) {
2534 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2535 DRM_DEBUG_KMS("FDI train 2 done.\n");
2536 break;
2537 }
2538 udelay(50);
8db9d77b 2539 }
fa37d39e
SP		 2540 if (retry < 5)
2541 break;
8db9d77b
ZW		 2542 }
2543 if (i == 4)
5eddb70b 2544 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2545
2546 DRM_DEBUG_KMS("FDI train done.\n");
2547}
2548
357555c0
JB		 2549/* Manual link training for Ivy Bridge A0 parts */
2550static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2551{
2552 struct drm_device *dev = crtc->dev;
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2555 int pipe = intel_crtc->pipe;
2556 u32 reg, temp, i;
2557
2558 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2559 for train result */
2560 reg = FDI_RX_IMR(pipe);
2561 temp = I915_READ(reg);
2562 temp &= ~FDI_RX_SYMBOL_LOCK;
2563 temp &= ~FDI_RX_BIT_LOCK;
2564 I915_WRITE(reg, temp);
2565
2566 POSTING_READ(reg);
2567 udelay(150);
2568
01a415fd
DV		 2569 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2570 I915_READ(FDI_RX_IIR(pipe)));
2571
357555c0
JB		 2572 /* enable CPU FDI TX and PCH FDI RX */
2573 reg = FDI_TX_CTL(pipe);
2574 temp = I915_READ(reg);
627eb5a3
DV		 2575 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2576 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2577 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2578 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2581 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2582 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2583
d74cf324
DV		 2584 I915_WRITE(FDI_RX_MISC(pipe),
2585 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2586
357555c0
JB		 2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~FDI_LINK_TRAIN_AUTO;
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2592 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2593 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2594
2595 POSTING_READ(reg);
2596 udelay(150);
2597
0206e353 2598 for (i = 0; i < 4; i++) {
357555c0
JB		 2599 reg = FDI_TX_CTL(pipe);
2600 temp = I915_READ(reg);
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= snb_b_fdi_train_param[i];
2603 I915_WRITE(reg, temp);
2604
2605 POSTING_READ(reg);
2606 udelay(500);
2607
2608 reg = FDI_RX_IIR(pipe);
2609 temp = I915_READ(reg);
2610 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2611
2612 if (temp & FDI_RX_BIT_LOCK ||
2613 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2614 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2615 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2616 break;
2617 }
2618 }
2619 if (i == 4)
2620 DRM_ERROR("FDI train 1 fail!\n");
2621
2622 /* Train 2 */
2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2625 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2626 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2629 I915_WRITE(reg, temp);
2630
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2635 I915_WRITE(reg, temp);
2636
2637 POSTING_READ(reg);
2638 udelay(150);
2639
0206e353 2640 for (i = 0; i < 4; i++) {
357555c0
JB		 2641 reg = FDI_TX_CTL(pipe);
2642 temp = I915_READ(reg);
2643 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644 temp |= snb_b_fdi_train_param[i];
2645 I915_WRITE(reg, temp);
2646
2647 POSTING_READ(reg);
2648 udelay(500);
2649
2650 reg = FDI_RX_IIR(pipe);
2651 temp = I915_READ(reg);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653
2654 if (temp & FDI_RX_SYMBOL_LOCK) {
2655 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2656 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2657 break;
2658 }
2659 }
2660 if (i == 4)
2661 DRM_ERROR("FDI train 2 fail!\n");
2662
2663 DRM_DEBUG_KMS("FDI train done.\n");
2664}
2665
88cefb6c 2666static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2667{
88cefb6c 2668 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2669 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2670 int pipe = intel_crtc->pipe;
5eddb70b 2671 u32 reg, temp;
79e53945 2672
c64e311e 2673
c98e9dcf 2674 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
627eb5a3
DV		 2677 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2678 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2679 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2680 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2681
2682 POSTING_READ(reg);
c98e9dcf
JB		 2683 udelay(200);
2684
2685 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2686 temp = I915_READ(reg);
2687 I915_WRITE(reg, temp | FDI_PCDCLK);
2688
2689 POSTING_READ(reg);
c98e9dcf
JB		 2690 udelay(200);
2691
20749730
PZ		 2692 /* Enable CPU FDI TX PLL, always on for Ironlake */
2693 reg = FDI_TX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2696 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2697
20749730
PZ		 2698 POSTING_READ(reg);
2699 udelay(100);
6be4a607 2700 }
0e23b99d
JB		 2701}
2702
88cefb6c
DV		 2703static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2704{
2705 struct drm_device *dev = intel_crtc->base.dev;
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp;
2709
2710 /* Switch from PCDclk to Rawclk */
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2714
2715 /* Disable CPU FDI TX PLL */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2719
2720 POSTING_READ(reg);
2721 udelay(100);
2722
2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2726
2727 /* Wait for the clocks to turn off. */
2728 POSTING_READ(reg);
2729 udelay(100);
2730}
2731
0fc932b8
JB		 2732static void ironlake_fdi_disable(struct drm_crtc *crtc)
2733{
2734 struct drm_device *dev = crtc->dev;
2735 struct drm_i915_private *dev_priv = dev->dev_private;
2736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2737 int pipe = intel_crtc->pipe;
2738 u32 reg, temp;
2739
2740 /* disable CPU FDI tx and PCH FDI rx */
2741 reg = FDI_TX_CTL(pipe);
2742 temp = I915_READ(reg);
2743 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2744 POSTING_READ(reg);
2745
2746 reg = FDI_RX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 temp &= ~(0x7 << 16);
dfd07d72 2749 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2750 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2751
2752 POSTING_READ(reg);
2753 udelay(100);
2754
2755 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2756 if (HAS_PCH_IBX(dev)) {
2757 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2758 }
0fc932b8
JB		 2759
2760 /* still set train pattern 1 */
2761 reg = FDI_TX_CTL(pipe);
2762 temp = I915_READ(reg);
2763 temp &= ~FDI_LINK_TRAIN_NONE;
2764 temp |= FDI_LINK_TRAIN_PATTERN_1;
2765 I915_WRITE(reg, temp);
2766
2767 reg = FDI_RX_CTL(pipe);
2768 temp = I915_READ(reg);
2769 if (HAS_PCH_CPT(dev)) {
2770 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2771 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2772 } else {
2773 temp &= ~FDI_LINK_TRAIN_NONE;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1;
2775 }
2776 /* BPC in FDI rx is consistent with that in PIPECONF */
2777 temp &= ~(0x07 << 16);
dfd07d72 2778 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2779 I915_WRITE(reg, temp);
2780
2781 POSTING_READ(reg);
2782 udelay(100);
2783}
2784
5bb61643
CW		 2785static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2786{
2787 struct drm_device *dev = crtc->dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2790 unsigned long flags;
2791 bool pending;
2792
10d83730
VS		 2793 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2794 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2795 return false;
2796
2797 spin_lock_irqsave(&dev->event_lock, flags);
2798 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2799 spin_unlock_irqrestore(&dev->event_lock, flags);
2800
2801 return pending;
2802}
2803
e6c3a2a6
CW		 2804static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2805{
0f91128d 2806 struct drm_device *dev = crtc->dev;
5bb61643 2807 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2808
2809 if (crtc->fb == NULL)
2810 return;
2811
2c10d571
DV		 2812 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2813
5bb61643
CW		 2814 wait_event(dev_priv->pending_flip_queue,
2815 !intel_crtc_has_pending_flip(crtc));
2816
0f91128d
CW		 2817 mutex_lock(&dev->struct_mutex);
2818 intel_finish_fb(crtc->fb);
2819 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2820}
2821
e615efe4
ED		 2822/* Program iCLKIP clock to the desired frequency */
2823static void lpt_program_iclkip(struct drm_crtc *crtc)
2824{
2825 struct drm_device *dev = crtc->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2828 u32 temp;
2829
09153000
DV		 2830 mutex_lock(&dev_priv->dpio_lock);
2831
e615efe4
ED		 2832 /* It is necessary to ungate the pixclk gate prior to programming
2833 * the divisors, and gate it back when it is done.
2834 */
2835 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2836
2837 /* Disable SSCCTL */
2838 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2839 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2840 SBI_SSCCTL_DISABLE,
2841 SBI_ICLK);
e615efe4
ED		 2842
2843 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2844 if (crtc->mode.clock == 20000) {
2845 auxdiv = 1;
2846 divsel = 0x41;
2847 phaseinc = 0x20;
2848 } else {
2849 /* The iCLK virtual clock root frequency is in MHz,
2850 * but the crtc->mode.clock in in KHz. To get the divisors,
2851 * it is necessary to divide one by another, so we
2852 * convert the virtual clock precision to KHz here for higher
2853 * precision.
2854 */
2855 u32 iclk_virtual_root_freq = 172800 * 1000;
2856 u32 iclk_pi_range = 64;
2857 u32 desired_divisor, msb_divisor_value, pi_value;
2858
2859 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2860 msb_divisor_value = desired_divisor / iclk_pi_range;
2861 pi_value = desired_divisor % iclk_pi_range;
2862
2863 auxdiv = 0;
2864 divsel = msb_divisor_value - 2;
2865 phaseinc = pi_value;
2866 }
2867
2868 /* This should not happen with any sane values */
2869 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2870 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2871 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2872 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2873
2874 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2875 crtc->mode.clock,
2876 auxdiv,
2877 divsel,
2878 phasedir,
2879 phaseinc);
2880
2881 /* Program SSCDIVINTPHASE6 */
988d6ee8 2882 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2883 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2884 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2885 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2886 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2887 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2888 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2889 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2890
2891 /* Program SSCAUXDIV */
988d6ee8 2892 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2893 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2894 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2895 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2896
2897 /* Enable modulator and associated divider */
988d6ee8 2898 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2899 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2900 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2901
2902 /* Wait for initialization time */
2903 udelay(24);
2904
2905 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2906
2907 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2908}
2909
275f01b2
DV		 2910static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2911 enum pipe pch_transcoder)
2912{
2913 struct drm_device *dev = crtc->base.dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2916
2917 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2918 I915_READ(HTOTAL(cpu_transcoder)));
2919 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2920 I915_READ(HBLANK(cpu_transcoder)));
2921 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2922 I915_READ(HSYNC(cpu_transcoder)));
2923
2924 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2925 I915_READ(VTOTAL(cpu_transcoder)));
2926 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2927 I915_READ(VBLANK(cpu_transcoder)));
2928 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2929 I915_READ(VSYNC(cpu_transcoder)));
2930 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2931 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2932}
2933
f67a559d
JB		 2934/*
2935 * Enable PCH resources required for PCH ports:
2936 * - PCH PLLs
2937 * - FDI training & RX/TX
2938 * - update transcoder timings
2939 * - DP transcoding bits
2940 * - transcoder
2941 */
2942static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2943{
2944 struct drm_device *dev = crtc->dev;
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947 int pipe = intel_crtc->pipe;
ee7b9f93 2948 u32 reg, temp;
2c07245f 2949
ab9412ba 2950 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2951
cd986abb
DV		 2952 /* Write the TU size bits before fdi link training, so that error
2953 * detection works. */
2954 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2955 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2956
c98e9dcf 2957 /* For PCH output, training FDI link */
674cf967 2958 dev_priv->display.fdi_link_train(crtc);
2c07245f 2959
572deb37
DV		 2960 /* XXX: pch pll's can be enabled any time before we enable the PCH
2961 * transcoder, and we actually should do this to not upset any PCH
2962 * transcoder that already use the clock when we share it.
2963 *
2964 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2965 * unconditionally resets the pll - we need that to have the right LVDS
2966 * enable sequence. */
b6b4e185 2967 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2968
303b81e0 2969 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2970 u32 sel;
4b645f14 2971
c98e9dcf 2972 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2973 switch (pipe) {
2974 default:
2975 case 0:
2976 temp |= TRANSA_DPLL_ENABLE;
2977 sel = TRANSA_DPLLB_SEL;
2978 break;
2979 case 1:
2980 temp |= TRANSB_DPLL_ENABLE;
2981 sel = TRANSB_DPLLB_SEL;
2982 break;
2983 case 2:
2984 temp |= TRANSC_DPLL_ENABLE;
2985 sel = TRANSC_DPLLB_SEL;
2986 break;
d64311ab 2987 }
ee7b9f93
JB		 2988 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2989 temp |= sel;
2990 else
2991 temp &= ~sel;
c98e9dcf 2992 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2993 }
5eddb70b 2994
d9b6cb56
JB		 2995 /* set transcoder timing, panel must allow it */
2996 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2997 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2998
303b81e0 2999 intel_fdi_normal_train(crtc);
5e84e1a4 3000
c98e9dcf
JB		 3001 /* For PCH DP, enable TRANS_DP_CTL */
3002 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3003 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3004 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3005 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3006 reg = TRANS_DP_CTL(pipe);
3007 temp = I915_READ(reg);
3008 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3009 TRANS_DP_SYNC_MASK |
3010 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3011 temp |= (TRANS_DP_OUTPUT_ENABLE |
3012 TRANS_DP_ENH_FRAMING);
9325c9f0 3013 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3014
3015 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3016 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3017 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3018 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3019
3020 switch (intel_trans_dp_port_sel(crtc)) {
3021 case PCH_DP_B:
5eddb70b 3022 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3023 break;
3024 case PCH_DP_C:
5eddb70b 3025 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3026 break;
3027 case PCH_DP_D:
5eddb70b 3028 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3029 break;
3030 default:
e95d41e1 3031 BUG();
32f9d658 3032 }
2c07245f 3033
5eddb70b 3034 I915_WRITE(reg, temp);
6be4a607 3035 }
b52eb4dc 3036
b8a4f404 3037 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3038}
3039
1507e5bd
PZ		 3040static void lpt_pch_enable(struct drm_crtc *crtc)
3041{
3042 struct drm_device *dev = crtc->dev;
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3045 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3046
ab9412ba 3047 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3048
8c52b5e8 3049 lpt_program_iclkip(crtc);
1507e5bd 3050
0540e488 3051 /* Set transcoder timing. */
275f01b2 3052 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3053
937bb610 3054 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3055}
3056
ee7b9f93
JB		 3057static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058{
3059 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061 if (pll == NULL)
3062 return;
3063
3064 if (pll->refcount == 0) {
3065 WARN(1, "bad PCH PLL refcount\n");
3066 return;
3067 }
3068
3069 --pll->refcount;
3070 intel_crtc->pch_pll = NULL;
3071}
3072
3073static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074{
3075 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076 struct intel_pch_pll *pll;
3077 int i;
3078
3079 pll = intel_crtc->pch_pll;
3080 if (pll) {
3081 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082 intel_crtc->base.base.id, pll->pll_reg);
3083 goto prepare;
3084 }
3085
98b6bd99
DV		 3086 if (HAS_PCH_IBX(dev_priv->dev)) {
3087 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088 i = intel_crtc->pipe;
3089 pll = &dev_priv->pch_plls[i];
3090
3091 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092 intel_crtc->base.base.id, pll->pll_reg);
3093
3094 goto found;
3095 }
3096
ee7b9f93
JB		 3097 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098 pll = &dev_priv->pch_plls[i];
3099
3100 /* Only want to check enabled timings first */
3101 if (pll->refcount == 0)
3102 continue;
3103
3104 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105 fp == I915_READ(pll->fp0_reg)) {
3106 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107 intel_crtc->base.base.id,
3108 pll->pll_reg, pll->refcount, pll->active);
3109
3110 goto found;
3111 }
3112 }
3113
3114 /* Ok no matching timings, maybe there's a free one? */
3115 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116 pll = &dev_priv->pch_plls[i];
3117 if (pll->refcount == 0) {
3118 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119 intel_crtc->base.base.id, pll->pll_reg);
3120 goto found;
3121 }
3122 }
3123
3124 return NULL;
3125
3126found:
3127 intel_crtc->pch_pll = pll;
3128 pll->refcount++;
84f44ce7 3129 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3130prepare: /* separate function? */
3131 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3132
e04c7350
CW		 3133 /* Wait for the clocks to stabilize before rewriting the regs */
3134 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3135 POSTING_READ(pll->pll_reg);
3136 udelay(150);
e04c7350
CW		 3137
3138 I915_WRITE(pll->fp0_reg, fp);
3139 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3140 pll->on = false;
3141 return pll;
3142}
3143
a1520318 3144static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3147 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3148 u32 temp;
3149
3150 temp = I915_READ(dslreg);
3151 udelay(500);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3153 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3154 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3155 }
3156}
3157
b074cec8
JB		 3158static void ironlake_pfit_enable(struct intel_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->base.dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162 int pipe = crtc->pipe;
3163
0ef37f3f 3164 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3165 /* Force use of hard-coded filter coefficients
3166 * as some pre-programmed values are broken,
3167 * e.g. x201.
3168 */
3169 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3170 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3171 PF_PIPE_SEL_IVB(pipe));
3172 else
3173 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3174 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3175 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3176 }
3177}
3178
bb53d4ae
VS		 3179static void intel_enable_planes(struct drm_crtc *crtc)
3180{
3181 struct drm_device *dev = crtc->dev;
3182 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3183 struct intel_plane *intel_plane;
3184
3185 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3186 if (intel_plane->pipe == pipe)
3187 intel_plane_restore(&intel_plane->base);
3188}
3189
3190static void intel_disable_planes(struct drm_crtc *crtc)
3191{
3192 struct drm_device *dev = crtc->dev;
3193 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3194 struct intel_plane *intel_plane;
3195
3196 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3197 if (intel_plane->pipe == pipe)
3198 intel_plane_disable(&intel_plane->base);
3199}
3200
f67a559d
JB		 3201static void ironlake_crtc_enable(struct drm_crtc *crtc)
3202{
3203 struct drm_device *dev = crtc->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3206 struct intel_encoder *encoder;
f67a559d
JB		 3207 int pipe = intel_crtc->pipe;
3208 int plane = intel_crtc->plane;
3209 u32 temp;
f67a559d 3210
08a48469
DV		 3211 WARN_ON(!crtc->enabled);
3212
f67a559d
JB		 3213 if (intel_crtc->active)
3214 return;
3215
3216 intel_crtc->active = true;
8664281b
PZ		 3217
3218 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3219 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3220
f67a559d
JB		 3221 intel_update_watermarks(dev);
3222
3223 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3224 temp = I915_READ(PCH_LVDS);
3225 if ((temp & LVDS_PORT_EN) == 0)
3226 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3227 }
3228
f67a559d 3229
5bfe2ac0 3230 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3231 /* Note: FDI PLL enabling _must_ be done before we enable the
3232 * cpu pipes, hence this is separate from all the other fdi/pch
3233 * enabling. */
88cefb6c 3234 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3235 } else {
3236 assert_fdi_tx_disabled(dev_priv, pipe);
3237 assert_fdi_rx_disabled(dev_priv, pipe);
3238 }
f67a559d 3239
bf49ec8c
DV		 3240 for_each_encoder_on_crtc(dev, crtc, encoder)
3241 if (encoder->pre_enable)
3242 encoder->pre_enable(encoder);
f67a559d
JB		 3243
3244 /* Enable panel fitting for LVDS */
b074cec8 3245 ironlake_pfit_enable(intel_crtc);
f67a559d 3246
9c54c0dd
JB		 3247 /*
3248 * On ILK+ LUT must be loaded before the pipe is running but with
3249 * clocks enabled
3250 */
3251 intel_crtc_load_lut(crtc);
3252
5bfe2ac0
DV		 3253 intel_enable_pipe(dev_priv, pipe,
3254 intel_crtc->config.has_pch_encoder);
f67a559d 3255 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3256 intel_enable_planes(crtc);
5c38d48c 3257 intel_crtc_update_cursor(crtc, true);
f67a559d 3258
5bfe2ac0 3259 if (intel_crtc->config.has_pch_encoder)
f67a559d 3260 ironlake_pch_enable(crtc);
c98e9dcf 3261
d1ebd816 3262 mutex_lock(&dev->struct_mutex);
bed4a673 3263 intel_update_fbc(dev);
d1ebd816
BW		 3264 mutex_unlock(&dev->struct_mutex);
3265
fa5c73b1
DV		 3266 for_each_encoder_on_crtc(dev, crtc, encoder)
3267 encoder->enable(encoder);
61b77ddd
DV		 3268
3269 if (HAS_PCH_CPT(dev))
a1520318 3270 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3271
3272 /*
3273 * There seems to be a race in PCH platform hw (at least on some
3274 * outputs) where an enabled pipe still completes any pageflip right
3275 * away (as if the pipe is off) instead of waiting for vblank. As soon
3276 * as the first vblank happend, everything works as expected. Hence just
3277 * wait for one vblank before returning to avoid strange things
3278 * happening.
3279 */
3280 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3281}
3282
42db64ef
PZ		 3283/* IPS only exists on ULT machines and is tied to pipe A. */
3284static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3285{
3286 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3287}
3288
3289static void hsw_enable_ips(struct intel_crtc *crtc)
3290{
3291 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3292
3293 if (!crtc->config.ips_enabled)
3294 return;
3295
3296 /* We can only enable IPS after we enable a plane and wait for a vblank.
3297 * We guarantee that the plane is enabled by calling intel_enable_ips
3298 * only after intel_enable_plane. And intel_enable_plane already waits
3299 * for a vblank, so all we need to do here is to enable the IPS bit. */
3300 assert_plane_enabled(dev_priv, crtc->plane);
3301 I915_WRITE(IPS_CTL, IPS_ENABLE);
3302}
3303
3304static void hsw_disable_ips(struct intel_crtc *crtc)
3305{
3306 struct drm_device *dev = crtc->base.dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308
3309 if (!crtc->config.ips_enabled)
3310 return;
3311
3312 assert_plane_enabled(dev_priv, crtc->plane);
3313 I915_WRITE(IPS_CTL, 0);
3314
3315 /* We need to wait for a vblank before we can disable the plane. */
3316 intel_wait_for_vblank(dev, crtc->pipe);
3317}
3318
4f771f10
PZ		 3319static void haswell_crtc_enable(struct drm_crtc *crtc)
3320{
3321 struct drm_device *dev = crtc->dev;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
3323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3324 struct intel_encoder *encoder;
3325 int pipe = intel_crtc->pipe;
3326 int plane = intel_crtc->plane;
4f771f10
PZ		 3327
3328 WARN_ON(!crtc->enabled);
3329
3330 if (intel_crtc->active)
3331 return;
3332
3333 intel_crtc->active = true;
8664281b
PZ		 3334
3335 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3336 if (intel_crtc->config.has_pch_encoder)
3337 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3338
4f771f10
PZ		 3339 intel_update_watermarks(dev);
3340
5bfe2ac0 3341 if (intel_crtc->config.has_pch_encoder)
04945641 3342 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3343
3344 for_each_encoder_on_crtc(dev, crtc, encoder)
3345 if (encoder->pre_enable)
3346 encoder->pre_enable(encoder);
3347
1f544388 3348 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3349
1f544388 3350 /* Enable panel fitting for eDP */
b074cec8 3351 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3352
3353 /*
3354 * On ILK+ LUT must be loaded before the pipe is running but with
3355 * clocks enabled
3356 */
3357 intel_crtc_load_lut(crtc);
3358
1f544388 3359 intel_ddi_set_pipe_settings(crtc);
8228c251 3360 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3361
5bfe2ac0
DV		 3362 intel_enable_pipe(dev_priv, pipe,
3363 intel_crtc->config.has_pch_encoder);
4f771f10 3364 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3365 intel_enable_planes(crtc);
5c38d48c 3366 intel_crtc_update_cursor(crtc, true);
4f771f10 3367
42db64ef
PZ		 3368 hsw_enable_ips(intel_crtc);
3369
5bfe2ac0 3370 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3371 lpt_pch_enable(crtc);
4f771f10
PZ		 3372
3373 mutex_lock(&dev->struct_mutex);
3374 intel_update_fbc(dev);
3375 mutex_unlock(&dev->struct_mutex);
3376
4f771f10
PZ		 3377 for_each_encoder_on_crtc(dev, crtc, encoder)
3378 encoder->enable(encoder);
3379
4f771f10
PZ		 3380 /*
3381 * There seems to be a race in PCH platform hw (at least on some
3382 * outputs) where an enabled pipe still completes any pageflip right
3383 * away (as if the pipe is off) instead of waiting for vblank. As soon
3384 * as the first vblank happend, everything works as expected. Hence just
3385 * wait for one vblank before returning to avoid strange things
3386 * happening.
3387 */
3388 intel_wait_for_vblank(dev, intel_crtc->pipe);
3389}
3390
3f8dce3a
DV		 3391static void ironlake_pfit_disable(struct intel_crtc *crtc)
3392{
3393 struct drm_device *dev = crtc->base.dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 int pipe = crtc->pipe;
3396
3397 /* To avoid upsetting the power well on haswell only disable the pfit if
3398 * it's in use. The hw state code will make sure we get this right. */
3399 if (crtc->config.pch_pfit.size) {
3400 I915_WRITE(PF_CTL(pipe), 0);
3401 I915_WRITE(PF_WIN_POS(pipe), 0);
3402 I915_WRITE(PF_WIN_SZ(pipe), 0);
3403 }
3404}
3405
6be4a607
JB		 3406static void ironlake_crtc_disable(struct drm_crtc *crtc)
3407{
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3411 struct intel_encoder *encoder;
6be4a607
JB		 3412 int pipe = intel_crtc->pipe;
3413 int plane = intel_crtc->plane;
5eddb70b 3414 u32 reg, temp;
b52eb4dc 3415
ef9c3aee 3416
f7abfe8b
CW		 3417 if (!intel_crtc->active)
3418 return;
3419
ea9d758d
DV		 3420 for_each_encoder_on_crtc(dev, crtc, encoder)
3421 encoder->disable(encoder);
3422
e6c3a2a6 3423 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3424 drm_vblank_off(dev, pipe);
913d8d11 3425
973d04f9
CW		 3426 if (dev_priv->cfb_plane == plane)
3427 intel_disable_fbc(dev);
2c07245f 3428
0d5b8c61 3429 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3430 intel_disable_planes(crtc);
0d5b8c61
VS		 3431 intel_disable_plane(dev_priv, plane, pipe);
3432
8664281b 3433 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3434 intel_disable_pipe(dev_priv, pipe);
32f9d658 3435
3f8dce3a 3436 ironlake_pfit_disable(intel_crtc);
2c07245f 3437
bf49ec8c
DV		 3438 for_each_encoder_on_crtc(dev, crtc, encoder)
3439 if (encoder->post_disable)
3440 encoder->post_disable(encoder);
2c07245f 3441
0fc932b8 3442 ironlake_fdi_disable(crtc);
249c0e64 3443
b8a4f404 3444 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3445 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3446
6be4a607
JB		 3447 if (HAS_PCH_CPT(dev)) {
3448 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3449 reg = TRANS_DP_CTL(pipe);
3450 temp = I915_READ(reg);
3451 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3452 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3453 I915_WRITE(reg, temp);
6be4a607
JB		 3454
3455 /* disable DPLL_SEL */
3456 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3457 switch (pipe) {
3458 case 0:
d64311ab 3459 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3460 break;
3461 case 1:
6be4a607 3462 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3463 break;
3464 case 2:
4b645f14 3465 /* C shares PLL A or B */
d64311ab 3466 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3467 break;
3468 default:
3469 BUG(); /* wtf */
3470 }
6be4a607 3471 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3472 }
e3421a18 3473
6be4a607 3474 /* disable PCH DPLL */
ee7b9f93 3475 intel_disable_pch_pll(intel_crtc);
8db9d77b 3476
88cefb6c 3477 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3478
f7abfe8b 3479 intel_crtc->active = false;
6b383a7f 3480 intel_update_watermarks(dev);
d1ebd816
BW		 3481
3482 mutex_lock(&dev->struct_mutex);
6b383a7f 3483 intel_update_fbc(dev);
d1ebd816 3484 mutex_unlock(&dev->struct_mutex);
6be4a607 3485}
1b3c7a47 3486
4f771f10 3487static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3488{
4f771f10
PZ		 3489 struct drm_device *dev = crtc->dev;
3490 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3492 struct intel_encoder *encoder;
3493 int pipe = intel_crtc->pipe;
3494 int plane = intel_crtc->plane;
3b117c8f 3495 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3496
4f771f10
PZ		 3497 if (!intel_crtc->active)
3498 return;
3499
3500 for_each_encoder_on_crtc(dev, crtc, encoder)
3501 encoder->disable(encoder);
3502
3503 intel_crtc_wait_for_pending_flips(crtc);
3504 drm_vblank_off(dev, pipe);
4f771f10 3505
891348b2 3506 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3507 if (dev_priv->cfb_plane == plane)
3508 intel_disable_fbc(dev);
3509
42db64ef
PZ		 3510 hsw_disable_ips(intel_crtc);
3511
0d5b8c61 3512 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3513 intel_disable_planes(crtc);
891348b2
RV		 3514 intel_disable_plane(dev_priv, plane, pipe);
3515
8664281b
PZ		 3516 if (intel_crtc->config.has_pch_encoder)
3517 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3518 intel_disable_pipe(dev_priv, pipe);
3519
ad80a810 3520 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3521
3f8dce3a 3522 ironlake_pfit_disable(intel_crtc);
4f771f10 3523
1f544388 3524 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3525
3526 for_each_encoder_on_crtc(dev, crtc, encoder)
3527 if (encoder->post_disable)
3528 encoder->post_disable(encoder);
3529
88adfff1 3530 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3531 lpt_disable_pch_transcoder(dev_priv);
8664281b 3532 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3533 intel_ddi_fdi_disable(crtc);
83616634 3534 }
4f771f10
PZ		 3535
3536 intel_crtc->active = false;
3537 intel_update_watermarks(dev);
3538
3539 mutex_lock(&dev->struct_mutex);
3540 intel_update_fbc(dev);
3541 mutex_unlock(&dev->struct_mutex);
3542}
3543
ee7b9f93
JB		 3544static void ironlake_crtc_off(struct drm_crtc *crtc)
3545{
3546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3547 intel_put_pch_pll(intel_crtc);
3548}
3549
6441ab5f
PZ		 3550static void haswell_crtc_off(struct drm_crtc *crtc)
3551{
3552 intel_ddi_put_crtc_pll(crtc);
3553}
3554
02e792fb
DV		 3555static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3556{
02e792fb 3557 if (!enable && intel_crtc->overlay) {
23f09ce3 3558 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3559 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3560
23f09ce3 3561 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3562 dev_priv->mm.interruptible = false;
3563 (void) intel_overlay_switch_off(intel_crtc->overlay);
3564 dev_priv->mm.interruptible = true;
23f09ce3 3565 mutex_unlock(&dev->struct_mutex);
02e792fb 3566 }
02e792fb 3567
5dcdbcb0
CW		 3568 /* Let userspace switch the overlay on again. In most cases userspace
3569 * has to recompute where to put it anyway.
3570 */
02e792fb
DV		 3571}
3572
61bc95c1
EE		 3573/**
3574 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3575 * cursor plane briefly if not already running after enabling the display
3576 * plane.
3577 * This workaround avoids occasional blank screens when self refresh is
3578 * enabled.
3579 */
3580static void
3581g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3582{
3583 u32 cntl = I915_READ(CURCNTR(pipe));
3584
3585 if ((cntl & CURSOR_MODE) == 0) {
3586 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3587
3588 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3589 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3590 intel_wait_for_vblank(dev_priv->dev, pipe);
3591 I915_WRITE(CURCNTR(pipe), cntl);
3592 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3593 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3594 }
3595}
3596
2dd24552
JB		 3597static void i9xx_pfit_enable(struct intel_crtc *crtc)
3598{
3599 struct drm_device *dev = crtc->base.dev;
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601 struct intel_crtc_config *pipe_config = &crtc->config;
3602
328d8e82 3603 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3604 return;
3605
2dd24552 3606 /*
c0b03411
DV		 3607 * The panel fitter should only be adjusted whilst the pipe is disabled,
3608 * according to register description and PRM.
2dd24552 3609 */
c0b03411
DV		 3610 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3611 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3612
b074cec8
JB		 3613 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3614 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3615
3616 /* Border color in case we don't scale up to the full screen. Black by
3617 * default, change to something else for debugging. */
3618 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3619}
3620
89b667f8
JB		 3621static void valleyview_crtc_enable(struct drm_crtc *crtc)
3622{
3623 struct drm_device *dev = crtc->dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626 struct intel_encoder *encoder;
3627 int pipe = intel_crtc->pipe;
3628 int plane = intel_crtc->plane;
3629
3630 WARN_ON(!crtc->enabled);
3631
3632 if (intel_crtc->active)
3633 return;
3634
3635 intel_crtc->active = true;
3636 intel_update_watermarks(dev);
3637
3638 mutex_lock(&dev_priv->dpio_lock);
3639
3640 for_each_encoder_on_crtc(dev, crtc, encoder)
3641 if (encoder->pre_pll_enable)
3642 encoder->pre_pll_enable(encoder);
3643
3644 intel_enable_pll(dev_priv, pipe);
3645
3646 for_each_encoder_on_crtc(dev, crtc, encoder)
3647 if (encoder->pre_enable)
3648 encoder->pre_enable(encoder);
3649
3650 /* VLV wants encoder enabling _before_ the pipe is up. */
3651 for_each_encoder_on_crtc(dev, crtc, encoder)
3652 encoder->enable(encoder);
3653
2dd24552
JB		 3654 /* Enable panel fitting for eDP */
3655 i9xx_pfit_enable(intel_crtc);
3656
63cbb074
VS		 3657 intel_crtc_load_lut(crtc);
3658
89b667f8
JB		 3659 intel_enable_pipe(dev_priv, pipe, false);
3660 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3661 intel_enable_planes(crtc);
5c38d48c 3662 intel_crtc_update_cursor(crtc, true);
89b667f8 3663
f440eb13
VS		 3664 intel_update_fbc(dev);
3665
89b667f8
JB		 3666 mutex_unlock(&dev_priv->dpio_lock);
3667}
3668
0b8765c6 3669static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3670{
3671 struct drm_device *dev = crtc->dev;
79e53945
JB		 3672 struct drm_i915_private *dev_priv = dev->dev_private;
3673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3674 struct intel_encoder *encoder;
79e53945 3675 int pipe = intel_crtc->pipe;
80824003 3676 int plane = intel_crtc->plane;
79e53945 3677
08a48469
DV		 3678 WARN_ON(!crtc->enabled);
3679
f7abfe8b
CW		 3680 if (intel_crtc->active)
3681 return;
3682
3683 intel_crtc->active = true;
6b383a7f
CW		 3684 intel_update_watermarks(dev);
3685
63d7bbe9 3686 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3687
3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 if (encoder->pre_enable)
3690 encoder->pre_enable(encoder);
3691
2dd24552
JB		 3692 /* Enable panel fitting for LVDS */
3693 i9xx_pfit_enable(intel_crtc);
3694
63cbb074
VS		 3695 intel_crtc_load_lut(crtc);
3696
040484af 3697 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3698 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3699 intel_enable_planes(crtc);
5c38d48c 3700 intel_crtc_update_cursor(crtc, true);
61bc95c1
EE		 3701 if (IS_G4X(dev))
3702 g4x_fixup_plane(dev_priv, pipe);
79e53945 3703
0b8765c6
JB		 3704 /* Give the overlay scaler a chance to enable if it's on this pipe */
3705 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3706
f440eb13
VS		 3707 intel_update_fbc(dev);
3708
fa5c73b1
DV		 3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 encoder->enable(encoder);
0b8765c6 3711}
79e53945 3712
87476d63
DV		 3713static void i9xx_pfit_disable(struct intel_crtc *crtc)
3714{
3715 struct drm_device *dev = crtc->base.dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3717
328d8e82
DV		 3718 if (!crtc->config.gmch_pfit.control)
3719 return;
87476d63 3720
328d8e82 3721 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3722
328d8e82
DV		 3723 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3724 I915_READ(PFIT_CONTROL));
3725 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3726}
3727
0b8765c6
JB		 3728static void i9xx_crtc_disable(struct drm_crtc *crtc)
3729{
3730 struct drm_device *dev = crtc->dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3733 struct intel_encoder *encoder;
0b8765c6
JB		 3734 int pipe = intel_crtc->pipe;
3735 int plane = intel_crtc->plane;
ef9c3aee 3736
f7abfe8b
CW		 3737 if (!intel_crtc->active)
3738 return;
3739
ea9d758d
DV		 3740 for_each_encoder_on_crtc(dev, crtc, encoder)
3741 encoder->disable(encoder);
3742
0b8765c6 3743 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3744 intel_crtc_wait_for_pending_flips(crtc);
3745 drm_vblank_off(dev, pipe);
0b8765c6 3746
973d04f9
CW		 3747 if (dev_priv->cfb_plane == plane)
3748 intel_disable_fbc(dev);
79e53945 3749
0d5b8c61
VS		 3750 intel_crtc_dpms_overlay(intel_crtc, false);
3751 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3752 intel_disable_planes(crtc);
b24e7179 3753 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3754
b24e7179 3755 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3756
87476d63 3757 i9xx_pfit_disable(intel_crtc);
24a1f16d 3758
89b667f8
JB		 3759 for_each_encoder_on_crtc(dev, crtc, encoder)
3760 if (encoder->post_disable)
3761 encoder->post_disable(encoder);
3762
63d7bbe9 3763 intel_disable_pll(dev_priv, pipe);
0b8765c6 3764
f7abfe8b 3765 intel_crtc->active = false;
6b383a7f
CW		 3766 intel_update_fbc(dev);
3767 intel_update_watermarks(dev);
0b8765c6
JB		 3768}
3769
ee7b9f93
JB		 3770static void i9xx_crtc_off(struct drm_crtc *crtc)
3771{
3772}
3773
976f8a20
DV		 3774static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3775 bool enabled)
2c07245f
ZW		 3776{
3777 struct drm_device *dev = crtc->dev;
3778 struct drm_i915_master_private *master_priv;
3779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3780 int pipe = intel_crtc->pipe;
79e53945
JB		 3781
3782 if (!dev->primary->master)
3783 return;
3784
3785 master_priv = dev->primary->master->driver_priv;
3786 if (!master_priv->sarea_priv)
3787 return;
3788
79e53945
JB		 3789 switch (pipe) {
3790 case 0:
3791 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3792 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3793 break;
3794 case 1:
3795 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3796 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3797 break;
3798 default:
9db4a9c7 3799 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3800 break;
3801 }
79e53945
JB		 3802}
3803
976f8a20
DV		 3804/**
3805 * Sets the power management mode of the pipe and plane.
3806 */
3807void intel_crtc_update_dpms(struct drm_crtc *crtc)
3808{
3809 struct drm_device *dev = crtc->dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 struct intel_encoder *intel_encoder;
3812 bool enable = false;
3813
3814 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3815 enable |= intel_encoder->connectors_active;
3816
3817 if (enable)
3818 dev_priv->display.crtc_enable(crtc);
3819 else
3820 dev_priv->display.crtc_disable(crtc);
3821
3822 intel_crtc_update_sarea(crtc, enable);
3823}
3824
cdd59983
CW		 3825static void intel_crtc_disable(struct drm_crtc *crtc)
3826{
cdd59983 3827 struct drm_device *dev = crtc->dev;
976f8a20 3828 struct drm_connector *connector;
ee7b9f93 3829 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3831
976f8a20
DV		 3832 /* crtc should still be enabled when we disable it. */
3833 WARN_ON(!crtc->enabled);
3834
3835 dev_priv->display.crtc_disable(crtc);
c77bf565 3836 intel_crtc->eld_vld = false;
976f8a20 3837 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3838 dev_priv->display.off(crtc);
3839
931872fc
CW		 3840 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3841 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3842
3843 if (crtc->fb) {
3844 mutex_lock(&dev->struct_mutex);
1690e1eb 3845 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3846 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3847 crtc->fb = NULL;
3848 }
3849
3850 /* Update computed state. */
3851 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3852 if (!connector->encoder || !connector->encoder->crtc)
3853 continue;
3854
3855 if (connector->encoder->crtc != crtc)
3856 continue;
3857
3858 connector->dpms = DRM_MODE_DPMS_OFF;
3859 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3860 }
3861}
3862
a261b246 3863void intel_modeset_disable(struct drm_device *dev)
79e53945 3864{
a261b246
DV		 3865 struct drm_crtc *crtc;
3866
3867 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3868 if (crtc->enabled)
3869 intel_crtc_disable(crtc);
3870 }
79e53945
JB		 3871}
3872
ea5b213a 3873void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3874{
4ef69c7a 3875 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3876
ea5b213a
CW		 3877 drm_encoder_cleanup(encoder);
3878 kfree(intel_encoder);
7e7d76c3
JB		 3879}
3880
5ab432ef
DV		 3881/* Simple dpms helper for encodres with just one connector, no cloning and only
3882 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3883 * state of the entire output pipe. */
3884void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3885{
5ab432ef
DV		 3886 if (mode == DRM_MODE_DPMS_ON) {
3887 encoder->connectors_active = true;
3888
b2cabb0e 3889 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3890 } else {
3891 encoder->connectors_active = false;
3892
b2cabb0e 3893 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3894 }
79e53945
JB		 3895}
3896
0a91ca29
DV		 3897/* Cross check the actual hw state with our own modeset state tracking (and it's
3898 * internal consistency). */
b980514c 3899static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3900{
0a91ca29
DV		 3901 if (connector->get_hw_state(connector)) {
3902 struct intel_encoder *encoder = connector->encoder;
3903 struct drm_crtc *crtc;
3904 bool encoder_enabled;
3905 enum pipe pipe;
3906
3907 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3908 connector->base.base.id,
3909 drm_get_connector_name(&connector->base));
3910
3911 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3912 "wrong connector dpms state\n");
3913 WARN(connector->base.encoder != &encoder->base,
3914 "active connector not linked to encoder\n");
3915 WARN(!encoder->connectors_active,
3916 "encoder->connectors_active not set\n");
3917
3918 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3919 WARN(!encoder_enabled, "encoder not enabled\n");
3920 if (WARN_ON(!encoder->base.crtc))
3921 return;
3922
3923 crtc = encoder->base.crtc;
3924
3925 WARN(!crtc->enabled, "crtc not enabled\n");
3926 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3927 WARN(pipe != to_intel_crtc(crtc)->pipe,
3928 "encoder active on the wrong pipe\n");
3929 }
79e53945
JB		 3930}
3931
5ab432ef
DV		 3932/* Even simpler default implementation, if there's really no special case to
3933 * consider. */
3934void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3935{
5ab432ef 3936 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3937
5ab432ef
DV		 3938 /* All the simple cases only support two dpms states. */
3939 if (mode != DRM_MODE_DPMS_ON)
3940 mode = DRM_MODE_DPMS_OFF;
d4270e57 3941
5ab432ef
DV		 3942 if (mode == connector->dpms)
3943 return;
3944
3945 connector->dpms = mode;
3946
3947 /* Only need to change hw state when actually enabled */
3948 if (encoder->base.crtc)
3949 intel_encoder_dpms(encoder, mode);
3950 else
8af6cf88 3951 WARN_ON(encoder->connectors_active != false);
0a91ca29 3952
b980514c 3953 intel_modeset_check_state(connector->dev);
79e53945
JB		 3954}
3955
f0947c37
DV		 3956/* Simple connector->get_hw_state implementation for encoders that support only
3957 * one connector and no cloning and hence the encoder state determines the state
3958 * of the connector. */
3959bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3960{
24929352 3961 enum pipe pipe = 0;
f0947c37 3962 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3963
f0947c37 3964 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3965}
3966
1857e1da
DV		 3967static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3968 struct intel_crtc_config *pipe_config)
3969{
3970 struct drm_i915_private *dev_priv = dev->dev_private;
3971 struct intel_crtc *pipe_B_crtc =
3972 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3973
3974 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3975 pipe_name(pipe), pipe_config->fdi_lanes);
3976 if (pipe_config->fdi_lanes > 4) {
3977 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3978 pipe_name(pipe), pipe_config->fdi_lanes);
3979 return false;
3980 }
3981
3982 if (IS_HASWELL(dev)) {
3983 if (pipe_config->fdi_lanes > 2) {
3984 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3985 pipe_config->fdi_lanes);
3986 return false;
3987 } else {
3988 return true;
3989 }
3990 }
3991
3992 if (INTEL_INFO(dev)->num_pipes == 2)
3993 return true;
3994
3995 /* Ivybridge 3 pipe is really complicated */
3996 switch (pipe) {
3997 case PIPE_A:
3998 return true;
3999 case PIPE_B:
4000 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4001 pipe_config->fdi_lanes > 2) {
4002 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4003 pipe_name(pipe), pipe_config->fdi_lanes);
4004 return false;
4005 }
4006 return true;
4007 case PIPE_C:
1e833f40 4008 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4009 pipe_B_crtc->config.fdi_lanes <= 2) {
4010 if (pipe_config->fdi_lanes > 2) {
4011 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4012 pipe_name(pipe), pipe_config->fdi_lanes);
4013 return false;
4014 }
4015 } else {
4016 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4017 return false;
4018 }
4019 return true;
4020 default:
4021 BUG();
4022 }
4023}
4024
e29c22c0
DV		 4025#define RETRY 1
4026static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4027 struct intel_crtc_config *pipe_config)
877d48d5 4028{
1857e1da 4029 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4030 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4031 int lane, link_bw, fdi_dotclock;
e29c22c0 4032 bool setup_ok, needs_recompute = false;
877d48d5 4033
e29c22c0 4034retry:
877d48d5
DV		 4035 /* FDI is a binary signal running at ~2.7GHz, encoding
4036 * each output octet as 10 bits. The actual frequency
4037 * is stored as a divider into a 100MHz clock, and the
4038 * mode pixel clock is stored in units of 1KHz.
4039 * Hence the bw of each lane in terms of the mode signal
4040 * is:
4041 */
4042 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4043
ff9a6750 4044 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4045 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4046
4047 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4048 pipe_config->pipe_bpp);
4049
4050 pipe_config->fdi_lanes = lane;
4051
2bd89a07 4052 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4053 link_bw, &pipe_config->fdi_m_n);
1857e1da 4054
e29c22c0
DV		 4055 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4056 intel_crtc->pipe, pipe_config);
4057 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4058 pipe_config->pipe_bpp -= 2*3;
4059 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4060 pipe_config->pipe_bpp);
4061 needs_recompute = true;
4062 pipe_config->bw_constrained = true;
4063
4064 goto retry;
4065 }
4066
4067 if (needs_recompute)
4068 return RETRY;
4069
4070 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4071}
4072
42db64ef
PZ		 4073static void hsw_compute_ips_config(struct intel_crtc *crtc,
4074 struct intel_crtc_config *pipe_config)
4075{
3c4ca58c
PZ		 4076 pipe_config->ips_enabled = i915_enable_ips &&
4077 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4078 pipe_config->pipe_bpp == 24;
4079}
4080
e29c22c0
DV		 4081static int intel_crtc_compute_config(struct drm_crtc *crtc,
4082 struct intel_crtc_config *pipe_config)
79e53945 4083{
2c07245f 4084 struct drm_device *dev = crtc->dev;
b8cecdf5 4085 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4087
bad720ff 4088 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4089 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4090 if (pipe_config->requested_mode.clock * 3
4091 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4092 return -EINVAL;
2c07245f 4093 }
89749350 4094
f9bef081
DV		 4095 /* All interlaced capable intel hw wants timings in frames. Note though
4096 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4097 * timings, so we need to be careful not to clobber these.*/
7ae89233 4098 if (!pipe_config->timings_set)
f9bef081 4099 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4100
8693a824
DL		 4101 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4102 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4103 */
4104 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4105 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4106 return -EINVAL;
44f46b42 4107
bd080ee5 4108 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4109 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4110 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4111 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4112 * for lvds. */
4113 pipe_config->pipe_bpp = 8*3;
4114 }
4115
42db64ef
PZ		 4116 if (IS_HASWELL(dev))
4117 hsw_compute_ips_config(intel_crtc, pipe_config);
4118
877d48d5 4119 if (pipe_config->has_pch_encoder)
42db64ef 4120 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4121
e29c22c0 4122 return 0;
79e53945
JB		 4123}
4124
25eb05fc
JB		 4125static int valleyview_get_display_clock_speed(struct drm_device *dev)
4126{
4127 return 400000; /* FIXME */
4128}
4129
e70236a8
JB		 4130static int i945_get_display_clock_speed(struct drm_device *dev)
4131{
4132 return 400000;
4133}
79e53945 4134
e70236a8 4135static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4136{
e70236a8
JB		 4137 return 333000;
4138}
79e53945 4139
e70236a8
JB		 4140static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4141{
4142 return 200000;
4143}
79e53945 4144
e70236a8
JB		 4145static int i915gm_get_display_clock_speed(struct drm_device *dev)
4146{
4147 u16 gcfgc = 0;
79e53945 4148
e70236a8
JB		 4149 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4150
4151 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4152 return 133000;
4153 else {
4154 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4155 case GC_DISPLAY_CLOCK_333_MHZ:
4156 return 333000;
4157 default:
4158 case GC_DISPLAY_CLOCK_190_200_MHZ:
4159 return 190000;
79e53945 4160 }
e70236a8
JB		 4161 }
4162}
4163
4164static int i865_get_display_clock_speed(struct drm_device *dev)
4165{
4166 return 266000;
4167}
4168
4169static int i855_get_display_clock_speed(struct drm_device *dev)
4170{
4171 u16 hpllcc = 0;
4172 /* Assume that the hardware is in the high speed state. This
4173 * should be the default.
4174 */
4175 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4176 case GC_CLOCK_133_200:
4177 case GC_CLOCK_100_200:
4178 return 200000;
4179 case GC_CLOCK_166_250:
4180 return 250000;
4181 case GC_CLOCK_100_133:
79e53945 4182 return 133000;
e70236a8 4183 }
79e53945 4184
e70236a8
JB		 4185 /* Shouldn't happen */
4186 return 0;
4187}
79e53945 4188
e70236a8
JB		 4189static int i830_get_display_clock_speed(struct drm_device *dev)
4190{
4191 return 133000;
79e53945
JB		 4192}
4193
2c07245f 4194static void
a65851af 4195intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4196{
a65851af
VS		 4197 while (*num > DATA_LINK_M_N_MASK ||
4198 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4199 *num >>= 1;
4200 *den >>= 1;
4201 }
4202}
4203
a65851af
VS		 4204static void compute_m_n(unsigned int m, unsigned int n,
4205 uint32_t *ret_m, uint32_t *ret_n)
4206{
4207 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4208 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4209 intel_reduce_m_n_ratio(ret_m, ret_n);
4210}
4211
e69d0bc1
DV		 4212void
4213intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4214 int pixel_clock, int link_clock,
4215 struct intel_link_m_n *m_n)
2c07245f 4216{
e69d0bc1 4217 m_n->tu = 64;
a65851af
VS		 4218
4219 compute_m_n(bits_per_pixel * pixel_clock,
4220 link_clock * nlanes * 8,
4221 &m_n->gmch_m, &m_n->gmch_n);
4222
4223 compute_m_n(pixel_clock, link_clock,
4224 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4225}
4226
a7615030
CW		 4227static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4228{
72bbe58c
KP		 4229 if (i915_panel_use_ssc >= 0)
4230 return i915_panel_use_ssc != 0;
41aa3448 4231 return dev_priv->vbt.lvds_use_ssc
435793df 4232 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4233}
4234
a0c4da24
JB		 4235static int vlv_get_refclk(struct drm_crtc *crtc)
4236{
4237 struct drm_device *dev = crtc->dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 int refclk = 27000; /* for DP & HDMI */
4240
4241 return 100000; /* only one validated so far */
4242
4243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4244 refclk = 96000;
4245 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4246 if (intel_panel_use_ssc(dev_priv))
4247 refclk = 100000;
4248 else
4249 refclk = 96000;
4250 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4251 refclk = 100000;
4252 }
4253
4254 return refclk;
4255}
4256
c65d77d8
JB		 4257static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4258{
4259 struct drm_device *dev = crtc->dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 int refclk;
4262
a0c4da24
JB		 4263 if (IS_VALLEYVIEW(dev)) {
4264 refclk = vlv_get_refclk(crtc);
4265 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4266 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4267 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4268 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4269 refclk / 1000);
4270 } else if (!IS_GEN2(dev)) {
4271 refclk = 96000;
4272 } else {
4273 refclk = 48000;
4274 }
4275
4276 return refclk;
4277}
4278
7429e9d4
DV		 4279static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4280{
4281 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4282}
4283
4284static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4285{
4286 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4287}
4288
f47709a9 4289static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4290 intel_clock_t *reduced_clock)
4291{
f47709a9 4292 struct drm_device *dev = crtc->base.dev;
a7516a05 4293 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4294 int pipe = crtc->pipe;
a7516a05
JB		 4295 u32 fp, fp2 = 0;
4296
4297 if (IS_PINEVIEW(dev)) {
7429e9d4 4298 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4299 if (reduced_clock)
7429e9d4 4300 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4301 } else {
7429e9d4 4302 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4303 if (reduced_clock)
7429e9d4 4304 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4305 }
4306
4307 I915_WRITE(FP0(pipe), fp);
4308
f47709a9
DV		 4309 crtc->lowfreq_avail = false;
4310 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4311 reduced_clock && i915_powersave) {
4312 I915_WRITE(FP1(pipe), fp2);
f47709a9 4313 crtc->lowfreq_avail = true;
a7516a05
JB		 4314 } else {
4315 I915_WRITE(FP1(pipe), fp);
4316 }
4317}
4318
89b667f8
JB		 4319static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4320{
4321 u32 reg_val;
4322
4323 /*
4324 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4325 * and set it to a reasonable value instead.
4326 */
ae99258f 4327 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4328 reg_val &= 0xffffff00;
4329 reg_val |= 0x00000030;
ae99258f 4330 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4331
ae99258f 4332 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4333 reg_val &= 0x8cffffff;
4334 reg_val = 0x8c000000;
ae99258f 4335 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4336
ae99258f 4337 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4338 reg_val &= 0xffffff00;
ae99258f 4339 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4340
ae99258f 4341 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4342 reg_val &= 0x00ffffff;
4343 reg_val |= 0xb0000000;
ae99258f 4344 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4345}
4346
b551842d
DV		 4347static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4348 struct intel_link_m_n *m_n)
4349{
4350 struct drm_device *dev = crtc->base.dev;
4351 struct drm_i915_private *dev_priv = dev->dev_private;
4352 int pipe = crtc->pipe;
4353
e3b95f1e
DV		 4354 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4355 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4356 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4357 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4358}
4359
4360static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4361 struct intel_link_m_n *m_n)
4362{
4363 struct drm_device *dev = crtc->base.dev;
4364 struct drm_i915_private *dev_priv = dev->dev_private;
4365 int pipe = crtc->pipe;
4366 enum transcoder transcoder = crtc->config.cpu_transcoder;
4367
4368 if (INTEL_INFO(dev)->gen >= 5) {
4369 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4370 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4371 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4372 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4373 } else {
e3b95f1e
DV		 4374 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4375 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4376 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4377 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4378 }
4379}
4380
03afc4a2
DV		 4381static void intel_dp_set_m_n(struct intel_crtc *crtc)
4382{
4383 if (crtc->config.has_pch_encoder)
4384 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4385 else
4386 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4387}
4388
f47709a9 4389static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4390{
f47709a9 4391 struct drm_device *dev = crtc->base.dev;
a0c4da24 4392 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4393 struct intel_encoder *encoder;
f47709a9 4394 int pipe = crtc->pipe;
89b667f8 4395 u32 dpll, mdiv;
a0c4da24 4396 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4397 bool is_hdmi;
198a037f 4398 u32 coreclk, reg_val, dpll_md;
a0c4da24 4399
09153000
DV		 4400 mutex_lock(&dev_priv->dpio_lock);
4401
89b667f8 4402 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4403
f47709a9
DV		 4404 bestn = crtc->config.dpll.n;
4405 bestm1 = crtc->config.dpll.m1;
4406 bestm2 = crtc->config.dpll.m2;
4407 bestp1 = crtc->config.dpll.p1;
4408 bestp2 = crtc->config.dpll.p2;
a0c4da24 4409
89b667f8
JB		 4410 /* See eDP HDMI DPIO driver vbios notes doc */
4411
4412 /* PLL B needs special handling */
4413 if (pipe)
4414 vlv_pllb_recal_opamp(dev_priv);
4415
4416 /* Set up Tx target for periodic Rcomp update */
ae99258f 4417 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4418
4419 /* Disable target IRef on PLL */
ae99258f 4420 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4421 reg_val &= 0x00ffffff;
ae99258f 4422 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4423
4424 /* Disable fast lock */
ae99258f 4425 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4426
4427 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4428 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4429 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4430 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4431 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4432
4433 /*
4434 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4435 * but we don't support that).
4436 * Note: don't use the DAC post divider as it seems unstable.
4437 */
4438 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4439 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4440
89b667f8 4441 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4442 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4443
89b667f8 4444 /* Set HBR and RBR LPF coefficients */
ff9a6750 4445 if (crtc->config.port_clock == 162000 ||
89b667f8 4446 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4447 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4448 0x005f0021);
4449 else
ae99258f 4450 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4451 0x00d0000f);
4452
4453 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4454 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4455 /* Use SSC source */
4456 if (!pipe)
ae99258f 4457 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4458 0x0df40000);
4459 else
ae99258f 4460 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4461 0x0df70000);
4462 } else { /* HDMI or VGA */
4463 /* Use bend source */
4464 if (!pipe)
ae99258f 4465 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4466 0x0df70000);
4467 else
ae99258f 4468 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4469 0x0df40000);
4470 }
a0c4da24 4471
ae99258f 4472 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4473 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4474 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4475 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4476 coreclk |= 0x01000000;
ae99258f 4477 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4478
ae99258f 4479 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4480
89b667f8
JB		 4481 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4482 if (encoder->pre_pll_enable)
4483 encoder->pre_pll_enable(encoder);
2a8f64ca 4484
89b667f8
JB		 4485 /* Enable DPIO clock input */
4486 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4487 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4488 if (pipe)
4489 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4490
89b667f8 4491 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4492 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4493 POSTING_READ(DPLL(pipe));
4494 udelay(150);
a0c4da24 4495
89b667f8
JB		 4496 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4497 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4498
ef1b460d
DV		 4499 dpll_md = (crtc->config.pixel_multiplier - 1)
4500 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4501 I915_WRITE(DPLL_MD(pipe), dpll_md);
4502 POSTING_READ(DPLL_MD(pipe));
f47709a9 4503
89b667f8
JB		 4504 if (crtc->config.has_dp_encoder)
4505 intel_dp_set_m_n(crtc);
09153000
DV		 4506
4507 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4508}
4509
f47709a9
DV		 4510static void i9xx_update_pll(struct intel_crtc *crtc,
4511 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4512 int num_connectors)
4513{
f47709a9 4514 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4515 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4516 struct intel_encoder *encoder;
f47709a9 4517 int pipe = crtc->pipe;
eb1cbe48
DV		 4518 u32 dpll;
4519 bool is_sdvo;
f47709a9 4520 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4521
f47709a9 4522 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4523
f47709a9
DV		 4524 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4525 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4526
4527 dpll = DPLL_VGA_MODE_DIS;
4528
f47709a9 4529 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4530 dpll |= DPLLB_MODE_LVDS;
4531 else
4532 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4533
ef1b460d 4534 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4535 dpll |= (crtc->config.pixel_multiplier - 1)
4536 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4537 }
198a037f
DV		 4538
4539 if (is_sdvo)
4540 dpll |= DPLL_DVO_HIGH_SPEED;
4541
f47709a9 4542 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4543 dpll |= DPLL_DVO_HIGH_SPEED;
4544
4545 /* compute bitmask from p1 value */
4546 if (IS_PINEVIEW(dev))
4547 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4548 else {
4549 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4550 if (IS_G4X(dev) && reduced_clock)
4551 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4552 }
4553 switch (clock->p2) {
4554 case 5:
4555 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4556 break;
4557 case 7:
4558 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4559 break;
4560 case 10:
4561 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4562 break;
4563 case 14:
4564 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4565 break;
4566 }
4567 if (INTEL_INFO(dev)->gen >= 4)
4568 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4569
09ede541 4570 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4571 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4572 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4573 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4574 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4575 else
4576 dpll |= PLL_REF_INPUT_DREFCLK;
4577
4578 dpll |= DPLL_VCO_ENABLE;
4579 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4580 POSTING_READ(DPLL(pipe));
4581 udelay(150);
4582
f47709a9 4583 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4584 if (encoder->pre_pll_enable)
4585 encoder->pre_pll_enable(encoder);
eb1cbe48 4586
f47709a9
DV		 4587 if (crtc->config.has_dp_encoder)
4588 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4589
4590 I915_WRITE(DPLL(pipe), dpll);
4591
4592 /* Wait for the clocks to stabilize. */
4593 POSTING_READ(DPLL(pipe));
4594 udelay(150);
4595
4596 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4597 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4598 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4599 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4600 } else {
4601 /* The pixel multiplier can only be updated once the
4602 * DPLL is enabled and the clocks are stable.
4603 *
4604 * So write it again.
4605 */
4606 I915_WRITE(DPLL(pipe), dpll);
4607 }
4608}
4609
f47709a9 4610static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4611 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4612 int num_connectors)
4613{
f47709a9 4614 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4615 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4616 struct intel_encoder *encoder;
f47709a9 4617 int pipe = crtc->pipe;
eb1cbe48 4618 u32 dpll;
f47709a9 4619 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4620
f47709a9 4621 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4622
eb1cbe48
DV		 4623 dpll = DPLL_VGA_MODE_DIS;
4624
f47709a9 4625 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4626 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4627 } else {
4628 if (clock->p1 == 2)
4629 dpll |= PLL_P1_DIVIDE_BY_TWO;
4630 else
4631 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4632 if (clock->p2 == 4)
4633 dpll |= PLL_P2_DIVIDE_BY_4;
4634 }
4635
f47709a9 4636 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4637 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4638 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4639 else
4640 dpll |= PLL_REF_INPUT_DREFCLK;
4641
4642 dpll |= DPLL_VCO_ENABLE;
4643 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4644 POSTING_READ(DPLL(pipe));
4645 udelay(150);
4646
f47709a9 4647 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4648 if (encoder->pre_pll_enable)
4649 encoder->pre_pll_enable(encoder);
eb1cbe48 4650
5b5896e4
DV		 4651 I915_WRITE(DPLL(pipe), dpll);
4652
4653 /* Wait for the clocks to stabilize. */
4654 POSTING_READ(DPLL(pipe));
4655 udelay(150);
4656
eb1cbe48
DV		 4657 /* The pixel multiplier can only be updated once the
4658 * DPLL is enabled and the clocks are stable.
4659 *
4660 * So write it again.
4661 */
4662 I915_WRITE(DPLL(pipe), dpll);
4663}
4664
8a654f3b 4665static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4666{
4667 struct drm_device *dev = intel_crtc->base.dev;
4668 struct drm_i915_private *dev_priv = dev->dev_private;
4669 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4670 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4671 struct drm_display_mode *adjusted_mode =
4672 &intel_crtc->config.adjusted_mode;
4673 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4674 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4675
4676 /* We need to be careful not to changed the adjusted mode, for otherwise
4677 * the hw state checker will get angry at the mismatch. */
4678 crtc_vtotal = adjusted_mode->crtc_vtotal;
4679 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4680
4681 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4682 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4683 crtc_vtotal -= 1;
4684 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4685 vsyncshift = adjusted_mode->crtc_hsync_start
4686 - adjusted_mode->crtc_htotal / 2;
4687 } else {
4688 vsyncshift = 0;
4689 }
4690
4691 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4692 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4693
fe2b8f9d 4694 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4695 (adjusted_mode->crtc_hdisplay - 1) |
4696 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4697 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4698 (adjusted_mode->crtc_hblank_start - 1) |
4699 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4700 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4701 (adjusted_mode->crtc_hsync_start - 1) |
4702 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4703
fe2b8f9d 4704 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4705 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4706 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4707 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4708 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4709 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4710 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4711 (adjusted_mode->crtc_vsync_start - 1) |
4712 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4713
b5e508d4
PZ		 4714 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4715 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4716 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4717 * bits. */
4718 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4719 (pipe == PIPE_B || pipe == PIPE_C))
4720 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4721
b0e77b9c
PZ		 4722 /* pipesrc controls the size that is scaled from, which should
4723 * always be the user's requested size.
4724 */
4725 I915_WRITE(PIPESRC(pipe),
4726 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4727}
4728
1bd1bd80
DV		 4729static void intel_get_pipe_timings(struct intel_crtc *crtc,
4730 struct intel_crtc_config *pipe_config)
4731{
4732 struct drm_device *dev = crtc->base.dev;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4735 uint32_t tmp;
4736
4737 tmp = I915_READ(HTOTAL(cpu_transcoder));
4738 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4739 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4740 tmp = I915_READ(HBLANK(cpu_transcoder));
4741 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4742 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4743 tmp = I915_READ(HSYNC(cpu_transcoder));
4744 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4745 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4746
4747 tmp = I915_READ(VTOTAL(cpu_transcoder));
4748 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4749 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4750 tmp = I915_READ(VBLANK(cpu_transcoder));
4751 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4752 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4753 tmp = I915_READ(VSYNC(cpu_transcoder));
4754 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4755 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4756
4757 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4758 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4759 pipe_config->adjusted_mode.crtc_vtotal += 1;
4760 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4761 }
4762
4763 tmp = I915_READ(PIPESRC(crtc->pipe));
4764 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4765 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4766}
4767
84b046f3
DV		 4768static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4769{
4770 struct drm_device *dev = intel_crtc->base.dev;
4771 struct drm_i915_private *dev_priv = dev->dev_private;
4772 uint32_t pipeconf;
4773
4774 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4775
4776 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4777 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4778 * core speed.
4779 *
4780 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4781 * pipe == 0 check?
4782 */
4783 if (intel_crtc->config.requested_mode.clock >
4784 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4785 pipeconf |= PIPECONF_DOUBLE_WIDE;
4786 else
4787 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4788 }
4789
ff9ce46e
DV		 4790 /* only g4x and later have fancy bpc/dither controls */
4791 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4792 pipeconf &= ~(PIPECONF_BPC_MASK |
4793 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4794
4795 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4796 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4797 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4798 PIPECONF_DITHER_TYPE_SP;
84b046f3 4799
ff9ce46e
DV		 4800 switch (intel_crtc->config.pipe_bpp) {
4801 case 18:
4802 pipeconf |= PIPECONF_6BPC;
4803 break;
4804 case 24:
4805 pipeconf |= PIPECONF_8BPC;
4806 break;
4807 case 30:
4808 pipeconf |= PIPECONF_10BPC;
4809 break;
4810 default:
4811 /* Case prevented by intel_choose_pipe_bpp_dither. */
4812 BUG();
84b046f3
DV		 4813 }
4814 }
4815
4816 if (HAS_PIPE_CXSR(dev)) {
4817 if (intel_crtc->lowfreq_avail) {
4818 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4819 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4820 } else {
4821 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4822 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4823 }
4824 }
4825
4826 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4827 if (!IS_GEN2(dev) &&
4828 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4829 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4830 else
4831 pipeconf |= PIPECONF_PROGRESSIVE;
4832
9c8e09b7
VS		 4833 if (IS_VALLEYVIEW(dev)) {
4834 if (intel_crtc->config.limited_color_range)
4835 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4836 else
4837 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4838 }
4839
84b046f3
DV		 4840 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4841 POSTING_READ(PIPECONF(intel_crtc->pipe));
4842}
4843
f564048e 4844static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4845 int x, int y,
94352cf9 4846 struct drm_framebuffer *fb)
79e53945
JB		 4847{
4848 struct drm_device *dev = crtc->dev;
4849 struct drm_i915_private *dev_priv = dev->dev_private;
4850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4851 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4852 int pipe = intel_crtc->pipe;
80824003 4853 int plane = intel_crtc->plane;
c751ce4f 4854 int refclk, num_connectors = 0;
652c393a 4855 intel_clock_t clock, reduced_clock;
84b046f3 4856 u32 dspcntr;
a16af721
DV		 4857 bool ok, has_reduced_clock = false;
4858 bool is_lvds = false;
5eddb70b 4859 struct intel_encoder *encoder;
d4906093 4860 const intel_limit_t *limit;
5c3b82e2 4861 int ret;
79e53945 4862
6c2b7c12 4863 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4864 switch (encoder->type) {
79e53945
JB		 4865 case INTEL_OUTPUT_LVDS:
4866 is_lvds = true;
4867 break;
79e53945 4868 }
43565a06 4869
c751ce4f 4870 num_connectors++;
79e53945
JB		 4871 }
4872
c65d77d8 4873 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4874
d4906093
ML		 4875 /*
4876 * Returns a set of divisors for the desired target clock with the given
4877 * refclk, or FALSE. The returned values represent the clock equation:
4878 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4879 */
1b894b59 4880 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4881 ok = dev_priv->display.find_dpll(limit, crtc,
4882 intel_crtc->config.port_clock,
ee9300bb
DV		 4883 refclk, NULL, &clock);
4884 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4885 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4886 return -EINVAL;
79e53945
JB		 4887 }
4888
cda4b7d3 4889 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4890 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4891
ddc9003c 4892 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4893 /*
4894 * Ensure we match the reduced clock's P to the target clock.
4895 * If the clocks don't match, we can't switch the display clock
4896 * by using the FP0/FP1. In such case we will disable the LVDS
4897 * downclock feature.
4898 */
ee9300bb
DV		 4899 has_reduced_clock =
4900 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4901 dev_priv->lvds_downclock,
ee9300bb 4902 refclk, &clock,
5eddb70b 4903 &reduced_clock);
7026d4ac 4904 }
f47709a9
DV		 4905 /* Compat-code for transition, will disappear. */
4906 if (!intel_crtc->config.clock_set) {
4907 intel_crtc->config.dpll.n = clock.n;
4908 intel_crtc->config.dpll.m1 = clock.m1;
4909 intel_crtc->config.dpll.m2 = clock.m2;
4910 intel_crtc->config.dpll.p1 = clock.p1;
4911 intel_crtc->config.dpll.p2 = clock.p2;
4912 }
7026d4ac 4913
eb1cbe48 4914 if (IS_GEN2(dev))
8a654f3b 4915 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4916 has_reduced_clock ? &reduced_clock : NULL,
4917 num_connectors);
a0c4da24 4918 else if (IS_VALLEYVIEW(dev))
f47709a9 4919 vlv_update_pll(intel_crtc);
79e53945 4920 else
f47709a9 4921 i9xx_update_pll(intel_crtc,
eb1cbe48 4922 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4923 num_connectors);
79e53945 4924
79e53945
JB		 4925 /* Set up the display plane register */
4926 dspcntr = DISPPLANE_GAMMA_ENABLE;
4927
da6ecc5d
JB		 4928 if (!IS_VALLEYVIEW(dev)) {
4929 if (pipe == 0)
4930 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4931 else
4932 dspcntr |= DISPPLANE_SEL_PIPE_B;
4933 }
79e53945 4934
8a654f3b 4935 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4936
4937 /* pipesrc and dspsize control the size that is scaled from,
4938 * which should always be the user's requested size.
79e53945 4939 */
929c77fb
EA		 4940 I915_WRITE(DSPSIZE(plane),
4941 ((mode->vdisplay - 1) << 16) |
4942 (mode->hdisplay - 1));
4943 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4944
84b046f3
DV		 4945 i9xx_set_pipeconf(intel_crtc);
4946
f564048e
EA		 4947 I915_WRITE(DSPCNTR(plane), dspcntr);
4948 POSTING_READ(DSPCNTR(plane));
4949
94352cf9 4950 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4951
4952 intel_update_watermarks(dev);
4953
f564048e
EA		 4954 return ret;
4955}
4956
2fa2fe9a
DV		 4957static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4958 struct intel_crtc_config *pipe_config)
4959{
4960 struct drm_device *dev = crtc->base.dev;
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 uint32_t tmp;
4963
4964 tmp = I915_READ(PFIT_CONTROL);
4965
4966 if (INTEL_INFO(dev)->gen < 4) {
4967 if (crtc->pipe != PIPE_B)
4968 return;
4969
4970 /* gen2/3 store dither state in pfit control, needs to match */
4971 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4972 } else {
4973 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4974 return;
4975 }
4976
4977 if (!(tmp & PFIT_ENABLE))
4978 return;
4979
4980 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4981 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4982 if (INTEL_INFO(dev)->gen < 5)
4983 pipe_config->gmch_pfit.lvds_border_bits =
4984 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4985}
4986
0e8ffe1b
DV		 4987static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4988 struct intel_crtc_config *pipe_config)
4989{
4990 struct drm_device *dev = crtc->base.dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 uint32_t tmp;
4993
eccb140b
DV		 4994 pipe_config->cpu_transcoder = crtc->pipe;
4995
0e8ffe1b
DV		 4996 tmp = I915_READ(PIPECONF(crtc->pipe));
4997 if (!(tmp & PIPECONF_ENABLE))
4998 return false;
4999
1bd1bd80
DV		 5000 intel_get_pipe_timings(crtc, pipe_config);
5001
2fa2fe9a
DV		 5002 i9xx_get_pfit_config(crtc, pipe_config);
5003
6c49f241
DV		 5004 if (INTEL_INFO(dev)->gen >= 4) {
5005 tmp = I915_READ(DPLL_MD(crtc->pipe));
5006 pipe_config->pixel_multiplier =
5007 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5008 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5009 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5010 tmp = I915_READ(DPLL(crtc->pipe));
5011 pipe_config->pixel_multiplier =
5012 ((tmp & SDVO_MULTIPLIER_MASK)
5013 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5014 } else {
5015 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5016 * port and will be fixed up in the encoder->get_config
5017 * function. */
5018 pipe_config->pixel_multiplier = 1;
5019 }
5020
0e8ffe1b
DV		 5021 return true;
5022}
5023
dde86e2d 5024static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5025{
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5028 struct intel_encoder *encoder;
74cfd7ac 5029 u32 val, final;
13d83a67 5030 bool has_lvds = false;
199e5d79 5031 bool has_cpu_edp = false;
199e5d79 5032 bool has_panel = false;
99eb6a01
KP		 5033 bool has_ck505 = false;
5034 bool can_ssc = false;
13d83a67
JB		 5035
5036 /* We need to take the global config into account */
199e5d79
KP		 5037 list_for_each_entry(encoder, &mode_config->encoder_list,
5038 base.head) {
5039 switch (encoder->type) {
5040 case INTEL_OUTPUT_LVDS:
5041 has_panel = true;
5042 has_lvds = true;
5043 break;
5044 case INTEL_OUTPUT_EDP:
5045 has_panel = true;
2de6905f 5046 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5047 has_cpu_edp = true;
5048 break;
13d83a67
JB		 5049 }
5050 }
5051
99eb6a01 5052 if (HAS_PCH_IBX(dev)) {
41aa3448 5053 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5054 can_ssc = has_ck505;
5055 } else {
5056 has_ck505 = false;
5057 can_ssc = true;
5058 }
5059
2de6905f
ID		 5060 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5061 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5062
5063 /* Ironlake: try to setup display ref clock before DPLL
5064 * enabling. This is only under driver's control after
5065 * PCH B stepping, previous chipset stepping should be
5066 * ignoring this setting.
5067 */
74cfd7ac
CW		 5068 val = I915_READ(PCH_DREF_CONTROL);
5069
5070 /* As we must carefully and slowly disable/enable each source in turn,
5071 * compute the final state we want first and check if we need to
5072 * make any changes at all.
5073 */
5074 final = val;
5075 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5076 if (has_ck505)
5077 final |= DREF_NONSPREAD_CK505_ENABLE;
5078 else
5079 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5080
5081 final &= ~DREF_SSC_SOURCE_MASK;
5082 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5083 final &= ~DREF_SSC1_ENABLE;
5084
5085 if (has_panel) {
5086 final |= DREF_SSC_SOURCE_ENABLE;
5087
5088 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5089 final |= DREF_SSC1_ENABLE;
5090
5091 if (has_cpu_edp) {
5092 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5093 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5094 else
5095 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5096 } else
5097 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5098 } else {
5099 final |= DREF_SSC_SOURCE_DISABLE;
5100 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5101 }
5102
5103 if (final == val)
5104 return;
5105
13d83a67 5106 /* Always enable nonspread source */
74cfd7ac 5107 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5108
99eb6a01 5109 if (has_ck505)
74cfd7ac 5110 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5111 else
74cfd7ac 5112 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5113
199e5d79 5114 if (has_panel) {
74cfd7ac
CW		 5115 val &= ~DREF_SSC_SOURCE_MASK;
5116 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5117
199e5d79 5118 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5119 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5120 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5121 val |= DREF_SSC1_ENABLE;
e77166b5 5122 } else
74cfd7ac 5123 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5124
5125 /* Get SSC going before enabling the outputs */
74cfd7ac 5126 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5127 POSTING_READ(PCH_DREF_CONTROL);
5128 udelay(200);
5129
74cfd7ac 5130 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5131
5132 /* Enable CPU source on CPU attached eDP */
199e5d79 5133 if (has_cpu_edp) {
99eb6a01 5134 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5135 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5136 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5137 }
13d83a67 5138 else
74cfd7ac 5139 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5140 } else
74cfd7ac 5141 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5142
74cfd7ac 5143 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5144 POSTING_READ(PCH_DREF_CONTROL);
5145 udelay(200);
5146 } else {
5147 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5148
74cfd7ac 5149 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5150
5151 /* Turn off CPU output */
74cfd7ac 5152 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5153
74cfd7ac 5154 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5155 POSTING_READ(PCH_DREF_CONTROL);
5156 udelay(200);
5157
5158 /* Turn off the SSC source */
74cfd7ac
CW		 5159 val &= ~DREF_SSC_SOURCE_MASK;
5160 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5161
5162 /* Turn off SSC1 */
74cfd7ac 5163 val &= ~DREF_SSC1_ENABLE;
199e5d79 5164
74cfd7ac 5165 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5166 POSTING_READ(PCH_DREF_CONTROL);
5167 udelay(200);
5168 }
74cfd7ac
CW		 5169
5170 BUG_ON(val != final);
13d83a67
JB		 5171}
5172
dde86e2d
PZ		 5173/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5174static void lpt_init_pch_refclk(struct drm_device *dev)
5175{
5176 struct drm_i915_private *dev_priv = dev->dev_private;
5177 struct drm_mode_config *mode_config = &dev->mode_config;
5178 struct intel_encoder *encoder;
5179 bool has_vga = false;
5180 bool is_sdv = false;
5181 u32 tmp;
5182
5183 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5184 switch (encoder->type) {
5185 case INTEL_OUTPUT_ANALOG:
5186 has_vga = true;
5187 break;
5188 }
5189 }
5190
5191 if (!has_vga)
5192 return;
5193
c00db246
DV		 5194 mutex_lock(&dev_priv->dpio_lock);
5195
dde86e2d
PZ		 5196 /* XXX: Rip out SDV support once Haswell ships for real. */
5197 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5198 is_sdv = true;
5199
5200 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5201 tmp &= ~SBI_SSCCTL_DISABLE;
5202 tmp |= SBI_SSCCTL_PATHALT;
5203 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5204
5205 udelay(24);
5206
5207 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5208 tmp &= ~SBI_SSCCTL_PATHALT;
5209 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5210
5211 if (!is_sdv) {
5212 tmp = I915_READ(SOUTH_CHICKEN2);
5213 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5214 I915_WRITE(SOUTH_CHICKEN2, tmp);
5215
5216 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5217 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5218 DRM_ERROR("FDI mPHY reset assert timeout\n");
5219
5220 tmp = I915_READ(SOUTH_CHICKEN2);
5221 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5222 I915_WRITE(SOUTH_CHICKEN2, tmp);
5223
5224 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5225 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5226 100))
5227 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5228 }
5229
5230 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5231 tmp &= ~(0xFF << 24);
5232 tmp |= (0x12 << 24);
5233 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5234
dde86e2d
PZ		 5235 if (is_sdv) {
5236 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5237 tmp |= 0x7FFF;
5238 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5239 }
5240
5241 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5242 tmp |= (1 << 11);
5243 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5244
5245 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5246 tmp |= (1 << 11);
5247 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5248
5249 if (is_sdv) {
5250 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5251 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5252 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5255 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5256 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5259 tmp |= (0x3F << 8);
5260 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5261
5262 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5263 tmp |= (0x3F << 8);
5264 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5265 }
5266
5267 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5268 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5269 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5270
5271 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5272 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5273 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5274
5275 if (!is_sdv) {
5276 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5277 tmp &= ~(7 << 13);
5278 tmp |= (5 << 13);
5279 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5280
5281 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5282 tmp &= ~(7 << 13);
5283 tmp |= (5 << 13);
5284 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5285 }
5286
5287 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5288 tmp &= ~0xFF;
5289 tmp |= 0x1C;
5290 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5291
5292 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5293 tmp &= ~0xFF;
5294 tmp |= 0x1C;
5295 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5296
5297 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5298 tmp &= ~(0xFF << 16);
5299 tmp |= (0x1C << 16);
5300 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5301
5302 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5303 tmp &= ~(0xFF << 16);
5304 tmp |= (0x1C << 16);
5305 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5306
5307 if (!is_sdv) {
5308 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5309 tmp |= (1 << 27);
5310 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5311
5312 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5313 tmp |= (1 << 27);
5314 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5315
5316 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5317 tmp &= ~(0xF << 28);
5318 tmp |= (4 << 28);
5319 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5320
5321 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5322 tmp &= ~(0xF << 28);
5323 tmp |= (4 << 28);
5324 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5325 }
5326
5327 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5328 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5329 tmp |= SBI_DBUFF0_ENABLE;
5330 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5331
5332 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5333}
5334
5335/*
5336 * Initialize reference clocks when the driver loads
5337 */
5338void intel_init_pch_refclk(struct drm_device *dev)
5339{
5340 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5341 ironlake_init_pch_refclk(dev);
5342 else if (HAS_PCH_LPT(dev))
5343 lpt_init_pch_refclk(dev);
5344}
5345
d9d444cb
JB		 5346static int ironlake_get_refclk(struct drm_crtc *crtc)
5347{
5348 struct drm_device *dev = crtc->dev;
5349 struct drm_i915_private *dev_priv = dev->dev_private;
5350 struct intel_encoder *encoder;
d9d444cb
JB		 5351 int num_connectors = 0;
5352 bool is_lvds = false;
5353
6c2b7c12 5354 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5355 switch (encoder->type) {
5356 case INTEL_OUTPUT_LVDS:
5357 is_lvds = true;
5358 break;
d9d444cb
JB		 5359 }
5360 num_connectors++;
5361 }
5362
5363 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5364 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5365 dev_priv->vbt.lvds_ssc_freq);
5366 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5367 }
5368
5369 return 120000;
5370}
5371
6ff93609 5372static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5373{
c8203565 5374 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376 int pipe = intel_crtc->pipe;
c8203565
PZ		 5377 uint32_t val;
5378
5379 val = I915_READ(PIPECONF(pipe));
5380
dfd07d72 5381 val &= ~PIPECONF_BPC_MASK;
965e0c48 5382 switch (intel_crtc->config.pipe_bpp) {
c8203565 5383 case 18:
dfd07d72 5384 val |= PIPECONF_6BPC;
c8203565
PZ		 5385 break;
5386 case 24:
dfd07d72 5387 val |= PIPECONF_8BPC;
c8203565
PZ		 5388 break;
5389 case 30:
dfd07d72 5390 val |= PIPECONF_10BPC;
c8203565
PZ		 5391 break;
5392 case 36:
dfd07d72 5393 val |= PIPECONF_12BPC;
c8203565
PZ		 5394 break;
5395 default:
cc769b62
PZ		 5396 /* Case prevented by intel_choose_pipe_bpp_dither. */
5397 BUG();
c8203565
PZ		 5398 }
5399
5400 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5401 if (intel_crtc->config.dither)
c8203565
PZ		 5402 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5403
5404 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5405 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5406 val |= PIPECONF_INTERLACED_ILK;
5407 else
5408 val |= PIPECONF_PROGRESSIVE;
5409
50f3b016 5410 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5411 val |= PIPECONF_COLOR_RANGE_SELECT;
5412 else
5413 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5414
c8203565
PZ		 5415 I915_WRITE(PIPECONF(pipe), val);
5416 POSTING_READ(PIPECONF(pipe));
5417}
5418
86d3efce
VS		 5419/*
5420 * Set up the pipe CSC unit.
5421 *
5422 * Currently only full range RGB to limited range RGB conversion
5423 * is supported, but eventually this should handle various
5424 * RGB<->YCbCr scenarios as well.
5425 */
50f3b016 5426static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5427{
5428 struct drm_device *dev = crtc->dev;
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431 int pipe = intel_crtc->pipe;
5432 uint16_t coeff = 0x7800; /* 1.0 */
5433
5434 /*
5435 * TODO: Check what kind of values actually come out of the pipe
5436 * with these coeff/postoff values and adjust to get the best
5437 * accuracy. Perhaps we even need to take the bpc value into
5438 * consideration.
5439 */
5440
50f3b016 5441 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5442 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5443
5444 /*
5445 * GY/GU and RY/RU should be the other way around according
5446 * to BSpec, but reality doesn't agree. Just set them up in
5447 * a way that results in the correct picture.
5448 */
5449 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5450 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5451
5452 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5453 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5454
5455 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5456 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5457
5458 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5459 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5460 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5461
5462 if (INTEL_INFO(dev)->gen > 6) {
5463 uint16_t postoff = 0;
5464
50f3b016 5465 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5466 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5467
5468 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5469 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5470 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5471
5472 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5473 } else {
5474 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5475
50f3b016 5476 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5477 mode |= CSC_BLACK_SCREEN_OFFSET;
5478
5479 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5480 }
5481}
5482
6ff93609 5483static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5484{
5485 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5487 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5488 uint32_t val;
5489
702e7a56 5490 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5491
5492 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5493 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5494 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5495
5496 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5497 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5498 val |= PIPECONF_INTERLACED_ILK;
5499 else
5500 val |= PIPECONF_PROGRESSIVE;
5501
702e7a56
PZ		 5502 I915_WRITE(PIPECONF(cpu_transcoder), val);
5503 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5504}
5505
6591c6e4 5506static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5507 intel_clock_t *clock,
5508 bool *has_reduced_clock,
5509 intel_clock_t *reduced_clock)
5510{
5511 struct drm_device *dev = crtc->dev;
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513 struct intel_encoder *intel_encoder;
5514 int refclk;
d4906093 5515 const intel_limit_t *limit;
a16af721 5516 bool ret, is_lvds = false;
79e53945 5517
6591c6e4
PZ		 5518 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5519 switch (intel_encoder->type) {
79e53945
JB		 5520 case INTEL_OUTPUT_LVDS:
5521 is_lvds = true;
5522 break;
79e53945
JB		 5523 }
5524 }
5525
d9d444cb 5526 refclk = ironlake_get_refclk(crtc);
79e53945 5527
d4906093
ML		 5528 /*
5529 * Returns a set of divisors for the desired target clock with the given
5530 * refclk, or FALSE. The returned values represent the clock equation:
5531 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5532 */
1b894b59 5533 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5534 ret = dev_priv->display.find_dpll(limit, crtc,
5535 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5536 refclk, NULL, clock);
6591c6e4
PZ		 5537 if (!ret)
5538 return false;
cda4b7d3 5539
ddc9003c 5540 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5541 /*
5542 * Ensure we match the reduced clock's P to the target clock.
5543 * If the clocks don't match, we can't switch the display clock
5544 * by using the FP0/FP1. In such case we will disable the LVDS
5545 * downclock feature.
5546 */
ee9300bb
DV		 5547 *has_reduced_clock =
5548 dev_priv->display.find_dpll(limit, crtc,
5549 dev_priv->lvds_downclock,
5550 refclk, clock,
5551 reduced_clock);
652c393a 5552 }
61e9653f 5553
6591c6e4
PZ		 5554 return true;
5555}
5556
01a415fd
DV		 5557static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5558{
5559 struct drm_i915_private *dev_priv = dev->dev_private;
5560 uint32_t temp;
5561
5562 temp = I915_READ(SOUTH_CHICKEN1);
5563 if (temp & FDI_BC_BIFURCATION_SELECT)
5564 return;
5565
5566 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5567 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5568
5569 temp |= FDI_BC_BIFURCATION_SELECT;
5570 DRM_DEBUG_KMS("enabling fdi C rx\n");
5571 I915_WRITE(SOUTH_CHICKEN1, temp);
5572 POSTING_READ(SOUTH_CHICKEN1);
5573}
5574
ebfd86fd
DV		 5575static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5576{
5577 struct drm_device *dev = intel_crtc->base.dev;
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5579
5580 switch (intel_crtc->pipe) {
5581 case PIPE_A:
5582 break;
5583 case PIPE_B:
5584 if (intel_crtc->config.fdi_lanes > 2)
5585 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5586 else
5587 cpt_enable_fdi_bc_bifurcation(dev);
5588
5589 break;
5590 case PIPE_C:
01a415fd
DV		 5591 cpt_enable_fdi_bc_bifurcation(dev);
5592
ebfd86fd 5593 break;
01a415fd
DV		 5594 default:
5595 BUG();
5596 }
5597}
5598
d4b1931c
PZ		 5599int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5600{
5601 /*
5602 * Account for spread spectrum to avoid
5603 * oversubscribing the link. Max center spread
5604 * is 2.5%; use 5% for safety's sake.
5605 */
5606 u32 bps = target_clock * bpp * 21 / 20;
5607 return bps / (link_bw * 8) + 1;
5608}
5609
7429e9d4
DV		 5610static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5611{
5612 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5613}
5614
de13a2e3 5615static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5616 u32 *fp,
9a7c7890 5617 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5618{
de13a2e3 5619 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5620 struct drm_device *dev = crtc->dev;
5621 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5622 struct intel_encoder *intel_encoder;
5623 uint32_t dpll;
6cc5f341 5624 int factor, num_connectors = 0;
09ede541 5625 bool is_lvds = false, is_sdvo = false;
79e53945 5626
de13a2e3
PZ		 5627 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5628 switch (intel_encoder->type) {
79e53945
JB		 5629 case INTEL_OUTPUT_LVDS:
5630 is_lvds = true;
5631 break;
5632 case INTEL_OUTPUT_SDVO:
7d57382e 5633 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5634 is_sdvo = true;
5635 break;
79e53945 5636 }
43565a06 5637
c751ce4f 5638 num_connectors++;
79e53945 5639 }
79e53945 5640
c1858123 5641 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5642 factor = 21;
5643 if (is_lvds) {
5644 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5645 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5646 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5647 factor = 25;
09ede541 5648 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5649 factor = 20;
c1858123 5650
7429e9d4 5651 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5652 *fp |= FP_CB_TUNE;
2c07245f 5653
9a7c7890
DV		 5654 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5655 *fp2 |= FP_CB_TUNE;
5656
5eddb70b 5657 dpll = 0;
2c07245f 5658
a07d6787
EA		 5659 if (is_lvds)
5660 dpll |= DPLLB_MODE_LVDS;
5661 else
5662 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5663
ef1b460d
DV		 5664 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5665 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5666
5667 if (is_sdvo)
5668 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5669 if (intel_crtc->config.has_dp_encoder)
a07d6787 5670 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5671
a07d6787 5672 /* compute bitmask from p1 value */
7429e9d4 5673 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5674 /* also FPA1 */
7429e9d4 5675 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5676
7429e9d4 5677 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5678 case 5:
5679 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5680 break;
5681 case 7:
5682 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5683 break;
5684 case 10:
5685 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5686 break;
5687 case 14:
5688 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5689 break;
79e53945
JB		 5690 }
5691
b4c09f3b 5692 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5693 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5694 else
5695 dpll |= PLL_REF_INPUT_DREFCLK;
5696
de13a2e3
PZ		 5697 return dpll;
5698}
5699
5700static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5701 int x, int y,
5702 struct drm_framebuffer *fb)
5703{
5704 struct drm_device *dev = crtc->dev;
5705 struct drm_i915_private *dev_priv = dev->dev_private;
5706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5707 int pipe = intel_crtc->pipe;
5708 int plane = intel_crtc->plane;
5709 int num_connectors = 0;
5710 intel_clock_t clock, reduced_clock;
cbbab5bd 5711 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5712 bool ok, has_reduced_clock = false;
8b47047b 5713 bool is_lvds = false;
de13a2e3 5714 struct intel_encoder *encoder;
de13a2e3 5715 int ret;
de13a2e3
PZ		 5716
5717 for_each_encoder_on_crtc(dev, crtc, encoder) {
5718 switch (encoder->type) {
5719 case INTEL_OUTPUT_LVDS:
5720 is_lvds = true;
5721 break;
de13a2e3
PZ		 5722 }
5723
5724 num_connectors++;
a07d6787 5725 }
79e53945 5726
5dc5298b
PZ		 5727 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5728 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5729
ff9a6750 5730 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5731 &has_reduced_clock, &reduced_clock);
ee9300bb 5732 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5733 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5734 return -EINVAL;
79e53945 5735 }
f47709a9
DV		 5736 /* Compat-code for transition, will disappear. */
5737 if (!intel_crtc->config.clock_set) {
5738 intel_crtc->config.dpll.n = clock.n;
5739 intel_crtc->config.dpll.m1 = clock.m1;
5740 intel_crtc->config.dpll.m2 = clock.m2;
5741 intel_crtc->config.dpll.p1 = clock.p1;
5742 intel_crtc->config.dpll.p2 = clock.p2;
5743 }
79e53945 5744
de13a2e3
PZ		 5745 /* Ensure that the cursor is valid for the new mode before changing... */
5746 intel_crtc_update_cursor(crtc, true);
5747
5dc5298b 5748 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5749 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5750 struct intel_pch_pll *pll;
4b645f14 5751
7429e9d4 5752 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5753 if (has_reduced_clock)
7429e9d4 5754 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5755
7429e9d4 5756 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5757 &fp, &reduced_clock,
5758 has_reduced_clock ? &fp2 : NULL);
5759
ee7b9f93
JB		 5760 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5761 if (pll == NULL) {
84f44ce7
VS		 5762 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5763 pipe_name(pipe));
4b645f14
JB		 5764 return -EINVAL;
5765 }
ee7b9f93
JB		 5766 } else
5767 intel_put_pch_pll(intel_crtc);
79e53945 5768
03afc4a2
DV		 5769 if (intel_crtc->config.has_dp_encoder)
5770 intel_dp_set_m_n(intel_crtc);
79e53945 5771
dafd226c
DV		 5772 for_each_encoder_on_crtc(dev, crtc, encoder)
5773 if (encoder->pre_pll_enable)
5774 encoder->pre_pll_enable(encoder);
79e53945 5775
ee7b9f93
JB		 5776 if (intel_crtc->pch_pll) {
5777 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5778
32f9d658 5779 /* Wait for the clocks to stabilize. */
ee7b9f93 5780 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5781 udelay(150);
5782
8febb297
EA		 5783 /* The pixel multiplier can only be updated once the
5784 * DPLL is enabled and the clocks are stable.
5785 *
5786 * So write it again.
5787 */
ee7b9f93 5788 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5789 }
79e53945 5790
5eddb70b 5791 intel_crtc->lowfreq_avail = false;
ee7b9f93 5792 if (intel_crtc->pch_pll) {
4b645f14 5793 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5794 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5795 intel_crtc->lowfreq_avail = true;
4b645f14 5796 } else {
ee7b9f93 5797 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5798 }
5799 }
5800
8a654f3b 5801 intel_set_pipe_timings(intel_crtc);
5eddb70b 5802
ca3a0ff8 5803 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5804 intel_cpu_transcoder_set_m_n(intel_crtc,
5805 &intel_crtc->config.fdi_m_n);
5806 }
2c07245f 5807
ebfd86fd
DV		 5808 if (IS_IVYBRIDGE(dev))
5809 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5810
6ff93609 5811 ironlake_set_pipeconf(crtc);
79e53945 5812
a1f9e77e
PZ		 5813 /* Set up the display plane register */
5814 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5815 POSTING_READ(DSPCNTR(plane));
79e53945 5816
94352cf9 5817 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5818
5819 intel_update_watermarks(dev);
5820
1857e1da 5821 return ret;
79e53945
JB		 5822}
5823
72419203
DV		 5824static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5825 struct intel_crtc_config *pipe_config)
5826{
5827 struct drm_device *dev = crtc->base.dev;
5828 struct drm_i915_private *dev_priv = dev->dev_private;
5829 enum transcoder transcoder = pipe_config->cpu_transcoder;
5830
5831 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5832 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5833 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5834 & ~TU_SIZE_MASK;
5835 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5836 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5837 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5838}
5839
2fa2fe9a
DV		 5840static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5841 struct intel_crtc_config *pipe_config)
5842{
5843 struct drm_device *dev = crtc->base.dev;
5844 struct drm_i915_private *dev_priv = dev->dev_private;
5845 uint32_t tmp;
5846
5847 tmp = I915_READ(PF_CTL(crtc->pipe));
5848
5849 if (tmp & PF_ENABLE) {
5850 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5851 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5852
5853 /* We currently do not free assignements of panel fitters on
5854 * ivb/hsw (since we don't use the higher upscaling modes which
5855 * differentiates them) so just WARN about this case for now. */
5856 if (IS_GEN7(dev)) {
5857 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5858 PF_PIPE_SEL_IVB(crtc->pipe));
5859 }
2fa2fe9a
DV		 5860 }
5861}
5862
0e8ffe1b
DV		 5863static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5864 struct intel_crtc_config *pipe_config)
5865{
5866 struct drm_device *dev = crtc->base.dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 uint32_t tmp;
5869
eccb140b
DV		 5870 pipe_config->cpu_transcoder = crtc->pipe;
5871
0e8ffe1b
DV		 5872 tmp = I915_READ(PIPECONF(crtc->pipe));
5873 if (!(tmp & PIPECONF_ENABLE))
5874 return false;
5875
ab9412ba 5876 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5877 pipe_config->has_pch_encoder = true;
5878
627eb5a3
DV		 5879 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5880 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5881 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5882
5883 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5884
5885 /* XXX: Can't properly read out the pch dpll pixel multiplier
5886 * since we don't have state tracking for pch clocks yet. */
5887 pipe_config->pixel_multiplier = 1;
5888 } else {
5889 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5890 }
5891
1bd1bd80
DV		 5892 intel_get_pipe_timings(crtc, pipe_config);
5893
2fa2fe9a
DV		 5894 ironlake_get_pfit_config(crtc, pipe_config);
5895
0e8ffe1b
DV		 5896 return true;
5897}
5898
d6dd9eb1
DV		 5899static void haswell_modeset_global_resources(struct drm_device *dev)
5900{
d6dd9eb1
DV		 5901 bool enable = false;
5902 struct intel_crtc *crtc;
d6dd9eb1
DV		 5903
5904 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5905 if (!crtc->base.enabled)
5906 continue;
d6dd9eb1 5907
e7a639c4
DV		 5908 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5909 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5910 enable = true;
5911 }
5912
d6dd9eb1
DV		 5913 intel_set_power_well(dev, enable);
5914}
5915
09b4ddf9 5916static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5917 int x, int y,
5918 struct drm_framebuffer *fb)
5919{
5920 struct drm_device *dev = crtc->dev;
5921 struct drm_i915_private *dev_priv = dev->dev_private;
5922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5923 int plane = intel_crtc->plane;
09b4ddf9 5924 int ret;
09b4ddf9 5925
ff9a6750 5926 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5927 return -EINVAL;
5928
09b4ddf9
PZ		 5929 /* Ensure that the cursor is valid for the new mode before changing... */
5930 intel_crtc_update_cursor(crtc, true);
5931
03afc4a2
DV		 5932 if (intel_crtc->config.has_dp_encoder)
5933 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5934
5935 intel_crtc->lowfreq_avail = false;
09b4ddf9 5936
8a654f3b 5937 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5938
ca3a0ff8 5939 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5940 intel_cpu_transcoder_set_m_n(intel_crtc,
5941 &intel_crtc->config.fdi_m_n);
5942 }
09b4ddf9 5943
6ff93609 5944 haswell_set_pipeconf(crtc);
09b4ddf9 5945
50f3b016 5946 intel_set_pipe_csc(crtc);
86d3efce 5947
09b4ddf9 5948 /* Set up the display plane register */
86d3efce 5949 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5950 POSTING_READ(DSPCNTR(plane));
5951
5952 ret = intel_pipe_set_base(crtc, x, y, fb);
5953
5954 intel_update_watermarks(dev);
5955
1f803ee5 5956 return ret;
79e53945
JB		 5957}
5958
0e8ffe1b
DV		 5959static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5960 struct intel_crtc_config *pipe_config)
5961{
5962 struct drm_device *dev = crtc->base.dev;
5963 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5964 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5965 uint32_t tmp;
5966
eccb140b
DV		 5967 pipe_config->cpu_transcoder = crtc->pipe;
5968 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5969 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5970 enum pipe trans_edp_pipe;
5971 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5972 default:
5973 WARN(1, "unknown pipe linked to edp transcoder\n");
5974 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5975 case TRANS_DDI_EDP_INPUT_A_ON:
5976 trans_edp_pipe = PIPE_A;
5977 break;
5978 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5979 trans_edp_pipe = PIPE_B;
5980 break;
5981 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5982 trans_edp_pipe = PIPE_C;
5983 break;
5984 }
5985
5986 if (trans_edp_pipe == crtc->pipe)
5987 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5988 }
5989
b97186f0 5990 if (!intel_display_power_enabled(dev,
eccb140b 5991 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5992 return false;
5993
eccb140b 5994 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5995 if (!(tmp & PIPECONF_ENABLE))
5996 return false;
5997
88adfff1 5998 /*
f196e6be 5999 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6000 * DDI E. So just check whether this pipe is wired to DDI E and whether
6001 * the PCH transcoder is on.
6002 */
eccb140b 6003 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6004 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6005 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6006 pipe_config->has_pch_encoder = true;
6007
627eb5a3
DV		 6008 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6009 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6010 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6011
6012 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6013 }
6014
1bd1bd80
DV		 6015 intel_get_pipe_timings(crtc, pipe_config);
6016
2fa2fe9a
DV		 6017 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6018 if (intel_display_power_enabled(dev, pfit_domain))
6019 ironlake_get_pfit_config(crtc, pipe_config);
6020
42db64ef
PZ		 6021 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6022 (I915_READ(IPS_CTL) & IPS_ENABLE);
6023
6c49f241
DV		 6024 pipe_config->pixel_multiplier = 1;
6025
0e8ffe1b
DV		 6026 return true;
6027}
6028
f564048e 6029static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6030 int x, int y,
94352cf9 6031 struct drm_framebuffer *fb)
f564048e
EA		 6032{
6033 struct drm_device *dev = crtc->dev;
6034 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6035 struct drm_encoder_helper_funcs *encoder_funcs;
6036 struct intel_encoder *encoder;
0b701d27 6037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6038 struct drm_display_mode *adjusted_mode =
6039 &intel_crtc->config.adjusted_mode;
6040 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6041 int pipe = intel_crtc->pipe;
f564048e
EA		 6042 int ret;
6043
0b701d27 6044 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6045
b8cecdf5
DV		 6046 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6047
79e53945 6048 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6049
9256aa19
DV		 6050 if (ret != 0)
6051 return ret;
6052
6053 for_each_encoder_on_crtc(dev, crtc, encoder) {
6054 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6055 encoder->base.base.id,
6056 drm_get_encoder_name(&encoder->base),
6057 mode->base.id, mode->name);
6cc5f341
DV		 6058 if (encoder->mode_set) {
6059 encoder->mode_set(encoder);
6060 } else {
6061 encoder_funcs = encoder->base.helper_private;
6062 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6063 }
9256aa19
DV		 6064 }
6065
6066 return 0;
79e53945
JB		 6067}
6068
3a9627f4
WF		 6069static bool intel_eld_uptodate(struct drm_connector *connector,
6070 int reg_eldv, uint32_t bits_eldv,
6071 int reg_elda, uint32_t bits_elda,
6072 int reg_edid)
6073{
6074 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6075 uint8_t *eld = connector->eld;
6076 uint32_t i;
6077
6078 i = I915_READ(reg_eldv);
6079 i &= bits_eldv;
6080
6081 if (!eld[0])
6082 return !i;
6083
6084 if (!i)
6085 return false;
6086
6087 i = I915_READ(reg_elda);
6088 i &= ~bits_elda;
6089 I915_WRITE(reg_elda, i);
6090
6091 for (i = 0; i < eld[2]; i++)
6092 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6093 return false;
6094
6095 return true;
6096}
6097
e0dac65e
WF		 6098static void g4x_write_eld(struct drm_connector *connector,
6099 struct drm_crtc *crtc)
6100{
6101 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6102 uint8_t *eld = connector->eld;
6103 uint32_t eldv;
6104 uint32_t len;
6105 uint32_t i;
6106
6107 i = I915_READ(G4X_AUD_VID_DID);
6108
6109 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6110 eldv = G4X_ELDV_DEVCL_DEVBLC;
6111 else
6112 eldv = G4X_ELDV_DEVCTG;
6113
3a9627f4
WF		 6114 if (intel_eld_uptodate(connector,
6115 G4X_AUD_CNTL_ST, eldv,
6116 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6117 G4X_HDMIW_HDMIEDID))
6118 return;
6119
e0dac65e
WF		 6120 i = I915_READ(G4X_AUD_CNTL_ST);
6121 i &= ~(eldv | G4X_ELD_ADDR);
6122 len = (i >> 9) & 0x1f; /* ELD buffer size */
6123 I915_WRITE(G4X_AUD_CNTL_ST, i);
6124
6125 if (!eld[0])
6126 return;
6127
6128 len = min_t(uint8_t, eld[2], len);
6129 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6130 for (i = 0; i < len; i++)
6131 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6132
6133 i = I915_READ(G4X_AUD_CNTL_ST);
6134 i |= eldv;
6135 I915_WRITE(G4X_AUD_CNTL_ST, i);
6136}
6137
83358c85
WX		 6138static void haswell_write_eld(struct drm_connector *connector,
6139 struct drm_crtc *crtc)
6140{
6141 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6142 uint8_t *eld = connector->eld;
6143 struct drm_device *dev = crtc->dev;
7b9f35a6 6144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6145 uint32_t eldv;
6146 uint32_t i;
6147 int len;
6148 int pipe = to_intel_crtc(crtc)->pipe;
6149 int tmp;
6150
6151 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6152 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6153 int aud_config = HSW_AUD_CFG(pipe);
6154 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6155
6156
6157 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6158
6159 /* Audio output enable */
6160 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6161 tmp = I915_READ(aud_cntrl_st2);
6162 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6163 I915_WRITE(aud_cntrl_st2, tmp);
6164
6165 /* Wait for 1 vertical blank */
6166 intel_wait_for_vblank(dev, pipe);
6167
6168 /* Set ELD valid state */
6169 tmp = I915_READ(aud_cntrl_st2);
6170 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6171 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6172 I915_WRITE(aud_cntrl_st2, tmp);
6173 tmp = I915_READ(aud_cntrl_st2);
6174 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6175
6176 /* Enable HDMI mode */
6177 tmp = I915_READ(aud_config);
6178 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6179 /* clear N_programing_enable and N_value_index */
6180 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6181 I915_WRITE(aud_config, tmp);
6182
6183 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6184
6185 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6186 intel_crtc->eld_vld = true;
83358c85
WX		 6187
6188 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6189 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6190 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6191 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6192 } else
6193 I915_WRITE(aud_config, 0);
6194
6195 if (intel_eld_uptodate(connector,
6196 aud_cntrl_st2, eldv,
6197 aud_cntl_st, IBX_ELD_ADDRESS,
6198 hdmiw_hdmiedid))
6199 return;
6200
6201 i = I915_READ(aud_cntrl_st2);
6202 i &= ~eldv;
6203 I915_WRITE(aud_cntrl_st2, i);
6204
6205 if (!eld[0])
6206 return;
6207
6208 i = I915_READ(aud_cntl_st);
6209 i &= ~IBX_ELD_ADDRESS;
6210 I915_WRITE(aud_cntl_st, i);
6211 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6212 DRM_DEBUG_DRIVER("port num:%d\n", i);
6213
6214 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6215 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6216 for (i = 0; i < len; i++)
6217 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6218
6219 i = I915_READ(aud_cntrl_st2);
6220 i |= eldv;
6221 I915_WRITE(aud_cntrl_st2, i);
6222
6223}
6224
e0dac65e
WF		 6225static void ironlake_write_eld(struct drm_connector *connector,
6226 struct drm_crtc *crtc)
6227{
6228 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6229 uint8_t *eld = connector->eld;
6230 uint32_t eldv;
6231 uint32_t i;
6232 int len;
6233 int hdmiw_hdmiedid;
b6daa025 6234 int aud_config;
e0dac65e
WF		 6235 int aud_cntl_st;
6236 int aud_cntrl_st2;
9b138a83 6237 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6238
b3f33cbf 6239 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6240 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6241 aud_config = IBX_AUD_CFG(pipe);
6242 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6243 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6244 } else {
9b138a83
WX		 6245 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6246 aud_config = CPT_AUD_CFG(pipe);
6247 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6248 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6249 }
6250
9b138a83 6251 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6252
6253 i = I915_READ(aud_cntl_st);
9b138a83 6254 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6255 if (!i) {
6256 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6257 /* operate blindly on all ports */
1202b4c6
WF		 6258 eldv = IBX_ELD_VALIDB;
6259 eldv |= IBX_ELD_VALIDB << 4;
6260 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6261 } else {
2582a850 6262 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6263 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6264 }
6265
3a9627f4
WF		 6266 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6267 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6268 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6269 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6270 } else
6271 I915_WRITE(aud_config, 0);
e0dac65e 6272
3a9627f4
WF		 6273 if (intel_eld_uptodate(connector,
6274 aud_cntrl_st2, eldv,
6275 aud_cntl_st, IBX_ELD_ADDRESS,
6276 hdmiw_hdmiedid))
6277 return;
6278
e0dac65e
WF		 6279 i = I915_READ(aud_cntrl_st2);
6280 i &= ~eldv;
6281 I915_WRITE(aud_cntrl_st2, i);
6282
6283 if (!eld[0])
6284 return;
6285
e0dac65e 6286 i = I915_READ(aud_cntl_st);
1202b4c6 6287 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6288 I915_WRITE(aud_cntl_st, i);
6289
6290 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6291 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6292 for (i = 0; i < len; i++)
6293 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6294
6295 i = I915_READ(aud_cntrl_st2);
6296 i |= eldv;
6297 I915_WRITE(aud_cntrl_st2, i);
6298}
6299
6300void intel_write_eld(struct drm_encoder *encoder,
6301 struct drm_display_mode *mode)
6302{
6303 struct drm_crtc *crtc = encoder->crtc;
6304 struct drm_connector *connector;
6305 struct drm_device *dev = encoder->dev;
6306 struct drm_i915_private *dev_priv = dev->dev_private;
6307
6308 connector = drm_select_eld(encoder, mode);
6309 if (!connector)
6310 return;
6311
6312 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6313 connector->base.id,
6314 drm_get_connector_name(connector),
6315 connector->encoder->base.id,
6316 drm_get_encoder_name(connector->encoder));
6317
6318 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6319
6320 if (dev_priv->display.write_eld)
6321 dev_priv->display.write_eld(connector, crtc);
6322}
6323
79e53945
JB		 6324/** Loads the palette/gamma unit for the CRTC with the prepared values */
6325void intel_crtc_load_lut(struct drm_crtc *crtc)
6326{
6327 struct drm_device *dev = crtc->dev;
6328 struct drm_i915_private *dev_priv = dev->dev_private;
6329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6330 enum pipe pipe = intel_crtc->pipe;
6331 int palreg = PALETTE(pipe);
79e53945 6332 int i;
42db64ef 6333 bool reenable_ips = false;
79e53945
JB		 6334
6335 /* The clocks have to be on to load the palette. */
aed3f09d 6336 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6337 return;
6338
14420bd0
VS		 6339 if (!HAS_PCH_SPLIT(dev_priv->dev))
6340 assert_pll_enabled(dev_priv, pipe);
6341
f2b115e6 6342 /* use legacy palette for Ironlake */
bad720ff 6343 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6344 palreg = LGC_PALETTE(pipe);
6345
6346 /* Workaround : Do not read or write the pipe palette/gamma data while
6347 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6348 */
6349 if (intel_crtc->config.ips_enabled &&
6350 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6351 GAMMA_MODE_MODE_SPLIT)) {
6352 hsw_disable_ips(intel_crtc);
6353 reenable_ips = true;
6354 }
2c07245f 6355
79e53945
JB		 6356 for (i = 0; i < 256; i++) {
6357 I915_WRITE(palreg + 4 * i,
6358 (intel_crtc->lut_r[i] << 16) |
6359 (intel_crtc->lut_g[i] << 8) |
6360 intel_crtc->lut_b[i]);
6361 }
42db64ef
PZ		 6362
6363 if (reenable_ips)
6364 hsw_enable_ips(intel_crtc);
79e53945
JB		 6365}
6366
560b85bb
CW		 6367static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6368{
6369 struct drm_device *dev = crtc->dev;
6370 struct drm_i915_private *dev_priv = dev->dev_private;
6371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6372 bool visible = base != 0;
6373 u32 cntl;
6374
6375 if (intel_crtc->cursor_visible == visible)
6376 return;
6377
9db4a9c7 6378 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6379 if (visible) {
6380 /* On these chipsets we can only modify the base whilst
6381 * the cursor is disabled.
6382 */
9db4a9c7 6383 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6384
6385 cntl &= ~(CURSOR_FORMAT_MASK);
6386 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6387 cntl |= CURSOR_ENABLE |
6388 CURSOR_GAMMA_ENABLE |
6389 CURSOR_FORMAT_ARGB;
6390 } else
6391 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6392 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6393
6394 intel_crtc->cursor_visible = visible;
6395}
6396
6397static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6398{
6399 struct drm_device *dev = crtc->dev;
6400 struct drm_i915_private *dev_priv = dev->dev_private;
6401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402 int pipe = intel_crtc->pipe;
6403 bool visible = base != 0;
6404
6405 if (intel_crtc->cursor_visible != visible) {
548f245b 6406 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6407 if (base) {
6408 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6409 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6410 cntl |= pipe << 28; /* Connect to correct pipe */
6411 } else {
6412 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6413 cntl |= CURSOR_MODE_DISABLE;
6414 }
9db4a9c7 6415 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6416
6417 intel_crtc->cursor_visible = visible;
6418 }
6419 /* and commit changes on next vblank */
9db4a9c7 6420 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6421}
6422
65a21cd6
JB		 6423static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6424{
6425 struct drm_device *dev = crtc->dev;
6426 struct drm_i915_private *dev_priv = dev->dev_private;
6427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6428 int pipe = intel_crtc->pipe;
6429 bool visible = base != 0;
6430
6431 if (intel_crtc->cursor_visible != visible) {
6432 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6433 if (base) {
6434 cntl &= ~CURSOR_MODE;
6435 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6436 } else {
6437 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6438 cntl |= CURSOR_MODE_DISABLE;
6439 }
86d3efce
VS		 6440 if (IS_HASWELL(dev))
6441 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6442 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6443
6444 intel_crtc->cursor_visible = visible;
6445 }
6446 /* and commit changes on next vblank */
6447 I915_WRITE(CURBASE_IVB(pipe), base);
6448}
6449
cda4b7d3 6450/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6451static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6452 bool on)
cda4b7d3
CW		 6453{
6454 struct drm_device *dev = crtc->dev;
6455 struct drm_i915_private *dev_priv = dev->dev_private;
6456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6457 int pipe = intel_crtc->pipe;
6458 int x = intel_crtc->cursor_x;
6459 int y = intel_crtc->cursor_y;
560b85bb 6460 u32 base, pos;
cda4b7d3
CW		 6461 bool visible;
6462
6463 pos = 0;
6464
6b383a7f 6465 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6466 base = intel_crtc->cursor_addr;
6467 if (x > (int) crtc->fb->width)
6468 base = 0;
6469
6470 if (y > (int) crtc->fb->height)
6471 base = 0;
6472 } else
6473 base = 0;
6474
6475 if (x < 0) {
6476 if (x + intel_crtc->cursor_width < 0)
6477 base = 0;
6478
6479 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6480 x = -x;
6481 }
6482 pos |= x << CURSOR_X_SHIFT;
6483
6484 if (y < 0) {
6485 if (y + intel_crtc->cursor_height < 0)
6486 base = 0;
6487
6488 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6489 y = -y;
6490 }
6491 pos |= y << CURSOR_Y_SHIFT;
6492
6493 visible = base != 0;
560b85bb 6494 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6495 return;
6496
0cd83aa9 6497 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6498 I915_WRITE(CURPOS_IVB(pipe), pos);
6499 ivb_update_cursor(crtc, base);
6500 } else {
6501 I915_WRITE(CURPOS(pipe), pos);
6502 if (IS_845G(dev) || IS_I865G(dev))
6503 i845_update_cursor(crtc, base);
6504 else
6505 i9xx_update_cursor(crtc, base);
6506 }
cda4b7d3
CW		 6507}
6508
79e53945 6509static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6510 struct drm_file *file,
79e53945
JB		 6511 uint32_t handle,
6512 uint32_t width, uint32_t height)
6513{
6514 struct drm_device *dev = crtc->dev;
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6517 struct drm_i915_gem_object *obj;
cda4b7d3 6518 uint32_t addr;
3f8bc370 6519 int ret;
79e53945 6520
79e53945
JB		 6521 /* if we want to turn off the cursor ignore width and height */
6522 if (!handle) {
28c97730 6523 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6524 addr = 0;
05394f39 6525 obj = NULL;
5004417d 6526 mutex_lock(&dev->struct_mutex);
3f8bc370 6527 goto finish;
79e53945
JB		 6528 }
6529
6530 /* Currently we only support 64x64 cursors */
6531 if (width != 64 || height != 64) {
6532 DRM_ERROR("we currently only support 64x64 cursors\n");
6533 return -EINVAL;
6534 }
6535
05394f39 6536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6537 if (&obj->base == NULL)
79e53945
JB		 6538 return -ENOENT;
6539
05394f39 6540 if (obj->base.size < width * height * 4) {
79e53945 6541 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6542 ret = -ENOMEM;
6543 goto fail;
79e53945
JB		 6544 }
6545
71acb5eb 6546 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6547 mutex_lock(&dev->struct_mutex);
b295d1b6 6548 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6549 unsigned alignment;
6550
d9e86c0e
CW		 6551 if (obj->tiling_mode) {
6552 DRM_ERROR("cursor cannot be tiled\n");
6553 ret = -EINVAL;
6554 goto fail_locked;
6555 }
6556
693db184
CW		 6557 /* Note that the w/a also requires 2 PTE of padding following
6558 * the bo. We currently fill all unused PTE with the shadow
6559 * page and so we should always have valid PTE following the
6560 * cursor preventing the VT-d warning.
6561 */
6562 alignment = 0;
6563 if (need_vtd_wa(dev))
6564 alignment = 64*1024;
6565
6566 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6567 if (ret) {
6568 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6569 goto fail_locked;
e7b526bb
CW		 6570 }
6571
d9e86c0e
CW		 6572 ret = i915_gem_object_put_fence(obj);
6573 if (ret) {
2da3b9b9 6574 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6575 goto fail_unpin;
6576 }
6577
05394f39 6578 addr = obj->gtt_offset;
71acb5eb 6579 } else {
6eeefaf3 6580 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6581 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6582 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6583 align);
71acb5eb
DA		 6584 if (ret) {
6585 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6586 goto fail_locked;
71acb5eb 6587 }
05394f39 6588 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6589 }
6590
a6c45cf0 6591 if (IS_GEN2(dev))
14b60391
JB		 6592 I915_WRITE(CURSIZE, (height << 12) | width);
6593
3f8bc370 6594 finish:
3f8bc370 6595 if (intel_crtc->cursor_bo) {
b295d1b6 6596 if (dev_priv->info->cursor_needs_physical) {
05394f39 6597 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6598 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6599 } else
6600 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6601 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6602 }
80824003 6603
7f9872e0 6604 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6605
6606 intel_crtc->cursor_addr = addr;
05394f39 6607 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6608 intel_crtc->cursor_width = width;
6609 intel_crtc->cursor_height = height;
6610
40ccc72b 6611 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6612
79e53945 6613 return 0;
e7b526bb 6614fail_unpin:
05394f39 6615 i915_gem_object_unpin(obj);
7f9872e0 6616fail_locked:
34b8686e 6617 mutex_unlock(&dev->struct_mutex);
bc9025bd 6618fail:
05394f39 6619 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6620 return ret;
79e53945
JB		 6621}
6622
6623static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6624{
79e53945 6625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6626
cda4b7d3
CW		 6627 intel_crtc->cursor_x = x;
6628 intel_crtc->cursor_y = y;
652c393a 6629
40ccc72b 6630 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6631
6632 return 0;
6633}
6634
6635/** Sets the color ramps on behalf of RandR */
6636void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6637 u16 blue, int regno)
6638{
6639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6640
6641 intel_crtc->lut_r[regno] = red >> 8;
6642 intel_crtc->lut_g[regno] = green >> 8;
6643 intel_crtc->lut_b[regno] = blue >> 8;
6644}
6645
b8c00ac5
DA		 6646void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6647 u16 *blue, int regno)
6648{
6649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650
6651 *red = intel_crtc->lut_r[regno] << 8;
6652 *green = intel_crtc->lut_g[regno] << 8;
6653 *blue = intel_crtc->lut_b[regno] << 8;
6654}
6655
79e53945 6656static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6657 u16 *blue, uint32_t start, uint32_t size)
79e53945 6658{
7203425a 6659 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6661
7203425a 6662 for (i = start; i < end; i++) {
79e53945
JB		 6663 intel_crtc->lut_r[i] = red[i] >> 8;
6664 intel_crtc->lut_g[i] = green[i] >> 8;
6665 intel_crtc->lut_b[i] = blue[i] >> 8;
6666 }
6667
6668 intel_crtc_load_lut(crtc);
6669}
6670
79e53945
JB		 6671/* VESA 640x480x72Hz mode to set on the pipe */
6672static struct drm_display_mode load_detect_mode = {
6673 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6674 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6675};
6676
d2dff872
CW		 6677static struct drm_framebuffer *
6678intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6679 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6680 struct drm_i915_gem_object *obj)
6681{
6682 struct intel_framebuffer *intel_fb;
6683 int ret;
6684
6685 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6686 if (!intel_fb) {
6687 drm_gem_object_unreference_unlocked(&obj->base);
6688 return ERR_PTR(-ENOMEM);
6689 }
6690
6691 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6692 if (ret) {
6693 drm_gem_object_unreference_unlocked(&obj->base);
6694 kfree(intel_fb);
6695 return ERR_PTR(ret);
6696 }
6697
6698 return &intel_fb->base;
6699}
6700
6701static u32
6702intel_framebuffer_pitch_for_width(int width, int bpp)
6703{
6704 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6705 return ALIGN(pitch, 64);
6706}
6707
6708static u32
6709intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6710{
6711 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6712 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6713}
6714
6715static struct drm_framebuffer *
6716intel_framebuffer_create_for_mode(struct drm_device *dev,
6717 struct drm_display_mode *mode,
6718 int depth, int bpp)
6719{
6720 struct drm_i915_gem_object *obj;
0fed39bd 6721 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6722
6723 obj = i915_gem_alloc_object(dev,
6724 intel_framebuffer_size_for_mode(mode, bpp));
6725 if (obj == NULL)
6726 return ERR_PTR(-ENOMEM);
6727
6728 mode_cmd.width = mode->hdisplay;
6729 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6730 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6731 bpp);
5ca0c34a 6732 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6733
6734 return intel_framebuffer_create(dev, &mode_cmd, obj);
6735}
6736
6737static struct drm_framebuffer *
6738mode_fits_in_fbdev(struct drm_device *dev,
6739 struct drm_display_mode *mode)
6740{
6741 struct drm_i915_private *dev_priv = dev->dev_private;
6742 struct drm_i915_gem_object *obj;
6743 struct drm_framebuffer *fb;
6744
6745 if (dev_priv->fbdev == NULL)
6746 return NULL;
6747
6748 obj = dev_priv->fbdev->ifb.obj;
6749 if (obj == NULL)
6750 return NULL;
6751
6752 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6753 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6754 fb->bits_per_pixel))
d2dff872
CW		 6755 return NULL;
6756
01f2c773 6757 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6758 return NULL;
6759
6760 return fb;
6761}
6762
d2434ab7 6763bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6764 struct drm_display_mode *mode,
8261b191 6765 struct intel_load_detect_pipe *old)
79e53945
JB		 6766{
6767 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6768 struct intel_encoder *intel_encoder =
6769 intel_attached_encoder(connector);
79e53945 6770 struct drm_crtc *possible_crtc;
4ef69c7a 6771 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6772 struct drm_crtc *crtc = NULL;
6773 struct drm_device *dev = encoder->dev;
94352cf9 6774 struct drm_framebuffer *fb;
79e53945
JB		 6775 int i = -1;
6776
d2dff872
CW		 6777 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6778 connector->base.id, drm_get_connector_name(connector),
6779 encoder->base.id, drm_get_encoder_name(encoder));
6780
79e53945
JB		 6781 /*
6782 * Algorithm gets a little messy:
7a5e4805 6783 *
79e53945
JB		 6784 * - if the connector already has an assigned crtc, use it (but make
6785 * sure it's on first)
7a5e4805 6786 *
79e53945
JB		 6787 * - try to find the first unused crtc that can drive this connector,
6788 * and use that if we find one
79e53945
JB		 6789 */
6790
6791 /* See if we already have a CRTC for this connector */
6792 if (encoder->crtc) {
6793 crtc = encoder->crtc;
8261b191 6794
7b24056b
DV		 6795 mutex_lock(&crtc->mutex);
6796
24218aac 6797 old->dpms_mode = connector->dpms;
8261b191
CW		 6798 old->load_detect_temp = false;
6799
6800 /* Make sure the crtc and connector are running */
24218aac
DV		 6801 if (connector->dpms != DRM_MODE_DPMS_ON)
6802 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6803
7173188d 6804 return true;
79e53945
JB		 6805 }
6806
6807 /* Find an unused one (if possible) */
6808 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6809 i++;
6810 if (!(encoder->possible_crtcs & (1 << i)))
6811 continue;
6812 if (!possible_crtc->enabled) {
6813 crtc = possible_crtc;
6814 break;
6815 }
79e53945
JB		 6816 }
6817
6818 /*
6819 * If we didn't find an unused CRTC, don't use any.
6820 */
6821 if (!crtc) {
7173188d
CW		 6822 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6823 return false;
79e53945
JB		 6824 }
6825
7b24056b 6826 mutex_lock(&crtc->mutex);
fc303101
DV		 6827 intel_encoder->new_crtc = to_intel_crtc(crtc);
6828 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6829
6830 intel_crtc = to_intel_crtc(crtc);
24218aac 6831 old->dpms_mode = connector->dpms;
8261b191 6832 old->load_detect_temp = true;
d2dff872 6833 old->release_fb = NULL;
79e53945 6834
6492711d
CW		 6835 if (!mode)
6836 mode = &load_detect_mode;
79e53945 6837
d2dff872
CW		 6838 /* We need a framebuffer large enough to accommodate all accesses
6839 * that the plane may generate whilst we perform load detection.
6840 * We can not rely on the fbcon either being present (we get called
6841 * during its initialisation to detect all boot displays, or it may
6842 * not even exist) or that it is large enough to satisfy the
6843 * requested mode.
6844 */
94352cf9
DV		 6845 fb = mode_fits_in_fbdev(dev, mode);
6846 if (fb == NULL) {
d2dff872 6847 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6848 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6849 old->release_fb = fb;
d2dff872
CW		 6850 } else
6851 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6852 if (IS_ERR(fb)) {
d2dff872 6853 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6854 mutex_unlock(&crtc->mutex);
0e8b3d3e 6855 return false;
79e53945 6856 }
79e53945 6857
c0c36b94 6858 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6859 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6860 if (old->release_fb)
6861 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6862 mutex_unlock(&crtc->mutex);
0e8b3d3e 6863 return false;
79e53945 6864 }
7173188d 6865
79e53945 6866 /* let the connector get through one full cycle before testing */
9d0498a2 6867 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6868 return true;
79e53945
JB		 6869}
6870
d2434ab7 6871void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6872 struct intel_load_detect_pipe *old)
79e53945 6873{
d2434ab7
DV		 6874 struct intel_encoder *intel_encoder =
6875 intel_attached_encoder(connector);
4ef69c7a 6876 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6877 struct drm_crtc *crtc = encoder->crtc;
79e53945 6878
d2dff872
CW		 6879 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6880 connector->base.id, drm_get_connector_name(connector),
6881 encoder->base.id, drm_get_encoder_name(encoder));
6882
8261b191 6883 if (old->load_detect_temp) {
fc303101
DV		 6884 to_intel_connector(connector)->new_encoder = NULL;
6885 intel_encoder->new_crtc = NULL;
6886 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6887
36206361
DV		 6888 if (old->release_fb) {
6889 drm_framebuffer_unregister_private(old->release_fb);
6890 drm_framebuffer_unreference(old->release_fb);
6891 }
d2dff872 6892
67c96400 6893 mutex_unlock(&crtc->mutex);
0622a53c 6894 return;
79e53945
JB		 6895 }
6896
c751ce4f 6897 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6898 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6899 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6900
6901 mutex_unlock(&crtc->mutex);
79e53945
JB		 6902}
6903
6904/* Returns the clock of the currently programmed mode of the given pipe. */
6905static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6906{
6907 struct drm_i915_private *dev_priv = dev->dev_private;
6908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6909 int pipe = intel_crtc->pipe;
548f245b 6910 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6911 u32 fp;
6912 intel_clock_t clock;
6913
6914 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6915 fp = I915_READ(FP0(pipe));
79e53945 6916 else
39adb7a5 6917 fp = I915_READ(FP1(pipe));
79e53945
JB		 6918
6919 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6920 if (IS_PINEVIEW(dev)) {
6921 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6922 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6923 } else {
6924 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6925 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6926 }
6927
a6c45cf0 6928 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6929 if (IS_PINEVIEW(dev))
6930 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6931 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6932 else
6933 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6934 DPLL_FPA01_P1_POST_DIV_SHIFT);
6935
6936 switch (dpll & DPLL_MODE_MASK) {
6937 case DPLLB_MODE_DAC_SERIAL:
6938 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6939 5 : 10;
6940 break;
6941 case DPLLB_MODE_LVDS:
6942 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6943 7 : 14;
6944 break;
6945 default:
28c97730 6946 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6947 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6948 return 0;
6949 }
6950
ac58c3f0
DV		 6951 if (IS_PINEVIEW(dev))
6952 pineview_clock(96000, &clock);
6953 else
6954 i9xx_clock(96000, &clock);
79e53945
JB		 6955 } else {
6956 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6957
6958 if (is_lvds) {
6959 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6960 DPLL_FPA01_P1_POST_DIV_SHIFT);
6961 clock.p2 = 14;
6962
6963 if ((dpll & PLL_REF_INPUT_MASK) ==
6964 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6965 /* XXX: might not be 66MHz */
ac58c3f0 6966 i9xx_clock(66000, &clock);
79e53945 6967 } else
ac58c3f0 6968 i9xx_clock(48000, &clock);
79e53945
JB		 6969 } else {
6970 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6971 clock.p1 = 2;
6972 else {
6973 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6974 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6975 }
6976 if (dpll & PLL_P2_DIVIDE_BY_4)
6977 clock.p2 = 4;
6978 else
6979 clock.p2 = 2;
6980
ac58c3f0 6981 i9xx_clock(48000, &clock);
79e53945
JB		 6982 }
6983 }
6984
6985 /* XXX: It would be nice to validate the clocks, but we can't reuse
6986 * i830PllIsValid() because it relies on the xf86_config connector
6987 * configuration being accurate, which it isn't necessarily.
6988 */
6989
6990 return clock.dot;
6991}
6992
6993/** Returns the currently programmed mode of the given pipe. */
6994struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6995 struct drm_crtc *crtc)
6996{
548f245b 6997 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6999 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7000 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7001 int htot = I915_READ(HTOTAL(cpu_transcoder));
7002 int hsync = I915_READ(HSYNC(cpu_transcoder));
7003 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7004 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7005
7006 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7007 if (!mode)
7008 return NULL;
7009
7010 mode->clock = intel_crtc_clock_get(dev, crtc);
7011 mode->hdisplay = (htot & 0xffff) + 1;
7012 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7013 mode->hsync_start = (hsync & 0xffff) + 1;
7014 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7015 mode->vdisplay = (vtot & 0xffff) + 1;
7016 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7017 mode->vsync_start = (vsync & 0xffff) + 1;
7018 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7019
7020 drm_mode_set_name(mode);
79e53945
JB		 7021
7022 return mode;
7023}
7024
3dec0095 7025static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7026{
7027 struct drm_device *dev = crtc->dev;
7028 drm_i915_private_t *dev_priv = dev->dev_private;
7029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7030 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7031 int dpll_reg = DPLL(pipe);
7032 int dpll;
652c393a 7033
bad720ff 7034 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7035 return;
7036
7037 if (!dev_priv->lvds_downclock_avail)
7038 return;
7039
dbdc6479 7040 dpll = I915_READ(dpll_reg);
652c393a 7041 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7042 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7043
8ac5a6d5 7044 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7045
7046 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7047 I915_WRITE(dpll_reg, dpll);
9d0498a2 7048 intel_wait_for_vblank(dev, pipe);
dbdc6479 7049
652c393a
JB		 7050 dpll = I915_READ(dpll_reg);
7051 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7052 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7053 }
652c393a
JB		 7054}
7055
7056static void intel_decrease_pllclock(struct drm_crtc *crtc)
7057{
7058 struct drm_device *dev = crtc->dev;
7059 drm_i915_private_t *dev_priv = dev->dev_private;
7060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7061
bad720ff 7062 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7063 return;
7064
7065 if (!dev_priv->lvds_downclock_avail)
7066 return;
7067
7068 /*
7069 * Since this is called by a timer, we should never get here in
7070 * the manual case.
7071 */
7072 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7073 int pipe = intel_crtc->pipe;
7074 int dpll_reg = DPLL(pipe);
7075 int dpll;
f6e5b160 7076
44d98a61 7077 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7078
8ac5a6d5 7079 assert_panel_unlocked(dev_priv, pipe);
652c393a 7080
dc257cf1 7081 dpll = I915_READ(dpll_reg);
652c393a
JB		 7082 dpll |= DISPLAY_RATE_SELECT_FPA1;
7083 I915_WRITE(dpll_reg, dpll);
9d0498a2 7084 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7085 dpll = I915_READ(dpll_reg);
7086 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7087 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7088 }
7089
7090}
7091
f047e395
CW		 7092void intel_mark_busy(struct drm_device *dev)
7093{
f047e395
CW		 7094 i915_update_gfx_val(dev->dev_private);
7095}
7096
7097void intel_mark_idle(struct drm_device *dev)
652c393a 7098{
652c393a 7099 struct drm_crtc *crtc;
652c393a
JB		 7100
7101 if (!i915_powersave)
7102 return;
7103
652c393a 7104 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7105 if (!crtc->fb)
7106 continue;
7107
725a5b54 7108 intel_decrease_pllclock(crtc);
652c393a 7109 }
652c393a
JB		 7110}
7111
725a5b54 7112void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7113{
f047e395
CW		 7114 struct drm_device *dev = obj->base.dev;
7115 struct drm_crtc *crtc;
652c393a 7116
f047e395 7117 if (!i915_powersave)
acb87dfb
CW		 7118 return;
7119
652c393a
JB		 7120 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7121 if (!crtc->fb)
7122 continue;
7123
f047e395 7124 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7125 intel_increase_pllclock(crtc);
652c393a
JB		 7126 }
7127}
7128
79e53945
JB		 7129static void intel_crtc_destroy(struct drm_crtc *crtc)
7130{
7131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7132 struct drm_device *dev = crtc->dev;
7133 struct intel_unpin_work *work;
7134 unsigned long flags;
7135
7136 spin_lock_irqsave(&dev->event_lock, flags);
7137 work = intel_crtc->unpin_work;
7138 intel_crtc->unpin_work = NULL;
7139 spin_unlock_irqrestore(&dev->event_lock, flags);
7140
7141 if (work) {
7142 cancel_work_sync(&work->work);
7143 kfree(work);
7144 }
79e53945 7145
40ccc72b
MK		 7146 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7147
79e53945 7148 drm_crtc_cleanup(crtc);
67e77c5a 7149
79e53945
JB		 7150 kfree(intel_crtc);
7151}
7152
6b95a207
KH		 7153static void intel_unpin_work_fn(struct work_struct *__work)
7154{
7155 struct intel_unpin_work *work =
7156 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7157 struct drm_device *dev = work->crtc->dev;
6b95a207 7158
b4a98e57 7159 mutex_lock(&dev->struct_mutex);
1690e1eb 7160 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7161 drm_gem_object_unreference(&work->pending_flip_obj->base);
7162 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7163
b4a98e57
CW		 7164 intel_update_fbc(dev);
7165 mutex_unlock(&dev->struct_mutex);
7166
7167 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7168 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7169
6b95a207
KH		 7170 kfree(work);
7171}
7172
1afe3e9d 7173static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7174 struct drm_crtc *crtc)
6b95a207
KH		 7175{
7176 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7178 struct intel_unpin_work *work;
6b95a207
KH		 7179 unsigned long flags;
7180
7181 /* Ignore early vblank irqs */
7182 if (intel_crtc == NULL)
7183 return;
7184
7185 spin_lock_irqsave(&dev->event_lock, flags);
7186 work = intel_crtc->unpin_work;
e7d841ca
CW		 7187
7188 /* Ensure we don't miss a work->pending update ... */
7189 smp_rmb();
7190
7191 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7192 spin_unlock_irqrestore(&dev->event_lock, flags);
7193 return;
7194 }
7195
e7d841ca
CW		 7196 /* and that the unpin work is consistent wrt ->pending. */
7197 smp_rmb();
7198
6b95a207 7199 intel_crtc->unpin_work = NULL;
6b95a207 7200
45a066eb
RC		 7201 if (work->event)
7202 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7203
0af7e4df
MK		 7204 drm_vblank_put(dev, intel_crtc->pipe);
7205
6b95a207
KH		 7206 spin_unlock_irqrestore(&dev->event_lock, flags);
7207
2c10d571 7208 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7209
7210 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7211
7212 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7213}
7214
1afe3e9d
JB		 7215void intel_finish_page_flip(struct drm_device *dev, int pipe)
7216{
7217 drm_i915_private_t *dev_priv = dev->dev_private;
7218 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7219
49b14a5c 7220 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7221}
7222
7223void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7224{
7225 drm_i915_private_t *dev_priv = dev->dev_private;
7226 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7227
49b14a5c 7228 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7229}
7230
6b95a207
KH		 7231void intel_prepare_page_flip(struct drm_device *dev, int plane)
7232{
7233 drm_i915_private_t *dev_priv = dev->dev_private;
7234 struct intel_crtc *intel_crtc =
7235 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7236 unsigned long flags;
7237
e7d841ca
CW		 7238 /* NB: An MMIO update of the plane base pointer will also
7239 * generate a page-flip completion irq, i.e. every modeset
7240 * is also accompanied by a spurious intel_prepare_page_flip().
7241 */
6b95a207 7242 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7243 if (intel_crtc->unpin_work)
7244 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7245 spin_unlock_irqrestore(&dev->event_lock, flags);
7246}
7247
e7d841ca
CW		 7248inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7249{
7250 /* Ensure that the work item is consistent when activating it ... */
7251 smp_wmb();
7252 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7253 /* and that it is marked active as soon as the irq could fire. */
7254 smp_wmb();
7255}
7256
8c9f3aaf
JB		 7257static int intel_gen2_queue_flip(struct drm_device *dev,
7258 struct drm_crtc *crtc,
7259 struct drm_framebuffer *fb,
7260 struct drm_i915_gem_object *obj)
7261{
7262 struct drm_i915_private *dev_priv = dev->dev_private;
7263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7264 u32 flip_mask;
6d90c952 7265 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7266 int ret;
7267
6d90c952 7268 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7269 if (ret)
83d4092b 7270 goto err;
8c9f3aaf 7271
6d90c952 7272 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7273 if (ret)
83d4092b 7274 goto err_unpin;
8c9f3aaf
JB		 7275
7276 /* Can't queue multiple flips, so wait for the previous
7277 * one to finish before executing the next.
7278 */
7279 if (intel_crtc->plane)
7280 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7281 else
7282 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7283 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7284 intel_ring_emit(ring, MI_NOOP);
7285 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7286 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7287 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7288 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7289 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7290
7291 intel_mark_page_flip_active(intel_crtc);
6d90c952 7292 intel_ring_advance(ring);
83d4092b
CW		 7293 return 0;
7294
7295err_unpin:
7296 intel_unpin_fb_obj(obj);
7297err:
8c9f3aaf
JB		 7298 return ret;
7299}
7300
7301static int intel_gen3_queue_flip(struct drm_device *dev,
7302 struct drm_crtc *crtc,
7303 struct drm_framebuffer *fb,
7304 struct drm_i915_gem_object *obj)
7305{
7306 struct drm_i915_private *dev_priv = dev->dev_private;
7307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7308 u32 flip_mask;
6d90c952 7309 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7310 int ret;
7311
6d90c952 7312 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7313 if (ret)
83d4092b 7314 goto err;
8c9f3aaf 7315
6d90c952 7316 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7317 if (ret)
83d4092b 7318 goto err_unpin;
8c9f3aaf
JB		 7319
7320 if (intel_crtc->plane)
7321 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7322 else
7323 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7324 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7325 intel_ring_emit(ring, MI_NOOP);
7326 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7327 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7328 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7329 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7330 intel_ring_emit(ring, MI_NOOP);
7331
e7d841ca 7332 intel_mark_page_flip_active(intel_crtc);
6d90c952 7333 intel_ring_advance(ring);
83d4092b
CW		 7334 return 0;
7335
7336err_unpin:
7337 intel_unpin_fb_obj(obj);
7338err:
8c9f3aaf
JB		 7339 return ret;
7340}
7341
7342static int intel_gen4_queue_flip(struct drm_device *dev,
7343 struct drm_crtc *crtc,
7344 struct drm_framebuffer *fb,
7345 struct drm_i915_gem_object *obj)
7346{
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7349 uint32_t pf, pipesrc;
6d90c952 7350 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7351 int ret;
7352
6d90c952 7353 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7354 if (ret)
83d4092b 7355 goto err;
8c9f3aaf 7356
6d90c952 7357 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7358 if (ret)
83d4092b 7359 goto err_unpin;
8c9f3aaf
JB		 7360
7361 /* i965+ uses the linear or tiled offsets from the
7362 * Display Registers (which do not change across a page-flip)
7363 * so we need only reprogram the base address.
7364 */
6d90c952
DV		 7365 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7367 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7368 intel_ring_emit(ring,
7369 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7370 obj->tiling_mode);
8c9f3aaf
JB		 7371
7372 /* XXX Enabling the panel-fitter across page-flip is so far
7373 * untested on non-native modes, so ignore it for now.
7374 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7375 */
7376 pf = 0;
7377 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7378 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7379
7380 intel_mark_page_flip_active(intel_crtc);
6d90c952 7381 intel_ring_advance(ring);
83d4092b
CW		 7382 return 0;
7383
7384err_unpin:
7385 intel_unpin_fb_obj(obj);
7386err:
8c9f3aaf
JB		 7387 return ret;
7388}
7389
7390static int intel_gen6_queue_flip(struct drm_device *dev,
7391 struct drm_crtc *crtc,
7392 struct drm_framebuffer *fb,
7393 struct drm_i915_gem_object *obj)
7394{
7395 struct drm_i915_private *dev_priv = dev->dev_private;
7396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7397 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7398 uint32_t pf, pipesrc;
7399 int ret;
7400
6d90c952 7401 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7402 if (ret)
83d4092b 7403 goto err;
8c9f3aaf 7404
6d90c952 7405 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7406 if (ret)
83d4092b 7407 goto err_unpin;
8c9f3aaf 7408
6d90c952
DV		 7409 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7410 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7411 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7412 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7413
dc257cf1
DV		 7414 /* Contrary to the suggestions in the documentation,
7415 * "Enable Panel Fitter" does not seem to be required when page
7416 * flipping with a non-native mode, and worse causes a normal
7417 * modeset to fail.
7418 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7419 */
7420 pf = 0;
8c9f3aaf 7421 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7422 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7423
7424 intel_mark_page_flip_active(intel_crtc);
6d90c952 7425 intel_ring_advance(ring);
83d4092b
CW		 7426 return 0;
7427
7428err_unpin:
7429 intel_unpin_fb_obj(obj);
7430err:
8c9f3aaf
JB		 7431 return ret;
7432}
7433
7c9017e5
JB		 7434/*
7435 * On gen7 we currently use the blit ring because (in early silicon at least)
7436 * the render ring doesn't give us interrpts for page flip completion, which
7437 * means clients will hang after the first flip is queued. Fortunately the
7438 * blit ring generates interrupts properly, so use it instead.
7439 */
7440static int intel_gen7_queue_flip(struct drm_device *dev,
7441 struct drm_crtc *crtc,
7442 struct drm_framebuffer *fb,
7443 struct drm_i915_gem_object *obj)
7444{
7445 struct drm_i915_private *dev_priv = dev->dev_private;
7446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7448 uint32_t plane_bit = 0;
7c9017e5
JB		 7449 int ret;
7450
7451 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7452 if (ret)
83d4092b 7453 goto err;
7c9017e5 7454
cb05d8de
DV		 7455 switch(intel_crtc->plane) {
7456 case PLANE_A:
7457 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7458 break;
7459 case PLANE_B:
7460 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7461 break;
7462 case PLANE_C:
7463 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7464 break;
7465 default:
7466 WARN_ONCE(1, "unknown plane in flip command\n");
7467 ret = -ENODEV;
ab3951eb 7468 goto err_unpin;
cb05d8de
DV		 7469 }
7470
7c9017e5
JB		 7471 ret = intel_ring_begin(ring, 4);
7472 if (ret)
83d4092b 7473 goto err_unpin;
7c9017e5 7474
cb05d8de 7475 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7476 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7477 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7478 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7479
7480 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7481 intel_ring_advance(ring);
83d4092b
CW		 7482 return 0;
7483
7484err_unpin:
7485 intel_unpin_fb_obj(obj);
7486err:
7c9017e5
JB		 7487 return ret;
7488}
7489
8c9f3aaf
JB		 7490static int intel_default_queue_flip(struct drm_device *dev,
7491 struct drm_crtc *crtc,
7492 struct drm_framebuffer *fb,
7493 struct drm_i915_gem_object *obj)
7494{
7495 return -ENODEV;
7496}
7497
6b95a207
KH		 7498static int intel_crtc_page_flip(struct drm_crtc *crtc,
7499 struct drm_framebuffer *fb,
7500 struct drm_pending_vblank_event *event)
7501{
7502 struct drm_device *dev = crtc->dev;
7503 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7504 struct drm_framebuffer *old_fb = crtc->fb;
7505 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7507 struct intel_unpin_work *work;
8c9f3aaf 7508 unsigned long flags;
52e68630 7509 int ret;
6b95a207 7510
e6a595d2
VS		 7511 /* Can't change pixel format via MI display flips. */
7512 if (fb->pixel_format != crtc->fb->pixel_format)
7513 return -EINVAL;
7514
7515 /*
7516 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7517 * Note that pitch changes could also affect these register.
7518 */
7519 if (INTEL_INFO(dev)->gen > 3 &&
7520 (fb->offsets[0] != crtc->fb->offsets[0] ||
7521 fb->pitches[0] != crtc->fb->pitches[0]))
7522 return -EINVAL;
7523
6b95a207
KH		 7524 work = kzalloc(sizeof *work, GFP_KERNEL);
7525 if (work == NULL)
7526 return -ENOMEM;
7527
6b95a207 7528 work->event = event;
b4a98e57 7529 work->crtc = crtc;
4a35f83b 7530 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7531 INIT_WORK(&work->work, intel_unpin_work_fn);
7532
7317c75e
JB		 7533 ret = drm_vblank_get(dev, intel_crtc->pipe);
7534 if (ret)
7535 goto free_work;
7536
6b95a207
KH		 7537 /* We borrow the event spin lock for protecting unpin_work */
7538 spin_lock_irqsave(&dev->event_lock, flags);
7539 if (intel_crtc->unpin_work) {
7540 spin_unlock_irqrestore(&dev->event_lock, flags);
7541 kfree(work);
7317c75e 7542 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7543
7544 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7545 return -EBUSY;
7546 }
7547 intel_crtc->unpin_work = work;
7548 spin_unlock_irqrestore(&dev->event_lock, flags);
7549
b4a98e57
CW		 7550 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7551 flush_workqueue(dev_priv->wq);
7552
79158103
CW		 7553 ret = i915_mutex_lock_interruptible(dev);
7554 if (ret)
7555 goto cleanup;
6b95a207 7556
75dfca80 7557 /* Reference the objects for the scheduled work. */
05394f39
CW		 7558 drm_gem_object_reference(&work->old_fb_obj->base);
7559 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7560
7561 crtc->fb = fb;
96b099fd 7562
e1f99ce6 7563 work->pending_flip_obj = obj;
e1f99ce6 7564
4e5359cd
SF		 7565 work->enable_stall_check = true;
7566
b4a98e57 7567 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7568 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7569
8c9f3aaf
JB		 7570 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7571 if (ret)
7572 goto cleanup_pending;
6b95a207 7573
7782de3b 7574 intel_disable_fbc(dev);
f047e395 7575 intel_mark_fb_busy(obj);
6b95a207
KH		 7576 mutex_unlock(&dev->struct_mutex);
7577
e5510fac
JB		 7578 trace_i915_flip_request(intel_crtc->plane, obj);
7579
6b95a207 7580 return 0;
96b099fd 7581
8c9f3aaf 7582cleanup_pending:
b4a98e57 7583 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7584 crtc->fb = old_fb;
05394f39
CW		 7585 drm_gem_object_unreference(&work->old_fb_obj->base);
7586 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7587 mutex_unlock(&dev->struct_mutex);
7588
79158103 7589cleanup:
96b099fd
CW		 7590 spin_lock_irqsave(&dev->event_lock, flags);
7591 intel_crtc->unpin_work = NULL;
7592 spin_unlock_irqrestore(&dev->event_lock, flags);
7593
7317c75e
JB		 7594 drm_vblank_put(dev, intel_crtc->pipe);
7595free_work:
96b099fd
CW		 7596 kfree(work);
7597
7598 return ret;
6b95a207
KH		 7599}
7600
f6e5b160 7601static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7602 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7603 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7604};
7605
50f56119
DV		 7606static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7607 struct drm_crtc *crtc)
7608{
7609 struct drm_device *dev;
7610 struct drm_crtc *tmp;
7611 int crtc_mask = 1;
47f1c6c9 7612
50f56119 7613 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7614
50f56119 7615 dev = crtc->dev;
47f1c6c9 7616
50f56119
DV		 7617 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7618 if (tmp == crtc)
7619 break;
7620 crtc_mask <<= 1;
7621 }
47f1c6c9 7622
50f56119
DV		 7623 if (encoder->possible_crtcs & crtc_mask)
7624 return true;
7625 return false;
47f1c6c9 7626}
79e53945 7627
9a935856
DV		 7628/**
7629 * intel_modeset_update_staged_output_state
7630 *
7631 * Updates the staged output configuration state, e.g. after we've read out the
7632 * current hw state.
7633 */
7634static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7635{
9a935856
DV		 7636 struct intel_encoder *encoder;
7637 struct intel_connector *connector;
f6e5b160 7638
9a935856
DV		 7639 list_for_each_entry(connector, &dev->mode_config.connector_list,
7640 base.head) {
7641 connector->new_encoder =
7642 to_intel_encoder(connector->base.encoder);
7643 }
f6e5b160 7644
9a935856
DV		 7645 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7646 base.head) {
7647 encoder->new_crtc =
7648 to_intel_crtc(encoder->base.crtc);
7649 }
f6e5b160
CW		 7650}
7651
9a935856
DV		 7652/**
7653 * intel_modeset_commit_output_state
7654 *
7655 * This function copies the stage display pipe configuration to the real one.
7656 */
7657static void intel_modeset_commit_output_state(struct drm_device *dev)
7658{
7659 struct intel_encoder *encoder;
7660 struct intel_connector *connector;
f6e5b160 7661
9a935856
DV		 7662 list_for_each_entry(connector, &dev->mode_config.connector_list,
7663 base.head) {
7664 connector->base.encoder = &connector->new_encoder->base;
7665 }
f6e5b160 7666
9a935856
DV		 7667 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7668 base.head) {
7669 encoder->base.crtc = &encoder->new_crtc->base;
7670 }
7671}
7672
050f7aeb
DV		 7673static void
7674connected_sink_compute_bpp(struct intel_connector * connector,
7675 struct intel_crtc_config *pipe_config)
7676{
7677 int bpp = pipe_config->pipe_bpp;
7678
7679 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7680 connector->base.base.id,
7681 drm_get_connector_name(&connector->base));
7682
7683 /* Don't use an invalid EDID bpc value */
7684 if (connector->base.display_info.bpc &&
7685 connector->base.display_info.bpc * 3 < bpp) {
7686 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7687 bpp, connector->base.display_info.bpc*3);
7688 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7689 }
7690
7691 /* Clamp bpp to 8 on screens without EDID 1.4 */
7692 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7693 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7694 bpp);
7695 pipe_config->pipe_bpp = 24;
7696 }
7697}
7698
4e53c2e0 7699static int
050f7aeb
DV		 7700compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7701 struct drm_framebuffer *fb,
7702 struct intel_crtc_config *pipe_config)
4e53c2e0 7703{
050f7aeb
DV		 7704 struct drm_device *dev = crtc->base.dev;
7705 struct intel_connector *connector;
4e53c2e0
DV		 7706 int bpp;
7707
d42264b1
DV		 7708 switch (fb->pixel_format) {
7709 case DRM_FORMAT_C8:
4e53c2e0
DV		 7710 bpp = 8*3; /* since we go through a colormap */
7711 break;
d42264b1
DV		 7712 case DRM_FORMAT_XRGB1555:
7713 case DRM_FORMAT_ARGB1555:
7714 /* checked in intel_framebuffer_init already */
7715 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7716 return -EINVAL;
7717 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7718 bpp = 6*3; /* min is 18bpp */
7719 break;
d42264b1
DV		 7720 case DRM_FORMAT_XBGR8888:
7721 case DRM_FORMAT_ABGR8888:
7722 /* checked in intel_framebuffer_init already */
7723 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7724 return -EINVAL;
7725 case DRM_FORMAT_XRGB8888:
7726 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7727 bpp = 8*3;
7728 break;
d42264b1
DV		 7729 case DRM_FORMAT_XRGB2101010:
7730 case DRM_FORMAT_ARGB2101010:
7731 case DRM_FORMAT_XBGR2101010:
7732 case DRM_FORMAT_ABGR2101010:
7733 /* checked in intel_framebuffer_init already */
7734 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7735 return -EINVAL;
4e53c2e0
DV		 7736 bpp = 10*3;
7737 break;
baba133a 7738 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7739 default:
7740 DRM_DEBUG_KMS("unsupported depth\n");
7741 return -EINVAL;
7742 }
7743
4e53c2e0
DV		 7744 pipe_config->pipe_bpp = bpp;
7745
7746 /* Clamp display bpp to EDID value */
7747 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7748 base.head) {
1b829e05
DV		 7749 if (!connector->new_encoder ||
7750 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7751 continue;
7752
050f7aeb 7753 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7754 }
7755
7756 return bpp;
7757}
7758
c0b03411
DV		 7759static void intel_dump_pipe_config(struct intel_crtc *crtc,
7760 struct intel_crtc_config *pipe_config,
7761 const char *context)
7762{
7763 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7764 context, pipe_name(crtc->pipe));
7765
7766 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7767 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7768 pipe_config->pipe_bpp, pipe_config->dither);
7769 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7770 pipe_config->has_pch_encoder,
7771 pipe_config->fdi_lanes,
7772 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7773 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7774 pipe_config->fdi_m_n.tu);
7775 DRM_DEBUG_KMS("requested mode:\n");
7776 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7777 DRM_DEBUG_KMS("adjusted mode:\n");
7778 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7779 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7780 pipe_config->gmch_pfit.control,
7781 pipe_config->gmch_pfit.pgm_ratios,
7782 pipe_config->gmch_pfit.lvds_border_bits);
7783 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7784 pipe_config->pch_pfit.pos,
7785 pipe_config->pch_pfit.size);
42db64ef 7786 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7787}
7788
accfc0c5
DV		 7789static bool check_encoder_cloning(struct drm_crtc *crtc)
7790{
7791 int num_encoders = 0;
7792 bool uncloneable_encoders = false;
7793 struct intel_encoder *encoder;
7794
7795 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7796 base.head) {
7797 if (&encoder->new_crtc->base != crtc)
7798 continue;
7799
7800 num_encoders++;
7801 if (!encoder->cloneable)
7802 uncloneable_encoders = true;
7803 }
7804
7805 return !(num_encoders > 1 && uncloneable_encoders);
7806}
7807
b8cecdf5
DV		 7808static struct intel_crtc_config *
7809intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7810 struct drm_framebuffer *fb,
b8cecdf5 7811 struct drm_display_mode *mode)
ee7b9f93 7812{
7758a113 7813 struct drm_device *dev = crtc->dev;
7758a113
DV		 7814 struct drm_encoder_helper_funcs *encoder_funcs;
7815 struct intel_encoder *encoder;
b8cecdf5 7816 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7817 int plane_bpp, ret = -EINVAL;
7818 bool retry = true;
ee7b9f93 7819
accfc0c5
DV		 7820 if (!check_encoder_cloning(crtc)) {
7821 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7822 return ERR_PTR(-EINVAL);
7823 }
7824
b8cecdf5
DV		 7825 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7826 if (!pipe_config)
7758a113
DV		 7827 return ERR_PTR(-ENOMEM);
7828
b8cecdf5
DV		 7829 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7830 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7831 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7832
050f7aeb
DV		 7833 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7834 * plane pixel format and any sink constraints into account. Returns the
7835 * source plane bpp so that dithering can be selected on mismatches
7836 * after encoders and crtc also have had their say. */
7837 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7838 fb, pipe_config);
4e53c2e0
DV		 7839 if (plane_bpp < 0)
7840 goto fail;
7841
e29c22c0 7842encoder_retry:
ef1b460d 7843 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7844 pipe_config->port_clock = 0;
ef1b460d 7845 pipe_config->pixel_multiplier = 1;
ff9a6750 7846
7758a113
DV		 7847 /* Pass our mode to the connectors and the CRTC to give them a chance to
7848 * adjust it according to limitations or connector properties, and also
7849 * a chance to reject the mode entirely.
47f1c6c9 7850 */
7758a113
DV		 7851 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7852 base.head) {
47f1c6c9 7853
7758a113
DV		 7854 if (&encoder->new_crtc->base != crtc)
7855 continue;
7ae89233
DV		 7856
7857 if (encoder->compute_config) {
7858 if (!(encoder->compute_config(encoder, pipe_config))) {
7859 DRM_DEBUG_KMS("Encoder config failure\n");
7860 goto fail;
7861 }
7862
7863 continue;
7864 }
7865
7758a113 7866 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7867 if (!(encoder_funcs->mode_fixup(&encoder->base,
7868 &pipe_config->requested_mode,
7869 &pipe_config->adjusted_mode))) {
7758a113
DV		 7870 DRM_DEBUG_KMS("Encoder fixup failed\n");
7871 goto fail;
7872 }
ee7b9f93 7873 }
47f1c6c9 7874
ff9a6750
DV		 7875 /* Set default port clock if not overwritten by the encoder. Needs to be
7876 * done afterwards in case the encoder adjusts the mode. */
7877 if (!pipe_config->port_clock)
7878 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7879
e29c22c0
DV		 7880 ret = intel_crtc_compute_config(crtc, pipe_config);
7881 if (ret < 0) {
7758a113
DV		 7882 DRM_DEBUG_KMS("CRTC fixup failed\n");
7883 goto fail;
ee7b9f93 7884 }
e29c22c0
DV		 7885
7886 if (ret == RETRY) {
7887 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7888 ret = -EINVAL;
7889 goto fail;
7890 }
7891
7892 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7893 retry = false;
7894 goto encoder_retry;
7895 }
7896
4e53c2e0
DV		 7897 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7898 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7899 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7900
b8cecdf5 7901 return pipe_config;
7758a113 7902fail:
b8cecdf5 7903 kfree(pipe_config);
e29c22c0 7904 return ERR_PTR(ret);
ee7b9f93 7905}
47f1c6c9 7906
e2e1ed41
DV		 7907/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7908 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7909static void
7910intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7911 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7912{
7913 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7914 struct drm_device *dev = crtc->dev;
7915 struct intel_encoder *encoder;
7916 struct intel_connector *connector;
7917 struct drm_crtc *tmp_crtc;
79e53945 7918
e2e1ed41 7919 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7920
e2e1ed41
DV		 7921 /* Check which crtcs have changed outputs connected to them, these need
7922 * to be part of the prepare_pipes mask. We don't (yet) support global
7923 * modeset across multiple crtcs, so modeset_pipes will only have one
7924 * bit set at most. */
7925 list_for_each_entry(connector, &dev->mode_config.connector_list,
7926 base.head) {
7927 if (connector->base.encoder == &connector->new_encoder->base)
7928 continue;
79e53945 7929
e2e1ed41
DV		 7930 if (connector->base.encoder) {
7931 tmp_crtc = connector->base.encoder->crtc;
7932
7933 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7934 }
7935
7936 if (connector->new_encoder)
7937 *prepare_pipes |=
7938 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7939 }
7940
e2e1ed41
DV		 7941 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7942 base.head) {
7943 if (encoder->base.crtc == &encoder->new_crtc->base)
7944 continue;
7945
7946 if (encoder->base.crtc) {
7947 tmp_crtc = encoder->base.crtc;
7948
7949 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7950 }
7951
7952 if (encoder->new_crtc)
7953 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7954 }
7955
e2e1ed41
DV		 7956 /* Check for any pipes that will be fully disabled ... */
7957 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7958 base.head) {
7959 bool used = false;
22fd0fab 7960
e2e1ed41
DV		 7961 /* Don't try to disable disabled crtcs. */
7962 if (!intel_crtc->base.enabled)
7963 continue;
7e7d76c3 7964
e2e1ed41
DV		 7965 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7966 base.head) {
7967 if (encoder->new_crtc == intel_crtc)
7968 used = true;
7969 }
7970
7971 if (!used)
7972 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7973 }
7974
e2e1ed41
DV		 7975
7976 /* set_mode is also used to update properties on life display pipes. */
7977 intel_crtc = to_intel_crtc(crtc);
7978 if (crtc->enabled)
7979 *prepare_pipes |= 1 << intel_crtc->pipe;
7980
b6c5164d
DV		 7981 /*
7982 * For simplicity do a full modeset on any pipe where the output routing
7983 * changed. We could be more clever, but that would require us to be
7984 * more careful with calling the relevant encoder->mode_set functions.
7985 */
e2e1ed41
DV		 7986 if (*prepare_pipes)
7987 *modeset_pipes = *prepare_pipes;
7988
7989 /* ... and mask these out. */
7990 *modeset_pipes &= ~(*disable_pipes);
7991 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7992
7993 /*
7994 * HACK: We don't (yet) fully support global modesets. intel_set_config
7995 * obies this rule, but the modeset restore mode of
7996 * intel_modeset_setup_hw_state does not.
7997 */
7998 *modeset_pipes &= 1 << intel_crtc->pipe;
7999 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8000
8001 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8002 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8003}
79e53945 8004
ea9d758d 8005static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8006{
ea9d758d 8007 struct drm_encoder *encoder;
f6e5b160 8008 struct drm_device *dev = crtc->dev;
f6e5b160 8009
ea9d758d
DV		 8010 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8011 if (encoder->crtc == crtc)
8012 return true;
8013
8014 return false;
8015}
8016
8017static void
8018intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8019{
8020 struct intel_encoder *intel_encoder;
8021 struct intel_crtc *intel_crtc;
8022 struct drm_connector *connector;
8023
8024 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8025 base.head) {
8026 if (!intel_encoder->base.crtc)
8027 continue;
8028
8029 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8030
8031 if (prepare_pipes & (1 << intel_crtc->pipe))
8032 intel_encoder->connectors_active = false;
8033 }
8034
8035 intel_modeset_commit_output_state(dev);
8036
8037 /* Update computed state. */
8038 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8039 base.head) {
8040 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8041 }
8042
8043 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8044 if (!connector->encoder || !connector->encoder->crtc)
8045 continue;
8046
8047 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8048
8049 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8050 struct drm_property *dpms_property =
8051 dev->mode_config.dpms_property;
8052
ea9d758d 8053 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8054 drm_object_property_set_value(&connector->base,
68d34720
DV		 8055 dpms_property,
8056 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8057
8058 intel_encoder = to_intel_encoder(connector->encoder);
8059 intel_encoder->connectors_active = true;
8060 }
8061 }
8062
8063}
8064
25c5b266
DV		 8065#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8066 list_for_each_entry((intel_crtc), \
8067 &(dev)->mode_config.crtc_list, \
8068 base.head) \
0973f18f 8069 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8070
0e8ffe1b 8071static bool
2fa2fe9a
DV		 8072intel_pipe_config_compare(struct drm_device *dev,
8073 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8074 struct intel_crtc_config *pipe_config)
8075{
08a24034
DV		 8076#define PIPE_CONF_CHECK_I(name) \
8077 if (current_config->name != pipe_config->name) { \
8078 DRM_ERROR("mismatch in " #name " " \
8079 "(expected %i, found %i)\n", \
8080 current_config->name, \
8081 pipe_config->name); \
8082 return false; \
88adfff1
DV		 8083 }
8084
1bd1bd80
DV		 8085#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8086 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8087 DRM_ERROR("mismatch in " #name " " \
8088 "(expected %i, found %i)\n", \
8089 current_config->name & (mask), \
8090 pipe_config->name & (mask)); \
8091 return false; \
8092 }
8093
bb760063
DV		 8094#define PIPE_CONF_QUIRK(quirk) \
8095 ((current_config->quirks | pipe_config->quirks) & (quirk))
8096
eccb140b
DV		 8097 PIPE_CONF_CHECK_I(cpu_transcoder);
8098
08a24034
DV		 8099 PIPE_CONF_CHECK_I(has_pch_encoder);
8100 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8101 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8102 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8103 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8104 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8105 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8106
1bd1bd80
DV		 8107 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8108 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8109 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8110 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8111 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8112 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8113
8114 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8115 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8116 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8117 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8118 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8119 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8120
6c49f241
DV		 8121 if (!HAS_PCH_SPLIT(dev))
8122 PIPE_CONF_CHECK_I(pixel_multiplier);
8123
1bd1bd80
DV		 8124 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8125 DRM_MODE_FLAG_INTERLACE);
8126
bb760063
DV		 8127 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8128 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8129 DRM_MODE_FLAG_PHSYNC);
8130 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8131 DRM_MODE_FLAG_NHSYNC);
8132 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8133 DRM_MODE_FLAG_PVSYNC);
8134 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8135 DRM_MODE_FLAG_NVSYNC);
8136 }
045ac3b5 8137
1bd1bd80
DV		 8138 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8139 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8140
2fa2fe9a
DV		 8141 PIPE_CONF_CHECK_I(gmch_pfit.control);
8142 /* pfit ratios are autocomputed by the hw on gen4+ */
8143 if (INTEL_INFO(dev)->gen < 4)
8144 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8145 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8146 PIPE_CONF_CHECK_I(pch_pfit.pos);
8147 PIPE_CONF_CHECK_I(pch_pfit.size);
8148
42db64ef
PZ		 8149 PIPE_CONF_CHECK_I(ips_enabled);
8150
08a24034 8151#undef PIPE_CONF_CHECK_I
1bd1bd80 8152#undef PIPE_CONF_CHECK_FLAGS
bb760063 8153#undef PIPE_CONF_QUIRK
627eb5a3 8154
0e8ffe1b
DV		 8155 return true;
8156}
8157
b980514c 8158void
8af6cf88
DV		 8159intel_modeset_check_state(struct drm_device *dev)
8160{
0e8ffe1b 8161 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8162 struct intel_crtc *crtc;
8163 struct intel_encoder *encoder;
8164 struct intel_connector *connector;
0e8ffe1b 8165 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8166
8167 list_for_each_entry(connector, &dev->mode_config.connector_list,
8168 base.head) {
8169 /* This also checks the encoder/connector hw state with the
8170 * ->get_hw_state callbacks. */
8171 intel_connector_check_state(connector);
8172
8173 WARN(&connector->new_encoder->base != connector->base.encoder,
8174 "connector's staged encoder doesn't match current encoder\n");
8175 }
8176
8177 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8178 base.head) {
8179 bool enabled = false;
8180 bool active = false;
8181 enum pipe pipe, tracked_pipe;
8182
8183 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8184 encoder->base.base.id,
8185 drm_get_encoder_name(&encoder->base));
8186
8187 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8188 "encoder's stage crtc doesn't match current crtc\n");
8189 WARN(encoder->connectors_active && !encoder->base.crtc,
8190 "encoder's active_connectors set, but no crtc\n");
8191
8192 list_for_each_entry(connector, &dev->mode_config.connector_list,
8193 base.head) {
8194 if (connector->base.encoder != &encoder->base)
8195 continue;
8196 enabled = true;
8197 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8198 active = true;
8199 }
8200 WARN(!!encoder->base.crtc != enabled,
8201 "encoder's enabled state mismatch "
8202 "(expected %i, found %i)\n",
8203 !!encoder->base.crtc, enabled);
8204 WARN(active && !encoder->base.crtc,
8205 "active encoder with no crtc\n");
8206
8207 WARN(encoder->connectors_active != active,
8208 "encoder's computed active state doesn't match tracked active state "
8209 "(expected %i, found %i)\n", active, encoder->connectors_active);
8210
8211 active = encoder->get_hw_state(encoder, &pipe);
8212 WARN(active != encoder->connectors_active,
8213 "encoder's hw state doesn't match sw tracking "
8214 "(expected %i, found %i)\n",
8215 encoder->connectors_active, active);
8216
8217 if (!encoder->base.crtc)
8218 continue;
8219
8220 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8221 WARN(active && pipe != tracked_pipe,
8222 "active encoder's pipe doesn't match"
8223 "(expected %i, found %i)\n",
8224 tracked_pipe, pipe);
8225
8226 }
8227
8228 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8229 base.head) {
8230 bool enabled = false;
8231 bool active = false;
8232
045ac3b5
JB		 8233 memset(&pipe_config, 0, sizeof(pipe_config));
8234
8af6cf88
DV		 8235 DRM_DEBUG_KMS("[CRTC:%d]\n",
8236 crtc->base.base.id);
8237
8238 WARN(crtc->active && !crtc->base.enabled,
8239 "active crtc, but not enabled in sw tracking\n");
8240
8241 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8242 base.head) {
8243 if (encoder->base.crtc != &crtc->base)
8244 continue;
8245 enabled = true;
8246 if (encoder->connectors_active)
8247 active = true;
8248 }
6c49f241 8249
8af6cf88
DV		 8250 WARN(active != crtc->active,
8251 "crtc's computed active state doesn't match tracked active state "
8252 "(expected %i, found %i)\n", active, crtc->active);
8253 WARN(enabled != crtc->base.enabled,
8254 "crtc's computed enabled state doesn't match tracked enabled state "
8255 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8256
0e8ffe1b
DV		 8257 active = dev_priv->display.get_pipe_config(crtc,
8258 &pipe_config);
6c49f241
DV		 8259 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8260 base.head) {
8261 if (encoder->base.crtc != &crtc->base)
8262 continue;
8263 if (encoder->get_config)
8264 encoder->get_config(encoder, &pipe_config);
8265 }
8266
0e8ffe1b
DV		 8267 WARN(crtc->active != active,
8268 "crtc active state doesn't match with hw state "
8269 "(expected %i, found %i)\n", crtc->active, active);
8270
c0b03411
DV		 8271 if (active &&
8272 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8273 WARN(1, "pipe state doesn't match!\n");
8274 intel_dump_pipe_config(crtc, &pipe_config,
8275 "[hw state]");
8276 intel_dump_pipe_config(crtc, &crtc->config,
8277 "[sw state]");
8278 }
8af6cf88
DV		 8279 }
8280}
8281
f30da187
DV		 8282static int __intel_set_mode(struct drm_crtc *crtc,
8283 struct drm_display_mode *mode,
8284 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8285{
8286 struct drm_device *dev = crtc->dev;
dbf2b54e 8287 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8288 struct drm_display_mode *saved_mode, *saved_hwmode;
8289 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8290 struct intel_crtc *intel_crtc;
8291 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8292 int ret = 0;
a6778b3c 8293
3ac18232 8294 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8295 if (!saved_mode)
8296 return -ENOMEM;
3ac18232 8297 saved_hwmode = saved_mode + 1;
a6778b3c 8298
e2e1ed41 8299 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8300 &prepare_pipes, &disable_pipes);
8301
3ac18232
TG		 8302 *saved_hwmode = crtc->hwmode;
8303 *saved_mode = crtc->mode;
a6778b3c 8304
25c5b266
DV		 8305 /* Hack: Because we don't (yet) support global modeset on multiple
8306 * crtcs, we don't keep track of the new mode for more than one crtc.
8307 * Hence simply check whether any bit is set in modeset_pipes in all the
8308 * pieces of code that are not yet converted to deal with mutliple crtcs
8309 * changing their mode at the same time. */
25c5b266 8310 if (modeset_pipes) {
4e53c2e0 8311 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8312 if (IS_ERR(pipe_config)) {
8313 ret = PTR_ERR(pipe_config);
8314 pipe_config = NULL;
8315
3ac18232 8316 goto out;
25c5b266 8317 }
c0b03411
DV		 8318 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8319 "[modeset]");
25c5b266 8320 }
a6778b3c 8321
460da916
DV		 8322 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8323 intel_crtc_disable(&intel_crtc->base);
8324
ea9d758d
DV		 8325 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8326 if (intel_crtc->base.enabled)
8327 dev_priv->display.crtc_disable(&intel_crtc->base);
8328 }
a6778b3c 8329
6c4c86f5
DV		 8330 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8331 * to set it here already despite that we pass it down the callchain.
f6e5b160 8332 */
b8cecdf5 8333 if (modeset_pipes) {
25c5b266 8334 crtc->mode = *mode;
b8cecdf5
DV		 8335 /* mode_set/enable/disable functions rely on a correct pipe
8336 * config. */
8337 to_intel_crtc(crtc)->config = *pipe_config;
8338 }
7758a113 8339
ea9d758d
DV		 8340 /* Only after disabling all output pipelines that will be changed can we
8341 * update the the output configuration. */
8342 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8343
47fab737
DV		 8344 if (dev_priv->display.modeset_global_resources)
8345 dev_priv->display.modeset_global_resources(dev);
8346
a6778b3c
DV		 8347 /* Set up the DPLL and any encoders state that needs to adjust or depend
8348 * on the DPLL.
f6e5b160 8349 */
25c5b266 8350 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8351 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8352 x, y, fb);
8353 if (ret)
8354 goto done;
a6778b3c
DV		 8355 }
8356
8357 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8358 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8359 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8360
25c5b266
DV		 8361 if (modeset_pipes) {
8362 /* Store real post-adjustment hardware mode. */
b8cecdf5 8363 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8364
25c5b266
DV		 8365 /* Calculate and store various constants which
8366 * are later needed by vblank and swap-completion
8367 * timestamping. They are derived from true hwmode.
8368 */
8369 drm_calc_timestamping_constants(crtc);
8370 }
a6778b3c
DV		 8371
8372 /* FIXME: add subpixel order */
8373done:
c0c36b94 8374 if (ret && crtc->enabled) {
3ac18232
TG		 8375 crtc->hwmode = *saved_hwmode;
8376 crtc->mode = *saved_mode;
a6778b3c
DV		 8377 }
8378
3ac18232 8379out:
b8cecdf5 8380 kfree(pipe_config);
3ac18232 8381 kfree(saved_mode);
a6778b3c 8382 return ret;
f6e5b160
CW		 8383}
8384
f30da187
DV		 8385int intel_set_mode(struct drm_crtc *crtc,
8386 struct drm_display_mode *mode,
8387 int x, int y, struct drm_framebuffer *fb)
8388{
8389 int ret;
8390
8391 ret = __intel_set_mode(crtc, mode, x, y, fb);
8392
8393 if (ret == 0)
8394 intel_modeset_check_state(crtc->dev);
8395
8396 return ret;
8397}
8398
c0c36b94
CW		 8399void intel_crtc_restore_mode(struct drm_crtc *crtc)
8400{
8401 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8402}
8403
25c5b266
DV		 8404#undef for_each_intel_crtc_masked
8405
d9e55608
DV		 8406static void intel_set_config_free(struct intel_set_config *config)
8407{
8408 if (!config)
8409 return;
8410
1aa4b628
DV		 8411 kfree(config->save_connector_encoders);
8412 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8413 kfree(config);
8414}
8415
85f9eb71
DV		 8416static int intel_set_config_save_state(struct drm_device *dev,
8417 struct intel_set_config *config)
8418{
85f9eb71
DV		 8419 struct drm_encoder *encoder;
8420 struct drm_connector *connector;
8421 int count;
8422
1aa4b628
DV		 8423 config->save_encoder_crtcs =
8424 kcalloc(dev->mode_config.num_encoder,
8425 sizeof(struct drm_crtc *), GFP_KERNEL);
8426 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8427 return -ENOMEM;
8428
1aa4b628
DV		 8429 config->save_connector_encoders =
8430 kcalloc(dev->mode_config.num_connector,
8431 sizeof(struct drm_encoder *), GFP_KERNEL);
8432 if (!config->save_connector_encoders)
85f9eb71
DV		 8433 return -ENOMEM;
8434
8435 /* Copy data. Note that driver private data is not affected.
8436 * Should anything bad happen only the expected state is
8437 * restored, not the drivers personal bookkeeping.
8438 */
85f9eb71
DV		 8439 count = 0;
8440 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8441 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8442 }
8443
8444 count = 0;
8445 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8446 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8447 }
8448
8449 return 0;
8450}
8451
8452static void intel_set_config_restore_state(struct drm_device *dev,
8453 struct intel_set_config *config)
8454{
9a935856
DV		 8455 struct intel_encoder *encoder;
8456 struct intel_connector *connector;
85f9eb71
DV		 8457 int count;
8458
85f9eb71 8459 count = 0;
9a935856
DV		 8460 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8461 encoder->new_crtc =
8462 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8463 }
8464
8465 count = 0;
9a935856
DV		 8466 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8467 connector->new_encoder =
8468 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8469 }
8470}
8471
5e2b584e
DV		 8472static void
8473intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8474 struct intel_set_config *config)
8475{
8476
8477 /* We should be able to check here if the fb has the same properties
8478 * and then just flip_or_move it */
8479 if (set->crtc->fb != set->fb) {
8480 /* If we have no fb then treat it as a full mode set */
8481 if (set->crtc->fb == NULL) {
8482 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8483 config->mode_changed = true;
8484 } else if (set->fb == NULL) {
8485 config->mode_changed = true;
72f4901e
DV		 8486 } else if (set->fb->pixel_format !=
8487 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8488 config->mode_changed = true;
8489 } else
8490 config->fb_changed = true;
8491 }
8492
835c5873 8493 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8494 config->fb_changed = true;
8495
8496 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8497 DRM_DEBUG_KMS("modes are different, full mode set\n");
8498 drm_mode_debug_printmodeline(&set->crtc->mode);
8499 drm_mode_debug_printmodeline(set->mode);
8500 config->mode_changed = true;
8501 }
8502}
8503
2e431051 8504static int
9a935856
DV		 8505intel_modeset_stage_output_state(struct drm_device *dev,
8506 struct drm_mode_set *set,
8507 struct intel_set_config *config)
50f56119 8508{
85f9eb71 8509 struct drm_crtc *new_crtc;
9a935856
DV		 8510 struct intel_connector *connector;
8511 struct intel_encoder *encoder;
2e431051 8512 int count, ro;
50f56119 8513
9abdda74 8514 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8515 * of connectors. For paranoia, double-check this. */
8516 WARN_ON(!set->fb && (set->num_connectors != 0));
8517 WARN_ON(set->fb && (set->num_connectors == 0));
8518
50f56119 8519 count = 0;
9a935856
DV		 8520 list_for_each_entry(connector, &dev->mode_config.connector_list,
8521 base.head) {
8522 /* Otherwise traverse passed in connector list and get encoders
8523 * for them. */
50f56119 8524 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8525 if (set->connectors[ro] == &connector->base) {
8526 connector->new_encoder = connector->encoder;
50f56119
DV		 8527 break;
8528 }
8529 }
8530
9a935856
DV		 8531 /* If we disable the crtc, disable all its connectors. Also, if
8532 * the connector is on the changing crtc but not on the new
8533 * connector list, disable it. */
8534 if ((!set->fb || ro == set->num_connectors) &&
8535 connector->base.encoder &&
8536 connector->base.encoder->crtc == set->crtc) {
8537 connector->new_encoder = NULL;
8538
8539 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8540 connector->base.base.id,
8541 drm_get_connector_name(&connector->base));
8542 }
8543
8544
8545 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8546 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8547 config->mode_changed = true;
50f56119
DV		 8548 }
8549 }
9a935856 8550 /* connector->new_encoder is now updated for all connectors. */
50f56119 8551
9a935856 8552 /* Update crtc of enabled connectors. */
50f56119 8553 count = 0;
9a935856
DV		 8554 list_for_each_entry(connector, &dev->mode_config.connector_list,
8555 base.head) {
8556 if (!connector->new_encoder)
50f56119
DV		 8557 continue;
8558
9a935856 8559 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8560
8561 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8562 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8563 new_crtc = set->crtc;
8564 }
8565
8566 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8567 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8568 new_crtc)) {
5e2b584e 8569 return -EINVAL;
50f56119 8570 }
9a935856
DV		 8571 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8572
8573 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8574 connector->base.base.id,
8575 drm_get_connector_name(&connector->base),
8576 new_crtc->base.id);
8577 }
8578
8579 /* Check for any encoders that needs to be disabled. */
8580 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8581 base.head) {
8582 list_for_each_entry(connector,
8583 &dev->mode_config.connector_list,
8584 base.head) {
8585 if (connector->new_encoder == encoder) {
8586 WARN_ON(!connector->new_encoder->new_crtc);
8587
8588 goto next_encoder;
8589 }
8590 }
8591 encoder->new_crtc = NULL;
8592next_encoder:
8593 /* Only now check for crtc changes so we don't miss encoders
8594 * that will be disabled. */
8595 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8596 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8597 config->mode_changed = true;
50f56119
DV		 8598 }
8599 }
9a935856 8600 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8601
2e431051
DV		 8602 return 0;
8603}
8604
8605static int intel_crtc_set_config(struct drm_mode_set *set)
8606{
8607 struct drm_device *dev;
2e431051
DV		 8608 struct drm_mode_set save_set;
8609 struct intel_set_config *config;
8610 int ret;
2e431051 8611
8d3e375e
DV		 8612 BUG_ON(!set);
8613 BUG_ON(!set->crtc);
8614 BUG_ON(!set->crtc->helper_private);
2e431051 8615
7e53f3a4
DV		 8616 /* Enforce sane interface api - has been abused by the fb helper. */
8617 BUG_ON(!set->mode && set->fb);
8618 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8619
2e431051
DV		 8620 if (set->fb) {
8621 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8622 set->crtc->base.id, set->fb->base.id,
8623 (int)set->num_connectors, set->x, set->y);
8624 } else {
8625 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8626 }
8627
8628 dev = set->crtc->dev;
8629
8630 ret = -ENOMEM;
8631 config = kzalloc(sizeof(*config), GFP_KERNEL);
8632 if (!config)
8633 goto out_config;
8634
8635 ret = intel_set_config_save_state(dev, config);
8636 if (ret)
8637 goto out_config;
8638
8639 save_set.crtc = set->crtc;
8640 save_set.mode = &set->crtc->mode;
8641 save_set.x = set->crtc->x;
8642 save_set.y = set->crtc->y;
8643 save_set.fb = set->crtc->fb;
8644
8645 /* Compute whether we need a full modeset, only an fb base update or no
8646 * change at all. In the future we might also check whether only the
8647 * mode changed, e.g. for LVDS where we only change the panel fitter in
8648 * such cases. */
8649 intel_set_config_compute_mode_changes(set, config);
8650
9a935856 8651 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8652 if (ret)
8653 goto fail;
8654
5e2b584e 8655 if (config->mode_changed) {
c0c36b94
CW		 8656 ret = intel_set_mode(set->crtc, set->mode,
8657 set->x, set->y, set->fb);
8658 if (ret) {
8659 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8660 set->crtc->base.id, ret);
87f1faa6
DV		 8661 goto fail;
8662 }
5e2b584e 8663 } else if (config->fb_changed) {
4878cae2
VS		 8664 intel_crtc_wait_for_pending_flips(set->crtc);
8665
4f660f49 8666 ret = intel_pipe_set_base(set->crtc,
94352cf9 8667 set->x, set->y, set->fb);
50f56119
DV		 8668 }
8669
d9e55608
DV		 8670 intel_set_config_free(config);
8671
50f56119
DV		 8672 return 0;
8673
8674fail:
85f9eb71 8675 intel_set_config_restore_state(dev, config);
50f56119
DV		 8676
8677 /* Try to restore the config */
5e2b584e 8678 if (config->mode_changed &&
c0c36b94
CW		 8679 intel_set_mode(save_set.crtc, save_set.mode,
8680 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8681 DRM_ERROR("failed to restore config after modeset failure\n");
8682
d9e55608
DV		 8683out_config:
8684 intel_set_config_free(config);
50f56119
DV		 8685 return ret;
8686}
f6e5b160
CW		 8687
8688static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8689 .cursor_set = intel_crtc_cursor_set,
8690 .cursor_move = intel_crtc_cursor_move,
8691 .gamma_set = intel_crtc_gamma_set,
50f56119 8692 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8693 .destroy = intel_crtc_destroy,
8694 .page_flip = intel_crtc_page_flip,
8695};
8696
79f689aa
PZ		 8697static void intel_cpu_pll_init(struct drm_device *dev)
8698{
affa9354 8699 if (HAS_DDI(dev))
79f689aa
PZ		 8700 intel_ddi_pll_init(dev);
8701}
8702
ee7b9f93
JB		 8703static void intel_pch_pll_init(struct drm_device *dev)
8704{
8705 drm_i915_private_t *dev_priv = dev->dev_private;
8706 int i;
8707
8708 if (dev_priv->num_pch_pll == 0) {
8709 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8710 return;
8711 }
8712
8713 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8714 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8715 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8716 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8717 }
8718}
8719
b358d0a6 8720static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8721{
22fd0fab 8722 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8723 struct intel_crtc *intel_crtc;
8724 int i;
8725
8726 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8727 if (intel_crtc == NULL)
8728 return;
8729
8730 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8731
8732 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8733 for (i = 0; i < 256; i++) {
8734 intel_crtc->lut_r[i] = i;
8735 intel_crtc->lut_g[i] = i;
8736 intel_crtc->lut_b[i] = i;
8737 }
8738
80824003
JB		 8739 /* Swap pipes & planes for FBC on pre-965 */
8740 intel_crtc->pipe = pipe;
8741 intel_crtc->plane = pipe;
e2e767ab 8742 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8743 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8744 intel_crtc->plane = !pipe;
80824003
JB		 8745 }
8746
22fd0fab
JB		 8747 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8748 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8749 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8750 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8751
79e53945 8752 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8753}
8754
08d7b3d1 8755int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8756 struct drm_file *file)
08d7b3d1 8757{
08d7b3d1 8758 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8759 struct drm_mode_object *drmmode_obj;
8760 struct intel_crtc *crtc;
08d7b3d1 8761
1cff8f6b
DV		 8762 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8763 return -ENODEV;
08d7b3d1 8764
c05422d5
DV		 8765 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8766 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8767
c05422d5 8768 if (!drmmode_obj) {
08d7b3d1
CW		 8769 DRM_ERROR("no such CRTC id\n");
8770 return -EINVAL;
8771 }
8772
c05422d5
DV		 8773 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8774 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8775
c05422d5 8776 return 0;
08d7b3d1
CW		 8777}
8778
66a9278e 8779static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8780{
66a9278e
DV		 8781 struct drm_device *dev = encoder->base.dev;
8782 struct intel_encoder *source_encoder;
79e53945 8783 int index_mask = 0;
79e53945
JB		 8784 int entry = 0;
8785
66a9278e
DV		 8786 list_for_each_entry(source_encoder,
8787 &dev->mode_config.encoder_list, base.head) {
8788
8789 if (encoder == source_encoder)
79e53945 8790 index_mask |= (1 << entry);
66a9278e
DV		 8791
8792 /* Intel hw has only one MUX where enocoders could be cloned. */
8793 if (encoder->cloneable && source_encoder->cloneable)
8794 index_mask |= (1 << entry);
8795
79e53945
JB		 8796 entry++;
8797 }
4ef69c7a 8798
79e53945
JB		 8799 return index_mask;
8800}
8801
4d302442
CW		 8802static bool has_edp_a(struct drm_device *dev)
8803{
8804 struct drm_i915_private *dev_priv = dev->dev_private;
8805
8806 if (!IS_MOBILE(dev))
8807 return false;
8808
8809 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8810 return false;
8811
8812 if (IS_GEN5(dev) &&
8813 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8814 return false;
8815
8816 return true;
8817}
8818
79e53945
JB		 8819static void intel_setup_outputs(struct drm_device *dev)
8820{
725e30ad 8821 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8822 struct intel_encoder *encoder;
cb0953d7 8823 bool dpd_is_edp = false;
f3cfcba6 8824 bool has_lvds;
79e53945 8825
f3cfcba6 8826 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8827 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8828 /* disable the panel fitter on everything but LVDS */
8829 I915_WRITE(PFIT_CONTROL, 0);
8830 }
79e53945 8831
c40c0f5b 8832 if (!IS_ULT(dev))
79935fca 8833 intel_crt_init(dev);
cb0953d7 8834
affa9354 8835 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8836 int found;
8837
8838 /* Haswell uses DDI functions to detect digital outputs */
8839 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8840 /* DDI A only supports eDP */
8841 if (found)
8842 intel_ddi_init(dev, PORT_A);
8843
8844 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8845 * register */
8846 found = I915_READ(SFUSE_STRAP);
8847
8848 if (found & SFUSE_STRAP_DDIB_DETECTED)
8849 intel_ddi_init(dev, PORT_B);
8850 if (found & SFUSE_STRAP_DDIC_DETECTED)
8851 intel_ddi_init(dev, PORT_C);
8852 if (found & SFUSE_STRAP_DDID_DETECTED)
8853 intel_ddi_init(dev, PORT_D);
8854 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8855 int found;
270b3042
DV		 8856 dpd_is_edp = intel_dpd_is_edp(dev);
8857
8858 if (has_edp_a(dev))
8859 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8860
dc0fa718 8861 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8862 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8863 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8864 if (!found)
e2debe91 8865 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8866 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8867 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8868 }
8869
dc0fa718 8870 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8871 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8872
dc0fa718 8873 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8874 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8875
5eb08b69 8876 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8877 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8878
270b3042 8879 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8880 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8881 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8882 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8883 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8884 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8885
dc0fa718 8886 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8887 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8888 PORT_B);
67cfc203
VS		 8889 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8890 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8891 }
103a196f 8892 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8893 bool found = false;
7d57382e 8894
e2debe91 8895 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8896 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8897 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8898 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8899 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8900 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8901 }
27185ae1 8902
e7281eab 8903 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8904 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8905 }
13520b05
KH		 8906
8907 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8908
e2debe91 8909 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8910 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8911 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8912 }
27185ae1 8913
e2debe91 8914 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8915
b01f2c3a
JB		 8916 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8917 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8918 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8919 }
e7281eab 8920 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8921 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8922 }
27185ae1 8923
b01f2c3a 8924 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8925 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8926 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8927 } else if (IS_GEN2(dev))
79e53945
JB		 8928 intel_dvo_init(dev);
8929
103a196f 8930 if (SUPPORTS_TV(dev))
79e53945
JB		 8931 intel_tv_init(dev);
8932
4ef69c7a
CW		 8933 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8934 encoder->base.possible_crtcs = encoder->crtc_mask;
8935 encoder->base.possible_clones =
66a9278e 8936 intel_encoder_clones(encoder);
79e53945 8937 }
47356eb6 8938
dde86e2d 8939 intel_init_pch_refclk(dev);
270b3042
DV		 8940
8941 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8942}
8943
8944static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8945{
8946 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8947
8948 drm_framebuffer_cleanup(fb);
05394f39 8949 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8950
8951 kfree(intel_fb);
8952}
8953
8954static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8955 struct drm_file *file,
79e53945
JB		 8956 unsigned int *handle)
8957{
8958 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8959 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8960
05394f39 8961 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8962}
8963
8964static const struct drm_framebuffer_funcs intel_fb_funcs = {
8965 .destroy = intel_user_framebuffer_destroy,
8966 .create_handle = intel_user_framebuffer_create_handle,
8967};
8968
38651674
DA		 8969int intel_framebuffer_init(struct drm_device *dev,
8970 struct intel_framebuffer *intel_fb,
308e5bcb 8971 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8972 struct drm_i915_gem_object *obj)
79e53945 8973{
79e53945
JB		 8974 int ret;
8975
c16ed4be
CW		 8976 if (obj->tiling_mode == I915_TILING_Y) {
8977 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8978 return -EINVAL;
c16ed4be 8979 }
57cd6508 8980
c16ed4be
CW		 8981 if (mode_cmd->pitches[0] & 63) {
8982 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8983 mode_cmd->pitches[0]);
57cd6508 8984 return -EINVAL;
c16ed4be 8985 }
57cd6508 8986
5d7bd705 8987 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8988 if (mode_cmd->pitches[0] > 32768) {
8989 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8990 mode_cmd->pitches[0]);
5d7bd705 8991 return -EINVAL;
c16ed4be 8992 }
5d7bd705
VS		 8993
8994 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8995 mode_cmd->pitches[0] != obj->stride) {
8996 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8997 mode_cmd->pitches[0], obj->stride);
5d7bd705 8998 return -EINVAL;
c16ed4be 8999 }
5d7bd705 9000
57779d06 9001 /* Reject formats not supported by any plane early. */
308e5bcb 9002 switch (mode_cmd->pixel_format) {
57779d06 9003 case DRM_FORMAT_C8:
04b3924d
VS		 9004 case DRM_FORMAT_RGB565:
9005 case DRM_FORMAT_XRGB8888:
9006 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9007 break;
9008 case DRM_FORMAT_XRGB1555:
9009 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9010 if (INTEL_INFO(dev)->gen > 3) {
9011 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9012 return -EINVAL;
c16ed4be 9013 }
57779d06
VS		 9014 break;
9015 case DRM_FORMAT_XBGR8888:
9016 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9017 case DRM_FORMAT_XRGB2101010:
9018 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9019 case DRM_FORMAT_XBGR2101010:
9020 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9021 if (INTEL_INFO(dev)->gen < 4) {
9022 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9023 return -EINVAL;
c16ed4be 9024 }
b5626747 9025 break;
04b3924d
VS		 9026 case DRM_FORMAT_YUYV:
9027 case DRM_FORMAT_UYVY:
9028 case DRM_FORMAT_YVYU:
9029 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9030 if (INTEL_INFO(dev)->gen < 5) {
9031 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9032 return -EINVAL;
c16ed4be 9033 }
57cd6508
CW		 9034 break;
9035 default:
c16ed4be 9036 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9037 return -EINVAL;
9038 }
9039
90f9a336
VS		 9040 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9041 if (mode_cmd->offsets[0] != 0)
9042 return -EINVAL;
9043
c7d73f6a
DV		 9044 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9045 intel_fb->obj = obj;
9046
79e53945
JB		 9047 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9048 if (ret) {
9049 DRM_ERROR("framebuffer init failed %d\n", ret);
9050 return ret;
9051 }
9052
79e53945
JB		 9053 return 0;
9054}
9055
79e53945
JB		 9056static struct drm_framebuffer *
9057intel_user_framebuffer_create(struct drm_device *dev,
9058 struct drm_file *filp,
308e5bcb 9059 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9060{
05394f39 9061 struct drm_i915_gem_object *obj;
79e53945 9062
308e5bcb
JB		 9063 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9064 mode_cmd->handles[0]));
c8725226 9065 if (&obj->base == NULL)
cce13ff7 9066 return ERR_PTR(-ENOENT);
79e53945 9067
d2dff872 9068 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9069}
9070
79e53945 9071static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9072 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9073 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9074};
9075
e70236a8
JB		 9076/* Set up chip specific display functions */
9077static void intel_init_display(struct drm_device *dev)
9078{
9079 struct drm_i915_private *dev_priv = dev->dev_private;
9080
ee9300bb
DV		 9081 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9082 dev_priv->display.find_dpll = g4x_find_best_dpll;
9083 else if (IS_VALLEYVIEW(dev))
9084 dev_priv->display.find_dpll = vlv_find_best_dpll;
9085 else if (IS_PINEVIEW(dev))
9086 dev_priv->display.find_dpll = pnv_find_best_dpll;
9087 else
9088 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9089
affa9354 9090 if (HAS_DDI(dev)) {
0e8ffe1b 9091 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9092 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9093 dev_priv->display.crtc_enable = haswell_crtc_enable;
9094 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9095 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9096 dev_priv->display.update_plane = ironlake_update_plane;
9097 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9098 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9099 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9100 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9101 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9102 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9103 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9104 } else if (IS_VALLEYVIEW(dev)) {
9105 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9106 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9107 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9108 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9109 dev_priv->display.off = i9xx_crtc_off;
9110 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9111 } else {
0e8ffe1b 9112 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9113 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9114 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9115 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9116 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9117 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9118 }
e70236a8 9119
e70236a8 9120 /* Returns the core display clock speed */
25eb05fc
JB		 9121 if (IS_VALLEYVIEW(dev))
9122 dev_priv->display.get_display_clock_speed =
9123 valleyview_get_display_clock_speed;
9124 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9125 dev_priv->display.get_display_clock_speed =
9126 i945_get_display_clock_speed;
9127 else if (IS_I915G(dev))
9128 dev_priv->display.get_display_clock_speed =
9129 i915_get_display_clock_speed;
f2b115e6 9130 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9131 dev_priv->display.get_display_clock_speed =
9132 i9xx_misc_get_display_clock_speed;
9133 else if (IS_I915GM(dev))
9134 dev_priv->display.get_display_clock_speed =
9135 i915gm_get_display_clock_speed;
9136 else if (IS_I865G(dev))
9137 dev_priv->display.get_display_clock_speed =
9138 i865_get_display_clock_speed;
f0f8a9ce 9139 else if (IS_I85X(dev))
e70236a8
JB		 9140 dev_priv->display.get_display_clock_speed =
9141 i855_get_display_clock_speed;
9142 else /* 852, 830 */
9143 dev_priv->display.get_display_clock_speed =
9144 i830_get_display_clock_speed;
9145
7f8a8569 9146 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9147 if (IS_GEN5(dev)) {
674cf967 9148 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9149 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9150 } else if (IS_GEN6(dev)) {
674cf967 9151 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9152 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9153 } else if (IS_IVYBRIDGE(dev)) {
9154 /* FIXME: detect B0+ stepping and use auto training */
9155 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9156 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9157 dev_priv->display.modeset_global_resources =
9158 ivb_modeset_global_resources;
c82e4d26
ED		 9159 } else if (IS_HASWELL(dev)) {
9160 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9161 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9162 dev_priv->display.modeset_global_resources =
9163 haswell_modeset_global_resources;
a0e63c22 9164 }
6067aaea 9165 } else if (IS_G4X(dev)) {
e0dac65e 9166 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9167 }
8c9f3aaf
JB		 9168
9169 /* Default just returns -ENODEV to indicate unsupported */
9170 dev_priv->display.queue_flip = intel_default_queue_flip;
9171
9172 switch (INTEL_INFO(dev)->gen) {
9173 case 2:
9174 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9175 break;
9176
9177 case 3:
9178 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9179 break;
9180
9181 case 4:
9182 case 5:
9183 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9184 break;
9185
9186 case 6:
9187 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9188 break;
7c9017e5
JB		 9189 case 7:
9190 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9191 break;
8c9f3aaf 9192 }
e70236a8
JB		 9193}
9194
b690e96c
JB		 9195/*
9196 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9197 * resume, or other times. This quirk makes sure that's the case for
9198 * affected systems.
9199 */
0206e353 9200static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9201{
9202 struct drm_i915_private *dev_priv = dev->dev_private;
9203
9204 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9205 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9206}
9207
435793df
KP		 9208/*
9209 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9210 */
9211static void quirk_ssc_force_disable(struct drm_device *dev)
9212{
9213 struct drm_i915_private *dev_priv = dev->dev_private;
9214 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9215 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9216}
9217
4dca20ef 9218/*
5a15ab5b
CE		 9219 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9220 * brightness value
4dca20ef
CE		 9221 */
9222static void quirk_invert_brightness(struct drm_device *dev)
9223{
9224 struct drm_i915_private *dev_priv = dev->dev_private;
9225 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9226 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9227}
9228
b690e96c
JB		 9229struct intel_quirk {
9230 int device;
9231 int subsystem_vendor;
9232 int subsystem_device;
9233 void (*hook)(struct drm_device *dev);
9234};
9235
5f85f176
EE		 9236/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9237struct intel_dmi_quirk {
9238 void (*hook)(struct drm_device *dev);
9239 const struct dmi_system_id (*dmi_id_list)[];
9240};
9241
9242static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9243{
9244 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9245 return 1;
9246}
9247
9248static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9249 {
9250 .dmi_id_list = &(const struct dmi_system_id[]) {
9251 {
9252 .callback = intel_dmi_reverse_brightness,
9253 .ident = "NCR Corporation",
9254 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9255 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9256 },
9257 },
9258 { } /* terminating entry */
9259 },
9260 .hook = quirk_invert_brightness,
9261 },
9262};
9263
c43b5634 9264static struct intel_quirk intel_quirks[] = {
b690e96c 9265 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9266 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9267
b690e96c
JB		 9268 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9269 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9270
b690e96c
JB		 9271 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9272 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9273
ccd0d36e 9274 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9275 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9276 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9277
9278 /* Lenovo U160 cannot use SSC on LVDS */
9279 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9280
9281 /* Sony Vaio Y cannot use SSC on LVDS */
9282 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9283
9284 /* Acer Aspire 5734Z must invert backlight brightness */
9285 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9286
9287 /* Acer/eMachines G725 */
9288 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9289
9290 /* Acer/eMachines e725 */
9291 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9292
9293 /* Acer/Packard Bell NCL20 */
9294 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9295
9296 /* Acer Aspire 4736Z */
9297 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9298};
9299
9300static void intel_init_quirks(struct drm_device *dev)
9301{
9302 struct pci_dev *d = dev->pdev;
9303 int i;
9304
9305 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9306 struct intel_quirk *q = &intel_quirks[i];
9307
9308 if (d->device == q->device &&
9309 (d->subsystem_vendor == q->subsystem_vendor ||
9310 q->subsystem_vendor == PCI_ANY_ID) &&
9311 (d->subsystem_device == q->subsystem_device ||
9312 q->subsystem_device == PCI_ANY_ID))
9313 q->hook(dev);
9314 }
5f85f176
EE		 9315 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9316 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9317 intel_dmi_quirks[i].hook(dev);
9318 }
b690e96c
JB		 9319}
9320
9cce37f4
JB		 9321/* Disable the VGA plane that we never use */
9322static void i915_disable_vga(struct drm_device *dev)
9323{
9324 struct drm_i915_private *dev_priv = dev->dev_private;
9325 u8 sr1;
766aa1c4 9326 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9327
9328 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9329 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9330 sr1 = inb(VGA_SR_DATA);
9331 outb(sr1 | 1<<5, VGA_SR_DATA);
9332 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9333 udelay(300);
9334
9335 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9336 POSTING_READ(vga_reg);
9337}
9338
f817586c
DV		 9339void intel_modeset_init_hw(struct drm_device *dev)
9340{
fa42e23c 9341 intel_init_power_well(dev);
0232e927 9342
a8f78b58
ED		 9343 intel_prepare_ddi(dev);
9344
f817586c
DV		 9345 intel_init_clock_gating(dev);
9346
79f5b2c7 9347 mutex_lock(&dev->struct_mutex);
8090c6b9 9348 intel_enable_gt_powersave(dev);
79f5b2c7 9349 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9350}
9351
7d708ee4
ID		 9352void intel_modeset_suspend_hw(struct drm_device *dev)
9353{
9354 intel_suspend_hw(dev);
9355}
9356
79e53945
JB		 9357void intel_modeset_init(struct drm_device *dev)
9358{
652c393a 9359 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9360 int i, j, ret;
79e53945
JB		 9361
9362 drm_mode_config_init(dev);
9363
9364 dev->mode_config.min_width = 0;
9365 dev->mode_config.min_height = 0;
9366
019d96cb
DA		 9367 dev->mode_config.preferred_depth = 24;
9368 dev->mode_config.prefer_shadow = 1;
9369
e6ecefaa 9370 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9371
b690e96c
JB		 9372 intel_init_quirks(dev);
9373
1fa61106
ED		 9374 intel_init_pm(dev);
9375
e3c74757
BW		 9376 if (INTEL_INFO(dev)->num_pipes == 0)
9377 return;
9378
e70236a8
JB		 9379 intel_init_display(dev);
9380
a6c45cf0
CW		 9381 if (IS_GEN2(dev)) {
9382 dev->mode_config.max_width = 2048;
9383 dev->mode_config.max_height = 2048;
9384 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9385 dev->mode_config.max_width = 4096;
9386 dev->mode_config.max_height = 4096;
79e53945 9387 } else {
a6c45cf0
CW		 9388 dev->mode_config.max_width = 8192;
9389 dev->mode_config.max_height = 8192;
79e53945 9390 }
5d4545ae 9391 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9392
28c97730 9393 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9394 INTEL_INFO(dev)->num_pipes,
9395 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9396
7eb552ae 9397 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9398 intel_crtc_init(dev, i);
7f1f3851
JB		 9399 for (j = 0; j < dev_priv->num_plane; j++) {
9400 ret = intel_plane_init(dev, i, j);
9401 if (ret)
06da8da2
VS		 9402 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9403 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9404 }
79e53945
JB		 9405 }
9406
79f689aa 9407 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9408 intel_pch_pll_init(dev);
9409
9cce37f4
JB		 9410 /* Just disable it once at startup */
9411 i915_disable_vga(dev);
79e53945 9412 intel_setup_outputs(dev);
11be49eb
CW		 9413
9414 /* Just in case the BIOS is doing something questionable. */
9415 intel_disable_fbc(dev);
2c7111db
CW		 9416}
9417
24929352
DV		 9418static void
9419intel_connector_break_all_links(struct intel_connector *connector)
9420{
9421 connector->base.dpms = DRM_MODE_DPMS_OFF;
9422 connector->base.encoder = NULL;
9423 connector->encoder->connectors_active = false;
9424 connector->encoder->base.crtc = NULL;
9425}
9426
7fad798e
DV		 9427static void intel_enable_pipe_a(struct drm_device *dev)
9428{
9429 struct intel_connector *connector;
9430 struct drm_connector *crt = NULL;
9431 struct intel_load_detect_pipe load_detect_temp;
9432
9433 /* We can't just switch on the pipe A, we need to set things up with a
9434 * proper mode and output configuration. As a gross hack, enable pipe A
9435 * by enabling the load detect pipe once. */
9436 list_for_each_entry(connector,
9437 &dev->mode_config.connector_list,
9438 base.head) {
9439 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9440 crt = &connector->base;
9441 break;
9442 }
9443 }
9444
9445 if (!crt)
9446 return;
9447
9448 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9449 intel_release_load_detect_pipe(crt, &load_detect_temp);
9450
652c393a 9451
7fad798e
DV		 9452}
9453
fa555837
DV		 9454static bool
9455intel_check_plane_mapping(struct intel_crtc *crtc)
9456{
7eb552ae
BW		 9457 struct drm_device *dev = crtc->base.dev;
9458 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9459 u32 reg, val;
9460
7eb552ae 9461 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9462 return true;
9463
9464 reg = DSPCNTR(!crtc->plane);
9465 val = I915_READ(reg);
9466
9467 if ((val & DISPLAY_PLANE_ENABLE) &&
9468 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9469 return false;
9470
9471 return true;
9472}
9473
24929352
DV		 9474static void intel_sanitize_crtc(struct intel_crtc *crtc)
9475{
9476 struct drm_device *dev = crtc->base.dev;
9477 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9478 u32 reg;
24929352 9479
24929352 9480 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9481 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9482 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9483
9484 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9485 * disable the crtc (and hence change the state) if it is wrong. Note
9486 * that gen4+ has a fixed plane -> pipe mapping. */
9487 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9488 struct intel_connector *connector;
9489 bool plane;
9490
24929352
DV		 9491 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9492 crtc->base.base.id);
9493
9494 /* Pipe has the wrong plane attached and the plane is active.
9495 * Temporarily change the plane mapping and disable everything
9496 * ... */
9497 plane = crtc->plane;
9498 crtc->plane = !plane;
9499 dev_priv->display.crtc_disable(&crtc->base);
9500 crtc->plane = plane;
9501
9502 /* ... and break all links. */
9503 list_for_each_entry(connector, &dev->mode_config.connector_list,
9504 base.head) {
9505 if (connector->encoder->base.crtc != &crtc->base)
9506 continue;
9507
9508 intel_connector_break_all_links(connector);
9509 }
9510
9511 WARN_ON(crtc->active);
9512 crtc->base.enabled = false;
9513 }
24929352 9514
7fad798e
DV		 9515 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9516 crtc->pipe == PIPE_A && !crtc->active) {
9517 /* BIOS forgot to enable pipe A, this mostly happens after
9518 * resume. Force-enable the pipe to fix this, the update_dpms
9519 * call below we restore the pipe to the right state, but leave
9520 * the required bits on. */
9521 intel_enable_pipe_a(dev);
9522 }
9523
24929352
DV		 9524 /* Adjust the state of the output pipe according to whether we
9525 * have active connectors/encoders. */
9526 intel_crtc_update_dpms(&crtc->base);
9527
9528 if (crtc->active != crtc->base.enabled) {
9529 struct intel_encoder *encoder;
9530
9531 /* This can happen either due to bugs in the get_hw_state
9532 * functions or because the pipe is force-enabled due to the
9533 * pipe A quirk. */
9534 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9535 crtc->base.base.id,
9536 crtc->base.enabled ? "enabled" : "disabled",
9537 crtc->active ? "enabled" : "disabled");
9538
9539 crtc->base.enabled = crtc->active;
9540
9541 /* Because we only establish the connector -> encoder ->
9542 * crtc links if something is active, this means the
9543 * crtc is now deactivated. Break the links. connector
9544 * -> encoder links are only establish when things are
9545 * actually up, hence no need to break them. */
9546 WARN_ON(crtc->active);
9547
9548 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9549 WARN_ON(encoder->connectors_active);
9550 encoder->base.crtc = NULL;
9551 }
9552 }
9553}
9554
9555static void intel_sanitize_encoder(struct intel_encoder *encoder)
9556{
9557 struct intel_connector *connector;
9558 struct drm_device *dev = encoder->base.dev;
9559
9560 /* We need to check both for a crtc link (meaning that the
9561 * encoder is active and trying to read from a pipe) and the
9562 * pipe itself being active. */
9563 bool has_active_crtc = encoder->base.crtc &&
9564 to_intel_crtc(encoder->base.crtc)->active;
9565
9566 if (encoder->connectors_active && !has_active_crtc) {
9567 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9568 encoder->base.base.id,
9569 drm_get_encoder_name(&encoder->base));
9570
9571 /* Connector is active, but has no active pipe. This is
9572 * fallout from our resume register restoring. Disable
9573 * the encoder manually again. */
9574 if (encoder->base.crtc) {
9575 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9576 encoder->base.base.id,
9577 drm_get_encoder_name(&encoder->base));
9578 encoder->disable(encoder);
9579 }
9580
9581 /* Inconsistent output/port/pipe state happens presumably due to
9582 * a bug in one of the get_hw_state functions. Or someplace else
9583 * in our code, like the register restore mess on resume. Clamp
9584 * things to off as a safer default. */
9585 list_for_each_entry(connector,
9586 &dev->mode_config.connector_list,
9587 base.head) {
9588 if (connector->encoder != encoder)
9589 continue;
9590
9591 intel_connector_break_all_links(connector);
9592 }
9593 }
9594 /* Enabled encoders without active connectors will be fixed in
9595 * the crtc fixup. */
9596}
9597
44cec740 9598void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9599{
9600 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9601 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9602
9603 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9604 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9605 i915_disable_vga(dev);
0fde901f
KM		 9606 }
9607}
9608
24929352
DV		 9609/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9610 * and i915 state tracking structures. */
45e2b5f6
DV		 9611void intel_modeset_setup_hw_state(struct drm_device *dev,
9612 bool force_restore)
24929352
DV		 9613{
9614 struct drm_i915_private *dev_priv = dev->dev_private;
9615 enum pipe pipe;
b5644d05 9616 struct drm_plane *plane;
24929352
DV		 9617 struct intel_crtc *crtc;
9618 struct intel_encoder *encoder;
9619 struct intel_connector *connector;
9620
0e8ffe1b
DV		 9621 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9622 base.head) {
88adfff1 9623 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9624
0e8ffe1b
DV		 9625 crtc->active = dev_priv->display.get_pipe_config(crtc,
9626 &crtc->config);
24929352
DV		 9627
9628 crtc->base.enabled = crtc->active;
9629
9630 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9631 crtc->base.base.id,
9632 crtc->active ? "enabled" : "disabled");
9633 }
9634
affa9354 9635 if (HAS_DDI(dev))
6441ab5f
PZ		 9636 intel_ddi_setup_hw_pll_state(dev);
9637
24929352
DV		 9638 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9639 base.head) {
9640 pipe = 0;
9641
9642 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9643 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9644 encoder->base.crtc = &crtc->base;
9645 if (encoder->get_config)
9646 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9647 } else {
9648 encoder->base.crtc = NULL;
9649 }
9650
9651 encoder->connectors_active = false;
9652 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9653 encoder->base.base.id,
9654 drm_get_encoder_name(&encoder->base),
9655 encoder->base.crtc ? "enabled" : "disabled",
9656 pipe);
9657 }
9658
9659 list_for_each_entry(connector, &dev->mode_config.connector_list,
9660 base.head) {
9661 if (connector->get_hw_state(connector)) {
9662 connector->base.dpms = DRM_MODE_DPMS_ON;
9663 connector->encoder->connectors_active = true;
9664 connector->base.encoder = &connector->encoder->base;
9665 } else {
9666 connector->base.dpms = DRM_MODE_DPMS_OFF;
9667 connector->base.encoder = NULL;
9668 }
9669 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9670 connector->base.base.id,
9671 drm_get_connector_name(&connector->base),
9672 connector->base.encoder ? "enabled" : "disabled");
9673 }
9674
9675 /* HW state is read out, now we need to sanitize this mess. */
9676 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9677 base.head) {
9678 intel_sanitize_encoder(encoder);
9679 }
9680
9681 for_each_pipe(pipe) {
9682 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9683 intel_sanitize_crtc(crtc);
c0b03411 9684 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9685 }
9a935856 9686
45e2b5f6 9687 if (force_restore) {
f30da187
DV		 9688 /*
9689 * We need to use raw interfaces for restoring state to avoid
9690 * checking (bogus) intermediate states.
9691 */
45e2b5f6 9692 for_each_pipe(pipe) {
b5644d05
JB		 9693 struct drm_crtc *crtc =
9694 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9695
9696 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9697 crtc->fb);
45e2b5f6 9698 }
b5644d05
JB		 9699 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9700 intel_plane_restore(plane);
0fde901f
KM		 9701
9702 i915_redisable_vga(dev);
45e2b5f6
DV		 9703 } else {
9704 intel_modeset_update_staged_output_state(dev);
9705 }
8af6cf88
DV		 9706
9707 intel_modeset_check_state(dev);
2e938892
DV		 9708
9709 drm_mode_config_reset(dev);
2c7111db
CW		 9710}
9711
9712void intel_modeset_gem_init(struct drm_device *dev)
9713{
1833b134 9714 intel_modeset_init_hw(dev);
02e792fb
DV		 9715
9716 intel_setup_overlay(dev);
24929352 9717
45e2b5f6 9718 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9719}
9720
9721void intel_modeset_cleanup(struct drm_device *dev)
9722{
652c393a
JB		 9723 struct drm_i915_private *dev_priv = dev->dev_private;
9724 struct drm_crtc *crtc;
9725 struct intel_crtc *intel_crtc;
9726
fd0c0642
DV		 9727 /*
9728 * Interrupts and polling as the first thing to avoid creating havoc.
9729 * Too much stuff here (turning of rps, connectors, ...) would
9730 * experience fancy races otherwise.
9731 */
9732 drm_irq_uninstall(dev);
9733 cancel_work_sync(&dev_priv->hotplug_work);
9734 /*
9735 * Due to the hpd irq storm handling the hotplug work can re-arm the
9736 * poll handlers. Hence disable polling after hpd handling is shut down.
9737 */
f87ea761 9738 drm_kms_helper_poll_fini(dev);
fd0c0642 9739
652c393a
JB		 9740 mutex_lock(&dev->struct_mutex);
9741
723bfd70
JB		 9742 intel_unregister_dsm_handler();
9743
652c393a
JB		 9744 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9745 /* Skip inactive CRTCs */
9746 if (!crtc->fb)
9747 continue;
9748
9749 intel_crtc = to_intel_crtc(crtc);
3dec0095 9750 intel_increase_pllclock(crtc);
652c393a
JB		 9751 }
9752
973d04f9 9753 intel_disable_fbc(dev);
e70236a8 9754
8090c6b9 9755 intel_disable_gt_powersave(dev);
0cdab21f 9756
930ebb46
DV		 9757 ironlake_teardown_rc6(dev);
9758
69341a5e
KH		 9759 mutex_unlock(&dev->struct_mutex);
9760
1630fe75
CW		 9761 /* flush any delayed tasks or pending work */
9762 flush_scheduled_work();
9763
dc652f90
JN		 9764 /* destroy backlight, if any, before the connectors */
9765 intel_panel_destroy_backlight(dev);
9766
79e53945 9767 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9768
9769 intel_cleanup_overlay(dev);
79e53945
JB		 9770}
9771
f1c79df3
ZW		 9772/*
9773 * Return which encoder is currently attached for connector.
9774 */
df0e9248 9775struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9776{
df0e9248
CW		 9777 return &intel_attached_encoder(connector)->base;
9778}
f1c79df3 9779
df0e9248
CW		 9780void intel_connector_attach_encoder(struct intel_connector *connector,
9781 struct intel_encoder *encoder)
9782{
9783 connector->encoder = encoder;
9784 drm_mode_connector_attach_encoder(&connector->base,
9785 &encoder->base);
79e53945 9786}
28d52043
DA		 9787
9788/*
9789 * set vga decode state - true == enable VGA decode
9790 */
9791int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9792{
9793 struct drm_i915_private *dev_priv = dev->dev_private;
9794 u16 gmch_ctrl;
9795
9796 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9797 if (state)
9798 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9799 else
9800 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9801 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9802 return 0;
9803}
c4a1d9e4
CW		 9804
9805#ifdef CONFIG_DEBUG_FS
9806#include <linux/seq_file.h>
9807
9808struct intel_display_error_state {
ff57f1b0
PZ		 9809
9810 u32 power_well_driver;
9811
c4a1d9e4
CW		 9812 struct intel_cursor_error_state {
9813 u32 control;
9814 u32 position;
9815 u32 base;
9816 u32 size;
52331309 9817 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9818
9819 struct intel_pipe_error_state {
ff57f1b0 9820 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9821 u32 conf;
9822 u32 source;
9823
9824 u32 htotal;
9825 u32 hblank;
9826 u32 hsync;
9827 u32 vtotal;
9828 u32 vblank;
9829 u32 vsync;
52331309 9830 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9831
9832 struct intel_plane_error_state {
9833 u32 control;
9834 u32 stride;
9835 u32 size;
9836 u32 pos;
9837 u32 addr;
9838 u32 surface;
9839 u32 tile_offset;
52331309 9840 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9841};
9842
9843struct intel_display_error_state *
9844intel_display_capture_error_state(struct drm_device *dev)
9845{
0206e353 9846 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9847 struct intel_display_error_state *error;
702e7a56 9848 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9849 int i;
9850
9851 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9852 if (error == NULL)
9853 return NULL;
9854
ff57f1b0
PZ		 9855 if (HAS_POWER_WELL(dev))
9856 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9857
52331309 9858 for_each_pipe(i) {
702e7a56 9859 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9860 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9861
a18c4c3d
PZ		 9862 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9863 error->cursor[i].control = I915_READ(CURCNTR(i));
9864 error->cursor[i].position = I915_READ(CURPOS(i));
9865 error->cursor[i].base = I915_READ(CURBASE(i));
9866 } else {
9867 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9868 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9869 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9870 }
c4a1d9e4
CW		 9871
9872 error->plane[i].control = I915_READ(DSPCNTR(i));
9873 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9874 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9875 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9876 error->plane[i].pos = I915_READ(DSPPOS(i));
9877 }
ca291363
PZ		 9878 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9879 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9880 if (INTEL_INFO(dev)->gen >= 4) {
9881 error->plane[i].surface = I915_READ(DSPSURF(i));
9882 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9883 }
9884
702e7a56 9885 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9886 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9887 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9888 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9889 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9890 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9891 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9892 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9893 }
9894
12d217c7
PZ		 9895 /* In the code above we read the registers without checking if the power
9896 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9897 * prevent the next I915_WRITE from detecting it and printing an error
9898 * message. */
9899 if (HAS_POWER_WELL(dev))
9900 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9901
c4a1d9e4
CW		 9902 return error;
9903}
9904
edc3d884
MK		 9905#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9906
c4a1d9e4 9907void
edc3d884 9908intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9909 struct drm_device *dev,
9910 struct intel_display_error_state *error)
9911{
9912 int i;
9913
edc3d884 9914 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9915 if (HAS_POWER_WELL(dev))
edc3d884 9916 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9917 error->power_well_driver);
52331309 9918 for_each_pipe(i) {
edc3d884
MK		 9919 err_printf(m, "Pipe [%d]:\n", i);
9920 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9921 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9922 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9923 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9924 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9925 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9926 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9927 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9928 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9929 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9930
9931 err_printf(m, "Plane [%d]:\n", i);
9932 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9933 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9934 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9935 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9936 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9937 }
4b71a570 9938 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9939 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9940 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9941 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9942 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9943 }
9944
edc3d884
MK		 9945 err_printf(m, "Cursor [%d]:\n", i);
9946 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9947 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9948 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9949 }
9950}
9951#endif
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