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drm/i915: Remove the unused p and m limits for VLV
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 316 .m1 = { .min = 2, .max = 3 },
317 .m2 = { .min = 11, .max = 156 },
811bbf05 318 .p1 = { .min = 2, .max = 3 },
a0c4da24 319 .p2 = { .dot_limit = 270000,
889059d8 320 .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 321};
322
323static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 324 .dot = { .min = 25000, .max = 270000 },
325 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 326 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 327 .m1 = { .min = 2, .max = 3 },
328 .m2 = { .min = 11, .max = 156 },
b99ab663 329 .p1 = { .min = 2, .max = 3 },
a0c4da24 330 .p2 = { .dot_limit = 270000,
889059d8 331 .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 332};
333
6b4bf1c4
VS		 334static void vlv_clock(int refclk, intel_clock_t *clock)
335{
336 clock->m = clock->m1 * clock->m2;
337 clock->p = clock->p1 * clock->p2;
338 clock->vco = refclk * clock->m / clock->n;
339 clock->dot = clock->vco / clock->p;
340}
341
e0638cdf
PZ		 342/**
343 * Returns whether any output on the specified pipe is of the specified type
344 */
345static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
346{
347 struct drm_device *dev = crtc->dev;
348 struct intel_encoder *encoder;
349
350 for_each_encoder_on_crtc(dev, crtc, encoder)
351 if (encoder->type == type)
352 return true;
353
354 return false;
355}
356
1b894b59
CW		 357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
2c07245f 359{
b91ad0ec 360 struct drm_device *dev = crtc->dev;
2c07245f 361 const intel_limit_t *limit;
b91ad0ec
ZW		 362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev)) {
1b894b59 365 if (refclk == 100000)
b91ad0ec
ZW		 366 limit = &intel_limits_ironlake_dual_lvds_100m;
367 else
368 limit = &intel_limits_ironlake_dual_lvds;
369 } else {
1b894b59 370 if (refclk == 100000)
b91ad0ec
ZW		 371 limit = &intel_limits_ironlake_single_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_single_lvds;
374 }
c6bb3538 375 } else
b91ad0ec 376 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 377
378 return limit;
379}
380
044c7c41
ML		 381static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
382{
383 struct drm_device *dev = crtc->dev;
044c7c41
ML		 384 const intel_limit_t *limit;
385
386 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 387 if (intel_is_dual_link_lvds(dev))
e4b36699 388 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 389 else
e4b36699 390 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 391 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
392 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 393 limit = &intel_limits_g4x_hdmi;
044c7c41 394 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 395 limit = &intel_limits_g4x_sdvo;
044c7c41 396 } else /* The option is for other outputs */
e4b36699 397 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 398
399 return limit;
400}
401
1b894b59 402static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 403{
404 struct drm_device *dev = crtc->dev;
405 const intel_limit_t *limit;
406
bad720ff 407 if (HAS_PCH_SPLIT(dev))
1b894b59 408 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 409 else if (IS_G4X(dev)) {
044c7c41 410 limit = intel_g4x_limit(crtc);
f2b115e6 411 } else if (IS_PINEVIEW(dev)) {
2177832f 412 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 413 limit = &intel_limits_pineview_lvds;
2177832f 414 else
f2b115e6 415 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 416 } else if (IS_VALLEYVIEW(dev)) {
417 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
418 limit = &intel_limits_vlv_dac;
a0c4da24 419 else
65ce4bf5 420 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
424 else
425 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 426 } else {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 428 limit = &intel_limits_i8xx_lvds;
5d536e28 429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 430 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 431 else
432 limit = &intel_limits_i8xx_dac;
79e53945
JB		 433 }
434 return limit;
435}
436
f2b115e6
AJ		 437/* m1 is reserved as 0 in Pineview, n is a ring counter */
438static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 439{
2177832f
SL		 440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
444}
445
7429e9d4
DV		 446static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
447{
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449}
450
ac58c3f0 451static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 452{
7429e9d4 453 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
457}
458
7c04d1d9 459#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 460/**
461 * Returns whether the given set of divisors are valid for a given refclk with
462 * the given connectors.
463 */
464
1b894b59
CW		 465static bool intel_PLL_is_valid(struct drm_device *dev,
466 const intel_limit_t *limit,
467 const intel_clock_t *clock)
79e53945 468{
79e53945 469 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 470 INTELPllInvalid("p1 out of range\n");
79e53945 471 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 472 INTELPllInvalid("p out of range\n");
79e53945 473 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 474 INTELPllInvalid("m2 out of range\n");
79e53945 475 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 476 INTELPllInvalid("m1 out of range\n");
f2b115e6 477 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 478 INTELPllInvalid("m1 <= m2\n");
79e53945 479 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 480 INTELPllInvalid("m out of range\n");
79e53945 481 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 482 INTELPllInvalid("n out of range\n");
79e53945 483 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 484 INTELPllInvalid("vco out of range\n");
79e53945
JB		 485 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
486 * connector, etc., rather than just a single range.
487 */
488 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 489 INTELPllInvalid("dot out of range\n");
79e53945
JB		 490
491 return true;
492}
493
d4906093 494static bool
ee9300bb 495i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 496 int target, int refclk, intel_clock_t *match_clock,
497 intel_clock_t *best_clock)
79e53945
JB		 498{
499 struct drm_device *dev = crtc->dev;
79e53945 500 intel_clock_t clock;
79e53945
JB		 501 int err = target;
502
a210b028 503 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 504 /*
a210b028
DV		 505 * For LVDS just rely on its current settings for dual-channel.
506 * We haven't figured out how to reliably set up different
507 * single/dual channel state, if we even can.
79e53945 508 */
1974cad0 509 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 510 clock.p2 = limit->p2.p2_fast;
511 else
512 clock.p2 = limit->p2.p2_slow;
513 } else {
514 if (target < limit->p2.dot_limit)
515 clock.p2 = limit->p2.p2_slow;
516 else
517 clock.p2 = limit->p2.p2_fast;
518 }
519
0206e353 520 memset(best_clock, 0, sizeof(*best_clock));
79e53945 521
42158660
ZY		 522 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
523 clock.m1++) {
524 for (clock.m2 = limit->m2.min;
525 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 526 if (clock.m2 >= clock.m1)
42158660
ZY		 527 break;
528 for (clock.n = limit->n.min;
529 clock.n <= limit->n.max; clock.n++) {
530 for (clock.p1 = limit->p1.min;
531 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 532 int this_err;
533
ac58c3f0
DV		 534 i9xx_clock(refclk, &clock);
535 if (!intel_PLL_is_valid(dev, limit,
536 &clock))
537 continue;
538 if (match_clock &&
539 clock.p != match_clock->p)
540 continue;
541
542 this_err = abs(clock.dot - target);
543 if (this_err < err) {
544 *best_clock = clock;
545 err = this_err;
546 }
547 }
548 }
549 }
550 }
551
552 return (err != target);
553}
554
555static bool
ee9300bb
DV		 556pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
557 int target, int refclk, intel_clock_t *match_clock,
558 intel_clock_t *best_clock)
79e53945
JB		 559{
560 struct drm_device *dev = crtc->dev;
79e53945 561 intel_clock_t clock;
79e53945
JB		 562 int err = target;
563
a210b028 564 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 565 /*
a210b028
DV		 566 * For LVDS just rely on its current settings for dual-channel.
567 * We haven't figured out how to reliably set up different
568 * single/dual channel state, if we even can.
79e53945 569 */
1974cad0 570 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 571 clock.p2 = limit->p2.p2_fast;
572 else
573 clock.p2 = limit->p2.p2_slow;
574 } else {
575 if (target < limit->p2.dot_limit)
576 clock.p2 = limit->p2.p2_slow;
577 else
578 clock.p2 = limit->p2.p2_fast;
579 }
580
0206e353 581 memset(best_clock, 0, sizeof(*best_clock));
79e53945 582
42158660
ZY		 583 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
584 clock.m1++) {
585 for (clock.m2 = limit->m2.min;
586 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 587 for (clock.n = limit->n.min;
588 clock.n <= limit->n.max; clock.n++) {
589 for (clock.p1 = limit->p1.min;
590 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 591 int this_err;
592
ac58c3f0 593 pineview_clock(refclk, &clock);
1b894b59
CW		 594 if (!intel_PLL_is_valid(dev, limit,
595 &clock))
79e53945 596 continue;
cec2f356
SP		 597 if (match_clock &&
598 clock.p != match_clock->p)
599 continue;
79e53945
JB		 600
601 this_err = abs(clock.dot - target);
602 if (this_err < err) {
603 *best_clock = clock;
604 err = this_err;
605 }
606 }
607 }
608 }
609 }
610
611 return (err != target);
612}
613
d4906093 614static bool
ee9300bb
DV		 615g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
616 int target, int refclk, intel_clock_t *match_clock,
617 intel_clock_t *best_clock)
d4906093
ML		 618{
619 struct drm_device *dev = crtc->dev;
d4906093
ML		 620 intel_clock_t clock;
621 int max_n;
622 bool found;
6ba770dc
AJ		 623 /* approximately equals target * 0.00585 */
624 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 625 found = false;
626
627 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 628 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 629 clock.p2 = limit->p2.p2_fast;
630 else
631 clock.p2 = limit->p2.p2_slow;
632 } else {
633 if (target < limit->p2.dot_limit)
634 clock.p2 = limit->p2.p2_slow;
635 else
636 clock.p2 = limit->p2.p2_fast;
637 }
638
639 memset(best_clock, 0, sizeof(*best_clock));
640 max_n = limit->n.max;
f77f13e2 641 /* based on hardware requirement, prefer smaller n to precision */
d4906093 642 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 643 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 644 for (clock.m1 = limit->m1.max;
645 clock.m1 >= limit->m1.min; clock.m1--) {
646 for (clock.m2 = limit->m2.max;
647 clock.m2 >= limit->m2.min; clock.m2--) {
648 for (clock.p1 = limit->p1.max;
649 clock.p1 >= limit->p1.min; clock.p1--) {
650 int this_err;
651
ac58c3f0 652 i9xx_clock(refclk, &clock);
1b894b59
CW		 653 if (!intel_PLL_is_valid(dev, limit,
654 &clock))
d4906093 655 continue;
1b894b59
CW		 656
657 this_err = abs(clock.dot - target);
d4906093
ML		 658 if (this_err < err_most) {
659 *best_clock = clock;
660 err_most = this_err;
661 max_n = clock.n;
662 found = true;
663 }
664 }
665 }
666 }
667 }
2c07245f
ZW		 668 return found;
669}
670
a0c4da24 671static bool
ee9300bb
DV		 672vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
673 int target, int refclk, intel_clock_t *match_clock,
674 intel_clock_t *best_clock)
a0c4da24 675{
6b4bf1c4 676 intel_clock_t clock;
69e4f900 677 unsigned int bestppm = 1000000;
27e639bf
VS		 678 /* min update 19.2 MHz */
679 int max_n = min(limit->n.max, refclk / 19200);
a0c4da24 680
6b4bf1c4
VS		 681 target *= 5; /* fast clock */
682
683 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 684
685 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 686 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 687 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 688 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 689 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 690 clock.p = clock.p1 * clock.p2;
a0c4da24 691 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 692 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 693 unsigned int ppm, diff;
694
6b4bf1c4
VS		 695 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
696 refclk * clock.m1);
697
698 vlv_clock(refclk, &clock);
43b0ac53 699
6b4bf1c4
VS		 700 if (clock.vco < limit->vco.min ||
701 clock.vco >= limit->vco.max)
43b0ac53
VS		 702 continue;
703
6b4bf1c4
VS		 704 diff = abs(clock.dot - target);
705 ppm = div_u64(1000000ULL * diff, target);
706
707 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 708 bestppm = 0;
6b4bf1c4 709 *best_clock = clock;
43b0ac53 710 }
6b4bf1c4 711
c686122c 712 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 713 bestppm = ppm;
6b4bf1c4 714 *best_clock = clock;
a0c4da24
JB		 715 }
716 }
717 }
718 }
719 }
a0c4da24
JB		 720
721 return true;
722}
a4fc5ed6 723
20ddf665
VS		 724bool intel_crtc_active(struct drm_crtc *crtc)
725{
726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
727
728 /* Be paranoid as we can arrive here with only partial
729 * state retrieved from the hardware during setup.
730 *
241bfc38 731 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 732 * as Haswell has gained clock readout/fastboot support.
733 *
734 * We can ditch the crtc->fb check as soon as we can
735 * properly reconstruct framebuffers.
736 */
737 return intel_crtc->active && crtc->fb &&
241bfc38 738 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 739}
740
a5c961d1
PZ		 741enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
742 enum pipe pipe)
743{
744 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
746
3b117c8f 747 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 748}
749
a928d536
PZ		 750static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
751{
752 struct drm_i915_private *dev_priv = dev->dev_private;
753 u32 frame, frame_reg = PIPEFRAME(pipe);
754
755 frame = I915_READ(frame_reg);
756
757 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
758 DRM_DEBUG_KMS("vblank wait timed out\n");
759}
760
9d0498a2
JB		 761/**
762 * intel_wait_for_vblank - wait for vblank on a given pipe
763 * @dev: drm device
764 * @pipe: pipe to wait for
765 *
766 * Wait for vblank to occur on a given pipe. Needed for various bits of
767 * mode setting code.
768 */
769void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 770{
9d0498a2 771 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 772 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 773
a928d536
PZ		 774 if (INTEL_INFO(dev)->gen >= 5) {
775 ironlake_wait_for_vblank(dev, pipe);
776 return;
777 }
778
300387c0
CW		 779 /* Clear existing vblank status. Note this will clear any other
780 * sticky status fields as well.
781 *
782 * This races with i915_driver_irq_handler() with the result
783 * that either function could miss a vblank event. Here it is not
784 * fatal, as we will either wait upon the next vblank interrupt or
785 * timeout. Generally speaking intel_wait_for_vblank() is only
786 * called during modeset at which time the GPU should be idle and
787 * should *not* be performing page flips and thus not waiting on
788 * vblanks...
789 * Currently, the result of us stealing a vblank from the irq
790 * handler is that a single frame will be skipped during swapbuffers.
791 */
792 I915_WRITE(pipestat_reg,
793 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
794
9d0498a2 795 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 796 if (wait_for(I915_READ(pipestat_reg) &
797 PIPE_VBLANK_INTERRUPT_STATUS,
798 50))
9d0498a2
JB		 799 DRM_DEBUG_KMS("vblank wait timed out\n");
800}
801
ab7ad7f6
KP		 802/*
803 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 804 * @dev: drm device
805 * @pipe: pipe to wait for
806 *
807 * After disabling a pipe, we can't wait for vblank in the usual way,
808 * spinning on the vblank interrupt status bit, since we won't actually
809 * see an interrupt when the pipe is disabled.
810 *
ab7ad7f6
KP		 811 * On Gen4 and above:
812 * wait for the pipe register state bit to turn off
813 *
814 * Otherwise:
815 * wait for the display line value to settle (it usually
816 * ends up stopping at the start of the next frame).
58e10eb9 817 *
9d0498a2 818 */
58e10eb9 819void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 820{
821 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 822 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
823 pipe);
ab7ad7f6
KP		 824
825 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 826 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 827
828 /* Wait for the Pipe State to go off */
58e10eb9
CW		 829 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
830 100))
284637d9 831 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 832 } else {
837ba00f 833 u32 last_line, line_mask;
58e10eb9 834 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 835 unsigned long timeout = jiffies + msecs_to_jiffies(100);
836
837ba00f
PZ		 837 if (IS_GEN2(dev))
838 line_mask = DSL_LINEMASK_GEN2;
839 else
840 line_mask = DSL_LINEMASK_GEN3;
841
ab7ad7f6
KP		 842 /* Wait for the display line to settle */
843 do {
837ba00f 844 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 845 mdelay(5);
837ba00f 846 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 847 time_after(timeout, jiffies));
848 if (time_after(jiffies, timeout))
284637d9 849 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 850 }
79e53945
JB		 851}
852
b0ea7d37
DL		 853/*
854 * ibx_digital_port_connected - is the specified port connected?
855 * @dev_priv: i915 private structure
856 * @port: the port to test
857 *
858 * Returns true if @port is connected, false otherwise.
859 */
860bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
861 struct intel_digital_port *port)
862{
863 u32 bit;
864
c36346e3
DL		 865 if (HAS_PCH_IBX(dev_priv->dev)) {
866 switch(port->port) {
867 case PORT_B:
868 bit = SDE_PORTB_HOTPLUG;
869 break;
870 case PORT_C:
871 bit = SDE_PORTC_HOTPLUG;
872 break;
873 case PORT_D:
874 bit = SDE_PORTD_HOTPLUG;
875 break;
876 default:
877 return true;
878 }
879 } else {
880 switch(port->port) {
881 case PORT_B:
882 bit = SDE_PORTB_HOTPLUG_CPT;
883 break;
884 case PORT_C:
885 bit = SDE_PORTC_HOTPLUG_CPT;
886 break;
887 case PORT_D:
888 bit = SDE_PORTD_HOTPLUG_CPT;
889 break;
890 default:
891 return true;
892 }
b0ea7d37
DL		 893 }
894
895 return I915_READ(SDEISR) & bit;
896}
897
b24e7179
JB		 898static const char *state_string(bool enabled)
899{
900 return enabled ? "on" : "off";
901}
902
903/* Only for pre-ILK configs */
55607e8a
DV		 904void assert_pll(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
909 bool cur_state;
910
911 reg = DPLL(pipe);
912 val = I915_READ(reg);
913 cur_state = !!(val & DPLL_VCO_ENABLE);
914 WARN(cur_state != state,
915 "PLL state assertion failure (expected %s, current %s)\n",
916 state_string(state), state_string(cur_state));
917}
b24e7179 918
23538ef1
JN		 919/* XXX: the dsi pll is shared between MIPI DSI ports */
920static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
921{
922 u32 val;
923 bool cur_state;
924
925 mutex_lock(&dev_priv->dpio_lock);
926 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
927 mutex_unlock(&dev_priv->dpio_lock);
928
929 cur_state = val & DSI_PLL_VCO_EN;
930 WARN(cur_state != state,
931 "DSI PLL state assertion failure (expected %s, current %s)\n",
932 state_string(state), state_string(cur_state));
933}
934#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
935#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
936
55607e8a 937struct intel_shared_dpll *
e2b78267
DV		 938intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
939{
940 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
941
a43f6e0f 942 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 943 return NULL;
944
a43f6e0f 945 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 946}
947
040484af 948/* For ILK+ */
55607e8a
DV		 949void assert_shared_dpll(struct drm_i915_private *dev_priv,
950 struct intel_shared_dpll *pll,
951 bool state)
040484af 952{
040484af 953 bool cur_state;
5358901f 954 struct intel_dpll_hw_state hw_state;
040484af 955
9d82aa17
ED		 956 if (HAS_PCH_LPT(dev_priv->dev)) {
957 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
958 return;
959 }
960
92b27b08 961 if (WARN (!pll,
46edb027 962 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 963 return;
ee7b9f93 964
5358901f 965 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 966 WARN(cur_state != state,
5358901f
DV		 967 "%s assertion failure (expected %s, current %s)\n",
968 pll->name, state_string(state), state_string(cur_state));
040484af 969}
040484af
JB		 970
971static void assert_fdi_tx(struct drm_i915_private *dev_priv,
972 enum pipe pipe, bool state)
973{
974 int reg;
975 u32 val;
976 bool cur_state;
ad80a810
PZ		 977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
040484af 979
affa9354
PZ		 980 if (HAS_DDI(dev_priv->dev)) {
981 /* DDI does not have a specific FDI_TX register */
ad80a810 982 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 983 val = I915_READ(reg);
ad80a810 984 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 985 } else {
986 reg = FDI_TX_CTL(pipe);
987 val = I915_READ(reg);
988 cur_state = !!(val & FDI_TX_ENABLE);
989 }
040484af
JB		 990 WARN(cur_state != state,
991 "FDI TX state assertion failure (expected %s, current %s)\n",
992 state_string(state), state_string(cur_state));
993}
994#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
995#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
996
997static void assert_fdi_rx(struct drm_i915_private *dev_priv,
998 enum pipe pipe, bool state)
999{
1000 int reg;
1001 u32 val;
1002 bool cur_state;
1003
d63fa0dc
PZ		 1004 reg = FDI_RX_CTL(pipe);
1005 val = I915_READ(reg);
1006 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1007 WARN(cur_state != state,
1008 "FDI RX state assertion failure (expected %s, current %s)\n",
1009 state_string(state), state_string(cur_state));
1010}
1011#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1012#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1013
1014static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1015 enum pipe pipe)
1016{
1017 int reg;
1018 u32 val;
1019
1020 /* ILK FDI PLL is always enabled */
1021 if (dev_priv->info->gen == 5)
1022 return;
1023
bf507ef7 1024 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1025 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1026 return;
1027
040484af
JB		 1028 reg = FDI_TX_CTL(pipe);
1029 val = I915_READ(reg);
1030 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1031}
1032
55607e8a
DV		 1033void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
040484af
JB		 1035{
1036 int reg;
1037 u32 val;
55607e8a 1038 bool cur_state;
040484af
JB		 1039
1040 reg = FDI_RX_CTL(pipe);
1041 val = I915_READ(reg);
55607e8a
DV		 1042 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1043 WARN(cur_state != state,
1044 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
040484af
JB		 1046}
1047
ea0760cf
JB		 1048static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1049 enum pipe pipe)
1050{
1051 int pp_reg, lvds_reg;
1052 u32 val;
1053 enum pipe panel_pipe = PIPE_A;
0de3b485 1054 bool locked = true;
ea0760cf
JB		 1055
1056 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1057 pp_reg = PCH_PP_CONTROL;
1058 lvds_reg = PCH_LVDS;
1059 } else {
1060 pp_reg = PP_CONTROL;
1061 lvds_reg = LVDS;
1062 }
1063
1064 val = I915_READ(pp_reg);
1065 if (!(val & PANEL_POWER_ON) ||
1066 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1067 locked = false;
1068
1069 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1070 panel_pipe = PIPE_B;
1071
1072 WARN(panel_pipe == pipe && locked,
1073 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1074 pipe_name(pipe));
ea0760cf
JB		 1075}
1076
93ce0ba6
JN		 1077static void assert_cursor(struct drm_i915_private *dev_priv,
1078 enum pipe pipe, bool state)
1079{
1080 struct drm_device *dev = dev_priv->dev;
1081 bool cur_state;
1082
1083 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1084 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1085 else if (IS_845G(dev) || IS_I865G(dev))
1086 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1087 else
1088 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1089
1090 WARN(cur_state != state,
1091 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1092 pipe_name(pipe), state_string(state), state_string(cur_state));
1093}
1094#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1095#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1096
b840d907
JB		 1097void assert_pipe(struct drm_i915_private *dev_priv,
1098 enum pipe pipe, bool state)
b24e7179
JB		 1099{
1100 int reg;
1101 u32 val;
63d7bbe9 1102 bool cur_state;
702e7a56
PZ		 1103 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1104 pipe);
b24e7179 1105
8e636784
DV		 1106 /* if we need the pipe A quirk it must be always on */
1107 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1108 state = true;
1109
b97186f0
PZ		 1110 if (!intel_display_power_enabled(dev_priv->dev,
1111 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1112 cur_state = false;
1113 } else {
1114 reg = PIPECONF(cpu_transcoder);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & PIPECONF_ENABLE);
1117 }
1118
63d7bbe9
JB		 1119 WARN(cur_state != state,
1120 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1121 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1122}
1123
931872fc
CW		 1124static void assert_plane(struct drm_i915_private *dev_priv,
1125 enum plane plane, bool state)
b24e7179
JB		 1126{
1127 int reg;
1128 u32 val;
931872fc 1129 bool cur_state;
b24e7179
JB		 1130
1131 reg = DSPCNTR(plane);
1132 val = I915_READ(reg);
931872fc
CW		 1133 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1134 WARN(cur_state != state,
1135 "plane %c assertion failure (expected %s, current %s)\n",
1136 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1137}
1138
931872fc
CW		 1139#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1140#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1141
b24e7179
JB		 1142static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1143 enum pipe pipe)
1144{
653e1026 1145 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1146 int reg, i;
1147 u32 val;
1148 int cur_pipe;
1149
653e1026
VS		 1150 /* Primary planes are fixed to pipes on gen4+ */
1151 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1152 reg = DSPCNTR(pipe);
1153 val = I915_READ(reg);
1154 WARN((val & DISPLAY_PLANE_ENABLE),
1155 "plane %c assertion failure, should be disabled but not\n",
1156 plane_name(pipe));
19ec1358 1157 return;
28c05794 1158 }
19ec1358 1159
b24e7179 1160 /* Need to check both planes against the pipe */
08e2a7de 1161 for_each_pipe(i) {
b24e7179
JB		 1162 reg = DSPCNTR(i);
1163 val = I915_READ(reg);
1164 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1165 DISPPLANE_SEL_PIPE_SHIFT;
1166 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1167 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1168 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1169 }
1170}
1171
19332d7a
JB		 1172static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1173 enum pipe pipe)
1174{
20674eef 1175 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1176 int reg, i;
1177 u32 val;
1178
20674eef
VS		 1179 if (IS_VALLEYVIEW(dev)) {
1180 for (i = 0; i < dev_priv->num_plane; i++) {
1181 reg = SPCNTR(pipe, i);
1182 val = I915_READ(reg);
1183 WARN((val & SP_ENABLE),
1184 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1185 sprite_name(pipe, i), pipe_name(pipe));
1186 }
1187 } else if (INTEL_INFO(dev)->gen >= 7) {
1188 reg = SPRCTL(pipe);
19332d7a 1189 val = I915_READ(reg);
20674eef 1190 WARN((val & SPRITE_ENABLE),
06da8da2 1191 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1192 plane_name(pipe), pipe_name(pipe));
1193 } else if (INTEL_INFO(dev)->gen >= 5) {
1194 reg = DVSCNTR(pipe);
19332d7a 1195 val = I915_READ(reg);
20674eef 1196 WARN((val & DVS_ENABLE),
06da8da2 1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1198 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1199 }
1200}
1201
92f2584a
JB		 1202static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1203{
1204 u32 val;
1205 bool enabled;
1206
9d82aa17
ED		 1207 if (HAS_PCH_LPT(dev_priv->dev)) {
1208 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1209 return;
1210 }
1211
92f2584a
JB		 1212 val = I915_READ(PCH_DREF_CONTROL);
1213 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1214 DREF_SUPERSPREAD_SOURCE_MASK));
1215 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1216}
1217
ab9412ba
DV		 1218static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe)
92f2584a
JB		 1220{
1221 int reg;
1222 u32 val;
1223 bool enabled;
1224
ab9412ba 1225 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1226 val = I915_READ(reg);
1227 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1228 WARN(enabled,
1229 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1230 pipe_name(pipe));
92f2584a
JB		 1231}
1232
4e634389
KP		 1233static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1234 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1235{
1236 if ((val & DP_PORT_EN) == 0)
1237 return false;
1238
1239 if (HAS_PCH_CPT(dev_priv->dev)) {
1240 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1241 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1242 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1243 return false;
1244 } else {
1245 if ((val & DP_PIPE_MASK) != (pipe << 30))
1246 return false;
1247 }
1248 return true;
1249}
1250
1519b995
KP		 1251static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, u32 val)
1253{
dc0fa718 1254 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1255 return false;
1256
1257 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1258 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1259 return false;
1260 } else {
dc0fa718 1261 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1262 return false;
1263 }
1264 return true;
1265}
1266
1267static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1268 enum pipe pipe, u32 val)
1269{
1270 if ((val & LVDS_PORT_EN) == 0)
1271 return false;
1272
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1275 return false;
1276 } else {
1277 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1278 return false;
1279 }
1280 return true;
1281}
1282
1283static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1284 enum pipe pipe, u32 val)
1285{
1286 if ((val & ADPA_DAC_ENABLE) == 0)
1287 return false;
1288 if (HAS_PCH_CPT(dev_priv->dev)) {
1289 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1290 return false;
1291 } else {
1292 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1293 return false;
1294 }
1295 return true;
1296}
1297
291906f1 1298static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1299 enum pipe pipe, int reg, u32 port_sel)
291906f1 1300{
47a05eca 1301 u32 val = I915_READ(reg);
4e634389 1302 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1303 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1304 reg, pipe_name(pipe));
de9a35ab 1305
75c5da27
DV		 1306 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1307 && (val & DP_PIPEB_SELECT),
de9a35ab 1308 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1309}
1310
1311static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1312 enum pipe pipe, int reg)
1313{
47a05eca 1314 u32 val = I915_READ(reg);
b70ad586 1315 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1316 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1317 reg, pipe_name(pipe));
de9a35ab 1318
dc0fa718 1319 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1320 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1321 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1322}
1323
1324static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe)
1326{
1327 int reg;
1328 u32 val;
291906f1 1329
f0575e92
KP		 1330 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1331 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1332 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1333
1334 reg = PCH_ADPA;
1335 val = I915_READ(reg);
b70ad586 1336 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1337 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1338 pipe_name(pipe));
291906f1
JB		 1339
1340 reg = PCH_LVDS;
1341 val = I915_READ(reg);
b70ad586 1342 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1343 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1344 pipe_name(pipe));
291906f1 1345
e2debe91
PZ		 1346 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1347 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1348 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1349}
1350
40e9cf64
JB		 1351static void intel_init_dpio(struct drm_device *dev)
1352{
1353 struct drm_i915_private *dev_priv = dev->dev_private;
1354
1355 if (!IS_VALLEYVIEW(dev))
1356 return;
1357
1358 /*
1359 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1360 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1361 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1362 * b. The other bits such as sfr settings / modesel may all be set
1363 * to 0.
1364 *
1365 * This should only be done on init and resume from S3 with both
1366 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1367 */
1368 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1369}
1370
426115cf 1371static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1372{
426115cf
DV		 1373 struct drm_device *dev = crtc->base.dev;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 int reg = DPLL(crtc->pipe);
1376 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1377
426115cf 1378 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1379
1380 /* No really, not for ILK+ */
1381 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1382
1383 /* PLL is protected by panel, make sure we can write it */
1384 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1385 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1386
426115cf
DV		 1387 I915_WRITE(reg, dpll);
1388 POSTING_READ(reg);
1389 udelay(150);
1390
1391 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1392 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1393
1394 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1395 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1396
1397 /* We do this three times for luck */
426115cf 1398 I915_WRITE(reg, dpll);
87442f73
DV		 1399 POSTING_READ(reg);
1400 udelay(150); /* wait for warmup */
426115cf 1401 I915_WRITE(reg, dpll);
87442f73
DV		 1402 POSTING_READ(reg);
1403 udelay(150); /* wait for warmup */
426115cf 1404 I915_WRITE(reg, dpll);
87442f73
DV		 1405 POSTING_READ(reg);
1406 udelay(150); /* wait for warmup */
1407}
1408
66e3d5c0 1409static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1410{
66e3d5c0
DV		 1411 struct drm_device *dev = crtc->base.dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 int reg = DPLL(crtc->pipe);
1414 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1415
66e3d5c0 1416 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1417
63d7bbe9 1418 /* No really, not for ILK+ */
87442f73 1419 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1420
1421 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1422 if (IS_MOBILE(dev) && !IS_I830(dev))
1423 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1424
66e3d5c0
DV		 1425 I915_WRITE(reg, dpll);
1426
1427 /* Wait for the clocks to stabilize. */
1428 POSTING_READ(reg);
1429 udelay(150);
1430
1431 if (INTEL_INFO(dev)->gen >= 4) {
1432 I915_WRITE(DPLL_MD(crtc->pipe),
1433 crtc->config.dpll_hw_state.dpll_md);
1434 } else {
1435 /* The pixel multiplier can only be updated once the
1436 * DPLL is enabled and the clocks are stable.
1437 *
1438 * So write it again.
1439 */
1440 I915_WRITE(reg, dpll);
1441 }
63d7bbe9
JB		 1442
1443 /* We do this three times for luck */
66e3d5c0 1444 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1445 POSTING_READ(reg);
1446 udelay(150); /* wait for warmup */
66e3d5c0 1447 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1448 POSTING_READ(reg);
1449 udelay(150); /* wait for warmup */
66e3d5c0 1450 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
1453}
1454
1455/**
50b44a44 1456 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1457 * @dev_priv: i915 private structure
1458 * @pipe: pipe PLL to disable
1459 *
1460 * Disable the PLL for @pipe, making sure the pipe is off first.
1461 *
1462 * Note! This is for pre-ILK only.
1463 */
50b44a44 1464static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1465{
63d7bbe9
JB		 1466 /* Don't disable pipe A or pipe A PLLs if needed */
1467 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1468 return;
1469
1470 /* Make sure the pipe isn't still relying on us */
1471 assert_pipe_disabled(dev_priv, pipe);
1472
50b44a44
DV		 1473 I915_WRITE(DPLL(pipe), 0);
1474 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1475}
1476
f6071166
JB		 1477static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478{
1479 u32 val = 0;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 /* Leave integrated clock source enabled */
1485 if (pipe == PIPE_B)
1486 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1487 I915_WRITE(DPLL(pipe), val);
1488 POSTING_READ(DPLL(pipe));
1489}
1490
89b667f8
JB		 1491void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1492{
1493 u32 port_mask;
1494
1495 if (!port)
1496 port_mask = DPLL_PORTB_READY_MASK;
1497 else
1498 port_mask = DPLL_PORTC_READY_MASK;
1499
1500 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1501 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1502 'B' + port, I915_READ(DPLL(0)));
1503}
1504
92f2584a 1505/**
e72f9fbf 1506 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1507 * @dev_priv: i915 private structure
1508 * @pipe: pipe PLL to enable
1509 *
1510 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1511 * drives the transcoder clock.
1512 */
e2b78267 1513static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1514{
e2b78267
DV		 1515 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1516 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1517
48da64a8 1518 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1519 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1520 if (WARN_ON(pll == NULL))
48da64a8
CW		 1521 return;
1522
1523 if (WARN_ON(pll->refcount == 0))
1524 return;
ee7b9f93 1525
46edb027
DV		 1526 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1527 pll->name, pll->active, pll->on,
e2b78267 1528 crtc->base.base.id);
92f2584a 1529
cdbd2316
DV		 1530 if (pll->active++) {
1531 WARN_ON(!pll->on);
e9d6944e 1532 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1533 return;
1534 }
f4a091c7 1535 WARN_ON(pll->on);
ee7b9f93 1536
46edb027 1537 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1538 pll->enable(dev_priv, pll);
ee7b9f93 1539 pll->on = true;
92f2584a
JB		 1540}
1541
e2b78267 1542static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1543{
e2b78267
DV		 1544 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1545 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1546
92f2584a
JB		 1547 /* PCH only available on ILK+ */
1548 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1549 if (WARN_ON(pll == NULL))
ee7b9f93 1550 return;
92f2584a 1551
48da64a8
CW		 1552 if (WARN_ON(pll->refcount == 0))
1553 return;
7a419866 1554
46edb027
DV		 1555 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1556 pll->name, pll->active, pll->on,
e2b78267 1557 crtc->base.base.id);
7a419866 1558
48da64a8 1559 if (WARN_ON(pll->active == 0)) {
e9d6944e 1560 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1561 return;
1562 }
1563
e9d6944e 1564 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1565 WARN_ON(!pll->on);
cdbd2316 1566 if (--pll->active)
7a419866 1567 return;
ee7b9f93 1568
46edb027 1569 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1570 pll->disable(dev_priv, pll);
ee7b9f93 1571 pll->on = false;
92f2584a
JB		 1572}
1573
b8a4f404
PZ		 1574static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1575 enum pipe pipe)
040484af 1576{
23670b32 1577 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1578 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1580 uint32_t reg, val, pipeconf_val;
040484af
JB		 1581
1582 /* PCH only available on ILK+ */
1583 BUG_ON(dev_priv->info->gen < 5);
1584
1585 /* Make sure PCH DPLL is enabled */
e72f9fbf 1586 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1587 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1588
1589 /* FDI must be feeding us bits for PCH ports */
1590 assert_fdi_tx_enabled(dev_priv, pipe);
1591 assert_fdi_rx_enabled(dev_priv, pipe);
1592
23670b32
DV		 1593 if (HAS_PCH_CPT(dev)) {
1594 /* Workaround: Set the timing override bit before enabling the
1595 * pch transcoder. */
1596 reg = TRANS_CHICKEN2(pipe);
1597 val = I915_READ(reg);
1598 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1599 I915_WRITE(reg, val);
59c859d6 1600 }
23670b32 1601
ab9412ba 1602 reg = PCH_TRANSCONF(pipe);
040484af 1603 val = I915_READ(reg);
5f7f726d 1604 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1605
1606 if (HAS_PCH_IBX(dev_priv->dev)) {
1607 /*
1608 * make the BPC in transcoder be consistent with
1609 * that in pipeconf reg.
1610 */
dfd07d72
DV		 1611 val &= ~PIPECONF_BPC_MASK;
1612 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1613 }
5f7f726d
PZ		 1614
1615 val &= ~TRANS_INTERLACE_MASK;
1616 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1617 if (HAS_PCH_IBX(dev_priv->dev) &&
1618 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1619 val |= TRANS_LEGACY_INTERLACED_ILK;
1620 else
1621 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1622 else
1623 val |= TRANS_PROGRESSIVE;
1624
040484af
JB		 1625 I915_WRITE(reg, val | TRANS_ENABLE);
1626 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1627 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1628}
1629
8fb033d7 1630static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1631 enum transcoder cpu_transcoder)
040484af 1632{
8fb033d7 1633 u32 val, pipeconf_val;
8fb033d7
PZ		 1634
1635 /* PCH only available on ILK+ */
1636 BUG_ON(dev_priv->info->gen < 5);
1637
8fb033d7 1638 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1639 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1640 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1641
223a6fdf
PZ		 1642 /* Workaround: set timing override bit. */
1643 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1644 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1645 I915_WRITE(_TRANSA_CHICKEN2, val);
1646
25f3ef11 1647 val = TRANS_ENABLE;
937bb610 1648 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1649
9a76b1c6
PZ		 1650 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1651 PIPECONF_INTERLACED_ILK)
a35f2679 1652 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1653 else
1654 val |= TRANS_PROGRESSIVE;
1655
ab9412ba
DV		 1656 I915_WRITE(LPT_TRANSCONF, val);
1657 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1658 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1659}
1660
b8a4f404
PZ		 1661static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
040484af 1663{
23670b32
DV		 1664 struct drm_device *dev = dev_priv->dev;
1665 uint32_t reg, val;
040484af
JB		 1666
1667 /* FDI relies on the transcoder */
1668 assert_fdi_tx_disabled(dev_priv, pipe);
1669 assert_fdi_rx_disabled(dev_priv, pipe);
1670
291906f1
JB		 1671 /* Ports must be off as well */
1672 assert_pch_ports_disabled(dev_priv, pipe);
1673
ab9412ba 1674 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1675 val = I915_READ(reg);
1676 val &= ~TRANS_ENABLE;
1677 I915_WRITE(reg, val);
1678 /* wait for PCH transcoder off, transcoder state */
1679 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1680 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1681
1682 if (!HAS_PCH_IBX(dev)) {
1683 /* Workaround: Clear the timing override chicken bit again. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1688 }
040484af
JB		 1689}
1690
ab4d966c 1691static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1692{
8fb033d7
PZ		 1693 u32 val;
1694
ab9412ba 1695 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1696 val &= ~TRANS_ENABLE;
ab9412ba 1697 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1698 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1699 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1700 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1701
1702 /* Workaround: clear timing override bit. */
1703 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1704 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1705 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1706}
1707
b24e7179 1708/**
309cfea8 1709 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1710 * @dev_priv: i915 private structure
1711 * @pipe: pipe to enable
040484af 1712 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1713 *
1714 * Enable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1716 *
1717 * @pipe should be %PIPE_A or %PIPE_B.
1718 *
1719 * Will wait until the pipe is actually running (i.e. first vblank) before
1720 * returning.
1721 */
040484af 1722static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1723 bool pch_port, bool dsi)
b24e7179 1724{
702e7a56
PZ		 1725 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1726 pipe);
1a240d4d 1727 enum pipe pch_transcoder;
b24e7179
JB		 1728 int reg;
1729 u32 val;
1730
58c6eaa2 1731 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1732 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1733 assert_sprites_disabled(dev_priv, pipe);
1734
681e5811 1735 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1736 pch_transcoder = TRANSCODER_A;
1737 else
1738 pch_transcoder = pipe;
1739
b24e7179
JB		 1740 /*
1741 * A pipe without a PLL won't actually be able to drive bits from
1742 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1743 * need the check.
1744 */
1745 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1746 if (dsi)
1747 assert_dsi_pll_enabled(dev_priv);
1748 else
1749 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1750 else {
1751 if (pch_port) {
1752 /* if driving the PCH, we need FDI enabled */
cc391bbb 1753 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1754 assert_fdi_tx_pll_enabled(dev_priv,
1755 (enum pipe) cpu_transcoder);
040484af
JB		 1756 }
1757 /* FIXME: assert CPU port conditions for SNB+ */
1758 }
b24e7179 1759
702e7a56 1760 reg = PIPECONF(cpu_transcoder);
b24e7179 1761 val = I915_READ(reg);
00d70b15
CW		 1762 if (val & PIPECONF_ENABLE)
1763 return;
1764
1765 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1766 intel_wait_for_vblank(dev_priv->dev, pipe);
1767}
1768
1769/**
309cfea8 1770 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1771 * @dev_priv: i915 private structure
1772 * @pipe: pipe to disable
1773 *
1774 * Disable @pipe, making sure that various hardware specific requirements
1775 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1776 *
1777 * @pipe should be %PIPE_A or %PIPE_B.
1778 *
1779 * Will wait until the pipe has shut down before returning.
1780 */
1781static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1782 enum pipe pipe)
1783{
702e7a56
PZ		 1784 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1785 pipe);
b24e7179
JB		 1786 int reg;
1787 u32 val;
1788
1789 /*
1790 * Make sure planes won't keep trying to pump pixels to us,
1791 * or we might hang the display.
1792 */
1793 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1794 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1795 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1796
1797 /* Don't disable pipe A or pipe A PLLs if needed */
1798 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1799 return;
1800
702e7a56 1801 reg = PIPECONF(cpu_transcoder);
b24e7179 1802 val = I915_READ(reg);
00d70b15
CW		 1803 if ((val & PIPECONF_ENABLE) == 0)
1804 return;
1805
1806 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1807 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1808}
1809
d74362c9
KP		 1810/*
1811 * Plane regs are double buffered, going from enabled->disabled needs a
1812 * trigger in order to latch. The display address reg provides this.
1813 */
6f1d69b0 1814void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1815 enum plane plane)
1816{
14f86147
DL		 1817 if (dev_priv->info->gen >= 4)
1818 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1819 else
1820 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1821}
1822
b24e7179
JB		 1823/**
1824 * intel_enable_plane - enable a display plane on a given pipe
1825 * @dev_priv: i915 private structure
1826 * @plane: plane to enable
1827 * @pipe: pipe being fed
1828 *
1829 * Enable @plane on @pipe, making sure that @pipe is running first.
1830 */
1831static void intel_enable_plane(struct drm_i915_private *dev_priv,
1832 enum plane plane, enum pipe pipe)
1833{
1834 int reg;
1835 u32 val;
1836
1837 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1838 assert_pipe_enabled(dev_priv, pipe);
1839
1840 reg = DSPCNTR(plane);
1841 val = I915_READ(reg);
00d70b15
CW		 1842 if (val & DISPLAY_PLANE_ENABLE)
1843 return;
1844
1845 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1846 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
b24e7179
JB		 1850/**
1851 * intel_disable_plane - disable a display plane
1852 * @dev_priv: i915 private structure
1853 * @plane: plane to disable
1854 * @pipe: pipe consuming the data
1855 *
1856 * Disable @plane; should be an independent operation.
1857 */
1858static void intel_disable_plane(struct drm_i915_private *dev_priv,
1859 enum plane plane, enum pipe pipe)
1860{
1861 int reg;
1862 u32 val;
1863
1864 reg = DSPCNTR(plane);
1865 val = I915_READ(reg);
00d70b15
CW		 1866 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1867 return;
1868
1869 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1870 intel_flush_display_plane(dev_priv, plane);
1871 intel_wait_for_vblank(dev_priv->dev, pipe);
1872}
1873
693db184
CW		 1874static bool need_vtd_wa(struct drm_device *dev)
1875{
1876#ifdef CONFIG_INTEL_IOMMU
1877 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1878 return true;
1879#endif
1880 return false;
1881}
1882
127bd2ac 1883int
48b956c5 1884intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1885 struct drm_i915_gem_object *obj,
919926ae 1886 struct intel_ring_buffer *pipelined)
6b95a207 1887{
ce453d81 1888 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1889 u32 alignment;
1890 int ret;
1891
05394f39 1892 switch (obj->tiling_mode) {
6b95a207 1893 case I915_TILING_NONE:
534843da
CW		 1894 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1895 alignment = 128 * 1024;
a6c45cf0 1896 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1897 alignment = 4 * 1024;
1898 else
1899 alignment = 64 * 1024;
6b95a207
KH		 1900 break;
1901 case I915_TILING_X:
1902 /* pin() will align the object as required by fence */
1903 alignment = 0;
1904 break;
1905 case I915_TILING_Y:
8bb6e959
DV		 1906 /* Despite that we check this in framebuffer_init userspace can
1907 * screw us over and change the tiling after the fact. Only
1908 * pinned buffers can't change their tiling. */
1909 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1910 return -EINVAL;
1911 default:
1912 BUG();
1913 }
1914
693db184
CW		 1915 /* Note that the w/a also requires 64 PTE of padding following the
1916 * bo. We currently fill all unused PTE with the shadow page and so
1917 * we should always have valid PTE following the scanout preventing
1918 * the VT-d warning.
1919 */
1920 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1921 alignment = 256 * 1024;
1922
ce453d81 1923 dev_priv->mm.interruptible = false;
2da3b9b9 1924 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1925 if (ret)
ce453d81 1926 goto err_interruptible;
6b95a207
KH		 1927
1928 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1929 * fence, whereas 965+ only requires a fence if using
1930 * framebuffer compression. For simplicity, we always install
1931 * a fence as the cost is not that onerous.
1932 */
06d98131 1933 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1934 if (ret)
1935 goto err_unpin;
1690e1eb 1936
9a5a53b3 1937 i915_gem_object_pin_fence(obj);
6b95a207 1938
ce453d81 1939 dev_priv->mm.interruptible = true;
6b95a207 1940 return 0;
48b956c5
CW		 1941
1942err_unpin:
cc98b413 1943 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1944err_interruptible:
1945 dev_priv->mm.interruptible = true;
48b956c5 1946 return ret;
6b95a207
KH		 1947}
1948
1690e1eb
CW		 1949void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1950{
1951 i915_gem_object_unpin_fence(obj);
cc98b413 1952 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1953}
1954
c2c75131
DV		 1955/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1956 * is assumed to be a power-of-two. */
bc752862
CW		 1957unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1958 unsigned int tiling_mode,
1959 unsigned int cpp,
1960 unsigned int pitch)
c2c75131 1961{
bc752862
CW		 1962 if (tiling_mode != I915_TILING_NONE) {
1963 unsigned int tile_rows, tiles;
c2c75131 1964
bc752862
CW		 1965 tile_rows = *y / 8;
1966 *y %= 8;
c2c75131 1967
bc752862
CW		 1968 tiles = *x / (512/cpp);
1969 *x %= 512/cpp;
1970
1971 return tile_rows * pitch * 8 + tiles * 4096;
1972 } else {
1973 unsigned int offset;
1974
1975 offset = *y * pitch + *x * cpp;
1976 *y = 0;
1977 *x = (offset & 4095) / cpp;
1978 return offset & -4096;
1979 }
c2c75131
DV		 1980}
1981
17638cd6
JB		 1982static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1983 int x, int y)
81255565
JB		 1984{
1985 struct drm_device *dev = crtc->dev;
1986 struct drm_i915_private *dev_priv = dev->dev_private;
1987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1988 struct intel_framebuffer *intel_fb;
05394f39 1989 struct drm_i915_gem_object *obj;
81255565 1990 int plane = intel_crtc->plane;
e506a0c6 1991 unsigned long linear_offset;
81255565 1992 u32 dspcntr;
5eddb70b 1993 u32 reg;
81255565
JB		 1994
1995 switch (plane) {
1996 case 0:
1997 case 1:
1998 break;
1999 default:
84f44ce7 2000 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2001 return -EINVAL;
2002 }
2003
2004 intel_fb = to_intel_framebuffer(fb);
2005 obj = intel_fb->obj;
81255565 2006
5eddb70b
CW		 2007 reg = DSPCNTR(plane);
2008 dspcntr = I915_READ(reg);
81255565
JB		 2009 /* Mask out pixel format bits in case we change it */
2010 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2011 switch (fb->pixel_format) {
2012 case DRM_FORMAT_C8:
81255565
JB		 2013 dspcntr |= DISPPLANE_8BPP;
2014 break;
57779d06
VS		 2015 case DRM_FORMAT_XRGB1555:
2016 case DRM_FORMAT_ARGB1555:
2017 dspcntr |= DISPPLANE_BGRX555;
81255565 2018 break;
57779d06
VS		 2019 case DRM_FORMAT_RGB565:
2020 dspcntr |= DISPPLANE_BGRX565;
2021 break;
2022 case DRM_FORMAT_XRGB8888:
2023 case DRM_FORMAT_ARGB8888:
2024 dspcntr |= DISPPLANE_BGRX888;
2025 break;
2026 case DRM_FORMAT_XBGR8888:
2027 case DRM_FORMAT_ABGR8888:
2028 dspcntr |= DISPPLANE_RGBX888;
2029 break;
2030 case DRM_FORMAT_XRGB2101010:
2031 case DRM_FORMAT_ARGB2101010:
2032 dspcntr |= DISPPLANE_BGRX101010;
2033 break;
2034 case DRM_FORMAT_XBGR2101010:
2035 case DRM_FORMAT_ABGR2101010:
2036 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2037 break;
2038 default:
baba133a 2039 BUG();
81255565 2040 }
57779d06 2041
a6c45cf0 2042 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2043 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2044 dspcntr |= DISPPLANE_TILED;
2045 else
2046 dspcntr &= ~DISPPLANE_TILED;
2047 }
2048
de1aa629
VS		 2049 if (IS_G4X(dev))
2050 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2051
5eddb70b 2052 I915_WRITE(reg, dspcntr);
81255565 2053
e506a0c6 2054 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2055
c2c75131
DV		 2056 if (INTEL_INFO(dev)->gen >= 4) {
2057 intel_crtc->dspaddr_offset =
bc752862
CW		 2058 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2059 fb->bits_per_pixel / 8,
2060 fb->pitches[0]);
c2c75131
DV		 2061 linear_offset -= intel_crtc->dspaddr_offset;
2062 } else {
e506a0c6 2063 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2064 }
e506a0c6 2065
f343c5f6
BW		 2066 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2067 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2068 fb->pitches[0]);
01f2c773 2069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2070 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2071 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2072 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2073 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2074 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2075 } else
f343c5f6 2076 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2077 POSTING_READ(reg);
81255565 2078
17638cd6
JB		 2079 return 0;
2080}
2081
2082static int ironlake_update_plane(struct drm_crtc *crtc,
2083 struct drm_framebuffer *fb, int x, int y)
2084{
2085 struct drm_device *dev = crtc->dev;
2086 struct drm_i915_private *dev_priv = dev->dev_private;
2087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2088 struct intel_framebuffer *intel_fb;
2089 struct drm_i915_gem_object *obj;
2090 int plane = intel_crtc->plane;
e506a0c6 2091 unsigned long linear_offset;
17638cd6
JB		 2092 u32 dspcntr;
2093 u32 reg;
2094
2095 switch (plane) {
2096 case 0:
2097 case 1:
27f8227b 2098 case 2:
17638cd6
JB		 2099 break;
2100 default:
84f44ce7 2101 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2102 return -EINVAL;
2103 }
2104
2105 intel_fb = to_intel_framebuffer(fb);
2106 obj = intel_fb->obj;
2107
2108 reg = DSPCNTR(plane);
2109 dspcntr = I915_READ(reg);
2110 /* Mask out pixel format bits in case we change it */
2111 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2112 switch (fb->pixel_format) {
2113 case DRM_FORMAT_C8:
17638cd6
JB		 2114 dspcntr |= DISPPLANE_8BPP;
2115 break;
57779d06
VS		 2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2118 break;
57779d06
VS		 2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2134 break;
2135 default:
baba133a 2136 BUG();
17638cd6
JB		 2137 }
2138
2139 if (obj->tiling_mode != I915_TILING_NONE)
2140 dspcntr |= DISPPLANE_TILED;
2141 else
2142 dspcntr &= ~DISPPLANE_TILED;
2143
1f5d76db
PZ		 2144 if (IS_HASWELL(dev))
2145 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2146 else
2147 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2148
2149 I915_WRITE(reg, dspcntr);
2150
e506a0c6 2151 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2152 intel_crtc->dspaddr_offset =
bc752862
CW		 2153 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2154 fb->bits_per_pixel / 8,
2155 fb->pitches[0]);
c2c75131 2156 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2157
f343c5f6
BW		 2158 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2159 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2160 fb->pitches[0]);
01f2c773 2161 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2162 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2163 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2164 if (IS_HASWELL(dev)) {
2165 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2166 } else {
2167 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2168 I915_WRITE(DSPLINOFF(plane), linear_offset);
2169 }
17638cd6
JB		 2170 POSTING_READ(reg);
2171
2172 return 0;
2173}
2174
2175/* Assume fb object is pinned & idle & fenced and just update base pointers */
2176static int
2177intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2178 int x, int y, enum mode_set_atomic state)
2179{
2180 struct drm_device *dev = crtc->dev;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2182
6b8e6ed0
CW		 2183 if (dev_priv->display.disable_fbc)
2184 dev_priv->display.disable_fbc(dev);
3dec0095 2185 intel_increase_pllclock(crtc);
81255565 2186
6b8e6ed0 2187 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2188}
2189
96a02917
VS		 2190void intel_display_handle_reset(struct drm_device *dev)
2191{
2192 struct drm_i915_private *dev_priv = dev->dev_private;
2193 struct drm_crtc *crtc;
2194
2195 /*
2196 * Flips in the rings have been nuked by the reset,
2197 * so complete all pending flips so that user space
2198 * will get its events and not get stuck.
2199 *
2200 * Also update the base address of all primary
2201 * planes to the the last fb to make sure we're
2202 * showing the correct fb after a reset.
2203 *
2204 * Need to make two loops over the crtcs so that we
2205 * don't try to grab a crtc mutex before the
2206 * pending_flip_queue really got woken up.
2207 */
2208
2209 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2211 enum plane plane = intel_crtc->plane;
2212
2213 intel_prepare_page_flip(dev, plane);
2214 intel_finish_page_flip_plane(dev, plane);
2215 }
2216
2217 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2219
2220 mutex_lock(&crtc->mutex);
2221 if (intel_crtc->active)
2222 dev_priv->display.update_plane(crtc, crtc->fb,
2223 crtc->x, crtc->y);
2224 mutex_unlock(&crtc->mutex);
2225 }
2226}
2227
14667a4b
CW		 2228static int
2229intel_finish_fb(struct drm_framebuffer *old_fb)
2230{
2231 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2232 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2233 bool was_interruptible = dev_priv->mm.interruptible;
2234 int ret;
2235
14667a4b
CW		 2236 /* Big Hammer, we also need to ensure that any pending
2237 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2238 * current scanout is retired before unpinning the old
2239 * framebuffer.
2240 *
2241 * This should only fail upon a hung GPU, in which case we
2242 * can safely continue.
2243 */
2244 dev_priv->mm.interruptible = false;
2245 ret = i915_gem_object_finish_gpu(obj);
2246 dev_priv->mm.interruptible = was_interruptible;
2247
2248 return ret;
2249}
2250
198598d0
VS		 2251static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2252{
2253 struct drm_device *dev = crtc->dev;
2254 struct drm_i915_master_private *master_priv;
2255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2256
2257 if (!dev->primary->master)
2258 return;
2259
2260 master_priv = dev->primary->master->driver_priv;
2261 if (!master_priv->sarea_priv)
2262 return;
2263
2264 switch (intel_crtc->pipe) {
2265 case 0:
2266 master_priv->sarea_priv->pipeA_x = x;
2267 master_priv->sarea_priv->pipeA_y = y;
2268 break;
2269 case 1:
2270 master_priv->sarea_priv->pipeB_x = x;
2271 master_priv->sarea_priv->pipeB_y = y;
2272 break;
2273 default:
2274 break;
2275 }
2276}
2277
5c3b82e2 2278static int
3c4fdcfb 2279intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2280 struct drm_framebuffer *fb)
79e53945
JB		 2281{
2282 struct drm_device *dev = crtc->dev;
6b8e6ed0 2283 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2285 struct drm_framebuffer *old_fb;
5c3b82e2 2286 int ret;
79e53945
JB		 2287
2288 /* no fb bound */
94352cf9 2289 if (!fb) {
a5071c2f 2290 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2291 return 0;
2292 }
2293
7eb552ae 2294 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2295 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2296 plane_name(intel_crtc->plane),
2297 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2298 return -EINVAL;
79e53945
JB		 2299 }
2300
5c3b82e2 2301 mutex_lock(&dev->struct_mutex);
265db958 2302 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2303 to_intel_framebuffer(fb)->obj,
919926ae 2304 NULL);
5c3b82e2
CW		 2305 if (ret != 0) {
2306 mutex_unlock(&dev->struct_mutex);
a5071c2f 2307 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2308 return ret;
2309 }
79e53945 2310
bb2043de
DL		 2311 /*
2312 * Update pipe size and adjust fitter if needed: the reason for this is
2313 * that in compute_mode_changes we check the native mode (not the pfit
2314 * mode) to see if we can flip rather than do a full mode set. In the
2315 * fastboot case, we'll flip, but if we don't update the pipesrc and
2316 * pfit state, we'll end up with a big fb scanned out into the wrong
2317 * sized surface.
2318 *
2319 * To fix this properly, we need to hoist the checks up into
2320 * compute_mode_changes (or above), check the actual pfit state and
2321 * whether the platform allows pfit disable with pipe active, and only
2322 * then update the pipesrc and pfit state, even on the flip path.
2323 */
4d6a3e63 2324 if (i915_fastboot) {
d7bf63f2
DL		 2325 const struct drm_display_mode *adjusted_mode =
2326 &intel_crtc->config.adjusted_mode;
2327
4d6a3e63 2328 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2329 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2330 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2331 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2332 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2333 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2334 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2335 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2336 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2337 }
2338 }
2339
94352cf9 2340 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2341 if (ret) {
94352cf9 2342 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2343 mutex_unlock(&dev->struct_mutex);
a5071c2f 2344 DRM_ERROR("failed to update base address\n");
4e6cfefc 2345 return ret;
79e53945 2346 }
3c4fdcfb 2347
94352cf9
DV		 2348 old_fb = crtc->fb;
2349 crtc->fb = fb;
6c4c86f5
DV		 2350 crtc->x = x;
2351 crtc->y = y;
94352cf9 2352
b7f1de28 2353 if (old_fb) {
d7697eea
DV		 2354 if (intel_crtc->active && old_fb != fb)
2355 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2356 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2357 }
652c393a 2358
6b8e6ed0 2359 intel_update_fbc(dev);
4906557e 2360 intel_edp_psr_update(dev);
5c3b82e2 2361 mutex_unlock(&dev->struct_mutex);
79e53945 2362
198598d0 2363 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2364
2365 return 0;
79e53945
JB		 2366}
2367
5e84e1a4
ZW		 2368static void intel_fdi_normal_train(struct drm_crtc *crtc)
2369{
2370 struct drm_device *dev = crtc->dev;
2371 struct drm_i915_private *dev_priv = dev->dev_private;
2372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2373 int pipe = intel_crtc->pipe;
2374 u32 reg, temp;
2375
2376 /* enable normal train */
2377 reg = FDI_TX_CTL(pipe);
2378 temp = I915_READ(reg);
61e499bf 2379 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2380 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2381 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2382 } else {
2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2385 }
5e84e1a4
ZW		 2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 if (HAS_PCH_CPT(dev)) {
2391 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2392 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2393 } else {
2394 temp &= ~FDI_LINK_TRAIN_NONE;
2395 temp |= FDI_LINK_TRAIN_NONE;
2396 }
2397 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2398
2399 /* wait one idle pattern time */
2400 POSTING_READ(reg);
2401 udelay(1000);
357555c0
JB		 2402
2403 /* IVB wants error correction enabled */
2404 if (IS_IVYBRIDGE(dev))
2405 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2406 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2407}
2408
1e833f40
DV		 2409static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2410{
2411 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2412}
2413
01a415fd
DV		 2414static void ivb_modeset_global_resources(struct drm_device *dev)
2415{
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417 struct intel_crtc *pipe_B_crtc =
2418 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2419 struct intel_crtc *pipe_C_crtc =
2420 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2421 uint32_t temp;
2422
1e833f40
DV		 2423 /*
2424 * When everything is off disable fdi C so that we could enable fdi B
2425 * with all lanes. Note that we don't care about enabled pipes without
2426 * an enabled pch encoder.
2427 */
2428 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2429 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2430 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2431 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2432
2433 temp = I915_READ(SOUTH_CHICKEN1);
2434 temp &= ~FDI_BC_BIFURCATION_SELECT;
2435 DRM_DEBUG_KMS("disabling fdi C rx\n");
2436 I915_WRITE(SOUTH_CHICKEN1, temp);
2437 }
2438}
2439
8db9d77b
ZW		 2440/* The FDI link training functions for ILK/Ibexpeak. */
2441static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2442{
2443 struct drm_device *dev = crtc->dev;
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2446 int pipe = intel_crtc->pipe;
0fc932b8 2447 int plane = intel_crtc->plane;
5eddb70b 2448 u32 reg, temp, tries;
8db9d77b 2449
0fc932b8
JB		 2450 /* FDI needs bits from pipe & plane first */
2451 assert_pipe_enabled(dev_priv, pipe);
2452 assert_plane_enabled(dev_priv, plane);
2453
e1a44743
AJ		 2454 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2455 for train result */
5eddb70b
CW		 2456 reg = FDI_RX_IMR(pipe);
2457 temp = I915_READ(reg);
e1a44743
AJ		 2458 temp &= ~FDI_RX_SYMBOL_LOCK;
2459 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2460 I915_WRITE(reg, temp);
2461 I915_READ(reg);
e1a44743
AJ		 2462 udelay(150);
2463
8db9d77b 2464 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
627eb5a3
DV		 2467 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2468 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2469 temp &= ~FDI_LINK_TRAIN_NONE;
2470 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2471 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2472
5eddb70b
CW		 2473 reg = FDI_RX_CTL(pipe);
2474 temp = I915_READ(reg);
8db9d77b
ZW		 2475 temp &= ~FDI_LINK_TRAIN_NONE;
2476 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2477 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2478
2479 POSTING_READ(reg);
8db9d77b
ZW		 2480 udelay(150);
2481
5b2adf89 2482 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2483 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2484 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2485 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2486
5eddb70b 2487 reg = FDI_RX_IIR(pipe);
e1a44743 2488 for (tries = 0; tries < 5; tries++) {
5eddb70b 2489 temp = I915_READ(reg);
8db9d77b
ZW		 2490 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2491
2492 if ((temp & FDI_RX_BIT_LOCK)) {
2493 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2494 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2495 break;
2496 }
8db9d77b 2497 }
e1a44743 2498 if (tries == 5)
5eddb70b 2499 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2500
2501 /* Train 2 */
5eddb70b
CW		 2502 reg = FDI_TX_CTL(pipe);
2503 temp = I915_READ(reg);
8db9d77b
ZW		 2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2506 I915_WRITE(reg, temp);
8db9d77b 2507
5eddb70b
CW		 2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 temp &= ~FDI_LINK_TRAIN_NONE;
2511 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2512 I915_WRITE(reg, temp);
8db9d77b 2513
5eddb70b
CW		 2514 POSTING_READ(reg);
2515 udelay(150);
8db9d77b 2516
5eddb70b 2517 reg = FDI_RX_IIR(pipe);
e1a44743 2518 for (tries = 0; tries < 5; tries++) {
5eddb70b 2519 temp = I915_READ(reg);
8db9d77b
ZW		 2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521
2522 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2523 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2524 DRM_DEBUG_KMS("FDI train 2 done.\n");
2525 break;
2526 }
8db9d77b 2527 }
e1a44743 2528 if (tries == 5)
5eddb70b 2529 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2530
2531 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2532
8db9d77b
ZW		 2533}
2534
0206e353 2535static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2536 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2537 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2538 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2539 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2540};
2541
2542/* The FDI link training functions for SNB/Cougarpoint. */
2543static void gen6_fdi_link_train(struct drm_crtc *crtc)
2544{
2545 struct drm_device *dev = crtc->dev;
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2548 int pipe = intel_crtc->pipe;
fa37d39e 2549 u32 reg, temp, i, retry;
8db9d77b 2550
e1a44743
AJ		 2551 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2552 for train result */
5eddb70b
CW		 2553 reg = FDI_RX_IMR(pipe);
2554 temp = I915_READ(reg);
e1a44743
AJ		 2555 temp &= ~FDI_RX_SYMBOL_LOCK;
2556 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2557 I915_WRITE(reg, temp);
2558
2559 POSTING_READ(reg);
e1a44743
AJ		 2560 udelay(150);
2561
8db9d77b 2562 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
627eb5a3
DV		 2565 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2566 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2567 temp &= ~FDI_LINK_TRAIN_NONE;
2568 temp |= FDI_LINK_TRAIN_PATTERN_1;
2569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2570 /* SNB-B */
2571 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2572 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2573
d74cf324
DV		 2574 I915_WRITE(FDI_RX_MISC(pipe),
2575 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2576
5eddb70b
CW		 2577 reg = FDI_RX_CTL(pipe);
2578 temp = I915_READ(reg);
8db9d77b
ZW		 2579 if (HAS_PCH_CPT(dev)) {
2580 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2581 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2582 } else {
2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 }
5eddb70b
CW		 2586 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2587
2588 POSTING_READ(reg);
8db9d77b
ZW		 2589 udelay(150);
2590
0206e353 2591 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2592 reg = FDI_TX_CTL(pipe);
2593 temp = I915_READ(reg);
8db9d77b
ZW		 2594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2595 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
8db9d77b
ZW		 2599 udelay(500);
2600
fa37d39e
SP		 2601 for (retry = 0; retry < 5; retry++) {
2602 reg = FDI_RX_IIR(pipe);
2603 temp = I915_READ(reg);
2604 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2605 if (temp & FDI_RX_BIT_LOCK) {
2606 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2607 DRM_DEBUG_KMS("FDI train 1 done.\n");
2608 break;
2609 }
2610 udelay(50);
8db9d77b 2611 }
fa37d39e
SP		 2612 if (retry < 5)
2613 break;
8db9d77b
ZW		 2614 }
2615 if (i == 4)
5eddb70b 2616 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2617
2618 /* Train 2 */
5eddb70b
CW		 2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
8db9d77b
ZW		 2621 temp &= ~FDI_LINK_TRAIN_NONE;
2622 temp |= FDI_LINK_TRAIN_PATTERN_2;
2623 if (IS_GEN6(dev)) {
2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 /* SNB-B */
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627 }
5eddb70b 2628 I915_WRITE(reg, temp);
8db9d77b 2629
5eddb70b
CW		 2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
8db9d77b
ZW		 2632 if (HAS_PCH_CPT(dev)) {
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2635 } else {
2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2;
2638 }
5eddb70b
CW		 2639 I915_WRITE(reg, temp);
2640
2641 POSTING_READ(reg);
8db9d77b
ZW		 2642 udelay(150);
2643
0206e353 2644 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
8db9d77b
ZW		 2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
8db9d77b
ZW		 2652 udelay(500);
2653
fa37d39e
SP		 2654 for (retry = 0; retry < 5; retry++) {
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658 if (temp & FDI_RX_SYMBOL_LOCK) {
2659 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2660 DRM_DEBUG_KMS("FDI train 2 done.\n");
2661 break;
2662 }
2663 udelay(50);
8db9d77b 2664 }
fa37d39e
SP		 2665 if (retry < 5)
2666 break;
8db9d77b
ZW		 2667 }
2668 if (i == 4)
5eddb70b 2669 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2670
2671 DRM_DEBUG_KMS("FDI train done.\n");
2672}
2673
357555c0
JB		 2674/* Manual link training for Ivy Bridge A0 parts */
2675static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2676{
2677 struct drm_device *dev = crtc->dev;
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2680 int pipe = intel_crtc->pipe;
139ccd3f 2681 u32 reg, temp, i, j;
357555c0
JB		 2682
2683 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2684 for train result */
2685 reg = FDI_RX_IMR(pipe);
2686 temp = I915_READ(reg);
2687 temp &= ~FDI_RX_SYMBOL_LOCK;
2688 temp &= ~FDI_RX_BIT_LOCK;
2689 I915_WRITE(reg, temp);
2690
2691 POSTING_READ(reg);
2692 udelay(150);
2693
01a415fd
DV		 2694 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2695 I915_READ(FDI_RX_IIR(pipe)));
2696
139ccd3f
JB		 2697 /* Try each vswing and preemphasis setting twice before moving on */
2698 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2699 /* disable first in case we need to retry */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2703 temp &= ~FDI_TX_ENABLE;
2704 I915_WRITE(reg, temp);
357555c0 2705
139ccd3f
JB		 2706 reg = FDI_RX_CTL(pipe);
2707 temp = I915_READ(reg);
2708 temp &= ~FDI_LINK_TRAIN_AUTO;
2709 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2710 temp &= ~FDI_RX_ENABLE;
2711 I915_WRITE(reg, temp);
357555c0 2712
139ccd3f 2713 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2714 reg = FDI_TX_CTL(pipe);
2715 temp = I915_READ(reg);
139ccd3f
JB		 2716 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2717 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2718 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2720 temp |= snb_b_fdi_train_param[j/2];
2721 temp |= FDI_COMPOSITE_SYNC;
2722 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2723
139ccd3f
JB		 2724 I915_WRITE(FDI_RX_MISC(pipe),
2725 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2726
139ccd3f 2727 reg = FDI_RX_CTL(pipe);
357555c0 2728 temp = I915_READ(reg);
139ccd3f
JB		 2729 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2730 temp |= FDI_COMPOSITE_SYNC;
2731 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2732
139ccd3f
JB		 2733 POSTING_READ(reg);
2734 udelay(1); /* should be 0.5us */
357555c0 2735
139ccd3f
JB		 2736 for (i = 0; i < 4; i++) {
2737 reg = FDI_RX_IIR(pipe);
2738 temp = I915_READ(reg);
2739 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2740
139ccd3f
JB		 2741 if (temp & FDI_RX_BIT_LOCK ||
2742 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2743 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2744 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2745 i);
2746 break;
2747 }
2748 udelay(1); /* should be 0.5us */
2749 }
2750 if (i == 4) {
2751 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2752 continue;
2753 }
357555c0 2754
139ccd3f 2755 /* Train 2 */
357555c0
JB		 2756 reg = FDI_TX_CTL(pipe);
2757 temp = I915_READ(reg);
139ccd3f
JB		 2758 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2759 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2760 I915_WRITE(reg, temp);
2761
2762 reg = FDI_RX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2765 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2766 I915_WRITE(reg, temp);
2767
2768 POSTING_READ(reg);
139ccd3f 2769 udelay(2); /* should be 1.5us */
357555c0 2770
139ccd3f
JB		 2771 for (i = 0; i < 4; i++) {
2772 reg = FDI_RX_IIR(pipe);
2773 temp = I915_READ(reg);
2774 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2775
139ccd3f
JB		 2776 if (temp & FDI_RX_SYMBOL_LOCK ||
2777 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2778 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2779 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2780 i);
2781 goto train_done;
2782 }
2783 udelay(2); /* should be 1.5us */
357555c0 2784 }
139ccd3f
JB		 2785 if (i == 4)
2786 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2787 }
357555c0 2788
139ccd3f 2789train_done:
357555c0
JB		 2790 DRM_DEBUG_KMS("FDI train done.\n");
2791}
2792
88cefb6c 2793static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2794{
88cefb6c 2795 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2796 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2797 int pipe = intel_crtc->pipe;
5eddb70b 2798 u32 reg, temp;
79e53945 2799
c64e311e 2800
c98e9dcf 2801 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2802 reg = FDI_RX_CTL(pipe);
2803 temp = I915_READ(reg);
627eb5a3
DV		 2804 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2805 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2806 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2807 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2808
2809 POSTING_READ(reg);
c98e9dcf
JB		 2810 udelay(200);
2811
2812 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2813 temp = I915_READ(reg);
2814 I915_WRITE(reg, temp | FDI_PCDCLK);
2815
2816 POSTING_READ(reg);
c98e9dcf
JB		 2817 udelay(200);
2818
20749730
PZ		 2819 /* Enable CPU FDI TX PLL, always on for Ironlake */
2820 reg = FDI_TX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2823 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2824
20749730
PZ		 2825 POSTING_READ(reg);
2826 udelay(100);
6be4a607 2827 }
0e23b99d
JB		 2828}
2829
88cefb6c
DV		 2830static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2831{
2832 struct drm_device *dev = intel_crtc->base.dev;
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834 int pipe = intel_crtc->pipe;
2835 u32 reg, temp;
2836
2837 /* Switch from PCDclk to Rawclk */
2838 reg = FDI_RX_CTL(pipe);
2839 temp = I915_READ(reg);
2840 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2841
2842 /* Disable CPU FDI TX PLL */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2846
2847 POSTING_READ(reg);
2848 udelay(100);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2853
2854 /* Wait for the clocks to turn off. */
2855 POSTING_READ(reg);
2856 udelay(100);
2857}
2858
0fc932b8
JB		 2859static void ironlake_fdi_disable(struct drm_crtc *crtc)
2860{
2861 struct drm_device *dev = crtc->dev;
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864 int pipe = intel_crtc->pipe;
2865 u32 reg, temp;
2866
2867 /* disable CPU FDI tx and PCH FDI rx */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2871 POSTING_READ(reg);
2872
2873 reg = FDI_RX_CTL(pipe);
2874 temp = I915_READ(reg);
2875 temp &= ~(0x7 << 16);
dfd07d72 2876 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2877 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2878
2879 POSTING_READ(reg);
2880 udelay(100);
2881
2882 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2883 if (HAS_PCH_IBX(dev)) {
2884 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2885 }
0fc932b8
JB		 2886
2887 /* still set train pattern 1 */
2888 reg = FDI_TX_CTL(pipe);
2889 temp = I915_READ(reg);
2890 temp &= ~FDI_LINK_TRAIN_NONE;
2891 temp |= FDI_LINK_TRAIN_PATTERN_1;
2892 I915_WRITE(reg, temp);
2893
2894 reg = FDI_RX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 if (HAS_PCH_CPT(dev)) {
2897 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2898 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2899 } else {
2900 temp &= ~FDI_LINK_TRAIN_NONE;
2901 temp |= FDI_LINK_TRAIN_PATTERN_1;
2902 }
2903 /* BPC in FDI rx is consistent with that in PIPECONF */
2904 temp &= ~(0x07 << 16);
dfd07d72 2905 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2906 I915_WRITE(reg, temp);
2907
2908 POSTING_READ(reg);
2909 udelay(100);
2910}
2911
5bb61643
CW		 2912static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2917 unsigned long flags;
2918 bool pending;
2919
10d83730
VS		 2920 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2921 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2922 return false;
2923
2924 spin_lock_irqsave(&dev->event_lock, flags);
2925 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2926 spin_unlock_irqrestore(&dev->event_lock, flags);
2927
2928 return pending;
2929}
2930
e6c3a2a6
CW		 2931static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2932{
0f91128d 2933 struct drm_device *dev = crtc->dev;
5bb61643 2934 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2935
2936 if (crtc->fb == NULL)
2937 return;
2938
2c10d571
DV		 2939 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2940
5bb61643
CW		 2941 wait_event(dev_priv->pending_flip_queue,
2942 !intel_crtc_has_pending_flip(crtc));
2943
0f91128d
CW		 2944 mutex_lock(&dev->struct_mutex);
2945 intel_finish_fb(crtc->fb);
2946 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2947}
2948
e615efe4
ED		 2949/* Program iCLKIP clock to the desired frequency */
2950static void lpt_program_iclkip(struct drm_crtc *crtc)
2951{
2952 struct drm_device *dev = crtc->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2954 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2955 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2956 u32 temp;
2957
09153000
DV		 2958 mutex_lock(&dev_priv->dpio_lock);
2959
e615efe4
ED		 2960 /* It is necessary to ungate the pixclk gate prior to programming
2961 * the divisors, and gate it back when it is done.
2962 */
2963 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2964
2965 /* Disable SSCCTL */
2966 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2967 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2968 SBI_SSCCTL_DISABLE,
2969 SBI_ICLK);
e615efe4
ED		 2970
2971 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2972 if (clock == 20000) {
e615efe4
ED		 2973 auxdiv = 1;
2974 divsel = 0x41;
2975 phaseinc = 0x20;
2976 } else {
2977 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2978 * but the adjusted_mode->crtc_clock in in KHz. To get the
2979 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2980 * convert the virtual clock precision to KHz here for higher
2981 * precision.
2982 */
2983 u32 iclk_virtual_root_freq = 172800 * 1000;
2984 u32 iclk_pi_range = 64;
2985 u32 desired_divisor, msb_divisor_value, pi_value;
2986
12d7ceed 2987 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2988 msb_divisor_value = desired_divisor / iclk_pi_range;
2989 pi_value = desired_divisor % iclk_pi_range;
2990
2991 auxdiv = 0;
2992 divsel = msb_divisor_value - 2;
2993 phaseinc = pi_value;
2994 }
2995
2996 /* This should not happen with any sane values */
2997 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2998 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2999 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3000 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3001
3002 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3003 clock,
e615efe4
ED		 3004 auxdiv,
3005 divsel,
3006 phasedir,
3007 phaseinc);
3008
3009 /* Program SSCDIVINTPHASE6 */
988d6ee8 3010 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3011 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3012 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3013 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3014 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3015 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3016 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3017 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3018
3019 /* Program SSCAUXDIV */
988d6ee8 3020 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3021 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3022 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3023 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3024
3025 /* Enable modulator and associated divider */
988d6ee8 3026 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3027 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3028 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3029
3030 /* Wait for initialization time */
3031 udelay(24);
3032
3033 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3034
3035 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3036}
3037
275f01b2
DV		 3038static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3039 enum pipe pch_transcoder)
3040{
3041 struct drm_device *dev = crtc->base.dev;
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3044
3045 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3046 I915_READ(HTOTAL(cpu_transcoder)));
3047 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3048 I915_READ(HBLANK(cpu_transcoder)));
3049 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3050 I915_READ(HSYNC(cpu_transcoder)));
3051
3052 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3053 I915_READ(VTOTAL(cpu_transcoder)));
3054 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3055 I915_READ(VBLANK(cpu_transcoder)));
3056 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3057 I915_READ(VSYNC(cpu_transcoder)));
3058 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3059 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3060}
3061
f67a559d
JB		 3062/*
3063 * Enable PCH resources required for PCH ports:
3064 * - PCH PLLs
3065 * - FDI training & RX/TX
3066 * - update transcoder timings
3067 * - DP transcoding bits
3068 * - transcoder
3069 */
3070static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3071{
3072 struct drm_device *dev = crtc->dev;
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075 int pipe = intel_crtc->pipe;
ee7b9f93 3076 u32 reg, temp;
2c07245f 3077
ab9412ba 3078 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3079
cd986abb
DV		 3080 /* Write the TU size bits before fdi link training, so that error
3081 * detection works. */
3082 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3083 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3084
c98e9dcf 3085 /* For PCH output, training FDI link */
674cf967 3086 dev_priv->display.fdi_link_train(crtc);
2c07245f 3087
3ad8a208
DV		 3088 /* We need to program the right clock selection before writing the pixel
3089 * mutliplier into the DPLL. */
303b81e0 3090 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3091 u32 sel;
4b645f14 3092
c98e9dcf 3093 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3094 temp |= TRANS_DPLL_ENABLE(pipe);
3095 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3096 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3097 temp |= sel;
3098 else
3099 temp &= ~sel;
c98e9dcf 3100 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3101 }
5eddb70b 3102
3ad8a208
DV		 3103 /* XXX: pch pll's can be enabled any time before we enable the PCH
3104 * transcoder, and we actually should do this to not upset any PCH
3105 * transcoder that already use the clock when we share it.
3106 *
3107 * Note that enable_shared_dpll tries to do the right thing, but
3108 * get_shared_dpll unconditionally resets the pll - we need that to have
3109 * the right LVDS enable sequence. */
3110 ironlake_enable_shared_dpll(intel_crtc);
3111
d9b6cb56
JB		 3112 /* set transcoder timing, panel must allow it */
3113 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3114 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3115
303b81e0 3116 intel_fdi_normal_train(crtc);
5e84e1a4 3117
c98e9dcf
JB		 3118 /* For PCH DP, enable TRANS_DP_CTL */
3119 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3120 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3121 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3122 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3123 reg = TRANS_DP_CTL(pipe);
3124 temp = I915_READ(reg);
3125 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3126 TRANS_DP_SYNC_MASK |
3127 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3128 temp |= (TRANS_DP_OUTPUT_ENABLE |
3129 TRANS_DP_ENH_FRAMING);
9325c9f0 3130 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3131
3132 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3133 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3134 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3135 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3136
3137 switch (intel_trans_dp_port_sel(crtc)) {
3138 case PCH_DP_B:
5eddb70b 3139 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3140 break;
3141 case PCH_DP_C:
5eddb70b 3142 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3143 break;
3144 case PCH_DP_D:
5eddb70b 3145 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3146 break;
3147 default:
e95d41e1 3148 BUG();
32f9d658 3149 }
2c07245f 3150
5eddb70b 3151 I915_WRITE(reg, temp);
6be4a607 3152 }
b52eb4dc 3153
b8a4f404 3154 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3155}
3156
1507e5bd
PZ		 3157static void lpt_pch_enable(struct drm_crtc *crtc)
3158{
3159 struct drm_device *dev = crtc->dev;
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3162 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3163
ab9412ba 3164 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3165
8c52b5e8 3166 lpt_program_iclkip(crtc);
1507e5bd 3167
0540e488 3168 /* Set transcoder timing. */
275f01b2 3169 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3170
937bb610 3171 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3172}
3173
e2b78267 3174static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3175{
e2b78267 3176 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3177
3178 if (pll == NULL)
3179 return;
3180
3181 if (pll->refcount == 0) {
46edb027 3182 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3183 return;
3184 }
3185
f4a091c7
DV		 3186 if (--pll->refcount == 0) {
3187 WARN_ON(pll->on);
3188 WARN_ON(pll->active);
3189 }
3190
a43f6e0f 3191 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3192}
3193
b89a1d39 3194static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3195{
e2b78267
DV		 3196 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3197 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3198 enum intel_dpll_id i;
ee7b9f93 3199
ee7b9f93 3200 if (pll) {
46edb027
DV		 3201 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3202 crtc->base.base.id, pll->name);
e2b78267 3203 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3204 }
3205
98b6bd99
DV		 3206 if (HAS_PCH_IBX(dev_priv->dev)) {
3207 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3208 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3209 pll = &dev_priv->shared_dplls[i];
98b6bd99 3210
46edb027
DV		 3211 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3212 crtc->base.base.id, pll->name);
98b6bd99
DV		 3213
3214 goto found;
3215 }
3216
e72f9fbf
DV		 3217 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3218 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3219
3220 /* Only want to check enabled timings first */
3221 if (pll->refcount == 0)
3222 continue;
3223
b89a1d39
DV		 3224 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3225 sizeof(pll->hw_state)) == 0) {
46edb027 3226 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3227 crtc->base.base.id,
46edb027 3228 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3229
3230 goto found;
3231 }
3232 }
3233
3234 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3235 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3236 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3237 if (pll->refcount == 0) {
46edb027
DV		 3238 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3239 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3240 goto found;
3241 }
3242 }
3243
3244 return NULL;
3245
3246found:
a43f6e0f 3247 crtc->config.shared_dpll = i;
46edb027
DV		 3248 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3249 pipe_name(crtc->pipe));
ee7b9f93 3250
cdbd2316 3251 if (pll->active == 0) {
66e985c0
DV		 3252 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3253 sizeof(pll->hw_state));
3254
46edb027 3255 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3256 WARN_ON(pll->on);
e9d6944e 3257 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3258
15bdd4cf 3259 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3260 }
3261 pll->refcount++;
e04c7350 3262
ee7b9f93
JB		 3263 return pll;
3264}
3265
a1520318 3266static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3267{
3268 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3269 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3270 u32 temp;
3271
3272 temp = I915_READ(dslreg);
3273 udelay(500);
3274 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3275 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3276 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3277 }
3278}
3279
b074cec8
JB		 3280static void ironlake_pfit_enable(struct intel_crtc *crtc)
3281{
3282 struct drm_device *dev = crtc->base.dev;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 int pipe = crtc->pipe;
3285
fd4daa9c 3286 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3287 /* Force use of hard-coded filter coefficients
3288 * as some pre-programmed values are broken,
3289 * e.g. x201.
3290 */
3291 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3292 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3293 PF_PIPE_SEL_IVB(pipe));
3294 else
3295 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3296 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3297 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3298 }
3299}
3300
bb53d4ae
VS		 3301static void intel_enable_planes(struct drm_crtc *crtc)
3302{
3303 struct drm_device *dev = crtc->dev;
3304 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3305 struct intel_plane *intel_plane;
3306
3307 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3308 if (intel_plane->pipe == pipe)
3309 intel_plane_restore(&intel_plane->base);
3310}
3311
3312static void intel_disable_planes(struct drm_crtc *crtc)
3313{
3314 struct drm_device *dev = crtc->dev;
3315 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3316 struct intel_plane *intel_plane;
3317
3318 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3319 if (intel_plane->pipe == pipe)
3320 intel_plane_disable(&intel_plane->base);
3321}
3322
d77e4531
PZ		 3323static void hsw_enable_ips(struct intel_crtc *crtc)
3324{
3325 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3326
3327 if (!crtc->config.ips_enabled)
3328 return;
3329
3330 /* We can only enable IPS after we enable a plane and wait for a vblank.
3331 * We guarantee that the plane is enabled by calling intel_enable_ips
3332 * only after intel_enable_plane. And intel_enable_plane already waits
3333 * for a vblank, so all we need to do here is to enable the IPS bit. */
3334 assert_plane_enabled(dev_priv, crtc->plane);
3335 I915_WRITE(IPS_CTL, IPS_ENABLE);
3336}
3337
3338static void hsw_disable_ips(struct intel_crtc *crtc)
3339{
3340 struct drm_device *dev = crtc->base.dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342
3343 if (!crtc->config.ips_enabled)
3344 return;
3345
3346 assert_plane_enabled(dev_priv, crtc->plane);
3347 I915_WRITE(IPS_CTL, 0);
3348 POSTING_READ(IPS_CTL);
3349
3350 /* We need to wait for a vblank before we can disable the plane. */
3351 intel_wait_for_vblank(dev, crtc->pipe);
3352}
3353
3354/** Loads the palette/gamma unit for the CRTC with the prepared values */
3355static void intel_crtc_load_lut(struct drm_crtc *crtc)
3356{
3357 struct drm_device *dev = crtc->dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3360 enum pipe pipe = intel_crtc->pipe;
3361 int palreg = PALETTE(pipe);
3362 int i;
3363 bool reenable_ips = false;
3364
3365 /* The clocks have to be on to load the palette. */
3366 if (!crtc->enabled || !intel_crtc->active)
3367 return;
3368
3369 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3371 assert_dsi_pll_enabled(dev_priv);
3372 else
3373 assert_pll_enabled(dev_priv, pipe);
3374 }
3375
3376 /* use legacy palette for Ironlake */
3377 if (HAS_PCH_SPLIT(dev))
3378 palreg = LGC_PALETTE(pipe);
3379
3380 /* Workaround : Do not read or write the pipe palette/gamma data while
3381 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3382 */
3383 if (intel_crtc->config.ips_enabled &&
3384 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3385 GAMMA_MODE_MODE_SPLIT)) {
3386 hsw_disable_ips(intel_crtc);
3387 reenable_ips = true;
3388 }
3389
3390 for (i = 0; i < 256; i++) {
3391 I915_WRITE(palreg + 4 * i,
3392 (intel_crtc->lut_r[i] << 16) |
3393 (intel_crtc->lut_g[i] << 8) |
3394 intel_crtc->lut_b[i]);
3395 }
3396
3397 if (reenable_ips)
3398 hsw_enable_ips(intel_crtc);
3399}
3400
f67a559d
JB		 3401static void ironlake_crtc_enable(struct drm_crtc *crtc)
3402{
3403 struct drm_device *dev = crtc->dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3406 struct intel_encoder *encoder;
f67a559d
JB		 3407 int pipe = intel_crtc->pipe;
3408 int plane = intel_crtc->plane;
f67a559d 3409
08a48469
DV		 3410 WARN_ON(!crtc->enabled);
3411
f67a559d
JB		 3412 if (intel_crtc->active)
3413 return;
3414
3415 intel_crtc->active = true;
8664281b
PZ		 3416
3417 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3418 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3419
f6736a1a 3420 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3421 if (encoder->pre_enable)
3422 encoder->pre_enable(encoder);
f67a559d 3423
5bfe2ac0 3424 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3425 /* Note: FDI PLL enabling _must_ be done before we enable the
3426 * cpu pipes, hence this is separate from all the other fdi/pch
3427 * enabling. */
88cefb6c 3428 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3429 } else {
3430 assert_fdi_tx_disabled(dev_priv, pipe);
3431 assert_fdi_rx_disabled(dev_priv, pipe);
3432 }
f67a559d 3433
b074cec8 3434 ironlake_pfit_enable(intel_crtc);
f67a559d 3435
9c54c0dd
JB		 3436 /*
3437 * On ILK+ LUT must be loaded before the pipe is running but with
3438 * clocks enabled
3439 */
3440 intel_crtc_load_lut(crtc);
3441
f37fcc2a 3442 intel_update_watermarks(crtc);
5bfe2ac0 3443 intel_enable_pipe(dev_priv, pipe,
23538ef1 3444 intel_crtc->config.has_pch_encoder, false);
f67a559d 3445 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3446 intel_enable_planes(crtc);
5c38d48c 3447 intel_crtc_update_cursor(crtc, true);
f67a559d 3448
5bfe2ac0 3449 if (intel_crtc->config.has_pch_encoder)
f67a559d 3450 ironlake_pch_enable(crtc);
c98e9dcf 3451
d1ebd816 3452 mutex_lock(&dev->struct_mutex);
bed4a673 3453 intel_update_fbc(dev);
d1ebd816
BW		 3454 mutex_unlock(&dev->struct_mutex);
3455
fa5c73b1
DV		 3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 encoder->enable(encoder);
61b77ddd
DV		 3458
3459 if (HAS_PCH_CPT(dev))
a1520318 3460 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3461
3462 /*
3463 * There seems to be a race in PCH platform hw (at least on some
3464 * outputs) where an enabled pipe still completes any pageflip right
3465 * away (as if the pipe is off) instead of waiting for vblank. As soon
3466 * as the first vblank happend, everything works as expected. Hence just
3467 * wait for one vblank before returning to avoid strange things
3468 * happening.
3469 */
3470 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3471}
3472
42db64ef
PZ		 3473/* IPS only exists on ULT machines and is tied to pipe A. */
3474static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3475{
f5adf94e 3476 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3477}
3478
dda9a66a
VS		 3479static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3480{
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484 int pipe = intel_crtc->pipe;
3485 int plane = intel_crtc->plane;
3486
3487 intel_enable_plane(dev_priv, plane, pipe);
3488 intel_enable_planes(crtc);
3489 intel_crtc_update_cursor(crtc, true);
3490
3491 hsw_enable_ips(intel_crtc);
3492
3493 mutex_lock(&dev->struct_mutex);
3494 intel_update_fbc(dev);
3495 mutex_unlock(&dev->struct_mutex);
3496}
3497
3498static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3499{
3500 struct drm_device *dev = crtc->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3503 int pipe = intel_crtc->pipe;
3504 int plane = intel_crtc->plane;
3505
3506 intel_crtc_wait_for_pending_flips(crtc);
3507 drm_vblank_off(dev, pipe);
3508
3509 /* FBC must be disabled before disabling the plane on HSW. */
3510 if (dev_priv->fbc.plane == plane)
3511 intel_disable_fbc(dev);
3512
3513 hsw_disable_ips(intel_crtc);
3514
3515 intel_crtc_update_cursor(crtc, false);
3516 intel_disable_planes(crtc);
3517 intel_disable_plane(dev_priv, plane, pipe);
3518}
3519
e4916946
PZ		 3520/*
3521 * This implements the workaround described in the "notes" section of the mode
3522 * set sequence documentation. When going from no pipes or single pipe to
3523 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3524 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3525 */
3526static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3527{
3528 struct drm_device *dev = crtc->base.dev;
3529 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3530
3531 /* We want to get the other_active_crtc only if there's only 1 other
3532 * active crtc. */
3533 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3534 if (!crtc_it->active || crtc_it == crtc)
3535 continue;
3536
3537 if (other_active_crtc)
3538 return;
3539
3540 other_active_crtc = crtc_it;
3541 }
3542 if (!other_active_crtc)
3543 return;
3544
3545 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3546 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3547}
3548
4f771f10
PZ		 3549static void haswell_crtc_enable(struct drm_crtc *crtc)
3550{
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 struct intel_encoder *encoder;
3555 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3556
3557 WARN_ON(!crtc->enabled);
3558
3559 if (intel_crtc->active)
3560 return;
3561
3562 intel_crtc->active = true;
8664281b
PZ		 3563
3564 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3565 if (intel_crtc->config.has_pch_encoder)
3566 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3567
5bfe2ac0 3568 if (intel_crtc->config.has_pch_encoder)
04945641 3569 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3570
3571 for_each_encoder_on_crtc(dev, crtc, encoder)
3572 if (encoder->pre_enable)
3573 encoder->pre_enable(encoder);
3574
1f544388 3575 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3576
b074cec8 3577 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3578
3579 /*
3580 * On ILK+ LUT must be loaded before the pipe is running but with
3581 * clocks enabled
3582 */
3583 intel_crtc_load_lut(crtc);
3584
1f544388 3585 intel_ddi_set_pipe_settings(crtc);
8228c251 3586 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3587
f37fcc2a 3588 intel_update_watermarks(crtc);
5bfe2ac0 3589 intel_enable_pipe(dev_priv, pipe,
23538ef1 3590 intel_crtc->config.has_pch_encoder, false);
42db64ef 3591
5bfe2ac0 3592 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3593 lpt_pch_enable(crtc);
4f771f10 3594
8807e55b 3595 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3596 encoder->enable(encoder);
8807e55b
JN		 3597 intel_opregion_notify_encoder(encoder, true);
3598 }
4f771f10 3599
e4916946
PZ		 3600 /* If we change the relative order between pipe/planes enabling, we need
3601 * to change the workaround. */
3602 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3603 haswell_crtc_enable_planes(crtc);
3604
4f771f10
PZ		 3605 /*
3606 * There seems to be a race in PCH platform hw (at least on some
3607 * outputs) where an enabled pipe still completes any pageflip right
3608 * away (as if the pipe is off) instead of waiting for vblank. As soon
3609 * as the first vblank happend, everything works as expected. Hence just
3610 * wait for one vblank before returning to avoid strange things
3611 * happening.
3612 */
3613 intel_wait_for_vblank(dev, intel_crtc->pipe);
3614}
3615
3f8dce3a
DV		 3616static void ironlake_pfit_disable(struct intel_crtc *crtc)
3617{
3618 struct drm_device *dev = crtc->base.dev;
3619 struct drm_i915_private *dev_priv = dev->dev_private;
3620 int pipe = crtc->pipe;
3621
3622 /* To avoid upsetting the power well on haswell only disable the pfit if
3623 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3624 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3625 I915_WRITE(PF_CTL(pipe), 0);
3626 I915_WRITE(PF_WIN_POS(pipe), 0);
3627 I915_WRITE(PF_WIN_SZ(pipe), 0);
3628 }
3629}
3630
6be4a607
JB		 3631static void ironlake_crtc_disable(struct drm_crtc *crtc)
3632{
3633 struct drm_device *dev = crtc->dev;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3636 struct intel_encoder *encoder;
6be4a607
JB		 3637 int pipe = intel_crtc->pipe;
3638 int plane = intel_crtc->plane;
5eddb70b 3639 u32 reg, temp;
b52eb4dc 3640
ef9c3aee 3641
f7abfe8b
CW		 3642 if (!intel_crtc->active)
3643 return;
3644
ea9d758d
DV		 3645 for_each_encoder_on_crtc(dev, crtc, encoder)
3646 encoder->disable(encoder);
3647
e6c3a2a6 3648 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3649 drm_vblank_off(dev, pipe);
913d8d11 3650
5c3fe8b0 3651 if (dev_priv->fbc.plane == plane)
973d04f9 3652 intel_disable_fbc(dev);
2c07245f 3653
0d5b8c61 3654 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3655 intel_disable_planes(crtc);
0d5b8c61
VS		 3656 intel_disable_plane(dev_priv, plane, pipe);
3657
d925c59a
DV		 3658 if (intel_crtc->config.has_pch_encoder)
3659 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3660
b24e7179 3661 intel_disable_pipe(dev_priv, pipe);
32f9d658 3662
3f8dce3a 3663 ironlake_pfit_disable(intel_crtc);
2c07245f 3664
bf49ec8c
DV		 3665 for_each_encoder_on_crtc(dev, crtc, encoder)
3666 if (encoder->post_disable)
3667 encoder->post_disable(encoder);
2c07245f 3668
d925c59a
DV		 3669 if (intel_crtc->config.has_pch_encoder) {
3670 ironlake_fdi_disable(crtc);
913d8d11 3671
d925c59a
DV		 3672 ironlake_disable_pch_transcoder(dev_priv, pipe);
3673 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3674
d925c59a
DV		 3675 if (HAS_PCH_CPT(dev)) {
3676 /* disable TRANS_DP_CTL */
3677 reg = TRANS_DP_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3680 TRANS_DP_PORT_SEL_MASK);
3681 temp |= TRANS_DP_PORT_SEL_NONE;
3682 I915_WRITE(reg, temp);
3683
3684 /* disable DPLL_SEL */
3685 temp = I915_READ(PCH_DPLL_SEL);
11887397 3686 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3687 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3688 }
e3421a18 3689
d925c59a 3690 /* disable PCH DPLL */
e72f9fbf 3691 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3692
d925c59a
DV		 3693 ironlake_fdi_pll_disable(intel_crtc);
3694 }
6b383a7f 3695
f7abfe8b 3696 intel_crtc->active = false;
46ba614c 3697 intel_update_watermarks(crtc);
d1ebd816
BW		 3698
3699 mutex_lock(&dev->struct_mutex);
6b383a7f 3700 intel_update_fbc(dev);
d1ebd816 3701 mutex_unlock(&dev->struct_mutex);
6be4a607 3702}
1b3c7a47 3703
4f771f10 3704static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3705{
4f771f10
PZ		 3706 struct drm_device *dev = crtc->dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3709 struct intel_encoder *encoder;
3710 int pipe = intel_crtc->pipe;
3b117c8f 3711 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3712
4f771f10
PZ		 3713 if (!intel_crtc->active)
3714 return;
3715
dda9a66a
VS		 3716 haswell_crtc_disable_planes(crtc);
3717
8807e55b
JN		 3718 for_each_encoder_on_crtc(dev, crtc, encoder) {
3719 intel_opregion_notify_encoder(encoder, false);
4f771f10 3720 encoder->disable(encoder);
8807e55b 3721 }
4f771f10 3722
8664281b
PZ		 3723 if (intel_crtc->config.has_pch_encoder)
3724 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3725 intel_disable_pipe(dev_priv, pipe);
3726
ad80a810 3727 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3728
3f8dce3a 3729 ironlake_pfit_disable(intel_crtc);
4f771f10 3730
1f544388 3731 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3732
3733 for_each_encoder_on_crtc(dev, crtc, encoder)
3734 if (encoder->post_disable)
3735 encoder->post_disable(encoder);
3736
88adfff1 3737 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3738 lpt_disable_pch_transcoder(dev_priv);
8664281b 3739 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3740 intel_ddi_fdi_disable(crtc);
83616634 3741 }
4f771f10
PZ		 3742
3743 intel_crtc->active = false;
46ba614c 3744 intel_update_watermarks(crtc);
4f771f10
PZ		 3745
3746 mutex_lock(&dev->struct_mutex);
3747 intel_update_fbc(dev);
3748 mutex_unlock(&dev->struct_mutex);
3749}
3750
ee7b9f93
JB		 3751static void ironlake_crtc_off(struct drm_crtc *crtc)
3752{
3753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3754 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3755}
3756
6441ab5f
PZ		 3757static void haswell_crtc_off(struct drm_crtc *crtc)
3758{
3759 intel_ddi_put_crtc_pll(crtc);
3760}
3761
02e792fb
DV		 3762static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3763{
02e792fb 3764 if (!enable && intel_crtc->overlay) {
23f09ce3 3765 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3766 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3767
23f09ce3 3768 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3769 dev_priv->mm.interruptible = false;
3770 (void) intel_overlay_switch_off(intel_crtc->overlay);
3771 dev_priv->mm.interruptible = true;
23f09ce3 3772 mutex_unlock(&dev->struct_mutex);
02e792fb 3773 }
02e792fb 3774
5dcdbcb0
CW		 3775 /* Let userspace switch the overlay on again. In most cases userspace
3776 * has to recompute where to put it anyway.
3777 */
02e792fb
DV		 3778}
3779
61bc95c1
EE		 3780/**
3781 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3782 * cursor plane briefly if not already running after enabling the display
3783 * plane.
3784 * This workaround avoids occasional blank screens when self refresh is
3785 * enabled.
3786 */
3787static void
3788g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3789{
3790 u32 cntl = I915_READ(CURCNTR(pipe));
3791
3792 if ((cntl & CURSOR_MODE) == 0) {
3793 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3794
3795 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3796 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3797 intel_wait_for_vblank(dev_priv->dev, pipe);
3798 I915_WRITE(CURCNTR(pipe), cntl);
3799 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3800 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3801 }
3802}
3803
2dd24552
JB		 3804static void i9xx_pfit_enable(struct intel_crtc *crtc)
3805{
3806 struct drm_device *dev = crtc->base.dev;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 struct intel_crtc_config *pipe_config = &crtc->config;
3809
328d8e82 3810 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3811 return;
3812
2dd24552 3813 /*
c0b03411
DV		 3814 * The panel fitter should only be adjusted whilst the pipe is disabled,
3815 * according to register description and PRM.
2dd24552 3816 */
c0b03411
DV		 3817 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3818 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3819
b074cec8
JB		 3820 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3821 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3822
3823 /* Border color in case we don't scale up to the full screen. Black by
3824 * default, change to something else for debugging. */
3825 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3826}
3827
89b667f8
JB		 3828static void valleyview_crtc_enable(struct drm_crtc *crtc)
3829{
3830 struct drm_device *dev = crtc->dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3833 struct intel_encoder *encoder;
3834 int pipe = intel_crtc->pipe;
3835 int plane = intel_crtc->plane;
23538ef1 3836 bool is_dsi;
89b667f8
JB		 3837
3838 WARN_ON(!crtc->enabled);
3839
3840 if (intel_crtc->active)
3841 return;
3842
3843 intel_crtc->active = true;
89b667f8 3844
89b667f8
JB		 3845 for_each_encoder_on_crtc(dev, crtc, encoder)
3846 if (encoder->pre_pll_enable)
3847 encoder->pre_pll_enable(encoder);
3848
23538ef1
JN		 3849 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3850
e9fd1c02
JN		 3851 if (!is_dsi)
3852 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3853
3854 for_each_encoder_on_crtc(dev, crtc, encoder)
3855 if (encoder->pre_enable)
3856 encoder->pre_enable(encoder);
3857
2dd24552
JB		 3858 i9xx_pfit_enable(intel_crtc);
3859
63cbb074
VS		 3860 intel_crtc_load_lut(crtc);
3861
f37fcc2a 3862 intel_update_watermarks(crtc);
23538ef1 3863 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3864 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3865 intel_enable_planes(crtc);
5c38d48c 3866 intel_crtc_update_cursor(crtc, true);
89b667f8 3867
89b667f8 3868 intel_update_fbc(dev);
5004945f
JN		 3869
3870 for_each_encoder_on_crtc(dev, crtc, encoder)
3871 encoder->enable(encoder);
89b667f8
JB		 3872}
3873
0b8765c6 3874static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3875{
3876 struct drm_device *dev = crtc->dev;
79e53945
JB		 3877 struct drm_i915_private *dev_priv = dev->dev_private;
3878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3879 struct intel_encoder *encoder;
79e53945 3880 int pipe = intel_crtc->pipe;
80824003 3881 int plane = intel_crtc->plane;
79e53945 3882
08a48469
DV		 3883 WARN_ON(!crtc->enabled);
3884
f7abfe8b
CW		 3885 if (intel_crtc->active)
3886 return;
3887
3888 intel_crtc->active = true;
6b383a7f 3889
9d6d9f19
MK		 3890 for_each_encoder_on_crtc(dev, crtc, encoder)
3891 if (encoder->pre_enable)
3892 encoder->pre_enable(encoder);
3893
f6736a1a
DV		 3894 i9xx_enable_pll(intel_crtc);
3895
2dd24552
JB		 3896 i9xx_pfit_enable(intel_crtc);
3897
63cbb074
VS		 3898 intel_crtc_load_lut(crtc);
3899
f37fcc2a 3900 intel_update_watermarks(crtc);
23538ef1 3901 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3902 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3903 intel_enable_planes(crtc);
22e407d7 3904 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3905 if (IS_G4X(dev))
3906 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3907 intel_crtc_update_cursor(crtc, true);
79e53945 3908
0b8765c6
JB		 3909 /* Give the overlay scaler a chance to enable if it's on this pipe */
3910 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3911
f440eb13 3912 intel_update_fbc(dev);
ef9c3aee 3913
fa5c73b1
DV		 3914 for_each_encoder_on_crtc(dev, crtc, encoder)
3915 encoder->enable(encoder);
0b8765c6 3916}
79e53945 3917
87476d63
DV		 3918static void i9xx_pfit_disable(struct intel_crtc *crtc)
3919{
3920 struct drm_device *dev = crtc->base.dev;
3921 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3922
328d8e82
DV		 3923 if (!crtc->config.gmch_pfit.control)
3924 return;
87476d63 3925
328d8e82 3926 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3927
328d8e82
DV		 3928 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3929 I915_READ(PFIT_CONTROL));
3930 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3931}
3932
0b8765c6
JB		 3933static void i9xx_crtc_disable(struct drm_crtc *crtc)
3934{
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3938 struct intel_encoder *encoder;
0b8765c6
JB		 3939 int pipe = intel_crtc->pipe;
3940 int plane = intel_crtc->plane;
ef9c3aee 3941
f7abfe8b
CW		 3942 if (!intel_crtc->active)
3943 return;
3944
ea9d758d
DV		 3945 for_each_encoder_on_crtc(dev, crtc, encoder)
3946 encoder->disable(encoder);
3947
0b8765c6 3948 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3949 intel_crtc_wait_for_pending_flips(crtc);
3950 drm_vblank_off(dev, pipe);
0b8765c6 3951
5c3fe8b0 3952 if (dev_priv->fbc.plane == plane)
973d04f9 3953 intel_disable_fbc(dev);
79e53945 3954
0d5b8c61
VS		 3955 intel_crtc_dpms_overlay(intel_crtc, false);
3956 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3957 intel_disable_planes(crtc);
b24e7179 3958 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3959
b24e7179 3960 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3961
87476d63 3962 i9xx_pfit_disable(intel_crtc);
24a1f16d 3963
89b667f8
JB		 3964 for_each_encoder_on_crtc(dev, crtc, encoder)
3965 if (encoder->post_disable)
3966 encoder->post_disable(encoder);
3967
f6071166
JB		 3968 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3969 vlv_disable_pll(dev_priv, pipe);
3970 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3971 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3972
f7abfe8b 3973 intel_crtc->active = false;
46ba614c 3974 intel_update_watermarks(crtc);
f37fcc2a 3975
6b383a7f 3976 intel_update_fbc(dev);
0b8765c6
JB		 3977}
3978
ee7b9f93
JB		 3979static void i9xx_crtc_off(struct drm_crtc *crtc)
3980{
3981}
3982
976f8a20
DV		 3983static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3984 bool enabled)
2c07245f
ZW		 3985{
3986 struct drm_device *dev = crtc->dev;
3987 struct drm_i915_master_private *master_priv;
3988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3989 int pipe = intel_crtc->pipe;
79e53945
JB		 3990
3991 if (!dev->primary->master)
3992 return;
3993
3994 master_priv = dev->primary->master->driver_priv;
3995 if (!master_priv->sarea_priv)
3996 return;
3997
79e53945
JB		 3998 switch (pipe) {
3999 case 0:
4000 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4001 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4002 break;
4003 case 1:
4004 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4005 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4006 break;
4007 default:
9db4a9c7 4008 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4009 break;
4010 }
79e53945
JB		 4011}
4012
976f8a20
DV		 4013/**
4014 * Sets the power management mode of the pipe and plane.
4015 */
4016void intel_crtc_update_dpms(struct drm_crtc *crtc)
4017{
4018 struct drm_device *dev = crtc->dev;
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 struct intel_encoder *intel_encoder;
4021 bool enable = false;
4022
4023 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4024 enable |= intel_encoder->connectors_active;
4025
4026 if (enable)
4027 dev_priv->display.crtc_enable(crtc);
4028 else
4029 dev_priv->display.crtc_disable(crtc);
4030
4031 intel_crtc_update_sarea(crtc, enable);
4032}
4033
cdd59983
CW		 4034static void intel_crtc_disable(struct drm_crtc *crtc)
4035{
cdd59983 4036 struct drm_device *dev = crtc->dev;
976f8a20 4037 struct drm_connector *connector;
ee7b9f93 4038 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4040
976f8a20
DV		 4041 /* crtc should still be enabled when we disable it. */
4042 WARN_ON(!crtc->enabled);
4043
4044 dev_priv->display.crtc_disable(crtc);
c77bf565 4045 intel_crtc->eld_vld = false;
976f8a20 4046 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4047 dev_priv->display.off(crtc);
4048
931872fc 4049 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4050 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4051 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4052
4053 if (crtc->fb) {
4054 mutex_lock(&dev->struct_mutex);
1690e1eb 4055 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4056 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4057 crtc->fb = NULL;
4058 }
4059
4060 /* Update computed state. */
4061 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4062 if (!connector->encoder || !connector->encoder->crtc)
4063 continue;
4064
4065 if (connector->encoder->crtc != crtc)
4066 continue;
4067
4068 connector->dpms = DRM_MODE_DPMS_OFF;
4069 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4070 }
4071}
4072
ea5b213a 4073void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4074{
4ef69c7a 4075 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4076
ea5b213a
CW		 4077 drm_encoder_cleanup(encoder);
4078 kfree(intel_encoder);
7e7d76c3
JB		 4079}
4080
9237329d 4081/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4082 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4083 * state of the entire output pipe. */
9237329d 4084static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4085{
5ab432ef
DV		 4086 if (mode == DRM_MODE_DPMS_ON) {
4087 encoder->connectors_active = true;
4088
b2cabb0e 4089 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4090 } else {
4091 encoder->connectors_active = false;
4092
b2cabb0e 4093 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4094 }
79e53945
JB		 4095}
4096
0a91ca29
DV		 4097/* Cross check the actual hw state with our own modeset state tracking (and it's
4098 * internal consistency). */
b980514c 4099static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4100{
0a91ca29
DV		 4101 if (connector->get_hw_state(connector)) {
4102 struct intel_encoder *encoder = connector->encoder;
4103 struct drm_crtc *crtc;
4104 bool encoder_enabled;
4105 enum pipe pipe;
4106
4107 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4108 connector->base.base.id,
4109 drm_get_connector_name(&connector->base));
4110
4111 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4112 "wrong connector dpms state\n");
4113 WARN(connector->base.encoder != &encoder->base,
4114 "active connector not linked to encoder\n");
4115 WARN(!encoder->connectors_active,
4116 "encoder->connectors_active not set\n");
4117
4118 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4119 WARN(!encoder_enabled, "encoder not enabled\n");
4120 if (WARN_ON(!encoder->base.crtc))
4121 return;
4122
4123 crtc = encoder->base.crtc;
4124
4125 WARN(!crtc->enabled, "crtc not enabled\n");
4126 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4127 WARN(pipe != to_intel_crtc(crtc)->pipe,
4128 "encoder active on the wrong pipe\n");
4129 }
79e53945
JB		 4130}
4131
5ab432ef
DV		 4132/* Even simpler default implementation, if there's really no special case to
4133 * consider. */
4134void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4135{
5ab432ef 4136 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4137
5ab432ef
DV		 4138 /* All the simple cases only support two dpms states. */
4139 if (mode != DRM_MODE_DPMS_ON)
4140 mode = DRM_MODE_DPMS_OFF;
d4270e57 4141
5ab432ef
DV		 4142 if (mode == connector->dpms)
4143 return;
4144
4145 connector->dpms = mode;
4146
4147 /* Only need to change hw state when actually enabled */
4148 if (encoder->base.crtc)
4149 intel_encoder_dpms(encoder, mode);
4150 else
8af6cf88 4151 WARN_ON(encoder->connectors_active != false);
0a91ca29 4152
b980514c 4153 intel_modeset_check_state(connector->dev);
79e53945
JB		 4154}
4155
f0947c37
DV		 4156/* Simple connector->get_hw_state implementation for encoders that support only
4157 * one connector and no cloning and hence the encoder state determines the state
4158 * of the connector. */
4159bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4160{
24929352 4161 enum pipe pipe = 0;
f0947c37 4162 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4163
f0947c37 4164 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4165}
4166
1857e1da
DV		 4167static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4168 struct intel_crtc_config *pipe_config)
4169{
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171 struct intel_crtc *pipe_B_crtc =
4172 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4173
4174 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4175 pipe_name(pipe), pipe_config->fdi_lanes);
4176 if (pipe_config->fdi_lanes > 4) {
4177 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4178 pipe_name(pipe), pipe_config->fdi_lanes);
4179 return false;
4180 }
4181
4182 if (IS_HASWELL(dev)) {
4183 if (pipe_config->fdi_lanes > 2) {
4184 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4185 pipe_config->fdi_lanes);
4186 return false;
4187 } else {
4188 return true;
4189 }
4190 }
4191
4192 if (INTEL_INFO(dev)->num_pipes == 2)
4193 return true;
4194
4195 /* Ivybridge 3 pipe is really complicated */
4196 switch (pipe) {
4197 case PIPE_A:
4198 return true;
4199 case PIPE_B:
4200 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4201 pipe_config->fdi_lanes > 2) {
4202 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4203 pipe_name(pipe), pipe_config->fdi_lanes);
4204 return false;
4205 }
4206 return true;
4207 case PIPE_C:
1e833f40 4208 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4209 pipe_B_crtc->config.fdi_lanes <= 2) {
4210 if (pipe_config->fdi_lanes > 2) {
4211 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4212 pipe_name(pipe), pipe_config->fdi_lanes);
4213 return false;
4214 }
4215 } else {
4216 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4217 return false;
4218 }
4219 return true;
4220 default:
4221 BUG();
4222 }
4223}
4224
e29c22c0
DV		 4225#define RETRY 1
4226static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4227 struct intel_crtc_config *pipe_config)
877d48d5 4228{
1857e1da 4229 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4230 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4231 int lane, link_bw, fdi_dotclock;
e29c22c0 4232 bool setup_ok, needs_recompute = false;
877d48d5 4233
e29c22c0 4234retry:
877d48d5
DV		 4235 /* FDI is a binary signal running at ~2.7GHz, encoding
4236 * each output octet as 10 bits. The actual frequency
4237 * is stored as a divider into a 100MHz clock, and the
4238 * mode pixel clock is stored in units of 1KHz.
4239 * Hence the bw of each lane in terms of the mode signal
4240 * is:
4241 */
4242 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4243
241bfc38 4244 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4245
2bd89a07 4246 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4247 pipe_config->pipe_bpp);
4248
4249 pipe_config->fdi_lanes = lane;
4250
2bd89a07 4251 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4252 link_bw, &pipe_config->fdi_m_n);
1857e1da 4253
e29c22c0
DV		 4254 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4255 intel_crtc->pipe, pipe_config);
4256 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4257 pipe_config->pipe_bpp -= 2*3;
4258 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4259 pipe_config->pipe_bpp);
4260 needs_recompute = true;
4261 pipe_config->bw_constrained = true;
4262
4263 goto retry;
4264 }
4265
4266 if (needs_recompute)
4267 return RETRY;
4268
4269 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4270}
4271
42db64ef
PZ		 4272static void hsw_compute_ips_config(struct intel_crtc *crtc,
4273 struct intel_crtc_config *pipe_config)
4274{
3c4ca58c
PZ		 4275 pipe_config->ips_enabled = i915_enable_ips &&
4276 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4277 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4278}
4279
a43f6e0f 4280static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4281 struct intel_crtc_config *pipe_config)
79e53945 4282{
a43f6e0f 4283 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4284 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4285
ad3a4479 4286 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4287 if (INTEL_INFO(dev)->gen < 4) {
4288 struct drm_i915_private *dev_priv = dev->dev_private;
4289 int clock_limit =
4290 dev_priv->display.get_display_clock_speed(dev);
4291
4292 /*
4293 * Enable pixel doubling when the dot clock
4294 * is > 90% of the (display) core speed.
4295 *
b397c96b
VS		 4296 * GDG double wide on either pipe,
4297 * otherwise pipe A only.
cf532bb2 4298 */
b397c96b 4299 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4300 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4301 clock_limit *= 2;
cf532bb2 4302 pipe_config->double_wide = true;
ad3a4479
VS		 4303 }
4304
241bfc38 4305 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4306 return -EINVAL;
2c07245f 4307 }
89749350 4308
1d1d0e27
VS		 4309 /*
4310 * Pipe horizontal size must be even in:
4311 * - DVO ganged mode
4312 * - LVDS dual channel mode
4313 * - Double wide pipe
4314 */
4315 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4316 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4317 pipe_config->pipe_src_w &= ~1;
4318
8693a824
DL		 4319 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4320 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4321 */
4322 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4323 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4324 return -EINVAL;
44f46b42 4325
bd080ee5 4326 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4327 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4328 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4329 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4330 * for lvds. */
4331 pipe_config->pipe_bpp = 8*3;
4332 }
4333
f5adf94e 4334 if (HAS_IPS(dev))
a43f6e0f
DV		 4335 hsw_compute_ips_config(crtc, pipe_config);
4336
4337 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4338 * clock survives for now. */
4339 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4340 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4341
877d48d5 4342 if (pipe_config->has_pch_encoder)
a43f6e0f 4343 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4344
e29c22c0 4345 return 0;
79e53945
JB		 4346}
4347
25eb05fc
JB		 4348static int valleyview_get_display_clock_speed(struct drm_device *dev)
4349{
4350 return 400000; /* FIXME */
4351}
4352
e70236a8
JB		 4353static int i945_get_display_clock_speed(struct drm_device *dev)
4354{
4355 return 400000;
4356}
79e53945 4357
e70236a8 4358static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4359{
e70236a8
JB		 4360 return 333000;
4361}
79e53945 4362
e70236a8
JB		 4363static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4364{
4365 return 200000;
4366}
79e53945 4367
257a7ffc
DV		 4368static int pnv_get_display_clock_speed(struct drm_device *dev)
4369{
4370 u16 gcfgc = 0;
4371
4372 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4373
4374 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4375 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4376 return 267000;
4377 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4378 return 333000;
4379 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4380 return 444000;
4381 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4382 return 200000;
4383 default:
4384 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4385 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4386 return 133000;
4387 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4388 return 167000;
4389 }
4390}
4391
e70236a8
JB		 4392static int i915gm_get_display_clock_speed(struct drm_device *dev)
4393{
4394 u16 gcfgc = 0;
79e53945 4395
e70236a8
JB		 4396 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4397
4398 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4399 return 133000;
4400 else {
4401 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4402 case GC_DISPLAY_CLOCK_333_MHZ:
4403 return 333000;
4404 default:
4405 case GC_DISPLAY_CLOCK_190_200_MHZ:
4406 return 190000;
79e53945 4407 }
e70236a8
JB		 4408 }
4409}
4410
4411static int i865_get_display_clock_speed(struct drm_device *dev)
4412{
4413 return 266000;
4414}
4415
4416static int i855_get_display_clock_speed(struct drm_device *dev)
4417{
4418 u16 hpllcc = 0;
4419 /* Assume that the hardware is in the high speed state. This
4420 * should be the default.
4421 */
4422 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4423 case GC_CLOCK_133_200:
4424 case GC_CLOCK_100_200:
4425 return 200000;
4426 case GC_CLOCK_166_250:
4427 return 250000;
4428 case GC_CLOCK_100_133:
79e53945 4429 return 133000;
e70236a8 4430 }
79e53945 4431
e70236a8
JB		 4432 /* Shouldn't happen */
4433 return 0;
4434}
79e53945 4435
e70236a8
JB		 4436static int i830_get_display_clock_speed(struct drm_device *dev)
4437{
4438 return 133000;
79e53945
JB		 4439}
4440
2c07245f 4441static void
a65851af 4442intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4443{
a65851af
VS		 4444 while (*num > DATA_LINK_M_N_MASK ||
4445 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4446 *num >>= 1;
4447 *den >>= 1;
4448 }
4449}
4450
a65851af
VS		 4451static void compute_m_n(unsigned int m, unsigned int n,
4452 uint32_t *ret_m, uint32_t *ret_n)
4453{
4454 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4455 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4456 intel_reduce_m_n_ratio(ret_m, ret_n);
4457}
4458
e69d0bc1
DV		 4459void
4460intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4461 int pixel_clock, int link_clock,
4462 struct intel_link_m_n *m_n)
2c07245f 4463{
e69d0bc1 4464 m_n->tu = 64;
a65851af
VS		 4465
4466 compute_m_n(bits_per_pixel * pixel_clock,
4467 link_clock * nlanes * 8,
4468 &m_n->gmch_m, &m_n->gmch_n);
4469
4470 compute_m_n(pixel_clock, link_clock,
4471 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4472}
4473
a7615030
CW		 4474static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4475{
72bbe58c
KP		 4476 if (i915_panel_use_ssc >= 0)
4477 return i915_panel_use_ssc != 0;
41aa3448 4478 return dev_priv->vbt.lvds_use_ssc
435793df 4479 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4480}
4481
c65d77d8
JB		 4482static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4483{
4484 struct drm_device *dev = crtc->dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 int refclk;
4487
a0c4da24 4488 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4489 refclk = 100000;
a0c4da24 4490 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4491 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4492 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4493 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4494 refclk / 1000);
4495 } else if (!IS_GEN2(dev)) {
4496 refclk = 96000;
4497 } else {
4498 refclk = 48000;
4499 }
4500
4501 return refclk;
4502}
4503
7429e9d4 4504static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4505{
7df00d7a 4506 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4507}
f47709a9 4508
7429e9d4
DV		 4509static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4510{
4511 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4512}
4513
f47709a9 4514static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4515 intel_clock_t *reduced_clock)
4516{
f47709a9 4517 struct drm_device *dev = crtc->base.dev;
a7516a05 4518 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4519 int pipe = crtc->pipe;
a7516a05
JB		 4520 u32 fp, fp2 = 0;
4521
4522 if (IS_PINEVIEW(dev)) {
7429e9d4 4523 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4524 if (reduced_clock)
7429e9d4 4525 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4526 } else {
7429e9d4 4527 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4528 if (reduced_clock)
7429e9d4 4529 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4530 }
4531
4532 I915_WRITE(FP0(pipe), fp);
8bcc2795 4533 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4534
f47709a9
DV		 4535 crtc->lowfreq_avail = false;
4536 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4537 reduced_clock && i915_powersave) {
4538 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4539 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4540 crtc->lowfreq_avail = true;
a7516a05
JB		 4541 } else {
4542 I915_WRITE(FP1(pipe), fp);
8bcc2795 4543 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4544 }
4545}
4546
5e69f97f
CML		 4547static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4548 pipe)
89b667f8
JB		 4549{
4550 u32 reg_val;
4551
4552 /*
4553 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4554 * and set it to a reasonable value instead.
4555 */
5e69f97f 4556 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4557 reg_val &= 0xffffff00;
4558 reg_val |= 0x00000030;
5e69f97f 4559 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4560
5e69f97f 4561 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4562 reg_val &= 0x8cffffff;
4563 reg_val = 0x8c000000;
5e69f97f 4564 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4565
5e69f97f 4566 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4567 reg_val &= 0xffffff00;
5e69f97f 4568 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4569
5e69f97f 4570 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4571 reg_val &= 0x00ffffff;
4572 reg_val |= 0xb0000000;
5e69f97f 4573 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4574}
4575
b551842d
DV		 4576static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4577 struct intel_link_m_n *m_n)
4578{
4579 struct drm_device *dev = crtc->base.dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 int pipe = crtc->pipe;
4582
e3b95f1e
DV		 4583 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4584 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4585 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4586 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4587}
4588
4589static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4590 struct intel_link_m_n *m_n)
4591{
4592 struct drm_device *dev = crtc->base.dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 int pipe = crtc->pipe;
4595 enum transcoder transcoder = crtc->config.cpu_transcoder;
4596
4597 if (INTEL_INFO(dev)->gen >= 5) {
4598 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4599 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4600 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4601 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4602 } else {
e3b95f1e
DV		 4603 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4604 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4605 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4606 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4607 }
4608}
4609
03afc4a2
DV		 4610static void intel_dp_set_m_n(struct intel_crtc *crtc)
4611{
4612 if (crtc->config.has_pch_encoder)
4613 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4614 else
4615 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4616}
4617
f47709a9 4618static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4619{
f47709a9 4620 struct drm_device *dev = crtc->base.dev;
a0c4da24 4621 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4622 int pipe = crtc->pipe;
89b667f8 4623 u32 dpll, mdiv;
a0c4da24 4624 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4625 u32 coreclk, reg_val, dpll_md;
a0c4da24 4626
09153000
DV		 4627 mutex_lock(&dev_priv->dpio_lock);
4628
f47709a9
DV		 4629 bestn = crtc->config.dpll.n;
4630 bestm1 = crtc->config.dpll.m1;
4631 bestm2 = crtc->config.dpll.m2;
4632 bestp1 = crtc->config.dpll.p1;
4633 bestp2 = crtc->config.dpll.p2;
a0c4da24 4634
89b667f8
JB		 4635 /* See eDP HDMI DPIO driver vbios notes doc */
4636
4637 /* PLL B needs special handling */
4638 if (pipe)
5e69f97f 4639 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4640
4641 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4642 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4643
4644 /* Disable target IRef on PLL */
5e69f97f 4645 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4646 reg_val &= 0x00ffffff;
5e69f97f 4647 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4648
4649 /* Disable fast lock */
5e69f97f 4650 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4651
4652 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4653 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4654 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4655 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4656 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4657
4658 /*
4659 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4660 * but we don't support that).
4661 * Note: don't use the DAC post divider as it seems unstable.
4662 */
4663 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4664 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4665
a0c4da24 4666 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4667 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4668
89b667f8 4669 /* Set HBR and RBR LPF coefficients */
ff9a6750 4670 if (crtc->config.port_clock == 162000 ||
99750bd4 4671 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4672 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4673 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4674 0x009f0003);
89b667f8 4675 else
5e69f97f 4676 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4677 0x00d0000f);
4678
4679 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4680 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4681 /* Use SSC source */
4682 if (!pipe)
5e69f97f 4683 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4684 0x0df40000);
4685 else
5e69f97f 4686 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4687 0x0df70000);
4688 } else { /* HDMI or VGA */
4689 /* Use bend source */
4690 if (!pipe)
5e69f97f 4691 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4692 0x0df70000);
4693 else
5e69f97f 4694 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4695 0x0df40000);
4696 }
a0c4da24 4697
5e69f97f 4698 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4699 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4700 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4701 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4702 coreclk |= 0x01000000;
5e69f97f 4703 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4704
5e69f97f 4705 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4706
89b667f8
JB		 4707 /* Enable DPIO clock input */
4708 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4709 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4710 /* We should never disable this, set it here for state tracking */
4711 if (pipe == PIPE_B)
89b667f8 4712 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4713 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4714 crtc->config.dpll_hw_state.dpll = dpll;
4715
ef1b460d
DV		 4716 dpll_md = (crtc->config.pixel_multiplier - 1)
4717 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4718 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4719
89b667f8
JB		 4720 if (crtc->config.has_dp_encoder)
4721 intel_dp_set_m_n(crtc);
09153000
DV		 4722
4723 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4724}
4725
f47709a9
DV		 4726static void i9xx_update_pll(struct intel_crtc *crtc,
4727 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4728 int num_connectors)
4729{
f47709a9 4730 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4731 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4732 u32 dpll;
4733 bool is_sdvo;
f47709a9 4734 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4735
f47709a9 4736 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4737
f47709a9
DV		 4738 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4739 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4740
4741 dpll = DPLL_VGA_MODE_DIS;
4742
f47709a9 4743 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4744 dpll |= DPLLB_MODE_LVDS;
4745 else
4746 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4747
ef1b460d 4748 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4749 dpll |= (crtc->config.pixel_multiplier - 1)
4750 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4751 }
198a037f
DV		 4752
4753 if (is_sdvo)
4a33e48d 4754 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4755
f47709a9 4756 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4757 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4758
4759 /* compute bitmask from p1 value */
4760 if (IS_PINEVIEW(dev))
4761 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4762 else {
4763 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4764 if (IS_G4X(dev) && reduced_clock)
4765 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4766 }
4767 switch (clock->p2) {
4768 case 5:
4769 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4770 break;
4771 case 7:
4772 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4773 break;
4774 case 10:
4775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4776 break;
4777 case 14:
4778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4779 break;
4780 }
4781 if (INTEL_INFO(dev)->gen >= 4)
4782 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4783
09ede541 4784 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4785 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4786 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4787 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4788 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4789 else
4790 dpll |= PLL_REF_INPUT_DREFCLK;
4791
4792 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4793 crtc->config.dpll_hw_state.dpll = dpll;
4794
eb1cbe48 4795 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4796 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4797 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4798 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4799 }
66e3d5c0
DV		 4800
4801 if (crtc->config.has_dp_encoder)
4802 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4803}
4804
f47709a9 4805static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4806 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4807 int num_connectors)
4808{
f47709a9 4809 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4810 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4811 u32 dpll;
f47709a9 4812 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4813
f47709a9 4814 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4815
eb1cbe48
DV		 4816 dpll = DPLL_VGA_MODE_DIS;
4817
f47709a9 4818 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4819 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4820 } else {
4821 if (clock->p1 == 2)
4822 dpll |= PLL_P1_DIVIDE_BY_TWO;
4823 else
4824 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4825 if (clock->p2 == 4)
4826 dpll |= PLL_P2_DIVIDE_BY_4;
4827 }
4828
4a33e48d
DV		 4829 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4830 dpll |= DPLL_DVO_2X_MODE;
4831
f47709a9 4832 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4833 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4834 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4835 else
4836 dpll |= PLL_REF_INPUT_DREFCLK;
4837
4838 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4839 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4840}
4841
8a654f3b 4842static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4843{
4844 struct drm_device *dev = intel_crtc->base.dev;
4845 struct drm_i915_private *dev_priv = dev->dev_private;
4846 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4847 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4848 struct drm_display_mode *adjusted_mode =
4849 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4850 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4851
4852 /* We need to be careful not to changed the adjusted mode, for otherwise
4853 * the hw state checker will get angry at the mismatch. */
4854 crtc_vtotal = adjusted_mode->crtc_vtotal;
4855 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4856
4857 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4858 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4859 crtc_vtotal -= 1;
4860 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4861 vsyncshift = adjusted_mode->crtc_hsync_start
4862 - adjusted_mode->crtc_htotal / 2;
4863 } else {
4864 vsyncshift = 0;
4865 }
4866
4867 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4868 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4869
fe2b8f9d 4870 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4871 (adjusted_mode->crtc_hdisplay - 1) |
4872 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4873 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4874 (adjusted_mode->crtc_hblank_start - 1) |
4875 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4876 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4877 (adjusted_mode->crtc_hsync_start - 1) |
4878 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4879
fe2b8f9d 4880 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4881 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4882 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4883 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4884 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4885 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4886 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4887 (adjusted_mode->crtc_vsync_start - 1) |
4888 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4889
b5e508d4
PZ		 4890 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4891 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4892 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4893 * bits. */
4894 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4895 (pipe == PIPE_B || pipe == PIPE_C))
4896 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4897
b0e77b9c
PZ		 4898 /* pipesrc controls the size that is scaled from, which should
4899 * always be the user's requested size.
4900 */
4901 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4902 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4903 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4904}
4905
1bd1bd80
DV		 4906static void intel_get_pipe_timings(struct intel_crtc *crtc,
4907 struct intel_crtc_config *pipe_config)
4908{
4909 struct drm_device *dev = crtc->base.dev;
4910 struct drm_i915_private *dev_priv = dev->dev_private;
4911 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4912 uint32_t tmp;
4913
4914 tmp = I915_READ(HTOTAL(cpu_transcoder));
4915 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4916 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4917 tmp = I915_READ(HBLANK(cpu_transcoder));
4918 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4919 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4920 tmp = I915_READ(HSYNC(cpu_transcoder));
4921 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4922 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4923
4924 tmp = I915_READ(VTOTAL(cpu_transcoder));
4925 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4926 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4927 tmp = I915_READ(VBLANK(cpu_transcoder));
4928 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4929 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4930 tmp = I915_READ(VSYNC(cpu_transcoder));
4931 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4932 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4933
4934 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4935 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4936 pipe_config->adjusted_mode.crtc_vtotal += 1;
4937 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4938 }
4939
4940 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4941 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4942 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4943
4944 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4945 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4946}
4947
babea61d
JB		 4948static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4949 struct intel_crtc_config *pipe_config)
4950{
4951 struct drm_crtc *crtc = &intel_crtc->base;
4952
4953 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4954 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4955 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4956 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4957
4958 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4959 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4960 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4961 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4962
4963 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4964
241bfc38 4965 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4966 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4967}
4968
84b046f3
DV		 4969static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4970{
4971 struct drm_device *dev = intel_crtc->base.dev;
4972 struct drm_i915_private *dev_priv = dev->dev_private;
4973 uint32_t pipeconf;
4974
9f11a9e4 4975 pipeconf = 0;
84b046f3 4976
67c72a12
DV		 4977 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4978 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4979 pipeconf |= PIPECONF_ENABLE;
4980
cf532bb2
VS		 4981 if (intel_crtc->config.double_wide)
4982 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4983
ff9ce46e
DV		 4984 /* only g4x and later have fancy bpc/dither controls */
4985 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4986 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4987 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4988 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4989 PIPECONF_DITHER_TYPE_SP;
84b046f3 4990
ff9ce46e
DV		 4991 switch (intel_crtc->config.pipe_bpp) {
4992 case 18:
4993 pipeconf |= PIPECONF_6BPC;
4994 break;
4995 case 24:
4996 pipeconf |= PIPECONF_8BPC;
4997 break;
4998 case 30:
4999 pipeconf |= PIPECONF_10BPC;
5000 break;
5001 default:
5002 /* Case prevented by intel_choose_pipe_bpp_dither. */
5003 BUG();
84b046f3
DV		 5004 }
5005 }
5006
5007 if (HAS_PIPE_CXSR(dev)) {
5008 if (intel_crtc->lowfreq_avail) {
5009 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5010 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5011 } else {
5012 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5013 }
5014 }
5015
84b046f3
DV		 5016 if (!IS_GEN2(dev) &&
5017 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5018 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5019 else
5020 pipeconf |= PIPECONF_PROGRESSIVE;
5021
9f11a9e4
DV		 5022 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5023 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5024
84b046f3
DV		 5025 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5026 POSTING_READ(PIPECONF(intel_crtc->pipe));
5027}
5028
f564048e 5029static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5030 int x, int y,
94352cf9 5031 struct drm_framebuffer *fb)
79e53945
JB		 5032{
5033 struct drm_device *dev = crtc->dev;
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5036 int pipe = intel_crtc->pipe;
80824003 5037 int plane = intel_crtc->plane;
c751ce4f 5038 int refclk, num_connectors = 0;
652c393a 5039 intel_clock_t clock, reduced_clock;
84b046f3 5040 u32 dspcntr;
a16af721 5041 bool ok, has_reduced_clock = false;
e9fd1c02 5042 bool is_lvds = false, is_dsi = false;
5eddb70b 5043 struct intel_encoder *encoder;
d4906093 5044 const intel_limit_t *limit;
5c3b82e2 5045 int ret;
79e53945 5046
6c2b7c12 5047 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5048 switch (encoder->type) {
79e53945
JB		 5049 case INTEL_OUTPUT_LVDS:
5050 is_lvds = true;
5051 break;
e9fd1c02
JN		 5052 case INTEL_OUTPUT_DSI:
5053 is_dsi = true;
5054 break;
79e53945 5055 }
43565a06 5056
c751ce4f 5057 num_connectors++;
79e53945
JB		 5058 }
5059
f2335330
JN		 5060 if (is_dsi)
5061 goto skip_dpll;
5062
5063 if (!intel_crtc->config.clock_set) {
5064 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5065
e9fd1c02
JN		 5066 /*
5067 * Returns a set of divisors for the desired target clock with
5068 * the given refclk, or FALSE. The returned values represent
5069 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5070 * 2) / p1 / p2.
5071 */
5072 limit = intel_limit(crtc, refclk);
5073 ok = dev_priv->display.find_dpll(limit, crtc,
5074 intel_crtc->config.port_clock,
5075 refclk, NULL, &clock);
f2335330 5076 if (!ok) {
e9fd1c02
JN		 5077 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5078 return -EINVAL;
5079 }
79e53945 5080
f2335330
JN		 5081 if (is_lvds && dev_priv->lvds_downclock_avail) {
5082 /*
5083 * Ensure we match the reduced clock's P to the target
5084 * clock. If the clocks don't match, we can't switch
5085 * the display clock by using the FP0/FP1. In such case
5086 * we will disable the LVDS downclock feature.
5087 */
5088 has_reduced_clock =
5089 dev_priv->display.find_dpll(limit, crtc,
5090 dev_priv->lvds_downclock,
5091 refclk, &clock,
5092 &reduced_clock);
5093 }
5094 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5095 intel_crtc->config.dpll.n = clock.n;
5096 intel_crtc->config.dpll.m1 = clock.m1;
5097 intel_crtc->config.dpll.m2 = clock.m2;
5098 intel_crtc->config.dpll.p1 = clock.p1;
5099 intel_crtc->config.dpll.p2 = clock.p2;
5100 }
7026d4ac 5101
e9fd1c02 5102 if (IS_GEN2(dev)) {
8a654f3b 5103 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5104 has_reduced_clock ? &reduced_clock : NULL,
5105 num_connectors);
e9fd1c02 5106 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5107 vlv_update_pll(intel_crtc);
e9fd1c02 5108 } else {
f47709a9 5109 i9xx_update_pll(intel_crtc,
eb1cbe48 5110 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5111 num_connectors);
e9fd1c02 5112 }
79e53945 5113
f2335330 5114skip_dpll:
79e53945
JB		 5115 /* Set up the display plane register */
5116 dspcntr = DISPPLANE_GAMMA_ENABLE;
5117
da6ecc5d
JB		 5118 if (!IS_VALLEYVIEW(dev)) {
5119 if (pipe == 0)
5120 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5121 else
5122 dspcntr |= DISPPLANE_SEL_PIPE_B;
5123 }
79e53945 5124
8a654f3b 5125 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5126
5127 /* pipesrc and dspsize control the size that is scaled from,
5128 * which should always be the user's requested size.
79e53945 5129 */
929c77fb 5130 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5131 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5132 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5133 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5134
84b046f3
DV		 5135 i9xx_set_pipeconf(intel_crtc);
5136
f564048e
EA		 5137 I915_WRITE(DSPCNTR(plane), dspcntr);
5138 POSTING_READ(DSPCNTR(plane));
5139
94352cf9 5140 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5141
f564048e
EA		 5142 return ret;
5143}
5144
2fa2fe9a
DV		 5145static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5146 struct intel_crtc_config *pipe_config)
5147{
5148 struct drm_device *dev = crtc->base.dev;
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5150 uint32_t tmp;
5151
5152 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5153 if (!(tmp & PFIT_ENABLE))
5154 return;
2fa2fe9a 5155
06922821 5156 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5157 if (INTEL_INFO(dev)->gen < 4) {
5158 if (crtc->pipe != PIPE_B)
5159 return;
2fa2fe9a
DV		 5160 } else {
5161 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5162 return;
5163 }
5164
06922821 5165 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5166 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5167 if (INTEL_INFO(dev)->gen < 5)
5168 pipe_config->gmch_pfit.lvds_border_bits =
5169 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5170}
5171
acbec814
JB		 5172static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5173 struct intel_crtc_config *pipe_config)
5174{
5175 struct drm_device *dev = crtc->base.dev;
5176 struct drm_i915_private *dev_priv = dev->dev_private;
5177 int pipe = pipe_config->cpu_transcoder;
5178 intel_clock_t clock;
5179 u32 mdiv;
662c6ecb 5180 int refclk = 100000;
acbec814
JB		 5181
5182 mutex_lock(&dev_priv->dpio_lock);
5183 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5184 mutex_unlock(&dev_priv->dpio_lock);
5185
5186 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5187 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5188 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5189 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5190 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5191
662c6ecb
CW		 5192 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5193 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5194
5195 pipe_config->port_clock = clock.dot / 10;
5196}
5197
0e8ffe1b
DV		 5198static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5199 struct intel_crtc_config *pipe_config)
5200{
5201 struct drm_device *dev = crtc->base.dev;
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 uint32_t tmp;
5204
e143a21c 5205 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5206 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5207
0e8ffe1b
DV		 5208 tmp = I915_READ(PIPECONF(crtc->pipe));
5209 if (!(tmp & PIPECONF_ENABLE))
5210 return false;
5211
42571aef
VS		 5212 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5213 switch (tmp & PIPECONF_BPC_MASK) {
5214 case PIPECONF_6BPC:
5215 pipe_config->pipe_bpp = 18;
5216 break;
5217 case PIPECONF_8BPC:
5218 pipe_config->pipe_bpp = 24;
5219 break;
5220 case PIPECONF_10BPC:
5221 pipe_config->pipe_bpp = 30;
5222 break;
5223 default:
5224 break;
5225 }
5226 }
5227
282740f7
VS		 5228 if (INTEL_INFO(dev)->gen < 4)
5229 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5230
1bd1bd80
DV		 5231 intel_get_pipe_timings(crtc, pipe_config);
5232
2fa2fe9a
DV		 5233 i9xx_get_pfit_config(crtc, pipe_config);
5234
6c49f241
DV		 5235 if (INTEL_INFO(dev)->gen >= 4) {
5236 tmp = I915_READ(DPLL_MD(crtc->pipe));
5237 pipe_config->pixel_multiplier =
5238 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5239 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5240 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5241 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5242 tmp = I915_READ(DPLL(crtc->pipe));
5243 pipe_config->pixel_multiplier =
5244 ((tmp & SDVO_MULTIPLIER_MASK)
5245 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5246 } else {
5247 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5248 * port and will be fixed up in the encoder->get_config
5249 * function. */
5250 pipe_config->pixel_multiplier = 1;
5251 }
8bcc2795
DV		 5252 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5253 if (!IS_VALLEYVIEW(dev)) {
5254 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5255 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5256 } else {
5257 /* Mask out read-only status bits. */
5258 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5259 DPLL_PORTC_READY_MASK |
5260 DPLL_PORTB_READY_MASK);
8bcc2795 5261 }
6c49f241 5262
acbec814
JB		 5263 if (IS_VALLEYVIEW(dev))
5264 vlv_crtc_clock_get(crtc, pipe_config);
5265 else
5266 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5267
0e8ffe1b
DV		 5268 return true;
5269}
5270
dde86e2d 5271static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5272{
5273 struct drm_i915_private *dev_priv = dev->dev_private;
5274 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5275 struct intel_encoder *encoder;
74cfd7ac 5276 u32 val, final;
13d83a67 5277 bool has_lvds = false;
199e5d79 5278 bool has_cpu_edp = false;
199e5d79 5279 bool has_panel = false;
99eb6a01
KP		 5280 bool has_ck505 = false;
5281 bool can_ssc = false;
13d83a67
JB		 5282
5283 /* We need to take the global config into account */
199e5d79
KP		 5284 list_for_each_entry(encoder, &mode_config->encoder_list,
5285 base.head) {
5286 switch (encoder->type) {
5287 case INTEL_OUTPUT_LVDS:
5288 has_panel = true;
5289 has_lvds = true;
5290 break;
5291 case INTEL_OUTPUT_EDP:
5292 has_panel = true;
2de6905f 5293 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5294 has_cpu_edp = true;
5295 break;
13d83a67
JB		 5296 }
5297 }
5298
99eb6a01 5299 if (HAS_PCH_IBX(dev)) {
41aa3448 5300 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5301 can_ssc = has_ck505;
5302 } else {
5303 has_ck505 = false;
5304 can_ssc = true;
5305 }
5306
2de6905f
ID		 5307 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5308 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5309
5310 /* Ironlake: try to setup display ref clock before DPLL
5311 * enabling. This is only under driver's control after
5312 * PCH B stepping, previous chipset stepping should be
5313 * ignoring this setting.
5314 */
74cfd7ac
CW		 5315 val = I915_READ(PCH_DREF_CONTROL);
5316
5317 /* As we must carefully and slowly disable/enable each source in turn,
5318 * compute the final state we want first and check if we need to
5319 * make any changes at all.
5320 */
5321 final = val;
5322 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5323 if (has_ck505)
5324 final |= DREF_NONSPREAD_CK505_ENABLE;
5325 else
5326 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5327
5328 final &= ~DREF_SSC_SOURCE_MASK;
5329 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5330 final &= ~DREF_SSC1_ENABLE;
5331
5332 if (has_panel) {
5333 final |= DREF_SSC_SOURCE_ENABLE;
5334
5335 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5336 final |= DREF_SSC1_ENABLE;
5337
5338 if (has_cpu_edp) {
5339 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5340 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5341 else
5342 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5343 } else
5344 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5345 } else {
5346 final |= DREF_SSC_SOURCE_DISABLE;
5347 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5348 }
5349
5350 if (final == val)
5351 return;
5352
13d83a67 5353 /* Always enable nonspread source */
74cfd7ac 5354 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5355
99eb6a01 5356 if (has_ck505)
74cfd7ac 5357 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5358 else
74cfd7ac 5359 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5360
199e5d79 5361 if (has_panel) {
74cfd7ac
CW		 5362 val &= ~DREF_SSC_SOURCE_MASK;
5363 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5364
199e5d79 5365 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5366 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5367 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5368 val |= DREF_SSC1_ENABLE;
e77166b5 5369 } else
74cfd7ac 5370 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5371
5372 /* Get SSC going before enabling the outputs */
74cfd7ac 5373 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5374 POSTING_READ(PCH_DREF_CONTROL);
5375 udelay(200);
5376
74cfd7ac 5377 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5378
5379 /* Enable CPU source on CPU attached eDP */
199e5d79 5380 if (has_cpu_edp) {
99eb6a01 5381 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5382 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5383 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5384 }
13d83a67 5385 else
74cfd7ac 5386 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5387 } else
74cfd7ac 5388 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5389
74cfd7ac 5390 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5391 POSTING_READ(PCH_DREF_CONTROL);
5392 udelay(200);
5393 } else {
5394 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5395
74cfd7ac 5396 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5397
5398 /* Turn off CPU output */
74cfd7ac 5399 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5400
74cfd7ac 5401 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5402 POSTING_READ(PCH_DREF_CONTROL);
5403 udelay(200);
5404
5405 /* Turn off the SSC source */
74cfd7ac
CW		 5406 val &= ~DREF_SSC_SOURCE_MASK;
5407 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5408
5409 /* Turn off SSC1 */
74cfd7ac 5410 val &= ~DREF_SSC1_ENABLE;
199e5d79 5411
74cfd7ac 5412 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5413 POSTING_READ(PCH_DREF_CONTROL);
5414 udelay(200);
5415 }
74cfd7ac
CW		 5416
5417 BUG_ON(val != final);
13d83a67
JB		 5418}
5419
f31f2d55 5420static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5421{
f31f2d55 5422 uint32_t tmp;
dde86e2d 5423
0ff066a9
PZ		 5424 tmp = I915_READ(SOUTH_CHICKEN2);
5425 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5426 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5427
0ff066a9
PZ		 5428 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5429 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5430 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5431
0ff066a9
PZ		 5432 tmp = I915_READ(SOUTH_CHICKEN2);
5433 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5434 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5435
0ff066a9
PZ		 5436 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5437 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5438 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5439}
5440
5441/* WaMPhyProgramming:hsw */
5442static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5443{
5444 uint32_t tmp;
dde86e2d
PZ		 5445
5446 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5447 tmp &= ~(0xFF << 24);
5448 tmp |= (0x12 << 24);
5449 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5450
dde86e2d
PZ		 5451 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5452 tmp |= (1 << 11);
5453 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5454
5455 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5456 tmp |= (1 << 11);
5457 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5458
dde86e2d
PZ		 5459 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5460 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5461 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5462
5463 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5464 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5465 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5466
0ff066a9
PZ		 5467 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5468 tmp &= ~(7 << 13);
5469 tmp |= (5 << 13);
5470 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5471
0ff066a9
PZ		 5472 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5473 tmp &= ~(7 << 13);
5474 tmp |= (5 << 13);
5475 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5476
5477 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5478 tmp &= ~0xFF;
5479 tmp |= 0x1C;
5480 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5481
5482 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5483 tmp &= ~0xFF;
5484 tmp |= 0x1C;
5485 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5486
5487 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5488 tmp &= ~(0xFF << 16);
5489 tmp |= (0x1C << 16);
5490 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5491
5492 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5493 tmp &= ~(0xFF << 16);
5494 tmp |= (0x1C << 16);
5495 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5496
0ff066a9
PZ		 5497 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5498 tmp |= (1 << 27);
5499 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5500
0ff066a9
PZ		 5501 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5502 tmp |= (1 << 27);
5503 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5504
0ff066a9
PZ		 5505 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5506 tmp &= ~(0xF << 28);
5507 tmp |= (4 << 28);
5508 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5509
0ff066a9
PZ		 5510 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5511 tmp &= ~(0xF << 28);
5512 tmp |= (4 << 28);
5513 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5514}
5515
2fa86a1f
PZ		 5516/* Implements 3 different sequences from BSpec chapter "Display iCLK
5517 * Programming" based on the parameters passed:
5518 * - Sequence to enable CLKOUT_DP
5519 * - Sequence to enable CLKOUT_DP without spread
5520 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5521 */
5522static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5523 bool with_fdi)
f31f2d55
PZ		 5524{
5525 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5526 uint32_t reg, tmp;
5527
5528 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5529 with_spread = true;
5530 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5531 with_fdi, "LP PCH doesn't have FDI\n"))
5532 with_fdi = false;
f31f2d55
PZ		 5533
5534 mutex_lock(&dev_priv->dpio_lock);
5535
5536 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5537 tmp &= ~SBI_SSCCTL_DISABLE;
5538 tmp |= SBI_SSCCTL_PATHALT;
5539 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5540
5541 udelay(24);
5542
2fa86a1f
PZ		 5543 if (with_spread) {
5544 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5545 tmp &= ~SBI_SSCCTL_PATHALT;
5546 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5547
2fa86a1f
PZ		 5548 if (with_fdi) {
5549 lpt_reset_fdi_mphy(dev_priv);
5550 lpt_program_fdi_mphy(dev_priv);
5551 }
5552 }
dde86e2d 5553
2fa86a1f
PZ		 5554 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5555 SBI_GEN0 : SBI_DBUFF0;
5556 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5557 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5558 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5559
5560 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5561}
5562
47701c3b
PZ		 5563/* Sequence to disable CLKOUT_DP */
5564static void lpt_disable_clkout_dp(struct drm_device *dev)
5565{
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 uint32_t reg, tmp;
5568
5569 mutex_lock(&dev_priv->dpio_lock);
5570
5571 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5572 SBI_GEN0 : SBI_DBUFF0;
5573 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5574 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5575 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5576
5577 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5578 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5579 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5580 tmp |= SBI_SSCCTL_PATHALT;
5581 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5582 udelay(32);
5583 }
5584 tmp |= SBI_SSCCTL_DISABLE;
5585 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5586 }
5587
5588 mutex_unlock(&dev_priv->dpio_lock);
5589}
5590
bf8fa3d3
PZ		 5591static void lpt_init_pch_refclk(struct drm_device *dev)
5592{
5593 struct drm_mode_config *mode_config = &dev->mode_config;
5594 struct intel_encoder *encoder;
5595 bool has_vga = false;
5596
5597 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5598 switch (encoder->type) {
5599 case INTEL_OUTPUT_ANALOG:
5600 has_vga = true;
5601 break;
5602 }
5603 }
5604
47701c3b
PZ		 5605 if (has_vga)
5606 lpt_enable_clkout_dp(dev, true, true);
5607 else
5608 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5609}
5610
dde86e2d
PZ		 5611/*
5612 * Initialize reference clocks when the driver loads
5613 */
5614void intel_init_pch_refclk(struct drm_device *dev)
5615{
5616 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5617 ironlake_init_pch_refclk(dev);
5618 else if (HAS_PCH_LPT(dev))
5619 lpt_init_pch_refclk(dev);
5620}
5621
d9d444cb
JB		 5622static int ironlake_get_refclk(struct drm_crtc *crtc)
5623{
5624 struct drm_device *dev = crtc->dev;
5625 struct drm_i915_private *dev_priv = dev->dev_private;
5626 struct intel_encoder *encoder;
d9d444cb
JB		 5627 int num_connectors = 0;
5628 bool is_lvds = false;
5629
6c2b7c12 5630 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5631 switch (encoder->type) {
5632 case INTEL_OUTPUT_LVDS:
5633 is_lvds = true;
5634 break;
d9d444cb
JB		 5635 }
5636 num_connectors++;
5637 }
5638
5639 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5640 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5641 dev_priv->vbt.lvds_ssc_freq);
5642 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5643 }
5644
5645 return 120000;
5646}
5647
6ff93609 5648static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5649{
c8203565 5650 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5652 int pipe = intel_crtc->pipe;
c8203565
PZ		 5653 uint32_t val;
5654
78114071 5655 val = 0;
c8203565 5656
965e0c48 5657 switch (intel_crtc->config.pipe_bpp) {
c8203565 5658 case 18:
dfd07d72 5659 val |= PIPECONF_6BPC;
c8203565
PZ		 5660 break;
5661 case 24:
dfd07d72 5662 val |= PIPECONF_8BPC;
c8203565
PZ		 5663 break;
5664 case 30:
dfd07d72 5665 val |= PIPECONF_10BPC;
c8203565
PZ		 5666 break;
5667 case 36:
dfd07d72 5668 val |= PIPECONF_12BPC;
c8203565
PZ		 5669 break;
5670 default:
cc769b62
PZ		 5671 /* Case prevented by intel_choose_pipe_bpp_dither. */
5672 BUG();
c8203565
PZ		 5673 }
5674
d8b32247 5675 if (intel_crtc->config.dither)
c8203565
PZ		 5676 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5677
6ff93609 5678 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5679 val |= PIPECONF_INTERLACED_ILK;
5680 else
5681 val |= PIPECONF_PROGRESSIVE;
5682
50f3b016 5683 if (intel_crtc->config.limited_color_range)
3685a8f3 5684 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5685
c8203565
PZ		 5686 I915_WRITE(PIPECONF(pipe), val);
5687 POSTING_READ(PIPECONF(pipe));
5688}
5689
86d3efce
VS		 5690/*
5691 * Set up the pipe CSC unit.
5692 *
5693 * Currently only full range RGB to limited range RGB conversion
5694 * is supported, but eventually this should handle various
5695 * RGB<->YCbCr scenarios as well.
5696 */
50f3b016 5697static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5698{
5699 struct drm_device *dev = crtc->dev;
5700 struct drm_i915_private *dev_priv = dev->dev_private;
5701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5702 int pipe = intel_crtc->pipe;
5703 uint16_t coeff = 0x7800; /* 1.0 */
5704
5705 /*
5706 * TODO: Check what kind of values actually come out of the pipe
5707 * with these coeff/postoff values and adjust to get the best
5708 * accuracy. Perhaps we even need to take the bpc value into
5709 * consideration.
5710 */
5711
50f3b016 5712 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5713 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5714
5715 /*
5716 * GY/GU and RY/RU should be the other way around according
5717 * to BSpec, but reality doesn't agree. Just set them up in
5718 * a way that results in the correct picture.
5719 */
5720 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5721 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5722
5723 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5724 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5725
5726 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5727 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5728
5729 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5730 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5731 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5732
5733 if (INTEL_INFO(dev)->gen > 6) {
5734 uint16_t postoff = 0;
5735
50f3b016 5736 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5737 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5738
5739 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5740 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5741 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5742
5743 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5744 } else {
5745 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5746
50f3b016 5747 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5748 mode |= CSC_BLACK_SCREEN_OFFSET;
5749
5750 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5751 }
5752}
5753
6ff93609 5754static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5755{
5756 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5758 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5759 uint32_t val;
5760
3eff4faa 5761 val = 0;
ee2b0b38 5762
d8b32247 5763 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5764 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5765
6ff93609 5766 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5767 val |= PIPECONF_INTERLACED_ILK;
5768 else
5769 val |= PIPECONF_PROGRESSIVE;
5770
702e7a56
PZ		 5771 I915_WRITE(PIPECONF(cpu_transcoder), val);
5772 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5773
5774 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5775 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5776}
5777
6591c6e4 5778static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5779 intel_clock_t *clock,
5780 bool *has_reduced_clock,
5781 intel_clock_t *reduced_clock)
5782{
5783 struct drm_device *dev = crtc->dev;
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 struct intel_encoder *intel_encoder;
5786 int refclk;
d4906093 5787 const intel_limit_t *limit;
a16af721 5788 bool ret, is_lvds = false;
79e53945 5789
6591c6e4
PZ		 5790 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5791 switch (intel_encoder->type) {
79e53945
JB		 5792 case INTEL_OUTPUT_LVDS:
5793 is_lvds = true;
5794 break;
79e53945
JB		 5795 }
5796 }
5797
d9d444cb 5798 refclk = ironlake_get_refclk(crtc);
79e53945 5799
d4906093
ML		 5800 /*
5801 * Returns a set of divisors for the desired target clock with the given
5802 * refclk, or FALSE. The returned values represent the clock equation:
5803 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5804 */
1b894b59 5805 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5806 ret = dev_priv->display.find_dpll(limit, crtc,
5807 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5808 refclk, NULL, clock);
6591c6e4
PZ		 5809 if (!ret)
5810 return false;
cda4b7d3 5811
ddc9003c 5812 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5813 /*
5814 * Ensure we match the reduced clock's P to the target clock.
5815 * If the clocks don't match, we can't switch the display clock
5816 * by using the FP0/FP1. In such case we will disable the LVDS
5817 * downclock feature.
5818 */
ee9300bb
DV		 5819 *has_reduced_clock =
5820 dev_priv->display.find_dpll(limit, crtc,
5821 dev_priv->lvds_downclock,
5822 refclk, clock,
5823 reduced_clock);
652c393a 5824 }
61e9653f 5825
6591c6e4
PZ		 5826 return true;
5827}
5828
01a415fd
DV		 5829static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5830{
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 uint32_t temp;
5833
5834 temp = I915_READ(SOUTH_CHICKEN1);
5835 if (temp & FDI_BC_BIFURCATION_SELECT)
5836 return;
5837
5838 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5839 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5840
5841 temp |= FDI_BC_BIFURCATION_SELECT;
5842 DRM_DEBUG_KMS("enabling fdi C rx\n");
5843 I915_WRITE(SOUTH_CHICKEN1, temp);
5844 POSTING_READ(SOUTH_CHICKEN1);
5845}
5846
ebfd86fd 5847static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5848{
5849 struct drm_device *dev = intel_crtc->base.dev;
5850 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5851
5852 switch (intel_crtc->pipe) {
5853 case PIPE_A:
ebfd86fd 5854 break;
01a415fd 5855 case PIPE_B:
ebfd86fd 5856 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5857 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5858 else
5859 cpt_enable_fdi_bc_bifurcation(dev);
5860
ebfd86fd 5861 break;
01a415fd 5862 case PIPE_C:
01a415fd
DV		 5863 cpt_enable_fdi_bc_bifurcation(dev);
5864
ebfd86fd 5865 break;
01a415fd
DV		 5866 default:
5867 BUG();
5868 }
5869}
5870
d4b1931c
PZ		 5871int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5872{
5873 /*
5874 * Account for spread spectrum to avoid
5875 * oversubscribing the link. Max center spread
5876 * is 2.5%; use 5% for safety's sake.
5877 */
5878 u32 bps = target_clock * bpp * 21 / 20;
5879 return bps / (link_bw * 8) + 1;
5880}
5881
7429e9d4 5882static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5883{
7429e9d4 5884 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5885}
5886
de13a2e3 5887static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5888 u32 *fp,
9a7c7890 5889 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5890{
de13a2e3 5891 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5892 struct drm_device *dev = crtc->dev;
5893 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5894 struct intel_encoder *intel_encoder;
5895 uint32_t dpll;
6cc5f341 5896 int factor, num_connectors = 0;
09ede541 5897 bool is_lvds = false, is_sdvo = false;
79e53945 5898
de13a2e3
PZ		 5899 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5900 switch (intel_encoder->type) {
79e53945
JB		 5901 case INTEL_OUTPUT_LVDS:
5902 is_lvds = true;
5903 break;
5904 case INTEL_OUTPUT_SDVO:
7d57382e 5905 case INTEL_OUTPUT_HDMI:
79e53945 5906 is_sdvo = true;
79e53945 5907 break;
79e53945 5908 }
43565a06 5909
c751ce4f 5910 num_connectors++;
79e53945 5911 }
79e53945 5912
c1858123 5913 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5914 factor = 21;
5915 if (is_lvds) {
5916 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5917 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5918 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5919 factor = 25;
09ede541 5920 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5921 factor = 20;
c1858123 5922
7429e9d4 5923 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5924 *fp |= FP_CB_TUNE;
2c07245f 5925
9a7c7890
DV		 5926 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5927 *fp2 |= FP_CB_TUNE;
5928
5eddb70b 5929 dpll = 0;
2c07245f 5930
a07d6787
EA		 5931 if (is_lvds)
5932 dpll |= DPLLB_MODE_LVDS;
5933 else
5934 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5935
ef1b460d
DV		 5936 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5937 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5938
5939 if (is_sdvo)
4a33e48d 5940 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5941 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5942 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5943
a07d6787 5944 /* compute bitmask from p1 value */
7429e9d4 5945 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5946 /* also FPA1 */
7429e9d4 5947 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5948
7429e9d4 5949 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5950 case 5:
5951 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5952 break;
5953 case 7:
5954 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5955 break;
5956 case 10:
5957 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5958 break;
5959 case 14:
5960 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5961 break;
79e53945
JB		 5962 }
5963
b4c09f3b 5964 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5965 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5966 else
5967 dpll |= PLL_REF_INPUT_DREFCLK;
5968
959e16d6 5969 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5970}
5971
5972static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5973 int x, int y,
5974 struct drm_framebuffer *fb)
5975{
5976 struct drm_device *dev = crtc->dev;
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5979 int pipe = intel_crtc->pipe;
5980 int plane = intel_crtc->plane;
5981 int num_connectors = 0;
5982 intel_clock_t clock, reduced_clock;
cbbab5bd 5983 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5984 bool ok, has_reduced_clock = false;
8b47047b 5985 bool is_lvds = false;
de13a2e3 5986 struct intel_encoder *encoder;
e2b78267 5987 struct intel_shared_dpll *pll;
de13a2e3 5988 int ret;
de13a2e3
PZ		 5989
5990 for_each_encoder_on_crtc(dev, crtc, encoder) {
5991 switch (encoder->type) {
5992 case INTEL_OUTPUT_LVDS:
5993 is_lvds = true;
5994 break;
de13a2e3
PZ		 5995 }
5996
5997 num_connectors++;
a07d6787 5998 }
79e53945 5999
5dc5298b
PZ		 6000 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6001 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6002
ff9a6750 6003 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6004 &has_reduced_clock, &reduced_clock);
ee9300bb 6005 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6006 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6007 return -EINVAL;
79e53945 6008 }
f47709a9
DV		 6009 /* Compat-code for transition, will disappear. */
6010 if (!intel_crtc->config.clock_set) {
6011 intel_crtc->config.dpll.n = clock.n;
6012 intel_crtc->config.dpll.m1 = clock.m1;
6013 intel_crtc->config.dpll.m2 = clock.m2;
6014 intel_crtc->config.dpll.p1 = clock.p1;
6015 intel_crtc->config.dpll.p2 = clock.p2;
6016 }
79e53945 6017
5dc5298b 6018 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6019 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6020 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6021 if (has_reduced_clock)
7429e9d4 6022 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6023
7429e9d4 6024 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6025 &fp, &reduced_clock,
6026 has_reduced_clock ? &fp2 : NULL);
6027
959e16d6 6028 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6029 intel_crtc->config.dpll_hw_state.fp0 = fp;
6030 if (has_reduced_clock)
6031 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6032 else
6033 intel_crtc->config.dpll_hw_state.fp1 = fp;
6034
b89a1d39 6035 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6036 if (pll == NULL) {
84f44ce7
VS		 6037 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6038 pipe_name(pipe));
4b645f14
JB		 6039 return -EINVAL;
6040 }
ee7b9f93 6041 } else
e72f9fbf 6042 intel_put_shared_dpll(intel_crtc);
79e53945 6043
03afc4a2
DV		 6044 if (intel_crtc->config.has_dp_encoder)
6045 intel_dp_set_m_n(intel_crtc);
79e53945 6046
bcd644e0
DV		 6047 if (is_lvds && has_reduced_clock && i915_powersave)
6048 intel_crtc->lowfreq_avail = true;
6049 else
6050 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6051
6052 if (intel_crtc->config.has_pch_encoder) {
6053 pll = intel_crtc_to_shared_dpll(intel_crtc);
6054
652c393a
JB		 6055 }
6056
8a654f3b 6057 intel_set_pipe_timings(intel_crtc);
5eddb70b 6058
ca3a0ff8 6059 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6060 intel_cpu_transcoder_set_m_n(intel_crtc,
6061 &intel_crtc->config.fdi_m_n);
6062 }
2c07245f 6063
ebfd86fd
DV		 6064 if (IS_IVYBRIDGE(dev))
6065 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6066
6ff93609 6067 ironlake_set_pipeconf(crtc);
79e53945 6068
a1f9e77e
PZ		 6069 /* Set up the display plane register */
6070 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6071 POSTING_READ(DSPCNTR(plane));
79e53945 6072
94352cf9 6073 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6074
1857e1da 6075 return ret;
79e53945
JB		 6076}
6077
eb14cb74
VS		 6078static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6079 struct intel_link_m_n *m_n)
6080{
6081 struct drm_device *dev = crtc->base.dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 enum pipe pipe = crtc->pipe;
6084
6085 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6086 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6087 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6088 & ~TU_SIZE_MASK;
6089 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6090 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6091 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6092}
6093
6094static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6095 enum transcoder transcoder,
6096 struct intel_link_m_n *m_n)
72419203
DV		 6097{
6098 struct drm_device *dev = crtc->base.dev;
6099 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6100 enum pipe pipe = crtc->pipe;
72419203 6101
eb14cb74
VS		 6102 if (INTEL_INFO(dev)->gen >= 5) {
6103 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6104 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6105 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6106 & ~TU_SIZE_MASK;
6107 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6108 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6109 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6110 } else {
6111 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6112 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6113 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6114 & ~TU_SIZE_MASK;
6115 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6116 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6117 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6118 }
6119}
6120
6121void intel_dp_get_m_n(struct intel_crtc *crtc,
6122 struct intel_crtc_config *pipe_config)
6123{
6124 if (crtc->config.has_pch_encoder)
6125 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6126 else
6127 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6128 &pipe_config->dp_m_n);
6129}
72419203 6130
eb14cb74
VS		 6131static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6132 struct intel_crtc_config *pipe_config)
6133{
6134 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6135 &pipe_config->fdi_m_n);
72419203
DV		 6136}
6137
2fa2fe9a
DV		 6138static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6139 struct intel_crtc_config *pipe_config)
6140{
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143 uint32_t tmp;
6144
6145 tmp = I915_READ(PF_CTL(crtc->pipe));
6146
6147 if (tmp & PF_ENABLE) {
fd4daa9c 6148 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6149 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6150 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6151
6152 /* We currently do not free assignements of panel fitters on
6153 * ivb/hsw (since we don't use the higher upscaling modes which
6154 * differentiates them) so just WARN about this case for now. */
6155 if (IS_GEN7(dev)) {
6156 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6157 PF_PIPE_SEL_IVB(crtc->pipe));
6158 }
2fa2fe9a 6159 }
79e53945
JB		 6160}
6161
0e8ffe1b
DV		 6162static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6163 struct intel_crtc_config *pipe_config)
6164{
6165 struct drm_device *dev = crtc->base.dev;
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167 uint32_t tmp;
6168
e143a21c 6169 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6170 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6171
0e8ffe1b
DV		 6172 tmp = I915_READ(PIPECONF(crtc->pipe));
6173 if (!(tmp & PIPECONF_ENABLE))
6174 return false;
6175
42571aef
VS		 6176 switch (tmp & PIPECONF_BPC_MASK) {
6177 case PIPECONF_6BPC:
6178 pipe_config->pipe_bpp = 18;
6179 break;
6180 case PIPECONF_8BPC:
6181 pipe_config->pipe_bpp = 24;
6182 break;
6183 case PIPECONF_10BPC:
6184 pipe_config->pipe_bpp = 30;
6185 break;
6186 case PIPECONF_12BPC:
6187 pipe_config->pipe_bpp = 36;
6188 break;
6189 default:
6190 break;
6191 }
6192
ab9412ba 6193 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6194 struct intel_shared_dpll *pll;
6195
88adfff1
DV		 6196 pipe_config->has_pch_encoder = true;
6197
627eb5a3
DV		 6198 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6199 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6200 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6201
6202 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6203
c0d43d62 6204 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6205 pipe_config->shared_dpll =
6206 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6207 } else {
6208 tmp = I915_READ(PCH_DPLL_SEL);
6209 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6210 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6211 else
6212 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6213 }
66e985c0
DV		 6214
6215 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6216
6217 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6218 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6219
6220 tmp = pipe_config->dpll_hw_state.dpll;
6221 pipe_config->pixel_multiplier =
6222 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6223 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6224
6225 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6226 } else {
6227 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6228 }
6229
1bd1bd80
DV		 6230 intel_get_pipe_timings(crtc, pipe_config);
6231
2fa2fe9a
DV		 6232 ironlake_get_pfit_config(crtc, pipe_config);
6233
0e8ffe1b
DV		 6234 return true;
6235}
6236
be256dc7
PZ		 6237static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6238{
6239 struct drm_device *dev = dev_priv->dev;
6240 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6241 struct intel_crtc *crtc;
6242 unsigned long irqflags;
bd633a7c 6243 uint32_t val;
be256dc7
PZ		 6244
6245 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6246 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6247 pipe_name(crtc->pipe));
6248
6249 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6250 WARN(plls->spll_refcount, "SPLL enabled\n");
6251 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6252 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6253 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6254 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6255 "CPU PWM1 enabled\n");
6256 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6257 "CPU PWM2 enabled\n");
6258 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6259 "PCH PWM1 enabled\n");
6260 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6261 "Utility pin enabled\n");
6262 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6263
6264 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6265 val = I915_READ(DEIMR);
6266 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6267 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6268 val = I915_READ(SDEIMR);
bd633a7c 6269 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6270 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6271 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6272}
6273
6274/*
6275 * This function implements pieces of two sequences from BSpec:
6276 * - Sequence for display software to disable LCPLL
6277 * - Sequence for display software to allow package C8+
6278 * The steps implemented here are just the steps that actually touch the LCPLL
6279 * register. Callers should take care of disabling all the display engine
6280 * functions, doing the mode unset, fixing interrupts, etc.
6281 */
6ff58d53
PZ		 6282static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6283 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6284{
6285 uint32_t val;
6286
6287 assert_can_disable_lcpll(dev_priv);
6288
6289 val = I915_READ(LCPLL_CTL);
6290
6291 if (switch_to_fclk) {
6292 val |= LCPLL_CD_SOURCE_FCLK;
6293 I915_WRITE(LCPLL_CTL, val);
6294
6295 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6296 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6297 DRM_ERROR("Switching to FCLK failed\n");
6298
6299 val = I915_READ(LCPLL_CTL);
6300 }
6301
6302 val |= LCPLL_PLL_DISABLE;
6303 I915_WRITE(LCPLL_CTL, val);
6304 POSTING_READ(LCPLL_CTL);
6305
6306 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6307 DRM_ERROR("LCPLL still locked\n");
6308
6309 val = I915_READ(D_COMP);
6310 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6311 mutex_lock(&dev_priv->rps.hw_lock);
6312 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6313 DRM_ERROR("Failed to disable D_COMP\n");
6314 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6315 POSTING_READ(D_COMP);
6316 ndelay(100);
6317
6318 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6319 DRM_ERROR("D_COMP RCOMP still in progress\n");
6320
6321 if (allow_power_down) {
6322 val = I915_READ(LCPLL_CTL);
6323 val |= LCPLL_POWER_DOWN_ALLOW;
6324 I915_WRITE(LCPLL_CTL, val);
6325 POSTING_READ(LCPLL_CTL);
6326 }
6327}
6328
6329/*
6330 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6331 * source.
6332 */
6ff58d53 6333static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6334{
6335 uint32_t val;
6336
6337 val = I915_READ(LCPLL_CTL);
6338
6339 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6340 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6341 return;
6342
215733fa
PZ		 6343 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6344 * we'll hang the machine! */
6345 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6346
be256dc7
PZ		 6347 if (val & LCPLL_POWER_DOWN_ALLOW) {
6348 val &= ~LCPLL_POWER_DOWN_ALLOW;
6349 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6350 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6351 }
6352
6353 val = I915_READ(D_COMP);
6354 val |= D_COMP_COMP_FORCE;
6355 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6356 mutex_lock(&dev_priv->rps.hw_lock);
6357 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6358 DRM_ERROR("Failed to enable D_COMP\n");
6359 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6360 POSTING_READ(D_COMP);
be256dc7
PZ		 6361
6362 val = I915_READ(LCPLL_CTL);
6363 val &= ~LCPLL_PLL_DISABLE;
6364 I915_WRITE(LCPLL_CTL, val);
6365
6366 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6367 DRM_ERROR("LCPLL not locked yet\n");
6368
6369 if (val & LCPLL_CD_SOURCE_FCLK) {
6370 val = I915_READ(LCPLL_CTL);
6371 val &= ~LCPLL_CD_SOURCE_FCLK;
6372 I915_WRITE(LCPLL_CTL, val);
6373
6374 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6375 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6376 DRM_ERROR("Switching back to LCPLL failed\n");
6377 }
215733fa
PZ		 6378
6379 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6380}
6381
c67a470b
PZ		 6382void hsw_enable_pc8_work(struct work_struct *__work)
6383{
6384 struct drm_i915_private *dev_priv =
6385 container_of(to_delayed_work(__work), struct drm_i915_private,
6386 pc8.enable_work);
6387 struct drm_device *dev = dev_priv->dev;
6388 uint32_t val;
6389
6390 if (dev_priv->pc8.enabled)
6391 return;
6392
6393 DRM_DEBUG_KMS("Enabling package C8+\n");
6394
6395 dev_priv->pc8.enabled = true;
6396
6397 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6398 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6399 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6400 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6401 }
6402
6403 lpt_disable_clkout_dp(dev);
6404 hsw_pc8_disable_interrupts(dev);
6405 hsw_disable_lcpll(dev_priv, true, true);
6406}
6407
6408static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6409{
6410 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6411 WARN(dev_priv->pc8.disable_count < 1,
6412 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6413
6414 dev_priv->pc8.disable_count--;
6415 if (dev_priv->pc8.disable_count != 0)
6416 return;
6417
6418 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6419 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6420}
6421
6422static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6423{
6424 struct drm_device *dev = dev_priv->dev;
6425 uint32_t val;
6426
6427 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6428 WARN(dev_priv->pc8.disable_count < 0,
6429 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6430
6431 dev_priv->pc8.disable_count++;
6432 if (dev_priv->pc8.disable_count != 1)
6433 return;
6434
6435 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6436 if (!dev_priv->pc8.enabled)
6437 return;
6438
6439 DRM_DEBUG_KMS("Disabling package C8+\n");
6440
6441 hsw_restore_lcpll(dev_priv);
6442 hsw_pc8_restore_interrupts(dev);
6443 lpt_init_pch_refclk(dev);
6444
6445 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6446 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6447 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6448 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6449 }
6450
6451 intel_prepare_ddi(dev);
6452 i915_gem_init_swizzling(dev);
6453 mutex_lock(&dev_priv->rps.hw_lock);
6454 gen6_update_ring_freq(dev);
6455 mutex_unlock(&dev_priv->rps.hw_lock);
6456 dev_priv->pc8.enabled = false;
6457}
6458
6459void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6460{
6461 mutex_lock(&dev_priv->pc8.lock);
6462 __hsw_enable_package_c8(dev_priv);
6463 mutex_unlock(&dev_priv->pc8.lock);
6464}
6465
6466void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6467{
6468 mutex_lock(&dev_priv->pc8.lock);
6469 __hsw_disable_package_c8(dev_priv);
6470 mutex_unlock(&dev_priv->pc8.lock);
6471}
6472
6473static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6474{
6475 struct drm_device *dev = dev_priv->dev;
6476 struct intel_crtc *crtc;
6477 uint32_t val;
6478
6479 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6480 if (crtc->base.enabled)
6481 return false;
6482
6483 /* This case is still possible since we have the i915.disable_power_well
6484 * parameter and also the KVMr or something else might be requesting the
6485 * power well. */
6486 val = I915_READ(HSW_PWR_WELL_DRIVER);
6487 if (val != 0) {
6488 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6489 return false;
6490 }
6491
6492 return true;
6493}
6494
6495/* Since we're called from modeset_global_resources there's no way to
6496 * symmetrically increase and decrease the refcount, so we use
6497 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6498 * or not.
6499 */
6500static void hsw_update_package_c8(struct drm_device *dev)
6501{
6502 struct drm_i915_private *dev_priv = dev->dev_private;
6503 bool allow;
6504
6505 if (!i915_enable_pc8)
6506 return;
6507
6508 mutex_lock(&dev_priv->pc8.lock);
6509
6510 allow = hsw_can_enable_package_c8(dev_priv);
6511
6512 if (allow == dev_priv->pc8.requirements_met)
6513 goto done;
6514
6515 dev_priv->pc8.requirements_met = allow;
6516
6517 if (allow)
6518 __hsw_enable_package_c8(dev_priv);
6519 else
6520 __hsw_disable_package_c8(dev_priv);
6521
6522done:
6523 mutex_unlock(&dev_priv->pc8.lock);
6524}
6525
6526static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6527{
6528 if (!dev_priv->pc8.gpu_idle) {
6529 dev_priv->pc8.gpu_idle = true;
6530 hsw_enable_package_c8(dev_priv);
6531 }
6532}
6533
6534static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6535{
6536 if (dev_priv->pc8.gpu_idle) {
6537 dev_priv->pc8.gpu_idle = false;
6538 hsw_disable_package_c8(dev_priv);
6539 }
be256dc7
PZ		 6540}
6541
d6dd9eb1
DV		 6542static void haswell_modeset_global_resources(struct drm_device *dev)
6543{
d6dd9eb1
DV		 6544 bool enable = false;
6545 struct intel_crtc *crtc;
d6dd9eb1
DV		 6546
6547 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6548 if (!crtc->base.enabled)
6549 continue;
d6dd9eb1 6550
fd4daa9c 6551 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6552 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6553 enable = true;
6554 }
6555
d6dd9eb1 6556 intel_set_power_well(dev, enable);
c67a470b
PZ		 6557
6558 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6559}
6560
09b4ddf9 6561static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6562 int x, int y,
6563 struct drm_framebuffer *fb)
6564{
6565 struct drm_device *dev = crtc->dev;
6566 struct drm_i915_private *dev_priv = dev->dev_private;
6567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6568 int plane = intel_crtc->plane;
09b4ddf9 6569 int ret;
09b4ddf9 6570
ff9a6750 6571 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6572 return -EINVAL;
6573
03afc4a2
DV		 6574 if (intel_crtc->config.has_dp_encoder)
6575 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6576
6577 intel_crtc->lowfreq_avail = false;
09b4ddf9 6578
8a654f3b 6579 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6580
ca3a0ff8 6581 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6582 intel_cpu_transcoder_set_m_n(intel_crtc,
6583 &intel_crtc->config.fdi_m_n);
6584 }
09b4ddf9 6585
6ff93609 6586 haswell_set_pipeconf(crtc);
09b4ddf9 6587
50f3b016 6588 intel_set_pipe_csc(crtc);
86d3efce 6589
09b4ddf9 6590 /* Set up the display plane register */
86d3efce 6591 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6592 POSTING_READ(DSPCNTR(plane));
6593
6594 ret = intel_pipe_set_base(crtc, x, y, fb);
6595
1f803ee5 6596 return ret;
79e53945
JB		 6597}
6598
0e8ffe1b
DV		 6599static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6600 struct intel_crtc_config *pipe_config)
6601{
6602 struct drm_device *dev = crtc->base.dev;
6603 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6604 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6605 uint32_t tmp;
6606
e143a21c 6607 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6608 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6609
eccb140b
DV		 6610 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6611 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6612 enum pipe trans_edp_pipe;
6613 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6614 default:
6615 WARN(1, "unknown pipe linked to edp transcoder\n");
6616 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6617 case TRANS_DDI_EDP_INPUT_A_ON:
6618 trans_edp_pipe = PIPE_A;
6619 break;
6620 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6621 trans_edp_pipe = PIPE_B;
6622 break;
6623 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6624 trans_edp_pipe = PIPE_C;
6625 break;
6626 }
6627
6628 if (trans_edp_pipe == crtc->pipe)
6629 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6630 }
6631
b97186f0 6632 if (!intel_display_power_enabled(dev,
eccb140b 6633 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6634 return false;
6635
eccb140b 6636 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6637 if (!(tmp & PIPECONF_ENABLE))
6638 return false;
6639
88adfff1 6640 /*
f196e6be 6641 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6642 * DDI E. So just check whether this pipe is wired to DDI E and whether
6643 * the PCH transcoder is on.
6644 */
eccb140b 6645 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6646 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6647 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6648 pipe_config->has_pch_encoder = true;
6649
627eb5a3
DV		 6650 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6651 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6652 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6653
6654 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6655 }
6656
1bd1bd80
DV		 6657 intel_get_pipe_timings(crtc, pipe_config);
6658
2fa2fe9a
DV		 6659 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6660 if (intel_display_power_enabled(dev, pfit_domain))
6661 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6662
42db64ef
PZ		 6663 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6664 (I915_READ(IPS_CTL) & IPS_ENABLE);
6665
6c49f241
DV		 6666 pipe_config->pixel_multiplier = 1;
6667
0e8ffe1b
DV		 6668 return true;
6669}
6670
f564048e 6671static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6672 int x, int y,
94352cf9 6673 struct drm_framebuffer *fb)
f564048e
EA		 6674{
6675 struct drm_device *dev = crtc->dev;
6676 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6677 struct intel_encoder *encoder;
0b701d27 6678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6679 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6680 int pipe = intel_crtc->pipe;
f564048e
EA		 6681 int ret;
6682
0b701d27 6683 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6684
b8cecdf5
DV		 6685 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6686
79e53945 6687 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6688
9256aa19
DV		 6689 if (ret != 0)
6690 return ret;
6691
6692 for_each_encoder_on_crtc(dev, crtc, encoder) {
6693 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6694 encoder->base.base.id,
6695 drm_get_encoder_name(&encoder->base),
6696 mode->base.id, mode->name);
36f2d1f1 6697 encoder->mode_set(encoder);
9256aa19
DV		 6698 }
6699
6700 return 0;
79e53945
JB		 6701}
6702
3a9627f4
WF		 6703static bool intel_eld_uptodate(struct drm_connector *connector,
6704 int reg_eldv, uint32_t bits_eldv,
6705 int reg_elda, uint32_t bits_elda,
6706 int reg_edid)
6707{
6708 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6709 uint8_t *eld = connector->eld;
6710 uint32_t i;
6711
6712 i = I915_READ(reg_eldv);
6713 i &= bits_eldv;
6714
6715 if (!eld[0])
6716 return !i;
6717
6718 if (!i)
6719 return false;
6720
6721 i = I915_READ(reg_elda);
6722 i &= ~bits_elda;
6723 I915_WRITE(reg_elda, i);
6724
6725 for (i = 0; i < eld[2]; i++)
6726 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6727 return false;
6728
6729 return true;
6730}
6731
e0dac65e
WF		 6732static void g4x_write_eld(struct drm_connector *connector,
6733 struct drm_crtc *crtc)
6734{
6735 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6736 uint8_t *eld = connector->eld;
6737 uint32_t eldv;
6738 uint32_t len;
6739 uint32_t i;
6740
6741 i = I915_READ(G4X_AUD_VID_DID);
6742
6743 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6744 eldv = G4X_ELDV_DEVCL_DEVBLC;
6745 else
6746 eldv = G4X_ELDV_DEVCTG;
6747
3a9627f4
WF		 6748 if (intel_eld_uptodate(connector,
6749 G4X_AUD_CNTL_ST, eldv,
6750 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6751 G4X_HDMIW_HDMIEDID))
6752 return;
6753
e0dac65e
WF		 6754 i = I915_READ(G4X_AUD_CNTL_ST);
6755 i &= ~(eldv | G4X_ELD_ADDR);
6756 len = (i >> 9) & 0x1f; /* ELD buffer size */
6757 I915_WRITE(G4X_AUD_CNTL_ST, i);
6758
6759 if (!eld[0])
6760 return;
6761
6762 len = min_t(uint8_t, eld[2], len);
6763 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6764 for (i = 0; i < len; i++)
6765 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6766
6767 i = I915_READ(G4X_AUD_CNTL_ST);
6768 i |= eldv;
6769 I915_WRITE(G4X_AUD_CNTL_ST, i);
6770}
6771
83358c85
WX		 6772static void haswell_write_eld(struct drm_connector *connector,
6773 struct drm_crtc *crtc)
6774{
6775 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6776 uint8_t *eld = connector->eld;
6777 struct drm_device *dev = crtc->dev;
7b9f35a6 6778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6779 uint32_t eldv;
6780 uint32_t i;
6781 int len;
6782 int pipe = to_intel_crtc(crtc)->pipe;
6783 int tmp;
6784
6785 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6786 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6787 int aud_config = HSW_AUD_CFG(pipe);
6788 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6789
6790
6791 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6792
6793 /* Audio output enable */
6794 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6795 tmp = I915_READ(aud_cntrl_st2);
6796 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6797 I915_WRITE(aud_cntrl_st2, tmp);
6798
6799 /* Wait for 1 vertical blank */
6800 intel_wait_for_vblank(dev, pipe);
6801
6802 /* Set ELD valid state */
6803 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6804 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6805 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6806 I915_WRITE(aud_cntrl_st2, tmp);
6807 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6808 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6809
6810 /* Enable HDMI mode */
6811 tmp = I915_READ(aud_config);
7e7cb34f 6812 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6813 /* clear N_programing_enable and N_value_index */
6814 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6815 I915_WRITE(aud_config, tmp);
6816
6817 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6818
6819 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6820 intel_crtc->eld_vld = true;
83358c85
WX		 6821
6822 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6823 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6824 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6825 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6826 } else
6827 I915_WRITE(aud_config, 0);
6828
6829 if (intel_eld_uptodate(connector,
6830 aud_cntrl_st2, eldv,
6831 aud_cntl_st, IBX_ELD_ADDRESS,
6832 hdmiw_hdmiedid))
6833 return;
6834
6835 i = I915_READ(aud_cntrl_st2);
6836 i &= ~eldv;
6837 I915_WRITE(aud_cntrl_st2, i);
6838
6839 if (!eld[0])
6840 return;
6841
6842 i = I915_READ(aud_cntl_st);
6843 i &= ~IBX_ELD_ADDRESS;
6844 I915_WRITE(aud_cntl_st, i);
6845 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6846 DRM_DEBUG_DRIVER("port num:%d\n", i);
6847
6848 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6849 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6850 for (i = 0; i < len; i++)
6851 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6852
6853 i = I915_READ(aud_cntrl_st2);
6854 i |= eldv;
6855 I915_WRITE(aud_cntrl_st2, i);
6856
6857}
6858
e0dac65e
WF		 6859static void ironlake_write_eld(struct drm_connector *connector,
6860 struct drm_crtc *crtc)
6861{
6862 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6863 uint8_t *eld = connector->eld;
6864 uint32_t eldv;
6865 uint32_t i;
6866 int len;
6867 int hdmiw_hdmiedid;
b6daa025 6868 int aud_config;
e0dac65e
WF		 6869 int aud_cntl_st;
6870 int aud_cntrl_st2;
9b138a83 6871 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6872
b3f33cbf 6873 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6874 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6875 aud_config = IBX_AUD_CFG(pipe);
6876 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6877 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6878 } else {
9b138a83
WX		 6879 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6880 aud_config = CPT_AUD_CFG(pipe);
6881 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6882 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6883 }
6884
9b138a83 6885 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6886
6887 i = I915_READ(aud_cntl_st);
9b138a83 6888 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6889 if (!i) {
6890 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6891 /* operate blindly on all ports */
1202b4c6
WF		 6892 eldv = IBX_ELD_VALIDB;
6893 eldv |= IBX_ELD_VALIDB << 4;
6894 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6895 } else {
2582a850 6896 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6897 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6898 }
6899
3a9627f4
WF		 6900 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6901 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6902 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6903 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6904 } else
6905 I915_WRITE(aud_config, 0);
e0dac65e 6906
3a9627f4
WF		 6907 if (intel_eld_uptodate(connector,
6908 aud_cntrl_st2, eldv,
6909 aud_cntl_st, IBX_ELD_ADDRESS,
6910 hdmiw_hdmiedid))
6911 return;
6912
e0dac65e
WF		 6913 i = I915_READ(aud_cntrl_st2);
6914 i &= ~eldv;
6915 I915_WRITE(aud_cntrl_st2, i);
6916
6917 if (!eld[0])
6918 return;
6919
e0dac65e 6920 i = I915_READ(aud_cntl_st);
1202b4c6 6921 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6922 I915_WRITE(aud_cntl_st, i);
6923
6924 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6925 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6926 for (i = 0; i < len; i++)
6927 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6928
6929 i = I915_READ(aud_cntrl_st2);
6930 i |= eldv;
6931 I915_WRITE(aud_cntrl_st2, i);
6932}
6933
6934void intel_write_eld(struct drm_encoder *encoder,
6935 struct drm_display_mode *mode)
6936{
6937 struct drm_crtc *crtc = encoder->crtc;
6938 struct drm_connector *connector;
6939 struct drm_device *dev = encoder->dev;
6940 struct drm_i915_private *dev_priv = dev->dev_private;
6941
6942 connector = drm_select_eld(encoder, mode);
6943 if (!connector)
6944 return;
6945
6946 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6947 connector->base.id,
6948 drm_get_connector_name(connector),
6949 connector->encoder->base.id,
6950 drm_get_encoder_name(connector->encoder));
6951
6952 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6953
6954 if (dev_priv->display.write_eld)
6955 dev_priv->display.write_eld(connector, crtc);
6956}
6957
560b85bb
CW		 6958static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6959{
6960 struct drm_device *dev = crtc->dev;
6961 struct drm_i915_private *dev_priv = dev->dev_private;
6962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6963 bool visible = base != 0;
6964 u32 cntl;
6965
6966 if (intel_crtc->cursor_visible == visible)
6967 return;
6968
9db4a9c7 6969 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6970 if (visible) {
6971 /* On these chipsets we can only modify the base whilst
6972 * the cursor is disabled.
6973 */
9db4a9c7 6974 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6975
6976 cntl &= ~(CURSOR_FORMAT_MASK);
6977 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6978 cntl |= CURSOR_ENABLE |
6979 CURSOR_GAMMA_ENABLE |
6980 CURSOR_FORMAT_ARGB;
6981 } else
6982 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6983 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6984
6985 intel_crtc->cursor_visible = visible;
6986}
6987
6988static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6989{
6990 struct drm_device *dev = crtc->dev;
6991 struct drm_i915_private *dev_priv = dev->dev_private;
6992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6993 int pipe = intel_crtc->pipe;
6994 bool visible = base != 0;
6995
6996 if (intel_crtc->cursor_visible != visible) {
548f245b 6997 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6998 if (base) {
6999 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7000 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7001 cntl |= pipe << 28; /* Connect to correct pipe */
7002 } else {
7003 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7004 cntl |= CURSOR_MODE_DISABLE;
7005 }
9db4a9c7 7006 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7007
7008 intel_crtc->cursor_visible = visible;
7009 }
7010 /* and commit changes on next vblank */
9db4a9c7 7011 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7012}
7013
65a21cd6
JB		 7014static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7015{
7016 struct drm_device *dev = crtc->dev;
7017 struct drm_i915_private *dev_priv = dev->dev_private;
7018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019 int pipe = intel_crtc->pipe;
7020 bool visible = base != 0;
7021
7022 if (intel_crtc->cursor_visible != visible) {
7023 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7024 if (base) {
7025 cntl &= ~CURSOR_MODE;
7026 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7027 } else {
7028 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7029 cntl |= CURSOR_MODE_DISABLE;
7030 }
1f5d76db 7031 if (IS_HASWELL(dev)) {
86d3efce 7032 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7033 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7034 }
65a21cd6
JB		 7035 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7036
7037 intel_crtc->cursor_visible = visible;
7038 }
7039 /* and commit changes on next vblank */
7040 I915_WRITE(CURBASE_IVB(pipe), base);
7041}
7042
cda4b7d3 7043/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7044static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7045 bool on)
cda4b7d3
CW		 7046{
7047 struct drm_device *dev = crtc->dev;
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050 int pipe = intel_crtc->pipe;
7051 int x = intel_crtc->cursor_x;
7052 int y = intel_crtc->cursor_y;
d6e4db15 7053 u32 base = 0, pos = 0;
cda4b7d3
CW		 7054 bool visible;
7055
d6e4db15 7056 if (on)
cda4b7d3 7057 base = intel_crtc->cursor_addr;
cda4b7d3 7058
d6e4db15
VS		 7059 if (x >= intel_crtc->config.pipe_src_w)
7060 base = 0;
7061
7062 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7063 base = 0;
7064
7065 if (x < 0) {
efc9064e 7066 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7067 base = 0;
7068
7069 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7070 x = -x;
7071 }
7072 pos |= x << CURSOR_X_SHIFT;
7073
7074 if (y < 0) {
efc9064e 7075 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7076 base = 0;
7077
7078 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7079 y = -y;
7080 }
7081 pos |= y << CURSOR_Y_SHIFT;
7082
7083 visible = base != 0;
560b85bb 7084 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7085 return;
7086
0cd83aa9 7087 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7088 I915_WRITE(CURPOS_IVB(pipe), pos);
7089 ivb_update_cursor(crtc, base);
7090 } else {
7091 I915_WRITE(CURPOS(pipe), pos);
7092 if (IS_845G(dev) || IS_I865G(dev))
7093 i845_update_cursor(crtc, base);
7094 else
7095 i9xx_update_cursor(crtc, base);
7096 }
cda4b7d3
CW		 7097}
7098
79e53945 7099static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7100 struct drm_file *file,
79e53945
JB		 7101 uint32_t handle,
7102 uint32_t width, uint32_t height)
7103{
7104 struct drm_device *dev = crtc->dev;
7105 struct drm_i915_private *dev_priv = dev->dev_private;
7106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7107 struct drm_i915_gem_object *obj;
cda4b7d3 7108 uint32_t addr;
3f8bc370 7109 int ret;
79e53945 7110
79e53945
JB		 7111 /* if we want to turn off the cursor ignore width and height */
7112 if (!handle) {
28c97730 7113 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7114 addr = 0;
05394f39 7115 obj = NULL;
5004417d 7116 mutex_lock(&dev->struct_mutex);
3f8bc370 7117 goto finish;
79e53945
JB		 7118 }
7119
7120 /* Currently we only support 64x64 cursors */
7121 if (width != 64 || height != 64) {
7122 DRM_ERROR("we currently only support 64x64 cursors\n");
7123 return -EINVAL;
7124 }
7125
05394f39 7126 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7127 if (&obj->base == NULL)
79e53945
JB		 7128 return -ENOENT;
7129
05394f39 7130 if (obj->base.size < width * height * 4) {
79e53945 7131 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7132 ret = -ENOMEM;
7133 goto fail;
79e53945
JB		 7134 }
7135
71acb5eb 7136 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7137 mutex_lock(&dev->struct_mutex);
b295d1b6 7138 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7139 unsigned alignment;
7140
d9e86c0e
CW		 7141 if (obj->tiling_mode) {
7142 DRM_ERROR("cursor cannot be tiled\n");
7143 ret = -EINVAL;
7144 goto fail_locked;
7145 }
7146
693db184
CW		 7147 /* Note that the w/a also requires 2 PTE of padding following
7148 * the bo. We currently fill all unused PTE with the shadow
7149 * page and so we should always have valid PTE following the
7150 * cursor preventing the VT-d warning.
7151 */
7152 alignment = 0;
7153 if (need_vtd_wa(dev))
7154 alignment = 64*1024;
7155
7156 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7157 if (ret) {
7158 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7159 goto fail_locked;
e7b526bb
CW		 7160 }
7161
d9e86c0e
CW		 7162 ret = i915_gem_object_put_fence(obj);
7163 if (ret) {
2da3b9b9 7164 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7165 goto fail_unpin;
7166 }
7167
f343c5f6 7168 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7169 } else {
6eeefaf3 7170 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7171 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7172 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7173 align);
71acb5eb
DA		 7174 if (ret) {
7175 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7176 goto fail_locked;
71acb5eb 7177 }
05394f39 7178 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7179 }
7180
a6c45cf0 7181 if (IS_GEN2(dev))
14b60391
JB		 7182 I915_WRITE(CURSIZE, (height << 12) | width);
7183
3f8bc370 7184 finish:
3f8bc370 7185 if (intel_crtc->cursor_bo) {
b295d1b6 7186 if (dev_priv->info->cursor_needs_physical) {
05394f39 7187 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7188 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7189 } else
cc98b413 7190 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7191 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7192 }
80824003 7193
7f9872e0 7194 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7195
7196 intel_crtc->cursor_addr = addr;
05394f39 7197 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7198 intel_crtc->cursor_width = width;
7199 intel_crtc->cursor_height = height;
7200
f2f5f771
VS		 7201 if (intel_crtc->active)
7202 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7203
79e53945 7204 return 0;
e7b526bb 7205fail_unpin:
cc98b413 7206 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7207fail_locked:
34b8686e 7208 mutex_unlock(&dev->struct_mutex);
bc9025bd 7209fail:
05394f39 7210 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7211 return ret;
79e53945
JB		 7212}
7213
7214static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7215{
79e53945 7216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7217
cda4b7d3
CW		 7218 intel_crtc->cursor_x = x;
7219 intel_crtc->cursor_y = y;
652c393a 7220
f2f5f771
VS		 7221 if (intel_crtc->active)
7222 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7223
7224 return 0;
b8c00ac5
DA		 7225}
7226
79e53945 7227static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7228 u16 *blue, uint32_t start, uint32_t size)
79e53945 7229{
7203425a 7230 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7232
7203425a 7233 for (i = start; i < end; i++) {
79e53945
JB		 7234 intel_crtc->lut_r[i] = red[i] >> 8;
7235 intel_crtc->lut_g[i] = green[i] >> 8;
7236 intel_crtc->lut_b[i] = blue[i] >> 8;
7237 }
7238
7239 intel_crtc_load_lut(crtc);
7240}
7241
79e53945
JB		 7242/* VESA 640x480x72Hz mode to set on the pipe */
7243static struct drm_display_mode load_detect_mode = {
7244 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7245 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7246};
7247
d2dff872
CW		 7248static struct drm_framebuffer *
7249intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7250 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7251 struct drm_i915_gem_object *obj)
7252{
7253 struct intel_framebuffer *intel_fb;
7254 int ret;
7255
7256 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7257 if (!intel_fb) {
7258 drm_gem_object_unreference_unlocked(&obj->base);
7259 return ERR_PTR(-ENOMEM);
7260 }
7261
7262 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7263 if (ret) {
7264 drm_gem_object_unreference_unlocked(&obj->base);
7265 kfree(intel_fb);
7266 return ERR_PTR(ret);
7267 }
7268
7269 return &intel_fb->base;
7270}
7271
7272static u32
7273intel_framebuffer_pitch_for_width(int width, int bpp)
7274{
7275 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7276 return ALIGN(pitch, 64);
7277}
7278
7279static u32
7280intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7281{
7282 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7283 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7284}
7285
7286static struct drm_framebuffer *
7287intel_framebuffer_create_for_mode(struct drm_device *dev,
7288 struct drm_display_mode *mode,
7289 int depth, int bpp)
7290{
7291 struct drm_i915_gem_object *obj;
0fed39bd 7292 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7293
7294 obj = i915_gem_alloc_object(dev,
7295 intel_framebuffer_size_for_mode(mode, bpp));
7296 if (obj == NULL)
7297 return ERR_PTR(-ENOMEM);
7298
7299 mode_cmd.width = mode->hdisplay;
7300 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7301 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7302 bpp);
5ca0c34a 7303 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7304
7305 return intel_framebuffer_create(dev, &mode_cmd, obj);
7306}
7307
7308static struct drm_framebuffer *
7309mode_fits_in_fbdev(struct drm_device *dev,
7310 struct drm_display_mode *mode)
7311{
7312 struct drm_i915_private *dev_priv = dev->dev_private;
7313 struct drm_i915_gem_object *obj;
7314 struct drm_framebuffer *fb;
7315
7316 if (dev_priv->fbdev == NULL)
7317 return NULL;
7318
7319 obj = dev_priv->fbdev->ifb.obj;
7320 if (obj == NULL)
7321 return NULL;
7322
7323 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7324 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7325 fb->bits_per_pixel))
d2dff872
CW		 7326 return NULL;
7327
01f2c773 7328 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7329 return NULL;
7330
7331 return fb;
7332}
7333
d2434ab7 7334bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7335 struct drm_display_mode *mode,
8261b191 7336 struct intel_load_detect_pipe *old)
79e53945
JB		 7337{
7338 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7339 struct intel_encoder *intel_encoder =
7340 intel_attached_encoder(connector);
79e53945 7341 struct drm_crtc *possible_crtc;
4ef69c7a 7342 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7343 struct drm_crtc *crtc = NULL;
7344 struct drm_device *dev = encoder->dev;
94352cf9 7345 struct drm_framebuffer *fb;
79e53945
JB		 7346 int i = -1;
7347
d2dff872
CW		 7348 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7349 connector->base.id, drm_get_connector_name(connector),
7350 encoder->base.id, drm_get_encoder_name(encoder));
7351
79e53945
JB		 7352 /*
7353 * Algorithm gets a little messy:
7a5e4805 7354 *
79e53945
JB		 7355 * - if the connector already has an assigned crtc, use it (but make
7356 * sure it's on first)
7a5e4805 7357 *
79e53945
JB		 7358 * - try to find the first unused crtc that can drive this connector,
7359 * and use that if we find one
79e53945
JB		 7360 */
7361
7362 /* See if we already have a CRTC for this connector */
7363 if (encoder->crtc) {
7364 crtc = encoder->crtc;
8261b191 7365
7b24056b
DV		 7366 mutex_lock(&crtc->mutex);
7367
24218aac 7368 old->dpms_mode = connector->dpms;
8261b191
CW		 7369 old->load_detect_temp = false;
7370
7371 /* Make sure the crtc and connector are running */
24218aac
DV		 7372 if (connector->dpms != DRM_MODE_DPMS_ON)
7373 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7374
7173188d 7375 return true;
79e53945
JB		 7376 }
7377
7378 /* Find an unused one (if possible) */
7379 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7380 i++;
7381 if (!(encoder->possible_crtcs & (1 << i)))
7382 continue;
7383 if (!possible_crtc->enabled) {
7384 crtc = possible_crtc;
7385 break;
7386 }
79e53945
JB		 7387 }
7388
7389 /*
7390 * If we didn't find an unused CRTC, don't use any.
7391 */
7392 if (!crtc) {
7173188d
CW		 7393 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7394 return false;
79e53945
JB		 7395 }
7396
7b24056b 7397 mutex_lock(&crtc->mutex);
fc303101
DV		 7398 intel_encoder->new_crtc = to_intel_crtc(crtc);
7399 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7400
7401 intel_crtc = to_intel_crtc(crtc);
24218aac 7402 old->dpms_mode = connector->dpms;
8261b191 7403 old->load_detect_temp = true;
d2dff872 7404 old->release_fb = NULL;
79e53945 7405
6492711d
CW		 7406 if (!mode)
7407 mode = &load_detect_mode;
79e53945 7408
d2dff872
CW		 7409 /* We need a framebuffer large enough to accommodate all accesses
7410 * that the plane may generate whilst we perform load detection.
7411 * We can not rely on the fbcon either being present (we get called
7412 * during its initialisation to detect all boot displays, or it may
7413 * not even exist) or that it is large enough to satisfy the
7414 * requested mode.
7415 */
94352cf9
DV		 7416 fb = mode_fits_in_fbdev(dev, mode);
7417 if (fb == NULL) {
d2dff872 7418 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7419 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7420 old->release_fb = fb;
d2dff872
CW		 7421 } else
7422 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7423 if (IS_ERR(fb)) {
d2dff872 7424 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7425 mutex_unlock(&crtc->mutex);
0e8b3d3e 7426 return false;
79e53945 7427 }
79e53945 7428
c0c36b94 7429 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7430 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7431 if (old->release_fb)
7432 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7433 mutex_unlock(&crtc->mutex);
0e8b3d3e 7434 return false;
79e53945 7435 }
7173188d 7436
79e53945 7437 /* let the connector get through one full cycle before testing */
9d0498a2 7438 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7439 return true;
79e53945
JB		 7440}
7441
d2434ab7 7442void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7443 struct intel_load_detect_pipe *old)
79e53945 7444{
d2434ab7
DV		 7445 struct intel_encoder *intel_encoder =
7446 intel_attached_encoder(connector);
4ef69c7a 7447 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7448 struct drm_crtc *crtc = encoder->crtc;
79e53945 7449
d2dff872
CW		 7450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7451 connector->base.id, drm_get_connector_name(connector),
7452 encoder->base.id, drm_get_encoder_name(encoder));
7453
8261b191 7454 if (old->load_detect_temp) {
fc303101
DV		 7455 to_intel_connector(connector)->new_encoder = NULL;
7456 intel_encoder->new_crtc = NULL;
7457 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7458
36206361
DV		 7459 if (old->release_fb) {
7460 drm_framebuffer_unregister_private(old->release_fb);
7461 drm_framebuffer_unreference(old->release_fb);
7462 }
d2dff872 7463
67c96400 7464 mutex_unlock(&crtc->mutex);
0622a53c 7465 return;
79e53945
JB		 7466 }
7467
c751ce4f 7468 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7469 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7470 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7471
7472 mutex_unlock(&crtc->mutex);
79e53945
JB		 7473}
7474
da4a1efa
VS		 7475static int i9xx_pll_refclk(struct drm_device *dev,
7476 const struct intel_crtc_config *pipe_config)
7477{
7478 struct drm_i915_private *dev_priv = dev->dev_private;
7479 u32 dpll = pipe_config->dpll_hw_state.dpll;
7480
7481 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7482 return dev_priv->vbt.lvds_ssc_freq * 1000;
7483 else if (HAS_PCH_SPLIT(dev))
7484 return 120000;
7485 else if (!IS_GEN2(dev))
7486 return 96000;
7487 else
7488 return 48000;
7489}
7490
79e53945 7491/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7492static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7493 struct intel_crtc_config *pipe_config)
79e53945 7494{
f1f644dc 7495 struct drm_device *dev = crtc->base.dev;
79e53945 7496 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7497 int pipe = pipe_config->cpu_transcoder;
293623f7 7498 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7499 u32 fp;
7500 intel_clock_t clock;
da4a1efa 7501 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7502
7503 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7504 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7505 else
293623f7 7506 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7507
7508 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7509 if (IS_PINEVIEW(dev)) {
7510 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7511 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7512 } else {
7513 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7514 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7515 }
7516
a6c45cf0 7517 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7518 if (IS_PINEVIEW(dev))
7519 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7520 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7521 else
7522 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7523 DPLL_FPA01_P1_POST_DIV_SHIFT);
7524
7525 switch (dpll & DPLL_MODE_MASK) {
7526 case DPLLB_MODE_DAC_SERIAL:
7527 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7528 5 : 10;
7529 break;
7530 case DPLLB_MODE_LVDS:
7531 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7532 7 : 14;
7533 break;
7534 default:
28c97730 7535 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7536 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7537 return;
79e53945
JB		 7538 }
7539
ac58c3f0 7540 if (IS_PINEVIEW(dev))
da4a1efa 7541 pineview_clock(refclk, &clock);
ac58c3f0 7542 else
da4a1efa 7543 i9xx_clock(refclk, &clock);
79e53945
JB		 7544 } else {
7545 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7546
7547 if (is_lvds) {
7548 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7549 DPLL_FPA01_P1_POST_DIV_SHIFT);
7550 clock.p2 = 14;
79e53945
JB		 7551 } else {
7552 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7553 clock.p1 = 2;
7554 else {
7555 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7556 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7557 }
7558 if (dpll & PLL_P2_DIVIDE_BY_4)
7559 clock.p2 = 4;
7560 else
7561 clock.p2 = 2;
79e53945 7562 }
da4a1efa
VS		 7563
7564 i9xx_clock(refclk, &clock);
79e53945
JB		 7565 }
7566
18442d08
VS		 7567 /*
7568 * This value includes pixel_multiplier. We will use
241bfc38 7569 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7570 * encoder's get_config() function.
7571 */
7572 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7573}
7574
6878da05
VS		 7575int intel_dotclock_calculate(int link_freq,
7576 const struct intel_link_m_n *m_n)
f1f644dc 7577{
f1f644dc
JB		 7578 /*
7579 * The calculation for the data clock is:
1041a02f 7580 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7581 * But we want to avoid losing precison if possible, so:
1041a02f 7582 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7583 *
7584 * and the link clock is simpler:
1041a02f 7585 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7586 */
7587
6878da05
VS		 7588 if (!m_n->link_n)
7589 return 0;
f1f644dc 7590
6878da05
VS		 7591 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7592}
f1f644dc 7593
18442d08
VS		 7594static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7595 struct intel_crtc_config *pipe_config)
6878da05
VS		 7596{
7597 struct drm_device *dev = crtc->base.dev;
79e53945 7598
18442d08
VS		 7599 /* read out port_clock from the DPLL */
7600 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7601
f1f644dc 7602 /*
18442d08 7603 * This value does not include pixel_multiplier.
241bfc38 7604 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7605 * agree once we know their relationship in the encoder's
7606 * get_config() function.
79e53945 7607 */
241bfc38 7608 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7609 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7610 &pipe_config->fdi_m_n);
79e53945
JB		 7611}
7612
7613/** Returns the currently programmed mode of the given pipe. */
7614struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7615 struct drm_crtc *crtc)
7616{
548f245b 7617 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7619 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7620 struct drm_display_mode *mode;
f1f644dc 7621 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7622 int htot = I915_READ(HTOTAL(cpu_transcoder));
7623 int hsync = I915_READ(HSYNC(cpu_transcoder));
7624 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7625 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7626 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7627
7628 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7629 if (!mode)
7630 return NULL;
7631
f1f644dc
JB		 7632 /*
7633 * Construct a pipe_config sufficient for getting the clock info
7634 * back out of crtc_clock_get.
7635 *
7636 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7637 * to use a real value here instead.
7638 */
293623f7 7639 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7640 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7641 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7642 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7643 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7644 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7645
773ae034 7646 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7647 mode->hdisplay = (htot & 0xffff) + 1;
7648 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7649 mode->hsync_start = (hsync & 0xffff) + 1;
7650 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7651 mode->vdisplay = (vtot & 0xffff) + 1;
7652 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7653 mode->vsync_start = (vsync & 0xffff) + 1;
7654 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7655
7656 drm_mode_set_name(mode);
79e53945
JB		 7657
7658 return mode;
7659}
7660
3dec0095 7661static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7662{
7663 struct drm_device *dev = crtc->dev;
7664 drm_i915_private_t *dev_priv = dev->dev_private;
7665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7666 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7667 int dpll_reg = DPLL(pipe);
7668 int dpll;
652c393a 7669
bad720ff 7670 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7671 return;
7672
7673 if (!dev_priv->lvds_downclock_avail)
7674 return;
7675
dbdc6479 7676 dpll = I915_READ(dpll_reg);
652c393a 7677 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7678 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7679
8ac5a6d5 7680 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7681
7682 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7683 I915_WRITE(dpll_reg, dpll);
9d0498a2 7684 intel_wait_for_vblank(dev, pipe);
dbdc6479 7685
652c393a
JB		 7686 dpll = I915_READ(dpll_reg);
7687 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7688 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7689 }
652c393a
JB		 7690}
7691
7692static void intel_decrease_pllclock(struct drm_crtc *crtc)
7693{
7694 struct drm_device *dev = crtc->dev;
7695 drm_i915_private_t *dev_priv = dev->dev_private;
7696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7697
bad720ff 7698 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7699 return;
7700
7701 if (!dev_priv->lvds_downclock_avail)
7702 return;
7703
7704 /*
7705 * Since this is called by a timer, we should never get here in
7706 * the manual case.
7707 */
7708 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7709 int pipe = intel_crtc->pipe;
7710 int dpll_reg = DPLL(pipe);
7711 int dpll;
f6e5b160 7712
44d98a61 7713 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7714
8ac5a6d5 7715 assert_panel_unlocked(dev_priv, pipe);
652c393a 7716
dc257cf1 7717 dpll = I915_READ(dpll_reg);
652c393a
JB		 7718 dpll |= DISPLAY_RATE_SELECT_FPA1;
7719 I915_WRITE(dpll_reg, dpll);
9d0498a2 7720 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7721 dpll = I915_READ(dpll_reg);
7722 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7723 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7724 }
7725
7726}
7727
f047e395
CW		 7728void intel_mark_busy(struct drm_device *dev)
7729{
c67a470b
PZ		 7730 struct drm_i915_private *dev_priv = dev->dev_private;
7731
7732 hsw_package_c8_gpu_busy(dev_priv);
7733 i915_update_gfx_val(dev_priv);
f047e395
CW		 7734}
7735
7736void intel_mark_idle(struct drm_device *dev)
652c393a 7737{
c67a470b 7738 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7739 struct drm_crtc *crtc;
652c393a 7740
c67a470b
PZ		 7741 hsw_package_c8_gpu_idle(dev_priv);
7742
652c393a
JB		 7743 if (!i915_powersave)
7744 return;
7745
652c393a 7746 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7747 if (!crtc->fb)
7748 continue;
7749
725a5b54 7750 intel_decrease_pllclock(crtc);
652c393a 7751 }
b29c19b6
CW		 7752
7753 if (dev_priv->info->gen >= 6)
7754 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7755}
7756
c65355bb
CW		 7757void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7758 struct intel_ring_buffer *ring)
652c393a 7759{
f047e395
CW		 7760 struct drm_device *dev = obj->base.dev;
7761 struct drm_crtc *crtc;
652c393a 7762
f047e395 7763 if (!i915_powersave)
acb87dfb
CW		 7764 return;
7765
652c393a
JB		 7766 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7767 if (!crtc->fb)
7768 continue;
7769
c65355bb
CW		 7770 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7771 continue;
7772
7773 intel_increase_pllclock(crtc);
7774 if (ring && intel_fbc_enabled(dev))
7775 ring->fbc_dirty = true;
652c393a
JB		 7776 }
7777}
7778
79e53945
JB		 7779static void intel_crtc_destroy(struct drm_crtc *crtc)
7780{
7781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7782 struct drm_device *dev = crtc->dev;
7783 struct intel_unpin_work *work;
7784 unsigned long flags;
7785
7786 spin_lock_irqsave(&dev->event_lock, flags);
7787 work = intel_crtc->unpin_work;
7788 intel_crtc->unpin_work = NULL;
7789 spin_unlock_irqrestore(&dev->event_lock, flags);
7790
7791 if (work) {
7792 cancel_work_sync(&work->work);
7793 kfree(work);
7794 }
79e53945 7795
40ccc72b
MK		 7796 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7797
79e53945 7798 drm_crtc_cleanup(crtc);
67e77c5a 7799
79e53945
JB		 7800 kfree(intel_crtc);
7801}
7802
6b95a207
KH		 7803static void intel_unpin_work_fn(struct work_struct *__work)
7804{
7805 struct intel_unpin_work *work =
7806 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7807 struct drm_device *dev = work->crtc->dev;
6b95a207 7808
b4a98e57 7809 mutex_lock(&dev->struct_mutex);
1690e1eb 7810 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7811 drm_gem_object_unreference(&work->pending_flip_obj->base);
7812 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7813
b4a98e57
CW		 7814 intel_update_fbc(dev);
7815 mutex_unlock(&dev->struct_mutex);
7816
7817 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7818 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7819
6b95a207
KH		 7820 kfree(work);
7821}
7822
1afe3e9d 7823static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7824 struct drm_crtc *crtc)
6b95a207
KH		 7825{
7826 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7828 struct intel_unpin_work *work;
6b95a207
KH		 7829 unsigned long flags;
7830
7831 /* Ignore early vblank irqs */
7832 if (intel_crtc == NULL)
7833 return;
7834
7835 spin_lock_irqsave(&dev->event_lock, flags);
7836 work = intel_crtc->unpin_work;
e7d841ca
CW		 7837
7838 /* Ensure we don't miss a work->pending update ... */
7839 smp_rmb();
7840
7841 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7842 spin_unlock_irqrestore(&dev->event_lock, flags);
7843 return;
7844 }
7845
e7d841ca
CW		 7846 /* and that the unpin work is consistent wrt ->pending. */
7847 smp_rmb();
7848
6b95a207 7849 intel_crtc->unpin_work = NULL;
6b95a207 7850
45a066eb
RC		 7851 if (work->event)
7852 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7853
0af7e4df
MK		 7854 drm_vblank_put(dev, intel_crtc->pipe);
7855
6b95a207
KH		 7856 spin_unlock_irqrestore(&dev->event_lock, flags);
7857
2c10d571 7858 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7859
7860 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7861
7862 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7863}
7864
1afe3e9d
JB		 7865void intel_finish_page_flip(struct drm_device *dev, int pipe)
7866{
7867 drm_i915_private_t *dev_priv = dev->dev_private;
7868 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7869
49b14a5c 7870 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7871}
7872
7873void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7874{
7875 drm_i915_private_t *dev_priv = dev->dev_private;
7876 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7877
49b14a5c 7878 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7879}
7880
6b95a207
KH		 7881void intel_prepare_page_flip(struct drm_device *dev, int plane)
7882{
7883 drm_i915_private_t *dev_priv = dev->dev_private;
7884 struct intel_crtc *intel_crtc =
7885 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7886 unsigned long flags;
7887
e7d841ca
CW		 7888 /* NB: An MMIO update of the plane base pointer will also
7889 * generate a page-flip completion irq, i.e. every modeset
7890 * is also accompanied by a spurious intel_prepare_page_flip().
7891 */
6b95a207 7892 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7893 if (intel_crtc->unpin_work)
7894 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7895 spin_unlock_irqrestore(&dev->event_lock, flags);
7896}
7897
e7d841ca
CW		 7898inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7899{
7900 /* Ensure that the work item is consistent when activating it ... */
7901 smp_wmb();
7902 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7903 /* and that it is marked active as soon as the irq could fire. */
7904 smp_wmb();
7905}
7906
8c9f3aaf
JB		 7907static int intel_gen2_queue_flip(struct drm_device *dev,
7908 struct drm_crtc *crtc,
7909 struct drm_framebuffer *fb,
ed8d1975
KP		 7910 struct drm_i915_gem_object *obj,
7911 uint32_t flags)
8c9f3aaf
JB		 7912{
7913 struct drm_i915_private *dev_priv = dev->dev_private;
7914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7915 u32 flip_mask;
6d90c952 7916 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7917 int ret;
7918
6d90c952 7919 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7920 if (ret)
83d4092b 7921 goto err;
8c9f3aaf 7922
6d90c952 7923 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7924 if (ret)
83d4092b 7925 goto err_unpin;
8c9f3aaf
JB		 7926
7927 /* Can't queue multiple flips, so wait for the previous
7928 * one to finish before executing the next.
7929 */
7930 if (intel_crtc->plane)
7931 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7932 else
7933 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7934 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7935 intel_ring_emit(ring, MI_NOOP);
7936 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7937 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7938 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7939 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7940 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7941
7942 intel_mark_page_flip_active(intel_crtc);
09246732 7943 __intel_ring_advance(ring);
83d4092b
CW		 7944 return 0;
7945
7946err_unpin:
7947 intel_unpin_fb_obj(obj);
7948err:
8c9f3aaf
JB		 7949 return ret;
7950}
7951
7952static int intel_gen3_queue_flip(struct drm_device *dev,
7953 struct drm_crtc *crtc,
7954 struct drm_framebuffer *fb,
ed8d1975
KP		 7955 struct drm_i915_gem_object *obj,
7956 uint32_t flags)
8c9f3aaf
JB		 7957{
7958 struct drm_i915_private *dev_priv = dev->dev_private;
7959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7960 u32 flip_mask;
6d90c952 7961 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7962 int ret;
7963
6d90c952 7964 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7965 if (ret)
83d4092b 7966 goto err;
8c9f3aaf 7967
6d90c952 7968 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7969 if (ret)
83d4092b 7970 goto err_unpin;
8c9f3aaf
JB		 7971
7972 if (intel_crtc->plane)
7973 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7974 else
7975 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7976 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7977 intel_ring_emit(ring, MI_NOOP);
7978 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7979 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7980 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7981 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7982 intel_ring_emit(ring, MI_NOOP);
7983
e7d841ca 7984 intel_mark_page_flip_active(intel_crtc);
09246732 7985 __intel_ring_advance(ring);
83d4092b
CW		 7986 return 0;
7987
7988err_unpin:
7989 intel_unpin_fb_obj(obj);
7990err:
8c9f3aaf
JB		 7991 return ret;
7992}
7993
7994static int intel_gen4_queue_flip(struct drm_device *dev,
7995 struct drm_crtc *crtc,
7996 struct drm_framebuffer *fb,
ed8d1975
KP		 7997 struct drm_i915_gem_object *obj,
7998 uint32_t flags)
8c9f3aaf
JB		 7999{
8000 struct drm_i915_private *dev_priv = dev->dev_private;
8001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8002 uint32_t pf, pipesrc;
6d90c952 8003 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8004 int ret;
8005
6d90c952 8006 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8007 if (ret)
83d4092b 8008 goto err;
8c9f3aaf 8009
6d90c952 8010 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8011 if (ret)
83d4092b 8012 goto err_unpin;
8c9f3aaf
JB		 8013
8014 /* i965+ uses the linear or tiled offsets from the
8015 * Display Registers (which do not change across a page-flip)
8016 * so we need only reprogram the base address.
8017 */
6d90c952
DV		 8018 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8019 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8020 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8021 intel_ring_emit(ring,
f343c5f6 8022 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8023 obj->tiling_mode);
8c9f3aaf
JB		 8024
8025 /* XXX Enabling the panel-fitter across page-flip is so far
8026 * untested on non-native modes, so ignore it for now.
8027 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8028 */
8029 pf = 0;
8030 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8031 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8032
8033 intel_mark_page_flip_active(intel_crtc);
09246732 8034 __intel_ring_advance(ring);
83d4092b
CW		 8035 return 0;
8036
8037err_unpin:
8038 intel_unpin_fb_obj(obj);
8039err:
8c9f3aaf
JB		 8040 return ret;
8041}
8042
8043static int intel_gen6_queue_flip(struct drm_device *dev,
8044 struct drm_crtc *crtc,
8045 struct drm_framebuffer *fb,
ed8d1975
KP		 8046 struct drm_i915_gem_object *obj,
8047 uint32_t flags)
8c9f3aaf
JB		 8048{
8049 struct drm_i915_private *dev_priv = dev->dev_private;
8050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8051 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8052 uint32_t pf, pipesrc;
8053 int ret;
8054
6d90c952 8055 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8056 if (ret)
83d4092b 8057 goto err;
8c9f3aaf 8058
6d90c952 8059 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8060 if (ret)
83d4092b 8061 goto err_unpin;
8c9f3aaf 8062
6d90c952
DV		 8063 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8064 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8065 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8066 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8067
dc257cf1
DV		 8068 /* Contrary to the suggestions in the documentation,
8069 * "Enable Panel Fitter" does not seem to be required when page
8070 * flipping with a non-native mode, and worse causes a normal
8071 * modeset to fail.
8072 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8073 */
8074 pf = 0;
8c9f3aaf 8075 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8076 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8077
8078 intel_mark_page_flip_active(intel_crtc);
09246732 8079 __intel_ring_advance(ring);
83d4092b
CW		 8080 return 0;
8081
8082err_unpin:
8083 intel_unpin_fb_obj(obj);
8084err:
8c9f3aaf
JB		 8085 return ret;
8086}
8087
7c9017e5
JB		 8088static int intel_gen7_queue_flip(struct drm_device *dev,
8089 struct drm_crtc *crtc,
8090 struct drm_framebuffer *fb,
ed8d1975
KP		 8091 struct drm_i915_gem_object *obj,
8092 uint32_t flags)
7c9017e5
JB		 8093{
8094 struct drm_i915_private *dev_priv = dev->dev_private;
8095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8096 struct intel_ring_buffer *ring;
cb05d8de 8097 uint32_t plane_bit = 0;
ffe74d75
CW		 8098 int len, ret;
8099
8100 ring = obj->ring;
1c5fd085 8101 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8102 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8103
8104 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8105 if (ret)
83d4092b 8106 goto err;
7c9017e5 8107
cb05d8de
DV		 8108 switch(intel_crtc->plane) {
8109 case PLANE_A:
8110 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8111 break;
8112 case PLANE_B:
8113 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8114 break;
8115 case PLANE_C:
8116 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8117 break;
8118 default:
8119 WARN_ONCE(1, "unknown plane in flip command\n");
8120 ret = -ENODEV;
ab3951eb 8121 goto err_unpin;
cb05d8de
DV		 8122 }
8123
ffe74d75
CW		 8124 len = 4;
8125 if (ring->id == RCS)
8126 len += 6;
8127
8128 ret = intel_ring_begin(ring, len);
7c9017e5 8129 if (ret)
83d4092b 8130 goto err_unpin;
7c9017e5 8131
ffe74d75
CW		 8132 /* Unmask the flip-done completion message. Note that the bspec says that
8133 * we should do this for both the BCS and RCS, and that we must not unmask
8134 * more than one flip event at any time (or ensure that one flip message
8135 * can be sent by waiting for flip-done prior to queueing new flips).
8136 * Experimentation says that BCS works despite DERRMR masking all
8137 * flip-done completion events and that unmasking all planes at once
8138 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8139 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8140 */
8141 if (ring->id == RCS) {
8142 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8143 intel_ring_emit(ring, DERRMR);
8144 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8145 DERRMR_PIPEB_PRI_FLIP_DONE |
8146 DERRMR_PIPEC_PRI_FLIP_DONE));
8147 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8148 intel_ring_emit(ring, DERRMR);
8149 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8150 }
8151
cb05d8de 8152 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8153 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8154 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8155 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8156
8157 intel_mark_page_flip_active(intel_crtc);
09246732 8158 __intel_ring_advance(ring);
83d4092b
CW		 8159 return 0;
8160
8161err_unpin:
8162 intel_unpin_fb_obj(obj);
8163err:
7c9017e5
JB		 8164 return ret;
8165}
8166
8c9f3aaf
JB		 8167static int intel_default_queue_flip(struct drm_device *dev,
8168 struct drm_crtc *crtc,
8169 struct drm_framebuffer *fb,
ed8d1975
KP		 8170 struct drm_i915_gem_object *obj,
8171 uint32_t flags)
8c9f3aaf
JB		 8172{
8173 return -ENODEV;
8174}
8175
6b95a207
KH		 8176static int intel_crtc_page_flip(struct drm_crtc *crtc,
8177 struct drm_framebuffer *fb,
ed8d1975
KP		 8178 struct drm_pending_vblank_event *event,
8179 uint32_t page_flip_flags)
6b95a207
KH		 8180{
8181 struct drm_device *dev = crtc->dev;
8182 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8183 struct drm_framebuffer *old_fb = crtc->fb;
8184 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8186 struct intel_unpin_work *work;
8c9f3aaf 8187 unsigned long flags;
52e68630 8188 int ret;
6b95a207 8189
e6a595d2
VS		 8190 /* Can't change pixel format via MI display flips. */
8191 if (fb->pixel_format != crtc->fb->pixel_format)
8192 return -EINVAL;
8193
8194 /*
8195 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8196 * Note that pitch changes could also affect these register.
8197 */
8198 if (INTEL_INFO(dev)->gen > 3 &&
8199 (fb->offsets[0] != crtc->fb->offsets[0] ||
8200 fb->pitches[0] != crtc->fb->pitches[0]))
8201 return -EINVAL;
8202
b14c5679 8203 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8204 if (work == NULL)
8205 return -ENOMEM;
8206
6b95a207 8207 work->event = event;
b4a98e57 8208 work->crtc = crtc;
4a35f83b 8209 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8210 INIT_WORK(&work->work, intel_unpin_work_fn);
8211
7317c75e
JB		 8212 ret = drm_vblank_get(dev, intel_crtc->pipe);
8213 if (ret)
8214 goto free_work;
8215
6b95a207
KH		 8216 /* We borrow the event spin lock for protecting unpin_work */
8217 spin_lock_irqsave(&dev->event_lock, flags);
8218 if (intel_crtc->unpin_work) {
8219 spin_unlock_irqrestore(&dev->event_lock, flags);
8220 kfree(work);
7317c75e 8221 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8222
8223 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8224 return -EBUSY;
8225 }
8226 intel_crtc->unpin_work = work;
8227 spin_unlock_irqrestore(&dev->event_lock, flags);
8228
b4a98e57
CW		 8229 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8230 flush_workqueue(dev_priv->wq);
8231
79158103
CW		 8232 ret = i915_mutex_lock_interruptible(dev);
8233 if (ret)
8234 goto cleanup;
6b95a207 8235
75dfca80 8236 /* Reference the objects for the scheduled work. */
05394f39
CW		 8237 drm_gem_object_reference(&work->old_fb_obj->base);
8238 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8239
8240 crtc->fb = fb;
96b099fd 8241
e1f99ce6 8242 work->pending_flip_obj = obj;
e1f99ce6 8243
4e5359cd
SF		 8244 work->enable_stall_check = true;
8245
b4a98e57 8246 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8247 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8248
ed8d1975 8249 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8250 if (ret)
8251 goto cleanup_pending;
6b95a207 8252
7782de3b 8253 intel_disable_fbc(dev);
c65355bb 8254 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8255 mutex_unlock(&dev->struct_mutex);
8256
e5510fac
JB		 8257 trace_i915_flip_request(intel_crtc->plane, obj);
8258
6b95a207 8259 return 0;
96b099fd 8260
8c9f3aaf 8261cleanup_pending:
b4a98e57 8262 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8263 crtc->fb = old_fb;
05394f39
CW		 8264 drm_gem_object_unreference(&work->old_fb_obj->base);
8265 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8266 mutex_unlock(&dev->struct_mutex);
8267
79158103 8268cleanup:
96b099fd
CW		 8269 spin_lock_irqsave(&dev->event_lock, flags);
8270 intel_crtc->unpin_work = NULL;
8271 spin_unlock_irqrestore(&dev->event_lock, flags);
8272
7317c75e
JB		 8273 drm_vblank_put(dev, intel_crtc->pipe);
8274free_work:
96b099fd
CW		 8275 kfree(work);
8276
8277 return ret;
6b95a207
KH		 8278}
8279
f6e5b160 8280static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8281 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8282 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8283};
8284
50f56119
DV		 8285static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8286 struct drm_crtc *crtc)
8287{
8288 struct drm_device *dev;
8289 struct drm_crtc *tmp;
8290 int crtc_mask = 1;
47f1c6c9 8291
50f56119 8292 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8293
50f56119 8294 dev = crtc->dev;
47f1c6c9 8295
50f56119
DV		 8296 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8297 if (tmp == crtc)
8298 break;
8299 crtc_mask <<= 1;
8300 }
47f1c6c9 8301
50f56119
DV		 8302 if (encoder->possible_crtcs & crtc_mask)
8303 return true;
8304 return false;
47f1c6c9 8305}
79e53945 8306
9a935856
DV		 8307/**
8308 * intel_modeset_update_staged_output_state
8309 *
8310 * Updates the staged output configuration state, e.g. after we've read out the
8311 * current hw state.
8312 */
8313static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8314{
9a935856
DV		 8315 struct intel_encoder *encoder;
8316 struct intel_connector *connector;
f6e5b160 8317
9a935856
DV		 8318 list_for_each_entry(connector, &dev->mode_config.connector_list,
8319 base.head) {
8320 connector->new_encoder =
8321 to_intel_encoder(connector->base.encoder);
8322 }
f6e5b160 8323
9a935856
DV		 8324 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8325 base.head) {
8326 encoder->new_crtc =
8327 to_intel_crtc(encoder->base.crtc);
8328 }
f6e5b160
CW		 8329}
8330
9a935856
DV		 8331/**
8332 * intel_modeset_commit_output_state
8333 *
8334 * This function copies the stage display pipe configuration to the real one.
8335 */
8336static void intel_modeset_commit_output_state(struct drm_device *dev)
8337{
8338 struct intel_encoder *encoder;
8339 struct intel_connector *connector;
f6e5b160 8340
9a935856
DV		 8341 list_for_each_entry(connector, &dev->mode_config.connector_list,
8342 base.head) {
8343 connector->base.encoder = &connector->new_encoder->base;
8344 }
f6e5b160 8345
9a935856
DV		 8346 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8347 base.head) {
8348 encoder->base.crtc = &encoder->new_crtc->base;
8349 }
8350}
8351
050f7aeb
DV		 8352static void
8353connected_sink_compute_bpp(struct intel_connector * connector,
8354 struct intel_crtc_config *pipe_config)
8355{
8356 int bpp = pipe_config->pipe_bpp;
8357
8358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8359 connector->base.base.id,
8360 drm_get_connector_name(&connector->base));
8361
8362 /* Don't use an invalid EDID bpc value */
8363 if (connector->base.display_info.bpc &&
8364 connector->base.display_info.bpc * 3 < bpp) {
8365 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8366 bpp, connector->base.display_info.bpc*3);
8367 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8368 }
8369
8370 /* Clamp bpp to 8 on screens without EDID 1.4 */
8371 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8372 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8373 bpp);
8374 pipe_config->pipe_bpp = 24;
8375 }
8376}
8377
4e53c2e0 8378static int
050f7aeb
DV		 8379compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8380 struct drm_framebuffer *fb,
8381 struct intel_crtc_config *pipe_config)
4e53c2e0 8382{
050f7aeb
DV		 8383 struct drm_device *dev = crtc->base.dev;
8384 struct intel_connector *connector;
4e53c2e0
DV		 8385 int bpp;
8386
d42264b1
DV		 8387 switch (fb->pixel_format) {
8388 case DRM_FORMAT_C8:
4e53c2e0
DV		 8389 bpp = 8*3; /* since we go through a colormap */
8390 break;
d42264b1
DV		 8391 case DRM_FORMAT_XRGB1555:
8392 case DRM_FORMAT_ARGB1555:
8393 /* checked in intel_framebuffer_init already */
8394 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8395 return -EINVAL;
8396 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8397 bpp = 6*3; /* min is 18bpp */
8398 break;
d42264b1
DV		 8399 case DRM_FORMAT_XBGR8888:
8400 case DRM_FORMAT_ABGR8888:
8401 /* checked in intel_framebuffer_init already */
8402 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8403 return -EINVAL;
8404 case DRM_FORMAT_XRGB8888:
8405 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8406 bpp = 8*3;
8407 break;
d42264b1
DV		 8408 case DRM_FORMAT_XRGB2101010:
8409 case DRM_FORMAT_ARGB2101010:
8410 case DRM_FORMAT_XBGR2101010:
8411 case DRM_FORMAT_ABGR2101010:
8412 /* checked in intel_framebuffer_init already */
8413 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8414 return -EINVAL;
4e53c2e0
DV		 8415 bpp = 10*3;
8416 break;
baba133a 8417 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8418 default:
8419 DRM_DEBUG_KMS("unsupported depth\n");
8420 return -EINVAL;
8421 }
8422
4e53c2e0
DV		 8423 pipe_config->pipe_bpp = bpp;
8424
8425 /* Clamp display bpp to EDID value */
8426 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8427 base.head) {
1b829e05
DV		 8428 if (!connector->new_encoder ||
8429 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8430 continue;
8431
050f7aeb 8432 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8433 }
8434
8435 return bpp;
8436}
8437
644db711
DV		 8438static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8439{
8440 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8441 "type: 0x%x flags: 0x%x\n",
1342830c 8442 mode->crtc_clock,
644db711
DV		 8443 mode->crtc_hdisplay, mode->crtc_hsync_start,
8444 mode->crtc_hsync_end, mode->crtc_htotal,
8445 mode->crtc_vdisplay, mode->crtc_vsync_start,
8446 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8447}
8448
c0b03411
DV		 8449static void intel_dump_pipe_config(struct intel_crtc *crtc,
8450 struct intel_crtc_config *pipe_config,
8451 const char *context)
8452{
8453 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8454 context, pipe_name(crtc->pipe));
8455
8456 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8457 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8458 pipe_config->pipe_bpp, pipe_config->dither);
8459 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8460 pipe_config->has_pch_encoder,
8461 pipe_config->fdi_lanes,
8462 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8463 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8464 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8465 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8466 pipe_config->has_dp_encoder,
8467 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8468 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8469 pipe_config->dp_m_n.tu);
c0b03411
DV		 8470 DRM_DEBUG_KMS("requested mode:\n");
8471 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8472 DRM_DEBUG_KMS("adjusted mode:\n");
8473 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8474 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8475 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8476 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8477 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8478 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8479 pipe_config->gmch_pfit.control,
8480 pipe_config->gmch_pfit.pgm_ratios,
8481 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8482 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8483 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8484 pipe_config->pch_pfit.size,
8485 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8486 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8487 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8488}
8489
accfc0c5
DV		 8490static bool check_encoder_cloning(struct drm_crtc *crtc)
8491{
8492 int num_encoders = 0;
8493 bool uncloneable_encoders = false;
8494 struct intel_encoder *encoder;
8495
8496 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8497 base.head) {
8498 if (&encoder->new_crtc->base != crtc)
8499 continue;
8500
8501 num_encoders++;
8502 if (!encoder->cloneable)
8503 uncloneable_encoders = true;
8504 }
8505
8506 return !(num_encoders > 1 && uncloneable_encoders);
8507}
8508
b8cecdf5
DV		 8509static struct intel_crtc_config *
8510intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8511 struct drm_framebuffer *fb,
b8cecdf5 8512 struct drm_display_mode *mode)
ee7b9f93 8513{
7758a113 8514 struct drm_device *dev = crtc->dev;
7758a113 8515 struct intel_encoder *encoder;
b8cecdf5 8516 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8517 int plane_bpp, ret = -EINVAL;
8518 bool retry = true;
ee7b9f93 8519
accfc0c5
DV		 8520 if (!check_encoder_cloning(crtc)) {
8521 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8522 return ERR_PTR(-EINVAL);
8523 }
8524
b8cecdf5
DV		 8525 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8526 if (!pipe_config)
7758a113
DV		 8527 return ERR_PTR(-ENOMEM);
8528
b8cecdf5
DV		 8529 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8530 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8531
e143a21c
DV		 8532 pipe_config->cpu_transcoder =
8533 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8534 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8535
2960bc9c
ID		 8536 /*
8537 * Sanitize sync polarity flags based on requested ones. If neither
8538 * positive or negative polarity is requested, treat this as meaning
8539 * negative polarity.
8540 */
8541 if (!(pipe_config->adjusted_mode.flags &
8542 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8543 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8544
8545 if (!(pipe_config->adjusted_mode.flags &
8546 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8547 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8548
050f7aeb
DV		 8549 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8550 * plane pixel format and any sink constraints into account. Returns the
8551 * source plane bpp so that dithering can be selected on mismatches
8552 * after encoders and crtc also have had their say. */
8553 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8554 fb, pipe_config);
4e53c2e0
DV		 8555 if (plane_bpp < 0)
8556 goto fail;
8557
e41a56be
VS		 8558 /*
8559 * Determine the real pipe dimensions. Note that stereo modes can
8560 * increase the actual pipe size due to the frame doubling and
8561 * insertion of additional space for blanks between the frame. This
8562 * is stored in the crtc timings. We use the requested mode to do this
8563 * computation to clearly distinguish it from the adjusted mode, which
8564 * can be changed by the connectors in the below retry loop.
8565 */
8566 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8567 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8568 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8569
e29c22c0 8570encoder_retry:
ef1b460d 8571 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8572 pipe_config->port_clock = 0;
ef1b460d 8573 pipe_config->pixel_multiplier = 1;
ff9a6750 8574
135c81b8 8575 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8576 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8577
7758a113
DV		 8578 /* Pass our mode to the connectors and the CRTC to give them a chance to
8579 * adjust it according to limitations or connector properties, and also
8580 * a chance to reject the mode entirely.
47f1c6c9 8581 */
7758a113
DV		 8582 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8583 base.head) {
47f1c6c9 8584
7758a113
DV		 8585 if (&encoder->new_crtc->base != crtc)
8586 continue;
7ae89233 8587
efea6e8e
DV		 8588 if (!(encoder->compute_config(encoder, pipe_config))) {
8589 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8590 goto fail;
8591 }
ee7b9f93 8592 }
47f1c6c9 8593
ff9a6750
DV		 8594 /* Set default port clock if not overwritten by the encoder. Needs to be
8595 * done afterwards in case the encoder adjusts the mode. */
8596 if (!pipe_config->port_clock)
241bfc38
DL		 8597 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8598 * pipe_config->pixel_multiplier;
ff9a6750 8599
a43f6e0f 8600 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8601 if (ret < 0) {
7758a113
DV		 8602 DRM_DEBUG_KMS("CRTC fixup failed\n");
8603 goto fail;
ee7b9f93 8604 }
e29c22c0
DV		 8605
8606 if (ret == RETRY) {
8607 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8608 ret = -EINVAL;
8609 goto fail;
8610 }
8611
8612 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8613 retry = false;
8614 goto encoder_retry;
8615 }
8616
4e53c2e0
DV		 8617 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8618 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8619 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8620
b8cecdf5 8621 return pipe_config;
7758a113 8622fail:
b8cecdf5 8623 kfree(pipe_config);
e29c22c0 8624 return ERR_PTR(ret);
ee7b9f93 8625}
47f1c6c9 8626
e2e1ed41
DV		 8627/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8628 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8629static void
8630intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8631 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8632{
8633 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8634 struct drm_device *dev = crtc->dev;
8635 struct intel_encoder *encoder;
8636 struct intel_connector *connector;
8637 struct drm_crtc *tmp_crtc;
79e53945 8638
e2e1ed41 8639 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8640
e2e1ed41
DV		 8641 /* Check which crtcs have changed outputs connected to them, these need
8642 * to be part of the prepare_pipes mask. We don't (yet) support global
8643 * modeset across multiple crtcs, so modeset_pipes will only have one
8644 * bit set at most. */
8645 list_for_each_entry(connector, &dev->mode_config.connector_list,
8646 base.head) {
8647 if (connector->base.encoder == &connector->new_encoder->base)
8648 continue;
79e53945 8649
e2e1ed41
DV		 8650 if (connector->base.encoder) {
8651 tmp_crtc = connector->base.encoder->crtc;
8652
8653 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8654 }
8655
8656 if (connector->new_encoder)
8657 *prepare_pipes |=
8658 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8659 }
8660
e2e1ed41
DV		 8661 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8662 base.head) {
8663 if (encoder->base.crtc == &encoder->new_crtc->base)
8664 continue;
8665
8666 if (encoder->base.crtc) {
8667 tmp_crtc = encoder->base.crtc;
8668
8669 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8670 }
8671
8672 if (encoder->new_crtc)
8673 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8674 }
8675
e2e1ed41
DV		 8676 /* Check for any pipes that will be fully disabled ... */
8677 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8678 base.head) {
8679 bool used = false;
22fd0fab 8680
e2e1ed41
DV		 8681 /* Don't try to disable disabled crtcs. */
8682 if (!intel_crtc->base.enabled)
8683 continue;
7e7d76c3 8684
e2e1ed41
DV		 8685 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8686 base.head) {
8687 if (encoder->new_crtc == intel_crtc)
8688 used = true;
8689 }
8690
8691 if (!used)
8692 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8693 }
8694
e2e1ed41
DV		 8695
8696 /* set_mode is also used to update properties on life display pipes. */
8697 intel_crtc = to_intel_crtc(crtc);
8698 if (crtc->enabled)
8699 *prepare_pipes |= 1 << intel_crtc->pipe;
8700
b6c5164d
DV		 8701 /*
8702 * For simplicity do a full modeset on any pipe where the output routing
8703 * changed. We could be more clever, but that would require us to be
8704 * more careful with calling the relevant encoder->mode_set functions.
8705 */
e2e1ed41
DV		 8706 if (*prepare_pipes)
8707 *modeset_pipes = *prepare_pipes;
8708
8709 /* ... and mask these out. */
8710 *modeset_pipes &= ~(*disable_pipes);
8711 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8712
8713 /*
8714 * HACK: We don't (yet) fully support global modesets. intel_set_config
8715 * obies this rule, but the modeset restore mode of
8716 * intel_modeset_setup_hw_state does not.
8717 */
8718 *modeset_pipes &= 1 << intel_crtc->pipe;
8719 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8720
8721 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8722 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8723}
79e53945 8724
ea9d758d 8725static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8726{
ea9d758d 8727 struct drm_encoder *encoder;
f6e5b160 8728 struct drm_device *dev = crtc->dev;
f6e5b160 8729
ea9d758d
DV		 8730 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8731 if (encoder->crtc == crtc)
8732 return true;
8733
8734 return false;
8735}
8736
8737static void
8738intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8739{
8740 struct intel_encoder *intel_encoder;
8741 struct intel_crtc *intel_crtc;
8742 struct drm_connector *connector;
8743
8744 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8745 base.head) {
8746 if (!intel_encoder->base.crtc)
8747 continue;
8748
8749 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8750
8751 if (prepare_pipes & (1 << intel_crtc->pipe))
8752 intel_encoder->connectors_active = false;
8753 }
8754
8755 intel_modeset_commit_output_state(dev);
8756
8757 /* Update computed state. */
8758 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8759 base.head) {
8760 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8761 }
8762
8763 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8764 if (!connector->encoder || !connector->encoder->crtc)
8765 continue;
8766
8767 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8768
8769 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8770 struct drm_property *dpms_property =
8771 dev->mode_config.dpms_property;
8772
ea9d758d 8773 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8774 drm_object_property_set_value(&connector->base,
68d34720
DV		 8775 dpms_property,
8776 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8777
8778 intel_encoder = to_intel_encoder(connector->encoder);
8779 intel_encoder->connectors_active = true;
8780 }
8781 }
8782
8783}
8784
3bd26263 8785static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8786{
3bd26263 8787 int diff;
f1f644dc
JB		 8788
8789 if (clock1 == clock2)
8790 return true;
8791
8792 if (!clock1 || !clock2)
8793 return false;
8794
8795 diff = abs(clock1 - clock2);
8796
8797 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8798 return true;
8799
8800 return false;
8801}
8802
25c5b266
DV		 8803#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8804 list_for_each_entry((intel_crtc), \
8805 &(dev)->mode_config.crtc_list, \
8806 base.head) \
0973f18f 8807 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8808
0e8ffe1b 8809static bool
2fa2fe9a
DV		 8810intel_pipe_config_compare(struct drm_device *dev,
8811 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8812 struct intel_crtc_config *pipe_config)
8813{
66e985c0
DV		 8814#define PIPE_CONF_CHECK_X(name) \
8815 if (current_config->name != pipe_config->name) { \
8816 DRM_ERROR("mismatch in " #name " " \
8817 "(expected 0x%08x, found 0x%08x)\n", \
8818 current_config->name, \
8819 pipe_config->name); \
8820 return false; \
8821 }
8822
08a24034
DV		 8823#define PIPE_CONF_CHECK_I(name) \
8824 if (current_config->name != pipe_config->name) { \
8825 DRM_ERROR("mismatch in " #name " " \
8826 "(expected %i, found %i)\n", \
8827 current_config->name, \
8828 pipe_config->name); \
8829 return false; \
88adfff1
DV		 8830 }
8831
1bd1bd80
DV		 8832#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8833 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8834 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8835 "(expected %i, found %i)\n", \
8836 current_config->name & (mask), \
8837 pipe_config->name & (mask)); \
8838 return false; \
8839 }
8840
5e550656
VS		 8841#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8842 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8843 DRM_ERROR("mismatch in " #name " " \
8844 "(expected %i, found %i)\n", \
8845 current_config->name, \
8846 pipe_config->name); \
8847 return false; \
8848 }
8849
bb760063
DV		 8850#define PIPE_CONF_QUIRK(quirk) \
8851 ((current_config->quirks | pipe_config->quirks) & (quirk))
8852
eccb140b
DV		 8853 PIPE_CONF_CHECK_I(cpu_transcoder);
8854
08a24034
DV		 8855 PIPE_CONF_CHECK_I(has_pch_encoder);
8856 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8857 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8858 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8859 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8860 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8861 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8862
eb14cb74
VS		 8863 PIPE_CONF_CHECK_I(has_dp_encoder);
8864 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8865 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8866 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8867 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8868 PIPE_CONF_CHECK_I(dp_m_n.tu);
8869
1bd1bd80
DV		 8870 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8871 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8872 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8873 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8874 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8875 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8876
8877 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8878 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8879 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8880 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8881 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8882 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8883
c93f54cf 8884 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8885
1bd1bd80
DV		 8886 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8887 DRM_MODE_FLAG_INTERLACE);
8888
bb760063
DV		 8889 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8890 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8891 DRM_MODE_FLAG_PHSYNC);
8892 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8893 DRM_MODE_FLAG_NHSYNC);
8894 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8895 DRM_MODE_FLAG_PVSYNC);
8896 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8897 DRM_MODE_FLAG_NVSYNC);
8898 }
045ac3b5 8899
37327abd
VS		 8900 PIPE_CONF_CHECK_I(pipe_src_w);
8901 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8902
2fa2fe9a
DV		 8903 PIPE_CONF_CHECK_I(gmch_pfit.control);
8904 /* pfit ratios are autocomputed by the hw on gen4+ */
8905 if (INTEL_INFO(dev)->gen < 4)
8906 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8907 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8908 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8909 if (current_config->pch_pfit.enabled) {
8910 PIPE_CONF_CHECK_I(pch_pfit.pos);
8911 PIPE_CONF_CHECK_I(pch_pfit.size);
8912 }
2fa2fe9a 8913
42db64ef
PZ		 8914 PIPE_CONF_CHECK_I(ips_enabled);
8915
282740f7
VS		 8916 PIPE_CONF_CHECK_I(double_wide);
8917
c0d43d62 8918 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8919 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8920 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8921 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8922 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8923
42571aef
VS		 8924 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8925 PIPE_CONF_CHECK_I(pipe_bpp);
8926
d71b8d4a 8927 if (!IS_HASWELL(dev)) {
241bfc38 8928 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8929 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8930 }
5e550656 8931
66e985c0 8932#undef PIPE_CONF_CHECK_X
08a24034 8933#undef PIPE_CONF_CHECK_I
1bd1bd80 8934#undef PIPE_CONF_CHECK_FLAGS
5e550656 8935#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8936#undef PIPE_CONF_QUIRK
88adfff1 8937
0e8ffe1b
DV		 8938 return true;
8939}
8940
91d1b4bd
DV		 8941static void
8942check_connector_state(struct drm_device *dev)
8af6cf88 8943{
8af6cf88
DV		 8944 struct intel_connector *connector;
8945
8946 list_for_each_entry(connector, &dev->mode_config.connector_list,
8947 base.head) {
8948 /* This also checks the encoder/connector hw state with the
8949 * ->get_hw_state callbacks. */
8950 intel_connector_check_state(connector);
8951
8952 WARN(&connector->new_encoder->base != connector->base.encoder,
8953 "connector's staged encoder doesn't match current encoder\n");
8954 }
91d1b4bd
DV		 8955}
8956
8957static void
8958check_encoder_state(struct drm_device *dev)
8959{
8960 struct intel_encoder *encoder;
8961 struct intel_connector *connector;
8af6cf88
DV		 8962
8963 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8964 base.head) {
8965 bool enabled = false;
8966 bool active = false;
8967 enum pipe pipe, tracked_pipe;
8968
8969 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8970 encoder->base.base.id,
8971 drm_get_encoder_name(&encoder->base));
8972
8973 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8974 "encoder's stage crtc doesn't match current crtc\n");
8975 WARN(encoder->connectors_active && !encoder->base.crtc,
8976 "encoder's active_connectors set, but no crtc\n");
8977
8978 list_for_each_entry(connector, &dev->mode_config.connector_list,
8979 base.head) {
8980 if (connector->base.encoder != &encoder->base)
8981 continue;
8982 enabled = true;
8983 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8984 active = true;
8985 }
8986 WARN(!!encoder->base.crtc != enabled,
8987 "encoder's enabled state mismatch "
8988 "(expected %i, found %i)\n",
8989 !!encoder->base.crtc, enabled);
8990 WARN(active && !encoder->base.crtc,
8991 "active encoder with no crtc\n");
8992
8993 WARN(encoder->connectors_active != active,
8994 "encoder's computed active state doesn't match tracked active state "
8995 "(expected %i, found %i)\n", active, encoder->connectors_active);
8996
8997 active = encoder->get_hw_state(encoder, &pipe);
8998 WARN(active != encoder->connectors_active,
8999 "encoder's hw state doesn't match sw tracking "
9000 "(expected %i, found %i)\n",
9001 encoder->connectors_active, active);
9002
9003 if (!encoder->base.crtc)
9004 continue;
9005
9006 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9007 WARN(active && pipe != tracked_pipe,
9008 "active encoder's pipe doesn't match"
9009 "(expected %i, found %i)\n",
9010 tracked_pipe, pipe);
9011
9012 }
91d1b4bd
DV		 9013}
9014
9015static void
9016check_crtc_state(struct drm_device *dev)
9017{
9018 drm_i915_private_t *dev_priv = dev->dev_private;
9019 struct intel_crtc *crtc;
9020 struct intel_encoder *encoder;
9021 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9022
9023 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9024 base.head) {
9025 bool enabled = false;
9026 bool active = false;
9027
045ac3b5
JB		 9028 memset(&pipe_config, 0, sizeof(pipe_config));
9029
8af6cf88
DV		 9030 DRM_DEBUG_KMS("[CRTC:%d]\n",
9031 crtc->base.base.id);
9032
9033 WARN(crtc->active && !crtc->base.enabled,
9034 "active crtc, but not enabled in sw tracking\n");
9035
9036 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9037 base.head) {
9038 if (encoder->base.crtc != &crtc->base)
9039 continue;
9040 enabled = true;
9041 if (encoder->connectors_active)
9042 active = true;
9043 }
6c49f241 9044
8af6cf88
DV		 9045 WARN(active != crtc->active,
9046 "crtc's computed active state doesn't match tracked active state "
9047 "(expected %i, found %i)\n", active, crtc->active);
9048 WARN(enabled != crtc->base.enabled,
9049 "crtc's computed enabled state doesn't match tracked enabled state "
9050 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9051
0e8ffe1b
DV		 9052 active = dev_priv->display.get_pipe_config(crtc,
9053 &pipe_config);
d62cf62a
DV		 9054
9055 /* hw state is inconsistent with the pipe A quirk */
9056 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9057 active = crtc->active;
9058
6c49f241
DV		 9059 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9060 base.head) {
3eaba51c 9061 enum pipe pipe;
6c49f241
DV		 9062 if (encoder->base.crtc != &crtc->base)
9063 continue;
3eaba51c
VS		 9064 if (encoder->get_config &&
9065 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9066 encoder->get_config(encoder, &pipe_config);
9067 }
9068
0e8ffe1b
DV		 9069 WARN(crtc->active != active,
9070 "crtc active state doesn't match with hw state "
9071 "(expected %i, found %i)\n", crtc->active, active);
9072
c0b03411
DV		 9073 if (active &&
9074 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9075 WARN(1, "pipe state doesn't match!\n");
9076 intel_dump_pipe_config(crtc, &pipe_config,
9077 "[hw state]");
9078 intel_dump_pipe_config(crtc, &crtc->config,
9079 "[sw state]");
9080 }
8af6cf88
DV		 9081 }
9082}
9083
91d1b4bd
DV		 9084static void
9085check_shared_dpll_state(struct drm_device *dev)
9086{
9087 drm_i915_private_t *dev_priv = dev->dev_private;
9088 struct intel_crtc *crtc;
9089 struct intel_dpll_hw_state dpll_hw_state;
9090 int i;
5358901f
DV		 9091
9092 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9093 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9094 int enabled_crtcs = 0, active_crtcs = 0;
9095 bool active;
9096
9097 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9098
9099 DRM_DEBUG_KMS("%s\n", pll->name);
9100
9101 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9102
9103 WARN(pll->active > pll->refcount,
9104 "more active pll users than references: %i vs %i\n",
9105 pll->active, pll->refcount);
9106 WARN(pll->active && !pll->on,
9107 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9108 WARN(pll->on && !pll->active,
9109 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9110 WARN(pll->on != active,
9111 "pll on state mismatch (expected %i, found %i)\n",
9112 pll->on, active);
9113
9114 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9115 base.head) {
9116 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9117 enabled_crtcs++;
9118 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9119 active_crtcs++;
9120 }
9121 WARN(pll->active != active_crtcs,
9122 "pll active crtcs mismatch (expected %i, found %i)\n",
9123 pll->active, active_crtcs);
9124 WARN(pll->refcount != enabled_crtcs,
9125 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9126 pll->refcount, enabled_crtcs);
66e985c0
DV		 9127
9128 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9129 sizeof(dpll_hw_state)),
9130 "pll hw state mismatch\n");
5358901f 9131 }
8af6cf88
DV		 9132}
9133
91d1b4bd
DV		 9134void
9135intel_modeset_check_state(struct drm_device *dev)
9136{
9137 check_connector_state(dev);
9138 check_encoder_state(dev);
9139 check_crtc_state(dev);
9140 check_shared_dpll_state(dev);
9141}
9142
18442d08
VS		 9143void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9144 int dotclock)
9145{
9146 /*
9147 * FDI already provided one idea for the dotclock.
9148 * Yell if the encoder disagrees.
9149 */
241bfc38 9150 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9151 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9152 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9153}
9154
f30da187
DV		 9155static int __intel_set_mode(struct drm_crtc *crtc,
9156 struct drm_display_mode *mode,
9157 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9158{
9159 struct drm_device *dev = crtc->dev;
dbf2b54e 9160 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9161 struct drm_display_mode *saved_mode, *saved_hwmode;
9162 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9163 struct intel_crtc *intel_crtc;
9164 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9165 int ret = 0;
a6778b3c 9166
a1e22653 9167 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9168 if (!saved_mode)
9169 return -ENOMEM;
3ac18232 9170 saved_hwmode = saved_mode + 1;
a6778b3c 9171
e2e1ed41 9172 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9173 &prepare_pipes, &disable_pipes);
9174
3ac18232
TG		 9175 *saved_hwmode = crtc->hwmode;
9176 *saved_mode = crtc->mode;
a6778b3c 9177
25c5b266
DV		 9178 /* Hack: Because we don't (yet) support global modeset on multiple
9179 * crtcs, we don't keep track of the new mode for more than one crtc.
9180 * Hence simply check whether any bit is set in modeset_pipes in all the
9181 * pieces of code that are not yet converted to deal with mutliple crtcs
9182 * changing their mode at the same time. */
25c5b266 9183 if (modeset_pipes) {
4e53c2e0 9184 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9185 if (IS_ERR(pipe_config)) {
9186 ret = PTR_ERR(pipe_config);
9187 pipe_config = NULL;
9188
3ac18232 9189 goto out;
25c5b266 9190 }
c0b03411
DV		 9191 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9192 "[modeset]");
25c5b266 9193 }
a6778b3c 9194
460da916
DV		 9195 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9196 intel_crtc_disable(&intel_crtc->base);
9197
ea9d758d
DV		 9198 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9199 if (intel_crtc->base.enabled)
9200 dev_priv->display.crtc_disable(&intel_crtc->base);
9201 }
a6778b3c 9202
6c4c86f5
DV		 9203 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9204 * to set it here already despite that we pass it down the callchain.
f6e5b160 9205 */
b8cecdf5 9206 if (modeset_pipes) {
25c5b266 9207 crtc->mode = *mode;
b8cecdf5
DV		 9208 /* mode_set/enable/disable functions rely on a correct pipe
9209 * config. */
9210 to_intel_crtc(crtc)->config = *pipe_config;
9211 }
7758a113 9212
ea9d758d
DV		 9213 /* Only after disabling all output pipelines that will be changed can we
9214 * update the the output configuration. */
9215 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9216
47fab737
DV		 9217 if (dev_priv->display.modeset_global_resources)
9218 dev_priv->display.modeset_global_resources(dev);
9219
a6778b3c
DV		 9220 /* Set up the DPLL and any encoders state that needs to adjust or depend
9221 * on the DPLL.
f6e5b160 9222 */
25c5b266 9223 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9224 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9225 x, y, fb);
9226 if (ret)
9227 goto done;
a6778b3c
DV		 9228 }
9229
9230 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9231 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9232 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9233
25c5b266
DV		 9234 if (modeset_pipes) {
9235 /* Store real post-adjustment hardware mode. */
b8cecdf5 9236 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9237
25c5b266
DV		 9238 /* Calculate and store various constants which
9239 * are later needed by vblank and swap-completion
9240 * timestamping. They are derived from true hwmode.
9241 */
9242 drm_calc_timestamping_constants(crtc);
9243 }
a6778b3c
DV		 9244
9245 /* FIXME: add subpixel order */
9246done:
c0c36b94 9247 if (ret && crtc->enabled) {
3ac18232
TG		 9248 crtc->hwmode = *saved_hwmode;
9249 crtc->mode = *saved_mode;
a6778b3c
DV		 9250 }
9251
3ac18232 9252out:
b8cecdf5 9253 kfree(pipe_config);
3ac18232 9254 kfree(saved_mode);
a6778b3c 9255 return ret;
f6e5b160
CW		 9256}
9257
e7457a9a
DL		 9258static int intel_set_mode(struct drm_crtc *crtc,
9259 struct drm_display_mode *mode,
9260 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9261{
9262 int ret;
9263
9264 ret = __intel_set_mode(crtc, mode, x, y, fb);
9265
9266 if (ret == 0)
9267 intel_modeset_check_state(crtc->dev);
9268
9269 return ret;
9270}
9271
c0c36b94
CW		 9272void intel_crtc_restore_mode(struct drm_crtc *crtc)
9273{
9274 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9275}
9276
25c5b266
DV		 9277#undef for_each_intel_crtc_masked
9278
d9e55608
DV		 9279static void intel_set_config_free(struct intel_set_config *config)
9280{
9281 if (!config)
9282 return;
9283
1aa4b628
DV		 9284 kfree(config->save_connector_encoders);
9285 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9286 kfree(config);
9287}
9288
85f9eb71
DV		 9289static int intel_set_config_save_state(struct drm_device *dev,
9290 struct intel_set_config *config)
9291{
85f9eb71
DV		 9292 struct drm_encoder *encoder;
9293 struct drm_connector *connector;
9294 int count;
9295
1aa4b628
DV		 9296 config->save_encoder_crtcs =
9297 kcalloc(dev->mode_config.num_encoder,
9298 sizeof(struct drm_crtc *), GFP_KERNEL);
9299 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9300 return -ENOMEM;
9301
1aa4b628
DV		 9302 config->save_connector_encoders =
9303 kcalloc(dev->mode_config.num_connector,
9304 sizeof(struct drm_encoder *), GFP_KERNEL);
9305 if (!config->save_connector_encoders)
85f9eb71
DV		 9306 return -ENOMEM;
9307
9308 /* Copy data. Note that driver private data is not affected.
9309 * Should anything bad happen only the expected state is
9310 * restored, not the drivers personal bookkeeping.
9311 */
85f9eb71
DV		 9312 count = 0;
9313 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9314 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9315 }
9316
9317 count = 0;
9318 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9319 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9320 }
9321
9322 return 0;
9323}
9324
9325static void intel_set_config_restore_state(struct drm_device *dev,
9326 struct intel_set_config *config)
9327{
9a935856
DV		 9328 struct intel_encoder *encoder;
9329 struct intel_connector *connector;
85f9eb71
DV		 9330 int count;
9331
85f9eb71 9332 count = 0;
9a935856
DV		 9333 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9334 encoder->new_crtc =
9335 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9336 }
9337
9338 count = 0;
9a935856
DV		 9339 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9340 connector->new_encoder =
9341 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9342 }
9343}
9344
e3de42b6 9345static bool
2e57f47d 9346is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9347{
9348 int i;
9349
2e57f47d
CW		 9350 if (set->num_connectors == 0)
9351 return false;
9352
9353 if (WARN_ON(set->connectors == NULL))
9354 return false;
9355
9356 for (i = 0; i < set->num_connectors; i++)
9357 if (set->connectors[i]->encoder &&
9358 set->connectors[i]->encoder->crtc == set->crtc &&
9359 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9360 return true;
9361
9362 return false;
9363}
9364
5e2b584e
DV		 9365static void
9366intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9367 struct intel_set_config *config)
9368{
9369
9370 /* We should be able to check here if the fb has the same properties
9371 * and then just flip_or_move it */
2e57f47d
CW		 9372 if (is_crtc_connector_off(set)) {
9373 config->mode_changed = true;
e3de42b6 9374 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9375 /* If we have no fb then treat it as a full mode set */
9376 if (set->crtc->fb == NULL) {
319d9827
JB		 9377 struct intel_crtc *intel_crtc =
9378 to_intel_crtc(set->crtc);
9379
9380 if (intel_crtc->active && i915_fastboot) {
9381 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9382 config->fb_changed = true;
9383 } else {
9384 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9385 config->mode_changed = true;
9386 }
5e2b584e
DV		 9387 } else if (set->fb == NULL) {
9388 config->mode_changed = true;
72f4901e
DV		 9389 } else if (set->fb->pixel_format !=
9390 set->crtc->fb->pixel_format) {
5e2b584e 9391 config->mode_changed = true;
e3de42b6 9392 } else {
5e2b584e 9393 config->fb_changed = true;
e3de42b6 9394 }
5e2b584e
DV		 9395 }
9396
835c5873 9397 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9398 config->fb_changed = true;
9399
9400 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9401 DRM_DEBUG_KMS("modes are different, full mode set\n");
9402 drm_mode_debug_printmodeline(&set->crtc->mode);
9403 drm_mode_debug_printmodeline(set->mode);
9404 config->mode_changed = true;
9405 }
a1d95703
CW		 9406
9407 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9408 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9409}
9410
2e431051 9411static int
9a935856
DV		 9412intel_modeset_stage_output_state(struct drm_device *dev,
9413 struct drm_mode_set *set,
9414 struct intel_set_config *config)
50f56119 9415{
85f9eb71 9416 struct drm_crtc *new_crtc;
9a935856
DV		 9417 struct intel_connector *connector;
9418 struct intel_encoder *encoder;
f3f08572 9419 int ro;
50f56119 9420
9abdda74 9421 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9422 * of connectors. For paranoia, double-check this. */
9423 WARN_ON(!set->fb && (set->num_connectors != 0));
9424 WARN_ON(set->fb && (set->num_connectors == 0));
9425
9a935856
DV		 9426 list_for_each_entry(connector, &dev->mode_config.connector_list,
9427 base.head) {
9428 /* Otherwise traverse passed in connector list and get encoders
9429 * for them. */
50f56119 9430 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9431 if (set->connectors[ro] == &connector->base) {
9432 connector->new_encoder = connector->encoder;
50f56119
DV		 9433 break;
9434 }
9435 }
9436
9a935856
DV		 9437 /* If we disable the crtc, disable all its connectors. Also, if
9438 * the connector is on the changing crtc but not on the new
9439 * connector list, disable it. */
9440 if ((!set->fb || ro == set->num_connectors) &&
9441 connector->base.encoder &&
9442 connector->base.encoder->crtc == set->crtc) {
9443 connector->new_encoder = NULL;
9444
9445 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9446 connector->base.base.id,
9447 drm_get_connector_name(&connector->base));
9448 }
9449
9450
9451 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9452 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9453 config->mode_changed = true;
50f56119
DV		 9454 }
9455 }
9a935856 9456 /* connector->new_encoder is now updated for all connectors. */
50f56119 9457
9a935856 9458 /* Update crtc of enabled connectors. */
9a935856
DV		 9459 list_for_each_entry(connector, &dev->mode_config.connector_list,
9460 base.head) {
9461 if (!connector->new_encoder)
50f56119
DV		 9462 continue;
9463
9a935856 9464 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9465
9466 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9467 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9468 new_crtc = set->crtc;
9469 }
9470
9471 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9472 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9473 new_crtc)) {
5e2b584e 9474 return -EINVAL;
50f56119 9475 }
9a935856
DV		 9476 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9477
9478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9479 connector->base.base.id,
9480 drm_get_connector_name(&connector->base),
9481 new_crtc->base.id);
9482 }
9483
9484 /* Check for any encoders that needs to be disabled. */
9485 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9486 base.head) {
9487 list_for_each_entry(connector,
9488 &dev->mode_config.connector_list,
9489 base.head) {
9490 if (connector->new_encoder == encoder) {
9491 WARN_ON(!connector->new_encoder->new_crtc);
9492
9493 goto next_encoder;
9494 }
9495 }
9496 encoder->new_crtc = NULL;
9497next_encoder:
9498 /* Only now check for crtc changes so we don't miss encoders
9499 * that will be disabled. */
9500 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9501 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9502 config->mode_changed = true;
50f56119
DV		 9503 }
9504 }
9a935856 9505 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9506
2e431051
DV		 9507 return 0;
9508}
9509
9510static int intel_crtc_set_config(struct drm_mode_set *set)
9511{
9512 struct drm_device *dev;
2e431051
DV		 9513 struct drm_mode_set save_set;
9514 struct intel_set_config *config;
9515 int ret;
2e431051 9516
8d3e375e
DV		 9517 BUG_ON(!set);
9518 BUG_ON(!set->crtc);
9519 BUG_ON(!set->crtc->helper_private);
2e431051 9520
7e53f3a4
DV		 9521 /* Enforce sane interface api - has been abused by the fb helper. */
9522 BUG_ON(!set->mode && set->fb);
9523 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9524
2e431051
DV		 9525 if (set->fb) {
9526 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9527 set->crtc->base.id, set->fb->base.id,
9528 (int)set->num_connectors, set->x, set->y);
9529 } else {
9530 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9531 }
9532
9533 dev = set->crtc->dev;
9534
9535 ret = -ENOMEM;
9536 config = kzalloc(sizeof(*config), GFP_KERNEL);
9537 if (!config)
9538 goto out_config;
9539
9540 ret = intel_set_config_save_state(dev, config);
9541 if (ret)
9542 goto out_config;
9543
9544 save_set.crtc = set->crtc;
9545 save_set.mode = &set->crtc->mode;
9546 save_set.x = set->crtc->x;
9547 save_set.y = set->crtc->y;
9548 save_set.fb = set->crtc->fb;
9549
9550 /* Compute whether we need a full modeset, only an fb base update or no
9551 * change at all. In the future we might also check whether only the
9552 * mode changed, e.g. for LVDS where we only change the panel fitter in
9553 * such cases. */
9554 intel_set_config_compute_mode_changes(set, config);
9555
9a935856 9556 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9557 if (ret)
9558 goto fail;
9559
5e2b584e 9560 if (config->mode_changed) {
c0c36b94
CW		 9561 ret = intel_set_mode(set->crtc, set->mode,
9562 set->x, set->y, set->fb);
5e2b584e 9563 } else if (config->fb_changed) {
4878cae2
VS		 9564 intel_crtc_wait_for_pending_flips(set->crtc);
9565
4f660f49 9566 ret = intel_pipe_set_base(set->crtc,
94352cf9 9567 set->x, set->y, set->fb);
50f56119
DV		 9568 }
9569
2d05eae1 9570 if (ret) {
bf67dfeb
DV		 9571 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9572 set->crtc->base.id, ret);
50f56119 9573fail:
2d05eae1 9574 intel_set_config_restore_state(dev, config);
50f56119 9575
2d05eae1
CW		 9576 /* Try to restore the config */
9577 if (config->mode_changed &&
9578 intel_set_mode(save_set.crtc, save_set.mode,
9579 save_set.x, save_set.y, save_set.fb))
9580 DRM_ERROR("failed to restore config after modeset failure\n");
9581 }
50f56119 9582
d9e55608
DV		 9583out_config:
9584 intel_set_config_free(config);
50f56119
DV		 9585 return ret;
9586}
f6e5b160
CW		 9587
9588static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9589 .cursor_set = intel_crtc_cursor_set,
9590 .cursor_move = intel_crtc_cursor_move,
9591 .gamma_set = intel_crtc_gamma_set,
50f56119 9592 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9593 .destroy = intel_crtc_destroy,
9594 .page_flip = intel_crtc_page_flip,
9595};
9596
79f689aa
PZ		 9597static void intel_cpu_pll_init(struct drm_device *dev)
9598{
affa9354 9599 if (HAS_DDI(dev))
79f689aa
PZ		 9600 intel_ddi_pll_init(dev);
9601}
9602
5358901f
DV		 9603static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9604 struct intel_shared_dpll *pll,
9605 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9606{
5358901f 9607 uint32_t val;
ee7b9f93 9608
5358901f 9609 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9610 hw_state->dpll = val;
9611 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9612 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9613
9614 return val & DPLL_VCO_ENABLE;
9615}
9616
15bdd4cf
DV		 9617static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9618 struct intel_shared_dpll *pll)
9619{
9620 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9621 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9622}
9623
e7b903d2
DV		 9624static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9625 struct intel_shared_dpll *pll)
9626{
e7b903d2
DV		 9627 /* PCH refclock must be enabled first */
9628 assert_pch_refclk_enabled(dev_priv);
9629
15bdd4cf
DV		 9630 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9631
9632 /* Wait for the clocks to stabilize. */
9633 POSTING_READ(PCH_DPLL(pll->id));
9634 udelay(150);
9635
9636 /* The pixel multiplier can only be updated once the
9637 * DPLL is enabled and the clocks are stable.
9638 *
9639 * So write it again.
9640 */
9641 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9642 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9643 udelay(200);
9644}
9645
9646static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9647 struct intel_shared_dpll *pll)
9648{
9649 struct drm_device *dev = dev_priv->dev;
9650 struct intel_crtc *crtc;
e7b903d2
DV		 9651
9652 /* Make sure no transcoder isn't still depending on us. */
9653 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9654 if (intel_crtc_to_shared_dpll(crtc) == pll)
9655 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9656 }
9657
15bdd4cf
DV		 9658 I915_WRITE(PCH_DPLL(pll->id), 0);
9659 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9660 udelay(200);
9661}
9662
46edb027
DV		 9663static char *ibx_pch_dpll_names[] = {
9664 "PCH DPLL A",
9665 "PCH DPLL B",
9666};
9667
7c74ade1 9668static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9669{
e7b903d2 9670 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9671 int i;
9672
7c74ade1 9673 dev_priv->num_shared_dpll = 2;
ee7b9f93 9674
e72f9fbf 9675 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9676 dev_priv->shared_dplls[i].id = i;
9677 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9678 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9679 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9680 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9681 dev_priv->shared_dplls[i].get_hw_state =
9682 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9683 }
9684}
9685
7c74ade1
DV		 9686static void intel_shared_dpll_init(struct drm_device *dev)
9687{
e7b903d2 9688 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9689
9690 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9691 ibx_pch_dpll_init(dev);
9692 else
9693 dev_priv->num_shared_dpll = 0;
9694
9695 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9696 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9697 dev_priv->num_shared_dpll);
9698}
9699
b358d0a6 9700static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9701{
22fd0fab 9702 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9703 struct intel_crtc *intel_crtc;
9704 int i;
9705
955382f3 9706 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9707 if (intel_crtc == NULL)
9708 return;
9709
9710 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9711
9712 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9713 for (i = 0; i < 256; i++) {
9714 intel_crtc->lut_r[i] = i;
9715 intel_crtc->lut_g[i] = i;
9716 intel_crtc->lut_b[i] = i;
9717 }
9718
80824003
JB		 9719 /* Swap pipes & planes for FBC on pre-965 */
9720 intel_crtc->pipe = pipe;
9721 intel_crtc->plane = pipe;
e2e767ab 9722 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9723 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9724 intel_crtc->plane = !pipe;
80824003
JB		 9725 }
9726
22fd0fab
JB		 9727 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9728 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9729 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9730 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9731
79e53945 9732 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9733}
9734
08d7b3d1 9735int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9736 struct drm_file *file)
08d7b3d1 9737{
08d7b3d1 9738 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9739 struct drm_mode_object *drmmode_obj;
9740 struct intel_crtc *crtc;
08d7b3d1 9741
1cff8f6b
DV		 9742 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9743 return -ENODEV;
08d7b3d1 9744
c05422d5
DV		 9745 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9746 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9747
c05422d5 9748 if (!drmmode_obj) {
08d7b3d1
CW		 9749 DRM_ERROR("no such CRTC id\n");
9750 return -EINVAL;
9751 }
9752
c05422d5
DV		 9753 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9754 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9755
c05422d5 9756 return 0;
08d7b3d1
CW		 9757}
9758
66a9278e 9759static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9760{
66a9278e
DV		 9761 struct drm_device *dev = encoder->base.dev;
9762 struct intel_encoder *source_encoder;
79e53945 9763 int index_mask = 0;
79e53945
JB		 9764 int entry = 0;
9765
66a9278e
DV		 9766 list_for_each_entry(source_encoder,
9767 &dev->mode_config.encoder_list, base.head) {
9768
9769 if (encoder == source_encoder)
79e53945 9770 index_mask |= (1 << entry);
66a9278e
DV		 9771
9772 /* Intel hw has only one MUX where enocoders could be cloned. */
9773 if (encoder->cloneable && source_encoder->cloneable)
9774 index_mask |= (1 << entry);
9775
79e53945
JB		 9776 entry++;
9777 }
4ef69c7a 9778
79e53945
JB		 9779 return index_mask;
9780}
9781
4d302442
CW		 9782static bool has_edp_a(struct drm_device *dev)
9783{
9784 struct drm_i915_private *dev_priv = dev->dev_private;
9785
9786 if (!IS_MOBILE(dev))
9787 return false;
9788
9789 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9790 return false;
9791
9792 if (IS_GEN5(dev) &&
9793 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9794 return false;
9795
9796 return true;
9797}
9798
79e53945
JB		 9799static void intel_setup_outputs(struct drm_device *dev)
9800{
725e30ad 9801 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9802 struct intel_encoder *encoder;
cb0953d7 9803 bool dpd_is_edp = false;
79e53945 9804
c9093354 9805 intel_lvds_init(dev);
79e53945 9806
c40c0f5b 9807 if (!IS_ULT(dev))
79935fca 9808 intel_crt_init(dev);
cb0953d7 9809
affa9354 9810 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9811 int found;
9812
9813 /* Haswell uses DDI functions to detect digital outputs */
9814 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9815 /* DDI A only supports eDP */
9816 if (found)
9817 intel_ddi_init(dev, PORT_A);
9818
9819 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9820 * register */
9821 found = I915_READ(SFUSE_STRAP);
9822
9823 if (found & SFUSE_STRAP_DDIB_DETECTED)
9824 intel_ddi_init(dev, PORT_B);
9825 if (found & SFUSE_STRAP_DDIC_DETECTED)
9826 intel_ddi_init(dev, PORT_C);
9827 if (found & SFUSE_STRAP_DDID_DETECTED)
9828 intel_ddi_init(dev, PORT_D);
9829 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9830 int found;
270b3042
DV		 9831 dpd_is_edp = intel_dpd_is_edp(dev);
9832
9833 if (has_edp_a(dev))
9834 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9835
dc0fa718 9836 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9837 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9838 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9839 if (!found)
e2debe91 9840 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9841 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9842 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9843 }
9844
dc0fa718 9845 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9846 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9847
dc0fa718 9848 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9849 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9850
5eb08b69 9851 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9852 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9853
270b3042 9854 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9855 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9856 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9857 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9858 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9859 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9860 PORT_C);
9861 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9862 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9863 PORT_C);
9864 }
19c03924 9865
dc0fa718 9866 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9867 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9868 PORT_B);
67cfc203
VS		 9869 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9870 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9871 }
3cfca973
JN		 9872
9873 intel_dsi_init(dev);
103a196f 9874 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9875 bool found = false;
7d57382e 9876
e2debe91 9877 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9878 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9879 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9880 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9881 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9882 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9883 }
27185ae1 9884
e7281eab 9885 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9886 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9887 }
13520b05
KH		 9888
9889 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9890
e2debe91 9891 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9892 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9893 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9894 }
27185ae1 9895
e2debe91 9896 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9897
b01f2c3a
JB		 9898 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9899 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9900 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9901 }
e7281eab 9902 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9903 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9904 }
27185ae1 9905
b01f2c3a 9906 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9907 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9908 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9909 } else if (IS_GEN2(dev))
79e53945
JB		 9910 intel_dvo_init(dev);
9911
103a196f 9912 if (SUPPORTS_TV(dev))
79e53945
JB		 9913 intel_tv_init(dev);
9914
4ef69c7a
CW		 9915 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9916 encoder->base.possible_crtcs = encoder->crtc_mask;
9917 encoder->base.possible_clones =
66a9278e 9918 intel_encoder_clones(encoder);
79e53945 9919 }
47356eb6 9920
dde86e2d 9921 intel_init_pch_refclk(dev);
270b3042
DV		 9922
9923 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9924}
9925
ddfe1567
CW		 9926void intel_framebuffer_fini(struct intel_framebuffer *fb)
9927{
9928 drm_framebuffer_cleanup(&fb->base);
9929 drm_gem_object_unreference_unlocked(&fb->obj->base);
9930}
9931
79e53945
JB		 9932static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9933{
9934 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9935
ddfe1567 9936 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9937 kfree(intel_fb);
9938}
9939
9940static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9941 struct drm_file *file,
79e53945
JB		 9942 unsigned int *handle)
9943{
9944 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9945 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9946
05394f39 9947 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9948}
9949
9950static const struct drm_framebuffer_funcs intel_fb_funcs = {
9951 .destroy = intel_user_framebuffer_destroy,
9952 .create_handle = intel_user_framebuffer_create_handle,
9953};
9954
38651674
DA		 9955int intel_framebuffer_init(struct drm_device *dev,
9956 struct intel_framebuffer *intel_fb,
308e5bcb 9957 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9958 struct drm_i915_gem_object *obj)
79e53945 9959{
a35cdaa0 9960 int pitch_limit;
79e53945
JB		 9961 int ret;
9962
c16ed4be
CW		 9963 if (obj->tiling_mode == I915_TILING_Y) {
9964 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9965 return -EINVAL;
c16ed4be 9966 }
57cd6508 9967
c16ed4be
CW		 9968 if (mode_cmd->pitches[0] & 63) {
9969 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9970 mode_cmd->pitches[0]);
57cd6508 9971 return -EINVAL;
c16ed4be 9972 }
57cd6508 9973
a35cdaa0
CW		 9974 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9975 pitch_limit = 32*1024;
9976 } else if (INTEL_INFO(dev)->gen >= 4) {
9977 if (obj->tiling_mode)
9978 pitch_limit = 16*1024;
9979 else
9980 pitch_limit = 32*1024;
9981 } else if (INTEL_INFO(dev)->gen >= 3) {
9982 if (obj->tiling_mode)
9983 pitch_limit = 8*1024;
9984 else
9985 pitch_limit = 16*1024;
9986 } else
9987 /* XXX DSPC is limited to 4k tiled */
9988 pitch_limit = 8*1024;
9989
9990 if (mode_cmd->pitches[0] > pitch_limit) {
9991 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9992 obj->tiling_mode ? "tiled" : "linear",
9993 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9994 return -EINVAL;
c16ed4be 9995 }
5d7bd705
VS		 9996
9997 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9998 mode_cmd->pitches[0] != obj->stride) {
9999 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10000 mode_cmd->pitches[0], obj->stride);
5d7bd705 10001 return -EINVAL;
c16ed4be 10002 }
5d7bd705 10003
57779d06 10004 /* Reject formats not supported by any plane early. */
308e5bcb 10005 switch (mode_cmd->pixel_format) {
57779d06 10006 case DRM_FORMAT_C8:
04b3924d
VS		 10007 case DRM_FORMAT_RGB565:
10008 case DRM_FORMAT_XRGB8888:
10009 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10010 break;
10011 case DRM_FORMAT_XRGB1555:
10012 case DRM_FORMAT_ARGB1555:
c16ed4be 10013 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10014 DRM_DEBUG("unsupported pixel format: %s\n",
10015 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10016 return -EINVAL;
c16ed4be 10017 }
57779d06
VS		 10018 break;
10019 case DRM_FORMAT_XBGR8888:
10020 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10021 case DRM_FORMAT_XRGB2101010:
10022 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10023 case DRM_FORMAT_XBGR2101010:
10024 case DRM_FORMAT_ABGR2101010:
c16ed4be 10025 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10026 DRM_DEBUG("unsupported pixel format: %s\n",
10027 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10028 return -EINVAL;
c16ed4be 10029 }
b5626747 10030 break;
04b3924d
VS		 10031 case DRM_FORMAT_YUYV:
10032 case DRM_FORMAT_UYVY:
10033 case DRM_FORMAT_YVYU:
10034 case DRM_FORMAT_VYUY:
c16ed4be 10035 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10036 DRM_DEBUG("unsupported pixel format: %s\n",
10037 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10038 return -EINVAL;
c16ed4be 10039 }
57cd6508
CW		 10040 break;
10041 default:
4ee62c76
VS		 10042 DRM_DEBUG("unsupported pixel format: %s\n",
10043 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10044 return -EINVAL;
10045 }
10046
90f9a336
VS		 10047 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10048 if (mode_cmd->offsets[0] != 0)
10049 return -EINVAL;
10050
c7d73f6a
DV		 10051 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10052 intel_fb->obj = obj;
10053
79e53945
JB		 10054 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10055 if (ret) {
10056 DRM_ERROR("framebuffer init failed %d\n", ret);
10057 return ret;
10058 }
10059
79e53945
JB		 10060 return 0;
10061}
10062
79e53945
JB		 10063static struct drm_framebuffer *
10064intel_user_framebuffer_create(struct drm_device *dev,
10065 struct drm_file *filp,
308e5bcb 10066 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10067{
05394f39 10068 struct drm_i915_gem_object *obj;
79e53945 10069
308e5bcb
JB		 10070 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10071 mode_cmd->handles[0]));
c8725226 10072 if (&obj->base == NULL)
cce13ff7 10073 return ERR_PTR(-ENOENT);
79e53945 10074
d2dff872 10075 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10076}
10077
79e53945 10078static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10079 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10080 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10081};
10082
e70236a8
JB		 10083/* Set up chip specific display functions */
10084static void intel_init_display(struct drm_device *dev)
10085{
10086 struct drm_i915_private *dev_priv = dev->dev_private;
10087
ee9300bb
DV		 10088 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10089 dev_priv->display.find_dpll = g4x_find_best_dpll;
10090 else if (IS_VALLEYVIEW(dev))
10091 dev_priv->display.find_dpll = vlv_find_best_dpll;
10092 else if (IS_PINEVIEW(dev))
10093 dev_priv->display.find_dpll = pnv_find_best_dpll;
10094 else
10095 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10096
affa9354 10097 if (HAS_DDI(dev)) {
0e8ffe1b 10098 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10099 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10100 dev_priv->display.crtc_enable = haswell_crtc_enable;
10101 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10102 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10103 dev_priv->display.update_plane = ironlake_update_plane;
10104 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10105 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10106 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10107 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10108 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10109 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10110 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10111 } else if (IS_VALLEYVIEW(dev)) {
10112 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10113 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10114 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10115 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10116 dev_priv->display.off = i9xx_crtc_off;
10117 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10118 } else {
0e8ffe1b 10119 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10120 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10121 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10122 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10123 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10124 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10125 }
e70236a8 10126
e70236a8 10127 /* Returns the core display clock speed */
25eb05fc
JB		 10128 if (IS_VALLEYVIEW(dev))
10129 dev_priv->display.get_display_clock_speed =
10130 valleyview_get_display_clock_speed;
10131 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10132 dev_priv->display.get_display_clock_speed =
10133 i945_get_display_clock_speed;
10134 else if (IS_I915G(dev))
10135 dev_priv->display.get_display_clock_speed =
10136 i915_get_display_clock_speed;
257a7ffc 10137 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10138 dev_priv->display.get_display_clock_speed =
10139 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10140 else if (IS_PINEVIEW(dev))
10141 dev_priv->display.get_display_clock_speed =
10142 pnv_get_display_clock_speed;
e70236a8
JB		 10143 else if (IS_I915GM(dev))
10144 dev_priv->display.get_display_clock_speed =
10145 i915gm_get_display_clock_speed;
10146 else if (IS_I865G(dev))
10147 dev_priv->display.get_display_clock_speed =
10148 i865_get_display_clock_speed;
f0f8a9ce 10149 else if (IS_I85X(dev))
e70236a8
JB		 10150 dev_priv->display.get_display_clock_speed =
10151 i855_get_display_clock_speed;
10152 else /* 852, 830 */
10153 dev_priv->display.get_display_clock_speed =
10154 i830_get_display_clock_speed;
10155
7f8a8569 10156 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10157 if (IS_GEN5(dev)) {
674cf967 10158 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10159 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10160 } else if (IS_GEN6(dev)) {
674cf967 10161 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10162 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10163 } else if (IS_IVYBRIDGE(dev)) {
10164 /* FIXME: detect B0+ stepping and use auto training */
10165 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10166 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10167 dev_priv->display.modeset_global_resources =
10168 ivb_modeset_global_resources;
c82e4d26
ED		 10169 } else if (IS_HASWELL(dev)) {
10170 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10171 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10172 dev_priv->display.modeset_global_resources =
10173 haswell_modeset_global_resources;
a0e63c22 10174 }
6067aaea 10175 } else if (IS_G4X(dev)) {
e0dac65e 10176 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10177 }
8c9f3aaf
JB		 10178
10179 /* Default just returns -ENODEV to indicate unsupported */
10180 dev_priv->display.queue_flip = intel_default_queue_flip;
10181
10182 switch (INTEL_INFO(dev)->gen) {
10183 case 2:
10184 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10185 break;
10186
10187 case 3:
10188 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10189 break;
10190
10191 case 4:
10192 case 5:
10193 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10194 break;
10195
10196 case 6:
10197 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10198 break;
7c9017e5
JB		 10199 case 7:
10200 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10201 break;
8c9f3aaf 10202 }
e70236a8
JB		 10203}
10204
b690e96c
JB		 10205/*
10206 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10207 * resume, or other times. This quirk makes sure that's the case for
10208 * affected systems.
10209 */
0206e353 10210static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10211{
10212 struct drm_i915_private *dev_priv = dev->dev_private;
10213
10214 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10215 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10216}
10217
435793df
KP		 10218/*
10219 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10220 */
10221static void quirk_ssc_force_disable(struct drm_device *dev)
10222{
10223 struct drm_i915_private *dev_priv = dev->dev_private;
10224 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10225 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10226}
10227
4dca20ef 10228/*
5a15ab5b
CE		 10229 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10230 * brightness value
4dca20ef
CE		 10231 */
10232static void quirk_invert_brightness(struct drm_device *dev)
10233{
10234 struct drm_i915_private *dev_priv = dev->dev_private;
10235 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10236 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10237}
10238
e85843be
KM		 10239/*
10240 * Some machines (Dell XPS13) suffer broken backlight controls if
10241 * BLM_PCH_PWM_ENABLE is set.
10242 */
10243static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10244{
10245 struct drm_i915_private *dev_priv = dev->dev_private;
10246 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10247 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10248}
10249
b690e96c
JB		 10250struct intel_quirk {
10251 int device;
10252 int subsystem_vendor;
10253 int subsystem_device;
10254 void (*hook)(struct drm_device *dev);
10255};
10256
5f85f176
EE		 10257/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10258struct intel_dmi_quirk {
10259 void (*hook)(struct drm_device *dev);
10260 const struct dmi_system_id (*dmi_id_list)[];
10261};
10262
10263static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10264{
10265 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10266 return 1;
10267}
10268
10269static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10270 {
10271 .dmi_id_list = &(const struct dmi_system_id[]) {
10272 {
10273 .callback = intel_dmi_reverse_brightness,
10274 .ident = "NCR Corporation",
10275 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10276 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10277 },
10278 },
10279 { } /* terminating entry */
10280 },
10281 .hook = quirk_invert_brightness,
10282 },
10283};
10284
c43b5634 10285static struct intel_quirk intel_quirks[] = {
b690e96c 10286 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10287 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10288
b690e96c
JB		 10289 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10290 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10291
b690e96c
JB		 10292 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10293 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10294
ccd0d36e 10295 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10296 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10297 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10298
10299 /* Lenovo U160 cannot use SSC on LVDS */
10300 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10301
10302 /* Sony Vaio Y cannot use SSC on LVDS */
10303 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10304
ee1452d7
JN		 10305 /*
10306 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10307 * seem to use inverted backlight PWM.
10308 */
10309 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10310
10311 /* Dell XPS13 HD Sandy Bridge */
10312 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10313 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10314 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10315};
10316
10317static void intel_init_quirks(struct drm_device *dev)
10318{
10319 struct pci_dev *d = dev->pdev;
10320 int i;
10321
10322 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10323 struct intel_quirk *q = &intel_quirks[i];
10324
10325 if (d->device == q->device &&
10326 (d->subsystem_vendor == q->subsystem_vendor ||
10327 q->subsystem_vendor == PCI_ANY_ID) &&
10328 (d->subsystem_device == q->subsystem_device ||
10329 q->subsystem_device == PCI_ANY_ID))
10330 q->hook(dev);
10331 }
5f85f176
EE		 10332 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10333 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10334 intel_dmi_quirks[i].hook(dev);
10335 }
b690e96c
JB		 10336}
10337
9cce37f4
JB		 10338/* Disable the VGA plane that we never use */
10339static void i915_disable_vga(struct drm_device *dev)
10340{
10341 struct drm_i915_private *dev_priv = dev->dev_private;
10342 u8 sr1;
766aa1c4 10343 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10344
10345 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10346 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10347 sr1 = inb(VGA_SR_DATA);
10348 outb(sr1 | 1<<5, VGA_SR_DATA);
10349 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10350 udelay(300);
10351
10352 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10353 POSTING_READ(vga_reg);
10354}
10355
6e1b4fda 10356static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10357{
10358 /* Enable VGA memory on Intel HD */
10359 if (HAS_PCH_SPLIT(dev)) {
10360 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10361 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10362 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10363 VGA_RSRC_LEGACY_MEM |
10364 VGA_RSRC_NORMAL_IO |
10365 VGA_RSRC_NORMAL_MEM);
10366 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10367 }
10368}
10369
6e1b4fda
VS		 10370void i915_disable_vga_mem(struct drm_device *dev)
10371{
10372 /* Disable VGA memory on Intel HD */
10373 if (HAS_PCH_SPLIT(dev)) {
10374 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10375 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10376 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10377 VGA_RSRC_NORMAL_IO |
10378 VGA_RSRC_NORMAL_MEM);
10379 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10380 }
10381}
10382
f817586c
DV		 10383void intel_modeset_init_hw(struct drm_device *dev)
10384{
f6071166
JB		 10385 struct drm_i915_private *dev_priv = dev->dev_private;
10386
a8f78b58
ED		 10387 intel_prepare_ddi(dev);
10388
f817586c
DV		 10389 intel_init_clock_gating(dev);
10390
f6071166
JB		 10391 /* Enable the CRI clock source so we can get at the display */
10392 if (IS_VALLEYVIEW(dev))
10393 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10394 DPLL_INTEGRATED_CRI_CLK_VLV);
10395
40e9cf64
JB		 10396 intel_init_dpio(dev);
10397
79f5b2c7 10398 mutex_lock(&dev->struct_mutex);
8090c6b9 10399 intel_enable_gt_powersave(dev);
79f5b2c7 10400 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10401}
10402
7d708ee4
ID		 10403void intel_modeset_suspend_hw(struct drm_device *dev)
10404{
10405 intel_suspend_hw(dev);
10406}
10407
79e53945
JB		 10408void intel_modeset_init(struct drm_device *dev)
10409{
652c393a 10410 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10411 int i, j, ret;
79e53945
JB		 10412
10413 drm_mode_config_init(dev);
10414
10415 dev->mode_config.min_width = 0;
10416 dev->mode_config.min_height = 0;
10417
019d96cb
DA		 10418 dev->mode_config.preferred_depth = 24;
10419 dev->mode_config.prefer_shadow = 1;
10420
e6ecefaa 10421 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10422
b690e96c
JB		 10423 intel_init_quirks(dev);
10424
1fa61106
ED		 10425 intel_init_pm(dev);
10426
e3c74757
BW		 10427 if (INTEL_INFO(dev)->num_pipes == 0)
10428 return;
10429
e70236a8
JB		 10430 intel_init_display(dev);
10431
a6c45cf0
CW		 10432 if (IS_GEN2(dev)) {
10433 dev->mode_config.max_width = 2048;
10434 dev->mode_config.max_height = 2048;
10435 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10436 dev->mode_config.max_width = 4096;
10437 dev->mode_config.max_height = 4096;
79e53945 10438 } else {
a6c45cf0
CW		 10439 dev->mode_config.max_width = 8192;
10440 dev->mode_config.max_height = 8192;
79e53945 10441 }
5d4545ae 10442 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10443
28c97730 10444 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10445 INTEL_INFO(dev)->num_pipes,
10446 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10447
08e2a7de 10448 for_each_pipe(i) {
79e53945 10449 intel_crtc_init(dev, i);
7f1f3851
JB		 10450 for (j = 0; j < dev_priv->num_plane; j++) {
10451 ret = intel_plane_init(dev, i, j);
10452 if (ret)
06da8da2
VS		 10453 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10454 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10455 }
79e53945
JB		 10456 }
10457
79f689aa 10458 intel_cpu_pll_init(dev);
e72f9fbf 10459 intel_shared_dpll_init(dev);
ee7b9f93 10460
9cce37f4
JB		 10461 /* Just disable it once at startup */
10462 i915_disable_vga(dev);
79e53945 10463 intel_setup_outputs(dev);
11be49eb
CW		 10464
10465 /* Just in case the BIOS is doing something questionable. */
10466 intel_disable_fbc(dev);
2c7111db
CW		 10467}
10468
24929352
DV		 10469static void
10470intel_connector_break_all_links(struct intel_connector *connector)
10471{
10472 connector->base.dpms = DRM_MODE_DPMS_OFF;
10473 connector->base.encoder = NULL;
10474 connector->encoder->connectors_active = false;
10475 connector->encoder->base.crtc = NULL;
10476}
10477
7fad798e
DV		 10478static void intel_enable_pipe_a(struct drm_device *dev)
10479{
10480 struct intel_connector *connector;
10481 struct drm_connector *crt = NULL;
10482 struct intel_load_detect_pipe load_detect_temp;
10483
10484 /* We can't just switch on the pipe A, we need to set things up with a
10485 * proper mode and output configuration. As a gross hack, enable pipe A
10486 * by enabling the load detect pipe once. */
10487 list_for_each_entry(connector,
10488 &dev->mode_config.connector_list,
10489 base.head) {
10490 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10491 crt = &connector->base;
10492 break;
10493 }
10494 }
10495
10496 if (!crt)
10497 return;
10498
10499 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10500 intel_release_load_detect_pipe(crt, &load_detect_temp);
10501
652c393a 10502
7fad798e
DV		 10503}
10504
fa555837
DV		 10505static bool
10506intel_check_plane_mapping(struct intel_crtc *crtc)
10507{
7eb552ae
BW		 10508 struct drm_device *dev = crtc->base.dev;
10509 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10510 u32 reg, val;
10511
7eb552ae 10512 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10513 return true;
10514
10515 reg = DSPCNTR(!crtc->plane);
10516 val = I915_READ(reg);
10517
10518 if ((val & DISPLAY_PLANE_ENABLE) &&
10519 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10520 return false;
10521
10522 return true;
10523}
10524
24929352
DV		 10525static void intel_sanitize_crtc(struct intel_crtc *crtc)
10526{
10527 struct drm_device *dev = crtc->base.dev;
10528 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10529 u32 reg;
24929352 10530
24929352 10531 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10532 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10533 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10534
10535 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10536 * disable the crtc (and hence change the state) if it is wrong. Note
10537 * that gen4+ has a fixed plane -> pipe mapping. */
10538 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10539 struct intel_connector *connector;
10540 bool plane;
10541
24929352
DV		 10542 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10543 crtc->base.base.id);
10544
10545 /* Pipe has the wrong plane attached and the plane is active.
10546 * Temporarily change the plane mapping and disable everything
10547 * ... */
10548 plane = crtc->plane;
10549 crtc->plane = !plane;
10550 dev_priv->display.crtc_disable(&crtc->base);
10551 crtc->plane = plane;
10552
10553 /* ... and break all links. */
10554 list_for_each_entry(connector, &dev->mode_config.connector_list,
10555 base.head) {
10556 if (connector->encoder->base.crtc != &crtc->base)
10557 continue;
10558
10559 intel_connector_break_all_links(connector);
10560 }
10561
10562 WARN_ON(crtc->active);
10563 crtc->base.enabled = false;
10564 }
24929352 10565
7fad798e
DV		 10566 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10567 crtc->pipe == PIPE_A && !crtc->active) {
10568 /* BIOS forgot to enable pipe A, this mostly happens after
10569 * resume. Force-enable the pipe to fix this, the update_dpms
10570 * call below we restore the pipe to the right state, but leave
10571 * the required bits on. */
10572 intel_enable_pipe_a(dev);
10573 }
10574
24929352
DV		 10575 /* Adjust the state of the output pipe according to whether we
10576 * have active connectors/encoders. */
10577 intel_crtc_update_dpms(&crtc->base);
10578
10579 if (crtc->active != crtc->base.enabled) {
10580 struct intel_encoder *encoder;
10581
10582 /* This can happen either due to bugs in the get_hw_state
10583 * functions or because the pipe is force-enabled due to the
10584 * pipe A quirk. */
10585 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10586 crtc->base.base.id,
10587 crtc->base.enabled ? "enabled" : "disabled",
10588 crtc->active ? "enabled" : "disabled");
10589
10590 crtc->base.enabled = crtc->active;
10591
10592 /* Because we only establish the connector -> encoder ->
10593 * crtc links if something is active, this means the
10594 * crtc is now deactivated. Break the links. connector
10595 * -> encoder links are only establish when things are
10596 * actually up, hence no need to break them. */
10597 WARN_ON(crtc->active);
10598
10599 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10600 WARN_ON(encoder->connectors_active);
10601 encoder->base.crtc = NULL;
10602 }
10603 }
10604}
10605
10606static void intel_sanitize_encoder(struct intel_encoder *encoder)
10607{
10608 struct intel_connector *connector;
10609 struct drm_device *dev = encoder->base.dev;
10610
10611 /* We need to check both for a crtc link (meaning that the
10612 * encoder is active and trying to read from a pipe) and the
10613 * pipe itself being active. */
10614 bool has_active_crtc = encoder->base.crtc &&
10615 to_intel_crtc(encoder->base.crtc)->active;
10616
10617 if (encoder->connectors_active && !has_active_crtc) {
10618 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10619 encoder->base.base.id,
10620 drm_get_encoder_name(&encoder->base));
10621
10622 /* Connector is active, but has no active pipe. This is
10623 * fallout from our resume register restoring. Disable
10624 * the encoder manually again. */
10625 if (encoder->base.crtc) {
10626 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10627 encoder->base.base.id,
10628 drm_get_encoder_name(&encoder->base));
10629 encoder->disable(encoder);
10630 }
10631
10632 /* Inconsistent output/port/pipe state happens presumably due to
10633 * a bug in one of the get_hw_state functions. Or someplace else
10634 * in our code, like the register restore mess on resume. Clamp
10635 * things to off as a safer default. */
10636 list_for_each_entry(connector,
10637 &dev->mode_config.connector_list,
10638 base.head) {
10639 if (connector->encoder != encoder)
10640 continue;
10641
10642 intel_connector_break_all_links(connector);
10643 }
10644 }
10645 /* Enabled encoders without active connectors will be fixed in
10646 * the crtc fixup. */
10647}
10648
44cec740 10649void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10650{
10651 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10652 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10653
8dc8a27c
PZ		 10654 /* This function can be called both from intel_modeset_setup_hw_state or
10655 * at a very early point in our resume sequence, where the power well
10656 * structures are not yet restored. Since this function is at a very
10657 * paranoid "someone might have enabled VGA while we were not looking"
10658 * level, just check if the power well is enabled instead of trying to
10659 * follow the "don't touch the power well if we don't need it" policy
10660 * the rest of the driver uses. */
10661 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10662 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10663 return;
10664
0fde901f
KM		 10665 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10666 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10667 i915_disable_vga(dev);
6e1b4fda 10668 i915_disable_vga_mem(dev);
0fde901f
KM		 10669 }
10670}
10671
30e984df 10672static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10673{
10674 struct drm_i915_private *dev_priv = dev->dev_private;
10675 enum pipe pipe;
24929352
DV		 10676 struct intel_crtc *crtc;
10677 struct intel_encoder *encoder;
10678 struct intel_connector *connector;
5358901f 10679 int i;
24929352 10680
0e8ffe1b
DV		 10681 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10682 base.head) {
88adfff1 10683 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10684
0e8ffe1b
DV		 10685 crtc->active = dev_priv->display.get_pipe_config(crtc,
10686 &crtc->config);
24929352
DV		 10687
10688 crtc->base.enabled = crtc->active;
10689
10690 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10691 crtc->base.base.id,
10692 crtc->active ? "enabled" : "disabled");
10693 }
10694
5358901f 10695 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10696 if (HAS_DDI(dev))
6441ab5f
PZ		 10697 intel_ddi_setup_hw_pll_state(dev);
10698
5358901f
DV		 10699 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10700 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10701
10702 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10703 pll->active = 0;
10704 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10705 base.head) {
10706 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10707 pll->active++;
10708 }
10709 pll->refcount = pll->active;
10710
35c95375
DV		 10711 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10712 pll->name, pll->refcount, pll->on);
5358901f
DV		 10713 }
10714
24929352
DV		 10715 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10716 base.head) {
10717 pipe = 0;
10718
10719 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10720 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10721 encoder->base.crtc = &crtc->base;
510d5f2f 10722 if (encoder->get_config)
045ac3b5 10723 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10724 } else {
10725 encoder->base.crtc = NULL;
10726 }
10727
10728 encoder->connectors_active = false;
10729 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10730 encoder->base.base.id,
10731 drm_get_encoder_name(&encoder->base),
10732 encoder->base.crtc ? "enabled" : "disabled",
10733 pipe);
10734 }
10735
10736 list_for_each_entry(connector, &dev->mode_config.connector_list,
10737 base.head) {
10738 if (connector->get_hw_state(connector)) {
10739 connector->base.dpms = DRM_MODE_DPMS_ON;
10740 connector->encoder->connectors_active = true;
10741 connector->base.encoder = &connector->encoder->base;
10742 } else {
10743 connector->base.dpms = DRM_MODE_DPMS_OFF;
10744 connector->base.encoder = NULL;
10745 }
10746 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10747 connector->base.base.id,
10748 drm_get_connector_name(&connector->base),
10749 connector->base.encoder ? "enabled" : "disabled");
10750 }
30e984df
DV		 10751}
10752
10753/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10754 * and i915 state tracking structures. */
10755void intel_modeset_setup_hw_state(struct drm_device *dev,
10756 bool force_restore)
10757{
10758 struct drm_i915_private *dev_priv = dev->dev_private;
10759 enum pipe pipe;
30e984df
DV		 10760 struct intel_crtc *crtc;
10761 struct intel_encoder *encoder;
35c95375 10762 int i;
30e984df
DV		 10763
10764 intel_modeset_readout_hw_state(dev);
24929352 10765
babea61d
JB		 10766 /*
10767 * Now that we have the config, copy it to each CRTC struct
10768 * Note that this could go away if we move to using crtc_config
10769 * checking everywhere.
10770 */
10771 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10772 base.head) {
10773 if (crtc->active && i915_fastboot) {
10774 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10775
10776 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10777 crtc->base.base.id);
10778 drm_mode_debug_printmodeline(&crtc->base.mode);
10779 }
10780 }
10781
24929352
DV		 10782 /* HW state is read out, now we need to sanitize this mess. */
10783 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10784 base.head) {
10785 intel_sanitize_encoder(encoder);
10786 }
10787
10788 for_each_pipe(pipe) {
10789 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10790 intel_sanitize_crtc(crtc);
c0b03411 10791 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10792 }
9a935856 10793
35c95375
DV		 10794 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10795 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10796
10797 if (!pll->on || pll->active)
10798 continue;
10799
10800 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10801
10802 pll->disable(dev_priv, pll);
10803 pll->on = false;
10804 }
10805
45e2b5f6 10806 if (force_restore) {
7d0bc1ea
VS		 10807 i915_redisable_vga(dev);
10808
f30da187
DV		 10809 /*
10810 * We need to use raw interfaces for restoring state to avoid
10811 * checking (bogus) intermediate states.
10812 */
45e2b5f6 10813 for_each_pipe(pipe) {
b5644d05
JB		 10814 struct drm_crtc *crtc =
10815 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10816
10817 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10818 crtc->fb);
45e2b5f6
DV		 10819 }
10820 } else {
10821 intel_modeset_update_staged_output_state(dev);
10822 }
8af6cf88
DV		 10823
10824 intel_modeset_check_state(dev);
2e938892
DV		 10825
10826 drm_mode_config_reset(dev);
2c7111db
CW		 10827}
10828
10829void intel_modeset_gem_init(struct drm_device *dev)
10830{
1833b134 10831 intel_modeset_init_hw(dev);
02e792fb
DV		 10832
10833 intel_setup_overlay(dev);
24929352 10834
45e2b5f6 10835 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10836}
10837
10838void intel_modeset_cleanup(struct drm_device *dev)
10839{
652c393a
JB		 10840 struct drm_i915_private *dev_priv = dev->dev_private;
10841 struct drm_crtc *crtc;
d9255d57 10842 struct drm_connector *connector;
652c393a 10843
fd0c0642
DV		 10844 /*
10845 * Interrupts and polling as the first thing to avoid creating havoc.
10846 * Too much stuff here (turning of rps, connectors, ...) would
10847 * experience fancy races otherwise.
10848 */
10849 drm_irq_uninstall(dev);
10850 cancel_work_sync(&dev_priv->hotplug_work);
10851 /*
10852 * Due to the hpd irq storm handling the hotplug work can re-arm the
10853 * poll handlers. Hence disable polling after hpd handling is shut down.
10854 */
f87ea761 10855 drm_kms_helper_poll_fini(dev);
fd0c0642 10856
652c393a
JB		 10857 mutex_lock(&dev->struct_mutex);
10858
723bfd70
JB		 10859 intel_unregister_dsm_handler();
10860
652c393a
JB		 10861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10862 /* Skip inactive CRTCs */
10863 if (!crtc->fb)
10864 continue;
10865
3dec0095 10866 intel_increase_pllclock(crtc);
652c393a
JB		 10867 }
10868
973d04f9 10869 intel_disable_fbc(dev);
e70236a8 10870
6e1b4fda 10871 i915_enable_vga_mem(dev);
81b5c7bc 10872
8090c6b9 10873 intel_disable_gt_powersave(dev);
0cdab21f 10874
930ebb46
DV		 10875 ironlake_teardown_rc6(dev);
10876
69341a5e
KH		 10877 mutex_unlock(&dev->struct_mutex);
10878
1630fe75
CW		 10879 /* flush any delayed tasks or pending work */
10880 flush_scheduled_work();
10881
dc652f90
JN		 10882 /* destroy backlight, if any, before the connectors */
10883 intel_panel_destroy_backlight(dev);
10884
d9255d57
PZ		 10885 /* destroy the sysfs files before encoders/connectors */
10886 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10887 drm_sysfs_connector_remove(connector);
10888
79e53945 10889 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10890
10891 intel_cleanup_overlay(dev);
79e53945
JB		 10892}
10893
f1c79df3
ZW		 10894/*
10895 * Return which encoder is currently attached for connector.
10896 */
df0e9248 10897struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10898{
df0e9248
CW		 10899 return &intel_attached_encoder(connector)->base;
10900}
f1c79df3 10901
df0e9248
CW		 10902void intel_connector_attach_encoder(struct intel_connector *connector,
10903 struct intel_encoder *encoder)
10904{
10905 connector->encoder = encoder;
10906 drm_mode_connector_attach_encoder(&connector->base,
10907 &encoder->base);
79e53945 10908}
28d52043
DA		 10909
10910/*
10911 * set vga decode state - true == enable VGA decode
10912 */
10913int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10914{
10915 struct drm_i915_private *dev_priv = dev->dev_private;
10916 u16 gmch_ctrl;
10917
10918 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10919 if (state)
10920 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10921 else
10922 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10923 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10924 return 0;
10925}
c4a1d9e4 10926
c4a1d9e4 10927struct intel_display_error_state {
ff57f1b0
PZ		 10928
10929 u32 power_well_driver;
10930
63b66e5b
CW		 10931 int num_transcoders;
10932
c4a1d9e4
CW		 10933 struct intel_cursor_error_state {
10934 u32 control;
10935 u32 position;
10936 u32 base;
10937 u32 size;
52331309 10938 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10939
10940 struct intel_pipe_error_state {
c4a1d9e4 10941 u32 source;
52331309 10942 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10943
10944 struct intel_plane_error_state {
10945 u32 control;
10946 u32 stride;
10947 u32 size;
10948 u32 pos;
10949 u32 addr;
10950 u32 surface;
10951 u32 tile_offset;
52331309 10952 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10953
10954 struct intel_transcoder_error_state {
10955 enum transcoder cpu_transcoder;
10956
10957 u32 conf;
10958
10959 u32 htotal;
10960 u32 hblank;
10961 u32 hsync;
10962 u32 vtotal;
10963 u32 vblank;
10964 u32 vsync;
10965 } transcoder[4];
c4a1d9e4
CW		 10966};
10967
10968struct intel_display_error_state *
10969intel_display_capture_error_state(struct drm_device *dev)
10970{
0206e353 10971 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10972 struct intel_display_error_state *error;
63b66e5b
CW		 10973 int transcoders[] = {
10974 TRANSCODER_A,
10975 TRANSCODER_B,
10976 TRANSCODER_C,
10977 TRANSCODER_EDP,
10978 };
c4a1d9e4
CW		 10979 int i;
10980
63b66e5b
CW		 10981 if (INTEL_INFO(dev)->num_pipes == 0)
10982 return NULL;
10983
c4a1d9e4
CW		 10984 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10985 if (error == NULL)
10986 return NULL;
10987
ff57f1b0
PZ		 10988 if (HAS_POWER_WELL(dev))
10989 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10990
52331309 10991 for_each_pipe(i) {
a18c4c3d
PZ		 10992 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10993 error->cursor[i].control = I915_READ(CURCNTR(i));
10994 error->cursor[i].position = I915_READ(CURPOS(i));
10995 error->cursor[i].base = I915_READ(CURBASE(i));
10996 } else {
10997 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10998 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10999 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11000 }
c4a1d9e4
CW		 11001
11002 error->plane[i].control = I915_READ(DSPCNTR(i));
11003 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11004 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11005 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11006 error->plane[i].pos = I915_READ(DSPPOS(i));
11007 }
ca291363
PZ		 11008 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11009 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11010 if (INTEL_INFO(dev)->gen >= 4) {
11011 error->plane[i].surface = I915_READ(DSPSURF(i));
11012 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11013 }
11014
c4a1d9e4 11015 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11016 }
11017
11018 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11019 if (HAS_DDI(dev_priv->dev))
11020 error->num_transcoders++; /* Account for eDP. */
11021
11022 for (i = 0; i < error->num_transcoders; i++) {
11023 enum transcoder cpu_transcoder = transcoders[i];
11024
11025 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11026
11027 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11028 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11029 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11030 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11031 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11032 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11033 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11034 }
11035
12d217c7
PZ		 11036 /* In the code above we read the registers without checking if the power
11037 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11038 * prevent the next I915_WRITE from detecting it and printing an error
11039 * message. */
907b28c5 11040 intel_uncore_clear_errors(dev);
12d217c7 11041
c4a1d9e4
CW		 11042 return error;
11043}
11044
edc3d884
MK		 11045#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11046
c4a1d9e4 11047void
edc3d884 11048intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11049 struct drm_device *dev,
11050 struct intel_display_error_state *error)
11051{
11052 int i;
11053
63b66e5b
CW		 11054 if (!error)
11055 return;
11056
edc3d884 11057 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11058 if (HAS_POWER_WELL(dev))
edc3d884 11059 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11060 error->power_well_driver);
52331309 11061 for_each_pipe(i) {
edc3d884 11062 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11063 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11064
11065 err_printf(m, "Plane [%d]:\n", i);
11066 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11067 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11068 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11069 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11070 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11071 }
4b71a570 11072 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11073 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11074 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11075 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11076 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11077 }
11078
edc3d884
MK		 11079 err_printf(m, "Cursor [%d]:\n", i);
11080 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11081 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11082 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11083 }
63b66e5b
CW		 11084
11085 for (i = 0; i < error->num_transcoders; i++) {
11086 err_printf(m, " CPU transcoder: %c\n",
11087 transcoder_name(error->transcoder[i].cpu_transcoder));
11088 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11089 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11090 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11091 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11092 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11093 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11094 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11095 }
c4a1d9e4 11096}
ubuntu-bionic-kernel mirror