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drm/i915: don't force matching p1 for g4x/ilk+ reduced pll settings
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
1b894b59
CW		 688
689 this_err = abs(clock.dot - target);
d4906093
ML		 690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
2c07245f
ZW		 700 return found;
701}
702
a0c4da24
JB		 703static bool
704intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707{
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
af447bd3 714 flag = 0;
a0c4da24
JB		 715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770}
a4fc5ed6 771
a5c961d1
PZ		 772enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774{
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
3b117c8f 778 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 779}
780
a928d536
PZ		 781static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790}
791
9d0498a2
JB		 792/**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 801{
9d0498a2 802 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 803 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 804
a928d536
PZ		 805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
300387c0
CW		 810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
9d0498a2 826 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
9d0498a2
JB		 830 DRM_DEBUG_KMS("vblank wait timed out\n");
831}
832
ab7ad7f6
KP		 833/*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
ab7ad7f6
KP		 842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
58e10eb9 848 *
9d0498a2 849 */
58e10eb9 850void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
ab7ad7f6
KP		 855
856 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 857 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 858
859 /* Wait for the Pipe State to go off */
58e10eb9
CW		 860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 } else {
837ba00f 864 u32 last_line, line_mask;
58e10eb9 865 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
837ba00f
PZ		 868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
ab7ad7f6
KP		 873 /* Wait for the display line to settle */
874 do {
837ba00f 875 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 876 mdelay(5);
837ba00f 877 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
284637d9 880 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 881 }
79e53945
JB		 882}
883
b0ea7d37
DL		 884/*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893{
894 u32 bit;
895
c36346e3
DL		 896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
b0ea7d37
DL		 924 }
925
926 return I915_READ(SDEISR) & bit;
927}
928
b24e7179
JB		 929static const char *state_string(bool enabled)
930{
931 return enabled ? "on" : "off";
932}
933
934/* Only for pre-ILK configs */
935static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937{
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948}
949#define assert_pll_enabled(d, p) assert_pll(d, p, true)
950#define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
040484af
JB		 952/* For ILK+ */
953static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
040484af 957{
040484af
JB		 958 u32 val;
959 bool cur_state;
960
9d82aa17
ED		 961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
92b27b08
CW		 966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 968 return;
ee7b9f93 969
92b27b08
CW		 970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
4bb6f1f3 987 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
4bb6f1f3 990 pipe_name(crtc->pipe),
92b27b08
CW		 991 val);
992 }
d3ccbe86 993 }
040484af 994}
92b27b08
CW		 995#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 997
998static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
ad80a810
PZ		 1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
040484af 1006
affa9354
PZ		 1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
ad80a810 1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1010 val = I915_READ(reg);
ad80a810 1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
040484af
JB		 1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020}
1021#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026{
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
d63fa0dc
PZ		 1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
bf507ef7 1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1052 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1053 return;
1054
040484af
JB		 1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058}
1059
1060static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069}
1070
ea0760cf
JB		 1071static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073{
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
0de3b485 1077 bool locked = true;
ea0760cf
JB		 1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1097 pipe_name(pipe));
ea0760cf
JB		 1098}
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
15d199ea
PZ		 1113 if (!intel_using_power_well(dev_priv->dev) &&
1114 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
19ec1358 1152 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
19ec1358 1159 return;
28c05794 1160 }
19ec1358 1161
b24e7179
JB		 1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1171 }
1172}
1173
19332d7a
JB		 1174static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176{
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
06da8da2
VS		 1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1190 }
1191}
1192
92f2584a
JB		 1193static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194{
1195 u32 val;
1196 bool enabled;
1197
9d82aa17
ED		 1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
92f2584a
JB		 1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207}
1208
1209static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
1216 reg = TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
92f2584a
JB		 1222}
1223
4e634389
KP		 1224static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1226{
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240}
1241
1519b995
KP		 1242static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
dc0fa718 1245 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1250 return false;
1251 } else {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272}
1273
1274static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276{
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
291906f1 1289static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1290 enum pipe pipe, int reg, u32 port_sel)
291906f1 1291{
47a05eca 1292 u32 val = I915_READ(reg);
4e634389 1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 reg, pipe_name(pipe));
de9a35ab 1296
75c5da27
DV		 1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
de9a35ab 1299 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1300}
1301
1302static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304{
47a05eca 1305 u32 val = I915_READ(reg);
b70ad586 1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
dc0fa718 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1311 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1312 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
1318 int reg;
1319 u32 val;
291906f1 1320
f0575e92
KP		 1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1
JB		 1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
b70ad586 1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1335 pipe_name(pipe));
291906f1 1336
e2debe91
PZ		 1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1340}
1341
63d7bbe9
JB		 1342/**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
7434a255
TR		 1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1354 */
1355static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356{
1357 int reg;
1358 u32 val;
1359
58c6eaa2
DV		 1360 assert_pipe_disabled(dev_priv, pipe);
1361
63d7bbe9 1362 /* No really, not for ILK+ */
a0c4da24 1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
a416edef
ED		 1413/* SBI access */
1414static void
988d6ee8
PZ		 1415intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
a416edef 1417{
988d6ee8 1418 u32 tmp;
a416edef 1419
09153000 1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1421
39fb50f6 1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1425 return;
a416edef
ED		 1426 }
1427
988d6ee8
PZ		 1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1436
39fb50f6 1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1440 return;
a416edef 1441 }
a416edef
ED		 1442}
1443
1444static u32
988d6ee8
PZ		 1445intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
a416edef 1447{
39fb50f6 1448 u32 value = 0;
09153000 1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1450
39fb50f6 1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1454 return 0;
a416edef
ED		 1455 }
1456
988d6ee8
PZ		 1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1464
39fb50f6 1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1468 return 0;
a416edef
ED		 1469 }
1470
09153000 1471 return I915_READ(SBI_DATA);
a416edef
ED		 1472}
1473
89b667f8
JB		 1474void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475{
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486}
1487
92f2584a 1488/**
b6b4e185 1489 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
b6b4e185 1496static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1497{
ee7b9f93 1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1499 struct intel_pch_pll *pll;
92f2584a
JB		 1500 int reg;
1501 u32 val;
1502
48da64a8 1503 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1504 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
ee7b9f93
JB		 1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
92f2584a
JB		 1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
ee7b9f93 1519 if (pll->active++ && pll->on) {
92b27b08 1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = true;
92f2584a
JB		 1534}
1535
ee7b9f93 1536static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1537{
ee7b9f93
JB		 1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1540 int reg;
ee7b9f93 1541 u32 val;
4c609cb8 1542
92f2584a
JB		 1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1545 if (pll == NULL)
1546 return;
92f2584a 1547
48da64a8
CW		 1548 if (WARN_ON(pll->refcount == 0))
1549 return;
7a419866 1550
ee7b9f93
JB		 1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
7a419866 1554
48da64a8 1555 if (WARN_ON(pll->active == 0)) {
92b27b08 1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1557 return;
1558 }
1559
ee7b9f93 1560 if (--pll->active) {
92b27b08 1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1562 return;
ee7b9f93
JB		 1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1569
ee7b9f93 1570 reg = pll->pll_reg;
92f2584a
JB		 1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
ee7b9f93
JB		 1576
1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1585 uint32_t reg, val, pipeconf_val;
040484af
JB		 1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
040484af
JB		 1608 reg = TRANSCONF(pipe);
1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
25f3ef11 1662 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1663 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
040484af
JB		 1680 reg = TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
8a52fd9f 1701 val = I915_READ(_TRANSACONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
8a52fd9f 1703 I915_WRITE(_TRANSACONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1705 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af
JB		 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2
DV		 1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
681e5811 1740 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
b24e7179
JB		 1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
cc391bbb 1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
040484af
JB		 1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
b24e7179 1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
1771/**
309cfea8 1772 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
b24e7179
JB		 1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
5eddb70b 2050 I915_WRITE(reg, dspcntr);
81255565 2051
e506a0c6 2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2053
c2c75131
DV		 2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
bc752862
CW		 2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
c2c75131
DV		 2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
e506a0c6 2061 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2062 }
e506a0c6
DV		 2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2067 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2072 } else
e506a0c6 2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2074 POSTING_READ(reg);
81255565 2075
17638cd6
JB		 2076 return 0;
2077}
2078
2079static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
17638cd6
JB		 2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
27f8227b 2095 case 2:
17638cd6
JB		 2096 break;
2097 default:
84f44ce7 2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
17638cd6
JB		 2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
17638cd6
JB		 2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
e506a0c6 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2147 intel_crtc->dspaddr_offset =
bc752862
CW		 2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
c2c75131 2151 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2152
e506a0c6
DV		 2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
17638cd6
JB		 2164 POSTING_READ(reg);
2165
2166 return 0;
2167}
2168
2169/* Assume fb object is pinned & idle & fenced and just update base pointers */
2170static int
2171intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2176
6b8e6ed0
CW		 2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
3dec0095 2179 intel_increase_pllclock(crtc);
81255565 2180
6b8e6ed0 2181 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2182}
2183
96a02917
VS		 2184void intel_display_handle_reset(struct drm_device *dev)
2185{
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220}
2221
14667a4b
CW		 2222static int
2223intel_finish_fb(struct drm_framebuffer *old_fb)
2224{
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
14667a4b
CW		 2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243}
2244
198598d0
VS		 2245static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246{
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270}
2271
5c3b82e2 2272static int
3c4fdcfb 2273intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2274 struct drm_framebuffer *fb)
79e53945
JB		 2275{
2276 struct drm_device *dev = crtc->dev;
6b8e6ed0 2277 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2279 struct drm_framebuffer *old_fb;
5c3b82e2 2280 int ret;
79e53945
JB		 2281
2282 /* no fb bound */
94352cf9 2283 if (!fb) {
a5071c2f 2284 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2285 return 0;
2286 }
2287
7eb552ae 2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2292 return -EINVAL;
79e53945
JB		 2293 }
2294
5c3b82e2 2295 mutex_lock(&dev->struct_mutex);
265db958 2296 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2297 to_intel_framebuffer(fb)->obj,
919926ae 2298 NULL);
5c3b82e2
CW		 2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2302 return ret;
2303 }
79e53945 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
01a415fd
DV		 2372static void ivb_modeset_global_resources(struct drm_device *dev)
2373{
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *pipe_B_crtc =
2376 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2377 struct intel_crtc *pipe_C_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2379 uint32_t temp;
2380
2381 /* When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. XXX: This misses the case where a pipe is not using
2383 * any pch resources and so doesn't need any fdi lanes. */
2384 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2386 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2387
2388 temp = I915_READ(SOUTH_CHICKEN1);
2389 temp &= ~FDI_BC_BIFURCATION_SELECT;
2390 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391 I915_WRITE(SOUTH_CHICKEN1, temp);
2392 }
2393}
2394
8db9d77b
ZW		 2395/* The FDI link training functions for ILK/Ibexpeak. */
2396static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2397{
2398 struct drm_device *dev = crtc->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401 int pipe = intel_crtc->pipe;
0fc932b8 2402 int plane = intel_crtc->plane;
5eddb70b 2403 u32 reg, temp, tries;
8db9d77b 2404
0fc932b8
JB		 2405 /* FDI needs bits from pipe & plane first */
2406 assert_pipe_enabled(dev_priv, pipe);
2407 assert_plane_enabled(dev_priv, plane);
2408
e1a44743
AJ		 2409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2410 for train result */
5eddb70b
CW		 2411 reg = FDI_RX_IMR(pipe);
2412 temp = I915_READ(reg);
e1a44743
AJ		 2413 temp &= ~FDI_RX_SYMBOL_LOCK;
2414 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2415 I915_WRITE(reg, temp);
2416 I915_READ(reg);
e1a44743
AJ		 2417 udelay(150);
2418
8db9d77b 2419 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2420 reg = FDI_TX_CTL(pipe);
2421 temp = I915_READ(reg);
77ffb597
AJ		 2422 temp &= ~(7 << 19);
2423 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2426 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2427
5eddb70b
CW		 2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2432 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2433
2434 POSTING_READ(reg);
8db9d77b
ZW		 2435 udelay(150);
2436
5b2adf89 2437 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2439 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2440 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2441
5eddb70b 2442 reg = FDI_RX_IIR(pipe);
e1a44743 2443 for (tries = 0; tries < 5; tries++) {
5eddb70b 2444 temp = I915_READ(reg);
8db9d77b
ZW		 2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446
2447 if ((temp & FDI_RX_BIT_LOCK)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2449 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2450 break;
2451 }
8db9d77b 2452 }
e1a44743 2453 if (tries == 5)
5eddb70b 2454 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2455
2456 /* Train 2 */
5eddb70b
CW		 2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
8db9d77b
ZW		 2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2461 I915_WRITE(reg, temp);
8db9d77b 2462
5eddb70b
CW		 2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
8db9d77b
ZW		 2465 temp &= ~FDI_LINK_TRAIN_NONE;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2467 I915_WRITE(reg, temp);
8db9d77b 2468
5eddb70b
CW		 2469 POSTING_READ(reg);
2470 udelay(150);
8db9d77b 2471
5eddb70b 2472 reg = FDI_RX_IIR(pipe);
e1a44743 2473 for (tries = 0; tries < 5; tries++) {
5eddb70b 2474 temp = I915_READ(reg);
8db9d77b
ZW		 2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476
2477 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2478 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2480 break;
2481 }
8db9d77b 2482 }
e1a44743 2483 if (tries == 5)
5eddb70b 2484 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2485
2486 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2487
8db9d77b
ZW		 2488}
2489
0206e353 2490static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2495};
2496
2497/* The FDI link training functions for SNB/Cougarpoint. */
2498static void gen6_fdi_link_train(struct drm_crtc *crtc)
2499{
2500 struct drm_device *dev = crtc->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 int pipe = intel_crtc->pipe;
fa37d39e 2504 u32 reg, temp, i, retry;
8db9d77b 2505
e1a44743
AJ		 2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507 for train result */
5eddb70b
CW		 2508 reg = FDI_RX_IMR(pipe);
2509 temp = I915_READ(reg);
e1a44743
AJ		 2510 temp &= ~FDI_RX_SYMBOL_LOCK;
2511 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597
AJ		 2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 /* SNB-B */
2526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2527 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2528
d74cf324
DV		 2529 I915_WRITE(FDI_RX_MISC(pipe),
2530 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2531
5eddb70b
CW		 2532 reg = FDI_RX_CTL(pipe);
2533 temp = I915_READ(reg);
8db9d77b
ZW		 2534 if (HAS_PCH_CPT(dev)) {
2535 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2537 } else {
2538 temp &= ~FDI_LINK_TRAIN_NONE;
2539 temp |= FDI_LINK_TRAIN_PATTERN_1;
2540 }
5eddb70b
CW		 2541 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2542
2543 POSTING_READ(reg);
8db9d77b
ZW		 2544 udelay(150);
2545
0206e353 2546 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2551 I915_WRITE(reg, temp);
2552
2553 POSTING_READ(reg);
8db9d77b
ZW		 2554 udelay(500);
2555
fa37d39e
SP		 2556 for (retry = 0; retry < 5; retry++) {
2557 reg = FDI_RX_IIR(pipe);
2558 temp = I915_READ(reg);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2560 if (temp & FDI_RX_BIT_LOCK) {
2561 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2563 break;
2564 }
2565 udelay(50);
8db9d77b 2566 }
fa37d39e
SP		 2567 if (retry < 5)
2568 break;
8db9d77b
ZW		 2569 }
2570 if (i == 4)
5eddb70b 2571 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2572
2573 /* Train 2 */
5eddb70b
CW		 2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578 if (IS_GEN6(dev)) {
2579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580 /* SNB-B */
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582 }
5eddb70b 2583 I915_WRITE(reg, temp);
8db9d77b 2584
5eddb70b
CW		 2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
8db9d77b
ZW		 2587 if (HAS_PCH_CPT(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2590 } else {
2591 temp &= ~FDI_LINK_TRAIN_NONE;
2592 temp |= FDI_LINK_TRAIN_PATTERN_2;
2593 }
5eddb70b
CW		 2594 I915_WRITE(reg, temp);
2595
2596 POSTING_READ(reg);
8db9d77b
ZW		 2597 udelay(150);
2598
0206e353 2599 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
8db9d77b
ZW		 2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
8db9d77b
ZW		 2607 udelay(500);
2608
fa37d39e
SP		 2609 for (retry = 0; retry < 5; retry++) {
2610 reg = FDI_RX_IIR(pipe);
2611 temp = I915_READ(reg);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_SYMBOL_LOCK) {
2614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2616 break;
2617 }
2618 udelay(50);
8db9d77b 2619 }
fa37d39e
SP		 2620 if (retry < 5)
2621 break;
8db9d77b
ZW		 2622 }
2623 if (i == 4)
5eddb70b 2624 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2625
2626 DRM_DEBUG_KMS("FDI train done.\n");
2627}
2628
357555c0
JB		 2629/* Manual link training for Ivy Bridge A0 parts */
2630static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2631{
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 int pipe = intel_crtc->pipe;
2636 u32 reg, temp, i;
2637
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639 for train result */
2640 reg = FDI_RX_IMR(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_RX_SYMBOL_LOCK;
2643 temp &= ~FDI_RX_BIT_LOCK;
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(150);
2648
01a415fd
DV		 2649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650 I915_READ(FDI_RX_IIR(pipe)));
2651
357555c0
JB		 2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~(7 << 19);
2656 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2661 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2663
d74cf324
DV		 2664 I915_WRITE(FDI_RX_MISC(pipe),
2665 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2666
357555c0
JB		 2667 reg = FDI_RX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_AUTO;
2670 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2672 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2674
2675 POSTING_READ(reg);
2676 udelay(150);
2677
0206e353 2678 for (i = 0; i < 4; i++) {
357555c0
JB		 2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2684
2685 POSTING_READ(reg);
2686 udelay(500);
2687
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2696 break;
2697 }
2698 }
2699 if (i == 4)
2700 DRM_ERROR("FDI train 1 fail!\n");
2701
2702 /* Train 2 */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2716
2717 POSTING_READ(reg);
2718 udelay(150);
2719
0206e353 2720 for (i = 0; i < 4; i++) {
357555c0
JB		 2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2726
2727 POSTING_READ(reg);
2728 udelay(500);
2729
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2733
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2736 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2737 break;
2738 }
2739 }
2740 if (i == 4)
2741 DRM_ERROR("FDI train 2 fail!\n");
2742
2743 DRM_DEBUG_KMS("FDI train done.\n");
2744}
2745
88cefb6c 2746static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2747{
88cefb6c 2748 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2749 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2750 int pipe = intel_crtc->pipe;
5eddb70b 2751 u32 reg, temp;
79e53945 2752
c64e311e 2753
c98e9dcf 2754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2758 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2759 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2760 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
2765 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp | FDI_PCDCLK);
2768
2769 POSTING_READ(reg);
c98e9dcf
JB		 2770 udelay(200);
2771
20749730
PZ		 2772 /* Enable CPU FDI TX PLL, always on for Ironlake */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2776 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2777
20749730
PZ		 2778 POSTING_READ(reg);
2779 udelay(100);
6be4a607 2780 }
0e23b99d
JB		 2781}
2782
88cefb6c
DV		 2783static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2784{
2785 struct drm_device *dev = intel_crtc->base.dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 int pipe = intel_crtc->pipe;
2788 u32 reg, temp;
2789
2790 /* Switch from PCDclk to Rawclk */
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2794
2795 /* Disable CPU FDI TX PLL */
2796 reg = FDI_TX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2799
2800 POSTING_READ(reg);
2801 udelay(100);
2802
2803 reg = FDI_RX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2806
2807 /* Wait for the clocks to turn off. */
2808 POSTING_READ(reg);
2809 udelay(100);
2810}
2811
0fc932b8
JB		 2812static void ironlake_fdi_disable(struct drm_crtc *crtc)
2813{
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 int pipe = intel_crtc->pipe;
2818 u32 reg, temp;
2819
2820 /* disable CPU FDI tx and PCH FDI rx */
2821 reg = FDI_TX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2824 POSTING_READ(reg);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~(0x7 << 16);
dfd07d72 2829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2831
2832 POSTING_READ(reg);
2833 udelay(100);
2834
2835 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2836 if (HAS_PCH_IBX(dev)) {
2837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2838 }
0fc932b8
JB		 2839
2840 /* still set train pattern 1 */
2841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~FDI_LINK_TRAIN_NONE;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1;
2845 I915_WRITE(reg, temp);
2846
2847 reg = FDI_RX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 if (HAS_PCH_CPT(dev)) {
2850 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2851 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2852 } else {
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 }
2856 /* BPC in FDI rx is consistent with that in PIPECONF */
2857 temp &= ~(0x07 << 16);
dfd07d72 2858 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2859 I915_WRITE(reg, temp);
2860
2861 POSTING_READ(reg);
2862 udelay(100);
2863}
2864
5bb61643
CW		 2865static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2866{
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2870 unsigned long flags;
2871 bool pending;
2872
10d83730
VS		 2873 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2874 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2875 return false;
2876
2877 spin_lock_irqsave(&dev->event_lock, flags);
2878 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879 spin_unlock_irqrestore(&dev->event_lock, flags);
2880
2881 return pending;
2882}
2883
e6c3a2a6
CW		 2884static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2885{
0f91128d 2886 struct drm_device *dev = crtc->dev;
5bb61643 2887 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2888
2889 if (crtc->fb == NULL)
2890 return;
2891
2c10d571
DV		 2892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2893
5bb61643
CW		 2894 wait_event(dev_priv->pending_flip_queue,
2895 !intel_crtc_has_pending_flip(crtc));
2896
0f91128d
CW		 2897 mutex_lock(&dev->struct_mutex);
2898 intel_finish_fb(crtc->fb);
2899 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2900}
2901
e615efe4
ED		 2902/* Program iCLKIP clock to the desired frequency */
2903static void lpt_program_iclkip(struct drm_crtc *crtc)
2904{
2905 struct drm_device *dev = crtc->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2908 u32 temp;
2909
09153000
DV		 2910 mutex_lock(&dev_priv->dpio_lock);
2911
e615efe4
ED		 2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2919 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2920 SBI_SSCCTL_DISABLE,
2921 SBI_ICLK);
e615efe4
ED		 2922
2923 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2924 if (crtc->mode.clock == 20000) {
2925 auxdiv = 1;
2926 divsel = 0x41;
2927 phaseinc = 0x20;
2928 } else {
2929 /* The iCLK virtual clock root frequency is in MHz,
2930 * but the crtc->mode.clock in in KHz. To get the divisors,
2931 * it is necessary to divide one by another, so we
2932 * convert the virtual clock precision to KHz here for higher
2933 * precision.
2934 */
2935 u32 iclk_virtual_root_freq = 172800 * 1000;
2936 u32 iclk_pi_range = 64;
2937 u32 desired_divisor, msb_divisor_value, pi_value;
2938
2939 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2940 msb_divisor_value = desired_divisor / iclk_pi_range;
2941 pi_value = desired_divisor % iclk_pi_range;
2942
2943 auxdiv = 0;
2944 divsel = msb_divisor_value - 2;
2945 phaseinc = pi_value;
2946 }
2947
2948 /* This should not happen with any sane values */
2949 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2950 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2952 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2953
2954 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2955 crtc->mode.clock,
2956 auxdiv,
2957 divsel,
2958 phasedir,
2959 phaseinc);
2960
2961 /* Program SSCDIVINTPHASE6 */
988d6ee8 2962 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2963 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2964 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2965 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2967 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2968 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2969 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2970
2971 /* Program SSCAUXDIV */
988d6ee8 2972 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2973 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2974 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2975 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2976
2977 /* Enable modulator and associated divider */
988d6ee8 2978 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2979 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Wait for initialization time */
2983 udelay(24);
2984
2985 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2986
2987 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2988}
2989
f67a559d
JB		 2990/*
2991 * Enable PCH resources required for PCH ports:
2992 * - PCH PLLs
2993 * - FDI training & RX/TX
2994 * - update transcoder timings
2995 * - DP transcoding bits
2996 * - transcoder
2997 */
2998static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2999{
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003 int pipe = intel_crtc->pipe;
ee7b9f93 3004 u32 reg, temp;
2c07245f 3005
e7e164db
CW		 3006 assert_transcoder_disabled(dev_priv, pipe);
3007
cd986abb
DV		 3008 /* Write the TU size bits before fdi link training, so that error
3009 * detection works. */
3010 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3011 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3012
c98e9dcf 3013 /* For PCH output, training FDI link */
674cf967 3014 dev_priv->display.fdi_link_train(crtc);
2c07245f 3015
572deb37
DV		 3016 /* XXX: pch pll's can be enabled any time before we enable the PCH
3017 * transcoder, and we actually should do this to not upset any PCH
3018 * transcoder that already use the clock when we share it.
3019 *
3020 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3021 * unconditionally resets the pll - we need that to have the right LVDS
3022 * enable sequence. */
b6b4e185 3023 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3024
303b81e0 3025 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3026 u32 sel;
4b645f14 3027
c98e9dcf 3028 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3029 switch (pipe) {
3030 default:
3031 case 0:
3032 temp |= TRANSA_DPLL_ENABLE;
3033 sel = TRANSA_DPLLB_SEL;
3034 break;
3035 case 1:
3036 temp |= TRANSB_DPLL_ENABLE;
3037 sel = TRANSB_DPLLB_SEL;
3038 break;
3039 case 2:
3040 temp |= TRANSC_DPLL_ENABLE;
3041 sel = TRANSC_DPLLB_SEL;
3042 break;
d64311ab 3043 }
ee7b9f93
JB		 3044 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045 temp |= sel;
3046 else
3047 temp &= ~sel;
c98e9dcf 3048 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3049 }
5eddb70b 3050
d9b6cb56
JB		 3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3053 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3056
5eddb70b
CW		 3057 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3061
303b81e0 3062 intel_fdi_normal_train(crtc);
5e84e1a4 3063
c98e9dcf
JB		 3064 /* For PCH DP, enable TRANS_DP_CTL */
3065 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3066 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3067 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3068 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3069 reg = TRANS_DP_CTL(pipe);
3070 temp = I915_READ(reg);
3071 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3072 TRANS_DP_SYNC_MASK |
3073 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3074 temp |= (TRANS_DP_OUTPUT_ENABLE |
3075 TRANS_DP_ENH_FRAMING);
9325c9f0 3076 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3077
3078 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3079 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3080 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3081 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3082
3083 switch (intel_trans_dp_port_sel(crtc)) {
3084 case PCH_DP_B:
5eddb70b 3085 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3086 break;
3087 case PCH_DP_C:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3089 break;
3090 case PCH_DP_D:
5eddb70b 3091 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3092 break;
3093 default:
e95d41e1 3094 BUG();
32f9d658 3095 }
2c07245f 3096
5eddb70b 3097 I915_WRITE(reg, temp);
6be4a607 3098 }
b52eb4dc 3099
b8a4f404 3100 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3101}
3102
1507e5bd
PZ		 3103static void lpt_pch_enable(struct drm_crtc *crtc)
3104{
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3108 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3109
daed2dbb 3110 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3111
8c52b5e8 3112 lpt_program_iclkip(crtc);
1507e5bd 3113
0540e488 3114 /* Set transcoder timing. */
daed2dbb
PZ		 3115 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3116 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3117 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3118
daed2dbb
PZ		 3119 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3120 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3121 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3122 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3123
937bb610 3124 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3125}
3126
ee7b9f93
JB		 3127static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3128{
3129 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3130
3131 if (pll == NULL)
3132 return;
3133
3134 if (pll->refcount == 0) {
3135 WARN(1, "bad PCH PLL refcount\n");
3136 return;
3137 }
3138
3139 --pll->refcount;
3140 intel_crtc->pch_pll = NULL;
3141}
3142
3143static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3144{
3145 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3146 struct intel_pch_pll *pll;
3147 int i;
3148
3149 pll = intel_crtc->pch_pll;
3150 if (pll) {
3151 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3152 intel_crtc->base.base.id, pll->pll_reg);
3153 goto prepare;
3154 }
3155
98b6bd99
DV		 3156 if (HAS_PCH_IBX(dev_priv->dev)) {
3157 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3158 i = intel_crtc->pipe;
3159 pll = &dev_priv->pch_plls[i];
3160
3161 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3162 intel_crtc->base.base.id, pll->pll_reg);
3163
3164 goto found;
3165 }
3166
ee7b9f93
JB		 3167 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3168 pll = &dev_priv->pch_plls[i];
3169
3170 /* Only want to check enabled timings first */
3171 if (pll->refcount == 0)
3172 continue;
3173
3174 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3175 fp == I915_READ(pll->fp0_reg)) {
3176 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3177 intel_crtc->base.base.id,
3178 pll->pll_reg, pll->refcount, pll->active);
3179
3180 goto found;
3181 }
3182 }
3183
3184 /* Ok no matching timings, maybe there's a free one? */
3185 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186 pll = &dev_priv->pch_plls[i];
3187 if (pll->refcount == 0) {
3188 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3189 intel_crtc->base.base.id, pll->pll_reg);
3190 goto found;
3191 }
3192 }
3193
3194 return NULL;
3195
3196found:
3197 intel_crtc->pch_pll = pll;
3198 pll->refcount++;
84f44ce7 3199 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3200prepare: /* separate function? */
3201 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3202
e04c7350
CW		 3203 /* Wait for the clocks to stabilize before rewriting the regs */
3204 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3205 POSTING_READ(pll->pll_reg);
3206 udelay(150);
e04c7350
CW		 3207
3208 I915_WRITE(pll->fp0_reg, fp);
3209 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3210 pll->on = false;
3211 return pll;
3212}
3213
d4270e57
JB		 3214void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3215{
3216 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3217 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3218 u32 temp;
3219
3220 temp = I915_READ(dslreg);
3221 udelay(500);
3222 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3223 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3225 }
3226}
3227
f67a559d
JB		 3228static void ironlake_crtc_enable(struct drm_crtc *crtc)
3229{
3230 struct drm_device *dev = crtc->dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3233 struct intel_encoder *encoder;
f67a559d
JB		 3234 int pipe = intel_crtc->pipe;
3235 int plane = intel_crtc->plane;
3236 u32 temp;
f67a559d 3237
08a48469
DV		 3238 WARN_ON(!crtc->enabled);
3239
f67a559d
JB		 3240 if (intel_crtc->active)
3241 return;
3242
3243 intel_crtc->active = true;
8664281b
PZ		 3244
3245 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3246 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3247
f67a559d
JB		 3248 intel_update_watermarks(dev);
3249
3250 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3251 temp = I915_READ(PCH_LVDS);
3252 if ((temp & LVDS_PORT_EN) == 0)
3253 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3254 }
3255
f67a559d 3256
5bfe2ac0 3257 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3258 /* Note: FDI PLL enabling _must_ be done before we enable the
3259 * cpu pipes, hence this is separate from all the other fdi/pch
3260 * enabling. */
88cefb6c 3261 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3262 } else {
3263 assert_fdi_tx_disabled(dev_priv, pipe);
3264 assert_fdi_rx_disabled(dev_priv, pipe);
3265 }
f67a559d 3266
bf49ec8c
DV		 3267 for_each_encoder_on_crtc(dev, crtc, encoder)
3268 if (encoder->pre_enable)
3269 encoder->pre_enable(encoder);
f67a559d
JB		 3270
3271 /* Enable panel fitting for LVDS */
3272 if (dev_priv->pch_pf_size &&
547dc041
JN		 3273 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3274 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3275 /* Force use of hard-coded filter coefficients
3276 * as some pre-programmed values are broken,
3277 * e.g. x201.
3278 */
13888d78
PZ		 3279 if (IS_IVYBRIDGE(dev))
3280 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3281 PF_PIPE_SEL_IVB(pipe));
3282 else
3283 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3284 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3285 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3286 }
3287
9c54c0dd
JB		 3288 /*
3289 * On ILK+ LUT must be loaded before the pipe is running but with
3290 * clocks enabled
3291 */
3292 intel_crtc_load_lut(crtc);
3293
5bfe2ac0
DV		 3294 intel_enable_pipe(dev_priv, pipe,
3295 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3296 intel_enable_plane(dev_priv, plane, pipe);
3297
5bfe2ac0 3298 if (intel_crtc->config.has_pch_encoder)
f67a559d 3299 ironlake_pch_enable(crtc);
c98e9dcf 3300
d1ebd816 3301 mutex_lock(&dev->struct_mutex);
bed4a673 3302 intel_update_fbc(dev);
d1ebd816
BW		 3303 mutex_unlock(&dev->struct_mutex);
3304
6b383a7f 3305 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3306
fa5c73b1
DV		 3307 for_each_encoder_on_crtc(dev, crtc, encoder)
3308 encoder->enable(encoder);
61b77ddd
DV		 3309
3310 if (HAS_PCH_CPT(dev))
3311 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3312
3313 /*
3314 * There seems to be a race in PCH platform hw (at least on some
3315 * outputs) where an enabled pipe still completes any pageflip right
3316 * away (as if the pipe is off) instead of waiting for vblank. As soon
3317 * as the first vblank happend, everything works as expected. Hence just
3318 * wait for one vblank before returning to avoid strange things
3319 * happening.
3320 */
3321 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3322}
3323
4f771f10
PZ		 3324static void haswell_crtc_enable(struct drm_crtc *crtc)
3325{
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329 struct intel_encoder *encoder;
3330 int pipe = intel_crtc->pipe;
3331 int plane = intel_crtc->plane;
4f771f10
PZ		 3332
3333 WARN_ON(!crtc->enabled);
3334
3335 if (intel_crtc->active)
3336 return;
3337
3338 intel_crtc->active = true;
8664281b
PZ		 3339
3340 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3341 if (intel_crtc->config.has_pch_encoder)
3342 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3343
4f771f10
PZ		 3344 intel_update_watermarks(dev);
3345
5bfe2ac0 3346 if (intel_crtc->config.has_pch_encoder)
04945641 3347 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3348
3349 for_each_encoder_on_crtc(dev, crtc, encoder)
3350 if (encoder->pre_enable)
3351 encoder->pre_enable(encoder);
3352
1f544388 3353 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3354
1f544388 3355 /* Enable panel fitting for eDP */
547dc041
JN		 3356 if (dev_priv->pch_pf_size &&
3357 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3358 /* Force use of hard-coded filter coefficients
3359 * as some pre-programmed values are broken,
3360 * e.g. x201.
3361 */
54075a7d
PZ		 3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3363 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3364 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3365 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3366 }
3367
3368 /*
3369 * On ILK+ LUT must be loaded before the pipe is running but with
3370 * clocks enabled
3371 */
3372 intel_crtc_load_lut(crtc);
3373
1f544388 3374 intel_ddi_set_pipe_settings(crtc);
8228c251 3375 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3376
5bfe2ac0
DV		 3377 intel_enable_pipe(dev_priv, pipe,
3378 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3379 intel_enable_plane(dev_priv, plane, pipe);
3380
5bfe2ac0 3381 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3382 lpt_pch_enable(crtc);
4f771f10
PZ		 3383
3384 mutex_lock(&dev->struct_mutex);
3385 intel_update_fbc(dev);
3386 mutex_unlock(&dev->struct_mutex);
3387
3388 intel_crtc_update_cursor(crtc, true);
3389
3390 for_each_encoder_on_crtc(dev, crtc, encoder)
3391 encoder->enable(encoder);
3392
4f771f10
PZ		 3393 /*
3394 * There seems to be a race in PCH platform hw (at least on some
3395 * outputs) where an enabled pipe still completes any pageflip right
3396 * away (as if the pipe is off) instead of waiting for vblank. As soon
3397 * as the first vblank happend, everything works as expected. Hence just
3398 * wait for one vblank before returning to avoid strange things
3399 * happening.
3400 */
3401 intel_wait_for_vblank(dev, intel_crtc->pipe);
3402}
3403
6be4a607
JB		 3404static void ironlake_crtc_disable(struct drm_crtc *crtc)
3405{
3406 struct drm_device *dev = crtc->dev;
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3409 struct intel_encoder *encoder;
6be4a607
JB		 3410 int pipe = intel_crtc->pipe;
3411 int plane = intel_crtc->plane;
5eddb70b 3412 u32 reg, temp;
b52eb4dc 3413
ef9c3aee 3414
f7abfe8b
CW		 3415 if (!intel_crtc->active)
3416 return;
3417
ea9d758d
DV		 3418 for_each_encoder_on_crtc(dev, crtc, encoder)
3419 encoder->disable(encoder);
3420
e6c3a2a6 3421 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3422 drm_vblank_off(dev, pipe);
6b383a7f 3423 intel_crtc_update_cursor(crtc, false);
5eddb70b 3424
b24e7179 3425 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3426
973d04f9
CW		 3427 if (dev_priv->cfb_plane == plane)
3428 intel_disable_fbc(dev);
2c07245f 3429
8664281b 3430 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3431 intel_disable_pipe(dev_priv, pipe);
32f9d658 3432
6be4a607 3433 /* Disable PF */
9db4a9c7
JB		 3434 I915_WRITE(PF_CTL(pipe), 0);
3435 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3436
bf49ec8c
DV		 3437 for_each_encoder_on_crtc(dev, crtc, encoder)
3438 if (encoder->post_disable)
3439 encoder->post_disable(encoder);
2c07245f 3440
0fc932b8 3441 ironlake_fdi_disable(crtc);
249c0e64 3442
b8a4f404 3443 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3444 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3445
6be4a607
JB		 3446 if (HAS_PCH_CPT(dev)) {
3447 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3448 reg = TRANS_DP_CTL(pipe);
3449 temp = I915_READ(reg);
3450 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3451 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3452 I915_WRITE(reg, temp);
6be4a607
JB		 3453
3454 /* disable DPLL_SEL */
3455 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3456 switch (pipe) {
3457 case 0:
d64311ab 3458 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3459 break;
3460 case 1:
6be4a607 3461 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3462 break;
3463 case 2:
4b645f14 3464 /* C shares PLL A or B */
d64311ab 3465 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3466 break;
3467 default:
3468 BUG(); /* wtf */
3469 }
6be4a607 3470 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3471 }
e3421a18 3472
6be4a607 3473 /* disable PCH DPLL */
ee7b9f93 3474 intel_disable_pch_pll(intel_crtc);
8db9d77b 3475
88cefb6c 3476 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3477
f7abfe8b 3478 intel_crtc->active = false;
6b383a7f 3479 intel_update_watermarks(dev);
d1ebd816
BW		 3480
3481 mutex_lock(&dev->struct_mutex);
6b383a7f 3482 intel_update_fbc(dev);
d1ebd816 3483 mutex_unlock(&dev->struct_mutex);
6be4a607 3484}
1b3c7a47 3485
4f771f10 3486static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3487{
4f771f10
PZ		 3488 struct drm_device *dev = crtc->dev;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3491 struct intel_encoder *encoder;
3492 int pipe = intel_crtc->pipe;
3493 int plane = intel_crtc->plane;
3b117c8f 3494 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3495
4f771f10
PZ		 3496 if (!intel_crtc->active)
3497 return;
3498
3499 for_each_encoder_on_crtc(dev, crtc, encoder)
3500 encoder->disable(encoder);
3501
3502 intel_crtc_wait_for_pending_flips(crtc);
3503 drm_vblank_off(dev, pipe);
3504 intel_crtc_update_cursor(crtc, false);
3505
3506 intel_disable_plane(dev_priv, plane, pipe);
3507
3508 if (dev_priv->cfb_plane == plane)
3509 intel_disable_fbc(dev);
3510
8664281b
PZ		 3511 if (intel_crtc->config.has_pch_encoder)
3512 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3513 intel_disable_pipe(dev_priv, pipe);
3514
ad80a810 3515 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3516
f7708f78
PZ		 3517 /* XXX: Once we have proper panel fitter state tracking implemented with
3518 * hardware state read/check support we should switch to only disable
3519 * the panel fitter when we know it's used. */
3520 if (intel_using_power_well(dev)) {
3521 I915_WRITE(PF_CTL(pipe), 0);
3522 I915_WRITE(PF_WIN_SZ(pipe), 0);
3523 }
4f771f10 3524
1f544388 3525 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3526
3527 for_each_encoder_on_crtc(dev, crtc, encoder)
3528 if (encoder->post_disable)
3529 encoder->post_disable(encoder);
3530
88adfff1 3531 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3532 lpt_disable_pch_transcoder(dev_priv);
8664281b 3533 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3534 intel_ddi_fdi_disable(crtc);
83616634 3535 }
4f771f10
PZ		 3536
3537 intel_crtc->active = false;
3538 intel_update_watermarks(dev);
3539
3540 mutex_lock(&dev->struct_mutex);
3541 intel_update_fbc(dev);
3542 mutex_unlock(&dev->struct_mutex);
3543}
3544
ee7b9f93
JB		 3545static void ironlake_crtc_off(struct drm_crtc *crtc)
3546{
3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548 intel_put_pch_pll(intel_crtc);
3549}
3550
6441ab5f
PZ		 3551static void haswell_crtc_off(struct drm_crtc *crtc)
3552{
a5c961d1
PZ		 3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554
3555 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3556 * start using it. */
3b117c8f 3557 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3558
6441ab5f
PZ		 3559 intel_ddi_put_crtc_pll(crtc);
3560}
3561
02e792fb
DV		 3562static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3563{
02e792fb 3564 if (!enable && intel_crtc->overlay) {
23f09ce3 3565 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3566 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3567
23f09ce3 3568 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3569 dev_priv->mm.interruptible = false;
3570 (void) intel_overlay_switch_off(intel_crtc->overlay);
3571 dev_priv->mm.interruptible = true;
23f09ce3 3572 mutex_unlock(&dev->struct_mutex);
02e792fb 3573 }
02e792fb 3574
5dcdbcb0
CW		 3575 /* Let userspace switch the overlay on again. In most cases userspace
3576 * has to recompute where to put it anyway.
3577 */
02e792fb
DV		 3578}
3579
61bc95c1
EE		 3580/**
3581 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3582 * cursor plane briefly if not already running after enabling the display
3583 * plane.
3584 * This workaround avoids occasional blank screens when self refresh is
3585 * enabled.
3586 */
3587static void
3588g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3589{
3590 u32 cntl = I915_READ(CURCNTR(pipe));
3591
3592 if ((cntl & CURSOR_MODE) == 0) {
3593 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3594
3595 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3596 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3597 intel_wait_for_vblank(dev_priv->dev, pipe);
3598 I915_WRITE(CURCNTR(pipe), cntl);
3599 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3600 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3601 }
3602}
3603
89b667f8
JB		 3604static void valleyview_crtc_enable(struct drm_crtc *crtc)
3605{
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609 struct intel_encoder *encoder;
3610 int pipe = intel_crtc->pipe;
3611 int plane = intel_crtc->plane;
3612
3613 WARN_ON(!crtc->enabled);
3614
3615 if (intel_crtc->active)
3616 return;
3617
3618 intel_crtc->active = true;
3619 intel_update_watermarks(dev);
3620
3621 mutex_lock(&dev_priv->dpio_lock);
3622
3623 for_each_encoder_on_crtc(dev, crtc, encoder)
3624 if (encoder->pre_pll_enable)
3625 encoder->pre_pll_enable(encoder);
3626
3627 intel_enable_pll(dev_priv, pipe);
3628
3629 for_each_encoder_on_crtc(dev, crtc, encoder)
3630 if (encoder->pre_enable)
3631 encoder->pre_enable(encoder);
3632
3633 /* VLV wants encoder enabling _before_ the pipe is up. */
3634 for_each_encoder_on_crtc(dev, crtc, encoder)
3635 encoder->enable(encoder);
3636
3637 intel_enable_pipe(dev_priv, pipe, false);
3638 intel_enable_plane(dev_priv, plane, pipe);
3639
3640 intel_crtc_load_lut(crtc);
3641 intel_update_fbc(dev);
3642
3643 /* Give the overlay scaler a chance to enable if it's on this pipe */
3644 intel_crtc_dpms_overlay(intel_crtc, true);
3645 intel_crtc_update_cursor(crtc, true);
3646
3647 mutex_unlock(&dev_priv->dpio_lock);
3648}
3649
0b8765c6 3650static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3651{
3652 struct drm_device *dev = crtc->dev;
79e53945
JB		 3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3655 struct intel_encoder *encoder;
79e53945 3656 int pipe = intel_crtc->pipe;
80824003 3657 int plane = intel_crtc->plane;
79e53945 3658
08a48469
DV		 3659 WARN_ON(!crtc->enabled);
3660
f7abfe8b
CW		 3661 if (intel_crtc->active)
3662 return;
3663
3664 intel_crtc->active = true;
6b383a7f
CW		 3665 intel_update_watermarks(dev);
3666
63d7bbe9 3667 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3668
3669 for_each_encoder_on_crtc(dev, crtc, encoder)
3670 if (encoder->pre_enable)
3671 encoder->pre_enable(encoder);
3672
040484af 3673 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3674 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3675 if (IS_G4X(dev))
3676 g4x_fixup_plane(dev_priv, pipe);
79e53945 3677
0b8765c6 3678 intel_crtc_load_lut(crtc);
bed4a673 3679 intel_update_fbc(dev);
79e53945 3680
0b8765c6
JB		 3681 /* Give the overlay scaler a chance to enable if it's on this pipe */
3682 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3683 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3684
fa5c73b1
DV		 3685 for_each_encoder_on_crtc(dev, crtc, encoder)
3686 encoder->enable(encoder);
0b8765c6 3687}
79e53945 3688
87476d63
DV		 3689static void i9xx_pfit_disable(struct intel_crtc *crtc)
3690{
3691 struct drm_device *dev = crtc->base.dev;
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 enum pipe pipe;
3694 uint32_t pctl = I915_READ(PFIT_CONTROL);
3695
3696 assert_pipe_disabled(dev_priv, crtc->pipe);
3697
3698 if (INTEL_INFO(dev)->gen >= 4)
3699 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3700 else
3701 pipe = PIPE_B;
3702
3703 if (pipe == crtc->pipe) {
3704 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3705 I915_WRITE(PFIT_CONTROL, 0);
3706 }
3707}
3708
0b8765c6
JB		 3709static void i9xx_crtc_disable(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3714 struct intel_encoder *encoder;
0b8765c6
JB		 3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
ef9c3aee 3717
f7abfe8b
CW		 3718 if (!intel_crtc->active)
3719 return;
3720
ea9d758d
DV		 3721 for_each_encoder_on_crtc(dev, crtc, encoder)
3722 encoder->disable(encoder);
3723
0b8765c6 3724 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3725 intel_crtc_wait_for_pending_flips(crtc);
3726 drm_vblank_off(dev, pipe);
0b8765c6 3727 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3728 intel_crtc_update_cursor(crtc, false);
0b8765c6 3729
973d04f9
CW		 3730 if (dev_priv->cfb_plane == plane)
3731 intel_disable_fbc(dev);
79e53945 3732
b24e7179 3733 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3734 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3735
87476d63 3736 i9xx_pfit_disable(intel_crtc);
24a1f16d 3737
89b667f8
JB		 3738 for_each_encoder_on_crtc(dev, crtc, encoder)
3739 if (encoder->post_disable)
3740 encoder->post_disable(encoder);
3741
63d7bbe9 3742 intel_disable_pll(dev_priv, pipe);
0b8765c6 3743
f7abfe8b 3744 intel_crtc->active = false;
6b383a7f
CW		 3745 intel_update_fbc(dev);
3746 intel_update_watermarks(dev);
0b8765c6
JB		 3747}
3748
ee7b9f93
JB		 3749static void i9xx_crtc_off(struct drm_crtc *crtc)
3750{
3751}
3752
976f8a20
DV		 3753static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3754 bool enabled)
2c07245f
ZW		 3755{
3756 struct drm_device *dev = crtc->dev;
3757 struct drm_i915_master_private *master_priv;
3758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759 int pipe = intel_crtc->pipe;
79e53945
JB		 3760
3761 if (!dev->primary->master)
3762 return;
3763
3764 master_priv = dev->primary->master->driver_priv;
3765 if (!master_priv->sarea_priv)
3766 return;
3767
79e53945
JB		 3768 switch (pipe) {
3769 case 0:
3770 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3771 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3772 break;
3773 case 1:
3774 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3775 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3776 break;
3777 default:
9db4a9c7 3778 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3779 break;
3780 }
79e53945
JB		 3781}
3782
976f8a20
DV		 3783/**
3784 * Sets the power management mode of the pipe and plane.
3785 */
3786void intel_crtc_update_dpms(struct drm_crtc *crtc)
3787{
3788 struct drm_device *dev = crtc->dev;
3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 struct intel_encoder *intel_encoder;
3791 bool enable = false;
3792
3793 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3794 enable |= intel_encoder->connectors_active;
3795
3796 if (enable)
3797 dev_priv->display.crtc_enable(crtc);
3798 else
3799 dev_priv->display.crtc_disable(crtc);
3800
3801 intel_crtc_update_sarea(crtc, enable);
3802}
3803
cdd59983
CW		 3804static void intel_crtc_disable(struct drm_crtc *crtc)
3805{
cdd59983 3806 struct drm_device *dev = crtc->dev;
976f8a20 3807 struct drm_connector *connector;
ee7b9f93 3808 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3810
976f8a20
DV		 3811 /* crtc should still be enabled when we disable it. */
3812 WARN_ON(!crtc->enabled);
3813
7b9f35a6 3814 intel_crtc->eld_vld = false;
976f8a20
DV		 3815 dev_priv->display.crtc_disable(crtc);
3816 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3817 dev_priv->display.off(crtc);
3818
931872fc
CW		 3819 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3820 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3821
3822 if (crtc->fb) {
3823 mutex_lock(&dev->struct_mutex);
1690e1eb 3824 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3825 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3826 crtc->fb = NULL;
3827 }
3828
3829 /* Update computed state. */
3830 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3831 if (!connector->encoder || !connector->encoder->crtc)
3832 continue;
3833
3834 if (connector->encoder->crtc != crtc)
3835 continue;
3836
3837 connector->dpms = DRM_MODE_DPMS_OFF;
3838 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3839 }
3840}
3841
a261b246 3842void intel_modeset_disable(struct drm_device *dev)
79e53945 3843{
a261b246
DV		 3844 struct drm_crtc *crtc;
3845
3846 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3847 if (crtc->enabled)
3848 intel_crtc_disable(crtc);
3849 }
79e53945
JB		 3850}
3851
ea5b213a 3852void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3853{
4ef69c7a 3854 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3855
ea5b213a
CW		 3856 drm_encoder_cleanup(encoder);
3857 kfree(intel_encoder);
7e7d76c3
JB		 3858}
3859
5ab432ef
DV		 3860/* Simple dpms helper for encodres with just one connector, no cloning and only
3861 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3862 * state of the entire output pipe. */
3863void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3864{
5ab432ef
DV		 3865 if (mode == DRM_MODE_DPMS_ON) {
3866 encoder->connectors_active = true;
3867
b2cabb0e 3868 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3869 } else {
3870 encoder->connectors_active = false;
3871
b2cabb0e 3872 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3873 }
79e53945
JB		 3874}
3875
0a91ca29
DV		 3876/* Cross check the actual hw state with our own modeset state tracking (and it's
3877 * internal consistency). */
b980514c 3878static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3879{
0a91ca29
DV		 3880 if (connector->get_hw_state(connector)) {
3881 struct intel_encoder *encoder = connector->encoder;
3882 struct drm_crtc *crtc;
3883 bool encoder_enabled;
3884 enum pipe pipe;
3885
3886 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3887 connector->base.base.id,
3888 drm_get_connector_name(&connector->base));
3889
3890 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3891 "wrong connector dpms state\n");
3892 WARN(connector->base.encoder != &encoder->base,
3893 "active connector not linked to encoder\n");
3894 WARN(!encoder->connectors_active,
3895 "encoder->connectors_active not set\n");
3896
3897 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3898 WARN(!encoder_enabled, "encoder not enabled\n");
3899 if (WARN_ON(!encoder->base.crtc))
3900 return;
3901
3902 crtc = encoder->base.crtc;
3903
3904 WARN(!crtc->enabled, "crtc not enabled\n");
3905 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3906 WARN(pipe != to_intel_crtc(crtc)->pipe,
3907 "encoder active on the wrong pipe\n");
3908 }
79e53945
JB		 3909}
3910
5ab432ef
DV		 3911/* Even simpler default implementation, if there's really no special case to
3912 * consider. */
3913void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3914{
5ab432ef 3915 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3916
5ab432ef
DV		 3917 /* All the simple cases only support two dpms states. */
3918 if (mode != DRM_MODE_DPMS_ON)
3919 mode = DRM_MODE_DPMS_OFF;
d4270e57 3920
5ab432ef
DV		 3921 if (mode == connector->dpms)
3922 return;
3923
3924 connector->dpms = mode;
3925
3926 /* Only need to change hw state when actually enabled */
3927 if (encoder->base.crtc)
3928 intel_encoder_dpms(encoder, mode);
3929 else
8af6cf88 3930 WARN_ON(encoder->connectors_active != false);
0a91ca29 3931
b980514c 3932 intel_modeset_check_state(connector->dev);
79e53945
JB		 3933}
3934
f0947c37
DV		 3935/* Simple connector->get_hw_state implementation for encoders that support only
3936 * one connector and no cloning and hence the encoder state determines the state
3937 * of the connector. */
3938bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3939{
24929352 3940 enum pipe pipe = 0;
f0947c37 3941 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3942
f0947c37 3943 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3944}
3945
b8cecdf5
DV		 3946static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3947 struct intel_crtc_config *pipe_config)
79e53945 3948{
2c07245f 3949 struct drm_device *dev = crtc->dev;
b8cecdf5 3950 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3951
bad720ff 3952 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3953 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3954 if (pipe_config->requested_mode.clock * 3
3955 > IRONLAKE_FDI_FREQ * 4)
2377b741 3956 return false;
2c07245f 3957 }
89749350 3958
f9bef081
DV		 3959 /* All interlaced capable intel hw wants timings in frames. Note though
3960 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3961 * timings, so we need to be careful not to clobber these.*/
7ae89233 3962 if (!pipe_config->timings_set)
f9bef081 3963 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3964
44f46b42
CW		 3965 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3966 * with a hsync front porch of 0.
3967 */
3968 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3969 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3970 return false;
3971
bd080ee5 3972 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 3973 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 3974 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 3975 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3976 * for lvds. */
3977 pipe_config->pipe_bpp = 8*3;
3978 }
3979
79e53945
JB		 3980 return true;
3981}
3982
25eb05fc
JB		 3983static int valleyview_get_display_clock_speed(struct drm_device *dev)
3984{
3985 return 400000; /* FIXME */
3986}
3987
e70236a8
JB		 3988static int i945_get_display_clock_speed(struct drm_device *dev)
3989{
3990 return 400000;
3991}
79e53945 3992
e70236a8 3993static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3994{
e70236a8
JB		 3995 return 333000;
3996}
79e53945 3997
e70236a8
JB		 3998static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3999{
4000 return 200000;
4001}
79e53945 4002
e70236a8
JB		 4003static int i915gm_get_display_clock_speed(struct drm_device *dev)
4004{
4005 u16 gcfgc = 0;
79e53945 4006
e70236a8
JB		 4007 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4008
4009 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4010 return 133000;
4011 else {
4012 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4013 case GC_DISPLAY_CLOCK_333_MHZ:
4014 return 333000;
4015 default:
4016 case GC_DISPLAY_CLOCK_190_200_MHZ:
4017 return 190000;
79e53945 4018 }
e70236a8
JB		 4019 }
4020}
4021
4022static int i865_get_display_clock_speed(struct drm_device *dev)
4023{
4024 return 266000;
4025}
4026
4027static int i855_get_display_clock_speed(struct drm_device *dev)
4028{
4029 u16 hpllcc = 0;
4030 /* Assume that the hardware is in the high speed state. This
4031 * should be the default.
4032 */
4033 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4034 case GC_CLOCK_133_200:
4035 case GC_CLOCK_100_200:
4036 return 200000;
4037 case GC_CLOCK_166_250:
4038 return 250000;
4039 case GC_CLOCK_100_133:
79e53945 4040 return 133000;
e70236a8 4041 }
79e53945 4042
e70236a8
JB		 4043 /* Shouldn't happen */
4044 return 0;
4045}
79e53945 4046
e70236a8
JB		 4047static int i830_get_display_clock_speed(struct drm_device *dev)
4048{
4049 return 133000;
79e53945
JB		 4050}
4051
2c07245f 4052static void
e69d0bc1 4053intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4054{
4055 while (*num > 0xffffff || *den > 0xffffff) {
4056 *num >>= 1;
4057 *den >>= 1;
4058 }
4059}
4060
e69d0bc1
DV		 4061void
4062intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4063 int pixel_clock, int link_clock,
4064 struct intel_link_m_n *m_n)
2c07245f 4065{
e69d0bc1 4066 m_n->tu = 64;
22ed1113
CW		 4067 m_n->gmch_m = bits_per_pixel * pixel_clock;
4068 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4069 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4070 m_n->link_m = pixel_clock;
4071 m_n->link_n = link_clock;
e69d0bc1 4072 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4073}
4074
a7615030
CW		 4075static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4076{
72bbe58c
KP		 4077 if (i915_panel_use_ssc >= 0)
4078 return i915_panel_use_ssc != 0;
4079 return dev_priv->lvds_use_ssc
435793df 4080 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4081}
4082
a0c4da24
JB		 4083static int vlv_get_refclk(struct drm_crtc *crtc)
4084{
4085 struct drm_device *dev = crtc->dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 int refclk = 27000; /* for DP & HDMI */
4088
4089 return 100000; /* only one validated so far */
4090
4091 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4092 refclk = 96000;
4093 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4094 if (intel_panel_use_ssc(dev_priv))
4095 refclk = 100000;
4096 else
4097 refclk = 96000;
4098 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4099 refclk = 100000;
4100 }
4101
4102 return refclk;
4103}
4104
c65d77d8
JB		 4105static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4106{
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 int refclk;
4110
a0c4da24
JB		 4111 if (IS_VALLEYVIEW(dev)) {
4112 refclk = vlv_get_refclk(crtc);
4113 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4114 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4115 refclk = dev_priv->lvds_ssc_freq * 1000;
4116 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4117 refclk / 1000);
4118 } else if (!IS_GEN2(dev)) {
4119 refclk = 96000;
4120 } else {
4121 refclk = 48000;
4122 }
4123
4124 return refclk;
4125}
4126
f47709a9 4127static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4128{
f47709a9
DV		 4129 unsigned dotclock = crtc->config.adjusted_mode.clock;
4130 struct dpll *clock = &crtc->config.dpll;
4131
c65d77d8
JB		 4132 /* SDVO TV has fixed PLL values depend on its clock range,
4133 this mirrors vbios setting. */
f47709a9 4134 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4135 clock->p1 = 2;
4136 clock->p2 = 10;
4137 clock->n = 3;
4138 clock->m1 = 16;
4139 clock->m2 = 8;
f47709a9 4140 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4141 clock->p1 = 1;
4142 clock->p2 = 10;
4143 clock->n = 6;
4144 clock->m1 = 12;
4145 clock->m2 = 8;
4146 }
f47709a9
DV		 4147
4148 crtc->config.clock_set = true;
c65d77d8
JB		 4149}
4150
7429e9d4
DV		 4151static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4152{
4153 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4154}
4155
4156static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4157{
4158 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4159}
4160
f47709a9 4161static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4162 intel_clock_t *reduced_clock)
4163{
f47709a9 4164 struct drm_device *dev = crtc->base.dev;
a7516a05 4165 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4166 int pipe = crtc->pipe;
a7516a05
JB		 4167 u32 fp, fp2 = 0;
4168
4169 if (IS_PINEVIEW(dev)) {
7429e9d4 4170 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4171 if (reduced_clock)
7429e9d4 4172 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4173 } else {
7429e9d4 4174 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4175 if (reduced_clock)
7429e9d4 4176 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4177 }
4178
4179 I915_WRITE(FP0(pipe), fp);
4180
f47709a9
DV		 4181 crtc->lowfreq_avail = false;
4182 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4183 reduced_clock && i915_powersave) {
4184 I915_WRITE(FP1(pipe), fp2);
f47709a9 4185 crtc->lowfreq_avail = true;
a7516a05
JB		 4186 } else {
4187 I915_WRITE(FP1(pipe), fp);
4188 }
4189}
4190
89b667f8
JB		 4191static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4192{
4193 u32 reg_val;
4194
4195 /*
4196 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4197 * and set it to a reasonable value instead.
4198 */
4199 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4200 reg_val &= 0xffffff00;
4201 reg_val |= 0x00000030;
4202 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4203
4204 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4205 reg_val &= 0x8cffffff;
4206 reg_val = 0x8c000000;
4207 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4208
4209 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4210 reg_val &= 0xffffff00;
4211 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4212
4213 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4214 reg_val &= 0x00ffffff;
4215 reg_val |= 0xb0000000;
4216 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4217}
4218
03afc4a2
DV		 4219static void intel_dp_set_m_n(struct intel_crtc *crtc)
4220{
4221 if (crtc->config.has_pch_encoder)
4222 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4223 else
4224 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4225}
4226
f47709a9 4227static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4228{
f47709a9 4229 struct drm_device *dev = crtc->base.dev;
a0c4da24 4230 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4231 struct drm_display_mode *adjusted_mode =
4232 &crtc->config.adjusted_mode;
4233 struct intel_encoder *encoder;
f47709a9 4234 int pipe = crtc->pipe;
89b667f8 4235 u32 dpll, mdiv;
a0c4da24 4236 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8
JB		 4237 bool is_hdmi;
4238 u32 coreclk, reg_val, temp;
a0c4da24 4239
09153000
DV		 4240 mutex_lock(&dev_priv->dpio_lock);
4241
89b667f8 4242 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4243
f47709a9
DV		 4244 bestn = crtc->config.dpll.n;
4245 bestm1 = crtc->config.dpll.m1;
4246 bestm2 = crtc->config.dpll.m2;
4247 bestp1 = crtc->config.dpll.p1;
4248 bestp2 = crtc->config.dpll.p2;
a0c4da24 4249
89b667f8
JB		 4250 /* See eDP HDMI DPIO driver vbios notes doc */
4251
4252 /* PLL B needs special handling */
4253 if (pipe)
4254 vlv_pllb_recal_opamp(dev_priv);
4255
4256 /* Set up Tx target for periodic Rcomp update */
4257 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4258
4259 /* Disable target IRef on PLL */
4260 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4261 reg_val &= 0x00ffffff;
4262 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4263
4264 /* Disable fast lock */
4265 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4266
4267 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4268 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4269 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4270 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4271 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4272 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4273 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4274 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4275 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4276 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4277
89b667f8
JB		 4278 mdiv |= DPIO_ENABLE_CALIBRATION;
4279 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4280
89b667f8
JB		 4281 /* Set HBR and RBR LPF coefficients */
4282 if (adjusted_mode->clock == 162000 ||
4283 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4284 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4285 0x005f0021);
4286 else
4287 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4288 0x00d0000f);
4289
4290 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4291 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4292 /* Use SSC source */
4293 if (!pipe)
4294 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4295 0x0df40000);
4296 else
4297 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4298 0x0df70000);
4299 } else { /* HDMI or VGA */
4300 /* Use bend source */
4301 if (!pipe)
4302 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4303 0x0df70000);
4304 else
4305 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4306 0x0df40000);
4307 }
a0c4da24 4308
89b667f8
JB		 4309 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4310 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4311 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4312 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4313 coreclk |= 0x01000000;
4314 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4315
89b667f8 4316 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4317
89b667f8
JB		 4318 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4319 if (encoder->pre_pll_enable)
4320 encoder->pre_pll_enable(encoder);
2a8f64ca 4321
89b667f8
JB		 4322 /* Enable DPIO clock input */
4323 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4324 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4325 if (pipe)
4326 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4327
89b667f8 4328 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4329 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4330 POSTING_READ(DPLL(pipe));
4331 udelay(150);
a0c4da24 4332
89b667f8
JB		 4333 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4334 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4335
4336 if (is_hdmi) {
6cc5f341 4337 temp = 0;
f47709a9
DV		 4338 if (crtc->config.pixel_multiplier > 1) {
4339 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4340 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4341 }
a0c4da24 4342
89b667f8
JB		 4343 I915_WRITE(DPLL_MD(pipe), temp);
4344 POSTING_READ(DPLL_MD(pipe));
2a8f64ca 4345 }
f47709a9 4346
89b667f8
JB		 4347 if (crtc->config.has_dp_encoder)
4348 intel_dp_set_m_n(crtc);
09153000
DV		 4349
4350 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4351}
4352
f47709a9
DV		 4353static void i9xx_update_pll(struct intel_crtc *crtc,
4354 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4355 int num_connectors)
4356{
f47709a9 4357 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4358 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4359 struct intel_encoder *encoder;
f47709a9 4360 int pipe = crtc->pipe;
eb1cbe48
DV		 4361 u32 dpll;
4362 bool is_sdvo;
f47709a9 4363 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4364
f47709a9 4365 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4366
f47709a9
DV		 4367 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4368 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4369
4370 dpll = DPLL_VGA_MODE_DIS;
4371
f47709a9 4372 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4373 dpll |= DPLLB_MODE_LVDS;
4374 else
4375 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4376
eb1cbe48 4377 if (is_sdvo) {
f47709a9 4378 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4379 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4380 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4381 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4382 }
4383 dpll |= DPLL_DVO_HIGH_SPEED;
4384 }
f47709a9 4385 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4386 dpll |= DPLL_DVO_HIGH_SPEED;
4387
4388 /* compute bitmask from p1 value */
4389 if (IS_PINEVIEW(dev))
4390 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4391 else {
4392 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4393 if (IS_G4X(dev) && reduced_clock)
4394 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4395 }
4396 switch (clock->p2) {
4397 case 5:
4398 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4399 break;
4400 case 7:
4401 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4402 break;
4403 case 10:
4404 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4405 break;
4406 case 14:
4407 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4408 break;
4409 }
4410 if (INTEL_INFO(dev)->gen >= 4)
4411 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4412
f47709a9 4413 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4414 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4415 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4416 /* XXX: just matching BIOS for now */
4417 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4418 dpll |= 3;
f47709a9 4419 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4420 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4421 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4422 else
4423 dpll |= PLL_REF_INPUT_DREFCLK;
4424
4425 dpll |= DPLL_VCO_ENABLE;
4426 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4427 POSTING_READ(DPLL(pipe));
4428 udelay(150);
4429
f47709a9 4430 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4431 if (encoder->pre_pll_enable)
4432 encoder->pre_pll_enable(encoder);
eb1cbe48 4433
f47709a9
DV		 4434 if (crtc->config.has_dp_encoder)
4435 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4436
4437 I915_WRITE(DPLL(pipe), dpll);
4438
4439 /* Wait for the clocks to stabilize. */
4440 POSTING_READ(DPLL(pipe));
4441 udelay(150);
4442
4443 if (INTEL_INFO(dev)->gen >= 4) {
4444 u32 temp = 0;
4445 if (is_sdvo) {
6cc5f341 4446 temp = 0;
f47709a9
DV		 4447 if (crtc->config.pixel_multiplier > 1) {
4448 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4449 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4450 }
eb1cbe48
DV		 4451 }
4452 I915_WRITE(DPLL_MD(pipe), temp);
4453 } else {
4454 /* The pixel multiplier can only be updated once the
4455 * DPLL is enabled and the clocks are stable.
4456 *
4457 * So write it again.
4458 */
4459 I915_WRITE(DPLL(pipe), dpll);
4460 }
4461}
4462
f47709a9 4463static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4464 struct drm_display_mode *adjusted_mode,
f47709a9 4465 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4466 int num_connectors)
4467{
f47709a9 4468 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4469 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4470 struct intel_encoder *encoder;
f47709a9 4471 int pipe = crtc->pipe;
eb1cbe48 4472 u32 dpll;
f47709a9 4473 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4474
f47709a9 4475 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4476
eb1cbe48
DV		 4477 dpll = DPLL_VGA_MODE_DIS;
4478
f47709a9 4479 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4480 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4481 } else {
4482 if (clock->p1 == 2)
4483 dpll |= PLL_P1_DIVIDE_BY_TWO;
4484 else
4485 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4486 if (clock->p2 == 4)
4487 dpll |= PLL_P2_DIVIDE_BY_4;
4488 }
4489
f47709a9 4490 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4491 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4492 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4493 else
4494 dpll |= PLL_REF_INPUT_DREFCLK;
4495
4496 dpll |= DPLL_VCO_ENABLE;
4497 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4498 POSTING_READ(DPLL(pipe));
4499 udelay(150);
4500
f47709a9 4501 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4502 if (encoder->pre_pll_enable)
4503 encoder->pre_pll_enable(encoder);
eb1cbe48 4504
5b5896e4
DV		 4505 I915_WRITE(DPLL(pipe), dpll);
4506
4507 /* Wait for the clocks to stabilize. */
4508 POSTING_READ(DPLL(pipe));
4509 udelay(150);
4510
eb1cbe48
DV		 4511 /* The pixel multiplier can only be updated once the
4512 * DPLL is enabled and the clocks are stable.
4513 *
4514 * So write it again.
4515 */
4516 I915_WRITE(DPLL(pipe), dpll);
4517}
4518
b0e77b9c
PZ		 4519static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4520 struct drm_display_mode *mode,
4521 struct drm_display_mode *adjusted_mode)
4522{
4523 struct drm_device *dev = intel_crtc->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4526 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4527 uint32_t vsyncshift;
4528
4529 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4530 /* the chip adds 2 halflines automatically */
4531 adjusted_mode->crtc_vtotal -= 1;
4532 adjusted_mode->crtc_vblank_end -= 1;
4533 vsyncshift = adjusted_mode->crtc_hsync_start
4534 - adjusted_mode->crtc_htotal / 2;
4535 } else {
4536 vsyncshift = 0;
4537 }
4538
4539 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4540 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4541
fe2b8f9d 4542 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4543 (adjusted_mode->crtc_hdisplay - 1) |
4544 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4545 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4546 (adjusted_mode->crtc_hblank_start - 1) |
4547 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4548 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4549 (adjusted_mode->crtc_hsync_start - 1) |
4550 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4551
fe2b8f9d 4552 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4553 (adjusted_mode->crtc_vdisplay - 1) |
4554 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4555 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4556 (adjusted_mode->crtc_vblank_start - 1) |
4557 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4558 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4559 (adjusted_mode->crtc_vsync_start - 1) |
4560 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4561
b5e508d4
PZ		 4562 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4563 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4564 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4565 * bits. */
4566 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4567 (pipe == PIPE_B || pipe == PIPE_C))
4568 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4569
b0e77b9c
PZ		 4570 /* pipesrc controls the size that is scaled from, which should
4571 * always be the user's requested size.
4572 */
4573 I915_WRITE(PIPESRC(pipe),
4574 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4575}
4576
84b046f3
DV		 4577static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4578{
4579 struct drm_device *dev = intel_crtc->base.dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 uint32_t pipeconf;
4582
4583 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4584
4585 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4586 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4587 * core speed.
4588 *
4589 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4590 * pipe == 0 check?
4591 */
4592 if (intel_crtc->config.requested_mode.clock >
4593 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4594 pipeconf |= PIPECONF_DOUBLE_WIDE;
4595 else
4596 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4597 }
4598
4599 /* default to 8bpc */
4600 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4601 if (intel_crtc->config.has_dp_encoder) {
4602 if (intel_crtc->config.dither) {
4603 pipeconf |= PIPECONF_6BPC |
4604 PIPECONF_DITHER_EN |
4605 PIPECONF_DITHER_TYPE_SP;
4606 }
4607 }
4608
4609 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4610 INTEL_OUTPUT_EDP)) {
4611 if (intel_crtc->config.dither) {
4612 pipeconf |= PIPECONF_6BPC |
4613 PIPECONF_ENABLE |
4614 I965_PIPECONF_ACTIVE;
4615 }
4616 }
4617
4618 if (HAS_PIPE_CXSR(dev)) {
4619 if (intel_crtc->lowfreq_avail) {
4620 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4621 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4622 } else {
4623 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4624 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4625 }
4626 }
4627
4628 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4629 if (!IS_GEN2(dev) &&
4630 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4631 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4632 else
4633 pipeconf |= PIPECONF_PROGRESSIVE;
4634
9c8e09b7
VS		 4635 if (IS_VALLEYVIEW(dev)) {
4636 if (intel_crtc->config.limited_color_range)
4637 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4638 else
4639 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4640 }
4641
84b046f3
DV		 4642 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4643 POSTING_READ(PIPECONF(intel_crtc->pipe));
4644}
4645
f564048e 4646static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4647 int x, int y,
94352cf9 4648 struct drm_framebuffer *fb)
79e53945
JB		 4649{
4650 struct drm_device *dev = crtc->dev;
4651 struct drm_i915_private *dev_priv = dev->dev_private;
4652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4653 struct drm_display_mode *adjusted_mode =
4654 &intel_crtc->config.adjusted_mode;
4655 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4656 int pipe = intel_crtc->pipe;
80824003 4657 int plane = intel_crtc->plane;
c751ce4f 4658 int refclk, num_connectors = 0;
652c393a 4659 intel_clock_t clock, reduced_clock;
84b046f3 4660 u32 dspcntr;
eb1cbe48 4661 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4662 bool is_lvds = false, is_tv = false;
5eddb70b 4663 struct intel_encoder *encoder;
d4906093 4664 const intel_limit_t *limit;
5c3b82e2 4665 int ret;
79e53945 4666
6c2b7c12 4667 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4668 switch (encoder->type) {
79e53945
JB		 4669 case INTEL_OUTPUT_LVDS:
4670 is_lvds = true;
4671 break;
4672 case INTEL_OUTPUT_SDVO:
7d57382e 4673 case INTEL_OUTPUT_HDMI:
79e53945 4674 is_sdvo = true;
5eddb70b 4675 if (encoder->needs_tv_clock)
e2f0ba97 4676 is_tv = true;
79e53945 4677 break;
79e53945
JB		 4678 case INTEL_OUTPUT_TVOUT:
4679 is_tv = true;
4680 break;
79e53945 4681 }
43565a06 4682
c751ce4f 4683 num_connectors++;
79e53945
JB		 4684 }
4685
c65d77d8 4686 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4687
d4906093
ML		 4688 /*
4689 * Returns a set of divisors for the desired target clock with the given
4690 * refclk, or FALSE. The returned values represent the clock equation:
4691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4692 */
1b894b59 4693 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4694 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4695 &clock);
79e53945
JB		 4696 if (!ok) {
4697 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4698 return -EINVAL;
79e53945
JB		 4699 }
4700
cda4b7d3 4701 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4702 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4703
ddc9003c 4704 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4705 /*
4706 * Ensure we match the reduced clock's P to the target clock.
4707 * If the clocks don't match, we can't switch the display clock
4708 * by using the FP0/FP1. In such case we will disable the LVDS
4709 * downclock feature.
4710 */
ddc9003c 4711 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4712 dev_priv->lvds_downclock,
4713 refclk,
cec2f356 4714 &clock,
5eddb70b 4715 &reduced_clock);
7026d4ac 4716 }
f47709a9
DV		 4717 /* Compat-code for transition, will disappear. */
4718 if (!intel_crtc->config.clock_set) {
4719 intel_crtc->config.dpll.n = clock.n;
4720 intel_crtc->config.dpll.m1 = clock.m1;
4721 intel_crtc->config.dpll.m2 = clock.m2;
4722 intel_crtc->config.dpll.p1 = clock.p1;
4723 intel_crtc->config.dpll.p2 = clock.p2;
4724 }
7026d4ac 4725
c65d77d8 4726 if (is_sdvo && is_tv)
f47709a9 4727 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4728
eb1cbe48 4729 if (IS_GEN2(dev))
f47709a9 4730 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4731 has_reduced_clock ? &reduced_clock : NULL,
4732 num_connectors);
a0c4da24 4733 else if (IS_VALLEYVIEW(dev))
f47709a9 4734 vlv_update_pll(intel_crtc);
79e53945 4735 else
f47709a9 4736 i9xx_update_pll(intel_crtc,
eb1cbe48 4737 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4738 num_connectors);
79e53945 4739
79e53945
JB		 4740 /* Set up the display plane register */
4741 dspcntr = DISPPLANE_GAMMA_ENABLE;
4742
da6ecc5d
JB		 4743 if (!IS_VALLEYVIEW(dev)) {
4744 if (pipe == 0)
4745 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4746 else
4747 dspcntr |= DISPPLANE_SEL_PIPE_B;
4748 }
79e53945 4749
2582a850 4750 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4751 drm_mode_debug_printmodeline(mode);
4752
b0e77b9c 4753 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4754
4755 /* pipesrc and dspsize control the size that is scaled from,
4756 * which should always be the user's requested size.
79e53945 4757 */
929c77fb
EA		 4758 I915_WRITE(DSPSIZE(plane),
4759 ((mode->vdisplay - 1) << 16) |
4760 (mode->hdisplay - 1));
4761 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4762
84b046f3
DV		 4763 i9xx_set_pipeconf(intel_crtc);
4764
f564048e
EA		 4765 I915_WRITE(DSPCNTR(plane), dspcntr);
4766 POSTING_READ(DSPCNTR(plane));
4767
94352cf9 4768 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4769
4770 intel_update_watermarks(dev);
4771
f564048e
EA		 4772 return ret;
4773}
4774
0e8ffe1b
DV		 4775static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4776 struct intel_crtc_config *pipe_config)
4777{
4778 struct drm_device *dev = crtc->base.dev;
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4780 uint32_t tmp;
4781
4782 tmp = I915_READ(PIPECONF(crtc->pipe));
4783 if (!(tmp & PIPECONF_ENABLE))
4784 return false;
4785
4786 return true;
4787}
4788
dde86e2d 4789static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4790{
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4793 struct intel_encoder *encoder;
74cfd7ac 4794 u32 val, final;
13d83a67 4795 bool has_lvds = false;
199e5d79
KP		 4796 bool has_cpu_edp = false;
4797 bool has_pch_edp = false;
4798 bool has_panel = false;
99eb6a01
KP		 4799 bool has_ck505 = false;
4800 bool can_ssc = false;
13d83a67
JB		 4801
4802 /* We need to take the global config into account */
199e5d79
KP		 4803 list_for_each_entry(encoder, &mode_config->encoder_list,
4804 base.head) {
4805 switch (encoder->type) {
4806 case INTEL_OUTPUT_LVDS:
4807 has_panel = true;
4808 has_lvds = true;
4809 break;
4810 case INTEL_OUTPUT_EDP:
4811 has_panel = true;
4812 if (intel_encoder_is_pch_edp(&encoder->base))
4813 has_pch_edp = true;
4814 else
4815 has_cpu_edp = true;
4816 break;
13d83a67
JB		 4817 }
4818 }
4819
99eb6a01
KP		 4820 if (HAS_PCH_IBX(dev)) {
4821 has_ck505 = dev_priv->display_clock_mode;
4822 can_ssc = has_ck505;
4823 } else {
4824 has_ck505 = false;
4825 can_ssc = true;
4826 }
4827
4828 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4829 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4830 has_ck505);
13d83a67
JB		 4831
4832 /* Ironlake: try to setup display ref clock before DPLL
4833 * enabling. This is only under driver's control after
4834 * PCH B stepping, previous chipset stepping should be
4835 * ignoring this setting.
4836 */
74cfd7ac
CW		 4837 val = I915_READ(PCH_DREF_CONTROL);
4838
4839 /* As we must carefully and slowly disable/enable each source in turn,
4840 * compute the final state we want first and check if we need to
4841 * make any changes at all.
4842 */
4843 final = val;
4844 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4845 if (has_ck505)
4846 final |= DREF_NONSPREAD_CK505_ENABLE;
4847 else
4848 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4849
4850 final &= ~DREF_SSC_SOURCE_MASK;
4851 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4852 final &= ~DREF_SSC1_ENABLE;
4853
4854 if (has_panel) {
4855 final |= DREF_SSC_SOURCE_ENABLE;
4856
4857 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4858 final |= DREF_SSC1_ENABLE;
4859
4860 if (has_cpu_edp) {
4861 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4862 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4863 else
4864 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4865 } else
4866 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4867 } else {
4868 final |= DREF_SSC_SOURCE_DISABLE;
4869 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4870 }
4871
4872 if (final == val)
4873 return;
4874
13d83a67 4875 /* Always enable nonspread source */
74cfd7ac 4876 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4877
99eb6a01 4878 if (has_ck505)
74cfd7ac 4879 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4880 else
74cfd7ac 4881 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4882
199e5d79 4883 if (has_panel) {
74cfd7ac
CW		 4884 val &= ~DREF_SSC_SOURCE_MASK;
4885 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4886
199e5d79 4887 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4888 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4889 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4890 val |= DREF_SSC1_ENABLE;
e77166b5 4891 } else
74cfd7ac 4892 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4893
4894 /* Get SSC going before enabling the outputs */
74cfd7ac 4895 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4896 POSTING_READ(PCH_DREF_CONTROL);
4897 udelay(200);
4898
74cfd7ac 4899 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4900
4901 /* Enable CPU source on CPU attached eDP */
199e5d79 4902 if (has_cpu_edp) {
99eb6a01 4903 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4904 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4905 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4906 }
13d83a67 4907 else
74cfd7ac 4908 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4909 } else
74cfd7ac 4910 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4911
74cfd7ac 4912 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4913 POSTING_READ(PCH_DREF_CONTROL);
4914 udelay(200);
4915 } else {
4916 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4917
74cfd7ac 4918 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4919
4920 /* Turn off CPU output */
74cfd7ac 4921 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4922
74cfd7ac 4923 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4924 POSTING_READ(PCH_DREF_CONTROL);
4925 udelay(200);
4926
4927 /* Turn off the SSC source */
74cfd7ac
CW		 4928 val &= ~DREF_SSC_SOURCE_MASK;
4929 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4930
4931 /* Turn off SSC1 */
74cfd7ac 4932 val &= ~DREF_SSC1_ENABLE;
199e5d79 4933
74cfd7ac 4934 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4935 POSTING_READ(PCH_DREF_CONTROL);
4936 udelay(200);
4937 }
74cfd7ac
CW		 4938
4939 BUG_ON(val != final);
13d83a67
JB		 4940}
4941
dde86e2d
PZ		 4942/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4943static void lpt_init_pch_refclk(struct drm_device *dev)
4944{
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 struct drm_mode_config *mode_config = &dev->mode_config;
4947 struct intel_encoder *encoder;
4948 bool has_vga = false;
4949 bool is_sdv = false;
4950 u32 tmp;
4951
4952 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4953 switch (encoder->type) {
4954 case INTEL_OUTPUT_ANALOG:
4955 has_vga = true;
4956 break;
4957 }
4958 }
4959
4960 if (!has_vga)
4961 return;
4962
c00db246
DV		 4963 mutex_lock(&dev_priv->dpio_lock);
4964
dde86e2d
PZ		 4965 /* XXX: Rip out SDV support once Haswell ships for real. */
4966 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4967 is_sdv = true;
4968
4969 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4970 tmp &= ~SBI_SSCCTL_DISABLE;
4971 tmp |= SBI_SSCCTL_PATHALT;
4972 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4973
4974 udelay(24);
4975
4976 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4977 tmp &= ~SBI_SSCCTL_PATHALT;
4978 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4979
4980 if (!is_sdv) {
4981 tmp = I915_READ(SOUTH_CHICKEN2);
4982 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4983 I915_WRITE(SOUTH_CHICKEN2, tmp);
4984
4985 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4986 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4987 DRM_ERROR("FDI mPHY reset assert timeout\n");
4988
4989 tmp = I915_READ(SOUTH_CHICKEN2);
4990 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4991 I915_WRITE(SOUTH_CHICKEN2, tmp);
4992
4993 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4994 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4995 100))
4996 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4997 }
4998
4999 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5000 tmp &= ~(0xFF << 24);
5001 tmp |= (0x12 << 24);
5002 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5003
dde86e2d
PZ		 5004 if (is_sdv) {
5005 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5006 tmp |= 0x7FFF;
5007 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5008 }
5009
5010 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5011 tmp |= (1 << 11);
5012 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5013
5014 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5015 tmp |= (1 << 11);
5016 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5017
5018 if (is_sdv) {
5019 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5020 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5021 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5022
5023 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5024 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5025 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5026
5027 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5028 tmp |= (0x3F << 8);
5029 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5030
5031 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5032 tmp |= (0x3F << 8);
5033 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5034 }
5035
5036 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5037 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5038 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5039
5040 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5041 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5042 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5043
5044 if (!is_sdv) {
5045 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5046 tmp &= ~(7 << 13);
5047 tmp |= (5 << 13);
5048 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5049
5050 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5051 tmp &= ~(7 << 13);
5052 tmp |= (5 << 13);
5053 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5054 }
5055
5056 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5057 tmp &= ~0xFF;
5058 tmp |= 0x1C;
5059 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5060
5061 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5062 tmp &= ~0xFF;
5063 tmp |= 0x1C;
5064 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5065
5066 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5067 tmp &= ~(0xFF << 16);
5068 tmp |= (0x1C << 16);
5069 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5070
5071 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5072 tmp &= ~(0xFF << 16);
5073 tmp |= (0x1C << 16);
5074 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5075
5076 if (!is_sdv) {
5077 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5078 tmp |= (1 << 27);
5079 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5080
5081 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5082 tmp |= (1 << 27);
5083 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5084
5085 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5086 tmp &= ~(0xF << 28);
5087 tmp |= (4 << 28);
5088 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5089
5090 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5091 tmp &= ~(0xF << 28);
5092 tmp |= (4 << 28);
5093 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5094 }
5095
5096 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5097 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5098 tmp |= SBI_DBUFF0_ENABLE;
5099 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5100
5101 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5102}
5103
5104/*
5105 * Initialize reference clocks when the driver loads
5106 */
5107void intel_init_pch_refclk(struct drm_device *dev)
5108{
5109 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5110 ironlake_init_pch_refclk(dev);
5111 else if (HAS_PCH_LPT(dev))
5112 lpt_init_pch_refclk(dev);
5113}
5114
d9d444cb
JB		 5115static int ironlake_get_refclk(struct drm_crtc *crtc)
5116{
5117 struct drm_device *dev = crtc->dev;
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 struct intel_encoder *encoder;
d9d444cb
JB		 5120 struct intel_encoder *edp_encoder = NULL;
5121 int num_connectors = 0;
5122 bool is_lvds = false;
5123
6c2b7c12 5124 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5125 switch (encoder->type) {
5126 case INTEL_OUTPUT_LVDS:
5127 is_lvds = true;
5128 break;
5129 case INTEL_OUTPUT_EDP:
5130 edp_encoder = encoder;
5131 break;
5132 }
5133 num_connectors++;
5134 }
5135
5136 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5137 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5138 dev_priv->lvds_ssc_freq);
5139 return dev_priv->lvds_ssc_freq * 1000;
5140 }
5141
5142 return 120000;
5143}
5144
c8203565 5145static void ironlake_set_pipeconf(struct drm_crtc *crtc,
d8b32247 5146 struct drm_display_mode *adjusted_mode)
79e53945 5147{
c8203565 5148 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5150 int pipe = intel_crtc->pipe;
c8203565
PZ		 5151 uint32_t val;
5152
5153 val = I915_READ(PIPECONF(pipe));
5154
dfd07d72 5155 val &= ~PIPECONF_BPC_MASK;
965e0c48 5156 switch (intel_crtc->config.pipe_bpp) {
c8203565 5157 case 18:
dfd07d72 5158 val |= PIPECONF_6BPC;
c8203565
PZ		 5159 break;
5160 case 24:
dfd07d72 5161 val |= PIPECONF_8BPC;
c8203565
PZ		 5162 break;
5163 case 30:
dfd07d72 5164 val |= PIPECONF_10BPC;
c8203565
PZ		 5165 break;
5166 case 36:
dfd07d72 5167 val |= PIPECONF_12BPC;
c8203565
PZ		 5168 break;
5169 default:
cc769b62
PZ		 5170 /* Case prevented by intel_choose_pipe_bpp_dither. */
5171 BUG();
c8203565
PZ		 5172 }
5173
5174 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5175 if (intel_crtc->config.dither)
c8203565
PZ		 5176 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5177
5178 val &= ~PIPECONF_INTERLACE_MASK;
5179 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5180 val |= PIPECONF_INTERLACED_ILK;
5181 else
5182 val |= PIPECONF_PROGRESSIVE;
5183
50f3b016 5184 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5185 val |= PIPECONF_COLOR_RANGE_SELECT;
5186 else
5187 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5188
c8203565
PZ		 5189 I915_WRITE(PIPECONF(pipe), val);
5190 POSTING_READ(PIPECONF(pipe));
5191}
5192
86d3efce
VS		 5193/*
5194 * Set up the pipe CSC unit.
5195 *
5196 * Currently only full range RGB to limited range RGB conversion
5197 * is supported, but eventually this should handle various
5198 * RGB<->YCbCr scenarios as well.
5199 */
50f3b016 5200static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5201{
5202 struct drm_device *dev = crtc->dev;
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5205 int pipe = intel_crtc->pipe;
5206 uint16_t coeff = 0x7800; /* 1.0 */
5207
5208 /*
5209 * TODO: Check what kind of values actually come out of the pipe
5210 * with these coeff/postoff values and adjust to get the best
5211 * accuracy. Perhaps we even need to take the bpc value into
5212 * consideration.
5213 */
5214
50f3b016 5215 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5216 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5217
5218 /*
5219 * GY/GU and RY/RU should be the other way around according
5220 * to BSpec, but reality doesn't agree. Just set them up in
5221 * a way that results in the correct picture.
5222 */
5223 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5224 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5225
5226 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5227 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5228
5229 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5230 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5231
5232 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5233 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5234 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5235
5236 if (INTEL_INFO(dev)->gen > 6) {
5237 uint16_t postoff = 0;
5238
50f3b016 5239 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5240 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5241
5242 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5243 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5244 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5245
5246 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5247 } else {
5248 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5249
50f3b016 5250 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5251 mode |= CSC_BLACK_SCREEN_OFFSET;
5252
5253 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5254 }
5255}
5256
ee2b0b38 5257static void haswell_set_pipeconf(struct drm_crtc *crtc,
d8b32247 5258 struct drm_display_mode *adjusted_mode)
ee2b0b38
PZ		 5259{
5260 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5262 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5263 uint32_t val;
5264
702e7a56 5265 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5266
5267 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5268 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5269 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5270
5271 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5272 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5273 val |= PIPECONF_INTERLACED_ILK;
5274 else
5275 val |= PIPECONF_PROGRESSIVE;
5276
702e7a56
PZ		 5277 I915_WRITE(PIPECONF(cpu_transcoder), val);
5278 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5279}
5280
6591c6e4
PZ		 5281static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5282 struct drm_display_mode *adjusted_mode,
5283 intel_clock_t *clock,
5284 bool *has_reduced_clock,
5285 intel_clock_t *reduced_clock)
5286{
5287 struct drm_device *dev = crtc->dev;
5288 struct drm_i915_private *dev_priv = dev->dev_private;
5289 struct intel_encoder *intel_encoder;
5290 int refclk;
d4906093 5291 const intel_limit_t *limit;
6591c6e4 5292 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5293
6591c6e4
PZ		 5294 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5295 switch (intel_encoder->type) {
79e53945
JB		 5296 case INTEL_OUTPUT_LVDS:
5297 is_lvds = true;
5298 break;
5299 case INTEL_OUTPUT_SDVO:
7d57382e 5300 case INTEL_OUTPUT_HDMI:
79e53945 5301 is_sdvo = true;
6591c6e4 5302 if (intel_encoder->needs_tv_clock)
e2f0ba97 5303 is_tv = true;
79e53945 5304 break;
79e53945
JB		 5305 case INTEL_OUTPUT_TVOUT:
5306 is_tv = true;
5307 break;
79e53945
JB		 5308 }
5309 }
5310
d9d444cb 5311 refclk = ironlake_get_refclk(crtc);
79e53945 5312
d4906093
ML		 5313 /*
5314 * Returns a set of divisors for the desired target clock with the given
5315 * refclk, or FALSE. The returned values represent the clock equation:
5316 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5317 */
1b894b59 5318 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5319 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5320 clock);
5321 if (!ret)
5322 return false;
cda4b7d3 5323
ddc9003c 5324 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5325 /*
5326 * Ensure we match the reduced clock's P to the target clock.
5327 * If the clocks don't match, we can't switch the display clock
5328 * by using the FP0/FP1. In such case we will disable the LVDS
5329 * downclock feature.
5330 */
6591c6e4
PZ		 5331 *has_reduced_clock = limit->find_pll(limit, crtc,
5332 dev_priv->lvds_downclock,
5333 refclk,
5334 clock,
5335 reduced_clock);
652c393a 5336 }
61e9653f
DV		 5337
5338 if (is_sdvo && is_tv)
f47709a9 5339 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5340
5341 return true;
5342}
5343
01a415fd
DV		 5344static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5345{
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347 uint32_t temp;
5348
5349 temp = I915_READ(SOUTH_CHICKEN1);
5350 if (temp & FDI_BC_BIFURCATION_SELECT)
5351 return;
5352
5353 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5354 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5355
5356 temp |= FDI_BC_BIFURCATION_SELECT;
5357 DRM_DEBUG_KMS("enabling fdi C rx\n");
5358 I915_WRITE(SOUTH_CHICKEN1, temp);
5359 POSTING_READ(SOUTH_CHICKEN1);
5360}
5361
5362static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5363{
5364 struct drm_device *dev = intel_crtc->base.dev;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 struct intel_crtc *pipe_B_crtc =
5367 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5368
84f44ce7
VS		 5369 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5370 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd 5371 if (intel_crtc->fdi_lanes > 4) {
84f44ce7
VS		 5372 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5373 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5374 /* Clamp lanes to avoid programming the hw with bogus values. */
5375 intel_crtc->fdi_lanes = 4;
5376
5377 return false;
5378 }
5379
7eb552ae 5380 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5381 return true;
5382
5383 switch (intel_crtc->pipe) {
5384 case PIPE_A:
5385 return true;
5386 case PIPE_B:
5387 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5388 intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5389 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5390 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5391 /* Clamp lanes to avoid programming the hw with bogus values. */
5392 intel_crtc->fdi_lanes = 2;
5393
5394 return false;
5395 }
5396
5397 if (intel_crtc->fdi_lanes > 2)
5398 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5399 else
5400 cpt_enable_fdi_bc_bifurcation(dev);
5401
5402 return true;
5403 case PIPE_C:
5404 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5405 if (intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5406 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5407 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5408 /* Clamp lanes to avoid programming the hw with bogus values. */
5409 intel_crtc->fdi_lanes = 2;
5410
5411 return false;
5412 }
5413 } else {
5414 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5415 return false;
5416 }
5417
5418 cpt_enable_fdi_bc_bifurcation(dev);
5419
5420 return true;
5421 default:
5422 BUG();
5423 }
5424}
5425
d4b1931c
PZ		 5426int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5427{
5428 /*
5429 * Account for spread spectrum to avoid
5430 * oversubscribing the link. Max center spread
5431 * is 2.5%; use 5% for safety's sake.
5432 */
5433 u32 bps = target_clock * bpp * 21 / 20;
5434 return bps / (link_bw * 8) + 1;
5435}
5436
6cf86a5e
DV		 5437void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5438 struct intel_link_m_n *m_n)
79e53945 5439{
6cf86a5e
DV		 5440 struct drm_device *dev = crtc->base.dev;
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 int pipe = crtc->pipe;
5443
5444 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5445 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5446 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5447 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5448}
5449
5450void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5451 struct intel_link_m_n *m_n)
5452{
5453 struct drm_device *dev = crtc->base.dev;
79e53945 5454 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5455 int pipe = crtc->pipe;
3b117c8f 5456 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5457
5458 if (INTEL_INFO(dev)->gen >= 5) {
5459 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5460 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5461 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5462 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5463 } else {
5464 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5465 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5466 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5467 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5468 }
5469}
5470
5471static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5472{
5473 struct drm_device *dev = crtc->dev;
79e53945 5474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5475 struct drm_display_mode *adjusted_mode =
5476 &intel_crtc->config.adjusted_mode;
e69d0bc1 5477 struct intel_link_m_n m_n = {0};
6cc5f341 5478 int target_clock, lane, link_bw;
61e9653f 5479
6cf86a5e
DV		 5480 /* FDI is a binary signal running at ~2.7GHz, encoding
5481 * each output octet as 10 bits. The actual frequency
5482 * is stored as a divider into a 100MHz clock, and the
5483 * mode pixel clock is stored in units of 1KHz.
5484 * Hence the bw of each lane in terms of the mode signal
5485 * is:
5486 */
5487 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5488
df92b1e6
DV		 5489 if (intel_crtc->config.pixel_target_clock)
5490 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5491 else
5492 target_clock = adjusted_mode->clock;
5493
6cf86a5e
DV		 5494 lane = ironlake_get_lanes_required(target_clock, link_bw,
5495 intel_crtc->config.pipe_bpp);
2c07245f 5496
8febb297
EA		 5497 intel_crtc->fdi_lanes = lane;
5498
6cc5f341
DV		 5499 if (intel_crtc->config.pixel_multiplier > 1)
5500 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5501 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5502 link_bw, &m_n);
8febb297 5503
6cf86a5e 5504 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5505}
5506
7429e9d4
DV		 5507static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5508{
5509 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5510}
5511
de13a2e3 5512static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5513 u32 *fp,
9a7c7890 5514 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5515{
de13a2e3 5516 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5517 struct drm_device *dev = crtc->dev;
5518 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5519 struct intel_encoder *intel_encoder;
5520 uint32_t dpll;
6cc5f341 5521 int factor, num_connectors = 0;
de13a2e3 5522 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5523
de13a2e3
PZ		 5524 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5525 switch (intel_encoder->type) {
79e53945
JB		 5526 case INTEL_OUTPUT_LVDS:
5527 is_lvds = true;
5528 break;
5529 case INTEL_OUTPUT_SDVO:
7d57382e 5530 case INTEL_OUTPUT_HDMI:
79e53945 5531 is_sdvo = true;
de13a2e3 5532 if (intel_encoder->needs_tv_clock)
e2f0ba97 5533 is_tv = true;
79e53945 5534 break;
79e53945
JB		 5535 case INTEL_OUTPUT_TVOUT:
5536 is_tv = true;
5537 break;
79e53945 5538 }
43565a06 5539
c751ce4f 5540 num_connectors++;
79e53945 5541 }
79e53945 5542
c1858123 5543 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5544 factor = 21;
5545 if (is_lvds) {
5546 if ((intel_panel_use_ssc(dev_priv) &&
5547 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5548 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5549 factor = 25;
5550 } else if (is_sdvo && is_tv)
5551 factor = 20;
c1858123 5552
7429e9d4 5553 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5554 *fp |= FP_CB_TUNE;
2c07245f 5555
9a7c7890
DV		 5556 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5557 *fp2 |= FP_CB_TUNE;
5558
5eddb70b 5559 dpll = 0;
2c07245f 5560
a07d6787
EA		 5561 if (is_lvds)
5562 dpll |= DPLLB_MODE_LVDS;
5563 else
5564 dpll |= DPLLB_MODE_DAC_SERIAL;
5565 if (is_sdvo) {
6cc5f341
DV		 5566 if (intel_crtc->config.pixel_multiplier > 1) {
5567 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5568 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5569 }
a07d6787
EA		 5570 dpll |= DPLL_DVO_HIGH_SPEED;
5571 }
8b47047b
DV		 5572 if (intel_crtc->config.has_dp_encoder &&
5573 intel_crtc->config.has_pch_encoder)
a07d6787 5574 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5575
a07d6787 5576 /* compute bitmask from p1 value */
7429e9d4 5577 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5578 /* also FPA1 */
7429e9d4 5579 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5580
7429e9d4 5581 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5582 case 5:
5583 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5584 break;
5585 case 7:
5586 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5587 break;
5588 case 10:
5589 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5590 break;
5591 case 14:
5592 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5593 break;
79e53945
JB		 5594 }
5595
43565a06
KH		 5596 if (is_sdvo && is_tv)
5597 dpll |= PLL_REF_INPUT_TVCLKINBC;
5598 else if (is_tv)
79e53945 5599 /* XXX: just matching BIOS for now */
43565a06 5600 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5601 dpll |= 3;
a7615030 5602 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5604 else
5605 dpll |= PLL_REF_INPUT_DREFCLK;
5606
de13a2e3
PZ		 5607 return dpll;
5608}
5609
5610static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5611 int x, int y,
5612 struct drm_framebuffer *fb)
5613{
5614 struct drm_device *dev = crtc->dev;
5615 struct drm_i915_private *dev_priv = dev->dev_private;
5616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5617 struct drm_display_mode *adjusted_mode =
5618 &intel_crtc->config.adjusted_mode;
5619 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5620 int pipe = intel_crtc->pipe;
5621 int plane = intel_crtc->plane;
5622 int num_connectors = 0;
5623 intel_clock_t clock, reduced_clock;
cbbab5bd 5624 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5625 bool ok, has_reduced_clock = false;
8b47047b 5626 bool is_lvds = false;
de13a2e3 5627 struct intel_encoder *encoder;
de13a2e3 5628 int ret;
d8b32247 5629 bool fdi_config_ok;
de13a2e3
PZ		 5630
5631 for_each_encoder_on_crtc(dev, crtc, encoder) {
5632 switch (encoder->type) {
5633 case INTEL_OUTPUT_LVDS:
5634 is_lvds = true;
5635 break;
de13a2e3
PZ		 5636 }
5637
5638 num_connectors++;
a07d6787 5639 }
79e53945 5640
5dc5298b
PZ		 5641 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5642 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5643
3b117c8f 5644 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5645
de13a2e3
PZ		 5646 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5647 &has_reduced_clock, &reduced_clock);
5648 if (!ok) {
5649 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5650 return -EINVAL;
79e53945 5651 }
f47709a9
DV		 5652 /* Compat-code for transition, will disappear. */
5653 if (!intel_crtc->config.clock_set) {
5654 intel_crtc->config.dpll.n = clock.n;
5655 intel_crtc->config.dpll.m1 = clock.m1;
5656 intel_crtc->config.dpll.m2 = clock.m2;
5657 intel_crtc->config.dpll.p1 = clock.p1;
5658 intel_crtc->config.dpll.p2 = clock.p2;
5659 }
79e53945 5660
de13a2e3
PZ		 5661 /* Ensure that the cursor is valid for the new mode before changing... */
5662 intel_crtc_update_cursor(crtc, true);
5663
84f44ce7 5664 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5665 drm_mode_debug_printmodeline(mode);
5666
5dc5298b 5667 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5668 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5669 struct intel_pch_pll *pll;
4b645f14 5670
7429e9d4 5671 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5672 if (has_reduced_clock)
7429e9d4 5673 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5674
7429e9d4 5675 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5676 &fp, &reduced_clock,
5677 has_reduced_clock ? &fp2 : NULL);
5678
ee7b9f93
JB		 5679 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5680 if (pll == NULL) {
84f44ce7
VS		 5681 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5682 pipe_name(pipe));
4b645f14
JB		 5683 return -EINVAL;
5684 }
ee7b9f93
JB		 5685 } else
5686 intel_put_pch_pll(intel_crtc);
79e53945 5687
03afc4a2
DV		 5688 if (intel_crtc->config.has_dp_encoder)
5689 intel_dp_set_m_n(intel_crtc);
79e53945 5690
dafd226c
DV		 5691 for_each_encoder_on_crtc(dev, crtc, encoder)
5692 if (encoder->pre_pll_enable)
5693 encoder->pre_pll_enable(encoder);
79e53945 5694
ee7b9f93
JB		 5695 if (intel_crtc->pch_pll) {
5696 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5697
32f9d658 5698 /* Wait for the clocks to stabilize. */
ee7b9f93 5699 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5700 udelay(150);
5701
8febb297
EA		 5702 /* The pixel multiplier can only be updated once the
5703 * DPLL is enabled and the clocks are stable.
5704 *
5705 * So write it again.
5706 */
ee7b9f93 5707 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5708 }
79e53945 5709
5eddb70b 5710 intel_crtc->lowfreq_avail = false;
ee7b9f93 5711 if (intel_crtc->pch_pll) {
4b645f14 5712 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5713 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5714 intel_crtc->lowfreq_avail = true;
4b645f14 5715 } else {
ee7b9f93 5716 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5717 }
5718 }
5719
b0e77b9c 5720 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5721
01a415fd
DV		 5722 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5723 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5724 intel_crtc->fdi_lanes = 0;
5725 if (intel_crtc->config.has_pch_encoder)
5726 ironlake_fdi_set_m_n(crtc);
2c07245f 5727
01a415fd 5728 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5729
d8b32247 5730 ironlake_set_pipeconf(crtc, adjusted_mode);
79e53945 5731
a1f9e77e
PZ		 5732 /* Set up the display plane register */
5733 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5734 POSTING_READ(DSPCNTR(plane));
79e53945 5735
94352cf9 5736 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5737
5738 intel_update_watermarks(dev);
5739
1f8eeabf
ED		 5740 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5741
01a415fd 5742 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5743}
5744
0e8ffe1b
DV		 5745static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5746 struct intel_crtc_config *pipe_config)
5747{
5748 struct drm_device *dev = crtc->base.dev;
5749 struct drm_i915_private *dev_priv = dev->dev_private;
5750 uint32_t tmp;
5751
5752 tmp = I915_READ(PIPECONF(crtc->pipe));
5753 if (!(tmp & PIPECONF_ENABLE))
5754 return false;
5755
88adfff1
DV		 5756 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5757 pipe_config->has_pch_encoder = true;
5758
0e8ffe1b
DV		 5759 return true;
5760}
5761
d6dd9eb1
DV		 5762static void haswell_modeset_global_resources(struct drm_device *dev)
5763{
5764 struct drm_i915_private *dev_priv = dev->dev_private;
5765 bool enable = false;
5766 struct intel_crtc *crtc;
5767 struct intel_encoder *encoder;
5768
5769 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5770 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5771 enable = true;
5772 /* XXX: Should check for edp transcoder here, but thanks to init
5773 * sequence that's not yet available. Just in case desktop eDP
5774 * on PORT D is possible on haswell, too. */
5775 }
5776
5777 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5778 base.head) {
5779 if (encoder->type != INTEL_OUTPUT_EDP &&
5780 encoder->connectors_active)
5781 enable = true;
5782 }
5783
5784 /* Even the eDP panel fitter is outside the always-on well. */
5785 if (dev_priv->pch_pf_size)
5786 enable = true;
5787
5788 intel_set_power_well(dev, enable);
5789}
5790
09b4ddf9 5791static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5792 int x, int y,
5793 struct drm_framebuffer *fb)
5794{
5795 struct drm_device *dev = crtc->dev;
5796 struct drm_i915_private *dev_priv = dev->dev_private;
5797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5798 struct drm_display_mode *adjusted_mode =
5799 &intel_crtc->config.adjusted_mode;
5800 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5801 int pipe = intel_crtc->pipe;
5802 int plane = intel_crtc->plane;
5803 int num_connectors = 0;
8b47047b 5804 bool is_cpu_edp = false;
09b4ddf9 5805 struct intel_encoder *encoder;
09b4ddf9 5806 int ret;
09b4ddf9
PZ		 5807
5808 for_each_encoder_on_crtc(dev, crtc, encoder) {
5809 switch (encoder->type) {
09b4ddf9 5810 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5811 if (!intel_encoder_is_pch_edp(&encoder->base))
5812 is_cpu_edp = true;
5813 break;
5814 }
5815
5816 num_connectors++;
5817 }
5818
bba2181c 5819 if (is_cpu_edp)
3b117c8f 5820 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5821 else
3b117c8f 5822 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5823
5dc5298b
PZ		 5824 /* We are not sure yet this won't happen. */
5825 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5826 INTEL_PCH_TYPE(dev));
5827
5828 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5829 num_connectors, pipe_name(pipe));
5830
3b117c8f 5831 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5832 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5833
5834 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5835
6441ab5f
PZ		 5836 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5837 return -EINVAL;
5838
09b4ddf9
PZ		 5839 /* Ensure that the cursor is valid for the new mode before changing... */
5840 intel_crtc_update_cursor(crtc, true);
5841
84f44ce7 5842 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5843 drm_mode_debug_printmodeline(mode);
5844
03afc4a2
DV		 5845 if (intel_crtc->config.has_dp_encoder)
5846 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5847
5848 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5849
5850 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5851
6cf86a5e
DV		 5852 if (intel_crtc->config.has_pch_encoder)
5853 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5854
d8b32247 5855 haswell_set_pipeconf(crtc, adjusted_mode);
09b4ddf9 5856
50f3b016 5857 intel_set_pipe_csc(crtc);
86d3efce 5858
09b4ddf9 5859 /* Set up the display plane register */
86d3efce 5860 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5861 POSTING_READ(DSPCNTR(plane));
5862
5863 ret = intel_pipe_set_base(crtc, x, y, fb);
5864
5865 intel_update_watermarks(dev);
5866
5867 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5868
1f803ee5 5869 return ret;
79e53945
JB		 5870}
5871
0e8ffe1b
DV		 5872static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5873 struct intel_crtc_config *pipe_config)
5874{
5875 struct drm_device *dev = crtc->base.dev;
5876 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5877 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5878 uint32_t tmp;
5879
2bfce950
PZ		 5880 if (!intel_using_power_well(dev_priv->dev) &&
5881 cpu_transcoder != TRANSCODER_EDP)
5882 return false;
5883
5884 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5885 if (!(tmp & PIPECONF_ENABLE))
5886 return false;
5887
88adfff1 5888 /*
f196e6be 5889 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5890 * DDI E. So just check whether this pipe is wired to DDI E and whether
5891 * the PCH transcoder is on.
5892 */
f196e6be 5893 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1
DV		 5894 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5895 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5896 pipe_config->has_pch_encoder = true;
5897
0e8ffe1b
DV		 5898 return true;
5899}
5900
f564048e 5901static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5902 int x, int y,
94352cf9 5903 struct drm_framebuffer *fb)
f564048e
EA		 5904{
5905 struct drm_device *dev = crtc->dev;
5906 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5907 struct drm_encoder_helper_funcs *encoder_funcs;
5908 struct intel_encoder *encoder;
0b701d27 5909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5910 struct drm_display_mode *adjusted_mode =
5911 &intel_crtc->config.adjusted_mode;
5912 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5913 int pipe = intel_crtc->pipe;
f564048e
EA		 5914 int ret;
5915
0b701d27 5916 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5917
b8cecdf5
DV		 5918 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5919
79e53945 5920 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5921
9256aa19
DV		 5922 if (ret != 0)
5923 return ret;
5924
5925 for_each_encoder_on_crtc(dev, crtc, encoder) {
5926 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5927 encoder->base.base.id,
5928 drm_get_encoder_name(&encoder->base),
5929 mode->base.id, mode->name);
6cc5f341
DV		 5930 if (encoder->mode_set) {
5931 encoder->mode_set(encoder);
5932 } else {
5933 encoder_funcs = encoder->base.helper_private;
5934 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5935 }
9256aa19
DV		 5936 }
5937
5938 return 0;
79e53945
JB		 5939}
5940
3a9627f4
WF		 5941static bool intel_eld_uptodate(struct drm_connector *connector,
5942 int reg_eldv, uint32_t bits_eldv,
5943 int reg_elda, uint32_t bits_elda,
5944 int reg_edid)
5945{
5946 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5947 uint8_t *eld = connector->eld;
5948 uint32_t i;
5949
5950 i = I915_READ(reg_eldv);
5951 i &= bits_eldv;
5952
5953 if (!eld[0])
5954 return !i;
5955
5956 if (!i)
5957 return false;
5958
5959 i = I915_READ(reg_elda);
5960 i &= ~bits_elda;
5961 I915_WRITE(reg_elda, i);
5962
5963 for (i = 0; i < eld[2]; i++)
5964 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5965 return false;
5966
5967 return true;
5968}
5969
e0dac65e
WF		 5970static void g4x_write_eld(struct drm_connector *connector,
5971 struct drm_crtc *crtc)
5972{
5973 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5974 uint8_t *eld = connector->eld;
5975 uint32_t eldv;
5976 uint32_t len;
5977 uint32_t i;
5978
5979 i = I915_READ(G4X_AUD_VID_DID);
5980
5981 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5982 eldv = G4X_ELDV_DEVCL_DEVBLC;
5983 else
5984 eldv = G4X_ELDV_DEVCTG;
5985
3a9627f4
WF		 5986 if (intel_eld_uptodate(connector,
5987 G4X_AUD_CNTL_ST, eldv,
5988 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5989 G4X_HDMIW_HDMIEDID))
5990 return;
5991
e0dac65e
WF		 5992 i = I915_READ(G4X_AUD_CNTL_ST);
5993 i &= ~(eldv | G4X_ELD_ADDR);
5994 len = (i >> 9) & 0x1f; /* ELD buffer size */
5995 I915_WRITE(G4X_AUD_CNTL_ST, i);
5996
5997 if (!eld[0])
5998 return;
5999
6000 len = min_t(uint8_t, eld[2], len);
6001 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6002 for (i = 0; i < len; i++)
6003 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6004
6005 i = I915_READ(G4X_AUD_CNTL_ST);
6006 i |= eldv;
6007 I915_WRITE(G4X_AUD_CNTL_ST, i);
6008}
6009
83358c85
WX		 6010static void haswell_write_eld(struct drm_connector *connector,
6011 struct drm_crtc *crtc)
6012{
6013 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6014 uint8_t *eld = connector->eld;
6015 struct drm_device *dev = crtc->dev;
7b9f35a6 6016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6017 uint32_t eldv;
6018 uint32_t i;
6019 int len;
6020 int pipe = to_intel_crtc(crtc)->pipe;
6021 int tmp;
6022
6023 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6024 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6025 int aud_config = HSW_AUD_CFG(pipe);
6026 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6027
6028
6029 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6030
6031 /* Audio output enable */
6032 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6033 tmp = I915_READ(aud_cntrl_st2);
6034 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6035 I915_WRITE(aud_cntrl_st2, tmp);
6036
6037 /* Wait for 1 vertical blank */
6038 intel_wait_for_vblank(dev, pipe);
6039
6040 /* Set ELD valid state */
6041 tmp = I915_READ(aud_cntrl_st2);
6042 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6043 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6044 I915_WRITE(aud_cntrl_st2, tmp);
6045 tmp = I915_READ(aud_cntrl_st2);
6046 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6047
6048 /* Enable HDMI mode */
6049 tmp = I915_READ(aud_config);
6050 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6051 /* clear N_programing_enable and N_value_index */
6052 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6053 I915_WRITE(aud_config, tmp);
6054
6055 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6056
6057 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6058 intel_crtc->eld_vld = true;
83358c85
WX		 6059
6060 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6061 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6062 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6063 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6064 } else
6065 I915_WRITE(aud_config, 0);
6066
6067 if (intel_eld_uptodate(connector,
6068 aud_cntrl_st2, eldv,
6069 aud_cntl_st, IBX_ELD_ADDRESS,
6070 hdmiw_hdmiedid))
6071 return;
6072
6073 i = I915_READ(aud_cntrl_st2);
6074 i &= ~eldv;
6075 I915_WRITE(aud_cntrl_st2, i);
6076
6077 if (!eld[0])
6078 return;
6079
6080 i = I915_READ(aud_cntl_st);
6081 i &= ~IBX_ELD_ADDRESS;
6082 I915_WRITE(aud_cntl_st, i);
6083 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6084 DRM_DEBUG_DRIVER("port num:%d\n", i);
6085
6086 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6087 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6088 for (i = 0; i < len; i++)
6089 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6090
6091 i = I915_READ(aud_cntrl_st2);
6092 i |= eldv;
6093 I915_WRITE(aud_cntrl_st2, i);
6094
6095}
6096
e0dac65e
WF		 6097static void ironlake_write_eld(struct drm_connector *connector,
6098 struct drm_crtc *crtc)
6099{
6100 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6101 uint8_t *eld = connector->eld;
6102 uint32_t eldv;
6103 uint32_t i;
6104 int len;
6105 int hdmiw_hdmiedid;
b6daa025 6106 int aud_config;
e0dac65e
WF		 6107 int aud_cntl_st;
6108 int aud_cntrl_st2;
9b138a83 6109 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6110
b3f33cbf 6111 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6112 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6113 aud_config = IBX_AUD_CFG(pipe);
6114 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6115 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6116 } else {
9b138a83
WX		 6117 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6118 aud_config = CPT_AUD_CFG(pipe);
6119 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6120 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6121 }
6122
9b138a83 6123 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6124
6125 i = I915_READ(aud_cntl_st);
9b138a83 6126 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6127 if (!i) {
6128 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6129 /* operate blindly on all ports */
1202b4c6
WF		 6130 eldv = IBX_ELD_VALIDB;
6131 eldv |= IBX_ELD_VALIDB << 4;
6132 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6133 } else {
2582a850 6134 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6135 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6136 }
6137
3a9627f4
WF		 6138 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6139 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6140 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6141 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6142 } else
6143 I915_WRITE(aud_config, 0);
e0dac65e 6144
3a9627f4
WF		 6145 if (intel_eld_uptodate(connector,
6146 aud_cntrl_st2, eldv,
6147 aud_cntl_st, IBX_ELD_ADDRESS,
6148 hdmiw_hdmiedid))
6149 return;
6150
e0dac65e
WF		 6151 i = I915_READ(aud_cntrl_st2);
6152 i &= ~eldv;
6153 I915_WRITE(aud_cntrl_st2, i);
6154
6155 if (!eld[0])
6156 return;
6157
e0dac65e 6158 i = I915_READ(aud_cntl_st);
1202b4c6 6159 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6160 I915_WRITE(aud_cntl_st, i);
6161
6162 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6163 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6164 for (i = 0; i < len; i++)
6165 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6166
6167 i = I915_READ(aud_cntrl_st2);
6168 i |= eldv;
6169 I915_WRITE(aud_cntrl_st2, i);
6170}
6171
6172void intel_write_eld(struct drm_encoder *encoder,
6173 struct drm_display_mode *mode)
6174{
6175 struct drm_crtc *crtc = encoder->crtc;
6176 struct drm_connector *connector;
6177 struct drm_device *dev = encoder->dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179
6180 connector = drm_select_eld(encoder, mode);
6181 if (!connector)
6182 return;
6183
6184 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6185 connector->base.id,
6186 drm_get_connector_name(connector),
6187 connector->encoder->base.id,
6188 drm_get_encoder_name(connector->encoder));
6189
6190 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6191
6192 if (dev_priv->display.write_eld)
6193 dev_priv->display.write_eld(connector, crtc);
6194}
6195
79e53945
JB		 6196/** Loads the palette/gamma unit for the CRTC with the prepared values */
6197void intel_crtc_load_lut(struct drm_crtc *crtc)
6198{
6199 struct drm_device *dev = crtc->dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6202 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6203 int i;
6204
6205 /* The clocks have to be on to load the palette. */
aed3f09d 6206 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6207 return;
6208
f2b115e6 6209 /* use legacy palette for Ironlake */
bad720ff 6210 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6211 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6212
79e53945
JB		 6213 for (i = 0; i < 256; i++) {
6214 I915_WRITE(palreg + 4 * i,
6215 (intel_crtc->lut_r[i] << 16) |
6216 (intel_crtc->lut_g[i] << 8) |
6217 intel_crtc->lut_b[i]);
6218 }
6219}
6220
560b85bb
CW		 6221static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6222{
6223 struct drm_device *dev = crtc->dev;
6224 struct drm_i915_private *dev_priv = dev->dev_private;
6225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226 bool visible = base != 0;
6227 u32 cntl;
6228
6229 if (intel_crtc->cursor_visible == visible)
6230 return;
6231
9db4a9c7 6232 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6233 if (visible) {
6234 /* On these chipsets we can only modify the base whilst
6235 * the cursor is disabled.
6236 */
9db4a9c7 6237 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6238
6239 cntl &= ~(CURSOR_FORMAT_MASK);
6240 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6241 cntl |= CURSOR_ENABLE |
6242 CURSOR_GAMMA_ENABLE |
6243 CURSOR_FORMAT_ARGB;
6244 } else
6245 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6246 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6247
6248 intel_crtc->cursor_visible = visible;
6249}
6250
6251static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6252{
6253 struct drm_device *dev = crtc->dev;
6254 struct drm_i915_private *dev_priv = dev->dev_private;
6255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6256 int pipe = intel_crtc->pipe;
6257 bool visible = base != 0;
6258
6259 if (intel_crtc->cursor_visible != visible) {
548f245b 6260 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6261 if (base) {
6262 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6263 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6264 cntl |= pipe << 28; /* Connect to correct pipe */
6265 } else {
6266 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6267 cntl |= CURSOR_MODE_DISABLE;
6268 }
9db4a9c7 6269 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6270
6271 intel_crtc->cursor_visible = visible;
6272 }
6273 /* and commit changes on next vblank */
9db4a9c7 6274 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6275}
6276
65a21cd6
JB		 6277static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6278{
6279 struct drm_device *dev = crtc->dev;
6280 struct drm_i915_private *dev_priv = dev->dev_private;
6281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6282 int pipe = intel_crtc->pipe;
6283 bool visible = base != 0;
6284
6285 if (intel_crtc->cursor_visible != visible) {
6286 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6287 if (base) {
6288 cntl &= ~CURSOR_MODE;
6289 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6290 } else {
6291 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6292 cntl |= CURSOR_MODE_DISABLE;
6293 }
86d3efce
VS		 6294 if (IS_HASWELL(dev))
6295 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6296 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6297
6298 intel_crtc->cursor_visible = visible;
6299 }
6300 /* and commit changes on next vblank */
6301 I915_WRITE(CURBASE_IVB(pipe), base);
6302}
6303
cda4b7d3 6304/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6305static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6306 bool on)
cda4b7d3
CW		 6307{
6308 struct drm_device *dev = crtc->dev;
6309 struct drm_i915_private *dev_priv = dev->dev_private;
6310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6311 int pipe = intel_crtc->pipe;
6312 int x = intel_crtc->cursor_x;
6313 int y = intel_crtc->cursor_y;
560b85bb 6314 u32 base, pos;
cda4b7d3
CW		 6315 bool visible;
6316
6317 pos = 0;
6318
6b383a7f 6319 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6320 base = intel_crtc->cursor_addr;
6321 if (x > (int) crtc->fb->width)
6322 base = 0;
6323
6324 if (y > (int) crtc->fb->height)
6325 base = 0;
6326 } else
6327 base = 0;
6328
6329 if (x < 0) {
6330 if (x + intel_crtc->cursor_width < 0)
6331 base = 0;
6332
6333 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6334 x = -x;
6335 }
6336 pos |= x << CURSOR_X_SHIFT;
6337
6338 if (y < 0) {
6339 if (y + intel_crtc->cursor_height < 0)
6340 base = 0;
6341
6342 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6343 y = -y;
6344 }
6345 pos |= y << CURSOR_Y_SHIFT;
6346
6347 visible = base != 0;
560b85bb 6348 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6349 return;
6350
0cd83aa9 6351 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6352 I915_WRITE(CURPOS_IVB(pipe), pos);
6353 ivb_update_cursor(crtc, base);
6354 } else {
6355 I915_WRITE(CURPOS(pipe), pos);
6356 if (IS_845G(dev) || IS_I865G(dev))
6357 i845_update_cursor(crtc, base);
6358 else
6359 i9xx_update_cursor(crtc, base);
6360 }
cda4b7d3
CW		 6361}
6362
79e53945 6363static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6364 struct drm_file *file,
79e53945
JB		 6365 uint32_t handle,
6366 uint32_t width, uint32_t height)
6367{
6368 struct drm_device *dev = crtc->dev;
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6371 struct drm_i915_gem_object *obj;
cda4b7d3 6372 uint32_t addr;
3f8bc370 6373 int ret;
79e53945 6374
79e53945
JB		 6375 /* if we want to turn off the cursor ignore width and height */
6376 if (!handle) {
28c97730 6377 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6378 addr = 0;
05394f39 6379 obj = NULL;
5004417d 6380 mutex_lock(&dev->struct_mutex);
3f8bc370 6381 goto finish;
79e53945
JB		 6382 }
6383
6384 /* Currently we only support 64x64 cursors */
6385 if (width != 64 || height != 64) {
6386 DRM_ERROR("we currently only support 64x64 cursors\n");
6387 return -EINVAL;
6388 }
6389
05394f39 6390 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6391 if (&obj->base == NULL)
79e53945
JB		 6392 return -ENOENT;
6393
05394f39 6394 if (obj->base.size < width * height * 4) {
79e53945 6395 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6396 ret = -ENOMEM;
6397 goto fail;
79e53945
JB		 6398 }
6399
71acb5eb 6400 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6401 mutex_lock(&dev->struct_mutex);
b295d1b6 6402 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6403 unsigned alignment;
6404
d9e86c0e
CW		 6405 if (obj->tiling_mode) {
6406 DRM_ERROR("cursor cannot be tiled\n");
6407 ret = -EINVAL;
6408 goto fail_locked;
6409 }
6410
693db184
CW		 6411 /* Note that the w/a also requires 2 PTE of padding following
6412 * the bo. We currently fill all unused PTE with the shadow
6413 * page and so we should always have valid PTE following the
6414 * cursor preventing the VT-d warning.
6415 */
6416 alignment = 0;
6417 if (need_vtd_wa(dev))
6418 alignment = 64*1024;
6419
6420 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6421 if (ret) {
6422 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6423 goto fail_locked;
e7b526bb
CW		 6424 }
6425
d9e86c0e
CW		 6426 ret = i915_gem_object_put_fence(obj);
6427 if (ret) {
2da3b9b9 6428 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6429 goto fail_unpin;
6430 }
6431
05394f39 6432 addr = obj->gtt_offset;
71acb5eb 6433 } else {
6eeefaf3 6434 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6435 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6436 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6437 align);
71acb5eb
DA		 6438 if (ret) {
6439 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6440 goto fail_locked;
71acb5eb 6441 }
05394f39 6442 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6443 }
6444
a6c45cf0 6445 if (IS_GEN2(dev))
14b60391
JB		 6446 I915_WRITE(CURSIZE, (height << 12) | width);
6447
3f8bc370 6448 finish:
3f8bc370 6449 if (intel_crtc->cursor_bo) {
b295d1b6 6450 if (dev_priv->info->cursor_needs_physical) {
05394f39 6451 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6452 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6453 } else
6454 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6455 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6456 }
80824003 6457
7f9872e0 6458 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6459
6460 intel_crtc->cursor_addr = addr;
05394f39 6461 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6462 intel_crtc->cursor_width = width;
6463 intel_crtc->cursor_height = height;
6464
6b383a7f 6465 intel_crtc_update_cursor(crtc, true);
3f8bc370 6466
79e53945 6467 return 0;
e7b526bb 6468fail_unpin:
05394f39 6469 i915_gem_object_unpin(obj);
7f9872e0 6470fail_locked:
34b8686e 6471 mutex_unlock(&dev->struct_mutex);
bc9025bd 6472fail:
05394f39 6473 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6474 return ret;
79e53945
JB		 6475}
6476
6477static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6478{
79e53945 6479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6480
cda4b7d3
CW		 6481 intel_crtc->cursor_x = x;
6482 intel_crtc->cursor_y = y;
652c393a 6483
6b383a7f 6484 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6485
6486 return 0;
6487}
6488
6489/** Sets the color ramps on behalf of RandR */
6490void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6491 u16 blue, int regno)
6492{
6493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6494
6495 intel_crtc->lut_r[regno] = red >> 8;
6496 intel_crtc->lut_g[regno] = green >> 8;
6497 intel_crtc->lut_b[regno] = blue >> 8;
6498}
6499
b8c00ac5
DA		 6500void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6501 u16 *blue, int regno)
6502{
6503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6504
6505 *red = intel_crtc->lut_r[regno] << 8;
6506 *green = intel_crtc->lut_g[regno] << 8;
6507 *blue = intel_crtc->lut_b[regno] << 8;
6508}
6509
79e53945 6510static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6511 u16 *blue, uint32_t start, uint32_t size)
79e53945 6512{
7203425a 6513 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6515
7203425a 6516 for (i = start; i < end; i++) {
79e53945
JB		 6517 intel_crtc->lut_r[i] = red[i] >> 8;
6518 intel_crtc->lut_g[i] = green[i] >> 8;
6519 intel_crtc->lut_b[i] = blue[i] >> 8;
6520 }
6521
6522 intel_crtc_load_lut(crtc);
6523}
6524
79e53945
JB		 6525/* VESA 640x480x72Hz mode to set on the pipe */
6526static struct drm_display_mode load_detect_mode = {
6527 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6528 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6529};
6530
d2dff872
CW		 6531static struct drm_framebuffer *
6532intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6533 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6534 struct drm_i915_gem_object *obj)
6535{
6536 struct intel_framebuffer *intel_fb;
6537 int ret;
6538
6539 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6540 if (!intel_fb) {
6541 drm_gem_object_unreference_unlocked(&obj->base);
6542 return ERR_PTR(-ENOMEM);
6543 }
6544
6545 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6546 if (ret) {
6547 drm_gem_object_unreference_unlocked(&obj->base);
6548 kfree(intel_fb);
6549 return ERR_PTR(ret);
6550 }
6551
6552 return &intel_fb->base;
6553}
6554
6555static u32
6556intel_framebuffer_pitch_for_width(int width, int bpp)
6557{
6558 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6559 return ALIGN(pitch, 64);
6560}
6561
6562static u32
6563intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6564{
6565 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6566 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6567}
6568
6569static struct drm_framebuffer *
6570intel_framebuffer_create_for_mode(struct drm_device *dev,
6571 struct drm_display_mode *mode,
6572 int depth, int bpp)
6573{
6574 struct drm_i915_gem_object *obj;
0fed39bd 6575 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6576
6577 obj = i915_gem_alloc_object(dev,
6578 intel_framebuffer_size_for_mode(mode, bpp));
6579 if (obj == NULL)
6580 return ERR_PTR(-ENOMEM);
6581
6582 mode_cmd.width = mode->hdisplay;
6583 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6584 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6585 bpp);
5ca0c34a 6586 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6587
6588 return intel_framebuffer_create(dev, &mode_cmd, obj);
6589}
6590
6591static struct drm_framebuffer *
6592mode_fits_in_fbdev(struct drm_device *dev,
6593 struct drm_display_mode *mode)
6594{
6595 struct drm_i915_private *dev_priv = dev->dev_private;
6596 struct drm_i915_gem_object *obj;
6597 struct drm_framebuffer *fb;
6598
6599 if (dev_priv->fbdev == NULL)
6600 return NULL;
6601
6602 obj = dev_priv->fbdev->ifb.obj;
6603 if (obj == NULL)
6604 return NULL;
6605
6606 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6607 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6608 fb->bits_per_pixel))
d2dff872
CW		 6609 return NULL;
6610
01f2c773 6611 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6612 return NULL;
6613
6614 return fb;
6615}
6616
d2434ab7 6617bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6618 struct drm_display_mode *mode,
8261b191 6619 struct intel_load_detect_pipe *old)
79e53945
JB		 6620{
6621 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6622 struct intel_encoder *intel_encoder =
6623 intel_attached_encoder(connector);
79e53945 6624 struct drm_crtc *possible_crtc;
4ef69c7a 6625 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6626 struct drm_crtc *crtc = NULL;
6627 struct drm_device *dev = encoder->dev;
94352cf9 6628 struct drm_framebuffer *fb;
79e53945
JB		 6629 int i = -1;
6630
d2dff872
CW		 6631 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6632 connector->base.id, drm_get_connector_name(connector),
6633 encoder->base.id, drm_get_encoder_name(encoder));
6634
79e53945
JB		 6635 /*
6636 * Algorithm gets a little messy:
7a5e4805 6637 *
79e53945
JB		 6638 * - if the connector already has an assigned crtc, use it (but make
6639 * sure it's on first)
7a5e4805 6640 *
79e53945
JB		 6641 * - try to find the first unused crtc that can drive this connector,
6642 * and use that if we find one
79e53945
JB		 6643 */
6644
6645 /* See if we already have a CRTC for this connector */
6646 if (encoder->crtc) {
6647 crtc = encoder->crtc;
8261b191 6648
7b24056b
DV		 6649 mutex_lock(&crtc->mutex);
6650
24218aac 6651 old->dpms_mode = connector->dpms;
8261b191
CW		 6652 old->load_detect_temp = false;
6653
6654 /* Make sure the crtc and connector are running */
24218aac
DV		 6655 if (connector->dpms != DRM_MODE_DPMS_ON)
6656 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6657
7173188d 6658 return true;
79e53945
JB		 6659 }
6660
6661 /* Find an unused one (if possible) */
6662 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6663 i++;
6664 if (!(encoder->possible_crtcs & (1 << i)))
6665 continue;
6666 if (!possible_crtc->enabled) {
6667 crtc = possible_crtc;
6668 break;
6669 }
79e53945
JB		 6670 }
6671
6672 /*
6673 * If we didn't find an unused CRTC, don't use any.
6674 */
6675 if (!crtc) {
7173188d
CW		 6676 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6677 return false;
79e53945
JB		 6678 }
6679
7b24056b 6680 mutex_lock(&crtc->mutex);
fc303101
DV		 6681 intel_encoder->new_crtc = to_intel_crtc(crtc);
6682 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6683
6684 intel_crtc = to_intel_crtc(crtc);
24218aac 6685 old->dpms_mode = connector->dpms;
8261b191 6686 old->load_detect_temp = true;
d2dff872 6687 old->release_fb = NULL;
79e53945 6688
6492711d
CW		 6689 if (!mode)
6690 mode = &load_detect_mode;
79e53945 6691
d2dff872
CW		 6692 /* We need a framebuffer large enough to accommodate all accesses
6693 * that the plane may generate whilst we perform load detection.
6694 * We can not rely on the fbcon either being present (we get called
6695 * during its initialisation to detect all boot displays, or it may
6696 * not even exist) or that it is large enough to satisfy the
6697 * requested mode.
6698 */
94352cf9
DV		 6699 fb = mode_fits_in_fbdev(dev, mode);
6700 if (fb == NULL) {
d2dff872 6701 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6702 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6703 old->release_fb = fb;
d2dff872
CW		 6704 } else
6705 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6706 if (IS_ERR(fb)) {
d2dff872 6707 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6708 mutex_unlock(&crtc->mutex);
0e8b3d3e 6709 return false;
79e53945 6710 }
79e53945 6711
c0c36b94 6712 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6713 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6714 if (old->release_fb)
6715 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6716 mutex_unlock(&crtc->mutex);
0e8b3d3e 6717 return false;
79e53945 6718 }
7173188d 6719
79e53945 6720 /* let the connector get through one full cycle before testing */
9d0498a2 6721 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6722 return true;
79e53945
JB		 6723}
6724
d2434ab7 6725void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6726 struct intel_load_detect_pipe *old)
79e53945 6727{
d2434ab7
DV		 6728 struct intel_encoder *intel_encoder =
6729 intel_attached_encoder(connector);
4ef69c7a 6730 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6731 struct drm_crtc *crtc = encoder->crtc;
79e53945 6732
d2dff872
CW		 6733 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6734 connector->base.id, drm_get_connector_name(connector),
6735 encoder->base.id, drm_get_encoder_name(encoder));
6736
8261b191 6737 if (old->load_detect_temp) {
fc303101
DV		 6738 to_intel_connector(connector)->new_encoder = NULL;
6739 intel_encoder->new_crtc = NULL;
6740 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6741
36206361
DV		 6742 if (old->release_fb) {
6743 drm_framebuffer_unregister_private(old->release_fb);
6744 drm_framebuffer_unreference(old->release_fb);
6745 }
d2dff872 6746
67c96400 6747 mutex_unlock(&crtc->mutex);
0622a53c 6748 return;
79e53945
JB		 6749 }
6750
c751ce4f 6751 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6752 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6753 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6754
6755 mutex_unlock(&crtc->mutex);
79e53945
JB		 6756}
6757
6758/* Returns the clock of the currently programmed mode of the given pipe. */
6759static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6760{
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6763 int pipe = intel_crtc->pipe;
548f245b 6764 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6765 u32 fp;
6766 intel_clock_t clock;
6767
6768 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6769 fp = I915_READ(FP0(pipe));
79e53945 6770 else
39adb7a5 6771 fp = I915_READ(FP1(pipe));
79e53945
JB		 6772
6773 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6774 if (IS_PINEVIEW(dev)) {
6775 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6776 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6777 } else {
6778 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6779 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6780 }
6781
a6c45cf0 6782 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6783 if (IS_PINEVIEW(dev))
6784 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6785 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6786 else
6787 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6788 DPLL_FPA01_P1_POST_DIV_SHIFT);
6789
6790 switch (dpll & DPLL_MODE_MASK) {
6791 case DPLLB_MODE_DAC_SERIAL:
6792 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6793 5 : 10;
6794 break;
6795 case DPLLB_MODE_LVDS:
6796 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6797 7 : 14;
6798 break;
6799 default:
28c97730 6800 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6801 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6802 return 0;
6803 }
6804
6805 /* XXX: Handle the 100Mhz refclk */
2177832f 6806 intel_clock(dev, 96000, &clock);
79e53945
JB		 6807 } else {
6808 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6809
6810 if (is_lvds) {
6811 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6812 DPLL_FPA01_P1_POST_DIV_SHIFT);
6813 clock.p2 = 14;
6814
6815 if ((dpll & PLL_REF_INPUT_MASK) ==
6816 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6817 /* XXX: might not be 66MHz */
2177832f 6818 intel_clock(dev, 66000, &clock);
79e53945 6819 } else
2177832f 6820 intel_clock(dev, 48000, &clock);
79e53945
JB		 6821 } else {
6822 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6823 clock.p1 = 2;
6824 else {
6825 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6826 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6827 }
6828 if (dpll & PLL_P2_DIVIDE_BY_4)
6829 clock.p2 = 4;
6830 else
6831 clock.p2 = 2;
6832
2177832f 6833 intel_clock(dev, 48000, &clock);
79e53945
JB		 6834 }
6835 }
6836
6837 /* XXX: It would be nice to validate the clocks, but we can't reuse
6838 * i830PllIsValid() because it relies on the xf86_config connector
6839 * configuration being accurate, which it isn't necessarily.
6840 */
6841
6842 return clock.dot;
6843}
6844
6845/** Returns the currently programmed mode of the given pipe. */
6846struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6847 struct drm_crtc *crtc)
6848{
548f245b 6849 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6851 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6852 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6853 int htot = I915_READ(HTOTAL(cpu_transcoder));
6854 int hsync = I915_READ(HSYNC(cpu_transcoder));
6855 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6856 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6857
6858 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6859 if (!mode)
6860 return NULL;
6861
6862 mode->clock = intel_crtc_clock_get(dev, crtc);
6863 mode->hdisplay = (htot & 0xffff) + 1;
6864 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6865 mode->hsync_start = (hsync & 0xffff) + 1;
6866 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6867 mode->vdisplay = (vtot & 0xffff) + 1;
6868 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6869 mode->vsync_start = (vsync & 0xffff) + 1;
6870 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6871
6872 drm_mode_set_name(mode);
79e53945
JB		 6873
6874 return mode;
6875}
6876
3dec0095 6877static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6878{
6879 struct drm_device *dev = crtc->dev;
6880 drm_i915_private_t *dev_priv = dev->dev_private;
6881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6882 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6883 int dpll_reg = DPLL(pipe);
6884 int dpll;
652c393a 6885
bad720ff 6886 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6887 return;
6888
6889 if (!dev_priv->lvds_downclock_avail)
6890 return;
6891
dbdc6479 6892 dpll = I915_READ(dpll_reg);
652c393a 6893 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6894 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6895
8ac5a6d5 6896 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6897
6898 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6899 I915_WRITE(dpll_reg, dpll);
9d0498a2 6900 intel_wait_for_vblank(dev, pipe);
dbdc6479 6901
652c393a
JB		 6902 dpll = I915_READ(dpll_reg);
6903 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6904 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6905 }
652c393a
JB		 6906}
6907
6908static void intel_decrease_pllclock(struct drm_crtc *crtc)
6909{
6910 struct drm_device *dev = crtc->dev;
6911 drm_i915_private_t *dev_priv = dev->dev_private;
6912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6913
bad720ff 6914 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6915 return;
6916
6917 if (!dev_priv->lvds_downclock_avail)
6918 return;
6919
6920 /*
6921 * Since this is called by a timer, we should never get here in
6922 * the manual case.
6923 */
6924 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6925 int pipe = intel_crtc->pipe;
6926 int dpll_reg = DPLL(pipe);
6927 int dpll;
f6e5b160 6928
44d98a61 6929 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6930
8ac5a6d5 6931 assert_panel_unlocked(dev_priv, pipe);
652c393a 6932
dc257cf1 6933 dpll = I915_READ(dpll_reg);
652c393a
JB		 6934 dpll |= DISPLAY_RATE_SELECT_FPA1;
6935 I915_WRITE(dpll_reg, dpll);
9d0498a2 6936 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6937 dpll = I915_READ(dpll_reg);
6938 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6939 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6940 }
6941
6942}
6943
f047e395
CW		 6944void intel_mark_busy(struct drm_device *dev)
6945{
f047e395
CW		 6946 i915_update_gfx_val(dev->dev_private);
6947}
6948
6949void intel_mark_idle(struct drm_device *dev)
652c393a 6950{
652c393a 6951 struct drm_crtc *crtc;
652c393a
JB		 6952
6953 if (!i915_powersave)
6954 return;
6955
652c393a 6956 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6957 if (!crtc->fb)
6958 continue;
6959
725a5b54 6960 intel_decrease_pllclock(crtc);
652c393a 6961 }
652c393a
JB		 6962}
6963
725a5b54 6964void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6965{
f047e395
CW		 6966 struct drm_device *dev = obj->base.dev;
6967 struct drm_crtc *crtc;
652c393a 6968
f047e395 6969 if (!i915_powersave)
acb87dfb
CW		 6970 return;
6971
652c393a
JB		 6972 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6973 if (!crtc->fb)
6974 continue;
6975
f047e395 6976 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6977 intel_increase_pllclock(crtc);
652c393a
JB		 6978 }
6979}
6980
79e53945
JB		 6981static void intel_crtc_destroy(struct drm_crtc *crtc)
6982{
6983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6984 struct drm_device *dev = crtc->dev;
6985 struct intel_unpin_work *work;
6986 unsigned long flags;
6987
6988 spin_lock_irqsave(&dev->event_lock, flags);
6989 work = intel_crtc->unpin_work;
6990 intel_crtc->unpin_work = NULL;
6991 spin_unlock_irqrestore(&dev->event_lock, flags);
6992
6993 if (work) {
6994 cancel_work_sync(&work->work);
6995 kfree(work);
6996 }
79e53945
JB		 6997
6998 drm_crtc_cleanup(crtc);
67e77c5a 6999
79e53945
JB		 7000 kfree(intel_crtc);
7001}
7002
6b95a207
KH		 7003static void intel_unpin_work_fn(struct work_struct *__work)
7004{
7005 struct intel_unpin_work *work =
7006 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7007 struct drm_device *dev = work->crtc->dev;
6b95a207 7008
b4a98e57 7009 mutex_lock(&dev->struct_mutex);
1690e1eb 7010 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7011 drm_gem_object_unreference(&work->pending_flip_obj->base);
7012 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7013
b4a98e57
CW		 7014 intel_update_fbc(dev);
7015 mutex_unlock(&dev->struct_mutex);
7016
7017 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7018 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7019
6b95a207
KH		 7020 kfree(work);
7021}
7022
1afe3e9d 7023static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7024 struct drm_crtc *crtc)
6b95a207
KH		 7025{
7026 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7028 struct intel_unpin_work *work;
6b95a207
KH		 7029 unsigned long flags;
7030
7031 /* Ignore early vblank irqs */
7032 if (intel_crtc == NULL)
7033 return;
7034
7035 spin_lock_irqsave(&dev->event_lock, flags);
7036 work = intel_crtc->unpin_work;
e7d841ca
CW		 7037
7038 /* Ensure we don't miss a work->pending update ... */
7039 smp_rmb();
7040
7041 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7042 spin_unlock_irqrestore(&dev->event_lock, flags);
7043 return;
7044 }
7045
e7d841ca
CW		 7046 /* and that the unpin work is consistent wrt ->pending. */
7047 smp_rmb();
7048
6b95a207 7049 intel_crtc->unpin_work = NULL;
6b95a207 7050
45a066eb
RC		 7051 if (work->event)
7052 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7053
0af7e4df
MK		 7054 drm_vblank_put(dev, intel_crtc->pipe);
7055
6b95a207
KH		 7056 spin_unlock_irqrestore(&dev->event_lock, flags);
7057
2c10d571 7058 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7059
7060 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7061
7062 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7063}
7064
1afe3e9d
JB		 7065void intel_finish_page_flip(struct drm_device *dev, int pipe)
7066{
7067 drm_i915_private_t *dev_priv = dev->dev_private;
7068 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7069
49b14a5c 7070 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7071}
7072
7073void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7074{
7075 drm_i915_private_t *dev_priv = dev->dev_private;
7076 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7077
49b14a5c 7078 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7079}
7080
6b95a207
KH		 7081void intel_prepare_page_flip(struct drm_device *dev, int plane)
7082{
7083 drm_i915_private_t *dev_priv = dev->dev_private;
7084 struct intel_crtc *intel_crtc =
7085 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7086 unsigned long flags;
7087
e7d841ca
CW		 7088 /* NB: An MMIO update of the plane base pointer will also
7089 * generate a page-flip completion irq, i.e. every modeset
7090 * is also accompanied by a spurious intel_prepare_page_flip().
7091 */
6b95a207 7092 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7093 if (intel_crtc->unpin_work)
7094 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7095 spin_unlock_irqrestore(&dev->event_lock, flags);
7096}
7097
e7d841ca
CW		 7098inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7099{
7100 /* Ensure that the work item is consistent when activating it ... */
7101 smp_wmb();
7102 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7103 /* and that it is marked active as soon as the irq could fire. */
7104 smp_wmb();
7105}
7106
8c9f3aaf
JB		 7107static int intel_gen2_queue_flip(struct drm_device *dev,
7108 struct drm_crtc *crtc,
7109 struct drm_framebuffer *fb,
7110 struct drm_i915_gem_object *obj)
7111{
7112 struct drm_i915_private *dev_priv = dev->dev_private;
7113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7114 u32 flip_mask;
6d90c952 7115 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7116 int ret;
7117
6d90c952 7118 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7119 if (ret)
83d4092b 7120 goto err;
8c9f3aaf 7121
6d90c952 7122 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7123 if (ret)
83d4092b 7124 goto err_unpin;
8c9f3aaf
JB		 7125
7126 /* Can't queue multiple flips, so wait for the previous
7127 * one to finish before executing the next.
7128 */
7129 if (intel_crtc->plane)
7130 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7131 else
7132 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7133 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7134 intel_ring_emit(ring, MI_NOOP);
7135 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7136 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7137 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7138 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7139 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7140
7141 intel_mark_page_flip_active(intel_crtc);
6d90c952 7142 intel_ring_advance(ring);
83d4092b
CW		 7143 return 0;
7144
7145err_unpin:
7146 intel_unpin_fb_obj(obj);
7147err:
8c9f3aaf
JB		 7148 return ret;
7149}
7150
7151static int intel_gen3_queue_flip(struct drm_device *dev,
7152 struct drm_crtc *crtc,
7153 struct drm_framebuffer *fb,
7154 struct drm_i915_gem_object *obj)
7155{
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7158 u32 flip_mask;
6d90c952 7159 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7160 int ret;
7161
6d90c952 7162 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7163 if (ret)
83d4092b 7164 goto err;
8c9f3aaf 7165
6d90c952 7166 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7167 if (ret)
83d4092b 7168 goto err_unpin;
8c9f3aaf
JB		 7169
7170 if (intel_crtc->plane)
7171 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7172 else
7173 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7174 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7175 intel_ring_emit(ring, MI_NOOP);
7176 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7177 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7178 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7179 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7180 intel_ring_emit(ring, MI_NOOP);
7181
e7d841ca 7182 intel_mark_page_flip_active(intel_crtc);
6d90c952 7183 intel_ring_advance(ring);
83d4092b
CW		 7184 return 0;
7185
7186err_unpin:
7187 intel_unpin_fb_obj(obj);
7188err:
8c9f3aaf
JB		 7189 return ret;
7190}
7191
7192static int intel_gen4_queue_flip(struct drm_device *dev,
7193 struct drm_crtc *crtc,
7194 struct drm_framebuffer *fb,
7195 struct drm_i915_gem_object *obj)
7196{
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199 uint32_t pf, pipesrc;
6d90c952 7200 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7201 int ret;
7202
6d90c952 7203 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7204 if (ret)
83d4092b 7205 goto err;
8c9f3aaf 7206
6d90c952 7207 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7208 if (ret)
83d4092b 7209 goto err_unpin;
8c9f3aaf
JB		 7210
7211 /* i965+ uses the linear or tiled offsets from the
7212 * Display Registers (which do not change across a page-flip)
7213 * so we need only reprogram the base address.
7214 */
6d90c952
DV		 7215 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7216 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7217 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7218 intel_ring_emit(ring,
7219 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7220 obj->tiling_mode);
8c9f3aaf
JB		 7221
7222 /* XXX Enabling the panel-fitter across page-flip is so far
7223 * untested on non-native modes, so ignore it for now.
7224 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7225 */
7226 pf = 0;
7227 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7228 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7229
7230 intel_mark_page_flip_active(intel_crtc);
6d90c952 7231 intel_ring_advance(ring);
83d4092b
CW		 7232 return 0;
7233
7234err_unpin:
7235 intel_unpin_fb_obj(obj);
7236err:
8c9f3aaf
JB		 7237 return ret;
7238}
7239
7240static int intel_gen6_queue_flip(struct drm_device *dev,
7241 struct drm_crtc *crtc,
7242 struct drm_framebuffer *fb,
7243 struct drm_i915_gem_object *obj)
7244{
7245 struct drm_i915_private *dev_priv = dev->dev_private;
7246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7247 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7248 uint32_t pf, pipesrc;
7249 int ret;
7250
6d90c952 7251 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7252 if (ret)
83d4092b 7253 goto err;
8c9f3aaf 7254
6d90c952 7255 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7256 if (ret)
83d4092b 7257 goto err_unpin;
8c9f3aaf 7258
6d90c952
DV		 7259 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7260 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7261 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7262 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7263
dc257cf1
DV		 7264 /* Contrary to the suggestions in the documentation,
7265 * "Enable Panel Fitter" does not seem to be required when page
7266 * flipping with a non-native mode, and worse causes a normal
7267 * modeset to fail.
7268 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7269 */
7270 pf = 0;
8c9f3aaf 7271 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7272 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7273
7274 intel_mark_page_flip_active(intel_crtc);
6d90c952 7275 intel_ring_advance(ring);
83d4092b
CW		 7276 return 0;
7277
7278err_unpin:
7279 intel_unpin_fb_obj(obj);
7280err:
8c9f3aaf
JB		 7281 return ret;
7282}
7283
7c9017e5
JB		 7284/*
7285 * On gen7 we currently use the blit ring because (in early silicon at least)
7286 * the render ring doesn't give us interrpts for page flip completion, which
7287 * means clients will hang after the first flip is queued. Fortunately the
7288 * blit ring generates interrupts properly, so use it instead.
7289 */
7290static int intel_gen7_queue_flip(struct drm_device *dev,
7291 struct drm_crtc *crtc,
7292 struct drm_framebuffer *fb,
7293 struct drm_i915_gem_object *obj)
7294{
7295 struct drm_i915_private *dev_priv = dev->dev_private;
7296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7297 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7298 uint32_t plane_bit = 0;
7c9017e5
JB		 7299 int ret;
7300
7301 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7302 if (ret)
83d4092b 7303 goto err;
7c9017e5 7304
cb05d8de
DV		 7305 switch(intel_crtc->plane) {
7306 case PLANE_A:
7307 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7308 break;
7309 case PLANE_B:
7310 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7311 break;
7312 case PLANE_C:
7313 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7314 break;
7315 default:
7316 WARN_ONCE(1, "unknown plane in flip command\n");
7317 ret = -ENODEV;
ab3951eb 7318 goto err_unpin;
cb05d8de
DV		 7319 }
7320
7c9017e5
JB		 7321 ret = intel_ring_begin(ring, 4);
7322 if (ret)
83d4092b 7323 goto err_unpin;
7c9017e5 7324
cb05d8de 7325 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7326 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7327 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7328 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7329
7330 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7331 intel_ring_advance(ring);
83d4092b
CW		 7332 return 0;
7333
7334err_unpin:
7335 intel_unpin_fb_obj(obj);
7336err:
7c9017e5
JB		 7337 return ret;
7338}
7339
8c9f3aaf
JB		 7340static int intel_default_queue_flip(struct drm_device *dev,
7341 struct drm_crtc *crtc,
7342 struct drm_framebuffer *fb,
7343 struct drm_i915_gem_object *obj)
7344{
7345 return -ENODEV;
7346}
7347
6b95a207
KH		 7348static int intel_crtc_page_flip(struct drm_crtc *crtc,
7349 struct drm_framebuffer *fb,
7350 struct drm_pending_vblank_event *event)
7351{
7352 struct drm_device *dev = crtc->dev;
7353 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7354 struct drm_framebuffer *old_fb = crtc->fb;
7355 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357 struct intel_unpin_work *work;
8c9f3aaf 7358 unsigned long flags;
52e68630 7359 int ret;
6b95a207 7360
e6a595d2
VS		 7361 /* Can't change pixel format via MI display flips. */
7362 if (fb->pixel_format != crtc->fb->pixel_format)
7363 return -EINVAL;
7364
7365 /*
7366 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7367 * Note that pitch changes could also affect these register.
7368 */
7369 if (INTEL_INFO(dev)->gen > 3 &&
7370 (fb->offsets[0] != crtc->fb->offsets[0] ||
7371 fb->pitches[0] != crtc->fb->pitches[0]))
7372 return -EINVAL;
7373
6b95a207
KH		 7374 work = kzalloc(sizeof *work, GFP_KERNEL);
7375 if (work == NULL)
7376 return -ENOMEM;
7377
6b95a207 7378 work->event = event;
b4a98e57 7379 work->crtc = crtc;
4a35f83b 7380 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7381 INIT_WORK(&work->work, intel_unpin_work_fn);
7382
7317c75e
JB		 7383 ret = drm_vblank_get(dev, intel_crtc->pipe);
7384 if (ret)
7385 goto free_work;
7386
6b95a207
KH		 7387 /* We borrow the event spin lock for protecting unpin_work */
7388 spin_lock_irqsave(&dev->event_lock, flags);
7389 if (intel_crtc->unpin_work) {
7390 spin_unlock_irqrestore(&dev->event_lock, flags);
7391 kfree(work);
7317c75e 7392 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7393
7394 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7395 return -EBUSY;
7396 }
7397 intel_crtc->unpin_work = work;
7398 spin_unlock_irqrestore(&dev->event_lock, flags);
7399
b4a98e57
CW		 7400 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7401 flush_workqueue(dev_priv->wq);
7402
79158103
CW		 7403 ret = i915_mutex_lock_interruptible(dev);
7404 if (ret)
7405 goto cleanup;
6b95a207 7406
75dfca80 7407 /* Reference the objects for the scheduled work. */
05394f39
CW		 7408 drm_gem_object_reference(&work->old_fb_obj->base);
7409 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7410
7411 crtc->fb = fb;
96b099fd 7412
e1f99ce6 7413 work->pending_flip_obj = obj;
e1f99ce6 7414
4e5359cd
SF		 7415 work->enable_stall_check = true;
7416
b4a98e57 7417 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7418 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7419
8c9f3aaf
JB		 7420 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7421 if (ret)
7422 goto cleanup_pending;
6b95a207 7423
7782de3b 7424 intel_disable_fbc(dev);
f047e395 7425 intel_mark_fb_busy(obj);
6b95a207
KH		 7426 mutex_unlock(&dev->struct_mutex);
7427
e5510fac
JB		 7428 trace_i915_flip_request(intel_crtc->plane, obj);
7429
6b95a207 7430 return 0;
96b099fd 7431
8c9f3aaf 7432cleanup_pending:
b4a98e57 7433 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7434 crtc->fb = old_fb;
05394f39
CW		 7435 drm_gem_object_unreference(&work->old_fb_obj->base);
7436 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7437 mutex_unlock(&dev->struct_mutex);
7438
79158103 7439cleanup:
96b099fd
CW		 7440 spin_lock_irqsave(&dev->event_lock, flags);
7441 intel_crtc->unpin_work = NULL;
7442 spin_unlock_irqrestore(&dev->event_lock, flags);
7443
7317c75e
JB		 7444 drm_vblank_put(dev, intel_crtc->pipe);
7445free_work:
96b099fd
CW		 7446 kfree(work);
7447
7448 return ret;
6b95a207
KH		 7449}
7450
f6e5b160 7451static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7452 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7453 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7454};
7455
6ed0f796 7456bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7457{
6ed0f796
DV		 7458 struct intel_encoder *other_encoder;
7459 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7460
6ed0f796
DV		 7461 if (WARN_ON(!crtc))
7462 return false;
7463
7464 list_for_each_entry(other_encoder,
7465 &crtc->dev->mode_config.encoder_list,
7466 base.head) {
7467
7468 if (&other_encoder->new_crtc->base != crtc ||
7469 encoder == other_encoder)
7470 continue;
7471 else
7472 return true;
f47166d2
CW		 7473 }
7474
6ed0f796
DV		 7475 return false;
7476}
47f1c6c9 7477
50f56119
DV		 7478static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7479 struct drm_crtc *crtc)
7480{
7481 struct drm_device *dev;
7482 struct drm_crtc *tmp;
7483 int crtc_mask = 1;
47f1c6c9 7484
50f56119 7485 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7486
50f56119 7487 dev = crtc->dev;
47f1c6c9 7488
50f56119
DV		 7489 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7490 if (tmp == crtc)
7491 break;
7492 crtc_mask <<= 1;
7493 }
47f1c6c9 7494
50f56119
DV		 7495 if (encoder->possible_crtcs & crtc_mask)
7496 return true;
7497 return false;
47f1c6c9 7498}
79e53945 7499
9a935856
DV		 7500/**
7501 * intel_modeset_update_staged_output_state
7502 *
7503 * Updates the staged output configuration state, e.g. after we've read out the
7504 * current hw state.
7505 */
7506static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7507{
9a935856
DV		 7508 struct intel_encoder *encoder;
7509 struct intel_connector *connector;
f6e5b160 7510
9a935856
DV		 7511 list_for_each_entry(connector, &dev->mode_config.connector_list,
7512 base.head) {
7513 connector->new_encoder =
7514 to_intel_encoder(connector->base.encoder);
7515 }
f6e5b160 7516
9a935856
DV		 7517 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7518 base.head) {
7519 encoder->new_crtc =
7520 to_intel_crtc(encoder->base.crtc);
7521 }
f6e5b160
CW		 7522}
7523
9a935856
DV		 7524/**
7525 * intel_modeset_commit_output_state
7526 *
7527 * This function copies the stage display pipe configuration to the real one.
7528 */
7529static void intel_modeset_commit_output_state(struct drm_device *dev)
7530{
7531 struct intel_encoder *encoder;
7532 struct intel_connector *connector;
f6e5b160 7533
9a935856
DV		 7534 list_for_each_entry(connector, &dev->mode_config.connector_list,
7535 base.head) {
7536 connector->base.encoder = &connector->new_encoder->base;
7537 }
f6e5b160 7538
9a935856
DV		 7539 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7540 base.head) {
7541 encoder->base.crtc = &encoder->new_crtc->base;
7542 }
7543}
7544
4e53c2e0
DV		 7545static int
7546pipe_config_set_bpp(struct drm_crtc *crtc,
7547 struct drm_framebuffer *fb,
7548 struct intel_crtc_config *pipe_config)
7549{
7550 struct drm_device *dev = crtc->dev;
7551 struct drm_connector *connector;
7552 int bpp;
7553
d42264b1
DV		 7554 switch (fb->pixel_format) {
7555 case DRM_FORMAT_C8:
4e53c2e0
DV		 7556 bpp = 8*3; /* since we go through a colormap */
7557 break;
d42264b1
DV		 7558 case DRM_FORMAT_XRGB1555:
7559 case DRM_FORMAT_ARGB1555:
7560 /* checked in intel_framebuffer_init already */
7561 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7562 return -EINVAL;
7563 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7564 bpp = 6*3; /* min is 18bpp */
7565 break;
d42264b1
DV		 7566 case DRM_FORMAT_XBGR8888:
7567 case DRM_FORMAT_ABGR8888:
7568 /* checked in intel_framebuffer_init already */
7569 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7570 return -EINVAL;
7571 case DRM_FORMAT_XRGB8888:
7572 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7573 bpp = 8*3;
7574 break;
d42264b1
DV		 7575 case DRM_FORMAT_XRGB2101010:
7576 case DRM_FORMAT_ARGB2101010:
7577 case DRM_FORMAT_XBGR2101010:
7578 case DRM_FORMAT_ABGR2101010:
7579 /* checked in intel_framebuffer_init already */
7580 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7581 return -EINVAL;
4e53c2e0
DV		 7582 bpp = 10*3;
7583 break;
baba133a 7584 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7585 default:
7586 DRM_DEBUG_KMS("unsupported depth\n");
7587 return -EINVAL;
7588 }
7589
4e53c2e0
DV		 7590 pipe_config->pipe_bpp = bpp;
7591
7592 /* Clamp display bpp to EDID value */
7593 list_for_each_entry(connector, &dev->mode_config.connector_list,
7594 head) {
7595 if (connector->encoder && connector->encoder->crtc != crtc)
7596 continue;
7597
7598 /* Don't use an invalid EDID bpc value */
7599 if (connector->display_info.bpc &&
7600 connector->display_info.bpc * 3 < bpp) {
7601 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7602 bpp, connector->display_info.bpc*3);
7603 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7604 }
996a2239
DV		 7605
7606 /* Clamp bpp to 8 on screens without EDID 1.4 */
7607 if (connector->display_info.bpc == 0 && bpp > 24) {
7608 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7609 bpp);
7610 pipe_config->pipe_bpp = 24;
7611 }
4e53c2e0
DV		 7612 }
7613
7614 return bpp;
7615}
7616
b8cecdf5
DV		 7617static struct intel_crtc_config *
7618intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7619 struct drm_framebuffer *fb,
b8cecdf5 7620 struct drm_display_mode *mode)
ee7b9f93 7621{
7758a113 7622 struct drm_device *dev = crtc->dev;
7758a113
DV		 7623 struct drm_encoder_helper_funcs *encoder_funcs;
7624 struct intel_encoder *encoder;
b8cecdf5 7625 struct intel_crtc_config *pipe_config;
4e53c2e0 7626 int plane_bpp;
ee7b9f93 7627
b8cecdf5
DV		 7628 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7629 if (!pipe_config)
7758a113
DV		 7630 return ERR_PTR(-ENOMEM);
7631
b8cecdf5
DV		 7632 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7633 drm_mode_copy(&pipe_config->requested_mode, mode);
7634
4e53c2e0
DV		 7635 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7636 if (plane_bpp < 0)
7637 goto fail;
7638
7758a113
DV		 7639 /* Pass our mode to the connectors and the CRTC to give them a chance to
7640 * adjust it according to limitations or connector properties, and also
7641 * a chance to reject the mode entirely.
47f1c6c9 7642 */
7758a113
DV		 7643 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7644 base.head) {
47f1c6c9 7645
7758a113
DV		 7646 if (&encoder->new_crtc->base != crtc)
7647 continue;
7ae89233
DV		 7648
7649 if (encoder->compute_config) {
7650 if (!(encoder->compute_config(encoder, pipe_config))) {
7651 DRM_DEBUG_KMS("Encoder config failure\n");
7652 goto fail;
7653 }
7654
7655 continue;
7656 }
7657
7758a113 7658 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7659 if (!(encoder_funcs->mode_fixup(&encoder->base,
7660 &pipe_config->requested_mode,
7661 &pipe_config->adjusted_mode))) {
7758a113
DV		 7662 DRM_DEBUG_KMS("Encoder fixup failed\n");
7663 goto fail;
7664 }
ee7b9f93 7665 }
47f1c6c9 7666
b8cecdf5 7667 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7668 DRM_DEBUG_KMS("CRTC fixup failed\n");
7669 goto fail;
ee7b9f93 7670 }
7758a113 7671 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7672
4e53c2e0
DV		 7673 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7674 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7675 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7676
b8cecdf5 7677 return pipe_config;
7758a113 7678fail:
b8cecdf5 7679 kfree(pipe_config);
7758a113 7680 return ERR_PTR(-EINVAL);
ee7b9f93 7681}
47f1c6c9 7682
e2e1ed41
DV		 7683/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7684 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7685static void
7686intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7687 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7688{
7689 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7690 struct drm_device *dev = crtc->dev;
7691 struct intel_encoder *encoder;
7692 struct intel_connector *connector;
7693 struct drm_crtc *tmp_crtc;
79e53945 7694
e2e1ed41 7695 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7696
e2e1ed41
DV		 7697 /* Check which crtcs have changed outputs connected to them, these need
7698 * to be part of the prepare_pipes mask. We don't (yet) support global
7699 * modeset across multiple crtcs, so modeset_pipes will only have one
7700 * bit set at most. */
7701 list_for_each_entry(connector, &dev->mode_config.connector_list,
7702 base.head) {
7703 if (connector->base.encoder == &connector->new_encoder->base)
7704 continue;
79e53945 7705
e2e1ed41
DV		 7706 if (connector->base.encoder) {
7707 tmp_crtc = connector->base.encoder->crtc;
7708
7709 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7710 }
7711
7712 if (connector->new_encoder)
7713 *prepare_pipes |=
7714 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7715 }
7716
e2e1ed41
DV		 7717 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7718 base.head) {
7719 if (encoder->base.crtc == &encoder->new_crtc->base)
7720 continue;
7721
7722 if (encoder->base.crtc) {
7723 tmp_crtc = encoder->base.crtc;
7724
7725 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7726 }
7727
7728 if (encoder->new_crtc)
7729 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7730 }
7731
e2e1ed41
DV		 7732 /* Check for any pipes that will be fully disabled ... */
7733 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7734 base.head) {
7735 bool used = false;
22fd0fab 7736
e2e1ed41
DV		 7737 /* Don't try to disable disabled crtcs. */
7738 if (!intel_crtc->base.enabled)
7739 continue;
7e7d76c3 7740
e2e1ed41
DV		 7741 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7742 base.head) {
7743 if (encoder->new_crtc == intel_crtc)
7744 used = true;
7745 }
7746
7747 if (!used)
7748 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7749 }
7750
e2e1ed41
DV		 7751
7752 /* set_mode is also used to update properties on life display pipes. */
7753 intel_crtc = to_intel_crtc(crtc);
7754 if (crtc->enabled)
7755 *prepare_pipes |= 1 << intel_crtc->pipe;
7756
b6c5164d
DV		 7757 /*
7758 * For simplicity do a full modeset on any pipe where the output routing
7759 * changed. We could be more clever, but that would require us to be
7760 * more careful with calling the relevant encoder->mode_set functions.
7761 */
e2e1ed41
DV		 7762 if (*prepare_pipes)
7763 *modeset_pipes = *prepare_pipes;
7764
7765 /* ... and mask these out. */
7766 *modeset_pipes &= ~(*disable_pipes);
7767 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7768
7769 /*
7770 * HACK: We don't (yet) fully support global modesets. intel_set_config
7771 * obies this rule, but the modeset restore mode of
7772 * intel_modeset_setup_hw_state does not.
7773 */
7774 *modeset_pipes &= 1 << intel_crtc->pipe;
7775 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7776
7777 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7778 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7779}
79e53945 7780
ea9d758d 7781static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7782{
ea9d758d 7783 struct drm_encoder *encoder;
f6e5b160 7784 struct drm_device *dev = crtc->dev;
f6e5b160 7785
ea9d758d
DV		 7786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7787 if (encoder->crtc == crtc)
7788 return true;
7789
7790 return false;
7791}
7792
7793static void
7794intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7795{
7796 struct intel_encoder *intel_encoder;
7797 struct intel_crtc *intel_crtc;
7798 struct drm_connector *connector;
7799
7800 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7801 base.head) {
7802 if (!intel_encoder->base.crtc)
7803 continue;
7804
7805 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7806
7807 if (prepare_pipes & (1 << intel_crtc->pipe))
7808 intel_encoder->connectors_active = false;
7809 }
7810
7811 intel_modeset_commit_output_state(dev);
7812
7813 /* Update computed state. */
7814 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7815 base.head) {
7816 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7817 }
7818
7819 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7820 if (!connector->encoder || !connector->encoder->crtc)
7821 continue;
7822
7823 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7824
7825 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7826 struct drm_property *dpms_property =
7827 dev->mode_config.dpms_property;
7828
ea9d758d 7829 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7830 drm_object_property_set_value(&connector->base,
68d34720
DV		 7831 dpms_property,
7832 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7833
7834 intel_encoder = to_intel_encoder(connector->encoder);
7835 intel_encoder->connectors_active = true;
7836 }
7837 }
7838
7839}
7840
25c5b266
DV		 7841#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7842 list_for_each_entry((intel_crtc), \
7843 &(dev)->mode_config.crtc_list, \
7844 base.head) \
7845 if (mask & (1 <<(intel_crtc)->pipe)) \
7846
0e8ffe1b
DV		 7847static bool
7848intel_pipe_config_compare(struct intel_crtc_config *current_config,
7849 struct intel_crtc_config *pipe_config)
7850{
88adfff1
DV		 7851 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7852 DRM_ERROR("mismatch in has_pch_encoder "
7853 "(expected %i, found %i)\n",
7854 current_config->has_pch_encoder,
7855 pipe_config->has_pch_encoder);
7856 return false;
7857 }
7858
0e8ffe1b
DV		 7859 return true;
7860}
7861
b980514c 7862void
8af6cf88
DV		 7863intel_modeset_check_state(struct drm_device *dev)
7864{
0e8ffe1b 7865 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7866 struct intel_crtc *crtc;
7867 struct intel_encoder *encoder;
7868 struct intel_connector *connector;
0e8ffe1b 7869 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7870
7871 list_for_each_entry(connector, &dev->mode_config.connector_list,
7872 base.head) {
7873 /* This also checks the encoder/connector hw state with the
7874 * ->get_hw_state callbacks. */
7875 intel_connector_check_state(connector);
7876
7877 WARN(&connector->new_encoder->base != connector->base.encoder,
7878 "connector's staged encoder doesn't match current encoder\n");
7879 }
7880
7881 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7882 base.head) {
7883 bool enabled = false;
7884 bool active = false;
7885 enum pipe pipe, tracked_pipe;
7886
7887 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7888 encoder->base.base.id,
7889 drm_get_encoder_name(&encoder->base));
7890
7891 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7892 "encoder's stage crtc doesn't match current crtc\n");
7893 WARN(encoder->connectors_active && !encoder->base.crtc,
7894 "encoder's active_connectors set, but no crtc\n");
7895
7896 list_for_each_entry(connector, &dev->mode_config.connector_list,
7897 base.head) {
7898 if (connector->base.encoder != &encoder->base)
7899 continue;
7900 enabled = true;
7901 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7902 active = true;
7903 }
7904 WARN(!!encoder->base.crtc != enabled,
7905 "encoder's enabled state mismatch "
7906 "(expected %i, found %i)\n",
7907 !!encoder->base.crtc, enabled);
7908 WARN(active && !encoder->base.crtc,
7909 "active encoder with no crtc\n");
7910
7911 WARN(encoder->connectors_active != active,
7912 "encoder's computed active state doesn't match tracked active state "
7913 "(expected %i, found %i)\n", active, encoder->connectors_active);
7914
7915 active = encoder->get_hw_state(encoder, &pipe);
7916 WARN(active != encoder->connectors_active,
7917 "encoder's hw state doesn't match sw tracking "
7918 "(expected %i, found %i)\n",
7919 encoder->connectors_active, active);
7920
7921 if (!encoder->base.crtc)
7922 continue;
7923
7924 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7925 WARN(active && pipe != tracked_pipe,
7926 "active encoder's pipe doesn't match"
7927 "(expected %i, found %i)\n",
7928 tracked_pipe, pipe);
7929
7930 }
7931
7932 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7933 base.head) {
7934 bool enabled = false;
7935 bool active = false;
7936
7937 DRM_DEBUG_KMS("[CRTC:%d]\n",
7938 crtc->base.base.id);
7939
7940 WARN(crtc->active && !crtc->base.enabled,
7941 "active crtc, but not enabled in sw tracking\n");
7942
7943 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7944 base.head) {
7945 if (encoder->base.crtc != &crtc->base)
7946 continue;
7947 enabled = true;
7948 if (encoder->connectors_active)
7949 active = true;
7950 }
7951 WARN(active != crtc->active,
7952 "crtc's computed active state doesn't match tracked active state "
7953 "(expected %i, found %i)\n", active, crtc->active);
7954 WARN(enabled != crtc->base.enabled,
7955 "crtc's computed enabled state doesn't match tracked enabled state "
7956 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7957
88adfff1 7958 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 7959 active = dev_priv->display.get_pipe_config(crtc,
7960 &pipe_config);
7961 WARN(crtc->active != active,
7962 "crtc active state doesn't match with hw state "
7963 "(expected %i, found %i)\n", crtc->active, active);
7964
7965 WARN(active &&
7966 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7967 "pipe state doesn't match!\n");
8af6cf88
DV		 7968 }
7969}
7970
f30da187
DV		 7971static int __intel_set_mode(struct drm_crtc *crtc,
7972 struct drm_display_mode *mode,
7973 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7974{
7975 struct drm_device *dev = crtc->dev;
dbf2b54e 7976 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7977 struct drm_display_mode *saved_mode, *saved_hwmode;
7978 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7979 struct intel_crtc *intel_crtc;
7980 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7981 int ret = 0;
a6778b3c 7982
3ac18232 7983 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7984 if (!saved_mode)
7985 return -ENOMEM;
3ac18232 7986 saved_hwmode = saved_mode + 1;
a6778b3c 7987
e2e1ed41 7988 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7989 &prepare_pipes, &disable_pipes);
7990
3ac18232
TG		 7991 *saved_hwmode = crtc->hwmode;
7992 *saved_mode = crtc->mode;
a6778b3c 7993
25c5b266
DV		 7994 /* Hack: Because we don't (yet) support global modeset on multiple
7995 * crtcs, we don't keep track of the new mode for more than one crtc.
7996 * Hence simply check whether any bit is set in modeset_pipes in all the
7997 * pieces of code that are not yet converted to deal with mutliple crtcs
7998 * changing their mode at the same time. */
25c5b266 7999 if (modeset_pipes) {
4e53c2e0 8000 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8001 if (IS_ERR(pipe_config)) {
8002 ret = PTR_ERR(pipe_config);
8003 pipe_config = NULL;
8004
3ac18232 8005 goto out;
25c5b266 8006 }
25c5b266 8007 }
a6778b3c 8008
460da916
DV		 8009 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8010 intel_crtc_disable(&intel_crtc->base);
8011
ea9d758d
DV		 8012 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8013 if (intel_crtc->base.enabled)
8014 dev_priv->display.crtc_disable(&intel_crtc->base);
8015 }
a6778b3c 8016
6c4c86f5
DV		 8017 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8018 * to set it here already despite that we pass it down the callchain.
f6e5b160 8019 */
b8cecdf5 8020 if (modeset_pipes) {
3b117c8f 8021 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8022 crtc->mode = *mode;
b8cecdf5
DV		 8023 /* mode_set/enable/disable functions rely on a correct pipe
8024 * config. */
8025 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8026 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8027 }
7758a113 8028
ea9d758d
DV		 8029 /* Only after disabling all output pipelines that will be changed can we
8030 * update the the output configuration. */
8031 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8032
47fab737
DV		 8033 if (dev_priv->display.modeset_global_resources)
8034 dev_priv->display.modeset_global_resources(dev);
8035
a6778b3c
DV		 8036 /* Set up the DPLL and any encoders state that needs to adjust or depend
8037 * on the DPLL.
f6e5b160 8038 */
25c5b266 8039 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8040 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8041 x, y, fb);
8042 if (ret)
8043 goto done;
a6778b3c
DV		 8044 }
8045
8046 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8047 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8048 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8049
25c5b266
DV		 8050 if (modeset_pipes) {
8051 /* Store real post-adjustment hardware mode. */
b8cecdf5 8052 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8053
25c5b266
DV		 8054 /* Calculate and store various constants which
8055 * are later needed by vblank and swap-completion
8056 * timestamping. They are derived from true hwmode.
8057 */
8058 drm_calc_timestamping_constants(crtc);
8059 }
a6778b3c
DV		 8060
8061 /* FIXME: add subpixel order */
8062done:
c0c36b94 8063 if (ret && crtc->enabled) {
3ac18232
TG		 8064 crtc->hwmode = *saved_hwmode;
8065 crtc->mode = *saved_mode;
a6778b3c
DV		 8066 }
8067
3ac18232 8068out:
b8cecdf5 8069 kfree(pipe_config);
3ac18232 8070 kfree(saved_mode);
a6778b3c 8071 return ret;
f6e5b160
CW		 8072}
8073
f30da187
DV		 8074int intel_set_mode(struct drm_crtc *crtc,
8075 struct drm_display_mode *mode,
8076 int x, int y, struct drm_framebuffer *fb)
8077{
8078 int ret;
8079
8080 ret = __intel_set_mode(crtc, mode, x, y, fb);
8081
8082 if (ret == 0)
8083 intel_modeset_check_state(crtc->dev);
8084
8085 return ret;
8086}
8087
c0c36b94
CW		 8088void intel_crtc_restore_mode(struct drm_crtc *crtc)
8089{
8090 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8091}
8092
25c5b266
DV		 8093#undef for_each_intel_crtc_masked
8094
d9e55608
DV		 8095static void intel_set_config_free(struct intel_set_config *config)
8096{
8097 if (!config)
8098 return;
8099
1aa4b628
DV		 8100 kfree(config->save_connector_encoders);
8101 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8102 kfree(config);
8103}
8104
85f9eb71
DV		 8105static int intel_set_config_save_state(struct drm_device *dev,
8106 struct intel_set_config *config)
8107{
85f9eb71
DV		 8108 struct drm_encoder *encoder;
8109 struct drm_connector *connector;
8110 int count;
8111
1aa4b628
DV		 8112 config->save_encoder_crtcs =
8113 kcalloc(dev->mode_config.num_encoder,
8114 sizeof(struct drm_crtc *), GFP_KERNEL);
8115 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8116 return -ENOMEM;
8117
1aa4b628
DV		 8118 config->save_connector_encoders =
8119 kcalloc(dev->mode_config.num_connector,
8120 sizeof(struct drm_encoder *), GFP_KERNEL);
8121 if (!config->save_connector_encoders)
85f9eb71
DV		 8122 return -ENOMEM;
8123
8124 /* Copy data. Note that driver private data is not affected.
8125 * Should anything bad happen only the expected state is
8126 * restored, not the drivers personal bookkeeping.
8127 */
85f9eb71
DV		 8128 count = 0;
8129 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8130 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8131 }
8132
8133 count = 0;
8134 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8135 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8136 }
8137
8138 return 0;
8139}
8140
8141static void intel_set_config_restore_state(struct drm_device *dev,
8142 struct intel_set_config *config)
8143{
9a935856
DV		 8144 struct intel_encoder *encoder;
8145 struct intel_connector *connector;
85f9eb71
DV		 8146 int count;
8147
85f9eb71 8148 count = 0;
9a935856
DV		 8149 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8150 encoder->new_crtc =
8151 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8152 }
8153
8154 count = 0;
9a935856
DV		 8155 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8156 connector->new_encoder =
8157 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8158 }
8159}
8160
5e2b584e
DV		 8161static void
8162intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8163 struct intel_set_config *config)
8164{
8165
8166 /* We should be able to check here if the fb has the same properties
8167 * and then just flip_or_move it */
8168 if (set->crtc->fb != set->fb) {
8169 /* If we have no fb then treat it as a full mode set */
8170 if (set->crtc->fb == NULL) {
8171 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8172 config->mode_changed = true;
8173 } else if (set->fb == NULL) {
8174 config->mode_changed = true;
72f4901e
DV		 8175 } else if (set->fb->pixel_format !=
8176 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8177 config->mode_changed = true;
8178 } else
8179 config->fb_changed = true;
8180 }
8181
835c5873 8182 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8183 config->fb_changed = true;
8184
8185 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8186 DRM_DEBUG_KMS("modes are different, full mode set\n");
8187 drm_mode_debug_printmodeline(&set->crtc->mode);
8188 drm_mode_debug_printmodeline(set->mode);
8189 config->mode_changed = true;
8190 }
8191}
8192
2e431051 8193static int
9a935856
DV		 8194intel_modeset_stage_output_state(struct drm_device *dev,
8195 struct drm_mode_set *set,
8196 struct intel_set_config *config)
50f56119 8197{
85f9eb71 8198 struct drm_crtc *new_crtc;
9a935856
DV		 8199 struct intel_connector *connector;
8200 struct intel_encoder *encoder;
2e431051 8201 int count, ro;
50f56119 8202
9abdda74 8203 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8204 * of connectors. For paranoia, double-check this. */
8205 WARN_ON(!set->fb && (set->num_connectors != 0));
8206 WARN_ON(set->fb && (set->num_connectors == 0));
8207
50f56119 8208 count = 0;
9a935856
DV		 8209 list_for_each_entry(connector, &dev->mode_config.connector_list,
8210 base.head) {
8211 /* Otherwise traverse passed in connector list and get encoders
8212 * for them. */
50f56119 8213 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8214 if (set->connectors[ro] == &connector->base) {
8215 connector->new_encoder = connector->encoder;
50f56119
DV		 8216 break;
8217 }
8218 }
8219
9a935856
DV		 8220 /* If we disable the crtc, disable all its connectors. Also, if
8221 * the connector is on the changing crtc but not on the new
8222 * connector list, disable it. */
8223 if ((!set->fb || ro == set->num_connectors) &&
8224 connector->base.encoder &&
8225 connector->base.encoder->crtc == set->crtc) {
8226 connector->new_encoder = NULL;
8227
8228 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8229 connector->base.base.id,
8230 drm_get_connector_name(&connector->base));
8231 }
8232
8233
8234 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8235 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8236 config->mode_changed = true;
50f56119
DV		 8237 }
8238 }
9a935856 8239 /* connector->new_encoder is now updated for all connectors. */
50f56119 8240
9a935856 8241 /* Update crtc of enabled connectors. */
50f56119 8242 count = 0;
9a935856
DV		 8243 list_for_each_entry(connector, &dev->mode_config.connector_list,
8244 base.head) {
8245 if (!connector->new_encoder)
50f56119
DV		 8246 continue;
8247
9a935856 8248 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8249
8250 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8251 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8252 new_crtc = set->crtc;
8253 }
8254
8255 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8256 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8257 new_crtc)) {
5e2b584e 8258 return -EINVAL;
50f56119 8259 }
9a935856
DV		 8260 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8261
8262 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8263 connector->base.base.id,
8264 drm_get_connector_name(&connector->base),
8265 new_crtc->base.id);
8266 }
8267
8268 /* Check for any encoders that needs to be disabled. */
8269 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8270 base.head) {
8271 list_for_each_entry(connector,
8272 &dev->mode_config.connector_list,
8273 base.head) {
8274 if (connector->new_encoder == encoder) {
8275 WARN_ON(!connector->new_encoder->new_crtc);
8276
8277 goto next_encoder;
8278 }
8279 }
8280 encoder->new_crtc = NULL;
8281next_encoder:
8282 /* Only now check for crtc changes so we don't miss encoders
8283 * that will be disabled. */
8284 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8285 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8286 config->mode_changed = true;
50f56119
DV		 8287 }
8288 }
9a935856 8289 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8290
2e431051
DV		 8291 return 0;
8292}
8293
8294static int intel_crtc_set_config(struct drm_mode_set *set)
8295{
8296 struct drm_device *dev;
2e431051
DV		 8297 struct drm_mode_set save_set;
8298 struct intel_set_config *config;
8299 int ret;
2e431051 8300
8d3e375e
DV		 8301 BUG_ON(!set);
8302 BUG_ON(!set->crtc);
8303 BUG_ON(!set->crtc->helper_private);
2e431051 8304
7e53f3a4
DV		 8305 /* Enforce sane interface api - has been abused by the fb helper. */
8306 BUG_ON(!set->mode && set->fb);
8307 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8308
2e431051
DV		 8309 if (set->fb) {
8310 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8311 set->crtc->base.id, set->fb->base.id,
8312 (int)set->num_connectors, set->x, set->y);
8313 } else {
8314 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8315 }
8316
8317 dev = set->crtc->dev;
8318
8319 ret = -ENOMEM;
8320 config = kzalloc(sizeof(*config), GFP_KERNEL);
8321 if (!config)
8322 goto out_config;
8323
8324 ret = intel_set_config_save_state(dev, config);
8325 if (ret)
8326 goto out_config;
8327
8328 save_set.crtc = set->crtc;
8329 save_set.mode = &set->crtc->mode;
8330 save_set.x = set->crtc->x;
8331 save_set.y = set->crtc->y;
8332 save_set.fb = set->crtc->fb;
8333
8334 /* Compute whether we need a full modeset, only an fb base update or no
8335 * change at all. In the future we might also check whether only the
8336 * mode changed, e.g. for LVDS where we only change the panel fitter in
8337 * such cases. */
8338 intel_set_config_compute_mode_changes(set, config);
8339
9a935856 8340 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8341 if (ret)
8342 goto fail;
8343
5e2b584e 8344 if (config->mode_changed) {
87f1faa6 8345 if (set->mode) {
50f56119
DV		 8346 DRM_DEBUG_KMS("attempting to set mode from"
8347 " userspace\n");
8348 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8349 }
8350
c0c36b94
CW		 8351 ret = intel_set_mode(set->crtc, set->mode,
8352 set->x, set->y, set->fb);
8353 if (ret) {
8354 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8355 set->crtc->base.id, ret);
87f1faa6
DV		 8356 goto fail;
8357 }
5e2b584e 8358 } else if (config->fb_changed) {
4878cae2
VS		 8359 intel_crtc_wait_for_pending_flips(set->crtc);
8360
4f660f49 8361 ret = intel_pipe_set_base(set->crtc,
94352cf9 8362 set->x, set->y, set->fb);
50f56119
DV		 8363 }
8364
d9e55608
DV		 8365 intel_set_config_free(config);
8366
50f56119
DV		 8367 return 0;
8368
8369fail:
85f9eb71 8370 intel_set_config_restore_state(dev, config);
50f56119
DV		 8371
8372 /* Try to restore the config */
5e2b584e 8373 if (config->mode_changed &&
c0c36b94
CW		 8374 intel_set_mode(save_set.crtc, save_set.mode,
8375 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8376 DRM_ERROR("failed to restore config after modeset failure\n");
8377
d9e55608
DV		 8378out_config:
8379 intel_set_config_free(config);
50f56119
DV		 8380 return ret;
8381}
f6e5b160
CW		 8382
8383static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8384 .cursor_set = intel_crtc_cursor_set,
8385 .cursor_move = intel_crtc_cursor_move,
8386 .gamma_set = intel_crtc_gamma_set,
50f56119 8387 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8388 .destroy = intel_crtc_destroy,
8389 .page_flip = intel_crtc_page_flip,
8390};
8391
79f689aa
PZ		 8392static void intel_cpu_pll_init(struct drm_device *dev)
8393{
affa9354 8394 if (HAS_DDI(dev))
79f689aa
PZ		 8395 intel_ddi_pll_init(dev);
8396}
8397
ee7b9f93
JB		 8398static void intel_pch_pll_init(struct drm_device *dev)
8399{
8400 drm_i915_private_t *dev_priv = dev->dev_private;
8401 int i;
8402
8403 if (dev_priv->num_pch_pll == 0) {
8404 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8405 return;
8406 }
8407
8408 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8409 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8410 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8411 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8412 }
8413}
8414
b358d0a6 8415static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8416{
22fd0fab 8417 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8418 struct intel_crtc *intel_crtc;
8419 int i;
8420
8421 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8422 if (intel_crtc == NULL)
8423 return;
8424
8425 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8426
8427 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8428 for (i = 0; i < 256; i++) {
8429 intel_crtc->lut_r[i] = i;
8430 intel_crtc->lut_g[i] = i;
8431 intel_crtc->lut_b[i] = i;
8432 }
8433
80824003
JB		 8434 /* Swap pipes & planes for FBC on pre-965 */
8435 intel_crtc->pipe = pipe;
8436 intel_crtc->plane = pipe;
3b117c8f 8437 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8438 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8439 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8440 intel_crtc->plane = !pipe;
80824003
JB		 8441 }
8442
22fd0fab
JB		 8443 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8444 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8445 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8446 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8447
79e53945 8448 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8449}
8450
08d7b3d1 8451int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8452 struct drm_file *file)
08d7b3d1 8453{
08d7b3d1 8454 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8455 struct drm_mode_object *drmmode_obj;
8456 struct intel_crtc *crtc;
08d7b3d1 8457
1cff8f6b
DV		 8458 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8459 return -ENODEV;
08d7b3d1 8460
c05422d5
DV		 8461 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8462 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8463
c05422d5 8464 if (!drmmode_obj) {
08d7b3d1
CW		 8465 DRM_ERROR("no such CRTC id\n");
8466 return -EINVAL;
8467 }
8468
c05422d5
DV		 8469 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8470 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8471
c05422d5 8472 return 0;
08d7b3d1
CW		 8473}
8474
66a9278e 8475static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8476{
66a9278e
DV		 8477 struct drm_device *dev = encoder->base.dev;
8478 struct intel_encoder *source_encoder;
79e53945 8479 int index_mask = 0;
79e53945
JB		 8480 int entry = 0;
8481
66a9278e
DV		 8482 list_for_each_entry(source_encoder,
8483 &dev->mode_config.encoder_list, base.head) {
8484
8485 if (encoder == source_encoder)
79e53945 8486 index_mask |= (1 << entry);
66a9278e
DV		 8487
8488 /* Intel hw has only one MUX where enocoders could be cloned. */
8489 if (encoder->cloneable && source_encoder->cloneable)
8490 index_mask |= (1 << entry);
8491
79e53945
JB		 8492 entry++;
8493 }
4ef69c7a 8494
79e53945
JB		 8495 return index_mask;
8496}
8497
4d302442
CW		 8498static bool has_edp_a(struct drm_device *dev)
8499{
8500 struct drm_i915_private *dev_priv = dev->dev_private;
8501
8502 if (!IS_MOBILE(dev))
8503 return false;
8504
8505 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8506 return false;
8507
8508 if (IS_GEN5(dev) &&
8509 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8510 return false;
8511
8512 return true;
8513}
8514
79e53945
JB		 8515static void intel_setup_outputs(struct drm_device *dev)
8516{
725e30ad 8517 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8518 struct intel_encoder *encoder;
cb0953d7 8519 bool dpd_is_edp = false;
f3cfcba6 8520 bool has_lvds;
79e53945 8521
f3cfcba6 8522 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8523 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8524 /* disable the panel fitter on everything but LVDS */
8525 I915_WRITE(PFIT_CONTROL, 0);
8526 }
79e53945 8527
c40c0f5b 8528 if (!IS_ULT(dev))
79935fca 8529 intel_crt_init(dev);
cb0953d7 8530
affa9354 8531 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8532 int found;
8533
8534 /* Haswell uses DDI functions to detect digital outputs */
8535 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8536 /* DDI A only supports eDP */
8537 if (found)
8538 intel_ddi_init(dev, PORT_A);
8539
8540 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8541 * register */
8542 found = I915_READ(SFUSE_STRAP);
8543
8544 if (found & SFUSE_STRAP_DDIB_DETECTED)
8545 intel_ddi_init(dev, PORT_B);
8546 if (found & SFUSE_STRAP_DDIC_DETECTED)
8547 intel_ddi_init(dev, PORT_C);
8548 if (found & SFUSE_STRAP_DDID_DETECTED)
8549 intel_ddi_init(dev, PORT_D);
8550 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8551 int found;
270b3042
DV		 8552 dpd_is_edp = intel_dpd_is_edp(dev);
8553
8554 if (has_edp_a(dev))
8555 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8556
dc0fa718 8557 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8558 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8559 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8560 if (!found)
e2debe91 8561 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8562 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8563 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8564 }
8565
dc0fa718 8566 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8567 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8568
dc0fa718 8569 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8570 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8571
5eb08b69 8572 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8573 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8574
270b3042 8575 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8576 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8577 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8578 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8579 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8580 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8581
dc0fa718 8582 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8583 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8584 PORT_B);
67cfc203
VS		 8585 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8586 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8587 }
103a196f 8588 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8589 bool found = false;
7d57382e 8590
e2debe91 8591 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8592 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8593 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8594 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8595 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8596 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8597 }
27185ae1 8598
b01f2c3a
JB		 8599 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8600 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8601 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8602 }
725e30ad 8603 }
13520b05
KH		 8604
8605 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8606
e2debe91 8607 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8608 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8609 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8610 }
27185ae1 8611
e2debe91 8612 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8613
b01f2c3a
JB		 8614 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8615 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8616 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8617 }
8618 if (SUPPORTS_INTEGRATED_DP(dev)) {
8619 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8620 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8621 }
725e30ad 8622 }
27185ae1 8623
b01f2c3a
JB		 8624 if (SUPPORTS_INTEGRATED_DP(dev) &&
8625 (I915_READ(DP_D) & DP_DETECTED)) {
8626 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8627 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8628 }
bad720ff 8629 } else if (IS_GEN2(dev))
79e53945
JB		 8630 intel_dvo_init(dev);
8631
103a196f 8632 if (SUPPORTS_TV(dev))
79e53945
JB		 8633 intel_tv_init(dev);
8634
4ef69c7a
CW		 8635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8636 encoder->base.possible_crtcs = encoder->crtc_mask;
8637 encoder->base.possible_clones =
66a9278e 8638 intel_encoder_clones(encoder);
79e53945 8639 }
47356eb6 8640
dde86e2d 8641 intel_init_pch_refclk(dev);
270b3042
DV		 8642
8643 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8644}
8645
8646static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8647{
8648 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8649
8650 drm_framebuffer_cleanup(fb);
05394f39 8651 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8652
8653 kfree(intel_fb);
8654}
8655
8656static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8657 struct drm_file *file,
79e53945
JB		 8658 unsigned int *handle)
8659{
8660 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8661 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8662
05394f39 8663 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8664}
8665
8666static const struct drm_framebuffer_funcs intel_fb_funcs = {
8667 .destroy = intel_user_framebuffer_destroy,
8668 .create_handle = intel_user_framebuffer_create_handle,
8669};
8670
38651674
DA		 8671int intel_framebuffer_init(struct drm_device *dev,
8672 struct intel_framebuffer *intel_fb,
308e5bcb 8673 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8674 struct drm_i915_gem_object *obj)
79e53945 8675{
79e53945
JB		 8676 int ret;
8677
c16ed4be
CW		 8678 if (obj->tiling_mode == I915_TILING_Y) {
8679 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8680 return -EINVAL;
c16ed4be 8681 }
57cd6508 8682
c16ed4be
CW		 8683 if (mode_cmd->pitches[0] & 63) {
8684 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8685 mode_cmd->pitches[0]);
57cd6508 8686 return -EINVAL;
c16ed4be 8687 }
57cd6508 8688
5d7bd705 8689 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8690 if (mode_cmd->pitches[0] > 32768) {
8691 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8692 mode_cmd->pitches[0]);
5d7bd705 8693 return -EINVAL;
c16ed4be 8694 }
5d7bd705
VS		 8695
8696 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8697 mode_cmd->pitches[0] != obj->stride) {
8698 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8699 mode_cmd->pitches[0], obj->stride);
5d7bd705 8700 return -EINVAL;
c16ed4be 8701 }
5d7bd705 8702
57779d06 8703 /* Reject formats not supported by any plane early. */
308e5bcb 8704 switch (mode_cmd->pixel_format) {
57779d06 8705 case DRM_FORMAT_C8:
04b3924d
VS		 8706 case DRM_FORMAT_RGB565:
8707 case DRM_FORMAT_XRGB8888:
8708 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8709 break;
8710 case DRM_FORMAT_XRGB1555:
8711 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8712 if (INTEL_INFO(dev)->gen > 3) {
8713 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8714 return -EINVAL;
c16ed4be 8715 }
57779d06
VS		 8716 break;
8717 case DRM_FORMAT_XBGR8888:
8718 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8719 case DRM_FORMAT_XRGB2101010:
8720 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8721 case DRM_FORMAT_XBGR2101010:
8722 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8723 if (INTEL_INFO(dev)->gen < 4) {
8724 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8725 return -EINVAL;
c16ed4be 8726 }
b5626747 8727 break;
04b3924d
VS		 8728 case DRM_FORMAT_YUYV:
8729 case DRM_FORMAT_UYVY:
8730 case DRM_FORMAT_YVYU:
8731 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8732 if (INTEL_INFO(dev)->gen < 5) {
8733 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8734 return -EINVAL;
c16ed4be 8735 }
57cd6508
CW		 8736 break;
8737 default:
c16ed4be 8738 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8739 return -EINVAL;
8740 }
8741
90f9a336
VS		 8742 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8743 if (mode_cmd->offsets[0] != 0)
8744 return -EINVAL;
8745
c7d73f6a
DV		 8746 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8747 intel_fb->obj = obj;
8748
79e53945
JB		 8749 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8750 if (ret) {
8751 DRM_ERROR("framebuffer init failed %d\n", ret);
8752 return ret;
8753 }
8754
79e53945
JB		 8755 return 0;
8756}
8757
79e53945
JB		 8758static struct drm_framebuffer *
8759intel_user_framebuffer_create(struct drm_device *dev,
8760 struct drm_file *filp,
308e5bcb 8761 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8762{
05394f39 8763 struct drm_i915_gem_object *obj;
79e53945 8764
308e5bcb
JB		 8765 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8766 mode_cmd->handles[0]));
c8725226 8767 if (&obj->base == NULL)
cce13ff7 8768 return ERR_PTR(-ENOENT);
79e53945 8769
d2dff872 8770 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8771}
8772
79e53945 8773static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8774 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8775 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8776};
8777
e70236a8
JB		 8778/* Set up chip specific display functions */
8779static void intel_init_display(struct drm_device *dev)
8780{
8781 struct drm_i915_private *dev_priv = dev->dev_private;
8782
affa9354 8783 if (HAS_DDI(dev)) {
0e8ffe1b 8784 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8785 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8786 dev_priv->display.crtc_enable = haswell_crtc_enable;
8787 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8788 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8789 dev_priv->display.update_plane = ironlake_update_plane;
8790 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8791 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8792 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8793 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8794 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8795 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8796 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8797 } else if (IS_VALLEYVIEW(dev)) {
8798 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8799 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8800 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8801 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8802 dev_priv->display.off = i9xx_crtc_off;
8803 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8804 } else {
0e8ffe1b 8805 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8806 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8807 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8808 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8809 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8810 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8811 }
e70236a8 8812
e70236a8 8813 /* Returns the core display clock speed */
25eb05fc
JB		 8814 if (IS_VALLEYVIEW(dev))
8815 dev_priv->display.get_display_clock_speed =
8816 valleyview_get_display_clock_speed;
8817 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8818 dev_priv->display.get_display_clock_speed =
8819 i945_get_display_clock_speed;
8820 else if (IS_I915G(dev))
8821 dev_priv->display.get_display_clock_speed =
8822 i915_get_display_clock_speed;
f2b115e6 8823 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8824 dev_priv->display.get_display_clock_speed =
8825 i9xx_misc_get_display_clock_speed;
8826 else if (IS_I915GM(dev))
8827 dev_priv->display.get_display_clock_speed =
8828 i915gm_get_display_clock_speed;
8829 else if (IS_I865G(dev))
8830 dev_priv->display.get_display_clock_speed =
8831 i865_get_display_clock_speed;
f0f8a9ce 8832 else if (IS_I85X(dev))
e70236a8
JB		 8833 dev_priv->display.get_display_clock_speed =
8834 i855_get_display_clock_speed;
8835 else /* 852, 830 */
8836 dev_priv->display.get_display_clock_speed =
8837 i830_get_display_clock_speed;
8838
7f8a8569 8839 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8840 if (IS_GEN5(dev)) {
674cf967 8841 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8842 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8843 } else if (IS_GEN6(dev)) {
674cf967 8844 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8845 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8846 } else if (IS_IVYBRIDGE(dev)) {
8847 /* FIXME: detect B0+ stepping and use auto training */
8848 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8849 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8850 dev_priv->display.modeset_global_resources =
8851 ivb_modeset_global_resources;
c82e4d26
ED		 8852 } else if (IS_HASWELL(dev)) {
8853 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8854 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8855 dev_priv->display.modeset_global_resources =
8856 haswell_modeset_global_resources;
a0e63c22 8857 }
6067aaea 8858 } else if (IS_G4X(dev)) {
e0dac65e 8859 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8860 }
8c9f3aaf
JB		 8861
8862 /* Default just returns -ENODEV to indicate unsupported */
8863 dev_priv->display.queue_flip = intel_default_queue_flip;
8864
8865 switch (INTEL_INFO(dev)->gen) {
8866 case 2:
8867 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8868 break;
8869
8870 case 3:
8871 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8872 break;
8873
8874 case 4:
8875 case 5:
8876 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8877 break;
8878
8879 case 6:
8880 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8881 break;
7c9017e5
JB		 8882 case 7:
8883 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8884 break;
8c9f3aaf 8885 }
e70236a8
JB		 8886}
8887
b690e96c
JB		 8888/*
8889 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8890 * resume, or other times. This quirk makes sure that's the case for
8891 * affected systems.
8892 */
0206e353 8893static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8894{
8895 struct drm_i915_private *dev_priv = dev->dev_private;
8896
8897 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8898 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8899}
8900
435793df
KP		 8901/*
8902 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8903 */
8904static void quirk_ssc_force_disable(struct drm_device *dev)
8905{
8906 struct drm_i915_private *dev_priv = dev->dev_private;
8907 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8908 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8909}
8910
4dca20ef 8911/*
5a15ab5b
CE		 8912 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8913 * brightness value
4dca20ef
CE		 8914 */
8915static void quirk_invert_brightness(struct drm_device *dev)
8916{
8917 struct drm_i915_private *dev_priv = dev->dev_private;
8918 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8919 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8920}
8921
b690e96c
JB		 8922struct intel_quirk {
8923 int device;
8924 int subsystem_vendor;
8925 int subsystem_device;
8926 void (*hook)(struct drm_device *dev);
8927};
8928
5f85f176
EE		 8929/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8930struct intel_dmi_quirk {
8931 void (*hook)(struct drm_device *dev);
8932 const struct dmi_system_id (*dmi_id_list)[];
8933};
8934
8935static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8936{
8937 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8938 return 1;
8939}
8940
8941static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8942 {
8943 .dmi_id_list = &(const struct dmi_system_id[]) {
8944 {
8945 .callback = intel_dmi_reverse_brightness,
8946 .ident = "NCR Corporation",
8947 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8948 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8949 },
8950 },
8951 { } /* terminating entry */
8952 },
8953 .hook = quirk_invert_brightness,
8954 },
8955};
8956
c43b5634 8957static struct intel_quirk intel_quirks[] = {
b690e96c 8958 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8959 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8960
b690e96c
JB		 8961 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8962 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8963
b690e96c
JB		 8964 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8965 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8966
ccd0d36e 8967 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8968 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8969 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8970
8971 /* Lenovo U160 cannot use SSC on LVDS */
8972 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8973
8974 /* Sony Vaio Y cannot use SSC on LVDS */
8975 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8976
8977 /* Acer Aspire 5734Z must invert backlight brightness */
8978 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8979
8980 /* Acer/eMachines G725 */
8981 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8982
8983 /* Acer/eMachines e725 */
8984 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8985
8986 /* Acer/Packard Bell NCL20 */
8987 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8988
8989 /* Acer Aspire 4736Z */
8990 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8991};
8992
8993static void intel_init_quirks(struct drm_device *dev)
8994{
8995 struct pci_dev *d = dev->pdev;
8996 int i;
8997
8998 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8999 struct intel_quirk *q = &intel_quirks[i];
9000
9001 if (d->device == q->device &&
9002 (d->subsystem_vendor == q->subsystem_vendor ||
9003 q->subsystem_vendor == PCI_ANY_ID) &&
9004 (d->subsystem_device == q->subsystem_device ||
9005 q->subsystem_device == PCI_ANY_ID))
9006 q->hook(dev);
9007 }
5f85f176
EE		 9008 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9009 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9010 intel_dmi_quirks[i].hook(dev);
9011 }
b690e96c
JB		 9012}
9013
9cce37f4
JB		 9014/* Disable the VGA plane that we never use */
9015static void i915_disable_vga(struct drm_device *dev)
9016{
9017 struct drm_i915_private *dev_priv = dev->dev_private;
9018 u8 sr1;
766aa1c4 9019 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9020
9021 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9022 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9023 sr1 = inb(VGA_SR_DATA);
9024 outb(sr1 | 1<<5, VGA_SR_DATA);
9025 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9026 udelay(300);
9027
9028 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9029 POSTING_READ(vga_reg);
9030}
9031
f817586c
DV		 9032void intel_modeset_init_hw(struct drm_device *dev)
9033{
fa42e23c 9034 intel_init_power_well(dev);
0232e927 9035
a8f78b58
ED		 9036 intel_prepare_ddi(dev);
9037
f817586c
DV		 9038 intel_init_clock_gating(dev);
9039
79f5b2c7 9040 mutex_lock(&dev->struct_mutex);
8090c6b9 9041 intel_enable_gt_powersave(dev);
79f5b2c7 9042 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9043}
9044
79e53945
JB		 9045void intel_modeset_init(struct drm_device *dev)
9046{
652c393a 9047 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9048 int i, j, ret;
79e53945
JB		 9049
9050 drm_mode_config_init(dev);
9051
9052 dev->mode_config.min_width = 0;
9053 dev->mode_config.min_height = 0;
9054
019d96cb
DA		 9055 dev->mode_config.preferred_depth = 24;
9056 dev->mode_config.prefer_shadow = 1;
9057
e6ecefaa 9058 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9059
b690e96c
JB		 9060 intel_init_quirks(dev);
9061
1fa61106
ED		 9062 intel_init_pm(dev);
9063
e3c74757
BW		 9064 if (INTEL_INFO(dev)->num_pipes == 0)
9065 return;
9066
e70236a8
JB		 9067 intel_init_display(dev);
9068
a6c45cf0
CW		 9069 if (IS_GEN2(dev)) {
9070 dev->mode_config.max_width = 2048;
9071 dev->mode_config.max_height = 2048;
9072 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9073 dev->mode_config.max_width = 4096;
9074 dev->mode_config.max_height = 4096;
79e53945 9075 } else {
a6c45cf0
CW		 9076 dev->mode_config.max_width = 8192;
9077 dev->mode_config.max_height = 8192;
79e53945 9078 }
5d4545ae 9079 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9080
28c97730 9081 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9082 INTEL_INFO(dev)->num_pipes,
9083 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9084
7eb552ae 9085 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9086 intel_crtc_init(dev, i);
7f1f3851
JB		 9087 for (j = 0; j < dev_priv->num_plane; j++) {
9088 ret = intel_plane_init(dev, i, j);
9089 if (ret)
06da8da2
VS		 9090 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9091 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9092 }
79e53945
JB		 9093 }
9094
79f689aa 9095 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9096 intel_pch_pll_init(dev);
9097
9cce37f4
JB		 9098 /* Just disable it once at startup */
9099 i915_disable_vga(dev);
79e53945 9100 intel_setup_outputs(dev);
11be49eb
CW		 9101
9102 /* Just in case the BIOS is doing something questionable. */
9103 intel_disable_fbc(dev);
2c7111db
CW		 9104}
9105
24929352
DV		 9106static void
9107intel_connector_break_all_links(struct intel_connector *connector)
9108{
9109 connector->base.dpms = DRM_MODE_DPMS_OFF;
9110 connector->base.encoder = NULL;
9111 connector->encoder->connectors_active = false;
9112 connector->encoder->base.crtc = NULL;
9113}
9114
7fad798e
DV		 9115static void intel_enable_pipe_a(struct drm_device *dev)
9116{
9117 struct intel_connector *connector;
9118 struct drm_connector *crt = NULL;
9119 struct intel_load_detect_pipe load_detect_temp;
9120
9121 /* We can't just switch on the pipe A, we need to set things up with a
9122 * proper mode and output configuration. As a gross hack, enable pipe A
9123 * by enabling the load detect pipe once. */
9124 list_for_each_entry(connector,
9125 &dev->mode_config.connector_list,
9126 base.head) {
9127 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9128 crt = &connector->base;
9129 break;
9130 }
9131 }
9132
9133 if (!crt)
9134 return;
9135
9136 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9137 intel_release_load_detect_pipe(crt, &load_detect_temp);
9138
652c393a 9139
7fad798e
DV		 9140}
9141
fa555837
DV		 9142static bool
9143intel_check_plane_mapping(struct intel_crtc *crtc)
9144{
7eb552ae
BW		 9145 struct drm_device *dev = crtc->base.dev;
9146 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9147 u32 reg, val;
9148
7eb552ae 9149 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9150 return true;
9151
9152 reg = DSPCNTR(!crtc->plane);
9153 val = I915_READ(reg);
9154
9155 if ((val & DISPLAY_PLANE_ENABLE) &&
9156 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9157 return false;
9158
9159 return true;
9160}
9161
24929352
DV		 9162static void intel_sanitize_crtc(struct intel_crtc *crtc)
9163{
9164 struct drm_device *dev = crtc->base.dev;
9165 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9166 u32 reg;
24929352 9167
24929352 9168 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9169 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9170 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9171
9172 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9173 * disable the crtc (and hence change the state) if it is wrong. Note
9174 * that gen4+ has a fixed plane -> pipe mapping. */
9175 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9176 struct intel_connector *connector;
9177 bool plane;
9178
24929352
DV		 9179 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9180 crtc->base.base.id);
9181
9182 /* Pipe has the wrong plane attached and the plane is active.
9183 * Temporarily change the plane mapping and disable everything
9184 * ... */
9185 plane = crtc->plane;
9186 crtc->plane = !plane;
9187 dev_priv->display.crtc_disable(&crtc->base);
9188 crtc->plane = plane;
9189
9190 /* ... and break all links. */
9191 list_for_each_entry(connector, &dev->mode_config.connector_list,
9192 base.head) {
9193 if (connector->encoder->base.crtc != &crtc->base)
9194 continue;
9195
9196 intel_connector_break_all_links(connector);
9197 }
9198
9199 WARN_ON(crtc->active);
9200 crtc->base.enabled = false;
9201 }
24929352 9202
7fad798e
DV		 9203 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9204 crtc->pipe == PIPE_A && !crtc->active) {
9205 /* BIOS forgot to enable pipe A, this mostly happens after
9206 * resume. Force-enable the pipe to fix this, the update_dpms
9207 * call below we restore the pipe to the right state, but leave
9208 * the required bits on. */
9209 intel_enable_pipe_a(dev);
9210 }
9211
24929352
DV		 9212 /* Adjust the state of the output pipe according to whether we
9213 * have active connectors/encoders. */
9214 intel_crtc_update_dpms(&crtc->base);
9215
9216 if (crtc->active != crtc->base.enabled) {
9217 struct intel_encoder *encoder;
9218
9219 /* This can happen either due to bugs in the get_hw_state
9220 * functions or because the pipe is force-enabled due to the
9221 * pipe A quirk. */
9222 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9223 crtc->base.base.id,
9224 crtc->base.enabled ? "enabled" : "disabled",
9225 crtc->active ? "enabled" : "disabled");
9226
9227 crtc->base.enabled = crtc->active;
9228
9229 /* Because we only establish the connector -> encoder ->
9230 * crtc links if something is active, this means the
9231 * crtc is now deactivated. Break the links. connector
9232 * -> encoder links are only establish when things are
9233 * actually up, hence no need to break them. */
9234 WARN_ON(crtc->active);
9235
9236 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9237 WARN_ON(encoder->connectors_active);
9238 encoder->base.crtc = NULL;
9239 }
9240 }
9241}
9242
9243static void intel_sanitize_encoder(struct intel_encoder *encoder)
9244{
9245 struct intel_connector *connector;
9246 struct drm_device *dev = encoder->base.dev;
9247
9248 /* We need to check both for a crtc link (meaning that the
9249 * encoder is active and trying to read from a pipe) and the
9250 * pipe itself being active. */
9251 bool has_active_crtc = encoder->base.crtc &&
9252 to_intel_crtc(encoder->base.crtc)->active;
9253
9254 if (encoder->connectors_active && !has_active_crtc) {
9255 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9256 encoder->base.base.id,
9257 drm_get_encoder_name(&encoder->base));
9258
9259 /* Connector is active, but has no active pipe. This is
9260 * fallout from our resume register restoring. Disable
9261 * the encoder manually again. */
9262 if (encoder->base.crtc) {
9263 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9264 encoder->base.base.id,
9265 drm_get_encoder_name(&encoder->base));
9266 encoder->disable(encoder);
9267 }
9268
9269 /* Inconsistent output/port/pipe state happens presumably due to
9270 * a bug in one of the get_hw_state functions. Or someplace else
9271 * in our code, like the register restore mess on resume. Clamp
9272 * things to off as a safer default. */
9273 list_for_each_entry(connector,
9274 &dev->mode_config.connector_list,
9275 base.head) {
9276 if (connector->encoder != encoder)
9277 continue;
9278
9279 intel_connector_break_all_links(connector);
9280 }
9281 }
9282 /* Enabled encoders without active connectors will be fixed in
9283 * the crtc fixup. */
9284}
9285
44cec740 9286void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9287{
9288 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9289 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9290
9291 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9292 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9293 i915_disable_vga(dev);
0fde901f
KM		 9294 }
9295}
9296
24929352
DV		 9297/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9298 * and i915 state tracking structures. */
45e2b5f6
DV		 9299void intel_modeset_setup_hw_state(struct drm_device *dev,
9300 bool force_restore)
24929352
DV		 9301{
9302 struct drm_i915_private *dev_priv = dev->dev_private;
9303 enum pipe pipe;
9304 u32 tmp;
b5644d05 9305 struct drm_plane *plane;
24929352
DV		 9306 struct intel_crtc *crtc;
9307 struct intel_encoder *encoder;
9308 struct intel_connector *connector;
9309
affa9354 9310 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9311 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9312
9313 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9314 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9315 case TRANS_DDI_EDP_INPUT_A_ON:
9316 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9317 pipe = PIPE_A;
9318 break;
9319 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9320 pipe = PIPE_B;
9321 break;
9322 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9323 pipe = PIPE_C;
9324 break;
aaa148ec
DL		 9325 default:
9326 /* A bogus value has been programmed, disable
9327 * the transcoder */
9328 WARN(1, "Bogus eDP source %08x\n", tmp);
9329 intel_ddi_disable_transcoder_func(dev_priv,
9330 TRANSCODER_EDP);
9331 goto setup_pipes;
e28d54cb
PZ		 9332 }
9333
9334 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9335 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9336
9337 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9338 pipe_name(pipe));
9339 }
9340 }
9341
aaa148ec 9342setup_pipes:
0e8ffe1b
DV		 9343 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9344 base.head) {
3b117c8f 9345 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9346 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9347 crtc->config.cpu_transcoder = tmp;
9348
0e8ffe1b
DV		 9349 crtc->active = dev_priv->display.get_pipe_config(crtc,
9350 &crtc->config);
24929352
DV		 9351
9352 crtc->base.enabled = crtc->active;
9353
9354 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9355 crtc->base.base.id,
9356 crtc->active ? "enabled" : "disabled");
9357 }
9358
affa9354 9359 if (HAS_DDI(dev))
6441ab5f
PZ		 9360 intel_ddi_setup_hw_pll_state(dev);
9361
24929352
DV		 9362 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9363 base.head) {
9364 pipe = 0;
9365
9366 if (encoder->get_hw_state(encoder, &pipe)) {
9367 encoder->base.crtc =
9368 dev_priv->pipe_to_crtc_mapping[pipe];
9369 } else {
9370 encoder->base.crtc = NULL;
9371 }
9372
9373 encoder->connectors_active = false;
9374 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9375 encoder->base.base.id,
9376 drm_get_encoder_name(&encoder->base),
9377 encoder->base.crtc ? "enabled" : "disabled",
9378 pipe);
9379 }
9380
9381 list_for_each_entry(connector, &dev->mode_config.connector_list,
9382 base.head) {
9383 if (connector->get_hw_state(connector)) {
9384 connector->base.dpms = DRM_MODE_DPMS_ON;
9385 connector->encoder->connectors_active = true;
9386 connector->base.encoder = &connector->encoder->base;
9387 } else {
9388 connector->base.dpms = DRM_MODE_DPMS_OFF;
9389 connector->base.encoder = NULL;
9390 }
9391 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9392 connector->base.base.id,
9393 drm_get_connector_name(&connector->base),
9394 connector->base.encoder ? "enabled" : "disabled");
9395 }
9396
9397 /* HW state is read out, now we need to sanitize this mess. */
9398 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9399 base.head) {
9400 intel_sanitize_encoder(encoder);
9401 }
9402
9403 for_each_pipe(pipe) {
9404 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9405 intel_sanitize_crtc(crtc);
9406 }
9a935856 9407
45e2b5f6 9408 if (force_restore) {
f30da187
DV		 9409 /*
9410 * We need to use raw interfaces for restoring state to avoid
9411 * checking (bogus) intermediate states.
9412 */
45e2b5f6 9413 for_each_pipe(pipe) {
b5644d05
JB		 9414 struct drm_crtc *crtc =
9415 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9416
9417 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9418 crtc->fb);
45e2b5f6 9419 }
b5644d05
JB		 9420 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9421 intel_plane_restore(plane);
0fde901f
KM		 9422
9423 i915_redisable_vga(dev);
45e2b5f6
DV		 9424 } else {
9425 intel_modeset_update_staged_output_state(dev);
9426 }
8af6cf88
DV		 9427
9428 intel_modeset_check_state(dev);
2e938892
DV		 9429
9430 drm_mode_config_reset(dev);
2c7111db
CW		 9431}
9432
9433void intel_modeset_gem_init(struct drm_device *dev)
9434{
1833b134 9435 intel_modeset_init_hw(dev);
02e792fb
DV		 9436
9437 intel_setup_overlay(dev);
24929352 9438
45e2b5f6 9439 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9440}
9441
9442void intel_modeset_cleanup(struct drm_device *dev)
9443{
652c393a
JB		 9444 struct drm_i915_private *dev_priv = dev->dev_private;
9445 struct drm_crtc *crtc;
9446 struct intel_crtc *intel_crtc;
9447
fd0c0642
DV		 9448 /*
9449 * Interrupts and polling as the first thing to avoid creating havoc.
9450 * Too much stuff here (turning of rps, connectors, ...) would
9451 * experience fancy races otherwise.
9452 */
9453 drm_irq_uninstall(dev);
9454 cancel_work_sync(&dev_priv->hotplug_work);
9455 /*
9456 * Due to the hpd irq storm handling the hotplug work can re-arm the
9457 * poll handlers. Hence disable polling after hpd handling is shut down.
9458 */
f87ea761 9459 drm_kms_helper_poll_fini(dev);
fd0c0642 9460
652c393a
JB		 9461 mutex_lock(&dev->struct_mutex);
9462
723bfd70
JB		 9463 intel_unregister_dsm_handler();
9464
652c393a
JB		 9465 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9466 /* Skip inactive CRTCs */
9467 if (!crtc->fb)
9468 continue;
9469
9470 intel_crtc = to_intel_crtc(crtc);
3dec0095 9471 intel_increase_pllclock(crtc);
652c393a
JB		 9472 }
9473
973d04f9 9474 intel_disable_fbc(dev);
e70236a8 9475
8090c6b9 9476 intel_disable_gt_powersave(dev);
0cdab21f 9477
930ebb46
DV		 9478 ironlake_teardown_rc6(dev);
9479
69341a5e
KH		 9480 mutex_unlock(&dev->struct_mutex);
9481
1630fe75
CW		 9482 /* flush any delayed tasks or pending work */
9483 flush_scheduled_work();
9484
dc652f90
JN		 9485 /* destroy backlight, if any, before the connectors */
9486 intel_panel_destroy_backlight(dev);
9487
79e53945 9488 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9489
9490 intel_cleanup_overlay(dev);
79e53945
JB		 9491}
9492
f1c79df3
ZW		 9493/*
9494 * Return which encoder is currently attached for connector.
9495 */
df0e9248 9496struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9497{
df0e9248
CW		 9498 return &intel_attached_encoder(connector)->base;
9499}
f1c79df3 9500
df0e9248
CW		 9501void intel_connector_attach_encoder(struct intel_connector *connector,
9502 struct intel_encoder *encoder)
9503{
9504 connector->encoder = encoder;
9505 drm_mode_connector_attach_encoder(&connector->base,
9506 &encoder->base);
79e53945 9507}
28d52043
DA		 9508
9509/*
9510 * set vga decode state - true == enable VGA decode
9511 */
9512int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9513{
9514 struct drm_i915_private *dev_priv = dev->dev_private;
9515 u16 gmch_ctrl;
9516
9517 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9518 if (state)
9519 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9520 else
9521 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9522 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9523 return 0;
9524}
c4a1d9e4
CW		 9525
9526#ifdef CONFIG_DEBUG_FS
9527#include <linux/seq_file.h>
9528
9529struct intel_display_error_state {
9530 struct intel_cursor_error_state {
9531 u32 control;
9532 u32 position;
9533 u32 base;
9534 u32 size;
52331309 9535 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9536
9537 struct intel_pipe_error_state {
9538 u32 conf;
9539 u32 source;
9540
9541 u32 htotal;
9542 u32 hblank;
9543 u32 hsync;
9544 u32 vtotal;
9545 u32 vblank;
9546 u32 vsync;
52331309 9547 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9548
9549 struct intel_plane_error_state {
9550 u32 control;
9551 u32 stride;
9552 u32 size;
9553 u32 pos;
9554 u32 addr;
9555 u32 surface;
9556 u32 tile_offset;
52331309 9557 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9558};
9559
9560struct intel_display_error_state *
9561intel_display_capture_error_state(struct drm_device *dev)
9562{
0206e353 9563 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9564 struct intel_display_error_state *error;
702e7a56 9565 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9566 int i;
9567
9568 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9569 if (error == NULL)
9570 return NULL;
9571
52331309 9572 for_each_pipe(i) {
702e7a56
PZ		 9573 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9574
a18c4c3d
PZ		 9575 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9576 error->cursor[i].control = I915_READ(CURCNTR(i));
9577 error->cursor[i].position = I915_READ(CURPOS(i));
9578 error->cursor[i].base = I915_READ(CURBASE(i));
9579 } else {
9580 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9581 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9582 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9583 }
c4a1d9e4
CW		 9584
9585 error->plane[i].control = I915_READ(DSPCNTR(i));
9586 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9587 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9588 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9589 error->plane[i].pos = I915_READ(DSPPOS(i));
9590 }
ca291363
PZ		 9591 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9592 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9593 if (INTEL_INFO(dev)->gen >= 4) {
9594 error->plane[i].surface = I915_READ(DSPSURF(i));
9595 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9596 }
9597
702e7a56 9598 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9599 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9600 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9601 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9602 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9603 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9604 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9605 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9606 }
9607
9608 return error;
9609}
9610
9611void
9612intel_display_print_error_state(struct seq_file *m,
9613 struct drm_device *dev,
9614 struct intel_display_error_state *error)
9615{
9616 int i;
9617
7eb552ae 9618 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9619 for_each_pipe(i) {
c4a1d9e4
CW		 9620 seq_printf(m, "Pipe [%d]:\n", i);
9621 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9622 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9623 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9624 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9625 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9626 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9627 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9628 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9629
9630 seq_printf(m, "Plane [%d]:\n", i);
9631 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9632 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9633 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9634 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9635 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9636 }
4b71a570 9637 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9638 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9639 if (INTEL_INFO(dev)->gen >= 4) {
9640 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9641 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9642 }
9643
9644 seq_printf(m, "Cursor [%d]:\n", i);
9645 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9646 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9647 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9648 }
9649}
9650#endif
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