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drm/i915: Document the inteded use of requested_mode
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
18442d08
VS		 50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
f1f644dc 52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
743 * We can ditch the adjusted_mode.clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
750 intel_crtc->config.adjusted_mode.clock;
751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
89b667f8
JB		 1469void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470{
1471 u32 port_mask;
1472
1473 if (!port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1475 else
1476 port_mask = DPLL_PORTC_READY_MASK;
1477
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1481}
1482
92f2584a 1483/**
e72f9fbf 1484 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1487 *
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1490 */
e2b78267 1491static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1492{
e2b78267
DV		 1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1495
48da64a8 1496 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1497 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1498 if (WARN_ON(pll == NULL))
48da64a8
CW		 1499 return;
1500
1501 if (WARN_ON(pll->refcount == 0))
1502 return;
ee7b9f93 1503
46edb027
DV		 1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
e2b78267 1506 crtc->base.base.id);
92f2584a 1507
cdbd2316
DV		 1508 if (pll->active++) {
1509 WARN_ON(!pll->on);
e9d6944e 1510 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1511 return;
1512 }
f4a091c7 1513 WARN_ON(pll->on);
ee7b9f93 1514
46edb027 1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1516 pll->enable(dev_priv, pll);
ee7b9f93 1517 pll->on = true;
92f2584a
JB		 1518}
1519
e2b78267 1520static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1521{
e2b78267
DV		 1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1524
92f2584a
JB		 1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1527 if (WARN_ON(pll == NULL))
ee7b9f93 1528 return;
92f2584a 1529
48da64a8
CW		 1530 if (WARN_ON(pll->refcount == 0))
1531 return;
7a419866 1532
46edb027
DV		 1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
e2b78267 1535 crtc->base.base.id);
7a419866 1536
48da64a8 1537 if (WARN_ON(pll->active == 0)) {
e9d6944e 1538 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1539 return;
1540 }
1541
e9d6944e 1542 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1543 WARN_ON(!pll->on);
cdbd2316 1544 if (--pll->active)
7a419866 1545 return;
ee7b9f93 1546
46edb027 1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1548 pll->disable(dev_priv, pll);
ee7b9f93 1549 pll->on = false;
92f2584a
JB		 1550}
1551
b8a4f404
PZ		 1552static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
040484af 1554{
23670b32 1555 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1558 uint32_t reg, val, pipeconf_val;
040484af
JB		 1559
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1562
1563 /* Make sure PCH DPLL is enabled */
e72f9fbf 1564 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1565 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1566
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1570
23670b32
DV		 1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
59c859d6 1578 }
23670b32 1579
ab9412ba 1580 reg = PCH_TRANSCONF(pipe);
040484af 1581 val = I915_READ(reg);
5f7f726d 1582 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1583
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1585 /*
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1588 */
dfd07d72
DV		 1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1591 }
5f7f726d
PZ		 1592
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1598 else
1599 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1600 else
1601 val |= TRANS_PROGRESSIVE;
1602
040484af
JB		 1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1606}
1607
8fb033d7 1608static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1609 enum transcoder cpu_transcoder)
040484af 1610{
8fb033d7 1611 u32 val, pipeconf_val;
8fb033d7
PZ		 1612
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1615
8fb033d7 1616 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1619
223a6fdf
PZ		 1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1624
25f3ef11 1625 val = TRANS_ENABLE;
937bb610 1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1627
9a76b1c6
PZ		 1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
a35f2679 1630 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
ab9412ba
DV		 1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1636 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1637}
1638
b8a4f404
PZ		 1639static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum pipe pipe)
040484af 1641{
23670b32
DV		 1642 struct drm_device *dev = dev_priv->dev;
1643 uint32_t reg, val;
040484af
JB		 1644
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1648
291906f1
JB		 1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1651
ab9412ba 1652 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1659
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1666 }
040484af
JB		 1667}
1668
ab4d966c 1669static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1670{
8fb033d7
PZ		 1671 u32 val;
1672
ab9412ba 1673 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1674 val &= ~TRANS_ENABLE;
ab9412ba 1675 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1676 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1678 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1679
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1683 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1684}
1685
b24e7179 1686/**
309cfea8 1687 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
040484af 1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1691 *
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1698 * returning.
1699 */
040484af 1700static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1701 bool pch_port, bool dsi)
b24e7179 1702{
702e7a56
PZ		 1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704 pipe);
1a240d4d 1705 enum pipe pch_transcoder;
b24e7179
JB		 1706 int reg;
1707 u32 val;
1708
58c6eaa2 1709 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1710 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1711 assert_sprites_disabled(dev_priv, pipe);
1712
681e5811 1713 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1714 pch_transcoder = TRANSCODER_A;
1715 else
1716 pch_transcoder = pipe;
1717
b24e7179
JB		 1718 /*
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1721 * need the check.
1722 */
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1724 if (dsi)
1725 assert_dsi_pll_enabled(dev_priv);
1726 else
1727 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1728 else {
1729 if (pch_port) {
1730 /* if driving the PCH, we need FDI enabled */
cc391bbb 1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
040484af
JB		 1734 }
1735 /* FIXME: assert CPU port conditions for SNB+ */
1736 }
b24e7179 1737
702e7a56 1738 reg = PIPECONF(cpu_transcoder);
b24e7179 1739 val = I915_READ(reg);
00d70b15
CW		 1740 if (val & PIPECONF_ENABLE)
1741 return;
1742
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
1747/**
309cfea8 1748 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1751 *
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe has shut down before returning.
1758 */
1759static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760 enum pipe pipe)
1761{
702e7a56
PZ		 1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
b24e7179
JB		 1764 int reg;
1765 u32 val;
1766
1767 /*
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1770 */
1771 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1772 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1773 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1774
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777 return;
1778
702e7a56 1779 reg = PIPECONF(cpu_transcoder);
b24e7179 1780 val = I915_READ(reg);
00d70b15
CW		 1781 if ((val & PIPECONF_ENABLE) == 0)
1782 return;
1783
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786}
1787
d74362c9
KP		 1788/*
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1791 */
6f1d69b0 1792void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1793 enum plane plane)
1794{
14f86147
DL		 1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797 else
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1799}
1800
b24e7179
JB		 1801/**
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1806 *
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 */
1809static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1811{
1812 int reg;
1813 u32 val;
1814
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1817
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
00d70b15
CW		 1820 if (val & DISPLAY_PLANE_ENABLE)
1821 return;
1822
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1824 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1826}
1827
b24e7179
JB		 1828/**
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1833 *
1834 * Disable @plane; should be an independent operation.
1835 */
1836static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1838{
1839 int reg;
1840 u32 val;
1841
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
00d70b15
CW		 1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845 return;
1846
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
693db184
CW		 1852static bool need_vtd_wa(struct drm_device *dev)
1853{
1854#ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856 return true;
1857#endif
1858 return false;
1859}
1860
127bd2ac 1861int
48b956c5 1862intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1863 struct drm_i915_gem_object *obj,
919926ae 1864 struct intel_ring_buffer *pipelined)
6b95a207 1865{
ce453d81 1866 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1867 u32 alignment;
1868 int ret;
1869
05394f39 1870 switch (obj->tiling_mode) {
6b95a207 1871 case I915_TILING_NONE:
534843da
CW		 1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
a6c45cf0 1874 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1875 alignment = 4 * 1024;
1876 else
1877 alignment = 64 * 1024;
6b95a207
KH		 1878 break;
1879 case I915_TILING_X:
1880 /* pin() will align the object as required by fence */
1881 alignment = 0;
1882 break;
1883 case I915_TILING_Y:
8bb6e959
DV		 1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
693db184
CW		 1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1896 * the VT-d warning.
1897 */
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1900
ce453d81 1901 dev_priv->mm.interruptible = false;
2da3b9b9 1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1903 if (ret)
ce453d81 1904 goto err_interruptible;
6b95a207
KH		 1905
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1910 */
06d98131 1911 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1912 if (ret)
1913 goto err_unpin;
1690e1eb 1914
9a5a53b3 1915 i915_gem_object_pin_fence(obj);
6b95a207 1916
ce453d81 1917 dev_priv->mm.interruptible = true;
6b95a207 1918 return 0;
48b956c5
CW		 1919
1920err_unpin:
cc98b413 1921 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1922err_interruptible:
1923 dev_priv->mm.interruptible = true;
48b956c5 1924 return ret;
6b95a207
KH		 1925}
1926
1690e1eb
CW		 1927void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928{
1929 i915_gem_object_unpin_fence(obj);
cc98b413 1930 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1931}
1932
c2c75131
DV		 1933/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
bc752862
CW		 1935unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1937 unsigned int cpp,
1938 unsigned int pitch)
c2c75131 1939{
bc752862
CW		 1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
c2c75131 1942
bc752862
CW		 1943 tile_rows = *y / 8;
1944 *y %= 8;
c2c75131 1945
bc752862
CW		 1946 tiles = *x / (512/cpp);
1947 *x %= 512/cpp;
1948
1949 return tile_rows * pitch * 8 + tiles * 4096;
1950 } else {
1951 unsigned int offset;
1952
1953 offset = *y * pitch + *x * cpp;
1954 *y = 0;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1957 }
c2c75131
DV		 1958}
1959
17638cd6
JB		 1960static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961 int x, int y)
81255565
JB		 1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
05394f39 1967 struct drm_i915_gem_object *obj;
81255565 1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
81255565 1970 u32 dspcntr;
5eddb70b 1971 u32 reg;
81255565
JB		 1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 break;
1977 default:
84f44ce7 1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1979 return -EINVAL;
1980 }
1981
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
81255565 1984
5eddb70b
CW		 1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
81255565
JB		 1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1989 switch (fb->pixel_format) {
1990 case DRM_FORMAT_C8:
81255565
JB		 1991 dspcntr |= DISPPLANE_8BPP;
1992 break;
57779d06
VS		 1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
81255565 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
1999 break;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2003 break;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2007 break;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2011 break;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2015 break;
2016 default:
baba133a 2017 BUG();
81255565 2018 }
57779d06 2019
a6c45cf0 2020 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2021 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2022 dspcntr |= DISPPLANE_TILED;
2023 else
2024 dspcntr &= ~DISPPLANE_TILED;
2025 }
2026
de1aa629
VS		 2027 if (IS_G4X(dev))
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
5eddb70b 2030 I915_WRITE(reg, dspcntr);
81255565 2031
e506a0c6 2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2033
c2c75131
DV		 2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
bc752862
CW		 2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2038 fb->pitches[0]);
c2c75131
DV		 2039 linear_offset -= intel_crtc->dspaddr_offset;
2040 } else {
e506a0c6 2041 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2042 }
e506a0c6 2043
f343c5f6
BW		 2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046 fb->pitches[0]);
01f2c773 2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2048 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2053 } else
f343c5f6 2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2055 POSTING_READ(reg);
81255565 2056
17638cd6
JB		 2057 return 0;
2058}
2059
2060static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2062{
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
e506a0c6 2069 unsigned long linear_offset;
17638cd6
JB		 2070 u32 dspcntr;
2071 u32 reg;
2072
2073 switch (plane) {
2074 case 0:
2075 case 1:
27f8227b 2076 case 2:
17638cd6
JB		 2077 break;
2078 default:
84f44ce7 2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2080 return -EINVAL;
2081 }
2082
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2085
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2090 switch (fb->pixel_format) {
2091 case DRM_FORMAT_C8:
17638cd6
JB		 2092 dspcntr |= DISPPLANE_8BPP;
2093 break;
57779d06
VS		 2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2096 break;
57779d06
VS		 2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2100 break;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2104 break;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2108 break;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2112 break;
2113 default:
baba133a 2114 BUG();
17638cd6
JB		 2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
1f5d76db
PZ		 2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124 else
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2126
2127 I915_WRITE(reg, dspcntr);
2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2130 intel_crtc->dspaddr_offset =
bc752862
CW		 2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2133 fb->pitches[0]);
c2c75131 2134 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2135
f343c5f6
BW		 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138 fb->pitches[0]);
01f2c773 2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144 } else {
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147 }
17638cd6
JB		 2148 POSTING_READ(reg);
2149
2150 return 0;
2151}
2152
2153/* Assume fb object is pinned & idle & fenced and just update base pointers */
2154static int
2155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2160
6b8e6ed0
CW		 2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
3dec0095 2163 intel_increase_pllclock(crtc);
81255565 2164
6b8e6ed0 2165 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2166}
2167
96a02917
VS		 2168void intel_display_handle_reset(struct drm_device *dev)
2169{
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2172
2173 /*
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2177 *
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2181 *
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2185 */
2186
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2190
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2193 }
2194
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2201 crtc->x, crtc->y);
2202 mutex_unlock(&crtc->mutex);
2203 }
2204}
2205
14667a4b
CW		 2206static int
2207intel_finish_fb(struct drm_framebuffer *old_fb)
2208{
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2212 int ret;
2213
14667a4b
CW		 2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2217 * framebuffer.
2218 *
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2221 */
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2225
2226 return ret;
2227}
2228
198598d0
VS		 2229static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230{
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 if (!dev->primary->master)
2236 return;
2237
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2240 return;
2241
2242 switch (intel_crtc->pipe) {
2243 case 0:
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2246 break;
2247 case 1:
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2250 break;
2251 default:
2252 break;
2253 }
2254}
2255
5c3b82e2 2256static int
3c4fdcfb 2257intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2258 struct drm_framebuffer *fb)
79e53945
JB		 2259{
2260 struct drm_device *dev = crtc->dev;
6b8e6ed0 2261 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2263 struct drm_framebuffer *old_fb;
5c3b82e2 2264 int ret;
79e53945
JB		 2265
2266 /* no fb bound */
94352cf9 2267 if (!fb) {
a5071c2f 2268 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2269 return 0;
2270 }
2271
7eb552ae 2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2276 return -EINVAL;
79e53945
JB		 2277 }
2278
5c3b82e2 2279 mutex_lock(&dev->struct_mutex);
265db958 2280 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2281 to_intel_framebuffer(fb)->obj,
919926ae 2282 NULL);
5c3b82e2
CW		 2283 if (ret != 0) {
2284 mutex_unlock(&dev->struct_mutex);
a5071c2f 2285 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2286 return ret;
2287 }
79e53945 2288
4d6a3e63
JB		 2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
2294 if (!intel_crtc->config.pch_pfit.size &&
2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300 }
2301 }
2302
94352cf9 2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2304 if (ret) {
94352cf9 2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2306 mutex_unlock(&dev->struct_mutex);
a5071c2f 2307 DRM_ERROR("failed to update base address\n");
4e6cfefc 2308 return ret;
79e53945 2309 }
3c4fdcfb 2310
94352cf9
DV		 2311 old_fb = crtc->fb;
2312 crtc->fb = fb;
6c4c86f5
DV		 2313 crtc->x = x;
2314 crtc->y = y;
94352cf9 2315
b7f1de28 2316 if (old_fb) {
d7697eea
DV		 2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2320 }
652c393a 2321
6b8e6ed0 2322 intel_update_fbc(dev);
4906557e 2323 intel_edp_psr_update(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
139ccd3f 2644 u32 reg, temp, i, j;
357555c0
JB		 2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
139ccd3f
JB		 2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
357555c0 2668
139ccd3f
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
357555c0 2675
139ccd3f 2676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
139ccd3f
JB		 2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2686
139ccd3f
JB		 2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2689
139ccd3f 2690 reg = FDI_RX_CTL(pipe);
357555c0 2691 temp = I915_READ(reg);
139ccd3f
JB		 2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2695
139ccd3f
JB		 2696 POSTING_READ(reg);
2697 udelay(1); /* should be 0.5us */
357555c0 2698
139ccd3f
JB		 2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2703
139ccd3f
JB		 2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708 i);
2709 break;
2710 }
2711 udelay(1); /* should be 0.5us */
2712 }
2713 if (i == 4) {
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715 continue;
2716 }
357555c0 2717
139ccd3f 2718 /* Train 2 */
357555c0
JB		 2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
139ccd3f
JB		 2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2724
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
139ccd3f 2732 udelay(2); /* should be 1.5us */
357555c0 2733
139ccd3f
JB		 2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2738
139ccd3f
JB		 2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743 i);
2744 goto train_done;
2745 }
2746 udelay(2); /* should be 1.5us */
357555c0 2747 }
139ccd3f
JB		 2748 if (i == 4)
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2750 }
357555c0 2751
139ccd3f 2752train_done:
357555c0
JB		 2753 DRM_DEBUG_KMS("FDI train done.\n");
2754}
2755
88cefb6c 2756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2757{
88cefb6c 2758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2760 int pipe = intel_crtc->pipe;
5eddb70b 2761 u32 reg, temp;
79e53945 2762
c64e311e 2763
c98e9dcf 2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
627eb5a3
DV		 2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772 POSTING_READ(reg);
c98e9dcf
JB		 2773 udelay(200);
2774
2775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779 POSTING_READ(reg);
c98e9dcf
JB		 2780 udelay(200);
2781
20749730
PZ		 2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2787
20749730
PZ		 2788 POSTING_READ(reg);
2789 udelay(100);
6be4a607 2790 }
0e23b99d
JB		 2791}
2792
88cefb6c
DV		 2793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794{
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
2811 udelay(100);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817 /* Wait for the clocks to turn off. */
2818 POSTING_READ(reg);
2819 udelay(100);
2820}
2821
0fc932b8
JB		 2822static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 u32 reg, temp;
2829
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 POSTING_READ(reg);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
dfd07d72 2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842 POSTING_READ(reg);
2843 udelay(100);
2844
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2848 }
0fc932b8
JB		 2849
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2856
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862 } else {
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865 }
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
dfd07d72 2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
5bb61643
CW		 2875static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2880 unsigned long flags;
2881 bool pending;
2882
10d83730
VS		 2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2885 return false;
2886
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891 return pending;
2892}
2893
e6c3a2a6
CW		 2894static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895{
0f91128d 2896 struct drm_device *dev = crtc->dev;
5bb61643 2897 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2898
2899 if (crtc->fb == NULL)
2900 return;
2901
2c10d571
DV		 2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
5bb61643
CW		 2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2906
0f91128d
CW		 2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2910}
2911
e615efe4
ED		 2912/* Program iCLKIP clock to the desired frequency */
2913static void lpt_program_iclkip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
12d7ceed 2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
e615efe4
ED		 2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919 u32 temp;
2920
09153000
DV		 2921 mutex_lock(&dev_priv->dpio_lock);
2922
e615efe4
ED		 2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2925 */
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 SBI_SSCCTL_DISABLE,
2932 SBI_ICLK);
e615efe4
ED		 2933
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2935 if (clock == 20000) {
e615efe4
ED		 2936 auxdiv = 1;
2937 divsel = 0x41;
2938 phaseinc = 0x20;
2939 } else {
2940 /* The iCLK virtual clock root frequency is in MHz,
12d7ceed 2941 * but the adjusted_mode->clock in in KHz. To get the divisors,
e615efe4
ED		 2942 * it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2944 * precision.
2945 */
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2949
12d7ceed 2950 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2953
2954 auxdiv = 0;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2957 }
2958
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2966 clock,
e615efe4
ED		 2967 auxdiv,
2968 divsel,
2969 phasedir,
2970 phaseinc);
2971
2972 /* Program SSCDIVINTPHASE6 */
988d6ee8 2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Program SSCAUXDIV */
988d6ee8 2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2987
2988 /* Enable modulator and associated divider */
988d6ee8 2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2990 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2997
2998 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2999}
3000
275f01b2
DV		 3001static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3003{
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3014
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023}
3024
f67a559d
JB		 3025/*
3026 * Enable PCH resources required for PCH ports:
3027 * - PCH PLLs
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3031 * - transcoder
3032 */
3033static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
ee7b9f93 3039 u32 reg, temp;
2c07245f 3040
ab9412ba 3041 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3042
cd986abb
DV		 3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
c98e9dcf 3048 /* For PCH output, training FDI link */
674cf967 3049 dev_priv->display.fdi_link_train(crtc);
2c07245f 3050
3ad8a208
DV		 3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
303b81e0 3053 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3054 u32 sel;
4b645f14 3055
c98e9dcf 3056 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3060 temp |= sel;
3061 else
3062 temp &= ~sel;
c98e9dcf 3063 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3064 }
5eddb70b 3065
3ad8a208
DV		 3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3074
d9b6cb56
JB		 3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3078
303b81e0 3079 intel_fdi_normal_train(crtc);
5e84e1a4 3080
c98e9dcf
JB		 3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3089 TRANS_DP_SYNC_MASK |
3090 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
9325c9f0 3093 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3094
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3099
3100 switch (intel_trans_dp_port_sel(crtc)) {
3101 case PCH_DP_B:
5eddb70b 3102 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3103 break;
3104 case PCH_DP_C:
5eddb70b 3105 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3106 break;
3107 case PCH_DP_D:
5eddb70b 3108 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3109 break;
3110 default:
e95d41e1 3111 BUG();
32f9d658 3112 }
2c07245f 3113
5eddb70b 3114 I915_WRITE(reg, temp);
6be4a607 3115 }
b52eb4dc 3116
b8a4f404 3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3118}
3119
1507e5bd
PZ		 3120static void lpt_pch_enable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3126
ab9412ba 3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3128
8c52b5e8 3129 lpt_program_iclkip(crtc);
1507e5bd 3130
0540e488 3131 /* Set transcoder timing. */
275f01b2 3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3133
937bb610 3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3135}
3136
e2b78267 3137static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3138{
e2b78267 3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3140
3141 if (pll == NULL)
3142 return;
3143
3144 if (pll->refcount == 0) {
46edb027 3145 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3146 return;
3147 }
3148
f4a091c7
DV		 3149 if (--pll->refcount == 0) {
3150 WARN_ON(pll->on);
3151 WARN_ON(pll->active);
3152 }
3153
a43f6e0f 3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3155}
3156
b89a1d39 3157static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3158{
e2b78267
DV		 3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
ee7b9f93 3162
ee7b9f93 3163 if (pll) {
46edb027
DV		 3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
e2b78267 3166 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3167 }
3168
98b6bd99
DV		 3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3171 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3172 pll = &dev_priv->shared_dplls[i];
98b6bd99 3173
46edb027
DV		 3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
98b6bd99
DV		 3176
3177 goto found;
3178 }
3179
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
b89a1d39
DV		 3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
46edb027 3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3190 crtc->base.base.id,
46edb027 3191 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3200 if (pll->refcount == 0) {
46edb027
DV		 3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
a43f6e0f 3210 crtc->config.shared_dpll = i;
46edb027
DV		 3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
ee7b9f93 3213
cdbd2316 3214 if (pll->active == 0) {
66e985c0
DV		 3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3217
46edb027 3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3219 WARN_ON(pll->on);
e9d6944e 3220 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3221
15bdd4cf 3222 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3223 }
3224 pll->refcount++;
e04c7350 3225
ee7b9f93
JB		 3226 return pll;
3227}
3228
a1520318 3229static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3232 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3233 u32 temp;
3234
3235 temp = I915_READ(dslreg);
3236 udelay(500);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3238 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3240 }
3241}
3242
b074cec8
JB		 3243static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3248
0ef37f3f 3249 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3252 * e.g. x201.
3253 */
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3257 else
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3261 }
3262}
3263
bb53d4ae
VS		 3264static void intel_enable_planes(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3269
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3273}
3274
3275static void intel_disable_planes(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3280
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3284}
3285
f67a559d
JB		 3286static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3291 struct intel_encoder *encoder;
f67a559d
JB		 3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
f67a559d 3294
08a48469
DV		 3295 WARN_ON(!crtc->enabled);
3296
f67a559d
JB		 3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
8664281b
PZ		 3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
f6736a1a 3305 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3306 if (encoder->pre_enable)
3307 encoder->pre_enable(encoder);
f67a559d 3308
5bfe2ac0 3309 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3310 /* Note: FDI PLL enabling _must_ be done before we enable the
3311 * cpu pipes, hence this is separate from all the other fdi/pch
3312 * enabling. */
88cefb6c 3313 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3314 } else {
3315 assert_fdi_tx_disabled(dev_priv, pipe);
3316 assert_fdi_rx_disabled(dev_priv, pipe);
3317 }
f67a559d 3318
b074cec8 3319 ironlake_pfit_enable(intel_crtc);
f67a559d 3320
9c54c0dd
JB		 3321 /*
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3323 * clocks enabled
3324 */
3325 intel_crtc_load_lut(crtc);
3326
f37fcc2a 3327 intel_update_watermarks(crtc);
5bfe2ac0 3328 intel_enable_pipe(dev_priv, pipe,
23538ef1 3329 intel_crtc->config.has_pch_encoder, false);
f67a559d 3330 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3331 intel_enable_planes(crtc);
5c38d48c 3332 intel_crtc_update_cursor(crtc, true);
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
f67a559d 3335 ironlake_pch_enable(crtc);
c98e9dcf 3336
d1ebd816 3337 mutex_lock(&dev->struct_mutex);
bed4a673 3338 intel_update_fbc(dev);
d1ebd816
BW		 3339 mutex_unlock(&dev->struct_mutex);
3340
fa5c73b1
DV		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
61b77ddd
DV		 3343
3344 if (HAS_PCH_CPT(dev))
a1520318 3345 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3346
3347 /*
3348 * There seems to be a race in PCH platform hw (at least on some
3349 * outputs) where an enabled pipe still completes any pageflip right
3350 * away (as if the pipe is off) instead of waiting for vblank. As soon
3351 * as the first vblank happend, everything works as expected. Hence just
3352 * wait for one vblank before returning to avoid strange things
3353 * happening.
3354 */
3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3356}
3357
42db64ef
PZ		 3358/* IPS only exists on ULT machines and is tied to pipe A. */
3359static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360{
f5adf94e 3361 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3362}
3363
3364static void hsw_enable_ips(struct intel_crtc *crtc)
3365{
3366 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368 if (!crtc->config.ips_enabled)
3369 return;
3370
3371 /* We can only enable IPS after we enable a plane and wait for a vblank.
3372 * We guarantee that the plane is enabled by calling intel_enable_ips
3373 * only after intel_enable_plane. And intel_enable_plane already waits
3374 * for a vblank, so all we need to do here is to enable the IPS bit. */
3375 assert_plane_enabled(dev_priv, crtc->plane);
3376 I915_WRITE(IPS_CTL, IPS_ENABLE);
3377}
3378
3379static void hsw_disable_ips(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384 if (!crtc->config.ips_enabled)
3385 return;
3386
3387 assert_plane_enabled(dev_priv, crtc->plane);
3388 I915_WRITE(IPS_CTL, 0);
3389
3390 /* We need to wait for a vblank before we can disable the plane. */
3391 intel_wait_for_vblank(dev, crtc->pipe);
3392}
3393
4f771f10
PZ		 3394static void haswell_crtc_enable(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 struct intel_encoder *encoder;
3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
4f771f10
PZ		 3402
3403 WARN_ON(!crtc->enabled);
3404
3405 if (intel_crtc->active)
3406 return;
3407
3408 intel_crtc->active = true;
8664281b
PZ		 3409
3410 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411 if (intel_crtc->config.has_pch_encoder)
3412 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
5bfe2ac0 3414 if (intel_crtc->config.has_pch_encoder)
04945641 3415 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3416
3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 if (encoder->pre_enable)
3419 encoder->pre_enable(encoder);
3420
1f544388 3421 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3422
b074cec8 3423 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3424
3425 /*
3426 * On ILK+ LUT must be loaded before the pipe is running but with
3427 * clocks enabled
3428 */
3429 intel_crtc_load_lut(crtc);
3430
1f544388 3431 intel_ddi_set_pipe_settings(crtc);
8228c251 3432 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3433
f37fcc2a 3434 intel_update_watermarks(crtc);
5bfe2ac0 3435 intel_enable_pipe(dev_priv, pipe,
23538ef1 3436 intel_crtc->config.has_pch_encoder, false);
4f771f10 3437 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3438 intel_enable_planes(crtc);
5c38d48c 3439 intel_crtc_update_cursor(crtc, true);
4f771f10 3440
42db64ef
PZ		 3441 hsw_enable_ips(intel_crtc);
3442
5bfe2ac0 3443 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3444 lpt_pch_enable(crtc);
4f771f10
PZ		 3445
3446 mutex_lock(&dev->struct_mutex);
3447 intel_update_fbc(dev);
3448 mutex_unlock(&dev->struct_mutex);
3449
8807e55b 3450 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3451 encoder->enable(encoder);
8807e55b
JN		 3452 intel_opregion_notify_encoder(encoder, true);
3453 }
4f771f10 3454
4f771f10
PZ		 3455 /*
3456 * There seems to be a race in PCH platform hw (at least on some
3457 * outputs) where an enabled pipe still completes any pageflip right
3458 * away (as if the pipe is off) instead of waiting for vblank. As soon
3459 * as the first vblank happend, everything works as expected. Hence just
3460 * wait for one vblank before returning to avoid strange things
3461 * happening.
3462 */
3463 intel_wait_for_vblank(dev, intel_crtc->pipe);
3464}
3465
3f8dce3a
DV		 3466static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467{
3468 struct drm_device *dev = crtc->base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 int pipe = crtc->pipe;
3471
3472 /* To avoid upsetting the power well on haswell only disable the pfit if
3473 * it's in use. The hw state code will make sure we get this right. */
3474 if (crtc->config.pch_pfit.size) {
3475 I915_WRITE(PF_CTL(pipe), 0);
3476 I915_WRITE(PF_WIN_POS(pipe), 0);
3477 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478 }
3479}
3480
6be4a607
JB		 3481static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482{
3483 struct drm_device *dev = crtc->dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3486 struct intel_encoder *encoder;
6be4a607
JB		 3487 int pipe = intel_crtc->pipe;
3488 int plane = intel_crtc->plane;
5eddb70b 3489 u32 reg, temp;
b52eb4dc 3490
ef9c3aee 3491
f7abfe8b
CW		 3492 if (!intel_crtc->active)
3493 return;
3494
ea9d758d
DV		 3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->disable(encoder);
3497
e6c3a2a6 3498 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3499 drm_vblank_off(dev, pipe);
913d8d11 3500
5c3fe8b0 3501 if (dev_priv->fbc.plane == plane)
973d04f9 3502 intel_disable_fbc(dev);
2c07245f 3503
0d5b8c61 3504 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3505 intel_disable_planes(crtc);
0d5b8c61
VS		 3506 intel_disable_plane(dev_priv, plane, pipe);
3507
d925c59a
DV		 3508 if (intel_crtc->config.has_pch_encoder)
3509 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
b24e7179 3511 intel_disable_pipe(dev_priv, pipe);
32f9d658 3512
3f8dce3a 3513 ironlake_pfit_disable(intel_crtc);
2c07245f 3514
bf49ec8c
DV		 3515 for_each_encoder_on_crtc(dev, crtc, encoder)
3516 if (encoder->post_disable)
3517 encoder->post_disable(encoder);
2c07245f 3518
d925c59a
DV		 3519 if (intel_crtc->config.has_pch_encoder) {
3520 ironlake_fdi_disable(crtc);
913d8d11 3521
d925c59a
DV		 3522 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3524
d925c59a
DV		 3525 if (HAS_PCH_CPT(dev)) {
3526 /* disable TRANS_DP_CTL */
3527 reg = TRANS_DP_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530 TRANS_DP_PORT_SEL_MASK);
3531 temp |= TRANS_DP_PORT_SEL_NONE;
3532 I915_WRITE(reg, temp);
3533
3534 /* disable DPLL_SEL */
3535 temp = I915_READ(PCH_DPLL_SEL);
11887397 3536 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3537 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3538 }
e3421a18 3539
d925c59a 3540 /* disable PCH DPLL */
e72f9fbf 3541 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3542
d925c59a
DV		 3543 ironlake_fdi_pll_disable(intel_crtc);
3544 }
6b383a7f 3545
f7abfe8b 3546 intel_crtc->active = false;
46ba614c 3547 intel_update_watermarks(crtc);
d1ebd816
BW		 3548
3549 mutex_lock(&dev->struct_mutex);
6b383a7f 3550 intel_update_fbc(dev);
d1ebd816 3551 mutex_unlock(&dev->struct_mutex);
6be4a607 3552}
1b3c7a47 3553
4f771f10 3554static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3555{
4f771f10
PZ		 3556 struct drm_device *dev = crtc->dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3559 struct intel_encoder *encoder;
3560 int pipe = intel_crtc->pipe;
3561 int plane = intel_crtc->plane;
3b117c8f 3562 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3563
4f771f10
PZ		 3564 if (!intel_crtc->active)
3565 return;
3566
8807e55b
JN		 3567 for_each_encoder_on_crtc(dev, crtc, encoder) {
3568 intel_opregion_notify_encoder(encoder, false);
4f771f10 3569 encoder->disable(encoder);
8807e55b 3570 }
4f771f10
PZ		 3571
3572 intel_crtc_wait_for_pending_flips(crtc);
3573 drm_vblank_off(dev, pipe);
4f771f10 3574
891348b2 3575 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3576 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3577 intel_disable_fbc(dev);
3578
42db64ef
PZ		 3579 hsw_disable_ips(intel_crtc);
3580
0d5b8c61 3581 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3582 intel_disable_planes(crtc);
891348b2
RV		 3583 intel_disable_plane(dev_priv, plane, pipe);
3584
8664281b
PZ		 3585 if (intel_crtc->config.has_pch_encoder)
3586 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3587 intel_disable_pipe(dev_priv, pipe);
3588
ad80a810 3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3590
3f8dce3a 3591 ironlake_pfit_disable(intel_crtc);
4f771f10 3592
1f544388 3593 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3598
88adfff1 3599 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3600 lpt_disable_pch_transcoder(dev_priv);
8664281b 3601 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3602 intel_ddi_fdi_disable(crtc);
83616634 3603 }
4f771f10
PZ		 3604
3605 intel_crtc->active = false;
46ba614c 3606 intel_update_watermarks(crtc);
4f771f10
PZ		 3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611}
3612
ee7b9f93
JB		 3613static void ironlake_crtc_off(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3616 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3617}
3618
6441ab5f
PZ		 3619static void haswell_crtc_off(struct drm_crtc *crtc)
3620{
3621 intel_ddi_put_crtc_pll(crtc);
3622}
3623
02e792fb
DV		 3624static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625{
02e792fb 3626 if (!enable && intel_crtc->overlay) {
23f09ce3 3627 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3628 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3629
23f09ce3 3630 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3631 dev_priv->mm.interruptible = false;
3632 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633 dev_priv->mm.interruptible = true;
23f09ce3 3634 mutex_unlock(&dev->struct_mutex);
02e792fb 3635 }
02e792fb 3636
5dcdbcb0
CW		 3637 /* Let userspace switch the overlay on again. In most cases userspace
3638 * has to recompute where to put it anyway.
3639 */
02e792fb
DV		 3640}
3641
61bc95c1
EE		 3642/**
3643 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644 * cursor plane briefly if not already running after enabling the display
3645 * plane.
3646 * This workaround avoids occasional blank screens when self refresh is
3647 * enabled.
3648 */
3649static void
3650g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651{
3652 u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654 if ((cntl & CURSOR_MODE) == 0) {
3655 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659 intel_wait_for_vblank(dev_priv->dev, pipe);
3660 I915_WRITE(CURCNTR(pipe), cntl);
3661 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663 }
3664}
3665
2dd24552
JB		 3666static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc_config *pipe_config = &crtc->config;
3671
328d8e82 3672 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3673 return;
3674
2dd24552 3675 /*
c0b03411
DV		 3676 * The panel fitter should only be adjusted whilst the pipe is disabled,
3677 * according to register description and PRM.
2dd24552 3678 */
c0b03411
DV		 3679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3681
b074cec8
JB		 3682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3684
3685 /* Border color in case we don't scale up to the full screen. Black by
3686 * default, change to something else for debugging. */
3687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3688}
3689
89b667f8
JB		 3690static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691{
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
23538ef1 3698 bool is_dsi;
89b667f8
JB		 3699
3700 WARN_ON(!crtc->enabled);
3701
3702 if (intel_crtc->active)
3703 return;
3704
3705 intel_crtc->active = true;
89b667f8 3706
89b667f8
JB		 3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_pll_enable)
3709 encoder->pre_pll_enable(encoder);
3710
23538ef1
JN		 3711 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
e9fd1c02
JN		 3713 if (!is_dsi)
3714 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->pre_enable)
3718 encoder->pre_enable(encoder);
3719
2dd24552
JB		 3720 i9xx_pfit_enable(intel_crtc);
3721
63cbb074
VS		 3722 intel_crtc_load_lut(crtc);
3723
f37fcc2a 3724 intel_update_watermarks(crtc);
23538ef1 3725 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3726 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3727 intel_enable_planes(crtc);
5c38d48c 3728 intel_crtc_update_cursor(crtc, true);
89b667f8 3729
89b667f8 3730 intel_update_fbc(dev);
5004945f
JN		 3731
3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->enable(encoder);
89b667f8
JB		 3734}
3735
0b8765c6 3736static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3737{
3738 struct drm_device *dev = crtc->dev;
79e53945
JB		 3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3741 struct intel_encoder *encoder;
79e53945 3742 int pipe = intel_crtc->pipe;
80824003 3743 int plane = intel_crtc->plane;
79e53945 3744
08a48469
DV		 3745 WARN_ON(!crtc->enabled);
3746
f7abfe8b
CW		 3747 if (intel_crtc->active)
3748 return;
3749
3750 intel_crtc->active = true;
6b383a7f 3751
9d6d9f19
MK		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 if (encoder->pre_enable)
3754 encoder->pre_enable(encoder);
3755
f6736a1a
DV		 3756 i9xx_enable_pll(intel_crtc);
3757
2dd24552
JB		 3758 i9xx_pfit_enable(intel_crtc);
3759
63cbb074
VS		 3760 intel_crtc_load_lut(crtc);
3761
f37fcc2a 3762 intel_update_watermarks(crtc);
23538ef1 3763 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3764 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3765 intel_enable_planes(crtc);
22e407d7 3766 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3767 if (IS_G4X(dev))
3768 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3769 intel_crtc_update_cursor(crtc, true);
79e53945 3770
0b8765c6
JB		 3771 /* Give the overlay scaler a chance to enable if it's on this pipe */
3772 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3773
f440eb13 3774 intel_update_fbc(dev);
ef9c3aee 3775
fa5c73b1
DV		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 encoder->enable(encoder);
0b8765c6 3778}
79e53945 3779
87476d63
DV		 3780static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781{
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3784
328d8e82
DV		 3785 if (!crtc->config.gmch_pfit.control)
3786 return;
87476d63 3787
328d8e82 3788 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3789
328d8e82
DV		 3790 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791 I915_READ(PFIT_CONTROL));
3792 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3793}
3794
0b8765c6
JB		 3795static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3800 struct intel_encoder *encoder;
0b8765c6
JB		 3801 int pipe = intel_crtc->pipe;
3802 int plane = intel_crtc->plane;
ef9c3aee 3803
f7abfe8b
CW		 3804 if (!intel_crtc->active)
3805 return;
3806
ea9d758d
DV		 3807 for_each_encoder_on_crtc(dev, crtc, encoder)
3808 encoder->disable(encoder);
3809
0b8765c6 3810 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3811 intel_crtc_wait_for_pending_flips(crtc);
3812 drm_vblank_off(dev, pipe);
0b8765c6 3813
5c3fe8b0 3814 if (dev_priv->fbc.plane == plane)
973d04f9 3815 intel_disable_fbc(dev);
79e53945 3816
0d5b8c61
VS		 3817 intel_crtc_dpms_overlay(intel_crtc, false);
3818 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3819 intel_disable_planes(crtc);
b24e7179 3820 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3821
b24e7179 3822 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3823
87476d63 3824 i9xx_pfit_disable(intel_crtc);
24a1f16d 3825
89b667f8
JB		 3826 for_each_encoder_on_crtc(dev, crtc, encoder)
3827 if (encoder->post_disable)
3828 encoder->post_disable(encoder);
3829
e9fd1c02
JN		 3830 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3832
f7abfe8b 3833 intel_crtc->active = false;
46ba614c 3834 intel_update_watermarks(crtc);
f37fcc2a
VS		 3835
3836 intel_update_fbc(dev);
0b8765c6
JB		 3837}
3838
ee7b9f93
JB		 3839static void i9xx_crtc_off(struct drm_crtc *crtc)
3840{
3841}
3842
976f8a20
DV		 3843static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844 bool enabled)
2c07245f
ZW		 3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_master_private *master_priv;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 int pipe = intel_crtc->pipe;
79e53945
JB		 3850
3851 if (!dev->primary->master)
3852 return;
3853
3854 master_priv = dev->primary->master->driver_priv;
3855 if (!master_priv->sarea_priv)
3856 return;
3857
79e53945
JB		 3858 switch (pipe) {
3859 case 0:
3860 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862 break;
3863 case 1:
3864 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866 break;
3867 default:
9db4a9c7 3868 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3869 break;
3870 }
79e53945
JB		 3871}
3872
976f8a20
DV		 3873/**
3874 * Sets the power management mode of the pipe and plane.
3875 */
3876void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877{
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_encoder *intel_encoder;
3881 bool enable = false;
3882
3883 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884 enable |= intel_encoder->connectors_active;
3885
3886 if (enable)
3887 dev_priv->display.crtc_enable(crtc);
3888 else
3889 dev_priv->display.crtc_disable(crtc);
3890
3891 intel_crtc_update_sarea(crtc, enable);
3892}
3893
cdd59983
CW		 3894static void intel_crtc_disable(struct drm_crtc *crtc)
3895{
cdd59983 3896 struct drm_device *dev = crtc->dev;
976f8a20 3897 struct drm_connector *connector;
ee7b9f93 3898 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3900
976f8a20
DV		 3901 /* crtc should still be enabled when we disable it. */
3902 WARN_ON(!crtc->enabled);
3903
3904 dev_priv->display.crtc_disable(crtc);
c77bf565 3905 intel_crtc->eld_vld = false;
976f8a20 3906 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3907 dev_priv->display.off(crtc);
3908
931872fc 3909 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3910 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3911 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3912
3913 if (crtc->fb) {
3914 mutex_lock(&dev->struct_mutex);
1690e1eb 3915 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3916 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3917 crtc->fb = NULL;
3918 }
3919
3920 /* Update computed state. */
3921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922 if (!connector->encoder || !connector->encoder->crtc)
3923 continue;
3924
3925 if (connector->encoder->crtc != crtc)
3926 continue;
3927
3928 connector->dpms = DRM_MODE_DPMS_OFF;
3929 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3930 }
3931}
3932
ea5b213a 3933void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3934{
4ef69c7a 3935 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3936
ea5b213a
CW		 3937 drm_encoder_cleanup(encoder);
3938 kfree(intel_encoder);
7e7d76c3
JB		 3939}
3940
9237329d 3941/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3942 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943 * state of the entire output pipe. */
9237329d 3944static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3945{
5ab432ef
DV		 3946 if (mode == DRM_MODE_DPMS_ON) {
3947 encoder->connectors_active = true;
3948
b2cabb0e 3949 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3950 } else {
3951 encoder->connectors_active = false;
3952
b2cabb0e 3953 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3954 }
79e53945
JB		 3955}
3956
0a91ca29
DV		 3957/* Cross check the actual hw state with our own modeset state tracking (and it's
3958 * internal consistency). */
b980514c 3959static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3960{
0a91ca29
DV		 3961 if (connector->get_hw_state(connector)) {
3962 struct intel_encoder *encoder = connector->encoder;
3963 struct drm_crtc *crtc;
3964 bool encoder_enabled;
3965 enum pipe pipe;
3966
3967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968 connector->base.base.id,
3969 drm_get_connector_name(&connector->base));
3970
3971 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972 "wrong connector dpms state\n");
3973 WARN(connector->base.encoder != &encoder->base,
3974 "active connector not linked to encoder\n");
3975 WARN(!encoder->connectors_active,
3976 "encoder->connectors_active not set\n");
3977
3978 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979 WARN(!encoder_enabled, "encoder not enabled\n");
3980 if (WARN_ON(!encoder->base.crtc))
3981 return;
3982
3983 crtc = encoder->base.crtc;
3984
3985 WARN(!crtc->enabled, "crtc not enabled\n");
3986 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988 "encoder active on the wrong pipe\n");
3989 }
79e53945
JB		 3990}
3991
5ab432ef
DV		 3992/* Even simpler default implementation, if there's really no special case to
3993 * consider. */
3994void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3995{
5ab432ef 3996 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3997
5ab432ef
DV		 3998 /* All the simple cases only support two dpms states. */
3999 if (mode != DRM_MODE_DPMS_ON)
4000 mode = DRM_MODE_DPMS_OFF;
d4270e57 4001
5ab432ef
DV		 4002 if (mode == connector->dpms)
4003 return;
4004
4005 connector->dpms = mode;
4006
4007 /* Only need to change hw state when actually enabled */
4008 if (encoder->base.crtc)
4009 intel_encoder_dpms(encoder, mode);
4010 else
8af6cf88 4011 WARN_ON(encoder->connectors_active != false);
0a91ca29 4012
b980514c 4013 intel_modeset_check_state(connector->dev);
79e53945
JB		 4014}
4015
f0947c37
DV		 4016/* Simple connector->get_hw_state implementation for encoders that support only
4017 * one connector and no cloning and hence the encoder state determines the state
4018 * of the connector. */
4019bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4020{
24929352 4021 enum pipe pipe = 0;
f0947c37 4022 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4023
f0947c37 4024 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4025}
4026
1857e1da
DV		 4027static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028 struct intel_crtc_config *pipe_config)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_crtc *pipe_B_crtc =
4032 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 if (pipe_config->fdi_lanes > 4) {
4037 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038 pipe_name(pipe), pipe_config->fdi_lanes);
4039 return false;
4040 }
4041
4042 if (IS_HASWELL(dev)) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045 pipe_config->fdi_lanes);
4046 return false;
4047 } else {
4048 return true;
4049 }
4050 }
4051
4052 if (INTEL_INFO(dev)->num_pipes == 2)
4053 return true;
4054
4055 /* Ivybridge 3 pipe is really complicated */
4056 switch (pipe) {
4057 case PIPE_A:
4058 return true;
4059 case PIPE_B:
4060 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061 pipe_config->fdi_lanes > 2) {
4062 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063 pipe_name(pipe), pipe_config->fdi_lanes);
4064 return false;
4065 }
4066 return true;
4067 case PIPE_C:
1e833f40 4068 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4069 pipe_B_crtc->config.fdi_lanes <= 2) {
4070 if (pipe_config->fdi_lanes > 2) {
4071 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072 pipe_name(pipe), pipe_config->fdi_lanes);
4073 return false;
4074 }
4075 } else {
4076 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077 return false;
4078 }
4079 return true;
4080 default:
4081 BUG();
4082 }
4083}
4084
e29c22c0
DV		 4085#define RETRY 1
4086static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087 struct intel_crtc_config *pipe_config)
877d48d5 4088{
1857e1da 4089 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4090 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4091 int lane, link_bw, fdi_dotclock;
e29c22c0 4092 bool setup_ok, needs_recompute = false;
877d48d5 4093
e29c22c0 4094retry:
877d48d5
DV		 4095 /* FDI is a binary signal running at ~2.7GHz, encoding
4096 * each output octet as 10 bits. The actual frequency
4097 * is stored as a divider into a 100MHz clock, and the
4098 * mode pixel clock is stored in units of 1KHz.
4099 * Hence the bw of each lane in terms of the mode signal
4100 * is:
4101 */
4102 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
ff9a6750 4104 fdi_dotclock = adjusted_mode->clock;
877d48d5 4105
2bd89a07 4106 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4107 pipe_config->pipe_bpp);
4108
4109 pipe_config->fdi_lanes = lane;
4110
2bd89a07 4111 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4112 link_bw, &pipe_config->fdi_m_n);
1857e1da 4113
e29c22c0
DV		 4114 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115 intel_crtc->pipe, pipe_config);
4116 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117 pipe_config->pipe_bpp -= 2*3;
4118 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119 pipe_config->pipe_bpp);
4120 needs_recompute = true;
4121 pipe_config->bw_constrained = true;
4122
4123 goto retry;
4124 }
4125
4126 if (needs_recompute)
4127 return RETRY;
4128
4129 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4130}
4131
42db64ef
PZ		 4132static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133 struct intel_crtc_config *pipe_config)
4134{
3c4ca58c
PZ		 4135 pipe_config->ips_enabled = i915_enable_ips &&
4136 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4137 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4138}
4139
a43f6e0f 4140static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4141 struct intel_crtc_config *pipe_config)
79e53945 4142{
a43f6e0f 4143 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4144 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4145
8693a824
DL		 4146 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4147 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4148 */
4149 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4150 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4151 return -EINVAL;
44f46b42 4152
bd080ee5 4153 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4154 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4155 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4156 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4157 * for lvds. */
4158 pipe_config->pipe_bpp = 8*3;
4159 }
4160
f5adf94e 4161 if (HAS_IPS(dev))
a43f6e0f
DV		 4162 hsw_compute_ips_config(crtc, pipe_config);
4163
4164 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4165 * clock survives for now. */
4166 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4167 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4168
877d48d5 4169 if (pipe_config->has_pch_encoder)
a43f6e0f 4170 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4171
e29c22c0 4172 return 0;
79e53945
JB		 4173}
4174
25eb05fc
JB		 4175static int valleyview_get_display_clock_speed(struct drm_device *dev)
4176{
4177 return 400000; /* FIXME */
4178}
4179
e70236a8
JB		 4180static int i945_get_display_clock_speed(struct drm_device *dev)
4181{
4182 return 400000;
4183}
79e53945 4184
e70236a8 4185static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4186{
e70236a8
JB		 4187 return 333000;
4188}
79e53945 4189
e70236a8
JB		 4190static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4191{
4192 return 200000;
4193}
79e53945 4194
257a7ffc
DV		 4195static int pnv_get_display_clock_speed(struct drm_device *dev)
4196{
4197 u16 gcfgc = 0;
4198
4199 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4200
4201 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4202 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4203 return 267000;
4204 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4205 return 333000;
4206 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4207 return 444000;
4208 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4209 return 200000;
4210 default:
4211 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4212 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4213 return 133000;
4214 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4215 return 167000;
4216 }
4217}
4218
e70236a8
JB		 4219static int i915gm_get_display_clock_speed(struct drm_device *dev)
4220{
4221 u16 gcfgc = 0;
79e53945 4222
e70236a8
JB		 4223 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4224
4225 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4226 return 133000;
4227 else {
4228 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4229 case GC_DISPLAY_CLOCK_333_MHZ:
4230 return 333000;
4231 default:
4232 case GC_DISPLAY_CLOCK_190_200_MHZ:
4233 return 190000;
79e53945 4234 }
e70236a8
JB		 4235 }
4236}
4237
4238static int i865_get_display_clock_speed(struct drm_device *dev)
4239{
4240 return 266000;
4241}
4242
4243static int i855_get_display_clock_speed(struct drm_device *dev)
4244{
4245 u16 hpllcc = 0;
4246 /* Assume that the hardware is in the high speed state. This
4247 * should be the default.
4248 */
4249 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4250 case GC_CLOCK_133_200:
4251 case GC_CLOCK_100_200:
4252 return 200000;
4253 case GC_CLOCK_166_250:
4254 return 250000;
4255 case GC_CLOCK_100_133:
79e53945 4256 return 133000;
e70236a8 4257 }
79e53945 4258
e70236a8
JB		 4259 /* Shouldn't happen */
4260 return 0;
4261}
79e53945 4262
e70236a8
JB		 4263static int i830_get_display_clock_speed(struct drm_device *dev)
4264{
4265 return 133000;
79e53945
JB		 4266}
4267
2c07245f 4268static void
a65851af 4269intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4270{
a65851af
VS		 4271 while (*num > DATA_LINK_M_N_MASK ||
4272 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4273 *num >>= 1;
4274 *den >>= 1;
4275 }
4276}
4277
a65851af
VS		 4278static void compute_m_n(unsigned int m, unsigned int n,
4279 uint32_t *ret_m, uint32_t *ret_n)
4280{
4281 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4282 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4283 intel_reduce_m_n_ratio(ret_m, ret_n);
4284}
4285
e69d0bc1
DV		 4286void
4287intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4288 int pixel_clock, int link_clock,
4289 struct intel_link_m_n *m_n)
2c07245f 4290{
e69d0bc1 4291 m_n->tu = 64;
a65851af
VS		 4292
4293 compute_m_n(bits_per_pixel * pixel_clock,
4294 link_clock * nlanes * 8,
4295 &m_n->gmch_m, &m_n->gmch_n);
4296
4297 compute_m_n(pixel_clock, link_clock,
4298 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4299}
4300
a7615030
CW		 4301static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4302{
72bbe58c
KP		 4303 if (i915_panel_use_ssc >= 0)
4304 return i915_panel_use_ssc != 0;
41aa3448 4305 return dev_priv->vbt.lvds_use_ssc
435793df 4306 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4307}
4308
a0c4da24
JB		 4309static int vlv_get_refclk(struct drm_crtc *crtc)
4310{
4311 struct drm_device *dev = crtc->dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int refclk = 27000; /* for DP & HDMI */
4314
4315 return 100000; /* only one validated so far */
4316
4317 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4318 refclk = 96000;
4319 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4320 if (intel_panel_use_ssc(dev_priv))
4321 refclk = 100000;
4322 else
4323 refclk = 96000;
4324 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4325 refclk = 100000;
4326 }
4327
4328 return refclk;
4329}
4330
c65d77d8
JB		 4331static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4332{
4333 struct drm_device *dev = crtc->dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 int refclk;
4336
a0c4da24
JB		 4337 if (IS_VALLEYVIEW(dev)) {
4338 refclk = vlv_get_refclk(crtc);
4339 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4340 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4341 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4342 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4343 refclk / 1000);
4344 } else if (!IS_GEN2(dev)) {
4345 refclk = 96000;
4346 } else {
4347 refclk = 48000;
4348 }
4349
4350 return refclk;
4351}
4352
7429e9d4 4353static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4354{
7df00d7a 4355 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4356}
f47709a9 4357
7429e9d4
DV		 4358static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4359{
4360 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4361}
4362
f47709a9 4363static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4364 intel_clock_t *reduced_clock)
4365{
f47709a9 4366 struct drm_device *dev = crtc->base.dev;
a7516a05 4367 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4368 int pipe = crtc->pipe;
a7516a05
JB		 4369 u32 fp, fp2 = 0;
4370
4371 if (IS_PINEVIEW(dev)) {
7429e9d4 4372 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4373 if (reduced_clock)
7429e9d4 4374 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4375 } else {
7429e9d4 4376 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4377 if (reduced_clock)
7429e9d4 4378 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4379 }
4380
4381 I915_WRITE(FP0(pipe), fp);
8bcc2795 4382 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4383
f47709a9
DV		 4384 crtc->lowfreq_avail = false;
4385 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4386 reduced_clock && i915_powersave) {
4387 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4388 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4389 crtc->lowfreq_avail = true;
a7516a05
JB		 4390 } else {
4391 I915_WRITE(FP1(pipe), fp);
8bcc2795 4392 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4393 }
4394}
4395
5e69f97f
CML		 4396static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4397 pipe)
89b667f8
JB		 4398{
4399 u32 reg_val;
4400
4401 /*
4402 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4403 * and set it to a reasonable value instead.
4404 */
5e69f97f 4405 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4406 reg_val &= 0xffffff00;
4407 reg_val |= 0x00000030;
5e69f97f 4408 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4409
5e69f97f 4410 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4411 reg_val &= 0x8cffffff;
4412 reg_val = 0x8c000000;
5e69f97f 4413 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4414
5e69f97f 4415 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4416 reg_val &= 0xffffff00;
5e69f97f 4417 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4418
5e69f97f 4419 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4420 reg_val &= 0x00ffffff;
4421 reg_val |= 0xb0000000;
5e69f97f 4422 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4423}
4424
b551842d
DV		 4425static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4426 struct intel_link_m_n *m_n)
4427{
4428 struct drm_device *dev = crtc->base.dev;
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430 int pipe = crtc->pipe;
4431
e3b95f1e
DV		 4432 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4433 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4434 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4435 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4436}
4437
4438static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4439 struct intel_link_m_n *m_n)
4440{
4441 struct drm_device *dev = crtc->base.dev;
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 int pipe = crtc->pipe;
4444 enum transcoder transcoder = crtc->config.cpu_transcoder;
4445
4446 if (INTEL_INFO(dev)->gen >= 5) {
4447 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4448 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4449 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4450 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4451 } else {
e3b95f1e
DV		 4452 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4453 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4454 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4455 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4456 }
4457}
4458
03afc4a2
DV		 4459static void intel_dp_set_m_n(struct intel_crtc *crtc)
4460{
4461 if (crtc->config.has_pch_encoder)
4462 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4463 else
4464 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4465}
4466
f47709a9 4467static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4468{
f47709a9 4469 struct drm_device *dev = crtc->base.dev;
a0c4da24 4470 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4471 int pipe = crtc->pipe;
89b667f8 4472 u32 dpll, mdiv;
a0c4da24 4473 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4474 u32 coreclk, reg_val, dpll_md;
a0c4da24 4475
09153000
DV		 4476 mutex_lock(&dev_priv->dpio_lock);
4477
f47709a9
DV		 4478 bestn = crtc->config.dpll.n;
4479 bestm1 = crtc->config.dpll.m1;
4480 bestm2 = crtc->config.dpll.m2;
4481 bestp1 = crtc->config.dpll.p1;
4482 bestp2 = crtc->config.dpll.p2;
a0c4da24 4483
89b667f8
JB		 4484 /* See eDP HDMI DPIO driver vbios notes doc */
4485
4486 /* PLL B needs special handling */
4487 if (pipe)
5e69f97f 4488 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4489
4490 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4491 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4492
4493 /* Disable target IRef on PLL */
5e69f97f 4494 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4495 reg_val &= 0x00ffffff;
5e69f97f 4496 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4497
4498 /* Disable fast lock */
5e69f97f 4499 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4500
4501 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4502 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4503 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4504 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4505 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4506
4507 /*
4508 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4509 * but we don't support that).
4510 * Note: don't use the DAC post divider as it seems unstable.
4511 */
4512 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4513 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4514
a0c4da24 4515 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4516 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4517
89b667f8 4518 /* Set HBR and RBR LPF coefficients */
ff9a6750 4519 if (crtc->config.port_clock == 162000 ||
99750bd4 4520 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4521 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4522 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4523 0x009f0003);
89b667f8 4524 else
5e69f97f 4525 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4526 0x00d0000f);
4527
4528 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4529 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4530 /* Use SSC source */
4531 if (!pipe)
5e69f97f 4532 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4533 0x0df40000);
4534 else
5e69f97f 4535 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4536 0x0df70000);
4537 } else { /* HDMI or VGA */
4538 /* Use bend source */
4539 if (!pipe)
5e69f97f 4540 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4541 0x0df70000);
4542 else
5e69f97f 4543 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4544 0x0df40000);
4545 }
a0c4da24 4546
5e69f97f 4547 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4548 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4550 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4551 coreclk |= 0x01000000;
5e69f97f 4552 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4553
5e69f97f 4554 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4555
89b667f8
JB		 4556 /* Enable DPIO clock input */
4557 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4558 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4559 if (pipe)
4560 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4561
4562 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4563 crtc->config.dpll_hw_state.dpll = dpll;
4564
ef1b460d
DV		 4565 dpll_md = (crtc->config.pixel_multiplier - 1)
4566 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4567 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4568
89b667f8
JB		 4569 if (crtc->config.has_dp_encoder)
4570 intel_dp_set_m_n(crtc);
09153000
DV		 4571
4572 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4573}
4574
f47709a9
DV		 4575static void i9xx_update_pll(struct intel_crtc *crtc,
4576 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4577 int num_connectors)
4578{
f47709a9 4579 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4580 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4581 u32 dpll;
4582 bool is_sdvo;
f47709a9 4583 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4584
f47709a9 4585 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4586
f47709a9
DV		 4587 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4588 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4589
4590 dpll = DPLL_VGA_MODE_DIS;
4591
f47709a9 4592 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4593 dpll |= DPLLB_MODE_LVDS;
4594 else
4595 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4596
ef1b460d 4597 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4598 dpll |= (crtc->config.pixel_multiplier - 1)
4599 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4600 }
198a037f
DV		 4601
4602 if (is_sdvo)
4a33e48d 4603 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4604
f47709a9 4605 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4606 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4607
4608 /* compute bitmask from p1 value */
4609 if (IS_PINEVIEW(dev))
4610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4611 else {
4612 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4613 if (IS_G4X(dev) && reduced_clock)
4614 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4615 }
4616 switch (clock->p2) {
4617 case 5:
4618 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4619 break;
4620 case 7:
4621 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4622 break;
4623 case 10:
4624 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4625 break;
4626 case 14:
4627 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4628 break;
4629 }
4630 if (INTEL_INFO(dev)->gen >= 4)
4631 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4632
09ede541 4633 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4634 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4635 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4636 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4637 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4638 else
4639 dpll |= PLL_REF_INPUT_DREFCLK;
4640
4641 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4642 crtc->config.dpll_hw_state.dpll = dpll;
4643
eb1cbe48 4644 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4645 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4646 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4647 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4648 }
66e3d5c0
DV		 4649
4650 if (crtc->config.has_dp_encoder)
4651 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4652}
4653
f47709a9 4654static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4655 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4656 int num_connectors)
4657{
f47709a9 4658 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4659 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4660 u32 dpll;
f47709a9 4661 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4662
f47709a9 4663 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4664
eb1cbe48
DV		 4665 dpll = DPLL_VGA_MODE_DIS;
4666
f47709a9 4667 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4669 } else {
4670 if (clock->p1 == 2)
4671 dpll |= PLL_P1_DIVIDE_BY_TWO;
4672 else
4673 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4674 if (clock->p2 == 4)
4675 dpll |= PLL_P2_DIVIDE_BY_4;
4676 }
4677
4a33e48d
DV		 4678 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4679 dpll |= DPLL_DVO_2X_MODE;
4680
f47709a9 4681 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4682 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4684 else
4685 dpll |= PLL_REF_INPUT_DREFCLK;
4686
4687 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4688 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4689}
4690
8a654f3b 4691static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4692{
4693 struct drm_device *dev = intel_crtc->base.dev;
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4696 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4697 struct drm_display_mode *adjusted_mode =
4698 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4699 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4700
4701 /* We need to be careful not to changed the adjusted mode, for otherwise
4702 * the hw state checker will get angry at the mismatch. */
4703 crtc_vtotal = adjusted_mode->crtc_vtotal;
4704 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4705
4706 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4707 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4708 crtc_vtotal -= 1;
4709 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4710 vsyncshift = adjusted_mode->crtc_hsync_start
4711 - adjusted_mode->crtc_htotal / 2;
4712 } else {
4713 vsyncshift = 0;
4714 }
4715
4716 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4717 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4718
fe2b8f9d 4719 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4720 (adjusted_mode->crtc_hdisplay - 1) |
4721 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4722 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4723 (adjusted_mode->crtc_hblank_start - 1) |
4724 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4725 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4726 (adjusted_mode->crtc_hsync_start - 1) |
4727 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4728
fe2b8f9d 4729 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4730 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4731 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4732 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4733 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4734 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4735 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4736 (adjusted_mode->crtc_vsync_start - 1) |
4737 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4738
b5e508d4
PZ		 4739 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4740 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4741 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4742 * bits. */
4743 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4744 (pipe == PIPE_B || pipe == PIPE_C))
4745 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4746
b0e77b9c
PZ		 4747 /* pipesrc controls the size that is scaled from, which should
4748 * always be the user's requested size.
4749 */
4750 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4751 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4752 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4753}
4754
1bd1bd80
DV		 4755static void intel_get_pipe_timings(struct intel_crtc *crtc,
4756 struct intel_crtc_config *pipe_config)
4757{
4758 struct drm_device *dev = crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4761 uint32_t tmp;
4762
4763 tmp = I915_READ(HTOTAL(cpu_transcoder));
4764 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4765 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4766 tmp = I915_READ(HBLANK(cpu_transcoder));
4767 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4768 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4769 tmp = I915_READ(HSYNC(cpu_transcoder));
4770 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4771 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4772
4773 tmp = I915_READ(VTOTAL(cpu_transcoder));
4774 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4775 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4776 tmp = I915_READ(VBLANK(cpu_transcoder));
4777 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4778 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4779 tmp = I915_READ(VSYNC(cpu_transcoder));
4780 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4781 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4782
4783 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4784 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4785 pipe_config->adjusted_mode.crtc_vtotal += 1;
4786 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4787 }
4788
4789 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4790 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4791 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4792
4793 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4794 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4795}
4796
babea61d
JB		 4797static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4798 struct intel_crtc_config *pipe_config)
4799{
4800 struct drm_crtc *crtc = &intel_crtc->base;
4801
4802 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4803 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4804 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4805 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4806
4807 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4808 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4809 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4810 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4811
4812 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4813
4814 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4815 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4816}
4817
84b046f3
DV		 4818static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4819{
4820 struct drm_device *dev = intel_crtc->base.dev;
4821 struct drm_i915_private *dev_priv = dev->dev_private;
4822 uint32_t pipeconf;
4823
9f11a9e4 4824 pipeconf = 0;
84b046f3
DV		 4825
4826 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4827 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4828 * core speed.
4829 *
4830 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4831 * pipe == 0 check?
4832 */
a2b076b6 4833 if (intel_crtc->config.adjusted_mode.clock >
84b046f3
DV		 4834 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4835 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4836 }
4837
ff9ce46e
DV		 4838 /* only g4x and later have fancy bpc/dither controls */
4839 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4840 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4841 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4842 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4843 PIPECONF_DITHER_TYPE_SP;
84b046f3 4844
ff9ce46e
DV		 4845 switch (intel_crtc->config.pipe_bpp) {
4846 case 18:
4847 pipeconf |= PIPECONF_6BPC;
4848 break;
4849 case 24:
4850 pipeconf |= PIPECONF_8BPC;
4851 break;
4852 case 30:
4853 pipeconf |= PIPECONF_10BPC;
4854 break;
4855 default:
4856 /* Case prevented by intel_choose_pipe_bpp_dither. */
4857 BUG();
84b046f3
DV		 4858 }
4859 }
4860
4861 if (HAS_PIPE_CXSR(dev)) {
4862 if (intel_crtc->lowfreq_avail) {
4863 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4864 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4865 } else {
4866 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4867 }
4868 }
4869
84b046f3
DV		 4870 if (!IS_GEN2(dev) &&
4871 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4872 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4873 else
4874 pipeconf |= PIPECONF_PROGRESSIVE;
4875
9f11a9e4
DV		 4876 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4877 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4878
84b046f3
DV		 4879 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4880 POSTING_READ(PIPECONF(intel_crtc->pipe));
4881}
4882
f564048e 4883static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4884 int x, int y,
94352cf9 4885 struct drm_framebuffer *fb)
79e53945
JB		 4886{
4887 struct drm_device *dev = crtc->dev;
4888 struct drm_i915_private *dev_priv = dev->dev_private;
4889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4890 int pipe = intel_crtc->pipe;
80824003 4891 int plane = intel_crtc->plane;
c751ce4f 4892 int refclk, num_connectors = 0;
652c393a 4893 intel_clock_t clock, reduced_clock;
84b046f3 4894 u32 dspcntr;
a16af721 4895 bool ok, has_reduced_clock = false;
e9fd1c02 4896 bool is_lvds = false, is_dsi = false;
5eddb70b 4897 struct intel_encoder *encoder;
d4906093 4898 const intel_limit_t *limit;
5c3b82e2 4899 int ret;
79e53945 4900
6c2b7c12 4901 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4902 switch (encoder->type) {
79e53945
JB		 4903 case INTEL_OUTPUT_LVDS:
4904 is_lvds = true;
4905 break;
e9fd1c02
JN		 4906 case INTEL_OUTPUT_DSI:
4907 is_dsi = true;
4908 break;
79e53945 4909 }
43565a06 4910
c751ce4f 4911 num_connectors++;
79e53945
JB		 4912 }
4913
c65d77d8 4914 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4915
65ce4bf5 4916 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4917 /*
4918 * Returns a set of divisors for the desired target clock with
4919 * the given refclk, or FALSE. The returned values represent
4920 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4921 * 2) / p1 / p2.
4922 */
4923 limit = intel_limit(crtc, refclk);
4924 ok = dev_priv->display.find_dpll(limit, crtc,
4925 intel_crtc->config.port_clock,
4926 refclk, NULL, &clock);
4927 if (!ok && !intel_crtc->config.clock_set) {
4928 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4929 return -EINVAL;
4930 }
79e53945
JB		 4931 }
4932
cda4b7d3 4933 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4934 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4935
e9fd1c02 4936 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4937 /*
4938 * Ensure we match the reduced clock's P to the target clock.
4939 * If the clocks don't match, we can't switch the display clock
4940 * by using the FP0/FP1. In such case we will disable the LVDS
4941 * downclock feature.
4942 */
65ce4bf5 4943 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4944 has_reduced_clock =
4945 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4946 dev_priv->lvds_downclock,
ee9300bb 4947 refclk, &clock,
5eddb70b 4948 &reduced_clock);
7026d4ac 4949 }
f47709a9
DV		 4950 /* Compat-code for transition, will disappear. */
4951 if (!intel_crtc->config.clock_set) {
4952 intel_crtc->config.dpll.n = clock.n;
4953 intel_crtc->config.dpll.m1 = clock.m1;
4954 intel_crtc->config.dpll.m2 = clock.m2;
4955 intel_crtc->config.dpll.p1 = clock.p1;
4956 intel_crtc->config.dpll.p2 = clock.p2;
4957 }
7026d4ac 4958
e9fd1c02 4959 if (IS_GEN2(dev)) {
8a654f3b 4960 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4961 has_reduced_clock ? &reduced_clock : NULL,
4962 num_connectors);
e9fd1c02
JN		 4963 } else if (IS_VALLEYVIEW(dev)) {
4964 if (!is_dsi)
4965 vlv_update_pll(intel_crtc);
4966 } else {
f47709a9 4967 i9xx_update_pll(intel_crtc,
eb1cbe48 4968 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4969 num_connectors);
e9fd1c02 4970 }
79e53945 4971
79e53945
JB		 4972 /* Set up the display plane register */
4973 dspcntr = DISPPLANE_GAMMA_ENABLE;
4974
da6ecc5d
JB		 4975 if (!IS_VALLEYVIEW(dev)) {
4976 if (pipe == 0)
4977 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4978 else
4979 dspcntr |= DISPPLANE_SEL_PIPE_B;
4980 }
79e53945 4981
8a654f3b 4982 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4983
4984 /* pipesrc and dspsize control the size that is scaled from,
4985 * which should always be the user's requested size.
79e53945 4986 */
929c77fb 4987 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 4988 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4989 (intel_crtc->config.pipe_src_w - 1));
929c77fb 4990 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4991
84b046f3
DV		 4992 i9xx_set_pipeconf(intel_crtc);
4993
f564048e
EA		 4994 I915_WRITE(DSPCNTR(plane), dspcntr);
4995 POSTING_READ(DSPCNTR(plane));
4996
94352cf9 4997 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4998
f564048e
EA		 4999 return ret;
5000}
5001
2fa2fe9a
DV		 5002static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5003 struct intel_crtc_config *pipe_config)
5004{
5005 struct drm_device *dev = crtc->base.dev;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 uint32_t tmp;
5008
5009 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5010 if (!(tmp & PFIT_ENABLE))
5011 return;
2fa2fe9a 5012
06922821 5013 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5014 if (INTEL_INFO(dev)->gen < 4) {
5015 if (crtc->pipe != PIPE_B)
5016 return;
2fa2fe9a
DV		 5017 } else {
5018 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5019 return;
5020 }
5021
06922821 5022 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5023 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5024 if (INTEL_INFO(dev)->gen < 5)
5025 pipe_config->gmch_pfit.lvds_border_bits =
5026 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5027}
5028
0e8ffe1b
DV		 5029static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5030 struct intel_crtc_config *pipe_config)
5031{
5032 struct drm_device *dev = crtc->base.dev;
5033 struct drm_i915_private *dev_priv = dev->dev_private;
5034 uint32_t tmp;
5035
e143a21c 5036 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5037 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5038
0e8ffe1b
DV		 5039 tmp = I915_READ(PIPECONF(crtc->pipe));
5040 if (!(tmp & PIPECONF_ENABLE))
5041 return false;
5042
42571aef
VS		 5043 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5044 switch (tmp & PIPECONF_BPC_MASK) {
5045 case PIPECONF_6BPC:
5046 pipe_config->pipe_bpp = 18;
5047 break;
5048 case PIPECONF_8BPC:
5049 pipe_config->pipe_bpp = 24;
5050 break;
5051 case PIPECONF_10BPC:
5052 pipe_config->pipe_bpp = 30;
5053 break;
5054 default:
5055 break;
5056 }
5057 }
5058
1bd1bd80
DV		 5059 intel_get_pipe_timings(crtc, pipe_config);
5060
2fa2fe9a
DV		 5061 i9xx_get_pfit_config(crtc, pipe_config);
5062
6c49f241
DV		 5063 if (INTEL_INFO(dev)->gen >= 4) {
5064 tmp = I915_READ(DPLL_MD(crtc->pipe));
5065 pipe_config->pixel_multiplier =
5066 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5067 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5068 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5069 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5070 tmp = I915_READ(DPLL(crtc->pipe));
5071 pipe_config->pixel_multiplier =
5072 ((tmp & SDVO_MULTIPLIER_MASK)
5073 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5074 } else {
5075 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5076 * port and will be fixed up in the encoder->get_config
5077 * function. */
5078 pipe_config->pixel_multiplier = 1;
5079 }
8bcc2795
DV		 5080 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5081 if (!IS_VALLEYVIEW(dev)) {
5082 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5083 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5084 } else {
5085 /* Mask out read-only status bits. */
5086 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5087 DPLL_PORTC_READY_MASK |
5088 DPLL_PORTB_READY_MASK);
8bcc2795 5089 }
6c49f241 5090
18442d08
VS		 5091 i9xx_crtc_clock_get(crtc, pipe_config);
5092
0e8ffe1b
DV		 5093 return true;
5094}
5095
dde86e2d 5096static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5097{
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5100 struct intel_encoder *encoder;
74cfd7ac 5101 u32 val, final;
13d83a67 5102 bool has_lvds = false;
199e5d79 5103 bool has_cpu_edp = false;
199e5d79 5104 bool has_panel = false;
99eb6a01
KP		 5105 bool has_ck505 = false;
5106 bool can_ssc = false;
13d83a67
JB		 5107
5108 /* We need to take the global config into account */
199e5d79
KP		 5109 list_for_each_entry(encoder, &mode_config->encoder_list,
5110 base.head) {
5111 switch (encoder->type) {
5112 case INTEL_OUTPUT_LVDS:
5113 has_panel = true;
5114 has_lvds = true;
5115 break;
5116 case INTEL_OUTPUT_EDP:
5117 has_panel = true;
2de6905f 5118 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5119 has_cpu_edp = true;
5120 break;
13d83a67
JB		 5121 }
5122 }
5123
99eb6a01 5124 if (HAS_PCH_IBX(dev)) {
41aa3448 5125 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5126 can_ssc = has_ck505;
5127 } else {
5128 has_ck505 = false;
5129 can_ssc = true;
5130 }
5131
2de6905f
ID		 5132 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5133 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5134
5135 /* Ironlake: try to setup display ref clock before DPLL
5136 * enabling. This is only under driver's control after
5137 * PCH B stepping, previous chipset stepping should be
5138 * ignoring this setting.
5139 */
74cfd7ac
CW		 5140 val = I915_READ(PCH_DREF_CONTROL);
5141
5142 /* As we must carefully and slowly disable/enable each source in turn,
5143 * compute the final state we want first and check if we need to
5144 * make any changes at all.
5145 */
5146 final = val;
5147 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5148 if (has_ck505)
5149 final |= DREF_NONSPREAD_CK505_ENABLE;
5150 else
5151 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5152
5153 final &= ~DREF_SSC_SOURCE_MASK;
5154 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5155 final &= ~DREF_SSC1_ENABLE;
5156
5157 if (has_panel) {
5158 final |= DREF_SSC_SOURCE_ENABLE;
5159
5160 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5161 final |= DREF_SSC1_ENABLE;
5162
5163 if (has_cpu_edp) {
5164 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5165 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5166 else
5167 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5168 } else
5169 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5170 } else {
5171 final |= DREF_SSC_SOURCE_DISABLE;
5172 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5173 }
5174
5175 if (final == val)
5176 return;
5177
13d83a67 5178 /* Always enable nonspread source */
74cfd7ac 5179 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5180
99eb6a01 5181 if (has_ck505)
74cfd7ac 5182 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5183 else
74cfd7ac 5184 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5185
199e5d79 5186 if (has_panel) {
74cfd7ac
CW		 5187 val &= ~DREF_SSC_SOURCE_MASK;
5188 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5189
199e5d79 5190 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5191 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5192 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5193 val |= DREF_SSC1_ENABLE;
e77166b5 5194 } else
74cfd7ac 5195 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5196
5197 /* Get SSC going before enabling the outputs */
74cfd7ac 5198 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5199 POSTING_READ(PCH_DREF_CONTROL);
5200 udelay(200);
5201
74cfd7ac 5202 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5203
5204 /* Enable CPU source on CPU attached eDP */
199e5d79 5205 if (has_cpu_edp) {
99eb6a01 5206 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5207 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5208 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5209 }
13d83a67 5210 else
74cfd7ac 5211 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5212 } else
74cfd7ac 5213 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5214
74cfd7ac 5215 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5216 POSTING_READ(PCH_DREF_CONTROL);
5217 udelay(200);
5218 } else {
5219 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5220
74cfd7ac 5221 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5222
5223 /* Turn off CPU output */
74cfd7ac 5224 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5225
74cfd7ac 5226 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5227 POSTING_READ(PCH_DREF_CONTROL);
5228 udelay(200);
5229
5230 /* Turn off the SSC source */
74cfd7ac
CW		 5231 val &= ~DREF_SSC_SOURCE_MASK;
5232 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5233
5234 /* Turn off SSC1 */
74cfd7ac 5235 val &= ~DREF_SSC1_ENABLE;
199e5d79 5236
74cfd7ac 5237 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5238 POSTING_READ(PCH_DREF_CONTROL);
5239 udelay(200);
5240 }
74cfd7ac
CW		 5241
5242 BUG_ON(val != final);
13d83a67
JB		 5243}
5244
f31f2d55 5245static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5246{
f31f2d55 5247 uint32_t tmp;
dde86e2d 5248
0ff066a9
PZ		 5249 tmp = I915_READ(SOUTH_CHICKEN2);
5250 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5251 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5252
0ff066a9
PZ		 5253 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5254 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5255 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5256
0ff066a9
PZ		 5257 tmp = I915_READ(SOUTH_CHICKEN2);
5258 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5259 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5260
0ff066a9
PZ		 5261 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5262 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5263 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5264}
5265
5266/* WaMPhyProgramming:hsw */
5267static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5268{
5269 uint32_t tmp;
dde86e2d
PZ		 5270
5271 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5272 tmp &= ~(0xFF << 24);
5273 tmp |= (0x12 << 24);
5274 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5275
dde86e2d
PZ		 5276 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5277 tmp |= (1 << 11);
5278 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5279
5280 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5281 tmp |= (1 << 11);
5282 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5283
dde86e2d
PZ		 5284 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5285 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5286 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5287
5288 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5289 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5290 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5291
0ff066a9
PZ		 5292 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5293 tmp &= ~(7 << 13);
5294 tmp |= (5 << 13);
5295 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5296
0ff066a9
PZ		 5297 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5298 tmp &= ~(7 << 13);
5299 tmp |= (5 << 13);
5300 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5301
5302 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5303 tmp &= ~0xFF;
5304 tmp |= 0x1C;
5305 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5306
5307 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5308 tmp &= ~0xFF;
5309 tmp |= 0x1C;
5310 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5311
5312 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5313 tmp &= ~(0xFF << 16);
5314 tmp |= (0x1C << 16);
5315 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5316
5317 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5318 tmp &= ~(0xFF << 16);
5319 tmp |= (0x1C << 16);
5320 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5321
0ff066a9
PZ		 5322 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5323 tmp |= (1 << 27);
5324 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5325
0ff066a9
PZ		 5326 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5327 tmp |= (1 << 27);
5328 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5329
0ff066a9
PZ		 5330 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5331 tmp &= ~(0xF << 28);
5332 tmp |= (4 << 28);
5333 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5334
0ff066a9
PZ		 5335 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5336 tmp &= ~(0xF << 28);
5337 tmp |= (4 << 28);
5338 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5339}
5340
2fa86a1f
PZ		 5341/* Implements 3 different sequences from BSpec chapter "Display iCLK
5342 * Programming" based on the parameters passed:
5343 * - Sequence to enable CLKOUT_DP
5344 * - Sequence to enable CLKOUT_DP without spread
5345 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5346 */
5347static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5348 bool with_fdi)
f31f2d55
PZ		 5349{
5350 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5351 uint32_t reg, tmp;
5352
5353 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5354 with_spread = true;
5355 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5356 with_fdi, "LP PCH doesn't have FDI\n"))
5357 with_fdi = false;
f31f2d55
PZ		 5358
5359 mutex_lock(&dev_priv->dpio_lock);
5360
5361 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5362 tmp &= ~SBI_SSCCTL_DISABLE;
5363 tmp |= SBI_SSCCTL_PATHALT;
5364 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5365
5366 udelay(24);
5367
2fa86a1f
PZ		 5368 if (with_spread) {
5369 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5370 tmp &= ~SBI_SSCCTL_PATHALT;
5371 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5372
2fa86a1f
PZ		 5373 if (with_fdi) {
5374 lpt_reset_fdi_mphy(dev_priv);
5375 lpt_program_fdi_mphy(dev_priv);
5376 }
5377 }
dde86e2d 5378
2fa86a1f
PZ		 5379 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5380 SBI_GEN0 : SBI_DBUFF0;
5381 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5382 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5383 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5384
5385 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5386}
5387
47701c3b
PZ		 5388/* Sequence to disable CLKOUT_DP */
5389static void lpt_disable_clkout_dp(struct drm_device *dev)
5390{
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5392 uint32_t reg, tmp;
5393
5394 mutex_lock(&dev_priv->dpio_lock);
5395
5396 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5397 SBI_GEN0 : SBI_DBUFF0;
5398 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5399 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5400 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5401
5402 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5403 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5404 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5405 tmp |= SBI_SSCCTL_PATHALT;
5406 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5407 udelay(32);
5408 }
5409 tmp |= SBI_SSCCTL_DISABLE;
5410 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5411 }
5412
5413 mutex_unlock(&dev_priv->dpio_lock);
5414}
5415
bf8fa3d3
PZ		 5416static void lpt_init_pch_refclk(struct drm_device *dev)
5417{
5418 struct drm_mode_config *mode_config = &dev->mode_config;
5419 struct intel_encoder *encoder;
5420 bool has_vga = false;
5421
5422 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5423 switch (encoder->type) {
5424 case INTEL_OUTPUT_ANALOG:
5425 has_vga = true;
5426 break;
5427 }
5428 }
5429
47701c3b
PZ		 5430 if (has_vga)
5431 lpt_enable_clkout_dp(dev, true, true);
5432 else
5433 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5434}
5435
dde86e2d
PZ		 5436/*
5437 * Initialize reference clocks when the driver loads
5438 */
5439void intel_init_pch_refclk(struct drm_device *dev)
5440{
5441 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5442 ironlake_init_pch_refclk(dev);
5443 else if (HAS_PCH_LPT(dev))
5444 lpt_init_pch_refclk(dev);
5445}
5446
d9d444cb
JB		 5447static int ironlake_get_refclk(struct drm_crtc *crtc)
5448{
5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 struct intel_encoder *encoder;
d9d444cb
JB		 5452 int num_connectors = 0;
5453 bool is_lvds = false;
5454
6c2b7c12 5455 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5456 switch (encoder->type) {
5457 case INTEL_OUTPUT_LVDS:
5458 is_lvds = true;
5459 break;
d9d444cb
JB		 5460 }
5461 num_connectors++;
5462 }
5463
5464 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5465 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5466 dev_priv->vbt.lvds_ssc_freq);
5467 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5468 }
5469
5470 return 120000;
5471}
5472
6ff93609 5473static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5474{
c8203565 5475 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5477 int pipe = intel_crtc->pipe;
c8203565
PZ		 5478 uint32_t val;
5479
78114071 5480 val = 0;
c8203565 5481
965e0c48 5482 switch (intel_crtc->config.pipe_bpp) {
c8203565 5483 case 18:
dfd07d72 5484 val |= PIPECONF_6BPC;
c8203565
PZ		 5485 break;
5486 case 24:
dfd07d72 5487 val |= PIPECONF_8BPC;
c8203565
PZ		 5488 break;
5489 case 30:
dfd07d72 5490 val |= PIPECONF_10BPC;
c8203565
PZ		 5491 break;
5492 case 36:
dfd07d72 5493 val |= PIPECONF_12BPC;
c8203565
PZ		 5494 break;
5495 default:
cc769b62
PZ		 5496 /* Case prevented by intel_choose_pipe_bpp_dither. */
5497 BUG();
c8203565
PZ		 5498 }
5499
d8b32247 5500 if (intel_crtc->config.dither)
c8203565
PZ		 5501 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5502
6ff93609 5503 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5504 val |= PIPECONF_INTERLACED_ILK;
5505 else
5506 val |= PIPECONF_PROGRESSIVE;
5507
50f3b016 5508 if (intel_crtc->config.limited_color_range)
3685a8f3 5509 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5510
c8203565
PZ		 5511 I915_WRITE(PIPECONF(pipe), val);
5512 POSTING_READ(PIPECONF(pipe));
5513}
5514
86d3efce
VS		 5515/*
5516 * Set up the pipe CSC unit.
5517 *
5518 * Currently only full range RGB to limited range RGB conversion
5519 * is supported, but eventually this should handle various
5520 * RGB<->YCbCr scenarios as well.
5521 */
50f3b016 5522static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5523{
5524 struct drm_device *dev = crtc->dev;
5525 struct drm_i915_private *dev_priv = dev->dev_private;
5526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5527 int pipe = intel_crtc->pipe;
5528 uint16_t coeff = 0x7800; /* 1.0 */
5529
5530 /*
5531 * TODO: Check what kind of values actually come out of the pipe
5532 * with these coeff/postoff values and adjust to get the best
5533 * accuracy. Perhaps we even need to take the bpc value into
5534 * consideration.
5535 */
5536
50f3b016 5537 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5538 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5539
5540 /*
5541 * GY/GU and RY/RU should be the other way around according
5542 * to BSpec, but reality doesn't agree. Just set them up in
5543 * a way that results in the correct picture.
5544 */
5545 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5546 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5547
5548 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5549 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5550
5551 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5552 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5553
5554 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5555 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5556 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5557
5558 if (INTEL_INFO(dev)->gen > 6) {
5559 uint16_t postoff = 0;
5560
50f3b016 5561 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5562 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5563
5564 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5565 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5566 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5567
5568 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5569 } else {
5570 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5571
50f3b016 5572 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5573 mode |= CSC_BLACK_SCREEN_OFFSET;
5574
5575 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5576 }
5577}
5578
6ff93609 5579static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5580{
5581 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5583 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5584 uint32_t val;
5585
3eff4faa 5586 val = 0;
ee2b0b38 5587
d8b32247 5588 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5589 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5590
6ff93609 5591 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5592 val |= PIPECONF_INTERLACED_ILK;
5593 else
5594 val |= PIPECONF_PROGRESSIVE;
5595
702e7a56
PZ		 5596 I915_WRITE(PIPECONF(cpu_transcoder), val);
5597 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5598
5599 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5600 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5601}
5602
6591c6e4 5603static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5604 intel_clock_t *clock,
5605 bool *has_reduced_clock,
5606 intel_clock_t *reduced_clock)
5607{
5608 struct drm_device *dev = crtc->dev;
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 struct intel_encoder *intel_encoder;
5611 int refclk;
d4906093 5612 const intel_limit_t *limit;
a16af721 5613 bool ret, is_lvds = false;
79e53945 5614
6591c6e4
PZ		 5615 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5616 switch (intel_encoder->type) {
79e53945
JB		 5617 case INTEL_OUTPUT_LVDS:
5618 is_lvds = true;
5619 break;
79e53945
JB		 5620 }
5621 }
5622
d9d444cb 5623 refclk = ironlake_get_refclk(crtc);
79e53945 5624
d4906093
ML		 5625 /*
5626 * Returns a set of divisors for the desired target clock with the given
5627 * refclk, or FALSE. The returned values represent the clock equation:
5628 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5629 */
1b894b59 5630 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5631 ret = dev_priv->display.find_dpll(limit, crtc,
5632 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5633 refclk, NULL, clock);
6591c6e4
PZ		 5634 if (!ret)
5635 return false;
cda4b7d3 5636
ddc9003c 5637 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5638 /*
5639 * Ensure we match the reduced clock's P to the target clock.
5640 * If the clocks don't match, we can't switch the display clock
5641 * by using the FP0/FP1. In such case we will disable the LVDS
5642 * downclock feature.
5643 */
ee9300bb
DV		 5644 *has_reduced_clock =
5645 dev_priv->display.find_dpll(limit, crtc,
5646 dev_priv->lvds_downclock,
5647 refclk, clock,
5648 reduced_clock);
652c393a 5649 }
61e9653f 5650
6591c6e4
PZ		 5651 return true;
5652}
5653
01a415fd
DV		 5654static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5655{
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 uint32_t temp;
5658
5659 temp = I915_READ(SOUTH_CHICKEN1);
5660 if (temp & FDI_BC_BIFURCATION_SELECT)
5661 return;
5662
5663 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5664 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5665
5666 temp |= FDI_BC_BIFURCATION_SELECT;
5667 DRM_DEBUG_KMS("enabling fdi C rx\n");
5668 I915_WRITE(SOUTH_CHICKEN1, temp);
5669 POSTING_READ(SOUTH_CHICKEN1);
5670}
5671
ebfd86fd 5672static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5673{
5674 struct drm_device *dev = intel_crtc->base.dev;
5675 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5676
5677 switch (intel_crtc->pipe) {
5678 case PIPE_A:
ebfd86fd 5679 break;
01a415fd 5680 case PIPE_B:
ebfd86fd 5681 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5682 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5683 else
5684 cpt_enable_fdi_bc_bifurcation(dev);
5685
ebfd86fd 5686 break;
01a415fd 5687 case PIPE_C:
01a415fd
DV		 5688 cpt_enable_fdi_bc_bifurcation(dev);
5689
ebfd86fd 5690 break;
01a415fd
DV		 5691 default:
5692 BUG();
5693 }
5694}
5695
d4b1931c
PZ		 5696int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5697{
5698 /*
5699 * Account for spread spectrum to avoid
5700 * oversubscribing the link. Max center spread
5701 * is 2.5%; use 5% for safety's sake.
5702 */
5703 u32 bps = target_clock * bpp * 21 / 20;
5704 return bps / (link_bw * 8) + 1;
5705}
5706
7429e9d4 5707static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5708{
7429e9d4 5709 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5710}
5711
de13a2e3 5712static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5713 u32 *fp,
9a7c7890 5714 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5715{
de13a2e3 5716 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5717 struct drm_device *dev = crtc->dev;
5718 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5719 struct intel_encoder *intel_encoder;
5720 uint32_t dpll;
6cc5f341 5721 int factor, num_connectors = 0;
09ede541 5722 bool is_lvds = false, is_sdvo = false;
79e53945 5723
de13a2e3
PZ		 5724 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5725 switch (intel_encoder->type) {
79e53945
JB		 5726 case INTEL_OUTPUT_LVDS:
5727 is_lvds = true;
5728 break;
5729 case INTEL_OUTPUT_SDVO:
7d57382e 5730 case INTEL_OUTPUT_HDMI:
79e53945 5731 is_sdvo = true;
79e53945 5732 break;
79e53945 5733 }
43565a06 5734
c751ce4f 5735 num_connectors++;
79e53945 5736 }
79e53945 5737
c1858123 5738 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5739 factor = 21;
5740 if (is_lvds) {
5741 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5742 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5743 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5744 factor = 25;
09ede541 5745 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5746 factor = 20;
c1858123 5747
7429e9d4 5748 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5749 *fp |= FP_CB_TUNE;
2c07245f 5750
9a7c7890
DV		 5751 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5752 *fp2 |= FP_CB_TUNE;
5753
5eddb70b 5754 dpll = 0;
2c07245f 5755
a07d6787
EA		 5756 if (is_lvds)
5757 dpll |= DPLLB_MODE_LVDS;
5758 else
5759 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5760
ef1b460d
DV		 5761 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5762 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5763
5764 if (is_sdvo)
4a33e48d 5765 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5766 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5767 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5768
a07d6787 5769 /* compute bitmask from p1 value */
7429e9d4 5770 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5771 /* also FPA1 */
7429e9d4 5772 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5773
7429e9d4 5774 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5775 case 5:
5776 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5777 break;
5778 case 7:
5779 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5780 break;
5781 case 10:
5782 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5783 break;
5784 case 14:
5785 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5786 break;
79e53945
JB		 5787 }
5788
b4c09f3b 5789 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5790 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5791 else
5792 dpll |= PLL_REF_INPUT_DREFCLK;
5793
959e16d6 5794 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5795}
5796
5797static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5798 int x, int y,
5799 struct drm_framebuffer *fb)
5800{
5801 struct drm_device *dev = crtc->dev;
5802 struct drm_i915_private *dev_priv = dev->dev_private;
5803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5804 int pipe = intel_crtc->pipe;
5805 int plane = intel_crtc->plane;
5806 int num_connectors = 0;
5807 intel_clock_t clock, reduced_clock;
cbbab5bd 5808 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5809 bool ok, has_reduced_clock = false;
8b47047b 5810 bool is_lvds = false;
de13a2e3 5811 struct intel_encoder *encoder;
e2b78267 5812 struct intel_shared_dpll *pll;
de13a2e3 5813 int ret;
de13a2e3
PZ		 5814
5815 for_each_encoder_on_crtc(dev, crtc, encoder) {
5816 switch (encoder->type) {
5817 case INTEL_OUTPUT_LVDS:
5818 is_lvds = true;
5819 break;
de13a2e3
PZ		 5820 }
5821
5822 num_connectors++;
a07d6787 5823 }
79e53945 5824
5dc5298b
PZ		 5825 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5826 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5827
ff9a6750 5828 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5829 &has_reduced_clock, &reduced_clock);
ee9300bb 5830 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5831 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5832 return -EINVAL;
79e53945 5833 }
f47709a9
DV		 5834 /* Compat-code for transition, will disappear. */
5835 if (!intel_crtc->config.clock_set) {
5836 intel_crtc->config.dpll.n = clock.n;
5837 intel_crtc->config.dpll.m1 = clock.m1;
5838 intel_crtc->config.dpll.m2 = clock.m2;
5839 intel_crtc->config.dpll.p1 = clock.p1;
5840 intel_crtc->config.dpll.p2 = clock.p2;
5841 }
79e53945 5842
de13a2e3
PZ		 5843 /* Ensure that the cursor is valid for the new mode before changing... */
5844 intel_crtc_update_cursor(crtc, true);
5845
5dc5298b 5846 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5847 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5848 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5849 if (has_reduced_clock)
7429e9d4 5850 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5851
7429e9d4 5852 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5853 &fp, &reduced_clock,
5854 has_reduced_clock ? &fp2 : NULL);
5855
959e16d6 5856 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5857 intel_crtc->config.dpll_hw_state.fp0 = fp;
5858 if (has_reduced_clock)
5859 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5860 else
5861 intel_crtc->config.dpll_hw_state.fp1 = fp;
5862
b89a1d39 5863 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5864 if (pll == NULL) {
84f44ce7
VS		 5865 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5866 pipe_name(pipe));
4b645f14
JB		 5867 return -EINVAL;
5868 }
ee7b9f93 5869 } else
e72f9fbf 5870 intel_put_shared_dpll(intel_crtc);
79e53945 5871
03afc4a2
DV		 5872 if (intel_crtc->config.has_dp_encoder)
5873 intel_dp_set_m_n(intel_crtc);
79e53945 5874
bcd644e0
DV		 5875 if (is_lvds && has_reduced_clock && i915_powersave)
5876 intel_crtc->lowfreq_avail = true;
5877 else
5878 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5879
5880 if (intel_crtc->config.has_pch_encoder) {
5881 pll = intel_crtc_to_shared_dpll(intel_crtc);
5882
652c393a
JB		 5883 }
5884
8a654f3b 5885 intel_set_pipe_timings(intel_crtc);
5eddb70b 5886
ca3a0ff8 5887 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5888 intel_cpu_transcoder_set_m_n(intel_crtc,
5889 &intel_crtc->config.fdi_m_n);
5890 }
2c07245f 5891
ebfd86fd
DV		 5892 if (IS_IVYBRIDGE(dev))
5893 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5894
6ff93609 5895 ironlake_set_pipeconf(crtc);
79e53945 5896
a1f9e77e
PZ		 5897 /* Set up the display plane register */
5898 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5899 POSTING_READ(DSPCNTR(plane));
79e53945 5900
94352cf9 5901 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5902
1857e1da 5903 return ret;
79e53945
JB		 5904}
5905
eb14cb74
VS		 5906static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5907 struct intel_link_m_n *m_n)
5908{
5909 struct drm_device *dev = crtc->base.dev;
5910 struct drm_i915_private *dev_priv = dev->dev_private;
5911 enum pipe pipe = crtc->pipe;
5912
5913 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5914 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5915 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5916 & ~TU_SIZE_MASK;
5917 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5918 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5919 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5920}
5921
5922static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5923 enum transcoder transcoder,
5924 struct intel_link_m_n *m_n)
72419203
DV		 5925{
5926 struct drm_device *dev = crtc->base.dev;
5927 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5928 enum pipe pipe = crtc->pipe;
5929
5930 if (INTEL_INFO(dev)->gen >= 5) {
5931 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5932 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5933 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5934 & ~TU_SIZE_MASK;
5935 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5936 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5937 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5938 } else {
5939 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5940 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5941 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5942 & ~TU_SIZE_MASK;
5943 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5944 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5945 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5946 }
5947}
5948
5949void intel_dp_get_m_n(struct intel_crtc *crtc,
5950 struct intel_crtc_config *pipe_config)
5951{
5952 if (crtc->config.has_pch_encoder)
5953 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5954 else
5955 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5956 &pipe_config->dp_m_n);
5957}
72419203 5958
eb14cb74
VS		 5959static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5960 struct intel_crtc_config *pipe_config)
5961{
5962 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5963 &pipe_config->fdi_m_n);
72419203
DV		 5964}
5965
2fa2fe9a
DV		 5966static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5967 struct intel_crtc_config *pipe_config)
5968{
5969 struct drm_device *dev = crtc->base.dev;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
5971 uint32_t tmp;
5972
5973 tmp = I915_READ(PF_CTL(crtc->pipe));
5974
5975 if (tmp & PF_ENABLE) {
5976 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5977 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5978
5979 /* We currently do not free assignements of panel fitters on
5980 * ivb/hsw (since we don't use the higher upscaling modes which
5981 * differentiates them) so just WARN about this case for now. */
5982 if (IS_GEN7(dev)) {
5983 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5984 PF_PIPE_SEL_IVB(crtc->pipe));
5985 }
2fa2fe9a 5986 }
79e53945
JB		 5987}
5988
0e8ffe1b
DV		 5989static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5990 struct intel_crtc_config *pipe_config)
5991{
5992 struct drm_device *dev = crtc->base.dev;
5993 struct drm_i915_private *dev_priv = dev->dev_private;
5994 uint32_t tmp;
5995
e143a21c 5996 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5997 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5998
0e8ffe1b
DV		 5999 tmp = I915_READ(PIPECONF(crtc->pipe));
6000 if (!(tmp & PIPECONF_ENABLE))
6001 return false;
6002
42571aef
VS		 6003 switch (tmp & PIPECONF_BPC_MASK) {
6004 case PIPECONF_6BPC:
6005 pipe_config->pipe_bpp = 18;
6006 break;
6007 case PIPECONF_8BPC:
6008 pipe_config->pipe_bpp = 24;
6009 break;
6010 case PIPECONF_10BPC:
6011 pipe_config->pipe_bpp = 30;
6012 break;
6013 case PIPECONF_12BPC:
6014 pipe_config->pipe_bpp = 36;
6015 break;
6016 default:
6017 break;
6018 }
6019
ab9412ba 6020 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6021 struct intel_shared_dpll *pll;
6022
88adfff1
DV		 6023 pipe_config->has_pch_encoder = true;
6024
627eb5a3
DV		 6025 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6026 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6027 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6028
6029 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6030
c0d43d62 6031 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6032 pipe_config->shared_dpll =
6033 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6034 } else {
6035 tmp = I915_READ(PCH_DPLL_SEL);
6036 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6037 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6038 else
6039 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6040 }
66e985c0
DV		 6041
6042 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6043
6044 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6045 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6046
6047 tmp = pipe_config->dpll_hw_state.dpll;
6048 pipe_config->pixel_multiplier =
6049 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6050 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6051
6052 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6053 } else {
6054 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6055 }
6056
1bd1bd80
DV		 6057 intel_get_pipe_timings(crtc, pipe_config);
6058
2fa2fe9a
DV		 6059 ironlake_get_pfit_config(crtc, pipe_config);
6060
0e8ffe1b
DV		 6061 return true;
6062}
6063
be256dc7
PZ		 6064static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6065{
6066 struct drm_device *dev = dev_priv->dev;
6067 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6068 struct intel_crtc *crtc;
6069 unsigned long irqflags;
bd633a7c 6070 uint32_t val;
be256dc7
PZ		 6071
6072 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6073 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6074 pipe_name(crtc->pipe));
6075
6076 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6077 WARN(plls->spll_refcount, "SPLL enabled\n");
6078 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6079 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6080 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6081 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6082 "CPU PWM1 enabled\n");
6083 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6084 "CPU PWM2 enabled\n");
6085 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6086 "PCH PWM1 enabled\n");
6087 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6088 "Utility pin enabled\n");
6089 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6090
6091 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6092 val = I915_READ(DEIMR);
6093 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6094 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6095 val = I915_READ(SDEIMR);
bd633a7c 6096 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6097 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6098 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6099}
6100
6101/*
6102 * This function implements pieces of two sequences from BSpec:
6103 * - Sequence for display software to disable LCPLL
6104 * - Sequence for display software to allow package C8+
6105 * The steps implemented here are just the steps that actually touch the LCPLL
6106 * register. Callers should take care of disabling all the display engine
6107 * functions, doing the mode unset, fixing interrupts, etc.
6108 */
6109void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6110 bool switch_to_fclk, bool allow_power_down)
6111{
6112 uint32_t val;
6113
6114 assert_can_disable_lcpll(dev_priv);
6115
6116 val = I915_READ(LCPLL_CTL);
6117
6118 if (switch_to_fclk) {
6119 val |= LCPLL_CD_SOURCE_FCLK;
6120 I915_WRITE(LCPLL_CTL, val);
6121
6122 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6123 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6124 DRM_ERROR("Switching to FCLK failed\n");
6125
6126 val = I915_READ(LCPLL_CTL);
6127 }
6128
6129 val |= LCPLL_PLL_DISABLE;
6130 I915_WRITE(LCPLL_CTL, val);
6131 POSTING_READ(LCPLL_CTL);
6132
6133 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6134 DRM_ERROR("LCPLL still locked\n");
6135
6136 val = I915_READ(D_COMP);
6137 val |= D_COMP_COMP_DISABLE;
6138 I915_WRITE(D_COMP, val);
6139 POSTING_READ(D_COMP);
6140 ndelay(100);
6141
6142 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6143 DRM_ERROR("D_COMP RCOMP still in progress\n");
6144
6145 if (allow_power_down) {
6146 val = I915_READ(LCPLL_CTL);
6147 val |= LCPLL_POWER_DOWN_ALLOW;
6148 I915_WRITE(LCPLL_CTL, val);
6149 POSTING_READ(LCPLL_CTL);
6150 }
6151}
6152
6153/*
6154 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6155 * source.
6156 */
6157void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6158{
6159 uint32_t val;
6160
6161 val = I915_READ(LCPLL_CTL);
6162
6163 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6164 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6165 return;
6166
215733fa
PZ		 6167 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6168 * we'll hang the machine! */
6169 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6170
be256dc7
PZ		 6171 if (val & LCPLL_POWER_DOWN_ALLOW) {
6172 val &= ~LCPLL_POWER_DOWN_ALLOW;
6173 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6174 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6175 }
6176
6177 val = I915_READ(D_COMP);
6178 val |= D_COMP_COMP_FORCE;
6179 val &= ~D_COMP_COMP_DISABLE;
6180 I915_WRITE(D_COMP, val);
35d8f2eb 6181 POSTING_READ(D_COMP);
be256dc7
PZ		 6182
6183 val = I915_READ(LCPLL_CTL);
6184 val &= ~LCPLL_PLL_DISABLE;
6185 I915_WRITE(LCPLL_CTL, val);
6186
6187 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6188 DRM_ERROR("LCPLL not locked yet\n");
6189
6190 if (val & LCPLL_CD_SOURCE_FCLK) {
6191 val = I915_READ(LCPLL_CTL);
6192 val &= ~LCPLL_CD_SOURCE_FCLK;
6193 I915_WRITE(LCPLL_CTL, val);
6194
6195 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6196 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6197 DRM_ERROR("Switching back to LCPLL failed\n");
6198 }
215733fa
PZ		 6199
6200 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6201}
6202
c67a470b
PZ		 6203void hsw_enable_pc8_work(struct work_struct *__work)
6204{
6205 struct drm_i915_private *dev_priv =
6206 container_of(to_delayed_work(__work), struct drm_i915_private,
6207 pc8.enable_work);
6208 struct drm_device *dev = dev_priv->dev;
6209 uint32_t val;
6210
6211 if (dev_priv->pc8.enabled)
6212 return;
6213
6214 DRM_DEBUG_KMS("Enabling package C8+\n");
6215
6216 dev_priv->pc8.enabled = true;
6217
6218 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6219 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6220 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6221 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6222 }
6223
6224 lpt_disable_clkout_dp(dev);
6225 hsw_pc8_disable_interrupts(dev);
6226 hsw_disable_lcpll(dev_priv, true, true);
6227}
6228
6229static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6230{
6231 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6232 WARN(dev_priv->pc8.disable_count < 1,
6233 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6234
6235 dev_priv->pc8.disable_count--;
6236 if (dev_priv->pc8.disable_count != 0)
6237 return;
6238
6239 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6240 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6241}
6242
6243static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6244{
6245 struct drm_device *dev = dev_priv->dev;
6246 uint32_t val;
6247
6248 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6249 WARN(dev_priv->pc8.disable_count < 0,
6250 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6251
6252 dev_priv->pc8.disable_count++;
6253 if (dev_priv->pc8.disable_count != 1)
6254 return;
6255
6256 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6257 if (!dev_priv->pc8.enabled)
6258 return;
6259
6260 DRM_DEBUG_KMS("Disabling package C8+\n");
6261
6262 hsw_restore_lcpll(dev_priv);
6263 hsw_pc8_restore_interrupts(dev);
6264 lpt_init_pch_refclk(dev);
6265
6266 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6267 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6268 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6269 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6270 }
6271
6272 intel_prepare_ddi(dev);
6273 i915_gem_init_swizzling(dev);
6274 mutex_lock(&dev_priv->rps.hw_lock);
6275 gen6_update_ring_freq(dev);
6276 mutex_unlock(&dev_priv->rps.hw_lock);
6277 dev_priv->pc8.enabled = false;
6278}
6279
6280void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6281{
6282 mutex_lock(&dev_priv->pc8.lock);
6283 __hsw_enable_package_c8(dev_priv);
6284 mutex_unlock(&dev_priv->pc8.lock);
6285}
6286
6287void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6288{
6289 mutex_lock(&dev_priv->pc8.lock);
6290 __hsw_disable_package_c8(dev_priv);
6291 mutex_unlock(&dev_priv->pc8.lock);
6292}
6293
6294static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6295{
6296 struct drm_device *dev = dev_priv->dev;
6297 struct intel_crtc *crtc;
6298 uint32_t val;
6299
6300 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6301 if (crtc->base.enabled)
6302 return false;
6303
6304 /* This case is still possible since we have the i915.disable_power_well
6305 * parameter and also the KVMr or something else might be requesting the
6306 * power well. */
6307 val = I915_READ(HSW_PWR_WELL_DRIVER);
6308 if (val != 0) {
6309 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6310 return false;
6311 }
6312
6313 return true;
6314}
6315
6316/* Since we're called from modeset_global_resources there's no way to
6317 * symmetrically increase and decrease the refcount, so we use
6318 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6319 * or not.
6320 */
6321static void hsw_update_package_c8(struct drm_device *dev)
6322{
6323 struct drm_i915_private *dev_priv = dev->dev_private;
6324 bool allow;
6325
6326 if (!i915_enable_pc8)
6327 return;
6328
6329 mutex_lock(&dev_priv->pc8.lock);
6330
6331 allow = hsw_can_enable_package_c8(dev_priv);
6332
6333 if (allow == dev_priv->pc8.requirements_met)
6334 goto done;
6335
6336 dev_priv->pc8.requirements_met = allow;
6337
6338 if (allow)
6339 __hsw_enable_package_c8(dev_priv);
6340 else
6341 __hsw_disable_package_c8(dev_priv);
6342
6343done:
6344 mutex_unlock(&dev_priv->pc8.lock);
6345}
6346
6347static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6348{
6349 if (!dev_priv->pc8.gpu_idle) {
6350 dev_priv->pc8.gpu_idle = true;
6351 hsw_enable_package_c8(dev_priv);
6352 }
6353}
6354
6355static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6356{
6357 if (dev_priv->pc8.gpu_idle) {
6358 dev_priv->pc8.gpu_idle = false;
6359 hsw_disable_package_c8(dev_priv);
6360 }
be256dc7
PZ		 6361}
6362
d6dd9eb1
DV		 6363static void haswell_modeset_global_resources(struct drm_device *dev)
6364{
d6dd9eb1
DV		 6365 bool enable = false;
6366 struct intel_crtc *crtc;
d6dd9eb1
DV		 6367
6368 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6369 if (!crtc->base.enabled)
6370 continue;
d6dd9eb1 6371
e7a639c4
DV		 6372 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6373 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6374 enable = true;
6375 }
6376
d6dd9eb1 6377 intel_set_power_well(dev, enable);
c67a470b
PZ		 6378
6379 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6380}
6381
09b4ddf9 6382static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6383 int x, int y,
6384 struct drm_framebuffer *fb)
6385{
6386 struct drm_device *dev = crtc->dev;
6387 struct drm_i915_private *dev_priv = dev->dev_private;
6388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6389 int plane = intel_crtc->plane;
09b4ddf9 6390 int ret;
09b4ddf9 6391
ff9a6750 6392 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6393 return -EINVAL;
6394
09b4ddf9
PZ		 6395 /* Ensure that the cursor is valid for the new mode before changing... */
6396 intel_crtc_update_cursor(crtc, true);
6397
03afc4a2
DV		 6398 if (intel_crtc->config.has_dp_encoder)
6399 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6400
6401 intel_crtc->lowfreq_avail = false;
09b4ddf9 6402
8a654f3b 6403 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6404
ca3a0ff8 6405 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6406 intel_cpu_transcoder_set_m_n(intel_crtc,
6407 &intel_crtc->config.fdi_m_n);
6408 }
09b4ddf9 6409
6ff93609 6410 haswell_set_pipeconf(crtc);
09b4ddf9 6411
50f3b016 6412 intel_set_pipe_csc(crtc);
86d3efce 6413
09b4ddf9 6414 /* Set up the display plane register */
86d3efce 6415 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6416 POSTING_READ(DSPCNTR(plane));
6417
6418 ret = intel_pipe_set_base(crtc, x, y, fb);
6419
1f803ee5 6420 return ret;
79e53945
JB		 6421}
6422
0e8ffe1b
DV		 6423static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6424 struct intel_crtc_config *pipe_config)
6425{
6426 struct drm_device *dev = crtc->base.dev;
6427 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6428 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6429 uint32_t tmp;
6430
e143a21c 6431 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6432 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6433
eccb140b
DV		 6434 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6435 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6436 enum pipe trans_edp_pipe;
6437 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6438 default:
6439 WARN(1, "unknown pipe linked to edp transcoder\n");
6440 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6441 case TRANS_DDI_EDP_INPUT_A_ON:
6442 trans_edp_pipe = PIPE_A;
6443 break;
6444 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6445 trans_edp_pipe = PIPE_B;
6446 break;
6447 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6448 trans_edp_pipe = PIPE_C;
6449 break;
6450 }
6451
6452 if (trans_edp_pipe == crtc->pipe)
6453 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6454 }
6455
b97186f0 6456 if (!intel_display_power_enabled(dev,
eccb140b 6457 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6458 return false;
6459
eccb140b 6460 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6461 if (!(tmp & PIPECONF_ENABLE))
6462 return false;
6463
88adfff1 6464 /*
f196e6be 6465 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6466 * DDI E. So just check whether this pipe is wired to DDI E and whether
6467 * the PCH transcoder is on.
6468 */
eccb140b 6469 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6470 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6471 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6472 pipe_config->has_pch_encoder = true;
6473
627eb5a3
DV		 6474 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6475 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6476 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6477
6478 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6479 }
6480
1bd1bd80
DV		 6481 intel_get_pipe_timings(crtc, pipe_config);
6482
2fa2fe9a
DV		 6483 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6484 if (intel_display_power_enabled(dev, pfit_domain))
6485 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6486
42db64ef
PZ		 6487 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6488 (I915_READ(IPS_CTL) & IPS_ENABLE);
6489
6c49f241
DV		 6490 pipe_config->pixel_multiplier = 1;
6491
0e8ffe1b
DV		 6492 return true;
6493}
6494
f564048e 6495static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6496 int x, int y,
94352cf9 6497 struct drm_framebuffer *fb)
f564048e
EA		 6498{
6499 struct drm_device *dev = crtc->dev;
6500 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6501 struct intel_encoder *encoder;
0b701d27 6502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6503 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6504 int pipe = intel_crtc->pipe;
f564048e
EA		 6505 int ret;
6506
0b701d27 6507 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6508
b8cecdf5
DV		 6509 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6510
79e53945 6511 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6512
9256aa19
DV		 6513 if (ret != 0)
6514 return ret;
6515
6516 for_each_encoder_on_crtc(dev, crtc, encoder) {
6517 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6518 encoder->base.base.id,
6519 drm_get_encoder_name(&encoder->base),
6520 mode->base.id, mode->name);
36f2d1f1 6521 encoder->mode_set(encoder);
9256aa19
DV		 6522 }
6523
6524 return 0;
79e53945
JB		 6525}
6526
3a9627f4
WF		 6527static bool intel_eld_uptodate(struct drm_connector *connector,
6528 int reg_eldv, uint32_t bits_eldv,
6529 int reg_elda, uint32_t bits_elda,
6530 int reg_edid)
6531{
6532 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6533 uint8_t *eld = connector->eld;
6534 uint32_t i;
6535
6536 i = I915_READ(reg_eldv);
6537 i &= bits_eldv;
6538
6539 if (!eld[0])
6540 return !i;
6541
6542 if (!i)
6543 return false;
6544
6545 i = I915_READ(reg_elda);
6546 i &= ~bits_elda;
6547 I915_WRITE(reg_elda, i);
6548
6549 for (i = 0; i < eld[2]; i++)
6550 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6551 return false;
6552
6553 return true;
6554}
6555
e0dac65e
WF		 6556static void g4x_write_eld(struct drm_connector *connector,
6557 struct drm_crtc *crtc)
6558{
6559 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6560 uint8_t *eld = connector->eld;
6561 uint32_t eldv;
6562 uint32_t len;
6563 uint32_t i;
6564
6565 i = I915_READ(G4X_AUD_VID_DID);
6566
6567 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6568 eldv = G4X_ELDV_DEVCL_DEVBLC;
6569 else
6570 eldv = G4X_ELDV_DEVCTG;
6571
3a9627f4
WF		 6572 if (intel_eld_uptodate(connector,
6573 G4X_AUD_CNTL_ST, eldv,
6574 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6575 G4X_HDMIW_HDMIEDID))
6576 return;
6577
e0dac65e
WF		 6578 i = I915_READ(G4X_AUD_CNTL_ST);
6579 i &= ~(eldv | G4X_ELD_ADDR);
6580 len = (i >> 9) & 0x1f; /* ELD buffer size */
6581 I915_WRITE(G4X_AUD_CNTL_ST, i);
6582
6583 if (!eld[0])
6584 return;
6585
6586 len = min_t(uint8_t, eld[2], len);
6587 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6588 for (i = 0; i < len; i++)
6589 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6590
6591 i = I915_READ(G4X_AUD_CNTL_ST);
6592 i |= eldv;
6593 I915_WRITE(G4X_AUD_CNTL_ST, i);
6594}
6595
83358c85
WX		 6596static void haswell_write_eld(struct drm_connector *connector,
6597 struct drm_crtc *crtc)
6598{
6599 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6600 uint8_t *eld = connector->eld;
6601 struct drm_device *dev = crtc->dev;
7b9f35a6 6602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6603 uint32_t eldv;
6604 uint32_t i;
6605 int len;
6606 int pipe = to_intel_crtc(crtc)->pipe;
6607 int tmp;
6608
6609 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6610 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6611 int aud_config = HSW_AUD_CFG(pipe);
6612 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6613
6614
6615 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6616
6617 /* Audio output enable */
6618 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6619 tmp = I915_READ(aud_cntrl_st2);
6620 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6621 I915_WRITE(aud_cntrl_st2, tmp);
6622
6623 /* Wait for 1 vertical blank */
6624 intel_wait_for_vblank(dev, pipe);
6625
6626 /* Set ELD valid state */
6627 tmp = I915_READ(aud_cntrl_st2);
6628 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6629 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6630 I915_WRITE(aud_cntrl_st2, tmp);
6631 tmp = I915_READ(aud_cntrl_st2);
6632 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6633
6634 /* Enable HDMI mode */
6635 tmp = I915_READ(aud_config);
6636 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6637 /* clear N_programing_enable and N_value_index */
6638 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6639 I915_WRITE(aud_config, tmp);
6640
6641 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6642
6643 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6644 intel_crtc->eld_vld = true;
83358c85
WX		 6645
6646 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6647 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6648 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6649 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6650 } else
6651 I915_WRITE(aud_config, 0);
6652
6653 if (intel_eld_uptodate(connector,
6654 aud_cntrl_st2, eldv,
6655 aud_cntl_st, IBX_ELD_ADDRESS,
6656 hdmiw_hdmiedid))
6657 return;
6658
6659 i = I915_READ(aud_cntrl_st2);
6660 i &= ~eldv;
6661 I915_WRITE(aud_cntrl_st2, i);
6662
6663 if (!eld[0])
6664 return;
6665
6666 i = I915_READ(aud_cntl_st);
6667 i &= ~IBX_ELD_ADDRESS;
6668 I915_WRITE(aud_cntl_st, i);
6669 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6670 DRM_DEBUG_DRIVER("port num:%d\n", i);
6671
6672 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6673 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6674 for (i = 0; i < len; i++)
6675 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6676
6677 i = I915_READ(aud_cntrl_st2);
6678 i |= eldv;
6679 I915_WRITE(aud_cntrl_st2, i);
6680
6681}
6682
e0dac65e
WF		 6683static void ironlake_write_eld(struct drm_connector *connector,
6684 struct drm_crtc *crtc)
6685{
6686 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6687 uint8_t *eld = connector->eld;
6688 uint32_t eldv;
6689 uint32_t i;
6690 int len;
6691 int hdmiw_hdmiedid;
b6daa025 6692 int aud_config;
e0dac65e
WF		 6693 int aud_cntl_st;
6694 int aud_cntrl_st2;
9b138a83 6695 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6696
b3f33cbf 6697 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6698 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6699 aud_config = IBX_AUD_CFG(pipe);
6700 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6701 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6702 } else {
9b138a83
WX		 6703 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6704 aud_config = CPT_AUD_CFG(pipe);
6705 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6706 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6707 }
6708
9b138a83 6709 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6710
6711 i = I915_READ(aud_cntl_st);
9b138a83 6712 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6713 if (!i) {
6714 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6715 /* operate blindly on all ports */
1202b4c6
WF		 6716 eldv = IBX_ELD_VALIDB;
6717 eldv |= IBX_ELD_VALIDB << 4;
6718 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6719 } else {
2582a850 6720 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6721 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6722 }
6723
3a9627f4
WF		 6724 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6725 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6726 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6727 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6728 } else
6729 I915_WRITE(aud_config, 0);
e0dac65e 6730
3a9627f4
WF		 6731 if (intel_eld_uptodate(connector,
6732 aud_cntrl_st2, eldv,
6733 aud_cntl_st, IBX_ELD_ADDRESS,
6734 hdmiw_hdmiedid))
6735 return;
6736
e0dac65e
WF		 6737 i = I915_READ(aud_cntrl_st2);
6738 i &= ~eldv;
6739 I915_WRITE(aud_cntrl_st2, i);
6740
6741 if (!eld[0])
6742 return;
6743
e0dac65e 6744 i = I915_READ(aud_cntl_st);
1202b4c6 6745 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6746 I915_WRITE(aud_cntl_st, i);
6747
6748 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6749 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6750 for (i = 0; i < len; i++)
6751 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6752
6753 i = I915_READ(aud_cntrl_st2);
6754 i |= eldv;
6755 I915_WRITE(aud_cntrl_st2, i);
6756}
6757
6758void intel_write_eld(struct drm_encoder *encoder,
6759 struct drm_display_mode *mode)
6760{
6761 struct drm_crtc *crtc = encoder->crtc;
6762 struct drm_connector *connector;
6763 struct drm_device *dev = encoder->dev;
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765
6766 connector = drm_select_eld(encoder, mode);
6767 if (!connector)
6768 return;
6769
6770 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6771 connector->base.id,
6772 drm_get_connector_name(connector),
6773 connector->encoder->base.id,
6774 drm_get_encoder_name(connector->encoder));
6775
6776 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6777
6778 if (dev_priv->display.write_eld)
6779 dev_priv->display.write_eld(connector, crtc);
6780}
6781
79e53945
JB		 6782/** Loads the palette/gamma unit for the CRTC with the prepared values */
6783void intel_crtc_load_lut(struct drm_crtc *crtc)
6784{
6785 struct drm_device *dev = crtc->dev;
6786 struct drm_i915_private *dev_priv = dev->dev_private;
6787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6788 enum pipe pipe = intel_crtc->pipe;
6789 int palreg = PALETTE(pipe);
79e53945 6790 int i;
42db64ef 6791 bool reenable_ips = false;
79e53945
JB		 6792
6793 /* The clocks have to be on to load the palette. */
aed3f09d 6794 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6795 return;
6796
23538ef1
JN		 6797 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6798 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6799 assert_dsi_pll_enabled(dev_priv);
6800 else
6801 assert_pll_enabled(dev_priv, pipe);
6802 }
14420bd0 6803
f2b115e6 6804 /* use legacy palette for Ironlake */
bad720ff 6805 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6806 palreg = LGC_PALETTE(pipe);
6807
6808 /* Workaround : Do not read or write the pipe palette/gamma data while
6809 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6810 */
6811 if (intel_crtc->config.ips_enabled &&
6812 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6813 GAMMA_MODE_MODE_SPLIT)) {
6814 hsw_disable_ips(intel_crtc);
6815 reenable_ips = true;
6816 }
2c07245f 6817
79e53945
JB		 6818 for (i = 0; i < 256; i++) {
6819 I915_WRITE(palreg + 4 * i,
6820 (intel_crtc->lut_r[i] << 16) |
6821 (intel_crtc->lut_g[i] << 8) |
6822 intel_crtc->lut_b[i]);
6823 }
42db64ef
PZ		 6824
6825 if (reenable_ips)
6826 hsw_enable_ips(intel_crtc);
79e53945
JB		 6827}
6828
560b85bb
CW		 6829static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6830{
6831 struct drm_device *dev = crtc->dev;
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6834 bool visible = base != 0;
6835 u32 cntl;
6836
6837 if (intel_crtc->cursor_visible == visible)
6838 return;
6839
9db4a9c7 6840 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6841 if (visible) {
6842 /* On these chipsets we can only modify the base whilst
6843 * the cursor is disabled.
6844 */
9db4a9c7 6845 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6846
6847 cntl &= ~(CURSOR_FORMAT_MASK);
6848 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6849 cntl |= CURSOR_ENABLE |
6850 CURSOR_GAMMA_ENABLE |
6851 CURSOR_FORMAT_ARGB;
6852 } else
6853 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6854 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6855
6856 intel_crtc->cursor_visible = visible;
6857}
6858
6859static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6860{
6861 struct drm_device *dev = crtc->dev;
6862 struct drm_i915_private *dev_priv = dev->dev_private;
6863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6864 int pipe = intel_crtc->pipe;
6865 bool visible = base != 0;
6866
6867 if (intel_crtc->cursor_visible != visible) {
548f245b 6868 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6869 if (base) {
6870 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6871 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6872 cntl |= pipe << 28; /* Connect to correct pipe */
6873 } else {
6874 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6875 cntl |= CURSOR_MODE_DISABLE;
6876 }
9db4a9c7 6877 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6878
6879 intel_crtc->cursor_visible = visible;
6880 }
6881 /* and commit changes on next vblank */
9db4a9c7 6882 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6883}
6884
65a21cd6
JB		 6885static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6886{
6887 struct drm_device *dev = crtc->dev;
6888 struct drm_i915_private *dev_priv = dev->dev_private;
6889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6890 int pipe = intel_crtc->pipe;
6891 bool visible = base != 0;
6892
6893 if (intel_crtc->cursor_visible != visible) {
6894 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6895 if (base) {
6896 cntl &= ~CURSOR_MODE;
6897 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6898 } else {
6899 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6900 cntl |= CURSOR_MODE_DISABLE;
6901 }
1f5d76db 6902 if (IS_HASWELL(dev)) {
86d3efce 6903 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6904 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6905 }
65a21cd6
JB		 6906 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6907
6908 intel_crtc->cursor_visible = visible;
6909 }
6910 /* and commit changes on next vblank */
6911 I915_WRITE(CURBASE_IVB(pipe), base);
6912}
6913
cda4b7d3 6914/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6915static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6916 bool on)
cda4b7d3
CW		 6917{
6918 struct drm_device *dev = crtc->dev;
6919 struct drm_i915_private *dev_priv = dev->dev_private;
6920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6921 int pipe = intel_crtc->pipe;
6922 int x = intel_crtc->cursor_x;
6923 int y = intel_crtc->cursor_y;
560b85bb 6924 u32 base, pos;
cda4b7d3
CW		 6925 bool visible;
6926
6927 pos = 0;
6928
6b383a7f 6929 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6930 base = intel_crtc->cursor_addr;
6931 if (x > (int) crtc->fb->width)
6932 base = 0;
6933
6934 if (y > (int) crtc->fb->height)
6935 base = 0;
6936 } else
6937 base = 0;
6938
6939 if (x < 0) {
6940 if (x + intel_crtc->cursor_width < 0)
6941 base = 0;
6942
6943 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6944 x = -x;
6945 }
6946 pos |= x << CURSOR_X_SHIFT;
6947
6948 if (y < 0) {
6949 if (y + intel_crtc->cursor_height < 0)
6950 base = 0;
6951
6952 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6953 y = -y;
6954 }
6955 pos |= y << CURSOR_Y_SHIFT;
6956
6957 visible = base != 0;
560b85bb 6958 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6959 return;
6960
0cd83aa9 6961 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6962 I915_WRITE(CURPOS_IVB(pipe), pos);
6963 ivb_update_cursor(crtc, base);
6964 } else {
6965 I915_WRITE(CURPOS(pipe), pos);
6966 if (IS_845G(dev) || IS_I865G(dev))
6967 i845_update_cursor(crtc, base);
6968 else
6969 i9xx_update_cursor(crtc, base);
6970 }
cda4b7d3
CW		 6971}
6972
79e53945 6973static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6974 struct drm_file *file,
79e53945
JB		 6975 uint32_t handle,
6976 uint32_t width, uint32_t height)
6977{
6978 struct drm_device *dev = crtc->dev;
6979 struct drm_i915_private *dev_priv = dev->dev_private;
6980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6981 struct drm_i915_gem_object *obj;
cda4b7d3 6982 uint32_t addr;
3f8bc370 6983 int ret;
79e53945 6984
79e53945
JB		 6985 /* if we want to turn off the cursor ignore width and height */
6986 if (!handle) {
28c97730 6987 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6988 addr = 0;
05394f39 6989 obj = NULL;
5004417d 6990 mutex_lock(&dev->struct_mutex);
3f8bc370 6991 goto finish;
79e53945
JB		 6992 }
6993
6994 /* Currently we only support 64x64 cursors */
6995 if (width != 64 || height != 64) {
6996 DRM_ERROR("we currently only support 64x64 cursors\n");
6997 return -EINVAL;
6998 }
6999
05394f39 7000 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7001 if (&obj->base == NULL)
79e53945
JB		 7002 return -ENOENT;
7003
05394f39 7004 if (obj->base.size < width * height * 4) {
79e53945 7005 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7006 ret = -ENOMEM;
7007 goto fail;
79e53945
JB		 7008 }
7009
71acb5eb 7010 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7011 mutex_lock(&dev->struct_mutex);
b295d1b6 7012 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7013 unsigned alignment;
7014
d9e86c0e
CW		 7015 if (obj->tiling_mode) {
7016 DRM_ERROR("cursor cannot be tiled\n");
7017 ret = -EINVAL;
7018 goto fail_locked;
7019 }
7020
693db184
CW		 7021 /* Note that the w/a also requires 2 PTE of padding following
7022 * the bo. We currently fill all unused PTE with the shadow
7023 * page and so we should always have valid PTE following the
7024 * cursor preventing the VT-d warning.
7025 */
7026 alignment = 0;
7027 if (need_vtd_wa(dev))
7028 alignment = 64*1024;
7029
7030 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7031 if (ret) {
7032 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7033 goto fail_locked;
e7b526bb
CW		 7034 }
7035
d9e86c0e
CW		 7036 ret = i915_gem_object_put_fence(obj);
7037 if (ret) {
2da3b9b9 7038 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7039 goto fail_unpin;
7040 }
7041
f343c5f6 7042 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7043 } else {
6eeefaf3 7044 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7045 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7046 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7047 align);
71acb5eb
DA		 7048 if (ret) {
7049 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7050 goto fail_locked;
71acb5eb 7051 }
05394f39 7052 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7053 }
7054
a6c45cf0 7055 if (IS_GEN2(dev))
14b60391
JB		 7056 I915_WRITE(CURSIZE, (height << 12) | width);
7057
3f8bc370 7058 finish:
3f8bc370 7059 if (intel_crtc->cursor_bo) {
b295d1b6 7060 if (dev_priv->info->cursor_needs_physical) {
05394f39 7061 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7062 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7063 } else
cc98b413 7064 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7065 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7066 }
80824003 7067
7f9872e0 7068 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7069
7070 intel_crtc->cursor_addr = addr;
05394f39 7071 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7072 intel_crtc->cursor_width = width;
7073 intel_crtc->cursor_height = height;
7074
40ccc72b 7075 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7076
79e53945 7077 return 0;
e7b526bb 7078fail_unpin:
cc98b413 7079 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7080fail_locked:
34b8686e 7081 mutex_unlock(&dev->struct_mutex);
bc9025bd 7082fail:
05394f39 7083 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7084 return ret;
79e53945
JB		 7085}
7086
7087static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7088{
79e53945 7089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7090
cda4b7d3
CW		 7091 intel_crtc->cursor_x = x;
7092 intel_crtc->cursor_y = y;
652c393a 7093
40ccc72b 7094 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7095
7096 return 0;
7097}
7098
7099/** Sets the color ramps on behalf of RandR */
7100void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7101 u16 blue, int regno)
7102{
7103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7104
7105 intel_crtc->lut_r[regno] = red >> 8;
7106 intel_crtc->lut_g[regno] = green >> 8;
7107 intel_crtc->lut_b[regno] = blue >> 8;
7108}
7109
b8c00ac5
DA		 7110void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7111 u16 *blue, int regno)
7112{
7113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7114
7115 *red = intel_crtc->lut_r[regno] << 8;
7116 *green = intel_crtc->lut_g[regno] << 8;
7117 *blue = intel_crtc->lut_b[regno] << 8;
7118}
7119
79e53945 7120static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7121 u16 *blue, uint32_t start, uint32_t size)
79e53945 7122{
7203425a 7123 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7125
7203425a 7126 for (i = start; i < end; i++) {
79e53945
JB		 7127 intel_crtc->lut_r[i] = red[i] >> 8;
7128 intel_crtc->lut_g[i] = green[i] >> 8;
7129 intel_crtc->lut_b[i] = blue[i] >> 8;
7130 }
7131
7132 intel_crtc_load_lut(crtc);
7133}
7134
79e53945
JB		 7135/* VESA 640x480x72Hz mode to set on the pipe */
7136static struct drm_display_mode load_detect_mode = {
7137 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7138 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7139};
7140
d2dff872
CW		 7141static struct drm_framebuffer *
7142intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7143 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7144 struct drm_i915_gem_object *obj)
7145{
7146 struct intel_framebuffer *intel_fb;
7147 int ret;
7148
7149 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7150 if (!intel_fb) {
7151 drm_gem_object_unreference_unlocked(&obj->base);
7152 return ERR_PTR(-ENOMEM);
7153 }
7154
7155 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7156 if (ret) {
7157 drm_gem_object_unreference_unlocked(&obj->base);
7158 kfree(intel_fb);
7159 return ERR_PTR(ret);
7160 }
7161
7162 return &intel_fb->base;
7163}
7164
7165static u32
7166intel_framebuffer_pitch_for_width(int width, int bpp)
7167{
7168 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7169 return ALIGN(pitch, 64);
7170}
7171
7172static u32
7173intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7174{
7175 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7176 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7177}
7178
7179static struct drm_framebuffer *
7180intel_framebuffer_create_for_mode(struct drm_device *dev,
7181 struct drm_display_mode *mode,
7182 int depth, int bpp)
7183{
7184 struct drm_i915_gem_object *obj;
0fed39bd 7185 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7186
7187 obj = i915_gem_alloc_object(dev,
7188 intel_framebuffer_size_for_mode(mode, bpp));
7189 if (obj == NULL)
7190 return ERR_PTR(-ENOMEM);
7191
7192 mode_cmd.width = mode->hdisplay;
7193 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7194 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7195 bpp);
5ca0c34a 7196 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7197
7198 return intel_framebuffer_create(dev, &mode_cmd, obj);
7199}
7200
7201static struct drm_framebuffer *
7202mode_fits_in_fbdev(struct drm_device *dev,
7203 struct drm_display_mode *mode)
7204{
7205 struct drm_i915_private *dev_priv = dev->dev_private;
7206 struct drm_i915_gem_object *obj;
7207 struct drm_framebuffer *fb;
7208
7209 if (dev_priv->fbdev == NULL)
7210 return NULL;
7211
7212 obj = dev_priv->fbdev->ifb.obj;
7213 if (obj == NULL)
7214 return NULL;
7215
7216 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7217 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7218 fb->bits_per_pixel))
d2dff872
CW		 7219 return NULL;
7220
01f2c773 7221 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7222 return NULL;
7223
7224 return fb;
7225}
7226
d2434ab7 7227bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7228 struct drm_display_mode *mode,
8261b191 7229 struct intel_load_detect_pipe *old)
79e53945
JB		 7230{
7231 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7232 struct intel_encoder *intel_encoder =
7233 intel_attached_encoder(connector);
79e53945 7234 struct drm_crtc *possible_crtc;
4ef69c7a 7235 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7236 struct drm_crtc *crtc = NULL;
7237 struct drm_device *dev = encoder->dev;
94352cf9 7238 struct drm_framebuffer *fb;
79e53945
JB		 7239 int i = -1;
7240
d2dff872
CW		 7241 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7242 connector->base.id, drm_get_connector_name(connector),
7243 encoder->base.id, drm_get_encoder_name(encoder));
7244
79e53945
JB		 7245 /*
7246 * Algorithm gets a little messy:
7a5e4805 7247 *
79e53945
JB		 7248 * - if the connector already has an assigned crtc, use it (but make
7249 * sure it's on first)
7a5e4805 7250 *
79e53945
JB		 7251 * - try to find the first unused crtc that can drive this connector,
7252 * and use that if we find one
79e53945
JB		 7253 */
7254
7255 /* See if we already have a CRTC for this connector */
7256 if (encoder->crtc) {
7257 crtc = encoder->crtc;
8261b191 7258
7b24056b
DV		 7259 mutex_lock(&crtc->mutex);
7260
24218aac 7261 old->dpms_mode = connector->dpms;
8261b191
CW		 7262 old->load_detect_temp = false;
7263
7264 /* Make sure the crtc and connector are running */
24218aac
DV		 7265 if (connector->dpms != DRM_MODE_DPMS_ON)
7266 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7267
7173188d 7268 return true;
79e53945
JB		 7269 }
7270
7271 /* Find an unused one (if possible) */
7272 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7273 i++;
7274 if (!(encoder->possible_crtcs & (1 << i)))
7275 continue;
7276 if (!possible_crtc->enabled) {
7277 crtc = possible_crtc;
7278 break;
7279 }
79e53945
JB		 7280 }
7281
7282 /*
7283 * If we didn't find an unused CRTC, don't use any.
7284 */
7285 if (!crtc) {
7173188d
CW		 7286 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7287 return false;
79e53945
JB		 7288 }
7289
7b24056b 7290 mutex_lock(&crtc->mutex);
fc303101
DV		 7291 intel_encoder->new_crtc = to_intel_crtc(crtc);
7292 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7293
7294 intel_crtc = to_intel_crtc(crtc);
24218aac 7295 old->dpms_mode = connector->dpms;
8261b191 7296 old->load_detect_temp = true;
d2dff872 7297 old->release_fb = NULL;
79e53945 7298
6492711d
CW		 7299 if (!mode)
7300 mode = &load_detect_mode;
79e53945 7301
d2dff872
CW		 7302 /* We need a framebuffer large enough to accommodate all accesses
7303 * that the plane may generate whilst we perform load detection.
7304 * We can not rely on the fbcon either being present (we get called
7305 * during its initialisation to detect all boot displays, or it may
7306 * not even exist) or that it is large enough to satisfy the
7307 * requested mode.
7308 */
94352cf9
DV		 7309 fb = mode_fits_in_fbdev(dev, mode);
7310 if (fb == NULL) {
d2dff872 7311 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7312 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7313 old->release_fb = fb;
d2dff872
CW		 7314 } else
7315 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7316 if (IS_ERR(fb)) {
d2dff872 7317 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7318 mutex_unlock(&crtc->mutex);
0e8b3d3e 7319 return false;
79e53945 7320 }
79e53945 7321
c0c36b94 7322 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7323 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7324 if (old->release_fb)
7325 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7326 mutex_unlock(&crtc->mutex);
0e8b3d3e 7327 return false;
79e53945 7328 }
7173188d 7329
79e53945 7330 /* let the connector get through one full cycle before testing */
9d0498a2 7331 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7332 return true;
79e53945
JB		 7333}
7334
d2434ab7 7335void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7336 struct intel_load_detect_pipe *old)
79e53945 7337{
d2434ab7
DV		 7338 struct intel_encoder *intel_encoder =
7339 intel_attached_encoder(connector);
4ef69c7a 7340 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7341 struct drm_crtc *crtc = encoder->crtc;
79e53945 7342
d2dff872
CW		 7343 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7344 connector->base.id, drm_get_connector_name(connector),
7345 encoder->base.id, drm_get_encoder_name(encoder));
7346
8261b191 7347 if (old->load_detect_temp) {
fc303101
DV		 7348 to_intel_connector(connector)->new_encoder = NULL;
7349 intel_encoder->new_crtc = NULL;
7350 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7351
36206361
DV		 7352 if (old->release_fb) {
7353 drm_framebuffer_unregister_private(old->release_fb);
7354 drm_framebuffer_unreference(old->release_fb);
7355 }
d2dff872 7356
67c96400 7357 mutex_unlock(&crtc->mutex);
0622a53c 7358 return;
79e53945
JB		 7359 }
7360
c751ce4f 7361 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7362 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7363 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7364
7365 mutex_unlock(&crtc->mutex);
79e53945
JB		 7366}
7367
da4a1efa
VS		 7368static int i9xx_pll_refclk(struct drm_device *dev,
7369 const struct intel_crtc_config *pipe_config)
7370{
7371 struct drm_i915_private *dev_priv = dev->dev_private;
7372 u32 dpll = pipe_config->dpll_hw_state.dpll;
7373
7374 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7375 return dev_priv->vbt.lvds_ssc_freq * 1000;
7376 else if (HAS_PCH_SPLIT(dev))
7377 return 120000;
7378 else if (!IS_GEN2(dev))
7379 return 96000;
7380 else
7381 return 48000;
7382}
7383
79e53945 7384/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7385static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7386 struct intel_crtc_config *pipe_config)
79e53945 7387{
f1f644dc 7388 struct drm_device *dev = crtc->base.dev;
79e53945 7389 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7390 int pipe = pipe_config->cpu_transcoder;
293623f7 7391 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7392 u32 fp;
7393 intel_clock_t clock;
da4a1efa 7394 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7395
7396 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7397 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7398 else
293623f7 7399 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7400
7401 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7402 if (IS_PINEVIEW(dev)) {
7403 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7404 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7405 } else {
7406 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7407 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7408 }
7409
a6c45cf0 7410 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7411 if (IS_PINEVIEW(dev))
7412 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7413 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7414 else
7415 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7416 DPLL_FPA01_P1_POST_DIV_SHIFT);
7417
7418 switch (dpll & DPLL_MODE_MASK) {
7419 case DPLLB_MODE_DAC_SERIAL:
7420 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7421 5 : 10;
7422 break;
7423 case DPLLB_MODE_LVDS:
7424 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7425 7 : 14;
7426 break;
7427 default:
28c97730 7428 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7429 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7430 return;
79e53945
JB		 7431 }
7432
ac58c3f0 7433 if (IS_PINEVIEW(dev))
da4a1efa 7434 pineview_clock(refclk, &clock);
ac58c3f0 7435 else
da4a1efa 7436 i9xx_clock(refclk, &clock);
79e53945
JB		 7437 } else {
7438 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7439
7440 if (is_lvds) {
7441 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7442 DPLL_FPA01_P1_POST_DIV_SHIFT);
7443 clock.p2 = 14;
79e53945
JB		 7444 } else {
7445 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7446 clock.p1 = 2;
7447 else {
7448 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7449 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7450 }
7451 if (dpll & PLL_P2_DIVIDE_BY_4)
7452 clock.p2 = 4;
7453 else
7454 clock.p2 = 2;
79e53945 7455 }
da4a1efa
VS		 7456
7457 i9xx_clock(refclk, &clock);
79e53945
JB		 7458 }
7459
18442d08
VS		 7460 /*
7461 * This value includes pixel_multiplier. We will use
7462 * port_clock to compute adjusted_mode.clock in the
7463 * encoder's get_config() function.
7464 */
7465 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7466}
7467
6878da05
VS		 7468int intel_dotclock_calculate(int link_freq,
7469 const struct intel_link_m_n *m_n)
f1f644dc 7470{
f1f644dc
JB		 7471 /*
7472 * The calculation for the data clock is:
1041a02f 7473 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7474 * But we want to avoid losing precison if possible, so:
1041a02f 7475 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7476 *
7477 * and the link clock is simpler:
1041a02f 7478 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7479 */
7480
6878da05
VS		 7481 if (!m_n->link_n)
7482 return 0;
7483
7484 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7485}
7486
18442d08
VS		 7487static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7488 struct intel_crtc_config *pipe_config)
6878da05
VS		 7489{
7490 struct drm_device *dev = crtc->base.dev;
18442d08
VS		 7491
7492 /* read out port_clock from the DPLL */
7493 i9xx_crtc_clock_get(crtc, pipe_config);
6878da05 7494
f1f644dc 7495 /*
18442d08
VS		 7496 * This value does not include pixel_multiplier.
7497 * We will check that port_clock and adjusted_mode.clock
7498 * agree once we know their relationship in the encoder's
7499 * get_config() function.
79e53945 7500 */
18442d08
VS		 7501 pipe_config->adjusted_mode.clock =
7502 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7503 &pipe_config->fdi_m_n);
79e53945
JB		 7504}
7505
7506/** Returns the currently programmed mode of the given pipe. */
7507struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7508 struct drm_crtc *crtc)
7509{
548f245b 7510 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7512 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7513 struct drm_display_mode *mode;
f1f644dc 7514 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7515 int htot = I915_READ(HTOTAL(cpu_transcoder));
7516 int hsync = I915_READ(HSYNC(cpu_transcoder));
7517 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7518 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7519 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7520
7521 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7522 if (!mode)
7523 return NULL;
7524
f1f644dc
JB		 7525 /*
7526 * Construct a pipe_config sufficient for getting the clock info
7527 * back out of crtc_clock_get.
7528 *
7529 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7530 * to use a real value here instead.
7531 */
293623f7 7532 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7533 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7534 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7535 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7536 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7537 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7538
7539 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7540 mode->hdisplay = (htot & 0xffff) + 1;
7541 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7542 mode->hsync_start = (hsync & 0xffff) + 1;
7543 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7544 mode->vdisplay = (vtot & 0xffff) + 1;
7545 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7546 mode->vsync_start = (vsync & 0xffff) + 1;
7547 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7548
7549 drm_mode_set_name(mode);
79e53945
JB		 7550
7551 return mode;
7552}
7553
3dec0095 7554static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7555{
7556 struct drm_device *dev = crtc->dev;
7557 drm_i915_private_t *dev_priv = dev->dev_private;
7558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7559 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7560 int dpll_reg = DPLL(pipe);
7561 int dpll;
652c393a 7562
bad720ff 7563 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7564 return;
7565
7566 if (!dev_priv->lvds_downclock_avail)
7567 return;
7568
dbdc6479 7569 dpll = I915_READ(dpll_reg);
652c393a 7570 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7571 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7572
8ac5a6d5 7573 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7574
7575 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7576 I915_WRITE(dpll_reg, dpll);
9d0498a2 7577 intel_wait_for_vblank(dev, pipe);
dbdc6479 7578
652c393a
JB		 7579 dpll = I915_READ(dpll_reg);
7580 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7581 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7582 }
652c393a
JB		 7583}
7584
7585static void intel_decrease_pllclock(struct drm_crtc *crtc)
7586{
7587 struct drm_device *dev = crtc->dev;
7588 drm_i915_private_t *dev_priv = dev->dev_private;
7589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7590
bad720ff 7591 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7592 return;
7593
7594 if (!dev_priv->lvds_downclock_avail)
7595 return;
7596
7597 /*
7598 * Since this is called by a timer, we should never get here in
7599 * the manual case.
7600 */
7601 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7602 int pipe = intel_crtc->pipe;
7603 int dpll_reg = DPLL(pipe);
7604 int dpll;
f6e5b160 7605
44d98a61 7606 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7607
8ac5a6d5 7608 assert_panel_unlocked(dev_priv, pipe);
652c393a 7609
dc257cf1 7610 dpll = I915_READ(dpll_reg);
652c393a
JB		 7611 dpll |= DISPLAY_RATE_SELECT_FPA1;
7612 I915_WRITE(dpll_reg, dpll);
9d0498a2 7613 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7614 dpll = I915_READ(dpll_reg);
7615 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7616 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7617 }
7618
7619}
7620
f047e395
CW		 7621void intel_mark_busy(struct drm_device *dev)
7622{
c67a470b
PZ		 7623 struct drm_i915_private *dev_priv = dev->dev_private;
7624
7625 hsw_package_c8_gpu_busy(dev_priv);
7626 i915_update_gfx_val(dev_priv);
f047e395
CW		 7627}
7628
7629void intel_mark_idle(struct drm_device *dev)
652c393a 7630{
c67a470b 7631 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7632 struct drm_crtc *crtc;
652c393a 7633
c67a470b
PZ		 7634 hsw_package_c8_gpu_idle(dev_priv);
7635
652c393a
JB		 7636 if (!i915_powersave)
7637 return;
7638
652c393a 7639 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7640 if (!crtc->fb)
7641 continue;
7642
725a5b54 7643 intel_decrease_pllclock(crtc);
652c393a 7644 }
652c393a
JB		 7645}
7646
c65355bb
CW		 7647void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7648 struct intel_ring_buffer *ring)
652c393a 7649{
f047e395
CW		 7650 struct drm_device *dev = obj->base.dev;
7651 struct drm_crtc *crtc;
652c393a 7652
f047e395 7653 if (!i915_powersave)
acb87dfb
CW		 7654 return;
7655
652c393a
JB		 7656 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7657 if (!crtc->fb)
7658 continue;
7659
c65355bb
CW		 7660 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7661 continue;
7662
7663 intel_increase_pllclock(crtc);
7664 if (ring && intel_fbc_enabled(dev))
7665 ring->fbc_dirty = true;
652c393a
JB		 7666 }
7667}
7668
79e53945
JB		 7669static void intel_crtc_destroy(struct drm_crtc *crtc)
7670{
7671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7672 struct drm_device *dev = crtc->dev;
7673 struct intel_unpin_work *work;
7674 unsigned long flags;
7675
7676 spin_lock_irqsave(&dev->event_lock, flags);
7677 work = intel_crtc->unpin_work;
7678 intel_crtc->unpin_work = NULL;
7679 spin_unlock_irqrestore(&dev->event_lock, flags);
7680
7681 if (work) {
7682 cancel_work_sync(&work->work);
7683 kfree(work);
7684 }
79e53945 7685
40ccc72b
MK		 7686 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7687
79e53945 7688 drm_crtc_cleanup(crtc);
67e77c5a 7689
79e53945
JB		 7690 kfree(intel_crtc);
7691}
7692
6b95a207
KH		 7693static void intel_unpin_work_fn(struct work_struct *__work)
7694{
7695 struct intel_unpin_work *work =
7696 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7697 struct drm_device *dev = work->crtc->dev;
6b95a207 7698
b4a98e57 7699 mutex_lock(&dev->struct_mutex);
1690e1eb 7700 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7701 drm_gem_object_unreference(&work->pending_flip_obj->base);
7702 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7703
b4a98e57
CW		 7704 intel_update_fbc(dev);
7705 mutex_unlock(&dev->struct_mutex);
7706
7707 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7708 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7709
6b95a207
KH		 7710 kfree(work);
7711}
7712
1afe3e9d 7713static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7714 struct drm_crtc *crtc)
6b95a207
KH		 7715{
7716 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7718 struct intel_unpin_work *work;
6b95a207
KH		 7719 unsigned long flags;
7720
7721 /* Ignore early vblank irqs */
7722 if (intel_crtc == NULL)
7723 return;
7724
7725 spin_lock_irqsave(&dev->event_lock, flags);
7726 work = intel_crtc->unpin_work;
e7d841ca
CW		 7727
7728 /* Ensure we don't miss a work->pending update ... */
7729 smp_rmb();
7730
7731 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7732 spin_unlock_irqrestore(&dev->event_lock, flags);
7733 return;
7734 }
7735
e7d841ca
CW		 7736 /* and that the unpin work is consistent wrt ->pending. */
7737 smp_rmb();
7738
6b95a207 7739 intel_crtc->unpin_work = NULL;
6b95a207 7740
45a066eb
RC		 7741 if (work->event)
7742 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7743
0af7e4df
MK		 7744 drm_vblank_put(dev, intel_crtc->pipe);
7745
6b95a207
KH		 7746 spin_unlock_irqrestore(&dev->event_lock, flags);
7747
2c10d571 7748 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7749
7750 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7751
7752 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7753}
7754
1afe3e9d
JB		 7755void intel_finish_page_flip(struct drm_device *dev, int pipe)
7756{
7757 drm_i915_private_t *dev_priv = dev->dev_private;
7758 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7759
49b14a5c 7760 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7761}
7762
7763void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7764{
7765 drm_i915_private_t *dev_priv = dev->dev_private;
7766 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7767
49b14a5c 7768 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7769}
7770
6b95a207
KH		 7771void intel_prepare_page_flip(struct drm_device *dev, int plane)
7772{
7773 drm_i915_private_t *dev_priv = dev->dev_private;
7774 struct intel_crtc *intel_crtc =
7775 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7776 unsigned long flags;
7777
e7d841ca
CW		 7778 /* NB: An MMIO update of the plane base pointer will also
7779 * generate a page-flip completion irq, i.e. every modeset
7780 * is also accompanied by a spurious intel_prepare_page_flip().
7781 */
6b95a207 7782 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7783 if (intel_crtc->unpin_work)
7784 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7785 spin_unlock_irqrestore(&dev->event_lock, flags);
7786}
7787
e7d841ca
CW		 7788inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7789{
7790 /* Ensure that the work item is consistent when activating it ... */
7791 smp_wmb();
7792 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7793 /* and that it is marked active as soon as the irq could fire. */
7794 smp_wmb();
7795}
7796
8c9f3aaf
JB		 7797static int intel_gen2_queue_flip(struct drm_device *dev,
7798 struct drm_crtc *crtc,
7799 struct drm_framebuffer *fb,
ed8d1975
KP		 7800 struct drm_i915_gem_object *obj,
7801 uint32_t flags)
8c9f3aaf
JB		 7802{
7803 struct drm_i915_private *dev_priv = dev->dev_private;
7804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7805 u32 flip_mask;
6d90c952 7806 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7807 int ret;
7808
6d90c952 7809 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7810 if (ret)
83d4092b 7811 goto err;
8c9f3aaf 7812
6d90c952 7813 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7814 if (ret)
83d4092b 7815 goto err_unpin;
8c9f3aaf
JB		 7816
7817 /* Can't queue multiple flips, so wait for the previous
7818 * one to finish before executing the next.
7819 */
7820 if (intel_crtc->plane)
7821 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7822 else
7823 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7824 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7825 intel_ring_emit(ring, MI_NOOP);
7826 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7827 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7828 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7829 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7830 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7831
7832 intel_mark_page_flip_active(intel_crtc);
09246732 7833 __intel_ring_advance(ring);
83d4092b
CW		 7834 return 0;
7835
7836err_unpin:
7837 intel_unpin_fb_obj(obj);
7838err:
8c9f3aaf
JB		 7839 return ret;
7840}
7841
7842static int intel_gen3_queue_flip(struct drm_device *dev,
7843 struct drm_crtc *crtc,
7844 struct drm_framebuffer *fb,
ed8d1975
KP		 7845 struct drm_i915_gem_object *obj,
7846 uint32_t flags)
8c9f3aaf
JB		 7847{
7848 struct drm_i915_private *dev_priv = dev->dev_private;
7849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7850 u32 flip_mask;
6d90c952 7851 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7852 int ret;
7853
6d90c952 7854 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7855 if (ret)
83d4092b 7856 goto err;
8c9f3aaf 7857
6d90c952 7858 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7859 if (ret)
83d4092b 7860 goto err_unpin;
8c9f3aaf
JB		 7861
7862 if (intel_crtc->plane)
7863 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7864 else
7865 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7866 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7867 intel_ring_emit(ring, MI_NOOP);
7868 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7869 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7870 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7871 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7872 intel_ring_emit(ring, MI_NOOP);
7873
e7d841ca 7874 intel_mark_page_flip_active(intel_crtc);
09246732 7875 __intel_ring_advance(ring);
83d4092b
CW		 7876 return 0;
7877
7878err_unpin:
7879 intel_unpin_fb_obj(obj);
7880err:
8c9f3aaf
JB		 7881 return ret;
7882}
7883
7884static int intel_gen4_queue_flip(struct drm_device *dev,
7885 struct drm_crtc *crtc,
7886 struct drm_framebuffer *fb,
ed8d1975
KP		 7887 struct drm_i915_gem_object *obj,
7888 uint32_t flags)
8c9f3aaf
JB		 7889{
7890 struct drm_i915_private *dev_priv = dev->dev_private;
7891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7892 uint32_t pf, pipesrc;
6d90c952 7893 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7894 int ret;
7895
6d90c952 7896 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7897 if (ret)
83d4092b 7898 goto err;
8c9f3aaf 7899
6d90c952 7900 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7901 if (ret)
83d4092b 7902 goto err_unpin;
8c9f3aaf
JB		 7903
7904 /* i965+ uses the linear or tiled offsets from the
7905 * Display Registers (which do not change across a page-flip)
7906 * so we need only reprogram the base address.
7907 */
6d90c952
DV		 7908 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7909 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7910 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7911 intel_ring_emit(ring,
f343c5f6 7912 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7913 obj->tiling_mode);
8c9f3aaf
JB		 7914
7915 /* XXX Enabling the panel-fitter across page-flip is so far
7916 * untested on non-native modes, so ignore it for now.
7917 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7918 */
7919 pf = 0;
7920 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7921 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7922
7923 intel_mark_page_flip_active(intel_crtc);
09246732 7924 __intel_ring_advance(ring);
83d4092b
CW		 7925 return 0;
7926
7927err_unpin:
7928 intel_unpin_fb_obj(obj);
7929err:
8c9f3aaf
JB		 7930 return ret;
7931}
7932
7933static int intel_gen6_queue_flip(struct drm_device *dev,
7934 struct drm_crtc *crtc,
7935 struct drm_framebuffer *fb,
ed8d1975
KP		 7936 struct drm_i915_gem_object *obj,
7937 uint32_t flags)
8c9f3aaf
JB		 7938{
7939 struct drm_i915_private *dev_priv = dev->dev_private;
7940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7941 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7942 uint32_t pf, pipesrc;
7943 int ret;
7944
6d90c952 7945 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7946 if (ret)
83d4092b 7947 goto err;
8c9f3aaf 7948
6d90c952 7949 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7950 if (ret)
83d4092b 7951 goto err_unpin;
8c9f3aaf 7952
6d90c952
DV		 7953 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7954 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7955 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7956 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7957
dc257cf1
DV		 7958 /* Contrary to the suggestions in the documentation,
7959 * "Enable Panel Fitter" does not seem to be required when page
7960 * flipping with a non-native mode, and worse causes a normal
7961 * modeset to fail.
7962 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7963 */
7964 pf = 0;
8c9f3aaf 7965 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7966 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7967
7968 intel_mark_page_flip_active(intel_crtc);
09246732 7969 __intel_ring_advance(ring);
83d4092b
CW		 7970 return 0;
7971
7972err_unpin:
7973 intel_unpin_fb_obj(obj);
7974err:
8c9f3aaf
JB		 7975 return ret;
7976}
7977
7c9017e5
JB		 7978static int intel_gen7_queue_flip(struct drm_device *dev,
7979 struct drm_crtc *crtc,
7980 struct drm_framebuffer *fb,
ed8d1975
KP		 7981 struct drm_i915_gem_object *obj,
7982 uint32_t flags)
7c9017e5
JB		 7983{
7984 struct drm_i915_private *dev_priv = dev->dev_private;
7985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7986 struct intel_ring_buffer *ring;
cb05d8de 7987 uint32_t plane_bit = 0;
ffe74d75
CW		 7988 int len, ret;
7989
7990 ring = obj->ring;
7991 if (ring == NULL || ring->id != RCS)
7992 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7993
7994 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7995 if (ret)
83d4092b 7996 goto err;
7c9017e5 7997
cb05d8de
DV		 7998 switch(intel_crtc->plane) {
7999 case PLANE_A:
8000 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8001 break;
8002 case PLANE_B:
8003 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8004 break;
8005 case PLANE_C:
8006 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8007 break;
8008 default:
8009 WARN_ONCE(1, "unknown plane in flip command\n");
8010 ret = -ENODEV;
ab3951eb 8011 goto err_unpin;
cb05d8de
DV		 8012 }
8013
ffe74d75
CW		 8014 len = 4;
8015 if (ring->id == RCS)
8016 len += 6;
8017
8018 ret = intel_ring_begin(ring, len);
7c9017e5 8019 if (ret)
83d4092b 8020 goto err_unpin;
7c9017e5 8021
ffe74d75
CW		 8022 /* Unmask the flip-done completion message. Note that the bspec says that
8023 * we should do this for both the BCS and RCS, and that we must not unmask
8024 * more than one flip event at any time (or ensure that one flip message
8025 * can be sent by waiting for flip-done prior to queueing new flips).
8026 * Experimentation says that BCS works despite DERRMR masking all
8027 * flip-done completion events and that unmasking all planes at once
8028 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8029 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8030 */
8031 if (ring->id == RCS) {
8032 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8033 intel_ring_emit(ring, DERRMR);
8034 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8035 DERRMR_PIPEB_PRI_FLIP_DONE |
8036 DERRMR_PIPEC_PRI_FLIP_DONE));
8037 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8038 intel_ring_emit(ring, DERRMR);
8039 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8040 }
8041
cb05d8de 8042 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8043 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8044 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8045 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8046
8047 intel_mark_page_flip_active(intel_crtc);
09246732 8048 __intel_ring_advance(ring);
83d4092b
CW		 8049 return 0;
8050
8051err_unpin:
8052 intel_unpin_fb_obj(obj);
8053err:
7c9017e5
JB		 8054 return ret;
8055}
8056
8c9f3aaf
JB		 8057static int intel_default_queue_flip(struct drm_device *dev,
8058 struct drm_crtc *crtc,
8059 struct drm_framebuffer *fb,
ed8d1975
KP		 8060 struct drm_i915_gem_object *obj,
8061 uint32_t flags)
8c9f3aaf
JB		 8062{
8063 return -ENODEV;
8064}
8065
6b95a207
KH		 8066static int intel_crtc_page_flip(struct drm_crtc *crtc,
8067 struct drm_framebuffer *fb,
ed8d1975
KP		 8068 struct drm_pending_vblank_event *event,
8069 uint32_t page_flip_flags)
6b95a207
KH		 8070{
8071 struct drm_device *dev = crtc->dev;
8072 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8073 struct drm_framebuffer *old_fb = crtc->fb;
8074 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8076 struct intel_unpin_work *work;
8c9f3aaf 8077 unsigned long flags;
52e68630 8078 int ret;
6b95a207 8079
e6a595d2
VS		 8080 /* Can't change pixel format via MI display flips. */
8081 if (fb->pixel_format != crtc->fb->pixel_format)
8082 return -EINVAL;
8083
8084 /*
8085 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8086 * Note that pitch changes could also affect these register.
8087 */
8088 if (INTEL_INFO(dev)->gen > 3 &&
8089 (fb->offsets[0] != crtc->fb->offsets[0] ||
8090 fb->pitches[0] != crtc->fb->pitches[0]))
8091 return -EINVAL;
8092
6b95a207
KH		 8093 work = kzalloc(sizeof *work, GFP_KERNEL);
8094 if (work == NULL)
8095 return -ENOMEM;
8096
6b95a207 8097 work->event = event;
b4a98e57 8098 work->crtc = crtc;
4a35f83b 8099 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8100 INIT_WORK(&work->work, intel_unpin_work_fn);
8101
7317c75e
JB		 8102 ret = drm_vblank_get(dev, intel_crtc->pipe);
8103 if (ret)
8104 goto free_work;
8105
6b95a207
KH		 8106 /* We borrow the event spin lock for protecting unpin_work */
8107 spin_lock_irqsave(&dev->event_lock, flags);
8108 if (intel_crtc->unpin_work) {
8109 spin_unlock_irqrestore(&dev->event_lock, flags);
8110 kfree(work);
7317c75e 8111 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8112
8113 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8114 return -EBUSY;
8115 }
8116 intel_crtc->unpin_work = work;
8117 spin_unlock_irqrestore(&dev->event_lock, flags);
8118
b4a98e57
CW		 8119 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8120 flush_workqueue(dev_priv->wq);
8121
79158103
CW		 8122 ret = i915_mutex_lock_interruptible(dev);
8123 if (ret)
8124 goto cleanup;
6b95a207 8125
75dfca80 8126 /* Reference the objects for the scheduled work. */
05394f39
CW		 8127 drm_gem_object_reference(&work->old_fb_obj->base);
8128 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8129
8130 crtc->fb = fb;
96b099fd 8131
e1f99ce6 8132 work->pending_flip_obj = obj;
e1f99ce6 8133
4e5359cd
SF		 8134 work->enable_stall_check = true;
8135
b4a98e57 8136 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8137 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8138
ed8d1975 8139 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8140 if (ret)
8141 goto cleanup_pending;
6b95a207 8142
7782de3b 8143 intel_disable_fbc(dev);
c65355bb 8144 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8145 mutex_unlock(&dev->struct_mutex);
8146
e5510fac
JB		 8147 trace_i915_flip_request(intel_crtc->plane, obj);
8148
6b95a207 8149 return 0;
96b099fd 8150
8c9f3aaf 8151cleanup_pending:
b4a98e57 8152 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8153 crtc->fb = old_fb;
05394f39
CW		 8154 drm_gem_object_unreference(&work->old_fb_obj->base);
8155 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8156 mutex_unlock(&dev->struct_mutex);
8157
79158103 8158cleanup:
96b099fd
CW		 8159 spin_lock_irqsave(&dev->event_lock, flags);
8160 intel_crtc->unpin_work = NULL;
8161 spin_unlock_irqrestore(&dev->event_lock, flags);
8162
7317c75e
JB		 8163 drm_vblank_put(dev, intel_crtc->pipe);
8164free_work:
96b099fd
CW		 8165 kfree(work);
8166
8167 return ret;
6b95a207
KH		 8168}
8169
f6e5b160 8170static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8171 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8172 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8173};
8174
50f56119
DV		 8175static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8176 struct drm_crtc *crtc)
8177{
8178 struct drm_device *dev;
8179 struct drm_crtc *tmp;
8180 int crtc_mask = 1;
47f1c6c9 8181
50f56119 8182 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8183
50f56119 8184 dev = crtc->dev;
47f1c6c9 8185
50f56119
DV		 8186 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8187 if (tmp == crtc)
8188 break;
8189 crtc_mask <<= 1;
8190 }
47f1c6c9 8191
50f56119
DV		 8192 if (encoder->possible_crtcs & crtc_mask)
8193 return true;
8194 return false;
47f1c6c9 8195}
79e53945 8196
9a935856
DV		 8197/**
8198 * intel_modeset_update_staged_output_state
8199 *
8200 * Updates the staged output configuration state, e.g. after we've read out the
8201 * current hw state.
8202 */
8203static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8204{
9a935856
DV		 8205 struct intel_encoder *encoder;
8206 struct intel_connector *connector;
f6e5b160 8207
9a935856
DV		 8208 list_for_each_entry(connector, &dev->mode_config.connector_list,
8209 base.head) {
8210 connector->new_encoder =
8211 to_intel_encoder(connector->base.encoder);
8212 }
f6e5b160 8213
9a935856
DV		 8214 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8215 base.head) {
8216 encoder->new_crtc =
8217 to_intel_crtc(encoder->base.crtc);
8218 }
f6e5b160
CW		 8219}
8220
9a935856
DV		 8221/**
8222 * intel_modeset_commit_output_state
8223 *
8224 * This function copies the stage display pipe configuration to the real one.
8225 */
8226static void intel_modeset_commit_output_state(struct drm_device *dev)
8227{
8228 struct intel_encoder *encoder;
8229 struct intel_connector *connector;
f6e5b160 8230
9a935856
DV		 8231 list_for_each_entry(connector, &dev->mode_config.connector_list,
8232 base.head) {
8233 connector->base.encoder = &connector->new_encoder->base;
8234 }
f6e5b160 8235
9a935856
DV		 8236 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8237 base.head) {
8238 encoder->base.crtc = &encoder->new_crtc->base;
8239 }
8240}
8241
050f7aeb
DV		 8242static void
8243connected_sink_compute_bpp(struct intel_connector * connector,
8244 struct intel_crtc_config *pipe_config)
8245{
8246 int bpp = pipe_config->pipe_bpp;
8247
8248 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8249 connector->base.base.id,
8250 drm_get_connector_name(&connector->base));
8251
8252 /* Don't use an invalid EDID bpc value */
8253 if (connector->base.display_info.bpc &&
8254 connector->base.display_info.bpc * 3 < bpp) {
8255 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8256 bpp, connector->base.display_info.bpc*3);
8257 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8258 }
8259
8260 /* Clamp bpp to 8 on screens without EDID 1.4 */
8261 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8262 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8263 bpp);
8264 pipe_config->pipe_bpp = 24;
8265 }
8266}
8267
4e53c2e0 8268static int
050f7aeb
DV		 8269compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8270 struct drm_framebuffer *fb,
8271 struct intel_crtc_config *pipe_config)
4e53c2e0 8272{
050f7aeb
DV		 8273 struct drm_device *dev = crtc->base.dev;
8274 struct intel_connector *connector;
4e53c2e0
DV		 8275 int bpp;
8276
d42264b1
DV		 8277 switch (fb->pixel_format) {
8278 case DRM_FORMAT_C8:
4e53c2e0
DV		 8279 bpp = 8*3; /* since we go through a colormap */
8280 break;
d42264b1
DV		 8281 case DRM_FORMAT_XRGB1555:
8282 case DRM_FORMAT_ARGB1555:
8283 /* checked in intel_framebuffer_init already */
8284 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8285 return -EINVAL;
8286 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8287 bpp = 6*3; /* min is 18bpp */
8288 break;
d42264b1
DV		 8289 case DRM_FORMAT_XBGR8888:
8290 case DRM_FORMAT_ABGR8888:
8291 /* checked in intel_framebuffer_init already */
8292 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8293 return -EINVAL;
8294 case DRM_FORMAT_XRGB8888:
8295 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8296 bpp = 8*3;
8297 break;
d42264b1
DV		 8298 case DRM_FORMAT_XRGB2101010:
8299 case DRM_FORMAT_ARGB2101010:
8300 case DRM_FORMAT_XBGR2101010:
8301 case DRM_FORMAT_ABGR2101010:
8302 /* checked in intel_framebuffer_init already */
8303 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8304 return -EINVAL;
4e53c2e0
DV		 8305 bpp = 10*3;
8306 break;
baba133a 8307 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8308 default:
8309 DRM_DEBUG_KMS("unsupported depth\n");
8310 return -EINVAL;
8311 }
8312
4e53c2e0
DV		 8313 pipe_config->pipe_bpp = bpp;
8314
8315 /* Clamp display bpp to EDID value */
8316 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8317 base.head) {
1b829e05
DV		 8318 if (!connector->new_encoder ||
8319 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8320 continue;
8321
050f7aeb 8322 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8323 }
8324
8325 return bpp;
8326}
8327
c0b03411
DV		 8328static void intel_dump_pipe_config(struct intel_crtc *crtc,
8329 struct intel_crtc_config *pipe_config,
8330 const char *context)
8331{
8332 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8333 context, pipe_name(crtc->pipe));
8334
8335 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8336 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8337 pipe_config->pipe_bpp, pipe_config->dither);
8338 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8339 pipe_config->has_pch_encoder,
8340 pipe_config->fdi_lanes,
8341 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8342 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8343 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8344 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8345 pipe_config->has_dp_encoder,
8346 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8347 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8348 pipe_config->dp_m_n.tu);
c0b03411
DV		 8349 DRM_DEBUG_KMS("requested mode:\n");
8350 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8351 DRM_DEBUG_KMS("adjusted mode:\n");
8352 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
d71b8d4a 8353 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8354 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8355 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8356 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8357 pipe_config->gmch_pfit.control,
8358 pipe_config->gmch_pfit.pgm_ratios,
8359 pipe_config->gmch_pfit.lvds_border_bits);
8360 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8361 pipe_config->pch_pfit.pos,
8362 pipe_config->pch_pfit.size);
42db64ef 8363 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8364}
8365
accfc0c5
DV		 8366static bool check_encoder_cloning(struct drm_crtc *crtc)
8367{
8368 int num_encoders = 0;
8369 bool uncloneable_encoders = false;
8370 struct intel_encoder *encoder;
8371
8372 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8373 base.head) {
8374 if (&encoder->new_crtc->base != crtc)
8375 continue;
8376
8377 num_encoders++;
8378 if (!encoder->cloneable)
8379 uncloneable_encoders = true;
8380 }
8381
8382 return !(num_encoders > 1 && uncloneable_encoders);
8383}
8384
b8cecdf5
DV		 8385static struct intel_crtc_config *
8386intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8387 struct drm_framebuffer *fb,
b8cecdf5 8388 struct drm_display_mode *mode)
ee7b9f93 8389{
7758a113 8390 struct drm_device *dev = crtc->dev;
7758a113 8391 struct intel_encoder *encoder;
b8cecdf5 8392 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8393 int plane_bpp, ret = -EINVAL;
8394 bool retry = true;
ee7b9f93 8395
accfc0c5
DV		 8396 if (!check_encoder_cloning(crtc)) {
8397 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8398 return ERR_PTR(-EINVAL);
8399 }
8400
b8cecdf5
DV		 8401 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8402 if (!pipe_config)
7758a113
DV		 8403 return ERR_PTR(-ENOMEM);
8404
b8cecdf5
DV		 8405 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8406 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd
VS		 8407
8408 pipe_config->pipe_src_w = mode->hdisplay;
8409 pipe_config->pipe_src_h = mode->vdisplay;
8410
e143a21c
DV		 8411 pipe_config->cpu_transcoder =
8412 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8413 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8414
2960bc9c
ID		 8415 /*
8416 * Sanitize sync polarity flags based on requested ones. If neither
8417 * positive or negative polarity is requested, treat this as meaning
8418 * negative polarity.
8419 */
8420 if (!(pipe_config->adjusted_mode.flags &
8421 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8422 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8423
8424 if (!(pipe_config->adjusted_mode.flags &
8425 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8426 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8427
050f7aeb
DV		 8428 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8429 * plane pixel format and any sink constraints into account. Returns the
8430 * source plane bpp so that dithering can be selected on mismatches
8431 * after encoders and crtc also have had their say. */
8432 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8433 fb, pipe_config);
4e53c2e0
DV		 8434 if (plane_bpp < 0)
8435 goto fail;
8436
e29c22c0 8437encoder_retry:
ef1b460d 8438 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8439 pipe_config->port_clock = 0;
ef1b460d 8440 pipe_config->pixel_multiplier = 1;
ff9a6750 8441
135c81b8
DV		 8442 /* Fill in default crtc timings, allow encoders to overwrite them. */
8443 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8444
7758a113
DV		 8445 /* Pass our mode to the connectors and the CRTC to give them a chance to
8446 * adjust it according to limitations or connector properties, and also
8447 * a chance to reject the mode entirely.
47f1c6c9 8448 */
7758a113
DV		 8449 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8450 base.head) {
47f1c6c9 8451
7758a113
DV		 8452 if (&encoder->new_crtc->base != crtc)
8453 continue;
7ae89233 8454
efea6e8e
DV		 8455 if (!(encoder->compute_config(encoder, pipe_config))) {
8456 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8457 goto fail;
8458 }
ee7b9f93 8459 }
47f1c6c9 8460
ff9a6750
DV		 8461 /* Set default port clock if not overwritten by the encoder. Needs to be
8462 * done afterwards in case the encoder adjusts the mode. */
8463 if (!pipe_config->port_clock)
3c52f4eb
VS		 8464 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8465 pipe_config->pixel_multiplier;
ff9a6750 8466
a43f6e0f 8467 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8468 if (ret < 0) {
7758a113
DV		 8469 DRM_DEBUG_KMS("CRTC fixup failed\n");
8470 goto fail;
ee7b9f93 8471 }
e29c22c0
DV		 8472
8473 if (ret == RETRY) {
8474 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8475 ret = -EINVAL;
8476 goto fail;
8477 }
8478
8479 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8480 retry = false;
8481 goto encoder_retry;
8482 }
8483
4e53c2e0
DV		 8484 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8485 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8486 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8487
b8cecdf5 8488 return pipe_config;
7758a113 8489fail:
b8cecdf5 8490 kfree(pipe_config);
e29c22c0 8491 return ERR_PTR(ret);
ee7b9f93 8492}
47f1c6c9 8493
e2e1ed41
DV		 8494/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8495 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8496static void
8497intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8498 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8499{
8500 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8501 struct drm_device *dev = crtc->dev;
8502 struct intel_encoder *encoder;
8503 struct intel_connector *connector;
8504 struct drm_crtc *tmp_crtc;
79e53945 8505
e2e1ed41 8506 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8507
e2e1ed41
DV		 8508 /* Check which crtcs have changed outputs connected to them, these need
8509 * to be part of the prepare_pipes mask. We don't (yet) support global
8510 * modeset across multiple crtcs, so modeset_pipes will only have one
8511 * bit set at most. */
8512 list_for_each_entry(connector, &dev->mode_config.connector_list,
8513 base.head) {
8514 if (connector->base.encoder == &connector->new_encoder->base)
8515 continue;
79e53945 8516
e2e1ed41
DV		 8517 if (connector->base.encoder) {
8518 tmp_crtc = connector->base.encoder->crtc;
8519
8520 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8521 }
8522
8523 if (connector->new_encoder)
8524 *prepare_pipes |=
8525 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8526 }
8527
e2e1ed41
DV		 8528 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8529 base.head) {
8530 if (encoder->base.crtc == &encoder->new_crtc->base)
8531 continue;
8532
8533 if (encoder->base.crtc) {
8534 tmp_crtc = encoder->base.crtc;
8535
8536 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8537 }
8538
8539 if (encoder->new_crtc)
8540 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8541 }
8542
e2e1ed41
DV		 8543 /* Check for any pipes that will be fully disabled ... */
8544 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8545 base.head) {
8546 bool used = false;
22fd0fab 8547
e2e1ed41
DV		 8548 /* Don't try to disable disabled crtcs. */
8549 if (!intel_crtc->base.enabled)
8550 continue;
7e7d76c3 8551
e2e1ed41
DV		 8552 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8553 base.head) {
8554 if (encoder->new_crtc == intel_crtc)
8555 used = true;
8556 }
8557
8558 if (!used)
8559 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8560 }
8561
e2e1ed41
DV		 8562
8563 /* set_mode is also used to update properties on life display pipes. */
8564 intel_crtc = to_intel_crtc(crtc);
8565 if (crtc->enabled)
8566 *prepare_pipes |= 1 << intel_crtc->pipe;
8567
b6c5164d
DV		 8568 /*
8569 * For simplicity do a full modeset on any pipe where the output routing
8570 * changed. We could be more clever, but that would require us to be
8571 * more careful with calling the relevant encoder->mode_set functions.
8572 */
e2e1ed41
DV		 8573 if (*prepare_pipes)
8574 *modeset_pipes = *prepare_pipes;
8575
8576 /* ... and mask these out. */
8577 *modeset_pipes &= ~(*disable_pipes);
8578 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8579
8580 /*
8581 * HACK: We don't (yet) fully support global modesets. intel_set_config
8582 * obies this rule, but the modeset restore mode of
8583 * intel_modeset_setup_hw_state does not.
8584 */
8585 *modeset_pipes &= 1 << intel_crtc->pipe;
8586 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8587
8588 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8589 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8590}
79e53945 8591
ea9d758d 8592static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8593{
ea9d758d 8594 struct drm_encoder *encoder;
f6e5b160 8595 struct drm_device *dev = crtc->dev;
f6e5b160 8596
ea9d758d
DV		 8597 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8598 if (encoder->crtc == crtc)
8599 return true;
8600
8601 return false;
8602}
8603
8604static void
8605intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8606{
8607 struct intel_encoder *intel_encoder;
8608 struct intel_crtc *intel_crtc;
8609 struct drm_connector *connector;
8610
8611 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8612 base.head) {
8613 if (!intel_encoder->base.crtc)
8614 continue;
8615
8616 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8617
8618 if (prepare_pipes & (1 << intel_crtc->pipe))
8619 intel_encoder->connectors_active = false;
8620 }
8621
8622 intel_modeset_commit_output_state(dev);
8623
8624 /* Update computed state. */
8625 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8626 base.head) {
8627 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8628 }
8629
8630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8631 if (!connector->encoder || !connector->encoder->crtc)
8632 continue;
8633
8634 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8635
8636 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8637 struct drm_property *dpms_property =
8638 dev->mode_config.dpms_property;
8639
ea9d758d 8640 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8641 drm_object_property_set_value(&connector->base,
68d34720
DV		 8642 dpms_property,
8643 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8644
8645 intel_encoder = to_intel_encoder(connector->encoder);
8646 intel_encoder->connectors_active = true;
8647 }
8648 }
8649
8650}
8651
3bd26263 8652static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8653{
3bd26263 8654 int diff;
f1f644dc
JB		 8655
8656 if (clock1 == clock2)
8657 return true;
8658
8659 if (!clock1 || !clock2)
8660 return false;
8661
8662 diff = abs(clock1 - clock2);
8663
8664 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8665 return true;
8666
8667 return false;
8668}
8669
25c5b266
DV		 8670#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8671 list_for_each_entry((intel_crtc), \
8672 &(dev)->mode_config.crtc_list, \
8673 base.head) \
0973f18f 8674 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8675
0e8ffe1b 8676static bool
2fa2fe9a
DV		 8677intel_pipe_config_compare(struct drm_device *dev,
8678 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8679 struct intel_crtc_config *pipe_config)
8680{
66e985c0
DV		 8681#define PIPE_CONF_CHECK_X(name) \
8682 if (current_config->name != pipe_config->name) { \
8683 DRM_ERROR("mismatch in " #name " " \
8684 "(expected 0x%08x, found 0x%08x)\n", \
8685 current_config->name, \
8686 pipe_config->name); \
8687 return false; \
8688 }
8689
08a24034
DV		 8690#define PIPE_CONF_CHECK_I(name) \
8691 if (current_config->name != pipe_config->name) { \
8692 DRM_ERROR("mismatch in " #name " " \
8693 "(expected %i, found %i)\n", \
8694 current_config->name, \
8695 pipe_config->name); \
8696 return false; \
88adfff1
DV		 8697 }
8698
1bd1bd80
DV		 8699#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8700 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8701 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8702 "(expected %i, found %i)\n", \
8703 current_config->name & (mask), \
8704 pipe_config->name & (mask)); \
8705 return false; \
8706 }
8707
5e550656
VS		 8708#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8709 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8710 DRM_ERROR("mismatch in " #name " " \
8711 "(expected %i, found %i)\n", \
8712 current_config->name, \
8713 pipe_config->name); \
8714 return false; \
8715 }
8716
bb760063
DV		 8717#define PIPE_CONF_QUIRK(quirk) \
8718 ((current_config->quirks | pipe_config->quirks) & (quirk))
8719
eccb140b
DV		 8720 PIPE_CONF_CHECK_I(cpu_transcoder);
8721
08a24034
DV		 8722 PIPE_CONF_CHECK_I(has_pch_encoder);
8723 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8724 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8725 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8726 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8727 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8728 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8729
eb14cb74
VS		 8730 PIPE_CONF_CHECK_I(has_dp_encoder);
8731 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8732 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8733 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8734 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8735 PIPE_CONF_CHECK_I(dp_m_n.tu);
8736
1bd1bd80
DV		 8737 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8738 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8739 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8740 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8741 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8742 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8743
8744 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8745 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8746 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8747 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8748 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8749 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8750
c93f54cf 8751 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8752
1bd1bd80
DV		 8753 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8754 DRM_MODE_FLAG_INTERLACE);
8755
bb760063
DV		 8756 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8757 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8758 DRM_MODE_FLAG_PHSYNC);
8759 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8760 DRM_MODE_FLAG_NHSYNC);
8761 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8762 DRM_MODE_FLAG_PVSYNC);
8763 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8764 DRM_MODE_FLAG_NVSYNC);
8765 }
045ac3b5 8766
37327abd
VS		 8767 PIPE_CONF_CHECK_I(pipe_src_w);
8768 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8769
2fa2fe9a
DV		 8770 PIPE_CONF_CHECK_I(gmch_pfit.control);
8771 /* pfit ratios are autocomputed by the hw on gen4+ */
8772 if (INTEL_INFO(dev)->gen < 4)
8773 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8774 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8775 PIPE_CONF_CHECK_I(pch_pfit.pos);
8776 PIPE_CONF_CHECK_I(pch_pfit.size);
8777
42db64ef
PZ		 8778 PIPE_CONF_CHECK_I(ips_enabled);
8779
c0d43d62 8780 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8781 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8782 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8783 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8784 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8785
42571aef
VS		 8786 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8787 PIPE_CONF_CHECK_I(pipe_bpp);
8788
d71b8d4a 8789 if (!IS_HASWELL(dev)) {
5e550656 8790 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
d71b8d4a
VS		 8791 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8792 }
5e550656 8793
66e985c0 8794#undef PIPE_CONF_CHECK_X
08a24034 8795#undef PIPE_CONF_CHECK_I
1bd1bd80 8796#undef PIPE_CONF_CHECK_FLAGS
5e550656 8797#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8798#undef PIPE_CONF_QUIRK
88adfff1 8799
0e8ffe1b
DV		 8800 return true;
8801}
8802
91d1b4bd
DV		 8803static void
8804check_connector_state(struct drm_device *dev)
8af6cf88 8805{
8af6cf88
DV		 8806 struct intel_connector *connector;
8807
8808 list_for_each_entry(connector, &dev->mode_config.connector_list,
8809 base.head) {
8810 /* This also checks the encoder/connector hw state with the
8811 * ->get_hw_state callbacks. */
8812 intel_connector_check_state(connector);
8813
8814 WARN(&connector->new_encoder->base != connector->base.encoder,
8815 "connector's staged encoder doesn't match current encoder\n");
8816 }
91d1b4bd
DV		 8817}
8818
8819static void
8820check_encoder_state(struct drm_device *dev)
8821{
8822 struct intel_encoder *encoder;
8823 struct intel_connector *connector;
8af6cf88
DV		 8824
8825 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8826 base.head) {
8827 bool enabled = false;
8828 bool active = false;
8829 enum pipe pipe, tracked_pipe;
8830
8831 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8832 encoder->base.base.id,
8833 drm_get_encoder_name(&encoder->base));
8834
8835 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8836 "encoder's stage crtc doesn't match current crtc\n");
8837 WARN(encoder->connectors_active && !encoder->base.crtc,
8838 "encoder's active_connectors set, but no crtc\n");
8839
8840 list_for_each_entry(connector, &dev->mode_config.connector_list,
8841 base.head) {
8842 if (connector->base.encoder != &encoder->base)
8843 continue;
8844 enabled = true;
8845 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8846 active = true;
8847 }
8848 WARN(!!encoder->base.crtc != enabled,
8849 "encoder's enabled state mismatch "
8850 "(expected %i, found %i)\n",
8851 !!encoder->base.crtc, enabled);
8852 WARN(active && !encoder->base.crtc,
8853 "active encoder with no crtc\n");
8854
8855 WARN(encoder->connectors_active != active,
8856 "encoder's computed active state doesn't match tracked active state "
8857 "(expected %i, found %i)\n", active, encoder->connectors_active);
8858
8859 active = encoder->get_hw_state(encoder, &pipe);
8860 WARN(active != encoder->connectors_active,
8861 "encoder's hw state doesn't match sw tracking "
8862 "(expected %i, found %i)\n",
8863 encoder->connectors_active, active);
8864
8865 if (!encoder->base.crtc)
8866 continue;
8867
8868 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8869 WARN(active && pipe != tracked_pipe,
8870 "active encoder's pipe doesn't match"
8871 "(expected %i, found %i)\n",
8872 tracked_pipe, pipe);
8873
8874 }
91d1b4bd
DV		 8875}
8876
8877static void
8878check_crtc_state(struct drm_device *dev)
8879{
8880 drm_i915_private_t *dev_priv = dev->dev_private;
8881 struct intel_crtc *crtc;
8882 struct intel_encoder *encoder;
8883 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8884
8885 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8886 base.head) {
8887 bool enabled = false;
8888 bool active = false;
8889
045ac3b5
JB		 8890 memset(&pipe_config, 0, sizeof(pipe_config));
8891
8af6cf88
DV		 8892 DRM_DEBUG_KMS("[CRTC:%d]\n",
8893 crtc->base.base.id);
8894
8895 WARN(crtc->active && !crtc->base.enabled,
8896 "active crtc, but not enabled in sw tracking\n");
8897
8898 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8899 base.head) {
8900 if (encoder->base.crtc != &crtc->base)
8901 continue;
8902 enabled = true;
8903 if (encoder->connectors_active)
8904 active = true;
8905 }
6c49f241 8906
8af6cf88
DV		 8907 WARN(active != crtc->active,
8908 "crtc's computed active state doesn't match tracked active state "
8909 "(expected %i, found %i)\n", active, crtc->active);
8910 WARN(enabled != crtc->base.enabled,
8911 "crtc's computed enabled state doesn't match tracked enabled state "
8912 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8913
0e8ffe1b
DV		 8914 active = dev_priv->display.get_pipe_config(crtc,
8915 &pipe_config);
d62cf62a
DV		 8916
8917 /* hw state is inconsistent with the pipe A quirk */
8918 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8919 active = crtc->active;
8920
6c49f241
DV		 8921 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8922 base.head) {
3eaba51c 8923 enum pipe pipe;
6c49f241
DV		 8924 if (encoder->base.crtc != &crtc->base)
8925 continue;
3eaba51c
VS		 8926 if (encoder->get_config &&
8927 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8928 encoder->get_config(encoder, &pipe_config);
8929 }
8930
0e8ffe1b
DV		 8931 WARN(crtc->active != active,
8932 "crtc active state doesn't match with hw state "
8933 "(expected %i, found %i)\n", crtc->active, active);
8934
c0b03411
DV		 8935 if (active &&
8936 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8937 WARN(1, "pipe state doesn't match!\n");
8938 intel_dump_pipe_config(crtc, &pipe_config,
8939 "[hw state]");
8940 intel_dump_pipe_config(crtc, &crtc->config,
8941 "[sw state]");
8942 }
8af6cf88
DV		 8943 }
8944}
8945
91d1b4bd
DV		 8946static void
8947check_shared_dpll_state(struct drm_device *dev)
8948{
8949 drm_i915_private_t *dev_priv = dev->dev_private;
8950 struct intel_crtc *crtc;
8951 struct intel_dpll_hw_state dpll_hw_state;
8952 int i;
5358901f
DV		 8953
8954 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8955 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8956 int enabled_crtcs = 0, active_crtcs = 0;
8957 bool active;
8958
8959 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8960
8961 DRM_DEBUG_KMS("%s\n", pll->name);
8962
8963 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8964
8965 WARN(pll->active > pll->refcount,
8966 "more active pll users than references: %i vs %i\n",
8967 pll->active, pll->refcount);
8968 WARN(pll->active && !pll->on,
8969 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8970 WARN(pll->on && !pll->active,
8971 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8972 WARN(pll->on != active,
8973 "pll on state mismatch (expected %i, found %i)\n",
8974 pll->on, active);
8975
8976 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8977 base.head) {
8978 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8979 enabled_crtcs++;
8980 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8981 active_crtcs++;
8982 }
8983 WARN(pll->active != active_crtcs,
8984 "pll active crtcs mismatch (expected %i, found %i)\n",
8985 pll->active, active_crtcs);
8986 WARN(pll->refcount != enabled_crtcs,
8987 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8988 pll->refcount, enabled_crtcs);
66e985c0
DV		 8989
8990 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8991 sizeof(dpll_hw_state)),
8992 "pll hw state mismatch\n");
5358901f 8993 }
8af6cf88
DV		 8994}
8995
91d1b4bd
DV		 8996void
8997intel_modeset_check_state(struct drm_device *dev)
8998{
8999 check_connector_state(dev);
9000 check_encoder_state(dev);
9001 check_crtc_state(dev);
9002 check_shared_dpll_state(dev);
9003}
9004
18442d08
VS		 9005void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9006 int dotclock)
9007{
9008 /*
9009 * FDI already provided one idea for the dotclock.
9010 * Yell if the encoder disagrees.
9011 */
9012 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9013 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9014 pipe_config->adjusted_mode.clock, dotclock);
9015}
9016
f30da187
DV		 9017static int __intel_set_mode(struct drm_crtc *crtc,
9018 struct drm_display_mode *mode,
9019 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9020{
9021 struct drm_device *dev = crtc->dev;
dbf2b54e 9022 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9023 struct drm_display_mode *saved_mode, *saved_hwmode;
9024 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9025 struct intel_crtc *intel_crtc;
9026 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9027 int ret = 0;
a6778b3c 9028
3ac18232 9029 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9030 if (!saved_mode)
9031 return -ENOMEM;
3ac18232 9032 saved_hwmode = saved_mode + 1;
a6778b3c 9033
e2e1ed41 9034 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9035 &prepare_pipes, &disable_pipes);
9036
3ac18232
TG		 9037 *saved_hwmode = crtc->hwmode;
9038 *saved_mode = crtc->mode;
a6778b3c 9039
25c5b266
DV		 9040 /* Hack: Because we don't (yet) support global modeset on multiple
9041 * crtcs, we don't keep track of the new mode for more than one crtc.
9042 * Hence simply check whether any bit is set in modeset_pipes in all the
9043 * pieces of code that are not yet converted to deal with mutliple crtcs
9044 * changing their mode at the same time. */
25c5b266 9045 if (modeset_pipes) {
4e53c2e0 9046 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9047 if (IS_ERR(pipe_config)) {
9048 ret = PTR_ERR(pipe_config);
9049 pipe_config = NULL;
9050
3ac18232 9051 goto out;
25c5b266 9052 }
c0b03411
DV		 9053 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9054 "[modeset]");
25c5b266 9055 }
a6778b3c 9056
460da916
DV		 9057 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9058 intel_crtc_disable(&intel_crtc->base);
9059
ea9d758d
DV		 9060 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9061 if (intel_crtc->base.enabled)
9062 dev_priv->display.crtc_disable(&intel_crtc->base);
9063 }
a6778b3c 9064
6c4c86f5
DV		 9065 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9066 * to set it here already despite that we pass it down the callchain.
f6e5b160 9067 */
b8cecdf5 9068 if (modeset_pipes) {
25c5b266 9069 crtc->mode = *mode;
b8cecdf5
DV		 9070 /* mode_set/enable/disable functions rely on a correct pipe
9071 * config. */
9072 to_intel_crtc(crtc)->config = *pipe_config;
9073 }
7758a113 9074
ea9d758d
DV		 9075 /* Only after disabling all output pipelines that will be changed can we
9076 * update the the output configuration. */
9077 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9078
47fab737
DV		 9079 if (dev_priv->display.modeset_global_resources)
9080 dev_priv->display.modeset_global_resources(dev);
9081
a6778b3c
DV		 9082 /* Set up the DPLL and any encoders state that needs to adjust or depend
9083 * on the DPLL.
f6e5b160 9084 */
25c5b266 9085 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9086 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9087 x, y, fb);
9088 if (ret)
9089 goto done;
a6778b3c
DV		 9090 }
9091
9092 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9093 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9094 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9095
25c5b266
DV		 9096 if (modeset_pipes) {
9097 /* Store real post-adjustment hardware mode. */
b8cecdf5 9098 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9099
25c5b266
DV		 9100 /* Calculate and store various constants which
9101 * are later needed by vblank and swap-completion
9102 * timestamping. They are derived from true hwmode.
9103 */
9104 drm_calc_timestamping_constants(crtc);
9105 }
a6778b3c
DV		 9106
9107 /* FIXME: add subpixel order */
9108done:
c0c36b94 9109 if (ret && crtc->enabled) {
3ac18232
TG		 9110 crtc->hwmode = *saved_hwmode;
9111 crtc->mode = *saved_mode;
a6778b3c
DV		 9112 }
9113
3ac18232 9114out:
b8cecdf5 9115 kfree(pipe_config);
3ac18232 9116 kfree(saved_mode);
a6778b3c 9117 return ret;
f6e5b160
CW		 9118}
9119
e7457a9a
DL		 9120static int intel_set_mode(struct drm_crtc *crtc,
9121 struct drm_display_mode *mode,
9122 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9123{
9124 int ret;
9125
9126 ret = __intel_set_mode(crtc, mode, x, y, fb);
9127
9128 if (ret == 0)
9129 intel_modeset_check_state(crtc->dev);
9130
9131 return ret;
9132}
9133
c0c36b94
CW		 9134void intel_crtc_restore_mode(struct drm_crtc *crtc)
9135{
9136 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9137}
9138
25c5b266
DV		 9139#undef for_each_intel_crtc_masked
9140
d9e55608
DV		 9141static void intel_set_config_free(struct intel_set_config *config)
9142{
9143 if (!config)
9144 return;
9145
1aa4b628
DV		 9146 kfree(config->save_connector_encoders);
9147 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9148 kfree(config);
9149}
9150
85f9eb71
DV		 9151static int intel_set_config_save_state(struct drm_device *dev,
9152 struct intel_set_config *config)
9153{
85f9eb71
DV		 9154 struct drm_encoder *encoder;
9155 struct drm_connector *connector;
9156 int count;
9157
1aa4b628
DV		 9158 config->save_encoder_crtcs =
9159 kcalloc(dev->mode_config.num_encoder,
9160 sizeof(struct drm_crtc *), GFP_KERNEL);
9161 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9162 return -ENOMEM;
9163
1aa4b628
DV		 9164 config->save_connector_encoders =
9165 kcalloc(dev->mode_config.num_connector,
9166 sizeof(struct drm_encoder *), GFP_KERNEL);
9167 if (!config->save_connector_encoders)
85f9eb71
DV		 9168 return -ENOMEM;
9169
9170 /* Copy data. Note that driver private data is not affected.
9171 * Should anything bad happen only the expected state is
9172 * restored, not the drivers personal bookkeeping.
9173 */
85f9eb71
DV		 9174 count = 0;
9175 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9176 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9177 }
9178
9179 count = 0;
9180 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9181 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9182 }
9183
9184 return 0;
9185}
9186
9187static void intel_set_config_restore_state(struct drm_device *dev,
9188 struct intel_set_config *config)
9189{
9a935856
DV		 9190 struct intel_encoder *encoder;
9191 struct intel_connector *connector;
85f9eb71
DV		 9192 int count;
9193
85f9eb71 9194 count = 0;
9a935856
DV		 9195 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9196 encoder->new_crtc =
9197 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9198 }
9199
9200 count = 0;
9a935856
DV		 9201 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9202 connector->new_encoder =
9203 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9204 }
9205}
9206
e3de42b6 9207static bool
2e57f47d 9208is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9209{
9210 int i;
9211
2e57f47d
CW		 9212 if (set->num_connectors == 0)
9213 return false;
9214
9215 if (WARN_ON(set->connectors == NULL))
9216 return false;
9217
9218 for (i = 0; i < set->num_connectors; i++)
9219 if (set->connectors[i]->encoder &&
9220 set->connectors[i]->encoder->crtc == set->crtc &&
9221 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9222 return true;
9223
9224 return false;
9225}
9226
5e2b584e
DV		 9227static void
9228intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9229 struct intel_set_config *config)
9230{
9231
9232 /* We should be able to check here if the fb has the same properties
9233 * and then just flip_or_move it */
2e57f47d
CW		 9234 if (is_crtc_connector_off(set)) {
9235 config->mode_changed = true;
e3de42b6 9236 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9237 /* If we have no fb then treat it as a full mode set */
9238 if (set->crtc->fb == NULL) {
319d9827
JB		 9239 struct intel_crtc *intel_crtc =
9240 to_intel_crtc(set->crtc);
9241
9242 if (intel_crtc->active && i915_fastboot) {
9243 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9244 config->fb_changed = true;
9245 } else {
9246 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9247 config->mode_changed = true;
9248 }
5e2b584e
DV		 9249 } else if (set->fb == NULL) {
9250 config->mode_changed = true;
72f4901e
DV		 9251 } else if (set->fb->pixel_format !=
9252 set->crtc->fb->pixel_format) {
5e2b584e 9253 config->mode_changed = true;
e3de42b6 9254 } else {
5e2b584e 9255 config->fb_changed = true;
e3de42b6 9256 }
5e2b584e
DV		 9257 }
9258
835c5873 9259 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9260 config->fb_changed = true;
9261
9262 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9263 DRM_DEBUG_KMS("modes are different, full mode set\n");
9264 drm_mode_debug_printmodeline(&set->crtc->mode);
9265 drm_mode_debug_printmodeline(set->mode);
9266 config->mode_changed = true;
9267 }
a1d95703
CW		 9268
9269 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9270 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9271}
9272
2e431051 9273static int
9a935856
DV		 9274intel_modeset_stage_output_state(struct drm_device *dev,
9275 struct drm_mode_set *set,
9276 struct intel_set_config *config)
50f56119 9277{
85f9eb71 9278 struct drm_crtc *new_crtc;
9a935856
DV		 9279 struct intel_connector *connector;
9280 struct intel_encoder *encoder;
f3f08572 9281 int ro;
50f56119 9282
9abdda74 9283 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9284 * of connectors. For paranoia, double-check this. */
9285 WARN_ON(!set->fb && (set->num_connectors != 0));
9286 WARN_ON(set->fb && (set->num_connectors == 0));
9287
9a935856
DV		 9288 list_for_each_entry(connector, &dev->mode_config.connector_list,
9289 base.head) {
9290 /* Otherwise traverse passed in connector list and get encoders
9291 * for them. */
50f56119 9292 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9293 if (set->connectors[ro] == &connector->base) {
9294 connector->new_encoder = connector->encoder;
50f56119
DV		 9295 break;
9296 }
9297 }
9298
9a935856
DV		 9299 /* If we disable the crtc, disable all its connectors. Also, if
9300 * the connector is on the changing crtc but not on the new
9301 * connector list, disable it. */
9302 if ((!set->fb || ro == set->num_connectors) &&
9303 connector->base.encoder &&
9304 connector->base.encoder->crtc == set->crtc) {
9305 connector->new_encoder = NULL;
9306
9307 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9308 connector->base.base.id,
9309 drm_get_connector_name(&connector->base));
9310 }
9311
9312
9313 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9314 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9315 config->mode_changed = true;
50f56119
DV		 9316 }
9317 }
9a935856 9318 /* connector->new_encoder is now updated for all connectors. */
50f56119 9319
9a935856 9320 /* Update crtc of enabled connectors. */
9a935856
DV		 9321 list_for_each_entry(connector, &dev->mode_config.connector_list,
9322 base.head) {
9323 if (!connector->new_encoder)
50f56119
DV		 9324 continue;
9325
9a935856 9326 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9327
9328 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9329 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9330 new_crtc = set->crtc;
9331 }
9332
9333 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9334 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9335 new_crtc)) {
5e2b584e 9336 return -EINVAL;
50f56119 9337 }
9a935856
DV		 9338 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9339
9340 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9341 connector->base.base.id,
9342 drm_get_connector_name(&connector->base),
9343 new_crtc->base.id);
9344 }
9345
9346 /* Check for any encoders that needs to be disabled. */
9347 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9348 base.head) {
9349 list_for_each_entry(connector,
9350 &dev->mode_config.connector_list,
9351 base.head) {
9352 if (connector->new_encoder == encoder) {
9353 WARN_ON(!connector->new_encoder->new_crtc);
9354
9355 goto next_encoder;
9356 }
9357 }
9358 encoder->new_crtc = NULL;
9359next_encoder:
9360 /* Only now check for crtc changes so we don't miss encoders
9361 * that will be disabled. */
9362 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9363 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9364 config->mode_changed = true;
50f56119
DV		 9365 }
9366 }
9a935856 9367 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9368
2e431051
DV		 9369 return 0;
9370}
9371
9372static int intel_crtc_set_config(struct drm_mode_set *set)
9373{
9374 struct drm_device *dev;
2e431051
DV		 9375 struct drm_mode_set save_set;
9376 struct intel_set_config *config;
9377 int ret;
2e431051 9378
8d3e375e
DV		 9379 BUG_ON(!set);
9380 BUG_ON(!set->crtc);
9381 BUG_ON(!set->crtc->helper_private);
2e431051 9382
7e53f3a4
DV		 9383 /* Enforce sane interface api - has been abused by the fb helper. */
9384 BUG_ON(!set->mode && set->fb);
9385 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9386
2e431051
DV		 9387 if (set->fb) {
9388 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9389 set->crtc->base.id, set->fb->base.id,
9390 (int)set->num_connectors, set->x, set->y);
9391 } else {
9392 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9393 }
9394
9395 dev = set->crtc->dev;
9396
9397 ret = -ENOMEM;
9398 config = kzalloc(sizeof(*config), GFP_KERNEL);
9399 if (!config)
9400 goto out_config;
9401
9402 ret = intel_set_config_save_state(dev, config);
9403 if (ret)
9404 goto out_config;
9405
9406 save_set.crtc = set->crtc;
9407 save_set.mode = &set->crtc->mode;
9408 save_set.x = set->crtc->x;
9409 save_set.y = set->crtc->y;
9410 save_set.fb = set->crtc->fb;
9411
9412 /* Compute whether we need a full modeset, only an fb base update or no
9413 * change at all. In the future we might also check whether only the
9414 * mode changed, e.g. for LVDS where we only change the panel fitter in
9415 * such cases. */
9416 intel_set_config_compute_mode_changes(set, config);
9417
9a935856 9418 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9419 if (ret)
9420 goto fail;
9421
5e2b584e 9422 if (config->mode_changed) {
c0c36b94
CW		 9423 ret = intel_set_mode(set->crtc, set->mode,
9424 set->x, set->y, set->fb);
5e2b584e 9425 } else if (config->fb_changed) {
4878cae2
VS		 9426 intel_crtc_wait_for_pending_flips(set->crtc);
9427
4f660f49 9428 ret = intel_pipe_set_base(set->crtc,
94352cf9 9429 set->x, set->y, set->fb);
50f56119
DV		 9430 }
9431
2d05eae1 9432 if (ret) {
bf67dfeb
DV		 9433 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9434 set->crtc->base.id, ret);
50f56119 9435fail:
2d05eae1 9436 intel_set_config_restore_state(dev, config);
50f56119 9437
2d05eae1
CW		 9438 /* Try to restore the config */
9439 if (config->mode_changed &&
9440 intel_set_mode(save_set.crtc, save_set.mode,
9441 save_set.x, save_set.y, save_set.fb))
9442 DRM_ERROR("failed to restore config after modeset failure\n");
9443 }
50f56119 9444
d9e55608
DV		 9445out_config:
9446 intel_set_config_free(config);
50f56119
DV		 9447 return ret;
9448}
f6e5b160
CW		 9449
9450static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9451 .cursor_set = intel_crtc_cursor_set,
9452 .cursor_move = intel_crtc_cursor_move,
9453 .gamma_set = intel_crtc_gamma_set,
50f56119 9454 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9455 .destroy = intel_crtc_destroy,
9456 .page_flip = intel_crtc_page_flip,
9457};
9458
79f689aa
PZ		 9459static void intel_cpu_pll_init(struct drm_device *dev)
9460{
affa9354 9461 if (HAS_DDI(dev))
79f689aa
PZ		 9462 intel_ddi_pll_init(dev);
9463}
9464
5358901f
DV		 9465static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9466 struct intel_shared_dpll *pll,
9467 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9468{
5358901f 9469 uint32_t val;
ee7b9f93 9470
5358901f 9471 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9472 hw_state->dpll = val;
9473 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9474 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9475
9476 return val & DPLL_VCO_ENABLE;
9477}
9478
15bdd4cf
DV		 9479static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9480 struct intel_shared_dpll *pll)
9481{
9482 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9483 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9484}
9485
e7b903d2
DV		 9486static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9487 struct intel_shared_dpll *pll)
9488{
e7b903d2
DV		 9489 /* PCH refclock must be enabled first */
9490 assert_pch_refclk_enabled(dev_priv);
9491
15bdd4cf
DV		 9492 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9493
9494 /* Wait for the clocks to stabilize. */
9495 POSTING_READ(PCH_DPLL(pll->id));
9496 udelay(150);
9497
9498 /* The pixel multiplier can only be updated once the
9499 * DPLL is enabled and the clocks are stable.
9500 *
9501 * So write it again.
9502 */
9503 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9504 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9505 udelay(200);
9506}
9507
9508static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9509 struct intel_shared_dpll *pll)
9510{
9511 struct drm_device *dev = dev_priv->dev;
9512 struct intel_crtc *crtc;
e7b903d2
DV		 9513
9514 /* Make sure no transcoder isn't still depending on us. */
9515 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9516 if (intel_crtc_to_shared_dpll(crtc) == pll)
9517 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9518 }
9519
15bdd4cf
DV		 9520 I915_WRITE(PCH_DPLL(pll->id), 0);
9521 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9522 udelay(200);
9523}
9524
46edb027
DV		 9525static char *ibx_pch_dpll_names[] = {
9526 "PCH DPLL A",
9527 "PCH DPLL B",
9528};
9529
7c74ade1 9530static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9531{
e7b903d2 9532 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9533 int i;
9534
7c74ade1 9535 dev_priv->num_shared_dpll = 2;
ee7b9f93 9536
e72f9fbf 9537 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9538 dev_priv->shared_dplls[i].id = i;
9539 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9540 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9541 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9542 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9543 dev_priv->shared_dplls[i].get_hw_state =
9544 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9545 }
9546}
9547
7c74ade1
DV		 9548static void intel_shared_dpll_init(struct drm_device *dev)
9549{
e7b903d2 9550 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9551
9552 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9553 ibx_pch_dpll_init(dev);
9554 else
9555 dev_priv->num_shared_dpll = 0;
9556
9557 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9558 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9559 dev_priv->num_shared_dpll);
9560}
9561
b358d0a6 9562static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9563{
22fd0fab 9564 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9565 struct intel_crtc *intel_crtc;
9566 int i;
9567
9568 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9569 if (intel_crtc == NULL)
9570 return;
9571
9572 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9573
9574 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9575 for (i = 0; i < 256; i++) {
9576 intel_crtc->lut_r[i] = i;
9577 intel_crtc->lut_g[i] = i;
9578 intel_crtc->lut_b[i] = i;
9579 }
9580
80824003
JB		 9581 /* Swap pipes & planes for FBC on pre-965 */
9582 intel_crtc->pipe = pipe;
9583 intel_crtc->plane = pipe;
e2e767ab 9584 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9585 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9586 intel_crtc->plane = !pipe;
80824003
JB		 9587 }
9588
22fd0fab
JB		 9589 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9590 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9591 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9592 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9593
79e53945 9594 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9595}
9596
08d7b3d1 9597int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9598 struct drm_file *file)
08d7b3d1 9599{
08d7b3d1 9600 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9601 struct drm_mode_object *drmmode_obj;
9602 struct intel_crtc *crtc;
08d7b3d1 9603
1cff8f6b
DV		 9604 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9605 return -ENODEV;
08d7b3d1 9606
c05422d5
DV		 9607 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9608 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9609
c05422d5 9610 if (!drmmode_obj) {
08d7b3d1
CW		 9611 DRM_ERROR("no such CRTC id\n");
9612 return -EINVAL;
9613 }
9614
c05422d5
DV		 9615 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9616 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9617
c05422d5 9618 return 0;
08d7b3d1
CW		 9619}
9620
66a9278e 9621static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9622{
66a9278e
DV		 9623 struct drm_device *dev = encoder->base.dev;
9624 struct intel_encoder *source_encoder;
79e53945 9625 int index_mask = 0;
79e53945
JB		 9626 int entry = 0;
9627
66a9278e
DV		 9628 list_for_each_entry(source_encoder,
9629 &dev->mode_config.encoder_list, base.head) {
9630
9631 if (encoder == source_encoder)
79e53945 9632 index_mask |= (1 << entry);
66a9278e
DV		 9633
9634 /* Intel hw has only one MUX where enocoders could be cloned. */
9635 if (encoder->cloneable && source_encoder->cloneable)
9636 index_mask |= (1 << entry);
9637
79e53945
JB		 9638 entry++;
9639 }
4ef69c7a 9640
79e53945
JB		 9641 return index_mask;
9642}
9643
4d302442
CW		 9644static bool has_edp_a(struct drm_device *dev)
9645{
9646 struct drm_i915_private *dev_priv = dev->dev_private;
9647
9648 if (!IS_MOBILE(dev))
9649 return false;
9650
9651 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9652 return false;
9653
9654 if (IS_GEN5(dev) &&
9655 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9656 return false;
9657
9658 return true;
9659}
9660
79e53945
JB		 9661static void intel_setup_outputs(struct drm_device *dev)
9662{
725e30ad 9663 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9664 struct intel_encoder *encoder;
cb0953d7 9665 bool dpd_is_edp = false;
79e53945 9666
c9093354 9667 intel_lvds_init(dev);
79e53945 9668
c40c0f5b 9669 if (!IS_ULT(dev))
79935fca 9670 intel_crt_init(dev);
cb0953d7 9671
affa9354 9672 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9673 int found;
9674
9675 /* Haswell uses DDI functions to detect digital outputs */
9676 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9677 /* DDI A only supports eDP */
9678 if (found)
9679 intel_ddi_init(dev, PORT_A);
9680
9681 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9682 * register */
9683 found = I915_READ(SFUSE_STRAP);
9684
9685 if (found & SFUSE_STRAP_DDIB_DETECTED)
9686 intel_ddi_init(dev, PORT_B);
9687 if (found & SFUSE_STRAP_DDIC_DETECTED)
9688 intel_ddi_init(dev, PORT_C);
9689 if (found & SFUSE_STRAP_DDID_DETECTED)
9690 intel_ddi_init(dev, PORT_D);
9691 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9692 int found;
270b3042
DV		 9693 dpd_is_edp = intel_dpd_is_edp(dev);
9694
9695 if (has_edp_a(dev))
9696 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9697
dc0fa718 9698 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9699 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9700 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9701 if (!found)
e2debe91 9702 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9703 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9704 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9705 }
9706
dc0fa718 9707 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9708 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9709
dc0fa718 9710 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9711 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9712
5eb08b69 9713 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9714 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9715
270b3042 9716 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9717 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9718 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9719 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9720 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9721 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9722 PORT_C);
9723 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9724 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9725 PORT_C);
9726 }
19c03924 9727
dc0fa718 9728 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9729 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9730 PORT_B);
67cfc203
VS		 9731 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9732 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9733 }
3cfca973
JN		 9734
9735 intel_dsi_init(dev);
103a196f 9736 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9737 bool found = false;
7d57382e 9738
e2debe91 9739 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9740 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9741 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9742 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9743 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9744 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9745 }
27185ae1 9746
e7281eab 9747 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9748 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9749 }
13520b05
KH		 9750
9751 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9752
e2debe91 9753 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9754 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9755 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9756 }
27185ae1 9757
e2debe91 9758 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9759
b01f2c3a
JB		 9760 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9761 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9762 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9763 }
e7281eab 9764 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9765 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9766 }
27185ae1 9767
b01f2c3a 9768 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9769 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9770 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9771 } else if (IS_GEN2(dev))
79e53945
JB		 9772 intel_dvo_init(dev);
9773
103a196f 9774 if (SUPPORTS_TV(dev))
79e53945
JB		 9775 intel_tv_init(dev);
9776
4ef69c7a
CW		 9777 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9778 encoder->base.possible_crtcs = encoder->crtc_mask;
9779 encoder->base.possible_clones =
66a9278e 9780 intel_encoder_clones(encoder);
79e53945 9781 }
47356eb6 9782
dde86e2d 9783 intel_init_pch_refclk(dev);
270b3042
DV		 9784
9785 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9786}
9787
ddfe1567
CW		 9788void intel_framebuffer_fini(struct intel_framebuffer *fb)
9789{
9790 drm_framebuffer_cleanup(&fb->base);
9791 drm_gem_object_unreference_unlocked(&fb->obj->base);
9792}
9793
79e53945
JB		 9794static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9795{
9796 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9797
ddfe1567 9798 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9799 kfree(intel_fb);
9800}
9801
9802static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9803 struct drm_file *file,
79e53945
JB		 9804 unsigned int *handle)
9805{
9806 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9807 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9808
05394f39 9809 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9810}
9811
9812static const struct drm_framebuffer_funcs intel_fb_funcs = {
9813 .destroy = intel_user_framebuffer_destroy,
9814 .create_handle = intel_user_framebuffer_create_handle,
9815};
9816
38651674
DA		 9817int intel_framebuffer_init(struct drm_device *dev,
9818 struct intel_framebuffer *intel_fb,
308e5bcb 9819 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9820 struct drm_i915_gem_object *obj)
79e53945 9821{
a35cdaa0 9822 int pitch_limit;
79e53945
JB		 9823 int ret;
9824
c16ed4be
CW		 9825 if (obj->tiling_mode == I915_TILING_Y) {
9826 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9827 return -EINVAL;
c16ed4be 9828 }
57cd6508 9829
c16ed4be
CW		 9830 if (mode_cmd->pitches[0] & 63) {
9831 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9832 mode_cmd->pitches[0]);
57cd6508 9833 return -EINVAL;
c16ed4be 9834 }
57cd6508 9835
a35cdaa0
CW		 9836 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9837 pitch_limit = 32*1024;
9838 } else if (INTEL_INFO(dev)->gen >= 4) {
9839 if (obj->tiling_mode)
9840 pitch_limit = 16*1024;
9841 else
9842 pitch_limit = 32*1024;
9843 } else if (INTEL_INFO(dev)->gen >= 3) {
9844 if (obj->tiling_mode)
9845 pitch_limit = 8*1024;
9846 else
9847 pitch_limit = 16*1024;
9848 } else
9849 /* XXX DSPC is limited to 4k tiled */
9850 pitch_limit = 8*1024;
9851
9852 if (mode_cmd->pitches[0] > pitch_limit) {
9853 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9854 obj->tiling_mode ? "tiled" : "linear",
9855 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9856 return -EINVAL;
c16ed4be 9857 }
5d7bd705
VS		 9858
9859 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9860 mode_cmd->pitches[0] != obj->stride) {
9861 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9862 mode_cmd->pitches[0], obj->stride);
5d7bd705 9863 return -EINVAL;
c16ed4be 9864 }
5d7bd705 9865
57779d06 9866 /* Reject formats not supported by any plane early. */
308e5bcb 9867 switch (mode_cmd->pixel_format) {
57779d06 9868 case DRM_FORMAT_C8:
04b3924d
VS		 9869 case DRM_FORMAT_RGB565:
9870 case DRM_FORMAT_XRGB8888:
9871 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9872 break;
9873 case DRM_FORMAT_XRGB1555:
9874 case DRM_FORMAT_ARGB1555:
c16ed4be 9875 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9876 DRM_DEBUG("unsupported pixel format: %s\n",
9877 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9878 return -EINVAL;
c16ed4be 9879 }
57779d06
VS		 9880 break;
9881 case DRM_FORMAT_XBGR8888:
9882 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9883 case DRM_FORMAT_XRGB2101010:
9884 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9885 case DRM_FORMAT_XBGR2101010:
9886 case DRM_FORMAT_ABGR2101010:
c16ed4be 9887 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9888 DRM_DEBUG("unsupported pixel format: %s\n",
9889 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9890 return -EINVAL;
c16ed4be 9891 }
b5626747 9892 break;
04b3924d
VS		 9893 case DRM_FORMAT_YUYV:
9894 case DRM_FORMAT_UYVY:
9895 case DRM_FORMAT_YVYU:
9896 case DRM_FORMAT_VYUY:
c16ed4be 9897 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9898 DRM_DEBUG("unsupported pixel format: %s\n",
9899 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9900 return -EINVAL;
c16ed4be 9901 }
57cd6508
CW		 9902 break;
9903 default:
4ee62c76
VS		 9904 DRM_DEBUG("unsupported pixel format: %s\n",
9905 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9906 return -EINVAL;
9907 }
9908
90f9a336
VS		 9909 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9910 if (mode_cmd->offsets[0] != 0)
9911 return -EINVAL;
9912
c7d73f6a
DV		 9913 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9914 intel_fb->obj = obj;
9915
79e53945
JB		 9916 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9917 if (ret) {
9918 DRM_ERROR("framebuffer init failed %d\n", ret);
9919 return ret;
9920 }
9921
79e53945
JB		 9922 return 0;
9923}
9924
79e53945
JB		 9925static struct drm_framebuffer *
9926intel_user_framebuffer_create(struct drm_device *dev,
9927 struct drm_file *filp,
308e5bcb 9928 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9929{
05394f39 9930 struct drm_i915_gem_object *obj;
79e53945 9931
308e5bcb
JB		 9932 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9933 mode_cmd->handles[0]));
c8725226 9934 if (&obj->base == NULL)
cce13ff7 9935 return ERR_PTR(-ENOENT);
79e53945 9936
d2dff872 9937 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9938}
9939
79e53945 9940static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9941 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9942 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9943};
9944
e70236a8
JB		 9945/* Set up chip specific display functions */
9946static void intel_init_display(struct drm_device *dev)
9947{
9948 struct drm_i915_private *dev_priv = dev->dev_private;
9949
ee9300bb
DV		 9950 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9951 dev_priv->display.find_dpll = g4x_find_best_dpll;
9952 else if (IS_VALLEYVIEW(dev))
9953 dev_priv->display.find_dpll = vlv_find_best_dpll;
9954 else if (IS_PINEVIEW(dev))
9955 dev_priv->display.find_dpll = pnv_find_best_dpll;
9956 else
9957 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9958
affa9354 9959 if (HAS_DDI(dev)) {
0e8ffe1b 9960 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9961 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9962 dev_priv->display.crtc_enable = haswell_crtc_enable;
9963 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9964 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9965 dev_priv->display.update_plane = ironlake_update_plane;
9966 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9967 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9968 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9969 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9970 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9971 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9972 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9973 } else if (IS_VALLEYVIEW(dev)) {
9974 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9975 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9976 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9977 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9978 dev_priv->display.off = i9xx_crtc_off;
9979 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9980 } else {
0e8ffe1b 9981 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9982 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9983 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9984 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9985 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9986 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9987 }
e70236a8 9988
e70236a8 9989 /* Returns the core display clock speed */
25eb05fc
JB		 9990 if (IS_VALLEYVIEW(dev))
9991 dev_priv->display.get_display_clock_speed =
9992 valleyview_get_display_clock_speed;
9993 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9994 dev_priv->display.get_display_clock_speed =
9995 i945_get_display_clock_speed;
9996 else if (IS_I915G(dev))
9997 dev_priv->display.get_display_clock_speed =
9998 i915_get_display_clock_speed;
257a7ffc 9999 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10000 dev_priv->display.get_display_clock_speed =
10001 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10002 else if (IS_PINEVIEW(dev))
10003 dev_priv->display.get_display_clock_speed =
10004 pnv_get_display_clock_speed;
e70236a8
JB		 10005 else if (IS_I915GM(dev))
10006 dev_priv->display.get_display_clock_speed =
10007 i915gm_get_display_clock_speed;
10008 else if (IS_I865G(dev))
10009 dev_priv->display.get_display_clock_speed =
10010 i865_get_display_clock_speed;
f0f8a9ce 10011 else if (IS_I85X(dev))
e70236a8
JB		 10012 dev_priv->display.get_display_clock_speed =
10013 i855_get_display_clock_speed;
10014 else /* 852, 830 */
10015 dev_priv->display.get_display_clock_speed =
10016 i830_get_display_clock_speed;
10017
7f8a8569 10018 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10019 if (IS_GEN5(dev)) {
674cf967 10020 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10021 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10022 } else if (IS_GEN6(dev)) {
674cf967 10023 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10024 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10025 } else if (IS_IVYBRIDGE(dev)) {
10026 /* FIXME: detect B0+ stepping and use auto training */
10027 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10028 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10029 dev_priv->display.modeset_global_resources =
10030 ivb_modeset_global_resources;
c82e4d26
ED		 10031 } else if (IS_HASWELL(dev)) {
10032 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10033 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10034 dev_priv->display.modeset_global_resources =
10035 haswell_modeset_global_resources;
a0e63c22 10036 }
6067aaea 10037 } else if (IS_G4X(dev)) {
e0dac65e 10038 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10039 }
8c9f3aaf
JB		 10040
10041 /* Default just returns -ENODEV to indicate unsupported */
10042 dev_priv->display.queue_flip = intel_default_queue_flip;
10043
10044 switch (INTEL_INFO(dev)->gen) {
10045 case 2:
10046 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10047 break;
10048
10049 case 3:
10050 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10051 break;
10052
10053 case 4:
10054 case 5:
10055 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10056 break;
10057
10058 case 6:
10059 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10060 break;
7c9017e5
JB		 10061 case 7:
10062 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10063 break;
8c9f3aaf 10064 }
e70236a8
JB		 10065}
10066
b690e96c
JB		 10067/*
10068 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10069 * resume, or other times. This quirk makes sure that's the case for
10070 * affected systems.
10071 */
0206e353 10072static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10073{
10074 struct drm_i915_private *dev_priv = dev->dev_private;
10075
10076 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10077 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10078}
10079
435793df
KP		 10080/*
10081 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10082 */
10083static void quirk_ssc_force_disable(struct drm_device *dev)
10084{
10085 struct drm_i915_private *dev_priv = dev->dev_private;
10086 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10087 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10088}
10089
4dca20ef 10090/*
5a15ab5b
CE		 10091 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10092 * brightness value
4dca20ef
CE		 10093 */
10094static void quirk_invert_brightness(struct drm_device *dev)
10095{
10096 struct drm_i915_private *dev_priv = dev->dev_private;
10097 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10098 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10099}
10100
e85843be
KM		 10101/*
10102 * Some machines (Dell XPS13) suffer broken backlight controls if
10103 * BLM_PCH_PWM_ENABLE is set.
10104 */
10105static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10106{
10107 struct drm_i915_private *dev_priv = dev->dev_private;
10108 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10109 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10110}
10111
b690e96c
JB		 10112struct intel_quirk {
10113 int device;
10114 int subsystem_vendor;
10115 int subsystem_device;
10116 void (*hook)(struct drm_device *dev);
10117};
10118
5f85f176
EE		 10119/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10120struct intel_dmi_quirk {
10121 void (*hook)(struct drm_device *dev);
10122 const struct dmi_system_id (*dmi_id_list)[];
10123};
10124
10125static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10126{
10127 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10128 return 1;
10129}
10130
10131static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10132 {
10133 .dmi_id_list = &(const struct dmi_system_id[]) {
10134 {
10135 .callback = intel_dmi_reverse_brightness,
10136 .ident = "NCR Corporation",
10137 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10138 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10139 },
10140 },
10141 { } /* terminating entry */
10142 },
10143 .hook = quirk_invert_brightness,
10144 },
10145};
10146
c43b5634 10147static struct intel_quirk intel_quirks[] = {
b690e96c 10148 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10149 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10150
b690e96c
JB		 10151 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10152 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10153
b690e96c
JB		 10154 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10155 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10156
ccd0d36e 10157 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10158 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10159 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10160
10161 /* Lenovo U160 cannot use SSC on LVDS */
10162 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10163
10164 /* Sony Vaio Y cannot use SSC on LVDS */
10165 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10166
10167 /* Acer Aspire 5734Z must invert backlight brightness */
10168 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10169
10170 /* Acer/eMachines G725 */
10171 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10172
10173 /* Acer/eMachines e725 */
10174 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10175
10176 /* Acer/Packard Bell NCL20 */
10177 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10178
10179 /* Acer Aspire 4736Z */
10180 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10181
10182 /* Dell XPS13 HD Sandy Bridge */
10183 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10184 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10185 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10186};
10187
10188static void intel_init_quirks(struct drm_device *dev)
10189{
10190 struct pci_dev *d = dev->pdev;
10191 int i;
10192
10193 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10194 struct intel_quirk *q = &intel_quirks[i];
10195
10196 if (d->device == q->device &&
10197 (d->subsystem_vendor == q->subsystem_vendor ||
10198 q->subsystem_vendor == PCI_ANY_ID) &&
10199 (d->subsystem_device == q->subsystem_device ||
10200 q->subsystem_device == PCI_ANY_ID))
10201 q->hook(dev);
10202 }
5f85f176
EE		 10203 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10204 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10205 intel_dmi_quirks[i].hook(dev);
10206 }
b690e96c
JB		 10207}
10208
9cce37f4
JB		 10209/* Disable the VGA plane that we never use */
10210static void i915_disable_vga(struct drm_device *dev)
10211{
10212 struct drm_i915_private *dev_priv = dev->dev_private;
10213 u8 sr1;
766aa1c4 10214 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10215
10216 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10217 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10218 sr1 = inb(VGA_SR_DATA);
10219 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10220
10221 /* Disable VGA memory on Intel HD */
10222 if (HAS_PCH_SPLIT(dev)) {
10223 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10224 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10225 VGA_RSRC_NORMAL_IO |
10226 VGA_RSRC_NORMAL_MEM);
10227 }
10228
9cce37f4
JB		 10229 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10230 udelay(300);
10231
10232 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10233 POSTING_READ(vga_reg);
10234}
10235
81b5c7bc
AW		 10236static void i915_enable_vga(struct drm_device *dev)
10237{
10238 /* Enable VGA memory on Intel HD */
10239 if (HAS_PCH_SPLIT(dev)) {
10240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10241 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10242 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10243 VGA_RSRC_LEGACY_MEM |
10244 VGA_RSRC_NORMAL_IO |
10245 VGA_RSRC_NORMAL_MEM);
10246 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10247 }
10248}
10249
f817586c
DV		 10250void intel_modeset_init_hw(struct drm_device *dev)
10251{
fa42e23c 10252 intel_init_power_well(dev);
0232e927 10253
a8f78b58
ED		 10254 intel_prepare_ddi(dev);
10255
f817586c
DV		 10256 intel_init_clock_gating(dev);
10257
79f5b2c7 10258 mutex_lock(&dev->struct_mutex);
8090c6b9 10259 intel_enable_gt_powersave(dev);
79f5b2c7 10260 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10261}
10262
7d708ee4
ID		 10263void intel_modeset_suspend_hw(struct drm_device *dev)
10264{
10265 intel_suspend_hw(dev);
10266}
10267
79e53945
JB		 10268void intel_modeset_init(struct drm_device *dev)
10269{
652c393a 10270 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10271 int i, j, ret;
79e53945
JB		 10272
10273 drm_mode_config_init(dev);
10274
10275 dev->mode_config.min_width = 0;
10276 dev->mode_config.min_height = 0;
10277
019d96cb
DA		 10278 dev->mode_config.preferred_depth = 24;
10279 dev->mode_config.prefer_shadow = 1;
10280
e6ecefaa 10281 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10282
b690e96c
JB		 10283 intel_init_quirks(dev);
10284
1fa61106
ED		 10285 intel_init_pm(dev);
10286
e3c74757
BW		 10287 if (INTEL_INFO(dev)->num_pipes == 0)
10288 return;
10289
e70236a8
JB		 10290 intel_init_display(dev);
10291
a6c45cf0
CW		 10292 if (IS_GEN2(dev)) {
10293 dev->mode_config.max_width = 2048;
10294 dev->mode_config.max_height = 2048;
10295 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10296 dev->mode_config.max_width = 4096;
10297 dev->mode_config.max_height = 4096;
79e53945 10298 } else {
a6c45cf0
CW		 10299 dev->mode_config.max_width = 8192;
10300 dev->mode_config.max_height = 8192;
79e53945 10301 }
5d4545ae 10302 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10303
28c97730 10304 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10305 INTEL_INFO(dev)->num_pipes,
10306 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10307
08e2a7de 10308 for_each_pipe(i) {
79e53945 10309 intel_crtc_init(dev, i);
7f1f3851
JB		 10310 for (j = 0; j < dev_priv->num_plane; j++) {
10311 ret = intel_plane_init(dev, i, j);
10312 if (ret)
06da8da2
VS		 10313 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10314 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10315 }
79e53945
JB		 10316 }
10317
79f689aa 10318 intel_cpu_pll_init(dev);
e72f9fbf 10319 intel_shared_dpll_init(dev);
ee7b9f93 10320
9cce37f4
JB		 10321 /* Just disable it once at startup */
10322 i915_disable_vga(dev);
79e53945 10323 intel_setup_outputs(dev);
11be49eb
CW		 10324
10325 /* Just in case the BIOS is doing something questionable. */
10326 intel_disable_fbc(dev);
2c7111db
CW		 10327}
10328
24929352
DV		 10329static void
10330intel_connector_break_all_links(struct intel_connector *connector)
10331{
10332 connector->base.dpms = DRM_MODE_DPMS_OFF;
10333 connector->base.encoder = NULL;
10334 connector->encoder->connectors_active = false;
10335 connector->encoder->base.crtc = NULL;
10336}
10337
7fad798e
DV		 10338static void intel_enable_pipe_a(struct drm_device *dev)
10339{
10340 struct intel_connector *connector;
10341 struct drm_connector *crt = NULL;
10342 struct intel_load_detect_pipe load_detect_temp;
10343
10344 /* We can't just switch on the pipe A, we need to set things up with a
10345 * proper mode and output configuration. As a gross hack, enable pipe A
10346 * by enabling the load detect pipe once. */
10347 list_for_each_entry(connector,
10348 &dev->mode_config.connector_list,
10349 base.head) {
10350 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10351 crt = &connector->base;
10352 break;
10353 }
10354 }
10355
10356 if (!crt)
10357 return;
10358
10359 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10360 intel_release_load_detect_pipe(crt, &load_detect_temp);
10361
652c393a 10362
7fad798e
DV		 10363}
10364
fa555837
DV		 10365static bool
10366intel_check_plane_mapping(struct intel_crtc *crtc)
10367{
7eb552ae
BW		 10368 struct drm_device *dev = crtc->base.dev;
10369 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10370 u32 reg, val;
10371
7eb552ae 10372 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10373 return true;
10374
10375 reg = DSPCNTR(!crtc->plane);
10376 val = I915_READ(reg);
10377
10378 if ((val & DISPLAY_PLANE_ENABLE) &&
10379 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10380 return false;
10381
10382 return true;
10383}
10384
24929352
DV		 10385static void intel_sanitize_crtc(struct intel_crtc *crtc)
10386{
10387 struct drm_device *dev = crtc->base.dev;
10388 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10389 u32 reg;
24929352 10390
24929352 10391 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10392 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10393 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10394
10395 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10396 * disable the crtc (and hence change the state) if it is wrong. Note
10397 * that gen4+ has a fixed plane -> pipe mapping. */
10398 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10399 struct intel_connector *connector;
10400 bool plane;
10401
24929352
DV		 10402 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10403 crtc->base.base.id);
10404
10405 /* Pipe has the wrong plane attached and the plane is active.
10406 * Temporarily change the plane mapping and disable everything
10407 * ... */
10408 plane = crtc->plane;
10409 crtc->plane = !plane;
10410 dev_priv->display.crtc_disable(&crtc->base);
10411 crtc->plane = plane;
10412
10413 /* ... and break all links. */
10414 list_for_each_entry(connector, &dev->mode_config.connector_list,
10415 base.head) {
10416 if (connector->encoder->base.crtc != &crtc->base)
10417 continue;
10418
10419 intel_connector_break_all_links(connector);
10420 }
10421
10422 WARN_ON(crtc->active);
10423 crtc->base.enabled = false;
10424 }
24929352 10425
7fad798e
DV		 10426 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10427 crtc->pipe == PIPE_A && !crtc->active) {
10428 /* BIOS forgot to enable pipe A, this mostly happens after
10429 * resume. Force-enable the pipe to fix this, the update_dpms
10430 * call below we restore the pipe to the right state, but leave
10431 * the required bits on. */
10432 intel_enable_pipe_a(dev);
10433 }
10434
24929352
DV		 10435 /* Adjust the state of the output pipe according to whether we
10436 * have active connectors/encoders. */
10437 intel_crtc_update_dpms(&crtc->base);
10438
10439 if (crtc->active != crtc->base.enabled) {
10440 struct intel_encoder *encoder;
10441
10442 /* This can happen either due to bugs in the get_hw_state
10443 * functions or because the pipe is force-enabled due to the
10444 * pipe A quirk. */
10445 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10446 crtc->base.base.id,
10447 crtc->base.enabled ? "enabled" : "disabled",
10448 crtc->active ? "enabled" : "disabled");
10449
10450 crtc->base.enabled = crtc->active;
10451
10452 /* Because we only establish the connector -> encoder ->
10453 * crtc links if something is active, this means the
10454 * crtc is now deactivated. Break the links. connector
10455 * -> encoder links are only establish when things are
10456 * actually up, hence no need to break them. */
10457 WARN_ON(crtc->active);
10458
10459 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10460 WARN_ON(encoder->connectors_active);
10461 encoder->base.crtc = NULL;
10462 }
10463 }
10464}
10465
10466static void intel_sanitize_encoder(struct intel_encoder *encoder)
10467{
10468 struct intel_connector *connector;
10469 struct drm_device *dev = encoder->base.dev;
10470
10471 /* We need to check both for a crtc link (meaning that the
10472 * encoder is active and trying to read from a pipe) and the
10473 * pipe itself being active. */
10474 bool has_active_crtc = encoder->base.crtc &&
10475 to_intel_crtc(encoder->base.crtc)->active;
10476
10477 if (encoder->connectors_active && !has_active_crtc) {
10478 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10479 encoder->base.base.id,
10480 drm_get_encoder_name(&encoder->base));
10481
10482 /* Connector is active, but has no active pipe. This is
10483 * fallout from our resume register restoring. Disable
10484 * the encoder manually again. */
10485 if (encoder->base.crtc) {
10486 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10487 encoder->base.base.id,
10488 drm_get_encoder_name(&encoder->base));
10489 encoder->disable(encoder);
10490 }
10491
10492 /* Inconsistent output/port/pipe state happens presumably due to
10493 * a bug in one of the get_hw_state functions. Or someplace else
10494 * in our code, like the register restore mess on resume. Clamp
10495 * things to off as a safer default. */
10496 list_for_each_entry(connector,
10497 &dev->mode_config.connector_list,
10498 base.head) {
10499 if (connector->encoder != encoder)
10500 continue;
10501
10502 intel_connector_break_all_links(connector);
10503 }
10504 }
10505 /* Enabled encoders without active connectors will be fixed in
10506 * the crtc fixup. */
10507}
10508
44cec740 10509void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10510{
10511 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10512 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10513
8dc8a27c
PZ		 10514 /* This function can be called both from intel_modeset_setup_hw_state or
10515 * at a very early point in our resume sequence, where the power well
10516 * structures are not yet restored. Since this function is at a very
10517 * paranoid "someone might have enabled VGA while we were not looking"
10518 * level, just check if the power well is enabled instead of trying to
10519 * follow the "don't touch the power well if we don't need it" policy
10520 * the rest of the driver uses. */
10521 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10522 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10523 return;
10524
0fde901f
KM		 10525 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10526 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10527 i915_disable_vga(dev);
0fde901f
KM		 10528 }
10529}
10530
30e984df 10531static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10532{
10533 struct drm_i915_private *dev_priv = dev->dev_private;
10534 enum pipe pipe;
24929352
DV		 10535 struct intel_crtc *crtc;
10536 struct intel_encoder *encoder;
10537 struct intel_connector *connector;
5358901f 10538 int i;
24929352 10539
0e8ffe1b
DV		 10540 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10541 base.head) {
88adfff1 10542 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10543
0e8ffe1b
DV		 10544 crtc->active = dev_priv->display.get_pipe_config(crtc,
10545 &crtc->config);
24929352
DV		 10546
10547 crtc->base.enabled = crtc->active;
10548
10549 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10550 crtc->base.base.id,
10551 crtc->active ? "enabled" : "disabled");
10552 }
10553
5358901f 10554 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10555 if (HAS_DDI(dev))
6441ab5f
PZ		 10556 intel_ddi_setup_hw_pll_state(dev);
10557
5358901f
DV		 10558 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10559 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10560
10561 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10562 pll->active = 0;
10563 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10564 base.head) {
10565 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10566 pll->active++;
10567 }
10568 pll->refcount = pll->active;
10569
35c95375
DV		 10570 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10571 pll->name, pll->refcount, pll->on);
5358901f
DV		 10572 }
10573
24929352
DV		 10574 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10575 base.head) {
10576 pipe = 0;
10577
10578 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10579 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10580 encoder->base.crtc = &crtc->base;
510d5f2f 10581 if (encoder->get_config)
045ac3b5 10582 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10583 } else {
10584 encoder->base.crtc = NULL;
10585 }
10586
10587 encoder->connectors_active = false;
10588 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10589 encoder->base.base.id,
10590 drm_get_encoder_name(&encoder->base),
10591 encoder->base.crtc ? "enabled" : "disabled",
10592 pipe);
10593 }
10594
10595 list_for_each_entry(connector, &dev->mode_config.connector_list,
10596 base.head) {
10597 if (connector->get_hw_state(connector)) {
10598 connector->base.dpms = DRM_MODE_DPMS_ON;
10599 connector->encoder->connectors_active = true;
10600 connector->base.encoder = &connector->encoder->base;
10601 } else {
10602 connector->base.dpms = DRM_MODE_DPMS_OFF;
10603 connector->base.encoder = NULL;
10604 }
10605 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10606 connector->base.base.id,
10607 drm_get_connector_name(&connector->base),
10608 connector->base.encoder ? "enabled" : "disabled");
10609 }
30e984df
DV		 10610}
10611
10612/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10613 * and i915 state tracking structures. */
10614void intel_modeset_setup_hw_state(struct drm_device *dev,
10615 bool force_restore)
10616{
10617 struct drm_i915_private *dev_priv = dev->dev_private;
10618 enum pipe pipe;
10619 struct drm_plane *plane;
10620 struct intel_crtc *crtc;
10621 struct intel_encoder *encoder;
35c95375 10622 int i;
30e984df
DV		 10623
10624 intel_modeset_readout_hw_state(dev);
24929352 10625
babea61d
JB		 10626 /*
10627 * Now that we have the config, copy it to each CRTC struct
10628 * Note that this could go away if we move to using crtc_config
10629 * checking everywhere.
10630 */
10631 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10632 base.head) {
10633 if (crtc->active && i915_fastboot) {
10634 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10635
10636 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10637 crtc->base.base.id);
10638 drm_mode_debug_printmodeline(&crtc->base.mode);
10639 }
10640 }
10641
24929352
DV		 10642 /* HW state is read out, now we need to sanitize this mess. */
10643 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10644 base.head) {
10645 intel_sanitize_encoder(encoder);
10646 }
10647
10648 for_each_pipe(pipe) {
10649 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10650 intel_sanitize_crtc(crtc);
c0b03411 10651 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10652 }
9a935856 10653
35c95375
DV		 10654 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10655 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10656
10657 if (!pll->on || pll->active)
10658 continue;
10659
10660 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10661
10662 pll->disable(dev_priv, pll);
10663 pll->on = false;
10664 }
10665
45e2b5f6 10666 if (force_restore) {
f30da187
DV		 10667 /*
10668 * We need to use raw interfaces for restoring state to avoid
10669 * checking (bogus) intermediate states.
10670 */
45e2b5f6 10671 for_each_pipe(pipe) {
b5644d05
JB		 10672 struct drm_crtc *crtc =
10673 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10674
10675 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10676 crtc->fb);
45e2b5f6 10677 }
b5644d05
JB		 10678 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10679 intel_plane_restore(plane);
0fde901f
KM		 10680
10681 i915_redisable_vga(dev);
45e2b5f6
DV		 10682 } else {
10683 intel_modeset_update_staged_output_state(dev);
10684 }
8af6cf88
DV		 10685
10686 intel_modeset_check_state(dev);
2e938892
DV		 10687
10688 drm_mode_config_reset(dev);
2c7111db
CW		 10689}
10690
10691void intel_modeset_gem_init(struct drm_device *dev)
10692{
1833b134 10693 intel_modeset_init_hw(dev);
02e792fb
DV		 10694
10695 intel_setup_overlay(dev);
24929352 10696
45e2b5f6 10697 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10698}
10699
10700void intel_modeset_cleanup(struct drm_device *dev)
10701{
652c393a
JB		 10702 struct drm_i915_private *dev_priv = dev->dev_private;
10703 struct drm_crtc *crtc;
652c393a 10704
fd0c0642
DV		 10705 /*
10706 * Interrupts and polling as the first thing to avoid creating havoc.
10707 * Too much stuff here (turning of rps, connectors, ...) would
10708 * experience fancy races otherwise.
10709 */
10710 drm_irq_uninstall(dev);
10711 cancel_work_sync(&dev_priv->hotplug_work);
10712 /*
10713 * Due to the hpd irq storm handling the hotplug work can re-arm the
10714 * poll handlers. Hence disable polling after hpd handling is shut down.
10715 */
f87ea761 10716 drm_kms_helper_poll_fini(dev);
fd0c0642 10717
652c393a
JB		 10718 mutex_lock(&dev->struct_mutex);
10719
723bfd70
JB		 10720 intel_unregister_dsm_handler();
10721
652c393a
JB		 10722 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10723 /* Skip inactive CRTCs */
10724 if (!crtc->fb)
10725 continue;
10726
3dec0095 10727 intel_increase_pllclock(crtc);
652c393a
JB		 10728 }
10729
973d04f9 10730 intel_disable_fbc(dev);
e70236a8 10731
81b5c7bc
AW		 10732 i915_enable_vga(dev);
10733
8090c6b9 10734 intel_disable_gt_powersave(dev);
0cdab21f 10735
930ebb46
DV		 10736 ironlake_teardown_rc6(dev);
10737
69341a5e
KH		 10738 mutex_unlock(&dev->struct_mutex);
10739
1630fe75
CW		 10740 /* flush any delayed tasks or pending work */
10741 flush_scheduled_work();
10742
dc652f90
JN		 10743 /* destroy backlight, if any, before the connectors */
10744 intel_panel_destroy_backlight(dev);
10745
79e53945 10746 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10747
10748 intel_cleanup_overlay(dev);
79e53945
JB		 10749}
10750
f1c79df3
ZW		 10751/*
10752 * Return which encoder is currently attached for connector.
10753 */
df0e9248 10754struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10755{
df0e9248
CW		 10756 return &intel_attached_encoder(connector)->base;
10757}
f1c79df3 10758
df0e9248
CW		 10759void intel_connector_attach_encoder(struct intel_connector *connector,
10760 struct intel_encoder *encoder)
10761{
10762 connector->encoder = encoder;
10763 drm_mode_connector_attach_encoder(&connector->base,
10764 &encoder->base);
79e53945 10765}
28d52043
DA		 10766
10767/*
10768 * set vga decode state - true == enable VGA decode
10769 */
10770int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10771{
10772 struct drm_i915_private *dev_priv = dev->dev_private;
10773 u16 gmch_ctrl;
10774
10775 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10776 if (state)
10777 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10778 else
10779 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10780 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10781 return 0;
10782}
c4a1d9e4 10783
c4a1d9e4 10784struct intel_display_error_state {
ff57f1b0
PZ		 10785
10786 u32 power_well_driver;
10787
63b66e5b
CW		 10788 int num_transcoders;
10789
c4a1d9e4
CW		 10790 struct intel_cursor_error_state {
10791 u32 control;
10792 u32 position;
10793 u32 base;
10794 u32 size;
52331309 10795 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10796
10797 struct intel_pipe_error_state {
c4a1d9e4 10798 u32 source;
52331309 10799 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10800
10801 struct intel_plane_error_state {
10802 u32 control;
10803 u32 stride;
10804 u32 size;
10805 u32 pos;
10806 u32 addr;
10807 u32 surface;
10808 u32 tile_offset;
52331309 10809 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10810
10811 struct intel_transcoder_error_state {
10812 enum transcoder cpu_transcoder;
10813
10814 u32 conf;
10815
10816 u32 htotal;
10817 u32 hblank;
10818 u32 hsync;
10819 u32 vtotal;
10820 u32 vblank;
10821 u32 vsync;
10822 } transcoder[4];
c4a1d9e4
CW		 10823};
10824
10825struct intel_display_error_state *
10826intel_display_capture_error_state(struct drm_device *dev)
10827{
0206e353 10828 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10829 struct intel_display_error_state *error;
63b66e5b
CW		 10830 int transcoders[] = {
10831 TRANSCODER_A,
10832 TRANSCODER_B,
10833 TRANSCODER_C,
10834 TRANSCODER_EDP,
10835 };
c4a1d9e4
CW		 10836 int i;
10837
63b66e5b
CW		 10838 if (INTEL_INFO(dev)->num_pipes == 0)
10839 return NULL;
10840
c4a1d9e4
CW		 10841 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10842 if (error == NULL)
10843 return NULL;
10844
ff57f1b0
PZ		 10845 if (HAS_POWER_WELL(dev))
10846 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10847
52331309 10848 for_each_pipe(i) {
a18c4c3d
PZ		 10849 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10850 error->cursor[i].control = I915_READ(CURCNTR(i));
10851 error->cursor[i].position = I915_READ(CURPOS(i));
10852 error->cursor[i].base = I915_READ(CURBASE(i));
10853 } else {
10854 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10855 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10856 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10857 }
c4a1d9e4
CW		 10858
10859 error->plane[i].control = I915_READ(DSPCNTR(i));
10860 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10861 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10862 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10863 error->plane[i].pos = I915_READ(DSPPOS(i));
10864 }
ca291363
PZ		 10865 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10866 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10867 if (INTEL_INFO(dev)->gen >= 4) {
10868 error->plane[i].surface = I915_READ(DSPSURF(i));
10869 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10870 }
10871
c4a1d9e4 10872 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10873 }
10874
10875 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10876 if (HAS_DDI(dev_priv->dev))
10877 error->num_transcoders++; /* Account for eDP. */
10878
10879 for (i = 0; i < error->num_transcoders; i++) {
10880 enum transcoder cpu_transcoder = transcoders[i];
10881
10882 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10883
10884 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10885 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10886 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10887 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10888 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10889 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10890 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10891 }
10892
12d217c7
PZ		 10893 /* In the code above we read the registers without checking if the power
10894 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10895 * prevent the next I915_WRITE from detecting it and printing an error
10896 * message. */
907b28c5 10897 intel_uncore_clear_errors(dev);
12d217c7 10898
c4a1d9e4
CW		 10899 return error;
10900}
10901
edc3d884
MK		 10902#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10903
c4a1d9e4 10904void
edc3d884 10905intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10906 struct drm_device *dev,
10907 struct intel_display_error_state *error)
10908{
10909 int i;
10910
63b66e5b
CW		 10911 if (!error)
10912 return;
10913
edc3d884 10914 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10915 if (HAS_POWER_WELL(dev))
edc3d884 10916 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10917 error->power_well_driver);
52331309 10918 for_each_pipe(i) {
edc3d884 10919 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10920 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10921
10922 err_printf(m, "Plane [%d]:\n", i);
10923 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10924 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10925 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10926 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10927 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10928 }
4b71a570 10929 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10930 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10931 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10932 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10933 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10934 }
10935
edc3d884
MK		 10936 err_printf(m, "Cursor [%d]:\n", i);
10937 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10938 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10939 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10940 }
63b66e5b
CW		 10941
10942 for (i = 0; i < error->num_transcoders; i++) {
10943 err_printf(m, " CPU transcoder: %c\n",
10944 transcoder_name(error->transcoder[i].cpu_transcoder));
10945 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10946 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10947 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10948 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10949 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10950 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10951 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10952 }
c4a1d9e4 10953}
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