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drm/i915: add proper CPU/PCH checks to crtc_mode_set functions
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
17dc9257 383 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 396 .dot = { .min = 25000, .max = 270000 },
397 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 398 .n = { .min = 1, .max = 7 },
74a4dd2e 399 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
284637d9 1027 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab 1378
75c5da27
DV		 1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
de9a35ab 1381 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1382}
1383
1384static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1386{
47a05eca 1387 u32 val = I915_READ(reg);
e9a851ed 1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1390 reg, pipe_name(pipe));
de9a35ab 1391
75c5da27
DV		 1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1394 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1395}
1396
1397static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
1400 int reg;
1401 u32 val;
291906f1 1402
f0575e92
KP		 1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1406
1407 reg = PCH_ADPA;
1408 val = I915_READ(reg);
e9a851ed 1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1410 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1411 pipe_name(pipe));
291906f1
JB		 1412
1413 reg = PCH_LVDS;
1414 val = I915_READ(reg);
e9a851ed 1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1417 pipe_name(pipe));
291906f1
JB		 1418
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422}
1423
63d7bbe9
JB		 1424/**
1425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1428 *
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1432 *
1433 * Note! This is for pre-ILK only.
7434a255
TR		 1434 *
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1436 */
a37b9b34 1437static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1438{
1439 int reg;
1440 u32 val;
1441
1442 /* No really, not for ILK+ */
a0c4da24 1443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1444
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447 assert_panel_unlocked(dev_priv, pipe);
1448
1449 reg = DPLL(pipe);
1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1452
1453 /* We do this three times for luck */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463}
1464
1465/**
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1469 *
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1471 *
1472 * Note! This is for pre-ILK only.
1473 */
1474static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475{
1476 int reg;
1477 u32 val;
1478
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481 return;
1482
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1485
1486 reg = DPLL(pipe);
1487 val = I915_READ(reg);
1488 val &= ~DPLL_VCO_ENABLE;
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491}
1492
a416edef
ED		 1493/* SBI access */
1494static void
1495intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496{
1497 unsigned long flags;
1498
1499 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1500 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1501 100)) {
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503 goto out_unlock;
1504 }
1505
1506 I915_WRITE(SBI_ADDR,
1507 (reg << 16));
1508 I915_WRITE(SBI_DATA,
1509 value);
1510 I915_WRITE(SBI_CTL_STAT,
1511 SBI_BUSY |
1512 SBI_CTL_OP_CRWR);
1513
39fb50f6 1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517 goto out_unlock;
1518 }
1519
1520out_unlock:
1521 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522}
1523
1524static u32
1525intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526{
1527 unsigned long flags;
39fb50f6 1528 u32 value = 0;
a416edef
ED		 1529
1530 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1532 100)) {
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534 goto out_unlock;
1535 }
1536
1537 I915_WRITE(SBI_ADDR,
1538 (reg << 16));
1539 I915_WRITE(SBI_CTL_STAT,
1540 SBI_BUSY |
1541 SBI_CTL_OP_CRRD);
1542
39fb50f6 1543 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1544 100)) {
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546 goto out_unlock;
1547 }
1548
1549 value = I915_READ(SBI_DATA);
1550
1551out_unlock:
1552 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553 return value;
1554}
1555
92f2584a
JB		 1556/**
1557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1560 *
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1563 */
ee7b9f93 1564static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1565{
ee7b9f93 1566 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1567 struct intel_pch_pll *pll;
92f2584a
JB		 1568 int reg;
1569 u32 val;
1570
48da64a8 1571 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1572 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1573 pll = intel_crtc->pch_pll;
1574 if (pll == NULL)
1575 return;
1576
1577 if (WARN_ON(pll->refcount == 0))
1578 return;
ee7b9f93
JB		 1579
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
92f2584a
JB		 1583
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv);
1586
ee7b9f93 1587 if (pll->active++ && pll->on) {
92b27b08 1588 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1589 return;
1590 }
1591
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594 reg = pll->pll_reg;
92f2584a
JB		 1595 val = I915_READ(reg);
1596 val |= DPLL_VCO_ENABLE;
1597 I915_WRITE(reg, val);
1598 POSTING_READ(reg);
1599 udelay(200);
ee7b9f93
JB		 1600
1601 pll->on = true;
92f2584a
JB		 1602}
1603
ee7b9f93 1604static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1605{
ee7b9f93
JB		 1606 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1608 int reg;
ee7b9f93 1609 u32 val;
4c609cb8 1610
92f2584a
JB		 1611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1613 if (pll == NULL)
1614 return;
92f2584a 1615
48da64a8
CW		 1616 if (WARN_ON(pll->refcount == 0))
1617 return;
7a419866 1618
ee7b9f93
JB		 1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll->pll_reg, pll->active, pll->on,
1621 intel_crtc->base.base.id);
7a419866 1622
48da64a8 1623 if (WARN_ON(pll->active == 0)) {
92b27b08 1624 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1625 return;
1626 }
1627
ee7b9f93 1628 if (--pll->active) {
92b27b08 1629 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1630 return;
ee7b9f93
JB		 1631 }
1632
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635 /* Make sure transcoder isn't still depending on us */
1636 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1637
ee7b9f93 1638 reg = pll->pll_reg;
92f2584a
JB		 1639 val = I915_READ(reg);
1640 val &= ~DPLL_VCO_ENABLE;
1641 I915_WRITE(reg, val);
1642 POSTING_READ(reg);
1643 udelay(200);
ee7b9f93
JB		 1644
1645 pll->on = false;
92f2584a
JB		 1646}
1647
040484af
JB		 1648static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649 enum pipe pipe)
1650{
1651 int reg;
5f7f726d 1652 u32 val, pipeconf_val;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1654
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1657
1658 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1659 assert_pch_pll_enabled(dev_priv,
1660 to_intel_crtc(crtc)->pch_pll,
1661 to_intel_crtc(crtc));
040484af
JB		 1662
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv, pipe);
1665 assert_fdi_rx_enabled(dev_priv, pipe);
1666
59c859d6
ED		 1667 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 return;
1670 }
040484af
JB		 1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
5f7f726d 1673 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
1680 val &= ~PIPE_BPC_MASK;
5f7f726d 1681 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1682 }
5f7f726d
PZ		 1683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1691 else
1692 val |= TRANS_PROGRESSIVE;
1693
040484af
JB		 1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697}
1698
1699static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
1702 int reg;
1703 u32 val;
1704
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv, pipe);
1707 assert_fdi_rx_disabled(dev_priv, pipe);
1708
291906f1
JB		 1709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv, pipe);
1711
040484af
JB		 1712 reg = TRANSCONF(pipe);
1713 val = I915_READ(reg);
1714 val &= ~TRANS_ENABLE;
1715 I915_WRITE(reg, val);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1718 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1719}
1720
b24e7179 1721/**
309cfea8 1722 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
040484af 1725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1726 *
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729 *
1730 * @pipe should be %PIPE_A or %PIPE_B.
1731 *
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 * returning.
1734 */
040484af
JB		 1735static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736 bool pch_port)
b24e7179
JB		 1737{
1738 int reg;
1739 u32 val;
1740
1741 /*
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 * need the check.
1745 */
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1747 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1748 else {
1749 if (pch_port) {
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753 }
1754 /* FIXME: assert CPU port conditions for SNB+ */
1755 }
b24e7179
JB		 1756
1757 reg = PIPECONF(pipe);
1758 val = I915_READ(reg);
00d70b15
CW		 1759 if (val & PIPECONF_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1763 intel_wait_for_vblank(dev_priv->dev, pipe);
1764}
1765
1766/**
309cfea8 1767 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1770 *
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773 *
1774 * @pipe should be %PIPE_A or %PIPE_B.
1775 *
1776 * Will wait until the pipe has shut down before returning.
1777 */
1778static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779 enum pipe pipe)
1780{
1781 int reg;
1782 u32 val;
1783
1784 /*
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1787 */
1788 assert_planes_disabled(dev_priv, pipe);
1789
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792 return;
1793
1794 reg = PIPECONF(pipe);
1795 val = I915_READ(reg);
00d70b15
CW		 1796 if ((val & PIPECONF_ENABLE) == 0)
1797 return;
1798
1799 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1800 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801}
1802
d74362c9
KP		 1803/*
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1806 */
6f1d69b0 1807void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1808 enum plane plane)
1809{
1810 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812}
1813
b24e7179
JB		 1814/**
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1819 *
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1821 */
1822static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823 enum plane plane, enum pipe pipe)
1824{
1825 int reg;
1826 u32 val;
1827
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv, pipe);
1830
1831 reg = DSPCNTR(plane);
1832 val = I915_READ(reg);
00d70b15
CW		 1833 if (val & DISPLAY_PLANE_ENABLE)
1834 return;
1835
1836 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1837 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1838 intel_wait_for_vblank(dev_priv->dev, pipe);
1839}
1840
b24e7179
JB		 1841/**
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1846 *
1847 * Disable @plane; should be an independent operation.
1848 */
1849static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850 enum plane plane, enum pipe pipe)
1851{
1852 int reg;
1853 u32 val;
1854
1855 reg = DSPCNTR(plane);
1856 val = I915_READ(reg);
00d70b15
CW		 1857 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858 return;
1859
1860 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1861 intel_flush_display_plane(dev_priv, plane);
1862 intel_wait_for_vblank(dev_priv->dev, pipe);
1863}
1864
127bd2ac 1865int
48b956c5 1866intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1867 struct drm_i915_gem_object *obj,
919926ae 1868 struct intel_ring_buffer *pipelined)
6b95a207 1869{
ce453d81 1870 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1871 u32 alignment;
1872 int ret;
1873
05394f39 1874 switch (obj->tiling_mode) {
6b95a207 1875 case I915_TILING_NONE:
534843da
CW		 1876 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877 alignment = 128 * 1024;
a6c45cf0 1878 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1879 alignment = 4 * 1024;
1880 else
1881 alignment = 64 * 1024;
6b95a207
KH		 1882 break;
1883 case I915_TILING_X:
1884 /* pin() will align the object as required by fence */
1885 alignment = 0;
1886 break;
1887 case I915_TILING_Y:
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890 return -EINVAL;
1891 default:
1892 BUG();
1893 }
1894
ce453d81 1895 dev_priv->mm.interruptible = false;
2da3b9b9 1896 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1897 if (ret)
ce453d81 1898 goto err_interruptible;
6b95a207
KH		 1899
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1904 */
06d98131 1905 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1906 if (ret)
1907 goto err_unpin;
1690e1eb 1908
9a5a53b3 1909 i915_gem_object_pin_fence(obj);
6b95a207 1910
ce453d81 1911 dev_priv->mm.interruptible = true;
6b95a207 1912 return 0;
48b956c5
CW		 1913
1914err_unpin:
1915 i915_gem_object_unpin(obj);
ce453d81
CW		 1916err_interruptible:
1917 dev_priv->mm.interruptible = true;
48b956c5 1918 return ret;
6b95a207
KH		 1919}
1920
1690e1eb
CW		 1921void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922{
1923 i915_gem_object_unpin_fence(obj);
1924 i915_gem_object_unpin(obj);
1925}
1926
c2c75131
DV		 1927/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930 unsigned int bpp,
1931 unsigned int pitch)
1932{
1933 int tile_rows, tiles;
1934
1935 tile_rows = *y / 8;
1936 *y %= 8;
1937 tiles = *x / (512/bpp);
1938 *x %= 512/bpp;
1939
1940 return tile_rows * pitch * 8 + tiles * 4096;
1941}
1942
17638cd6
JB		 1943static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
81255565
JB		 1945{
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
05394f39 1950 struct drm_i915_gem_object *obj;
81255565 1951 int plane = intel_crtc->plane;
e506a0c6 1952 unsigned long linear_offset;
81255565 1953 u32 dspcntr;
5eddb70b 1954 u32 reg;
81255565
JB		 1955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
81255565 1967
5eddb70b
CW		 1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
81255565
JB		 1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1973 case 8:
1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
1976 case 16:
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1979 else
1980 dspcntr |= DISPPLANE_16BPP;
1981 break;
1982 case 24:
1983 case 32:
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985 break;
1986 default:
17638cd6 1987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1988 return -EINVAL;
1989 }
a6c45cf0 1990 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1991 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1992 dspcntr |= DISPPLANE_TILED;
1993 else
1994 dspcntr &= ~DISPPLANE_TILED;
1995 }
1996
5eddb70b 1997 I915_WRITE(reg, dspcntr);
81255565 1998
e506a0c6 1999 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2000
c2c75131
DV		 2001 if (INTEL_INFO(dev)->gen >= 4) {
2002 intel_crtc->dspaddr_offset =
2003 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004 fb->bits_per_pixel / 8,
2005 fb->pitches[0]);
2006 linear_offset -= intel_crtc->dspaddr_offset;
2007 } else {
e506a0c6 2008 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2009 }
e506a0c6
DV		 2010
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2013 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2014 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2015 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2017 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2018 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2019 } else
e506a0c6 2020 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2021 POSTING_READ(reg);
81255565 2022
17638cd6
JB		 2023 return 0;
2024}
2025
2026static int ironlake_update_plane(struct drm_crtc *crtc,
2027 struct drm_framebuffer *fb, int x, int y)
2028{
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 struct intel_framebuffer *intel_fb;
2033 struct drm_i915_gem_object *obj;
2034 int plane = intel_crtc->plane;
e506a0c6 2035 unsigned long linear_offset;
17638cd6
JB		 2036 u32 dspcntr;
2037 u32 reg;
2038
2039 switch (plane) {
2040 case 0:
2041 case 1:
27f8227b 2042 case 2:
17638cd6
JB		 2043 break;
2044 default:
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046 return -EINVAL;
2047 }
2048
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2051
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2057 case 8:
2058 dspcntr |= DISPPLANE_8BPP;
2059 break;
2060 case 16:
2061 if (fb->depth != 16)
2062 return -EINVAL;
2063
2064 dspcntr |= DISPPLANE_16BPP;
2065 break;
2066 case 24:
2067 case 32:
2068 if (fb->depth == 24)
2069 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070 else if (fb->depth == 30)
2071 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072 else
2073 return -EINVAL;
2074 break;
2075 default:
2076 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077 return -EINVAL;
2078 }
2079
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084
2085 /* must disable */
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088 I915_WRITE(reg, dspcntr);
2089
e506a0c6 2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2091 intel_crtc->dspaddr_offset =
2092 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
2095 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2096
e506a0c6
DV		 2097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2099 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2103 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2104 POSTING_READ(reg);
2105
2106 return 0;
2107}
2108
2109/* Assume fb object is pinned & idle & fenced and just update base pointers */
2110static int
2111intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2113{
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2116
6b8e6ed0
CW		 2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
3dec0095 2119 intel_increase_pllclock(crtc);
81255565 2120
6b8e6ed0 2121 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2122}
2123
14667a4b
CW		 2124static int
2125intel_finish_fb(struct drm_framebuffer *old_fb)
2126{
2127 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 bool was_interruptible = dev_priv->mm.interruptible;
2130 int ret;
2131
2132 wait_event(dev_priv->pending_flip_queue,
2133 atomic_read(&dev_priv->mm.wedged) ||
2134 atomic_read(&obj->pending_flip) == 0);
2135
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2139 * framebuffer.
2140 *
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2143 */
2144 dev_priv->mm.interruptible = false;
2145 ret = i915_gem_object_finish_gpu(obj);
2146 dev_priv->mm.interruptible = was_interruptible;
2147
2148 return ret;
2149}
2150
5c3b82e2 2151static int
3c4fdcfb 2152intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2153 struct drm_framebuffer *fb)
79e53945
JB		 2154{
2155 struct drm_device *dev = crtc->dev;
6b8e6ed0 2156 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2157 struct drm_i915_master_private *master_priv;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2159 struct drm_framebuffer *old_fb;
5c3b82e2 2160 int ret;
79e53945
JB		 2161
2162 /* no fb bound */
94352cf9 2163 if (!fb) {
a5071c2f 2164 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2165 return 0;
2166 }
2167
5826eca5
ED		 2168 if(intel_crtc->plane > dev_priv->num_pipe) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170 intel_crtc->plane,
2171 dev_priv->num_pipe);
5c3b82e2 2172 return -EINVAL;
79e53945
JB		 2173 }
2174
5c3b82e2 2175 mutex_lock(&dev->struct_mutex);
265db958 2176 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2177 to_intel_framebuffer(fb)->obj,
919926ae 2178 NULL);
5c3b82e2
CW		 2179 if (ret != 0) {
2180 mutex_unlock(&dev->struct_mutex);
a5071c2f 2181 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2182 return ret;
2183 }
79e53945 2184
94352cf9
DV		 2185 if (crtc->fb)
2186 intel_finish_fb(crtc->fb);
265db958 2187
94352cf9 2188 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2189 if (ret) {
94352cf9 2190 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2191 mutex_unlock(&dev->struct_mutex);
a5071c2f 2192 DRM_ERROR("failed to update base address\n");
4e6cfefc 2193 return ret;
79e53945 2194 }
3c4fdcfb 2195
94352cf9
DV		 2196 old_fb = crtc->fb;
2197 crtc->fb = fb;
6c4c86f5
DV		 2198 crtc->x = x;
2199 crtc->y = y;
94352cf9 2200
b7f1de28
CW		 2201 if (old_fb) {
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2204 }
652c393a 2205
6b8e6ed0 2206 intel_update_fbc(dev);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2208
2209 if (!dev->primary->master)
5c3b82e2 2210 return 0;
79e53945
JB		 2211
2212 master_priv = dev->primary->master->driver_priv;
2213 if (!master_priv->sarea_priv)
5c3b82e2 2214 return 0;
79e53945 2215
265db958 2216 if (intel_crtc->pipe) {
79e53945
JB		 2217 master_priv->sarea_priv->pipeB_x = x;
2218 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2219 } else {
2220 master_priv->sarea_priv->pipeA_x = x;
2221 master_priv->sarea_priv->pipeA_y = y;
79e53945 2222 }
5c3b82e2
CW		 2223
2224 return 0;
79e53945
JB		 2225}
2226
5eddb70b 2227static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2228{
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 u32 dpa_ctl;
2232
28c97730 2233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2234 dpa_ctl = I915_READ(DP_A);
2235 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237 if (clock < 200000) {
2238 u32 temp;
2239 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2245 */
2246 temp = I915_READ(0x4600c);
2247 temp &= 0xffff0000;
2248 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250 temp = I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp | 1);
2252
2253 temp = I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp | (1 << 24));
2255 } else {
2256 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257 }
2258 I915_WRITE(DP_A, dpa_ctl);
2259
5eddb70b 2260 POSTING_READ(DP_A);
32f9d658
ZW		 2261 udelay(500);
2262}
2263
5e84e1a4
ZW		 2264static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265{
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 int pipe = intel_crtc->pipe;
2270 u32 reg, temp;
2271
2272 /* enable normal train */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
61e499bf 2275 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2278 } else {
2279 temp &= ~FDI_LINK_TRAIN_NONE;
2280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2281 }
5e84e1a4
ZW		 2282 I915_WRITE(reg, temp);
2283
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289 } else {
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_NONE;
2292 }
2293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295 /* wait one idle pattern time */
2296 POSTING_READ(reg);
2297 udelay(1000);
357555c0
JB		 2298
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev))
2301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2303}
2304
291427f5
JB		 2305static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306{
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310 flags |= FDI_PHASE_SYNC_OVR(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312 flags |= FDI_PHASE_SYNC_EN(pipe);
2313 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1);
2315}
2316
8db9d77b
ZW		 2317/* The FDI link training functions for ILK/Ibexpeak. */
2318static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
0fc932b8 2324 int plane = intel_crtc->plane;
5eddb70b 2325 u32 reg, temp, tries;
8db9d77b 2326
0fc932b8
JB		 2327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv, pipe);
2329 assert_plane_enabled(dev_priv, plane);
2330
e1a44743
AJ		 2331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332 for train result */
5eddb70b
CW		 2333 reg = FDI_RX_IMR(pipe);
2334 temp = I915_READ(reg);
e1a44743
AJ		 2335 temp &= ~FDI_RX_SYMBOL_LOCK;
2336 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2337 I915_WRITE(reg, temp);
2338 I915_READ(reg);
e1a44743
AJ		 2339 udelay(150);
2340
8db9d77b 2341 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
77ffb597
AJ		 2344 temp &= ~(7 << 19);
2345 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2349
5eddb70b
CW		 2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
8db9d77b
ZW		 2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356 POSTING_READ(reg);
8db9d77b
ZW		 2357 udelay(150);
2358
5b2adf89 2359 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2360 if (HAS_PCH_IBX(dev)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
2364 }
5b2adf89 2365
5eddb70b 2366 reg = FDI_RX_IIR(pipe);
e1a44743 2367 for (tries = 0; tries < 5; tries++) {
5eddb70b 2368 temp = I915_READ(reg);
8db9d77b
ZW		 2369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371 if ((temp & FDI_RX_BIT_LOCK)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2373 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2374 break;
2375 }
8db9d77b 2376 }
e1a44743 2377 if (tries == 5)
5eddb70b 2378 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2379
2380 /* Train 2 */
5eddb70b
CW		 2381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2385 I915_WRITE(reg, temp);
8db9d77b 2386
5eddb70b
CW		 2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
8db9d77b
ZW		 2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2391 I915_WRITE(reg, temp);
8db9d77b 2392
5eddb70b
CW		 2393 POSTING_READ(reg);
2394 udelay(150);
8db9d77b 2395
5eddb70b 2396 reg = FDI_RX_IIR(pipe);
e1a44743 2397 for (tries = 0; tries < 5; tries++) {
5eddb70b 2398 temp = I915_READ(reg);
8db9d77b
ZW		 2399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2402 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2404 break;
2405 }
8db9d77b 2406 }
e1a44743 2407 if (tries == 5)
5eddb70b 2408 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2409
2410 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2411
8db9d77b
ZW		 2412}
2413
0206e353 2414static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2415 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419};
2420
2421/* The FDI link training functions for SNB/Cougarpoint. */
2422static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423{
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
fa37d39e 2428 u32 reg, temp, i, retry;
8db9d77b 2429
e1a44743
AJ		 2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
5eddb70b
CW		 2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
e1a44743
AJ		 2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
e1a44743
AJ		 2439 udelay(150);
2440
8db9d77b 2441 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
77ffb597
AJ		 2444 temp &= ~(7 << 19);
2445 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449 /* SNB-B */
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2452
5eddb70b
CW		 2453 reg = FDI_RX_CTL(pipe);
2454 temp = I915_READ(reg);
8db9d77b
ZW		 2455 if (HAS_PCH_CPT(dev)) {
2456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458 } else {
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461 }
5eddb70b
CW		 2462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464 POSTING_READ(reg);
8db9d77b
ZW		 2465 udelay(150);
2466
291427f5
JB		 2467 if (HAS_PCH_CPT(dev))
2468 cpt_phase_pointer_enable(dev, pipe);
2469
0206e353 2470 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
8db9d77b
ZW		 2478 udelay(500);
2479
fa37d39e
SP		 2480 for (retry = 0; retry < 5; retry++) {
2481 reg = FDI_RX_IIR(pipe);
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484 if (temp & FDI_RX_BIT_LOCK) {
2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487 break;
2488 }
2489 udelay(50);
8db9d77b 2490 }
fa37d39e
SP		 2491 if (retry < 5)
2492 break;
8db9d77b
ZW		 2493 }
2494 if (i == 4)
5eddb70b 2495 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2496
2497 /* Train 2 */
5eddb70b
CW		 2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_2;
2502 if (IS_GEN6(dev)) {
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504 /* SNB-B */
2505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506 }
5eddb70b 2507 I915_WRITE(reg, temp);
8db9d77b 2508
5eddb70b
CW		 2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 if (HAS_PCH_CPT(dev)) {
2512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514 } else {
2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517 }
5eddb70b
CW		 2518 I915_WRITE(reg, temp);
2519
2520 POSTING_READ(reg);
8db9d77b
ZW		 2521 udelay(150);
2522
0206e353 2523 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(500);
2532
fa37d39e
SP		 2533 for (retry = 0; retry < 5; retry++) {
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540 break;
2541 }
2542 udelay(50);
8db9d77b 2543 }
fa37d39e
SP		 2544 if (retry < 5)
2545 break;
8db9d77b
ZW		 2546 }
2547 if (i == 4)
5eddb70b 2548 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2549
2550 DRM_DEBUG_KMS("FDI train done.\n");
2551}
2552
357555c0
JB		 2553/* Manual link training for Ivy Bridge A0 parts */
2554static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555{
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2560 u32 reg, temp, i;
2561
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563 for train result */
2564 reg = FDI_RX_IMR(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_RX_SYMBOL_LOCK;
2567 temp &= ~FDI_RX_BIT_LOCK;
2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
2571 udelay(150);
2572
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~(7 << 19);
2577 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2582 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_AUTO;
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2590 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593 POSTING_READ(reg);
2594 udelay(150);
2595
291427f5
JB		 2596 if (HAS_PCH_CPT(dev))
2597 cpt_phase_pointer_enable(dev, pipe);
2598
0206e353 2599 for (i = 0; i < 4; i++) {
357555c0
JB		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
2607 udelay(500);
2608
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613 if (temp & FDI_RX_BIT_LOCK ||
2614 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2617 break;
2618 }
2619 }
2620 if (i == 4)
2621 DRM_ERROR("FDI train 1 fail!\n");
2622
2623 /* Train 2 */
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp);
2631
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
0206e353 2641 for (i = 0; i < 4; i++) {
357555c0
JB		 2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(500);
2650
2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2658 break;
2659 }
2660 }
2661 if (i == 4)
2662 DRM_ERROR("FDI train 2 fail!\n");
2663
2664 DRM_DEBUG_KMS("FDI train done.\n");
2665}
2666
88cefb6c 2667static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2668{
88cefb6c 2669 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2670 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2671 int pipe = intel_crtc->pipe;
5eddb70b 2672 u32 reg, temp;
79e53945 2673
c64e311e 2674 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2675 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2677
c98e9dcf 2678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2679 reg = FDI_RX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2683 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686 POSTING_READ(reg);
c98e9dcf
JB		 2687 udelay(200);
2688
2689 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2690 temp = I915_READ(reg);
2691 I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693 POSTING_READ(reg);
c98e9dcf
JB		 2694 udelay(200);
2695
bf507ef7
ED		 2696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2704
bf507ef7
ED		 2705 POSTING_READ(reg);
2706 udelay(100);
2707 }
6be4a607 2708 }
0e23b99d
JB		 2709}
2710
88cefb6c
DV		 2711static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712{
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp;
2717
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
2729 udelay(100);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735 /* Wait for the clocks to turn off. */
2736 POSTING_READ(reg);
2737 udelay(100);
2738}
2739
291427f5
JB		 2740static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741{
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1);
2750}
0fc932b8
JB		 2751static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752{
2753 struct drm_device *dev = crtc->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756 int pipe = intel_crtc->pipe;
2757 u32 reg, temp;
2758
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763 POSTING_READ(reg);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(0x7 << 16);
2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(100);
2773
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2775 if (HAS_PCH_IBX(dev)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2777 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2779 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2780 } else if (HAS_PCH_CPT(dev)) {
2781 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2782 }
0fc932b8
JB		 2783
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799 }
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(100);
2807}
2808
e6c3a2a6
CW		 2809static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810{
0f91128d 2811 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2812
2813 if (crtc->fb == NULL)
2814 return;
2815
0f91128d
CW		 2816 mutex_lock(&dev->struct_mutex);
2817 intel_finish_fb(crtc->fb);
2818 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2819}
2820
040484af
JB		 2821static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2822{
2823 struct drm_device *dev = crtc->dev;
228d3e36 2824 struct intel_encoder *intel_encoder;
040484af
JB		 2825
2826 /*
2827 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828 * must be driven by its own crtc; no sharing is possible.
2829 */
228d3e36 2830 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2831
6ee8bab0
ED		 2832 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833 * CPU handles all others */
2834 if (IS_HASWELL(dev)) {
2835 /* It is still unclear how this will work on PPT, so throw up a warning */
2836 WARN_ON(!HAS_PCH_LPT(dev));
2837
228d3e36 2838 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2839 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2840 return true;
2841 } else {
2842 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2843 intel_encoder->type);
6ee8bab0
ED		 2844 return false;
2845 }
2846 }
2847
228d3e36 2848 switch (intel_encoder->type) {
040484af 2849 case INTEL_OUTPUT_EDP:
228d3e36 2850 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2851 return false;
2852 continue;
2853 }
2854 }
2855
2856 return true;
2857}
2858
e615efe4
ED		 2859/* Program iCLKIP clock to the desired frequency */
2860static void lpt_program_iclkip(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2865 u32 temp;
2866
2867 /* It is necessary to ungate the pixclk gate prior to programming
2868 * the divisors, and gate it back when it is done.
2869 */
2870 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2871
2872 /* Disable SSCCTL */
2873 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2874 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2875 SBI_SSCCTL_DISABLE);
2876
2877 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878 if (crtc->mode.clock == 20000) {
2879 auxdiv = 1;
2880 divsel = 0x41;
2881 phaseinc = 0x20;
2882 } else {
2883 /* The iCLK virtual clock root frequency is in MHz,
2884 * but the crtc->mode.clock in in KHz. To get the divisors,
2885 * it is necessary to divide one by another, so we
2886 * convert the virtual clock precision to KHz here for higher
2887 * precision.
2888 */
2889 u32 iclk_virtual_root_freq = 172800 * 1000;
2890 u32 iclk_pi_range = 64;
2891 u32 desired_divisor, msb_divisor_value, pi_value;
2892
2893 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2894 msb_divisor_value = desired_divisor / iclk_pi_range;
2895 pi_value = desired_divisor % iclk_pi_range;
2896
2897 auxdiv = 0;
2898 divsel = msb_divisor_value - 2;
2899 phaseinc = pi_value;
2900 }
2901
2902 /* This should not happen with any sane values */
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2904 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2905 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2906 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2907
2908 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2909 crtc->mode.clock,
2910 auxdiv,
2911 divsel,
2912 phasedir,
2913 phaseinc);
2914
2915 /* Program SSCDIVINTPHASE6 */
2916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2923
2924 intel_sbi_write(dev_priv,
2925 SBI_SSCDIVINTPHASE6,
2926 temp);
2927
2928 /* Program SSCAUXDIV */
2929 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2930 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2932 intel_sbi_write(dev_priv,
2933 SBI_SSCAUXDIV6,
2934 temp);
2935
2936
2937 /* Enable modulator and associated divider */
2938 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2939 temp &= ~SBI_SSCCTL_DISABLE;
2940 intel_sbi_write(dev_priv,
2941 SBI_SSCCTL6,
2942 temp);
2943
2944 /* Wait for initialization time */
2945 udelay(24);
2946
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948}
2949
f67a559d
JB		 2950/*
2951 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2956 * - transcoder
2957 */
2958static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
ee7b9f93 2964 u32 reg, temp;
2c07245f 2965
e7e164db
CW		 2966 assert_transcoder_disabled(dev_priv, pipe);
2967
c98e9dcf 2968 /* For PCH output, training FDI link */
674cf967 2969 dev_priv->display.fdi_link_train(crtc);
2c07245f 2970
6f13b7b5
CW		 2971 intel_enable_pch_pll(intel_crtc);
2972
e615efe4
ED		 2973 if (HAS_PCH_LPT(dev)) {
2974 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975 lpt_program_iclkip(crtc);
2976 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2977 u32 sel;
4b645f14 2978
c98e9dcf 2979 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2980 switch (pipe) {
2981 default:
2982 case 0:
2983 temp |= TRANSA_DPLL_ENABLE;
2984 sel = TRANSA_DPLLB_SEL;
2985 break;
2986 case 1:
2987 temp |= TRANSB_DPLL_ENABLE;
2988 sel = TRANSB_DPLLB_SEL;
2989 break;
2990 case 2:
2991 temp |= TRANSC_DPLL_ENABLE;
2992 sel = TRANSC_DPLLB_SEL;
2993 break;
d64311ab 2994 }
ee7b9f93
JB		 2995 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2996 temp |= sel;
2997 else
2998 temp &= ~sel;
c98e9dcf 2999 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3000 }
5eddb70b 3001
d9b6cb56
JB		 3002 /* set transcoder timing, panel must allow it */
3003 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3004 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3005 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3006 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3007
5eddb70b
CW		 3008 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3009 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3010 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3011 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3012
f57e1e3a
ED		 3013 if (!IS_HASWELL(dev))
3014 intel_fdi_normal_train(crtc);
5e84e1a4 3015
c98e9dcf
JB		 3016 /* For PCH DP, enable TRANS_DP_CTL */
3017 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3018 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3019 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3020 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3021 reg = TRANS_DP_CTL(pipe);
3022 temp = I915_READ(reg);
3023 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3024 TRANS_DP_SYNC_MASK |
3025 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3026 temp |= (TRANS_DP_OUTPUT_ENABLE |
3027 TRANS_DP_ENH_FRAMING);
9325c9f0 3028 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3029
3030 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3031 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3032 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3033 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3034
3035 switch (intel_trans_dp_port_sel(crtc)) {
3036 case PCH_DP_B:
5eddb70b 3037 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3038 break;
3039 case PCH_DP_C:
5eddb70b 3040 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3041 break;
3042 case PCH_DP_D:
5eddb70b 3043 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3044 break;
3045 default:
3046 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3047 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3048 break;
32f9d658 3049 }
2c07245f 3050
5eddb70b 3051 I915_WRITE(reg, temp);
6be4a607 3052 }
b52eb4dc 3053
040484af 3054 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3055}
3056
ee7b9f93
JB		 3057static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058{
3059 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061 if (pll == NULL)
3062 return;
3063
3064 if (pll->refcount == 0) {
3065 WARN(1, "bad PCH PLL refcount\n");
3066 return;
3067 }
3068
3069 --pll->refcount;
3070 intel_crtc->pch_pll = NULL;
3071}
3072
3073static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074{
3075 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076 struct intel_pch_pll *pll;
3077 int i;
3078
3079 pll = intel_crtc->pch_pll;
3080 if (pll) {
3081 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082 intel_crtc->base.base.id, pll->pll_reg);
3083 goto prepare;
3084 }
3085
98b6bd99
DV		 3086 if (HAS_PCH_IBX(dev_priv->dev)) {
3087 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088 i = intel_crtc->pipe;
3089 pll = &dev_priv->pch_plls[i];
3090
3091 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092 intel_crtc->base.base.id, pll->pll_reg);
3093
3094 goto found;
3095 }
3096
ee7b9f93
JB		 3097 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098 pll = &dev_priv->pch_plls[i];
3099
3100 /* Only want to check enabled timings first */
3101 if (pll->refcount == 0)
3102 continue;
3103
3104 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105 fp == I915_READ(pll->fp0_reg)) {
3106 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107 intel_crtc->base.base.id,
3108 pll->pll_reg, pll->refcount, pll->active);
3109
3110 goto found;
3111 }
3112 }
3113
3114 /* Ok no matching timings, maybe there's a free one? */
3115 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116 pll = &dev_priv->pch_plls[i];
3117 if (pll->refcount == 0) {
3118 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119 intel_crtc->base.base.id, pll->pll_reg);
3120 goto found;
3121 }
3122 }
3123
3124 return NULL;
3125
3126found:
3127 intel_crtc->pch_pll = pll;
3128 pll->refcount++;
3129 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3130prepare: /* separate function? */
3131 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3132
e04c7350
CW		 3133 /* Wait for the clocks to stabilize before rewriting the regs */
3134 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3135 POSTING_READ(pll->pll_reg);
3136 udelay(150);
e04c7350
CW		 3137
3138 I915_WRITE(pll->fp0_reg, fp);
3139 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3140 pll->on = false;
3141 return pll;
3142}
3143
d4270e57
JB		 3144void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3148 u32 temp;
3149
3150 temp = I915_READ(dslreg);
3151 udelay(500);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153 /* Without this, mode sets may fail silently on FDI */
3154 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3155 udelay(250);
3156 I915_WRITE(tc2reg, 0);
3157 if (wait_for(I915_READ(dslreg) != temp, 5))
3158 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3159 }
3160}
3161
f67a559d
JB		 3162static void ironlake_crtc_enable(struct drm_crtc *crtc)
3163{
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3167 struct intel_encoder *encoder;
f67a559d
JB		 3168 int pipe = intel_crtc->pipe;
3169 int plane = intel_crtc->plane;
3170 u32 temp;
3171 bool is_pch_port;
3172
08a48469
DV		 3173 WARN_ON(!crtc->enabled);
3174
f67a559d
JB		 3175 if (intel_crtc->active)
3176 return;
3177
3178 intel_crtc->active = true;
3179 intel_update_watermarks(dev);
3180
3181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3182 temp = I915_READ(PCH_LVDS);
3183 if ((temp & LVDS_PORT_EN) == 0)
3184 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3185 }
3186
3187 is_pch_port = intel_crtc_driving_pch(crtc);
3188
46b6f814 3189 if (is_pch_port) {
88cefb6c 3190 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3191 } else {
3192 assert_fdi_tx_disabled(dev_priv, pipe);
3193 assert_fdi_rx_disabled(dev_priv, pipe);
3194 }
f67a559d 3195
bf49ec8c
DV		 3196 for_each_encoder_on_crtc(dev, crtc, encoder)
3197 if (encoder->pre_enable)
3198 encoder->pre_enable(encoder);
3199
fc914639
PZ		 3200 if (IS_HASWELL(dev))
3201 intel_ddi_enable_pipe_clock(intel_crtc);
3202
f67a559d
JB		 3203 /* Enable panel fitting for LVDS */
3204 if (dev_priv->pch_pf_size &&
3205 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3206 /* Force use of hard-coded filter coefficients
3207 * as some pre-programmed values are broken,
3208 * e.g. x201.
3209 */
9db4a9c7
JB		 3210 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3211 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3212 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3213 }
3214
9c54c0dd
JB		 3215 /*
3216 * On ILK+ LUT must be loaded before the pipe is running but with
3217 * clocks enabled
3218 */
3219 intel_crtc_load_lut(crtc);
3220
8d9ddbcb
PZ		 3221 if (IS_HASWELL(dev))
3222 intel_ddi_enable_pipe_func(crtc);
3223
f67a559d
JB		 3224 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3225 intel_enable_plane(dev_priv, plane, pipe);
3226
3227 if (is_pch_port)
3228 ironlake_pch_enable(crtc);
c98e9dcf 3229
d1ebd816 3230 mutex_lock(&dev->struct_mutex);
bed4a673 3231 intel_update_fbc(dev);
d1ebd816
BW		 3232 mutex_unlock(&dev->struct_mutex);
3233
6b383a7f 3234 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3235
fa5c73b1
DV		 3236 for_each_encoder_on_crtc(dev, crtc, encoder)
3237 encoder->enable(encoder);
61b77ddd
DV		 3238
3239 if (HAS_PCH_CPT(dev))
3240 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3241}
3242
3243static void ironlake_crtc_disable(struct drm_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3248 struct intel_encoder *encoder;
6be4a607
JB		 3249 int pipe = intel_crtc->pipe;
3250 int plane = intel_crtc->plane;
5eddb70b 3251 u32 reg, temp;
b52eb4dc 3252
ef9c3aee 3253
f7abfe8b
CW		 3254 if (!intel_crtc->active)
3255 return;
3256
ea9d758d
DV		 3257 for_each_encoder_on_crtc(dev, crtc, encoder)
3258 encoder->disable(encoder);
3259
e6c3a2a6 3260 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3261 drm_vblank_off(dev, pipe);
6b383a7f 3262 intel_crtc_update_cursor(crtc, false);
5eddb70b 3263
b24e7179 3264 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3265
973d04f9
CW		 3266 if (dev_priv->cfb_plane == plane)
3267 intel_disable_fbc(dev);
2c07245f 3268
b24e7179 3269 intel_disable_pipe(dev_priv, pipe);
32f9d658 3270
8d9ddbcb
PZ		 3271 if (IS_HASWELL(dev))
3272 intel_ddi_disable_pipe_func(dev_priv, pipe);
3273
6be4a607 3274 /* Disable PF */
9db4a9c7
JB		 3275 I915_WRITE(PF_CTL(pipe), 0);
3276 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3277
fc914639
PZ		 3278 if (IS_HASWELL(dev))
3279 intel_ddi_disable_pipe_clock(intel_crtc);
3280
bf49ec8c
DV		 3281 for_each_encoder_on_crtc(dev, crtc, encoder)
3282 if (encoder->post_disable)
3283 encoder->post_disable(encoder);
3284
0fc932b8 3285 ironlake_fdi_disable(crtc);
2c07245f 3286
040484af 3287 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3288
6be4a607
JB		 3289 if (HAS_PCH_CPT(dev)) {
3290 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3291 reg = TRANS_DP_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3294 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3295 I915_WRITE(reg, temp);
6be4a607
JB		 3296
3297 /* disable DPLL_SEL */
3298 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3299 switch (pipe) {
3300 case 0:
d64311ab 3301 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3302 break;
3303 case 1:
6be4a607 3304 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3305 break;
3306 case 2:
4b645f14 3307 /* C shares PLL A or B */
d64311ab 3308 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3309 break;
3310 default:
3311 BUG(); /* wtf */
3312 }
6be4a607 3313 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3314 }
e3421a18 3315
6be4a607 3316 /* disable PCH DPLL */
ee7b9f93 3317 intel_disable_pch_pll(intel_crtc);
8db9d77b 3318
88cefb6c 3319 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3320
f7abfe8b 3321 intel_crtc->active = false;
6b383a7f 3322 intel_update_watermarks(dev);
d1ebd816
BW		 3323
3324 mutex_lock(&dev->struct_mutex);
6b383a7f 3325 intel_update_fbc(dev);
d1ebd816 3326 mutex_unlock(&dev->struct_mutex);
6be4a607 3327}
1b3c7a47 3328
ee7b9f93
JB		 3329static void ironlake_crtc_off(struct drm_crtc *crtc)
3330{
3331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332 intel_put_pch_pll(intel_crtc);
3333}
3334
02e792fb
DV		 3335static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3336{
02e792fb 3337 if (!enable && intel_crtc->overlay) {
23f09ce3 3338 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3339 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3340
23f09ce3 3341 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3342 dev_priv->mm.interruptible = false;
3343 (void) intel_overlay_switch_off(intel_crtc->overlay);
3344 dev_priv->mm.interruptible = true;
23f09ce3 3345 mutex_unlock(&dev->struct_mutex);
02e792fb 3346 }
02e792fb 3347
5dcdbcb0
CW		 3348 /* Let userspace switch the overlay on again. In most cases userspace
3349 * has to recompute where to put it anyway.
3350 */
02e792fb
DV		 3351}
3352
0b8765c6 3353static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3354{
3355 struct drm_device *dev = crtc->dev;
79e53945
JB		 3356 struct drm_i915_private *dev_priv = dev->dev_private;
3357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3358 struct intel_encoder *encoder;
79e53945 3359 int pipe = intel_crtc->pipe;
80824003 3360 int plane = intel_crtc->plane;
79e53945 3361
08a48469
DV		 3362 WARN_ON(!crtc->enabled);
3363
f7abfe8b
CW		 3364 if (intel_crtc->active)
3365 return;
3366
3367 intel_crtc->active = true;
6b383a7f
CW		 3368 intel_update_watermarks(dev);
3369
63d7bbe9 3370 intel_enable_pll(dev_priv, pipe);
040484af 3371 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3372 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3373
0b8765c6 3374 intel_crtc_load_lut(crtc);
bed4a673 3375 intel_update_fbc(dev);
79e53945 3376
0b8765c6
JB		 3377 /* Give the overlay scaler a chance to enable if it's on this pipe */
3378 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3379 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3380
fa5c73b1
DV		 3381 for_each_encoder_on_crtc(dev, crtc, encoder)
3382 encoder->enable(encoder);
0b8765c6 3383}
79e53945 3384
0b8765c6
JB		 3385static void i9xx_crtc_disable(struct drm_crtc *crtc)
3386{
3387 struct drm_device *dev = crtc->dev;
3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3390 struct intel_encoder *encoder;
0b8765c6
JB		 3391 int pipe = intel_crtc->pipe;
3392 int plane = intel_crtc->plane;
b690e96c 3393
ef9c3aee 3394
f7abfe8b
CW		 3395 if (!intel_crtc->active)
3396 return;
3397
ea9d758d
DV		 3398 for_each_encoder_on_crtc(dev, crtc, encoder)
3399 encoder->disable(encoder);
3400
0b8765c6 3401 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3402 intel_crtc_wait_for_pending_flips(crtc);
3403 drm_vblank_off(dev, pipe);
0b8765c6 3404 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3405 intel_crtc_update_cursor(crtc, false);
0b8765c6 3406
973d04f9
CW		 3407 if (dev_priv->cfb_plane == plane)
3408 intel_disable_fbc(dev);
79e53945 3409
b24e7179 3410 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3411 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3412 intel_disable_pll(dev_priv, pipe);
0b8765c6 3413
f7abfe8b 3414 intel_crtc->active = false;
6b383a7f
CW		 3415 intel_update_fbc(dev);
3416 intel_update_watermarks(dev);
0b8765c6
JB		 3417}
3418
ee7b9f93
JB		 3419static void i9xx_crtc_off(struct drm_crtc *crtc)
3420{
3421}
3422
976f8a20
DV		 3423static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3424 bool enabled)
2c07245f
ZW		 3425{
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_master_private *master_priv;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429 int pipe = intel_crtc->pipe;
79e53945
JB		 3430
3431 if (!dev->primary->master)
3432 return;
3433
3434 master_priv = dev->primary->master->driver_priv;
3435 if (!master_priv->sarea_priv)
3436 return;
3437
79e53945
JB		 3438 switch (pipe) {
3439 case 0:
3440 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3441 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3442 break;
3443 case 1:
3444 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3445 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3446 break;
3447 default:
9db4a9c7 3448 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3449 break;
3450 }
79e53945
JB		 3451}
3452
976f8a20
DV		 3453/**
3454 * Sets the power management mode of the pipe and plane.
3455 */
3456void intel_crtc_update_dpms(struct drm_crtc *crtc)
3457{
3458 struct drm_device *dev = crtc->dev;
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460 struct intel_encoder *intel_encoder;
3461 bool enable = false;
3462
3463 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3464 enable |= intel_encoder->connectors_active;
3465
3466 if (enable)
3467 dev_priv->display.crtc_enable(crtc);
3468 else
3469 dev_priv->display.crtc_disable(crtc);
3470
3471 intel_crtc_update_sarea(crtc, enable);
3472}
3473
3474static void intel_crtc_noop(struct drm_crtc *crtc)
3475{
3476}
3477
cdd59983
CW		 3478static void intel_crtc_disable(struct drm_crtc *crtc)
3479{
cdd59983 3480 struct drm_device *dev = crtc->dev;
976f8a20 3481 struct drm_connector *connector;
ee7b9f93 3482 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3483
976f8a20
DV		 3484 /* crtc should still be enabled when we disable it. */
3485 WARN_ON(!crtc->enabled);
3486
3487 dev_priv->display.crtc_disable(crtc);
3488 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3489 dev_priv->display.off(crtc);
3490
931872fc
CW		 3491 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3492 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3493
3494 if (crtc->fb) {
3495 mutex_lock(&dev->struct_mutex);
1690e1eb 3496 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3497 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3498 crtc->fb = NULL;
3499 }
3500
3501 /* Update computed state. */
3502 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3503 if (!connector->encoder || !connector->encoder->crtc)
3504 continue;
3505
3506 if (connector->encoder->crtc != crtc)
3507 continue;
3508
3509 connector->dpms = DRM_MODE_DPMS_OFF;
3510 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3511 }
3512}
3513
a261b246 3514void intel_modeset_disable(struct drm_device *dev)
79e53945 3515{
a261b246
DV		 3516 struct drm_crtc *crtc;
3517
3518 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3519 if (crtc->enabled)
3520 intel_crtc_disable(crtc);
3521 }
79e53945
JB		 3522}
3523
1f703855 3524void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3525{
7e7d76c3
JB		 3526}
3527
ea5b213a 3528void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3529{
4ef69c7a 3530 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3531
ea5b213a
CW		 3532 drm_encoder_cleanup(encoder);
3533 kfree(intel_encoder);
7e7d76c3
JB		 3534}
3535
5ab432ef
DV		 3536/* Simple dpms helper for encodres with just one connector, no cloning and only
3537 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3538 * state of the entire output pipe. */
3539void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3540{
5ab432ef
DV		 3541 if (mode == DRM_MODE_DPMS_ON) {
3542 encoder->connectors_active = true;
3543
b2cabb0e 3544 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3545 } else {
3546 encoder->connectors_active = false;
3547
b2cabb0e 3548 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3549 }
79e53945
JB		 3550}
3551
0a91ca29
DV		 3552/* Cross check the actual hw state with our own modeset state tracking (and it's
3553 * internal consistency). */
b980514c 3554static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3555{
0a91ca29
DV		 3556 if (connector->get_hw_state(connector)) {
3557 struct intel_encoder *encoder = connector->encoder;
3558 struct drm_crtc *crtc;
3559 bool encoder_enabled;
3560 enum pipe pipe;
3561
3562 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3563 connector->base.base.id,
3564 drm_get_connector_name(&connector->base));
3565
3566 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3567 "wrong connector dpms state\n");
3568 WARN(connector->base.encoder != &encoder->base,
3569 "active connector not linked to encoder\n");
3570 WARN(!encoder->connectors_active,
3571 "encoder->connectors_active not set\n");
3572
3573 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3574 WARN(!encoder_enabled, "encoder not enabled\n");
3575 if (WARN_ON(!encoder->base.crtc))
3576 return;
3577
3578 crtc = encoder->base.crtc;
3579
3580 WARN(!crtc->enabled, "crtc not enabled\n");
3581 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3582 WARN(pipe != to_intel_crtc(crtc)->pipe,
3583 "encoder active on the wrong pipe\n");
3584 }
79e53945
JB		 3585}
3586
5ab432ef
DV		 3587/* Even simpler default implementation, if there's really no special case to
3588 * consider. */
3589void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3590{
5ab432ef 3591 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3592
5ab432ef
DV		 3593 /* All the simple cases only support two dpms states. */
3594 if (mode != DRM_MODE_DPMS_ON)
3595 mode = DRM_MODE_DPMS_OFF;
d4270e57 3596
5ab432ef
DV		 3597 if (mode == connector->dpms)
3598 return;
3599
3600 connector->dpms = mode;
3601
3602 /* Only need to change hw state when actually enabled */
3603 if (encoder->base.crtc)
3604 intel_encoder_dpms(encoder, mode);
3605 else
8af6cf88 3606 WARN_ON(encoder->connectors_active != false);
0a91ca29 3607
b980514c 3608 intel_modeset_check_state(connector->dev);
79e53945
JB		 3609}
3610
f0947c37
DV		 3611/* Simple connector->get_hw_state implementation for encoders that support only
3612 * one connector and no cloning and hence the encoder state determines the state
3613 * of the connector. */
3614bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3615{
24929352 3616 enum pipe pipe = 0;
f0947c37 3617 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3618
f0947c37 3619 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3620}
3621
79e53945 3622static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3623 const struct drm_display_mode *mode,
79e53945
JB		 3624 struct drm_display_mode *adjusted_mode)
3625{
2c07245f 3626 struct drm_device *dev = crtc->dev;
89749350 3627
bad720ff 3628 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3629 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3630 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3631 return false;
2c07245f 3632 }
89749350 3633
f9bef081
DV		 3634 /* All interlaced capable intel hw wants timings in frames. Note though
3635 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3636 * timings, so we need to be careful not to clobber these.*/
3637 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3638 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3639
44f46b42
CW		 3640 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3641 * with a hsync front porch of 0.
3642 */
3643 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3644 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3645 return false;
3646
79e53945
JB		 3647 return true;
3648}
3649
25eb05fc
JB		 3650static int valleyview_get_display_clock_speed(struct drm_device *dev)
3651{
3652 return 400000; /* FIXME */
3653}
3654
e70236a8
JB		 3655static int i945_get_display_clock_speed(struct drm_device *dev)
3656{
3657 return 400000;
3658}
79e53945 3659
e70236a8 3660static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3661{
e70236a8
JB		 3662 return 333000;
3663}
79e53945 3664
e70236a8
JB		 3665static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3666{
3667 return 200000;
3668}
79e53945 3669
e70236a8
JB		 3670static int i915gm_get_display_clock_speed(struct drm_device *dev)
3671{
3672 u16 gcfgc = 0;
79e53945 3673
e70236a8
JB		 3674 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3675
3676 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3677 return 133000;
3678 else {
3679 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3680 case GC_DISPLAY_CLOCK_333_MHZ:
3681 return 333000;
3682 default:
3683 case GC_DISPLAY_CLOCK_190_200_MHZ:
3684 return 190000;
79e53945 3685 }
e70236a8
JB		 3686 }
3687}
3688
3689static int i865_get_display_clock_speed(struct drm_device *dev)
3690{
3691 return 266000;
3692}
3693
3694static int i855_get_display_clock_speed(struct drm_device *dev)
3695{
3696 u16 hpllcc = 0;
3697 /* Assume that the hardware is in the high speed state. This
3698 * should be the default.
3699 */
3700 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3701 case GC_CLOCK_133_200:
3702 case GC_CLOCK_100_200:
3703 return 200000;
3704 case GC_CLOCK_166_250:
3705 return 250000;
3706 case GC_CLOCK_100_133:
79e53945 3707 return 133000;
e70236a8 3708 }
79e53945 3709
e70236a8
JB		 3710 /* Shouldn't happen */
3711 return 0;
3712}
79e53945 3713
e70236a8
JB		 3714static int i830_get_display_clock_speed(struct drm_device *dev)
3715{
3716 return 133000;
79e53945
JB		 3717}
3718
2c07245f
ZW		 3719struct fdi_m_n {
3720 u32 tu;
3721 u32 gmch_m;
3722 u32 gmch_n;
3723 u32 link_m;
3724 u32 link_n;
3725};
3726
3727static void
3728fdi_reduce_ratio(u32 *num, u32 *den)
3729{
3730 while (*num > 0xffffff || *den > 0xffffff) {
3731 *num >>= 1;
3732 *den >>= 1;
3733 }
3734}
3735
2c07245f 3736static void
f2b115e6
AJ		 3737ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3738 int link_clock, struct fdi_m_n *m_n)
2c07245f 3739{
2c07245f
ZW		 3740 m_n->tu = 64; /* default size */
3741
22ed1113
CW		 3742 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3743 m_n->gmch_m = bits_per_pixel * pixel_clock;
3744 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3745 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3746
22ed1113
CW		 3747 m_n->link_m = pixel_clock;
3748 m_n->link_n = link_clock;
2c07245f
ZW		 3749 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3750}
3751
a7615030
CW		 3752static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3753{
72bbe58c
KP		 3754 if (i915_panel_use_ssc >= 0)
3755 return i915_panel_use_ssc != 0;
3756 return dev_priv->lvds_use_ssc
435793df 3757 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3758}
3759
5a354204
JB		 3760/**
3761 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3762 * @crtc: CRTC structure
3b5c78a3 3763 * @mode: requested mode
5a354204
JB		 3764 *
3765 * A pipe may be connected to one or more outputs. Based on the depth of the
3766 * attached framebuffer, choose a good color depth to use on the pipe.
3767 *
3768 * If possible, match the pipe depth to the fb depth. In some cases, this
3769 * isn't ideal, because the connected output supports a lesser or restricted
3770 * set of depths. Resolve that here:
3771 * LVDS typically supports only 6bpc, so clamp down in that case
3772 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3773 * Displays may support a restricted set as well, check EDID and clamp as
3774 * appropriate.
3b5c78a3 3775 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3776 *
3777 * RETURNS:
3778 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3779 * true if they don't match).
3780 */
3781static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3782 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3783 unsigned int *pipe_bpp,
3784 struct drm_display_mode *mode)
5a354204
JB		 3785{
3786 struct drm_device *dev = crtc->dev;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3788 struct drm_connector *connector;
6c2b7c12 3789 struct intel_encoder *intel_encoder;
5a354204
JB		 3790 unsigned int display_bpc = UINT_MAX, bpc;
3791
3792 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3793 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3794
3795 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3796 unsigned int lvds_bpc;
3797
3798 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3799 LVDS_A3_POWER_UP)
3800 lvds_bpc = 8;
3801 else
3802 lvds_bpc = 6;
3803
3804 if (lvds_bpc < display_bpc) {
82820490 3805 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3806 display_bpc = lvds_bpc;
3807 }
3808 continue;
3809 }
3810
5a354204
JB		 3811 /* Not one of the known troublemakers, check the EDID */
3812 list_for_each_entry(connector, &dev->mode_config.connector_list,
3813 head) {
6c2b7c12 3814 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3815 continue;
3816
62ac41a6
JB		 3817 /* Don't use an invalid EDID bpc value */
3818 if (connector->display_info.bpc &&
3819 connector->display_info.bpc < display_bpc) {
82820490 3820 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3821 display_bpc = connector->display_info.bpc;
3822 }
3823 }
3824
3825 /*
3826 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3827 * through, clamp it down. (Note: >12bpc will be caught below.)
3828 */
3829 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3830 if (display_bpc > 8 && display_bpc < 12) {
82820490 3831 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3832 display_bpc = 12;
3833 } else {
82820490 3834 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3835 display_bpc = 8;
3836 }
3837 }
3838 }
3839
3b5c78a3
AJ		 3840 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3841 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3842 display_bpc = 6;
3843 }
3844
5a354204
JB		 3845 /*
3846 * We could just drive the pipe at the highest bpc all the time and
3847 * enable dithering as needed, but that costs bandwidth. So choose
3848 * the minimum value that expresses the full color range of the fb but
3849 * also stays within the max display bpc discovered above.
3850 */
3851
94352cf9 3852 switch (fb->depth) {
5a354204
JB		 3853 case 8:
3854 bpc = 8; /* since we go through a colormap */
3855 break;
3856 case 15:
3857 case 16:
3858 bpc = 6; /* min is 18bpp */
3859 break;
3860 case 24:
578393cd 3861 bpc = 8;
5a354204
JB		 3862 break;
3863 case 30:
578393cd 3864 bpc = 10;
5a354204
JB		 3865 break;
3866 case 48:
578393cd 3867 bpc = 12;
5a354204
JB		 3868 break;
3869 default:
3870 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3871 bpc = min((unsigned int)8, display_bpc);
3872 break;
3873 }
3874
578393cd
KP		 3875 display_bpc = min(display_bpc, bpc);
3876
82820490
AJ		 3877 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3878 bpc, display_bpc);
5a354204 3879
578393cd 3880 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3881
3882 return display_bpc != bpc;
3883}
3884
a0c4da24
JB		 3885static int vlv_get_refclk(struct drm_crtc *crtc)
3886{
3887 struct drm_device *dev = crtc->dev;
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 int refclk = 27000; /* for DP & HDMI */
3890
3891 return 100000; /* only one validated so far */
3892
3893 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3894 refclk = 96000;
3895 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3896 if (intel_panel_use_ssc(dev_priv))
3897 refclk = 100000;
3898 else
3899 refclk = 96000;
3900 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3901 refclk = 100000;
3902 }
3903
3904 return refclk;
3905}
3906
c65d77d8
JB		 3907static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3908{
3909 struct drm_device *dev = crtc->dev;
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911 int refclk;
3912
a0c4da24
JB		 3913 if (IS_VALLEYVIEW(dev)) {
3914 refclk = vlv_get_refclk(crtc);
3915 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3916 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3917 refclk = dev_priv->lvds_ssc_freq * 1000;
3918 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3919 refclk / 1000);
3920 } else if (!IS_GEN2(dev)) {
3921 refclk = 96000;
3922 } else {
3923 refclk = 48000;
3924 }
3925
3926 return refclk;
3927}
3928
3929static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3930 intel_clock_t *clock)
3931{
3932 /* SDVO TV has fixed PLL values depend on its clock range,
3933 this mirrors vbios setting. */
3934 if (adjusted_mode->clock >= 100000
3935 && adjusted_mode->clock < 140500) {
3936 clock->p1 = 2;
3937 clock->p2 = 10;
3938 clock->n = 3;
3939 clock->m1 = 16;
3940 clock->m2 = 8;
3941 } else if (adjusted_mode->clock >= 140500
3942 && adjusted_mode->clock <= 200000) {
3943 clock->p1 = 1;
3944 clock->p2 = 10;
3945 clock->n = 6;
3946 clock->m1 = 12;
3947 clock->m2 = 8;
3948 }
3949}
3950
a7516a05
JB		 3951static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3952 intel_clock_t *clock,
3953 intel_clock_t *reduced_clock)
3954{
3955 struct drm_device *dev = crtc->dev;
3956 struct drm_i915_private *dev_priv = dev->dev_private;
3957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3958 int pipe = intel_crtc->pipe;
3959 u32 fp, fp2 = 0;
3960
3961 if (IS_PINEVIEW(dev)) {
3962 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3963 if (reduced_clock)
3964 fp2 = (1 << reduced_clock->n) << 16 |
3965 reduced_clock->m1 << 8 | reduced_clock->m2;
3966 } else {
3967 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3968 if (reduced_clock)
3969 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3970 reduced_clock->m2;
3971 }
3972
3973 I915_WRITE(FP0(pipe), fp);
3974
3975 intel_crtc->lowfreq_avail = false;
3976 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3977 reduced_clock && i915_powersave) {
3978 I915_WRITE(FP1(pipe), fp2);
3979 intel_crtc->lowfreq_avail = true;
3980 } else {
3981 I915_WRITE(FP1(pipe), fp);
3982 }
3983}
3984
93e537a1
DV		 3985static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3986 struct drm_display_mode *adjusted_mode)
3987{
3988 struct drm_device *dev = crtc->dev;
3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3991 int pipe = intel_crtc->pipe;
284d5df5 3992 u32 temp;
93e537a1
DV		 3993
3994 temp = I915_READ(LVDS);
3995 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3996 if (pipe == 1) {
3997 temp |= LVDS_PIPEB_SELECT;
3998 } else {
3999 temp &= ~LVDS_PIPEB_SELECT;
4000 }
4001 /* set the corresponsding LVDS_BORDER bit */
4002 temp |= dev_priv->lvds_border_bits;
4003 /* Set the B0-B3 data pairs corresponding to whether we're going to
4004 * set the DPLLs for dual-channel mode or not.
4005 */
4006 if (clock->p2 == 7)
4007 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4008 else
4009 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4010
4011 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4012 * appropriately here, but we need to look more thoroughly into how
4013 * panels behave in the two modes.
4014 */
4015 /* set the dithering flag on LVDS as needed */
4016 if (INTEL_INFO(dev)->gen >= 4) {
4017 if (dev_priv->lvds_dither)
4018 temp |= LVDS_ENABLE_DITHER;
4019 else
4020 temp &= ~LVDS_ENABLE_DITHER;
4021 }
284d5df5 4022 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4023 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4024 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4025 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4026 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4027 I915_WRITE(LVDS, temp);
4028}
4029
a0c4da24
JB		 4030static void vlv_update_pll(struct drm_crtc *crtc,
4031 struct drm_display_mode *mode,
4032 struct drm_display_mode *adjusted_mode,
4033 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4034 int num_connectors)
a0c4da24
JB		 4035{
4036 struct drm_device *dev = crtc->dev;
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039 int pipe = intel_crtc->pipe;
4040 u32 dpll, mdiv, pdiv;
4041 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4042 bool is_sdvo;
4043 u32 temp;
4044
4045 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4046 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4047
2a8f64ca
VP		 4048 dpll = DPLL_VGA_MODE_DIS;
4049 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4050 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4051 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4052
4053 I915_WRITE(DPLL(pipe), dpll);
4054 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4055
4056 bestn = clock->n;
4057 bestm1 = clock->m1;
4058 bestm2 = clock->m2;
4059 bestp1 = clock->p1;
4060 bestp2 = clock->p2;
4061
2a8f64ca
VP		 4062 /*
4063 * In Valleyview PLL and program lane counter registers are exposed
4064 * through DPIO interface
4065 */
a0c4da24
JB		 4066 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4067 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4068 mdiv |= ((bestn << DPIO_N_SHIFT));
4069 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4070 mdiv |= (1 << DPIO_K_SHIFT);
4071 mdiv |= DPIO_ENABLE_CALIBRATION;
4072 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4073
4074 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4075
2a8f64ca 4076 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4077 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4078 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4079 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4080 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4081
2a8f64ca 4082 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4083
4084 dpll |= DPLL_VCO_ENABLE;
4085 I915_WRITE(DPLL(pipe), dpll);
4086 POSTING_READ(DPLL(pipe));
4087 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4088 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4089
2a8f64ca
VP		 4090 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4091
4092 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4093 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4094
4095 I915_WRITE(DPLL(pipe), dpll);
4096
4097 /* Wait for the clocks to stabilize. */
4098 POSTING_READ(DPLL(pipe));
4099 udelay(150);
a0c4da24 4100
2a8f64ca
VP		 4101 temp = 0;
4102 if (is_sdvo) {
4103 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4104 if (temp > 1)
4105 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4106 else
4107 temp = 0;
a0c4da24 4108 }
2a8f64ca
VP		 4109 I915_WRITE(DPLL_MD(pipe), temp);
4110 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4111
2a8f64ca
VP		 4112 /* Now program lane control registers */
4113 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4114 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4115 {
4116 temp = 0x1000C4;
4117 if(pipe == 1)
4118 temp |= (1 << 21);
4119 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4120 }
4121 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4122 {
4123 temp = 0x1000C4;
4124 if(pipe == 1)
4125 temp |= (1 << 21);
4126 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4127 }
a0c4da24
JB		 4128}
4129
eb1cbe48
DV		 4130static void i9xx_update_pll(struct drm_crtc *crtc,
4131 struct drm_display_mode *mode,
4132 struct drm_display_mode *adjusted_mode,
4133 intel_clock_t *clock, intel_clock_t *reduced_clock,
4134 int num_connectors)
4135{
4136 struct drm_device *dev = crtc->dev;
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4139 int pipe = intel_crtc->pipe;
4140 u32 dpll;
4141 bool is_sdvo;
4142
2a8f64ca
VP		 4143 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4144
eb1cbe48
DV		 4145 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4146 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4147
4148 dpll = DPLL_VGA_MODE_DIS;
4149
4150 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4151 dpll |= DPLLB_MODE_LVDS;
4152 else
4153 dpll |= DPLLB_MODE_DAC_SERIAL;
4154 if (is_sdvo) {
4155 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4156 if (pixel_multiplier > 1) {
4157 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4158 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4159 }
4160 dpll |= DPLL_DVO_HIGH_SPEED;
4161 }
4162 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4163 dpll |= DPLL_DVO_HIGH_SPEED;
4164
4165 /* compute bitmask from p1 value */
4166 if (IS_PINEVIEW(dev))
4167 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4168 else {
4169 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4170 if (IS_G4X(dev) && reduced_clock)
4171 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4172 }
4173 switch (clock->p2) {
4174 case 5:
4175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4176 break;
4177 case 7:
4178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4179 break;
4180 case 10:
4181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4182 break;
4183 case 14:
4184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4185 break;
4186 }
4187 if (INTEL_INFO(dev)->gen >= 4)
4188 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4189
4190 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4191 dpll |= PLL_REF_INPUT_TVCLKINBC;
4192 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4193 /* XXX: just matching BIOS for now */
4194 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4195 dpll |= 3;
4196 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4198 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4199 else
4200 dpll |= PLL_REF_INPUT_DREFCLK;
4201
4202 dpll |= DPLL_VCO_ENABLE;
4203 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4204 POSTING_READ(DPLL(pipe));
4205 udelay(150);
4206
4207 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4208 * This is an exception to the general rule that mode_set doesn't turn
4209 * things on.
4210 */
4211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4212 intel_update_lvds(crtc, clock, adjusted_mode);
4213
4214 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4215 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4216
4217 I915_WRITE(DPLL(pipe), dpll);
4218
4219 /* Wait for the clocks to stabilize. */
4220 POSTING_READ(DPLL(pipe));
4221 udelay(150);
4222
4223 if (INTEL_INFO(dev)->gen >= 4) {
4224 u32 temp = 0;
4225 if (is_sdvo) {
4226 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4227 if (temp > 1)
4228 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4229 else
4230 temp = 0;
4231 }
4232 I915_WRITE(DPLL_MD(pipe), temp);
4233 } else {
4234 /* The pixel multiplier can only be updated once the
4235 * DPLL is enabled and the clocks are stable.
4236 *
4237 * So write it again.
4238 */
4239 I915_WRITE(DPLL(pipe), dpll);
4240 }
4241}
4242
4243static void i8xx_update_pll(struct drm_crtc *crtc,
4244 struct drm_display_mode *adjusted_mode,
2a8f64ca 4245 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4246 int num_connectors)
4247{
4248 struct drm_device *dev = crtc->dev;
4249 struct drm_i915_private *dev_priv = dev->dev_private;
4250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251 int pipe = intel_crtc->pipe;
4252 u32 dpll;
4253
2a8f64ca
VP		 4254 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4255
eb1cbe48
DV		 4256 dpll = DPLL_VGA_MODE_DIS;
4257
4258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4259 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4260 } else {
4261 if (clock->p1 == 2)
4262 dpll |= PLL_P1_DIVIDE_BY_TWO;
4263 else
4264 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4265 if (clock->p2 == 4)
4266 dpll |= PLL_P2_DIVIDE_BY_4;
4267 }
4268
4269 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4270 /* XXX: just matching BIOS for now */
4271 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4272 dpll |= 3;
4273 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4274 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4275 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4276 else
4277 dpll |= PLL_REF_INPUT_DREFCLK;
4278
4279 dpll |= DPLL_VCO_ENABLE;
4280 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4281 POSTING_READ(DPLL(pipe));
4282 udelay(150);
4283
eb1cbe48
DV		 4284 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4285 * This is an exception to the general rule that mode_set doesn't turn
4286 * things on.
4287 */
4288 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4289 intel_update_lvds(crtc, clock, adjusted_mode);
4290
5b5896e4
DV		 4291 I915_WRITE(DPLL(pipe), dpll);
4292
4293 /* Wait for the clocks to stabilize. */
4294 POSTING_READ(DPLL(pipe));
4295 udelay(150);
4296
eb1cbe48
DV		 4297 /* The pixel multiplier can only be updated once the
4298 * DPLL is enabled and the clocks are stable.
4299 *
4300 * So write it again.
4301 */
4302 I915_WRITE(DPLL(pipe), dpll);
4303}
4304
b0e77b9c
PZ		 4305static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4306 struct drm_display_mode *mode,
4307 struct drm_display_mode *adjusted_mode)
4308{
4309 struct drm_device *dev = intel_crtc->base.dev;
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 enum pipe pipe = intel_crtc->pipe;
4312 uint32_t vsyncshift;
4313
4314 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4315 /* the chip adds 2 halflines automatically */
4316 adjusted_mode->crtc_vtotal -= 1;
4317 adjusted_mode->crtc_vblank_end -= 1;
4318 vsyncshift = adjusted_mode->crtc_hsync_start
4319 - adjusted_mode->crtc_htotal / 2;
4320 } else {
4321 vsyncshift = 0;
4322 }
4323
4324 if (INTEL_INFO(dev)->gen > 3)
4325 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4326
4327 I915_WRITE(HTOTAL(pipe),
4328 (adjusted_mode->crtc_hdisplay - 1) |
4329 ((adjusted_mode->crtc_htotal - 1) << 16));
4330 I915_WRITE(HBLANK(pipe),
4331 (adjusted_mode->crtc_hblank_start - 1) |
4332 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4333 I915_WRITE(HSYNC(pipe),
4334 (adjusted_mode->crtc_hsync_start - 1) |
4335 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4336
4337 I915_WRITE(VTOTAL(pipe),
4338 (adjusted_mode->crtc_vdisplay - 1) |
4339 ((adjusted_mode->crtc_vtotal - 1) << 16));
4340 I915_WRITE(VBLANK(pipe),
4341 (adjusted_mode->crtc_vblank_start - 1) |
4342 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4343 I915_WRITE(VSYNC(pipe),
4344 (adjusted_mode->crtc_vsync_start - 1) |
4345 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4346
4347 /* pipesrc controls the size that is scaled from, which should
4348 * always be the user's requested size.
4349 */
4350 I915_WRITE(PIPESRC(pipe),
4351 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4352}
4353
f564048e
EA		 4354static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4355 struct drm_display_mode *mode,
4356 struct drm_display_mode *adjusted_mode,
4357 int x, int y,
94352cf9 4358 struct drm_framebuffer *fb)
79e53945
JB		 4359{
4360 struct drm_device *dev = crtc->dev;
4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4363 int pipe = intel_crtc->pipe;
80824003 4364 int plane = intel_crtc->plane;
c751ce4f 4365 int refclk, num_connectors = 0;
652c393a 4366 intel_clock_t clock, reduced_clock;
b0e77b9c 4367 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4368 bool ok, has_reduced_clock = false, is_sdvo = false;
4369 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4370 struct intel_encoder *encoder;
d4906093 4371 const intel_limit_t *limit;
5c3b82e2 4372 int ret;
79e53945 4373
6c2b7c12 4374 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4375 switch (encoder->type) {
79e53945
JB		 4376 case INTEL_OUTPUT_LVDS:
4377 is_lvds = true;
4378 break;
4379 case INTEL_OUTPUT_SDVO:
7d57382e 4380 case INTEL_OUTPUT_HDMI:
79e53945 4381 is_sdvo = true;
5eddb70b 4382 if (encoder->needs_tv_clock)
e2f0ba97 4383 is_tv = true;
79e53945 4384 break;
79e53945
JB		 4385 case INTEL_OUTPUT_TVOUT:
4386 is_tv = true;
4387 break;
a4fc5ed6
KP		 4388 case INTEL_OUTPUT_DISPLAYPORT:
4389 is_dp = true;
4390 break;
79e53945 4391 }
43565a06 4392
c751ce4f 4393 num_connectors++;
79e53945
JB		 4394 }
4395
c65d77d8 4396 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4397
d4906093
ML		 4398 /*
4399 * Returns a set of divisors for the desired target clock with the given
4400 * refclk, or FALSE. The returned values represent the clock equation:
4401 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4402 */
1b894b59 4403 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4404 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4405 &clock);
79e53945
JB		 4406 if (!ok) {
4407 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4408 return -EINVAL;
79e53945
JB		 4409 }
4410
cda4b7d3 4411 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4412 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4413
ddc9003c 4414 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4415 /*
4416 * Ensure we match the reduced clock's P to the target clock.
4417 * If the clocks don't match, we can't switch the display clock
4418 * by using the FP0/FP1. In such case we will disable the LVDS
4419 * downclock feature.
4420 */
ddc9003c 4421 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4422 dev_priv->lvds_downclock,
4423 refclk,
cec2f356 4424 &clock,
5eddb70b 4425 &reduced_clock);
7026d4ac
ZW		 4426 }
4427
c65d77d8
JB		 4428 if (is_sdvo && is_tv)
4429 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4430
eb1cbe48 4431 if (IS_GEN2(dev))
2a8f64ca
VP		 4432 i8xx_update_pll(crtc, adjusted_mode, &clock,
4433 has_reduced_clock ? &reduced_clock : NULL,
4434 num_connectors);
a0c4da24 4435 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4436 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4437 has_reduced_clock ? &reduced_clock : NULL,
4438 num_connectors);
79e53945 4439 else
eb1cbe48
DV		 4440 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4441 has_reduced_clock ? &reduced_clock : NULL,
4442 num_connectors);
79e53945
JB		 4443
4444 /* setup pipeconf */
5eddb70b 4445 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4446
4447 /* Set up the display plane register */
4448 dspcntr = DISPPLANE_GAMMA_ENABLE;
4449
929c77fb
EA		 4450 if (pipe == 0)
4451 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4452 else
4453 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4454
a6c45cf0 4455 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4456 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4457 * core speed.
4458 *
4459 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4460 * pipe == 0 check?
4461 */
e70236a8
JB		 4462 if (mode->clock >
4463 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4464 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4465 else
5eddb70b 4466 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4467 }
4468
3b5c78a3
AJ		 4469 /* default to 8bpc */
4470 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4471 if (is_dp) {
4472 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4473 pipeconf |= PIPECONF_BPP_6 |
4474 PIPECONF_DITHER_EN |
4475 PIPECONF_DITHER_TYPE_SP;
4476 }
4477 }
4478
19c03924
GB		 4479 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4480 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4481 pipeconf |= PIPECONF_BPP_6 |
4482 PIPECONF_ENABLE |
4483 I965_PIPECONF_ACTIVE;
4484 }
4485 }
4486
28c97730 4487 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4488 drm_mode_debug_printmodeline(mode);
4489
a7516a05
JB		 4490 if (HAS_PIPE_CXSR(dev)) {
4491 if (intel_crtc->lowfreq_avail) {
28c97730 4492 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4493 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4494 } else {
28c97730 4495 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4496 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4497 }
4498 }
4499
617cf884 4500 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4501 if (!IS_GEN2(dev) &&
b0e77b9c 4502 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4503 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4504 else
617cf884 4505 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4506
b0e77b9c 4507 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4508
4509 /* pipesrc and dspsize control the size that is scaled from,
4510 * which should always be the user's requested size.
79e53945 4511 */
929c77fb
EA		 4512 I915_WRITE(DSPSIZE(plane),
4513 ((mode->vdisplay - 1) << 16) |
4514 (mode->hdisplay - 1));
4515 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4516
f564048e
EA		 4517 I915_WRITE(PIPECONF(pipe), pipeconf);
4518 POSTING_READ(PIPECONF(pipe));
929c77fb 4519 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4520
4521 intel_wait_for_vblank(dev, pipe);
4522
f564048e
EA		 4523 I915_WRITE(DSPCNTR(plane), dspcntr);
4524 POSTING_READ(DSPCNTR(plane));
4525
94352cf9 4526 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4527
4528 intel_update_watermarks(dev);
4529
f564048e
EA		 4530 return ret;
4531}
4532
9fb526db
KP		 4533/*
4534 * Initialize reference clocks when the driver loads
4535 */
4536void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4537{
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4540 struct intel_encoder *encoder;
13d83a67
JB		 4541 u32 temp;
4542 bool has_lvds = false;
199e5d79
KP		 4543 bool has_cpu_edp = false;
4544 bool has_pch_edp = false;
4545 bool has_panel = false;
99eb6a01
KP		 4546 bool has_ck505 = false;
4547 bool can_ssc = false;
13d83a67
JB		 4548
4549 /* We need to take the global config into account */
199e5d79
KP		 4550 list_for_each_entry(encoder, &mode_config->encoder_list,
4551 base.head) {
4552 switch (encoder->type) {
4553 case INTEL_OUTPUT_LVDS:
4554 has_panel = true;
4555 has_lvds = true;
4556 break;
4557 case INTEL_OUTPUT_EDP:
4558 has_panel = true;
4559 if (intel_encoder_is_pch_edp(&encoder->base))
4560 has_pch_edp = true;
4561 else
4562 has_cpu_edp = true;
4563 break;
13d83a67
JB		 4564 }
4565 }
4566
99eb6a01
KP		 4567 if (HAS_PCH_IBX(dev)) {
4568 has_ck505 = dev_priv->display_clock_mode;
4569 can_ssc = has_ck505;
4570 } else {
4571 has_ck505 = false;
4572 can_ssc = true;
4573 }
4574
4575 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4576 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4577 has_ck505);
13d83a67
JB		 4578
4579 /* Ironlake: try to setup display ref clock before DPLL
4580 * enabling. This is only under driver's control after
4581 * PCH B stepping, previous chipset stepping should be
4582 * ignoring this setting.
4583 */
4584 temp = I915_READ(PCH_DREF_CONTROL);
4585 /* Always enable nonspread source */
4586 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4587
99eb6a01
KP		 4588 if (has_ck505)
4589 temp |= DREF_NONSPREAD_CK505_ENABLE;
4590 else
4591 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4592
199e5d79
KP		 4593 if (has_panel) {
4594 temp &= ~DREF_SSC_SOURCE_MASK;
4595 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4596
199e5d79 4597 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4598 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4599 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4600 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4601 } else
4602 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4603
4604 /* Get SSC going before enabling the outputs */
4605 I915_WRITE(PCH_DREF_CONTROL, temp);
4606 POSTING_READ(PCH_DREF_CONTROL);
4607 udelay(200);
4608
13d83a67
JB		 4609 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4610
4611 /* Enable CPU source on CPU attached eDP */
199e5d79 4612 if (has_cpu_edp) {
99eb6a01 4613 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4614 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4615 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4616 }
13d83a67
JB		 4617 else
4618 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4619 } else
4620 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4621
4622 I915_WRITE(PCH_DREF_CONTROL, temp);
4623 POSTING_READ(PCH_DREF_CONTROL);
4624 udelay(200);
4625 } else {
4626 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4627
4628 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4629
4630 /* Turn off CPU output */
4631 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4632
4633 I915_WRITE(PCH_DREF_CONTROL, temp);
4634 POSTING_READ(PCH_DREF_CONTROL);
4635 udelay(200);
4636
4637 /* Turn off the SSC source */
4638 temp &= ~DREF_SSC_SOURCE_MASK;
4639 temp |= DREF_SSC_SOURCE_DISABLE;
4640
4641 /* Turn off SSC1 */
4642 temp &= ~ DREF_SSC1_ENABLE;
4643
13d83a67
JB		 4644 I915_WRITE(PCH_DREF_CONTROL, temp);
4645 POSTING_READ(PCH_DREF_CONTROL);
4646 udelay(200);
4647 }
4648}
4649
d9d444cb
JB		 4650static int ironlake_get_refclk(struct drm_crtc *crtc)
4651{
4652 struct drm_device *dev = crtc->dev;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654 struct intel_encoder *encoder;
d9d444cb
JB		 4655 struct intel_encoder *edp_encoder = NULL;
4656 int num_connectors = 0;
4657 bool is_lvds = false;
4658
6c2b7c12 4659 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4660 switch (encoder->type) {
4661 case INTEL_OUTPUT_LVDS:
4662 is_lvds = true;
4663 break;
4664 case INTEL_OUTPUT_EDP:
4665 edp_encoder = encoder;
4666 break;
4667 }
4668 num_connectors++;
4669 }
4670
4671 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4672 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4673 dev_priv->lvds_ssc_freq);
4674 return dev_priv->lvds_ssc_freq * 1000;
4675 }
4676
4677 return 120000;
4678}
4679
c8203565
PZ		 4680static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4681 struct drm_display_mode *adjusted_mode,
4682 bool dither)
4683{
4684 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4686 int pipe = intel_crtc->pipe;
4687 uint32_t val;
4688
4689 val = I915_READ(PIPECONF(pipe));
4690
4691 val &= ~PIPE_BPC_MASK;
4692 switch (intel_crtc->bpp) {
4693 case 18:
4694 val |= PIPE_6BPC;
4695 break;
4696 case 24:
4697 val |= PIPE_8BPC;
4698 break;
4699 case 30:
4700 val |= PIPE_10BPC;
4701 break;
4702 case 36:
4703 val |= PIPE_12BPC;
4704 break;
4705 default:
cc769b62
PZ		 4706 /* Case prevented by intel_choose_pipe_bpp_dither. */
4707 BUG();
c8203565
PZ		 4708 }
4709
4710 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4711 if (dither)
4712 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4713
4714 val &= ~PIPECONF_INTERLACE_MASK;
4715 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4716 val |= PIPECONF_INTERLACED_ILK;
4717 else
4718 val |= PIPECONF_PROGRESSIVE;
4719
4720 I915_WRITE(PIPECONF(pipe), val);
4721 POSTING_READ(PIPECONF(pipe));
4722}
4723
6591c6e4
PZ		 4724static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4725 struct drm_display_mode *adjusted_mode,
4726 intel_clock_t *clock,
4727 bool *has_reduced_clock,
4728 intel_clock_t *reduced_clock)
4729{
4730 struct drm_device *dev = crtc->dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732 struct intel_encoder *intel_encoder;
4733 int refclk;
4734 const intel_limit_t *limit;
4735 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4736
4737 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4738 switch (intel_encoder->type) {
4739 case INTEL_OUTPUT_LVDS:
4740 is_lvds = true;
4741 break;
4742 case INTEL_OUTPUT_SDVO:
4743 case INTEL_OUTPUT_HDMI:
4744 is_sdvo = true;
4745 if (intel_encoder->needs_tv_clock)
4746 is_tv = true;
4747 break;
4748 case INTEL_OUTPUT_TVOUT:
4749 is_tv = true;
4750 break;
4751 }
4752 }
4753
4754 refclk = ironlake_get_refclk(crtc);
4755
4756 /*
4757 * Returns a set of divisors for the desired target clock with the given
4758 * refclk, or FALSE. The returned values represent the clock equation:
4759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4760 */
4761 limit = intel_limit(crtc, refclk);
4762 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4763 clock);
4764 if (!ret)
4765 return false;
4766
4767 if (is_lvds && dev_priv->lvds_downclock_avail) {
4768 /*
4769 * Ensure we match the reduced clock's P to the target clock.
4770 * If the clocks don't match, we can't switch the display clock
4771 * by using the FP0/FP1. In such case we will disable the LVDS
4772 * downclock feature.
4773 */
4774 *has_reduced_clock = limit->find_pll(limit, crtc,
4775 dev_priv->lvds_downclock,
4776 refclk,
4777 clock,
4778 reduced_clock);
4779 }
4780
4781 if (is_sdvo && is_tv)
4782 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4783
4784 return true;
4785}
4786
f48d8f23
PZ		 4787static void ironlake_set_m_n(struct drm_crtc *crtc,
4788 struct drm_display_mode *mode,
4789 struct drm_display_mode *adjusted_mode)
4790{
4791 struct drm_device *dev = crtc->dev;
4792 struct drm_i915_private *dev_priv = dev->dev_private;
4793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794 enum pipe pipe = intel_crtc->pipe;
4795 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4796 struct fdi_m_n m_n = {0};
4797 int target_clock, pixel_multiplier, lane, link_bw;
4798 bool is_dp = false, is_cpu_edp = false;
4799
4800 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4801 switch (intel_encoder->type) {
4802 case INTEL_OUTPUT_DISPLAYPORT:
4803 is_dp = true;
4804 break;
4805 case INTEL_OUTPUT_EDP:
4806 is_dp = true;
4807 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4808 is_cpu_edp = true;
4809 edp_encoder = intel_encoder;
4810 break;
4811 }
4812 }
4813
4814 /* FDI link */
4815 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4816 lane = 0;
4817 /* CPU eDP doesn't require FDI link, so just set DP M/N
4818 according to current link config */
4819 if (is_cpu_edp) {
4820 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4821 } else {
4822 /* FDI is a binary signal running at ~2.7GHz, encoding
4823 * each output octet as 10 bits. The actual frequency
4824 * is stored as a divider into a 100MHz clock, and the
4825 * mode pixel clock is stored in units of 1KHz.
4826 * Hence the bw of each lane in terms of the mode signal
4827 * is:
4828 */
4829 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4830 }
4831
4832 /* [e]DP over FDI requires target mode clock instead of link clock. */
4833 if (edp_encoder)
4834 target_clock = intel_edp_target_clock(edp_encoder, mode);
4835 else if (is_dp)
4836 target_clock = mode->clock;
4837 else
4838 target_clock = adjusted_mode->clock;
4839
4840 if (!lane) {
4841 /*
4842 * Account for spread spectrum to avoid
4843 * oversubscribing the link. Max center spread
4844 * is 2.5%; use 5% for safety's sake.
4845 */
4846 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4847 lane = bps / (link_bw * 8) + 1;
4848 }
4849
4850 intel_crtc->fdi_lanes = lane;
4851
4852 if (pixel_multiplier > 1)
4853 link_bw *= pixel_multiplier;
4854 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4855 &m_n);
4856
4857 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4858 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4859 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4860 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4861}
4862
de13a2e3
PZ		 4863static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4864 struct drm_display_mode *adjusted_mode,
4865 intel_clock_t *clock, u32 fp)
79e53945 4866{
de13a2e3 4867 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 4868 struct drm_device *dev = crtc->dev;
4869 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 4870 struct intel_encoder *intel_encoder;
4871 uint32_t dpll;
4872 int factor, pixel_multiplier, num_connectors = 0;
4873 bool is_lvds = false, is_sdvo = false, is_tv = false;
4874 bool is_dp = false, is_cpu_edp = false;
79e53945 4875
de13a2e3
PZ		 4876 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4877 switch (intel_encoder->type) {
79e53945
JB		 4878 case INTEL_OUTPUT_LVDS:
4879 is_lvds = true;
4880 break;
4881 case INTEL_OUTPUT_SDVO:
7d57382e 4882 case INTEL_OUTPUT_HDMI:
79e53945 4883 is_sdvo = true;
de13a2e3 4884 if (intel_encoder->needs_tv_clock)
e2f0ba97 4885 is_tv = true;
79e53945 4886 break;
79e53945
JB		 4887 case INTEL_OUTPUT_TVOUT:
4888 is_tv = true;
4889 break;
a4fc5ed6
KP		 4890 case INTEL_OUTPUT_DISPLAYPORT:
4891 is_dp = true;
4892 break;
32f9d658 4893 case INTEL_OUTPUT_EDP:
e3aef172 4894 is_dp = true;
de13a2e3 4895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 4896 is_cpu_edp = true;
32f9d658 4897 break;
79e53945 4898 }
43565a06 4899
c751ce4f 4900 num_connectors++;
79e53945
JB		 4901 }
4902
c1858123 4903 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4904 factor = 21;
4905 if (is_lvds) {
4906 if ((intel_panel_use_ssc(dev_priv) &&
4907 dev_priv->lvds_ssc_freq == 100) ||
4908 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4909 factor = 25;
4910 } else if (is_sdvo && is_tv)
4911 factor = 20;
c1858123 4912
de13a2e3 4913 if (clock->m < factor * clock->n)
8febb297 4914 fp |= FP_CB_TUNE;
2c07245f 4915
5eddb70b 4916 dpll = 0;
2c07245f 4917
a07d6787
EA		 4918 if (is_lvds)
4919 dpll |= DPLLB_MODE_LVDS;
4920 else
4921 dpll |= DPLLB_MODE_DAC_SERIAL;
4922 if (is_sdvo) {
de13a2e3 4923 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 4924 if (pixel_multiplier > 1) {
4925 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4926 }
a07d6787
EA		 4927 dpll |= DPLL_DVO_HIGH_SPEED;
4928 }
e3aef172 4929 if (is_dp && !is_cpu_edp)
a07d6787 4930 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4931
a07d6787 4932 /* compute bitmask from p1 value */
de13a2e3 4933 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 4934 /* also FPA1 */
de13a2e3 4935 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 4936
de13a2e3 4937 switch (clock->p2) {
a07d6787
EA		 4938 case 5:
4939 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4940 break;
4941 case 7:
4942 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4943 break;
4944 case 10:
4945 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4946 break;
4947 case 14:
4948 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4949 break;
79e53945
JB		 4950 }
4951
43565a06
KH		 4952 if (is_sdvo && is_tv)
4953 dpll |= PLL_REF_INPUT_TVCLKINBC;
4954 else if (is_tv)
79e53945 4955 /* XXX: just matching BIOS for now */
43565a06 4956 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4957 dpll |= 3;
a7615030 4958 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4959 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4960 else
4961 dpll |= PLL_REF_INPUT_DREFCLK;
4962
de13a2e3
PZ		 4963 return dpll;
4964}
4965
4966static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4967 struct drm_display_mode *mode,
4968 struct drm_display_mode *adjusted_mode,
4969 int x, int y,
4970 struct drm_framebuffer *fb)
4971{
4972 struct drm_device *dev = crtc->dev;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4975 int pipe = intel_crtc->pipe;
4976 int plane = intel_crtc->plane;
4977 int num_connectors = 0;
4978 intel_clock_t clock, reduced_clock;
4979 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 4980 bool ok, has_reduced_clock = false;
4981 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 4982 struct intel_encoder *encoder;
4983 u32 temp;
4984 int ret;
4985 bool dither;
de13a2e3
PZ		 4986
4987 for_each_encoder_on_crtc(dev, crtc, encoder) {
4988 switch (encoder->type) {
4989 case INTEL_OUTPUT_LVDS:
4990 is_lvds = true;
4991 break;
de13a2e3
PZ		 4992 case INTEL_OUTPUT_DISPLAYPORT:
4993 is_dp = true;
4994 break;
4995 case INTEL_OUTPUT_EDP:
4996 is_dp = true;
e2f12b07 4997 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 4998 is_cpu_edp = true;
4999 break;
5000 }
5001
5002 num_connectors++;
5003 }
5004
5dc5298b
PZ		 5005 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5006 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5007
de13a2e3
PZ		 5008 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5009 &has_reduced_clock, &reduced_clock);
5010 if (!ok) {
5011 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5012 return -EINVAL;
5013 }
5014
5015 /* Ensure that the cursor is valid for the new mode before changing... */
5016 intel_crtc_update_cursor(crtc, true);
5017
5018 /* determine panel color depth */
5019 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5020 if (is_lvds && dev_priv->lvds_dither)
5021 dither = true;
5022
5023 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5024 if (has_reduced_clock)
5025 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5026 reduced_clock.m2;
5027
5028 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5029
f7cb34d4 5030 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5031 drm_mode_debug_printmodeline(mode);
5032
5dc5298b
PZ		 5033 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5034 if (!is_cpu_edp) {
ee7b9f93 5035 struct intel_pch_pll *pll;
4b645f14 5036
ee7b9f93
JB		 5037 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5038 if (pll == NULL) {
5039 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5040 pipe);
4b645f14
JB		 5041 return -EINVAL;
5042 }
ee7b9f93
JB		 5043 } else
5044 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5045
5046 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5047 * This is an exception to the general rule that mode_set doesn't turn
5048 * things on.
5049 */
5050 if (is_lvds) {
fae14981 5051 temp = I915_READ(PCH_LVDS);
5eddb70b 5052 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5053 if (HAS_PCH_CPT(dev)) {
5054 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5055 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5056 } else {
5057 if (pipe == 1)
5058 temp |= LVDS_PIPEB_SELECT;
5059 else
5060 temp &= ~LVDS_PIPEB_SELECT;
5061 }
4b645f14 5062
a3e17eb8 5063 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5064 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5065 /* Set the B0-B3 data pairs corresponding to whether we're going to
5066 * set the DPLLs for dual-channel mode or not.
5067 */
5068 if (clock.p2 == 7)
5eddb70b 5069 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5070 else
5eddb70b 5071 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5072
5073 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5074 * appropriately here, but we need to look more thoroughly into how
5075 * panels behave in the two modes.
5076 */
284d5df5 5077 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5078 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5079 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5080 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5081 temp |= LVDS_VSYNC_POLARITY;
fae14981 5082 I915_WRITE(PCH_LVDS, temp);
79e53945 5083 }
434ed097 5084
e3aef172 5085 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5086 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5087 } else {
8db9d77b 5088 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5089 I915_WRITE(TRANSDATA_M1(pipe), 0);
5090 I915_WRITE(TRANSDATA_N1(pipe), 0);
5091 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5092 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5093 }
79e53945 5094
ee7b9f93
JB		 5095 if (intel_crtc->pch_pll) {
5096 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5097
32f9d658 5098 /* Wait for the clocks to stabilize. */
ee7b9f93 5099 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5100 udelay(150);
5101
8febb297
EA		 5102 /* The pixel multiplier can only be updated once the
5103 * DPLL is enabled and the clocks are stable.
5104 *
5105 * So write it again.
5106 */
ee7b9f93 5107 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5108 }
79e53945 5109
5eddb70b 5110 intel_crtc->lowfreq_avail = false;
ee7b9f93 5111 if (intel_crtc->pch_pll) {
4b645f14 5112 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5113 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5114 intel_crtc->lowfreq_avail = true;
4b645f14 5115 } else {
ee7b9f93 5116 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5117 }
5118 }
5119
b0e77b9c 5120 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5121
f48d8f23 5122 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5123
e3aef172 5124 if (is_cpu_edp)
8febb297 5125 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5126
c8203565 5127 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5128
9d0498a2 5129 intel_wait_for_vblank(dev, pipe);
79e53945 5130
a1f9e77e
PZ		 5131 /* Set up the display plane register */
5132 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5133 POSTING_READ(DSPCNTR(plane));
79e53945 5134
94352cf9 5135 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5136
5137 intel_update_watermarks(dev);
5138
1f8eeabf
ED		 5139 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5140
1f803ee5 5141 return ret;
79e53945
JB		 5142}
5143
09b4ddf9
PZ		 5144static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5145 struct drm_display_mode *mode,
5146 struct drm_display_mode *adjusted_mode,
5147 int x, int y,
5148 struct drm_framebuffer *fb)
5149{
5150 struct drm_device *dev = crtc->dev;
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153 int pipe = intel_crtc->pipe;
5154 int plane = intel_crtc->plane;
5155 int num_connectors = 0;
5156 intel_clock_t clock, reduced_clock;
5dc5298b 5157 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5158 bool ok, has_reduced_clock = false;
5159 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5160 struct intel_encoder *encoder;
5161 u32 temp;
5162 int ret;
5163 bool dither;
5164
5165 for_each_encoder_on_crtc(dev, crtc, encoder) {
5166 switch (encoder->type) {
5167 case INTEL_OUTPUT_LVDS:
5168 is_lvds = true;
5169 break;
5170 case INTEL_OUTPUT_DISPLAYPORT:
5171 is_dp = true;
5172 break;
5173 case INTEL_OUTPUT_EDP:
5174 is_dp = true;
5175 if (!intel_encoder_is_pch_edp(&encoder->base))
5176 is_cpu_edp = true;
5177 break;
5178 }
5179
5180 num_connectors++;
5181 }
5182
5dc5298b
PZ		 5183 /* We are not sure yet this won't happen. */
5184 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5185 INTEL_PCH_TYPE(dev));
5186
5187 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5188 num_connectors, pipe_name(pipe));
5189
5190 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5191 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5192 &has_reduced_clock,
5193 &reduced_clock);
5194 if (!ok) {
5195 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5196 return -EINVAL;
5197 }
09b4ddf9
PZ		 5198 }
5199
5200 /* Ensure that the cursor is valid for the new mode before changing... */
5201 intel_crtc_update_cursor(crtc, true);
5202
5203 /* determine panel color depth */
5204 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5205 if (is_lvds && dev_priv->lvds_dither)
5206 dither = true;
5207
09b4ddf9
PZ		 5208 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5209 drm_mode_debug_printmodeline(mode);
5210
5dc5298b
PZ		 5211 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5212 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5213 if (has_reduced_clock)
5214 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5215 reduced_clock.m2;
5216
5217 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5218 fp);
5219
5220 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5221 * own on pre-Haswell/LPT generation */
5222 if (!is_cpu_edp) {
5223 struct intel_pch_pll *pll;
5224
5225 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5226 if (pll == NULL) {
5227 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5228 pipe);
5229 return -EINVAL;
5230 }
5231 } else
5232 intel_put_pch_pll(intel_crtc);
09b4ddf9 5233
5dc5298b
PZ		 5234 /* The LVDS pin pair needs to be on before the DPLLs are
5235 * enabled. This is an exception to the general rule that
5236 * mode_set doesn't turn things on.
5237 */
5238 if (is_lvds) {
5239 temp = I915_READ(PCH_LVDS);
5240 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5241 if (HAS_PCH_CPT(dev)) {
5242 temp &= ~PORT_TRANS_SEL_MASK;
5243 temp |= PORT_TRANS_SEL_CPT(pipe);
5244 } else {
5245 if (pipe == 1)
5246 temp |= LVDS_PIPEB_SELECT;
5247 else
5248 temp &= ~LVDS_PIPEB_SELECT;
5249 }
09b4ddf9 5250
5dc5298b
PZ		 5251 /* set the corresponsding LVDS_BORDER bit */
5252 temp |= dev_priv->lvds_border_bits;
5253 /* Set the B0-B3 data pairs corresponding to whether
5254 * we're going to set the DPLLs for dual-channel mode or
5255 * not.
5256 */
5257 if (clock.p2 == 7)
5258 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5259 else
5dc5298b
PZ		 5260 temp &= ~(LVDS_B0B3_POWER_UP |
5261 LVDS_CLKB_POWER_UP);
5262
5263 /* It would be nice to set 24 vs 18-bit mode
5264 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5265 * look more thoroughly into how panels behave in the
5266 * two modes.
5267 */
5268 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5269 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5270 temp |= LVDS_HSYNC_POLARITY;
5271 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5272 temp |= LVDS_VSYNC_POLARITY;
5273 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5274 }
09b4ddf9
PZ		 5275 }
5276
5277 if (is_dp && !is_cpu_edp) {
5278 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5279 } else {
5dc5298b
PZ		 5280 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5281 /* For non-DP output, clear any trans DP clock recovery
5282 * setting.*/
5283 I915_WRITE(TRANSDATA_M1(pipe), 0);
5284 I915_WRITE(TRANSDATA_N1(pipe), 0);
5285 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5286 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5287 }
09b4ddf9
PZ		 5288 }
5289
5290 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5291 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5292 if (intel_crtc->pch_pll) {
5293 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5294
5295 /* Wait for the clocks to stabilize. */
5296 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5297 udelay(150);
5298
5299 /* The pixel multiplier can only be updated once the
5300 * DPLL is enabled and the clocks are stable.
5301 *
5302 * So write it again.
5303 */
5304 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5305 }
5306
5307 if (intel_crtc->pch_pll) {
5308 if (is_lvds && has_reduced_clock && i915_powersave) {
5309 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5310 intel_crtc->lowfreq_avail = true;
5311 } else {
5312 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5313 }
09b4ddf9
PZ		 5314 }
5315 }
5316
5317 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5318
5319 ironlake_set_m_n(crtc, mode, adjusted_mode);
5320
5dc5298b
PZ		 5321 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5322 if (is_cpu_edp)
5323 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9
PZ		 5324
5325 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5326
5327 intel_wait_for_vblank(dev, pipe);
5328
5329 /* Set up the display plane register */
5330 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5331 POSTING_READ(DSPCNTR(plane));
5332
5333 ret = intel_pipe_set_base(crtc, x, y, fb);
5334
5335 intel_update_watermarks(dev);
5336
5337 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5338
5339 return ret;
5340}
5341
f564048e
EA		 5342static int intel_crtc_mode_set(struct drm_crtc *crtc,
5343 struct drm_display_mode *mode,
5344 struct drm_display_mode *adjusted_mode,
5345 int x, int y,
94352cf9 5346 struct drm_framebuffer *fb)
f564048e
EA		 5347{
5348 struct drm_device *dev = crtc->dev;
5349 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5351 int pipe = intel_crtc->pipe;
f564048e
EA		 5352 int ret;
5353
0b701d27 5354 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5355
f564048e 5356 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5357 x, y, fb);
79e53945 5358 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5359
1f803ee5 5360 return ret;
79e53945
JB		 5361}
5362
3a9627f4
WF		 5363static bool intel_eld_uptodate(struct drm_connector *connector,
5364 int reg_eldv, uint32_t bits_eldv,
5365 int reg_elda, uint32_t bits_elda,
5366 int reg_edid)
5367{
5368 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5369 uint8_t *eld = connector->eld;
5370 uint32_t i;
5371
5372 i = I915_READ(reg_eldv);
5373 i &= bits_eldv;
5374
5375 if (!eld[0])
5376 return !i;
5377
5378 if (!i)
5379 return false;
5380
5381 i = I915_READ(reg_elda);
5382 i &= ~bits_elda;
5383 I915_WRITE(reg_elda, i);
5384
5385 for (i = 0; i < eld[2]; i++)
5386 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5387 return false;
5388
5389 return true;
5390}
5391
e0dac65e
WF		 5392static void g4x_write_eld(struct drm_connector *connector,
5393 struct drm_crtc *crtc)
5394{
5395 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5396 uint8_t *eld = connector->eld;
5397 uint32_t eldv;
5398 uint32_t len;
5399 uint32_t i;
5400
5401 i = I915_READ(G4X_AUD_VID_DID);
5402
5403 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5404 eldv = G4X_ELDV_DEVCL_DEVBLC;
5405 else
5406 eldv = G4X_ELDV_DEVCTG;
5407
3a9627f4
WF		 5408 if (intel_eld_uptodate(connector,
5409 G4X_AUD_CNTL_ST, eldv,
5410 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5411 G4X_HDMIW_HDMIEDID))
5412 return;
5413
e0dac65e
WF		 5414 i = I915_READ(G4X_AUD_CNTL_ST);
5415 i &= ~(eldv | G4X_ELD_ADDR);
5416 len = (i >> 9) & 0x1f; /* ELD buffer size */
5417 I915_WRITE(G4X_AUD_CNTL_ST, i);
5418
5419 if (!eld[0])
5420 return;
5421
5422 len = min_t(uint8_t, eld[2], len);
5423 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5424 for (i = 0; i < len; i++)
5425 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5426
5427 i = I915_READ(G4X_AUD_CNTL_ST);
5428 i |= eldv;
5429 I915_WRITE(G4X_AUD_CNTL_ST, i);
5430}
5431
83358c85
WX		 5432static void haswell_write_eld(struct drm_connector *connector,
5433 struct drm_crtc *crtc)
5434{
5435 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5436 uint8_t *eld = connector->eld;
5437 struct drm_device *dev = crtc->dev;
5438 uint32_t eldv;
5439 uint32_t i;
5440 int len;
5441 int pipe = to_intel_crtc(crtc)->pipe;
5442 int tmp;
5443
5444 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5445 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5446 int aud_config = HSW_AUD_CFG(pipe);
5447 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5448
5449
5450 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5451
5452 /* Audio output enable */
5453 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5454 tmp = I915_READ(aud_cntrl_st2);
5455 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5456 I915_WRITE(aud_cntrl_st2, tmp);
5457
5458 /* Wait for 1 vertical blank */
5459 intel_wait_for_vblank(dev, pipe);
5460
5461 /* Set ELD valid state */
5462 tmp = I915_READ(aud_cntrl_st2);
5463 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5464 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5465 I915_WRITE(aud_cntrl_st2, tmp);
5466 tmp = I915_READ(aud_cntrl_st2);
5467 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5468
5469 /* Enable HDMI mode */
5470 tmp = I915_READ(aud_config);
5471 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5472 /* clear N_programing_enable and N_value_index */
5473 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5474 I915_WRITE(aud_config, tmp);
5475
5476 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5477
5478 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5479
5480 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5481 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5482 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5483 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5484 } else
5485 I915_WRITE(aud_config, 0);
5486
5487 if (intel_eld_uptodate(connector,
5488 aud_cntrl_st2, eldv,
5489 aud_cntl_st, IBX_ELD_ADDRESS,
5490 hdmiw_hdmiedid))
5491 return;
5492
5493 i = I915_READ(aud_cntrl_st2);
5494 i &= ~eldv;
5495 I915_WRITE(aud_cntrl_st2, i);
5496
5497 if (!eld[0])
5498 return;
5499
5500 i = I915_READ(aud_cntl_st);
5501 i &= ~IBX_ELD_ADDRESS;
5502 I915_WRITE(aud_cntl_st, i);
5503 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5504 DRM_DEBUG_DRIVER("port num:%d\n", i);
5505
5506 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5507 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5508 for (i = 0; i < len; i++)
5509 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5510
5511 i = I915_READ(aud_cntrl_st2);
5512 i |= eldv;
5513 I915_WRITE(aud_cntrl_st2, i);
5514
5515}
5516
e0dac65e
WF		 5517static void ironlake_write_eld(struct drm_connector *connector,
5518 struct drm_crtc *crtc)
5519{
5520 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5521 uint8_t *eld = connector->eld;
5522 uint32_t eldv;
5523 uint32_t i;
5524 int len;
5525 int hdmiw_hdmiedid;
b6daa025 5526 int aud_config;
e0dac65e
WF		 5527 int aud_cntl_st;
5528 int aud_cntrl_st2;
9b138a83 5529 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5530
b3f33cbf 5531 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5532 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5533 aud_config = IBX_AUD_CFG(pipe);
5534 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5535 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5536 } else {
9b138a83
WX		 5537 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5538 aud_config = CPT_AUD_CFG(pipe);
5539 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5540 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5541 }
5542
9b138a83 5543 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5544
5545 i = I915_READ(aud_cntl_st);
9b138a83 5546 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5547 if (!i) {
5548 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5549 /* operate blindly on all ports */
1202b4c6
WF		 5550 eldv = IBX_ELD_VALIDB;
5551 eldv |= IBX_ELD_VALIDB << 4;
5552 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5553 } else {
5554 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5555 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5556 }
5557
3a9627f4
WF		 5558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5559 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5560 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5561 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5562 } else
5563 I915_WRITE(aud_config, 0);
e0dac65e 5564
3a9627f4
WF		 5565 if (intel_eld_uptodate(connector,
5566 aud_cntrl_st2, eldv,
5567 aud_cntl_st, IBX_ELD_ADDRESS,
5568 hdmiw_hdmiedid))
5569 return;
5570
e0dac65e
WF		 5571 i = I915_READ(aud_cntrl_st2);
5572 i &= ~eldv;
5573 I915_WRITE(aud_cntrl_st2, i);
5574
5575 if (!eld[0])
5576 return;
5577
e0dac65e 5578 i = I915_READ(aud_cntl_st);
1202b4c6 5579 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5580 I915_WRITE(aud_cntl_st, i);
5581
5582 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5583 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5584 for (i = 0; i < len; i++)
5585 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5586
5587 i = I915_READ(aud_cntrl_st2);
5588 i |= eldv;
5589 I915_WRITE(aud_cntrl_st2, i);
5590}
5591
5592void intel_write_eld(struct drm_encoder *encoder,
5593 struct drm_display_mode *mode)
5594{
5595 struct drm_crtc *crtc = encoder->crtc;
5596 struct drm_connector *connector;
5597 struct drm_device *dev = encoder->dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599
5600 connector = drm_select_eld(encoder, mode);
5601 if (!connector)
5602 return;
5603
5604 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5605 connector->base.id,
5606 drm_get_connector_name(connector),
5607 connector->encoder->base.id,
5608 drm_get_encoder_name(connector->encoder));
5609
5610 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5611
5612 if (dev_priv->display.write_eld)
5613 dev_priv->display.write_eld(connector, crtc);
5614}
5615
79e53945
JB		 5616/** Loads the palette/gamma unit for the CRTC with the prepared values */
5617void intel_crtc_load_lut(struct drm_crtc *crtc)
5618{
5619 struct drm_device *dev = crtc->dev;
5620 struct drm_i915_private *dev_priv = dev->dev_private;
5621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5622 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5623 int i;
5624
5625 /* The clocks have to be on to load the palette. */
aed3f09d 5626 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5627 return;
5628
f2b115e6 5629 /* use legacy palette for Ironlake */
bad720ff 5630 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5631 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5632
79e53945
JB		 5633 for (i = 0; i < 256; i++) {
5634 I915_WRITE(palreg + 4 * i,
5635 (intel_crtc->lut_r[i] << 16) |
5636 (intel_crtc->lut_g[i] << 8) |
5637 intel_crtc->lut_b[i]);
5638 }
5639}
5640
560b85bb
CW		 5641static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5642{
5643 struct drm_device *dev = crtc->dev;
5644 struct drm_i915_private *dev_priv = dev->dev_private;
5645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5646 bool visible = base != 0;
5647 u32 cntl;
5648
5649 if (intel_crtc->cursor_visible == visible)
5650 return;
5651
9db4a9c7 5652 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5653 if (visible) {
5654 /* On these chipsets we can only modify the base whilst
5655 * the cursor is disabled.
5656 */
9db4a9c7 5657 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5658
5659 cntl &= ~(CURSOR_FORMAT_MASK);
5660 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5661 cntl |= CURSOR_ENABLE |
5662 CURSOR_GAMMA_ENABLE |
5663 CURSOR_FORMAT_ARGB;
5664 } else
5665 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5666 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5667
5668 intel_crtc->cursor_visible = visible;
5669}
5670
5671static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5672{
5673 struct drm_device *dev = crtc->dev;
5674 struct drm_i915_private *dev_priv = dev->dev_private;
5675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5676 int pipe = intel_crtc->pipe;
5677 bool visible = base != 0;
5678
5679 if (intel_crtc->cursor_visible != visible) {
548f245b 5680 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5681 if (base) {
5682 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5683 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5684 cntl |= pipe << 28; /* Connect to correct pipe */
5685 } else {
5686 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5687 cntl |= CURSOR_MODE_DISABLE;
5688 }
9db4a9c7 5689 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5690
5691 intel_crtc->cursor_visible = visible;
5692 }
5693 /* and commit changes on next vblank */
9db4a9c7 5694 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5695}
5696
65a21cd6
JB		 5697static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5698{
5699 struct drm_device *dev = crtc->dev;
5700 struct drm_i915_private *dev_priv = dev->dev_private;
5701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5702 int pipe = intel_crtc->pipe;
5703 bool visible = base != 0;
5704
5705 if (intel_crtc->cursor_visible != visible) {
5706 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5707 if (base) {
5708 cntl &= ~CURSOR_MODE;
5709 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5710 } else {
5711 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5712 cntl |= CURSOR_MODE_DISABLE;
5713 }
5714 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5715
5716 intel_crtc->cursor_visible = visible;
5717 }
5718 /* and commit changes on next vblank */
5719 I915_WRITE(CURBASE_IVB(pipe), base);
5720}
5721
cda4b7d3 5722/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5723static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5724 bool on)
cda4b7d3
CW		 5725{
5726 struct drm_device *dev = crtc->dev;
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729 int pipe = intel_crtc->pipe;
5730 int x = intel_crtc->cursor_x;
5731 int y = intel_crtc->cursor_y;
560b85bb 5732 u32 base, pos;
cda4b7d3
CW		 5733 bool visible;
5734
5735 pos = 0;
5736
6b383a7f 5737 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5738 base = intel_crtc->cursor_addr;
5739 if (x > (int) crtc->fb->width)
5740 base = 0;
5741
5742 if (y > (int) crtc->fb->height)
5743 base = 0;
5744 } else
5745 base = 0;
5746
5747 if (x < 0) {
5748 if (x + intel_crtc->cursor_width < 0)
5749 base = 0;
5750
5751 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5752 x = -x;
5753 }
5754 pos |= x << CURSOR_X_SHIFT;
5755
5756 if (y < 0) {
5757 if (y + intel_crtc->cursor_height < 0)
5758 base = 0;
5759
5760 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5761 y = -y;
5762 }
5763 pos |= y << CURSOR_Y_SHIFT;
5764
5765 visible = base != 0;
560b85bb 5766 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5767 return;
5768
0cd83aa9 5769 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5770 I915_WRITE(CURPOS_IVB(pipe), pos);
5771 ivb_update_cursor(crtc, base);
5772 } else {
5773 I915_WRITE(CURPOS(pipe), pos);
5774 if (IS_845G(dev) || IS_I865G(dev))
5775 i845_update_cursor(crtc, base);
5776 else
5777 i9xx_update_cursor(crtc, base);
5778 }
cda4b7d3
CW		 5779}
5780
79e53945 5781static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5782 struct drm_file *file,
79e53945
JB		 5783 uint32_t handle,
5784 uint32_t width, uint32_t height)
5785{
5786 struct drm_device *dev = crtc->dev;
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5789 struct drm_i915_gem_object *obj;
cda4b7d3 5790 uint32_t addr;
3f8bc370 5791 int ret;
79e53945 5792
79e53945
JB		 5793 /* if we want to turn off the cursor ignore width and height */
5794 if (!handle) {
28c97730 5795 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5796 addr = 0;
05394f39 5797 obj = NULL;
5004417d 5798 mutex_lock(&dev->struct_mutex);
3f8bc370 5799 goto finish;
79e53945
JB		 5800 }
5801
5802 /* Currently we only support 64x64 cursors */
5803 if (width != 64 || height != 64) {
5804 DRM_ERROR("we currently only support 64x64 cursors\n");
5805 return -EINVAL;
5806 }
5807
05394f39 5808 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5809 if (&obj->base == NULL)
79e53945
JB		 5810 return -ENOENT;
5811
05394f39 5812 if (obj->base.size < width * height * 4) {
79e53945 5813 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5814 ret = -ENOMEM;
5815 goto fail;
79e53945
JB		 5816 }
5817
71acb5eb 5818 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5819 mutex_lock(&dev->struct_mutex);
b295d1b6 5820 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5821 if (obj->tiling_mode) {
5822 DRM_ERROR("cursor cannot be tiled\n");
5823 ret = -EINVAL;
5824 goto fail_locked;
5825 }
5826
2da3b9b9 5827 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5828 if (ret) {
5829 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5830 goto fail_locked;
e7b526bb
CW		 5831 }
5832
d9e86c0e
CW		 5833 ret = i915_gem_object_put_fence(obj);
5834 if (ret) {
2da3b9b9 5835 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5836 goto fail_unpin;
5837 }
5838
05394f39 5839 addr = obj->gtt_offset;
71acb5eb 5840 } else {
6eeefaf3 5841 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5842 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5843 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5844 align);
71acb5eb
DA		 5845 if (ret) {
5846 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5847 goto fail_locked;
71acb5eb 5848 }
05394f39 5849 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5850 }
5851
a6c45cf0 5852 if (IS_GEN2(dev))
14b60391
JB		 5853 I915_WRITE(CURSIZE, (height << 12) | width);
5854
3f8bc370 5855 finish:
3f8bc370 5856 if (intel_crtc->cursor_bo) {
b295d1b6 5857 if (dev_priv->info->cursor_needs_physical) {
05394f39 5858 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5859 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5860 } else
5861 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5862 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5863 }
80824003 5864
7f9872e0 5865 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5866
5867 intel_crtc->cursor_addr = addr;
05394f39 5868 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5869 intel_crtc->cursor_width = width;
5870 intel_crtc->cursor_height = height;
5871
6b383a7f 5872 intel_crtc_update_cursor(crtc, true);
3f8bc370 5873
79e53945 5874 return 0;
e7b526bb 5875fail_unpin:
05394f39 5876 i915_gem_object_unpin(obj);
7f9872e0 5877fail_locked:
34b8686e 5878 mutex_unlock(&dev->struct_mutex);
bc9025bd 5879fail:
05394f39 5880 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5881 return ret;
79e53945
JB		 5882}
5883
5884static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5885{
79e53945 5886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5887
cda4b7d3
CW		 5888 intel_crtc->cursor_x = x;
5889 intel_crtc->cursor_y = y;
652c393a 5890
6b383a7f 5891 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5892
5893 return 0;
5894}
5895
5896/** Sets the color ramps on behalf of RandR */
5897void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5898 u16 blue, int regno)
5899{
5900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5901
5902 intel_crtc->lut_r[regno] = red >> 8;
5903 intel_crtc->lut_g[regno] = green >> 8;
5904 intel_crtc->lut_b[regno] = blue >> 8;
5905}
5906
b8c00ac5
DA		 5907void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5908 u16 *blue, int regno)
5909{
5910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5911
5912 *red = intel_crtc->lut_r[regno] << 8;
5913 *green = intel_crtc->lut_g[regno] << 8;
5914 *blue = intel_crtc->lut_b[regno] << 8;
5915}
5916
79e53945 5917static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5918 u16 *blue, uint32_t start, uint32_t size)
79e53945 5919{
7203425a 5920 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5922
7203425a 5923 for (i = start; i < end; i++) {
79e53945
JB		 5924 intel_crtc->lut_r[i] = red[i] >> 8;
5925 intel_crtc->lut_g[i] = green[i] >> 8;
5926 intel_crtc->lut_b[i] = blue[i] >> 8;
5927 }
5928
5929 intel_crtc_load_lut(crtc);
5930}
5931
5932/**
5933 * Get a pipe with a simple mode set on it for doing load-based monitor
5934 * detection.
5935 *
5936 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5937 * its requirements. The pipe will be connected to no other encoders.
79e53945 5938 *
c751ce4f 5939 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5940 * configured for it. In the future, it could choose to temporarily disable
5941 * some outputs to free up a pipe for its use.
5942 *
5943 * \return crtc, or NULL if no pipes are available.
5944 */
5945
5946/* VESA 640x480x72Hz mode to set on the pipe */
5947static struct drm_display_mode load_detect_mode = {
5948 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5949 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5950};
5951
d2dff872
CW		 5952static struct drm_framebuffer *
5953intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5954 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5955 struct drm_i915_gem_object *obj)
5956{
5957 struct intel_framebuffer *intel_fb;
5958 int ret;
5959
5960 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5961 if (!intel_fb) {
5962 drm_gem_object_unreference_unlocked(&obj->base);
5963 return ERR_PTR(-ENOMEM);
5964 }
5965
5966 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5967 if (ret) {
5968 drm_gem_object_unreference_unlocked(&obj->base);
5969 kfree(intel_fb);
5970 return ERR_PTR(ret);
5971 }
5972
5973 return &intel_fb->base;
5974}
5975
5976static u32
5977intel_framebuffer_pitch_for_width(int width, int bpp)
5978{
5979 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5980 return ALIGN(pitch, 64);
5981}
5982
5983static u32
5984intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5985{
5986 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5987 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5988}
5989
5990static struct drm_framebuffer *
5991intel_framebuffer_create_for_mode(struct drm_device *dev,
5992 struct drm_display_mode *mode,
5993 int depth, int bpp)
5994{
5995 struct drm_i915_gem_object *obj;
308e5bcb 5996 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5997
5998 obj = i915_gem_alloc_object(dev,
5999 intel_framebuffer_size_for_mode(mode, bpp));
6000 if (obj == NULL)
6001 return ERR_PTR(-ENOMEM);
6002
6003 mode_cmd.width = mode->hdisplay;
6004 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6005 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6006 bpp);
5ca0c34a 6007 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6008
6009 return intel_framebuffer_create(dev, &mode_cmd, obj);
6010}
6011
6012static struct drm_framebuffer *
6013mode_fits_in_fbdev(struct drm_device *dev,
6014 struct drm_display_mode *mode)
6015{
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017 struct drm_i915_gem_object *obj;
6018 struct drm_framebuffer *fb;
6019
6020 if (dev_priv->fbdev == NULL)
6021 return NULL;
6022
6023 obj = dev_priv->fbdev->ifb.obj;
6024 if (obj == NULL)
6025 return NULL;
6026
6027 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6028 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6029 fb->bits_per_pixel))
d2dff872
CW		 6030 return NULL;
6031
01f2c773 6032 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6033 return NULL;
6034
6035 return fb;
6036}
6037
d2434ab7 6038bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6039 struct drm_display_mode *mode,
8261b191 6040 struct intel_load_detect_pipe *old)
79e53945
JB		 6041{
6042 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6043 struct intel_encoder *intel_encoder =
6044 intel_attached_encoder(connector);
79e53945 6045 struct drm_crtc *possible_crtc;
4ef69c7a 6046 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6047 struct drm_crtc *crtc = NULL;
6048 struct drm_device *dev = encoder->dev;
94352cf9 6049 struct drm_framebuffer *fb;
79e53945
JB		 6050 int i = -1;
6051
d2dff872
CW		 6052 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6053 connector->base.id, drm_get_connector_name(connector),
6054 encoder->base.id, drm_get_encoder_name(encoder));
6055
79e53945
JB		 6056 /*
6057 * Algorithm gets a little messy:
7a5e4805 6058 *
79e53945
JB		 6059 * - if the connector already has an assigned crtc, use it (but make
6060 * sure it's on first)
7a5e4805 6061 *
79e53945
JB		 6062 * - try to find the first unused crtc that can drive this connector,
6063 * and use that if we find one
79e53945
JB		 6064 */
6065
6066 /* See if we already have a CRTC for this connector */
6067 if (encoder->crtc) {
6068 crtc = encoder->crtc;
8261b191 6069
24218aac 6070 old->dpms_mode = connector->dpms;
8261b191
CW		 6071 old->load_detect_temp = false;
6072
6073 /* Make sure the crtc and connector are running */
24218aac
DV		 6074 if (connector->dpms != DRM_MODE_DPMS_ON)
6075 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6076
7173188d 6077 return true;
79e53945
JB		 6078 }
6079
6080 /* Find an unused one (if possible) */
6081 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6082 i++;
6083 if (!(encoder->possible_crtcs & (1 << i)))
6084 continue;
6085 if (!possible_crtc->enabled) {
6086 crtc = possible_crtc;
6087 break;
6088 }
79e53945
JB		 6089 }
6090
6091 /*
6092 * If we didn't find an unused CRTC, don't use any.
6093 */
6094 if (!crtc) {
7173188d
CW		 6095 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6096 return false;
79e53945
JB		 6097 }
6098
fc303101
DV		 6099 intel_encoder->new_crtc = to_intel_crtc(crtc);
6100 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6101
6102 intel_crtc = to_intel_crtc(crtc);
24218aac 6103 old->dpms_mode = connector->dpms;
8261b191 6104 old->load_detect_temp = true;
d2dff872 6105 old->release_fb = NULL;
79e53945 6106
6492711d
CW		 6107 if (!mode)
6108 mode = &load_detect_mode;
79e53945 6109
d2dff872
CW		 6110 /* We need a framebuffer large enough to accommodate all accesses
6111 * that the plane may generate whilst we perform load detection.
6112 * We can not rely on the fbcon either being present (we get called
6113 * during its initialisation to detect all boot displays, or it may
6114 * not even exist) or that it is large enough to satisfy the
6115 * requested mode.
6116 */
94352cf9
DV		 6117 fb = mode_fits_in_fbdev(dev, mode);
6118 if (fb == NULL) {
d2dff872 6119 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6120 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6121 old->release_fb = fb;
d2dff872
CW		 6122 } else
6123 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6124 if (IS_ERR(fb)) {
d2dff872 6125 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6126 goto fail;
79e53945 6127 }
79e53945 6128
94352cf9 6129 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6130 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6131 if (old->release_fb)
6132 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6133 goto fail;
79e53945 6134 }
7173188d 6135
79e53945 6136 /* let the connector get through one full cycle before testing */
9d0498a2 6137 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6138
7173188d 6139 return true;
24218aac
DV		 6140fail:
6141 connector->encoder = NULL;
6142 encoder->crtc = NULL;
24218aac 6143 return false;
79e53945
JB		 6144}
6145
d2434ab7 6146void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6147 struct intel_load_detect_pipe *old)
79e53945 6148{
d2434ab7
DV		 6149 struct intel_encoder *intel_encoder =
6150 intel_attached_encoder(connector);
4ef69c7a 6151 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6152
d2dff872
CW		 6153 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6154 connector->base.id, drm_get_connector_name(connector),
6155 encoder->base.id, drm_get_encoder_name(encoder));
6156
8261b191 6157 if (old->load_detect_temp) {
fc303101
DV		 6158 struct drm_crtc *crtc = encoder->crtc;
6159
6160 to_intel_connector(connector)->new_encoder = NULL;
6161 intel_encoder->new_crtc = NULL;
6162 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6163
6164 if (old->release_fb)
6165 old->release_fb->funcs->destroy(old->release_fb);
6166
0622a53c 6167 return;
79e53945
JB		 6168 }
6169
c751ce4f 6170 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6171 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6172 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6173}
6174
6175/* Returns the clock of the currently programmed mode of the given pipe. */
6176static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6177{
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 int pipe = intel_crtc->pipe;
548f245b 6181 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6182 u32 fp;
6183 intel_clock_t clock;
6184
6185 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6186 fp = I915_READ(FP0(pipe));
79e53945 6187 else
39adb7a5 6188 fp = I915_READ(FP1(pipe));
79e53945
JB		 6189
6190 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6191 if (IS_PINEVIEW(dev)) {
6192 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6193 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6194 } else {
6195 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6196 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6197 }
6198
a6c45cf0 6199 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6200 if (IS_PINEVIEW(dev))
6201 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6202 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6203 else
6204 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6205 DPLL_FPA01_P1_POST_DIV_SHIFT);
6206
6207 switch (dpll & DPLL_MODE_MASK) {
6208 case DPLLB_MODE_DAC_SERIAL:
6209 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6210 5 : 10;
6211 break;
6212 case DPLLB_MODE_LVDS:
6213 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6214 7 : 14;
6215 break;
6216 default:
28c97730 6217 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6218 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6219 return 0;
6220 }
6221
6222 /* XXX: Handle the 100Mhz refclk */
2177832f 6223 intel_clock(dev, 96000, &clock);
79e53945
JB		 6224 } else {
6225 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6226
6227 if (is_lvds) {
6228 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6229 DPLL_FPA01_P1_POST_DIV_SHIFT);
6230 clock.p2 = 14;
6231
6232 if ((dpll & PLL_REF_INPUT_MASK) ==
6233 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6234 /* XXX: might not be 66MHz */
2177832f 6235 intel_clock(dev, 66000, &clock);
79e53945 6236 } else
2177832f 6237 intel_clock(dev, 48000, &clock);
79e53945
JB		 6238 } else {
6239 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6240 clock.p1 = 2;
6241 else {
6242 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6243 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6244 }
6245 if (dpll & PLL_P2_DIVIDE_BY_4)
6246 clock.p2 = 4;
6247 else
6248 clock.p2 = 2;
6249
2177832f 6250 intel_clock(dev, 48000, &clock);
79e53945
JB		 6251 }
6252 }
6253
6254 /* XXX: It would be nice to validate the clocks, but we can't reuse
6255 * i830PllIsValid() because it relies on the xf86_config connector
6256 * configuration being accurate, which it isn't necessarily.
6257 */
6258
6259 return clock.dot;
6260}
6261
6262/** Returns the currently programmed mode of the given pipe. */
6263struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6264 struct drm_crtc *crtc)
6265{
548f245b 6266 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6268 int pipe = intel_crtc->pipe;
6269 struct drm_display_mode *mode;
548f245b
JB		 6270 int htot = I915_READ(HTOTAL(pipe));
6271 int hsync = I915_READ(HSYNC(pipe));
6272 int vtot = I915_READ(VTOTAL(pipe));
6273 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6274
6275 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6276 if (!mode)
6277 return NULL;
6278
6279 mode->clock = intel_crtc_clock_get(dev, crtc);
6280 mode->hdisplay = (htot & 0xffff) + 1;
6281 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6282 mode->hsync_start = (hsync & 0xffff) + 1;
6283 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6284 mode->vdisplay = (vtot & 0xffff) + 1;
6285 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6286 mode->vsync_start = (vsync & 0xffff) + 1;
6287 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6288
6289 drm_mode_set_name(mode);
79e53945
JB		 6290
6291 return mode;
6292}
6293
3dec0095 6294static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6295{
6296 struct drm_device *dev = crtc->dev;
6297 drm_i915_private_t *dev_priv = dev->dev_private;
6298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6300 int dpll_reg = DPLL(pipe);
6301 int dpll;
652c393a 6302
bad720ff 6303 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6304 return;
6305
6306 if (!dev_priv->lvds_downclock_avail)
6307 return;
6308
dbdc6479 6309 dpll = I915_READ(dpll_reg);
652c393a 6310 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6311 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6312
8ac5a6d5 6313 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6314
6315 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6316 I915_WRITE(dpll_reg, dpll);
9d0498a2 6317 intel_wait_for_vblank(dev, pipe);
dbdc6479 6318
652c393a
JB		 6319 dpll = I915_READ(dpll_reg);
6320 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6321 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6322 }
652c393a
JB		 6323}
6324
6325static void intel_decrease_pllclock(struct drm_crtc *crtc)
6326{
6327 struct drm_device *dev = crtc->dev;
6328 drm_i915_private_t *dev_priv = dev->dev_private;
6329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6330
bad720ff 6331 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6332 return;
6333
6334 if (!dev_priv->lvds_downclock_avail)
6335 return;
6336
6337 /*
6338 * Since this is called by a timer, we should never get here in
6339 * the manual case.
6340 */
6341 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6342 int pipe = intel_crtc->pipe;
6343 int dpll_reg = DPLL(pipe);
6344 int dpll;
f6e5b160 6345
44d98a61 6346 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6347
8ac5a6d5 6348 assert_panel_unlocked(dev_priv, pipe);
652c393a 6349
dc257cf1 6350 dpll = I915_READ(dpll_reg);
652c393a
JB		 6351 dpll |= DISPLAY_RATE_SELECT_FPA1;
6352 I915_WRITE(dpll_reg, dpll);
9d0498a2 6353 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6354 dpll = I915_READ(dpll_reg);
6355 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6356 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6357 }
6358
6359}
6360
f047e395
CW		 6361void intel_mark_busy(struct drm_device *dev)
6362{
f047e395
CW		 6363 i915_update_gfx_val(dev->dev_private);
6364}
6365
6366void intel_mark_idle(struct drm_device *dev)
652c393a 6367{
f047e395
CW		 6368}
6369
6370void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6371{
6372 struct drm_device *dev = obj->base.dev;
652c393a 6373 struct drm_crtc *crtc;
652c393a
JB		 6374
6375 if (!i915_powersave)
6376 return;
6377
652c393a 6378 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6379 if (!crtc->fb)
6380 continue;
6381
f047e395
CW		 6382 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6383 intel_increase_pllclock(crtc);
652c393a 6384 }
652c393a
JB		 6385}
6386
f047e395 6387void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6388{
f047e395
CW		 6389 struct drm_device *dev = obj->base.dev;
6390 struct drm_crtc *crtc;
652c393a 6391
f047e395 6392 if (!i915_powersave)
acb87dfb
CW		 6393 return;
6394
652c393a
JB		 6395 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6396 if (!crtc->fb)
6397 continue;
6398
f047e395
CW		 6399 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6400 intel_decrease_pllclock(crtc);
652c393a
JB		 6401 }
6402}
6403
79e53945
JB		 6404static void intel_crtc_destroy(struct drm_crtc *crtc)
6405{
6406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6407 struct drm_device *dev = crtc->dev;
6408 struct intel_unpin_work *work;
6409 unsigned long flags;
6410
6411 spin_lock_irqsave(&dev->event_lock, flags);
6412 work = intel_crtc->unpin_work;
6413 intel_crtc->unpin_work = NULL;
6414 spin_unlock_irqrestore(&dev->event_lock, flags);
6415
6416 if (work) {
6417 cancel_work_sync(&work->work);
6418 kfree(work);
6419 }
79e53945
JB		 6420
6421 drm_crtc_cleanup(crtc);
67e77c5a 6422
79e53945
JB		 6423 kfree(intel_crtc);
6424}
6425
6b95a207
KH		 6426static void intel_unpin_work_fn(struct work_struct *__work)
6427{
6428 struct intel_unpin_work *work =
6429 container_of(__work, struct intel_unpin_work, work);
6430
6431 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6432 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6433 drm_gem_object_unreference(&work->pending_flip_obj->base);
6434 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6435
7782de3b 6436 intel_update_fbc(work->dev);
6b95a207
KH		 6437 mutex_unlock(&work->dev->struct_mutex);
6438 kfree(work);
6439}
6440
1afe3e9d 6441static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6442 struct drm_crtc *crtc)
6b95a207
KH		 6443{
6444 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6446 struct intel_unpin_work *work;
05394f39 6447 struct drm_i915_gem_object *obj;
6b95a207 6448 struct drm_pending_vblank_event *e;
49b14a5c 6449 struct timeval tnow, tvbl;
6b95a207
KH		 6450 unsigned long flags;
6451
6452 /* Ignore early vblank irqs */
6453 if (intel_crtc == NULL)
6454 return;
6455
49b14a5c
MK		 6456 do_gettimeofday(&tnow);
6457
6b95a207
KH		 6458 spin_lock_irqsave(&dev->event_lock, flags);
6459 work = intel_crtc->unpin_work;
6460 if (work == NULL || !work->pending) {
6461 spin_unlock_irqrestore(&dev->event_lock, flags);
6462 return;
6463 }
6464
6465 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6466
6467 if (work->event) {
6468 e = work->event;
49b14a5c 6469 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6470
6471 /* Called before vblank count and timestamps have
6472 * been updated for the vblank interval of flip
6473 * completion? Need to increment vblank count and
6474 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6475 * to account for this. We assume this happened if we
6476 * get called over 0.9 frame durations after the last
6477 * timestamped vblank.
6478 *
6479 * This calculation can not be used with vrefresh rates
6480 * below 5Hz (10Hz to be on the safe side) without
6481 * promoting to 64 integers.
0af7e4df 6482 */
49b14a5c
MK		 6483 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6484 9 * crtc->framedur_ns) {
0af7e4df 6485 e->event.sequence++;
49b14a5c
MK		 6486 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6487 crtc->framedur_ns);
0af7e4df
MK		 6488 }
6489
49b14a5c
MK		 6490 e->event.tv_sec = tvbl.tv_sec;
6491 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6492
6b95a207
KH		 6493 list_add_tail(&e->base.link,
6494 &e->base.file_priv->event_list);
6495 wake_up_interruptible(&e->base.file_priv->event_wait);
6496 }
6497
0af7e4df
MK		 6498 drm_vblank_put(dev, intel_crtc->pipe);
6499
6b95a207
KH		 6500 spin_unlock_irqrestore(&dev->event_lock, flags);
6501
05394f39 6502 obj = work->old_fb_obj;
d9e86c0e 6503
e59f2bac 6504 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6505 &obj->pending_flip.counter);
6506 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6507 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6508
6b95a207 6509 schedule_work(&work->work);
e5510fac
JB		 6510
6511 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6512}
6513
1afe3e9d
JB		 6514void intel_finish_page_flip(struct drm_device *dev, int pipe)
6515{
6516 drm_i915_private_t *dev_priv = dev->dev_private;
6517 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6518
49b14a5c 6519 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6520}
6521
6522void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6523{
6524 drm_i915_private_t *dev_priv = dev->dev_private;
6525 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6526
49b14a5c 6527 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6528}
6529
6b95a207
KH		 6530void intel_prepare_page_flip(struct drm_device *dev, int plane)
6531{
6532 drm_i915_private_t *dev_priv = dev->dev_private;
6533 struct intel_crtc *intel_crtc =
6534 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6535 unsigned long flags;
6536
6537 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6538 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6539 if ((++intel_crtc->unpin_work->pending) > 1)
6540 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6541 } else {
6542 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6543 }
6b95a207
KH		 6544 spin_unlock_irqrestore(&dev->event_lock, flags);
6545}
6546
8c9f3aaf
JB		 6547static int intel_gen2_queue_flip(struct drm_device *dev,
6548 struct drm_crtc *crtc,
6549 struct drm_framebuffer *fb,
6550 struct drm_i915_gem_object *obj)
6551{
6552 struct drm_i915_private *dev_priv = dev->dev_private;
6553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6554 u32 flip_mask;
6d90c952 6555 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6556 int ret;
6557
6d90c952 6558 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6559 if (ret)
83d4092b 6560 goto err;
8c9f3aaf 6561
6d90c952 6562 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6563 if (ret)
83d4092b 6564 goto err_unpin;
8c9f3aaf
JB		 6565
6566 /* Can't queue multiple flips, so wait for the previous
6567 * one to finish before executing the next.
6568 */
6569 if (intel_crtc->plane)
6570 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6571 else
6572 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6573 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6574 intel_ring_emit(ring, MI_NOOP);
6575 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6576 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6577 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6578 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6579 intel_ring_emit(ring, 0); /* aux display base address, unused */
6580 intel_ring_advance(ring);
83d4092b
CW		 6581 return 0;
6582
6583err_unpin:
6584 intel_unpin_fb_obj(obj);
6585err:
8c9f3aaf
JB		 6586 return ret;
6587}
6588
6589static int intel_gen3_queue_flip(struct drm_device *dev,
6590 struct drm_crtc *crtc,
6591 struct drm_framebuffer *fb,
6592 struct drm_i915_gem_object *obj)
6593{
6594 struct drm_i915_private *dev_priv = dev->dev_private;
6595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6596 u32 flip_mask;
6d90c952 6597 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6598 int ret;
6599
6d90c952 6600 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6601 if (ret)
83d4092b 6602 goto err;
8c9f3aaf 6603
6d90c952 6604 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6605 if (ret)
83d4092b 6606 goto err_unpin;
8c9f3aaf
JB		 6607
6608 if (intel_crtc->plane)
6609 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6610 else
6611 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6612 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6613 intel_ring_emit(ring, MI_NOOP);
6614 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6615 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6616 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6617 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6618 intel_ring_emit(ring, MI_NOOP);
6619
6620 intel_ring_advance(ring);
83d4092b
CW		 6621 return 0;
6622
6623err_unpin:
6624 intel_unpin_fb_obj(obj);
6625err:
8c9f3aaf
JB		 6626 return ret;
6627}
6628
6629static int intel_gen4_queue_flip(struct drm_device *dev,
6630 struct drm_crtc *crtc,
6631 struct drm_framebuffer *fb,
6632 struct drm_i915_gem_object *obj)
6633{
6634 struct drm_i915_private *dev_priv = dev->dev_private;
6635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6636 uint32_t pf, pipesrc;
6d90c952 6637 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6638 int ret;
6639
6d90c952 6640 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6641 if (ret)
83d4092b 6642 goto err;
8c9f3aaf 6643
6d90c952 6644 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6645 if (ret)
83d4092b 6646 goto err_unpin;
8c9f3aaf
JB		 6647
6648 /* i965+ uses the linear or tiled offsets from the
6649 * Display Registers (which do not change across a page-flip)
6650 * so we need only reprogram the base address.
6651 */
6d90c952
DV		 6652 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6653 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6654 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6655 intel_ring_emit(ring,
6656 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6657 obj->tiling_mode);
8c9f3aaf
JB		 6658
6659 /* XXX Enabling the panel-fitter across page-flip is so far
6660 * untested on non-native modes, so ignore it for now.
6661 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6662 */
6663 pf = 0;
6664 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6665 intel_ring_emit(ring, pf | pipesrc);
6666 intel_ring_advance(ring);
83d4092b
CW		 6667 return 0;
6668
6669err_unpin:
6670 intel_unpin_fb_obj(obj);
6671err:
8c9f3aaf
JB		 6672 return ret;
6673}
6674
6675static int intel_gen6_queue_flip(struct drm_device *dev,
6676 struct drm_crtc *crtc,
6677 struct drm_framebuffer *fb,
6678 struct drm_i915_gem_object *obj)
6679{
6680 struct drm_i915_private *dev_priv = dev->dev_private;
6681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6682 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6683 uint32_t pf, pipesrc;
6684 int ret;
6685
6d90c952 6686 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6687 if (ret)
83d4092b 6688 goto err;
8c9f3aaf 6689
6d90c952 6690 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6691 if (ret)
83d4092b 6692 goto err_unpin;
8c9f3aaf 6693
6d90c952
DV		 6694 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6695 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6696 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6697 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6698
dc257cf1
DV		 6699 /* Contrary to the suggestions in the documentation,
6700 * "Enable Panel Fitter" does not seem to be required when page
6701 * flipping with a non-native mode, and worse causes a normal
6702 * modeset to fail.
6703 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6704 */
6705 pf = 0;
8c9f3aaf 6706 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6707 intel_ring_emit(ring, pf | pipesrc);
6708 intel_ring_advance(ring);
83d4092b
CW		 6709 return 0;
6710
6711err_unpin:
6712 intel_unpin_fb_obj(obj);
6713err:
8c9f3aaf
JB		 6714 return ret;
6715}
6716
7c9017e5
JB		 6717/*
6718 * On gen7 we currently use the blit ring because (in early silicon at least)
6719 * the render ring doesn't give us interrpts for page flip completion, which
6720 * means clients will hang after the first flip is queued. Fortunately the
6721 * blit ring generates interrupts properly, so use it instead.
6722 */
6723static int intel_gen7_queue_flip(struct drm_device *dev,
6724 struct drm_crtc *crtc,
6725 struct drm_framebuffer *fb,
6726 struct drm_i915_gem_object *obj)
6727{
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6730 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6731 uint32_t plane_bit = 0;
7c9017e5
JB		 6732 int ret;
6733
6734 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6735 if (ret)
83d4092b 6736 goto err;
7c9017e5 6737
cb05d8de
DV		 6738 switch(intel_crtc->plane) {
6739 case PLANE_A:
6740 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6741 break;
6742 case PLANE_B:
6743 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6744 break;
6745 case PLANE_C:
6746 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6747 break;
6748 default:
6749 WARN_ONCE(1, "unknown plane in flip command\n");
6750 ret = -ENODEV;
ab3951eb 6751 goto err_unpin;
cb05d8de
DV		 6752 }
6753
7c9017e5
JB		 6754 ret = intel_ring_begin(ring, 4);
6755 if (ret)
83d4092b 6756 goto err_unpin;
7c9017e5 6757
cb05d8de 6758 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6759 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6760 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6761 intel_ring_emit(ring, (MI_NOOP));
6762 intel_ring_advance(ring);
83d4092b
CW		 6763 return 0;
6764
6765err_unpin:
6766 intel_unpin_fb_obj(obj);
6767err:
7c9017e5
JB		 6768 return ret;
6769}
6770
8c9f3aaf
JB		 6771static int intel_default_queue_flip(struct drm_device *dev,
6772 struct drm_crtc *crtc,
6773 struct drm_framebuffer *fb,
6774 struct drm_i915_gem_object *obj)
6775{
6776 return -ENODEV;
6777}
6778
6b95a207
KH		 6779static int intel_crtc_page_flip(struct drm_crtc *crtc,
6780 struct drm_framebuffer *fb,
6781 struct drm_pending_vblank_event *event)
6782{
6783 struct drm_device *dev = crtc->dev;
6784 struct drm_i915_private *dev_priv = dev->dev_private;
6785 struct intel_framebuffer *intel_fb;
05394f39 6786 struct drm_i915_gem_object *obj;
6b95a207
KH		 6787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6788 struct intel_unpin_work *work;
8c9f3aaf 6789 unsigned long flags;
52e68630 6790 int ret;
6b95a207 6791
e6a595d2
VS		 6792 /* Can't change pixel format via MI display flips. */
6793 if (fb->pixel_format != crtc->fb->pixel_format)
6794 return -EINVAL;
6795
6796 /*
6797 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6798 * Note that pitch changes could also affect these register.
6799 */
6800 if (INTEL_INFO(dev)->gen > 3 &&
6801 (fb->offsets[0] != crtc->fb->offsets[0] ||
6802 fb->pitches[0] != crtc->fb->pitches[0]))
6803 return -EINVAL;
6804
6b95a207
KH		 6805 work = kzalloc(sizeof *work, GFP_KERNEL);
6806 if (work == NULL)
6807 return -ENOMEM;
6808
6b95a207
KH		 6809 work->event = event;
6810 work->dev = crtc->dev;
6811 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6812 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6813 INIT_WORK(&work->work, intel_unpin_work_fn);
6814
7317c75e
JB		 6815 ret = drm_vblank_get(dev, intel_crtc->pipe);
6816 if (ret)
6817 goto free_work;
6818
6b95a207
KH		 6819 /* We borrow the event spin lock for protecting unpin_work */
6820 spin_lock_irqsave(&dev->event_lock, flags);
6821 if (intel_crtc->unpin_work) {
6822 spin_unlock_irqrestore(&dev->event_lock, flags);
6823 kfree(work);
7317c75e 6824 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6825
6826 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6827 return -EBUSY;
6828 }
6829 intel_crtc->unpin_work = work;
6830 spin_unlock_irqrestore(&dev->event_lock, flags);
6831
6832 intel_fb = to_intel_framebuffer(fb);
6833 obj = intel_fb->obj;
6834
79158103
CW		 6835 ret = i915_mutex_lock_interruptible(dev);
6836 if (ret)
6837 goto cleanup;
6b95a207 6838
75dfca80 6839 /* Reference the objects for the scheduled work. */
05394f39
CW		 6840 drm_gem_object_reference(&work->old_fb_obj->base);
6841 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6842
6843 crtc->fb = fb;
96b099fd 6844
e1f99ce6 6845 work->pending_flip_obj = obj;
e1f99ce6 6846
4e5359cd
SF		 6847 work->enable_stall_check = true;
6848
e1f99ce6
CW		 6849 /* Block clients from rendering to the new back buffer until
6850 * the flip occurs and the object is no longer visible.
6851 */
05394f39 6852 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6853
8c9f3aaf
JB		 6854 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6855 if (ret)
6856 goto cleanup_pending;
6b95a207 6857
7782de3b 6858 intel_disable_fbc(dev);
f047e395 6859 intel_mark_fb_busy(obj);
6b95a207
KH		 6860 mutex_unlock(&dev->struct_mutex);
6861
e5510fac
JB		 6862 trace_i915_flip_request(intel_crtc->plane, obj);
6863
6b95a207 6864 return 0;
96b099fd 6865
8c9f3aaf
JB		 6866cleanup_pending:
6867 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6868 drm_gem_object_unreference(&work->old_fb_obj->base);
6869 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6870 mutex_unlock(&dev->struct_mutex);
6871
79158103 6872cleanup:
96b099fd
CW		 6873 spin_lock_irqsave(&dev->event_lock, flags);
6874 intel_crtc->unpin_work = NULL;
6875 spin_unlock_irqrestore(&dev->event_lock, flags);
6876
7317c75e
JB		 6877 drm_vblank_put(dev, intel_crtc->pipe);
6878free_work:
96b099fd
CW		 6879 kfree(work);
6880
6881 return ret;
6b95a207
KH		 6882}
6883
f6e5b160 6884static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6885 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6886 .load_lut = intel_crtc_load_lut,
976f8a20 6887 .disable = intel_crtc_noop,
f6e5b160
CW		 6888};
6889
6ed0f796 6890bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 6891{
6ed0f796
DV		 6892 struct intel_encoder *other_encoder;
6893 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 6894
6ed0f796
DV		 6895 if (WARN_ON(!crtc))
6896 return false;
6897
6898 list_for_each_entry(other_encoder,
6899 &crtc->dev->mode_config.encoder_list,
6900 base.head) {
6901
6902 if (&other_encoder->new_crtc->base != crtc ||
6903 encoder == other_encoder)
6904 continue;
6905 else
6906 return true;
f47166d2
CW		 6907 }
6908
6ed0f796
DV		 6909 return false;
6910}
47f1c6c9 6911
50f56119
DV		 6912static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6913 struct drm_crtc *crtc)
6914{
6915 struct drm_device *dev;
6916 struct drm_crtc *tmp;
6917 int crtc_mask = 1;
47f1c6c9 6918
50f56119 6919 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 6920
50f56119 6921 dev = crtc->dev;
47f1c6c9 6922
50f56119
DV		 6923 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6924 if (tmp == crtc)
6925 break;
6926 crtc_mask <<= 1;
6927 }
47f1c6c9 6928
50f56119
DV		 6929 if (encoder->possible_crtcs & crtc_mask)
6930 return true;
6931 return false;
47f1c6c9 6932}
79e53945 6933
9a935856
DV		 6934/**
6935 * intel_modeset_update_staged_output_state
6936 *
6937 * Updates the staged output configuration state, e.g. after we've read out the
6938 * current hw state.
6939 */
6940static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 6941{
9a935856
DV		 6942 struct intel_encoder *encoder;
6943 struct intel_connector *connector;
f6e5b160 6944
9a935856
DV		 6945 list_for_each_entry(connector, &dev->mode_config.connector_list,
6946 base.head) {
6947 connector->new_encoder =
6948 to_intel_encoder(connector->base.encoder);
6949 }
f6e5b160 6950
9a935856
DV		 6951 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6952 base.head) {
6953 encoder->new_crtc =
6954 to_intel_crtc(encoder->base.crtc);
6955 }
f6e5b160
CW		 6956}
6957
9a935856
DV		 6958/**
6959 * intel_modeset_commit_output_state
6960 *
6961 * This function copies the stage display pipe configuration to the real one.
6962 */
6963static void intel_modeset_commit_output_state(struct drm_device *dev)
6964{
6965 struct intel_encoder *encoder;
6966 struct intel_connector *connector;
f6e5b160 6967
9a935856
DV		 6968 list_for_each_entry(connector, &dev->mode_config.connector_list,
6969 base.head) {
6970 connector->base.encoder = &connector->new_encoder->base;
6971 }
f6e5b160 6972
9a935856
DV		 6973 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6974 base.head) {
6975 encoder->base.crtc = &encoder->new_crtc->base;
6976 }
6977}
6978
7758a113
DV		 6979static struct drm_display_mode *
6980intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6981 struct drm_display_mode *mode)
ee7b9f93 6982{
7758a113
DV		 6983 struct drm_device *dev = crtc->dev;
6984 struct drm_display_mode *adjusted_mode;
6985 struct drm_encoder_helper_funcs *encoder_funcs;
6986 struct intel_encoder *encoder;
ee7b9f93 6987
7758a113
DV		 6988 adjusted_mode = drm_mode_duplicate(dev, mode);
6989 if (!adjusted_mode)
6990 return ERR_PTR(-ENOMEM);
6991
6992 /* Pass our mode to the connectors and the CRTC to give them a chance to
6993 * adjust it according to limitations or connector properties, and also
6994 * a chance to reject the mode entirely.
6995 */
6996 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6997 base.head) {
6998
6999 if (&encoder->new_crtc->base != crtc)
7000 continue;
7001 encoder_funcs = encoder->base.helper_private;
7002 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7003 adjusted_mode))) {
7004 DRM_DEBUG_KMS("Encoder fixup failed\n");
7005 goto fail;
7006 }
ee7b9f93
JB		 7007 }
7008
7758a113
DV		 7009 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7010 DRM_DEBUG_KMS("CRTC fixup failed\n");
7011 goto fail;
ee7b9f93 7012 }
7758a113
DV		 7013 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7014
7015 return adjusted_mode;
7016fail:
7017 drm_mode_destroy(dev, adjusted_mode);
7018 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7019}
7020
e2e1ed41
DV		 7021/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7022 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7023static void
7024intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7025 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7026{
7027 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7028 struct drm_device *dev = crtc->dev;
7029 struct intel_encoder *encoder;
7030 struct intel_connector *connector;
7031 struct drm_crtc *tmp_crtc;
79e53945 7032
e2e1ed41 7033 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7034
e2e1ed41
DV		 7035 /* Check which crtcs have changed outputs connected to them, these need
7036 * to be part of the prepare_pipes mask. We don't (yet) support global
7037 * modeset across multiple crtcs, so modeset_pipes will only have one
7038 * bit set at most. */
7039 list_for_each_entry(connector, &dev->mode_config.connector_list,
7040 base.head) {
7041 if (connector->base.encoder == &connector->new_encoder->base)
7042 continue;
79e53945 7043
e2e1ed41
DV		 7044 if (connector->base.encoder) {
7045 tmp_crtc = connector->base.encoder->crtc;
7046
7047 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7048 }
7049
7050 if (connector->new_encoder)
7051 *prepare_pipes |=
7052 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7053 }
7054
e2e1ed41
DV		 7055 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7056 base.head) {
7057 if (encoder->base.crtc == &encoder->new_crtc->base)
7058 continue;
7059
7060 if (encoder->base.crtc) {
7061 tmp_crtc = encoder->base.crtc;
7062
7063 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7064 }
7065
7066 if (encoder->new_crtc)
7067 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7068 }
7069
e2e1ed41
DV		 7070 /* Check for any pipes that will be fully disabled ... */
7071 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7072 base.head) {
7073 bool used = false;
22fd0fab 7074
e2e1ed41
DV		 7075 /* Don't try to disable disabled crtcs. */
7076 if (!intel_crtc->base.enabled)
7077 continue;
7e7d76c3 7078
e2e1ed41
DV		 7079 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7080 base.head) {
7081 if (encoder->new_crtc == intel_crtc)
7082 used = true;
7083 }
7084
7085 if (!used)
7086 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7087 }
7088
e2e1ed41
DV		 7089
7090 /* set_mode is also used to update properties on life display pipes. */
7091 intel_crtc = to_intel_crtc(crtc);
7092 if (crtc->enabled)
7093 *prepare_pipes |= 1 << intel_crtc->pipe;
7094
7095 /* We only support modeset on one single crtc, hence we need to do that
7096 * only for the passed in crtc iff we change anything else than just
7097 * disable crtcs.
7098 *
7099 * This is actually not true, to be fully compatible with the old crtc
7100 * helper we automatically disable _any_ output (i.e. doesn't need to be
7101 * connected to the crtc we're modesetting on) if it's disconnected.
7102 * Which is a rather nutty api (since changed the output configuration
7103 * without userspace's explicit request can lead to confusion), but
7104 * alas. Hence we currently need to modeset on all pipes we prepare. */
7105 if (*prepare_pipes)
7106 *modeset_pipes = *prepare_pipes;
7107
7108 /* ... and mask these out. */
7109 *modeset_pipes &= ~(*disable_pipes);
7110 *prepare_pipes &= ~(*disable_pipes);
7111}
7112
ea9d758d
DV		 7113static bool intel_crtc_in_use(struct drm_crtc *crtc)
7114{
7115 struct drm_encoder *encoder;
7116 struct drm_device *dev = crtc->dev;
7117
7118 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7119 if (encoder->crtc == crtc)
7120 return true;
7121
7122 return false;
7123}
7124
7125static void
7126intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7127{
7128 struct intel_encoder *intel_encoder;
7129 struct intel_crtc *intel_crtc;
7130 struct drm_connector *connector;
7131
7132 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7133 base.head) {
7134 if (!intel_encoder->base.crtc)
7135 continue;
7136
7137 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7138
7139 if (prepare_pipes & (1 << intel_crtc->pipe))
7140 intel_encoder->connectors_active = false;
7141 }
7142
7143 intel_modeset_commit_output_state(dev);
7144
7145 /* Update computed state. */
7146 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7147 base.head) {
7148 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7149 }
7150
7151 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7152 if (!connector->encoder || !connector->encoder->crtc)
7153 continue;
7154
7155 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7156
7157 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7158 struct drm_property *dpms_property =
7159 dev->mode_config.dpms_property;
7160
ea9d758d 7161 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7162 drm_connector_property_set_value(connector,
7163 dpms_property,
7164 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7165
7166 intel_encoder = to_intel_encoder(connector->encoder);
7167 intel_encoder->connectors_active = true;
7168 }
7169 }
7170
7171}
7172
25c5b266
DV		 7173#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7174 list_for_each_entry((intel_crtc), \
7175 &(dev)->mode_config.crtc_list, \
7176 base.head) \
7177 if (mask & (1 <<(intel_crtc)->pipe)) \
7178
b980514c 7179void
8af6cf88
DV		 7180intel_modeset_check_state(struct drm_device *dev)
7181{
7182 struct intel_crtc *crtc;
7183 struct intel_encoder *encoder;
7184 struct intel_connector *connector;
7185
7186 list_for_each_entry(connector, &dev->mode_config.connector_list,
7187 base.head) {
7188 /* This also checks the encoder/connector hw state with the
7189 * ->get_hw_state callbacks. */
7190 intel_connector_check_state(connector);
7191
7192 WARN(&connector->new_encoder->base != connector->base.encoder,
7193 "connector's staged encoder doesn't match current encoder\n");
7194 }
7195
7196 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7197 base.head) {
7198 bool enabled = false;
7199 bool active = false;
7200 enum pipe pipe, tracked_pipe;
7201
7202 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7203 encoder->base.base.id,
7204 drm_get_encoder_name(&encoder->base));
7205
7206 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7207 "encoder's stage crtc doesn't match current crtc\n");
7208 WARN(encoder->connectors_active && !encoder->base.crtc,
7209 "encoder's active_connectors set, but no crtc\n");
7210
7211 list_for_each_entry(connector, &dev->mode_config.connector_list,
7212 base.head) {
7213 if (connector->base.encoder != &encoder->base)
7214 continue;
7215 enabled = true;
7216 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7217 active = true;
7218 }
7219 WARN(!!encoder->base.crtc != enabled,
7220 "encoder's enabled state mismatch "
7221 "(expected %i, found %i)\n",
7222 !!encoder->base.crtc, enabled);
7223 WARN(active && !encoder->base.crtc,
7224 "active encoder with no crtc\n");
7225
7226 WARN(encoder->connectors_active != active,
7227 "encoder's computed active state doesn't match tracked active state "
7228 "(expected %i, found %i)\n", active, encoder->connectors_active);
7229
7230 active = encoder->get_hw_state(encoder, &pipe);
7231 WARN(active != encoder->connectors_active,
7232 "encoder's hw state doesn't match sw tracking "
7233 "(expected %i, found %i)\n",
7234 encoder->connectors_active, active);
7235
7236 if (!encoder->base.crtc)
7237 continue;
7238
7239 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7240 WARN(active && pipe != tracked_pipe,
7241 "active encoder's pipe doesn't match"
7242 "(expected %i, found %i)\n",
7243 tracked_pipe, pipe);
7244
7245 }
7246
7247 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7248 base.head) {
7249 bool enabled = false;
7250 bool active = false;
7251
7252 DRM_DEBUG_KMS("[CRTC:%d]\n",
7253 crtc->base.base.id);
7254
7255 WARN(crtc->active && !crtc->base.enabled,
7256 "active crtc, but not enabled in sw tracking\n");
7257
7258 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7259 base.head) {
7260 if (encoder->base.crtc != &crtc->base)
7261 continue;
7262 enabled = true;
7263 if (encoder->connectors_active)
7264 active = true;
7265 }
7266 WARN(active != crtc->active,
7267 "crtc's computed active state doesn't match tracked active state "
7268 "(expected %i, found %i)\n", active, crtc->active);
7269 WARN(enabled != crtc->base.enabled,
7270 "crtc's computed enabled state doesn't match tracked enabled state "
7271 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7272
7273 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7274 }
7275}
7276
a6778b3c
DV		 7277bool intel_set_mode(struct drm_crtc *crtc,
7278 struct drm_display_mode *mode,
94352cf9 7279 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7280{
7281 struct drm_device *dev = crtc->dev;
dbf2b54e 7282 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7283 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 7284 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 7285 struct drm_encoder *encoder;
25c5b266
DV		 7286 struct intel_crtc *intel_crtc;
7287 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7288 bool ret = true;
7289
e2e1ed41 7290 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7291 &prepare_pipes, &disable_pipes);
7292
7293 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7294 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7295
976f8a20
DV		 7296 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7297 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7298
a6778b3c
DV		 7299 saved_hwmode = crtc->hwmode;
7300 saved_mode = crtc->mode;
a6778b3c 7301
25c5b266
DV		 7302 /* Hack: Because we don't (yet) support global modeset on multiple
7303 * crtcs, we don't keep track of the new mode for more than one crtc.
7304 * Hence simply check whether any bit is set in modeset_pipes in all the
7305 * pieces of code that are not yet converted to deal with mutliple crtcs
7306 * changing their mode at the same time. */
7307 adjusted_mode = NULL;
7308 if (modeset_pipes) {
7309 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7310 if (IS_ERR(adjusted_mode)) {
7311 return false;
7312 }
25c5b266 7313 }
a6778b3c 7314
ea9d758d
DV		 7315 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7316 if (intel_crtc->base.enabled)
7317 dev_priv->display.crtc_disable(&intel_crtc->base);
7318 }
a6778b3c 7319
6c4c86f5
DV		 7320 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7321 * to set it here already despite that we pass it down the callchain.
7322 */
7323 if (modeset_pipes)
25c5b266 7324 crtc->mode = *mode;
7758a113 7325
ea9d758d
DV		 7326 /* Only after disabling all output pipelines that will be changed can we
7327 * update the the output configuration. */
7328 intel_modeset_update_state(dev, prepare_pipes);
7329
a6778b3c
DV		 7330 /* Set up the DPLL and any encoders state that needs to adjust or depend
7331 * on the DPLL.
7332 */
25c5b266
DV		 7333 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7334 ret = !intel_crtc_mode_set(&intel_crtc->base,
7335 mode, adjusted_mode,
7336 x, y, fb);
7337 if (!ret)
7338 goto done;
a6778b3c 7339
25c5b266 7340 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7341
25c5b266
DV		 7342 if (encoder->crtc != &intel_crtc->base)
7343 continue;
a6778b3c 7344
25c5b266
DV		 7345 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7346 encoder->base.id, drm_get_encoder_name(encoder),
7347 mode->base.id, mode->name);
7348 encoder_funcs = encoder->helper_private;
7349 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7350 }
a6778b3c
DV		 7351 }
7352
7353 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7354 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7355 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7356
25c5b266
DV		 7357 if (modeset_pipes) {
7358 /* Store real post-adjustment hardware mode. */
7359 crtc->hwmode = *adjusted_mode;
a6778b3c 7360
25c5b266
DV		 7361 /* Calculate and store various constants which
7362 * are later needed by vblank and swap-completion
7363 * timestamping. They are derived from true hwmode.
7364 */
7365 drm_calc_timestamping_constants(crtc);
7366 }
a6778b3c
DV		 7367
7368 /* FIXME: add subpixel order */
7369done:
7370 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7371 if (!ret && crtc->enabled) {
a6778b3c
DV		 7372 crtc->hwmode = saved_hwmode;
7373 crtc->mode = saved_mode;
8af6cf88
DV		 7374 } else {
7375 intel_modeset_check_state(dev);
a6778b3c
DV		 7376 }
7377
7378 return ret;
7379}
7380
25c5b266
DV		 7381#undef for_each_intel_crtc_masked
7382
d9e55608
DV		 7383static void intel_set_config_free(struct intel_set_config *config)
7384{
7385 if (!config)
7386 return;
7387
1aa4b628
DV		 7388 kfree(config->save_connector_encoders);
7389 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7390 kfree(config);
7391}
7392
85f9eb71
DV		 7393static int intel_set_config_save_state(struct drm_device *dev,
7394 struct intel_set_config *config)
7395{
85f9eb71
DV		 7396 struct drm_encoder *encoder;
7397 struct drm_connector *connector;
7398 int count;
7399
1aa4b628
DV		 7400 config->save_encoder_crtcs =
7401 kcalloc(dev->mode_config.num_encoder,
7402 sizeof(struct drm_crtc *), GFP_KERNEL);
7403 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7404 return -ENOMEM;
7405
1aa4b628
DV		 7406 config->save_connector_encoders =
7407 kcalloc(dev->mode_config.num_connector,
7408 sizeof(struct drm_encoder *), GFP_KERNEL);
7409 if (!config->save_connector_encoders)
85f9eb71
DV		 7410 return -ENOMEM;
7411
7412 /* Copy data. Note that driver private data is not affected.
7413 * Should anything bad happen only the expected state is
7414 * restored, not the drivers personal bookkeeping.
7415 */
85f9eb71
DV		 7416 count = 0;
7417 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7418 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7419 }
7420
7421 count = 0;
7422 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7423 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7424 }
7425
7426 return 0;
7427}
7428
7429static void intel_set_config_restore_state(struct drm_device *dev,
7430 struct intel_set_config *config)
7431{
9a935856
DV		 7432 struct intel_encoder *encoder;
7433 struct intel_connector *connector;
85f9eb71
DV		 7434 int count;
7435
85f9eb71 7436 count = 0;
9a935856
DV		 7437 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7438 encoder->new_crtc =
7439 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7440 }
7441
7442 count = 0;
9a935856
DV		 7443 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7444 connector->new_encoder =
7445 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7446 }
7447}
7448
5e2b584e
DV		 7449static void
7450intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7451 struct intel_set_config *config)
7452{
7453
7454 /* We should be able to check here if the fb has the same properties
7455 * and then just flip_or_move it */
7456 if (set->crtc->fb != set->fb) {
7457 /* If we have no fb then treat it as a full mode set */
7458 if (set->crtc->fb == NULL) {
7459 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7460 config->mode_changed = true;
7461 } else if (set->fb == NULL) {
7462 config->mode_changed = true;
7463 } else if (set->fb->depth != set->crtc->fb->depth) {
7464 config->mode_changed = true;
7465 } else if (set->fb->bits_per_pixel !=
7466 set->crtc->fb->bits_per_pixel) {
7467 config->mode_changed = true;
7468 } else
7469 config->fb_changed = true;
7470 }
7471
835c5873 7472 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7473 config->fb_changed = true;
7474
7475 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7476 DRM_DEBUG_KMS("modes are different, full mode set\n");
7477 drm_mode_debug_printmodeline(&set->crtc->mode);
7478 drm_mode_debug_printmodeline(set->mode);
7479 config->mode_changed = true;
7480 }
7481}
7482
2e431051 7483static int
9a935856
DV		 7484intel_modeset_stage_output_state(struct drm_device *dev,
7485 struct drm_mode_set *set,
7486 struct intel_set_config *config)
50f56119 7487{
85f9eb71 7488 struct drm_crtc *new_crtc;
9a935856
DV		 7489 struct intel_connector *connector;
7490 struct intel_encoder *encoder;
2e431051 7491 int count, ro;
50f56119 7492
9a935856
DV		 7493 /* The upper layers ensure that we either disabl a crtc or have a list
7494 * of connectors. For paranoia, double-check this. */
7495 WARN_ON(!set->fb && (set->num_connectors != 0));
7496 WARN_ON(set->fb && (set->num_connectors == 0));
7497
50f56119 7498 count = 0;
9a935856
DV		 7499 list_for_each_entry(connector, &dev->mode_config.connector_list,
7500 base.head) {
7501 /* Otherwise traverse passed in connector list and get encoders
7502 * for them. */
50f56119 7503 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7504 if (set->connectors[ro] == &connector->base) {
7505 connector->new_encoder = connector->encoder;
50f56119
DV		 7506 break;
7507 }
7508 }
7509
9a935856
DV		 7510 /* If we disable the crtc, disable all its connectors. Also, if
7511 * the connector is on the changing crtc but not on the new
7512 * connector list, disable it. */
7513 if ((!set->fb || ro == set->num_connectors) &&
7514 connector->base.encoder &&
7515 connector->base.encoder->crtc == set->crtc) {
7516 connector->new_encoder = NULL;
7517
7518 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7519 connector->base.base.id,
7520 drm_get_connector_name(&connector->base));
7521 }
7522
7523
7524 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7525 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7526 config->mode_changed = true;
50f56119 7527 }
9a935856
DV		 7528
7529 /* Disable all disconnected encoders. */
7530 if (connector->base.status == connector_status_disconnected)
7531 connector->new_encoder = NULL;
50f56119 7532 }
9a935856 7533 /* connector->new_encoder is now updated for all connectors. */
50f56119 7534
9a935856 7535 /* Update crtc of enabled connectors. */
50f56119 7536 count = 0;
9a935856
DV		 7537 list_for_each_entry(connector, &dev->mode_config.connector_list,
7538 base.head) {
7539 if (!connector->new_encoder)
50f56119
DV		 7540 continue;
7541
9a935856 7542 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7543
7544 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7545 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7546 new_crtc = set->crtc;
7547 }
7548
7549 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7550 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7551 new_crtc)) {
5e2b584e 7552 return -EINVAL;
50f56119 7553 }
9a935856
DV		 7554 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7555
7556 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7557 connector->base.base.id,
7558 drm_get_connector_name(&connector->base),
7559 new_crtc->base.id);
7560 }
7561
7562 /* Check for any encoders that needs to be disabled. */
7563 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7564 base.head) {
7565 list_for_each_entry(connector,
7566 &dev->mode_config.connector_list,
7567 base.head) {
7568 if (connector->new_encoder == encoder) {
7569 WARN_ON(!connector->new_encoder->new_crtc);
7570
7571 goto next_encoder;
7572 }
7573 }
7574 encoder->new_crtc = NULL;
7575next_encoder:
7576 /* Only now check for crtc changes so we don't miss encoders
7577 * that will be disabled. */
7578 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7579 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7580 config->mode_changed = true;
50f56119
DV		 7581 }
7582 }
9a935856 7583 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7584
2e431051
DV		 7585 return 0;
7586}
7587
7588static int intel_crtc_set_config(struct drm_mode_set *set)
7589{
7590 struct drm_device *dev;
2e431051
DV		 7591 struct drm_mode_set save_set;
7592 struct intel_set_config *config;
7593 int ret;
2e431051 7594
8d3e375e
DV		 7595 BUG_ON(!set);
7596 BUG_ON(!set->crtc);
7597 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7598
7599 if (!set->mode)
7600 set->fb = NULL;
7601
431e50f7
DV		 7602 /* The fb helper likes to play gross jokes with ->mode_set_config.
7603 * Unfortunately the crtc helper doesn't do much at all for this case,
7604 * so we have to cope with this madness until the fb helper is fixed up. */
7605 if (set->fb && set->num_connectors == 0)
7606 return 0;
7607
2e431051
DV		 7608 if (set->fb) {
7609 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7610 set->crtc->base.id, set->fb->base.id,
7611 (int)set->num_connectors, set->x, set->y);
7612 } else {
7613 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7614 }
7615
7616 dev = set->crtc->dev;
7617
7618 ret = -ENOMEM;
7619 config = kzalloc(sizeof(*config), GFP_KERNEL);
7620 if (!config)
7621 goto out_config;
7622
7623 ret = intel_set_config_save_state(dev, config);
7624 if (ret)
7625 goto out_config;
7626
7627 save_set.crtc = set->crtc;
7628 save_set.mode = &set->crtc->mode;
7629 save_set.x = set->crtc->x;
7630 save_set.y = set->crtc->y;
7631 save_set.fb = set->crtc->fb;
7632
7633 /* Compute whether we need a full modeset, only an fb base update or no
7634 * change at all. In the future we might also check whether only the
7635 * mode changed, e.g. for LVDS where we only change the panel fitter in
7636 * such cases. */
7637 intel_set_config_compute_mode_changes(set, config);
7638
9a935856 7639 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7640 if (ret)
7641 goto fail;
7642
5e2b584e 7643 if (config->mode_changed) {
87f1faa6 7644 if (set->mode) {
50f56119
DV		 7645 DRM_DEBUG_KMS("attempting to set mode from"
7646 " userspace\n");
7647 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7648 }
7649
7650 if (!intel_set_mode(set->crtc, set->mode,
7651 set->x, set->y, set->fb)) {
7652 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7653 set->crtc->base.id);
7654 ret = -EINVAL;
7655 goto fail;
7656 }
5e2b584e 7657 } else if (config->fb_changed) {
4f660f49 7658 ret = intel_pipe_set_base(set->crtc,
94352cf9 7659 set->x, set->y, set->fb);
50f56119
DV		 7660 }
7661
d9e55608
DV		 7662 intel_set_config_free(config);
7663
50f56119
DV		 7664 return 0;
7665
7666fail:
85f9eb71 7667 intel_set_config_restore_state(dev, config);
50f56119
DV		 7668
7669 /* Try to restore the config */
5e2b584e 7670 if (config->mode_changed &&
a6778b3c
DV		 7671 !intel_set_mode(save_set.crtc, save_set.mode,
7672 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7673 DRM_ERROR("failed to restore config after modeset failure\n");
7674
d9e55608
DV		 7675out_config:
7676 intel_set_config_free(config);
50f56119
DV		 7677 return ret;
7678}
7679
f6e5b160 7680static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7681 .cursor_set = intel_crtc_cursor_set,
7682 .cursor_move = intel_crtc_cursor_move,
7683 .gamma_set = intel_crtc_gamma_set,
50f56119 7684 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7685 .destroy = intel_crtc_destroy,
7686 .page_flip = intel_crtc_page_flip,
7687};
7688
79f689aa
PZ		 7689static void intel_cpu_pll_init(struct drm_device *dev)
7690{
7691 if (IS_HASWELL(dev))
7692 intel_ddi_pll_init(dev);
7693}
7694
ee7b9f93
JB		 7695static void intel_pch_pll_init(struct drm_device *dev)
7696{
7697 drm_i915_private_t *dev_priv = dev->dev_private;
7698 int i;
7699
7700 if (dev_priv->num_pch_pll == 0) {
7701 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7702 return;
7703 }
7704
7705 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7706 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7707 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7708 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7709 }
7710}
7711
b358d0a6 7712static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7713{
22fd0fab 7714 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7715 struct intel_crtc *intel_crtc;
7716 int i;
7717
7718 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7719 if (intel_crtc == NULL)
7720 return;
7721
7722 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7723
7724 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7725 for (i = 0; i < 256; i++) {
7726 intel_crtc->lut_r[i] = i;
7727 intel_crtc->lut_g[i] = i;
7728 intel_crtc->lut_b[i] = i;
7729 }
7730
80824003
JB		 7731 /* Swap pipes & planes for FBC on pre-965 */
7732 intel_crtc->pipe = pipe;
7733 intel_crtc->plane = pipe;
e2e767ab 7734 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7735 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7736 intel_crtc->plane = !pipe;
80824003
JB		 7737 }
7738
22fd0fab
JB		 7739 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7740 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7741 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7742 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7743
5a354204 7744 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7745
79e53945 7746 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7747}
7748
08d7b3d1 7749int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7750 struct drm_file *file)
08d7b3d1 7751{
08d7b3d1 7752 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7753 struct drm_mode_object *drmmode_obj;
7754 struct intel_crtc *crtc;
08d7b3d1 7755
1cff8f6b
DV		 7756 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7757 return -ENODEV;
08d7b3d1 7758
c05422d5
DV		 7759 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7760 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7761
c05422d5 7762 if (!drmmode_obj) {
08d7b3d1
CW		 7763 DRM_ERROR("no such CRTC id\n");
7764 return -EINVAL;
7765 }
7766
c05422d5
DV		 7767 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7768 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7769
c05422d5 7770 return 0;
08d7b3d1
CW		 7771}
7772
66a9278e 7773static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7774{
66a9278e
DV		 7775 struct drm_device *dev = encoder->base.dev;
7776 struct intel_encoder *source_encoder;
79e53945 7777 int index_mask = 0;
79e53945
JB		 7778 int entry = 0;
7779
66a9278e
DV		 7780 list_for_each_entry(source_encoder,
7781 &dev->mode_config.encoder_list, base.head) {
7782
7783 if (encoder == source_encoder)
79e53945 7784 index_mask |= (1 << entry);
66a9278e
DV		 7785
7786 /* Intel hw has only one MUX where enocoders could be cloned. */
7787 if (encoder->cloneable && source_encoder->cloneable)
7788 index_mask |= (1 << entry);
7789
79e53945
JB		 7790 entry++;
7791 }
4ef69c7a 7792
79e53945
JB		 7793 return index_mask;
7794}
7795
4d302442
CW		 7796static bool has_edp_a(struct drm_device *dev)
7797{
7798 struct drm_i915_private *dev_priv = dev->dev_private;
7799
7800 if (!IS_MOBILE(dev))
7801 return false;
7802
7803 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7804 return false;
7805
7806 if (IS_GEN5(dev) &&
7807 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7808 return false;
7809
7810 return true;
7811}
7812
79e53945
JB		 7813static void intel_setup_outputs(struct drm_device *dev)
7814{
725e30ad 7815 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7816 struct intel_encoder *encoder;
cb0953d7 7817 bool dpd_is_edp = false;
f3cfcba6 7818 bool has_lvds;
79e53945 7819
f3cfcba6 7820 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7821 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7822 /* disable the panel fitter on everything but LVDS */
7823 I915_WRITE(PFIT_CONTROL, 0);
7824 }
79e53945 7825
bad720ff 7826 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7827 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7828
4d302442 7829 if (has_edp_a(dev))
ab9d7c30 7830 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7831
cb0953d7 7832 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7833 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7834 }
7835
7836 intel_crt_init(dev);
7837
0e72a5b5
ED		 7838 if (IS_HASWELL(dev)) {
7839 int found;
7840
7841 /* Haswell uses DDI functions to detect digital outputs */
7842 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7843 /* DDI A only supports eDP */
7844 if (found)
7845 intel_ddi_init(dev, PORT_A);
7846
7847 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7848 * register */
7849 found = I915_READ(SFUSE_STRAP);
7850
7851 if (found & SFUSE_STRAP_DDIB_DETECTED)
7852 intel_ddi_init(dev, PORT_B);
7853 if (found & SFUSE_STRAP_DDIC_DETECTED)
7854 intel_ddi_init(dev, PORT_C);
7855 if (found & SFUSE_STRAP_DDID_DETECTED)
7856 intel_ddi_init(dev, PORT_D);
7857 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7858 int found;
7859
30ad48b7 7860 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7861 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7862 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7863 if (!found)
08d644ad 7864 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7865 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7866 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7867 }
7868
7869 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7870 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7871
b708a1d5 7872 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7873 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7874
5eb08b69 7875 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7876 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7877
cb0953d7 7878 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7879 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7880 } else if (IS_VALLEYVIEW(dev)) {
7881 int found;
7882
19c03924
GB		 7883 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7884 if (I915_READ(DP_C) & DP_DETECTED)
7885 intel_dp_init(dev, DP_C, PORT_C);
7886
4a87d65d
JB		 7887 if (I915_READ(SDVOB) & PORT_DETECTED) {
7888 /* SDVOB multiplex with HDMIB */
7889 found = intel_sdvo_init(dev, SDVOB, true);
7890 if (!found)
08d644ad 7891 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7892 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7893 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7894 }
7895
7896 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7897 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7898
103a196f 7899 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7900 bool found = false;
7d57382e 7901
725e30ad 7902 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7903 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7904 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7905 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7906 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7907 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7908 }
27185ae1 7909
b01f2c3a
JB		 7910 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7911 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7912 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7913 }
725e30ad 7914 }
13520b05
KH		 7915
7916 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7917
b01f2c3a
JB		 7918 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7919 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7920 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7921 }
27185ae1
ML		 7922
7923 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7924
b01f2c3a
JB		 7925 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7926 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7927 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7928 }
7929 if (SUPPORTS_INTEGRATED_DP(dev)) {
7930 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7931 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7932 }
725e30ad 7933 }
27185ae1 7934
b01f2c3a
JB		 7935 if (SUPPORTS_INTEGRATED_DP(dev) &&
7936 (I915_READ(DP_D) & DP_DETECTED)) {
7937 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7938 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7939 }
bad720ff 7940 } else if (IS_GEN2(dev))
79e53945
JB		 7941 intel_dvo_init(dev);
7942
103a196f 7943 if (SUPPORTS_TV(dev))
79e53945
JB		 7944 intel_tv_init(dev);
7945
4ef69c7a
CW		 7946 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7947 encoder->base.possible_crtcs = encoder->crtc_mask;
7948 encoder->base.possible_clones =
66a9278e 7949 intel_encoder_clones(encoder);
79e53945 7950 }
47356eb6 7951
40579abe 7952 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7953 ironlake_init_pch_refclk(dev);
79e53945
JB		 7954}
7955
7956static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7957{
7958 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7959
7960 drm_framebuffer_cleanup(fb);
05394f39 7961 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7962
7963 kfree(intel_fb);
7964}
7965
7966static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7967 struct drm_file *file,
79e53945
JB		 7968 unsigned int *handle)
7969{
7970 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7971 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7972
05394f39 7973 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7974}
7975
7976static const struct drm_framebuffer_funcs intel_fb_funcs = {
7977 .destroy = intel_user_framebuffer_destroy,
7978 .create_handle = intel_user_framebuffer_create_handle,
7979};
7980
38651674
DA		 7981int intel_framebuffer_init(struct drm_device *dev,
7982 struct intel_framebuffer *intel_fb,
308e5bcb 7983 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7984 struct drm_i915_gem_object *obj)
79e53945 7985{
79e53945
JB		 7986 int ret;
7987
05394f39 7988 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7989 return -EINVAL;
7990
308e5bcb 7991 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7992 return -EINVAL;
7993
308e5bcb 7994 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7995 case DRM_FORMAT_RGB332:
7996 case DRM_FORMAT_RGB565:
7997 case DRM_FORMAT_XRGB8888:
b250da79 7998 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7999 case DRM_FORMAT_ARGB8888:
8000 case DRM_FORMAT_XRGB2101010:
8001 case DRM_FORMAT_ARGB2101010:
308e5bcb 8002 /* RGB formats are common across chipsets */
b5626747 8003 break;
04b3924d
VS		 8004 case DRM_FORMAT_YUYV:
8005 case DRM_FORMAT_UYVY:
8006 case DRM_FORMAT_YVYU:
8007 case DRM_FORMAT_VYUY:
57cd6508
CW		 8008 break;
8009 default:
aca25848
ED		 8010 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8011 mode_cmd->pixel_format);
57cd6508
CW		 8012 return -EINVAL;
8013 }
8014
79e53945
JB		 8015 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8016 if (ret) {
8017 DRM_ERROR("framebuffer init failed %d\n", ret);
8018 return ret;
8019 }
8020
8021 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8022 intel_fb->obj = obj;
79e53945
JB		 8023 return 0;
8024}
8025
79e53945
JB		 8026static struct drm_framebuffer *
8027intel_user_framebuffer_create(struct drm_device *dev,
8028 struct drm_file *filp,
308e5bcb 8029 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8030{
05394f39 8031 struct drm_i915_gem_object *obj;
79e53945 8032
308e5bcb
JB		 8033 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8034 mode_cmd->handles[0]));
c8725226 8035 if (&obj->base == NULL)
cce13ff7 8036 return ERR_PTR(-ENOENT);
79e53945 8037
d2dff872 8038 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8039}
8040
79e53945 8041static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8042 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8043 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8044};
8045
e70236a8
JB		 8046/* Set up chip specific display functions */
8047static void intel_init_display(struct drm_device *dev)
8048{
8049 struct drm_i915_private *dev_priv = dev->dev_private;
8050
8051 /* We always want a DPMS function */
09b4ddf9
PZ		 8052 if (IS_HASWELL(dev)) {
8053 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8054 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8055 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8056 dev_priv->display.off = ironlake_crtc_off;
8057 dev_priv->display.update_plane = ironlake_update_plane;
8058 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8059 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8060 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8061 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8062 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8063 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8064 } else {
f564048e 8065 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8066 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8067 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8068 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8069 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8070 }
e70236a8 8071
e70236a8 8072 /* Returns the core display clock speed */
25eb05fc
JB		 8073 if (IS_VALLEYVIEW(dev))
8074 dev_priv->display.get_display_clock_speed =
8075 valleyview_get_display_clock_speed;
8076 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8077 dev_priv->display.get_display_clock_speed =
8078 i945_get_display_clock_speed;
8079 else if (IS_I915G(dev))
8080 dev_priv->display.get_display_clock_speed =
8081 i915_get_display_clock_speed;
f2b115e6 8082 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8083 dev_priv->display.get_display_clock_speed =
8084 i9xx_misc_get_display_clock_speed;
8085 else if (IS_I915GM(dev))
8086 dev_priv->display.get_display_clock_speed =
8087 i915gm_get_display_clock_speed;
8088 else if (IS_I865G(dev))
8089 dev_priv->display.get_display_clock_speed =
8090 i865_get_display_clock_speed;
f0f8a9ce 8091 else if (IS_I85X(dev))
e70236a8
JB		 8092 dev_priv->display.get_display_clock_speed =
8093 i855_get_display_clock_speed;
8094 else /* 852, 830 */
8095 dev_priv->display.get_display_clock_speed =
8096 i830_get_display_clock_speed;
8097
7f8a8569 8098 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8099 if (IS_GEN5(dev)) {
674cf967 8100 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8101 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8102 } else if (IS_GEN6(dev)) {
674cf967 8103 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8104 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8105 } else if (IS_IVYBRIDGE(dev)) {
8106 /* FIXME: detect B0+ stepping and use auto training */
8107 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8108 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 8109 } else if (IS_HASWELL(dev)) {
8110 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8111 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8112 } else
8113 dev_priv->display.update_wm = NULL;
6067aaea 8114 } else if (IS_G4X(dev)) {
e0dac65e 8115 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8116 }
8c9f3aaf
JB		 8117
8118 /* Default just returns -ENODEV to indicate unsupported */
8119 dev_priv->display.queue_flip = intel_default_queue_flip;
8120
8121 switch (INTEL_INFO(dev)->gen) {
8122 case 2:
8123 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8124 break;
8125
8126 case 3:
8127 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8128 break;
8129
8130 case 4:
8131 case 5:
8132 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8133 break;
8134
8135 case 6:
8136 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8137 break;
7c9017e5
JB		 8138 case 7:
8139 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8140 break;
8c9f3aaf 8141 }
e70236a8
JB		 8142}
8143
b690e96c
JB		 8144/*
8145 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8146 * resume, or other times. This quirk makes sure that's the case for
8147 * affected systems.
8148 */
0206e353 8149static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8150{
8151 struct drm_i915_private *dev_priv = dev->dev_private;
8152
8153 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8154 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8155}
8156
435793df
KP		 8157/*
8158 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8159 */
8160static void quirk_ssc_force_disable(struct drm_device *dev)
8161{
8162 struct drm_i915_private *dev_priv = dev->dev_private;
8163 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8164 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8165}
8166
4dca20ef 8167/*
5a15ab5b
CE		 8168 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8169 * brightness value
4dca20ef
CE		 8170 */
8171static void quirk_invert_brightness(struct drm_device *dev)
8172{
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8175 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8176}
8177
b690e96c
JB		 8178struct intel_quirk {
8179 int device;
8180 int subsystem_vendor;
8181 int subsystem_device;
8182 void (*hook)(struct drm_device *dev);
8183};
8184
c43b5634 8185static struct intel_quirk intel_quirks[] = {
b690e96c 8186 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8187 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8188
b690e96c
JB		 8189 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8190 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8191
b690e96c
JB		 8192 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8193 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8194
8195 /* 855 & before need to leave pipe A & dpll A up */
8196 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8197 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8198 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8199
8200 /* Lenovo U160 cannot use SSC on LVDS */
8201 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8202
8203 /* Sony Vaio Y cannot use SSC on LVDS */
8204 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8205
8206 /* Acer Aspire 5734Z must invert backlight brightness */
8207 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8208};
8209
8210static void intel_init_quirks(struct drm_device *dev)
8211{
8212 struct pci_dev *d = dev->pdev;
8213 int i;
8214
8215 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8216 struct intel_quirk *q = &intel_quirks[i];
8217
8218 if (d->device == q->device &&
8219 (d->subsystem_vendor == q->subsystem_vendor ||
8220 q->subsystem_vendor == PCI_ANY_ID) &&
8221 (d->subsystem_device == q->subsystem_device ||
8222 q->subsystem_device == PCI_ANY_ID))
8223 q->hook(dev);
8224 }
8225}
8226
9cce37f4
JB		 8227/* Disable the VGA plane that we never use */
8228static void i915_disable_vga(struct drm_device *dev)
8229{
8230 struct drm_i915_private *dev_priv = dev->dev_private;
8231 u8 sr1;
8232 u32 vga_reg;
8233
8234 if (HAS_PCH_SPLIT(dev))
8235 vga_reg = CPU_VGACNTRL;
8236 else
8237 vga_reg = VGACNTRL;
8238
8239 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8240 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8241 sr1 = inb(VGA_SR_DATA);
8242 outb(sr1 | 1<<5, VGA_SR_DATA);
8243 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8244 udelay(300);
8245
8246 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8247 POSTING_READ(vga_reg);
8248}
8249
f817586c
DV		 8250void intel_modeset_init_hw(struct drm_device *dev)
8251{
0232e927
ED		 8252 /* We attempt to init the necessary power wells early in the initialization
8253 * time, so the subsystems that expect power to be enabled can work.
8254 */
8255 intel_init_power_wells(dev);
8256
a8f78b58
ED		 8257 intel_prepare_ddi(dev);
8258
f817586c
DV		 8259 intel_init_clock_gating(dev);
8260
79f5b2c7 8261 mutex_lock(&dev->struct_mutex);
8090c6b9 8262 intel_enable_gt_powersave(dev);
79f5b2c7 8263 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8264}
8265
79e53945
JB		 8266void intel_modeset_init(struct drm_device *dev)
8267{
652c393a 8268 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8269 int i, ret;
79e53945
JB		 8270
8271 drm_mode_config_init(dev);
8272
8273 dev->mode_config.min_width = 0;
8274 dev->mode_config.min_height = 0;
8275
019d96cb
DA		 8276 dev->mode_config.preferred_depth = 24;
8277 dev->mode_config.prefer_shadow = 1;
8278
e6ecefaa 8279 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8280
b690e96c
JB		 8281 intel_init_quirks(dev);
8282
1fa61106
ED		 8283 intel_init_pm(dev);
8284
e70236a8
JB		 8285 intel_init_display(dev);
8286
a6c45cf0
CW		 8287 if (IS_GEN2(dev)) {
8288 dev->mode_config.max_width = 2048;
8289 dev->mode_config.max_height = 2048;
8290 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8291 dev->mode_config.max_width = 4096;
8292 dev->mode_config.max_height = 4096;
79e53945 8293 } else {
a6c45cf0
CW		 8294 dev->mode_config.max_width = 8192;
8295 dev->mode_config.max_height = 8192;
79e53945 8296 }
dd2757f8 8297 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8298
28c97730 8299 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8300 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8301
a3524f1b 8302 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8303 intel_crtc_init(dev, i);
00c2064b
JB		 8304 ret = intel_plane_init(dev, i);
8305 if (ret)
8306 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8307 }
8308
79f689aa 8309 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8310 intel_pch_pll_init(dev);
8311
9cce37f4
JB		 8312 /* Just disable it once at startup */
8313 i915_disable_vga(dev);
79e53945 8314 intel_setup_outputs(dev);
2c7111db
CW		 8315}
8316
24929352
DV		 8317static void
8318intel_connector_break_all_links(struct intel_connector *connector)
8319{
8320 connector->base.dpms = DRM_MODE_DPMS_OFF;
8321 connector->base.encoder = NULL;
8322 connector->encoder->connectors_active = false;
8323 connector->encoder->base.crtc = NULL;
8324}
8325
7fad798e
DV		 8326static void intel_enable_pipe_a(struct drm_device *dev)
8327{
8328 struct intel_connector *connector;
8329 struct drm_connector *crt = NULL;
8330 struct intel_load_detect_pipe load_detect_temp;
8331
8332 /* We can't just switch on the pipe A, we need to set things up with a
8333 * proper mode and output configuration. As a gross hack, enable pipe A
8334 * by enabling the load detect pipe once. */
8335 list_for_each_entry(connector,
8336 &dev->mode_config.connector_list,
8337 base.head) {
8338 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8339 crt = &connector->base;
8340 break;
8341 }
8342 }
8343
8344 if (!crt)
8345 return;
8346
8347 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8348 intel_release_load_detect_pipe(crt, &load_detect_temp);
8349
8350
8351}
8352
24929352
DV		 8353static void intel_sanitize_crtc(struct intel_crtc *crtc)
8354{
8355 struct drm_device *dev = crtc->base.dev;
8356 struct drm_i915_private *dev_priv = dev->dev_private;
8357 u32 reg, val;
8358
24929352
DV		 8359 /* Clear any frame start delays used for debugging left by the BIOS */
8360 reg = PIPECONF(crtc->pipe);
8361 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8362
8363 /* We need to sanitize the plane -> pipe mapping first because this will
8364 * disable the crtc (and hence change the state) if it is wrong. */
8365 if (!HAS_PCH_SPLIT(dev)) {
8366 struct intel_connector *connector;
8367 bool plane;
8368
8369 reg = DSPCNTR(crtc->plane);
8370 val = I915_READ(reg);
8371
8372 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8373 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8374 goto ok;
8375
8376 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8377 crtc->base.base.id);
8378
8379 /* Pipe has the wrong plane attached and the plane is active.
8380 * Temporarily change the plane mapping and disable everything
8381 * ... */
8382 plane = crtc->plane;
8383 crtc->plane = !plane;
8384 dev_priv->display.crtc_disable(&crtc->base);
8385 crtc->plane = plane;
8386
8387 /* ... and break all links. */
8388 list_for_each_entry(connector, &dev->mode_config.connector_list,
8389 base.head) {
8390 if (connector->encoder->base.crtc != &crtc->base)
8391 continue;
8392
8393 intel_connector_break_all_links(connector);
8394 }
8395
8396 WARN_ON(crtc->active);
8397 crtc->base.enabled = false;
8398 }
8399ok:
8400
7fad798e
DV		 8401 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8402 crtc->pipe == PIPE_A && !crtc->active) {
8403 /* BIOS forgot to enable pipe A, this mostly happens after
8404 * resume. Force-enable the pipe to fix this, the update_dpms
8405 * call below we restore the pipe to the right state, but leave
8406 * the required bits on. */
8407 intel_enable_pipe_a(dev);
8408 }
8409
24929352
DV		 8410 /* Adjust the state of the output pipe according to whether we
8411 * have active connectors/encoders. */
8412 intel_crtc_update_dpms(&crtc->base);
8413
8414 if (crtc->active != crtc->base.enabled) {
8415 struct intel_encoder *encoder;
8416
8417 /* This can happen either due to bugs in the get_hw_state
8418 * functions or because the pipe is force-enabled due to the
8419 * pipe A quirk. */
8420 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8421 crtc->base.base.id,
8422 crtc->base.enabled ? "enabled" : "disabled",
8423 crtc->active ? "enabled" : "disabled");
8424
8425 crtc->base.enabled = crtc->active;
8426
8427 /* Because we only establish the connector -> encoder ->
8428 * crtc links if something is active, this means the
8429 * crtc is now deactivated. Break the links. connector
8430 * -> encoder links are only establish when things are
8431 * actually up, hence no need to break them. */
8432 WARN_ON(crtc->active);
8433
8434 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8435 WARN_ON(encoder->connectors_active);
8436 encoder->base.crtc = NULL;
8437 }
8438 }
8439}
8440
8441static void intel_sanitize_encoder(struct intel_encoder *encoder)
8442{
8443 struct intel_connector *connector;
8444 struct drm_device *dev = encoder->base.dev;
8445
8446 /* We need to check both for a crtc link (meaning that the
8447 * encoder is active and trying to read from a pipe) and the
8448 * pipe itself being active. */
8449 bool has_active_crtc = encoder->base.crtc &&
8450 to_intel_crtc(encoder->base.crtc)->active;
8451
8452 if (encoder->connectors_active && !has_active_crtc) {
8453 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8454 encoder->base.base.id,
8455 drm_get_encoder_name(&encoder->base));
8456
8457 /* Connector is active, but has no active pipe. This is
8458 * fallout from our resume register restoring. Disable
8459 * the encoder manually again. */
8460 if (encoder->base.crtc) {
8461 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8462 encoder->base.base.id,
8463 drm_get_encoder_name(&encoder->base));
8464 encoder->disable(encoder);
8465 }
8466
8467 /* Inconsistent output/port/pipe state happens presumably due to
8468 * a bug in one of the get_hw_state functions. Or someplace else
8469 * in our code, like the register restore mess on resume. Clamp
8470 * things to off as a safer default. */
8471 list_for_each_entry(connector,
8472 &dev->mode_config.connector_list,
8473 base.head) {
8474 if (connector->encoder != encoder)
8475 continue;
8476
8477 intel_connector_break_all_links(connector);
8478 }
8479 }
8480 /* Enabled encoders without active connectors will be fixed in
8481 * the crtc fixup. */
8482}
8483
8484/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8485 * and i915 state tracking structures. */
8486void intel_modeset_setup_hw_state(struct drm_device *dev)
8487{
8488 struct drm_i915_private *dev_priv = dev->dev_private;
8489 enum pipe pipe;
8490 u32 tmp;
8491 struct intel_crtc *crtc;
8492 struct intel_encoder *encoder;
8493 struct intel_connector *connector;
8494
8495 for_each_pipe(pipe) {
8496 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8497
8498 tmp = I915_READ(PIPECONF(pipe));
8499 if (tmp & PIPECONF_ENABLE)
8500 crtc->active = true;
8501 else
8502 crtc->active = false;
8503
8504 crtc->base.enabled = crtc->active;
8505
8506 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8507 crtc->base.base.id,
8508 crtc->active ? "enabled" : "disabled");
8509 }
8510
8511 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8512 base.head) {
8513 pipe = 0;
8514
8515 if (encoder->get_hw_state(encoder, &pipe)) {
8516 encoder->base.crtc =
8517 dev_priv->pipe_to_crtc_mapping[pipe];
8518 } else {
8519 encoder->base.crtc = NULL;
8520 }
8521
8522 encoder->connectors_active = false;
8523 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8524 encoder->base.base.id,
8525 drm_get_encoder_name(&encoder->base),
8526 encoder->base.crtc ? "enabled" : "disabled",
8527 pipe);
8528 }
8529
8530 list_for_each_entry(connector, &dev->mode_config.connector_list,
8531 base.head) {
8532 if (connector->get_hw_state(connector)) {
8533 connector->base.dpms = DRM_MODE_DPMS_ON;
8534 connector->encoder->connectors_active = true;
8535 connector->base.encoder = &connector->encoder->base;
8536 } else {
8537 connector->base.dpms = DRM_MODE_DPMS_OFF;
8538 connector->base.encoder = NULL;
8539 }
8540 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8541 connector->base.base.id,
8542 drm_get_connector_name(&connector->base),
8543 connector->base.encoder ? "enabled" : "disabled");
8544 }
8545
8546 /* HW state is read out, now we need to sanitize this mess. */
8547 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8548 base.head) {
8549 intel_sanitize_encoder(encoder);
8550 }
8551
8552 for_each_pipe(pipe) {
8553 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8554 intel_sanitize_crtc(crtc);
8555 }
9a935856
DV		 8556
8557 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8558
8559 intel_modeset_check_state(dev);
24929352
DV		 8560}
8561
2c7111db
CW		 8562void intel_modeset_gem_init(struct drm_device *dev)
8563{
1833b134 8564 intel_modeset_init_hw(dev);
02e792fb
DV		 8565
8566 intel_setup_overlay(dev);
24929352
DV		 8567
8568 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8569}
8570
8571void intel_modeset_cleanup(struct drm_device *dev)
8572{
652c393a
JB		 8573 struct drm_i915_private *dev_priv = dev->dev_private;
8574 struct drm_crtc *crtc;
8575 struct intel_crtc *intel_crtc;
8576
f87ea761 8577 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8578 mutex_lock(&dev->struct_mutex);
8579
723bfd70
JB		 8580 intel_unregister_dsm_handler();
8581
8582
652c393a
JB		 8583 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8584 /* Skip inactive CRTCs */
8585 if (!crtc->fb)
8586 continue;
8587
8588 intel_crtc = to_intel_crtc(crtc);
3dec0095 8589 intel_increase_pllclock(crtc);
652c393a
JB		 8590 }
8591
973d04f9 8592 intel_disable_fbc(dev);
e70236a8 8593
8090c6b9 8594 intel_disable_gt_powersave(dev);
0cdab21f 8595
930ebb46
DV		 8596 ironlake_teardown_rc6(dev);
8597
57f350b6
JB		 8598 if (IS_VALLEYVIEW(dev))
8599 vlv_init_dpio(dev);
8600
69341a5e
KH		 8601 mutex_unlock(&dev->struct_mutex);
8602
6c0d9350
DV		 8603 /* Disable the irq before mode object teardown, for the irq might
8604 * enqueue unpin/hotplug work. */
8605 drm_irq_uninstall(dev);
8606 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8607 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8608
1630fe75
CW		 8609 /* flush any delayed tasks or pending work */
8610 flush_scheduled_work();
8611
79e53945
JB		 8612 drm_mode_config_cleanup(dev);
8613}
8614
f1c79df3
ZW		 8615/*
8616 * Return which encoder is currently attached for connector.
8617 */
df0e9248 8618struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8619{
df0e9248
CW		 8620 return &intel_attached_encoder(connector)->base;
8621}
f1c79df3 8622
df0e9248
CW		 8623void intel_connector_attach_encoder(struct intel_connector *connector,
8624 struct intel_encoder *encoder)
8625{
8626 connector->encoder = encoder;
8627 drm_mode_connector_attach_encoder(&connector->base,
8628 &encoder->base);
79e53945 8629}
28d52043
DA		 8630
8631/*
8632 * set vga decode state - true == enable VGA decode
8633 */
8634int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8635{
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 u16 gmch_ctrl;
8638
8639 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8640 if (state)
8641 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8642 else
8643 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8644 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8645 return 0;
8646}
c4a1d9e4
CW		 8647
8648#ifdef CONFIG_DEBUG_FS
8649#include <linux/seq_file.h>
8650
8651struct intel_display_error_state {
8652 struct intel_cursor_error_state {
8653 u32 control;
8654 u32 position;
8655 u32 base;
8656 u32 size;
52331309 8657 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8658
8659 struct intel_pipe_error_state {
8660 u32 conf;
8661 u32 source;
8662
8663 u32 htotal;
8664 u32 hblank;
8665 u32 hsync;
8666 u32 vtotal;
8667 u32 vblank;
8668 u32 vsync;
52331309 8669 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8670
8671 struct intel_plane_error_state {
8672 u32 control;
8673 u32 stride;
8674 u32 size;
8675 u32 pos;
8676 u32 addr;
8677 u32 surface;
8678 u32 tile_offset;
52331309 8679 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8680};
8681
8682struct intel_display_error_state *
8683intel_display_capture_error_state(struct drm_device *dev)
8684{
0206e353 8685 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8686 struct intel_display_error_state *error;
8687 int i;
8688
8689 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8690 if (error == NULL)
8691 return NULL;
8692
52331309 8693 for_each_pipe(i) {
c4a1d9e4
CW		 8694 error->cursor[i].control = I915_READ(CURCNTR(i));
8695 error->cursor[i].position = I915_READ(CURPOS(i));
8696 error->cursor[i].base = I915_READ(CURBASE(i));
8697
8698 error->plane[i].control = I915_READ(DSPCNTR(i));
8699 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8700 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8701 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8702 error->plane[i].addr = I915_READ(DSPADDR(i));
8703 if (INTEL_INFO(dev)->gen >= 4) {
8704 error->plane[i].surface = I915_READ(DSPSURF(i));
8705 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8706 }
8707
8708 error->pipe[i].conf = I915_READ(PIPECONF(i));
8709 error->pipe[i].source = I915_READ(PIPESRC(i));
8710 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8711 error->pipe[i].hblank = I915_READ(HBLANK(i));
8712 error->pipe[i].hsync = I915_READ(HSYNC(i));
8713 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8714 error->pipe[i].vblank = I915_READ(VBLANK(i));
8715 error->pipe[i].vsync = I915_READ(VSYNC(i));
8716 }
8717
8718 return error;
8719}
8720
8721void
8722intel_display_print_error_state(struct seq_file *m,
8723 struct drm_device *dev,
8724 struct intel_display_error_state *error)
8725{
52331309 8726 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8727 int i;
8728
52331309
DL		 8729 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8730 for_each_pipe(i) {
c4a1d9e4
CW		 8731 seq_printf(m, "Pipe [%d]:\n", i);
8732 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8733 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8734 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8735 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8736 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8737 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8738 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8739 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8740
8741 seq_printf(m, "Plane [%d]:\n", i);
8742 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8743 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8744 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8745 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8746 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8747 if (INTEL_INFO(dev)->gen >= 4) {
8748 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8749 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8750 }
8751
8752 seq_printf(m, "Cursor [%d]:\n", i);
8753 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8754 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8755 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8756 }
8757}
8758#endif
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