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drm/i915: hw state readout and cross-checking for shared dplls
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
e2b78267
DV		 912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
a43f6e0f 917 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 918 return NULL;
919
a43f6e0f 920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 921}
922
040484af 923/* For ILK+ */
e72f9fbf
DV		 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
e72f9fbf 926 bool state)
040484af 927{
040484af 928 bool cur_state;
5358901f 929 struct intel_dpll_hw_state hw_state;
040484af 930
9d82aa17
ED		 931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
933 return;
934 }
935
92b27b08 936 if (WARN (!pll,
46edb027 937 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 938 return;
ee7b9f93 939
5358901f 940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 941 WARN(cur_state != state,
5358901f
DV		 942 "%s assertion failure (expected %s, current %s)\n",
943 pll->name, state_string(state), state_string(cur_state));
040484af 944}
e9d6944e
DV		 945#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
946#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
040484af
JB		 947
948static void assert_fdi_tx(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state)
950{
951 int reg;
952 u32 val;
953 bool cur_state;
ad80a810
PZ		 954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
955 pipe);
040484af 956
affa9354
PZ		 957 if (HAS_DDI(dev_priv->dev)) {
958 /* DDI does not have a specific FDI_TX register */
ad80a810 959 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 960 val = I915_READ(reg);
ad80a810 961 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 962 } else {
963 reg = FDI_TX_CTL(pipe);
964 val = I915_READ(reg);
965 cur_state = !!(val & FDI_TX_ENABLE);
966 }
040484af
JB		 967 WARN(cur_state != state,
968 "FDI TX state assertion failure (expected %s, current %s)\n",
969 state_string(state), state_string(cur_state));
970}
971#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
972#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
973
974static void assert_fdi_rx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
976{
977 int reg;
978 u32 val;
979 bool cur_state;
980
d63fa0dc
PZ		 981 reg = FDI_RX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 984 WARN(cur_state != state,
985 "FDI RX state assertion failure (expected %s, current %s)\n",
986 state_string(state), state_string(cur_state));
987}
988#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
989#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
990
991static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993{
994 int reg;
995 u32 val;
996
997 /* ILK FDI PLL is always enabled */
998 if (dev_priv->info->gen == 5)
999 return;
1000
bf507ef7 1001 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1002 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1003 return;
1004
040484af
JB		 1005 reg = FDI_TX_CTL(pipe);
1006 val = I915_READ(reg);
1007 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008}
1009
1010static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012{
1013 int reg;
1014 u32 val;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019}
1020
ea0760cf
JB		 1021static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023{
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
0de3b485 1027 bool locked = true;
ea0760cf
JB		 1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1047 pipe_name(pipe));
ea0760cf
JB		 1048}
1049
b840d907
JB		 1050void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
b24e7179
JB		 1052{
1053 int reg;
1054 u32 val;
63d7bbe9 1055 bool cur_state;
702e7a56
PZ		 1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
b24e7179 1058
8e636784
DV		 1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
b97186f0
PZ		 1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
63d7bbe9
JB		 1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
653e1026 1098 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
653e1026
VS		 1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
19ec1358 1110 return;
28c05794 1111 }
19ec1358 1112
b24e7179 1113 /* Need to check both planes against the pipe */
653e1026 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1122 }
1123}
1124
19332d7a
JB		 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
20674eef 1128 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1129 int reg, i;
1130 u32 val;
1131
20674eef
VS		 1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
1142 val = I915_READ(reg);
1143 WARN((val & SPRITE_ENABLE),
1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
19332d7a 1148 val = I915_READ(reg);
20674eef 1149 WARN((val & DVS_ENABLE),
06da8da2 1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1151 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1152 }
1153}
1154
92f2584a
JB		 1155static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156{
1157 u32 val;
1158 bool enabled;
1159
9d82aa17
ED		 1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
92f2584a
JB		 1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169}
1170
ab9412ba
DV		 1171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
92f2584a
JB		 1173{
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
ab9412ba 1178 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
92f2584a
JB		 1184}
1185
4e634389
KP		 1186static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1188{
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202}
1203
1519b995
KP		 1204static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206{
dc0fa718 1207 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1212 return false;
1213 } else {
dc0fa718 1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1215 return false;
1216 }
1217 return true;
1218}
1219
1220static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222{
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234}
1235
1236static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249}
1250
291906f1 1251static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1252 enum pipe pipe, int reg, u32 port_sel)
291906f1 1253{
47a05eca 1254 u32 val = I915_READ(reg);
4e634389 1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1257 reg, pipe_name(pipe));
de9a35ab 1258
75c5da27
DV		 1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
de9a35ab 1261 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1262}
1263
1264static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266{
47a05eca 1267 u32 val = I915_READ(reg);
b70ad586 1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1270 reg, pipe_name(pipe));
de9a35ab 1271
dc0fa718 1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1273 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1274 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1275}
1276
1277static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279{
1280 int reg;
1281 u32 val;
291906f1 1282
f0575e92
KP		 1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
b70ad586 1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 pipe_name(pipe));
291906f1
JB		 1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
b70ad586 1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 pipe_name(pipe));
291906f1 1298
e2debe91
PZ		 1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1302}
1303
63d7bbe9
JB		 1304/**
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1308 *
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1312 *
1313 * Note! This is for pre-ILK only.
7434a255
TR		 1314 *
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1316 */
1317static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321
58c6eaa2
DV		 1322 assert_pipe_disabled(dev_priv, pipe);
1323
63d7bbe9 1324 /* No really, not for ILK+ */
a0c4da24 1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1326
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1330
1331 reg = DPLL(pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1334
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1337 POSTING_READ(reg);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344 udelay(150); /* wait for warmup */
1345}
1346
1347/**
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1351 *
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1353 *
1354 * Note! This is for pre-ILK only.
1355 */
1356static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357{
1358 int reg;
1359 u32 val;
1360
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 return;
1364
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1367
1368 reg = DPLL(pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373}
1374
89b667f8
JB		 1375void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376{
1377 u32 port_mask;
1378
1379 if (!port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1381 else
1382 port_mask = DPLL_PORTC_READY_MASK;
1383
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1387}
1388
92f2584a 1389/**
e72f9fbf 1390 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1393 *
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1396 */
e2b78267 1397static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1398{
e2b78267
DV		 1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1404 if (WARN_ON(pll == NULL))
48da64a8
CW		 1405 return;
1406
1407 if (WARN_ON(pll->refcount == 0))
1408 return;
ee7b9f93 1409
46edb027
DV		 1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411 pll->name, pll->active, pll->on,
e2b78267 1412 crtc->base.base.id);
92f2584a 1413
cdbd2316
DV		 1414 if (pll->active++) {
1415 WARN_ON(!pll->on);
e9d6944e 1416 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1417 return;
1418 }
f4a091c7 1419 WARN_ON(pll->on);
ee7b9f93 1420
46edb027 1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1422 pll->enable(dev_priv, pll);
ee7b9f93 1423 pll->on = true;
92f2584a
JB		 1424}
1425
e2b78267 1426static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1427{
e2b78267
DV		 1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1430
92f2584a
JB		 1431 /* PCH only available on ILK+ */
1432 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1433 if (WARN_ON(pll == NULL))
ee7b9f93 1434 return;
92f2584a 1435
48da64a8
CW		 1436 if (WARN_ON(pll->refcount == 0))
1437 return;
7a419866 1438
46edb027
DV		 1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440 pll->name, pll->active, pll->on,
e2b78267 1441 crtc->base.base.id);
7a419866 1442
48da64a8 1443 if (WARN_ON(pll->active == 0)) {
e9d6944e 1444 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1445 return;
1446 }
1447
e9d6944e 1448 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1449 WARN_ON(!pll->on);
cdbd2316 1450 if (--pll->active)
7a419866 1451 return;
ee7b9f93 1452
46edb027 1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1454 pll->disable(dev_priv, pll);
ee7b9f93 1455 pll->on = false;
92f2584a
JB		 1456}
1457
b8a4f404
PZ		 1458static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
040484af 1460{
23670b32 1461 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1464 uint32_t reg, val, pipeconf_val;
040484af
JB		 1465
1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
1468
1469 /* Make sure PCH DPLL is enabled */
e72f9fbf 1470 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1471 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1472
1473 /* FDI must be feeding us bits for PCH ports */
1474 assert_fdi_tx_enabled(dev_priv, pipe);
1475 assert_fdi_rx_enabled(dev_priv, pipe);
1476
23670b32
DV		 1477 if (HAS_PCH_CPT(dev)) {
1478 /* Workaround: Set the timing override bit before enabling the
1479 * pch transcoder. */
1480 reg = TRANS_CHICKEN2(pipe);
1481 val = I915_READ(reg);
1482 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483 I915_WRITE(reg, val);
59c859d6 1484 }
23670b32 1485
ab9412ba 1486 reg = PCH_TRANSCONF(pipe);
040484af 1487 val = I915_READ(reg);
5f7f726d 1488 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1489
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1491 /*
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1494 */
dfd07d72
DV		 1495 val &= ~PIPECONF_BPC_MASK;
1496 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1497 }
5f7f726d
PZ		 1498
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1504 else
1505 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1506 else
1507 val |= TRANS_PROGRESSIVE;
1508
040484af
JB		 1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1512}
1513
8fb033d7 1514static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1515 enum transcoder cpu_transcoder)
040484af 1516{
8fb033d7 1517 u32 val, pipeconf_val;
8fb033d7
PZ		 1518
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1521
8fb033d7 1522 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1523 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1524 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1525
223a6fdf
PZ		 1526 /* Workaround: set timing override bit. */
1527 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1529 I915_WRITE(_TRANSA_CHICKEN2, val);
1530
25f3ef11 1531 val = TRANS_ENABLE;
937bb610 1532 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1533
9a76b1c6
PZ		 1534 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535 PIPECONF_INTERLACED_ILK)
a35f2679 1536 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1537 else
1538 val |= TRANS_PROGRESSIVE;
1539
ab9412ba
DV		 1540 I915_WRITE(LPT_TRANSCONF, val);
1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1542 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1543}
1544
b8a4f404
PZ		 1545static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546 enum pipe pipe)
040484af 1547{
23670b32
DV		 1548 struct drm_device *dev = dev_priv->dev;
1549 uint32_t reg, val;
040484af
JB		 1550
1551 /* FDI relies on the transcoder */
1552 assert_fdi_tx_disabled(dev_priv, pipe);
1553 assert_fdi_rx_disabled(dev_priv, pipe);
1554
291906f1
JB		 1555 /* Ports must be off as well */
1556 assert_pch_ports_disabled(dev_priv, pipe);
1557
ab9412ba 1558 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1559 val = I915_READ(reg);
1560 val &= ~TRANS_ENABLE;
1561 I915_WRITE(reg, val);
1562 /* wait for PCH transcoder off, transcoder state */
1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1565
1566 if (!HAS_PCH_IBX(dev)) {
1567 /* Workaround: Clear the timing override chicken bit again. */
1568 reg = TRANS_CHICKEN2(pipe);
1569 val = I915_READ(reg);
1570 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571 I915_WRITE(reg, val);
1572 }
040484af
JB		 1573}
1574
ab4d966c 1575static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1576{
8fb033d7
PZ		 1577 u32 val;
1578
ab9412ba 1579 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1580 val &= ~TRANS_ENABLE;
ab9412ba 1581 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1582 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1584 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1585
1586 /* Workaround: clear timing override bit. */
1587 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1589 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1590}
1591
b24e7179 1592/**
309cfea8 1593 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1594 * @dev_priv: i915 private structure
1595 * @pipe: pipe to enable
040484af 1596 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1597 *
1598 * Enable @pipe, making sure that various hardware specific requirements
1599 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600 *
1601 * @pipe should be %PIPE_A or %PIPE_B.
1602 *
1603 * Will wait until the pipe is actually running (i.e. first vblank) before
1604 * returning.
1605 */
040484af
JB		 1606static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607 bool pch_port)
b24e7179 1608{
702e7a56
PZ		 1609 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610 pipe);
1a240d4d 1611 enum pipe pch_transcoder;
b24e7179
JB		 1612 int reg;
1613 u32 val;
1614
58c6eaa2
DV		 1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1617
681e5811 1618 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1619 pch_transcoder = TRANSCODER_A;
1620 else
1621 pch_transcoder = pipe;
1622
b24e7179
JB		 1623 /*
1624 * A pipe without a PLL won't actually be able to drive bits from
1625 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1626 * need the check.
1627 */
1628 if (!HAS_PCH_SPLIT(dev_priv->dev))
1629 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1630 else {
1631 if (pch_port) {
1632 /* if driving the PCH, we need FDI enabled */
cc391bbb 1633 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1634 assert_fdi_tx_pll_enabled(dev_priv,
1635 (enum pipe) cpu_transcoder);
040484af
JB		 1636 }
1637 /* FIXME: assert CPU port conditions for SNB+ */
1638 }
b24e7179 1639
702e7a56 1640 reg = PIPECONF(cpu_transcoder);
b24e7179 1641 val = I915_READ(reg);
00d70b15
CW		 1642 if (val & PIPECONF_ENABLE)
1643 return;
1644
1645 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1646 intel_wait_for_vblank(dev_priv->dev, pipe);
1647}
1648
1649/**
309cfea8 1650 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to disable
1653 *
1654 * Disable @pipe, making sure that various hardware specific requirements
1655 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656 *
1657 * @pipe should be %PIPE_A or %PIPE_B.
1658 *
1659 * Will wait until the pipe has shut down before returning.
1660 */
1661static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663{
702e7a56
PZ		 1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
b24e7179
JB		 1666 int reg;
1667 u32 val;
1668
1669 /*
1670 * Make sure planes won't keep trying to pump pixels to us,
1671 * or we might hang the display.
1672 */
1673 assert_planes_disabled(dev_priv, pipe);
19332d7a 1674 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1675
1676 /* Don't disable pipe A or pipe A PLLs if needed */
1677 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678 return;
1679
702e7a56 1680 reg = PIPECONF(cpu_transcoder);
b24e7179 1681 val = I915_READ(reg);
00d70b15
CW		 1682 if ((val & PIPECONF_ENABLE) == 0)
1683 return;
1684
1685 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1686 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687}
1688
d74362c9
KP		 1689/*
1690 * Plane regs are double buffered, going from enabled->disabled needs a
1691 * trigger in order to latch. The display address reg provides this.
1692 */
6f1d69b0 1693void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1694 enum plane plane)
1695{
14f86147
DL		 1696 if (dev_priv->info->gen >= 4)
1697 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698 else
1699 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1700}
1701
b24e7179
JB		 1702/**
1703 * intel_enable_plane - enable a display plane on a given pipe
1704 * @dev_priv: i915 private structure
1705 * @plane: plane to enable
1706 * @pipe: pipe being fed
1707 *
1708 * Enable @plane on @pipe, making sure that @pipe is running first.
1709 */
1710static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711 enum plane plane, enum pipe pipe)
1712{
1713 int reg;
1714 u32 val;
1715
1716 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717 assert_pipe_enabled(dev_priv, pipe);
1718
1719 reg = DSPCNTR(plane);
1720 val = I915_READ(reg);
00d70b15
CW		 1721 if (val & DISPLAY_PLANE_ENABLE)
1722 return;
1723
1724 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1725 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1726 intel_wait_for_vblank(dev_priv->dev, pipe);
1727}
1728
b24e7179
JB		 1729/**
1730 * intel_disable_plane - disable a display plane
1731 * @dev_priv: i915 private structure
1732 * @plane: plane to disable
1733 * @pipe: pipe consuming the data
1734 *
1735 * Disable @plane; should be an independent operation.
1736 */
1737static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738 enum plane plane, enum pipe pipe)
1739{
1740 int reg;
1741 u32 val;
1742
1743 reg = DSPCNTR(plane);
1744 val = I915_READ(reg);
00d70b15
CW		 1745 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746 return;
1747
1748 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1749 intel_flush_display_plane(dev_priv, plane);
1750 intel_wait_for_vblank(dev_priv->dev, pipe);
1751}
1752
693db184
CW		 1753static bool need_vtd_wa(struct drm_device *dev)
1754{
1755#ifdef CONFIG_INTEL_IOMMU
1756 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757 return true;
1758#endif
1759 return false;
1760}
1761
127bd2ac 1762int
48b956c5 1763intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1764 struct drm_i915_gem_object *obj,
919926ae 1765 struct intel_ring_buffer *pipelined)
6b95a207 1766{
ce453d81 1767 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1768 u32 alignment;
1769 int ret;
1770
05394f39 1771 switch (obj->tiling_mode) {
6b95a207 1772 case I915_TILING_NONE:
534843da
CW		 1773 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774 alignment = 128 * 1024;
a6c45cf0 1775 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1776 alignment = 4 * 1024;
1777 else
1778 alignment = 64 * 1024;
6b95a207
KH		 1779 break;
1780 case I915_TILING_X:
1781 /* pin() will align the object as required by fence */
1782 alignment = 0;
1783 break;
1784 case I915_TILING_Y:
8bb6e959
DV		 1785 /* Despite that we check this in framebuffer_init userspace can
1786 * screw us over and change the tiling after the fact. Only
1787 * pinned buffers can't change their tiling. */
1788 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1789 return -EINVAL;
1790 default:
1791 BUG();
1792 }
1793
693db184
CW		 1794 /* Note that the w/a also requires 64 PTE of padding following the
1795 * bo. We currently fill all unused PTE with the shadow page and so
1796 * we should always have valid PTE following the scanout preventing
1797 * the VT-d warning.
1798 */
1799 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800 alignment = 256 * 1024;
1801
ce453d81 1802 dev_priv->mm.interruptible = false;
2da3b9b9 1803 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1804 if (ret)
ce453d81 1805 goto err_interruptible;
6b95a207
KH		 1806
1807 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808 * fence, whereas 965+ only requires a fence if using
1809 * framebuffer compression. For simplicity, we always install
1810 * a fence as the cost is not that onerous.
1811 */
06d98131 1812 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1813 if (ret)
1814 goto err_unpin;
1690e1eb 1815
9a5a53b3 1816 i915_gem_object_pin_fence(obj);
6b95a207 1817
ce453d81 1818 dev_priv->mm.interruptible = true;
6b95a207 1819 return 0;
48b956c5
CW		 1820
1821err_unpin:
1822 i915_gem_object_unpin(obj);
ce453d81
CW		 1823err_interruptible:
1824 dev_priv->mm.interruptible = true;
48b956c5 1825 return ret;
6b95a207
KH		 1826}
1827
1690e1eb
CW		 1828void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829{
1830 i915_gem_object_unpin_fence(obj);
1831 i915_gem_object_unpin(obj);
1832}
1833
c2c75131
DV		 1834/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835 * is assumed to be a power-of-two. */
bc752862
CW		 1836unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837 unsigned int tiling_mode,
1838 unsigned int cpp,
1839 unsigned int pitch)
c2c75131 1840{
bc752862
CW		 1841 if (tiling_mode != I915_TILING_NONE) {
1842 unsigned int tile_rows, tiles;
c2c75131 1843
bc752862
CW		 1844 tile_rows = *y / 8;
1845 *y %= 8;
c2c75131 1846
bc752862
CW		 1847 tiles = *x / (512/cpp);
1848 *x %= 512/cpp;
1849
1850 return tile_rows * pitch * 8 + tiles * 4096;
1851 } else {
1852 unsigned int offset;
1853
1854 offset = *y * pitch + *x * cpp;
1855 *y = 0;
1856 *x = (offset & 4095) / cpp;
1857 return offset & -4096;
1858 }
c2c75131
DV		 1859}
1860
17638cd6
JB		 1861static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862 int x, int y)
81255565
JB		 1863{
1864 struct drm_device *dev = crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867 struct intel_framebuffer *intel_fb;
05394f39 1868 struct drm_i915_gem_object *obj;
81255565 1869 int plane = intel_crtc->plane;
e506a0c6 1870 unsigned long linear_offset;
81255565 1871 u32 dspcntr;
5eddb70b 1872 u32 reg;
81255565
JB		 1873
1874 switch (plane) {
1875 case 0:
1876 case 1:
1877 break;
1878 default:
84f44ce7 1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1880 return -EINVAL;
1881 }
1882
1883 intel_fb = to_intel_framebuffer(fb);
1884 obj = intel_fb->obj;
81255565 1885
5eddb70b
CW		 1886 reg = DSPCNTR(plane);
1887 dspcntr = I915_READ(reg);
81255565
JB		 1888 /* Mask out pixel format bits in case we change it */
1889 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1890 switch (fb->pixel_format) {
1891 case DRM_FORMAT_C8:
81255565
JB		 1892 dspcntr |= DISPPLANE_8BPP;
1893 break;
57779d06
VS		 1894 case DRM_FORMAT_XRGB1555:
1895 case DRM_FORMAT_ARGB1555:
1896 dspcntr |= DISPPLANE_BGRX555;
81255565 1897 break;
57779d06
VS		 1898 case DRM_FORMAT_RGB565:
1899 dspcntr |= DISPPLANE_BGRX565;
1900 break;
1901 case DRM_FORMAT_XRGB8888:
1902 case DRM_FORMAT_ARGB8888:
1903 dspcntr |= DISPPLANE_BGRX888;
1904 break;
1905 case DRM_FORMAT_XBGR8888:
1906 case DRM_FORMAT_ABGR8888:
1907 dspcntr |= DISPPLANE_RGBX888;
1908 break;
1909 case DRM_FORMAT_XRGB2101010:
1910 case DRM_FORMAT_ARGB2101010:
1911 dspcntr |= DISPPLANE_BGRX101010;
1912 break;
1913 case DRM_FORMAT_XBGR2101010:
1914 case DRM_FORMAT_ABGR2101010:
1915 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1916 break;
1917 default:
baba133a 1918 BUG();
81255565 1919 }
57779d06 1920
a6c45cf0 1921 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1922 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1923 dspcntr |= DISPPLANE_TILED;
1924 else
1925 dspcntr &= ~DISPPLANE_TILED;
1926 }
1927
de1aa629
VS		 1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
5eddb70b 1931 I915_WRITE(reg, dspcntr);
81255565 1932
e506a0c6 1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1934
c2c75131
DV		 1935 if (INTEL_INFO(dev)->gen >= 4) {
1936 intel_crtc->dspaddr_offset =
bc752862
CW		 1937 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938 fb->bits_per_pixel / 8,
1939 fb->pitches[0]);
c2c75131
DV		 1940 linear_offset -= intel_crtc->dspaddr_offset;
1941 } else {
e506a0c6 1942 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1943 }
e506a0c6
DV		 1944
1945 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1947 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1948 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1949 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1951 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1952 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1953 } else
e506a0c6 1954 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1955 POSTING_READ(reg);
81255565 1956
17638cd6
JB		 1957 return 0;
1958}
1959
1960static int ironlake_update_plane(struct drm_crtc *crtc,
1961 struct drm_framebuffer *fb, int x, int y)
1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
17638cd6
JB		 1970 u32 dspcntr;
1971 u32 reg;
1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
27f8227b 1976 case 2:
17638cd6
JB		 1977 break;
1978 default:
84f44ce7 1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1980 return -EINVAL;
1981 }
1982
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
1985
1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1990 switch (fb->pixel_format) {
1991 case DRM_FORMAT_C8:
17638cd6
JB		 1992 dspcntr |= DISPPLANE_8BPP;
1993 break;
57779d06
VS		 1994 case DRM_FORMAT_RGB565:
1995 dspcntr |= DISPPLANE_BGRX565;
17638cd6 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_XRGB8888:
1998 case DRM_FORMAT_ARGB8888:
1999 dspcntr |= DISPPLANE_BGRX888;
2000 break;
2001 case DRM_FORMAT_XBGR8888:
2002 case DRM_FORMAT_ABGR8888:
2003 dspcntr |= DISPPLANE_RGBX888;
2004 break;
2005 case DRM_FORMAT_XRGB2101010:
2006 case DRM_FORMAT_ARGB2101010:
2007 dspcntr |= DISPPLANE_BGRX101010;
2008 break;
2009 case DRM_FORMAT_XBGR2101010:
2010 case DRM_FORMAT_ABGR2101010:
2011 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2012 break;
2013 default:
baba133a 2014 BUG();
17638cd6
JB		 2015 }
2016
2017 if (obj->tiling_mode != I915_TILING_NONE)
2018 dspcntr |= DISPPLANE_TILED;
2019 else
2020 dspcntr &= ~DISPPLANE_TILED;
2021
2022 /* must disable */
2023 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025 I915_WRITE(reg, dspcntr);
2026
e506a0c6 2027 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2028 intel_crtc->dspaddr_offset =
bc752862
CW		 2029 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030 fb->bits_per_pixel / 8,
2031 fb->pitches[0]);
c2c75131 2032 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2033
e506a0c6
DV		 2034 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2036 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2037 I915_MODIFY_DISPBASE(DSPSURF(plane),
2038 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2039 if (IS_HASWELL(dev)) {
2040 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041 } else {
2042 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044 }
17638cd6
JB		 2045 POSTING_READ(reg);
2046
2047 return 0;
2048}
2049
2050/* Assume fb object is pinned & idle & fenced and just update base pointers */
2051static int
2052intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y, enum mode_set_atomic state)
2054{
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2057
6b8e6ed0
CW		 2058 if (dev_priv->display.disable_fbc)
2059 dev_priv->display.disable_fbc(dev);
3dec0095 2060 intel_increase_pllclock(crtc);
81255565 2061
6b8e6ed0 2062 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2063}
2064
96a02917
VS		 2065void intel_display_handle_reset(struct drm_device *dev)
2066{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct drm_crtc *crtc;
2069
2070 /*
2071 * Flips in the rings have been nuked by the reset,
2072 * so complete all pending flips so that user space
2073 * will get its events and not get stuck.
2074 *
2075 * Also update the base address of all primary
2076 * planes to the the last fb to make sure we're
2077 * showing the correct fb after a reset.
2078 *
2079 * Need to make two loops over the crtcs so that we
2080 * don't try to grab a crtc mutex before the
2081 * pending_flip_queue really got woken up.
2082 */
2083
2084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086 enum plane plane = intel_crtc->plane;
2087
2088 intel_prepare_page_flip(dev, plane);
2089 intel_finish_page_flip_plane(dev, plane);
2090 }
2091
2092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095 mutex_lock(&crtc->mutex);
2096 if (intel_crtc->active)
2097 dev_priv->display.update_plane(crtc, crtc->fb,
2098 crtc->x, crtc->y);
2099 mutex_unlock(&crtc->mutex);
2100 }
2101}
2102
14667a4b
CW		 2103static int
2104intel_finish_fb(struct drm_framebuffer *old_fb)
2105{
2106 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108 bool was_interruptible = dev_priv->mm.interruptible;
2109 int ret;
2110
14667a4b
CW		 2111 /* Big Hammer, we also need to ensure that any pending
2112 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113 * current scanout is retired before unpinning the old
2114 * framebuffer.
2115 *
2116 * This should only fail upon a hung GPU, in which case we
2117 * can safely continue.
2118 */
2119 dev_priv->mm.interruptible = false;
2120 ret = i915_gem_object_finish_gpu(obj);
2121 dev_priv->mm.interruptible = was_interruptible;
2122
2123 return ret;
2124}
2125
198598d0
VS		 2126static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127{
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_master_private *master_priv;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132 if (!dev->primary->master)
2133 return;
2134
2135 master_priv = dev->primary->master->driver_priv;
2136 if (!master_priv->sarea_priv)
2137 return;
2138
2139 switch (intel_crtc->pipe) {
2140 case 0:
2141 master_priv->sarea_priv->pipeA_x = x;
2142 master_priv->sarea_priv->pipeA_y = y;
2143 break;
2144 case 1:
2145 master_priv->sarea_priv->pipeB_x = x;
2146 master_priv->sarea_priv->pipeB_y = y;
2147 break;
2148 default:
2149 break;
2150 }
2151}
2152
5c3b82e2 2153static int
3c4fdcfb 2154intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2155 struct drm_framebuffer *fb)
79e53945
JB		 2156{
2157 struct drm_device *dev = crtc->dev;
6b8e6ed0 2158 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2160 struct drm_framebuffer *old_fb;
5c3b82e2 2161 int ret;
79e53945
JB		 2162
2163 /* no fb bound */
94352cf9 2164 if (!fb) {
a5071c2f 2165 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2166 return 0;
2167 }
2168
7eb552ae 2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171 plane_name(intel_crtc->plane),
2172 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2173 return -EINVAL;
79e53945
JB		 2174 }
2175
5c3b82e2 2176 mutex_lock(&dev->struct_mutex);
265db958 2177 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2178 to_intel_framebuffer(fb)->obj,
919926ae 2179 NULL);
5c3b82e2
CW		 2180 if (ret != 0) {
2181 mutex_unlock(&dev->struct_mutex);
a5071c2f 2182 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2183 return ret;
2184 }
79e53945 2185
94352cf9 2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2187 if (ret) {
94352cf9 2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2189 mutex_unlock(&dev->struct_mutex);
a5071c2f 2190 DRM_ERROR("failed to update base address\n");
4e6cfefc 2191 return ret;
79e53945 2192 }
3c4fdcfb 2193
94352cf9
DV		 2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
6c4c86f5
DV		 2196 crtc->x = x;
2197 crtc->y = y;
94352cf9 2198
b7f1de28 2199 if (old_fb) {
d7697eea
DV		 2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2203 }
652c393a 2204
6b8e6ed0 2205 intel_update_fbc(dev);
5c3b82e2 2206 mutex_unlock(&dev->struct_mutex);
79e53945 2207
198598d0 2208 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2209
2210 return 0;
79e53945
JB		 2211}
2212
5e84e1a4
ZW		 2213static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214{
2215 struct drm_device *dev = crtc->dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218 int pipe = intel_crtc->pipe;
2219 u32 reg, temp;
2220
2221 /* enable normal train */
2222 reg = FDI_TX_CTL(pipe);
2223 temp = I915_READ(reg);
61e499bf 2224 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2227 } else {
2228 temp &= ~FDI_LINK_TRAIN_NONE;
2229 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2230 }
5e84e1a4
ZW		 2231 I915_WRITE(reg, temp);
2232
2233 reg = FDI_RX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 if (HAS_PCH_CPT(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238 } else {
2239 temp &= ~FDI_LINK_TRAIN_NONE;
2240 temp |= FDI_LINK_TRAIN_NONE;
2241 }
2242 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244 /* wait one idle pattern time */
2245 POSTING_READ(reg);
2246 udelay(1000);
357555c0
JB		 2247
2248 /* IVB wants error correction enabled */
2249 if (IS_IVYBRIDGE(dev))
2250 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2252}
2253
1e833f40
DV		 2254static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255{
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257}
2258
01a415fd
DV		 2259static void ivb_modeset_global_resources(struct drm_device *dev)
2260{
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *pipe_B_crtc =
2263 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264 struct intel_crtc *pipe_C_crtc =
2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266 uint32_t temp;
2267
1e833f40
DV		 2268 /*
2269 * When everything is off disable fdi C so that we could enable fdi B
2270 * with all lanes. Note that we don't care about enabled pipes without
2271 * an enabled pch encoder.
2272 */
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278 temp = I915_READ(SOUTH_CHICKEN1);
2279 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281 I915_WRITE(SOUTH_CHICKEN1, temp);
2282 }
2283}
2284
8db9d77b
ZW		 2285/* The FDI link training functions for ILK/Ibexpeak. */
2286static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287{
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
0fc932b8 2292 int plane = intel_crtc->plane;
5eddb70b 2293 u32 reg, temp, tries;
8db9d77b 2294
0fc932b8
JB		 2295 /* FDI needs bits from pipe & plane first */
2296 assert_pipe_enabled(dev_priv, pipe);
2297 assert_plane_enabled(dev_priv, plane);
2298
e1a44743
AJ		 2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
5eddb70b
CW		 2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
e1a44743
AJ		 2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2305 I915_WRITE(reg, temp);
2306 I915_READ(reg);
e1a44743
AJ		 2307 udelay(150);
2308
8db9d77b 2309 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2310 reg = FDI_TX_CTL(pipe);
2311 temp = I915_READ(reg);
627eb5a3
DV		 2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2317
5eddb70b
CW		 2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
8db9d77b
ZW		 2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324 POSTING_READ(reg);
8db9d77b
ZW		 2325 udelay(150);
2326
5b2adf89 2327 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2328 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2331
5eddb70b 2332 reg = FDI_RX_IIR(pipe);
e1a44743 2333 for (tries = 0; tries < 5; tries++) {
5eddb70b 2334 temp = I915_READ(reg);
8db9d77b
ZW		 2335 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337 if ((temp & FDI_RX_BIT_LOCK)) {
2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2339 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2340 break;
2341 }
8db9d77b 2342 }
e1a44743 2343 if (tries == 5)
5eddb70b 2344 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2345
2346 /* Train 2 */
5eddb70b
CW		 2347 reg = FDI_TX_CTL(pipe);
2348 temp = I915_READ(reg);
8db9d77b
ZW		 2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2351 I915_WRITE(reg, temp);
8db9d77b 2352
5eddb70b
CW		 2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
8db9d77b
ZW		 2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2357 I915_WRITE(reg, temp);
8db9d77b 2358
5eddb70b
CW		 2359 POSTING_READ(reg);
2360 udelay(150);
8db9d77b 2361
5eddb70b 2362 reg = FDI_RX_IIR(pipe);
e1a44743 2363 for (tries = 0; tries < 5; tries++) {
5eddb70b 2364 temp = I915_READ(reg);
8db9d77b
ZW		 2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2369 DRM_DEBUG_KMS("FDI train 2 done.\n");
2370 break;
2371 }
8db9d77b 2372 }
e1a44743 2373 if (tries == 5)
5eddb70b 2374 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2375
2376 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2377
8db9d77b
ZW		 2378}
2379
0206e353 2380static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2381 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385};
2386
2387/* The FDI link training functions for SNB/Cougarpoint. */
2388static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389{
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
fa37d39e 2394 u32 reg, temp, i, retry;
8db9d77b 2395
e1a44743
AJ		 2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
5eddb70b
CW		 2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
e1a44743
AJ		 2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
e1a44743
AJ		 2405 udelay(150);
2406
8db9d77b 2407 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
627eb5a3
DV		 2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415 /* SNB-B */
2416 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2418
d74cf324
DV		 2419 I915_WRITE(FDI_RX_MISC(pipe),
2420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
5eddb70b
CW		 2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
8db9d77b
ZW		 2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427 } else {
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430 }
5eddb70b
CW		 2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433 POSTING_READ(reg);
8db9d77b
ZW		 2434 udelay(150);
2435
0206e353 2436 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2441 I915_WRITE(reg, temp);
2442
2443 POSTING_READ(reg);
8db9d77b
ZW		 2444 udelay(500);
2445
fa37d39e
SP		 2446 for (retry = 0; retry < 5; retry++) {
2447 reg = FDI_RX_IIR(pipe);
2448 temp = I915_READ(reg);
2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_BIT_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453 break;
2454 }
2455 udelay(50);
8db9d77b 2456 }
fa37d39e
SP		 2457 if (retry < 5)
2458 break;
8db9d77b
ZW		 2459 }
2460 if (i == 4)
5eddb70b 2461 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2462
2463 /* Train 2 */
5eddb70b
CW		 2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
2468 if (IS_GEN6(dev)) {
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 /* SNB-B */
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472 }
5eddb70b 2473 I915_WRITE(reg, temp);
8db9d77b 2474
5eddb70b
CW		 2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480 } else {
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 }
5eddb70b
CW		 2484 I915_WRITE(reg, temp);
2485
2486 POSTING_READ(reg);
8db9d77b
ZW		 2487 udelay(150);
2488
0206e353 2489 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
8db9d77b
ZW		 2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
8db9d77b
ZW		 2497 udelay(500);
2498
fa37d39e
SP		 2499 for (retry = 0; retry < 5; retry++) {
2500 reg = FDI_RX_IIR(pipe);
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503 if (temp & FDI_RX_SYMBOL_LOCK) {
2504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506 break;
2507 }
2508 udelay(50);
8db9d77b 2509 }
fa37d39e
SP		 2510 if (retry < 5)
2511 break;
8db9d77b
ZW		 2512 }
2513 if (i == 4)
5eddb70b 2514 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2515
2516 DRM_DEBUG_KMS("FDI train done.\n");
2517}
2518
357555c0
JB		 2519/* Manual link training for Ivy Bridge A0 parts */
2520static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2526 u32 reg, temp, i;
2527
2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
2537 udelay(150);
2538
01a415fd
DV		 2539 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540 I915_READ(FDI_RX_IIR(pipe)));
2541
357555c0
JB		 2542 /* enable CPU FDI TX and PCH FDI RX */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
627eb5a3
DV		 2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2551 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
d74cf324
DV		 2554 I915_WRITE(FDI_RX_MISC(pipe),
2555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
357555c0
JB		 2557 reg = FDI_RX_CTL(pipe);
2558 temp = I915_READ(reg);
2559 temp &= ~FDI_LINK_TRAIN_AUTO;
2560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2562 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
357555c0
JB		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582 if (temp & FDI_RX_BIT_LOCK ||
2583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp);
2600
2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
2608 udelay(150);
2609
0206e353 2610 for (i = 0; i < 4; i++) {
357555c0
JB		 2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(500);
2619
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
2625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2626 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2627 break;
2628 }
2629 }
2630 if (i == 4)
2631 DRM_ERROR("FDI train 2 fail!\n");
2632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634}
2635
88cefb6c 2636static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2637{
88cefb6c 2638 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2639 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2640 int pipe = intel_crtc->pipe;
5eddb70b 2641 u32 reg, temp;
79e53945 2642
c64e311e 2643
c98e9dcf 2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
627eb5a3
DV		 2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652 POSTING_READ(reg);
c98e9dcf
JB		 2653 udelay(200);
2654
2655 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2656 temp = I915_READ(reg);
2657 I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659 POSTING_READ(reg);
c98e9dcf
JB		 2660 udelay(200);
2661
20749730
PZ		 2662 /* Enable CPU FDI TX PLL, always on for Ironlake */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2667
20749730
PZ		 2668 POSTING_READ(reg);
2669 udelay(100);
6be4a607 2670 }
0e23b99d
JB		 2671}
2672
88cefb6c
DV		 2673static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674{
2675 struct drm_device *dev = intel_crtc->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int pipe = intel_crtc->pipe;
2678 u32 reg, temp;
2679
2680 /* Switch from PCDclk to Rawclk */
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685 /* Disable CPU FDI TX PLL */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
2691 udelay(100);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697 /* Wait for the clocks to turn off. */
2698 POSTING_READ(reg);
2699 udelay(100);
2700}
2701
0fc932b8
JB		 2702static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703{
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp;
2709
2710 /* disable CPU FDI tx and PCH FDI rx */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714 POSTING_READ(reg);
2715
2716 reg = FDI_RX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(0x7 << 16);
dfd07d72 2719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722 POSTING_READ(reg);
2723 udelay(100);
2724
2725 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2726 if (HAS_PCH_IBX(dev)) {
2727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2728 }
0fc932b8
JB		 2729
2730 /* still set train pattern 1 */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1;
2735 I915_WRITE(reg, temp);
2736
2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (HAS_PCH_CPT(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 }
2746 /* BPC in FDI rx is consistent with that in PIPECONF */
2747 temp &= ~(0x07 << 16);
dfd07d72 2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2749 I915_WRITE(reg, temp);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753}
2754
5bb61643
CW		 2755static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756{
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2760 unsigned long flags;
2761 bool pending;
2762
10d83730
VS		 2763 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2765 return false;
2766
2767 spin_lock_irqsave(&dev->event_lock, flags);
2768 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769 spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771 return pending;
2772}
2773
e6c3a2a6
CW		 2774static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775{
0f91128d 2776 struct drm_device *dev = crtc->dev;
5bb61643 2777 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2778
2779 if (crtc->fb == NULL)
2780 return;
2781
2c10d571
DV		 2782 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
5bb61643
CW		 2784 wait_event(dev_priv->pending_flip_queue,
2785 !intel_crtc_has_pending_flip(crtc));
2786
0f91128d
CW		 2787 mutex_lock(&dev->struct_mutex);
2788 intel_finish_fb(crtc->fb);
2789 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2790}
2791
e615efe4
ED		 2792/* Program iCLKIP clock to the desired frequency */
2793static void lpt_program_iclkip(struct drm_crtc *crtc)
2794{
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798 u32 temp;
2799
09153000
DV		 2800 mutex_lock(&dev_priv->dpio_lock);
2801
e615efe4
ED		 2802 /* It is necessary to ungate the pixclk gate prior to programming
2803 * the divisors, and gate it back when it is done.
2804 */
2805 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807 /* Disable SSCCTL */
2808 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2809 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810 SBI_SSCCTL_DISABLE,
2811 SBI_ICLK);
e615efe4
ED		 2812
2813 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814 if (crtc->mode.clock == 20000) {
2815 auxdiv = 1;
2816 divsel = 0x41;
2817 phaseinc = 0x20;
2818 } else {
2819 /* The iCLK virtual clock root frequency is in MHz,
2820 * but the crtc->mode.clock in in KHz. To get the divisors,
2821 * it is necessary to divide one by another, so we
2822 * convert the virtual clock precision to KHz here for higher
2823 * precision.
2824 */
2825 u32 iclk_virtual_root_freq = 172800 * 1000;
2826 u32 iclk_pi_range = 64;
2827 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830 msb_divisor_value = desired_divisor / iclk_pi_range;
2831 pi_value = desired_divisor % iclk_pi_range;
2832
2833 auxdiv = 0;
2834 divsel = msb_divisor_value - 2;
2835 phaseinc = pi_value;
2836 }
2837
2838 /* This should not happen with any sane values */
2839 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845 crtc->mode.clock,
2846 auxdiv,
2847 divsel,
2848 phasedir,
2849 phaseinc);
2850
2851 /* Program SSCDIVINTPHASE6 */
988d6ee8 2852 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2853 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2859 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2860
2861 /* Program SSCAUXDIV */
988d6ee8 2862 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2863 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2865 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2866
2867 /* Enable modulator and associated divider */
988d6ee8 2868 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2869 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2870 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2871
2872 /* Wait for initialization time */
2873 udelay(24);
2874
2875 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2876
2877 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2878}
2879
275f01b2
DV		 2880static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2882{
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2893
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902}
2903
f67a559d
JB		 2904/*
2905 * Enable PCH resources required for PCH ports:
2906 * - PCH PLLs
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2910 * - transcoder
2911 */
2912static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
ee7b9f93 2918 u32 reg, temp;
2c07245f 2919
ab9412ba 2920 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2921
cd986abb
DV		 2922 /* Write the TU size bits before fdi link training, so that error
2923 * detection works. */
2924 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
c98e9dcf 2927 /* For PCH output, training FDI link */
674cf967 2928 dev_priv->display.fdi_link_train(crtc);
2c07245f 2929
572deb37
DV		 2930 /* XXX: pch pll's can be enabled any time before we enable the PCH
2931 * transcoder, and we actually should do this to not upset any PCH
2932 * transcoder that already use the clock when we share it.
2933 *
e72f9fbf
DV		 2934 * Note that enable_shared_dpll tries to do the right thing, but
2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2936 * the right LVDS enable sequence. */
2937 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2938
303b81e0 2939 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2940 u32 sel;
4b645f14 2941
c98e9dcf 2942 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2943 temp |= TRANS_DPLL_ENABLE(pipe);
2944 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2946 temp |= sel;
2947 else
2948 temp &= ~sel;
c98e9dcf 2949 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2950 }
5eddb70b 2951
d9b6cb56
JB		 2952 /* set transcoder timing, panel must allow it */
2953 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2955
303b81e0 2956 intel_fdi_normal_train(crtc);
5e84e1a4 2957
c98e9dcf
JB		 2958 /* For PCH DP, enable TRANS_DP_CTL */
2959 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2960 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2962 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2963 reg = TRANS_DP_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2966 TRANS_DP_SYNC_MASK |
2967 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2968 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969 TRANS_DP_ENH_FRAMING);
9325c9f0 2970 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2971
2972 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2973 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2974 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2975 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2976
2977 switch (intel_trans_dp_port_sel(crtc)) {
2978 case PCH_DP_B:
5eddb70b 2979 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2980 break;
2981 case PCH_DP_C:
5eddb70b 2982 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2983 break;
2984 case PCH_DP_D:
5eddb70b 2985 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2986 break;
2987 default:
e95d41e1 2988 BUG();
32f9d658 2989 }
2c07245f 2990
5eddb70b 2991 I915_WRITE(reg, temp);
6be4a607 2992 }
b52eb4dc 2993
b8a4f404 2994 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 2995}
2996
1507e5bd
PZ		 2997static void lpt_pch_enable(struct drm_crtc *crtc)
2998{
2999 struct drm_device *dev = crtc->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3003
ab9412ba 3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3005
8c52b5e8 3006 lpt_program_iclkip(crtc);
1507e5bd 3007
0540e488 3008 /* Set transcoder timing. */
275f01b2 3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3010
937bb610 3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3012}
3013
e2b78267 3014static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3015{
e2b78267 3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3017
3018 if (pll == NULL)
3019 return;
3020
3021 if (pll->refcount == 0) {
46edb027 3022 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3023 return;
3024 }
3025
f4a091c7
DV		 3026 if (--pll->refcount == 0) {
3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
a43f6e0f 3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3032}
3033
e2b78267 3034static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
ee7b9f93 3035{
e2b78267
DV		 3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038 enum intel_dpll_id i;
ee7b9f93 3039
ee7b9f93 3040 if (pll) {
46edb027
DV		 3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042 crtc->base.base.id, pll->name);
e2b78267 3043 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3044 }
3045
98b6bd99
DV		 3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3048 i = crtc->pipe;
e72f9fbf 3049 pll = &dev_priv->shared_dplls[i];
98b6bd99 3050
46edb027
DV		 3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052 crtc->base.base.id, pll->name);
98b6bd99
DV		 3053
3054 goto found;
3055 }
3056
e72f9fbf
DV		 3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3059
3060 /* Only want to check enabled timings first */
3061 if (pll->refcount == 0)
3062 continue;
3063
e9a632a5
DV		 3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065 fp == I915_READ(PCH_FP0(pll->id))) {
46edb027 3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3067 crtc->base.base.id,
46edb027 3068 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3069
3070 goto found;
3071 }
3072 }
3073
3074 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3077 if (pll->refcount == 0) {
46edb027
DV		 3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3080 goto found;
3081 }
3082 }
3083
3084 return NULL;
3085
3086found:
a43f6e0f 3087 crtc->config.shared_dpll = i;
46edb027
DV		 3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089 pipe_name(crtc->pipe));
66e985c0 3090
cdbd2316 3091 if (pll->active == 0) {
66e985c0
DV		 3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093 sizeof(pll->hw_state));
3094
46edb027 3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3096 WARN_ON(pll->on);
e9d6944e 3097 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3098
cdbd2316 3099 /* Wait for the clocks to stabilize before rewriting the regs */
e9a632a5
DV		 3100 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101 POSTING_READ(PCH_DPLL(pll->id));
cdbd2316
DV		 3102 udelay(150);
3103
e9a632a5
DV		 3104 I915_WRITE(PCH_FP0(pll->id), fp);
3105 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
cdbd2316
DV		 3106 }
3107 pll->refcount++;
e04c7350 3108
ee7b9f93
JB		 3109 return pll;
3110}
3111
a1520318 3112static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3113{
3114 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3115 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3116 u32 temp;
3117
3118 temp = I915_READ(dslreg);
3119 udelay(500);
3120 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3121 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3122 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3123 }
3124}
3125
b074cec8
JB		 3126static void ironlake_pfit_enable(struct intel_crtc *crtc)
3127{
3128 struct drm_device *dev = crtc->base.dev;
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 int pipe = crtc->pipe;
3131
0ef37f3f 3132 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3133 /* Force use of hard-coded filter coefficients
3134 * as some pre-programmed values are broken,
3135 * e.g. x201.
3136 */
3137 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139 PF_PIPE_SEL_IVB(pipe));
3140 else
3141 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3144 }
3145}
3146
bb53d4ae
VS		 3147static void intel_enable_planes(struct drm_crtc *crtc)
3148{
3149 struct drm_device *dev = crtc->dev;
3150 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151 struct intel_plane *intel_plane;
3152
3153 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154 if (intel_plane->pipe == pipe)
3155 intel_plane_restore(&intel_plane->base);
3156}
3157
3158static void intel_disable_planes(struct drm_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3163
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_disable(&intel_plane->base);
3167}
3168
f67a559d
JB		 3169static void ironlake_crtc_enable(struct drm_crtc *crtc)
3170{
3171 struct drm_device *dev = crtc->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3174 struct intel_encoder *encoder;
f67a559d
JB		 3175 int pipe = intel_crtc->pipe;
3176 int plane = intel_crtc->plane;
3177 u32 temp;
f67a559d 3178
08a48469
DV		 3179 WARN_ON(!crtc->enabled);
3180
f67a559d
JB		 3181 if (intel_crtc->active)
3182 return;
3183
3184 intel_crtc->active = true;
8664281b
PZ		 3185
3186 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3188
f67a559d
JB		 3189 intel_update_watermarks(dev);
3190
3191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3192 temp = I915_READ(PCH_LVDS);
3193 if ((temp & LVDS_PORT_EN) == 0)
3194 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3195 }
3196
f67a559d 3197
5bfe2ac0 3198 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3199 /* Note: FDI PLL enabling _must_ be done before we enable the
3200 * cpu pipes, hence this is separate from all the other fdi/pch
3201 * enabling. */
88cefb6c 3202 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3203 } else {
3204 assert_fdi_tx_disabled(dev_priv, pipe);
3205 assert_fdi_rx_disabled(dev_priv, pipe);
3206 }
f67a559d 3207
bf49ec8c
DV		 3208 for_each_encoder_on_crtc(dev, crtc, encoder)
3209 if (encoder->pre_enable)
3210 encoder->pre_enable(encoder);
f67a559d
JB		 3211
3212 /* Enable panel fitting for LVDS */
b074cec8 3213 ironlake_pfit_enable(intel_crtc);
f67a559d 3214
9c54c0dd
JB		 3215 /*
3216 * On ILK+ LUT must be loaded before the pipe is running but with
3217 * clocks enabled
3218 */
3219 intel_crtc_load_lut(crtc);
3220
5bfe2ac0
DV		 3221 intel_enable_pipe(dev_priv, pipe,
3222 intel_crtc->config.has_pch_encoder);
f67a559d 3223 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3224 intel_enable_planes(crtc);
5c38d48c 3225 intel_crtc_update_cursor(crtc, true);
f67a559d 3226
5bfe2ac0 3227 if (intel_crtc->config.has_pch_encoder)
f67a559d 3228 ironlake_pch_enable(crtc);
c98e9dcf 3229
d1ebd816 3230 mutex_lock(&dev->struct_mutex);
bed4a673 3231 intel_update_fbc(dev);
d1ebd816
BW		 3232 mutex_unlock(&dev->struct_mutex);
3233
fa5c73b1
DV		 3234 for_each_encoder_on_crtc(dev, crtc, encoder)
3235 encoder->enable(encoder);
61b77ddd
DV		 3236
3237 if (HAS_PCH_CPT(dev))
a1520318 3238 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3239
3240 /*
3241 * There seems to be a race in PCH platform hw (at least on some
3242 * outputs) where an enabled pipe still completes any pageflip right
3243 * away (as if the pipe is off) instead of waiting for vblank. As soon
3244 * as the first vblank happend, everything works as expected. Hence just
3245 * wait for one vblank before returning to avoid strange things
3246 * happening.
3247 */
3248 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3249}
3250
42db64ef
PZ		 3251/* IPS only exists on ULT machines and is tied to pipe A. */
3252static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3253{
3254 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3255}
3256
3257static void hsw_enable_ips(struct intel_crtc *crtc)
3258{
3259 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3260
3261 if (!crtc->config.ips_enabled)
3262 return;
3263
3264 /* We can only enable IPS after we enable a plane and wait for a vblank.
3265 * We guarantee that the plane is enabled by calling intel_enable_ips
3266 * only after intel_enable_plane. And intel_enable_plane already waits
3267 * for a vblank, so all we need to do here is to enable the IPS bit. */
3268 assert_plane_enabled(dev_priv, crtc->plane);
3269 I915_WRITE(IPS_CTL, IPS_ENABLE);
3270}
3271
3272static void hsw_disable_ips(struct intel_crtc *crtc)
3273{
3274 struct drm_device *dev = crtc->base.dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276
3277 if (!crtc->config.ips_enabled)
3278 return;
3279
3280 assert_plane_enabled(dev_priv, crtc->plane);
3281 I915_WRITE(IPS_CTL, 0);
3282
3283 /* We need to wait for a vblank before we can disable the plane. */
3284 intel_wait_for_vblank(dev, crtc->pipe);
3285}
3286
4f771f10
PZ		 3287static void haswell_crtc_enable(struct drm_crtc *crtc)
3288{
3289 struct drm_device *dev = crtc->dev;
3290 struct drm_i915_private *dev_priv = dev->dev_private;
3291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292 struct intel_encoder *encoder;
3293 int pipe = intel_crtc->pipe;
3294 int plane = intel_crtc->plane;
4f771f10
PZ		 3295
3296 WARN_ON(!crtc->enabled);
3297
3298 if (intel_crtc->active)
3299 return;
3300
3301 intel_crtc->active = true;
8664281b
PZ		 3302
3303 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3304 if (intel_crtc->config.has_pch_encoder)
3305 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3306
4f771f10
PZ		 3307 intel_update_watermarks(dev);
3308
5bfe2ac0 3309 if (intel_crtc->config.has_pch_encoder)
04945641 3310 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3311
3312 for_each_encoder_on_crtc(dev, crtc, encoder)
3313 if (encoder->pre_enable)
3314 encoder->pre_enable(encoder);
3315
1f544388 3316 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3317
1f544388 3318 /* Enable panel fitting for eDP */
b074cec8 3319 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3320
3321 /*
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3323 * clocks enabled
3324 */
3325 intel_crtc_load_lut(crtc);
3326
1f544388 3327 intel_ddi_set_pipe_settings(crtc);
8228c251 3328 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3329
5bfe2ac0
DV		 3330 intel_enable_pipe(dev_priv, pipe,
3331 intel_crtc->config.has_pch_encoder);
4f771f10 3332 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3333 intel_enable_planes(crtc);
5c38d48c 3334 intel_crtc_update_cursor(crtc, true);
4f771f10 3335
42db64ef
PZ		 3336 hsw_enable_ips(intel_crtc);
3337
5bfe2ac0 3338 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3339 lpt_pch_enable(crtc);
4f771f10
PZ		 3340
3341 mutex_lock(&dev->struct_mutex);
3342 intel_update_fbc(dev);
3343 mutex_unlock(&dev->struct_mutex);
3344
4f771f10
PZ		 3345 for_each_encoder_on_crtc(dev, crtc, encoder)
3346 encoder->enable(encoder);
3347
4f771f10
PZ		 3348 /*
3349 * There seems to be a race in PCH platform hw (at least on some
3350 * outputs) where an enabled pipe still completes any pageflip right
3351 * away (as if the pipe is off) instead of waiting for vblank. As soon
3352 * as the first vblank happend, everything works as expected. Hence just
3353 * wait for one vblank before returning to avoid strange things
3354 * happening.
3355 */
3356 intel_wait_for_vblank(dev, intel_crtc->pipe);
3357}
3358
3f8dce3a
DV		 3359static void ironlake_pfit_disable(struct intel_crtc *crtc)
3360{
3361 struct drm_device *dev = crtc->base.dev;
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363 int pipe = crtc->pipe;
3364
3365 /* To avoid upsetting the power well on haswell only disable the pfit if
3366 * it's in use. The hw state code will make sure we get this right. */
3367 if (crtc->config.pch_pfit.size) {
3368 I915_WRITE(PF_CTL(pipe), 0);
3369 I915_WRITE(PF_WIN_POS(pipe), 0);
3370 I915_WRITE(PF_WIN_SZ(pipe), 0);
3371 }
3372}
3373
6be4a607
JB		 3374static void ironlake_crtc_disable(struct drm_crtc *crtc)
3375{
3376 struct drm_device *dev = crtc->dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3379 struct intel_encoder *encoder;
6be4a607
JB		 3380 int pipe = intel_crtc->pipe;
3381 int plane = intel_crtc->plane;
5eddb70b 3382 u32 reg, temp;
b52eb4dc 3383
ef9c3aee 3384
f7abfe8b
CW		 3385 if (!intel_crtc->active)
3386 return;
3387
ea9d758d
DV		 3388 for_each_encoder_on_crtc(dev, crtc, encoder)
3389 encoder->disable(encoder);
3390
e6c3a2a6 3391 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3392 drm_vblank_off(dev, pipe);
913d8d11 3393
973d04f9
CW		 3394 if (dev_priv->cfb_plane == plane)
3395 intel_disable_fbc(dev);
2c07245f 3396
0d5b8c61 3397 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3398 intel_disable_planes(crtc);
0d5b8c61
VS		 3399 intel_disable_plane(dev_priv, plane, pipe);
3400
d925c59a
DV		 3401 if (intel_crtc->config.has_pch_encoder)
3402 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3403
b24e7179 3404 intel_disable_pipe(dev_priv, pipe);
32f9d658 3405
3f8dce3a 3406 ironlake_pfit_disable(intel_crtc);
2c07245f 3407
bf49ec8c
DV		 3408 for_each_encoder_on_crtc(dev, crtc, encoder)
3409 if (encoder->post_disable)
3410 encoder->post_disable(encoder);
2c07245f 3411
d925c59a
DV		 3412 if (intel_crtc->config.has_pch_encoder) {
3413 ironlake_fdi_disable(crtc);
249c0e64 3414
d925c59a
DV		 3415 ironlake_disable_pch_transcoder(dev_priv, pipe);
3416 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3417
d925c59a
DV		 3418 if (HAS_PCH_CPT(dev)) {
3419 /* disable TRANS_DP_CTL */
3420 reg = TRANS_DP_CTL(pipe);
3421 temp = I915_READ(reg);
3422 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3423 TRANS_DP_PORT_SEL_MASK);
3424 temp |= TRANS_DP_PORT_SEL_NONE;
3425 I915_WRITE(reg, temp);
3426
3427 /* disable DPLL_SEL */
3428 temp = I915_READ(PCH_DPLL_SEL);
11887397 3429 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3430 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3431 }
e3421a18 3432
d925c59a 3433 /* disable PCH DPLL */
e72f9fbf 3434 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3435
d925c59a
DV		 3436 ironlake_fdi_pll_disable(intel_crtc);
3437 }
6b383a7f 3438
f7abfe8b 3439 intel_crtc->active = false;
6b383a7f 3440 intel_update_watermarks(dev);
d1ebd816
BW		 3441
3442 mutex_lock(&dev->struct_mutex);
6b383a7f 3443 intel_update_fbc(dev);
d1ebd816 3444 mutex_unlock(&dev->struct_mutex);
6be4a607 3445}
1b3c7a47 3446
4f771f10 3447static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3448{
4f771f10
PZ		 3449 struct drm_device *dev = crtc->dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3452 struct intel_encoder *encoder;
3453 int pipe = intel_crtc->pipe;
3454 int plane = intel_crtc->plane;
3b117c8f 3455 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3456
4f771f10
PZ		 3457 if (!intel_crtc->active)
3458 return;
3459
3460 for_each_encoder_on_crtc(dev, crtc, encoder)
3461 encoder->disable(encoder);
3462
3463 intel_crtc_wait_for_pending_flips(crtc);
3464 drm_vblank_off(dev, pipe);
4f771f10 3465
891348b2 3466 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3467 if (dev_priv->cfb_plane == plane)
3468 intel_disable_fbc(dev);
3469
42db64ef
PZ		 3470 hsw_disable_ips(intel_crtc);
3471
0d5b8c61 3472 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3473 intel_disable_planes(crtc);
891348b2
RV		 3474 intel_disable_plane(dev_priv, plane, pipe);
3475
8664281b
PZ		 3476 if (intel_crtc->config.has_pch_encoder)
3477 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3478 intel_disable_pipe(dev_priv, pipe);
3479
ad80a810 3480 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3481
3f8dce3a 3482 ironlake_pfit_disable(intel_crtc);
4f771f10 3483
1f544388 3484 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3485
3486 for_each_encoder_on_crtc(dev, crtc, encoder)
3487 if (encoder->post_disable)
3488 encoder->post_disable(encoder);
3489
88adfff1 3490 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3491 lpt_disable_pch_transcoder(dev_priv);
8664281b 3492 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3493 intel_ddi_fdi_disable(crtc);
83616634 3494 }
4f771f10
PZ		 3495
3496 intel_crtc->active = false;
3497 intel_update_watermarks(dev);
3498
3499 mutex_lock(&dev->struct_mutex);
3500 intel_update_fbc(dev);
3501 mutex_unlock(&dev->struct_mutex);
3502}
3503
ee7b9f93
JB		 3504static void ironlake_crtc_off(struct drm_crtc *crtc)
3505{
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3507 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3508}
3509
6441ab5f
PZ		 3510static void haswell_crtc_off(struct drm_crtc *crtc)
3511{
3512 intel_ddi_put_crtc_pll(crtc);
3513}
3514
02e792fb
DV		 3515static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3516{
02e792fb 3517 if (!enable && intel_crtc->overlay) {
23f09ce3 3518 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3519 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3520
23f09ce3 3521 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3522 dev_priv->mm.interruptible = false;
3523 (void) intel_overlay_switch_off(intel_crtc->overlay);
3524 dev_priv->mm.interruptible = true;
23f09ce3 3525 mutex_unlock(&dev->struct_mutex);
02e792fb 3526 }
02e792fb 3527
5dcdbcb0
CW		 3528 /* Let userspace switch the overlay on again. In most cases userspace
3529 * has to recompute where to put it anyway.
3530 */
02e792fb
DV		 3531}
3532
61bc95c1
EE		 3533/**
3534 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3535 * cursor plane briefly if not already running after enabling the display
3536 * plane.
3537 * This workaround avoids occasional blank screens when self refresh is
3538 * enabled.
3539 */
3540static void
3541g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3542{
3543 u32 cntl = I915_READ(CURCNTR(pipe));
3544
3545 if ((cntl & CURSOR_MODE) == 0) {
3546 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3547
3548 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3549 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3550 intel_wait_for_vblank(dev_priv->dev, pipe);
3551 I915_WRITE(CURCNTR(pipe), cntl);
3552 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3553 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3554 }
3555}
3556
2dd24552
JB		 3557static void i9xx_pfit_enable(struct intel_crtc *crtc)
3558{
3559 struct drm_device *dev = crtc->base.dev;
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 struct intel_crtc_config *pipe_config = &crtc->config;
3562
328d8e82 3563 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3564 return;
3565
2dd24552 3566 /*
c0b03411
DV		 3567 * The panel fitter should only be adjusted whilst the pipe is disabled,
3568 * according to register description and PRM.
2dd24552 3569 */
c0b03411
DV		 3570 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3571 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3572
b074cec8
JB		 3573 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3574 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3575
3576 /* Border color in case we don't scale up to the full screen. Black by
3577 * default, change to something else for debugging. */
3578 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3579}
3580
89b667f8
JB		 3581static void valleyview_crtc_enable(struct drm_crtc *crtc)
3582{
3583 struct drm_device *dev = crtc->dev;
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586 struct intel_encoder *encoder;
3587 int pipe = intel_crtc->pipe;
3588 int plane = intel_crtc->plane;
3589
3590 WARN_ON(!crtc->enabled);
3591
3592 if (intel_crtc->active)
3593 return;
3594
3595 intel_crtc->active = true;
3596 intel_update_watermarks(dev);
3597
3598 mutex_lock(&dev_priv->dpio_lock);
3599
3600 for_each_encoder_on_crtc(dev, crtc, encoder)
3601 if (encoder->pre_pll_enable)
3602 encoder->pre_pll_enable(encoder);
3603
3604 intel_enable_pll(dev_priv, pipe);
3605
3606 for_each_encoder_on_crtc(dev, crtc, encoder)
3607 if (encoder->pre_enable)
3608 encoder->pre_enable(encoder);
3609
3610 /* VLV wants encoder enabling _before_ the pipe is up. */
3611 for_each_encoder_on_crtc(dev, crtc, encoder)
3612 encoder->enable(encoder);
3613
2dd24552
JB		 3614 /* Enable panel fitting for eDP */
3615 i9xx_pfit_enable(intel_crtc);
3616
63cbb074
VS		 3617 intel_crtc_load_lut(crtc);
3618
89b667f8
JB		 3619 intel_enable_pipe(dev_priv, pipe, false);
3620 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3621 intel_enable_planes(crtc);
5c38d48c 3622 intel_crtc_update_cursor(crtc, true);
89b667f8 3623
f440eb13
VS		 3624 intel_update_fbc(dev);
3625
89b667f8
JB		 3626 mutex_unlock(&dev_priv->dpio_lock);
3627}
3628
0b8765c6 3629static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3630{
3631 struct drm_device *dev = crtc->dev;
79e53945
JB		 3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3634 struct intel_encoder *encoder;
79e53945 3635 int pipe = intel_crtc->pipe;
80824003 3636 int plane = intel_crtc->plane;
79e53945 3637
08a48469
DV		 3638 WARN_ON(!crtc->enabled);
3639
f7abfe8b
CW		 3640 if (intel_crtc->active)
3641 return;
3642
3643 intel_crtc->active = true;
6b383a7f
CW		 3644 intel_update_watermarks(dev);
3645
63d7bbe9 3646 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3647
3648 for_each_encoder_on_crtc(dev, crtc, encoder)
3649 if (encoder->pre_enable)
3650 encoder->pre_enable(encoder);
3651
2dd24552
JB		 3652 /* Enable panel fitting for LVDS */
3653 i9xx_pfit_enable(intel_crtc);
3654
63cbb074
VS		 3655 intel_crtc_load_lut(crtc);
3656
040484af 3657 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3658 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3659 intel_enable_planes(crtc);
22e407d7 3660 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3661 if (IS_G4X(dev))
3662 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3663 intel_crtc_update_cursor(crtc, true);
79e53945 3664
0b8765c6
JB		 3665 /* Give the overlay scaler a chance to enable if it's on this pipe */
3666 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3667
f440eb13
VS		 3668 intel_update_fbc(dev);
3669
fa5c73b1
DV		 3670 for_each_encoder_on_crtc(dev, crtc, encoder)
3671 encoder->enable(encoder);
0b8765c6 3672}
79e53945 3673
87476d63
DV		 3674static void i9xx_pfit_disable(struct intel_crtc *crtc)
3675{
3676 struct drm_device *dev = crtc->base.dev;
3677 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3678
328d8e82
DV		 3679 if (!crtc->config.gmch_pfit.control)
3680 return;
87476d63 3681
328d8e82 3682 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3683
328d8e82
DV		 3684 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3685 I915_READ(PFIT_CONTROL));
3686 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3687}
3688
0b8765c6
JB		 3689static void i9xx_crtc_disable(struct drm_crtc *crtc)
3690{
3691 struct drm_device *dev = crtc->dev;
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3694 struct intel_encoder *encoder;
0b8765c6
JB		 3695 int pipe = intel_crtc->pipe;
3696 int plane = intel_crtc->plane;
ef9c3aee 3697
f7abfe8b
CW		 3698 if (!intel_crtc->active)
3699 return;
3700
ea9d758d
DV		 3701 for_each_encoder_on_crtc(dev, crtc, encoder)
3702 encoder->disable(encoder);
3703
0b8765c6 3704 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3705 intel_crtc_wait_for_pending_flips(crtc);
3706 drm_vblank_off(dev, pipe);
0b8765c6 3707
973d04f9
CW		 3708 if (dev_priv->cfb_plane == plane)
3709 intel_disable_fbc(dev);
79e53945 3710
0d5b8c61
VS		 3711 intel_crtc_dpms_overlay(intel_crtc, false);
3712 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3713 intel_disable_planes(crtc);
b24e7179 3714 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3715
b24e7179 3716 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3717
87476d63 3718 i9xx_pfit_disable(intel_crtc);
24a1f16d 3719
89b667f8
JB		 3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->post_disable)
3722 encoder->post_disable(encoder);
3723
63d7bbe9 3724 intel_disable_pll(dev_priv, pipe);
0b8765c6 3725
f7abfe8b 3726 intel_crtc->active = false;
6b383a7f
CW		 3727 intel_update_fbc(dev);
3728 intel_update_watermarks(dev);
0b8765c6
JB		 3729}
3730
ee7b9f93
JB		 3731static void i9xx_crtc_off(struct drm_crtc *crtc)
3732{
3733}
3734
976f8a20
DV		 3735static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736 bool enabled)
2c07245f
ZW		 3737{
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_master_private *master_priv;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
79e53945
JB		 3742
3743 if (!dev->primary->master)
3744 return;
3745
3746 master_priv = dev->primary->master->driver_priv;
3747 if (!master_priv->sarea_priv)
3748 return;
3749
79e53945
JB		 3750 switch (pipe) {
3751 case 0:
3752 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 case 1:
3756 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758 break;
3759 default:
9db4a9c7 3760 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3761 break;
3762 }
79e53945
JB		 3763}
3764
976f8a20
DV		 3765/**
3766 * Sets the power management mode of the pipe and plane.
3767 */
3768void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_encoder *intel_encoder;
3773 bool enable = false;
3774
3775 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776 enable |= intel_encoder->connectors_active;
3777
3778 if (enable)
3779 dev_priv->display.crtc_enable(crtc);
3780 else
3781 dev_priv->display.crtc_disable(crtc);
3782
3783 intel_crtc_update_sarea(crtc, enable);
3784}
3785
cdd59983
CW		 3786static void intel_crtc_disable(struct drm_crtc *crtc)
3787{
cdd59983 3788 struct drm_device *dev = crtc->dev;
976f8a20 3789 struct drm_connector *connector;
ee7b9f93 3790 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3792
976f8a20
DV		 3793 /* crtc should still be enabled when we disable it. */
3794 WARN_ON(!crtc->enabled);
3795
3796 dev_priv->display.crtc_disable(crtc);
c77bf565 3797 intel_crtc->eld_vld = false;
976f8a20 3798 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3799 dev_priv->display.off(crtc);
3800
931872fc
CW		 3801 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3803
3804 if (crtc->fb) {
3805 mutex_lock(&dev->struct_mutex);
1690e1eb 3806 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3807 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3808 crtc->fb = NULL;
3809 }
3810
3811 /* Update computed state. */
3812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813 if (!connector->encoder || !connector->encoder->crtc)
3814 continue;
3815
3816 if (connector->encoder->crtc != crtc)
3817 continue;
3818
3819 connector->dpms = DRM_MODE_DPMS_OFF;
3820 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3821 }
3822}
3823
a261b246 3824void intel_modeset_disable(struct drm_device *dev)
79e53945 3825{
a261b246
DV		 3826 struct drm_crtc *crtc;
3827
3828 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829 if (crtc->enabled)
3830 intel_crtc_disable(crtc);
3831 }
79e53945
JB		 3832}
3833
ea5b213a 3834void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3835{
4ef69c7a 3836 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3837
ea5b213a
CW		 3838 drm_encoder_cleanup(encoder);
3839 kfree(intel_encoder);
7e7d76c3
JB		 3840}
3841
5ab432ef
DV		 3842/* Simple dpms helper for encodres with just one connector, no cloning and only
3843 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844 * state of the entire output pipe. */
3845void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3846{
5ab432ef
DV		 3847 if (mode == DRM_MODE_DPMS_ON) {
3848 encoder->connectors_active = true;
3849
b2cabb0e 3850 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3851 } else {
3852 encoder->connectors_active = false;
3853
b2cabb0e 3854 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3855 }
79e53945
JB		 3856}
3857
0a91ca29
DV		 3858/* Cross check the actual hw state with our own modeset state tracking (and it's
3859 * internal consistency). */
b980514c 3860static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3861{
0a91ca29
DV		 3862 if (connector->get_hw_state(connector)) {
3863 struct intel_encoder *encoder = connector->encoder;
3864 struct drm_crtc *crtc;
3865 bool encoder_enabled;
3866 enum pipe pipe;
3867
3868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869 connector->base.base.id,
3870 drm_get_connector_name(&connector->base));
3871
3872 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873 "wrong connector dpms state\n");
3874 WARN(connector->base.encoder != &encoder->base,
3875 "active connector not linked to encoder\n");
3876 WARN(!encoder->connectors_active,
3877 "encoder->connectors_active not set\n");
3878
3879 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880 WARN(!encoder_enabled, "encoder not enabled\n");
3881 if (WARN_ON(!encoder->base.crtc))
3882 return;
3883
3884 crtc = encoder->base.crtc;
3885
3886 WARN(!crtc->enabled, "crtc not enabled\n");
3887 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889 "encoder active on the wrong pipe\n");
3890 }
79e53945
JB		 3891}
3892
5ab432ef
DV		 3893/* Even simpler default implementation, if there's really no special case to
3894 * consider. */
3895void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3896{
5ab432ef 3897 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3898
5ab432ef
DV		 3899 /* All the simple cases only support two dpms states. */
3900 if (mode != DRM_MODE_DPMS_ON)
3901 mode = DRM_MODE_DPMS_OFF;
d4270e57 3902
5ab432ef
DV		 3903 if (mode == connector->dpms)
3904 return;
3905
3906 connector->dpms = mode;
3907
3908 /* Only need to change hw state when actually enabled */
3909 if (encoder->base.crtc)
3910 intel_encoder_dpms(encoder, mode);
3911 else
8af6cf88 3912 WARN_ON(encoder->connectors_active != false);
0a91ca29 3913
b980514c 3914 intel_modeset_check_state(connector->dev);
79e53945
JB		 3915}
3916
f0947c37
DV		 3917/* Simple connector->get_hw_state implementation for encoders that support only
3918 * one connector and no cloning and hence the encoder state determines the state
3919 * of the connector. */
3920bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3921{
24929352 3922 enum pipe pipe = 0;
f0947c37 3923 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3924
f0947c37 3925 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3926}
3927
1857e1da
DV		 3928static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929 struct intel_crtc_config *pipe_config)
3930{
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932 struct intel_crtc *pipe_B_crtc =
3933 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 if (pipe_config->fdi_lanes > 4) {
3938 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939 pipe_name(pipe), pipe_config->fdi_lanes);
3940 return false;
3941 }
3942
3943 if (IS_HASWELL(dev)) {
3944 if (pipe_config->fdi_lanes > 2) {
3945 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946 pipe_config->fdi_lanes);
3947 return false;
3948 } else {
3949 return true;
3950 }
3951 }
3952
3953 if (INTEL_INFO(dev)->num_pipes == 2)
3954 return true;
3955
3956 /* Ivybridge 3 pipe is really complicated */
3957 switch (pipe) {
3958 case PIPE_A:
3959 return true;
3960 case PIPE_B:
3961 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962 pipe_config->fdi_lanes > 2) {
3963 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964 pipe_name(pipe), pipe_config->fdi_lanes);
3965 return false;
3966 }
3967 return true;
3968 case PIPE_C:
1e833f40 3969 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3970 pipe_B_crtc->config.fdi_lanes <= 2) {
3971 if (pipe_config->fdi_lanes > 2) {
3972 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3974 return false;
3975 }
3976 } else {
3977 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978 return false;
3979 }
3980 return true;
3981 default:
3982 BUG();
3983 }
3984}
3985
e29c22c0
DV		 3986#define RETRY 1
3987static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988 struct intel_crtc_config *pipe_config)
877d48d5 3989{
1857e1da 3990 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3991 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 3992 int lane, link_bw, fdi_dotclock;
e29c22c0 3993 bool setup_ok, needs_recompute = false;
877d48d5 3994
e29c22c0 3995retry:
877d48d5
DV		 3996 /* FDI is a binary signal running at ~2.7GHz, encoding
3997 * each output octet as 10 bits. The actual frequency
3998 * is stored as a divider into a 100MHz clock, and the
3999 * mode pixel clock is stored in units of 1KHz.
4000 * Hence the bw of each lane in terms of the mode signal
4001 * is:
4002 */
4003 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
ff9a6750 4005 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4006 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4007
4008 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4009 pipe_config->pipe_bpp);
4010
4011 pipe_config->fdi_lanes = lane;
4012
2bd89a07 4013 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4014 link_bw, &pipe_config->fdi_m_n);
1857e1da 4015
e29c22c0
DV		 4016 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4017 intel_crtc->pipe, pipe_config);
4018 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4019 pipe_config->pipe_bpp -= 2*3;
4020 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4021 pipe_config->pipe_bpp);
4022 needs_recompute = true;
4023 pipe_config->bw_constrained = true;
4024
4025 goto retry;
4026 }
4027
4028 if (needs_recompute)
4029 return RETRY;
4030
4031 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4032}
4033
42db64ef
PZ		 4034static void hsw_compute_ips_config(struct intel_crtc *crtc,
4035 struct intel_crtc_config *pipe_config)
4036{
3c4ca58c
PZ		 4037 pipe_config->ips_enabled = i915_enable_ips &&
4038 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4039 pipe_config->pipe_bpp == 24;
4040}
4041
a43f6e0f 4042static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4043 struct intel_crtc_config *pipe_config)
79e53945 4044{
a43f6e0f 4045 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4046 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4047
bad720ff 4048 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4049 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4050 if (pipe_config->requested_mode.clock * 3
4051 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4052 return -EINVAL;
2c07245f 4053 }
89749350 4054
f9bef081
DV		 4055 /* All interlaced capable intel hw wants timings in frames. Note though
4056 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4057 * timings, so we need to be careful not to clobber these.*/
7ae89233 4058 if (!pipe_config->timings_set)
f9bef081 4059 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4060
8693a824
DL		 4061 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4062 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4063 */
4064 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4065 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4066 return -EINVAL;
44f46b42 4067
bd080ee5 4068 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4069 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4070 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4071 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4072 * for lvds. */
4073 pipe_config->pipe_bpp = 8*3;
4074 }
4075
42db64ef 4076 if (IS_HASWELL(dev))
a43f6e0f
DV		 4077 hsw_compute_ips_config(crtc, pipe_config);
4078
4079 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4080 * clock survives for now. */
4081 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4082 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4083
877d48d5 4084 if (pipe_config->has_pch_encoder)
a43f6e0f 4085 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4086
e29c22c0 4087 return 0;
79e53945
JB		 4088}
4089
25eb05fc
JB		 4090static int valleyview_get_display_clock_speed(struct drm_device *dev)
4091{
4092 return 400000; /* FIXME */
4093}
4094
e70236a8
JB		 4095static int i945_get_display_clock_speed(struct drm_device *dev)
4096{
4097 return 400000;
4098}
79e53945 4099
e70236a8 4100static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4101{
e70236a8
JB		 4102 return 333000;
4103}
79e53945 4104
e70236a8
JB		 4105static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4106{
4107 return 200000;
4108}
79e53945 4109
e70236a8
JB		 4110static int i915gm_get_display_clock_speed(struct drm_device *dev)
4111{
4112 u16 gcfgc = 0;
79e53945 4113
e70236a8
JB		 4114 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4115
4116 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4117 return 133000;
4118 else {
4119 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4120 case GC_DISPLAY_CLOCK_333_MHZ:
4121 return 333000;
4122 default:
4123 case GC_DISPLAY_CLOCK_190_200_MHZ:
4124 return 190000;
79e53945 4125 }
e70236a8
JB		 4126 }
4127}
4128
4129static int i865_get_display_clock_speed(struct drm_device *dev)
4130{
4131 return 266000;
4132}
4133
4134static int i855_get_display_clock_speed(struct drm_device *dev)
4135{
4136 u16 hpllcc = 0;
4137 /* Assume that the hardware is in the high speed state. This
4138 * should be the default.
4139 */
4140 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4141 case GC_CLOCK_133_200:
4142 case GC_CLOCK_100_200:
4143 return 200000;
4144 case GC_CLOCK_166_250:
4145 return 250000;
4146 case GC_CLOCK_100_133:
79e53945 4147 return 133000;
e70236a8 4148 }
79e53945 4149
e70236a8
JB		 4150 /* Shouldn't happen */
4151 return 0;
4152}
79e53945 4153
e70236a8
JB		 4154static int i830_get_display_clock_speed(struct drm_device *dev)
4155{
4156 return 133000;
79e53945
JB		 4157}
4158
2c07245f 4159static void
a65851af 4160intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4161{
a65851af
VS		 4162 while (*num > DATA_LINK_M_N_MASK ||
4163 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4164 *num >>= 1;
4165 *den >>= 1;
4166 }
4167}
4168
a65851af
VS		 4169static void compute_m_n(unsigned int m, unsigned int n,
4170 uint32_t *ret_m, uint32_t *ret_n)
4171{
4172 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4173 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4174 intel_reduce_m_n_ratio(ret_m, ret_n);
4175}
4176
e69d0bc1
DV		 4177void
4178intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4179 int pixel_clock, int link_clock,
4180 struct intel_link_m_n *m_n)
2c07245f 4181{
e69d0bc1 4182 m_n->tu = 64;
a65851af
VS		 4183
4184 compute_m_n(bits_per_pixel * pixel_clock,
4185 link_clock * nlanes * 8,
4186 &m_n->gmch_m, &m_n->gmch_n);
4187
4188 compute_m_n(pixel_clock, link_clock,
4189 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4190}
4191
a7615030
CW		 4192static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4193{
72bbe58c
KP		 4194 if (i915_panel_use_ssc >= 0)
4195 return i915_panel_use_ssc != 0;
41aa3448 4196 return dev_priv->vbt.lvds_use_ssc
435793df 4197 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4198}
4199
a0c4da24
JB		 4200static int vlv_get_refclk(struct drm_crtc *crtc)
4201{
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 int refclk = 27000; /* for DP & HDMI */
4205
4206 return 100000; /* only one validated so far */
4207
4208 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4209 refclk = 96000;
4210 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4211 if (intel_panel_use_ssc(dev_priv))
4212 refclk = 100000;
4213 else
4214 refclk = 96000;
4215 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4216 refclk = 100000;
4217 }
4218
4219 return refclk;
4220}
4221
c65d77d8
JB		 4222static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4223{
4224 struct drm_device *dev = crtc->dev;
4225 struct drm_i915_private *dev_priv = dev->dev_private;
4226 int refclk;
4227
a0c4da24
JB		 4228 if (IS_VALLEYVIEW(dev)) {
4229 refclk = vlv_get_refclk(crtc);
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4231 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4232 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4233 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4234 refclk / 1000);
4235 } else if (!IS_GEN2(dev)) {
4236 refclk = 96000;
4237 } else {
4238 refclk = 48000;
4239 }
4240
4241 return refclk;
4242}
4243
7429e9d4
DV		 4244static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4245{
7df00d7a 4246 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4
DV		 4247}
4248
4249static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4250{
4251 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4252}
4253
f47709a9 4254static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4255 intel_clock_t *reduced_clock)
4256{
f47709a9 4257 struct drm_device *dev = crtc->base.dev;
a7516a05 4258 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4259 int pipe = crtc->pipe;
a7516a05
JB		 4260 u32 fp, fp2 = 0;
4261
4262 if (IS_PINEVIEW(dev)) {
7429e9d4 4263 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4264 if (reduced_clock)
7429e9d4 4265 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4266 } else {
7429e9d4 4267 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4268 if (reduced_clock)
7429e9d4 4269 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4270 }
4271
4272 I915_WRITE(FP0(pipe), fp);
4273
f47709a9
DV		 4274 crtc->lowfreq_avail = false;
4275 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4276 reduced_clock && i915_powersave) {
4277 I915_WRITE(FP1(pipe), fp2);
f47709a9 4278 crtc->lowfreq_avail = true;
a7516a05
JB		 4279 } else {
4280 I915_WRITE(FP1(pipe), fp);
4281 }
4282}
4283
89b667f8
JB		 4284static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4285{
4286 u32 reg_val;
4287
4288 /*
4289 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4290 * and set it to a reasonable value instead.
4291 */
ae99258f 4292 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4293 reg_val &= 0xffffff00;
4294 reg_val |= 0x00000030;
ae99258f 4295 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4296
ae99258f 4297 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4298 reg_val &= 0x8cffffff;
4299 reg_val = 0x8c000000;
ae99258f 4300 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4301
ae99258f 4302 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4303 reg_val &= 0xffffff00;
ae99258f 4304 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4305
ae99258f 4306 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4307 reg_val &= 0x00ffffff;
4308 reg_val |= 0xb0000000;
ae99258f 4309 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4310}
4311
b551842d
DV		 4312static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4313 struct intel_link_m_n *m_n)
4314{
4315 struct drm_device *dev = crtc->base.dev;
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 int pipe = crtc->pipe;
4318
e3b95f1e
DV		 4319 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4320 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4321 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4322 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4323}
4324
4325static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4326 struct intel_link_m_n *m_n)
4327{
4328 struct drm_device *dev = crtc->base.dev;
4329 struct drm_i915_private *dev_priv = dev->dev_private;
4330 int pipe = crtc->pipe;
4331 enum transcoder transcoder = crtc->config.cpu_transcoder;
4332
4333 if (INTEL_INFO(dev)->gen >= 5) {
4334 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4335 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4336 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4337 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4338 } else {
e3b95f1e
DV		 4339 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4340 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4341 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4342 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4343 }
4344}
4345
03afc4a2
DV		 4346static void intel_dp_set_m_n(struct intel_crtc *crtc)
4347{
4348 if (crtc->config.has_pch_encoder)
4349 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4350 else
4351 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4352}
4353
f47709a9 4354static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4355{
f47709a9 4356 struct drm_device *dev = crtc->base.dev;
a0c4da24 4357 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4358 struct intel_encoder *encoder;
f47709a9 4359 int pipe = crtc->pipe;
89b667f8 4360 u32 dpll, mdiv;
a0c4da24 4361 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4362 bool is_hdmi;
198a037f 4363 u32 coreclk, reg_val, dpll_md;
a0c4da24 4364
09153000
DV		 4365 mutex_lock(&dev_priv->dpio_lock);
4366
89b667f8 4367 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4368
f47709a9
DV		 4369 bestn = crtc->config.dpll.n;
4370 bestm1 = crtc->config.dpll.m1;
4371 bestm2 = crtc->config.dpll.m2;
4372 bestp1 = crtc->config.dpll.p1;
4373 bestp2 = crtc->config.dpll.p2;
a0c4da24 4374
89b667f8
JB		 4375 /* See eDP HDMI DPIO driver vbios notes doc */
4376
4377 /* PLL B needs special handling */
4378 if (pipe)
4379 vlv_pllb_recal_opamp(dev_priv);
4380
4381 /* Set up Tx target for periodic Rcomp update */
ae99258f 4382 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4383
4384 /* Disable target IRef on PLL */
ae99258f 4385 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4386 reg_val &= 0x00ffffff;
ae99258f 4387 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4388
4389 /* Disable fast lock */
ae99258f 4390 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4391
4392 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4393 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4394 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4395 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4396 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4397
4398 /*
4399 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4400 * but we don't support that).
4401 * Note: don't use the DAC post divider as it seems unstable.
4402 */
4403 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4404 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4405
89b667f8 4406 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4407 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4408
89b667f8 4409 /* Set HBR and RBR LPF coefficients */
ff9a6750 4410 if (crtc->config.port_clock == 162000 ||
89b667f8 4411 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4412 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4413 0x005f0021);
4414 else
ae99258f 4415 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4416 0x00d0000f);
4417
4418 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4419 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4420 /* Use SSC source */
4421 if (!pipe)
ae99258f 4422 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4423 0x0df40000);
4424 else
ae99258f 4425 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4426 0x0df70000);
4427 } else { /* HDMI or VGA */
4428 /* Use bend source */
4429 if (!pipe)
ae99258f 4430 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4431 0x0df70000);
4432 else
ae99258f 4433 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4434 0x0df40000);
4435 }
a0c4da24 4436
ae99258f 4437 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4438 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4439 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4440 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4441 coreclk |= 0x01000000;
ae99258f 4442 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4443
ae99258f 4444 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4445
89b667f8
JB		 4446 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4447 if (encoder->pre_pll_enable)
4448 encoder->pre_pll_enable(encoder);
2a8f64ca 4449
89b667f8
JB		 4450 /* Enable DPIO clock input */
4451 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4452 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4453 if (pipe)
4454 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4455
89b667f8 4456 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4457 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4458 POSTING_READ(DPLL(pipe));
4459 udelay(150);
a0c4da24 4460
89b667f8
JB		 4461 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4462 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4463
ef1b460d
DV		 4464 dpll_md = (crtc->config.pixel_multiplier - 1)
4465 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4466 I915_WRITE(DPLL_MD(pipe), dpll_md);
4467 POSTING_READ(DPLL_MD(pipe));
f47709a9 4468
89b667f8
JB		 4469 if (crtc->config.has_dp_encoder)
4470 intel_dp_set_m_n(crtc);
09153000
DV		 4471
4472 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4473}
4474
f47709a9
DV		 4475static void i9xx_update_pll(struct intel_crtc *crtc,
4476 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4477 int num_connectors)
4478{
f47709a9 4479 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4480 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4481 struct intel_encoder *encoder;
f47709a9 4482 int pipe = crtc->pipe;
eb1cbe48
DV		 4483 u32 dpll;
4484 bool is_sdvo;
f47709a9 4485 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4486
f47709a9 4487 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4488
f47709a9
DV		 4489 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4490 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4491
4492 dpll = DPLL_VGA_MODE_DIS;
4493
f47709a9 4494 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4495 dpll |= DPLLB_MODE_LVDS;
4496 else
4497 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4498
ef1b460d 4499 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4500 dpll |= (crtc->config.pixel_multiplier - 1)
4501 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4502 }
198a037f
DV		 4503
4504 if (is_sdvo)
4505 dpll |= DPLL_DVO_HIGH_SPEED;
4506
f47709a9 4507 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4508 dpll |= DPLL_DVO_HIGH_SPEED;
4509
4510 /* compute bitmask from p1 value */
4511 if (IS_PINEVIEW(dev))
4512 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4513 else {
4514 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4515 if (IS_G4X(dev) && reduced_clock)
4516 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4517 }
4518 switch (clock->p2) {
4519 case 5:
4520 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4521 break;
4522 case 7:
4523 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4524 break;
4525 case 10:
4526 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4527 break;
4528 case 14:
4529 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4530 break;
4531 }
4532 if (INTEL_INFO(dev)->gen >= 4)
4533 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4534
09ede541 4535 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4536 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4537 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4538 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4539 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4540 else
4541 dpll |= PLL_REF_INPUT_DREFCLK;
4542
4543 dpll |= DPLL_VCO_ENABLE;
4544 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4545 POSTING_READ(DPLL(pipe));
4546 udelay(150);
4547
f47709a9 4548 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4549 if (encoder->pre_pll_enable)
4550 encoder->pre_pll_enable(encoder);
eb1cbe48 4551
f47709a9
DV		 4552 if (crtc->config.has_dp_encoder)
4553 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4554
4555 I915_WRITE(DPLL(pipe), dpll);
4556
4557 /* Wait for the clocks to stabilize. */
4558 POSTING_READ(DPLL(pipe));
4559 udelay(150);
4560
4561 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4562 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4563 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4564 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4565 } else {
4566 /* The pixel multiplier can only be updated once the
4567 * DPLL is enabled and the clocks are stable.
4568 *
4569 * So write it again.
4570 */
4571 I915_WRITE(DPLL(pipe), dpll);
4572 }
4573}
4574
f47709a9 4575static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4576 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4577 int num_connectors)
4578{
f47709a9 4579 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4580 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4581 struct intel_encoder *encoder;
f47709a9 4582 int pipe = crtc->pipe;
eb1cbe48 4583 u32 dpll;
f47709a9 4584 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4585
f47709a9 4586 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4587
eb1cbe48
DV		 4588 dpll = DPLL_VGA_MODE_DIS;
4589
f47709a9 4590 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592 } else {
4593 if (clock->p1 == 2)
4594 dpll |= PLL_P1_DIVIDE_BY_TWO;
4595 else
4596 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 if (clock->p2 == 4)
4598 dpll |= PLL_P2_DIVIDE_BY_4;
4599 }
4600
f47709a9 4601 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4602 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604 else
4605 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607 dpll |= DPLL_VCO_ENABLE;
4608 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4609 POSTING_READ(DPLL(pipe));
4610 udelay(150);
4611
f47709a9 4612 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4613 if (encoder->pre_pll_enable)
4614 encoder->pre_pll_enable(encoder);
eb1cbe48 4615
5b5896e4
DV		 4616 I915_WRITE(DPLL(pipe), dpll);
4617
4618 /* Wait for the clocks to stabilize. */
4619 POSTING_READ(DPLL(pipe));
4620 udelay(150);
4621
eb1cbe48
DV		 4622 /* The pixel multiplier can only be updated once the
4623 * DPLL is enabled and the clocks are stable.
4624 *
4625 * So write it again.
4626 */
4627 I915_WRITE(DPLL(pipe), dpll);
4628}
4629
8a654f3b 4630static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4631{
4632 struct drm_device *dev = intel_crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4635 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4636 struct drm_display_mode *adjusted_mode =
4637 &intel_crtc->config.adjusted_mode;
4638 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4639 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4640
4641 /* We need to be careful not to changed the adjusted mode, for otherwise
4642 * the hw state checker will get angry at the mismatch. */
4643 crtc_vtotal = adjusted_mode->crtc_vtotal;
4644 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4645
4646 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4648 crtc_vtotal -= 1;
4649 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4650 vsyncshift = adjusted_mode->crtc_hsync_start
4651 - adjusted_mode->crtc_htotal / 2;
4652 } else {
4653 vsyncshift = 0;
4654 }
4655
4656 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4657 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4658
fe2b8f9d 4659 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4660 (adjusted_mode->crtc_hdisplay - 1) |
4661 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4662 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_hblank_start - 1) |
4664 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4665 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4666 (adjusted_mode->crtc_hsync_start - 1) |
4667 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
fe2b8f9d 4669 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4670 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4671 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4672 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4673 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4674 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4675 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4676 (adjusted_mode->crtc_vsync_start - 1) |
4677 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
b5e508d4
PZ		 4679 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682 * bits. */
4683 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684 (pipe == PIPE_B || pipe == PIPE_C))
4685 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686
b0e77b9c
PZ		 4687 /* pipesrc controls the size that is scaled from, which should
4688 * always be the user's requested size.
4689 */
4690 I915_WRITE(PIPESRC(pipe),
4691 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4692}
4693
1bd1bd80
DV		 4694static void intel_get_pipe_timings(struct intel_crtc *crtc,
4695 struct intel_crtc_config *pipe_config)
4696{
4697 struct drm_device *dev = crtc->base.dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4700 uint32_t tmp;
4701
4702 tmp = I915_READ(HTOTAL(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HBLANK(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4708 tmp = I915_READ(HSYNC(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4711
4712 tmp = I915_READ(VTOTAL(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VBLANK(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4718 tmp = I915_READ(VSYNC(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4723 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4724 pipe_config->adjusted_mode.crtc_vtotal += 1;
4725 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4726 }
4727
4728 tmp = I915_READ(PIPESRC(crtc->pipe));
4729 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4730 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4731}
4732
84b046f3
DV		 4733static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4734{
4735 struct drm_device *dev = intel_crtc->base.dev;
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737 uint32_t pipeconf;
4738
4739 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4740
4741 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4742 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4743 * core speed.
4744 *
4745 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4746 * pipe == 0 check?
4747 */
4748 if (intel_crtc->config.requested_mode.clock >
4749 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4750 pipeconf |= PIPECONF_DOUBLE_WIDE;
4751 else
4752 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4753 }
4754
ff9ce46e
DV		 4755 /* only g4x and later have fancy bpc/dither controls */
4756 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4757 pipeconf &= ~(PIPECONF_BPC_MASK |
4758 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4759
4760 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4761 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4762 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4763 PIPECONF_DITHER_TYPE_SP;
84b046f3 4764
ff9ce46e
DV		 4765 switch (intel_crtc->config.pipe_bpp) {
4766 case 18:
4767 pipeconf |= PIPECONF_6BPC;
4768 break;
4769 case 24:
4770 pipeconf |= PIPECONF_8BPC;
4771 break;
4772 case 30:
4773 pipeconf |= PIPECONF_10BPC;
4774 break;
4775 default:
4776 /* Case prevented by intel_choose_pipe_bpp_dither. */
4777 BUG();
84b046f3
DV		 4778 }
4779 }
4780
4781 if (HAS_PIPE_CXSR(dev)) {
4782 if (intel_crtc->lowfreq_avail) {
4783 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4784 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4785 } else {
4786 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4787 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4788 }
4789 }
4790
4791 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4792 if (!IS_GEN2(dev) &&
4793 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4794 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4795 else
4796 pipeconf |= PIPECONF_PROGRESSIVE;
4797
9c8e09b7
VS		 4798 if (IS_VALLEYVIEW(dev)) {
4799 if (intel_crtc->config.limited_color_range)
4800 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4801 else
4802 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4803 }
4804
84b046f3
DV		 4805 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4806 POSTING_READ(PIPECONF(intel_crtc->pipe));
4807}
4808
f564048e 4809static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4810 int x, int y,
94352cf9 4811 struct drm_framebuffer *fb)
79e53945
JB		 4812{
4813 struct drm_device *dev = crtc->dev;
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4816 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4817 int pipe = intel_crtc->pipe;
80824003 4818 int plane = intel_crtc->plane;
c751ce4f 4819 int refclk, num_connectors = 0;
652c393a 4820 intel_clock_t clock, reduced_clock;
84b046f3 4821 u32 dspcntr;
a16af721
DV		 4822 bool ok, has_reduced_clock = false;
4823 bool is_lvds = false;
5eddb70b 4824 struct intel_encoder *encoder;
d4906093 4825 const intel_limit_t *limit;
5c3b82e2 4826 int ret;
79e53945 4827
6c2b7c12 4828 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4829 switch (encoder->type) {
79e53945
JB		 4830 case INTEL_OUTPUT_LVDS:
4831 is_lvds = true;
4832 break;
79e53945 4833 }
43565a06 4834
c751ce4f 4835 num_connectors++;
79e53945
JB		 4836 }
4837
c65d77d8 4838 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4839
d4906093
ML		 4840 /*
4841 * Returns a set of divisors for the desired target clock with the given
4842 * refclk, or FALSE. The returned values represent the clock equation:
4843 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4844 */
1b894b59 4845 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4846 ok = dev_priv->display.find_dpll(limit, crtc,
4847 intel_crtc->config.port_clock,
ee9300bb
DV		 4848 refclk, NULL, &clock);
4849 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4850 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4851 return -EINVAL;
79e53945
JB		 4852 }
4853
cda4b7d3 4854 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4855 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4856
ddc9003c 4857 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4858 /*
4859 * Ensure we match the reduced clock's P to the target clock.
4860 * If the clocks don't match, we can't switch the display clock
4861 * by using the FP0/FP1. In such case we will disable the LVDS
4862 * downclock feature.
4863 */
ee9300bb
DV		 4864 has_reduced_clock =
4865 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4866 dev_priv->lvds_downclock,
ee9300bb 4867 refclk, &clock,
5eddb70b 4868 &reduced_clock);
7026d4ac 4869 }
f47709a9
DV		 4870 /* Compat-code for transition, will disappear. */
4871 if (!intel_crtc->config.clock_set) {
4872 intel_crtc->config.dpll.n = clock.n;
4873 intel_crtc->config.dpll.m1 = clock.m1;
4874 intel_crtc->config.dpll.m2 = clock.m2;
4875 intel_crtc->config.dpll.p1 = clock.p1;
4876 intel_crtc->config.dpll.p2 = clock.p2;
4877 }
7026d4ac 4878
eb1cbe48 4879 if (IS_GEN2(dev))
8a654f3b 4880 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4881 has_reduced_clock ? &reduced_clock : NULL,
4882 num_connectors);
a0c4da24 4883 else if (IS_VALLEYVIEW(dev))
f47709a9 4884 vlv_update_pll(intel_crtc);
79e53945 4885 else
f47709a9 4886 i9xx_update_pll(intel_crtc,
eb1cbe48 4887 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4888 num_connectors);
79e53945 4889
79e53945
JB		 4890 /* Set up the display plane register */
4891 dspcntr = DISPPLANE_GAMMA_ENABLE;
4892
da6ecc5d
JB		 4893 if (!IS_VALLEYVIEW(dev)) {
4894 if (pipe == 0)
4895 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4896 else
4897 dspcntr |= DISPPLANE_SEL_PIPE_B;
4898 }
79e53945 4899
8a654f3b 4900 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4901
4902 /* pipesrc and dspsize control the size that is scaled from,
4903 * which should always be the user's requested size.
79e53945 4904 */
929c77fb
EA		 4905 I915_WRITE(DSPSIZE(plane),
4906 ((mode->vdisplay - 1) << 16) |
4907 (mode->hdisplay - 1));
4908 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4909
84b046f3
DV		 4910 i9xx_set_pipeconf(intel_crtc);
4911
f564048e
EA		 4912 I915_WRITE(DSPCNTR(plane), dspcntr);
4913 POSTING_READ(DSPCNTR(plane));
4914
94352cf9 4915 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4916
4917 intel_update_watermarks(dev);
4918
f564048e
EA		 4919 return ret;
4920}
4921
2fa2fe9a
DV		 4922static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4923 struct intel_crtc_config *pipe_config)
4924{
4925 struct drm_device *dev = crtc->base.dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 uint32_t tmp;
4928
4929 tmp = I915_READ(PFIT_CONTROL);
4930
4931 if (INTEL_INFO(dev)->gen < 4) {
4932 if (crtc->pipe != PIPE_B)
4933 return;
4934
4935 /* gen2/3 store dither state in pfit control, needs to match */
4936 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4937 } else {
4938 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4939 return;
4940 }
4941
4942 if (!(tmp & PFIT_ENABLE))
4943 return;
4944
4945 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4946 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4947 if (INTEL_INFO(dev)->gen < 5)
4948 pipe_config->gmch_pfit.lvds_border_bits =
4949 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4950}
4951
0e8ffe1b
DV		 4952static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4953 struct intel_crtc_config *pipe_config)
4954{
4955 struct drm_device *dev = crtc->base.dev;
4956 struct drm_i915_private *dev_priv = dev->dev_private;
4957 uint32_t tmp;
4958
eccb140b 4959 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4960 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4961
0e8ffe1b
DV		 4962 tmp = I915_READ(PIPECONF(crtc->pipe));
4963 if (!(tmp & PIPECONF_ENABLE))
4964 return false;
4965
1bd1bd80
DV		 4966 intel_get_pipe_timings(crtc, pipe_config);
4967
2fa2fe9a
DV		 4968 i9xx_get_pfit_config(crtc, pipe_config);
4969
6c49f241
DV		 4970 if (INTEL_INFO(dev)->gen >= 4) {
4971 tmp = I915_READ(DPLL_MD(crtc->pipe));
4972 pipe_config->pixel_multiplier =
4973 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4974 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4975 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4976 tmp = I915_READ(DPLL(crtc->pipe));
4977 pipe_config->pixel_multiplier =
4978 ((tmp & SDVO_MULTIPLIER_MASK)
4979 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4980 } else {
4981 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4982 * port and will be fixed up in the encoder->get_config
4983 * function. */
4984 pipe_config->pixel_multiplier = 1;
4985 }
4986
0e8ffe1b
DV		 4987 return true;
4988}
4989
dde86e2d 4990static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4991{
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4994 struct intel_encoder *encoder;
74cfd7ac 4995 u32 val, final;
13d83a67 4996 bool has_lvds = false;
199e5d79 4997 bool has_cpu_edp = false;
199e5d79 4998 bool has_panel = false;
99eb6a01
KP		 4999 bool has_ck505 = false;
5000 bool can_ssc = false;
13d83a67
JB		 5001
5002 /* We need to take the global config into account */
199e5d79
KP		 5003 list_for_each_entry(encoder, &mode_config->encoder_list,
5004 base.head) {
5005 switch (encoder->type) {
5006 case INTEL_OUTPUT_LVDS:
5007 has_panel = true;
5008 has_lvds = true;
5009 break;
5010 case INTEL_OUTPUT_EDP:
5011 has_panel = true;
2de6905f 5012 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5013 has_cpu_edp = true;
5014 break;
13d83a67
JB		 5015 }
5016 }
5017
99eb6a01 5018 if (HAS_PCH_IBX(dev)) {
41aa3448 5019 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5020 can_ssc = has_ck505;
5021 } else {
5022 has_ck505 = false;
5023 can_ssc = true;
5024 }
5025
2de6905f
ID		 5026 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5027 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5028
5029 /* Ironlake: try to setup display ref clock before DPLL
5030 * enabling. This is only under driver's control after
5031 * PCH B stepping, previous chipset stepping should be
5032 * ignoring this setting.
5033 */
74cfd7ac
CW		 5034 val = I915_READ(PCH_DREF_CONTROL);
5035
5036 /* As we must carefully and slowly disable/enable each source in turn,
5037 * compute the final state we want first and check if we need to
5038 * make any changes at all.
5039 */
5040 final = val;
5041 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5042 if (has_ck505)
5043 final |= DREF_NONSPREAD_CK505_ENABLE;
5044 else
5045 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5046
5047 final &= ~DREF_SSC_SOURCE_MASK;
5048 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5049 final &= ~DREF_SSC1_ENABLE;
5050
5051 if (has_panel) {
5052 final |= DREF_SSC_SOURCE_ENABLE;
5053
5054 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5055 final |= DREF_SSC1_ENABLE;
5056
5057 if (has_cpu_edp) {
5058 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5059 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5060 else
5061 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5062 } else
5063 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5064 } else {
5065 final |= DREF_SSC_SOURCE_DISABLE;
5066 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5067 }
5068
5069 if (final == val)
5070 return;
5071
13d83a67 5072 /* Always enable nonspread source */
74cfd7ac 5073 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5074
99eb6a01 5075 if (has_ck505)
74cfd7ac 5076 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5077 else
74cfd7ac 5078 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5079
199e5d79 5080 if (has_panel) {
74cfd7ac
CW		 5081 val &= ~DREF_SSC_SOURCE_MASK;
5082 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5083
199e5d79 5084 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5085 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5086 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5087 val |= DREF_SSC1_ENABLE;
e77166b5 5088 } else
74cfd7ac 5089 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5090
5091 /* Get SSC going before enabling the outputs */
74cfd7ac 5092 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5093 POSTING_READ(PCH_DREF_CONTROL);
5094 udelay(200);
5095
74cfd7ac 5096 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5097
5098 /* Enable CPU source on CPU attached eDP */
199e5d79 5099 if (has_cpu_edp) {
99eb6a01 5100 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5101 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5102 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5103 }
13d83a67 5104 else
74cfd7ac 5105 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5106 } else
74cfd7ac 5107 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5108
74cfd7ac 5109 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5110 POSTING_READ(PCH_DREF_CONTROL);
5111 udelay(200);
5112 } else {
5113 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5114
74cfd7ac 5115 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5116
5117 /* Turn off CPU output */
74cfd7ac 5118 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5119
74cfd7ac 5120 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5121 POSTING_READ(PCH_DREF_CONTROL);
5122 udelay(200);
5123
5124 /* Turn off the SSC source */
74cfd7ac
CW		 5125 val &= ~DREF_SSC_SOURCE_MASK;
5126 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5127
5128 /* Turn off SSC1 */
74cfd7ac 5129 val &= ~DREF_SSC1_ENABLE;
199e5d79 5130
74cfd7ac 5131 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5132 POSTING_READ(PCH_DREF_CONTROL);
5133 udelay(200);
5134 }
74cfd7ac
CW		 5135
5136 BUG_ON(val != final);
13d83a67
JB		 5137}
5138
dde86e2d
PZ		 5139/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5140static void lpt_init_pch_refclk(struct drm_device *dev)
5141{
5142 struct drm_i915_private *dev_priv = dev->dev_private;
5143 struct drm_mode_config *mode_config = &dev->mode_config;
5144 struct intel_encoder *encoder;
5145 bool has_vga = false;
5146 bool is_sdv = false;
5147 u32 tmp;
5148
5149 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5150 switch (encoder->type) {
5151 case INTEL_OUTPUT_ANALOG:
5152 has_vga = true;
5153 break;
5154 }
5155 }
5156
5157 if (!has_vga)
5158 return;
5159
c00db246
DV		 5160 mutex_lock(&dev_priv->dpio_lock);
5161
dde86e2d
PZ		 5162 /* XXX: Rip out SDV support once Haswell ships for real. */
5163 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5164 is_sdv = true;
5165
5166 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5167 tmp &= ~SBI_SSCCTL_DISABLE;
5168 tmp |= SBI_SSCCTL_PATHALT;
5169 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5170
5171 udelay(24);
5172
5173 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5174 tmp &= ~SBI_SSCCTL_PATHALT;
5175 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5176
5177 if (!is_sdv) {
5178 tmp = I915_READ(SOUTH_CHICKEN2);
5179 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5180 I915_WRITE(SOUTH_CHICKEN2, tmp);
5181
5182 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5183 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5184 DRM_ERROR("FDI mPHY reset assert timeout\n");
5185
5186 tmp = I915_READ(SOUTH_CHICKEN2);
5187 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5188 I915_WRITE(SOUTH_CHICKEN2, tmp);
5189
5190 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5191 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5192 100))
5193 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5194 }
5195
5196 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5197 tmp &= ~(0xFF << 24);
5198 tmp |= (0x12 << 24);
5199 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5200
dde86e2d
PZ		 5201 if (is_sdv) {
5202 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5203 tmp |= 0x7FFF;
5204 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5205 }
5206
5207 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5208 tmp |= (1 << 11);
5209 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5210
5211 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5212 tmp |= (1 << 11);
5213 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5214
5215 if (is_sdv) {
5216 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5217 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5218 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5219
5220 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5221 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5222 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5223
5224 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5225 tmp |= (0x3F << 8);
5226 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5227
5228 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5229 tmp |= (0x3F << 8);
5230 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5231 }
5232
5233 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5234 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5235 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5236
5237 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5238 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5239 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5240
5241 if (!is_sdv) {
5242 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5243 tmp &= ~(7 << 13);
5244 tmp |= (5 << 13);
5245 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5246
5247 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5248 tmp &= ~(7 << 13);
5249 tmp |= (5 << 13);
5250 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5251 }
5252
5253 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5254 tmp &= ~0xFF;
5255 tmp |= 0x1C;
5256 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5259 tmp &= ~0xFF;
5260 tmp |= 0x1C;
5261 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5264 tmp &= ~(0xFF << 16);
5265 tmp |= (0x1C << 16);
5266 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5269 tmp &= ~(0xFF << 16);
5270 tmp |= (0x1C << 16);
5271 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5272
5273 if (!is_sdv) {
5274 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5275 tmp |= (1 << 27);
5276 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5279 tmp |= (1 << 27);
5280 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5281
5282 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5283 tmp &= ~(0xF << 28);
5284 tmp |= (4 << 28);
5285 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5286
5287 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5288 tmp &= ~(0xF << 28);
5289 tmp |= (4 << 28);
5290 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5291 }
5292
5293 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5294 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5295 tmp |= SBI_DBUFF0_ENABLE;
5296 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5297
5298 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5299}
5300
5301/*
5302 * Initialize reference clocks when the driver loads
5303 */
5304void intel_init_pch_refclk(struct drm_device *dev)
5305{
5306 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5307 ironlake_init_pch_refclk(dev);
5308 else if (HAS_PCH_LPT(dev))
5309 lpt_init_pch_refclk(dev);
5310}
5311
d9d444cb
JB		 5312static int ironlake_get_refclk(struct drm_crtc *crtc)
5313{
5314 struct drm_device *dev = crtc->dev;
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316 struct intel_encoder *encoder;
d9d444cb
JB		 5317 int num_connectors = 0;
5318 bool is_lvds = false;
5319
6c2b7c12 5320 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5321 switch (encoder->type) {
5322 case INTEL_OUTPUT_LVDS:
5323 is_lvds = true;
5324 break;
d9d444cb
JB		 5325 }
5326 num_connectors++;
5327 }
5328
5329 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5330 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5331 dev_priv->vbt.lvds_ssc_freq);
5332 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5333 }
5334
5335 return 120000;
5336}
5337
6ff93609 5338static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5339{
c8203565 5340 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5342 int pipe = intel_crtc->pipe;
c8203565
PZ		 5343 uint32_t val;
5344
5345 val = I915_READ(PIPECONF(pipe));
5346
dfd07d72 5347 val &= ~PIPECONF_BPC_MASK;
965e0c48 5348 switch (intel_crtc->config.pipe_bpp) {
c8203565 5349 case 18:
dfd07d72 5350 val |= PIPECONF_6BPC;
c8203565
PZ		 5351 break;
5352 case 24:
dfd07d72 5353 val |= PIPECONF_8BPC;
c8203565
PZ		 5354 break;
5355 case 30:
dfd07d72 5356 val |= PIPECONF_10BPC;
c8203565
PZ		 5357 break;
5358 case 36:
dfd07d72 5359 val |= PIPECONF_12BPC;
c8203565
PZ		 5360 break;
5361 default:
cc769b62
PZ		 5362 /* Case prevented by intel_choose_pipe_bpp_dither. */
5363 BUG();
c8203565
PZ		 5364 }
5365
5366 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5367 if (intel_crtc->config.dither)
c8203565
PZ		 5368 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5369
5370 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5371 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5372 val |= PIPECONF_INTERLACED_ILK;
5373 else
5374 val |= PIPECONF_PROGRESSIVE;
5375
50f3b016 5376 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5377 val |= PIPECONF_COLOR_RANGE_SELECT;
5378 else
5379 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5380
c8203565
PZ		 5381 I915_WRITE(PIPECONF(pipe), val);
5382 POSTING_READ(PIPECONF(pipe));
5383}
5384
86d3efce
VS		 5385/*
5386 * Set up the pipe CSC unit.
5387 *
5388 * Currently only full range RGB to limited range RGB conversion
5389 * is supported, but eventually this should handle various
5390 * RGB<->YCbCr scenarios as well.
5391 */
50f3b016 5392static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5393{
5394 struct drm_device *dev = crtc->dev;
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5397 int pipe = intel_crtc->pipe;
5398 uint16_t coeff = 0x7800; /* 1.0 */
5399
5400 /*
5401 * TODO: Check what kind of values actually come out of the pipe
5402 * with these coeff/postoff values and adjust to get the best
5403 * accuracy. Perhaps we even need to take the bpc value into
5404 * consideration.
5405 */
5406
50f3b016 5407 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5408 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5409
5410 /*
5411 * GY/GU and RY/RU should be the other way around according
5412 * to BSpec, but reality doesn't agree. Just set them up in
5413 * a way that results in the correct picture.
5414 */
5415 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5416 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5417
5418 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5419 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5420
5421 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5422 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5423
5424 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5425 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5426 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5427
5428 if (INTEL_INFO(dev)->gen > 6) {
5429 uint16_t postoff = 0;
5430
50f3b016 5431 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5432 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5433
5434 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5435 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5436 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5437
5438 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5439 } else {
5440 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5441
50f3b016 5442 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5443 mode |= CSC_BLACK_SCREEN_OFFSET;
5444
5445 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5446 }
5447}
5448
6ff93609 5449static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5450{
5451 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5454 uint32_t val;
5455
702e7a56 5456 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5457
5458 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5459 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5460 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5461
5462 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5463 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5464 val |= PIPECONF_INTERLACED_ILK;
5465 else
5466 val |= PIPECONF_PROGRESSIVE;
5467
702e7a56
PZ		 5468 I915_WRITE(PIPECONF(cpu_transcoder), val);
5469 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5470}
5471
6591c6e4 5472static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5473 intel_clock_t *clock,
5474 bool *has_reduced_clock,
5475 intel_clock_t *reduced_clock)
5476{
5477 struct drm_device *dev = crtc->dev;
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479 struct intel_encoder *intel_encoder;
5480 int refclk;
d4906093 5481 const intel_limit_t *limit;
a16af721 5482 bool ret, is_lvds = false;
79e53945 5483
6591c6e4
PZ		 5484 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5485 switch (intel_encoder->type) {
79e53945
JB		 5486 case INTEL_OUTPUT_LVDS:
5487 is_lvds = true;
5488 break;
79e53945
JB		 5489 }
5490 }
5491
d9d444cb 5492 refclk = ironlake_get_refclk(crtc);
79e53945 5493
d4906093
ML		 5494 /*
5495 * Returns a set of divisors for the desired target clock with the given
5496 * refclk, or FALSE. The returned values represent the clock equation:
5497 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5498 */
1b894b59 5499 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5500 ret = dev_priv->display.find_dpll(limit, crtc,
5501 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5502 refclk, NULL, clock);
6591c6e4
PZ		 5503 if (!ret)
5504 return false;
cda4b7d3 5505
ddc9003c 5506 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5507 /*
5508 * Ensure we match the reduced clock's P to the target clock.
5509 * If the clocks don't match, we can't switch the display clock
5510 * by using the FP0/FP1. In such case we will disable the LVDS
5511 * downclock feature.
5512 */
ee9300bb
DV		 5513 *has_reduced_clock =
5514 dev_priv->display.find_dpll(limit, crtc,
5515 dev_priv->lvds_downclock,
5516 refclk, clock,
5517 reduced_clock);
652c393a 5518 }
61e9653f 5519
6591c6e4
PZ		 5520 return true;
5521}
5522
01a415fd
DV		 5523static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5524{
5525 struct drm_i915_private *dev_priv = dev->dev_private;
5526 uint32_t temp;
5527
5528 temp = I915_READ(SOUTH_CHICKEN1);
5529 if (temp & FDI_BC_BIFURCATION_SELECT)
5530 return;
5531
5532 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5533 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5534
5535 temp |= FDI_BC_BIFURCATION_SELECT;
5536 DRM_DEBUG_KMS("enabling fdi C rx\n");
5537 I915_WRITE(SOUTH_CHICKEN1, temp);
5538 POSTING_READ(SOUTH_CHICKEN1);
5539}
5540
ebfd86fd
DV		 5541static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5542{
5543 struct drm_device *dev = intel_crtc->base.dev;
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5545
5546 switch (intel_crtc->pipe) {
5547 case PIPE_A:
5548 break;
5549 case PIPE_B:
5550 if (intel_crtc->config.fdi_lanes > 2)
5551 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5552 else
5553 cpt_enable_fdi_bc_bifurcation(dev);
5554
5555 break;
5556 case PIPE_C:
01a415fd
DV		 5557 cpt_enable_fdi_bc_bifurcation(dev);
5558
ebfd86fd 5559 break;
01a415fd
DV		 5560 default:
5561 BUG();
5562 }
5563}
5564
d4b1931c
PZ		 5565int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5566{
5567 /*
5568 * Account for spread spectrum to avoid
5569 * oversubscribing the link. Max center spread
5570 * is 2.5%; use 5% for safety's sake.
5571 */
5572 u32 bps = target_clock * bpp * 21 / 20;
5573 return bps / (link_bw * 8) + 1;
5574}
5575
7429e9d4
DV		 5576static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5577{
5578 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5579}
5580
de13a2e3 5581static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5582 u32 *fp,
9a7c7890 5583 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5584{
de13a2e3 5585 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5586 struct drm_device *dev = crtc->dev;
5587 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5588 struct intel_encoder *intel_encoder;
5589 uint32_t dpll;
6cc5f341 5590 int factor, num_connectors = 0;
09ede541 5591 bool is_lvds = false, is_sdvo = false;
79e53945 5592
de13a2e3
PZ		 5593 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5594 switch (intel_encoder->type) {
79e53945
JB		 5595 case INTEL_OUTPUT_LVDS:
5596 is_lvds = true;
5597 break;
5598 case INTEL_OUTPUT_SDVO:
7d57382e 5599 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5600 is_sdvo = true;
5601 break;
79e53945 5602 }
43565a06 5603
c751ce4f 5604 num_connectors++;
79e53945 5605 }
79e53945 5606
c1858123 5607 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5608 factor = 21;
5609 if (is_lvds) {
5610 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5611 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5612 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5613 factor = 25;
09ede541 5614 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5615 factor = 20;
c1858123 5616
7429e9d4 5617 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5618 *fp |= FP_CB_TUNE;
2c07245f 5619
9a7c7890
DV		 5620 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5621 *fp2 |= FP_CB_TUNE;
5622
5eddb70b 5623 dpll = 0;
2c07245f 5624
a07d6787
EA		 5625 if (is_lvds)
5626 dpll |= DPLLB_MODE_LVDS;
5627 else
5628 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5629
ef1b460d
DV		 5630 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5631 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5632
5633 if (is_sdvo)
5634 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5635 if (intel_crtc->config.has_dp_encoder)
a07d6787 5636 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5637
a07d6787 5638 /* compute bitmask from p1 value */
7429e9d4 5639 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5640 /* also FPA1 */
7429e9d4 5641 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5642
7429e9d4 5643 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5644 case 5:
5645 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5646 break;
5647 case 7:
5648 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5649 break;
5650 case 10:
5651 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5652 break;
5653 case 14:
5654 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5655 break;
79e53945
JB		 5656 }
5657
b4c09f3b 5658 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5659 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5660 else
5661 dpll |= PLL_REF_INPUT_DREFCLK;
5662
de13a2e3
PZ		 5663 return dpll;
5664}
5665
5666static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5667 int x, int y,
5668 struct drm_framebuffer *fb)
5669{
5670 struct drm_device *dev = crtc->dev;
5671 struct drm_i915_private *dev_priv = dev->dev_private;
5672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5673 int pipe = intel_crtc->pipe;
5674 int plane = intel_crtc->plane;
5675 int num_connectors = 0;
5676 intel_clock_t clock, reduced_clock;
cbbab5bd 5677 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5678 bool ok, has_reduced_clock = false;
8b47047b 5679 bool is_lvds = false;
de13a2e3 5680 struct intel_encoder *encoder;
e2b78267 5681 struct intel_shared_dpll *pll;
de13a2e3 5682 int ret;
de13a2e3
PZ		 5683
5684 for_each_encoder_on_crtc(dev, crtc, encoder) {
5685 switch (encoder->type) {
5686 case INTEL_OUTPUT_LVDS:
5687 is_lvds = true;
5688 break;
de13a2e3
PZ		 5689 }
5690
5691 num_connectors++;
a07d6787 5692 }
79e53945 5693
5dc5298b
PZ		 5694 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5695 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5696
ff9a6750 5697 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5698 &has_reduced_clock, &reduced_clock);
ee9300bb 5699 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5700 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5701 return -EINVAL;
79e53945 5702 }
f47709a9
DV		 5703 /* Compat-code for transition, will disappear. */
5704 if (!intel_crtc->config.clock_set) {
5705 intel_crtc->config.dpll.n = clock.n;
5706 intel_crtc->config.dpll.m1 = clock.m1;
5707 intel_crtc->config.dpll.m2 = clock.m2;
5708 intel_crtc->config.dpll.p1 = clock.p1;
5709 intel_crtc->config.dpll.p2 = clock.p2;
5710 }
79e53945 5711
de13a2e3
PZ		 5712 /* Ensure that the cursor is valid for the new mode before changing... */
5713 intel_crtc_update_cursor(crtc, true);
5714
5dc5298b 5715 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5716 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5717 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5718 if (has_reduced_clock)
7429e9d4 5719 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5720
7429e9d4 5721 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5722 &fp, &reduced_clock,
5723 has_reduced_clock ? &fp2 : NULL);
5724
66e985c0
DV		 5725 intel_crtc->config.dpll_hw_state.dpll = dpll | DPLL_VCO_ENABLE;
5726 intel_crtc->config.dpll_hw_state.fp0 = fp;
5727 if (has_reduced_clock)
5728 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5729 else
5730 intel_crtc->config.dpll_hw_state.fp1 = fp;
5731
e72f9fbf 5732 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
ee7b9f93 5733 if (pll == NULL) {
84f44ce7
VS		 5734 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5735 pipe_name(pipe));
4b645f14
JB		 5736 return -EINVAL;
5737 }
ee7b9f93 5738 } else
e72f9fbf 5739 intel_put_shared_dpll(intel_crtc);
79e53945 5740
03afc4a2
DV		 5741 if (intel_crtc->config.has_dp_encoder)
5742 intel_dp_set_m_n(intel_crtc);
79e53945 5743
dafd226c
DV		 5744 for_each_encoder_on_crtc(dev, crtc, encoder)
5745 if (encoder->pre_pll_enable)
5746 encoder->pre_pll_enable(encoder);
79e53945 5747
e2b78267
DV		 5748 intel_crtc->lowfreq_avail = false;
5749
5750 if (intel_crtc->config.has_pch_encoder) {
5751 pll = intel_crtc_to_shared_dpll(intel_crtc);
5752
e9a632a5 5753 I915_WRITE(PCH_DPLL(pll->id), dpll);
5eddb70b 5754
32f9d658 5755 /* Wait for the clocks to stabilize. */
e9a632a5 5756 POSTING_READ(PCH_DPLL(pll->id));
32f9d658
ZW		 5757 udelay(150);
5758
8febb297
EA		 5759 /* The pixel multiplier can only be updated once the
5760 * DPLL is enabled and the clocks are stable.
5761 *
5762 * So write it again.
5763 */
e9a632a5 5764 I915_WRITE(PCH_DPLL(pll->id), dpll);
79e53945 5765
4b645f14 5766 if (is_lvds && has_reduced_clock && i915_powersave) {
e9a632a5 5767 I915_WRITE(PCH_FP1(pll->id), fp2);
4b645f14 5768 intel_crtc->lowfreq_avail = true;
4b645f14 5769 } else {
e9a632a5 5770 I915_WRITE(PCH_FP1(pll->id), fp);
652c393a
JB		 5771 }
5772 }
5773
8a654f3b 5774 intel_set_pipe_timings(intel_crtc);
5eddb70b 5775
ca3a0ff8 5776 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5777 intel_cpu_transcoder_set_m_n(intel_crtc,
5778 &intel_crtc->config.fdi_m_n);
5779 }
2c07245f 5780
ebfd86fd
DV		 5781 if (IS_IVYBRIDGE(dev))
5782 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5783
6ff93609 5784 ironlake_set_pipeconf(crtc);
79e53945 5785
a1f9e77e
PZ		 5786 /* Set up the display plane register */
5787 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5788 POSTING_READ(DSPCNTR(plane));
79e53945 5789
94352cf9 5790 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5791
5792 intel_update_watermarks(dev);
5793
1857e1da 5794 return ret;
79e53945
JB		 5795}
5796
72419203
DV		 5797static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5798 struct intel_crtc_config *pipe_config)
5799{
5800 struct drm_device *dev = crtc->base.dev;
5801 struct drm_i915_private *dev_priv = dev->dev_private;
5802 enum transcoder transcoder = pipe_config->cpu_transcoder;
5803
5804 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5805 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5806 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5807 & ~TU_SIZE_MASK;
5808 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5809 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5810 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5811}
5812
2fa2fe9a
DV		 5813static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5814 struct intel_crtc_config *pipe_config)
5815{
5816 struct drm_device *dev = crtc->base.dev;
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5818 uint32_t tmp;
5819
5820 tmp = I915_READ(PF_CTL(crtc->pipe));
5821
5822 if (tmp & PF_ENABLE) {
5823 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5824 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5825
5826 /* We currently do not free assignements of panel fitters on
5827 * ivb/hsw (since we don't use the higher upscaling modes which
5828 * differentiates them) so just WARN about this case for now. */
5829 if (IS_GEN7(dev)) {
5830 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5831 PF_PIPE_SEL_IVB(crtc->pipe));
5832 }
2fa2fe9a
DV		 5833 }
5834}
5835
0e8ffe1b
DV		 5836static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5837 struct intel_crtc_config *pipe_config)
5838{
5839 struct drm_device *dev = crtc->base.dev;
5840 struct drm_i915_private *dev_priv = dev->dev_private;
5841 uint32_t tmp;
5842
eccb140b 5843 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5844 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5845
0e8ffe1b
DV		 5846 tmp = I915_READ(PIPECONF(crtc->pipe));
5847 if (!(tmp & PIPECONF_ENABLE))
5848 return false;
5849
ab9412ba 5850 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5851 struct intel_shared_dpll *pll;
5852
88adfff1
DV		 5853 pipe_config->has_pch_encoder = true;
5854
627eb5a3
DV		 5855 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5856 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5857 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5858
5859 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5860
5861 /* XXX: Can't properly read out the pch dpll pixel multiplier
5862 * since we don't have state tracking for pch clocks yet. */
5863 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5864
5865 if (HAS_PCH_IBX(dev_priv->dev)) {
5866 pipe_config->shared_dpll = crtc->pipe;
5867 } else {
5868 tmp = I915_READ(PCH_DPLL_SEL);
5869 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5870 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5871 else
5872 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5873 }
66e985c0
DV		 5874
5875 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5876
5877 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5878 &pipe_config->dpll_hw_state));
6c49f241
DV		 5879 } else {
5880 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5881 }
5882
1bd1bd80
DV		 5883 intel_get_pipe_timings(crtc, pipe_config);
5884
2fa2fe9a
DV		 5885 ironlake_get_pfit_config(crtc, pipe_config);
5886
0e8ffe1b
DV		 5887 return true;
5888}
5889
d6dd9eb1
DV		 5890static void haswell_modeset_global_resources(struct drm_device *dev)
5891{
d6dd9eb1
DV		 5892 bool enable = false;
5893 struct intel_crtc *crtc;
d6dd9eb1
DV		 5894
5895 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5896 if (!crtc->base.enabled)
5897 continue;
d6dd9eb1 5898
e7a639c4
DV		 5899 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5900 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5901 enable = true;
5902 }
5903
d6dd9eb1
DV		 5904 intel_set_power_well(dev, enable);
5905}
5906
09b4ddf9 5907static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5908 int x, int y,
5909 struct drm_framebuffer *fb)
5910{
5911 struct drm_device *dev = crtc->dev;
5912 struct drm_i915_private *dev_priv = dev->dev_private;
5913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5914 int plane = intel_crtc->plane;
09b4ddf9 5915 int ret;
09b4ddf9 5916
ff9a6750 5917 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5918 return -EINVAL;
5919
09b4ddf9
PZ		 5920 /* Ensure that the cursor is valid for the new mode before changing... */
5921 intel_crtc_update_cursor(crtc, true);
5922
03afc4a2
DV		 5923 if (intel_crtc->config.has_dp_encoder)
5924 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5925
5926 intel_crtc->lowfreq_avail = false;
09b4ddf9 5927
8a654f3b 5928 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5929
ca3a0ff8 5930 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5931 intel_cpu_transcoder_set_m_n(intel_crtc,
5932 &intel_crtc->config.fdi_m_n);
5933 }
09b4ddf9 5934
6ff93609 5935 haswell_set_pipeconf(crtc);
09b4ddf9 5936
50f3b016 5937 intel_set_pipe_csc(crtc);
86d3efce 5938
09b4ddf9 5939 /* Set up the display plane register */
86d3efce 5940 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5941 POSTING_READ(DSPCNTR(plane));
5942
5943 ret = intel_pipe_set_base(crtc, x, y, fb);
5944
5945 intel_update_watermarks(dev);
5946
1f803ee5 5947 return ret;
79e53945
JB		 5948}
5949
0e8ffe1b
DV		 5950static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5951 struct intel_crtc_config *pipe_config)
5952{
5953 struct drm_device *dev = crtc->base.dev;
5954 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5955 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5956 uint32_t tmp;
5957
eccb140b 5958 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5959 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5960
eccb140b
DV		 5961 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5962 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5963 enum pipe trans_edp_pipe;
5964 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5965 default:
5966 WARN(1, "unknown pipe linked to edp transcoder\n");
5967 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5968 case TRANS_DDI_EDP_INPUT_A_ON:
5969 trans_edp_pipe = PIPE_A;
5970 break;
5971 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5972 trans_edp_pipe = PIPE_B;
5973 break;
5974 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5975 trans_edp_pipe = PIPE_C;
5976 break;
5977 }
5978
5979 if (trans_edp_pipe == crtc->pipe)
5980 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5981 }
5982
b97186f0 5983 if (!intel_display_power_enabled(dev,
eccb140b 5984 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5985 return false;
5986
eccb140b 5987 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5988 if (!(tmp & PIPECONF_ENABLE))
5989 return false;
5990
88adfff1 5991 /*
f196e6be 5992 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5993 * DDI E. So just check whether this pipe is wired to DDI E and whether
5994 * the PCH transcoder is on.
5995 */
eccb140b 5996 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5997 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5998 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5999 pipe_config->has_pch_encoder = true;
6000
627eb5a3
DV		 6001 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6002 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6003 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6004
6005 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6006 }
6007
1bd1bd80
DV		 6008 intel_get_pipe_timings(crtc, pipe_config);
6009
2fa2fe9a
DV		 6010 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6011 if (intel_display_power_enabled(dev, pfit_domain))
6012 ironlake_get_pfit_config(crtc, pipe_config);
6013
42db64ef
PZ		 6014 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6015 (I915_READ(IPS_CTL) & IPS_ENABLE);
6016
6c49f241
DV		 6017 pipe_config->pixel_multiplier = 1;
6018
0e8ffe1b
DV		 6019 return true;
6020}
6021
f564048e 6022static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6023 int x, int y,
94352cf9 6024 struct drm_framebuffer *fb)
f564048e
EA		 6025{
6026 struct drm_device *dev = crtc->dev;
6027 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6028 struct drm_encoder_helper_funcs *encoder_funcs;
6029 struct intel_encoder *encoder;
0b701d27 6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6031 struct drm_display_mode *adjusted_mode =
6032 &intel_crtc->config.adjusted_mode;
6033 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6034 int pipe = intel_crtc->pipe;
f564048e
EA		 6035 int ret;
6036
0b701d27 6037 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6038
b8cecdf5
DV		 6039 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6040
79e53945 6041 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6042
9256aa19
DV		 6043 if (ret != 0)
6044 return ret;
6045
6046 for_each_encoder_on_crtc(dev, crtc, encoder) {
6047 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6048 encoder->base.base.id,
6049 drm_get_encoder_name(&encoder->base),
6050 mode->base.id, mode->name);
6cc5f341
DV		 6051 if (encoder->mode_set) {
6052 encoder->mode_set(encoder);
6053 } else {
6054 encoder_funcs = encoder->base.helper_private;
6055 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6056 }
9256aa19
DV		 6057 }
6058
6059 return 0;
79e53945
JB		 6060}
6061
3a9627f4
WF		 6062static bool intel_eld_uptodate(struct drm_connector *connector,
6063 int reg_eldv, uint32_t bits_eldv,
6064 int reg_elda, uint32_t bits_elda,
6065 int reg_edid)
6066{
6067 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6068 uint8_t *eld = connector->eld;
6069 uint32_t i;
6070
6071 i = I915_READ(reg_eldv);
6072 i &= bits_eldv;
6073
6074 if (!eld[0])
6075 return !i;
6076
6077 if (!i)
6078 return false;
6079
6080 i = I915_READ(reg_elda);
6081 i &= ~bits_elda;
6082 I915_WRITE(reg_elda, i);
6083
6084 for (i = 0; i < eld[2]; i++)
6085 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6086 return false;
6087
6088 return true;
6089}
6090
e0dac65e
WF		 6091static void g4x_write_eld(struct drm_connector *connector,
6092 struct drm_crtc *crtc)
6093{
6094 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6095 uint8_t *eld = connector->eld;
6096 uint32_t eldv;
6097 uint32_t len;
6098 uint32_t i;
6099
6100 i = I915_READ(G4X_AUD_VID_DID);
6101
6102 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6103 eldv = G4X_ELDV_DEVCL_DEVBLC;
6104 else
6105 eldv = G4X_ELDV_DEVCTG;
6106
3a9627f4
WF		 6107 if (intel_eld_uptodate(connector,
6108 G4X_AUD_CNTL_ST, eldv,
6109 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6110 G4X_HDMIW_HDMIEDID))
6111 return;
6112
e0dac65e
WF		 6113 i = I915_READ(G4X_AUD_CNTL_ST);
6114 i &= ~(eldv | G4X_ELD_ADDR);
6115 len = (i >> 9) & 0x1f; /* ELD buffer size */
6116 I915_WRITE(G4X_AUD_CNTL_ST, i);
6117
6118 if (!eld[0])
6119 return;
6120
6121 len = min_t(uint8_t, eld[2], len);
6122 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6123 for (i = 0; i < len; i++)
6124 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6125
6126 i = I915_READ(G4X_AUD_CNTL_ST);
6127 i |= eldv;
6128 I915_WRITE(G4X_AUD_CNTL_ST, i);
6129}
6130
83358c85
WX		 6131static void haswell_write_eld(struct drm_connector *connector,
6132 struct drm_crtc *crtc)
6133{
6134 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6135 uint8_t *eld = connector->eld;
6136 struct drm_device *dev = crtc->dev;
7b9f35a6 6137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6138 uint32_t eldv;
6139 uint32_t i;
6140 int len;
6141 int pipe = to_intel_crtc(crtc)->pipe;
6142 int tmp;
6143
6144 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6145 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6146 int aud_config = HSW_AUD_CFG(pipe);
6147 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6148
6149
6150 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6151
6152 /* Audio output enable */
6153 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6154 tmp = I915_READ(aud_cntrl_st2);
6155 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6156 I915_WRITE(aud_cntrl_st2, tmp);
6157
6158 /* Wait for 1 vertical blank */
6159 intel_wait_for_vblank(dev, pipe);
6160
6161 /* Set ELD valid state */
6162 tmp = I915_READ(aud_cntrl_st2);
6163 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6164 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6165 I915_WRITE(aud_cntrl_st2, tmp);
6166 tmp = I915_READ(aud_cntrl_st2);
6167 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6168
6169 /* Enable HDMI mode */
6170 tmp = I915_READ(aud_config);
6171 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6172 /* clear N_programing_enable and N_value_index */
6173 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6174 I915_WRITE(aud_config, tmp);
6175
6176 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6177
6178 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6179 intel_crtc->eld_vld = true;
83358c85
WX		 6180
6181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6182 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6183 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6184 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6185 } else
6186 I915_WRITE(aud_config, 0);
6187
6188 if (intel_eld_uptodate(connector,
6189 aud_cntrl_st2, eldv,
6190 aud_cntl_st, IBX_ELD_ADDRESS,
6191 hdmiw_hdmiedid))
6192 return;
6193
6194 i = I915_READ(aud_cntrl_st2);
6195 i &= ~eldv;
6196 I915_WRITE(aud_cntrl_st2, i);
6197
6198 if (!eld[0])
6199 return;
6200
6201 i = I915_READ(aud_cntl_st);
6202 i &= ~IBX_ELD_ADDRESS;
6203 I915_WRITE(aud_cntl_st, i);
6204 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6205 DRM_DEBUG_DRIVER("port num:%d\n", i);
6206
6207 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6208 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6209 for (i = 0; i < len; i++)
6210 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6211
6212 i = I915_READ(aud_cntrl_st2);
6213 i |= eldv;
6214 I915_WRITE(aud_cntrl_st2, i);
6215
6216}
6217
e0dac65e
WF		 6218static void ironlake_write_eld(struct drm_connector *connector,
6219 struct drm_crtc *crtc)
6220{
6221 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6222 uint8_t *eld = connector->eld;
6223 uint32_t eldv;
6224 uint32_t i;
6225 int len;
6226 int hdmiw_hdmiedid;
b6daa025 6227 int aud_config;
e0dac65e
WF		 6228 int aud_cntl_st;
6229 int aud_cntrl_st2;
9b138a83 6230 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6231
b3f33cbf 6232 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6233 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6234 aud_config = IBX_AUD_CFG(pipe);
6235 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6236 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6237 } else {
9b138a83
WX		 6238 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6239 aud_config = CPT_AUD_CFG(pipe);
6240 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6241 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6242 }
6243
9b138a83 6244 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6245
6246 i = I915_READ(aud_cntl_st);
9b138a83 6247 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6248 if (!i) {
6249 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6250 /* operate blindly on all ports */
1202b4c6
WF		 6251 eldv = IBX_ELD_VALIDB;
6252 eldv |= IBX_ELD_VALIDB << 4;
6253 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6254 } else {
2582a850 6255 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6256 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6257 }
6258
3a9627f4
WF		 6259 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6260 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6261 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6262 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6263 } else
6264 I915_WRITE(aud_config, 0);
e0dac65e 6265
3a9627f4
WF		 6266 if (intel_eld_uptodate(connector,
6267 aud_cntrl_st2, eldv,
6268 aud_cntl_st, IBX_ELD_ADDRESS,
6269 hdmiw_hdmiedid))
6270 return;
6271
e0dac65e
WF		 6272 i = I915_READ(aud_cntrl_st2);
6273 i &= ~eldv;
6274 I915_WRITE(aud_cntrl_st2, i);
6275
6276 if (!eld[0])
6277 return;
6278
e0dac65e 6279 i = I915_READ(aud_cntl_st);
1202b4c6 6280 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6281 I915_WRITE(aud_cntl_st, i);
6282
6283 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6284 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6285 for (i = 0; i < len; i++)
6286 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6287
6288 i = I915_READ(aud_cntrl_st2);
6289 i |= eldv;
6290 I915_WRITE(aud_cntrl_st2, i);
6291}
6292
6293void intel_write_eld(struct drm_encoder *encoder,
6294 struct drm_display_mode *mode)
6295{
6296 struct drm_crtc *crtc = encoder->crtc;
6297 struct drm_connector *connector;
6298 struct drm_device *dev = encoder->dev;
6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300
6301 connector = drm_select_eld(encoder, mode);
6302 if (!connector)
6303 return;
6304
6305 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6306 connector->base.id,
6307 drm_get_connector_name(connector),
6308 connector->encoder->base.id,
6309 drm_get_encoder_name(connector->encoder));
6310
6311 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6312
6313 if (dev_priv->display.write_eld)
6314 dev_priv->display.write_eld(connector, crtc);
6315}
6316
79e53945
JB		 6317/** Loads the palette/gamma unit for the CRTC with the prepared values */
6318void intel_crtc_load_lut(struct drm_crtc *crtc)
6319{
6320 struct drm_device *dev = crtc->dev;
6321 struct drm_i915_private *dev_priv = dev->dev_private;
6322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6323 enum pipe pipe = intel_crtc->pipe;
6324 int palreg = PALETTE(pipe);
79e53945 6325 int i;
42db64ef 6326 bool reenable_ips = false;
79e53945
JB		 6327
6328 /* The clocks have to be on to load the palette. */
aed3f09d 6329 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6330 return;
6331
14420bd0
VS		 6332 if (!HAS_PCH_SPLIT(dev_priv->dev))
6333 assert_pll_enabled(dev_priv, pipe);
6334
f2b115e6 6335 /* use legacy palette for Ironlake */
bad720ff 6336 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6337 palreg = LGC_PALETTE(pipe);
6338
6339 /* Workaround : Do not read or write the pipe palette/gamma data while
6340 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6341 */
6342 if (intel_crtc->config.ips_enabled &&
6343 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6344 GAMMA_MODE_MODE_SPLIT)) {
6345 hsw_disable_ips(intel_crtc);
6346 reenable_ips = true;
6347 }
2c07245f 6348
79e53945
JB		 6349 for (i = 0; i < 256; i++) {
6350 I915_WRITE(palreg + 4 * i,
6351 (intel_crtc->lut_r[i] << 16) |
6352 (intel_crtc->lut_g[i] << 8) |
6353 intel_crtc->lut_b[i]);
6354 }
42db64ef
PZ		 6355
6356 if (reenable_ips)
6357 hsw_enable_ips(intel_crtc);
79e53945
JB		 6358}
6359
560b85bb
CW		 6360static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6361{
6362 struct drm_device *dev = crtc->dev;
6363 struct drm_i915_private *dev_priv = dev->dev_private;
6364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6365 bool visible = base != 0;
6366 u32 cntl;
6367
6368 if (intel_crtc->cursor_visible == visible)
6369 return;
6370
9db4a9c7 6371 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6372 if (visible) {
6373 /* On these chipsets we can only modify the base whilst
6374 * the cursor is disabled.
6375 */
9db4a9c7 6376 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6377
6378 cntl &= ~(CURSOR_FORMAT_MASK);
6379 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6380 cntl |= CURSOR_ENABLE |
6381 CURSOR_GAMMA_ENABLE |
6382 CURSOR_FORMAT_ARGB;
6383 } else
6384 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6385 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6386
6387 intel_crtc->cursor_visible = visible;
6388}
6389
6390static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6391{
6392 struct drm_device *dev = crtc->dev;
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6395 int pipe = intel_crtc->pipe;
6396 bool visible = base != 0;
6397
6398 if (intel_crtc->cursor_visible != visible) {
548f245b 6399 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6400 if (base) {
6401 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6402 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6403 cntl |= pipe << 28; /* Connect to correct pipe */
6404 } else {
6405 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6406 cntl |= CURSOR_MODE_DISABLE;
6407 }
9db4a9c7 6408 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6409
6410 intel_crtc->cursor_visible = visible;
6411 }
6412 /* and commit changes on next vblank */
9db4a9c7 6413 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6414}
6415
65a21cd6
JB		 6416static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6417{
6418 struct drm_device *dev = crtc->dev;
6419 struct drm_i915_private *dev_priv = dev->dev_private;
6420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6421 int pipe = intel_crtc->pipe;
6422 bool visible = base != 0;
6423
6424 if (intel_crtc->cursor_visible != visible) {
6425 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6426 if (base) {
6427 cntl &= ~CURSOR_MODE;
6428 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6429 } else {
6430 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6431 cntl |= CURSOR_MODE_DISABLE;
6432 }
86d3efce
VS		 6433 if (IS_HASWELL(dev))
6434 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6435 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6436
6437 intel_crtc->cursor_visible = visible;
6438 }
6439 /* and commit changes on next vblank */
6440 I915_WRITE(CURBASE_IVB(pipe), base);
6441}
6442
cda4b7d3 6443/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6444static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6445 bool on)
cda4b7d3
CW		 6446{
6447 struct drm_device *dev = crtc->dev;
6448 struct drm_i915_private *dev_priv = dev->dev_private;
6449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6450 int pipe = intel_crtc->pipe;
6451 int x = intel_crtc->cursor_x;
6452 int y = intel_crtc->cursor_y;
560b85bb 6453 u32 base, pos;
cda4b7d3
CW		 6454 bool visible;
6455
6456 pos = 0;
6457
6b383a7f 6458 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6459 base = intel_crtc->cursor_addr;
6460 if (x > (int) crtc->fb->width)
6461 base = 0;
6462
6463 if (y > (int) crtc->fb->height)
6464 base = 0;
6465 } else
6466 base = 0;
6467
6468 if (x < 0) {
6469 if (x + intel_crtc->cursor_width < 0)
6470 base = 0;
6471
6472 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6473 x = -x;
6474 }
6475 pos |= x << CURSOR_X_SHIFT;
6476
6477 if (y < 0) {
6478 if (y + intel_crtc->cursor_height < 0)
6479 base = 0;
6480
6481 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6482 y = -y;
6483 }
6484 pos |= y << CURSOR_Y_SHIFT;
6485
6486 visible = base != 0;
560b85bb 6487 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6488 return;
6489
0cd83aa9 6490 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6491 I915_WRITE(CURPOS_IVB(pipe), pos);
6492 ivb_update_cursor(crtc, base);
6493 } else {
6494 I915_WRITE(CURPOS(pipe), pos);
6495 if (IS_845G(dev) || IS_I865G(dev))
6496 i845_update_cursor(crtc, base);
6497 else
6498 i9xx_update_cursor(crtc, base);
6499 }
cda4b7d3
CW		 6500}
6501
79e53945 6502static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6503 struct drm_file *file,
79e53945
JB		 6504 uint32_t handle,
6505 uint32_t width, uint32_t height)
6506{
6507 struct drm_device *dev = crtc->dev;
6508 struct drm_i915_private *dev_priv = dev->dev_private;
6509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6510 struct drm_i915_gem_object *obj;
cda4b7d3 6511 uint32_t addr;
3f8bc370 6512 int ret;
79e53945 6513
79e53945
JB		 6514 /* if we want to turn off the cursor ignore width and height */
6515 if (!handle) {
28c97730 6516 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6517 addr = 0;
05394f39 6518 obj = NULL;
5004417d 6519 mutex_lock(&dev->struct_mutex);
3f8bc370 6520 goto finish;
79e53945
JB		 6521 }
6522
6523 /* Currently we only support 64x64 cursors */
6524 if (width != 64 || height != 64) {
6525 DRM_ERROR("we currently only support 64x64 cursors\n");
6526 return -EINVAL;
6527 }
6528
05394f39 6529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6530 if (&obj->base == NULL)
79e53945
JB		 6531 return -ENOENT;
6532
05394f39 6533 if (obj->base.size < width * height * 4) {
79e53945 6534 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6535 ret = -ENOMEM;
6536 goto fail;
79e53945
JB		 6537 }
6538
71acb5eb 6539 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6540 mutex_lock(&dev->struct_mutex);
b295d1b6 6541 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6542 unsigned alignment;
6543
d9e86c0e
CW		 6544 if (obj->tiling_mode) {
6545 DRM_ERROR("cursor cannot be tiled\n");
6546 ret = -EINVAL;
6547 goto fail_locked;
6548 }
6549
693db184
CW		 6550 /* Note that the w/a also requires 2 PTE of padding following
6551 * the bo. We currently fill all unused PTE with the shadow
6552 * page and so we should always have valid PTE following the
6553 * cursor preventing the VT-d warning.
6554 */
6555 alignment = 0;
6556 if (need_vtd_wa(dev))
6557 alignment = 64*1024;
6558
6559 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6560 if (ret) {
6561 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6562 goto fail_locked;
e7b526bb
CW		 6563 }
6564
d9e86c0e
CW		 6565 ret = i915_gem_object_put_fence(obj);
6566 if (ret) {
2da3b9b9 6567 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6568 goto fail_unpin;
6569 }
6570
05394f39 6571 addr = obj->gtt_offset;
71acb5eb 6572 } else {
6eeefaf3 6573 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6574 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6575 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6576 align);
71acb5eb
DA		 6577 if (ret) {
6578 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6579 goto fail_locked;
71acb5eb 6580 }
05394f39 6581 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6582 }
6583
a6c45cf0 6584 if (IS_GEN2(dev))
14b60391
JB		 6585 I915_WRITE(CURSIZE, (height << 12) | width);
6586
3f8bc370 6587 finish:
3f8bc370 6588 if (intel_crtc->cursor_bo) {
b295d1b6 6589 if (dev_priv->info->cursor_needs_physical) {
05394f39 6590 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6591 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6592 } else
6593 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6594 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6595 }
80824003 6596
7f9872e0 6597 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6598
6599 intel_crtc->cursor_addr = addr;
05394f39 6600 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6601 intel_crtc->cursor_width = width;
6602 intel_crtc->cursor_height = height;
6603
40ccc72b 6604 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6605
79e53945 6606 return 0;
e7b526bb 6607fail_unpin:
05394f39 6608 i915_gem_object_unpin(obj);
7f9872e0 6609fail_locked:
34b8686e 6610 mutex_unlock(&dev->struct_mutex);
bc9025bd 6611fail:
05394f39 6612 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6613 return ret;
79e53945
JB		 6614}
6615
6616static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6617{
79e53945 6618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6619
cda4b7d3
CW		 6620 intel_crtc->cursor_x = x;
6621 intel_crtc->cursor_y = y;
652c393a 6622
40ccc72b 6623 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6624
6625 return 0;
6626}
6627
6628/** Sets the color ramps on behalf of RandR */
6629void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6630 u16 blue, int regno)
6631{
6632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6633
6634 intel_crtc->lut_r[regno] = red >> 8;
6635 intel_crtc->lut_g[regno] = green >> 8;
6636 intel_crtc->lut_b[regno] = blue >> 8;
6637}
6638
b8c00ac5
DA		 6639void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6640 u16 *blue, int regno)
6641{
6642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643
6644 *red = intel_crtc->lut_r[regno] << 8;
6645 *green = intel_crtc->lut_g[regno] << 8;
6646 *blue = intel_crtc->lut_b[regno] << 8;
6647}
6648
79e53945 6649static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6650 u16 *blue, uint32_t start, uint32_t size)
79e53945 6651{
7203425a 6652 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6654
7203425a 6655 for (i = start; i < end; i++) {
79e53945
JB		 6656 intel_crtc->lut_r[i] = red[i] >> 8;
6657 intel_crtc->lut_g[i] = green[i] >> 8;
6658 intel_crtc->lut_b[i] = blue[i] >> 8;
6659 }
6660
6661 intel_crtc_load_lut(crtc);
6662}
6663
79e53945
JB		 6664/* VESA 640x480x72Hz mode to set on the pipe */
6665static struct drm_display_mode load_detect_mode = {
6666 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6667 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6668};
6669
d2dff872
CW		 6670static struct drm_framebuffer *
6671intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6672 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6673 struct drm_i915_gem_object *obj)
6674{
6675 struct intel_framebuffer *intel_fb;
6676 int ret;
6677
6678 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6679 if (!intel_fb) {
6680 drm_gem_object_unreference_unlocked(&obj->base);
6681 return ERR_PTR(-ENOMEM);
6682 }
6683
6684 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6685 if (ret) {
6686 drm_gem_object_unreference_unlocked(&obj->base);
6687 kfree(intel_fb);
6688 return ERR_PTR(ret);
6689 }
6690
6691 return &intel_fb->base;
6692}
6693
6694static u32
6695intel_framebuffer_pitch_for_width(int width, int bpp)
6696{
6697 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6698 return ALIGN(pitch, 64);
6699}
6700
6701static u32
6702intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6703{
6704 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6705 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6706}
6707
6708static struct drm_framebuffer *
6709intel_framebuffer_create_for_mode(struct drm_device *dev,
6710 struct drm_display_mode *mode,
6711 int depth, int bpp)
6712{
6713 struct drm_i915_gem_object *obj;
0fed39bd 6714 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6715
6716 obj = i915_gem_alloc_object(dev,
6717 intel_framebuffer_size_for_mode(mode, bpp));
6718 if (obj == NULL)
6719 return ERR_PTR(-ENOMEM);
6720
6721 mode_cmd.width = mode->hdisplay;
6722 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6723 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6724 bpp);
5ca0c34a 6725 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6726
6727 return intel_framebuffer_create(dev, &mode_cmd, obj);
6728}
6729
6730static struct drm_framebuffer *
6731mode_fits_in_fbdev(struct drm_device *dev,
6732 struct drm_display_mode *mode)
6733{
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735 struct drm_i915_gem_object *obj;
6736 struct drm_framebuffer *fb;
6737
6738 if (dev_priv->fbdev == NULL)
6739 return NULL;
6740
6741 obj = dev_priv->fbdev->ifb.obj;
6742 if (obj == NULL)
6743 return NULL;
6744
6745 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6746 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6747 fb->bits_per_pixel))
d2dff872
CW		 6748 return NULL;
6749
01f2c773 6750 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6751 return NULL;
6752
6753 return fb;
6754}
6755
d2434ab7 6756bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6757 struct drm_display_mode *mode,
8261b191 6758 struct intel_load_detect_pipe *old)
79e53945
JB		 6759{
6760 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6761 struct intel_encoder *intel_encoder =
6762 intel_attached_encoder(connector);
79e53945 6763 struct drm_crtc *possible_crtc;
4ef69c7a 6764 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6765 struct drm_crtc *crtc = NULL;
6766 struct drm_device *dev = encoder->dev;
94352cf9 6767 struct drm_framebuffer *fb;
79e53945
JB		 6768 int i = -1;
6769
d2dff872
CW		 6770 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6771 connector->base.id, drm_get_connector_name(connector),
6772 encoder->base.id, drm_get_encoder_name(encoder));
6773
79e53945
JB		 6774 /*
6775 * Algorithm gets a little messy:
7a5e4805 6776 *
79e53945
JB		 6777 * - if the connector already has an assigned crtc, use it (but make
6778 * sure it's on first)
7a5e4805 6779 *
79e53945
JB		 6780 * - try to find the first unused crtc that can drive this connector,
6781 * and use that if we find one
79e53945
JB		 6782 */
6783
6784 /* See if we already have a CRTC for this connector */
6785 if (encoder->crtc) {
6786 crtc = encoder->crtc;
8261b191 6787
7b24056b
DV		 6788 mutex_lock(&crtc->mutex);
6789
24218aac 6790 old->dpms_mode = connector->dpms;
8261b191
CW		 6791 old->load_detect_temp = false;
6792
6793 /* Make sure the crtc and connector are running */
24218aac
DV		 6794 if (connector->dpms != DRM_MODE_DPMS_ON)
6795 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6796
7173188d 6797 return true;
79e53945
JB		 6798 }
6799
6800 /* Find an unused one (if possible) */
6801 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6802 i++;
6803 if (!(encoder->possible_crtcs & (1 << i)))
6804 continue;
6805 if (!possible_crtc->enabled) {
6806 crtc = possible_crtc;
6807 break;
6808 }
79e53945
JB		 6809 }
6810
6811 /*
6812 * If we didn't find an unused CRTC, don't use any.
6813 */
6814 if (!crtc) {
7173188d
CW		 6815 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6816 return false;
79e53945
JB		 6817 }
6818
7b24056b 6819 mutex_lock(&crtc->mutex);
fc303101
DV		 6820 intel_encoder->new_crtc = to_intel_crtc(crtc);
6821 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6822
6823 intel_crtc = to_intel_crtc(crtc);
24218aac 6824 old->dpms_mode = connector->dpms;
8261b191 6825 old->load_detect_temp = true;
d2dff872 6826 old->release_fb = NULL;
79e53945 6827
6492711d
CW		 6828 if (!mode)
6829 mode = &load_detect_mode;
79e53945 6830
d2dff872
CW		 6831 /* We need a framebuffer large enough to accommodate all accesses
6832 * that the plane may generate whilst we perform load detection.
6833 * We can not rely on the fbcon either being present (we get called
6834 * during its initialisation to detect all boot displays, or it may
6835 * not even exist) or that it is large enough to satisfy the
6836 * requested mode.
6837 */
94352cf9
DV		 6838 fb = mode_fits_in_fbdev(dev, mode);
6839 if (fb == NULL) {
d2dff872 6840 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6841 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6842 old->release_fb = fb;
d2dff872
CW		 6843 } else
6844 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6845 if (IS_ERR(fb)) {
d2dff872 6846 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6847 mutex_unlock(&crtc->mutex);
0e8b3d3e 6848 return false;
79e53945 6849 }
79e53945 6850
c0c36b94 6851 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6852 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6853 if (old->release_fb)
6854 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6855 mutex_unlock(&crtc->mutex);
0e8b3d3e 6856 return false;
79e53945 6857 }
7173188d 6858
79e53945 6859 /* let the connector get through one full cycle before testing */
9d0498a2 6860 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6861 return true;
79e53945
JB		 6862}
6863
d2434ab7 6864void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6865 struct intel_load_detect_pipe *old)
79e53945 6866{
d2434ab7
DV		 6867 struct intel_encoder *intel_encoder =
6868 intel_attached_encoder(connector);
4ef69c7a 6869 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6870 struct drm_crtc *crtc = encoder->crtc;
79e53945 6871
d2dff872
CW		 6872 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6873 connector->base.id, drm_get_connector_name(connector),
6874 encoder->base.id, drm_get_encoder_name(encoder));
6875
8261b191 6876 if (old->load_detect_temp) {
fc303101
DV		 6877 to_intel_connector(connector)->new_encoder = NULL;
6878 intel_encoder->new_crtc = NULL;
6879 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6880
36206361
DV		 6881 if (old->release_fb) {
6882 drm_framebuffer_unregister_private(old->release_fb);
6883 drm_framebuffer_unreference(old->release_fb);
6884 }
d2dff872 6885
67c96400 6886 mutex_unlock(&crtc->mutex);
0622a53c 6887 return;
79e53945
JB		 6888 }
6889
c751ce4f 6890 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6891 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6892 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6893
6894 mutex_unlock(&crtc->mutex);
79e53945
JB		 6895}
6896
6897/* Returns the clock of the currently programmed mode of the given pipe. */
6898static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6899{
6900 struct drm_i915_private *dev_priv = dev->dev_private;
6901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6902 int pipe = intel_crtc->pipe;
548f245b 6903 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6904 u32 fp;
6905 intel_clock_t clock;
6906
6907 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6908 fp = I915_READ(FP0(pipe));
79e53945 6909 else
39adb7a5 6910 fp = I915_READ(FP1(pipe));
79e53945
JB		 6911
6912 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6913 if (IS_PINEVIEW(dev)) {
6914 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6915 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6916 } else {
6917 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6918 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6919 }
6920
a6c45cf0 6921 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6922 if (IS_PINEVIEW(dev))
6923 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6924 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6925 else
6926 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6927 DPLL_FPA01_P1_POST_DIV_SHIFT);
6928
6929 switch (dpll & DPLL_MODE_MASK) {
6930 case DPLLB_MODE_DAC_SERIAL:
6931 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6932 5 : 10;
6933 break;
6934 case DPLLB_MODE_LVDS:
6935 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6936 7 : 14;
6937 break;
6938 default:
28c97730 6939 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6940 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6941 return 0;
6942 }
6943
ac58c3f0
DV		 6944 if (IS_PINEVIEW(dev))
6945 pineview_clock(96000, &clock);
6946 else
6947 i9xx_clock(96000, &clock);
79e53945
JB		 6948 } else {
6949 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6950
6951 if (is_lvds) {
6952 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6953 DPLL_FPA01_P1_POST_DIV_SHIFT);
6954 clock.p2 = 14;
6955
6956 if ((dpll & PLL_REF_INPUT_MASK) ==
6957 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6958 /* XXX: might not be 66MHz */
ac58c3f0 6959 i9xx_clock(66000, &clock);
79e53945 6960 } else
ac58c3f0 6961 i9xx_clock(48000, &clock);
79e53945
JB		 6962 } else {
6963 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6964 clock.p1 = 2;
6965 else {
6966 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6967 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6968 }
6969 if (dpll & PLL_P2_DIVIDE_BY_4)
6970 clock.p2 = 4;
6971 else
6972 clock.p2 = 2;
6973
ac58c3f0 6974 i9xx_clock(48000, &clock);
79e53945
JB		 6975 }
6976 }
6977
6978 /* XXX: It would be nice to validate the clocks, but we can't reuse
6979 * i830PllIsValid() because it relies on the xf86_config connector
6980 * configuration being accurate, which it isn't necessarily.
6981 */
6982
6983 return clock.dot;
6984}
6985
6986/** Returns the currently programmed mode of the given pipe. */
6987struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6988 struct drm_crtc *crtc)
6989{
548f245b 6990 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6992 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6993 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6994 int htot = I915_READ(HTOTAL(cpu_transcoder));
6995 int hsync = I915_READ(HSYNC(cpu_transcoder));
6996 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6997 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6998
6999 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7000 if (!mode)
7001 return NULL;
7002
7003 mode->clock = intel_crtc_clock_get(dev, crtc);
7004 mode->hdisplay = (htot & 0xffff) + 1;
7005 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7006 mode->hsync_start = (hsync & 0xffff) + 1;
7007 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7008 mode->vdisplay = (vtot & 0xffff) + 1;
7009 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7010 mode->vsync_start = (vsync & 0xffff) + 1;
7011 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7012
7013 drm_mode_set_name(mode);
79e53945
JB		 7014
7015 return mode;
7016}
7017
3dec0095 7018static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7019{
7020 struct drm_device *dev = crtc->dev;
7021 drm_i915_private_t *dev_priv = dev->dev_private;
7022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7024 int dpll_reg = DPLL(pipe);
7025 int dpll;
652c393a 7026
bad720ff 7027 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7028 return;
7029
7030 if (!dev_priv->lvds_downclock_avail)
7031 return;
7032
dbdc6479 7033 dpll = I915_READ(dpll_reg);
652c393a 7034 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7035 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7036
8ac5a6d5 7037 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7038
7039 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7040 I915_WRITE(dpll_reg, dpll);
9d0498a2 7041 intel_wait_for_vblank(dev, pipe);
dbdc6479 7042
652c393a
JB		 7043 dpll = I915_READ(dpll_reg);
7044 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7045 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7046 }
652c393a
JB		 7047}
7048
7049static void intel_decrease_pllclock(struct drm_crtc *crtc)
7050{
7051 struct drm_device *dev = crtc->dev;
7052 drm_i915_private_t *dev_priv = dev->dev_private;
7053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7054
bad720ff 7055 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7056 return;
7057
7058 if (!dev_priv->lvds_downclock_avail)
7059 return;
7060
7061 /*
7062 * Since this is called by a timer, we should never get here in
7063 * the manual case.
7064 */
7065 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7066 int pipe = intel_crtc->pipe;
7067 int dpll_reg = DPLL(pipe);
7068 int dpll;
f6e5b160 7069
44d98a61 7070 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7071
8ac5a6d5 7072 assert_panel_unlocked(dev_priv, pipe);
652c393a 7073
dc257cf1 7074 dpll = I915_READ(dpll_reg);
652c393a
JB		 7075 dpll |= DISPLAY_RATE_SELECT_FPA1;
7076 I915_WRITE(dpll_reg, dpll);
9d0498a2 7077 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7078 dpll = I915_READ(dpll_reg);
7079 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7080 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7081 }
7082
7083}
7084
f047e395
CW		 7085void intel_mark_busy(struct drm_device *dev)
7086{
f047e395
CW		 7087 i915_update_gfx_val(dev->dev_private);
7088}
7089
7090void intel_mark_idle(struct drm_device *dev)
652c393a 7091{
652c393a 7092 struct drm_crtc *crtc;
652c393a
JB		 7093
7094 if (!i915_powersave)
7095 return;
7096
652c393a 7097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7098 if (!crtc->fb)
7099 continue;
7100
725a5b54 7101 intel_decrease_pllclock(crtc);
652c393a 7102 }
652c393a
JB		 7103}
7104
c65355bb
CW		 7105void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7106 struct intel_ring_buffer *ring)
652c393a 7107{
f047e395
CW		 7108 struct drm_device *dev = obj->base.dev;
7109 struct drm_crtc *crtc;
652c393a 7110
f047e395 7111 if (!i915_powersave)
acb87dfb
CW		 7112 return;
7113
652c393a
JB		 7114 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7115 if (!crtc->fb)
7116 continue;
7117
c65355bb
CW		 7118 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7119 continue;
7120
7121 intel_increase_pllclock(crtc);
7122 if (ring && intel_fbc_enabled(dev))
7123 ring->fbc_dirty = true;
652c393a
JB		 7124 }
7125}
7126
79e53945
JB		 7127static void intel_crtc_destroy(struct drm_crtc *crtc)
7128{
7129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7130 struct drm_device *dev = crtc->dev;
7131 struct intel_unpin_work *work;
7132 unsigned long flags;
7133
7134 spin_lock_irqsave(&dev->event_lock, flags);
7135 work = intel_crtc->unpin_work;
7136 intel_crtc->unpin_work = NULL;
7137 spin_unlock_irqrestore(&dev->event_lock, flags);
7138
7139 if (work) {
7140 cancel_work_sync(&work->work);
7141 kfree(work);
7142 }
79e53945 7143
40ccc72b
MK		 7144 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7145
79e53945 7146 drm_crtc_cleanup(crtc);
67e77c5a 7147
79e53945
JB		 7148 kfree(intel_crtc);
7149}
7150
6b95a207
KH		 7151static void intel_unpin_work_fn(struct work_struct *__work)
7152{
7153 struct intel_unpin_work *work =
7154 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7155 struct drm_device *dev = work->crtc->dev;
6b95a207 7156
b4a98e57 7157 mutex_lock(&dev->struct_mutex);
1690e1eb 7158 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7159 drm_gem_object_unreference(&work->pending_flip_obj->base);
7160 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7161
b4a98e57
CW		 7162 intel_update_fbc(dev);
7163 mutex_unlock(&dev->struct_mutex);
7164
7165 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7166 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7167
6b95a207
KH		 7168 kfree(work);
7169}
7170
1afe3e9d 7171static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7172 struct drm_crtc *crtc)
6b95a207
KH		 7173{
7174 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7176 struct intel_unpin_work *work;
6b95a207
KH		 7177 unsigned long flags;
7178
7179 /* Ignore early vblank irqs */
7180 if (intel_crtc == NULL)
7181 return;
7182
7183 spin_lock_irqsave(&dev->event_lock, flags);
7184 work = intel_crtc->unpin_work;
e7d841ca
CW		 7185
7186 /* Ensure we don't miss a work->pending update ... */
7187 smp_rmb();
7188
7189 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7190 spin_unlock_irqrestore(&dev->event_lock, flags);
7191 return;
7192 }
7193
e7d841ca
CW		 7194 /* and that the unpin work is consistent wrt ->pending. */
7195 smp_rmb();
7196
6b95a207 7197 intel_crtc->unpin_work = NULL;
6b95a207 7198
45a066eb
RC		 7199 if (work->event)
7200 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7201
0af7e4df
MK		 7202 drm_vblank_put(dev, intel_crtc->pipe);
7203
6b95a207
KH		 7204 spin_unlock_irqrestore(&dev->event_lock, flags);
7205
2c10d571 7206 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7207
7208 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7209
7210 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7211}
7212
1afe3e9d
JB		 7213void intel_finish_page_flip(struct drm_device *dev, int pipe)
7214{
7215 drm_i915_private_t *dev_priv = dev->dev_private;
7216 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7217
49b14a5c 7218 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7219}
7220
7221void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7222{
7223 drm_i915_private_t *dev_priv = dev->dev_private;
7224 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7225
49b14a5c 7226 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7227}
7228
6b95a207
KH		 7229void intel_prepare_page_flip(struct drm_device *dev, int plane)
7230{
7231 drm_i915_private_t *dev_priv = dev->dev_private;
7232 struct intel_crtc *intel_crtc =
7233 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7234 unsigned long flags;
7235
e7d841ca
CW		 7236 /* NB: An MMIO update of the plane base pointer will also
7237 * generate a page-flip completion irq, i.e. every modeset
7238 * is also accompanied by a spurious intel_prepare_page_flip().
7239 */
6b95a207 7240 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7241 if (intel_crtc->unpin_work)
7242 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7243 spin_unlock_irqrestore(&dev->event_lock, flags);
7244}
7245
e7d841ca
CW		 7246inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7247{
7248 /* Ensure that the work item is consistent when activating it ... */
7249 smp_wmb();
7250 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7251 /* and that it is marked active as soon as the irq could fire. */
7252 smp_wmb();
7253}
7254
8c9f3aaf
JB		 7255static int intel_gen2_queue_flip(struct drm_device *dev,
7256 struct drm_crtc *crtc,
7257 struct drm_framebuffer *fb,
7258 struct drm_i915_gem_object *obj)
7259{
7260 struct drm_i915_private *dev_priv = dev->dev_private;
7261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7262 u32 flip_mask;
6d90c952 7263 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7264 int ret;
7265
6d90c952 7266 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7267 if (ret)
83d4092b 7268 goto err;
8c9f3aaf 7269
6d90c952 7270 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7271 if (ret)
83d4092b 7272 goto err_unpin;
8c9f3aaf
JB		 7273
7274 /* Can't queue multiple flips, so wait for the previous
7275 * one to finish before executing the next.
7276 */
7277 if (intel_crtc->plane)
7278 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7279 else
7280 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7281 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7282 intel_ring_emit(ring, MI_NOOP);
7283 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7284 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7285 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7286 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7287 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7288
7289 intel_mark_page_flip_active(intel_crtc);
6d90c952 7290 intel_ring_advance(ring);
83d4092b
CW		 7291 return 0;
7292
7293err_unpin:
7294 intel_unpin_fb_obj(obj);
7295err:
8c9f3aaf
JB		 7296 return ret;
7297}
7298
7299static int intel_gen3_queue_flip(struct drm_device *dev,
7300 struct drm_crtc *crtc,
7301 struct drm_framebuffer *fb,
7302 struct drm_i915_gem_object *obj)
7303{
7304 struct drm_i915_private *dev_priv = dev->dev_private;
7305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7306 u32 flip_mask;
6d90c952 7307 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7308 int ret;
7309
6d90c952 7310 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7311 if (ret)
83d4092b 7312 goto err;
8c9f3aaf 7313
6d90c952 7314 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7315 if (ret)
83d4092b 7316 goto err_unpin;
8c9f3aaf
JB		 7317
7318 if (intel_crtc->plane)
7319 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7320 else
7321 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7322 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7323 intel_ring_emit(ring, MI_NOOP);
7324 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7326 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7327 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7328 intel_ring_emit(ring, MI_NOOP);
7329
e7d841ca 7330 intel_mark_page_flip_active(intel_crtc);
6d90c952 7331 intel_ring_advance(ring);
83d4092b
CW		 7332 return 0;
7333
7334err_unpin:
7335 intel_unpin_fb_obj(obj);
7336err:
8c9f3aaf
JB		 7337 return ret;
7338}
7339
7340static int intel_gen4_queue_flip(struct drm_device *dev,
7341 struct drm_crtc *crtc,
7342 struct drm_framebuffer *fb,
7343 struct drm_i915_gem_object *obj)
7344{
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7347 uint32_t pf, pipesrc;
6d90c952 7348 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7349 int ret;
7350
6d90c952 7351 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7352 if (ret)
83d4092b 7353 goto err;
8c9f3aaf 7354
6d90c952 7355 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7356 if (ret)
83d4092b 7357 goto err_unpin;
8c9f3aaf
JB		 7358
7359 /* i965+ uses the linear or tiled offsets from the
7360 * Display Registers (which do not change across a page-flip)
7361 * so we need only reprogram the base address.
7362 */
6d90c952
DV		 7363 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7364 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7365 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7366 intel_ring_emit(ring,
7367 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7368 obj->tiling_mode);
8c9f3aaf
JB		 7369
7370 /* XXX Enabling the panel-fitter across page-flip is so far
7371 * untested on non-native modes, so ignore it for now.
7372 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7373 */
7374 pf = 0;
7375 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7376 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7377
7378 intel_mark_page_flip_active(intel_crtc);
6d90c952 7379 intel_ring_advance(ring);
83d4092b
CW		 7380 return 0;
7381
7382err_unpin:
7383 intel_unpin_fb_obj(obj);
7384err:
8c9f3aaf
JB		 7385 return ret;
7386}
7387
7388static int intel_gen6_queue_flip(struct drm_device *dev,
7389 struct drm_crtc *crtc,
7390 struct drm_framebuffer *fb,
7391 struct drm_i915_gem_object *obj)
7392{
7393 struct drm_i915_private *dev_priv = dev->dev_private;
7394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7395 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7396 uint32_t pf, pipesrc;
7397 int ret;
7398
6d90c952 7399 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7400 if (ret)
83d4092b 7401 goto err;
8c9f3aaf 7402
6d90c952 7403 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7404 if (ret)
83d4092b 7405 goto err_unpin;
8c9f3aaf 7406
6d90c952
DV		 7407 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7408 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7409 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7410 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7411
dc257cf1
DV		 7412 /* Contrary to the suggestions in the documentation,
7413 * "Enable Panel Fitter" does not seem to be required when page
7414 * flipping with a non-native mode, and worse causes a normal
7415 * modeset to fail.
7416 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7417 */
7418 pf = 0;
8c9f3aaf 7419 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7420 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7421
7422 intel_mark_page_flip_active(intel_crtc);
6d90c952 7423 intel_ring_advance(ring);
83d4092b
CW		 7424 return 0;
7425
7426err_unpin:
7427 intel_unpin_fb_obj(obj);
7428err:
8c9f3aaf
JB		 7429 return ret;
7430}
7431
7c9017e5
JB		 7432/*
7433 * On gen7 we currently use the blit ring because (in early silicon at least)
7434 * the render ring doesn't give us interrpts for page flip completion, which
7435 * means clients will hang after the first flip is queued. Fortunately the
7436 * blit ring generates interrupts properly, so use it instead.
7437 */
7438static int intel_gen7_queue_flip(struct drm_device *dev,
7439 struct drm_crtc *crtc,
7440 struct drm_framebuffer *fb,
7441 struct drm_i915_gem_object *obj)
7442{
7443 struct drm_i915_private *dev_priv = dev->dev_private;
7444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7445 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7446 uint32_t plane_bit = 0;
7c9017e5
JB		 7447 int ret;
7448
7449 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7450 if (ret)
83d4092b 7451 goto err;
7c9017e5 7452
cb05d8de
DV		 7453 switch(intel_crtc->plane) {
7454 case PLANE_A:
7455 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7456 break;
7457 case PLANE_B:
7458 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7459 break;
7460 case PLANE_C:
7461 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7462 break;
7463 default:
7464 WARN_ONCE(1, "unknown plane in flip command\n");
7465 ret = -ENODEV;
ab3951eb 7466 goto err_unpin;
cb05d8de
DV		 7467 }
7468
7c9017e5
JB		 7469 ret = intel_ring_begin(ring, 4);
7470 if (ret)
83d4092b 7471 goto err_unpin;
7c9017e5 7472
cb05d8de 7473 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7474 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7475 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7476 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7477
7478 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7479 intel_ring_advance(ring);
83d4092b
CW		 7480 return 0;
7481
7482err_unpin:
7483 intel_unpin_fb_obj(obj);
7484err:
7c9017e5
JB		 7485 return ret;
7486}
7487
8c9f3aaf
JB		 7488static int intel_default_queue_flip(struct drm_device *dev,
7489 struct drm_crtc *crtc,
7490 struct drm_framebuffer *fb,
7491 struct drm_i915_gem_object *obj)
7492{
7493 return -ENODEV;
7494}
7495
6b95a207
KH		 7496static int intel_crtc_page_flip(struct drm_crtc *crtc,
7497 struct drm_framebuffer *fb,
7498 struct drm_pending_vblank_event *event)
7499{
7500 struct drm_device *dev = crtc->dev;
7501 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7502 struct drm_framebuffer *old_fb = crtc->fb;
7503 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7505 struct intel_unpin_work *work;
8c9f3aaf 7506 unsigned long flags;
52e68630 7507 int ret;
6b95a207 7508
e6a595d2
VS		 7509 /* Can't change pixel format via MI display flips. */
7510 if (fb->pixel_format != crtc->fb->pixel_format)
7511 return -EINVAL;
7512
7513 /*
7514 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7515 * Note that pitch changes could also affect these register.
7516 */
7517 if (INTEL_INFO(dev)->gen > 3 &&
7518 (fb->offsets[0] != crtc->fb->offsets[0] ||
7519 fb->pitches[0] != crtc->fb->pitches[0]))
7520 return -EINVAL;
7521
6b95a207
KH		 7522 work = kzalloc(sizeof *work, GFP_KERNEL);
7523 if (work == NULL)
7524 return -ENOMEM;
7525
6b95a207 7526 work->event = event;
b4a98e57 7527 work->crtc = crtc;
4a35f83b 7528 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7529 INIT_WORK(&work->work, intel_unpin_work_fn);
7530
7317c75e
JB		 7531 ret = drm_vblank_get(dev, intel_crtc->pipe);
7532 if (ret)
7533 goto free_work;
7534
6b95a207
KH		 7535 /* We borrow the event spin lock for protecting unpin_work */
7536 spin_lock_irqsave(&dev->event_lock, flags);
7537 if (intel_crtc->unpin_work) {
7538 spin_unlock_irqrestore(&dev->event_lock, flags);
7539 kfree(work);
7317c75e 7540 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7541
7542 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7543 return -EBUSY;
7544 }
7545 intel_crtc->unpin_work = work;
7546 spin_unlock_irqrestore(&dev->event_lock, flags);
7547
b4a98e57
CW		 7548 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7549 flush_workqueue(dev_priv->wq);
7550
79158103
CW		 7551 ret = i915_mutex_lock_interruptible(dev);
7552 if (ret)
7553 goto cleanup;
6b95a207 7554
75dfca80 7555 /* Reference the objects for the scheduled work. */
05394f39
CW		 7556 drm_gem_object_reference(&work->old_fb_obj->base);
7557 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7558
7559 crtc->fb = fb;
96b099fd 7560
e1f99ce6 7561 work->pending_flip_obj = obj;
e1f99ce6 7562
4e5359cd
SF		 7563 work->enable_stall_check = true;
7564
b4a98e57 7565 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7566 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7567
8c9f3aaf
JB		 7568 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7569 if (ret)
7570 goto cleanup_pending;
6b95a207 7571
7782de3b 7572 intel_disable_fbc(dev);
c65355bb 7573 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7574 mutex_unlock(&dev->struct_mutex);
7575
e5510fac
JB		 7576 trace_i915_flip_request(intel_crtc->plane, obj);
7577
6b95a207 7578 return 0;
96b099fd 7579
8c9f3aaf 7580cleanup_pending:
b4a98e57 7581 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7582 crtc->fb = old_fb;
05394f39
CW		 7583 drm_gem_object_unreference(&work->old_fb_obj->base);
7584 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7585 mutex_unlock(&dev->struct_mutex);
7586
79158103 7587cleanup:
96b099fd
CW		 7588 spin_lock_irqsave(&dev->event_lock, flags);
7589 intel_crtc->unpin_work = NULL;
7590 spin_unlock_irqrestore(&dev->event_lock, flags);
7591
7317c75e
JB		 7592 drm_vblank_put(dev, intel_crtc->pipe);
7593free_work:
96b099fd
CW		 7594 kfree(work);
7595
7596 return ret;
6b95a207
KH		 7597}
7598
f6e5b160 7599static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7600 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7601 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7602};
7603
50f56119
DV		 7604static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7605 struct drm_crtc *crtc)
7606{
7607 struct drm_device *dev;
7608 struct drm_crtc *tmp;
7609 int crtc_mask = 1;
47f1c6c9 7610
50f56119 7611 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7612
50f56119 7613 dev = crtc->dev;
47f1c6c9 7614
50f56119
DV		 7615 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7616 if (tmp == crtc)
7617 break;
7618 crtc_mask <<= 1;
7619 }
47f1c6c9 7620
50f56119
DV		 7621 if (encoder->possible_crtcs & crtc_mask)
7622 return true;
7623 return false;
47f1c6c9 7624}
79e53945 7625
9a935856
DV		 7626/**
7627 * intel_modeset_update_staged_output_state
7628 *
7629 * Updates the staged output configuration state, e.g. after we've read out the
7630 * current hw state.
7631 */
7632static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7633{
9a935856
DV		 7634 struct intel_encoder *encoder;
7635 struct intel_connector *connector;
f6e5b160 7636
9a935856
DV		 7637 list_for_each_entry(connector, &dev->mode_config.connector_list,
7638 base.head) {
7639 connector->new_encoder =
7640 to_intel_encoder(connector->base.encoder);
7641 }
f6e5b160 7642
9a935856
DV		 7643 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7644 base.head) {
7645 encoder->new_crtc =
7646 to_intel_crtc(encoder->base.crtc);
7647 }
f6e5b160
CW		 7648}
7649
9a935856
DV		 7650/**
7651 * intel_modeset_commit_output_state
7652 *
7653 * This function copies the stage display pipe configuration to the real one.
7654 */
7655static void intel_modeset_commit_output_state(struct drm_device *dev)
7656{
7657 struct intel_encoder *encoder;
7658 struct intel_connector *connector;
f6e5b160 7659
9a935856
DV		 7660 list_for_each_entry(connector, &dev->mode_config.connector_list,
7661 base.head) {
7662 connector->base.encoder = &connector->new_encoder->base;
7663 }
f6e5b160 7664
9a935856
DV		 7665 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7666 base.head) {
7667 encoder->base.crtc = &encoder->new_crtc->base;
7668 }
7669}
7670
050f7aeb
DV		 7671static void
7672connected_sink_compute_bpp(struct intel_connector * connector,
7673 struct intel_crtc_config *pipe_config)
7674{
7675 int bpp = pipe_config->pipe_bpp;
7676
7677 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7678 connector->base.base.id,
7679 drm_get_connector_name(&connector->base));
7680
7681 /* Don't use an invalid EDID bpc value */
7682 if (connector->base.display_info.bpc &&
7683 connector->base.display_info.bpc * 3 < bpp) {
7684 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7685 bpp, connector->base.display_info.bpc*3);
7686 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7687 }
7688
7689 /* Clamp bpp to 8 on screens without EDID 1.4 */
7690 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7691 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7692 bpp);
7693 pipe_config->pipe_bpp = 24;
7694 }
7695}
7696
4e53c2e0 7697static int
050f7aeb
DV		 7698compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7699 struct drm_framebuffer *fb,
7700 struct intel_crtc_config *pipe_config)
4e53c2e0 7701{
050f7aeb
DV		 7702 struct drm_device *dev = crtc->base.dev;
7703 struct intel_connector *connector;
4e53c2e0
DV		 7704 int bpp;
7705
d42264b1
DV		 7706 switch (fb->pixel_format) {
7707 case DRM_FORMAT_C8:
4e53c2e0
DV		 7708 bpp = 8*3; /* since we go through a colormap */
7709 break;
d42264b1
DV		 7710 case DRM_FORMAT_XRGB1555:
7711 case DRM_FORMAT_ARGB1555:
7712 /* checked in intel_framebuffer_init already */
7713 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7714 return -EINVAL;
7715 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7716 bpp = 6*3; /* min is 18bpp */
7717 break;
d42264b1
DV		 7718 case DRM_FORMAT_XBGR8888:
7719 case DRM_FORMAT_ABGR8888:
7720 /* checked in intel_framebuffer_init already */
7721 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7722 return -EINVAL;
7723 case DRM_FORMAT_XRGB8888:
7724 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7725 bpp = 8*3;
7726 break;
d42264b1
DV		 7727 case DRM_FORMAT_XRGB2101010:
7728 case DRM_FORMAT_ARGB2101010:
7729 case DRM_FORMAT_XBGR2101010:
7730 case DRM_FORMAT_ABGR2101010:
7731 /* checked in intel_framebuffer_init already */
7732 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7733 return -EINVAL;
4e53c2e0
DV		 7734 bpp = 10*3;
7735 break;
baba133a 7736 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7737 default:
7738 DRM_DEBUG_KMS("unsupported depth\n");
7739 return -EINVAL;
7740 }
7741
4e53c2e0
DV		 7742 pipe_config->pipe_bpp = bpp;
7743
7744 /* Clamp display bpp to EDID value */
7745 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7746 base.head) {
1b829e05
DV		 7747 if (!connector->new_encoder ||
7748 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7749 continue;
7750
050f7aeb 7751 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7752 }
7753
7754 return bpp;
7755}
7756
c0b03411
DV		 7757static void intel_dump_pipe_config(struct intel_crtc *crtc,
7758 struct intel_crtc_config *pipe_config,
7759 const char *context)
7760{
7761 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7762 context, pipe_name(crtc->pipe));
7763
7764 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7765 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7766 pipe_config->pipe_bpp, pipe_config->dither);
7767 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7768 pipe_config->has_pch_encoder,
7769 pipe_config->fdi_lanes,
7770 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7771 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7772 pipe_config->fdi_m_n.tu);
7773 DRM_DEBUG_KMS("requested mode:\n");
7774 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7775 DRM_DEBUG_KMS("adjusted mode:\n");
7776 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7777 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7778 pipe_config->gmch_pfit.control,
7779 pipe_config->gmch_pfit.pgm_ratios,
7780 pipe_config->gmch_pfit.lvds_border_bits);
7781 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7782 pipe_config->pch_pfit.pos,
7783 pipe_config->pch_pfit.size);
42db64ef 7784 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7785}
7786
accfc0c5
DV		 7787static bool check_encoder_cloning(struct drm_crtc *crtc)
7788{
7789 int num_encoders = 0;
7790 bool uncloneable_encoders = false;
7791 struct intel_encoder *encoder;
7792
7793 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7794 base.head) {
7795 if (&encoder->new_crtc->base != crtc)
7796 continue;
7797
7798 num_encoders++;
7799 if (!encoder->cloneable)
7800 uncloneable_encoders = true;
7801 }
7802
7803 return !(num_encoders > 1 && uncloneable_encoders);
7804}
7805
b8cecdf5
DV		 7806static struct intel_crtc_config *
7807intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7808 struct drm_framebuffer *fb,
b8cecdf5 7809 struct drm_display_mode *mode)
ee7b9f93 7810{
7758a113 7811 struct drm_device *dev = crtc->dev;
7758a113
DV		 7812 struct drm_encoder_helper_funcs *encoder_funcs;
7813 struct intel_encoder *encoder;
b8cecdf5 7814 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7815 int plane_bpp, ret = -EINVAL;
7816 bool retry = true;
ee7b9f93 7817
accfc0c5
DV		 7818 if (!check_encoder_cloning(crtc)) {
7819 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7820 return ERR_PTR(-EINVAL);
7821 }
7822
b8cecdf5
DV		 7823 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7824 if (!pipe_config)
7758a113
DV		 7825 return ERR_PTR(-ENOMEM);
7826
b8cecdf5
DV		 7827 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7828 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7829 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7830 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7831
050f7aeb
DV		 7832 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7833 * plane pixel format and any sink constraints into account. Returns the
7834 * source plane bpp so that dithering can be selected on mismatches
7835 * after encoders and crtc also have had their say. */
7836 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7837 fb, pipe_config);
4e53c2e0
DV		 7838 if (plane_bpp < 0)
7839 goto fail;
7840
e29c22c0 7841encoder_retry:
ef1b460d 7842 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7843 pipe_config->port_clock = 0;
ef1b460d 7844 pipe_config->pixel_multiplier = 1;
ff9a6750 7845
7758a113
DV		 7846 /* Pass our mode to the connectors and the CRTC to give them a chance to
7847 * adjust it according to limitations or connector properties, and also
7848 * a chance to reject the mode entirely.
47f1c6c9 7849 */
7758a113
DV		 7850 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7851 base.head) {
47f1c6c9 7852
7758a113
DV		 7853 if (&encoder->new_crtc->base != crtc)
7854 continue;
7ae89233
DV		 7855
7856 if (encoder->compute_config) {
7857 if (!(encoder->compute_config(encoder, pipe_config))) {
7858 DRM_DEBUG_KMS("Encoder config failure\n");
7859 goto fail;
7860 }
7861
7862 continue;
7863 }
7864
7758a113 7865 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7866 if (!(encoder_funcs->mode_fixup(&encoder->base,
7867 &pipe_config->requested_mode,
7868 &pipe_config->adjusted_mode))) {
7758a113
DV		 7869 DRM_DEBUG_KMS("Encoder fixup failed\n");
7870 goto fail;
7871 }
ee7b9f93 7872 }
47f1c6c9 7873
ff9a6750
DV		 7874 /* Set default port clock if not overwritten by the encoder. Needs to be
7875 * done afterwards in case the encoder adjusts the mode. */
7876 if (!pipe_config->port_clock)
7877 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7878
a43f6e0f 7879 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7880 if (ret < 0) {
7758a113
DV		 7881 DRM_DEBUG_KMS("CRTC fixup failed\n");
7882 goto fail;
ee7b9f93 7883 }
e29c22c0
DV		 7884
7885 if (ret == RETRY) {
7886 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7887 ret = -EINVAL;
7888 goto fail;
7889 }
7890
7891 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7892 retry = false;
7893 goto encoder_retry;
7894 }
7895
4e53c2e0
DV		 7896 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7897 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7898 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7899
b8cecdf5 7900 return pipe_config;
7758a113 7901fail:
b8cecdf5 7902 kfree(pipe_config);
e29c22c0 7903 return ERR_PTR(ret);
ee7b9f93 7904}
47f1c6c9 7905
e2e1ed41
DV		 7906/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7907 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7908static void
7909intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7910 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7911{
7912 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7913 struct drm_device *dev = crtc->dev;
7914 struct intel_encoder *encoder;
7915 struct intel_connector *connector;
7916 struct drm_crtc *tmp_crtc;
79e53945 7917
e2e1ed41 7918 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7919
e2e1ed41
DV		 7920 /* Check which crtcs have changed outputs connected to them, these need
7921 * to be part of the prepare_pipes mask. We don't (yet) support global
7922 * modeset across multiple crtcs, so modeset_pipes will only have one
7923 * bit set at most. */
7924 list_for_each_entry(connector, &dev->mode_config.connector_list,
7925 base.head) {
7926 if (connector->base.encoder == &connector->new_encoder->base)
7927 continue;
79e53945 7928
e2e1ed41
DV		 7929 if (connector->base.encoder) {
7930 tmp_crtc = connector->base.encoder->crtc;
7931
7932 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7933 }
7934
7935 if (connector->new_encoder)
7936 *prepare_pipes |=
7937 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7938 }
7939
e2e1ed41
DV		 7940 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7941 base.head) {
7942 if (encoder->base.crtc == &encoder->new_crtc->base)
7943 continue;
7944
7945 if (encoder->base.crtc) {
7946 tmp_crtc = encoder->base.crtc;
7947
7948 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7949 }
7950
7951 if (encoder->new_crtc)
7952 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7953 }
7954
e2e1ed41
DV		 7955 /* Check for any pipes that will be fully disabled ... */
7956 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7957 base.head) {
7958 bool used = false;
22fd0fab 7959
e2e1ed41
DV		 7960 /* Don't try to disable disabled crtcs. */
7961 if (!intel_crtc->base.enabled)
7962 continue;
7e7d76c3 7963
e2e1ed41
DV		 7964 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7965 base.head) {
7966 if (encoder->new_crtc == intel_crtc)
7967 used = true;
7968 }
7969
7970 if (!used)
7971 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7972 }
7973
e2e1ed41
DV		 7974
7975 /* set_mode is also used to update properties on life display pipes. */
7976 intel_crtc = to_intel_crtc(crtc);
7977 if (crtc->enabled)
7978 *prepare_pipes |= 1 << intel_crtc->pipe;
7979
b6c5164d
DV		 7980 /*
7981 * For simplicity do a full modeset on any pipe where the output routing
7982 * changed. We could be more clever, but that would require us to be
7983 * more careful with calling the relevant encoder->mode_set functions.
7984 */
e2e1ed41
DV		 7985 if (*prepare_pipes)
7986 *modeset_pipes = *prepare_pipes;
7987
7988 /* ... and mask these out. */
7989 *modeset_pipes &= ~(*disable_pipes);
7990 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7991
7992 /*
7993 * HACK: We don't (yet) fully support global modesets. intel_set_config
7994 * obies this rule, but the modeset restore mode of
7995 * intel_modeset_setup_hw_state does not.
7996 */
7997 *modeset_pipes &= 1 << intel_crtc->pipe;
7998 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7999
8000 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8001 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8002}
79e53945 8003
ea9d758d 8004static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8005{
ea9d758d 8006 struct drm_encoder *encoder;
f6e5b160 8007 struct drm_device *dev = crtc->dev;
f6e5b160 8008
ea9d758d
DV		 8009 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8010 if (encoder->crtc == crtc)
8011 return true;
8012
8013 return false;
8014}
8015
8016static void
8017intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8018{
8019 struct intel_encoder *intel_encoder;
8020 struct intel_crtc *intel_crtc;
8021 struct drm_connector *connector;
8022
8023 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8024 base.head) {
8025 if (!intel_encoder->base.crtc)
8026 continue;
8027
8028 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8029
8030 if (prepare_pipes & (1 << intel_crtc->pipe))
8031 intel_encoder->connectors_active = false;
8032 }
8033
8034 intel_modeset_commit_output_state(dev);
8035
8036 /* Update computed state. */
8037 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8038 base.head) {
8039 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8040 }
8041
8042 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8043 if (!connector->encoder || !connector->encoder->crtc)
8044 continue;
8045
8046 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8047
8048 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8049 struct drm_property *dpms_property =
8050 dev->mode_config.dpms_property;
8051
ea9d758d 8052 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8053 drm_object_property_set_value(&connector->base,
68d34720
DV		 8054 dpms_property,
8055 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8056
8057 intel_encoder = to_intel_encoder(connector->encoder);
8058 intel_encoder->connectors_active = true;
8059 }
8060 }
8061
8062}
8063
25c5b266
DV		 8064#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8065 list_for_each_entry((intel_crtc), \
8066 &(dev)->mode_config.crtc_list, \
8067 base.head) \
0973f18f 8068 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8069
0e8ffe1b 8070static bool
2fa2fe9a
DV		 8071intel_pipe_config_compare(struct drm_device *dev,
8072 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8073 struct intel_crtc_config *pipe_config)
8074{
66e985c0
DV		 8075#define PIPE_CONF_CHECK_X(name) \
8076 if (current_config->name != pipe_config->name) { \
8077 DRM_ERROR("mismatch in " #name " " \
8078 "(expected 0x%08x, found 0x%08x)\n", \
8079 current_config->name, \
8080 pipe_config->name); \
8081 return false; \
8082 }
8083
08a24034
DV		 8084#define PIPE_CONF_CHECK_I(name) \
8085 if (current_config->name != pipe_config->name) { \
8086 DRM_ERROR("mismatch in " #name " " \
8087 "(expected %i, found %i)\n", \
8088 current_config->name, \
8089 pipe_config->name); \
8090 return false; \
88adfff1
DV		 8091 }
8092
1bd1bd80
DV		 8093#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8094 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8095 DRM_ERROR("mismatch in " #name " " \
8096 "(expected %i, found %i)\n", \
8097 current_config->name & (mask), \
8098 pipe_config->name & (mask)); \
8099 return false; \
8100 }
8101
bb760063
DV		 8102#define PIPE_CONF_QUIRK(quirk) \
8103 ((current_config->quirks | pipe_config->quirks) & (quirk))
8104
eccb140b
DV		 8105 PIPE_CONF_CHECK_I(cpu_transcoder);
8106
08a24034
DV		 8107 PIPE_CONF_CHECK_I(has_pch_encoder);
8108 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8109 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8110 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8111 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8112 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8113 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8114
1bd1bd80
DV		 8115 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8116 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8117 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8118 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8119 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8120 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8121
8122 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8123 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8124 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8125 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8126 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8127 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8128
6c49f241
DV		 8129 if (!HAS_PCH_SPLIT(dev))
8130 PIPE_CONF_CHECK_I(pixel_multiplier);
8131
1bd1bd80
DV		 8132 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8133 DRM_MODE_FLAG_INTERLACE);
8134
bb760063
DV		 8135 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8136 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8137 DRM_MODE_FLAG_PHSYNC);
8138 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8139 DRM_MODE_FLAG_NHSYNC);
8140 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8141 DRM_MODE_FLAG_PVSYNC);
8142 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8143 DRM_MODE_FLAG_NVSYNC);
8144 }
045ac3b5 8145
1bd1bd80
DV		 8146 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8147 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8148
2fa2fe9a
DV		 8149 PIPE_CONF_CHECK_I(gmch_pfit.control);
8150 /* pfit ratios are autocomputed by the hw on gen4+ */
8151 if (INTEL_INFO(dev)->gen < 4)
8152 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8153 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8154 PIPE_CONF_CHECK_I(pch_pfit.pos);
8155 PIPE_CONF_CHECK_I(pch_pfit.size);
8156
42db64ef
PZ		 8157 PIPE_CONF_CHECK_I(ips_enabled);
8158
c0d43d62 8159 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0
DV		 8160 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8161 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8162 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8163
66e985c0 8164#undef PIPE_CONF_CHECK_X
08a24034 8165#undef PIPE_CONF_CHECK_I
1bd1bd80 8166#undef PIPE_CONF_CHECK_FLAGS
bb760063 8167#undef PIPE_CONF_QUIRK
627eb5a3 8168
0e8ffe1b
DV		 8169 return true;
8170}
8171
91d1b4bd
DV		 8172static void
8173check_connector_state(struct drm_device *dev)
8af6cf88 8174{
8af6cf88
DV		 8175 struct intel_connector *connector;
8176
8177 list_for_each_entry(connector, &dev->mode_config.connector_list,
8178 base.head) {
8179 /* This also checks the encoder/connector hw state with the
8180 * ->get_hw_state callbacks. */
8181 intel_connector_check_state(connector);
8182
8183 WARN(&connector->new_encoder->base != connector->base.encoder,
8184 "connector's staged encoder doesn't match current encoder\n");
8185 }
91d1b4bd
DV		 8186}
8187
8188static void
8189check_encoder_state(struct drm_device *dev)
8190{
8191 struct intel_encoder *encoder;
8192 struct intel_connector *connector;
8af6cf88
DV		 8193
8194 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8195 base.head) {
8196 bool enabled = false;
8197 bool active = false;
8198 enum pipe pipe, tracked_pipe;
8199
8200 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8201 encoder->base.base.id,
8202 drm_get_encoder_name(&encoder->base));
8203
8204 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8205 "encoder's stage crtc doesn't match current crtc\n");
8206 WARN(encoder->connectors_active && !encoder->base.crtc,
8207 "encoder's active_connectors set, but no crtc\n");
8208
8209 list_for_each_entry(connector, &dev->mode_config.connector_list,
8210 base.head) {
8211 if (connector->base.encoder != &encoder->base)
8212 continue;
8213 enabled = true;
8214 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8215 active = true;
8216 }
8217 WARN(!!encoder->base.crtc != enabled,
8218 "encoder's enabled state mismatch "
8219 "(expected %i, found %i)\n",
8220 !!encoder->base.crtc, enabled);
8221 WARN(active && !encoder->base.crtc,
8222 "active encoder with no crtc\n");
8223
8224 WARN(encoder->connectors_active != active,
8225 "encoder's computed active state doesn't match tracked active state "
8226 "(expected %i, found %i)\n", active, encoder->connectors_active);
8227
8228 active = encoder->get_hw_state(encoder, &pipe);
8229 WARN(active != encoder->connectors_active,
8230 "encoder's hw state doesn't match sw tracking "
8231 "(expected %i, found %i)\n",
8232 encoder->connectors_active, active);
8233
8234 if (!encoder->base.crtc)
8235 continue;
8236
8237 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8238 WARN(active && pipe != tracked_pipe,
8239 "active encoder's pipe doesn't match"
8240 "(expected %i, found %i)\n",
8241 tracked_pipe, pipe);
8242
8243 }
91d1b4bd
DV		 8244}
8245
8246static void
8247check_crtc_state(struct drm_device *dev)
8248{
8249 drm_i915_private_t *dev_priv = dev->dev_private;
8250 struct intel_crtc *crtc;
8251 struct intel_encoder *encoder;
8252 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8253
8254 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8255 base.head) {
8256 bool enabled = false;
8257 bool active = false;
8258
045ac3b5
JB		 8259 memset(&pipe_config, 0, sizeof(pipe_config));
8260
8af6cf88
DV		 8261 DRM_DEBUG_KMS("[CRTC:%d]\n",
8262 crtc->base.base.id);
8263
8264 WARN(crtc->active && !crtc->base.enabled,
8265 "active crtc, but not enabled in sw tracking\n");
8266
8267 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8268 base.head) {
8269 if (encoder->base.crtc != &crtc->base)
8270 continue;
8271 enabled = true;
8272 if (encoder->connectors_active)
8273 active = true;
8274 }
6c49f241 8275
8af6cf88
DV		 8276 WARN(active != crtc->active,
8277 "crtc's computed active state doesn't match tracked active state "
8278 "(expected %i, found %i)\n", active, crtc->active);
8279 WARN(enabled != crtc->base.enabled,
8280 "crtc's computed enabled state doesn't match tracked enabled state "
8281 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8282
0e8ffe1b
DV		 8283 active = dev_priv->display.get_pipe_config(crtc,
8284 &pipe_config);
6c49f241
DV		 8285 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8286 base.head) {
8287 if (encoder->base.crtc != &crtc->base)
8288 continue;
8289 if (encoder->get_config)
8290 encoder->get_config(encoder, &pipe_config);
8291 }
8292
0e8ffe1b
DV		 8293 WARN(crtc->active != active,
8294 "crtc active state doesn't match with hw state "
8295 "(expected %i, found %i)\n", crtc->active, active);
8296
c0b03411
DV		 8297 if (active &&
8298 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8299 WARN(1, "pipe state doesn't match!\n");
8300 intel_dump_pipe_config(crtc, &pipe_config,
8301 "[hw state]");
8302 intel_dump_pipe_config(crtc, &crtc->config,
8303 "[sw state]");
8304 }
8af6cf88 8305 }
91d1b4bd
DV		 8306}
8307
8308static void
8309check_shared_dpll_state(struct drm_device *dev)
8310{
8311 drm_i915_private_t *dev_priv = dev->dev_private;
8312 struct intel_crtc *crtc;
8313 struct intel_dpll_hw_state dpll_hw_state;
8314 int i;
5358901f
DV		 8315
8316 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8317 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8318 int enabled_crtcs = 0, active_crtcs = 0;
8319 bool active;
8320
8321 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8322
8323 DRM_DEBUG_KMS("%s\n", pll->name);
8324
8325 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8326
8327 WARN(pll->active > pll->refcount,
8328 "more active pll users than references: %i vs %i\n",
8329 pll->active, pll->refcount);
8330 WARN(pll->active && !pll->on,
8331 "pll in active use but not on in sw tracking\n");
8332 WARN(pll->on != active,
8333 "pll on state mismatch (expected %i, found %i)\n",
8334 pll->on, active);
8335
8336 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8337 base.head) {
8338 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8339 enabled_crtcs++;
8340 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8341 active_crtcs++;
8342 }
8343 WARN(pll->active != active_crtcs,
8344 "pll active crtcs mismatch (expected %i, found %i)\n",
8345 pll->active, active_crtcs);
8346 WARN(pll->refcount != enabled_crtcs,
8347 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8348 pll->refcount, enabled_crtcs);
66e985c0
DV		 8349
8350 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8351 sizeof(dpll_hw_state)),
8352 "pll hw state mismatch\n");
5358901f 8353 }
8af6cf88
DV		 8354}
8355
91d1b4bd
DV		 8356void
8357intel_modeset_check_state(struct drm_device *dev)
8358{
8359 check_connector_state(dev);
8360 check_encoder_state(dev);
8361 check_crtc_state(dev);
8362 check_shared_dpll_state(dev);
8363}
8364
f30da187
DV		 8365static int __intel_set_mode(struct drm_crtc *crtc,
8366 struct drm_display_mode *mode,
8367 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8368{
8369 struct drm_device *dev = crtc->dev;
dbf2b54e 8370 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8371 struct drm_display_mode *saved_mode, *saved_hwmode;
8372 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8373 struct intel_crtc *intel_crtc;
8374 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8375 int ret = 0;
a6778b3c 8376
3ac18232 8377 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8378 if (!saved_mode)
8379 return -ENOMEM;
3ac18232 8380 saved_hwmode = saved_mode + 1;
a6778b3c 8381
e2e1ed41 8382 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8383 &prepare_pipes, &disable_pipes);
8384
3ac18232
TG		 8385 *saved_hwmode = crtc->hwmode;
8386 *saved_mode = crtc->mode;
a6778b3c 8387
25c5b266
DV		 8388 /* Hack: Because we don't (yet) support global modeset on multiple
8389 * crtcs, we don't keep track of the new mode for more than one crtc.
8390 * Hence simply check whether any bit is set in modeset_pipes in all the
8391 * pieces of code that are not yet converted to deal with mutliple crtcs
8392 * changing their mode at the same time. */
25c5b266 8393 if (modeset_pipes) {
4e53c2e0 8394 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8395 if (IS_ERR(pipe_config)) {
8396 ret = PTR_ERR(pipe_config);
8397 pipe_config = NULL;
8398
3ac18232 8399 goto out;
25c5b266 8400 }
c0b03411
DV		 8401 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8402 "[modeset]");
25c5b266 8403 }
a6778b3c 8404
460da916
DV		 8405 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8406 intel_crtc_disable(&intel_crtc->base);
8407
ea9d758d
DV		 8408 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8409 if (intel_crtc->base.enabled)
8410 dev_priv->display.crtc_disable(&intel_crtc->base);
8411 }
a6778b3c 8412
6c4c86f5
DV		 8413 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8414 * to set it here already despite that we pass it down the callchain.
f6e5b160 8415 */
b8cecdf5 8416 if (modeset_pipes) {
25c5b266 8417 crtc->mode = *mode;
b8cecdf5
DV		 8418 /* mode_set/enable/disable functions rely on a correct pipe
8419 * config. */
8420 to_intel_crtc(crtc)->config = *pipe_config;
8421 }
7758a113 8422
ea9d758d
DV		 8423 /* Only after disabling all output pipelines that will be changed can we
8424 * update the the output configuration. */
8425 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8426
47fab737
DV		 8427 if (dev_priv->display.modeset_global_resources)
8428 dev_priv->display.modeset_global_resources(dev);
8429
a6778b3c
DV		 8430 /* Set up the DPLL and any encoders state that needs to adjust or depend
8431 * on the DPLL.
f6e5b160 8432 */
25c5b266 8433 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8434 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8435 x, y, fb);
8436 if (ret)
8437 goto done;
a6778b3c
DV		 8438 }
8439
8440 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8441 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8442 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8443
25c5b266
DV		 8444 if (modeset_pipes) {
8445 /* Store real post-adjustment hardware mode. */
b8cecdf5 8446 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8447
25c5b266
DV		 8448 /* Calculate and store various constants which
8449 * are later needed by vblank and swap-completion
8450 * timestamping. They are derived from true hwmode.
8451 */
8452 drm_calc_timestamping_constants(crtc);
8453 }
a6778b3c
DV		 8454
8455 /* FIXME: add subpixel order */
8456done:
c0c36b94 8457 if (ret && crtc->enabled) {
3ac18232
TG		 8458 crtc->hwmode = *saved_hwmode;
8459 crtc->mode = *saved_mode;
a6778b3c
DV		 8460 }
8461
3ac18232 8462out:
b8cecdf5 8463 kfree(pipe_config);
3ac18232 8464 kfree(saved_mode);
a6778b3c 8465 return ret;
f6e5b160
CW		 8466}
8467
f30da187
DV		 8468int intel_set_mode(struct drm_crtc *crtc,
8469 struct drm_display_mode *mode,
8470 int x, int y, struct drm_framebuffer *fb)
8471{
8472 int ret;
8473
8474 ret = __intel_set_mode(crtc, mode, x, y, fb);
8475
8476 if (ret == 0)
8477 intel_modeset_check_state(crtc->dev);
8478
8479 return ret;
8480}
8481
c0c36b94
CW		 8482void intel_crtc_restore_mode(struct drm_crtc *crtc)
8483{
8484 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8485}
8486
25c5b266
DV		 8487#undef for_each_intel_crtc_masked
8488
d9e55608
DV		 8489static void intel_set_config_free(struct intel_set_config *config)
8490{
8491 if (!config)
8492 return;
8493
1aa4b628
DV		 8494 kfree(config->save_connector_encoders);
8495 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8496 kfree(config);
8497}
8498
85f9eb71
DV		 8499static int intel_set_config_save_state(struct drm_device *dev,
8500 struct intel_set_config *config)
8501{
85f9eb71
DV		 8502 struct drm_encoder *encoder;
8503 struct drm_connector *connector;
8504 int count;
8505
1aa4b628
DV		 8506 config->save_encoder_crtcs =
8507 kcalloc(dev->mode_config.num_encoder,
8508 sizeof(struct drm_crtc *), GFP_KERNEL);
8509 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8510 return -ENOMEM;
8511
1aa4b628
DV		 8512 config->save_connector_encoders =
8513 kcalloc(dev->mode_config.num_connector,
8514 sizeof(struct drm_encoder *), GFP_KERNEL);
8515 if (!config->save_connector_encoders)
85f9eb71
DV		 8516 return -ENOMEM;
8517
8518 /* Copy data. Note that driver private data is not affected.
8519 * Should anything bad happen only the expected state is
8520 * restored, not the drivers personal bookkeeping.
8521 */
85f9eb71
DV		 8522 count = 0;
8523 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8524 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8525 }
8526
8527 count = 0;
8528 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8529 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8530 }
8531
8532 return 0;
8533}
8534
8535static void intel_set_config_restore_state(struct drm_device *dev,
8536 struct intel_set_config *config)
8537{
9a935856
DV		 8538 struct intel_encoder *encoder;
8539 struct intel_connector *connector;
85f9eb71
DV		 8540 int count;
8541
85f9eb71 8542 count = 0;
9a935856
DV		 8543 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8544 encoder->new_crtc =
8545 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8546 }
8547
8548 count = 0;
9a935856
DV		 8549 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8550 connector->new_encoder =
8551 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8552 }
8553}
8554
5e2b584e
DV		 8555static void
8556intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8557 struct intel_set_config *config)
8558{
8559
8560 /* We should be able to check here if the fb has the same properties
8561 * and then just flip_or_move it */
8562 if (set->crtc->fb != set->fb) {
8563 /* If we have no fb then treat it as a full mode set */
8564 if (set->crtc->fb == NULL) {
8565 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8566 config->mode_changed = true;
8567 } else if (set->fb == NULL) {
8568 config->mode_changed = true;
72f4901e
DV		 8569 } else if (set->fb->pixel_format !=
8570 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8571 config->mode_changed = true;
8572 } else
8573 config->fb_changed = true;
8574 }
8575
835c5873 8576 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8577 config->fb_changed = true;
8578
8579 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8580 DRM_DEBUG_KMS("modes are different, full mode set\n");
8581 drm_mode_debug_printmodeline(&set->crtc->mode);
8582 drm_mode_debug_printmodeline(set->mode);
8583 config->mode_changed = true;
8584 }
8585}
8586
2e431051 8587static int
9a935856
DV		 8588intel_modeset_stage_output_state(struct drm_device *dev,
8589 struct drm_mode_set *set,
8590 struct intel_set_config *config)
50f56119 8591{
85f9eb71 8592 struct drm_crtc *new_crtc;
9a935856
DV		 8593 struct intel_connector *connector;
8594 struct intel_encoder *encoder;
2e431051 8595 int count, ro;
50f56119 8596
9abdda74 8597 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8598 * of connectors. For paranoia, double-check this. */
8599 WARN_ON(!set->fb && (set->num_connectors != 0));
8600 WARN_ON(set->fb && (set->num_connectors == 0));
8601
50f56119 8602 count = 0;
9a935856
DV		 8603 list_for_each_entry(connector, &dev->mode_config.connector_list,
8604 base.head) {
8605 /* Otherwise traverse passed in connector list and get encoders
8606 * for them. */
50f56119 8607 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8608 if (set->connectors[ro] == &connector->base) {
8609 connector->new_encoder = connector->encoder;
50f56119
DV		 8610 break;
8611 }
8612 }
8613
9a935856
DV		 8614 /* If we disable the crtc, disable all its connectors. Also, if
8615 * the connector is on the changing crtc but not on the new
8616 * connector list, disable it. */
8617 if ((!set->fb || ro == set->num_connectors) &&
8618 connector->base.encoder &&
8619 connector->base.encoder->crtc == set->crtc) {
8620 connector->new_encoder = NULL;
8621
8622 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8623 connector->base.base.id,
8624 drm_get_connector_name(&connector->base));
8625 }
8626
8627
8628 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8629 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8630 config->mode_changed = true;
50f56119
DV		 8631 }
8632 }
9a935856 8633 /* connector->new_encoder is now updated for all connectors. */
50f56119 8634
9a935856 8635 /* Update crtc of enabled connectors. */
50f56119 8636 count = 0;
9a935856
DV		 8637 list_for_each_entry(connector, &dev->mode_config.connector_list,
8638 base.head) {
8639 if (!connector->new_encoder)
50f56119
DV		 8640 continue;
8641
9a935856 8642 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8643
8644 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8645 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8646 new_crtc = set->crtc;
8647 }
8648
8649 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8650 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8651 new_crtc)) {
5e2b584e 8652 return -EINVAL;
50f56119 8653 }
9a935856
DV		 8654 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8655
8656 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8657 connector->base.base.id,
8658 drm_get_connector_name(&connector->base),
8659 new_crtc->base.id);
8660 }
8661
8662 /* Check for any encoders that needs to be disabled. */
8663 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8664 base.head) {
8665 list_for_each_entry(connector,
8666 &dev->mode_config.connector_list,
8667 base.head) {
8668 if (connector->new_encoder == encoder) {
8669 WARN_ON(!connector->new_encoder->new_crtc);
8670
8671 goto next_encoder;
8672 }
8673 }
8674 encoder->new_crtc = NULL;
8675next_encoder:
8676 /* Only now check for crtc changes so we don't miss encoders
8677 * that will be disabled. */
8678 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8679 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8680 config->mode_changed = true;
50f56119
DV		 8681 }
8682 }
9a935856 8683 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8684
2e431051
DV		 8685 return 0;
8686}
8687
8688static int intel_crtc_set_config(struct drm_mode_set *set)
8689{
8690 struct drm_device *dev;
2e431051
DV		 8691 struct drm_mode_set save_set;
8692 struct intel_set_config *config;
8693 int ret;
2e431051 8694
8d3e375e
DV		 8695 BUG_ON(!set);
8696 BUG_ON(!set->crtc);
8697 BUG_ON(!set->crtc->helper_private);
2e431051 8698
7e53f3a4
DV		 8699 /* Enforce sane interface api - has been abused by the fb helper. */
8700 BUG_ON(!set->mode && set->fb);
8701 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8702
2e431051
DV		 8703 if (set->fb) {
8704 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8705 set->crtc->base.id, set->fb->base.id,
8706 (int)set->num_connectors, set->x, set->y);
8707 } else {
8708 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8709 }
8710
8711 dev = set->crtc->dev;
8712
8713 ret = -ENOMEM;
8714 config = kzalloc(sizeof(*config), GFP_KERNEL);
8715 if (!config)
8716 goto out_config;
8717
8718 ret = intel_set_config_save_state(dev, config);
8719 if (ret)
8720 goto out_config;
8721
8722 save_set.crtc = set->crtc;
8723 save_set.mode = &set->crtc->mode;
8724 save_set.x = set->crtc->x;
8725 save_set.y = set->crtc->y;
8726 save_set.fb = set->crtc->fb;
8727
8728 /* Compute whether we need a full modeset, only an fb base update or no
8729 * change at all. In the future we might also check whether only the
8730 * mode changed, e.g. for LVDS where we only change the panel fitter in
8731 * such cases. */
8732 intel_set_config_compute_mode_changes(set, config);
8733
9a935856 8734 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8735 if (ret)
8736 goto fail;
8737
5e2b584e 8738 if (config->mode_changed) {
c0c36b94
CW		 8739 ret = intel_set_mode(set->crtc, set->mode,
8740 set->x, set->y, set->fb);
8741 if (ret) {
8742 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8743 set->crtc->base.id, ret);
87f1faa6
DV		 8744 goto fail;
8745 }
5e2b584e 8746 } else if (config->fb_changed) {
4878cae2
VS		 8747 intel_crtc_wait_for_pending_flips(set->crtc);
8748
4f660f49 8749 ret = intel_pipe_set_base(set->crtc,
94352cf9 8750 set->x, set->y, set->fb);
50f56119
DV		 8751 }
8752
d9e55608
DV		 8753 intel_set_config_free(config);
8754
50f56119
DV		 8755 return 0;
8756
8757fail:
85f9eb71 8758 intel_set_config_restore_state(dev, config);
50f56119
DV		 8759
8760 /* Try to restore the config */
5e2b584e 8761 if (config->mode_changed &&
c0c36b94
CW		 8762 intel_set_mode(save_set.crtc, save_set.mode,
8763 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8764 DRM_ERROR("failed to restore config after modeset failure\n");
8765
d9e55608
DV		 8766out_config:
8767 intel_set_config_free(config);
50f56119
DV		 8768 return ret;
8769}
f6e5b160
CW		 8770
8771static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8772 .cursor_set = intel_crtc_cursor_set,
8773 .cursor_move = intel_crtc_cursor_move,
8774 .gamma_set = intel_crtc_gamma_set,
50f56119 8775 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8776 .destroy = intel_crtc_destroy,
8777 .page_flip = intel_crtc_page_flip,
8778};
8779
79f689aa
PZ		 8780static void intel_cpu_pll_init(struct drm_device *dev)
8781{
affa9354 8782 if (HAS_DDI(dev))
79f689aa
PZ		 8783 intel_ddi_pll_init(dev);
8784}
8785
5358901f
DV		 8786static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8787 struct intel_shared_dpll *pll,
8788 struct intel_dpll_hw_state *hw_state)
8789{
8790 uint32_t val;
8791
8792 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8793 hw_state->dpll = val;
8794 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8795 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8796
8797 return val & DPLL_VCO_ENABLE;
8798}
8799
e7b903d2
DV		 8800static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8801 struct intel_shared_dpll *pll)
8802{
8803 uint32_t reg, val;
8804
8805 /* PCH refclock must be enabled first */
8806 assert_pch_refclk_enabled(dev_priv);
8807
8808 reg = PCH_DPLL(pll->id);
8809 val = I915_READ(reg);
8810 val |= DPLL_VCO_ENABLE;
8811 I915_WRITE(reg, val);
8812 POSTING_READ(reg);
8813 udelay(200);
8814}
8815
8816static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8817 struct intel_shared_dpll *pll)
8818{
8819 struct drm_device *dev = dev_priv->dev;
8820 struct intel_crtc *crtc;
8821 uint32_t reg, val;
8822
8823 /* Make sure no transcoder isn't still depending on us. */
8824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8825 if (intel_crtc_to_shared_dpll(crtc) == pll)
8826 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8827 }
8828
8829 reg = PCH_DPLL(pll->id);
8830 val = I915_READ(reg);
8831 val &= ~DPLL_VCO_ENABLE;
8832 I915_WRITE(reg, val);
8833 POSTING_READ(reg);
8834 udelay(200);
8835}
8836
46edb027
DV		 8837static char *ibx_pch_dpll_names[] = {
8838 "PCH DPLL A",
8839 "PCH DPLL B",
8840};
8841
7c74ade1 8842static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8843{
e7b903d2 8844 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8845 int i;
8846
7c74ade1 8847 dev_priv->num_shared_dpll = 2;
ee7b9f93 8848
e72f9fbf 8849 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8850 dev_priv->shared_dplls[i].id = i;
8851 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
e7b903d2
DV		 8852 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8853 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8854 dev_priv->shared_dplls[i].get_hw_state =
8855 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8856 }
8857}
8858
7c74ade1
DV		 8859static void intel_shared_dpll_init(struct drm_device *dev)
8860{
e7b903d2 8861 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8862
8863 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8864 ibx_pch_dpll_init(dev);
8865 else
8866 dev_priv->num_shared_dpll = 0;
8867
8868 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8869 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8870 dev_priv->num_shared_dpll);
8871}
8872
b358d0a6 8873static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8874{
22fd0fab 8875 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8876 struct intel_crtc *intel_crtc;
8877 int i;
8878
8879 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8880 if (intel_crtc == NULL)
8881 return;
8882
8883 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8884
8885 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8886 for (i = 0; i < 256; i++) {
8887 intel_crtc->lut_r[i] = i;
8888 intel_crtc->lut_g[i] = i;
8889 intel_crtc->lut_b[i] = i;
8890 }
8891
80824003
JB		 8892 /* Swap pipes & planes for FBC on pre-965 */
8893 intel_crtc->pipe = pipe;
8894 intel_crtc->plane = pipe;
e2e767ab 8895 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8896 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8897 intel_crtc->plane = !pipe;
80824003
JB		 8898 }
8899
22fd0fab
JB		 8900 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8901 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8902 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8903 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8904
79e53945 8905 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8906}
8907
08d7b3d1 8908int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8909 struct drm_file *file)
08d7b3d1 8910{
08d7b3d1 8911 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8912 struct drm_mode_object *drmmode_obj;
8913 struct intel_crtc *crtc;
08d7b3d1 8914
1cff8f6b
DV		 8915 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8916 return -ENODEV;
08d7b3d1 8917
c05422d5
DV		 8918 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8919 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8920
c05422d5 8921 if (!drmmode_obj) {
08d7b3d1
CW		 8922 DRM_ERROR("no such CRTC id\n");
8923 return -EINVAL;
8924 }
8925
c05422d5
DV		 8926 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8927 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8928
c05422d5 8929 return 0;
08d7b3d1
CW		 8930}
8931
66a9278e 8932static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8933{
66a9278e
DV		 8934 struct drm_device *dev = encoder->base.dev;
8935 struct intel_encoder *source_encoder;
79e53945 8936 int index_mask = 0;
79e53945
JB		 8937 int entry = 0;
8938
66a9278e
DV		 8939 list_for_each_entry(source_encoder,
8940 &dev->mode_config.encoder_list, base.head) {
8941
8942 if (encoder == source_encoder)
79e53945 8943 index_mask |= (1 << entry);
66a9278e
DV		 8944
8945 /* Intel hw has only one MUX where enocoders could be cloned. */
8946 if (encoder->cloneable && source_encoder->cloneable)
8947 index_mask |= (1 << entry);
8948
79e53945
JB		 8949 entry++;
8950 }
4ef69c7a 8951
79e53945
JB		 8952 return index_mask;
8953}
8954
4d302442
CW		 8955static bool has_edp_a(struct drm_device *dev)
8956{
8957 struct drm_i915_private *dev_priv = dev->dev_private;
8958
8959 if (!IS_MOBILE(dev))
8960 return false;
8961
8962 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8963 return false;
8964
8965 if (IS_GEN5(dev) &&
8966 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8967 return false;
8968
8969 return true;
8970}
8971
79e53945
JB		 8972static void intel_setup_outputs(struct drm_device *dev)
8973{
725e30ad 8974 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8975 struct intel_encoder *encoder;
cb0953d7 8976 bool dpd_is_edp = false;
f3cfcba6 8977 bool has_lvds;
79e53945 8978
f3cfcba6 8979 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8980 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8981 /* disable the panel fitter on everything but LVDS */
8982 I915_WRITE(PFIT_CONTROL, 0);
8983 }
79e53945 8984
c40c0f5b 8985 if (!IS_ULT(dev))
79935fca 8986 intel_crt_init(dev);
cb0953d7 8987
affa9354 8988 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8989 int found;
8990
8991 /* Haswell uses DDI functions to detect digital outputs */
8992 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8993 /* DDI A only supports eDP */
8994 if (found)
8995 intel_ddi_init(dev, PORT_A);
8996
8997 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8998 * register */
8999 found = I915_READ(SFUSE_STRAP);
9000
9001 if (found & SFUSE_STRAP_DDIB_DETECTED)
9002 intel_ddi_init(dev, PORT_B);
9003 if (found & SFUSE_STRAP_DDIC_DETECTED)
9004 intel_ddi_init(dev, PORT_C);
9005 if (found & SFUSE_STRAP_DDID_DETECTED)
9006 intel_ddi_init(dev, PORT_D);
9007 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9008 int found;
270b3042
DV		 9009 dpd_is_edp = intel_dpd_is_edp(dev);
9010
9011 if (has_edp_a(dev))
9012 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9013
dc0fa718 9014 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9015 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9016 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9017 if (!found)
e2debe91 9018 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9019 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9020 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9021 }
9022
dc0fa718 9023 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9024 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9025
dc0fa718 9026 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9027 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9028
5eb08b69 9029 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9030 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9031
270b3042 9032 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9033 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9034 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9035 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9036 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9037 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9038
dc0fa718 9039 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9040 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9041 PORT_B);
67cfc203
VS		 9042 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9043 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9044 }
103a196f 9045 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9046 bool found = false;
7d57382e 9047
e2debe91 9048 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9049 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9050 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9051 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9052 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9053 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9054 }
27185ae1 9055
e7281eab 9056 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9057 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9058 }
13520b05
KH		 9059
9060 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9061
e2debe91 9062 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9063 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9064 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9065 }
27185ae1 9066
e2debe91 9067 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9068
b01f2c3a
JB		 9069 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9070 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9071 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9072 }
e7281eab 9073 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9074 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9075 }
27185ae1 9076
b01f2c3a 9077 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9078 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9079 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9080 } else if (IS_GEN2(dev))
79e53945
JB		 9081 intel_dvo_init(dev);
9082
103a196f 9083 if (SUPPORTS_TV(dev))
79e53945
JB		 9084 intel_tv_init(dev);
9085
4ef69c7a
CW		 9086 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9087 encoder->base.possible_crtcs = encoder->crtc_mask;
9088 encoder->base.possible_clones =
66a9278e 9089 intel_encoder_clones(encoder);
79e53945 9090 }
47356eb6 9091
dde86e2d 9092 intel_init_pch_refclk(dev);
270b3042
DV		 9093
9094 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9095}
9096
9097static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9098{
9099 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9100
9101 drm_framebuffer_cleanup(fb);
05394f39 9102 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9103
9104 kfree(intel_fb);
9105}
9106
9107static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9108 struct drm_file *file,
79e53945
JB		 9109 unsigned int *handle)
9110{
9111 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9112 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9113
05394f39 9114 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9115}
9116
9117static const struct drm_framebuffer_funcs intel_fb_funcs = {
9118 .destroy = intel_user_framebuffer_destroy,
9119 .create_handle = intel_user_framebuffer_create_handle,
9120};
9121
38651674
DA		 9122int intel_framebuffer_init(struct drm_device *dev,
9123 struct intel_framebuffer *intel_fb,
308e5bcb 9124 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9125 struct drm_i915_gem_object *obj)
79e53945 9126{
79e53945
JB		 9127 int ret;
9128
c16ed4be
CW		 9129 if (obj->tiling_mode == I915_TILING_Y) {
9130 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9131 return -EINVAL;
c16ed4be 9132 }
57cd6508 9133
c16ed4be
CW		 9134 if (mode_cmd->pitches[0] & 63) {
9135 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9136 mode_cmd->pitches[0]);
57cd6508 9137 return -EINVAL;
c16ed4be 9138 }
57cd6508 9139
5d7bd705 9140 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 9141 if (mode_cmd->pitches[0] > 32768) {
9142 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9143 mode_cmd->pitches[0]);
5d7bd705 9144 return -EINVAL;
c16ed4be 9145 }
5d7bd705
VS		 9146
9147 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9148 mode_cmd->pitches[0] != obj->stride) {
9149 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9150 mode_cmd->pitches[0], obj->stride);
5d7bd705 9151 return -EINVAL;
c16ed4be 9152 }
5d7bd705 9153
57779d06 9154 /* Reject formats not supported by any plane early. */
308e5bcb 9155 switch (mode_cmd->pixel_format) {
57779d06 9156 case DRM_FORMAT_C8:
04b3924d
VS		 9157 case DRM_FORMAT_RGB565:
9158 case DRM_FORMAT_XRGB8888:
9159 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9160 break;
9161 case DRM_FORMAT_XRGB1555:
9162 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9163 if (INTEL_INFO(dev)->gen > 3) {
9164 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9165 return -EINVAL;
c16ed4be 9166 }
57779d06
VS		 9167 break;
9168 case DRM_FORMAT_XBGR8888:
9169 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9170 case DRM_FORMAT_XRGB2101010:
9171 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9172 case DRM_FORMAT_XBGR2101010:
9173 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9174 if (INTEL_INFO(dev)->gen < 4) {
9175 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9176 return -EINVAL;
c16ed4be 9177 }
b5626747 9178 break;
04b3924d
VS		 9179 case DRM_FORMAT_YUYV:
9180 case DRM_FORMAT_UYVY:
9181 case DRM_FORMAT_YVYU:
9182 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9183 if (INTEL_INFO(dev)->gen < 5) {
9184 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9185 return -EINVAL;
c16ed4be 9186 }
57cd6508
CW		 9187 break;
9188 default:
c16ed4be 9189 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9190 return -EINVAL;
9191 }
9192
90f9a336
VS		 9193 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9194 if (mode_cmd->offsets[0] != 0)
9195 return -EINVAL;
9196
c7d73f6a
DV		 9197 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9198 intel_fb->obj = obj;
9199
79e53945
JB		 9200 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9201 if (ret) {
9202 DRM_ERROR("framebuffer init failed %d\n", ret);
9203 return ret;
9204 }
9205
79e53945
JB		 9206 return 0;
9207}
9208
79e53945
JB		 9209static struct drm_framebuffer *
9210intel_user_framebuffer_create(struct drm_device *dev,
9211 struct drm_file *filp,
308e5bcb 9212 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9213{
05394f39 9214 struct drm_i915_gem_object *obj;
79e53945 9215
308e5bcb
JB		 9216 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9217 mode_cmd->handles[0]));
c8725226 9218 if (&obj->base == NULL)
cce13ff7 9219 return ERR_PTR(-ENOENT);
79e53945 9220
d2dff872 9221 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9222}
9223
79e53945 9224static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9225 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9226 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9227};
9228
e70236a8
JB		 9229/* Set up chip specific display functions */
9230static void intel_init_display(struct drm_device *dev)
9231{
9232 struct drm_i915_private *dev_priv = dev->dev_private;
9233
ee9300bb
DV		 9234 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9235 dev_priv->display.find_dpll = g4x_find_best_dpll;
9236 else if (IS_VALLEYVIEW(dev))
9237 dev_priv->display.find_dpll = vlv_find_best_dpll;
9238 else if (IS_PINEVIEW(dev))
9239 dev_priv->display.find_dpll = pnv_find_best_dpll;
9240 else
9241 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9242
affa9354 9243 if (HAS_DDI(dev)) {
0e8ffe1b 9244 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9245 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9246 dev_priv->display.crtc_enable = haswell_crtc_enable;
9247 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9248 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9249 dev_priv->display.update_plane = ironlake_update_plane;
9250 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9251 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9252 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9253 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9254 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9255 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9256 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9257 } else if (IS_VALLEYVIEW(dev)) {
9258 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9259 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9260 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9261 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9262 dev_priv->display.off = i9xx_crtc_off;
9263 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9264 } else {
0e8ffe1b 9265 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9266 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9267 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9268 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9269 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9270 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9271 }
e70236a8 9272
e70236a8 9273 /* Returns the core display clock speed */
25eb05fc
JB		 9274 if (IS_VALLEYVIEW(dev))
9275 dev_priv->display.get_display_clock_speed =
9276 valleyview_get_display_clock_speed;
9277 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9278 dev_priv->display.get_display_clock_speed =
9279 i945_get_display_clock_speed;
9280 else if (IS_I915G(dev))
9281 dev_priv->display.get_display_clock_speed =
9282 i915_get_display_clock_speed;
f2b115e6 9283 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9284 dev_priv->display.get_display_clock_speed =
9285 i9xx_misc_get_display_clock_speed;
9286 else if (IS_I915GM(dev))
9287 dev_priv->display.get_display_clock_speed =
9288 i915gm_get_display_clock_speed;
9289 else if (IS_I865G(dev))
9290 dev_priv->display.get_display_clock_speed =
9291 i865_get_display_clock_speed;
f0f8a9ce 9292 else if (IS_I85X(dev))
e70236a8
JB		 9293 dev_priv->display.get_display_clock_speed =
9294 i855_get_display_clock_speed;
9295 else /* 852, 830 */
9296 dev_priv->display.get_display_clock_speed =
9297 i830_get_display_clock_speed;
9298
7f8a8569 9299 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9300 if (IS_GEN5(dev)) {
674cf967 9301 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9302 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9303 } else if (IS_GEN6(dev)) {
674cf967 9304 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9305 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9306 } else if (IS_IVYBRIDGE(dev)) {
9307 /* FIXME: detect B0+ stepping and use auto training */
9308 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9309 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9310 dev_priv->display.modeset_global_resources =
9311 ivb_modeset_global_resources;
c82e4d26
ED		 9312 } else if (IS_HASWELL(dev)) {
9313 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9314 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9315 dev_priv->display.modeset_global_resources =
9316 haswell_modeset_global_resources;
a0e63c22 9317 }
6067aaea 9318 } else if (IS_G4X(dev)) {
e0dac65e 9319 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9320 }
8c9f3aaf
JB		 9321
9322 /* Default just returns -ENODEV to indicate unsupported */
9323 dev_priv->display.queue_flip = intel_default_queue_flip;
9324
9325 switch (INTEL_INFO(dev)->gen) {
9326 case 2:
9327 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9328 break;
9329
9330 case 3:
9331 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9332 break;
9333
9334 case 4:
9335 case 5:
9336 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9337 break;
9338
9339 case 6:
9340 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9341 break;
7c9017e5
JB		 9342 case 7:
9343 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9344 break;
8c9f3aaf 9345 }
e70236a8
JB		 9346}
9347
b690e96c
JB		 9348/*
9349 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9350 * resume, or other times. This quirk makes sure that's the case for
9351 * affected systems.
9352 */
0206e353 9353static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9354{
9355 struct drm_i915_private *dev_priv = dev->dev_private;
9356
9357 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9358 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9359}
9360
435793df
KP		 9361/*
9362 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9363 */
9364static void quirk_ssc_force_disable(struct drm_device *dev)
9365{
9366 struct drm_i915_private *dev_priv = dev->dev_private;
9367 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9368 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9369}
9370
4dca20ef 9371/*
5a15ab5b
CE		 9372 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9373 * brightness value
4dca20ef
CE		 9374 */
9375static void quirk_invert_brightness(struct drm_device *dev)
9376{
9377 struct drm_i915_private *dev_priv = dev->dev_private;
9378 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9379 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9380}
9381
b690e96c
JB		 9382struct intel_quirk {
9383 int device;
9384 int subsystem_vendor;
9385 int subsystem_device;
9386 void (*hook)(struct drm_device *dev);
9387};
9388
5f85f176
EE		 9389/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9390struct intel_dmi_quirk {
9391 void (*hook)(struct drm_device *dev);
9392 const struct dmi_system_id (*dmi_id_list)[];
9393};
9394
9395static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9396{
9397 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9398 return 1;
9399}
9400
9401static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9402 {
9403 .dmi_id_list = &(const struct dmi_system_id[]) {
9404 {
9405 .callback = intel_dmi_reverse_brightness,
9406 .ident = "NCR Corporation",
9407 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9408 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9409 },
9410 },
9411 { } /* terminating entry */
9412 },
9413 .hook = quirk_invert_brightness,
9414 },
9415};
9416
c43b5634 9417static struct intel_quirk intel_quirks[] = {
b690e96c 9418 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9419 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9420
b690e96c
JB		 9421 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9422 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9423
b690e96c
JB		 9424 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9425 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9426
ccd0d36e 9427 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9428 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9429 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9430
9431 /* Lenovo U160 cannot use SSC on LVDS */
9432 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9433
9434 /* Sony Vaio Y cannot use SSC on LVDS */
9435 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9436
9437 /* Acer Aspire 5734Z must invert backlight brightness */
9438 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9439
9440 /* Acer/eMachines G725 */
9441 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9442
9443 /* Acer/eMachines e725 */
9444 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9445
9446 /* Acer/Packard Bell NCL20 */
9447 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9448
9449 /* Acer Aspire 4736Z */
9450 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9451};
9452
9453static void intel_init_quirks(struct drm_device *dev)
9454{
9455 struct pci_dev *d = dev->pdev;
9456 int i;
9457
9458 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9459 struct intel_quirk *q = &intel_quirks[i];
9460
9461 if (d->device == q->device &&
9462 (d->subsystem_vendor == q->subsystem_vendor ||
9463 q->subsystem_vendor == PCI_ANY_ID) &&
9464 (d->subsystem_device == q->subsystem_device ||
9465 q->subsystem_device == PCI_ANY_ID))
9466 q->hook(dev);
9467 }
5f85f176
EE		 9468 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9469 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9470 intel_dmi_quirks[i].hook(dev);
9471 }
b690e96c
JB		 9472}
9473
9cce37f4
JB		 9474/* Disable the VGA plane that we never use */
9475static void i915_disable_vga(struct drm_device *dev)
9476{
9477 struct drm_i915_private *dev_priv = dev->dev_private;
9478 u8 sr1;
766aa1c4 9479 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9480
9481 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9482 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9483 sr1 = inb(VGA_SR_DATA);
9484 outb(sr1 | 1<<5, VGA_SR_DATA);
9485 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9486 udelay(300);
9487
9488 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9489 POSTING_READ(vga_reg);
9490}
9491
f817586c
DV		 9492void intel_modeset_init_hw(struct drm_device *dev)
9493{
fa42e23c 9494 intel_init_power_well(dev);
0232e927 9495
a8f78b58
ED		 9496 intel_prepare_ddi(dev);
9497
f817586c
DV		 9498 intel_init_clock_gating(dev);
9499
79f5b2c7 9500 mutex_lock(&dev->struct_mutex);
8090c6b9 9501 intel_enable_gt_powersave(dev);
79f5b2c7 9502 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9503}
9504
7d708ee4
ID		 9505void intel_modeset_suspend_hw(struct drm_device *dev)
9506{
9507 intel_suspend_hw(dev);
9508}
9509
79e53945
JB		 9510void intel_modeset_init(struct drm_device *dev)
9511{
652c393a 9512 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9513 int i, j, ret;
79e53945
JB		 9514
9515 drm_mode_config_init(dev);
9516
9517 dev->mode_config.min_width = 0;
9518 dev->mode_config.min_height = 0;
9519
019d96cb
DA		 9520 dev->mode_config.preferred_depth = 24;
9521 dev->mode_config.prefer_shadow = 1;
9522
e6ecefaa 9523 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9524
b690e96c
JB		 9525 intel_init_quirks(dev);
9526
1fa61106
ED		 9527 intel_init_pm(dev);
9528
e3c74757
BW		 9529 if (INTEL_INFO(dev)->num_pipes == 0)
9530 return;
9531
e70236a8
JB		 9532 intel_init_display(dev);
9533
a6c45cf0
CW		 9534 if (IS_GEN2(dev)) {
9535 dev->mode_config.max_width = 2048;
9536 dev->mode_config.max_height = 2048;
9537 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9538 dev->mode_config.max_width = 4096;
9539 dev->mode_config.max_height = 4096;
79e53945 9540 } else {
a6c45cf0
CW		 9541 dev->mode_config.max_width = 8192;
9542 dev->mode_config.max_height = 8192;
79e53945 9543 }
5d4545ae 9544 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9545
28c97730 9546 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9547 INTEL_INFO(dev)->num_pipes,
9548 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9549
7eb552ae 9550 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9551 intel_crtc_init(dev, i);
7f1f3851
JB		 9552 for (j = 0; j < dev_priv->num_plane; j++) {
9553 ret = intel_plane_init(dev, i, j);
9554 if (ret)
06da8da2
VS		 9555 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9556 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9557 }
79e53945
JB		 9558 }
9559
79f689aa 9560 intel_cpu_pll_init(dev);
e72f9fbf 9561 intel_shared_dpll_init(dev);
ee7b9f93 9562
9cce37f4
JB		 9563 /* Just disable it once at startup */
9564 i915_disable_vga(dev);
79e53945 9565 intel_setup_outputs(dev);
11be49eb
CW		 9566
9567 /* Just in case the BIOS is doing something questionable. */
9568 intel_disable_fbc(dev);
2c7111db
CW		 9569}
9570
24929352
DV		 9571static void
9572intel_connector_break_all_links(struct intel_connector *connector)
9573{
9574 connector->base.dpms = DRM_MODE_DPMS_OFF;
9575 connector->base.encoder = NULL;
9576 connector->encoder->connectors_active = false;
9577 connector->encoder->base.crtc = NULL;
9578}
9579
7fad798e
DV		 9580static void intel_enable_pipe_a(struct drm_device *dev)
9581{
9582 struct intel_connector *connector;
9583 struct drm_connector *crt = NULL;
9584 struct intel_load_detect_pipe load_detect_temp;
9585
9586 /* We can't just switch on the pipe A, we need to set things up with a
9587 * proper mode and output configuration. As a gross hack, enable pipe A
9588 * by enabling the load detect pipe once. */
9589 list_for_each_entry(connector,
9590 &dev->mode_config.connector_list,
9591 base.head) {
9592 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9593 crt = &connector->base;
9594 break;
9595 }
9596 }
9597
9598 if (!crt)
9599 return;
9600
9601 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9602 intel_release_load_detect_pipe(crt, &load_detect_temp);
9603
652c393a 9604
7fad798e
DV		 9605}
9606
fa555837
DV		 9607static bool
9608intel_check_plane_mapping(struct intel_crtc *crtc)
9609{
7eb552ae
BW		 9610 struct drm_device *dev = crtc->base.dev;
9611 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9612 u32 reg, val;
9613
7eb552ae 9614 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9615 return true;
9616
9617 reg = DSPCNTR(!crtc->plane);
9618 val = I915_READ(reg);
9619
9620 if ((val & DISPLAY_PLANE_ENABLE) &&
9621 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9622 return false;
9623
9624 return true;
9625}
9626
24929352
DV		 9627static void intel_sanitize_crtc(struct intel_crtc *crtc)
9628{
9629 struct drm_device *dev = crtc->base.dev;
9630 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9631 u32 reg;
24929352 9632
24929352 9633 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9634 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9635 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9636
9637 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9638 * disable the crtc (and hence change the state) if it is wrong. Note
9639 * that gen4+ has a fixed plane -> pipe mapping. */
9640 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9641 struct intel_connector *connector;
9642 bool plane;
9643
24929352
DV		 9644 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9645 crtc->base.base.id);
9646
9647 /* Pipe has the wrong plane attached and the plane is active.
9648 * Temporarily change the plane mapping and disable everything
9649 * ... */
9650 plane = crtc->plane;
9651 crtc->plane = !plane;
9652 dev_priv->display.crtc_disable(&crtc->base);
9653 crtc->plane = plane;
9654
9655 /* ... and break all links. */
9656 list_for_each_entry(connector, &dev->mode_config.connector_list,
9657 base.head) {
9658 if (connector->encoder->base.crtc != &crtc->base)
9659 continue;
9660
9661 intel_connector_break_all_links(connector);
9662 }
9663
9664 WARN_ON(crtc->active);
9665 crtc->base.enabled = false;
9666 }
24929352 9667
7fad798e
DV		 9668 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9669 crtc->pipe == PIPE_A && !crtc->active) {
9670 /* BIOS forgot to enable pipe A, this mostly happens after
9671 * resume. Force-enable the pipe to fix this, the update_dpms
9672 * call below we restore the pipe to the right state, but leave
9673 * the required bits on. */
9674 intel_enable_pipe_a(dev);
9675 }
9676
24929352
DV		 9677 /* Adjust the state of the output pipe according to whether we
9678 * have active connectors/encoders. */
9679 intel_crtc_update_dpms(&crtc->base);
9680
9681 if (crtc->active != crtc->base.enabled) {
9682 struct intel_encoder *encoder;
9683
9684 /* This can happen either due to bugs in the get_hw_state
9685 * functions or because the pipe is force-enabled due to the
9686 * pipe A quirk. */
9687 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9688 crtc->base.base.id,
9689 crtc->base.enabled ? "enabled" : "disabled",
9690 crtc->active ? "enabled" : "disabled");
9691
9692 crtc->base.enabled = crtc->active;
9693
9694 /* Because we only establish the connector -> encoder ->
9695 * crtc links if something is active, this means the
9696 * crtc is now deactivated. Break the links. connector
9697 * -> encoder links are only establish when things are
9698 * actually up, hence no need to break them. */
9699 WARN_ON(crtc->active);
9700
9701 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9702 WARN_ON(encoder->connectors_active);
9703 encoder->base.crtc = NULL;
9704 }
9705 }
9706}
9707
9708static void intel_sanitize_encoder(struct intel_encoder *encoder)
9709{
9710 struct intel_connector *connector;
9711 struct drm_device *dev = encoder->base.dev;
9712
9713 /* We need to check both for a crtc link (meaning that the
9714 * encoder is active and trying to read from a pipe) and the
9715 * pipe itself being active. */
9716 bool has_active_crtc = encoder->base.crtc &&
9717 to_intel_crtc(encoder->base.crtc)->active;
9718
9719 if (encoder->connectors_active && !has_active_crtc) {
9720 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9721 encoder->base.base.id,
9722 drm_get_encoder_name(&encoder->base));
9723
9724 /* Connector is active, but has no active pipe. This is
9725 * fallout from our resume register restoring. Disable
9726 * the encoder manually again. */
9727 if (encoder->base.crtc) {
9728 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9729 encoder->base.base.id,
9730 drm_get_encoder_name(&encoder->base));
9731 encoder->disable(encoder);
9732 }
9733
9734 /* Inconsistent output/port/pipe state happens presumably due to
9735 * a bug in one of the get_hw_state functions. Or someplace else
9736 * in our code, like the register restore mess on resume. Clamp
9737 * things to off as a safer default. */
9738 list_for_each_entry(connector,
9739 &dev->mode_config.connector_list,
9740 base.head) {
9741 if (connector->encoder != encoder)
9742 continue;
9743
9744 intel_connector_break_all_links(connector);
9745 }
9746 }
9747 /* Enabled encoders without active connectors will be fixed in
9748 * the crtc fixup. */
9749}
9750
44cec740 9751void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9752{
9753 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9754 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9755
9756 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9757 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9758 i915_disable_vga(dev);
0fde901f
KM		 9759 }
9760}
9761
30e984df 9762static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9763{
9764 struct drm_i915_private *dev_priv = dev->dev_private;
9765 enum pipe pipe;
24929352
DV		 9766 struct intel_crtc *crtc;
9767 struct intel_encoder *encoder;
9768 struct intel_connector *connector;
5358901f 9769 int i;
24929352 9770
0e8ffe1b
DV		 9771 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9772 base.head) {
88adfff1 9773 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9774
0e8ffe1b
DV		 9775 crtc->active = dev_priv->display.get_pipe_config(crtc,
9776 &crtc->config);
24929352
DV		 9777
9778 crtc->base.enabled = crtc->active;
9779
9780 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9781 crtc->base.base.id,
9782 crtc->active ? "enabled" : "disabled");
9783 }
9784
5358901f 9785 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9786 if (HAS_DDI(dev))
6441ab5f
PZ		 9787 intel_ddi_setup_hw_pll_state(dev);
9788
5358901f
DV		 9789 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9790 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9791
9792 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9793 pll->active = 0;
9794 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9795 base.head) {
9796 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9797 pll->active++;
9798 }
9799 pll->refcount = pll->active;
9800
9801 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9802 pll->name, pll->refcount);
9803 }
9804
24929352
DV		 9805 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9806 base.head) {
9807 pipe = 0;
9808
9809 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9810 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9811 encoder->base.crtc = &crtc->base;
9812 if (encoder->get_config)
9813 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9814 } else {
9815 encoder->base.crtc = NULL;
9816 }
9817
9818 encoder->connectors_active = false;
9819 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9820 encoder->base.base.id,
9821 drm_get_encoder_name(&encoder->base),
9822 encoder->base.crtc ? "enabled" : "disabled",
9823 pipe);
9824 }
9825
9826 list_for_each_entry(connector, &dev->mode_config.connector_list,
9827 base.head) {
9828 if (connector->get_hw_state(connector)) {
9829 connector->base.dpms = DRM_MODE_DPMS_ON;
9830 connector->encoder->connectors_active = true;
9831 connector->base.encoder = &connector->encoder->base;
9832 } else {
9833 connector->base.dpms = DRM_MODE_DPMS_OFF;
9834 connector->base.encoder = NULL;
9835 }
9836 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9837 connector->base.base.id,
9838 drm_get_connector_name(&connector->base),
9839 connector->base.encoder ? "enabled" : "disabled");
9840 }
30e984df
DV		 9841}
9842
9843/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9844 * and i915 state tracking structures. */
9845void intel_modeset_setup_hw_state(struct drm_device *dev,
9846 bool force_restore)
9847{
9848 struct drm_i915_private *dev_priv = dev->dev_private;
9849 enum pipe pipe;
9850 struct drm_plane *plane;
9851 struct intel_crtc *crtc;
9852 struct intel_encoder *encoder;
9853
9854 intel_modeset_readout_hw_state(dev);
24929352
DV		 9855
9856 /* HW state is read out, now we need to sanitize this mess. */
9857 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9858 base.head) {
9859 intel_sanitize_encoder(encoder);
9860 }
9861
9862 for_each_pipe(pipe) {
9863 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9864 intel_sanitize_crtc(crtc);
c0b03411 9865 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9866 }
9a935856 9867
45e2b5f6 9868 if (force_restore) {
f30da187
DV		 9869 /*
9870 * We need to use raw interfaces for restoring state to avoid
9871 * checking (bogus) intermediate states.
9872 */
45e2b5f6 9873 for_each_pipe(pipe) {
b5644d05
JB		 9874 struct drm_crtc *crtc =
9875 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9876
9877 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9878 crtc->fb);
45e2b5f6 9879 }
b5644d05
JB		 9880 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9881 intel_plane_restore(plane);
0fde901f
KM		 9882
9883 i915_redisable_vga(dev);
45e2b5f6
DV		 9884 } else {
9885 intel_modeset_update_staged_output_state(dev);
9886 }
8af6cf88
DV		 9887
9888 intel_modeset_check_state(dev);
2e938892
DV		 9889
9890 drm_mode_config_reset(dev);
2c7111db
CW		 9891}
9892
9893void intel_modeset_gem_init(struct drm_device *dev)
9894{
1833b134 9895 intel_modeset_init_hw(dev);
02e792fb
DV		 9896
9897 intel_setup_overlay(dev);
24929352 9898
45e2b5f6 9899 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9900}
9901
9902void intel_modeset_cleanup(struct drm_device *dev)
9903{
652c393a
JB		 9904 struct drm_i915_private *dev_priv = dev->dev_private;
9905 struct drm_crtc *crtc;
9906 struct intel_crtc *intel_crtc;
9907
fd0c0642
DV		 9908 /*
9909 * Interrupts and polling as the first thing to avoid creating havoc.
9910 * Too much stuff here (turning of rps, connectors, ...) would
9911 * experience fancy races otherwise.
9912 */
9913 drm_irq_uninstall(dev);
9914 cancel_work_sync(&dev_priv->hotplug_work);
9915 /*
9916 * Due to the hpd irq storm handling the hotplug work can re-arm the
9917 * poll handlers. Hence disable polling after hpd handling is shut down.
9918 */
f87ea761 9919 drm_kms_helper_poll_fini(dev);
fd0c0642 9920
652c393a
JB		 9921 mutex_lock(&dev->struct_mutex);
9922
723bfd70
JB		 9923 intel_unregister_dsm_handler();
9924
652c393a
JB		 9925 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9926 /* Skip inactive CRTCs */
9927 if (!crtc->fb)
9928 continue;
9929
9930 intel_crtc = to_intel_crtc(crtc);
3dec0095 9931 intel_increase_pllclock(crtc);
652c393a
JB		 9932 }
9933
973d04f9 9934 intel_disable_fbc(dev);
e70236a8 9935
8090c6b9 9936 intel_disable_gt_powersave(dev);
0cdab21f 9937
930ebb46
DV		 9938 ironlake_teardown_rc6(dev);
9939
69341a5e
KH		 9940 mutex_unlock(&dev->struct_mutex);
9941
1630fe75
CW		 9942 /* flush any delayed tasks or pending work */
9943 flush_scheduled_work();
9944
dc652f90
JN		 9945 /* destroy backlight, if any, before the connectors */
9946 intel_panel_destroy_backlight(dev);
9947
79e53945 9948 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9949
9950 intel_cleanup_overlay(dev);
79e53945
JB		 9951}
9952
f1c79df3
ZW		 9953/*
9954 * Return which encoder is currently attached for connector.
9955 */
df0e9248 9956struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9957{
df0e9248
CW		 9958 return &intel_attached_encoder(connector)->base;
9959}
f1c79df3 9960
df0e9248
CW		 9961void intel_connector_attach_encoder(struct intel_connector *connector,
9962 struct intel_encoder *encoder)
9963{
9964 connector->encoder = encoder;
9965 drm_mode_connector_attach_encoder(&connector->base,
9966 &encoder->base);
79e53945 9967}
28d52043
DA		 9968
9969/*
9970 * set vga decode state - true == enable VGA decode
9971 */
9972int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9973{
9974 struct drm_i915_private *dev_priv = dev->dev_private;
9975 u16 gmch_ctrl;
9976
9977 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9978 if (state)
9979 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9980 else
9981 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9982 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9983 return 0;
9984}
c4a1d9e4
CW		 9985
9986#ifdef CONFIG_DEBUG_FS
9987#include <linux/seq_file.h>
9988
9989struct intel_display_error_state {
ff57f1b0
PZ		 9990
9991 u32 power_well_driver;
9992
c4a1d9e4
CW		 9993 struct intel_cursor_error_state {
9994 u32 control;
9995 u32 position;
9996 u32 base;
9997 u32 size;
52331309 9998 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9999
10000 struct intel_pipe_error_state {
ff57f1b0 10001 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10002 u32 conf;
10003 u32 source;
10004
10005 u32 htotal;
10006 u32 hblank;
10007 u32 hsync;
10008 u32 vtotal;
10009 u32 vblank;
10010 u32 vsync;
52331309 10011 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10012
10013 struct intel_plane_error_state {
10014 u32 control;
10015 u32 stride;
10016 u32 size;
10017 u32 pos;
10018 u32 addr;
10019 u32 surface;
10020 u32 tile_offset;
52331309 10021 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10022};
10023
10024struct intel_display_error_state *
10025intel_display_capture_error_state(struct drm_device *dev)
10026{
0206e353 10027 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10028 struct intel_display_error_state *error;
702e7a56 10029 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10030 int i;
10031
10032 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10033 if (error == NULL)
10034 return NULL;
10035
ff57f1b0
PZ		 10036 if (HAS_POWER_WELL(dev))
10037 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10038
52331309 10039 for_each_pipe(i) {
702e7a56 10040 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10041 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10042
a18c4c3d
PZ		 10043 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10044 error->cursor[i].control = I915_READ(CURCNTR(i));
10045 error->cursor[i].position = I915_READ(CURPOS(i));
10046 error->cursor[i].base = I915_READ(CURBASE(i));
10047 } else {
10048 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10049 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10050 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10051 }
c4a1d9e4
CW		 10052
10053 error->plane[i].control = I915_READ(DSPCNTR(i));
10054 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10055 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10056 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10057 error->plane[i].pos = I915_READ(DSPPOS(i));
10058 }
ca291363
PZ		 10059 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10060 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10061 if (INTEL_INFO(dev)->gen >= 4) {
10062 error->plane[i].surface = I915_READ(DSPSURF(i));
10063 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10064 }
10065
702e7a56 10066 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10067 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10068 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10069 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10070 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10071 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10072 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10073 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10074 }
10075
12d217c7
PZ		 10076 /* In the code above we read the registers without checking if the power
10077 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10078 * prevent the next I915_WRITE from detecting it and printing an error
10079 * message. */
10080 if (HAS_POWER_WELL(dev))
10081 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10082
c4a1d9e4
CW		 10083 return error;
10084}
10085
edc3d884
MK		 10086#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10087
c4a1d9e4 10088void
edc3d884 10089intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10090 struct drm_device *dev,
10091 struct intel_display_error_state *error)
10092{
10093 int i;
10094
edc3d884 10095 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10096 if (HAS_POWER_WELL(dev))
edc3d884 10097 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10098 error->power_well_driver);
52331309 10099 for_each_pipe(i) {
edc3d884
MK		 10100 err_printf(m, "Pipe [%d]:\n", i);
10101 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10102 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10103 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10104 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10105 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10106 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10107 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10108 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10109 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10110 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10111
10112 err_printf(m, "Plane [%d]:\n", i);
10113 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10114 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10115 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10116 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10117 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10118 }
4b71a570 10119 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10120 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10121 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10122 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10123 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10124 }
10125
edc3d884
MK		 10126 err_printf(m, "Cursor [%d]:\n", i);
10127 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10128 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10129 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10130 }
10131}
10132#endif
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