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drm/i915: move clock gating functionality into intel_pm module
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
387static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
388 u32 val)
389{
390 unsigned long flags;
391
392 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
393 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
394 DRM_ERROR("DPIO idle wait timed out\n");
395 goto out_unlock;
396 }
397
398 I915_WRITE(DPIO_DATA, val);
399 I915_WRITE(DPIO_REG, reg);
400 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
401 DPIO_BYTE);
402 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
403 DRM_ERROR("DPIO write wait timed out\n");
404
405out_unlock:
406 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
407}
408
409static void vlv_init_dpio(struct drm_device *dev)
410{
411 struct drm_i915_private *dev_priv = dev->dev_private;
412
413 /* Reset the DPIO config */
414 I915_WRITE(DPIO_CTL, 0);
415 POSTING_READ(DPIO_CTL);
416 I915_WRITE(DPIO_CTL, 1);
417 POSTING_READ(DPIO_CTL);
418}
419
618563e3
DV		 420static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
421{
422 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
423 return 1;
424}
425
426static const struct dmi_system_id intel_dual_link_lvds[] = {
427 {
428 .callback = intel_dual_link_lvds_callback,
429 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
430 .matches = {
431 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
432 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
433 },
434 },
435 { } /* terminating entry */
436};
437
b0354385
TI		 438static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
439 unsigned int reg)
440{
441 unsigned int val;
442
121d527a
TI		 443 /* use the module option value if specified */
444 if (i915_lvds_channel_mode > 0)
445 return i915_lvds_channel_mode == 2;
446
618563e3
DV		 447 if (dmi_check_system(intel_dual_link_lvds))
448 return true;
449
b0354385
TI		 450 if (dev_priv->lvds_val)
451 val = dev_priv->lvds_val;
452 else {
453 /* BIOS should set the proper LVDS register value at boot, but
454 * in reality, it doesn't set the value when the lid is closed;
455 * we need to check "the value to be set" in VBT when LVDS
456 * register is uninitialized.
457 */
458 val = I915_READ(reg);
459 if (!(val & ~LVDS_DETECTED))
460 val = dev_priv->bios_lvds_val;
461 dev_priv->lvds_val = val;
462 }
463 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec
ZW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 471 const intel_limit_t *limit;
b91ad0ec
ZW		 472
473 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 474 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 475 /* LVDS dual channel */
1b894b59 476 if (refclk == 100000)
b91ad0ec
ZW		 477 limit = &intel_limits_ironlake_dual_lvds_100m;
478 else
479 limit = &intel_limits_ironlake_dual_lvds;
480 } else {
1b894b59 481 if (refclk == 100000)
b91ad0ec
ZW		 482 limit = &intel_limits_ironlake_single_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_single_lvds;
485 }
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 487 HAS_eDP)
488 limit = &intel_limits_ironlake_display_port;
2c07245f 489 else
b91ad0ec 490 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 491
492 return limit;
493}
494
044c7c41
ML		 495static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
496{
497 struct drm_device *dev = crtc->dev;
498 struct drm_i915_private *dev_priv = dev->dev_private;
499 const intel_limit_t *limit;
500
501 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 502 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 503 /* LVDS with dual channel */
e4b36699 504 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 505 else
506 /* LVDS with dual channel */
e4b36699 507 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 508 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 510 limit = &intel_limits_g4x_hdmi;
044c7c41 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 512 limit = &intel_limits_g4x_sdvo;
0206e353 513 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 514 limit = &intel_limits_g4x_display_port;
044c7c41 515 } else /* The option is for other outputs */
e4b36699 516 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 517
518 return limit;
519}
520
1b894b59 521static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 522{
523 struct drm_device *dev = crtc->dev;
524 const intel_limit_t *limit;
525
bad720ff 526 if (HAS_PCH_SPLIT(dev))
1b894b59 527 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 528 else if (IS_G4X(dev)) {
044c7c41 529 limit = intel_g4x_limit(crtc);
f2b115e6 530 } else if (IS_PINEVIEW(dev)) {
2177832f 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 532 limit = &intel_limits_pineview_lvds;
2177832f 533 else
f2b115e6 534 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 535 } else if (!IS_GEN2(dev)) {
536 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
537 limit = &intel_limits_i9xx_lvds;
538 else
539 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 540 } else {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 542 limit = &intel_limits_i8xx_lvds;
79e53945 543 else
e4b36699 544 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 545 }
546 return limit;
547}
548
f2b115e6
AJ		 549/* m1 is reserved as 0 in Pineview, n is a ring counter */
550static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 551{
2177832f
SL		 552 clock->m = clock->m2 + 2;
553 clock->p = clock->p1 * clock->p2;
554 clock->vco = refclk * clock->m / clock->n;
555 clock->dot = clock->vco / clock->p;
556}
557
558static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
559{
f2b115e6
AJ		 560 if (IS_PINEVIEW(dev)) {
561 pineview_clock(refclk, clock);
2177832f
SL		 562 return;
563 }
79e53945
JB		 564 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
565 clock->p = clock->p1 * clock->p2;
566 clock->vco = refclk * clock->m / (clock->n + 2);
567 clock->dot = clock->vco / clock->p;
568}
569
79e53945
JB		 570/**
571 * Returns whether any output on the specified pipe is of the specified type
572 */
4ef69c7a 573bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 574{
4ef69c7a
CW		 575 struct drm_device *dev = crtc->dev;
576 struct drm_mode_config *mode_config = &dev->mode_config;
577 struct intel_encoder *encoder;
578
579 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
580 if (encoder->base.crtc == crtc && encoder->type == type)
581 return true;
582
583 return false;
79e53945
JB		 584}
585
7c04d1d9 586#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 587/**
588 * Returns whether the given set of divisors are valid for a given refclk with
589 * the given connectors.
590 */
591
1b894b59
CW		 592static bool intel_PLL_is_valid(struct drm_device *dev,
593 const intel_limit_t *limit,
594 const intel_clock_t *clock)
79e53945 595{
79e53945 596 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 597 INTELPllInvalid("p1 out of range\n");
79e53945 598 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 599 INTELPllInvalid("p out of range\n");
79e53945 600 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 601 INTELPllInvalid("m2 out of range\n");
79e53945 602 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 603 INTELPllInvalid("m1 out of range\n");
f2b115e6 604 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 605 INTELPllInvalid("m1 <= m2\n");
79e53945 606 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 607 INTELPllInvalid("m out of range\n");
79e53945 608 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 609 INTELPllInvalid("n out of range\n");
79e53945 610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 611 INTELPllInvalid("vco out of range\n");
79e53945
JB		 612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 616 INTELPllInvalid("dot out of range\n");
79e53945
JB		 617
618 return true;
619}
620
d4906093
ML		 621static bool
622intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 623 int target, int refclk, intel_clock_t *match_clock,
624 intel_clock_t *best_clock)
d4906093 625
79e53945
JB		 626{
627 struct drm_device *dev = crtc->dev;
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 intel_clock_t clock;
79e53945
JB		 630 int err = target;
631
bc5e5718 632 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 633 (I915_READ(LVDS)) != 0) {
79e53945
JB		 634 /*
635 * For LVDS, if the panel is on, just rely on its current
636 * settings for dual-channel. We haven't figured out how to
637 * reliably set up different single/dual channel state, if we
638 * even can.
639 */
b0354385 640 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
0206e353 651 memset(best_clock, 0, sizeof(*best_clock));
79e53945 652
42158660
ZY		 653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
654 clock.m1++) {
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 657 /* m1 is always 0 in Pineview */
658 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 659 break;
660 for (clock.n = limit->n.min;
661 clock.n <= limit->n.max; clock.n++) {
662 for (clock.p1 = limit->p1.min;
663 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 664 int this_err;
665
2177832f 666 intel_clock(dev, refclk, &clock);
1b894b59
CW		 667 if (!intel_PLL_is_valid(dev, limit,
668 &clock))
79e53945 669 continue;
cec2f356
SP		 670 if (match_clock &&
671 clock.p != match_clock->p)
672 continue;
79e53945
JB		 673
674 this_err = abs(clock.dot - target);
675 if (this_err < err) {
676 *best_clock = clock;
677 err = this_err;
678 }
679 }
680 }
681 }
682 }
683
684 return (err != target);
685}
686
d4906093
ML		 687static bool
688intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
d4906093
ML		 691{
692 struct drm_device *dev = crtc->dev;
693 struct drm_i915_private *dev_priv = dev->dev_private;
694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
708 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 709 LVDS_CLKB_POWER_UP)
710 clock.p2 = limit->p2.p2_fast;
711 else
712 clock.p2 = limit->p2.p2_slow;
713 } else {
714 if (target < limit->p2.dot_limit)
715 clock.p2 = limit->p2.p2_slow;
716 else
717 clock.p2 = limit->p2.p2_fast;
718 }
719
720 memset(best_clock, 0, sizeof(*best_clock));
721 max_n = limit->n.max;
f77f13e2 722 /* based on hardware requirement, prefer smaller n to precision */
d4906093 723 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 724 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 725 for (clock.m1 = limit->m1.max;
726 clock.m1 >= limit->m1.min; clock.m1--) {
727 for (clock.m2 = limit->m2.max;
728 clock.m2 >= limit->m2.min; clock.m2--) {
729 for (clock.p1 = limit->p1.max;
730 clock.p1 >= limit->p1.min; clock.p1--) {
731 int this_err;
732
2177832f 733 intel_clock(dev, refclk, &clock);
1b894b59
CW		 734 if (!intel_PLL_is_valid(dev, limit,
735 &clock))
d4906093 736 continue;
cec2f356
SP		 737 if (match_clock &&
738 clock.p != match_clock->p)
739 continue;
1b894b59
CW		 740
741 this_err = abs(clock.dot - target);
d4906093
ML		 742 if (this_err < err_most) {
743 *best_clock = clock;
744 err_most = this_err;
745 max_n = clock.n;
746 found = true;
747 }
748 }
749 }
750 }
751 }
2c07245f
ZW		 752 return found;
753}
754
5eb08b69 755static bool
f2b115e6 756intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 757 int target, int refclk, intel_clock_t *match_clock,
758 intel_clock_t *best_clock)
5eb08b69
ZW		 759{
760 struct drm_device *dev = crtc->dev;
761 intel_clock_t clock;
4547668a 762
5eb08b69
ZW		 763 if (target < 200000) {
764 clock.n = 1;
765 clock.p1 = 2;
766 clock.p2 = 10;
767 clock.m1 = 12;
768 clock.m2 = 9;
769 } else {
770 clock.n = 2;
771 clock.p1 = 1;
772 clock.p2 = 10;
773 clock.m1 = 14;
774 clock.m2 = 8;
775 }
776 intel_clock(dev, refclk, &clock);
777 memcpy(best_clock, &clock, sizeof(intel_clock_t));
778 return true;
779}
780
a4fc5ed6
KP		 781/* DisplayPort has only two frequencies, 162MHz and 270MHz */
782static bool
783intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 784 int target, int refclk, intel_clock_t *match_clock,
785 intel_clock_t *best_clock)
a4fc5ed6 786{
5eddb70b
CW		 787 intel_clock_t clock;
788 if (target < 200000) {
789 clock.p1 = 2;
790 clock.p2 = 10;
791 clock.n = 2;
792 clock.m1 = 23;
793 clock.m2 = 8;
794 } else {
795 clock.p1 = 1;
796 clock.p2 = 10;
797 clock.n = 1;
798 clock.m1 = 14;
799 clock.m2 = 2;
800 }
801 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
802 clock.p = (clock.p1 * clock.p2);
803 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
804 clock.vco = 0;
805 memcpy(best_clock, &clock, sizeof(intel_clock_t));
806 return true;
a4fc5ed6
KP		 807}
808
9d0498a2
JB		 809/**
810 * intel_wait_for_vblank - wait for vblank on a given pipe
811 * @dev: drm device
812 * @pipe: pipe to wait for
813 *
814 * Wait for vblank to occur on a given pipe. Needed for various bits of
815 * mode setting code.
816 */
817void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 818{
9d0498a2 819 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 820 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 821
300387c0
CW		 822 /* Clear existing vblank status. Note this will clear any other
823 * sticky status fields as well.
824 *
825 * This races with i915_driver_irq_handler() with the result
826 * that either function could miss a vblank event. Here it is not
827 * fatal, as we will either wait upon the next vblank interrupt or
828 * timeout. Generally speaking intel_wait_for_vblank() is only
829 * called during modeset at which time the GPU should be idle and
830 * should *not* be performing page flips and thus not waiting on
831 * vblanks...
832 * Currently, the result of us stealing a vblank from the irq
833 * handler is that a single frame will be skipped during swapbuffers.
834 */
835 I915_WRITE(pipestat_reg,
836 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
837
9d0498a2 838 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 839 if (wait_for(I915_READ(pipestat_reg) &
840 PIPE_VBLANK_INTERRUPT_STATUS,
841 50))
9d0498a2
JB		 842 DRM_DEBUG_KMS("vblank wait timed out\n");
843}
844
ab7ad7f6
KP		 845/*
846 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 847 * @dev: drm device
848 * @pipe: pipe to wait for
849 *
850 * After disabling a pipe, we can't wait for vblank in the usual way,
851 * spinning on the vblank interrupt status bit, since we won't actually
852 * see an interrupt when the pipe is disabled.
853 *
ab7ad7f6
KP		 854 * On Gen4 and above:
855 * wait for the pipe register state bit to turn off
856 *
857 * Otherwise:
858 * wait for the display line value to settle (it usually
859 * ends up stopping at the start of the next frame).
58e10eb9 860 *
9d0498a2 861 */
58e10eb9 862void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 863{
864 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 865
866 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 867 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 868
869 /* Wait for the Pipe State to go off */
58e10eb9
CW		 870 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
871 100))
ab7ad7f6
KP		 872 DRM_DEBUG_KMS("pipe_off wait timed out\n");
873 } else {
874 u32 last_line;
58e10eb9 875 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 876 unsigned long timeout = jiffies + msecs_to_jiffies(100);
877
878 /* Wait for the display line to settle */
879 do {
58e10eb9 880 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 881 mdelay(5);
58e10eb9 882 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 883 time_after(timeout, jiffies));
884 if (time_after(jiffies, timeout))
885 DRM_DEBUG_KMS("pipe_off wait timed out\n");
886 }
79e53945
JB		 887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
914 enum pipe pipe, bool state)
915{
916 int reg;
917 u32 val;
918 bool cur_state;
919
d3ccbe86
JB		 920 if (HAS_PCH_CPT(dev_priv->dev)) {
921 u32 pch_dpll;
922
923 pch_dpll = I915_READ(PCH_DPLL_SEL);
924
925 /* Make sure the selected PLL is enabled to the transcoder */
926 WARN(!((pch_dpll >> (4 * pipe)) & 8),
927 "transcoder %d PLL not enabled\n", pipe);
928
929 /* Convert the transcoder pipe number to a pll pipe number */
930 pipe = (pch_dpll >> (4 * pipe)) & 1;
931 }
932
040484af
JB		 933 reg = PCH_DPLL(pipe);
934 val = I915_READ(reg);
935 cur_state = !!(val & DPLL_VCO_ENABLE);
936 WARN(cur_state != state,
937 "PCH PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
939}
940#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
941#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
942
943static void assert_fdi_tx(struct drm_i915_private *dev_priv,
944 enum pipe pipe, bool state)
945{
946 int reg;
947 u32 val;
948 bool cur_state;
949
950 reg = FDI_TX_CTL(pipe);
951 val = I915_READ(reg);
952 cur_state = !!(val & FDI_TX_ENABLE);
953 WARN(cur_state != state,
954 "FDI TX state assertion failure (expected %s, current %s)\n",
955 state_string(state), state_string(cur_state));
956}
957#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
958#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
959
960static void assert_fdi_rx(struct drm_i915_private *dev_priv,
961 enum pipe pipe, bool state)
962{
963 int reg;
964 u32 val;
965 bool cur_state;
966
967 reg = FDI_RX_CTL(pipe);
968 val = I915_READ(reg);
969 cur_state = !!(val & FDI_RX_ENABLE);
970 WARN(cur_state != state,
971 "FDI RX state assertion failure (expected %s, current %s)\n",
972 state_string(state), state_string(cur_state));
973}
974#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
975#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
976
977static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979{
980 int reg;
981 u32 val;
982
983 /* ILK FDI PLL is always enabled */
984 if (dev_priv->info->gen == 5)
985 return;
986
987 reg = FDI_TX_CTL(pipe);
988 val = I915_READ(reg);
989 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
990}
991
992static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994{
995 int reg;
996 u32 val;
997
998 reg = FDI_RX_CTL(pipe);
999 val = I915_READ(reg);
1000 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1001}
1002
ea0760cf
JB		 1003static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1004 enum pipe pipe)
1005{
1006 int pp_reg, lvds_reg;
1007 u32 val;
1008 enum pipe panel_pipe = PIPE_A;
0de3b485 1009 bool locked = true;
ea0760cf
JB		 1010
1011 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1012 pp_reg = PCH_PP_CONTROL;
1013 lvds_reg = PCH_LVDS;
1014 } else {
1015 pp_reg = PP_CONTROL;
1016 lvds_reg = LVDS;
1017 }
1018
1019 val = I915_READ(pp_reg);
1020 if (!(val & PANEL_POWER_ON) ||
1021 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1022 locked = false;
1023
1024 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1025 panel_pipe = PIPE_B;
1026
1027 WARN(panel_pipe == pipe && locked,
1028 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1029 pipe_name(pipe));
ea0760cf
JB		 1030}
1031
b840d907
JB		 1032void assert_pipe(struct drm_i915_private *dev_priv,
1033 enum pipe pipe, bool state)
b24e7179
JB		 1034{
1035 int reg;
1036 u32 val;
63d7bbe9 1037 bool cur_state;
b24e7179 1038
8e636784
DV		 1039 /* if we need the pipe A quirk it must be always on */
1040 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1041 state = true;
1042
b24e7179
JB		 1043 reg = PIPECONF(pipe);
1044 val = I915_READ(reg);
63d7bbe9
JB		 1045 cur_state = !!(val & PIPECONF_ENABLE);
1046 WARN(cur_state != state,
1047 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1048 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1049}
1050
931872fc
CW		 1051static void assert_plane(struct drm_i915_private *dev_priv,
1052 enum plane plane, bool state)
b24e7179
JB		 1053{
1054 int reg;
1055 u32 val;
931872fc 1056 bool cur_state;
b24e7179
JB		 1057
1058 reg = DSPCNTR(plane);
1059 val = I915_READ(reg);
931872fc
CW		 1060 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1061 WARN(cur_state != state,
1062 "plane %c assertion failure (expected %s, current %s)\n",
1063 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1064}
1065
931872fc
CW		 1066#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1067#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1068
b24e7179
JB		 1069static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1070 enum pipe pipe)
1071{
1072 int reg, i;
1073 u32 val;
1074 int cur_pipe;
1075
19ec1358 1076 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1077 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1078 reg = DSPCNTR(pipe);
1079 val = I915_READ(reg);
1080 WARN((val & DISPLAY_PLANE_ENABLE),
1081 "plane %c assertion failure, should be disabled but not\n",
1082 plane_name(pipe));
19ec1358 1083 return;
28c05794 1084 }
19ec1358 1085
b24e7179
JB		 1086 /* Need to check both planes against the pipe */
1087 for (i = 0; i < 2; i++) {
1088 reg = DSPCNTR(i);
1089 val = I915_READ(reg);
1090 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1091 DISPPLANE_SEL_PIPE_SHIFT;
1092 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1093 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1094 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1095 }
1096}
1097
92f2584a
JB		 1098static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1099{
1100 u32 val;
1101 bool enabled;
1102
1103 val = I915_READ(PCH_DREF_CONTROL);
1104 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1105 DREF_SUPERSPREAD_SOURCE_MASK));
1106 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1107}
1108
1109static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1110 enum pipe pipe)
1111{
1112 int reg;
1113 u32 val;
1114 bool enabled;
1115
1116 reg = TRANSCONF(pipe);
1117 val = I915_READ(reg);
1118 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1119 WARN(enabled,
1120 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1121 pipe_name(pipe));
92f2584a
JB		 1122}
1123
4e634389
KP		 1124static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1126{
1127 if ((val & DP_PORT_EN) == 0)
1128 return false;
1129
1130 if (HAS_PCH_CPT(dev_priv->dev)) {
1131 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1132 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1133 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1134 return false;
1135 } else {
1136 if ((val & DP_PIPE_MASK) != (pipe << 30))
1137 return false;
1138 }
1139 return true;
1140}
1141
1519b995
KP		 1142static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, u32 val)
1144{
1145 if ((val & PORT_ENABLE) == 0)
1146 return false;
1147
1148 if (HAS_PCH_CPT(dev_priv->dev)) {
1149 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1150 return false;
1151 } else {
1152 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1153 return false;
1154 }
1155 return true;
1156}
1157
1158static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe, u32 val)
1160{
1161 if ((val & LVDS_PORT_EN) == 0)
1162 return false;
1163
1164 if (HAS_PCH_CPT(dev_priv->dev)) {
1165 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1166 return false;
1167 } else {
1168 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1169 return false;
1170 }
1171 return true;
1172}
1173
1174static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, u32 val)
1176{
1177 if ((val & ADPA_DAC_ENABLE) == 0)
1178 return false;
1179 if (HAS_PCH_CPT(dev_priv->dev)) {
1180 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1181 return false;
1182 } else {
1183 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1184 return false;
1185 }
1186 return true;
1187}
1188
291906f1 1189static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1190 enum pipe pipe, int reg, u32 port_sel)
291906f1 1191{
47a05eca 1192 u32 val = I915_READ(reg);
4e634389 1193 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1194 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1195 reg, pipe_name(pipe));
291906f1
JB		 1196}
1197
1198static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, int reg)
1200{
47a05eca 1201 u32 val = I915_READ(reg);
1519b995 1202 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1203 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1204 reg, pipe_name(pipe));
291906f1
JB		 1205}
1206
1207static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1208 enum pipe pipe)
1209{
1210 int reg;
1211 u32 val;
291906f1 1212
f0575e92
KP		 1213 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1214 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1215 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1216
1217 reg = PCH_ADPA;
1218 val = I915_READ(reg);
1519b995 1219 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1220 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1221 pipe_name(pipe));
291906f1
JB		 1222
1223 reg = PCH_LVDS;
1224 val = I915_READ(reg);
1519b995 1225 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1226 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1227 pipe_name(pipe));
291906f1
JB		 1228
1229 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1230 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1231 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1232}
1233
63d7bbe9
JB		 1234/**
1235 * intel_enable_pll - enable a PLL
1236 * @dev_priv: i915 private structure
1237 * @pipe: pipe PLL to enable
1238 *
1239 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1240 * make sure the PLL reg is writable first though, since the panel write
1241 * protect mechanism may be enabled.
1242 *
1243 * Note! This is for pre-ILK only.
1244 */
1245static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1246{
1247 int reg;
1248 u32 val;
1249
1250 /* No really, not for ILK+ */
1251 BUG_ON(dev_priv->info->gen >= 5);
1252
1253 /* PLL is protected by panel, make sure we can write it */
1254 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1255 assert_panel_unlocked(dev_priv, pipe);
1256
1257 reg = DPLL(pipe);
1258 val = I915_READ(reg);
1259 val |= DPLL_VCO_ENABLE;
1260
1261 /* We do this three times for luck */
1262 I915_WRITE(reg, val);
1263 POSTING_READ(reg);
1264 udelay(150); /* wait for warmup */
1265 I915_WRITE(reg, val);
1266 POSTING_READ(reg);
1267 udelay(150); /* wait for warmup */
1268 I915_WRITE(reg, val);
1269 POSTING_READ(reg);
1270 udelay(150); /* wait for warmup */
1271}
1272
1273/**
1274 * intel_disable_pll - disable a PLL
1275 * @dev_priv: i915 private structure
1276 * @pipe: pipe PLL to disable
1277 *
1278 * Disable the PLL for @pipe, making sure the pipe is off first.
1279 *
1280 * Note! This is for pre-ILK only.
1281 */
1282static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1283{
1284 int reg;
1285 u32 val;
1286
1287 /* Don't disable pipe A or pipe A PLLs if needed */
1288 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1289 return;
1290
1291 /* Make sure the pipe isn't still relying on us */
1292 assert_pipe_disabled(dev_priv, pipe);
1293
1294 reg = DPLL(pipe);
1295 val = I915_READ(reg);
1296 val &= ~DPLL_VCO_ENABLE;
1297 I915_WRITE(reg, val);
1298 POSTING_READ(reg);
1299}
1300
92f2584a
JB		 1301/**
1302 * intel_enable_pch_pll - enable PCH PLL
1303 * @dev_priv: i915 private structure
1304 * @pipe: pipe PLL to enable
1305 *
1306 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1307 * drives the transcoder clock.
1308 */
1309static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311{
1312 int reg;
1313 u32 val;
1314
4c609cb8
JB		 1315 if (pipe > 1)
1316 return;
1317
92f2584a
JB		 1318 /* PCH only available on ILK+ */
1319 BUG_ON(dev_priv->info->gen < 5);
1320
1321 /* PCH refclock must be enabled first */
1322 assert_pch_refclk_enabled(dev_priv);
1323
1324 reg = PCH_DPLL(pipe);
1325 val = I915_READ(reg);
1326 val |= DPLL_VCO_ENABLE;
1327 I915_WRITE(reg, val);
1328 POSTING_READ(reg);
1329 udelay(200);
1330}
1331
1332static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1333 enum pipe pipe)
1334{
1335 int reg;
7a419866
JB		 1336 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1337 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1338
4c609cb8
JB		 1339 if (pipe > 1)
1340 return;
1341
92f2584a
JB		 1342 /* PCH only available on ILK+ */
1343 BUG_ON(dev_priv->info->gen < 5);
1344
1345 /* Make sure transcoder isn't still depending on us */
1346 assert_transcoder_disabled(dev_priv, pipe);
1347
7a419866
JB		 1348 if (pipe == 0)
1349 pll_sel |= TRANSC_DPLLA_SEL;
1350 else if (pipe == 1)
1351 pll_sel |= TRANSC_DPLLB_SEL;
1352
1353
1354 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1355 return;
1356
92f2584a
JB		 1357 reg = PCH_DPLL(pipe);
1358 val = I915_READ(reg);
1359 val &= ~DPLL_VCO_ENABLE;
1360 I915_WRITE(reg, val);
1361 POSTING_READ(reg);
1362 udelay(200);
1363}
1364
040484af
JB		 1365static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1366 enum pipe pipe)
1367{
1368 int reg;
5f7f726d 1369 u32 val, pipeconf_val;
7c26e5c6 1370 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1371
1372 /* PCH only available on ILK+ */
1373 BUG_ON(dev_priv->info->gen < 5);
1374
1375 /* Make sure PCH DPLL is enabled */
1376 assert_pch_pll_enabled(dev_priv, pipe);
1377
1378 /* FDI must be feeding us bits for PCH ports */
1379 assert_fdi_tx_enabled(dev_priv, pipe);
1380 assert_fdi_rx_enabled(dev_priv, pipe);
1381
1382 reg = TRANSCONF(pipe);
1383 val = I915_READ(reg);
5f7f726d 1384 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1385
1386 if (HAS_PCH_IBX(dev_priv->dev)) {
1387 /*
1388 * make the BPC in transcoder be consistent with
1389 * that in pipeconf reg.
1390 */
1391 val &= ~PIPE_BPC_MASK;
5f7f726d 1392 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1393 }
5f7f726d
PZ		 1394
1395 val &= ~TRANS_INTERLACE_MASK;
1396 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1397 if (HAS_PCH_IBX(dev_priv->dev) &&
1398 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1399 val |= TRANS_LEGACY_INTERLACED_ILK;
1400 else
1401 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1402 else
1403 val |= TRANS_PROGRESSIVE;
1404
040484af
JB		 1405 I915_WRITE(reg, val | TRANS_ENABLE);
1406 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1407 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1408}
1409
1410static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1411 enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 /* FDI relies on the transcoder */
1417 assert_fdi_tx_disabled(dev_priv, pipe);
1418 assert_fdi_rx_disabled(dev_priv, pipe);
1419
291906f1
JB		 1420 /* Ports must be off as well */
1421 assert_pch_ports_disabled(dev_priv, pipe);
1422
040484af
JB		 1423 reg = TRANSCONF(pipe);
1424 val = I915_READ(reg);
1425 val &= ~TRANS_ENABLE;
1426 I915_WRITE(reg, val);
1427 /* wait for PCH transcoder off, transcoder state */
1428 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1429 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1430}
1431
b24e7179 1432/**
309cfea8 1433 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1434 * @dev_priv: i915 private structure
1435 * @pipe: pipe to enable
040484af 1436 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1437 *
1438 * Enable @pipe, making sure that various hardware specific requirements
1439 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1440 *
1441 * @pipe should be %PIPE_A or %PIPE_B.
1442 *
1443 * Will wait until the pipe is actually running (i.e. first vblank) before
1444 * returning.
1445 */
040484af
JB		 1446static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1447 bool pch_port)
b24e7179
JB		 1448{
1449 int reg;
1450 u32 val;
1451
1452 /*
1453 * A pipe without a PLL won't actually be able to drive bits from
1454 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1455 * need the check.
1456 */
1457 if (!HAS_PCH_SPLIT(dev_priv->dev))
1458 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1459 else {
1460 if (pch_port) {
1461 /* if driving the PCH, we need FDI enabled */
1462 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1463 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1464 }
1465 /* FIXME: assert CPU port conditions for SNB+ */
1466 }
b24e7179
JB		 1467
1468 reg = PIPECONF(pipe);
1469 val = I915_READ(reg);
00d70b15
CW		 1470 if (val & PIPECONF_ENABLE)
1471 return;
1472
1473 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1474 intel_wait_for_vblank(dev_priv->dev, pipe);
1475}
1476
1477/**
309cfea8 1478 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1479 * @dev_priv: i915 private structure
1480 * @pipe: pipe to disable
1481 *
1482 * Disable @pipe, making sure that various hardware specific requirements
1483 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1484 *
1485 * @pipe should be %PIPE_A or %PIPE_B.
1486 *
1487 * Will wait until the pipe has shut down before returning.
1488 */
1489static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1490 enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /*
1496 * Make sure planes won't keep trying to pump pixels to us,
1497 * or we might hang the display.
1498 */
1499 assert_planes_disabled(dev_priv, pipe);
1500
1501 /* Don't disable pipe A or pipe A PLLs if needed */
1502 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1503 return;
1504
1505 reg = PIPECONF(pipe);
1506 val = I915_READ(reg);
00d70b15
CW		 1507 if ((val & PIPECONF_ENABLE) == 0)
1508 return;
1509
1510 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1511 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1512}
1513
d74362c9
KP		 1514/*
1515 * Plane regs are double buffered, going from enabled->disabled needs a
1516 * trigger in order to latch. The display address reg provides this.
1517 */
6f1d69b0 1518void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1519 enum plane plane)
1520{
1521 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1522 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1523}
1524
b24e7179
JB		 1525/**
1526 * intel_enable_plane - enable a display plane on a given pipe
1527 * @dev_priv: i915 private structure
1528 * @plane: plane to enable
1529 * @pipe: pipe being fed
1530 *
1531 * Enable @plane on @pipe, making sure that @pipe is running first.
1532 */
1533static void intel_enable_plane(struct drm_i915_private *dev_priv,
1534 enum plane plane, enum pipe pipe)
1535{
1536 int reg;
1537 u32 val;
1538
1539 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1540 assert_pipe_enabled(dev_priv, pipe);
1541
1542 reg = DSPCNTR(plane);
1543 val = I915_READ(reg);
00d70b15
CW		 1544 if (val & DISPLAY_PLANE_ENABLE)
1545 return;
1546
1547 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1548 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1549 intel_wait_for_vblank(dev_priv->dev, pipe);
1550}
1551
b24e7179
JB		 1552/**
1553 * intel_disable_plane - disable a display plane
1554 * @dev_priv: i915 private structure
1555 * @plane: plane to disable
1556 * @pipe: pipe consuming the data
1557 *
1558 * Disable @plane; should be an independent operation.
1559 */
1560static void intel_disable_plane(struct drm_i915_private *dev_priv,
1561 enum plane plane, enum pipe pipe)
1562{
1563 int reg;
1564 u32 val;
1565
1566 reg = DSPCNTR(plane);
1567 val = I915_READ(reg);
00d70b15
CW		 1568 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1569 return;
1570
1571 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1572 intel_flush_display_plane(dev_priv, plane);
1573 intel_wait_for_vblank(dev_priv->dev, pipe);
1574}
1575
47a05eca 1576static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1577 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1578{
1579 u32 val = I915_READ(reg);
4e634389 1580 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1581 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1582 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1583 }
47a05eca
JB		 1584}
1585
1586static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1587 enum pipe pipe, int reg)
1588{
1589 u32 val = I915_READ(reg);
1519b995 1590 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1591 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1592 reg, pipe);
47a05eca 1593 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1594 }
47a05eca
JB		 1595}
1596
1597/* Disable any ports connected to this transcoder */
1598static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1599 enum pipe pipe)
1600{
1601 u32 reg, val;
1602
1603 val = I915_READ(PCH_PP_CONTROL);
1604 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1605
f0575e92
KP		 1606 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1609
1610 reg = PCH_ADPA;
1611 val = I915_READ(reg);
1519b995 1612 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1613 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1614
1615 reg = PCH_LVDS;
1616 val = I915_READ(reg);
1519b995
KP		 1617 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1618 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1619 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1620 POSTING_READ(reg);
1621 udelay(100);
1622 }
1623
1624 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1625 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1626 disable_pch_hdmi(dev_priv, pipe, HDMID);
1627}
1628
127bd2ac 1629int
48b956c5 1630intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1631 struct drm_i915_gem_object *obj,
919926ae 1632 struct intel_ring_buffer *pipelined)
6b95a207 1633{
ce453d81 1634 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1635 u32 alignment;
1636 int ret;
1637
05394f39 1638 switch (obj->tiling_mode) {
6b95a207 1639 case I915_TILING_NONE:
534843da
CW		 1640 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1641 alignment = 128 * 1024;
a6c45cf0 1642 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1643 alignment = 4 * 1024;
1644 else
1645 alignment = 64 * 1024;
6b95a207
KH		 1646 break;
1647 case I915_TILING_X:
1648 /* pin() will align the object as required by fence */
1649 alignment = 0;
1650 break;
1651 case I915_TILING_Y:
1652 /* FIXME: Is this true? */
1653 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1654 return -EINVAL;
1655 default:
1656 BUG();
1657 }
1658
ce453d81 1659 dev_priv->mm.interruptible = false;
2da3b9b9 1660 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1661 if (ret)
ce453d81 1662 goto err_interruptible;
6b95a207
KH		 1663
1664 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1665 * fence, whereas 965+ only requires a fence if using
1666 * framebuffer compression. For simplicity, we always install
1667 * a fence as the cost is not that onerous.
1668 */
06d98131 1669 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1670 if (ret)
1671 goto err_unpin;
1690e1eb 1672
9a5a53b3 1673 i915_gem_object_pin_fence(obj);
6b95a207 1674
ce453d81 1675 dev_priv->mm.interruptible = true;
6b95a207 1676 return 0;
48b956c5
CW		 1677
1678err_unpin:
1679 i915_gem_object_unpin(obj);
ce453d81
CW		 1680err_interruptible:
1681 dev_priv->mm.interruptible = true;
48b956c5 1682 return ret;
6b95a207
KH		 1683}
1684
1690e1eb
CW		 1685void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1686{
1687 i915_gem_object_unpin_fence(obj);
1688 i915_gem_object_unpin(obj);
1689}
1690
17638cd6
JB		 1691static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1692 int x, int y)
81255565
JB		 1693{
1694 struct drm_device *dev = crtc->dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1697 struct intel_framebuffer *intel_fb;
05394f39 1698 struct drm_i915_gem_object *obj;
81255565
JB		 1699 int plane = intel_crtc->plane;
1700 unsigned long Start, Offset;
81255565 1701 u32 dspcntr;
5eddb70b 1702 u32 reg;
81255565
JB		 1703
1704 switch (plane) {
1705 case 0:
1706 case 1:
1707 break;
1708 default:
1709 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1710 return -EINVAL;
1711 }
1712
1713 intel_fb = to_intel_framebuffer(fb);
1714 obj = intel_fb->obj;
81255565 1715
5eddb70b
CW		 1716 reg = DSPCNTR(plane);
1717 dspcntr = I915_READ(reg);
81255565
JB		 1718 /* Mask out pixel format bits in case we change it */
1719 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1720 switch (fb->bits_per_pixel) {
1721 case 8:
1722 dspcntr |= DISPPLANE_8BPP;
1723 break;
1724 case 16:
1725 if (fb->depth == 15)
1726 dspcntr |= DISPPLANE_15_16BPP;
1727 else
1728 dspcntr |= DISPPLANE_16BPP;
1729 break;
1730 case 24:
1731 case 32:
1732 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1733 break;
1734 default:
17638cd6 1735 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1736 return -EINVAL;
1737 }
a6c45cf0 1738 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1739 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1740 dspcntr |= DISPPLANE_TILED;
1741 else
1742 dspcntr &= ~DISPPLANE_TILED;
1743 }
1744
5eddb70b 1745 I915_WRITE(reg, dspcntr);
81255565 1746
05394f39 1747 Start = obj->gtt_offset;
01f2c773 1748 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1749
4e6cfefc 1750 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1751 Start, Offset, x, y, fb->pitches[0]);
1752 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1753 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1754 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1755 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1756 I915_WRITE(DSPADDR(plane), Offset);
1757 } else
1758 I915_WRITE(DSPADDR(plane), Start + Offset);
1759 POSTING_READ(reg);
81255565 1760
17638cd6
JB		 1761 return 0;
1762}
1763
1764static int ironlake_update_plane(struct drm_crtc *crtc,
1765 struct drm_framebuffer *fb, int x, int y)
1766{
1767 struct drm_device *dev = crtc->dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1770 struct intel_framebuffer *intel_fb;
1771 struct drm_i915_gem_object *obj;
1772 int plane = intel_crtc->plane;
1773 unsigned long Start, Offset;
1774 u32 dspcntr;
1775 u32 reg;
1776
1777 switch (plane) {
1778 case 0:
1779 case 1:
27f8227b 1780 case 2:
17638cd6
JB		 1781 break;
1782 default:
1783 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1784 return -EINVAL;
1785 }
1786
1787 intel_fb = to_intel_framebuffer(fb);
1788 obj = intel_fb->obj;
1789
1790 reg = DSPCNTR(plane);
1791 dspcntr = I915_READ(reg);
1792 /* Mask out pixel format bits in case we change it */
1793 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1794 switch (fb->bits_per_pixel) {
1795 case 8:
1796 dspcntr |= DISPPLANE_8BPP;
1797 break;
1798 case 16:
1799 if (fb->depth != 16)
1800 return -EINVAL;
1801
1802 dspcntr |= DISPPLANE_16BPP;
1803 break;
1804 case 24:
1805 case 32:
1806 if (fb->depth == 24)
1807 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1808 else if (fb->depth == 30)
1809 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1810 else
1811 return -EINVAL;
1812 break;
1813 default:
1814 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1815 return -EINVAL;
1816 }
1817
1818 if (obj->tiling_mode != I915_TILING_NONE)
1819 dspcntr |= DISPPLANE_TILED;
1820 else
1821 dspcntr &= ~DISPPLANE_TILED;
1822
1823 /* must disable */
1824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1825
1826 I915_WRITE(reg, dspcntr);
1827
1828 Start = obj->gtt_offset;
01f2c773 1829 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1830
1831 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1832 Start, Offset, x, y, fb->pitches[0]);
1833 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1834 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1835 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1836 I915_WRITE(DSPADDR(plane), Offset);
1837 POSTING_READ(reg);
1838
1839 return 0;
1840}
1841
1842/* Assume fb object is pinned & idle & fenced and just update base pointers */
1843static int
1844intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1845 int x, int y, enum mode_set_atomic state)
1846{
1847 struct drm_device *dev = crtc->dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1849
6b8e6ed0
CW		 1850 if (dev_priv->display.disable_fbc)
1851 dev_priv->display.disable_fbc(dev);
3dec0095 1852 intel_increase_pllclock(crtc);
81255565 1853
6b8e6ed0 1854 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1855}
1856
14667a4b
CW		 1857static int
1858intel_finish_fb(struct drm_framebuffer *old_fb)
1859{
1860 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1861 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1862 bool was_interruptible = dev_priv->mm.interruptible;
1863 int ret;
1864
1865 wait_event(dev_priv->pending_flip_queue,
1866 atomic_read(&dev_priv->mm.wedged) ||
1867 atomic_read(&obj->pending_flip) == 0);
1868
1869 /* Big Hammer, we also need to ensure that any pending
1870 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1871 * current scanout is retired before unpinning the old
1872 * framebuffer.
1873 *
1874 * This should only fail upon a hung GPU, in which case we
1875 * can safely continue.
1876 */
1877 dev_priv->mm.interruptible = false;
1878 ret = i915_gem_object_finish_gpu(obj);
1879 dev_priv->mm.interruptible = was_interruptible;
1880
1881 return ret;
1882}
1883
5c3b82e2 1884static int
3c4fdcfb
KH		 1885intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1886 struct drm_framebuffer *old_fb)
79e53945
JB		 1887{
1888 struct drm_device *dev = crtc->dev;
6b8e6ed0 1889 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1890 struct drm_i915_master_private *master_priv;
1891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1892 int ret;
79e53945
JB		 1893
1894 /* no fb bound */
1895 if (!crtc->fb) {
a5071c2f 1896 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 1897 return 0;
1898 }
1899
265db958 1900 switch (intel_crtc->plane) {
5c3b82e2
CW		 1901 case 0:
1902 case 1:
1903 break;
27f8227b
JB		 1904 case 2:
1905 if (IS_IVYBRIDGE(dev))
1906 break;
1907 /* fall through otherwise */
5c3b82e2 1908 default:
a5071c2f 1909 DRM_ERROR("no plane for crtc\n");
5c3b82e2 1910 return -EINVAL;
79e53945
JB		 1911 }
1912
5c3b82e2 1913 mutex_lock(&dev->struct_mutex);
265db958
CW		 1914 ret = intel_pin_and_fence_fb_obj(dev,
1915 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1916 NULL);
5c3b82e2
CW		 1917 if (ret != 0) {
1918 mutex_unlock(&dev->struct_mutex);
a5071c2f 1919 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 1920 return ret;
1921 }
79e53945 1922
14667a4b
CW		 1923 if (old_fb)
1924 intel_finish_fb(old_fb);
265db958 1925
6b8e6ed0 1926 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 1927 if (ret) {
1690e1eb 1928 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1929 mutex_unlock(&dev->struct_mutex);
a5071c2f 1930 DRM_ERROR("failed to update base address\n");
4e6cfefc 1931 return ret;
79e53945 1932 }
3c4fdcfb 1933
b7f1de28
CW		 1934 if (old_fb) {
1935 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 1936 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 1937 }
652c393a 1938
6b8e6ed0 1939 intel_update_fbc(dev);
5c3b82e2 1940 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1941
1942 if (!dev->primary->master)
5c3b82e2 1943 return 0;
79e53945
JB		 1944
1945 master_priv = dev->primary->master->driver_priv;
1946 if (!master_priv->sarea_priv)
5c3b82e2 1947 return 0;
79e53945 1948
265db958 1949 if (intel_crtc->pipe) {
79e53945
JB		 1950 master_priv->sarea_priv->pipeB_x = x;
1951 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 1952 } else {
1953 master_priv->sarea_priv->pipeA_x = x;
1954 master_priv->sarea_priv->pipeA_y = y;
79e53945 1955 }
5c3b82e2
CW		 1956
1957 return 0;
79e53945
JB		 1958}
1959
5eddb70b 1960static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 1961{
1962 struct drm_device *dev = crtc->dev;
1963 struct drm_i915_private *dev_priv = dev->dev_private;
1964 u32 dpa_ctl;
1965
28c97730 1966 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 1967 dpa_ctl = I915_READ(DP_A);
1968 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1969
1970 if (clock < 200000) {
1971 u32 temp;
1972 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1973 /* workaround for 160Mhz:
1974 1) program 0x4600c bits 15:0 = 0x8124
1975 2) program 0x46010 bit 0 = 1
1976 3) program 0x46034 bit 24 = 1
1977 4) program 0x64000 bit 14 = 1
1978 */
1979 temp = I915_READ(0x4600c);
1980 temp &= 0xffff0000;
1981 I915_WRITE(0x4600c, temp | 0x8124);
1982
1983 temp = I915_READ(0x46010);
1984 I915_WRITE(0x46010, temp | 1);
1985
1986 temp = I915_READ(0x46034);
1987 I915_WRITE(0x46034, temp | (1 << 24));
1988 } else {
1989 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1990 }
1991 I915_WRITE(DP_A, dpa_ctl);
1992
5eddb70b 1993 POSTING_READ(DP_A);
32f9d658
ZW		 1994 udelay(500);
1995}
1996
5e84e1a4
ZW		 1997static void intel_fdi_normal_train(struct drm_crtc *crtc)
1998{
1999 struct drm_device *dev = crtc->dev;
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2002 int pipe = intel_crtc->pipe;
2003 u32 reg, temp;
2004
2005 /* enable normal train */
2006 reg = FDI_TX_CTL(pipe);
2007 temp = I915_READ(reg);
61e499bf 2008 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2009 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2010 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2011 } else {
2012 temp &= ~FDI_LINK_TRAIN_NONE;
2013 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2014 }
5e84e1a4
ZW		 2015 I915_WRITE(reg, temp);
2016
2017 reg = FDI_RX_CTL(pipe);
2018 temp = I915_READ(reg);
2019 if (HAS_PCH_CPT(dev)) {
2020 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2021 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2022 } else {
2023 temp &= ~FDI_LINK_TRAIN_NONE;
2024 temp |= FDI_LINK_TRAIN_NONE;
2025 }
2026 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2027
2028 /* wait one idle pattern time */
2029 POSTING_READ(reg);
2030 udelay(1000);
357555c0
JB		 2031
2032 /* IVB wants error correction enabled */
2033 if (IS_IVYBRIDGE(dev))
2034 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2035 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2036}
2037
291427f5
JB		 2038static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2039{
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 u32 flags = I915_READ(SOUTH_CHICKEN1);
2042
2043 flags |= FDI_PHASE_SYNC_OVR(pipe);
2044 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2045 flags |= FDI_PHASE_SYNC_EN(pipe);
2046 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2047 POSTING_READ(SOUTH_CHICKEN1);
2048}
2049
8db9d77b
ZW		 2050/* The FDI link training functions for ILK/Ibexpeak. */
2051static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2052{
2053 struct drm_device *dev = crtc->dev;
2054 struct drm_i915_private *dev_priv = dev->dev_private;
2055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2056 int pipe = intel_crtc->pipe;
0fc932b8 2057 int plane = intel_crtc->plane;
5eddb70b 2058 u32 reg, temp, tries;
8db9d77b 2059
0fc932b8
JB		 2060 /* FDI needs bits from pipe & plane first */
2061 assert_pipe_enabled(dev_priv, pipe);
2062 assert_plane_enabled(dev_priv, plane);
2063
e1a44743
AJ		 2064 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2065 for train result */
5eddb70b
CW		 2066 reg = FDI_RX_IMR(pipe);
2067 temp = I915_READ(reg);
e1a44743
AJ		 2068 temp &= ~FDI_RX_SYMBOL_LOCK;
2069 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2070 I915_WRITE(reg, temp);
2071 I915_READ(reg);
e1a44743
AJ		 2072 udelay(150);
2073
8db9d77b 2074 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2075 reg = FDI_TX_CTL(pipe);
2076 temp = I915_READ(reg);
77ffb597
AJ		 2077 temp &= ~(7 << 19);
2078 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2079 temp &= ~FDI_LINK_TRAIN_NONE;
2080 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2081 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2082
5eddb70b
CW		 2083 reg = FDI_RX_CTL(pipe);
2084 temp = I915_READ(reg);
8db9d77b
ZW		 2085 temp &= ~FDI_LINK_TRAIN_NONE;
2086 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2087 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2088
2089 POSTING_READ(reg);
8db9d77b
ZW		 2090 udelay(150);
2091
5b2adf89 2092 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2093 if (HAS_PCH_IBX(dev)) {
2094 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2095 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2096 FDI_RX_PHASE_SYNC_POINTER_EN);
2097 }
5b2adf89 2098
5eddb70b 2099 reg = FDI_RX_IIR(pipe);
e1a44743 2100 for (tries = 0; tries < 5; tries++) {
5eddb70b 2101 temp = I915_READ(reg);
8db9d77b
ZW		 2102 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2103
2104 if ((temp & FDI_RX_BIT_LOCK)) {
2105 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2106 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2107 break;
2108 }
8db9d77b 2109 }
e1a44743 2110 if (tries == 5)
5eddb70b 2111 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2112
2113 /* Train 2 */
5eddb70b
CW		 2114 reg = FDI_TX_CTL(pipe);
2115 temp = I915_READ(reg);
8db9d77b
ZW		 2116 temp &= ~FDI_LINK_TRAIN_NONE;
2117 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2118 I915_WRITE(reg, temp);
8db9d77b 2119
5eddb70b
CW		 2120 reg = FDI_RX_CTL(pipe);
2121 temp = I915_READ(reg);
8db9d77b
ZW		 2122 temp &= ~FDI_LINK_TRAIN_NONE;
2123 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2124 I915_WRITE(reg, temp);
8db9d77b 2125
5eddb70b
CW		 2126 POSTING_READ(reg);
2127 udelay(150);
8db9d77b 2128
5eddb70b 2129 reg = FDI_RX_IIR(pipe);
e1a44743 2130 for (tries = 0; tries < 5; tries++) {
5eddb70b 2131 temp = I915_READ(reg);
8db9d77b
ZW		 2132 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2133
2134 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2135 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2136 DRM_DEBUG_KMS("FDI train 2 done.\n");
2137 break;
2138 }
8db9d77b 2139 }
e1a44743 2140 if (tries == 5)
5eddb70b 2141 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2142
2143 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2144
8db9d77b
ZW		 2145}
2146
0206e353 2147static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2148 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2149 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2150 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2151 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2152};
2153
2154/* The FDI link training functions for SNB/Cougarpoint. */
2155static void gen6_fdi_link_train(struct drm_crtc *crtc)
2156{
2157 struct drm_device *dev = crtc->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160 int pipe = intel_crtc->pipe;
fa37d39e 2161 u32 reg, temp, i, retry;
8db9d77b 2162
e1a44743
AJ		 2163 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2164 for train result */
5eddb70b
CW		 2165 reg = FDI_RX_IMR(pipe);
2166 temp = I915_READ(reg);
e1a44743
AJ		 2167 temp &= ~FDI_RX_SYMBOL_LOCK;
2168 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2169 I915_WRITE(reg, temp);
2170
2171 POSTING_READ(reg);
e1a44743
AJ		 2172 udelay(150);
2173
8db9d77b 2174 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2175 reg = FDI_TX_CTL(pipe);
2176 temp = I915_READ(reg);
77ffb597
AJ		 2177 temp &= ~(7 << 19);
2178 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2179 temp &= ~FDI_LINK_TRAIN_NONE;
2180 temp |= FDI_LINK_TRAIN_PATTERN_1;
2181 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2182 /* SNB-B */
2183 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2184 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2185
5eddb70b
CW		 2186 reg = FDI_RX_CTL(pipe);
2187 temp = I915_READ(reg);
8db9d77b
ZW		 2188 if (HAS_PCH_CPT(dev)) {
2189 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2190 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2191 } else {
2192 temp &= ~FDI_LINK_TRAIN_NONE;
2193 temp |= FDI_LINK_TRAIN_PATTERN_1;
2194 }
5eddb70b
CW		 2195 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2196
2197 POSTING_READ(reg);
8db9d77b
ZW		 2198 udelay(150);
2199
291427f5
JB		 2200 if (HAS_PCH_CPT(dev))
2201 cpt_phase_pointer_enable(dev, pipe);
2202
0206e353 2203 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2204 reg = FDI_TX_CTL(pipe);
2205 temp = I915_READ(reg);
8db9d77b
ZW		 2206 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2207 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2208 I915_WRITE(reg, temp);
2209
2210 POSTING_READ(reg);
8db9d77b
ZW		 2211 udelay(500);
2212
fa37d39e
SP		 2213 for (retry = 0; retry < 5; retry++) {
2214 reg = FDI_RX_IIR(pipe);
2215 temp = I915_READ(reg);
2216 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2217 if (temp & FDI_RX_BIT_LOCK) {
2218 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2219 DRM_DEBUG_KMS("FDI train 1 done.\n");
2220 break;
2221 }
2222 udelay(50);
8db9d77b 2223 }
fa37d39e
SP		 2224 if (retry < 5)
2225 break;
8db9d77b
ZW		 2226 }
2227 if (i == 4)
5eddb70b 2228 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2229
2230 /* Train 2 */
5eddb70b
CW		 2231 reg = FDI_TX_CTL(pipe);
2232 temp = I915_READ(reg);
8db9d77b
ZW		 2233 temp &= ~FDI_LINK_TRAIN_NONE;
2234 temp |= FDI_LINK_TRAIN_PATTERN_2;
2235 if (IS_GEN6(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2237 /* SNB-B */
2238 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2239 }
5eddb70b 2240 I915_WRITE(reg, temp);
8db9d77b 2241
5eddb70b
CW		 2242 reg = FDI_RX_CTL(pipe);
2243 temp = I915_READ(reg);
8db9d77b
ZW		 2244 if (HAS_PCH_CPT(dev)) {
2245 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2246 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2247 } else {
2248 temp &= ~FDI_LINK_TRAIN_NONE;
2249 temp |= FDI_LINK_TRAIN_PATTERN_2;
2250 }
5eddb70b
CW		 2251 I915_WRITE(reg, temp);
2252
2253 POSTING_READ(reg);
8db9d77b
ZW		 2254 udelay(150);
2255
0206e353 2256 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2257 reg = FDI_TX_CTL(pipe);
2258 temp = I915_READ(reg);
8db9d77b
ZW		 2259 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2260 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2261 I915_WRITE(reg, temp);
2262
2263 POSTING_READ(reg);
8db9d77b
ZW		 2264 udelay(500);
2265
fa37d39e
SP		 2266 for (retry = 0; retry < 5; retry++) {
2267 reg = FDI_RX_IIR(pipe);
2268 temp = I915_READ(reg);
2269 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2270 if (temp & FDI_RX_SYMBOL_LOCK) {
2271 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2272 DRM_DEBUG_KMS("FDI train 2 done.\n");
2273 break;
2274 }
2275 udelay(50);
8db9d77b 2276 }
fa37d39e
SP		 2277 if (retry < 5)
2278 break;
8db9d77b
ZW		 2279 }
2280 if (i == 4)
5eddb70b 2281 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2282
2283 DRM_DEBUG_KMS("FDI train done.\n");
2284}
2285
357555c0
JB		 2286/* Manual link training for Ivy Bridge A0 parts */
2287static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2288{
2289 struct drm_device *dev = crtc->dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292 int pipe = intel_crtc->pipe;
2293 u32 reg, temp, i;
2294
2295 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2296 for train result */
2297 reg = FDI_RX_IMR(pipe);
2298 temp = I915_READ(reg);
2299 temp &= ~FDI_RX_SYMBOL_LOCK;
2300 temp &= ~FDI_RX_BIT_LOCK;
2301 I915_WRITE(reg, temp);
2302
2303 POSTING_READ(reg);
2304 udelay(150);
2305
2306 /* enable CPU FDI TX and PCH FDI RX */
2307 reg = FDI_TX_CTL(pipe);
2308 temp = I915_READ(reg);
2309 temp &= ~(7 << 19);
2310 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2311 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2312 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2313 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2314 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2315 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2317
2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 temp &= ~FDI_LINK_TRAIN_AUTO;
2321 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2322 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2323 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2324 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2325
2326 POSTING_READ(reg);
2327 udelay(150);
2328
291427f5
JB		 2329 if (HAS_PCH_CPT(dev))
2330 cpt_phase_pointer_enable(dev, pipe);
2331
0206e353 2332 for (i = 0; i < 4; i++) {
357555c0
JB		 2333 reg = FDI_TX_CTL(pipe);
2334 temp = I915_READ(reg);
2335 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2336 temp |= snb_b_fdi_train_param[i];
2337 I915_WRITE(reg, temp);
2338
2339 POSTING_READ(reg);
2340 udelay(500);
2341
2342 reg = FDI_RX_IIR(pipe);
2343 temp = I915_READ(reg);
2344 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2345
2346 if (temp & FDI_RX_BIT_LOCK ||
2347 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2348 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2349 DRM_DEBUG_KMS("FDI train 1 done.\n");
2350 break;
2351 }
2352 }
2353 if (i == 4)
2354 DRM_ERROR("FDI train 1 fail!\n");
2355
2356 /* Train 2 */
2357 reg = FDI_TX_CTL(pipe);
2358 temp = I915_READ(reg);
2359 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2360 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2361 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2362 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2363 I915_WRITE(reg, temp);
2364
2365 reg = FDI_RX_CTL(pipe);
2366 temp = I915_READ(reg);
2367 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2369 I915_WRITE(reg, temp);
2370
2371 POSTING_READ(reg);
2372 udelay(150);
2373
0206e353 2374 for (i = 0; i < 4; i++) {
357555c0
JB		 2375 reg = FDI_TX_CTL(pipe);
2376 temp = I915_READ(reg);
2377 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2378 temp |= snb_b_fdi_train_param[i];
2379 I915_WRITE(reg, temp);
2380
2381 POSTING_READ(reg);
2382 udelay(500);
2383
2384 reg = FDI_RX_IIR(pipe);
2385 temp = I915_READ(reg);
2386 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2387
2388 if (temp & FDI_RX_SYMBOL_LOCK) {
2389 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2390 DRM_DEBUG_KMS("FDI train 2 done.\n");
2391 break;
2392 }
2393 }
2394 if (i == 4)
2395 DRM_ERROR("FDI train 2 fail!\n");
2396
2397 DRM_DEBUG_KMS("FDI train done.\n");
2398}
2399
2400static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2401{
2402 struct drm_device *dev = crtc->dev;
2403 struct drm_i915_private *dev_priv = dev->dev_private;
2404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2405 int pipe = intel_crtc->pipe;
5eddb70b 2406 u32 reg, temp;
79e53945 2407
c64e311e 2408 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2409 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2410 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2411
c98e9dcf 2412 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2413 reg = FDI_RX_CTL(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2416 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2417 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2418 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2419
2420 POSTING_READ(reg);
c98e9dcf
JB		 2421 udelay(200);
2422
2423 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2424 temp = I915_READ(reg);
2425 I915_WRITE(reg, temp | FDI_PCDCLK);
2426
2427 POSTING_READ(reg);
c98e9dcf
JB		 2428 udelay(200);
2429
2430 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
c98e9dcf 2433 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2434 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2435
2436 POSTING_READ(reg);
c98e9dcf 2437 udelay(100);
6be4a607 2438 }
0e23b99d
JB		 2439}
2440
291427f5
JB		 2441static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2442{
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 u32 flags = I915_READ(SOUTH_CHICKEN1);
2445
2446 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2447 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2448 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2449 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2450 POSTING_READ(SOUTH_CHICKEN1);
2451}
0fc932b8
JB		 2452static void ironlake_fdi_disable(struct drm_crtc *crtc)
2453{
2454 struct drm_device *dev = crtc->dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457 int pipe = intel_crtc->pipe;
2458 u32 reg, temp;
2459
2460 /* disable CPU FDI tx and PCH FDI rx */
2461 reg = FDI_TX_CTL(pipe);
2462 temp = I915_READ(reg);
2463 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2464 POSTING_READ(reg);
2465
2466 reg = FDI_RX_CTL(pipe);
2467 temp = I915_READ(reg);
2468 temp &= ~(0x7 << 16);
2469 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2470 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2471
2472 POSTING_READ(reg);
2473 udelay(100);
2474
2475 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2476 if (HAS_PCH_IBX(dev)) {
2477 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2478 I915_WRITE(FDI_RX_CHICKEN(pipe),
2479 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2480 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2481 } else if (HAS_PCH_CPT(dev)) {
2482 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2483 }
0fc932b8
JB		 2484
2485 /* still set train pattern 1 */
2486 reg = FDI_TX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490 I915_WRITE(reg, temp);
2491
2492 reg = FDI_RX_CTL(pipe);
2493 temp = I915_READ(reg);
2494 if (HAS_PCH_CPT(dev)) {
2495 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2496 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2497 } else {
2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_1;
2500 }
2501 /* BPC in FDI rx is consistent with that in PIPECONF */
2502 temp &= ~(0x07 << 16);
2503 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
2507 udelay(100);
2508}
2509
6b383a7f
CW		 2510/*
2511 * When we disable a pipe, we need to clear any pending scanline wait events
2512 * to avoid hanging the ring, which we assume we are waiting on.
2513 */
2514static void intel_clear_scanline_wait(struct drm_device *dev)
2515{
2516 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2517 struct intel_ring_buffer *ring;
6b383a7f
CW		 2518 u32 tmp;
2519
2520 if (IS_GEN2(dev))
2521 /* Can't break the hang on i8xx */
2522 return;
2523
1ec14ad3 2524 ring = LP_RING(dev_priv);
8168bd48
CW		 2525 tmp = I915_READ_CTL(ring);
2526 if (tmp & RING_WAIT)
2527 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2528}
2529
e6c3a2a6
CW		 2530static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2531{
0f91128d 2532 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2533
2534 if (crtc->fb == NULL)
2535 return;
2536
0f91128d
CW		 2537 mutex_lock(&dev->struct_mutex);
2538 intel_finish_fb(crtc->fb);
2539 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2540}
2541
040484af
JB		 2542static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2543{
2544 struct drm_device *dev = crtc->dev;
2545 struct drm_mode_config *mode_config = &dev->mode_config;
2546 struct intel_encoder *encoder;
2547
2548 /*
2549 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2550 * must be driven by its own crtc; no sharing is possible.
2551 */
2552 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2553 if (encoder->base.crtc != crtc)
2554 continue;
2555
2556 switch (encoder->type) {
2557 case INTEL_OUTPUT_EDP:
2558 if (!intel_encoder_is_pch_edp(&encoder->base))
2559 return false;
2560 continue;
2561 }
2562 }
2563
2564 return true;
2565}
2566
f67a559d
JB		 2567/*
2568 * Enable PCH resources required for PCH ports:
2569 * - PCH PLLs
2570 * - FDI training & RX/TX
2571 * - update transcoder timings
2572 * - DP transcoding bits
2573 * - transcoder
2574 */
2575static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2576{
2577 struct drm_device *dev = crtc->dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580 int pipe = intel_crtc->pipe;
4b645f14 2581 u32 reg, temp, transc_sel;
2c07245f 2582
c98e9dcf 2583 /* For PCH output, training FDI link */
674cf967 2584 dev_priv->display.fdi_link_train(crtc);
2c07245f 2585
92f2584a 2586 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2587
c98e9dcf 2588 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2589 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2590 TRANSC_DPLLB_SEL;
2591
c98e9dcf
JB		 2592 /* Be sure PCH DPLL SEL is set */
2593 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2594 if (pipe == 0) {
2595 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2596 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2597 } else if (pipe == 1) {
2598 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2599 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2600 } else if (pipe == 2) {
2601 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2602 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2603 }
c98e9dcf 2604 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2605 }
5eddb70b 2606
d9b6cb56
JB		 2607 /* set transcoder timing, panel must allow it */
2608 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2609 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2610 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2611 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2612
5eddb70b
CW		 2613 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2614 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2615 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2616 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2617
5e84e1a4
ZW		 2618 intel_fdi_normal_train(crtc);
2619
c98e9dcf
JB		 2620 /* For PCH DP, enable TRANS_DP_CTL */
2621 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2622 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2623 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2624 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2625 reg = TRANS_DP_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2628 TRANS_DP_SYNC_MASK |
2629 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2630 temp |= (TRANS_DP_OUTPUT_ENABLE |
2631 TRANS_DP_ENH_FRAMING);
9325c9f0 2632 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2633
2634 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2635 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2636 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2637 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2638
2639 switch (intel_trans_dp_port_sel(crtc)) {
2640 case PCH_DP_B:
5eddb70b 2641 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2642 break;
2643 case PCH_DP_C:
5eddb70b 2644 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2645 break;
2646 case PCH_DP_D:
5eddb70b 2647 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2648 break;
2649 default:
2650 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2651 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2652 break;
32f9d658 2653 }
2c07245f 2654
5eddb70b 2655 I915_WRITE(reg, temp);
6be4a607 2656 }
b52eb4dc 2657
040484af 2658 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2659}
2660
d4270e57
JB		 2661void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2662{
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2665 u32 temp;
2666
2667 temp = I915_READ(dslreg);
2668 udelay(500);
2669 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2670 /* Without this, mode sets may fail silently on FDI */
2671 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2672 udelay(250);
2673 I915_WRITE(tc2reg, 0);
2674 if (wait_for(I915_READ(dslreg) != temp, 5))
2675 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2676 }
2677}
2678
f67a559d
JB		 2679static void ironlake_crtc_enable(struct drm_crtc *crtc)
2680{
2681 struct drm_device *dev = crtc->dev;
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2684 int pipe = intel_crtc->pipe;
2685 int plane = intel_crtc->plane;
2686 u32 temp;
2687 bool is_pch_port;
2688
2689 if (intel_crtc->active)
2690 return;
2691
2692 intel_crtc->active = true;
2693 intel_update_watermarks(dev);
2694
2695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2696 temp = I915_READ(PCH_LVDS);
2697 if ((temp & LVDS_PORT_EN) == 0)
2698 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2699 }
2700
2701 is_pch_port = intel_crtc_driving_pch(crtc);
2702
2703 if (is_pch_port)
357555c0 2704 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2705 else
2706 ironlake_fdi_disable(crtc);
2707
2708 /* Enable panel fitting for LVDS */
2709 if (dev_priv->pch_pf_size &&
2710 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2711 /* Force use of hard-coded filter coefficients
2712 * as some pre-programmed values are broken,
2713 * e.g. x201.
2714 */
9db4a9c7
JB		 2715 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2716 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2717 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2718 }
2719
9c54c0dd
JB		 2720 /*
2721 * On ILK+ LUT must be loaded before the pipe is running but with
2722 * clocks enabled
2723 */
2724 intel_crtc_load_lut(crtc);
2725
f67a559d
JB		 2726 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2727 intel_enable_plane(dev_priv, plane, pipe);
2728
2729 if (is_pch_port)
2730 ironlake_pch_enable(crtc);
c98e9dcf 2731
d1ebd816 2732 mutex_lock(&dev->struct_mutex);
bed4a673 2733 intel_update_fbc(dev);
d1ebd816
BW		 2734 mutex_unlock(&dev->struct_mutex);
2735
6b383a7f 2736 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2737}
2738
2739static void ironlake_crtc_disable(struct drm_crtc *crtc)
2740{
2741 struct drm_device *dev = crtc->dev;
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2744 int pipe = intel_crtc->pipe;
2745 int plane = intel_crtc->plane;
5eddb70b 2746 u32 reg, temp;
b52eb4dc 2747
f7abfe8b
CW		 2748 if (!intel_crtc->active)
2749 return;
2750
e6c3a2a6 2751 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2752 drm_vblank_off(dev, pipe);
6b383a7f 2753 intel_crtc_update_cursor(crtc, false);
5eddb70b 2754
b24e7179 2755 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2756
973d04f9
CW		 2757 if (dev_priv->cfb_plane == plane)
2758 intel_disable_fbc(dev);
2c07245f 2759
b24e7179 2760 intel_disable_pipe(dev_priv, pipe);
32f9d658 2761
6be4a607 2762 /* Disable PF */
9db4a9c7
JB		 2763 I915_WRITE(PF_CTL(pipe), 0);
2764 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2765
0fc932b8 2766 ironlake_fdi_disable(crtc);
2c07245f 2767
47a05eca
JB		 2768 /* This is a horrible layering violation; we should be doing this in
2769 * the connector/encoder ->prepare instead, but we don't always have
2770 * enough information there about the config to know whether it will
2771 * actually be necessary or just cause undesired flicker.
2772 */
2773 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2774
040484af 2775 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2776
6be4a607
JB		 2777 if (HAS_PCH_CPT(dev)) {
2778 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2779 reg = TRANS_DP_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2782 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2783 I915_WRITE(reg, temp);
6be4a607
JB		 2784
2785 /* disable DPLL_SEL */
2786 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2787 switch (pipe) {
2788 case 0:
d64311ab 2789 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 2790 break;
2791 case 1:
6be4a607 2792 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2793 break;
2794 case 2:
4b645f14 2795 /* C shares PLL A or B */
d64311ab 2796 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 2797 break;
2798 default:
2799 BUG(); /* wtf */
2800 }
6be4a607 2801 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2802 }
e3421a18 2803
6be4a607 2804 /* disable PCH DPLL */
4b645f14
JB		 2805 if (!intel_crtc->no_pll)
2806 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2807
6be4a607 2808 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2812
6be4a607 2813 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2817
2818 POSTING_READ(reg);
6be4a607 2819 udelay(100);
8db9d77b 2820
5eddb70b
CW		 2821 reg = FDI_RX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2824
6be4a607 2825 /* Wait for the clocks to turn off. */
5eddb70b 2826 POSTING_READ(reg);
6be4a607 2827 udelay(100);
6b383a7f 2828
f7abfe8b 2829 intel_crtc->active = false;
6b383a7f 2830 intel_update_watermarks(dev);
d1ebd816
BW		 2831
2832 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2833 intel_update_fbc(dev);
2834 intel_clear_scanline_wait(dev);
d1ebd816 2835 mutex_unlock(&dev->struct_mutex);
6be4a607 2836}
1b3c7a47 2837
6be4a607
JB		 2838static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2839{
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 int pipe = intel_crtc->pipe;
2842 int plane = intel_crtc->plane;
8db9d77b 2843
6be4a607
JB		 2844 /* XXX: When our outputs are all unaware of DPMS modes other than off
2845 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2846 */
2847 switch (mode) {
2848 case DRM_MODE_DPMS_ON:
2849 case DRM_MODE_DPMS_STANDBY:
2850 case DRM_MODE_DPMS_SUSPEND:
2851 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2852 ironlake_crtc_enable(crtc);
2853 break;
1b3c7a47 2854
6be4a607
JB		 2855 case DRM_MODE_DPMS_OFF:
2856 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2857 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2858 break;
2859 }
2860}
2861
02e792fb
DV		 2862static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2863{
02e792fb 2864 if (!enable && intel_crtc->overlay) {
23f09ce3 2865 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2866 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2867
23f09ce3 2868 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2869 dev_priv->mm.interruptible = false;
2870 (void) intel_overlay_switch_off(intel_crtc->overlay);
2871 dev_priv->mm.interruptible = true;
23f09ce3 2872 mutex_unlock(&dev->struct_mutex);
02e792fb 2873 }
02e792fb 2874
5dcdbcb0
CW		 2875 /* Let userspace switch the overlay on again. In most cases userspace
2876 * has to recompute where to put it anyway.
2877 */
02e792fb
DV		 2878}
2879
0b8765c6 2880static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2881{
2882 struct drm_device *dev = crtc->dev;
79e53945
JB		 2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 int pipe = intel_crtc->pipe;
80824003 2886 int plane = intel_crtc->plane;
79e53945 2887
f7abfe8b
CW		 2888 if (intel_crtc->active)
2889 return;
2890
2891 intel_crtc->active = true;
6b383a7f
CW		 2892 intel_update_watermarks(dev);
2893
63d7bbe9 2894 intel_enable_pll(dev_priv, pipe);
040484af 2895 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2896 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2897
0b8765c6 2898 intel_crtc_load_lut(crtc);
bed4a673 2899 intel_update_fbc(dev);
79e53945 2900
0b8765c6
JB		 2901 /* Give the overlay scaler a chance to enable if it's on this pipe */
2902 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2903 intel_crtc_update_cursor(crtc, true);
0b8765c6 2904}
79e53945 2905
0b8765c6
JB		 2906static void i9xx_crtc_disable(struct drm_crtc *crtc)
2907{
2908 struct drm_device *dev = crtc->dev;
2909 struct drm_i915_private *dev_priv = dev->dev_private;
2910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2911 int pipe = intel_crtc->pipe;
2912 int plane = intel_crtc->plane;
b690e96c 2913
f7abfe8b
CW		 2914 if (!intel_crtc->active)
2915 return;
2916
0b8765c6 2917 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2918 intel_crtc_wait_for_pending_flips(crtc);
2919 drm_vblank_off(dev, pipe);
0b8765c6 2920 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2921 intel_crtc_update_cursor(crtc, false);
0b8765c6 2922
973d04f9
CW		 2923 if (dev_priv->cfb_plane == plane)
2924 intel_disable_fbc(dev);
79e53945 2925
b24e7179 2926 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2927 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2928 intel_disable_pll(dev_priv, pipe);
0b8765c6 2929
f7abfe8b 2930 intel_crtc->active = false;
6b383a7f
CW		 2931 intel_update_fbc(dev);
2932 intel_update_watermarks(dev);
2933 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2934}
2935
2936static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2937{
2938 /* XXX: When our outputs are all unaware of DPMS modes other than off
2939 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2940 */
2941 switch (mode) {
2942 case DRM_MODE_DPMS_ON:
2943 case DRM_MODE_DPMS_STANDBY:
2944 case DRM_MODE_DPMS_SUSPEND:
2945 i9xx_crtc_enable(crtc);
2946 break;
2947 case DRM_MODE_DPMS_OFF:
2948 i9xx_crtc_disable(crtc);
79e53945
JB		 2949 break;
2950 }
2c07245f
ZW		 2951}
2952
2953/**
2954 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2955 */
2956static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2957{
2958 struct drm_device *dev = crtc->dev;
e70236a8 2959 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2960 struct drm_i915_master_private *master_priv;
2961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2962 int pipe = intel_crtc->pipe;
2963 bool enabled;
2964
032d2a0d
CW		 2965 if (intel_crtc->dpms_mode == mode)
2966 return;
2967
65655d4a 2968 intel_crtc->dpms_mode = mode;
debcaddc 2969
e70236a8 2970 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2971
2972 if (!dev->primary->master)
2973 return;
2974
2975 master_priv = dev->primary->master->driver_priv;
2976 if (!master_priv->sarea_priv)
2977 return;
2978
2979 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2980
2981 switch (pipe) {
2982 case 0:
2983 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2984 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2985 break;
2986 case 1:
2987 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2988 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2989 break;
2990 default:
9db4a9c7 2991 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2992 break;
2993 }
79e53945
JB		 2994}
2995
cdd59983
CW		 2996static void intel_crtc_disable(struct drm_crtc *crtc)
2997{
2998 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2999 struct drm_device *dev = crtc->dev;
3000
3001 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3002 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3003 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3004
3005 if (crtc->fb) {
3006 mutex_lock(&dev->struct_mutex);
1690e1eb 3007 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3008 mutex_unlock(&dev->struct_mutex);
3009 }
3010}
3011
7e7d76c3
JB		 3012/* Prepare for a mode set.
3013 *
3014 * Note we could be a lot smarter here. We need to figure out which outputs
3015 * will be enabled, which disabled (in short, how the config will changes)
3016 * and perform the minimum necessary steps to accomplish that, e.g. updating
3017 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3018 * panel fitting is in the proper state, etc.
3019 */
3020static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3021{
7e7d76c3 3022 i9xx_crtc_disable(crtc);
79e53945
JB		 3023}
3024
7e7d76c3 3025static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3026{
7e7d76c3 3027 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3028}
3029
3030static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3031{
7e7d76c3 3032 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3033}
3034
3035static void ironlake_crtc_commit(struct drm_crtc *crtc)
3036{
7e7d76c3 3037 ironlake_crtc_enable(crtc);
79e53945
JB		 3038}
3039
0206e353 3040void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3041{
3042 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3043 /* lvds has its own version of prepare see intel_lvds_prepare */
3044 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3045}
3046
0206e353 3047void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3048{
3049 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3050 struct drm_device *dev = encoder->dev;
3051 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3052 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3053
79e53945
JB		 3054 /* lvds has its own version of commit see intel_lvds_commit */
3055 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3056
3057 if (HAS_PCH_CPT(dev))
3058 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3059}
3060
ea5b213a
CW		 3061void intel_encoder_destroy(struct drm_encoder *encoder)
3062{
4ef69c7a 3063 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3064
ea5b213a
CW		 3065 drm_encoder_cleanup(encoder);
3066 kfree(intel_encoder);
3067}
3068
79e53945
JB		 3069static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3070 struct drm_display_mode *mode,
3071 struct drm_display_mode *adjusted_mode)
3072{
2c07245f 3073 struct drm_device *dev = crtc->dev;
89749350 3074
bad720ff 3075 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3076 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3077 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3078 return false;
2c07245f 3079 }
89749350 3080
ca9bfa7e
DV		 3081 /* All interlaced capable intel hw wants timings in frames. */
3082 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3083
79e53945
JB		 3084 return true;
3085}
3086
25eb05fc
JB		 3087static int valleyview_get_display_clock_speed(struct drm_device *dev)
3088{
3089 return 400000; /* FIXME */
3090}
3091
e70236a8
JB		 3092static int i945_get_display_clock_speed(struct drm_device *dev)
3093{
3094 return 400000;
3095}
79e53945 3096
e70236a8 3097static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3098{
e70236a8
JB		 3099 return 333000;
3100}
79e53945 3101
e70236a8
JB		 3102static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3103{
3104 return 200000;
3105}
79e53945 3106
e70236a8
JB		 3107static int i915gm_get_display_clock_speed(struct drm_device *dev)
3108{
3109 u16 gcfgc = 0;
79e53945 3110
e70236a8
JB		 3111 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3112
3113 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3114 return 133000;
3115 else {
3116 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3117 case GC_DISPLAY_CLOCK_333_MHZ:
3118 return 333000;
3119 default:
3120 case GC_DISPLAY_CLOCK_190_200_MHZ:
3121 return 190000;
79e53945 3122 }
e70236a8
JB		 3123 }
3124}
3125
3126static int i865_get_display_clock_speed(struct drm_device *dev)
3127{
3128 return 266000;
3129}
3130
3131static int i855_get_display_clock_speed(struct drm_device *dev)
3132{
3133 u16 hpllcc = 0;
3134 /* Assume that the hardware is in the high speed state. This
3135 * should be the default.
3136 */
3137 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3138 case GC_CLOCK_133_200:
3139 case GC_CLOCK_100_200:
3140 return 200000;
3141 case GC_CLOCK_166_250:
3142 return 250000;
3143 case GC_CLOCK_100_133:
79e53945 3144 return 133000;
e70236a8 3145 }
79e53945 3146
e70236a8
JB		 3147 /* Shouldn't happen */
3148 return 0;
3149}
79e53945 3150
e70236a8
JB		 3151static int i830_get_display_clock_speed(struct drm_device *dev)
3152{
3153 return 133000;
79e53945
JB		 3154}
3155
2c07245f
ZW		 3156struct fdi_m_n {
3157 u32 tu;
3158 u32 gmch_m;
3159 u32 gmch_n;
3160 u32 link_m;
3161 u32 link_n;
3162};
3163
3164static void
3165fdi_reduce_ratio(u32 *num, u32 *den)
3166{
3167 while (*num > 0xffffff || *den > 0xffffff) {
3168 *num >>= 1;
3169 *den >>= 1;
3170 }
3171}
3172
2c07245f 3173static void
f2b115e6
AJ		 3174ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3175 int link_clock, struct fdi_m_n *m_n)
2c07245f 3176{
2c07245f
ZW		 3177 m_n->tu = 64; /* default size */
3178
22ed1113
CW		 3179 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3180 m_n->gmch_m = bits_per_pixel * pixel_clock;
3181 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3182 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3183
22ed1113
CW		 3184 m_n->link_m = pixel_clock;
3185 m_n->link_n = link_clock;
2c07245f
ZW		 3186 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3187}
3188
a7615030
CW		 3189static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3190{
72bbe58c
KP		 3191 if (i915_panel_use_ssc >= 0)
3192 return i915_panel_use_ssc != 0;
3193 return dev_priv->lvds_use_ssc
435793df 3194 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3195}
3196
5a354204
JB		 3197/**
3198 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3199 * @crtc: CRTC structure
3b5c78a3 3200 * @mode: requested mode
5a354204
JB		 3201 *
3202 * A pipe may be connected to one or more outputs. Based on the depth of the
3203 * attached framebuffer, choose a good color depth to use on the pipe.
3204 *
3205 * If possible, match the pipe depth to the fb depth. In some cases, this
3206 * isn't ideal, because the connected output supports a lesser or restricted
3207 * set of depths. Resolve that here:
3208 * LVDS typically supports only 6bpc, so clamp down in that case
3209 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3210 * Displays may support a restricted set as well, check EDID and clamp as
3211 * appropriate.
3b5c78a3 3212 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3213 *
3214 * RETURNS:
3215 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3216 * true if they don't match).
3217 */
3218static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3219 unsigned int *pipe_bpp,
3220 struct drm_display_mode *mode)
5a354204
JB		 3221{
3222 struct drm_device *dev = crtc->dev;
3223 struct drm_i915_private *dev_priv = dev->dev_private;
3224 struct drm_encoder *encoder;
3225 struct drm_connector *connector;
3226 unsigned int display_bpc = UINT_MAX, bpc;
3227
3228 /* Walk the encoders & connectors on this crtc, get min bpc */
3229 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3230 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3231
3232 if (encoder->crtc != crtc)
3233 continue;
3234
3235 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3236 unsigned int lvds_bpc;
3237
3238 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3239 LVDS_A3_POWER_UP)
3240 lvds_bpc = 8;
3241 else
3242 lvds_bpc = 6;
3243
3244 if (lvds_bpc < display_bpc) {
82820490 3245 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3246 display_bpc = lvds_bpc;
3247 }
3248 continue;
3249 }
3250
3251 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3252 /* Use VBT settings if we have an eDP panel */
3253 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3254
3255 if (edp_bpc < display_bpc) {
82820490 3256 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3257 display_bpc = edp_bpc;
3258 }
3259 continue;
3260 }
3261
3262 /* Not one of the known troublemakers, check the EDID */
3263 list_for_each_entry(connector, &dev->mode_config.connector_list,
3264 head) {
3265 if (connector->encoder != encoder)
3266 continue;
3267
62ac41a6
JB		 3268 /* Don't use an invalid EDID bpc value */
3269 if (connector->display_info.bpc &&
3270 connector->display_info.bpc < display_bpc) {
82820490 3271 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3272 display_bpc = connector->display_info.bpc;
3273 }
3274 }
3275
3276 /*
3277 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3278 * through, clamp it down. (Note: >12bpc will be caught below.)
3279 */
3280 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3281 if (display_bpc > 8 && display_bpc < 12) {
82820490 3282 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3283 display_bpc = 12;
3284 } else {
82820490 3285 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3286 display_bpc = 8;
3287 }
3288 }
3289 }
3290
3b5c78a3
AJ		 3291 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3292 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3293 display_bpc = 6;
3294 }
3295
5a354204
JB		 3296 /*
3297 * We could just drive the pipe at the highest bpc all the time and
3298 * enable dithering as needed, but that costs bandwidth. So choose
3299 * the minimum value that expresses the full color range of the fb but
3300 * also stays within the max display bpc discovered above.
3301 */
3302
3303 switch (crtc->fb->depth) {
3304 case 8:
3305 bpc = 8; /* since we go through a colormap */
3306 break;
3307 case 15:
3308 case 16:
3309 bpc = 6; /* min is 18bpp */
3310 break;
3311 case 24:
578393cd 3312 bpc = 8;
5a354204
JB		 3313 break;
3314 case 30:
578393cd 3315 bpc = 10;
5a354204
JB		 3316 break;
3317 case 48:
578393cd 3318 bpc = 12;
5a354204
JB		 3319 break;
3320 default:
3321 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3322 bpc = min((unsigned int)8, display_bpc);
3323 break;
3324 }
3325
578393cd
KP		 3326 display_bpc = min(display_bpc, bpc);
3327
82820490
AJ		 3328 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3329 bpc, display_bpc);
5a354204 3330
578393cd 3331 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3332
3333 return display_bpc != bpc;
3334}
3335
c65d77d8
JB		 3336static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3337{
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 int refclk;
3341
3342 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3343 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3344 refclk = dev_priv->lvds_ssc_freq * 1000;
3345 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3346 refclk / 1000);
3347 } else if (!IS_GEN2(dev)) {
3348 refclk = 96000;
3349 } else {
3350 refclk = 48000;
3351 }
3352
3353 return refclk;
3354}
3355
3356static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3357 intel_clock_t *clock)
3358{
3359 /* SDVO TV has fixed PLL values depend on its clock range,
3360 this mirrors vbios setting. */
3361 if (adjusted_mode->clock >= 100000
3362 && adjusted_mode->clock < 140500) {
3363 clock->p1 = 2;
3364 clock->p2 = 10;
3365 clock->n = 3;
3366 clock->m1 = 16;
3367 clock->m2 = 8;
3368 } else if (adjusted_mode->clock >= 140500
3369 && adjusted_mode->clock <= 200000) {
3370 clock->p1 = 1;
3371 clock->p2 = 10;
3372 clock->n = 6;
3373 clock->m1 = 12;
3374 clock->m2 = 8;
3375 }
3376}
3377
a7516a05
JB		 3378static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3379 intel_clock_t *clock,
3380 intel_clock_t *reduced_clock)
3381{
3382 struct drm_device *dev = crtc->dev;
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385 int pipe = intel_crtc->pipe;
3386 u32 fp, fp2 = 0;
3387
3388 if (IS_PINEVIEW(dev)) {
3389 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3390 if (reduced_clock)
3391 fp2 = (1 << reduced_clock->n) << 16 |
3392 reduced_clock->m1 << 8 | reduced_clock->m2;
3393 } else {
3394 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3395 if (reduced_clock)
3396 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3397 reduced_clock->m2;
3398 }
3399
3400 I915_WRITE(FP0(pipe), fp);
3401
3402 intel_crtc->lowfreq_avail = false;
3403 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3404 reduced_clock && i915_powersave) {
3405 I915_WRITE(FP1(pipe), fp2);
3406 intel_crtc->lowfreq_avail = true;
3407 } else {
3408 I915_WRITE(FP1(pipe), fp);
3409 }
3410}
3411
93e537a1
DV		 3412static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3413 struct drm_display_mode *adjusted_mode)
3414{
3415 struct drm_device *dev = crtc->dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3418 int pipe = intel_crtc->pipe;
3419 u32 temp, lvds_sync = 0;
3420
3421 temp = I915_READ(LVDS);
3422 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3423 if (pipe == 1) {
3424 temp |= LVDS_PIPEB_SELECT;
3425 } else {
3426 temp &= ~LVDS_PIPEB_SELECT;
3427 }
3428 /* set the corresponsding LVDS_BORDER bit */
3429 temp |= dev_priv->lvds_border_bits;
3430 /* Set the B0-B3 data pairs corresponding to whether we're going to
3431 * set the DPLLs for dual-channel mode or not.
3432 */
3433 if (clock->p2 == 7)
3434 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3435 else
3436 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3437
3438 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3439 * appropriately here, but we need to look more thoroughly into how
3440 * panels behave in the two modes.
3441 */
3442 /* set the dithering flag on LVDS as needed */
3443 if (INTEL_INFO(dev)->gen >= 4) {
3444 if (dev_priv->lvds_dither)
3445 temp |= LVDS_ENABLE_DITHER;
3446 else
3447 temp &= ~LVDS_ENABLE_DITHER;
3448 }
3449 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3450 lvds_sync |= LVDS_HSYNC_POLARITY;
3451 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3452 lvds_sync |= LVDS_VSYNC_POLARITY;
3453 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
3454 != lvds_sync) {
3455 char flags[2] = "-+";
3456 DRM_INFO("Changing LVDS panel from "
3457 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
3458 flags[!(temp & LVDS_HSYNC_POLARITY)],
3459 flags[!(temp & LVDS_VSYNC_POLARITY)],
3460 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
3461 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
3462 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3463 temp |= lvds_sync;
3464 }
3465 I915_WRITE(LVDS, temp);
3466}
3467
eb1cbe48
DV		 3468static void i9xx_update_pll(struct drm_crtc *crtc,
3469 struct drm_display_mode *mode,
3470 struct drm_display_mode *adjusted_mode,
3471 intel_clock_t *clock, intel_clock_t *reduced_clock,
3472 int num_connectors)
3473{
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477 int pipe = intel_crtc->pipe;
3478 u32 dpll;
3479 bool is_sdvo;
3480
3481 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3482 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3483
3484 dpll = DPLL_VGA_MODE_DIS;
3485
3486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3487 dpll |= DPLLB_MODE_LVDS;
3488 else
3489 dpll |= DPLLB_MODE_DAC_SERIAL;
3490 if (is_sdvo) {
3491 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3492 if (pixel_multiplier > 1) {
3493 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3494 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3495 }
3496 dpll |= DPLL_DVO_HIGH_SPEED;
3497 }
3498 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3499 dpll |= DPLL_DVO_HIGH_SPEED;
3500
3501 /* compute bitmask from p1 value */
3502 if (IS_PINEVIEW(dev))
3503 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3504 else {
3505 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3506 if (IS_G4X(dev) && reduced_clock)
3507 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3508 }
3509 switch (clock->p2) {
3510 case 5:
3511 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3512 break;
3513 case 7:
3514 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3515 break;
3516 case 10:
3517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3518 break;
3519 case 14:
3520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3521 break;
3522 }
3523 if (INTEL_INFO(dev)->gen >= 4)
3524 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3525
3526 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3527 dpll |= PLL_REF_INPUT_TVCLKINBC;
3528 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3529 /* XXX: just matching BIOS for now */
3530 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3531 dpll |= 3;
3532 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3533 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3534 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3535 else
3536 dpll |= PLL_REF_INPUT_DREFCLK;
3537
3538 dpll |= DPLL_VCO_ENABLE;
3539 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3540 POSTING_READ(DPLL(pipe));
3541 udelay(150);
3542
3543 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3544 * This is an exception to the general rule that mode_set doesn't turn
3545 * things on.
3546 */
3547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3548 intel_update_lvds(crtc, clock, adjusted_mode);
3549
3550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3551 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3552
3553 I915_WRITE(DPLL(pipe), dpll);
3554
3555 /* Wait for the clocks to stabilize. */
3556 POSTING_READ(DPLL(pipe));
3557 udelay(150);
3558
3559 if (INTEL_INFO(dev)->gen >= 4) {
3560 u32 temp = 0;
3561 if (is_sdvo) {
3562 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3563 if (temp > 1)
3564 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3565 else
3566 temp = 0;
3567 }
3568 I915_WRITE(DPLL_MD(pipe), temp);
3569 } else {
3570 /* The pixel multiplier can only be updated once the
3571 * DPLL is enabled and the clocks are stable.
3572 *
3573 * So write it again.
3574 */
3575 I915_WRITE(DPLL(pipe), dpll);
3576 }
3577}
3578
3579static void i8xx_update_pll(struct drm_crtc *crtc,
3580 struct drm_display_mode *adjusted_mode,
3581 intel_clock_t *clock,
3582 int num_connectors)
3583{
3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3587 int pipe = intel_crtc->pipe;
3588 u32 dpll;
3589
3590 dpll = DPLL_VGA_MODE_DIS;
3591
3592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3593 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3594 } else {
3595 if (clock->p1 == 2)
3596 dpll |= PLL_P1_DIVIDE_BY_TWO;
3597 else
3598 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3599 if (clock->p2 == 4)
3600 dpll |= PLL_P2_DIVIDE_BY_4;
3601 }
3602
3603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3604 /* XXX: just matching BIOS for now */
3605 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3606 dpll |= 3;
3607 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3608 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3609 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3610 else
3611 dpll |= PLL_REF_INPUT_DREFCLK;
3612
3613 dpll |= DPLL_VCO_ENABLE;
3614 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3615 POSTING_READ(DPLL(pipe));
3616 udelay(150);
3617
3618 I915_WRITE(DPLL(pipe), dpll);
3619
3620 /* Wait for the clocks to stabilize. */
3621 POSTING_READ(DPLL(pipe));
3622 udelay(150);
3623
3624 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3625 * This is an exception to the general rule that mode_set doesn't turn
3626 * things on.
3627 */
3628 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3629 intel_update_lvds(crtc, clock, adjusted_mode);
3630
3631 /* The pixel multiplier can only be updated once the
3632 * DPLL is enabled and the clocks are stable.
3633 *
3634 * So write it again.
3635 */
3636 I915_WRITE(DPLL(pipe), dpll);
3637}
3638
f564048e
EA		 3639static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3640 struct drm_display_mode *mode,
3641 struct drm_display_mode *adjusted_mode,
3642 int x, int y,
3643 struct drm_framebuffer *old_fb)
79e53945
JB		 3644{
3645 struct drm_device *dev = crtc->dev;
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648 int pipe = intel_crtc->pipe;
80824003 3649 int plane = intel_crtc->plane;
c751ce4f 3650 int refclk, num_connectors = 0;
652c393a 3651 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3652 u32 dspcntr, pipeconf, vsyncshift;
3653 bool ok, has_reduced_clock = false, is_sdvo = false;
3654 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3655 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3656 struct intel_encoder *encoder;
d4906093 3657 const intel_limit_t *limit;
5c3b82e2 3658 int ret;
79e53945 3659
5eddb70b
CW		 3660 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3661 if (encoder->base.crtc != crtc)
79e53945
JB		 3662 continue;
3663
5eddb70b 3664 switch (encoder->type) {
79e53945
JB		 3665 case INTEL_OUTPUT_LVDS:
3666 is_lvds = true;
3667 break;
3668 case INTEL_OUTPUT_SDVO:
7d57382e 3669 case INTEL_OUTPUT_HDMI:
79e53945 3670 is_sdvo = true;
5eddb70b 3671 if (encoder->needs_tv_clock)
e2f0ba97 3672 is_tv = true;
79e53945 3673 break;
79e53945
JB		 3674 case INTEL_OUTPUT_TVOUT:
3675 is_tv = true;
3676 break;
a4fc5ed6
KP		 3677 case INTEL_OUTPUT_DISPLAYPORT:
3678 is_dp = true;
3679 break;
79e53945 3680 }
43565a06 3681
c751ce4f 3682 num_connectors++;
79e53945
JB		 3683 }
3684
c65d77d8 3685 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3686
d4906093
ML		 3687 /*
3688 * Returns a set of divisors for the desired target clock with the given
3689 * refclk, or FALSE. The returned values represent the clock equation:
3690 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3691 */
1b894b59 3692 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3693 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3694 &clock);
79e53945
JB		 3695 if (!ok) {
3696 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3697 return -EINVAL;
79e53945
JB		 3698 }
3699
cda4b7d3 3700 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3701 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3702
ddc9003c 3703 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 3704 /*
3705 * Ensure we match the reduced clock's P to the target clock.
3706 * If the clocks don't match, we can't switch the display clock
3707 * by using the FP0/FP1. In such case we will disable the LVDS
3708 * downclock feature.
3709 */
ddc9003c 3710 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 3711 dev_priv->lvds_downclock,
3712 refclk,
cec2f356 3713 &clock,
5eddb70b 3714 &reduced_clock);
7026d4ac
ZW		 3715 }
3716
c65d77d8
JB		 3717 if (is_sdvo && is_tv)
3718 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 3719
a7516a05
JB		 3720 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3721 &reduced_clock : NULL);
79e53945 3722
eb1cbe48
DV		 3723 if (IS_GEN2(dev))
3724 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 3725 else
eb1cbe48
DV		 3726 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3727 has_reduced_clock ? &reduced_clock : NULL,
3728 num_connectors);
79e53945
JB		 3729
3730 /* setup pipeconf */
5eddb70b 3731 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 3732
3733 /* Set up the display plane register */
3734 dspcntr = DISPPLANE_GAMMA_ENABLE;
3735
929c77fb
EA		 3736 if (pipe == 0)
3737 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3738 else
3739 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 3740
a6c45cf0 3741 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 3742 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3743 * core speed.
3744 *
3745 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3746 * pipe == 0 check?
3747 */
e70236a8
JB		 3748 if (mode->clock >
3749 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 3750 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 3751 else
5eddb70b 3752 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 3753 }
3754
3b5c78a3
AJ		 3755 /* default to 8bpc */
3756 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3757 if (is_dp) {
3758 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3759 pipeconf |= PIPECONF_BPP_6 |
3760 PIPECONF_DITHER_EN |
3761 PIPECONF_DITHER_TYPE_SP;
3762 }
3763 }
3764
28c97730 3765 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 3766 drm_mode_debug_printmodeline(mode);
3767
a7516a05
JB		 3768 if (HAS_PIPE_CXSR(dev)) {
3769 if (intel_crtc->lowfreq_avail) {
28c97730 3770 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 3771 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 3772 } else {
28c97730 3773 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 3774 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3775 }
3776 }
3777
617cf884 3778 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 3779 if (!IS_GEN2(dev) &&
3780 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 3781 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3782 /* the chip adds 2 halflines automatically */
734b4157 3783 adjusted_mode->crtc_vtotal -= 1;
734b4157 3784 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 3785 vsyncshift = adjusted_mode->crtc_hsync_start
3786 - adjusted_mode->crtc_htotal/2;
3787 } else {
617cf884 3788 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 3789 vsyncshift = 0;
3790 }
3791
3792 if (!IS_GEN3(dev))
3793 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 3794
5eddb70b
CW		 3795 I915_WRITE(HTOTAL(pipe),
3796 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 3797 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 3798 I915_WRITE(HBLANK(pipe),
3799 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 3800 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 3801 I915_WRITE(HSYNC(pipe),
3802 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 3803 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 3804
3805 I915_WRITE(VTOTAL(pipe),
3806 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 3807 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 3808 I915_WRITE(VBLANK(pipe),
3809 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 3810 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 3811 I915_WRITE(VSYNC(pipe),
3812 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 3813 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 3814
3815 /* pipesrc and dspsize control the size that is scaled from,
3816 * which should always be the user's requested size.
79e53945 3817 */
929c77fb
EA		 3818 I915_WRITE(DSPSIZE(plane),
3819 ((mode->vdisplay - 1) << 16) |
3820 (mode->hdisplay - 1));
3821 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 3822 I915_WRITE(PIPESRC(pipe),
3823 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 3824
f564048e
EA		 3825 I915_WRITE(PIPECONF(pipe), pipeconf);
3826 POSTING_READ(PIPECONF(pipe));
929c77fb 3827 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 3828
3829 intel_wait_for_vblank(dev, pipe);
3830
f564048e
EA		 3831 I915_WRITE(DSPCNTR(plane), dspcntr);
3832 POSTING_READ(DSPCNTR(plane));
284d9529 3833 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 3834
3835 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3836
3837 intel_update_watermarks(dev);
3838
f564048e
EA		 3839 return ret;
3840}
3841
9fb526db
KP		 3842/*
3843 * Initialize reference clocks when the driver loads
3844 */
3845void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 3846{
3847 struct drm_i915_private *dev_priv = dev->dev_private;
3848 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 3849 struct intel_encoder *encoder;
13d83a67
JB		 3850 u32 temp;
3851 bool has_lvds = false;
199e5d79
KP		 3852 bool has_cpu_edp = false;
3853 bool has_pch_edp = false;
3854 bool has_panel = false;
99eb6a01
KP		 3855 bool has_ck505 = false;
3856 bool can_ssc = false;
13d83a67
JB		 3857
3858 /* We need to take the global config into account */
199e5d79
KP		 3859 list_for_each_entry(encoder, &mode_config->encoder_list,
3860 base.head) {
3861 switch (encoder->type) {
3862 case INTEL_OUTPUT_LVDS:
3863 has_panel = true;
3864 has_lvds = true;
3865 break;
3866 case INTEL_OUTPUT_EDP:
3867 has_panel = true;
3868 if (intel_encoder_is_pch_edp(&encoder->base))
3869 has_pch_edp = true;
3870 else
3871 has_cpu_edp = true;
3872 break;
13d83a67
JB		 3873 }
3874 }
3875
99eb6a01
KP		 3876 if (HAS_PCH_IBX(dev)) {
3877 has_ck505 = dev_priv->display_clock_mode;
3878 can_ssc = has_ck505;
3879 } else {
3880 has_ck505 = false;
3881 can_ssc = true;
3882 }
3883
3884 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3885 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3886 has_ck505);
13d83a67
JB		 3887
3888 /* Ironlake: try to setup display ref clock before DPLL
3889 * enabling. This is only under driver's control after
3890 * PCH B stepping, previous chipset stepping should be
3891 * ignoring this setting.
3892 */
3893 temp = I915_READ(PCH_DREF_CONTROL);
3894 /* Always enable nonspread source */
3895 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 3896
99eb6a01
KP		 3897 if (has_ck505)
3898 temp |= DREF_NONSPREAD_CK505_ENABLE;
3899 else
3900 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 3901
199e5d79
KP		 3902 if (has_panel) {
3903 temp &= ~DREF_SSC_SOURCE_MASK;
3904 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 3905
199e5d79 3906 /* SSC must be turned on before enabling the CPU output */
99eb6a01 3907 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 3908 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 3909 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 3910 } else
3911 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 3912
3913 /* Get SSC going before enabling the outputs */
3914 I915_WRITE(PCH_DREF_CONTROL, temp);
3915 POSTING_READ(PCH_DREF_CONTROL);
3916 udelay(200);
3917
13d83a67
JB		 3918 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3919
3920 /* Enable CPU source on CPU attached eDP */
199e5d79 3921 if (has_cpu_edp) {
99eb6a01 3922 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 3923 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 3924 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 3925 }
13d83a67
JB		 3926 else
3927 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 3928 } else
3929 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3930
3931 I915_WRITE(PCH_DREF_CONTROL, temp);
3932 POSTING_READ(PCH_DREF_CONTROL);
3933 udelay(200);
3934 } else {
3935 DRM_DEBUG_KMS("Disabling SSC entirely\n");
3936
3937 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3938
3939 /* Turn off CPU output */
3940 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3941
3942 I915_WRITE(PCH_DREF_CONTROL, temp);
3943 POSTING_READ(PCH_DREF_CONTROL);
3944 udelay(200);
3945
3946 /* Turn off the SSC source */
3947 temp &= ~DREF_SSC_SOURCE_MASK;
3948 temp |= DREF_SSC_SOURCE_DISABLE;
3949
3950 /* Turn off SSC1 */
3951 temp &= ~ DREF_SSC1_ENABLE;
3952
13d83a67
JB		 3953 I915_WRITE(PCH_DREF_CONTROL, temp);
3954 POSTING_READ(PCH_DREF_CONTROL);
3955 udelay(200);
3956 }
3957}
3958
d9d444cb
JB		 3959static int ironlake_get_refclk(struct drm_crtc *crtc)
3960{
3961 struct drm_device *dev = crtc->dev;
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 struct intel_encoder *encoder;
3964 struct drm_mode_config *mode_config = &dev->mode_config;
3965 struct intel_encoder *edp_encoder = NULL;
3966 int num_connectors = 0;
3967 bool is_lvds = false;
3968
3969 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3970 if (encoder->base.crtc != crtc)
3971 continue;
3972
3973 switch (encoder->type) {
3974 case INTEL_OUTPUT_LVDS:
3975 is_lvds = true;
3976 break;
3977 case INTEL_OUTPUT_EDP:
3978 edp_encoder = encoder;
3979 break;
3980 }
3981 num_connectors++;
3982 }
3983
3984 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3985 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3986 dev_priv->lvds_ssc_freq);
3987 return dev_priv->lvds_ssc_freq * 1000;
3988 }
3989
3990 return 120000;
3991}
3992
f564048e
EA		 3993static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
3994 struct drm_display_mode *mode,
3995 struct drm_display_mode *adjusted_mode,
3996 int x, int y,
3997 struct drm_framebuffer *old_fb)
79e53945
JB		 3998{
3999 struct drm_device *dev = crtc->dev;
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4002 int pipe = intel_crtc->pipe;
80824003 4003 int plane = intel_crtc->plane;
c751ce4f 4004 int refclk, num_connectors = 0;
652c393a 4005 intel_clock_t clock, reduced_clock;
5eddb70b 4006 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4007 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4008 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4009 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4010 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4011 const intel_limit_t *limit;
5c3b82e2 4012 int ret;
2c07245f 4013 struct fdi_m_n m_n = {0};
fae14981 4014 u32 temp;
aa9b500d 4015 u32 lvds_sync = 0;
5a354204
JB		 4016 int target_clock, pixel_multiplier, lane, link_bw, factor;
4017 unsigned int pipe_bpp;
4018 bool dither;
e3aef172 4019 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4020
5eddb70b
CW		 4021 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4022 if (encoder->base.crtc != crtc)
79e53945
JB		 4023 continue;
4024
5eddb70b 4025 switch (encoder->type) {
79e53945
JB		 4026 case INTEL_OUTPUT_LVDS:
4027 is_lvds = true;
4028 break;
4029 case INTEL_OUTPUT_SDVO:
7d57382e 4030 case INTEL_OUTPUT_HDMI:
79e53945 4031 is_sdvo = true;
5eddb70b 4032 if (encoder->needs_tv_clock)
e2f0ba97 4033 is_tv = true;
79e53945 4034 break;
79e53945
JB		 4035 case INTEL_OUTPUT_TVOUT:
4036 is_tv = true;
4037 break;
4038 case INTEL_OUTPUT_ANALOG:
4039 is_crt = true;
4040 break;
a4fc5ed6
KP		 4041 case INTEL_OUTPUT_DISPLAYPORT:
4042 is_dp = true;
4043 break;
32f9d658 4044 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4045 is_dp = true;
4046 if (intel_encoder_is_pch_edp(&encoder->base))
4047 is_pch_edp = true;
4048 else
4049 is_cpu_edp = true;
4050 edp_encoder = encoder;
32f9d658 4051 break;
79e53945 4052 }
43565a06 4053
c751ce4f 4054 num_connectors++;
79e53945
JB		 4055 }
4056
d9d444cb 4057 refclk = ironlake_get_refclk(crtc);
79e53945 4058
d4906093
ML		 4059 /*
4060 * Returns a set of divisors for the desired target clock with the given
4061 * refclk, or FALSE. The returned values represent the clock equation:
4062 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4063 */
1b894b59 4064 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4065 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4066 &clock);
79e53945
JB		 4067 if (!ok) {
4068 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4069 return -EINVAL;
79e53945
JB		 4070 }
4071
cda4b7d3 4072 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4073 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4074
ddc9003c 4075 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4076 /*
4077 * Ensure we match the reduced clock's P to the target clock.
4078 * If the clocks don't match, we can't switch the display clock
4079 * by using the FP0/FP1. In such case we will disable the LVDS
4080 * downclock feature.
4081 */
ddc9003c 4082 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4083 dev_priv->lvds_downclock,
4084 refclk,
cec2f356 4085 &clock,
5eddb70b 4086 &reduced_clock);
652c393a 4087 }
7026d4ac
ZW		 4088 /* SDVO TV has fixed PLL values depend on its clock range,
4089 this mirrors vbios setting. */
4090 if (is_sdvo && is_tv) {
4091 if (adjusted_mode->clock >= 100000
5eddb70b 4092 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4093 clock.p1 = 2;
4094 clock.p2 = 10;
4095 clock.n = 3;
4096 clock.m1 = 16;
4097 clock.m2 = 8;
4098 } else if (adjusted_mode->clock >= 140500
5eddb70b 4099 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4100 clock.p1 = 1;
4101 clock.p2 = 10;
4102 clock.n = 6;
4103 clock.m1 = 12;
4104 clock.m2 = 8;
4105 }
4106 }
4107
2c07245f 4108 /* FDI link */
8febb297
EA		 4109 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4110 lane = 0;
4111 /* CPU eDP doesn't require FDI link, so just set DP M/N
4112 according to current link config */
e3aef172 4113 if (is_cpu_edp) {
8febb297 4114 target_clock = mode->clock;
e3aef172 4115 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4116 } else {
4117 /* [e]DP over FDI requires target mode clock
4118 instead of link clock */
e3aef172 4119 if (is_dp)
5eb08b69 4120 target_clock = mode->clock;
8febb297
EA		 4121 else
4122 target_clock = adjusted_mode->clock;
4123
4124 /* FDI is a binary signal running at ~2.7GHz, encoding
4125 * each output octet as 10 bits. The actual frequency
4126 * is stored as a divider into a 100MHz clock, and the
4127 * mode pixel clock is stored in units of 1KHz.
4128 * Hence the bw of each lane in terms of the mode signal
4129 * is:
4130 */
4131 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4132 }
58a27471 4133
8febb297
EA		 4134 /* determine panel color depth */
4135 temp = I915_READ(PIPECONF(pipe));
4136 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4137 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4138 switch (pipe_bpp) {
4139 case 18:
4140 temp |= PIPE_6BPC;
8febb297 4141 break;
5a354204
JB		 4142 case 24:
4143 temp |= PIPE_8BPC;
8febb297 4144 break;
5a354204
JB		 4145 case 30:
4146 temp |= PIPE_10BPC;
8febb297 4147 break;
5a354204
JB		 4148 case 36:
4149 temp |= PIPE_12BPC;
8febb297
EA		 4150 break;
4151 default:
62ac41a6
JB		 4152 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4153 pipe_bpp);
5a354204
JB		 4154 temp |= PIPE_8BPC;
4155 pipe_bpp = 24;
4156 break;
8febb297 4157 }
77ffb597 4158
5a354204
JB		 4159 intel_crtc->bpp = pipe_bpp;
4160 I915_WRITE(PIPECONF(pipe), temp);
4161
8febb297
EA		 4162 if (!lane) {
4163 /*
4164 * Account for spread spectrum to avoid
4165 * oversubscribing the link. Max center spread
4166 * is 2.5%; use 5% for safety's sake.
4167 */
5a354204 4168 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4169 lane = bps / (link_bw * 8) + 1;
5eb08b69 4170 }
2c07245f 4171
8febb297
EA		 4172 intel_crtc->fdi_lanes = lane;
4173
4174 if (pixel_multiplier > 1)
4175 link_bw *= pixel_multiplier;
5a354204
JB		 4176 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4177 &m_n);
8febb297 4178
a07d6787
EA		 4179 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4180 if (has_reduced_clock)
4181 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4182 reduced_clock.m2;
79e53945 4183
c1858123 4184 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4185 factor = 21;
4186 if (is_lvds) {
4187 if ((intel_panel_use_ssc(dev_priv) &&
4188 dev_priv->lvds_ssc_freq == 100) ||
4189 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4190 factor = 25;
4191 } else if (is_sdvo && is_tv)
4192 factor = 20;
c1858123 4193
cb0e0931 4194 if (clock.m < factor * clock.n)
8febb297 4195 fp |= FP_CB_TUNE;
2c07245f 4196
5eddb70b 4197 dpll = 0;
2c07245f 4198
a07d6787
EA		 4199 if (is_lvds)
4200 dpll |= DPLLB_MODE_LVDS;
4201 else
4202 dpll |= DPLLB_MODE_DAC_SERIAL;
4203 if (is_sdvo) {
4204 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4205 if (pixel_multiplier > 1) {
4206 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4207 }
a07d6787
EA		 4208 dpll |= DPLL_DVO_HIGH_SPEED;
4209 }
e3aef172 4210 if (is_dp && !is_cpu_edp)
a07d6787 4211 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4212
a07d6787
EA		 4213 /* compute bitmask from p1 value */
4214 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4215 /* also FPA1 */
4216 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4217
4218 switch (clock.p2) {
4219 case 5:
4220 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4221 break;
4222 case 7:
4223 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4224 break;
4225 case 10:
4226 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4227 break;
4228 case 14:
4229 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4230 break;
79e53945
JB		 4231 }
4232
43565a06
KH		 4233 if (is_sdvo && is_tv)
4234 dpll |= PLL_REF_INPUT_TVCLKINBC;
4235 else if (is_tv)
79e53945 4236 /* XXX: just matching BIOS for now */
43565a06 4237 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4238 dpll |= 3;
a7615030 4239 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4240 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4241 else
4242 dpll |= PLL_REF_INPUT_DREFCLK;
4243
4244 /* setup pipeconf */
5eddb70b 4245 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4246
4247 /* Set up the display plane register */
4248 dspcntr = DISPPLANE_GAMMA_ENABLE;
4249
f7cb34d4 4250 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4251 drm_mode_debug_printmodeline(mode);
4252
5c5313c8 4253 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14 4254 if (!intel_crtc->no_pll) {
e3aef172 4255 if (!is_cpu_edp) {
4b645f14
JB		 4256 I915_WRITE(PCH_FP0(pipe), fp);
4257 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4258
4259 POSTING_READ(PCH_DPLL(pipe));
4260 udelay(150);
4261 }
4262 } else {
4263 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
4264 fp == I915_READ(PCH_FP0(0))) {
4265 intel_crtc->use_pll_a = true;
4266 DRM_DEBUG_KMS("using pipe a dpll\n");
4267 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
4268 fp == I915_READ(PCH_FP0(1))) {
4269 intel_crtc->use_pll_a = false;
4270 DRM_DEBUG_KMS("using pipe b dpll\n");
4271 } else {
4272 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
4273 return -EINVAL;
4274 }
79e53945
JB		 4275 }
4276
4277 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4278 * This is an exception to the general rule that mode_set doesn't turn
4279 * things on.
4280 */
4281 if (is_lvds) {
fae14981 4282 temp = I915_READ(PCH_LVDS);
5eddb70b 4283 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4284 if (HAS_PCH_CPT(dev)) {
4285 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4286 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4287 } else {
4288 if (pipe == 1)
4289 temp |= LVDS_PIPEB_SELECT;
4290 else
4291 temp &= ~LVDS_PIPEB_SELECT;
4292 }
4b645f14 4293
a3e17eb8 4294 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4295 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4296 /* Set the B0-B3 data pairs corresponding to whether we're going to
4297 * set the DPLLs for dual-channel mode or not.
4298 */
4299 if (clock.p2 == 7)
5eddb70b 4300 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4301 else
5eddb70b 4302 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4303
4304 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4305 * appropriately here, but we need to look more thoroughly into how
4306 * panels behave in the two modes.
4307 */
aa9b500d
BF		 4308 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4309 lvds_sync |= LVDS_HSYNC_POLARITY;
4310 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4311 lvds_sync |= LVDS_VSYNC_POLARITY;
4312 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4313 != lvds_sync) {
4314 char flags[2] = "-+";
4315 DRM_INFO("Changing LVDS panel from "
4316 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4317 flags[!(temp & LVDS_HSYNC_POLARITY)],
4318 flags[!(temp & LVDS_VSYNC_POLARITY)],
4319 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4320 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4321 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4322 temp |= lvds_sync;
4323 }
fae14981 4324 I915_WRITE(PCH_LVDS, temp);
79e53945 4325 }
434ed097 4326
8febb297
EA		 4327 pipeconf &= ~PIPECONF_DITHER_EN;
4328 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4329 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4330 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4331 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4332 }
e3aef172 4333 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4334 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4335 } else {
8db9d77b 4336 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4337 I915_WRITE(TRANSDATA_M1(pipe), 0);
4338 I915_WRITE(TRANSDATA_N1(pipe), 0);
4339 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4340 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4341 }
79e53945 4342
e3aef172 4343 if (!intel_crtc->no_pll && (!edp_encoder || is_pch_edp)) {
fae14981 4344 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 4345
32f9d658 4346 /* Wait for the clocks to stabilize. */
fae14981 4347 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 4348 udelay(150);
4349
8febb297
EA		 4350 /* The pixel multiplier can only be updated once the
4351 * DPLL is enabled and the clocks are stable.
4352 *
4353 * So write it again.
4354 */
fae14981 4355 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 4356 }
79e53945 4357
5eddb70b 4358 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 4359 if (!intel_crtc->no_pll) {
4360 if (is_lvds && has_reduced_clock && i915_powersave) {
4361 I915_WRITE(PCH_FP1(pipe), fp2);
4362 intel_crtc->lowfreq_avail = true;
4363 if (HAS_PIPE_CXSR(dev)) {
4364 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4365 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4366 }
4367 } else {
4368 I915_WRITE(PCH_FP1(pipe), fp);
4369 if (HAS_PIPE_CXSR(dev)) {
4370 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4371 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4372 }
652c393a
JB		 4373 }
4374 }
4375
617cf884 4376 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4377 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4378 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4379 /* the chip adds 2 halflines automatically */
734b4157 4380 adjusted_mode->crtc_vtotal -= 1;
734b4157 4381 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4382 I915_WRITE(VSYNCSHIFT(pipe),
4383 adjusted_mode->crtc_hsync_start
4384 - adjusted_mode->crtc_htotal/2);
4385 } else {
617cf884 4386 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4387 I915_WRITE(VSYNCSHIFT(pipe), 0);
4388 }
734b4157 4389
5eddb70b
CW		 4390 I915_WRITE(HTOTAL(pipe),
4391 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4392 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4393 I915_WRITE(HBLANK(pipe),
4394 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4395 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4396 I915_WRITE(HSYNC(pipe),
4397 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4398 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4399
4400 I915_WRITE(VTOTAL(pipe),
4401 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4402 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4403 I915_WRITE(VBLANK(pipe),
4404 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4405 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4406 I915_WRITE(VSYNC(pipe),
4407 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4408 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4409
8febb297
EA		 4410 /* pipesrc controls the size that is scaled from, which should
4411 * always be the user's requested size.
79e53945 4412 */
5eddb70b
CW		 4413 I915_WRITE(PIPESRC(pipe),
4414 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4415
8febb297
EA		 4416 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4417 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4418 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4419 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4420
e3aef172 4421 if (is_cpu_edp)
8febb297 4422 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4423
5eddb70b
CW		 4424 I915_WRITE(PIPECONF(pipe), pipeconf);
4425 POSTING_READ(PIPECONF(pipe));
79e53945 4426
9d0498a2 4427 intel_wait_for_vblank(dev, pipe);
79e53945 4428
5eddb70b 4429 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4430 POSTING_READ(DSPCNTR(plane));
79e53945 4431
5c3b82e2 4432 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4433
4434 intel_update_watermarks(dev);
4435
1f803ee5 4436 return ret;
79e53945
JB		 4437}
4438
f564048e
EA		 4439static int intel_crtc_mode_set(struct drm_crtc *crtc,
4440 struct drm_display_mode *mode,
4441 struct drm_display_mode *adjusted_mode,
4442 int x, int y,
4443 struct drm_framebuffer *old_fb)
4444{
4445 struct drm_device *dev = crtc->dev;
4446 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4448 int pipe = intel_crtc->pipe;
f564048e
EA		 4449 int ret;
4450
0b701d27 4451 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4452
f564048e
EA		 4453 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4454 x, y, old_fb);
79e53945 4455 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4456
d8e70a25
JB		 4457 if (ret)
4458 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4459 else
4460 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4461
1f803ee5 4462 return ret;
79e53945
JB		 4463}
4464
3a9627f4
WF		 4465static bool intel_eld_uptodate(struct drm_connector *connector,
4466 int reg_eldv, uint32_t bits_eldv,
4467 int reg_elda, uint32_t bits_elda,
4468 int reg_edid)
4469{
4470 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4471 uint8_t *eld = connector->eld;
4472 uint32_t i;
4473
4474 i = I915_READ(reg_eldv);
4475 i &= bits_eldv;
4476
4477 if (!eld[0])
4478 return !i;
4479
4480 if (!i)
4481 return false;
4482
4483 i = I915_READ(reg_elda);
4484 i &= ~bits_elda;
4485 I915_WRITE(reg_elda, i);
4486
4487 for (i = 0; i < eld[2]; i++)
4488 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4489 return false;
4490
4491 return true;
4492}
4493
e0dac65e
WF		 4494static void g4x_write_eld(struct drm_connector *connector,
4495 struct drm_crtc *crtc)
4496{
4497 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4498 uint8_t *eld = connector->eld;
4499 uint32_t eldv;
4500 uint32_t len;
4501 uint32_t i;
4502
4503 i = I915_READ(G4X_AUD_VID_DID);
4504
4505 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4506 eldv = G4X_ELDV_DEVCL_DEVBLC;
4507 else
4508 eldv = G4X_ELDV_DEVCTG;
4509
3a9627f4
WF		 4510 if (intel_eld_uptodate(connector,
4511 G4X_AUD_CNTL_ST, eldv,
4512 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4513 G4X_HDMIW_HDMIEDID))
4514 return;
4515
e0dac65e
WF		 4516 i = I915_READ(G4X_AUD_CNTL_ST);
4517 i &= ~(eldv | G4X_ELD_ADDR);
4518 len = (i >> 9) & 0x1f; /* ELD buffer size */
4519 I915_WRITE(G4X_AUD_CNTL_ST, i);
4520
4521 if (!eld[0])
4522 return;
4523
4524 len = min_t(uint8_t, eld[2], len);
4525 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4526 for (i = 0; i < len; i++)
4527 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4528
4529 i = I915_READ(G4X_AUD_CNTL_ST);
4530 i |= eldv;
4531 I915_WRITE(G4X_AUD_CNTL_ST, i);
4532}
4533
4534static void ironlake_write_eld(struct drm_connector *connector,
4535 struct drm_crtc *crtc)
4536{
4537 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4538 uint8_t *eld = connector->eld;
4539 uint32_t eldv;
4540 uint32_t i;
4541 int len;
4542 int hdmiw_hdmiedid;
b6daa025 4543 int aud_config;
e0dac65e
WF		 4544 int aud_cntl_st;
4545 int aud_cntrl_st2;
4546
b3f33cbf 4547 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4548 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4549 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4550 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4551 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4552 } else {
1202b4c6 4553 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4554 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4555 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4556 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4557 }
4558
4559 i = to_intel_crtc(crtc)->pipe;
4560 hdmiw_hdmiedid += i * 0x100;
4561 aud_cntl_st += i * 0x100;
b6daa025 4562 aud_config += i * 0x100;
e0dac65e
WF		 4563
4564 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4565
4566 i = I915_READ(aud_cntl_st);
4567 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4568 if (!i) {
4569 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4570 /* operate blindly on all ports */
1202b4c6
WF		 4571 eldv = IBX_ELD_VALIDB;
4572 eldv |= IBX_ELD_VALIDB << 4;
4573 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4574 } else {
4575 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4576 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4577 }
4578
3a9627f4
WF		 4579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4580 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4581 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4582 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4583 } else
4584 I915_WRITE(aud_config, 0);
e0dac65e 4585
3a9627f4
WF		 4586 if (intel_eld_uptodate(connector,
4587 aud_cntrl_st2, eldv,
4588 aud_cntl_st, IBX_ELD_ADDRESS,
4589 hdmiw_hdmiedid))
4590 return;
4591
e0dac65e
WF		 4592 i = I915_READ(aud_cntrl_st2);
4593 i &= ~eldv;
4594 I915_WRITE(aud_cntrl_st2, i);
4595
4596 if (!eld[0])
4597 return;
4598
e0dac65e 4599 i = I915_READ(aud_cntl_st);
1202b4c6 4600 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4601 I915_WRITE(aud_cntl_st, i);
4602
4603 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4604 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4605 for (i = 0; i < len; i++)
4606 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4607
4608 i = I915_READ(aud_cntrl_st2);
4609 i |= eldv;
4610 I915_WRITE(aud_cntrl_st2, i);
4611}
4612
4613void intel_write_eld(struct drm_encoder *encoder,
4614 struct drm_display_mode *mode)
4615{
4616 struct drm_crtc *crtc = encoder->crtc;
4617 struct drm_connector *connector;
4618 struct drm_device *dev = encoder->dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620
4621 connector = drm_select_eld(encoder, mode);
4622 if (!connector)
4623 return;
4624
4625 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4626 connector->base.id,
4627 drm_get_connector_name(connector),
4628 connector->encoder->base.id,
4629 drm_get_encoder_name(connector->encoder));
4630
4631 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4632
4633 if (dev_priv->display.write_eld)
4634 dev_priv->display.write_eld(connector, crtc);
4635}
4636
79e53945
JB		 4637/** Loads the palette/gamma unit for the CRTC with the prepared values */
4638void intel_crtc_load_lut(struct drm_crtc *crtc)
4639{
4640 struct drm_device *dev = crtc->dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4643 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4644 int i;
4645
4646 /* The clocks have to be on to load the palette. */
aed3f09d 4647 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4648 return;
4649
f2b115e6 4650 /* use legacy palette for Ironlake */
bad720ff 4651 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4652 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4653
79e53945
JB		 4654 for (i = 0; i < 256; i++) {
4655 I915_WRITE(palreg + 4 * i,
4656 (intel_crtc->lut_r[i] << 16) |
4657 (intel_crtc->lut_g[i] << 8) |
4658 intel_crtc->lut_b[i]);
4659 }
4660}
4661
560b85bb
CW		 4662static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4663{
4664 struct drm_device *dev = crtc->dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4667 bool visible = base != 0;
4668 u32 cntl;
4669
4670 if (intel_crtc->cursor_visible == visible)
4671 return;
4672
9db4a9c7 4673 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4674 if (visible) {
4675 /* On these chipsets we can only modify the base whilst
4676 * the cursor is disabled.
4677 */
9db4a9c7 4678 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4679
4680 cntl &= ~(CURSOR_FORMAT_MASK);
4681 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4682 cntl |= CURSOR_ENABLE |
4683 CURSOR_GAMMA_ENABLE |
4684 CURSOR_FORMAT_ARGB;
4685 } else
4686 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4687 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4688
4689 intel_crtc->cursor_visible = visible;
4690}
4691
4692static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4693{
4694 struct drm_device *dev = crtc->dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4697 int pipe = intel_crtc->pipe;
4698 bool visible = base != 0;
4699
4700 if (intel_crtc->cursor_visible != visible) {
548f245b 4701 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4702 if (base) {
4703 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4704 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4705 cntl |= pipe << 28; /* Connect to correct pipe */
4706 } else {
4707 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4708 cntl |= CURSOR_MODE_DISABLE;
4709 }
9db4a9c7 4710 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4711
4712 intel_crtc->cursor_visible = visible;
4713 }
4714 /* and commit changes on next vblank */
9db4a9c7 4715 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4716}
4717
65a21cd6
JB		 4718static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4719{
4720 struct drm_device *dev = crtc->dev;
4721 struct drm_i915_private *dev_priv = dev->dev_private;
4722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4723 int pipe = intel_crtc->pipe;
4724 bool visible = base != 0;
4725
4726 if (intel_crtc->cursor_visible != visible) {
4727 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4728 if (base) {
4729 cntl &= ~CURSOR_MODE;
4730 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4731 } else {
4732 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4733 cntl |= CURSOR_MODE_DISABLE;
4734 }
4735 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4736
4737 intel_crtc->cursor_visible = visible;
4738 }
4739 /* and commit changes on next vblank */
4740 I915_WRITE(CURBASE_IVB(pipe), base);
4741}
4742
cda4b7d3 4743/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 4744static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4745 bool on)
cda4b7d3
CW		 4746{
4747 struct drm_device *dev = crtc->dev;
4748 struct drm_i915_private *dev_priv = dev->dev_private;
4749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4750 int pipe = intel_crtc->pipe;
4751 int x = intel_crtc->cursor_x;
4752 int y = intel_crtc->cursor_y;
560b85bb 4753 u32 base, pos;
cda4b7d3
CW		 4754 bool visible;
4755
4756 pos = 0;
4757
6b383a7f 4758 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 4759 base = intel_crtc->cursor_addr;
4760 if (x > (int) crtc->fb->width)
4761 base = 0;
4762
4763 if (y > (int) crtc->fb->height)
4764 base = 0;
4765 } else
4766 base = 0;
4767
4768 if (x < 0) {
4769 if (x + intel_crtc->cursor_width < 0)
4770 base = 0;
4771
4772 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4773 x = -x;
4774 }
4775 pos |= x << CURSOR_X_SHIFT;
4776
4777 if (y < 0) {
4778 if (y + intel_crtc->cursor_height < 0)
4779 base = 0;
4780
4781 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4782 y = -y;
4783 }
4784 pos |= y << CURSOR_Y_SHIFT;
4785
4786 visible = base != 0;
560b85bb 4787 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 4788 return;
4789
0cd83aa9 4790 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 4791 I915_WRITE(CURPOS_IVB(pipe), pos);
4792 ivb_update_cursor(crtc, base);
4793 } else {
4794 I915_WRITE(CURPOS(pipe), pos);
4795 if (IS_845G(dev) || IS_I865G(dev))
4796 i845_update_cursor(crtc, base);
4797 else
4798 i9xx_update_cursor(crtc, base);
4799 }
cda4b7d3
CW		 4800
4801 if (visible)
4802 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4803}
4804
79e53945 4805static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 4806 struct drm_file *file,
79e53945
JB		 4807 uint32_t handle,
4808 uint32_t width, uint32_t height)
4809{
4810 struct drm_device *dev = crtc->dev;
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 4813 struct drm_i915_gem_object *obj;
cda4b7d3 4814 uint32_t addr;
3f8bc370 4815 int ret;
79e53945 4816
28c97730 4817 DRM_DEBUG_KMS("\n");
79e53945
JB		 4818
4819 /* if we want to turn off the cursor ignore width and height */
4820 if (!handle) {
28c97730 4821 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 4822 addr = 0;
05394f39 4823 obj = NULL;
5004417d 4824 mutex_lock(&dev->struct_mutex);
3f8bc370 4825 goto finish;
79e53945
JB		 4826 }
4827
4828 /* Currently we only support 64x64 cursors */
4829 if (width != 64 || height != 64) {
4830 DRM_ERROR("we currently only support 64x64 cursors\n");
4831 return -EINVAL;
4832 }
4833
05394f39 4834 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 4835 if (&obj->base == NULL)
79e53945
JB		 4836 return -ENOENT;
4837
05394f39 4838 if (obj->base.size < width * height * 4) {
79e53945 4839 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 4840 ret = -ENOMEM;
4841 goto fail;
79e53945
JB		 4842 }
4843
71acb5eb 4844 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 4845 mutex_lock(&dev->struct_mutex);
b295d1b6 4846 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 4847 if (obj->tiling_mode) {
4848 DRM_ERROR("cursor cannot be tiled\n");
4849 ret = -EINVAL;
4850 goto fail_locked;
4851 }
4852
2da3b9b9 4853 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 4854 if (ret) {
4855 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 4856 goto fail_locked;
e7b526bb
CW		 4857 }
4858
d9e86c0e
CW		 4859 ret = i915_gem_object_put_fence(obj);
4860 if (ret) {
2da3b9b9 4861 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 4862 goto fail_unpin;
4863 }
4864
05394f39 4865 addr = obj->gtt_offset;
71acb5eb 4866 } else {
6eeefaf3 4867 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 4868 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 4869 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4870 align);
71acb5eb
DA		 4871 if (ret) {
4872 DRM_ERROR("failed to attach phys object\n");
7f9872e0 4873 goto fail_locked;
71acb5eb 4874 }
05394f39 4875 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 4876 }
4877
a6c45cf0 4878 if (IS_GEN2(dev))
14b60391
JB		 4879 I915_WRITE(CURSIZE, (height << 12) | width);
4880
3f8bc370 4881 finish:
3f8bc370 4882 if (intel_crtc->cursor_bo) {
b295d1b6 4883 if (dev_priv->info->cursor_needs_physical) {
05394f39 4884 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 4885 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4886 } else
4887 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 4888 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 4889 }
80824003 4890
7f9872e0 4891 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 4892
4893 intel_crtc->cursor_addr = addr;
05394f39 4894 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 4895 intel_crtc->cursor_width = width;
4896 intel_crtc->cursor_height = height;
4897
6b383a7f 4898 intel_crtc_update_cursor(crtc, true);
3f8bc370 4899
79e53945 4900 return 0;
e7b526bb 4901fail_unpin:
05394f39 4902 i915_gem_object_unpin(obj);
7f9872e0 4903fail_locked:
34b8686e 4904 mutex_unlock(&dev->struct_mutex);
bc9025bd 4905fail:
05394f39 4906 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 4907 return ret;
79e53945
JB		 4908}
4909
4910static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4911{
79e53945 4912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 4913
cda4b7d3
CW		 4914 intel_crtc->cursor_x = x;
4915 intel_crtc->cursor_y = y;
652c393a 4916
6b383a7f 4917 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 4918
4919 return 0;
4920}
4921
4922/** Sets the color ramps on behalf of RandR */
4923void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4924 u16 blue, int regno)
4925{
4926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4927
4928 intel_crtc->lut_r[regno] = red >> 8;
4929 intel_crtc->lut_g[regno] = green >> 8;
4930 intel_crtc->lut_b[regno] = blue >> 8;
4931}
4932
b8c00ac5
DA		 4933void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4934 u16 *blue, int regno)
4935{
4936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937
4938 *red = intel_crtc->lut_r[regno] << 8;
4939 *green = intel_crtc->lut_g[regno] << 8;
4940 *blue = intel_crtc->lut_b[regno] << 8;
4941}
4942
79e53945 4943static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 4944 u16 *blue, uint32_t start, uint32_t size)
79e53945 4945{
7203425a 4946 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 4947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 4948
7203425a 4949 for (i = start; i < end; i++) {
79e53945
JB		 4950 intel_crtc->lut_r[i] = red[i] >> 8;
4951 intel_crtc->lut_g[i] = green[i] >> 8;
4952 intel_crtc->lut_b[i] = blue[i] >> 8;
4953 }
4954
4955 intel_crtc_load_lut(crtc);
4956}
4957
4958/**
4959 * Get a pipe with a simple mode set on it for doing load-based monitor
4960 * detection.
4961 *
4962 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 4963 * its requirements. The pipe will be connected to no other encoders.
79e53945 4964 *
c751ce4f 4965 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 4966 * configured for it. In the future, it could choose to temporarily disable
4967 * some outputs to free up a pipe for its use.
4968 *
4969 * \return crtc, or NULL if no pipes are available.
4970 */
4971
4972/* VESA 640x480x72Hz mode to set on the pipe */
4973static struct drm_display_mode load_detect_mode = {
4974 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4975 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4976};
4977
d2dff872
CW		 4978static struct drm_framebuffer *
4979intel_framebuffer_create(struct drm_device *dev,
308e5bcb 4980 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 4981 struct drm_i915_gem_object *obj)
4982{
4983 struct intel_framebuffer *intel_fb;
4984 int ret;
4985
4986 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4987 if (!intel_fb) {
4988 drm_gem_object_unreference_unlocked(&obj->base);
4989 return ERR_PTR(-ENOMEM);
4990 }
4991
4992 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
4993 if (ret) {
4994 drm_gem_object_unreference_unlocked(&obj->base);
4995 kfree(intel_fb);
4996 return ERR_PTR(ret);
4997 }
4998
4999 return &intel_fb->base;
5000}
5001
5002static u32
5003intel_framebuffer_pitch_for_width(int width, int bpp)
5004{
5005 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5006 return ALIGN(pitch, 64);
5007}
5008
5009static u32
5010intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5011{
5012 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5013 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5014}
5015
5016static struct drm_framebuffer *
5017intel_framebuffer_create_for_mode(struct drm_device *dev,
5018 struct drm_display_mode *mode,
5019 int depth, int bpp)
5020{
5021 struct drm_i915_gem_object *obj;
308e5bcb 5022 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5023
5024 obj = i915_gem_alloc_object(dev,
5025 intel_framebuffer_size_for_mode(mode, bpp));
5026 if (obj == NULL)
5027 return ERR_PTR(-ENOMEM);
5028
5029 mode_cmd.width = mode->hdisplay;
5030 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5031 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5032 bpp);
5ca0c34a 5033 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5034
5035 return intel_framebuffer_create(dev, &mode_cmd, obj);
5036}
5037
5038static struct drm_framebuffer *
5039mode_fits_in_fbdev(struct drm_device *dev,
5040 struct drm_display_mode *mode)
5041{
5042 struct drm_i915_private *dev_priv = dev->dev_private;
5043 struct drm_i915_gem_object *obj;
5044 struct drm_framebuffer *fb;
5045
5046 if (dev_priv->fbdev == NULL)
5047 return NULL;
5048
5049 obj = dev_priv->fbdev->ifb.obj;
5050 if (obj == NULL)
5051 return NULL;
5052
5053 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5054 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5055 fb->bits_per_pixel))
d2dff872
CW		 5056 return NULL;
5057
01f2c773 5058 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5059 return NULL;
5060
5061 return fb;
5062}
5063
7173188d
CW		 5064bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5065 struct drm_connector *connector,
5066 struct drm_display_mode *mode,
8261b191 5067 struct intel_load_detect_pipe *old)
79e53945
JB		 5068{
5069 struct intel_crtc *intel_crtc;
5070 struct drm_crtc *possible_crtc;
4ef69c7a 5071 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5072 struct drm_crtc *crtc = NULL;
5073 struct drm_device *dev = encoder->dev;
d2dff872 5074 struct drm_framebuffer *old_fb;
79e53945
JB		 5075 int i = -1;
5076
d2dff872
CW		 5077 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5078 connector->base.id, drm_get_connector_name(connector),
5079 encoder->base.id, drm_get_encoder_name(encoder));
5080
79e53945
JB		 5081 /*
5082 * Algorithm gets a little messy:
7a5e4805 5083 *
79e53945
JB		 5084 * - if the connector already has an assigned crtc, use it (but make
5085 * sure it's on first)
7a5e4805 5086 *
79e53945
JB		 5087 * - try to find the first unused crtc that can drive this connector,
5088 * and use that if we find one
79e53945
JB		 5089 */
5090
5091 /* See if we already have a CRTC for this connector */
5092 if (encoder->crtc) {
5093 crtc = encoder->crtc;
8261b191 5094
79e53945 5095 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5096 old->dpms_mode = intel_crtc->dpms_mode;
5097 old->load_detect_temp = false;
5098
5099 /* Make sure the crtc and connector are running */
79e53945 5100 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5101 struct drm_encoder_helper_funcs *encoder_funcs;
5102 struct drm_crtc_helper_funcs *crtc_funcs;
5103
79e53945
JB		 5104 crtc_funcs = crtc->helper_private;
5105 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5106
5107 encoder_funcs = encoder->helper_private;
79e53945
JB		 5108 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5109 }
8261b191 5110
7173188d 5111 return true;
79e53945
JB		 5112 }
5113
5114 /* Find an unused one (if possible) */
5115 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5116 i++;
5117 if (!(encoder->possible_crtcs & (1 << i)))
5118 continue;
5119 if (!possible_crtc->enabled) {
5120 crtc = possible_crtc;
5121 break;
5122 }
79e53945
JB		 5123 }
5124
5125 /*
5126 * If we didn't find an unused CRTC, don't use any.
5127 */
5128 if (!crtc) {
7173188d
CW		 5129 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5130 return false;
79e53945
JB		 5131 }
5132
5133 encoder->crtc = crtc;
c1c43977 5134 connector->encoder = encoder;
79e53945
JB		 5135
5136 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5137 old->dpms_mode = intel_crtc->dpms_mode;
5138 old->load_detect_temp = true;
d2dff872 5139 old->release_fb = NULL;
79e53945 5140
6492711d
CW		 5141 if (!mode)
5142 mode = &load_detect_mode;
79e53945 5143
d2dff872
CW		 5144 old_fb = crtc->fb;
5145
5146 /* We need a framebuffer large enough to accommodate all accesses
5147 * that the plane may generate whilst we perform load detection.
5148 * We can not rely on the fbcon either being present (we get called
5149 * during its initialisation to detect all boot displays, or it may
5150 * not even exist) or that it is large enough to satisfy the
5151 * requested mode.
5152 */
5153 crtc->fb = mode_fits_in_fbdev(dev, mode);
5154 if (crtc->fb == NULL) {
5155 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5156 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5157 old->release_fb = crtc->fb;
5158 } else
5159 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5160 if (IS_ERR(crtc->fb)) {
5161 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5162 crtc->fb = old_fb;
5163 return false;
79e53945 5164 }
79e53945 5165
d2dff872 5166 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5167 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5168 if (old->release_fb)
5169 old->release_fb->funcs->destroy(old->release_fb);
5170 crtc->fb = old_fb;
6492711d 5171 return false;
79e53945 5172 }
7173188d 5173
79e53945 5174 /* let the connector get through one full cycle before testing */
9d0498a2 5175 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5176
7173188d 5177 return true;
79e53945
JB		 5178}
5179
c1c43977 5180void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5181 struct drm_connector *connector,
5182 struct intel_load_detect_pipe *old)
79e53945 5183{
4ef69c7a 5184 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5185 struct drm_device *dev = encoder->dev;
5186 struct drm_crtc *crtc = encoder->crtc;
5187 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5188 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5189
d2dff872
CW		 5190 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5191 connector->base.id, drm_get_connector_name(connector),
5192 encoder->base.id, drm_get_encoder_name(encoder));
5193
8261b191 5194 if (old->load_detect_temp) {
c1c43977 5195 connector->encoder = NULL;
79e53945 5196 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5197
5198 if (old->release_fb)
5199 old->release_fb->funcs->destroy(old->release_fb);
5200
0622a53c 5201 return;
79e53945
JB		 5202 }
5203
c751ce4f 5204 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5205 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5206 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5207 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5208 }
5209}
5210
5211/* Returns the clock of the currently programmed mode of the given pipe. */
5212static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5213{
5214 struct drm_i915_private *dev_priv = dev->dev_private;
5215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216 int pipe = intel_crtc->pipe;
548f245b 5217 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5218 u32 fp;
5219 intel_clock_t clock;
5220
5221 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5222 fp = I915_READ(FP0(pipe));
79e53945 5223 else
39adb7a5 5224 fp = I915_READ(FP1(pipe));
79e53945
JB		 5225
5226 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5227 if (IS_PINEVIEW(dev)) {
5228 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5229 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5230 } else {
5231 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5232 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5233 }
5234
a6c45cf0 5235 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5236 if (IS_PINEVIEW(dev))
5237 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5238 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5239 else
5240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5241 DPLL_FPA01_P1_POST_DIV_SHIFT);
5242
5243 switch (dpll & DPLL_MODE_MASK) {
5244 case DPLLB_MODE_DAC_SERIAL:
5245 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5246 5 : 10;
5247 break;
5248 case DPLLB_MODE_LVDS:
5249 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5250 7 : 14;
5251 break;
5252 default:
28c97730 5253 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5254 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5255 return 0;
5256 }
5257
5258 /* XXX: Handle the 100Mhz refclk */
2177832f 5259 intel_clock(dev, 96000, &clock);
79e53945
JB		 5260 } else {
5261 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5262
5263 if (is_lvds) {
5264 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5265 DPLL_FPA01_P1_POST_DIV_SHIFT);
5266 clock.p2 = 14;
5267
5268 if ((dpll & PLL_REF_INPUT_MASK) ==
5269 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5270 /* XXX: might not be 66MHz */
2177832f 5271 intel_clock(dev, 66000, &clock);
79e53945 5272 } else
2177832f 5273 intel_clock(dev, 48000, &clock);
79e53945
JB		 5274 } else {
5275 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5276 clock.p1 = 2;
5277 else {
5278 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5279 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5280 }
5281 if (dpll & PLL_P2_DIVIDE_BY_4)
5282 clock.p2 = 4;
5283 else
5284 clock.p2 = 2;
5285
2177832f 5286 intel_clock(dev, 48000, &clock);
79e53945
JB		 5287 }
5288 }
5289
5290 /* XXX: It would be nice to validate the clocks, but we can't reuse
5291 * i830PllIsValid() because it relies on the xf86_config connector
5292 * configuration being accurate, which it isn't necessarily.
5293 */
5294
5295 return clock.dot;
5296}
5297
5298/** Returns the currently programmed mode of the given pipe. */
5299struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5300 struct drm_crtc *crtc)
5301{
548f245b 5302 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304 int pipe = intel_crtc->pipe;
5305 struct drm_display_mode *mode;
548f245b
JB		 5306 int htot = I915_READ(HTOTAL(pipe));
5307 int hsync = I915_READ(HSYNC(pipe));
5308 int vtot = I915_READ(VTOTAL(pipe));
5309 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5310
5311 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5312 if (!mode)
5313 return NULL;
5314
5315 mode->clock = intel_crtc_clock_get(dev, crtc);
5316 mode->hdisplay = (htot & 0xffff) + 1;
5317 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5318 mode->hsync_start = (hsync & 0xffff) + 1;
5319 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5320 mode->vdisplay = (vtot & 0xffff) + 1;
5321 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5322 mode->vsync_start = (vsync & 0xffff) + 1;
5323 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5324
5325 drm_mode_set_name(mode);
5326 drm_mode_set_crtcinfo(mode, 0);
5327
5328 return mode;
5329}
5330
652c393a
JB		 5331#define GPU_IDLE_TIMEOUT 500 /* ms */
5332
5333/* When this timer fires, we've been idle for awhile */
5334static void intel_gpu_idle_timer(unsigned long arg)
5335{
5336 struct drm_device *dev = (struct drm_device *)arg;
5337 drm_i915_private_t *dev_priv = dev->dev_private;
5338
ff7ea4c0
CW		 5339 if (!list_empty(&dev_priv->mm.active_list)) {
5340 /* Still processing requests, so just re-arm the timer. */
5341 mod_timer(&dev_priv->idle_timer, jiffies +
5342 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5343 return;
5344 }
652c393a 5345
ff7ea4c0 5346 dev_priv->busy = false;
01dfba93 5347 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5348}
5349
652c393a
JB		 5350#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5351
5352static void intel_crtc_idle_timer(unsigned long arg)
5353{
5354 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5355 struct drm_crtc *crtc = &intel_crtc->base;
5356 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5357 struct intel_framebuffer *intel_fb;
652c393a 5358
ff7ea4c0
CW		 5359 intel_fb = to_intel_framebuffer(crtc->fb);
5360 if (intel_fb && intel_fb->obj->active) {
5361 /* The framebuffer is still being accessed by the GPU. */
5362 mod_timer(&intel_crtc->idle_timer, jiffies +
5363 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5364 return;
5365 }
652c393a 5366
ff7ea4c0 5367 intel_crtc->busy = false;
01dfba93 5368 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5369}
5370
3dec0095 5371static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5372{
5373 struct drm_device *dev = crtc->dev;
5374 drm_i915_private_t *dev_priv = dev->dev_private;
5375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5377 int dpll_reg = DPLL(pipe);
5378 int dpll;
652c393a 5379
bad720ff 5380 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5381 return;
5382
5383 if (!dev_priv->lvds_downclock_avail)
5384 return;
5385
dbdc6479 5386 dpll = I915_READ(dpll_reg);
652c393a 5387 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5388 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5389
8ac5a6d5 5390 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5391
5392 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5393 I915_WRITE(dpll_reg, dpll);
9d0498a2 5394 intel_wait_for_vblank(dev, pipe);
dbdc6479 5395
652c393a
JB		 5396 dpll = I915_READ(dpll_reg);
5397 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5398 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5399 }
5400
5401 /* Schedule downclock */
3dec0095
DV		 5402 mod_timer(&intel_crtc->idle_timer, jiffies +
5403 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5404}
5405
5406static void intel_decrease_pllclock(struct drm_crtc *crtc)
5407{
5408 struct drm_device *dev = crtc->dev;
5409 drm_i915_private_t *dev_priv = dev->dev_private;
5410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411 int pipe = intel_crtc->pipe;
9db4a9c7 5412 int dpll_reg = DPLL(pipe);
652c393a
JB		 5413 int dpll = I915_READ(dpll_reg);
5414
bad720ff 5415 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5416 return;
5417
5418 if (!dev_priv->lvds_downclock_avail)
5419 return;
5420
5421 /*
5422 * Since this is called by a timer, we should never get here in
5423 * the manual case.
5424 */
5425 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 5426 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5427
8ac5a6d5 5428 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5429
5430 dpll |= DISPLAY_RATE_SELECT_FPA1;
5431 I915_WRITE(dpll_reg, dpll);
9d0498a2 5432 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5433 dpll = I915_READ(dpll_reg);
5434 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5435 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5436 }
5437
5438}
5439
5440/**
5441 * intel_idle_update - adjust clocks for idleness
5442 * @work: work struct
5443 *
5444 * Either the GPU or display (or both) went idle. Check the busy status
5445 * here and adjust the CRTC and GPU clocks as necessary.
5446 */
5447static void intel_idle_update(struct work_struct *work)
5448{
5449 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5450 idle_work);
5451 struct drm_device *dev = dev_priv->dev;
5452 struct drm_crtc *crtc;
5453 struct intel_crtc *intel_crtc;
5454
5455 if (!i915_powersave)
5456 return;
5457
5458 mutex_lock(&dev->struct_mutex);
5459
7648fa99
JB		 5460 i915_update_gfx_val(dev_priv);
5461
652c393a
JB		 5462 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5463 /* Skip inactive CRTCs */
5464 if (!crtc->fb)
5465 continue;
5466
5467 intel_crtc = to_intel_crtc(crtc);
5468 if (!intel_crtc->busy)
5469 intel_decrease_pllclock(crtc);
5470 }
5471
45ac22c8 5472
652c393a
JB		 5473 mutex_unlock(&dev->struct_mutex);
5474}
5475
5476/**
5477 * intel_mark_busy - mark the GPU and possibly the display busy
5478 * @dev: drm device
5479 * @obj: object we're operating on
5480 *
5481 * Callers can use this function to indicate that the GPU is busy processing
5482 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5483 * buffer), we'll also mark the display as busy, so we know to increase its
5484 * clock frequency.
5485 */
05394f39 5486void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5487{
5488 drm_i915_private_t *dev_priv = dev->dev_private;
5489 struct drm_crtc *crtc = NULL;
5490 struct intel_framebuffer *intel_fb;
5491 struct intel_crtc *intel_crtc;
5492
5e17ee74
ZW		 5493 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5494 return;
5495
18b2190c 5496 if (!dev_priv->busy)
28cf798f 5497 dev_priv->busy = true;
18b2190c 5498 else
28cf798f
CW		 5499 mod_timer(&dev_priv->idle_timer, jiffies +
5500 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 5501
5502 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5503 if (!crtc->fb)
5504 continue;
5505
5506 intel_crtc = to_intel_crtc(crtc);
5507 intel_fb = to_intel_framebuffer(crtc->fb);
5508 if (intel_fb->obj == obj) {
5509 if (!intel_crtc->busy) {
5510 /* Non-busy -> busy, upclock */
3dec0095 5511 intel_increase_pllclock(crtc);
652c393a
JB		 5512 intel_crtc->busy = true;
5513 } else {
5514 /* Busy -> busy, put off timer */
5515 mod_timer(&intel_crtc->idle_timer, jiffies +
5516 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5517 }
5518 }
5519 }
5520}
5521
79e53945
JB		 5522static void intel_crtc_destroy(struct drm_crtc *crtc)
5523{
5524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5525 struct drm_device *dev = crtc->dev;
5526 struct intel_unpin_work *work;
5527 unsigned long flags;
5528
5529 spin_lock_irqsave(&dev->event_lock, flags);
5530 work = intel_crtc->unpin_work;
5531 intel_crtc->unpin_work = NULL;
5532 spin_unlock_irqrestore(&dev->event_lock, flags);
5533
5534 if (work) {
5535 cancel_work_sync(&work->work);
5536 kfree(work);
5537 }
79e53945
JB		 5538
5539 drm_crtc_cleanup(crtc);
67e77c5a 5540
79e53945
JB		 5541 kfree(intel_crtc);
5542}
5543
6b95a207
KH		 5544static void intel_unpin_work_fn(struct work_struct *__work)
5545{
5546 struct intel_unpin_work *work =
5547 container_of(__work, struct intel_unpin_work, work);
5548
5549 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5550 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5551 drm_gem_object_unreference(&work->pending_flip_obj->base);
5552 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5553
7782de3b 5554 intel_update_fbc(work->dev);
6b95a207
KH		 5555 mutex_unlock(&work->dev->struct_mutex);
5556 kfree(work);
5557}
5558
1afe3e9d 5559static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5560 struct drm_crtc *crtc)
6b95a207
KH		 5561{
5562 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5564 struct intel_unpin_work *work;
05394f39 5565 struct drm_i915_gem_object *obj;
6b95a207 5566 struct drm_pending_vblank_event *e;
49b14a5c 5567 struct timeval tnow, tvbl;
6b95a207
KH		 5568 unsigned long flags;
5569
5570 /* Ignore early vblank irqs */
5571 if (intel_crtc == NULL)
5572 return;
5573
49b14a5c
MK		 5574 do_gettimeofday(&tnow);
5575
6b95a207
KH		 5576 spin_lock_irqsave(&dev->event_lock, flags);
5577 work = intel_crtc->unpin_work;
5578 if (work == NULL || !work->pending) {
5579 spin_unlock_irqrestore(&dev->event_lock, flags);
5580 return;
5581 }
5582
5583 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5584
5585 if (work->event) {
5586 e = work->event;
49b14a5c 5587 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5588
5589 /* Called before vblank count and timestamps have
5590 * been updated for the vblank interval of flip
5591 * completion? Need to increment vblank count and
5592 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5593 * to account for this. We assume this happened if we
5594 * get called over 0.9 frame durations after the last
5595 * timestamped vblank.
5596 *
5597 * This calculation can not be used with vrefresh rates
5598 * below 5Hz (10Hz to be on the safe side) without
5599 * promoting to 64 integers.
0af7e4df 5600 */
49b14a5c
MK		 5601 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5602 9 * crtc->framedur_ns) {
0af7e4df 5603 e->event.sequence++;
49b14a5c
MK		 5604 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5605 crtc->framedur_ns);
0af7e4df
MK		 5606 }
5607
49b14a5c
MK		 5608 e->event.tv_sec = tvbl.tv_sec;
5609 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5610
6b95a207
KH		 5611 list_add_tail(&e->base.link,
5612 &e->base.file_priv->event_list);
5613 wake_up_interruptible(&e->base.file_priv->event_wait);
5614 }
5615
0af7e4df
MK		 5616 drm_vblank_put(dev, intel_crtc->pipe);
5617
6b95a207
KH		 5618 spin_unlock_irqrestore(&dev->event_lock, flags);
5619
05394f39 5620 obj = work->old_fb_obj;
d9e86c0e 5621
e59f2bac 5622 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5623 &obj->pending_flip.counter);
5624 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5625 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5626
6b95a207 5627 schedule_work(&work->work);
e5510fac
JB		 5628
5629 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5630}
5631
1afe3e9d
JB		 5632void intel_finish_page_flip(struct drm_device *dev, int pipe)
5633{
5634 drm_i915_private_t *dev_priv = dev->dev_private;
5635 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5636
49b14a5c 5637 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5638}
5639
5640void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5641{
5642 drm_i915_private_t *dev_priv = dev->dev_private;
5643 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5644
49b14a5c 5645 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5646}
5647
6b95a207
KH		 5648void intel_prepare_page_flip(struct drm_device *dev, int plane)
5649{
5650 drm_i915_private_t *dev_priv = dev->dev_private;
5651 struct intel_crtc *intel_crtc =
5652 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5653 unsigned long flags;
5654
5655 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5656 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5657 if ((++intel_crtc->unpin_work->pending) > 1)
5658 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5659 } else {
5660 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5661 }
6b95a207
KH		 5662 spin_unlock_irqrestore(&dev->event_lock, flags);
5663}
5664
8c9f3aaf
JB		 5665static int intel_gen2_queue_flip(struct drm_device *dev,
5666 struct drm_crtc *crtc,
5667 struct drm_framebuffer *fb,
5668 struct drm_i915_gem_object *obj)
5669{
5670 struct drm_i915_private *dev_priv = dev->dev_private;
5671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5672 unsigned long offset;
5673 u32 flip_mask;
5674 int ret;
5675
5676 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5677 if (ret)
83d4092b 5678 goto err;
8c9f3aaf
JB		 5679
5680 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5681 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 5682
5683 ret = BEGIN_LP_RING(6);
5684 if (ret)
83d4092b 5685 goto err_unpin;
8c9f3aaf
JB		 5686
5687 /* Can't queue multiple flips, so wait for the previous
5688 * one to finish before executing the next.
5689 */
5690 if (intel_crtc->plane)
5691 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5692 else
5693 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5694 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5695 OUT_RING(MI_NOOP);
5696 OUT_RING(MI_DISPLAY_FLIP |
5697 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 5698 OUT_RING(fb->pitches[0]);
8c9f3aaf 5699 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 5700 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf 5701 ADVANCE_LP_RING();
83d4092b
CW		 5702 return 0;
5703
5704err_unpin:
5705 intel_unpin_fb_obj(obj);
5706err:
8c9f3aaf
JB		 5707 return ret;
5708}
5709
5710static int intel_gen3_queue_flip(struct drm_device *dev,
5711 struct drm_crtc *crtc,
5712 struct drm_framebuffer *fb,
5713 struct drm_i915_gem_object *obj)
5714{
5715 struct drm_i915_private *dev_priv = dev->dev_private;
5716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5717 unsigned long offset;
5718 u32 flip_mask;
5719 int ret;
5720
5721 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5722 if (ret)
83d4092b 5723 goto err;
8c9f3aaf
JB		 5724
5725 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5726 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 5727
5728 ret = BEGIN_LP_RING(6);
5729 if (ret)
83d4092b 5730 goto err_unpin;
8c9f3aaf
JB		 5731
5732 if (intel_crtc->plane)
5733 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5734 else
5735 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5736 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5737 OUT_RING(MI_NOOP);
5738 OUT_RING(MI_DISPLAY_FLIP_I915 |
5739 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 5740 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 5741 OUT_RING(obj->gtt_offset + offset);
5742 OUT_RING(MI_NOOP);
5743
5744 ADVANCE_LP_RING();
83d4092b
CW		 5745 return 0;
5746
5747err_unpin:
5748 intel_unpin_fb_obj(obj);
5749err:
8c9f3aaf
JB		 5750 return ret;
5751}
5752
5753static int intel_gen4_queue_flip(struct drm_device *dev,
5754 struct drm_crtc *crtc,
5755 struct drm_framebuffer *fb,
5756 struct drm_i915_gem_object *obj)
5757{
5758 struct drm_i915_private *dev_priv = dev->dev_private;
5759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760 uint32_t pf, pipesrc;
5761 int ret;
5762
5763 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5764 if (ret)
83d4092b 5765 goto err;
8c9f3aaf
JB		 5766
5767 ret = BEGIN_LP_RING(4);
5768 if (ret)
83d4092b 5769 goto err_unpin;
8c9f3aaf
JB		 5770
5771 /* i965+ uses the linear or tiled offsets from the
5772 * Display Registers (which do not change across a page-flip)
5773 * so we need only reprogram the base address.
5774 */
5775 OUT_RING(MI_DISPLAY_FLIP |
5776 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 5777 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 5778 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5779
5780 /* XXX Enabling the panel-fitter across page-flip is so far
5781 * untested on non-native modes, so ignore it for now.
5782 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5783 */
5784 pf = 0;
5785 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5786 OUT_RING(pf | pipesrc);
5787 ADVANCE_LP_RING();
83d4092b
CW		 5788 return 0;
5789
5790err_unpin:
5791 intel_unpin_fb_obj(obj);
5792err:
8c9f3aaf
JB		 5793 return ret;
5794}
5795
5796static int intel_gen6_queue_flip(struct drm_device *dev,
5797 struct drm_crtc *crtc,
5798 struct drm_framebuffer *fb,
5799 struct drm_i915_gem_object *obj)
5800{
5801 struct drm_i915_private *dev_priv = dev->dev_private;
5802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5803 uint32_t pf, pipesrc;
5804 int ret;
5805
5806 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5807 if (ret)
83d4092b 5808 goto err;
8c9f3aaf
JB		 5809
5810 ret = BEGIN_LP_RING(4);
5811 if (ret)
83d4092b 5812 goto err_unpin;
8c9f3aaf
JB		 5813
5814 OUT_RING(MI_DISPLAY_FLIP |
5815 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 5816 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 5817 OUT_RING(obj->gtt_offset);
5818
5819 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5820 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5821 OUT_RING(pf | pipesrc);
5822 ADVANCE_LP_RING();
83d4092b
CW		 5823 return 0;
5824
5825err_unpin:
5826 intel_unpin_fb_obj(obj);
5827err:
8c9f3aaf
JB		 5828 return ret;
5829}
5830
7c9017e5
JB		 5831/*
5832 * On gen7 we currently use the blit ring because (in early silicon at least)
5833 * the render ring doesn't give us interrpts for page flip completion, which
5834 * means clients will hang after the first flip is queued. Fortunately the
5835 * blit ring generates interrupts properly, so use it instead.
5836 */
5837static int intel_gen7_queue_flip(struct drm_device *dev,
5838 struct drm_crtc *crtc,
5839 struct drm_framebuffer *fb,
5840 struct drm_i915_gem_object *obj)
5841{
5842 struct drm_i915_private *dev_priv = dev->dev_private;
5843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5844 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5845 int ret;
5846
5847 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5848 if (ret)
83d4092b 5849 goto err;
7c9017e5
JB		 5850
5851 ret = intel_ring_begin(ring, 4);
5852 if (ret)
83d4092b 5853 goto err_unpin;
7c9017e5
JB		 5854
5855 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 5856 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 5857 intel_ring_emit(ring, (obj->gtt_offset));
5858 intel_ring_emit(ring, (MI_NOOP));
5859 intel_ring_advance(ring);
83d4092b
CW		 5860 return 0;
5861
5862err_unpin:
5863 intel_unpin_fb_obj(obj);
5864err:
7c9017e5
JB		 5865 return ret;
5866}
5867
8c9f3aaf
JB		 5868static int intel_default_queue_flip(struct drm_device *dev,
5869 struct drm_crtc *crtc,
5870 struct drm_framebuffer *fb,
5871 struct drm_i915_gem_object *obj)
5872{
5873 return -ENODEV;
5874}
5875
6b95a207
KH		 5876static int intel_crtc_page_flip(struct drm_crtc *crtc,
5877 struct drm_framebuffer *fb,
5878 struct drm_pending_vblank_event *event)
5879{
5880 struct drm_device *dev = crtc->dev;
5881 struct drm_i915_private *dev_priv = dev->dev_private;
5882 struct intel_framebuffer *intel_fb;
05394f39 5883 struct drm_i915_gem_object *obj;
6b95a207
KH		 5884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5885 struct intel_unpin_work *work;
8c9f3aaf 5886 unsigned long flags;
52e68630 5887 int ret;
6b95a207
KH		 5888
5889 work = kzalloc(sizeof *work, GFP_KERNEL);
5890 if (work == NULL)
5891 return -ENOMEM;
5892
6b95a207
KH		 5893 work->event = event;
5894 work->dev = crtc->dev;
5895 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 5896 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 5897 INIT_WORK(&work->work, intel_unpin_work_fn);
5898
7317c75e
JB		 5899 ret = drm_vblank_get(dev, intel_crtc->pipe);
5900 if (ret)
5901 goto free_work;
5902
6b95a207
KH		 5903 /* We borrow the event spin lock for protecting unpin_work */
5904 spin_lock_irqsave(&dev->event_lock, flags);
5905 if (intel_crtc->unpin_work) {
5906 spin_unlock_irqrestore(&dev->event_lock, flags);
5907 kfree(work);
7317c75e 5908 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 5909
5910 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 5911 return -EBUSY;
5912 }
5913 intel_crtc->unpin_work = work;
5914 spin_unlock_irqrestore(&dev->event_lock, flags);
5915
5916 intel_fb = to_intel_framebuffer(fb);
5917 obj = intel_fb->obj;
5918
468f0b44 5919 mutex_lock(&dev->struct_mutex);
6b95a207 5920
75dfca80 5921 /* Reference the objects for the scheduled work. */
05394f39
CW		 5922 drm_gem_object_reference(&work->old_fb_obj->base);
5923 drm_gem_object_reference(&obj->base);
6b95a207
KH		 5924
5925 crtc->fb = fb;
96b099fd 5926
e1f99ce6 5927 work->pending_flip_obj = obj;
e1f99ce6 5928
4e5359cd
SF		 5929 work->enable_stall_check = true;
5930
e1f99ce6
CW		 5931 /* Block clients from rendering to the new back buffer until
5932 * the flip occurs and the object is no longer visible.
5933 */
05394f39 5934 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 5935
8c9f3aaf
JB		 5936 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5937 if (ret)
5938 goto cleanup_pending;
6b95a207 5939
7782de3b 5940 intel_disable_fbc(dev);
6b95a207
KH		 5941 mutex_unlock(&dev->struct_mutex);
5942
e5510fac
JB		 5943 trace_i915_flip_request(intel_crtc->plane, obj);
5944
6b95a207 5945 return 0;
96b099fd 5946
8c9f3aaf
JB		 5947cleanup_pending:
5948 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 5949 drm_gem_object_unreference(&work->old_fb_obj->base);
5950 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 5951 mutex_unlock(&dev->struct_mutex);
5952
5953 spin_lock_irqsave(&dev->event_lock, flags);
5954 intel_crtc->unpin_work = NULL;
5955 spin_unlock_irqrestore(&dev->event_lock, flags);
5956
7317c75e
JB		 5957 drm_vblank_put(dev, intel_crtc->pipe);
5958free_work:
96b099fd
CW		 5959 kfree(work);
5960
5961 return ret;
6b95a207
KH		 5962}
5963
47f1c6c9
CW		 5964static void intel_sanitize_modesetting(struct drm_device *dev,
5965 int pipe, int plane)
5966{
5967 struct drm_i915_private *dev_priv = dev->dev_private;
5968 u32 reg, val;
5969
f47166d2
CW		 5970 /* Clear any frame start delays used for debugging left by the BIOS */
5971 for_each_pipe(pipe) {
5972 reg = PIPECONF(pipe);
5973 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
5974 }
5975
47f1c6c9
CW		 5976 if (HAS_PCH_SPLIT(dev))
5977 return;
5978
5979 /* Who knows what state these registers were left in by the BIOS or
5980 * grub?
5981 *
5982 * If we leave the registers in a conflicting state (e.g. with the
5983 * display plane reading from the other pipe than the one we intend
5984 * to use) then when we attempt to teardown the active mode, we will
5985 * not disable the pipes and planes in the correct order -- leaving
5986 * a plane reading from a disabled pipe and possibly leading to
5987 * undefined behaviour.
5988 */
5989
5990 reg = DSPCNTR(plane);
5991 val = I915_READ(reg);
5992
5993 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5994 return;
5995 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5996 return;
5997
5998 /* This display plane is active and attached to the other CPU pipe. */
5999 pipe = !pipe;
6000
6001 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6002 intel_disable_plane(dev_priv, plane, pipe);
6003 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6004}
79e53945 6005
f6e5b160
CW		 6006static void intel_crtc_reset(struct drm_crtc *crtc)
6007{
6008 struct drm_device *dev = crtc->dev;
6009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6010
6011 /* Reset flags back to the 'unknown' status so that they
6012 * will be correctly set on the initial modeset.
6013 */
6014 intel_crtc->dpms_mode = -1;
6015
6016 /* We need to fix up any BIOS configuration that conflicts with
6017 * our expectations.
6018 */
6019 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6020}
6021
6022static struct drm_crtc_helper_funcs intel_helper_funcs = {
6023 .dpms = intel_crtc_dpms,
6024 .mode_fixup = intel_crtc_mode_fixup,
6025 .mode_set = intel_crtc_mode_set,
6026 .mode_set_base = intel_pipe_set_base,
6027 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6028 .load_lut = intel_crtc_load_lut,
6029 .disable = intel_crtc_disable,
6030};
6031
6032static const struct drm_crtc_funcs intel_crtc_funcs = {
6033 .reset = intel_crtc_reset,
6034 .cursor_set = intel_crtc_cursor_set,
6035 .cursor_move = intel_crtc_cursor_move,
6036 .gamma_set = intel_crtc_gamma_set,
6037 .set_config = drm_crtc_helper_set_config,
6038 .destroy = intel_crtc_destroy,
6039 .page_flip = intel_crtc_page_flip,
6040};
6041
b358d0a6 6042static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6043{
22fd0fab 6044 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6045 struct intel_crtc *intel_crtc;
6046 int i;
6047
6048 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6049 if (intel_crtc == NULL)
6050 return;
6051
6052 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6053
6054 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6055 for (i = 0; i < 256; i++) {
6056 intel_crtc->lut_r[i] = i;
6057 intel_crtc->lut_g[i] = i;
6058 intel_crtc->lut_b[i] = i;
6059 }
6060
80824003
JB		 6061 /* Swap pipes & planes for FBC on pre-965 */
6062 intel_crtc->pipe = pipe;
6063 intel_crtc->plane = pipe;
e2e767ab 6064 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6065 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6066 intel_crtc->plane = !pipe;
80824003
JB		 6067 }
6068
22fd0fab
JB		 6069 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6070 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6071 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6072 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6073
5d1d0cc8 6074 intel_crtc_reset(&intel_crtc->base);
04dbff52 6075 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6076 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6077
6078 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 6079 if (pipe == 2 && IS_IVYBRIDGE(dev))
6080 intel_crtc->no_pll = true;
7e7d76c3
JB		 6081 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6082 intel_helper_funcs.commit = ironlake_crtc_commit;
6083 } else {
6084 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6085 intel_helper_funcs.commit = i9xx_crtc_commit;
6086 }
6087
79e53945
JB		 6088 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6089
652c393a
JB		 6090 intel_crtc->busy = false;
6091
6092 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6093 (unsigned long)intel_crtc);
79e53945
JB		 6094}
6095
08d7b3d1 6096int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6097 struct drm_file *file)
08d7b3d1
CW		 6098{
6099 drm_i915_private_t *dev_priv = dev->dev_private;
6100 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6101 struct drm_mode_object *drmmode_obj;
6102 struct intel_crtc *crtc;
08d7b3d1
CW		 6103
6104 if (!dev_priv) {
6105 DRM_ERROR("called with no initialization\n");
6106 return -EINVAL;
6107 }
6108
c05422d5
DV		 6109 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6110 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6111
c05422d5 6112 if (!drmmode_obj) {
08d7b3d1
CW		 6113 DRM_ERROR("no such CRTC id\n");
6114 return -EINVAL;
6115 }
6116
c05422d5
DV		 6117 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6118 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6119
c05422d5 6120 return 0;
08d7b3d1
CW		 6121}
6122
c5e4df33 6123static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6124{
4ef69c7a 6125 struct intel_encoder *encoder;
79e53945 6126 int index_mask = 0;
79e53945
JB		 6127 int entry = 0;
6128
4ef69c7a
CW		 6129 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6130 if (type_mask & encoder->clone_mask)
79e53945
JB		 6131 index_mask |= (1 << entry);
6132 entry++;
6133 }
4ef69c7a 6134
79e53945
JB		 6135 return index_mask;
6136}
6137
4d302442
CW		 6138static bool has_edp_a(struct drm_device *dev)
6139{
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142 if (!IS_MOBILE(dev))
6143 return false;
6144
6145 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6146 return false;
6147
6148 if (IS_GEN5(dev) &&
6149 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6150 return false;
6151
6152 return true;
6153}
6154
79e53945
JB		 6155static void intel_setup_outputs(struct drm_device *dev)
6156{
725e30ad 6157 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6158 struct intel_encoder *encoder;
cb0953d7 6159 bool dpd_is_edp = false;
f3cfcba6 6160 bool has_lvds;
79e53945 6161
f3cfcba6 6162 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6163 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6164 /* disable the panel fitter on everything but LVDS */
6165 I915_WRITE(PFIT_CONTROL, 0);
6166 }
79e53945 6167
bad720ff 6168 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6169 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6170
4d302442 6171 if (has_edp_a(dev))
32f9d658
ZW		 6172 intel_dp_init(dev, DP_A);
6173
cb0953d7
AJ		 6174 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6175 intel_dp_init(dev, PCH_DP_D);
6176 }
6177
6178 intel_crt_init(dev);
6179
6180 if (HAS_PCH_SPLIT(dev)) {
6181 int found;
6182
30ad48b7 6183 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6184 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6185 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6186 if (!found)
6187 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6188 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6189 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6190 }
6191
6192 if (I915_READ(HDMIC) & PORT_DETECTED)
6193 intel_hdmi_init(dev, HDMIC);
6194
6195 if (I915_READ(HDMID) & PORT_DETECTED)
6196 intel_hdmi_init(dev, HDMID);
6197
5eb08b69
ZW		 6198 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6199 intel_dp_init(dev, PCH_DP_C);
6200
cb0953d7 6201 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6202 intel_dp_init(dev, PCH_DP_D);
6203
103a196f 6204 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6205 bool found = false;
7d57382e 6206
725e30ad 6207 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6208 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6209 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6210 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6211 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6212 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6213 }
27185ae1 6214
b01f2c3a
JB		 6215 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6216 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6217 intel_dp_init(dev, DP_B);
b01f2c3a 6218 }
725e30ad 6219 }
13520b05
KH		 6220
6221 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6222
b01f2c3a
JB		 6223 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6224 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6225 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6226 }
27185ae1
ML		 6227
6228 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6229
b01f2c3a
JB		 6230 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6231 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6232 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6233 }
6234 if (SUPPORTS_INTEGRATED_DP(dev)) {
6235 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6236 intel_dp_init(dev, DP_C);
b01f2c3a 6237 }
725e30ad 6238 }
27185ae1 6239
b01f2c3a
JB		 6240 if (SUPPORTS_INTEGRATED_DP(dev) &&
6241 (I915_READ(DP_D) & DP_DETECTED)) {
6242 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6243 intel_dp_init(dev, DP_D);
b01f2c3a 6244 }
bad720ff 6245 } else if (IS_GEN2(dev))
79e53945
JB		 6246 intel_dvo_init(dev);
6247
103a196f 6248 if (SUPPORTS_TV(dev))
79e53945
JB		 6249 intel_tv_init(dev);
6250
4ef69c7a
CW		 6251 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6252 encoder->base.possible_crtcs = encoder->crtc_mask;
6253 encoder->base.possible_clones =
6254 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6255 }
47356eb6 6256
2c7111db
CW		 6257 /* disable all the possible outputs/crtcs before entering KMS mode */
6258 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6259
6260 if (HAS_PCH_SPLIT(dev))
6261 ironlake_init_pch_refclk(dev);
79e53945
JB		 6262}
6263
6264static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6265{
6266 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6267
6268 drm_framebuffer_cleanup(fb);
05394f39 6269 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6270
6271 kfree(intel_fb);
6272}
6273
6274static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6275 struct drm_file *file,
79e53945
JB		 6276 unsigned int *handle)
6277{
6278 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6279 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6280
05394f39 6281 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6282}
6283
6284static const struct drm_framebuffer_funcs intel_fb_funcs = {
6285 .destroy = intel_user_framebuffer_destroy,
6286 .create_handle = intel_user_framebuffer_create_handle,
6287};
6288
38651674
DA		 6289int intel_framebuffer_init(struct drm_device *dev,
6290 struct intel_framebuffer *intel_fb,
308e5bcb 6291 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6292 struct drm_i915_gem_object *obj)
79e53945 6293{
79e53945
JB		 6294 int ret;
6295
05394f39 6296 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6297 return -EINVAL;
6298
308e5bcb 6299 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6300 return -EINVAL;
6301
308e5bcb 6302 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6303 case DRM_FORMAT_RGB332:
6304 case DRM_FORMAT_RGB565:
6305 case DRM_FORMAT_XRGB8888:
b250da79 6306 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6307 case DRM_FORMAT_ARGB8888:
6308 case DRM_FORMAT_XRGB2101010:
6309 case DRM_FORMAT_ARGB2101010:
308e5bcb 6310 /* RGB formats are common across chipsets */
b5626747 6311 break;
04b3924d
VS		 6312 case DRM_FORMAT_YUYV:
6313 case DRM_FORMAT_UYVY:
6314 case DRM_FORMAT_YVYU:
6315 case DRM_FORMAT_VYUY:
57cd6508
CW		 6316 break;
6317 default:
aca25848
ED		 6318 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6319 mode_cmd->pixel_format);
57cd6508
CW		 6320 return -EINVAL;
6321 }
6322
79e53945
JB		 6323 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6324 if (ret) {
6325 DRM_ERROR("framebuffer init failed %d\n", ret);
6326 return ret;
6327 }
6328
6329 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6330 intel_fb->obj = obj;
79e53945
JB		 6331 return 0;
6332}
6333
79e53945
JB		 6334static struct drm_framebuffer *
6335intel_user_framebuffer_create(struct drm_device *dev,
6336 struct drm_file *filp,
308e5bcb 6337 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6338{
05394f39 6339 struct drm_i915_gem_object *obj;
79e53945 6340
308e5bcb
JB		 6341 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6342 mode_cmd->handles[0]));
c8725226 6343 if (&obj->base == NULL)
cce13ff7 6344 return ERR_PTR(-ENOENT);
79e53945 6345
d2dff872 6346 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6347}
6348
79e53945 6349static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6350 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6351 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6352};
6353
e70236a8
JB		 6354/* Set up chip specific display functions */
6355static void intel_init_display(struct drm_device *dev)
6356{
6357 struct drm_i915_private *dev_priv = dev->dev_private;
6358
6359 /* We always want a DPMS function */
f564048e 6360 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6361 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6362 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 6363 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6364 } else {
e70236a8 6365 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6366 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 6367 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6368 }
e70236a8 6369
ee5382ae 6370 if (I915_HAS_FBC(dev)) {
9c04f015 6371 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 6372 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6373 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6374 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6375 } else if (IS_GM45(dev)) {
74dff282
JB		 6376 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6377 dev_priv->display.enable_fbc = g4x_enable_fbc;
6378 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 6379 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 6380 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6381 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6382 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6383 }
74dff282 6384 /* 855GM needs testing */
e70236a8
JB		 6385 }
6386
6387 /* Returns the core display clock speed */
25eb05fc
JB		 6388 if (IS_VALLEYVIEW(dev))
6389 dev_priv->display.get_display_clock_speed =
6390 valleyview_get_display_clock_speed;
6391 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6392 dev_priv->display.get_display_clock_speed =
6393 i945_get_display_clock_speed;
6394 else if (IS_I915G(dev))
6395 dev_priv->display.get_display_clock_speed =
6396 i915_get_display_clock_speed;
f2b115e6 6397 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6398 dev_priv->display.get_display_clock_speed =
6399 i9xx_misc_get_display_clock_speed;
6400 else if (IS_I915GM(dev))
6401 dev_priv->display.get_display_clock_speed =
6402 i915gm_get_display_clock_speed;
6403 else if (IS_I865G(dev))
6404 dev_priv->display.get_display_clock_speed =
6405 i865_get_display_clock_speed;
f0f8a9ce 6406 else if (IS_I85X(dev))
e70236a8
JB		 6407 dev_priv->display.get_display_clock_speed =
6408 i855_get_display_clock_speed;
6409 else /* 852, 830 */
6410 dev_priv->display.get_display_clock_speed =
6411 i830_get_display_clock_speed;
6412
6413 /* For FIFO watermark updates */
7f8a8569 6414 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 6415 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
6416 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
6417
6418 /* IVB configs may use multi-threaded forcewake */
246bdbeb 6419 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
8d715f00
KP		 6420 u32 ecobus;
6421
c7dffff7
KP		 6422 /* A small trick here - if the bios hasn't configured MT forcewake,
6423 * and if the device is in RC6, then force_wake_mt_get will not wake
6424 * the device and the ECOBUS read will return zero. Which will be
6425 * (correctly) interpreted by the test below as MT forcewake being
6426 * disabled.
6427 */
8d715f00
KP		 6428 mutex_lock(&dev->struct_mutex);
6429 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 6430 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 6431 __gen6_gt_force_wake_mt_put(dev_priv);
6432 mutex_unlock(&dev->struct_mutex);
6433
6434 if (ecobus & FORCEWAKE_MT_ENABLE) {
6435 DRM_DEBUG_KMS("Using MT version of forcewake\n");
6436 dev_priv->display.force_wake_get =
6437 __gen6_gt_force_wake_mt_get;
6438 dev_priv->display.force_wake_put =
6439 __gen6_gt_force_wake_mt_put;
6440 }
6441 }
6442
645c62a5
JB		 6443 if (HAS_PCH_IBX(dev))
6444 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
6445 else if (HAS_PCH_CPT(dev))
6446 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
6447
f00a3ddf 6448 if (IS_GEN5(dev)) {
7f8a8569
ZW		 6449 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6450 dev_priv->display.update_wm = ironlake_update_wm;
6451 else {
6452 DRM_DEBUG_KMS("Failed to get proper latency. "
6453 "Disable CxSR\n");
6454 dev_priv->display.update_wm = NULL;
1398261a 6455 }
674cf967 6456 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 6457 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 6458 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 6459 } else if (IS_GEN6(dev)) {
6460 if (SNB_READ_WM0_LATENCY()) {
6461 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 6462 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 6463 } else {
6464 DRM_DEBUG_KMS("Failed to read display plane latency. "
6465 "Disable CxSR\n");
6466 dev_priv->display.update_wm = NULL;
7f8a8569 6467 }
674cf967 6468 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 6469 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 6470 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6471 } else if (IS_IVYBRIDGE(dev)) {
6472 /* FIXME: detect B0+ stepping and use auto training */
6473 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 6474 if (SNB_READ_WM0_LATENCY()) {
6475 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 6476 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 6477 } else {
6478 DRM_DEBUG_KMS("Failed to read display plane latency. "
6479 "Disable CxSR\n");
6480 dev_priv->display.update_wm = NULL;
6481 }
28963a3e 6482 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 6483 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6484 } else
6485 dev_priv->display.update_wm = NULL;
ceb04246
JB		 6486 } else if (IS_VALLEYVIEW(dev)) {
6487 dev_priv->display.update_wm = valleyview_update_wm;
fb046853
JB		 6488 dev_priv->display.init_clock_gating =
6489 valleyview_init_clock_gating;
575155a9
JB		 6490 dev_priv->display.force_wake_get = vlv_force_wake_get;
6491 dev_priv->display.force_wake_put = vlv_force_wake_put;
7f8a8569 6492 } else if (IS_PINEVIEW(dev)) {
d4294342 6493 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 6494 dev_priv->is_ddr3,
d4294342
ZY		 6495 dev_priv->fsb_freq,
6496 dev_priv->mem_freq)) {
6497 DRM_INFO("failed to find known CxSR latency "
95534263 6498 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 6499 "disabling CxSR\n",
0206e353 6500 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 6501 dev_priv->fsb_freq, dev_priv->mem_freq);
6502 /* Disable CxSR and never update its watermark again */
6503 pineview_disable_cxsr(dev);
6504 dev_priv->display.update_wm = NULL;
6505 } else
6506 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 6507 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 6508 } else if (IS_G4X(dev)) {
e0dac65e 6509 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6510 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 6511 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6512 } else if (IS_GEN4(dev)) {
e70236a8 6513 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 6514 if (IS_CRESTLINE(dev))
6515 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6516 else if (IS_BROADWATER(dev))
6517 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6518 } else if (IS_GEN3(dev)) {
e70236a8
JB		 6519 dev_priv->display.update_wm = i9xx_update_wm;
6520 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 6521 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6522 } else if (IS_I865G(dev)) {
6523 dev_priv->display.update_wm = i830_update_wm;
6524 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6525 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 6526 } else if (IS_I85X(dev)) {
6527 dev_priv->display.update_wm = i9xx_update_wm;
6528 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 6529 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 6530 } else {
8f4695ed 6531 dev_priv->display.update_wm = i830_update_wm;
6067aaea 6532 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 6533 if (IS_845G(dev))
e70236a8
JB		 6534 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6535 else
6536 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 6537 }
8c9f3aaf
JB		 6538
6539 /* Default just returns -ENODEV to indicate unsupported */
6540 dev_priv->display.queue_flip = intel_default_queue_flip;
6541
6542 switch (INTEL_INFO(dev)->gen) {
6543 case 2:
6544 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6545 break;
6546
6547 case 3:
6548 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6549 break;
6550
6551 case 4:
6552 case 5:
6553 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6554 break;
6555
6556 case 6:
6557 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6558 break;
7c9017e5
JB		 6559 case 7:
6560 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6561 break;
8c9f3aaf 6562 }
e70236a8
JB		 6563}
6564
b690e96c
JB		 6565/*
6566 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6567 * resume, or other times. This quirk makes sure that's the case for
6568 * affected systems.
6569 */
0206e353 6570static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6571{
6572 struct drm_i915_private *dev_priv = dev->dev_private;
6573
6574 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6575 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6576}
6577
435793df
KP		 6578/*
6579 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6580 */
6581static void quirk_ssc_force_disable(struct drm_device *dev)
6582{
6583 struct drm_i915_private *dev_priv = dev->dev_private;
6584 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6585 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6586}
6587
4dca20ef 6588/*
5a15ab5b
CE		 6589 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6590 * brightness value
4dca20ef
CE		 6591 */
6592static void quirk_invert_brightness(struct drm_device *dev)
6593{
6594 struct drm_i915_private *dev_priv = dev->dev_private;
6595 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6596 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6597}
6598
b690e96c
JB		 6599struct intel_quirk {
6600 int device;
6601 int subsystem_vendor;
6602 int subsystem_device;
6603 void (*hook)(struct drm_device *dev);
6604};
6605
c43b5634 6606static struct intel_quirk intel_quirks[] = {
b690e96c 6607 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6608 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6609
6610 /* Thinkpad R31 needs pipe A force quirk */
6611 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6612 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6613 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6614
6615 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6616 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6617 /* ThinkPad X40 needs pipe A force quirk */
6618
6619 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6620 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6621
6622 /* 855 & before need to leave pipe A & dpll A up */
6623 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6624 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6625
6626 /* Lenovo U160 cannot use SSC on LVDS */
6627 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6628
6629 /* Sony Vaio Y cannot use SSC on LVDS */
6630 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6631
6632 /* Acer Aspire 5734Z must invert backlight brightness */
6633 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6634};
6635
6636static void intel_init_quirks(struct drm_device *dev)
6637{
6638 struct pci_dev *d = dev->pdev;
6639 int i;
6640
6641 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6642 struct intel_quirk *q = &intel_quirks[i];
6643
6644 if (d->device == q->device &&
6645 (d->subsystem_vendor == q->subsystem_vendor ||
6646 q->subsystem_vendor == PCI_ANY_ID) &&
6647 (d->subsystem_device == q->subsystem_device ||
6648 q->subsystem_device == PCI_ANY_ID))
6649 q->hook(dev);
6650 }
6651}
6652
9cce37f4
JB		 6653/* Disable the VGA plane that we never use */
6654static void i915_disable_vga(struct drm_device *dev)
6655{
6656 struct drm_i915_private *dev_priv = dev->dev_private;
6657 u8 sr1;
6658 u32 vga_reg;
6659
6660 if (HAS_PCH_SPLIT(dev))
6661 vga_reg = CPU_VGACNTRL;
6662 else
6663 vga_reg = VGACNTRL;
6664
6665 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6666 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6667 sr1 = inb(VGA_SR_DATA);
6668 outb(sr1 | 1<<5, VGA_SR_DATA);
6669 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6670 udelay(300);
6671
6672 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6673 POSTING_READ(vga_reg);
6674}
6675
f82cfb6b
JB		 6676static void ivb_pch_pwm_override(struct drm_device *dev)
6677{
6678 struct drm_i915_private *dev_priv = dev->dev_private;
6679
6680 /*
6681 * IVB has CPU eDP backlight regs too, set things up to let the
6682 * PCH regs control the backlight
6683 */
6684 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6685 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6686 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6687}
6688
f817586c
DV		 6689void intel_modeset_init_hw(struct drm_device *dev)
6690{
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692
6693 intel_init_clock_gating(dev);
6694
6695 if (IS_IRONLAKE_M(dev)) {
6696 ironlake_enable_drps(dev);
6697 intel_init_emon(dev);
6698 }
6699
b6834bd6 6700 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6701 gen6_enable_rps(dev_priv);
6702 gen6_update_ring_freq(dev_priv);
6703 }
f82cfb6b
JB		 6704
6705 if (IS_IVYBRIDGE(dev))
6706 ivb_pch_pwm_override(dev);
f817586c
DV		 6707}
6708
79e53945
JB		 6709void intel_modeset_init(struct drm_device *dev)
6710{
652c393a 6711 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6712 int i, ret;
79e53945
JB		 6713
6714 drm_mode_config_init(dev);
6715
6716 dev->mode_config.min_width = 0;
6717 dev->mode_config.min_height = 0;
6718
019d96cb
DA		 6719 dev->mode_config.preferred_depth = 24;
6720 dev->mode_config.prefer_shadow = 1;
6721
79e53945
JB		 6722 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6723
b690e96c
JB		 6724 intel_init_quirks(dev);
6725
e70236a8
JB		 6726 intel_init_display(dev);
6727
a6c45cf0
CW		 6728 if (IS_GEN2(dev)) {
6729 dev->mode_config.max_width = 2048;
6730 dev->mode_config.max_height = 2048;
6731 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6732 dev->mode_config.max_width = 4096;
6733 dev->mode_config.max_height = 4096;
79e53945 6734 } else {
a6c45cf0
CW		 6735 dev->mode_config.max_width = 8192;
6736 dev->mode_config.max_height = 8192;
79e53945 6737 }
35c3047a 6738 dev->mode_config.fb_base = dev->agp->base;
79e53945 6739
28c97730 6740 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6741 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6742
a3524f1b 6743 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6744 intel_crtc_init(dev, i);
00c2064b
JB		 6745 ret = intel_plane_init(dev, i);
6746 if (ret)
6747 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6748 }
6749
9cce37f4
JB		 6750 /* Just disable it once at startup */
6751 i915_disable_vga(dev);
79e53945 6752 intel_setup_outputs(dev);
652c393a 6753
f817586c 6754 intel_modeset_init_hw(dev);
3b8d8d91 6755
652c393a
JB		 6756 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6757 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6758 (unsigned long)dev);
2c7111db
CW		 6759}
6760
6761void intel_modeset_gem_init(struct drm_device *dev)
6762{
6763 if (IS_IRONLAKE_M(dev))
6764 ironlake_enable_rc6(dev);
02e792fb
DV		 6765
6766 intel_setup_overlay(dev);
79e53945
JB		 6767}
6768
6769void intel_modeset_cleanup(struct drm_device *dev)
6770{
652c393a
JB		 6771 struct drm_i915_private *dev_priv = dev->dev_private;
6772 struct drm_crtc *crtc;
6773 struct intel_crtc *intel_crtc;
6774
f87ea761 6775 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6776 mutex_lock(&dev->struct_mutex);
6777
723bfd70
JB		 6778 intel_unregister_dsm_handler();
6779
6780
652c393a
JB		 6781 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6782 /* Skip inactive CRTCs */
6783 if (!crtc->fb)
6784 continue;
6785
6786 intel_crtc = to_intel_crtc(crtc);
3dec0095 6787 intel_increase_pllclock(crtc);
652c393a
JB		 6788 }
6789
973d04f9 6790 intel_disable_fbc(dev);
e70236a8 6791
f97108d1
JB		 6792 if (IS_IRONLAKE_M(dev))
6793 ironlake_disable_drps(dev);
b6834bd6 6794 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 6795 gen6_disable_rps(dev);
f97108d1 6796
d5bb081b
JB		 6797 if (IS_IRONLAKE_M(dev))
6798 ironlake_disable_rc6(dev);
0cdab21f 6799
57f350b6
JB		 6800 if (IS_VALLEYVIEW(dev))
6801 vlv_init_dpio(dev);
6802
69341a5e
KH		 6803 mutex_unlock(&dev->struct_mutex);
6804
6c0d9350
DV		 6805 /* Disable the irq before mode object teardown, for the irq might
6806 * enqueue unpin/hotplug work. */
6807 drm_irq_uninstall(dev);
6808 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 6809 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 6810
1630fe75
CW		 6811 /* flush any delayed tasks or pending work */
6812 flush_scheduled_work();
6813
3dec0095
DV		 6814 /* Shut off idle work before the crtcs get freed. */
6815 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6816 intel_crtc = to_intel_crtc(crtc);
6817 del_timer_sync(&intel_crtc->idle_timer);
6818 }
6819 del_timer_sync(&dev_priv->idle_timer);
6820 cancel_work_sync(&dev_priv->idle_work);
6821
79e53945
JB		 6822 drm_mode_config_cleanup(dev);
6823}
6824
f1c79df3
ZW		 6825/*
6826 * Return which encoder is currently attached for connector.
6827 */
df0e9248 6828struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 6829{
df0e9248
CW		 6830 return &intel_attached_encoder(connector)->base;
6831}
f1c79df3 6832
df0e9248
CW		 6833void intel_connector_attach_encoder(struct intel_connector *connector,
6834 struct intel_encoder *encoder)
6835{
6836 connector->encoder = encoder;
6837 drm_mode_connector_attach_encoder(&connector->base,
6838 &encoder->base);
79e53945 6839}
28d52043
DA		 6840
6841/*
6842 * set vga decode state - true == enable VGA decode
6843 */
6844int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6845{
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 u16 gmch_ctrl;
6848
6849 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6850 if (state)
6851 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6852 else
6853 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6854 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6855 return 0;
6856}
c4a1d9e4
CW		 6857
6858#ifdef CONFIG_DEBUG_FS
6859#include <linux/seq_file.h>
6860
6861struct intel_display_error_state {
6862 struct intel_cursor_error_state {
6863 u32 control;
6864 u32 position;
6865 u32 base;
6866 u32 size;
6867 } cursor[2];
6868
6869 struct intel_pipe_error_state {
6870 u32 conf;
6871 u32 source;
6872
6873 u32 htotal;
6874 u32 hblank;
6875 u32 hsync;
6876 u32 vtotal;
6877 u32 vblank;
6878 u32 vsync;
6879 } pipe[2];
6880
6881 struct intel_plane_error_state {
6882 u32 control;
6883 u32 stride;
6884 u32 size;
6885 u32 pos;
6886 u32 addr;
6887 u32 surface;
6888 u32 tile_offset;
6889 } plane[2];
6890};
6891
6892struct intel_display_error_state *
6893intel_display_capture_error_state(struct drm_device *dev)
6894{
0206e353 6895 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 6896 struct intel_display_error_state *error;
6897 int i;
6898
6899 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6900 if (error == NULL)
6901 return NULL;
6902
6903 for (i = 0; i < 2; i++) {
6904 error->cursor[i].control = I915_READ(CURCNTR(i));
6905 error->cursor[i].position = I915_READ(CURPOS(i));
6906 error->cursor[i].base = I915_READ(CURBASE(i));
6907
6908 error->plane[i].control = I915_READ(DSPCNTR(i));
6909 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6910 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 6911 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 6912 error->plane[i].addr = I915_READ(DSPADDR(i));
6913 if (INTEL_INFO(dev)->gen >= 4) {
6914 error->plane[i].surface = I915_READ(DSPSURF(i));
6915 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6916 }
6917
6918 error->pipe[i].conf = I915_READ(PIPECONF(i));
6919 error->pipe[i].source = I915_READ(PIPESRC(i));
6920 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6921 error->pipe[i].hblank = I915_READ(HBLANK(i));
6922 error->pipe[i].hsync = I915_READ(HSYNC(i));
6923 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6924 error->pipe[i].vblank = I915_READ(VBLANK(i));
6925 error->pipe[i].vsync = I915_READ(VSYNC(i));
6926 }
6927
6928 return error;
6929}
6930
6931void
6932intel_display_print_error_state(struct seq_file *m,
6933 struct drm_device *dev,
6934 struct intel_display_error_state *error)
6935{
6936 int i;
6937
6938 for (i = 0; i < 2; i++) {
6939 seq_printf(m, "Pipe [%d]:\n", i);
6940 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6941 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6942 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6943 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6944 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6945 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6946 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6947 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6948
6949 seq_printf(m, "Plane [%d]:\n", i);
6950 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6951 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6952 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6953 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6954 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6955 if (INTEL_INFO(dev)->gen >= 4) {
6956 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6957 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6958 }
6959
6960 seq_printf(m, "Cursor [%d]:\n", i);
6961 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6962 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6963 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6964 }
6965}
6966#endif
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