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drm/i915: drop adjusted_mode from *_set_pipeconf functions
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
1b894b59
CW		 688
689 this_err = abs(clock.dot - target);
d4906093
ML		 690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
2c07245f
ZW		 700 return found;
701}
702
a0c4da24
JB		 703static bool
704intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707{
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
af447bd3 714 flag = 0;
a0c4da24
JB		 715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770}
a4fc5ed6 771
a5c961d1
PZ		 772enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774{
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
3b117c8f 778 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 779}
780
a928d536
PZ		 781static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790}
791
9d0498a2
JB		 792/**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 801{
9d0498a2 802 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 803 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 804
a928d536
PZ		 805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
300387c0
CW		 810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
9d0498a2 826 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
9d0498a2
JB		 830 DRM_DEBUG_KMS("vblank wait timed out\n");
831}
832
ab7ad7f6
KP		 833/*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
ab7ad7f6
KP		 842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
58e10eb9 848 *
9d0498a2 849 */
58e10eb9 850void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
ab7ad7f6
KP		 855
856 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 857 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 858
859 /* Wait for the Pipe State to go off */
58e10eb9
CW		 860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 } else {
837ba00f 864 u32 last_line, line_mask;
58e10eb9 865 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
837ba00f
PZ		 868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
ab7ad7f6
KP		 873 /* Wait for the display line to settle */
874 do {
837ba00f 875 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 876 mdelay(5);
837ba00f 877 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
284637d9 880 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 881 }
79e53945
JB		 882}
883
b0ea7d37
DL		 884/*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893{
894 u32 bit;
895
c36346e3
DL		 896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
b0ea7d37
DL		 924 }
925
926 return I915_READ(SDEISR) & bit;
927}
928
b24e7179
JB		 929static const char *state_string(bool enabled)
930{
931 return enabled ? "on" : "off";
932}
933
934/* Only for pre-ILK configs */
935static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937{
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948}
949#define assert_pll_enabled(d, p) assert_pll(d, p, true)
950#define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
040484af
JB		 952/* For ILK+ */
953static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
040484af 957{
040484af
JB		 958 u32 val;
959 bool cur_state;
960
9d82aa17
ED		 961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
92b27b08
CW		 966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 968 return;
ee7b9f93 969
92b27b08
CW		 970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
4bb6f1f3 987 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
4bb6f1f3 990 pipe_name(crtc->pipe),
92b27b08
CW		 991 val);
992 }
d3ccbe86 993 }
040484af 994}
92b27b08
CW		 995#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 997
998static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
ad80a810
PZ		 1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
040484af 1006
affa9354
PZ		 1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
ad80a810 1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1010 val = I915_READ(reg);
ad80a810 1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
040484af
JB		 1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020}
1021#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026{
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
d63fa0dc
PZ		 1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
bf507ef7 1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1052 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1053 return;
1054
040484af
JB		 1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058}
1059
1060static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069}
1070
ea0760cf
JB		 1071static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073{
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
0de3b485 1077 bool locked = true;
ea0760cf
JB		 1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1097 pipe_name(pipe));
ea0760cf
JB		 1098}
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
15d199ea
PZ		 1113 if (!intel_using_power_well(dev_priv->dev) &&
1114 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
19ec1358 1152 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
19ec1358 1159 return;
28c05794 1160 }
19ec1358 1161
b24e7179
JB		 1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1171 }
1172}
1173
19332d7a
JB		 1174static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176{
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
06da8da2
VS		 1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1190 }
1191}
1192
92f2584a
JB		 1193static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194{
1195 u32 val;
1196 bool enabled;
1197
9d82aa17
ED		 1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
92f2584a
JB		 1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207}
1208
1209static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
1216 reg = TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
92f2584a
JB		 1222}
1223
4e634389
KP		 1224static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1226{
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240}
1241
1519b995
KP		 1242static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
dc0fa718 1245 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1250 return false;
1251 } else {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272}
1273
1274static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276{
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
291906f1 1289static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1290 enum pipe pipe, int reg, u32 port_sel)
291906f1 1291{
47a05eca 1292 u32 val = I915_READ(reg);
4e634389 1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 reg, pipe_name(pipe));
de9a35ab 1296
75c5da27
DV		 1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
de9a35ab 1299 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1300}
1301
1302static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304{
47a05eca 1305 u32 val = I915_READ(reg);
b70ad586 1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
dc0fa718 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1311 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1312 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
1318 int reg;
1319 u32 val;
291906f1 1320
f0575e92
KP		 1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1
JB		 1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
b70ad586 1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1335 pipe_name(pipe));
291906f1 1336
e2debe91
PZ		 1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1340}
1341
63d7bbe9
JB		 1342/**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
7434a255
TR		 1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1354 */
1355static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356{
1357 int reg;
1358 u32 val;
1359
58c6eaa2
DV		 1360 assert_pipe_disabled(dev_priv, pipe);
1361
63d7bbe9 1362 /* No really, not for ILK+ */
a0c4da24 1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
a416edef
ED		 1413/* SBI access */
1414static void
988d6ee8
PZ		 1415intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
a416edef 1417{
988d6ee8 1418 u32 tmp;
a416edef 1419
09153000 1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1421
39fb50f6 1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1425 return;
a416edef
ED		 1426 }
1427
988d6ee8
PZ		 1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1436
39fb50f6 1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1440 return;
a416edef 1441 }
a416edef
ED		 1442}
1443
1444static u32
988d6ee8
PZ		 1445intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
a416edef 1447{
39fb50f6 1448 u32 value = 0;
09153000 1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1450
39fb50f6 1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1454 return 0;
a416edef
ED		 1455 }
1456
988d6ee8
PZ		 1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1464
39fb50f6 1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1468 return 0;
a416edef
ED		 1469 }
1470
09153000 1471 return I915_READ(SBI_DATA);
a416edef
ED		 1472}
1473
89b667f8
JB		 1474void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475{
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486}
1487
92f2584a 1488/**
b6b4e185 1489 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
b6b4e185 1496static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1497{
ee7b9f93 1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1499 struct intel_pch_pll *pll;
92f2584a
JB		 1500 int reg;
1501 u32 val;
1502
48da64a8 1503 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1504 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
ee7b9f93
JB		 1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
92f2584a
JB		 1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
ee7b9f93 1519 if (pll->active++ && pll->on) {
92b27b08 1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = true;
92f2584a
JB		 1534}
1535
ee7b9f93 1536static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1537{
ee7b9f93
JB		 1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1540 int reg;
ee7b9f93 1541 u32 val;
4c609cb8 1542
92f2584a
JB		 1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1545 if (pll == NULL)
1546 return;
92f2584a 1547
48da64a8
CW		 1548 if (WARN_ON(pll->refcount == 0))
1549 return;
7a419866 1550
ee7b9f93
JB		 1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
7a419866 1554
48da64a8 1555 if (WARN_ON(pll->active == 0)) {
92b27b08 1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1557 return;
1558 }
1559
ee7b9f93 1560 if (--pll->active) {
92b27b08 1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1562 return;
ee7b9f93
JB		 1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1569
ee7b9f93 1570 reg = pll->pll_reg;
92f2584a
JB		 1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
ee7b9f93
JB		 1576
1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1585 uint32_t reg, val, pipeconf_val;
040484af
JB		 1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
040484af
JB		 1608 reg = TRANSCONF(pipe);
1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
25f3ef11 1662 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1663 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
040484af
JB		 1680 reg = TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
8a52fd9f 1701 val = I915_READ(_TRANSACONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
8a52fd9f 1703 I915_WRITE(_TRANSACONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1705 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af
JB		 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2
DV		 1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
681e5811 1740 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
b24e7179
JB		 1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
cc391bbb 1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
040484af
JB		 1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
b24e7179 1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
1771/**
309cfea8 1772 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
b24e7179
JB		 1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
5eddb70b 2050 I915_WRITE(reg, dspcntr);
81255565 2051
e506a0c6 2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2053
c2c75131
DV		 2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
bc752862
CW		 2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
c2c75131
DV		 2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
e506a0c6 2061 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2062 }
e506a0c6
DV		 2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2067 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2072 } else
e506a0c6 2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2074 POSTING_READ(reg);
81255565 2075
17638cd6
JB		 2076 return 0;
2077}
2078
2079static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
17638cd6
JB		 2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
27f8227b 2095 case 2:
17638cd6
JB		 2096 break;
2097 default:
84f44ce7 2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
17638cd6
JB		 2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
17638cd6
JB		 2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
e506a0c6 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2147 intel_crtc->dspaddr_offset =
bc752862
CW		 2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
c2c75131 2151 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2152
e506a0c6
DV		 2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
17638cd6
JB		 2164 POSTING_READ(reg);
2165
2166 return 0;
2167}
2168
2169/* Assume fb object is pinned & idle & fenced and just update base pointers */
2170static int
2171intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2176
6b8e6ed0
CW		 2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
3dec0095 2179 intel_increase_pllclock(crtc);
81255565 2180
6b8e6ed0 2181 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2182}
2183
96a02917
VS		 2184void intel_display_handle_reset(struct drm_device *dev)
2185{
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220}
2221
14667a4b
CW		 2222static int
2223intel_finish_fb(struct drm_framebuffer *old_fb)
2224{
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
14667a4b
CW		 2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243}
2244
198598d0
VS		 2245static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246{
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270}
2271
5c3b82e2 2272static int
3c4fdcfb 2273intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2274 struct drm_framebuffer *fb)
79e53945
JB		 2275{
2276 struct drm_device *dev = crtc->dev;
6b8e6ed0 2277 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2279 struct drm_framebuffer *old_fb;
5c3b82e2 2280 int ret;
79e53945
JB		 2281
2282 /* no fb bound */
94352cf9 2283 if (!fb) {
a5071c2f 2284 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2285 return 0;
2286 }
2287
7eb552ae 2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2292 return -EINVAL;
79e53945
JB		 2293 }
2294
5c3b82e2 2295 mutex_lock(&dev->struct_mutex);
265db958 2296 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2297 to_intel_framebuffer(fb)->obj,
919926ae 2298 NULL);
5c3b82e2
CW		 2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2302 return ret;
2303 }
79e53945 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
01a415fd
DV		 2372static void ivb_modeset_global_resources(struct drm_device *dev)
2373{
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *pipe_B_crtc =
2376 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2377 struct intel_crtc *pipe_C_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2379 uint32_t temp;
2380
2381 /* When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. XXX: This misses the case where a pipe is not using
2383 * any pch resources and so doesn't need any fdi lanes. */
2384 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2386 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2387
2388 temp = I915_READ(SOUTH_CHICKEN1);
2389 temp &= ~FDI_BC_BIFURCATION_SELECT;
2390 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391 I915_WRITE(SOUTH_CHICKEN1, temp);
2392 }
2393}
2394
8db9d77b
ZW		 2395/* The FDI link training functions for ILK/Ibexpeak. */
2396static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2397{
2398 struct drm_device *dev = crtc->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401 int pipe = intel_crtc->pipe;
0fc932b8 2402 int plane = intel_crtc->plane;
5eddb70b 2403 u32 reg, temp, tries;
8db9d77b 2404
0fc932b8
JB		 2405 /* FDI needs bits from pipe & plane first */
2406 assert_pipe_enabled(dev_priv, pipe);
2407 assert_plane_enabled(dev_priv, plane);
2408
e1a44743
AJ		 2409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2410 for train result */
5eddb70b
CW		 2411 reg = FDI_RX_IMR(pipe);
2412 temp = I915_READ(reg);
e1a44743
AJ		 2413 temp &= ~FDI_RX_SYMBOL_LOCK;
2414 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2415 I915_WRITE(reg, temp);
2416 I915_READ(reg);
e1a44743
AJ		 2417 udelay(150);
2418
8db9d77b 2419 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2420 reg = FDI_TX_CTL(pipe);
2421 temp = I915_READ(reg);
77ffb597
AJ		 2422 temp &= ~(7 << 19);
2423 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2426 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2427
5eddb70b
CW		 2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2432 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2433
2434 POSTING_READ(reg);
8db9d77b
ZW		 2435 udelay(150);
2436
5b2adf89 2437 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2439 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2440 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2441
5eddb70b 2442 reg = FDI_RX_IIR(pipe);
e1a44743 2443 for (tries = 0; tries < 5; tries++) {
5eddb70b 2444 temp = I915_READ(reg);
8db9d77b
ZW		 2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446
2447 if ((temp & FDI_RX_BIT_LOCK)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2449 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2450 break;
2451 }
8db9d77b 2452 }
e1a44743 2453 if (tries == 5)
5eddb70b 2454 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2455
2456 /* Train 2 */
5eddb70b
CW		 2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
8db9d77b
ZW		 2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2461 I915_WRITE(reg, temp);
8db9d77b 2462
5eddb70b
CW		 2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
8db9d77b
ZW		 2465 temp &= ~FDI_LINK_TRAIN_NONE;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2467 I915_WRITE(reg, temp);
8db9d77b 2468
5eddb70b
CW		 2469 POSTING_READ(reg);
2470 udelay(150);
8db9d77b 2471
5eddb70b 2472 reg = FDI_RX_IIR(pipe);
e1a44743 2473 for (tries = 0; tries < 5; tries++) {
5eddb70b 2474 temp = I915_READ(reg);
8db9d77b
ZW		 2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476
2477 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2478 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2480 break;
2481 }
8db9d77b 2482 }
e1a44743 2483 if (tries == 5)
5eddb70b 2484 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2485
2486 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2487
8db9d77b
ZW		 2488}
2489
0206e353 2490static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2495};
2496
2497/* The FDI link training functions for SNB/Cougarpoint. */
2498static void gen6_fdi_link_train(struct drm_crtc *crtc)
2499{
2500 struct drm_device *dev = crtc->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 int pipe = intel_crtc->pipe;
fa37d39e 2504 u32 reg, temp, i, retry;
8db9d77b 2505
e1a44743
AJ		 2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507 for train result */
5eddb70b
CW		 2508 reg = FDI_RX_IMR(pipe);
2509 temp = I915_READ(reg);
e1a44743
AJ		 2510 temp &= ~FDI_RX_SYMBOL_LOCK;
2511 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597
AJ		 2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 /* SNB-B */
2526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2527 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2528
d74cf324
DV		 2529 I915_WRITE(FDI_RX_MISC(pipe),
2530 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2531
5eddb70b
CW		 2532 reg = FDI_RX_CTL(pipe);
2533 temp = I915_READ(reg);
8db9d77b
ZW		 2534 if (HAS_PCH_CPT(dev)) {
2535 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2537 } else {
2538 temp &= ~FDI_LINK_TRAIN_NONE;
2539 temp |= FDI_LINK_TRAIN_PATTERN_1;
2540 }
5eddb70b
CW		 2541 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2542
2543 POSTING_READ(reg);
8db9d77b
ZW		 2544 udelay(150);
2545
0206e353 2546 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2551 I915_WRITE(reg, temp);
2552
2553 POSTING_READ(reg);
8db9d77b
ZW		 2554 udelay(500);
2555
fa37d39e
SP		 2556 for (retry = 0; retry < 5; retry++) {
2557 reg = FDI_RX_IIR(pipe);
2558 temp = I915_READ(reg);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2560 if (temp & FDI_RX_BIT_LOCK) {
2561 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2563 break;
2564 }
2565 udelay(50);
8db9d77b 2566 }
fa37d39e
SP		 2567 if (retry < 5)
2568 break;
8db9d77b
ZW		 2569 }
2570 if (i == 4)
5eddb70b 2571 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2572
2573 /* Train 2 */
5eddb70b
CW		 2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578 if (IS_GEN6(dev)) {
2579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580 /* SNB-B */
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582 }
5eddb70b 2583 I915_WRITE(reg, temp);
8db9d77b 2584
5eddb70b
CW		 2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
8db9d77b
ZW		 2587 if (HAS_PCH_CPT(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2590 } else {
2591 temp &= ~FDI_LINK_TRAIN_NONE;
2592 temp |= FDI_LINK_TRAIN_PATTERN_2;
2593 }
5eddb70b
CW		 2594 I915_WRITE(reg, temp);
2595
2596 POSTING_READ(reg);
8db9d77b
ZW		 2597 udelay(150);
2598
0206e353 2599 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
8db9d77b
ZW		 2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
8db9d77b
ZW		 2607 udelay(500);
2608
fa37d39e
SP		 2609 for (retry = 0; retry < 5; retry++) {
2610 reg = FDI_RX_IIR(pipe);
2611 temp = I915_READ(reg);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_SYMBOL_LOCK) {
2614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2616 break;
2617 }
2618 udelay(50);
8db9d77b 2619 }
fa37d39e
SP		 2620 if (retry < 5)
2621 break;
8db9d77b
ZW		 2622 }
2623 if (i == 4)
5eddb70b 2624 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2625
2626 DRM_DEBUG_KMS("FDI train done.\n");
2627}
2628
357555c0
JB		 2629/* Manual link training for Ivy Bridge A0 parts */
2630static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2631{
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 int pipe = intel_crtc->pipe;
2636 u32 reg, temp, i;
2637
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639 for train result */
2640 reg = FDI_RX_IMR(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_RX_SYMBOL_LOCK;
2643 temp &= ~FDI_RX_BIT_LOCK;
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(150);
2648
01a415fd
DV		 2649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650 I915_READ(FDI_RX_IIR(pipe)));
2651
357555c0
JB		 2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~(7 << 19);
2656 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2661 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2663
d74cf324
DV		 2664 I915_WRITE(FDI_RX_MISC(pipe),
2665 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2666
357555c0
JB		 2667 reg = FDI_RX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_AUTO;
2670 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2672 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2674
2675 POSTING_READ(reg);
2676 udelay(150);
2677
0206e353 2678 for (i = 0; i < 4; i++) {
357555c0
JB		 2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2684
2685 POSTING_READ(reg);
2686 udelay(500);
2687
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2696 break;
2697 }
2698 }
2699 if (i == 4)
2700 DRM_ERROR("FDI train 1 fail!\n");
2701
2702 /* Train 2 */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2716
2717 POSTING_READ(reg);
2718 udelay(150);
2719
0206e353 2720 for (i = 0; i < 4; i++) {
357555c0
JB		 2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2726
2727 POSTING_READ(reg);
2728 udelay(500);
2729
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2733
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2736 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2737 break;
2738 }
2739 }
2740 if (i == 4)
2741 DRM_ERROR("FDI train 2 fail!\n");
2742
2743 DRM_DEBUG_KMS("FDI train done.\n");
2744}
2745
88cefb6c 2746static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2747{
88cefb6c 2748 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2749 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2750 int pipe = intel_crtc->pipe;
5eddb70b 2751 u32 reg, temp;
79e53945 2752
c64e311e 2753
c98e9dcf 2754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2758 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2759 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2760 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
2765 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp | FDI_PCDCLK);
2768
2769 POSTING_READ(reg);
c98e9dcf
JB		 2770 udelay(200);
2771
20749730
PZ		 2772 /* Enable CPU FDI TX PLL, always on for Ironlake */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2776 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2777
20749730
PZ		 2778 POSTING_READ(reg);
2779 udelay(100);
6be4a607 2780 }
0e23b99d
JB		 2781}
2782
88cefb6c
DV		 2783static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2784{
2785 struct drm_device *dev = intel_crtc->base.dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 int pipe = intel_crtc->pipe;
2788 u32 reg, temp;
2789
2790 /* Switch from PCDclk to Rawclk */
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2794
2795 /* Disable CPU FDI TX PLL */
2796 reg = FDI_TX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2799
2800 POSTING_READ(reg);
2801 udelay(100);
2802
2803 reg = FDI_RX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2806
2807 /* Wait for the clocks to turn off. */
2808 POSTING_READ(reg);
2809 udelay(100);
2810}
2811
0fc932b8
JB		 2812static void ironlake_fdi_disable(struct drm_crtc *crtc)
2813{
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 int pipe = intel_crtc->pipe;
2818 u32 reg, temp;
2819
2820 /* disable CPU FDI tx and PCH FDI rx */
2821 reg = FDI_TX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2824 POSTING_READ(reg);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~(0x7 << 16);
dfd07d72 2829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2831
2832 POSTING_READ(reg);
2833 udelay(100);
2834
2835 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2836 if (HAS_PCH_IBX(dev)) {
2837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2838 }
0fc932b8
JB		 2839
2840 /* still set train pattern 1 */
2841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~FDI_LINK_TRAIN_NONE;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1;
2845 I915_WRITE(reg, temp);
2846
2847 reg = FDI_RX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 if (HAS_PCH_CPT(dev)) {
2850 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2851 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2852 } else {
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 }
2856 /* BPC in FDI rx is consistent with that in PIPECONF */
2857 temp &= ~(0x07 << 16);
dfd07d72 2858 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2859 I915_WRITE(reg, temp);
2860
2861 POSTING_READ(reg);
2862 udelay(100);
2863}
2864
5bb61643
CW		 2865static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2866{
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2870 unsigned long flags;
2871 bool pending;
2872
10d83730
VS		 2873 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2874 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2875 return false;
2876
2877 spin_lock_irqsave(&dev->event_lock, flags);
2878 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879 spin_unlock_irqrestore(&dev->event_lock, flags);
2880
2881 return pending;
2882}
2883
e6c3a2a6
CW		 2884static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2885{
0f91128d 2886 struct drm_device *dev = crtc->dev;
5bb61643 2887 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2888
2889 if (crtc->fb == NULL)
2890 return;
2891
2c10d571
DV		 2892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2893
5bb61643
CW		 2894 wait_event(dev_priv->pending_flip_queue,
2895 !intel_crtc_has_pending_flip(crtc));
2896
0f91128d
CW		 2897 mutex_lock(&dev->struct_mutex);
2898 intel_finish_fb(crtc->fb);
2899 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2900}
2901
e615efe4
ED		 2902/* Program iCLKIP clock to the desired frequency */
2903static void lpt_program_iclkip(struct drm_crtc *crtc)
2904{
2905 struct drm_device *dev = crtc->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2908 u32 temp;
2909
09153000
DV		 2910 mutex_lock(&dev_priv->dpio_lock);
2911
e615efe4
ED		 2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2919 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2920 SBI_SSCCTL_DISABLE,
2921 SBI_ICLK);
e615efe4
ED		 2922
2923 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2924 if (crtc->mode.clock == 20000) {
2925 auxdiv = 1;
2926 divsel = 0x41;
2927 phaseinc = 0x20;
2928 } else {
2929 /* The iCLK virtual clock root frequency is in MHz,
2930 * but the crtc->mode.clock in in KHz. To get the divisors,
2931 * it is necessary to divide one by another, so we
2932 * convert the virtual clock precision to KHz here for higher
2933 * precision.
2934 */
2935 u32 iclk_virtual_root_freq = 172800 * 1000;
2936 u32 iclk_pi_range = 64;
2937 u32 desired_divisor, msb_divisor_value, pi_value;
2938
2939 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2940 msb_divisor_value = desired_divisor / iclk_pi_range;
2941 pi_value = desired_divisor % iclk_pi_range;
2942
2943 auxdiv = 0;
2944 divsel = msb_divisor_value - 2;
2945 phaseinc = pi_value;
2946 }
2947
2948 /* This should not happen with any sane values */
2949 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2950 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2952 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2953
2954 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2955 crtc->mode.clock,
2956 auxdiv,
2957 divsel,
2958 phasedir,
2959 phaseinc);
2960
2961 /* Program SSCDIVINTPHASE6 */
988d6ee8 2962 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2963 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2964 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2965 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2967 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2968 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2969 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2970
2971 /* Program SSCAUXDIV */
988d6ee8 2972 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2973 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2974 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2975 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2976
2977 /* Enable modulator and associated divider */
988d6ee8 2978 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2979 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Wait for initialization time */
2983 udelay(24);
2984
2985 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2986
2987 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2988}
2989
f67a559d
JB		 2990/*
2991 * Enable PCH resources required for PCH ports:
2992 * - PCH PLLs
2993 * - FDI training & RX/TX
2994 * - update transcoder timings
2995 * - DP transcoding bits
2996 * - transcoder
2997 */
2998static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2999{
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003 int pipe = intel_crtc->pipe;
ee7b9f93 3004 u32 reg, temp;
2c07245f 3005
e7e164db
CW		 3006 assert_transcoder_disabled(dev_priv, pipe);
3007
cd986abb
DV		 3008 /* Write the TU size bits before fdi link training, so that error
3009 * detection works. */
3010 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3011 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3012
c98e9dcf 3013 /* For PCH output, training FDI link */
674cf967 3014 dev_priv->display.fdi_link_train(crtc);
2c07245f 3015
572deb37
DV		 3016 /* XXX: pch pll's can be enabled any time before we enable the PCH
3017 * transcoder, and we actually should do this to not upset any PCH
3018 * transcoder that already use the clock when we share it.
3019 *
3020 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3021 * unconditionally resets the pll - we need that to have the right LVDS
3022 * enable sequence. */
b6b4e185 3023 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3024
303b81e0 3025 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3026 u32 sel;
4b645f14 3027
c98e9dcf 3028 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3029 switch (pipe) {
3030 default:
3031 case 0:
3032 temp |= TRANSA_DPLL_ENABLE;
3033 sel = TRANSA_DPLLB_SEL;
3034 break;
3035 case 1:
3036 temp |= TRANSB_DPLL_ENABLE;
3037 sel = TRANSB_DPLLB_SEL;
3038 break;
3039 case 2:
3040 temp |= TRANSC_DPLL_ENABLE;
3041 sel = TRANSC_DPLLB_SEL;
3042 break;
d64311ab 3043 }
ee7b9f93
JB		 3044 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045 temp |= sel;
3046 else
3047 temp &= ~sel;
c98e9dcf 3048 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3049 }
5eddb70b 3050
d9b6cb56
JB		 3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3053 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3056
5eddb70b
CW		 3057 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3061
303b81e0 3062 intel_fdi_normal_train(crtc);
5e84e1a4 3063
c98e9dcf
JB		 3064 /* For PCH DP, enable TRANS_DP_CTL */
3065 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3066 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3067 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3068 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3069 reg = TRANS_DP_CTL(pipe);
3070 temp = I915_READ(reg);
3071 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3072 TRANS_DP_SYNC_MASK |
3073 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3074 temp |= (TRANS_DP_OUTPUT_ENABLE |
3075 TRANS_DP_ENH_FRAMING);
9325c9f0 3076 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3077
3078 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3079 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3080 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3081 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3082
3083 switch (intel_trans_dp_port_sel(crtc)) {
3084 case PCH_DP_B:
5eddb70b 3085 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3086 break;
3087 case PCH_DP_C:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3089 break;
3090 case PCH_DP_D:
5eddb70b 3091 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3092 break;
3093 default:
e95d41e1 3094 BUG();
32f9d658 3095 }
2c07245f 3096
5eddb70b 3097 I915_WRITE(reg, temp);
6be4a607 3098 }
b52eb4dc 3099
b8a4f404 3100 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3101}
3102
1507e5bd
PZ		 3103static void lpt_pch_enable(struct drm_crtc *crtc)
3104{
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3108 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3109
daed2dbb 3110 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3111
8c52b5e8 3112 lpt_program_iclkip(crtc);
1507e5bd 3113
0540e488 3114 /* Set transcoder timing. */
daed2dbb
PZ		 3115 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3116 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3117 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3118
daed2dbb
PZ		 3119 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3120 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3121 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3122 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3123
937bb610 3124 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3125}
3126
ee7b9f93
JB		 3127static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3128{
3129 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3130
3131 if (pll == NULL)
3132 return;
3133
3134 if (pll->refcount == 0) {
3135 WARN(1, "bad PCH PLL refcount\n");
3136 return;
3137 }
3138
3139 --pll->refcount;
3140 intel_crtc->pch_pll = NULL;
3141}
3142
3143static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3144{
3145 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3146 struct intel_pch_pll *pll;
3147 int i;
3148
3149 pll = intel_crtc->pch_pll;
3150 if (pll) {
3151 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3152 intel_crtc->base.base.id, pll->pll_reg);
3153 goto prepare;
3154 }
3155
98b6bd99
DV		 3156 if (HAS_PCH_IBX(dev_priv->dev)) {
3157 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3158 i = intel_crtc->pipe;
3159 pll = &dev_priv->pch_plls[i];
3160
3161 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3162 intel_crtc->base.base.id, pll->pll_reg);
3163
3164 goto found;
3165 }
3166
ee7b9f93
JB		 3167 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3168 pll = &dev_priv->pch_plls[i];
3169
3170 /* Only want to check enabled timings first */
3171 if (pll->refcount == 0)
3172 continue;
3173
3174 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3175 fp == I915_READ(pll->fp0_reg)) {
3176 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3177 intel_crtc->base.base.id,
3178 pll->pll_reg, pll->refcount, pll->active);
3179
3180 goto found;
3181 }
3182 }
3183
3184 /* Ok no matching timings, maybe there's a free one? */
3185 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186 pll = &dev_priv->pch_plls[i];
3187 if (pll->refcount == 0) {
3188 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3189 intel_crtc->base.base.id, pll->pll_reg);
3190 goto found;
3191 }
3192 }
3193
3194 return NULL;
3195
3196found:
3197 intel_crtc->pch_pll = pll;
3198 pll->refcount++;
84f44ce7 3199 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3200prepare: /* separate function? */
3201 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3202
e04c7350
CW		 3203 /* Wait for the clocks to stabilize before rewriting the regs */
3204 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3205 POSTING_READ(pll->pll_reg);
3206 udelay(150);
e04c7350
CW		 3207
3208 I915_WRITE(pll->fp0_reg, fp);
3209 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3210 pll->on = false;
3211 return pll;
3212}
3213
d4270e57
JB		 3214void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3215{
3216 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3217 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3218 u32 temp;
3219
3220 temp = I915_READ(dslreg);
3221 udelay(500);
3222 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3223 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3225 }
3226}
3227
b074cec8
JB		 3228static void ironlake_pfit_enable(struct intel_crtc *crtc)
3229{
3230 struct drm_device *dev = crtc->base.dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 int pipe = crtc->pipe;
3233
3234 if (crtc->config.pch_pfit.size &&
3235 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3236 /* Force use of hard-coded filter coefficients
3237 * as some pre-programmed values are broken,
3238 * e.g. x201.
3239 */
3240 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3241 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3242 PF_PIPE_SEL_IVB(pipe));
3243 else
3244 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3245 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3246 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3247 }
3248}
3249
f67a559d
JB		 3250static void ironlake_crtc_enable(struct drm_crtc *crtc)
3251{
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3255 struct intel_encoder *encoder;
f67a559d
JB		 3256 int pipe = intel_crtc->pipe;
3257 int plane = intel_crtc->plane;
3258 u32 temp;
f67a559d 3259
08a48469
DV		 3260 WARN_ON(!crtc->enabled);
3261
f67a559d
JB		 3262 if (intel_crtc->active)
3263 return;
3264
3265 intel_crtc->active = true;
8664281b
PZ		 3266
3267 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3268 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3269
f67a559d
JB		 3270 intel_update_watermarks(dev);
3271
3272 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3273 temp = I915_READ(PCH_LVDS);
3274 if ((temp & LVDS_PORT_EN) == 0)
3275 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3276 }
3277
f67a559d 3278
5bfe2ac0 3279 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3280 /* Note: FDI PLL enabling _must_ be done before we enable the
3281 * cpu pipes, hence this is separate from all the other fdi/pch
3282 * enabling. */
88cefb6c 3283 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3284 } else {
3285 assert_fdi_tx_disabled(dev_priv, pipe);
3286 assert_fdi_rx_disabled(dev_priv, pipe);
3287 }
f67a559d 3288
bf49ec8c
DV		 3289 for_each_encoder_on_crtc(dev, crtc, encoder)
3290 if (encoder->pre_enable)
3291 encoder->pre_enable(encoder);
f67a559d
JB		 3292
3293 /* Enable panel fitting for LVDS */
b074cec8 3294 ironlake_pfit_enable(intel_crtc);
f67a559d 3295
9c54c0dd
JB		 3296 /*
3297 * On ILK+ LUT must be loaded before the pipe is running but with
3298 * clocks enabled
3299 */
3300 intel_crtc_load_lut(crtc);
3301
5bfe2ac0
DV		 3302 intel_enable_pipe(dev_priv, pipe,
3303 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3304 intel_enable_plane(dev_priv, plane, pipe);
3305
5bfe2ac0 3306 if (intel_crtc->config.has_pch_encoder)
f67a559d 3307 ironlake_pch_enable(crtc);
c98e9dcf 3308
d1ebd816 3309 mutex_lock(&dev->struct_mutex);
bed4a673 3310 intel_update_fbc(dev);
d1ebd816
BW		 3311 mutex_unlock(&dev->struct_mutex);
3312
6b383a7f 3313 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3314
fa5c73b1
DV		 3315 for_each_encoder_on_crtc(dev, crtc, encoder)
3316 encoder->enable(encoder);
61b77ddd
DV		 3317
3318 if (HAS_PCH_CPT(dev))
3319 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3320
3321 /*
3322 * There seems to be a race in PCH platform hw (at least on some
3323 * outputs) where an enabled pipe still completes any pageflip right
3324 * away (as if the pipe is off) instead of waiting for vblank. As soon
3325 * as the first vblank happend, everything works as expected. Hence just
3326 * wait for one vblank before returning to avoid strange things
3327 * happening.
3328 */
3329 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3330}
3331
4f771f10
PZ		 3332static void haswell_crtc_enable(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 struct intel_encoder *encoder;
3338 int pipe = intel_crtc->pipe;
3339 int plane = intel_crtc->plane;
4f771f10
PZ		 3340
3341 WARN_ON(!crtc->enabled);
3342
3343 if (intel_crtc->active)
3344 return;
3345
3346 intel_crtc->active = true;
8664281b
PZ		 3347
3348 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3349 if (intel_crtc->config.has_pch_encoder)
3350 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3351
4f771f10
PZ		 3352 intel_update_watermarks(dev);
3353
5bfe2ac0 3354 if (intel_crtc->config.has_pch_encoder)
04945641 3355 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3356
3357 for_each_encoder_on_crtc(dev, crtc, encoder)
3358 if (encoder->pre_enable)
3359 encoder->pre_enable(encoder);
3360
1f544388 3361 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3362
1f544388 3363 /* Enable panel fitting for eDP */
b074cec8 3364 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3365
3366 /*
3367 * On ILK+ LUT must be loaded before the pipe is running but with
3368 * clocks enabled
3369 */
3370 intel_crtc_load_lut(crtc);
3371
1f544388 3372 intel_ddi_set_pipe_settings(crtc);
8228c251 3373 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3374
5bfe2ac0
DV		 3375 intel_enable_pipe(dev_priv, pipe,
3376 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3377 intel_enable_plane(dev_priv, plane, pipe);
3378
5bfe2ac0 3379 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3380 lpt_pch_enable(crtc);
4f771f10
PZ		 3381
3382 mutex_lock(&dev->struct_mutex);
3383 intel_update_fbc(dev);
3384 mutex_unlock(&dev->struct_mutex);
3385
3386 intel_crtc_update_cursor(crtc, true);
3387
3388 for_each_encoder_on_crtc(dev, crtc, encoder)
3389 encoder->enable(encoder);
3390
4f771f10
PZ		 3391 /*
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3397 * happening.
3398 */
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
3400}
3401
6be4a607
JB		 3402static void ironlake_crtc_disable(struct drm_crtc *crtc)
3403{
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3407 struct intel_encoder *encoder;
6be4a607
JB		 3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
5eddb70b 3410 u32 reg, temp;
b52eb4dc 3411
ef9c3aee 3412
f7abfe8b
CW		 3413 if (!intel_crtc->active)
3414 return;
3415
ea9d758d
DV		 3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->disable(encoder);
3418
e6c3a2a6 3419 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3420 drm_vblank_off(dev, pipe);
6b383a7f 3421 intel_crtc_update_cursor(crtc, false);
5eddb70b 3422
b24e7179 3423 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3424
973d04f9
CW		 3425 if (dev_priv->cfb_plane == plane)
3426 intel_disable_fbc(dev);
2c07245f 3427
8664281b 3428 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3429 intel_disable_pipe(dev_priv, pipe);
32f9d658 3430
6be4a607 3431 /* Disable PF */
9db4a9c7
JB		 3432 I915_WRITE(PF_CTL(pipe), 0);
3433 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3434
bf49ec8c
DV		 3435 for_each_encoder_on_crtc(dev, crtc, encoder)
3436 if (encoder->post_disable)
3437 encoder->post_disable(encoder);
2c07245f 3438
0fc932b8 3439 ironlake_fdi_disable(crtc);
249c0e64 3440
b8a4f404 3441 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3442 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3443
6be4a607
JB		 3444 if (HAS_PCH_CPT(dev)) {
3445 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3446 reg = TRANS_DP_CTL(pipe);
3447 temp = I915_READ(reg);
3448 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3449 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3450 I915_WRITE(reg, temp);
6be4a607
JB		 3451
3452 /* disable DPLL_SEL */
3453 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3454 switch (pipe) {
3455 case 0:
d64311ab 3456 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3457 break;
3458 case 1:
6be4a607 3459 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3460 break;
3461 case 2:
4b645f14 3462 /* C shares PLL A or B */
d64311ab 3463 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3464 break;
3465 default:
3466 BUG(); /* wtf */
3467 }
6be4a607 3468 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3469 }
e3421a18 3470
6be4a607 3471 /* disable PCH DPLL */
ee7b9f93 3472 intel_disable_pch_pll(intel_crtc);
8db9d77b 3473
88cefb6c 3474 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3475
f7abfe8b 3476 intel_crtc->active = false;
6b383a7f 3477 intel_update_watermarks(dev);
d1ebd816
BW		 3478
3479 mutex_lock(&dev->struct_mutex);
6b383a7f 3480 intel_update_fbc(dev);
d1ebd816 3481 mutex_unlock(&dev->struct_mutex);
6be4a607 3482}
1b3c7a47 3483
4f771f10 3484static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3485{
4f771f10
PZ		 3486 struct drm_device *dev = crtc->dev;
3487 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3489 struct intel_encoder *encoder;
3490 int pipe = intel_crtc->pipe;
3491 int plane = intel_crtc->plane;
3b117c8f 3492 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3493
4f771f10
PZ		 3494 if (!intel_crtc->active)
3495 return;
3496
3497 for_each_encoder_on_crtc(dev, crtc, encoder)
3498 encoder->disable(encoder);
3499
3500 intel_crtc_wait_for_pending_flips(crtc);
3501 drm_vblank_off(dev, pipe);
3502 intel_crtc_update_cursor(crtc, false);
3503
3504 intel_disable_plane(dev_priv, plane, pipe);
3505
3506 if (dev_priv->cfb_plane == plane)
3507 intel_disable_fbc(dev);
3508
8664281b
PZ		 3509 if (intel_crtc->config.has_pch_encoder)
3510 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3511 intel_disable_pipe(dev_priv, pipe);
3512
ad80a810 3513 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3514
f7708f78
PZ		 3515 /* XXX: Once we have proper panel fitter state tracking implemented with
3516 * hardware state read/check support we should switch to only disable
3517 * the panel fitter when we know it's used. */
3518 if (intel_using_power_well(dev)) {
3519 I915_WRITE(PF_CTL(pipe), 0);
3520 I915_WRITE(PF_WIN_SZ(pipe), 0);
3521 }
4f771f10 3522
1f544388 3523 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3524
3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 if (encoder->post_disable)
3527 encoder->post_disable(encoder);
3528
88adfff1 3529 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3530 lpt_disable_pch_transcoder(dev_priv);
8664281b 3531 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3532 intel_ddi_fdi_disable(crtc);
83616634 3533 }
4f771f10
PZ		 3534
3535 intel_crtc->active = false;
3536 intel_update_watermarks(dev);
3537
3538 mutex_lock(&dev->struct_mutex);
3539 intel_update_fbc(dev);
3540 mutex_unlock(&dev->struct_mutex);
3541}
3542
ee7b9f93
JB		 3543static void ironlake_crtc_off(struct drm_crtc *crtc)
3544{
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 intel_put_pch_pll(intel_crtc);
3547}
3548
6441ab5f
PZ		 3549static void haswell_crtc_off(struct drm_crtc *crtc)
3550{
a5c961d1
PZ		 3551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552
3553 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3554 * start using it. */
3b117c8f 3555 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3556
6441ab5f
PZ		 3557 intel_ddi_put_crtc_pll(crtc);
3558}
3559
02e792fb
DV		 3560static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3561{
02e792fb 3562 if (!enable && intel_crtc->overlay) {
23f09ce3 3563 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3564 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3565
23f09ce3 3566 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3567 dev_priv->mm.interruptible = false;
3568 (void) intel_overlay_switch_off(intel_crtc->overlay);
3569 dev_priv->mm.interruptible = true;
23f09ce3 3570 mutex_unlock(&dev->struct_mutex);
02e792fb 3571 }
02e792fb 3572
5dcdbcb0
CW		 3573 /* Let userspace switch the overlay on again. In most cases userspace
3574 * has to recompute where to put it anyway.
3575 */
02e792fb
DV		 3576}
3577
61bc95c1
EE		 3578/**
3579 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3580 * cursor plane briefly if not already running after enabling the display
3581 * plane.
3582 * This workaround avoids occasional blank screens when self refresh is
3583 * enabled.
3584 */
3585static void
3586g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3587{
3588 u32 cntl = I915_READ(CURCNTR(pipe));
3589
3590 if ((cntl & CURSOR_MODE) == 0) {
3591 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3592
3593 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3594 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3595 intel_wait_for_vblank(dev_priv->dev, pipe);
3596 I915_WRITE(CURCNTR(pipe), cntl);
3597 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3598 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3599 }
3600}
3601
2dd24552
JB		 3602static void i9xx_pfit_enable(struct intel_crtc *crtc)
3603{
3604 struct drm_device *dev = crtc->base.dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc_config *pipe_config = &crtc->config;
3607
3608 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3609 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3610 return;
3611
3612 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3613 assert_pipe_disabled(dev_priv, crtc->pipe);
3614
3615 /*
3616 * Enable automatic panel scaling so that non-native modes
3617 * fill the screen. The panel fitter should only be
3618 * adjusted whilst the pipe is disabled, according to
3619 * register description and PRM.
3620 */
3621 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3622 pipe_config->gmch_pfit.control,
3623 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3624
b074cec8
JB		 3625 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3626 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
2dd24552
JB		 3627}
3628
89b667f8
JB		 3629static void valleyview_crtc_enable(struct drm_crtc *crtc)
3630{
3631 struct drm_device *dev = crtc->dev;
3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634 struct intel_encoder *encoder;
3635 int pipe = intel_crtc->pipe;
3636 int plane = intel_crtc->plane;
3637
3638 WARN_ON(!crtc->enabled);
3639
3640 if (intel_crtc->active)
3641 return;
3642
3643 intel_crtc->active = true;
3644 intel_update_watermarks(dev);
3645
3646 mutex_lock(&dev_priv->dpio_lock);
3647
3648 for_each_encoder_on_crtc(dev, crtc, encoder)
3649 if (encoder->pre_pll_enable)
3650 encoder->pre_pll_enable(encoder);
3651
3652 intel_enable_pll(dev_priv, pipe);
3653
3654 for_each_encoder_on_crtc(dev, crtc, encoder)
3655 if (encoder->pre_enable)
3656 encoder->pre_enable(encoder);
3657
3658 /* VLV wants encoder enabling _before_ the pipe is up. */
3659 for_each_encoder_on_crtc(dev, crtc, encoder)
3660 encoder->enable(encoder);
3661
2dd24552
JB		 3662 /* Enable panel fitting for eDP */
3663 i9xx_pfit_enable(intel_crtc);
3664
89b667f8
JB		 3665 intel_enable_pipe(dev_priv, pipe, false);
3666 intel_enable_plane(dev_priv, plane, pipe);
3667
3668 intel_crtc_load_lut(crtc);
3669 intel_update_fbc(dev);
3670
3671 /* Give the overlay scaler a chance to enable if it's on this pipe */
3672 intel_crtc_dpms_overlay(intel_crtc, true);
3673 intel_crtc_update_cursor(crtc, true);
3674
3675 mutex_unlock(&dev_priv->dpio_lock);
3676}
3677
0b8765c6 3678static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3679{
3680 struct drm_device *dev = crtc->dev;
79e53945
JB		 3681 struct drm_i915_private *dev_priv = dev->dev_private;
3682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3683 struct intel_encoder *encoder;
79e53945 3684 int pipe = intel_crtc->pipe;
80824003 3685 int plane = intel_crtc->plane;
79e53945 3686
08a48469
DV		 3687 WARN_ON(!crtc->enabled);
3688
f7abfe8b
CW		 3689 if (intel_crtc->active)
3690 return;
3691
3692 intel_crtc->active = true;
6b383a7f
CW		 3693 intel_update_watermarks(dev);
3694
63d7bbe9 3695 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3696
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 if (encoder->pre_enable)
3699 encoder->pre_enable(encoder);
3700
2dd24552
JB		 3701 /* Enable panel fitting for LVDS */
3702 i9xx_pfit_enable(intel_crtc);
3703
040484af 3704 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3705 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3706 if (IS_G4X(dev))
3707 g4x_fixup_plane(dev_priv, pipe);
79e53945 3708
0b8765c6 3709 intel_crtc_load_lut(crtc);
bed4a673 3710 intel_update_fbc(dev);
79e53945 3711
0b8765c6
JB		 3712 /* Give the overlay scaler a chance to enable if it's on this pipe */
3713 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3714 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3715
fa5c73b1
DV		 3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 encoder->enable(encoder);
0b8765c6 3718}
79e53945 3719
87476d63
DV		 3720static void i9xx_pfit_disable(struct intel_crtc *crtc)
3721{
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 enum pipe pipe;
3725 uint32_t pctl = I915_READ(PFIT_CONTROL);
3726
3727 assert_pipe_disabled(dev_priv, crtc->pipe);
3728
3729 if (INTEL_INFO(dev)->gen >= 4)
3730 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3731 else
3732 pipe = PIPE_B;
3733
3734 if (pipe == crtc->pipe) {
3735 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3736 I915_WRITE(PFIT_CONTROL, 0);
3737 }
3738}
3739
0b8765c6
JB		 3740static void i9xx_crtc_disable(struct drm_crtc *crtc)
3741{
3742 struct drm_device *dev = crtc->dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3745 struct intel_encoder *encoder;
0b8765c6
JB		 3746 int pipe = intel_crtc->pipe;
3747 int plane = intel_crtc->plane;
ef9c3aee 3748
f7abfe8b
CW		 3749 if (!intel_crtc->active)
3750 return;
3751
ea9d758d
DV		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 encoder->disable(encoder);
3754
0b8765c6 3755 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3756 intel_crtc_wait_for_pending_flips(crtc);
3757 drm_vblank_off(dev, pipe);
0b8765c6 3758 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3759 intel_crtc_update_cursor(crtc, false);
0b8765c6 3760
973d04f9
CW		 3761 if (dev_priv->cfb_plane == plane)
3762 intel_disable_fbc(dev);
79e53945 3763
b24e7179 3764 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3765 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3766
87476d63 3767 i9xx_pfit_disable(intel_crtc);
24a1f16d 3768
89b667f8
JB		 3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 if (encoder->post_disable)
3771 encoder->post_disable(encoder);
3772
63d7bbe9 3773 intel_disable_pll(dev_priv, pipe);
0b8765c6 3774
f7abfe8b 3775 intel_crtc->active = false;
6b383a7f
CW		 3776 intel_update_fbc(dev);
3777 intel_update_watermarks(dev);
0b8765c6
JB		 3778}
3779
ee7b9f93
JB		 3780static void i9xx_crtc_off(struct drm_crtc *crtc)
3781{
3782}
3783
976f8a20
DV		 3784static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3785 bool enabled)
2c07245f
ZW		 3786{
3787 struct drm_device *dev = crtc->dev;
3788 struct drm_i915_master_private *master_priv;
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790 int pipe = intel_crtc->pipe;
79e53945
JB		 3791
3792 if (!dev->primary->master)
3793 return;
3794
3795 master_priv = dev->primary->master->driver_priv;
3796 if (!master_priv->sarea_priv)
3797 return;
3798
79e53945
JB		 3799 switch (pipe) {
3800 case 0:
3801 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3802 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3803 break;
3804 case 1:
3805 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3806 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3807 break;
3808 default:
9db4a9c7 3809 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3810 break;
3811 }
79e53945
JB		 3812}
3813
976f8a20
DV		 3814/**
3815 * Sets the power management mode of the pipe and plane.
3816 */
3817void intel_crtc_update_dpms(struct drm_crtc *crtc)
3818{
3819 struct drm_device *dev = crtc->dev;
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821 struct intel_encoder *intel_encoder;
3822 bool enable = false;
3823
3824 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3825 enable |= intel_encoder->connectors_active;
3826
3827 if (enable)
3828 dev_priv->display.crtc_enable(crtc);
3829 else
3830 dev_priv->display.crtc_disable(crtc);
3831
3832 intel_crtc_update_sarea(crtc, enable);
3833}
3834
cdd59983
CW		 3835static void intel_crtc_disable(struct drm_crtc *crtc)
3836{
cdd59983 3837 struct drm_device *dev = crtc->dev;
976f8a20 3838 struct drm_connector *connector;
ee7b9f93 3839 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3841
976f8a20
DV		 3842 /* crtc should still be enabled when we disable it. */
3843 WARN_ON(!crtc->enabled);
3844
7b9f35a6 3845 intel_crtc->eld_vld = false;
976f8a20
DV		 3846 dev_priv->display.crtc_disable(crtc);
3847 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3848 dev_priv->display.off(crtc);
3849
931872fc
CW		 3850 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3851 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3852
3853 if (crtc->fb) {
3854 mutex_lock(&dev->struct_mutex);
1690e1eb 3855 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3856 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3857 crtc->fb = NULL;
3858 }
3859
3860 /* Update computed state. */
3861 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3862 if (!connector->encoder || !connector->encoder->crtc)
3863 continue;
3864
3865 if (connector->encoder->crtc != crtc)
3866 continue;
3867
3868 connector->dpms = DRM_MODE_DPMS_OFF;
3869 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3870 }
3871}
3872
a261b246 3873void intel_modeset_disable(struct drm_device *dev)
79e53945 3874{
a261b246
DV		 3875 struct drm_crtc *crtc;
3876
3877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3878 if (crtc->enabled)
3879 intel_crtc_disable(crtc);
3880 }
79e53945
JB		 3881}
3882
ea5b213a 3883void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3884{
4ef69c7a 3885 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3886
ea5b213a
CW		 3887 drm_encoder_cleanup(encoder);
3888 kfree(intel_encoder);
7e7d76c3
JB		 3889}
3890
5ab432ef
DV		 3891/* Simple dpms helper for encodres with just one connector, no cloning and only
3892 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3893 * state of the entire output pipe. */
3894void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3895{
5ab432ef
DV		 3896 if (mode == DRM_MODE_DPMS_ON) {
3897 encoder->connectors_active = true;
3898
b2cabb0e 3899 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3900 } else {
3901 encoder->connectors_active = false;
3902
b2cabb0e 3903 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3904 }
79e53945
JB		 3905}
3906
0a91ca29
DV		 3907/* Cross check the actual hw state with our own modeset state tracking (and it's
3908 * internal consistency). */
b980514c 3909static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3910{
0a91ca29
DV		 3911 if (connector->get_hw_state(connector)) {
3912 struct intel_encoder *encoder = connector->encoder;
3913 struct drm_crtc *crtc;
3914 bool encoder_enabled;
3915 enum pipe pipe;
3916
3917 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3918 connector->base.base.id,
3919 drm_get_connector_name(&connector->base));
3920
3921 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3922 "wrong connector dpms state\n");
3923 WARN(connector->base.encoder != &encoder->base,
3924 "active connector not linked to encoder\n");
3925 WARN(!encoder->connectors_active,
3926 "encoder->connectors_active not set\n");
3927
3928 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3929 WARN(!encoder_enabled, "encoder not enabled\n");
3930 if (WARN_ON(!encoder->base.crtc))
3931 return;
3932
3933 crtc = encoder->base.crtc;
3934
3935 WARN(!crtc->enabled, "crtc not enabled\n");
3936 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3937 WARN(pipe != to_intel_crtc(crtc)->pipe,
3938 "encoder active on the wrong pipe\n");
3939 }
79e53945
JB		 3940}
3941
5ab432ef
DV		 3942/* Even simpler default implementation, if there's really no special case to
3943 * consider. */
3944void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3945{
5ab432ef 3946 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3947
5ab432ef
DV		 3948 /* All the simple cases only support two dpms states. */
3949 if (mode != DRM_MODE_DPMS_ON)
3950 mode = DRM_MODE_DPMS_OFF;
d4270e57 3951
5ab432ef
DV		 3952 if (mode == connector->dpms)
3953 return;
3954
3955 connector->dpms = mode;
3956
3957 /* Only need to change hw state when actually enabled */
3958 if (encoder->base.crtc)
3959 intel_encoder_dpms(encoder, mode);
3960 else
8af6cf88 3961 WARN_ON(encoder->connectors_active != false);
0a91ca29 3962
b980514c 3963 intel_modeset_check_state(connector->dev);
79e53945
JB		 3964}
3965
f0947c37
DV		 3966/* Simple connector->get_hw_state implementation for encoders that support only
3967 * one connector and no cloning and hence the encoder state determines the state
3968 * of the connector. */
3969bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3970{
24929352 3971 enum pipe pipe = 0;
f0947c37 3972 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3973
f0947c37 3974 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3975}
3976
b8cecdf5
DV		 3977static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3978 struct intel_crtc_config *pipe_config)
79e53945 3979{
2c07245f 3980 struct drm_device *dev = crtc->dev;
b8cecdf5 3981 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3982
bad720ff 3983 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3984 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3985 if (pipe_config->requested_mode.clock * 3
3986 > IRONLAKE_FDI_FREQ * 4)
2377b741 3987 return false;
2c07245f 3988 }
89749350 3989
f9bef081
DV		 3990 /* All interlaced capable intel hw wants timings in frames. Note though
3991 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3992 * timings, so we need to be careful not to clobber these.*/
7ae89233 3993 if (!pipe_config->timings_set)
f9bef081 3994 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3995
44f46b42
CW		 3996 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3997 * with a hsync front porch of 0.
3998 */
3999 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4000 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4001 return false;
4002
bd080ee5 4003 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4004 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4005 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4006 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4007 * for lvds. */
4008 pipe_config->pipe_bpp = 8*3;
4009 }
4010
79e53945
JB		 4011 return true;
4012}
4013
25eb05fc
JB		 4014static int valleyview_get_display_clock_speed(struct drm_device *dev)
4015{
4016 return 400000; /* FIXME */
4017}
4018
e70236a8
JB		 4019static int i945_get_display_clock_speed(struct drm_device *dev)
4020{
4021 return 400000;
4022}
79e53945 4023
e70236a8 4024static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4025{
e70236a8
JB		 4026 return 333000;
4027}
79e53945 4028
e70236a8
JB		 4029static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4030{
4031 return 200000;
4032}
79e53945 4033
e70236a8
JB		 4034static int i915gm_get_display_clock_speed(struct drm_device *dev)
4035{
4036 u16 gcfgc = 0;
79e53945 4037
e70236a8
JB		 4038 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4039
4040 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4041 return 133000;
4042 else {
4043 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4044 case GC_DISPLAY_CLOCK_333_MHZ:
4045 return 333000;
4046 default:
4047 case GC_DISPLAY_CLOCK_190_200_MHZ:
4048 return 190000;
79e53945 4049 }
e70236a8
JB		 4050 }
4051}
4052
4053static int i865_get_display_clock_speed(struct drm_device *dev)
4054{
4055 return 266000;
4056}
4057
4058static int i855_get_display_clock_speed(struct drm_device *dev)
4059{
4060 u16 hpllcc = 0;
4061 /* Assume that the hardware is in the high speed state. This
4062 * should be the default.
4063 */
4064 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4065 case GC_CLOCK_133_200:
4066 case GC_CLOCK_100_200:
4067 return 200000;
4068 case GC_CLOCK_166_250:
4069 return 250000;
4070 case GC_CLOCK_100_133:
79e53945 4071 return 133000;
e70236a8 4072 }
79e53945 4073
e70236a8
JB		 4074 /* Shouldn't happen */
4075 return 0;
4076}
79e53945 4077
e70236a8
JB		 4078static int i830_get_display_clock_speed(struct drm_device *dev)
4079{
4080 return 133000;
79e53945
JB		 4081}
4082
2c07245f 4083static void
e69d0bc1 4084intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4085{
4086 while (*num > 0xffffff || *den > 0xffffff) {
4087 *num >>= 1;
4088 *den >>= 1;
4089 }
4090}
4091
e69d0bc1
DV		 4092void
4093intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4094 int pixel_clock, int link_clock,
4095 struct intel_link_m_n *m_n)
2c07245f 4096{
e69d0bc1 4097 m_n->tu = 64;
22ed1113
CW		 4098 m_n->gmch_m = bits_per_pixel * pixel_clock;
4099 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4100 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4101 m_n->link_m = pixel_clock;
4102 m_n->link_n = link_clock;
e69d0bc1 4103 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4104}
4105
a7615030
CW		 4106static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4107{
72bbe58c
KP		 4108 if (i915_panel_use_ssc >= 0)
4109 return i915_panel_use_ssc != 0;
4110 return dev_priv->lvds_use_ssc
435793df 4111 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4112}
4113
a0c4da24
JB		 4114static int vlv_get_refclk(struct drm_crtc *crtc)
4115{
4116 struct drm_device *dev = crtc->dev;
4117 struct drm_i915_private *dev_priv = dev->dev_private;
4118 int refclk = 27000; /* for DP & HDMI */
4119
4120 return 100000; /* only one validated so far */
4121
4122 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4123 refclk = 96000;
4124 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4125 if (intel_panel_use_ssc(dev_priv))
4126 refclk = 100000;
4127 else
4128 refclk = 96000;
4129 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4130 refclk = 100000;
4131 }
4132
4133 return refclk;
4134}
4135
c65d77d8
JB		 4136static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4137{
4138 struct drm_device *dev = crtc->dev;
4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 int refclk;
4141
a0c4da24
JB		 4142 if (IS_VALLEYVIEW(dev)) {
4143 refclk = vlv_get_refclk(crtc);
4144 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4145 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4146 refclk = dev_priv->lvds_ssc_freq * 1000;
4147 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4148 refclk / 1000);
4149 } else if (!IS_GEN2(dev)) {
4150 refclk = 96000;
4151 } else {
4152 refclk = 48000;
4153 }
4154
4155 return refclk;
4156}
4157
f47709a9 4158static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4159{
f47709a9
DV		 4160 unsigned dotclock = crtc->config.adjusted_mode.clock;
4161 struct dpll *clock = &crtc->config.dpll;
4162
c65d77d8
JB		 4163 /* SDVO TV has fixed PLL values depend on its clock range,
4164 this mirrors vbios setting. */
f47709a9 4165 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4166 clock->p1 = 2;
4167 clock->p2 = 10;
4168 clock->n = 3;
4169 clock->m1 = 16;
4170 clock->m2 = 8;
f47709a9 4171 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4172 clock->p1 = 1;
4173 clock->p2 = 10;
4174 clock->n = 6;
4175 clock->m1 = 12;
4176 clock->m2 = 8;
4177 }
f47709a9
DV		 4178
4179 crtc->config.clock_set = true;
c65d77d8
JB		 4180}
4181
7429e9d4
DV		 4182static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4183{
4184 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4185}
4186
4187static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4188{
4189 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4190}
4191
f47709a9 4192static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4193 intel_clock_t *reduced_clock)
4194{
f47709a9 4195 struct drm_device *dev = crtc->base.dev;
a7516a05 4196 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4197 int pipe = crtc->pipe;
a7516a05
JB		 4198 u32 fp, fp2 = 0;
4199
4200 if (IS_PINEVIEW(dev)) {
7429e9d4 4201 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4202 if (reduced_clock)
7429e9d4 4203 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4204 } else {
7429e9d4 4205 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4206 if (reduced_clock)
7429e9d4 4207 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4208 }
4209
4210 I915_WRITE(FP0(pipe), fp);
4211
f47709a9
DV		 4212 crtc->lowfreq_avail = false;
4213 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4214 reduced_clock && i915_powersave) {
4215 I915_WRITE(FP1(pipe), fp2);
f47709a9 4216 crtc->lowfreq_avail = true;
a7516a05
JB		 4217 } else {
4218 I915_WRITE(FP1(pipe), fp);
4219 }
4220}
4221
89b667f8
JB		 4222static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4223{
4224 u32 reg_val;
4225
4226 /*
4227 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4228 * and set it to a reasonable value instead.
4229 */
4230 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4231 reg_val &= 0xffffff00;
4232 reg_val |= 0x00000030;
4233 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4234
4235 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4236 reg_val &= 0x8cffffff;
4237 reg_val = 0x8c000000;
4238 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4239
4240 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4241 reg_val &= 0xffffff00;
4242 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4243
4244 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4245 reg_val &= 0x00ffffff;
4246 reg_val |= 0xb0000000;
4247 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4248}
4249
03afc4a2
DV		 4250static void intel_dp_set_m_n(struct intel_crtc *crtc)
4251{
4252 if (crtc->config.has_pch_encoder)
4253 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4254 else
4255 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4256}
4257
f47709a9 4258static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4259{
f47709a9 4260 struct drm_device *dev = crtc->base.dev;
a0c4da24 4261 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4262 struct drm_display_mode *adjusted_mode =
4263 &crtc->config.adjusted_mode;
4264 struct intel_encoder *encoder;
f47709a9 4265 int pipe = crtc->pipe;
89b667f8 4266 u32 dpll, mdiv;
a0c4da24 4267 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4268 bool is_hdmi;
198a037f 4269 u32 coreclk, reg_val, dpll_md;
a0c4da24 4270
09153000
DV		 4271 mutex_lock(&dev_priv->dpio_lock);
4272
89b667f8 4273 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4274
f47709a9
DV		 4275 bestn = crtc->config.dpll.n;
4276 bestm1 = crtc->config.dpll.m1;
4277 bestm2 = crtc->config.dpll.m2;
4278 bestp1 = crtc->config.dpll.p1;
4279 bestp2 = crtc->config.dpll.p2;
a0c4da24 4280
89b667f8
JB		 4281 /* See eDP HDMI DPIO driver vbios notes doc */
4282
4283 /* PLL B needs special handling */
4284 if (pipe)
4285 vlv_pllb_recal_opamp(dev_priv);
4286
4287 /* Set up Tx target for periodic Rcomp update */
4288 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4289
4290 /* Disable target IRef on PLL */
4291 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4292 reg_val &= 0x00ffffff;
4293 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4294
4295 /* Disable fast lock */
4296 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4297
4298 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4299 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4300 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4301 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4302 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4303 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4304 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4305 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4306 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4307 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4308
89b667f8
JB		 4309 mdiv |= DPIO_ENABLE_CALIBRATION;
4310 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4311
89b667f8
JB		 4312 /* Set HBR and RBR LPF coefficients */
4313 if (adjusted_mode->clock == 162000 ||
4314 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4315 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4316 0x005f0021);
4317 else
4318 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4319 0x00d0000f);
4320
4321 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4322 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4323 /* Use SSC source */
4324 if (!pipe)
4325 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4326 0x0df40000);
4327 else
4328 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4329 0x0df70000);
4330 } else { /* HDMI or VGA */
4331 /* Use bend source */
4332 if (!pipe)
4333 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4334 0x0df70000);
4335 else
4336 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4337 0x0df40000);
4338 }
a0c4da24 4339
89b667f8
JB		 4340 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4341 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4342 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4343 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4344 coreclk |= 0x01000000;
4345 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4346
89b667f8 4347 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4348
89b667f8
JB		 4349 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4350 if (encoder->pre_pll_enable)
4351 encoder->pre_pll_enable(encoder);
2a8f64ca 4352
89b667f8
JB		 4353 /* Enable DPIO clock input */
4354 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4355 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4356 if (pipe)
4357 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4358
89b667f8 4359 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4360 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4361 POSTING_READ(DPLL(pipe));
4362 udelay(150);
a0c4da24 4363
89b667f8
JB		 4364 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4365 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4366
198a037f
DV		 4367 dpll_md = 0;
4368 if (crtc->config.pixel_multiplier > 1) {
4369 dpll_md = (crtc->config.pixel_multiplier - 1)
4370 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4371 }
198a037f
DV		 4372 I915_WRITE(DPLL_MD(pipe), dpll_md);
4373 POSTING_READ(DPLL_MD(pipe));
f47709a9 4374
89b667f8
JB		 4375 if (crtc->config.has_dp_encoder)
4376 intel_dp_set_m_n(crtc);
09153000
DV		 4377
4378 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4379}
4380
f47709a9
DV		 4381static void i9xx_update_pll(struct intel_crtc *crtc,
4382 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4383 int num_connectors)
4384{
f47709a9 4385 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4386 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4387 struct intel_encoder *encoder;
f47709a9 4388 int pipe = crtc->pipe;
eb1cbe48
DV		 4389 u32 dpll;
4390 bool is_sdvo;
f47709a9 4391 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4392
f47709a9 4393 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4394
f47709a9
DV		 4395 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4396 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4397
4398 dpll = DPLL_VGA_MODE_DIS;
4399
f47709a9 4400 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4401 dpll |= DPLLB_MODE_LVDS;
4402 else
4403 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4404
198a037f
DV		 4405 if ((crtc->config.pixel_multiplier > 1) &&
4406 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4407 dpll |= (crtc->config.pixel_multiplier - 1)
4408 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4409 }
198a037f
DV		 4410
4411 if (is_sdvo)
4412 dpll |= DPLL_DVO_HIGH_SPEED;
4413
f47709a9 4414 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4415 dpll |= DPLL_DVO_HIGH_SPEED;
4416
4417 /* compute bitmask from p1 value */
4418 if (IS_PINEVIEW(dev))
4419 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4420 else {
4421 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4422 if (IS_G4X(dev) && reduced_clock)
4423 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4424 }
4425 switch (clock->p2) {
4426 case 5:
4427 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4428 break;
4429 case 7:
4430 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4431 break;
4432 case 10:
4433 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4434 break;
4435 case 14:
4436 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4437 break;
4438 }
4439 if (INTEL_INFO(dev)->gen >= 4)
4440 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4441
f47709a9 4442 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4443 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4444 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4445 /* XXX: just matching BIOS for now */
4446 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4447 dpll |= 3;
f47709a9 4448 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4449 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4450 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4451 else
4452 dpll |= PLL_REF_INPUT_DREFCLK;
4453
4454 dpll |= DPLL_VCO_ENABLE;
4455 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4456 POSTING_READ(DPLL(pipe));
4457 udelay(150);
4458
f47709a9 4459 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4460 if (encoder->pre_pll_enable)
4461 encoder->pre_pll_enable(encoder);
eb1cbe48 4462
f47709a9
DV		 4463 if (crtc->config.has_dp_encoder)
4464 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4465
4466 I915_WRITE(DPLL(pipe), dpll);
4467
4468 /* Wait for the clocks to stabilize. */
4469 POSTING_READ(DPLL(pipe));
4470 udelay(150);
4471
4472 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4473 u32 dpll_md = 0;
4474 if (crtc->config.pixel_multiplier > 1) {
4475 dpll_md = (crtc->config.pixel_multiplier - 1)
4476 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4477 }
198a037f 4478 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4479 } else {
4480 /* The pixel multiplier can only be updated once the
4481 * DPLL is enabled and the clocks are stable.
4482 *
4483 * So write it again.
4484 */
4485 I915_WRITE(DPLL(pipe), dpll);
4486 }
4487}
4488
f47709a9 4489static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4490 struct drm_display_mode *adjusted_mode,
f47709a9 4491 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4492 int num_connectors)
4493{
f47709a9 4494 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4495 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4496 struct intel_encoder *encoder;
f47709a9 4497 int pipe = crtc->pipe;
eb1cbe48 4498 u32 dpll;
f47709a9 4499 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4500
f47709a9 4501 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4502
eb1cbe48
DV		 4503 dpll = DPLL_VGA_MODE_DIS;
4504
f47709a9 4505 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4506 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4507 } else {
4508 if (clock->p1 == 2)
4509 dpll |= PLL_P1_DIVIDE_BY_TWO;
4510 else
4511 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 if (clock->p2 == 4)
4513 dpll |= PLL_P2_DIVIDE_BY_4;
4514 }
4515
f47709a9 4516 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4517 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4518 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4519 else
4520 dpll |= PLL_REF_INPUT_DREFCLK;
4521
4522 dpll |= DPLL_VCO_ENABLE;
4523 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4524 POSTING_READ(DPLL(pipe));
4525 udelay(150);
4526
f47709a9 4527 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4528 if (encoder->pre_pll_enable)
4529 encoder->pre_pll_enable(encoder);
eb1cbe48 4530
5b5896e4
DV		 4531 I915_WRITE(DPLL(pipe), dpll);
4532
4533 /* Wait for the clocks to stabilize. */
4534 POSTING_READ(DPLL(pipe));
4535 udelay(150);
4536
eb1cbe48
DV		 4537 /* The pixel multiplier can only be updated once the
4538 * DPLL is enabled and the clocks are stable.
4539 *
4540 * So write it again.
4541 */
4542 I915_WRITE(DPLL(pipe), dpll);
4543}
4544
b0e77b9c
PZ		 4545static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4546 struct drm_display_mode *mode,
4547 struct drm_display_mode *adjusted_mode)
4548{
4549 struct drm_device *dev = intel_crtc->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4552 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4553 uint32_t vsyncshift;
4554
4555 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4556 /* the chip adds 2 halflines automatically */
4557 adjusted_mode->crtc_vtotal -= 1;
4558 adjusted_mode->crtc_vblank_end -= 1;
4559 vsyncshift = adjusted_mode->crtc_hsync_start
4560 - adjusted_mode->crtc_htotal / 2;
4561 } else {
4562 vsyncshift = 0;
4563 }
4564
4565 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4566 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4567
fe2b8f9d 4568 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4569 (adjusted_mode->crtc_hdisplay - 1) |
4570 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4571 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4572 (adjusted_mode->crtc_hblank_start - 1) |
4573 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4574 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4575 (adjusted_mode->crtc_hsync_start - 1) |
4576 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4577
fe2b8f9d 4578 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4579 (adjusted_mode->crtc_vdisplay - 1) |
4580 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4581 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4582 (adjusted_mode->crtc_vblank_start - 1) |
4583 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4584 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4585 (adjusted_mode->crtc_vsync_start - 1) |
4586 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4587
b5e508d4
PZ		 4588 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4589 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4590 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4591 * bits. */
4592 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4593 (pipe == PIPE_B || pipe == PIPE_C))
4594 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4595
b0e77b9c
PZ		 4596 /* pipesrc controls the size that is scaled from, which should
4597 * always be the user's requested size.
4598 */
4599 I915_WRITE(PIPESRC(pipe),
4600 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4601}
4602
84b046f3
DV		 4603static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4604{
4605 struct drm_device *dev = intel_crtc->base.dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 uint32_t pipeconf;
4608
4609 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4610
4611 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4612 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4613 * core speed.
4614 *
4615 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4616 * pipe == 0 check?
4617 */
4618 if (intel_crtc->config.requested_mode.clock >
4619 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4620 pipeconf |= PIPECONF_DOUBLE_WIDE;
4621 else
4622 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4623 }
4624
4625 /* default to 8bpc */
4626 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4627 if (intel_crtc->config.has_dp_encoder) {
4628 if (intel_crtc->config.dither) {
4629 pipeconf |= PIPECONF_6BPC |
4630 PIPECONF_DITHER_EN |
4631 PIPECONF_DITHER_TYPE_SP;
4632 }
4633 }
4634
4635 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4636 INTEL_OUTPUT_EDP)) {
4637 if (intel_crtc->config.dither) {
4638 pipeconf |= PIPECONF_6BPC |
4639 PIPECONF_ENABLE |
4640 I965_PIPECONF_ACTIVE;
4641 }
4642 }
4643
4644 if (HAS_PIPE_CXSR(dev)) {
4645 if (intel_crtc->lowfreq_avail) {
4646 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4647 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4648 } else {
4649 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4650 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4651 }
4652 }
4653
4654 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4655 if (!IS_GEN2(dev) &&
4656 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4657 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4658 else
4659 pipeconf |= PIPECONF_PROGRESSIVE;
4660
9c8e09b7
VS		 4661 if (IS_VALLEYVIEW(dev)) {
4662 if (intel_crtc->config.limited_color_range)
4663 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4664 else
4665 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4666 }
4667
84b046f3
DV		 4668 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4669 POSTING_READ(PIPECONF(intel_crtc->pipe));
4670}
4671
f564048e 4672static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4673 int x, int y,
94352cf9 4674 struct drm_framebuffer *fb)
79e53945
JB		 4675{
4676 struct drm_device *dev = crtc->dev;
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4679 struct drm_display_mode *adjusted_mode =
4680 &intel_crtc->config.adjusted_mode;
4681 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4682 int pipe = intel_crtc->pipe;
80824003 4683 int plane = intel_crtc->plane;
c751ce4f 4684 int refclk, num_connectors = 0;
652c393a 4685 intel_clock_t clock, reduced_clock;
84b046f3 4686 u32 dspcntr;
eb1cbe48 4687 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4688 bool is_lvds = false, is_tv = false;
5eddb70b 4689 struct intel_encoder *encoder;
d4906093 4690 const intel_limit_t *limit;
5c3b82e2 4691 int ret;
79e53945 4692
6c2b7c12 4693 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4694 switch (encoder->type) {
79e53945
JB		 4695 case INTEL_OUTPUT_LVDS:
4696 is_lvds = true;
4697 break;
4698 case INTEL_OUTPUT_SDVO:
7d57382e 4699 case INTEL_OUTPUT_HDMI:
79e53945 4700 is_sdvo = true;
5eddb70b 4701 if (encoder->needs_tv_clock)
e2f0ba97 4702 is_tv = true;
79e53945 4703 break;
79e53945
JB		 4704 case INTEL_OUTPUT_TVOUT:
4705 is_tv = true;
4706 break;
79e53945 4707 }
43565a06 4708
c751ce4f 4709 num_connectors++;
79e53945
JB		 4710 }
4711
c65d77d8 4712 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4713
d4906093
ML		 4714 /*
4715 * Returns a set of divisors for the desired target clock with the given
4716 * refclk, or FALSE. The returned values represent the clock equation:
4717 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4718 */
1b894b59 4719 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4720 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4721 &clock);
79e53945
JB		 4722 if (!ok) {
4723 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4724 return -EINVAL;
79e53945
JB		 4725 }
4726
cda4b7d3 4727 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4728 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4729
ddc9003c 4730 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4731 /*
4732 * Ensure we match the reduced clock's P to the target clock.
4733 * If the clocks don't match, we can't switch the display clock
4734 * by using the FP0/FP1. In such case we will disable the LVDS
4735 * downclock feature.
4736 */
ddc9003c 4737 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4738 dev_priv->lvds_downclock,
4739 refclk,
cec2f356 4740 &clock,
5eddb70b 4741 &reduced_clock);
7026d4ac 4742 }
f47709a9
DV		 4743 /* Compat-code for transition, will disappear. */
4744 if (!intel_crtc->config.clock_set) {
4745 intel_crtc->config.dpll.n = clock.n;
4746 intel_crtc->config.dpll.m1 = clock.m1;
4747 intel_crtc->config.dpll.m2 = clock.m2;
4748 intel_crtc->config.dpll.p1 = clock.p1;
4749 intel_crtc->config.dpll.p2 = clock.p2;
4750 }
7026d4ac 4751
c65d77d8 4752 if (is_sdvo && is_tv)
f47709a9 4753 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4754
eb1cbe48 4755 if (IS_GEN2(dev))
f47709a9 4756 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4757 has_reduced_clock ? &reduced_clock : NULL,
4758 num_connectors);
a0c4da24 4759 else if (IS_VALLEYVIEW(dev))
f47709a9 4760 vlv_update_pll(intel_crtc);
79e53945 4761 else
f47709a9 4762 i9xx_update_pll(intel_crtc,
eb1cbe48 4763 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4764 num_connectors);
79e53945 4765
79e53945
JB		 4766 /* Set up the display plane register */
4767 dspcntr = DISPPLANE_GAMMA_ENABLE;
4768
da6ecc5d
JB		 4769 if (!IS_VALLEYVIEW(dev)) {
4770 if (pipe == 0)
4771 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4772 else
4773 dspcntr |= DISPPLANE_SEL_PIPE_B;
4774 }
79e53945 4775
2582a850 4776 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4777 drm_mode_debug_printmodeline(mode);
4778
b0e77b9c 4779 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4780
4781 /* pipesrc and dspsize control the size that is scaled from,
4782 * which should always be the user's requested size.
79e53945 4783 */
929c77fb
EA		 4784 I915_WRITE(DSPSIZE(plane),
4785 ((mode->vdisplay - 1) << 16) |
4786 (mode->hdisplay - 1));
4787 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4788
84b046f3
DV		 4789 i9xx_set_pipeconf(intel_crtc);
4790
f564048e
EA		 4791 I915_WRITE(DSPCNTR(plane), dspcntr);
4792 POSTING_READ(DSPCNTR(plane));
4793
94352cf9 4794 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4795
4796 intel_update_watermarks(dev);
4797
f564048e
EA		 4798 return ret;
4799}
4800
0e8ffe1b
DV		 4801static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4802 struct intel_crtc_config *pipe_config)
4803{
4804 struct drm_device *dev = crtc->base.dev;
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 uint32_t tmp;
4807
4808 tmp = I915_READ(PIPECONF(crtc->pipe));
4809 if (!(tmp & PIPECONF_ENABLE))
4810 return false;
4811
4812 return true;
4813}
4814
dde86e2d 4815static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4816{
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4819 struct intel_encoder *encoder;
74cfd7ac 4820 u32 val, final;
13d83a67 4821 bool has_lvds = false;
199e5d79
KP		 4822 bool has_cpu_edp = false;
4823 bool has_pch_edp = false;
4824 bool has_panel = false;
99eb6a01
KP		 4825 bool has_ck505 = false;
4826 bool can_ssc = false;
13d83a67
JB		 4827
4828 /* We need to take the global config into account */
199e5d79
KP		 4829 list_for_each_entry(encoder, &mode_config->encoder_list,
4830 base.head) {
4831 switch (encoder->type) {
4832 case INTEL_OUTPUT_LVDS:
4833 has_panel = true;
4834 has_lvds = true;
4835 break;
4836 case INTEL_OUTPUT_EDP:
4837 has_panel = true;
4838 if (intel_encoder_is_pch_edp(&encoder->base))
4839 has_pch_edp = true;
4840 else
4841 has_cpu_edp = true;
4842 break;
13d83a67
JB		 4843 }
4844 }
4845
99eb6a01
KP		 4846 if (HAS_PCH_IBX(dev)) {
4847 has_ck505 = dev_priv->display_clock_mode;
4848 can_ssc = has_ck505;
4849 } else {
4850 has_ck505 = false;
4851 can_ssc = true;
4852 }
4853
4854 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4855 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4856 has_ck505);
13d83a67
JB		 4857
4858 /* Ironlake: try to setup display ref clock before DPLL
4859 * enabling. This is only under driver's control after
4860 * PCH B stepping, previous chipset stepping should be
4861 * ignoring this setting.
4862 */
74cfd7ac
CW		 4863 val = I915_READ(PCH_DREF_CONTROL);
4864
4865 /* As we must carefully and slowly disable/enable each source in turn,
4866 * compute the final state we want first and check if we need to
4867 * make any changes at all.
4868 */
4869 final = val;
4870 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4871 if (has_ck505)
4872 final |= DREF_NONSPREAD_CK505_ENABLE;
4873 else
4874 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4875
4876 final &= ~DREF_SSC_SOURCE_MASK;
4877 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4878 final &= ~DREF_SSC1_ENABLE;
4879
4880 if (has_panel) {
4881 final |= DREF_SSC_SOURCE_ENABLE;
4882
4883 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4884 final |= DREF_SSC1_ENABLE;
4885
4886 if (has_cpu_edp) {
4887 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4888 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4889 else
4890 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4891 } else
4892 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4893 } else {
4894 final |= DREF_SSC_SOURCE_DISABLE;
4895 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4896 }
4897
4898 if (final == val)
4899 return;
4900
13d83a67 4901 /* Always enable nonspread source */
74cfd7ac 4902 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4903
99eb6a01 4904 if (has_ck505)
74cfd7ac 4905 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4906 else
74cfd7ac 4907 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4908
199e5d79 4909 if (has_panel) {
74cfd7ac
CW		 4910 val &= ~DREF_SSC_SOURCE_MASK;
4911 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4912
199e5d79 4913 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4914 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4915 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4916 val |= DREF_SSC1_ENABLE;
e77166b5 4917 } else
74cfd7ac 4918 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4919
4920 /* Get SSC going before enabling the outputs */
74cfd7ac 4921 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4922 POSTING_READ(PCH_DREF_CONTROL);
4923 udelay(200);
4924
74cfd7ac 4925 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4926
4927 /* Enable CPU source on CPU attached eDP */
199e5d79 4928 if (has_cpu_edp) {
99eb6a01 4929 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4930 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4931 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4932 }
13d83a67 4933 else
74cfd7ac 4934 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4935 } else
74cfd7ac 4936 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4937
74cfd7ac 4938 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4939 POSTING_READ(PCH_DREF_CONTROL);
4940 udelay(200);
4941 } else {
4942 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4943
74cfd7ac 4944 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4945
4946 /* Turn off CPU output */
74cfd7ac 4947 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4948
74cfd7ac 4949 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4950 POSTING_READ(PCH_DREF_CONTROL);
4951 udelay(200);
4952
4953 /* Turn off the SSC source */
74cfd7ac
CW		 4954 val &= ~DREF_SSC_SOURCE_MASK;
4955 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4956
4957 /* Turn off SSC1 */
74cfd7ac 4958 val &= ~DREF_SSC1_ENABLE;
199e5d79 4959
74cfd7ac 4960 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4961 POSTING_READ(PCH_DREF_CONTROL);
4962 udelay(200);
4963 }
74cfd7ac
CW		 4964
4965 BUG_ON(val != final);
13d83a67
JB		 4966}
4967
dde86e2d
PZ		 4968/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4969static void lpt_init_pch_refclk(struct drm_device *dev)
4970{
4971 struct drm_i915_private *dev_priv = dev->dev_private;
4972 struct drm_mode_config *mode_config = &dev->mode_config;
4973 struct intel_encoder *encoder;
4974 bool has_vga = false;
4975 bool is_sdv = false;
4976 u32 tmp;
4977
4978 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4979 switch (encoder->type) {
4980 case INTEL_OUTPUT_ANALOG:
4981 has_vga = true;
4982 break;
4983 }
4984 }
4985
4986 if (!has_vga)
4987 return;
4988
c00db246
DV		 4989 mutex_lock(&dev_priv->dpio_lock);
4990
dde86e2d
PZ		 4991 /* XXX: Rip out SDV support once Haswell ships for real. */
4992 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4993 is_sdv = true;
4994
4995 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4996 tmp &= ~SBI_SSCCTL_DISABLE;
4997 tmp |= SBI_SSCCTL_PATHALT;
4998 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4999
5000 udelay(24);
5001
5002 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5003 tmp &= ~SBI_SSCCTL_PATHALT;
5004 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5005
5006 if (!is_sdv) {
5007 tmp = I915_READ(SOUTH_CHICKEN2);
5008 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5009 I915_WRITE(SOUTH_CHICKEN2, tmp);
5010
5011 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5012 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5013 DRM_ERROR("FDI mPHY reset assert timeout\n");
5014
5015 tmp = I915_READ(SOUTH_CHICKEN2);
5016 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5017 I915_WRITE(SOUTH_CHICKEN2, tmp);
5018
5019 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5020 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5021 100))
5022 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5023 }
5024
5025 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5026 tmp &= ~(0xFF << 24);
5027 tmp |= (0x12 << 24);
5028 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5029
dde86e2d
PZ		 5030 if (is_sdv) {
5031 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5032 tmp |= 0x7FFF;
5033 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5034 }
5035
5036 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5037 tmp |= (1 << 11);
5038 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5039
5040 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5041 tmp |= (1 << 11);
5042 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5043
5044 if (is_sdv) {
5045 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5046 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5047 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5048
5049 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5050 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5051 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5052
5053 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5054 tmp |= (0x3F << 8);
5055 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5056
5057 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5058 tmp |= (0x3F << 8);
5059 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5060 }
5061
5062 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5063 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5064 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5065
5066 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5067 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5068 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5069
5070 if (!is_sdv) {
5071 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5072 tmp &= ~(7 << 13);
5073 tmp |= (5 << 13);
5074 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5075
5076 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5077 tmp &= ~(7 << 13);
5078 tmp |= (5 << 13);
5079 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5080 }
5081
5082 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5083 tmp &= ~0xFF;
5084 tmp |= 0x1C;
5085 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5086
5087 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5088 tmp &= ~0xFF;
5089 tmp |= 0x1C;
5090 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5091
5092 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5093 tmp &= ~(0xFF << 16);
5094 tmp |= (0x1C << 16);
5095 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5096
5097 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5098 tmp &= ~(0xFF << 16);
5099 tmp |= (0x1C << 16);
5100 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5101
5102 if (!is_sdv) {
5103 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5104 tmp |= (1 << 27);
5105 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5106
5107 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5108 tmp |= (1 << 27);
5109 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5110
5111 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5112 tmp &= ~(0xF << 28);
5113 tmp |= (4 << 28);
5114 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5115
5116 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5117 tmp &= ~(0xF << 28);
5118 tmp |= (4 << 28);
5119 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5120 }
5121
5122 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5123 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5124 tmp |= SBI_DBUFF0_ENABLE;
5125 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5126
5127 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5128}
5129
5130/*
5131 * Initialize reference clocks when the driver loads
5132 */
5133void intel_init_pch_refclk(struct drm_device *dev)
5134{
5135 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5136 ironlake_init_pch_refclk(dev);
5137 else if (HAS_PCH_LPT(dev))
5138 lpt_init_pch_refclk(dev);
5139}
5140
d9d444cb
JB		 5141static int ironlake_get_refclk(struct drm_crtc *crtc)
5142{
5143 struct drm_device *dev = crtc->dev;
5144 struct drm_i915_private *dev_priv = dev->dev_private;
5145 struct intel_encoder *encoder;
d9d444cb
JB		 5146 struct intel_encoder *edp_encoder = NULL;
5147 int num_connectors = 0;
5148 bool is_lvds = false;
5149
6c2b7c12 5150 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5151 switch (encoder->type) {
5152 case INTEL_OUTPUT_LVDS:
5153 is_lvds = true;
5154 break;
5155 case INTEL_OUTPUT_EDP:
5156 edp_encoder = encoder;
5157 break;
5158 }
5159 num_connectors++;
5160 }
5161
5162 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5163 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5164 dev_priv->lvds_ssc_freq);
5165 return dev_priv->lvds_ssc_freq * 1000;
5166 }
5167
5168 return 120000;
5169}
5170
6ff93609 5171static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5172{
c8203565 5173 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175 int pipe = intel_crtc->pipe;
c8203565
PZ		 5176 uint32_t val;
5177
5178 val = I915_READ(PIPECONF(pipe));
5179
dfd07d72 5180 val &= ~PIPECONF_BPC_MASK;
965e0c48 5181 switch (intel_crtc->config.pipe_bpp) {
c8203565 5182 case 18:
dfd07d72 5183 val |= PIPECONF_6BPC;
c8203565
PZ		 5184 break;
5185 case 24:
dfd07d72 5186 val |= PIPECONF_8BPC;
c8203565
PZ		 5187 break;
5188 case 30:
dfd07d72 5189 val |= PIPECONF_10BPC;
c8203565
PZ		 5190 break;
5191 case 36:
dfd07d72 5192 val |= PIPECONF_12BPC;
c8203565
PZ		 5193 break;
5194 default:
cc769b62
PZ		 5195 /* Case prevented by intel_choose_pipe_bpp_dither. */
5196 BUG();
c8203565
PZ		 5197 }
5198
5199 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5200 if (intel_crtc->config.dither)
c8203565
PZ		 5201 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5202
5203 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5204 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5205 val |= PIPECONF_INTERLACED_ILK;
5206 else
5207 val |= PIPECONF_PROGRESSIVE;
5208
50f3b016 5209 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5210 val |= PIPECONF_COLOR_RANGE_SELECT;
5211 else
5212 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5213
c8203565
PZ		 5214 I915_WRITE(PIPECONF(pipe), val);
5215 POSTING_READ(PIPECONF(pipe));
5216}
5217
86d3efce
VS		 5218/*
5219 * Set up the pipe CSC unit.
5220 *
5221 * Currently only full range RGB to limited range RGB conversion
5222 * is supported, but eventually this should handle various
5223 * RGB<->YCbCr scenarios as well.
5224 */
50f3b016 5225static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5226{
5227 struct drm_device *dev = crtc->dev;
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5230 int pipe = intel_crtc->pipe;
5231 uint16_t coeff = 0x7800; /* 1.0 */
5232
5233 /*
5234 * TODO: Check what kind of values actually come out of the pipe
5235 * with these coeff/postoff values and adjust to get the best
5236 * accuracy. Perhaps we even need to take the bpc value into
5237 * consideration.
5238 */
5239
50f3b016 5240 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5241 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5242
5243 /*
5244 * GY/GU and RY/RU should be the other way around according
5245 * to BSpec, but reality doesn't agree. Just set them up in
5246 * a way that results in the correct picture.
5247 */
5248 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5249 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5250
5251 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5252 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5253
5254 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5255 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5256
5257 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5258 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5259 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5260
5261 if (INTEL_INFO(dev)->gen > 6) {
5262 uint16_t postoff = 0;
5263
50f3b016 5264 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5265 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5266
5267 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5268 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5269 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5270
5271 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5272 } else {
5273 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5274
50f3b016 5275 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5276 mode |= CSC_BLACK_SCREEN_OFFSET;
5277
5278 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5279 }
5280}
5281
6ff93609 5282static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5283{
5284 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5286 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5287 uint32_t val;
5288
702e7a56 5289 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5290
5291 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5292 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5293 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5294
5295 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5296 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5297 val |= PIPECONF_INTERLACED_ILK;
5298 else
5299 val |= PIPECONF_PROGRESSIVE;
5300
702e7a56
PZ		 5301 I915_WRITE(PIPECONF(cpu_transcoder), val);
5302 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5303}
5304
6591c6e4
PZ		 5305static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5306 struct drm_display_mode *adjusted_mode,
5307 intel_clock_t *clock,
5308 bool *has_reduced_clock,
5309 intel_clock_t *reduced_clock)
5310{
5311 struct drm_device *dev = crtc->dev;
5312 struct drm_i915_private *dev_priv = dev->dev_private;
5313 struct intel_encoder *intel_encoder;
5314 int refclk;
d4906093 5315 const intel_limit_t *limit;
6591c6e4 5316 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5317
6591c6e4
PZ		 5318 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5319 switch (intel_encoder->type) {
79e53945
JB		 5320 case INTEL_OUTPUT_LVDS:
5321 is_lvds = true;
5322 break;
5323 case INTEL_OUTPUT_SDVO:
7d57382e 5324 case INTEL_OUTPUT_HDMI:
79e53945 5325 is_sdvo = true;
6591c6e4 5326 if (intel_encoder->needs_tv_clock)
e2f0ba97 5327 is_tv = true;
79e53945 5328 break;
79e53945
JB		 5329 case INTEL_OUTPUT_TVOUT:
5330 is_tv = true;
5331 break;
79e53945
JB		 5332 }
5333 }
5334
d9d444cb 5335 refclk = ironlake_get_refclk(crtc);
79e53945 5336
d4906093
ML		 5337 /*
5338 * Returns a set of divisors for the desired target clock with the given
5339 * refclk, or FALSE. The returned values represent the clock equation:
5340 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5341 */
1b894b59 5342 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5343 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5344 clock);
5345 if (!ret)
5346 return false;
cda4b7d3 5347
ddc9003c 5348 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5349 /*
5350 * Ensure we match the reduced clock's P to the target clock.
5351 * If the clocks don't match, we can't switch the display clock
5352 * by using the FP0/FP1. In such case we will disable the LVDS
5353 * downclock feature.
5354 */
6591c6e4
PZ		 5355 *has_reduced_clock = limit->find_pll(limit, crtc,
5356 dev_priv->lvds_downclock,
5357 refclk,
5358 clock,
5359 reduced_clock);
652c393a 5360 }
61e9653f
DV		 5361
5362 if (is_sdvo && is_tv)
f47709a9 5363 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5364
5365 return true;
5366}
5367
01a415fd
DV		 5368static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5369{
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371 uint32_t temp;
5372
5373 temp = I915_READ(SOUTH_CHICKEN1);
5374 if (temp & FDI_BC_BIFURCATION_SELECT)
5375 return;
5376
5377 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5378 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5379
5380 temp |= FDI_BC_BIFURCATION_SELECT;
5381 DRM_DEBUG_KMS("enabling fdi C rx\n");
5382 I915_WRITE(SOUTH_CHICKEN1, temp);
5383 POSTING_READ(SOUTH_CHICKEN1);
5384}
5385
5386static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5387{
5388 struct drm_device *dev = intel_crtc->base.dev;
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390 struct intel_crtc *pipe_B_crtc =
5391 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5392
84f44ce7
VS		 5393 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5394 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd 5395 if (intel_crtc->fdi_lanes > 4) {
84f44ce7
VS		 5396 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5397 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5398 /* Clamp lanes to avoid programming the hw with bogus values. */
5399 intel_crtc->fdi_lanes = 4;
5400
5401 return false;
5402 }
5403
7eb552ae 5404 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5405 return true;
5406
5407 switch (intel_crtc->pipe) {
5408 case PIPE_A:
5409 return true;
5410 case PIPE_B:
5411 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5412 intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5413 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5414 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5415 /* Clamp lanes to avoid programming the hw with bogus values. */
5416 intel_crtc->fdi_lanes = 2;
5417
5418 return false;
5419 }
5420
5421 if (intel_crtc->fdi_lanes > 2)
5422 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5423 else
5424 cpt_enable_fdi_bc_bifurcation(dev);
5425
5426 return true;
5427 case PIPE_C:
5428 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5429 if (intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5430 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5431 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5432 /* Clamp lanes to avoid programming the hw with bogus values. */
5433 intel_crtc->fdi_lanes = 2;
5434
5435 return false;
5436 }
5437 } else {
5438 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5439 return false;
5440 }
5441
5442 cpt_enable_fdi_bc_bifurcation(dev);
5443
5444 return true;
5445 default:
5446 BUG();
5447 }
5448}
5449
d4b1931c
PZ		 5450int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5451{
5452 /*
5453 * Account for spread spectrum to avoid
5454 * oversubscribing the link. Max center spread
5455 * is 2.5%; use 5% for safety's sake.
5456 */
5457 u32 bps = target_clock * bpp * 21 / 20;
5458 return bps / (link_bw * 8) + 1;
5459}
5460
6cf86a5e
DV		 5461void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5462 struct intel_link_m_n *m_n)
79e53945 5463{
6cf86a5e
DV		 5464 struct drm_device *dev = crtc->base.dev;
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 int pipe = crtc->pipe;
5467
5468 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5469 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5470 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5471 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5472}
5473
5474void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5475 struct intel_link_m_n *m_n)
5476{
5477 struct drm_device *dev = crtc->base.dev;
79e53945 5478 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5479 int pipe = crtc->pipe;
3b117c8f 5480 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5481
5482 if (INTEL_INFO(dev)->gen >= 5) {
5483 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5484 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5485 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5486 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5487 } else {
5488 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5489 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5490 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5491 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5492 }
5493}
5494
5495static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5496{
5497 struct drm_device *dev = crtc->dev;
79e53945 5498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5499 struct drm_display_mode *adjusted_mode =
5500 &intel_crtc->config.adjusted_mode;
e69d0bc1 5501 struct intel_link_m_n m_n = {0};
6cc5f341 5502 int target_clock, lane, link_bw;
61e9653f 5503
6cf86a5e
DV		 5504 /* FDI is a binary signal running at ~2.7GHz, encoding
5505 * each output octet as 10 bits. The actual frequency
5506 * is stored as a divider into a 100MHz clock, and the
5507 * mode pixel clock is stored in units of 1KHz.
5508 * Hence the bw of each lane in terms of the mode signal
5509 * is:
5510 */
5511 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5512
df92b1e6
DV		 5513 if (intel_crtc->config.pixel_target_clock)
5514 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5515 else
5516 target_clock = adjusted_mode->clock;
5517
6cf86a5e
DV		 5518 lane = ironlake_get_lanes_required(target_clock, link_bw,
5519 intel_crtc->config.pipe_bpp);
2c07245f 5520
8febb297
EA		 5521 intel_crtc->fdi_lanes = lane;
5522
6cc5f341
DV		 5523 if (intel_crtc->config.pixel_multiplier > 1)
5524 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5525 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5526 link_bw, &m_n);
8febb297 5527
6cf86a5e 5528 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5529}
5530
7429e9d4
DV		 5531static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5532{
5533 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5534}
5535
de13a2e3 5536static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5537 u32 *fp,
9a7c7890 5538 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5539{
de13a2e3 5540 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5541 struct drm_device *dev = crtc->dev;
5542 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5543 struct intel_encoder *intel_encoder;
5544 uint32_t dpll;
6cc5f341 5545 int factor, num_connectors = 0;
de13a2e3 5546 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5547
de13a2e3
PZ		 5548 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5549 switch (intel_encoder->type) {
79e53945
JB		 5550 case INTEL_OUTPUT_LVDS:
5551 is_lvds = true;
5552 break;
5553 case INTEL_OUTPUT_SDVO:
7d57382e 5554 case INTEL_OUTPUT_HDMI:
79e53945 5555 is_sdvo = true;
de13a2e3 5556 if (intel_encoder->needs_tv_clock)
e2f0ba97 5557 is_tv = true;
79e53945 5558 break;
79e53945
JB		 5559 case INTEL_OUTPUT_TVOUT:
5560 is_tv = true;
5561 break;
79e53945 5562 }
43565a06 5563
c751ce4f 5564 num_connectors++;
79e53945 5565 }
79e53945 5566
c1858123 5567 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5568 factor = 21;
5569 if (is_lvds) {
5570 if ((intel_panel_use_ssc(dev_priv) &&
5571 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5572 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5573 factor = 25;
5574 } else if (is_sdvo && is_tv)
5575 factor = 20;
c1858123 5576
7429e9d4 5577 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5578 *fp |= FP_CB_TUNE;
2c07245f 5579
9a7c7890
DV		 5580 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5581 *fp2 |= FP_CB_TUNE;
5582
5eddb70b 5583 dpll = 0;
2c07245f 5584
a07d6787
EA		 5585 if (is_lvds)
5586 dpll |= DPLLB_MODE_LVDS;
5587 else
5588 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5589
5590 if (intel_crtc->config.pixel_multiplier > 1) {
5591 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5592 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5593 }
198a037f
DV		 5594
5595 if (is_sdvo)
5596 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5597 if (intel_crtc->config.has_dp_encoder)
a07d6787 5598 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5599
a07d6787 5600 /* compute bitmask from p1 value */
7429e9d4 5601 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5602 /* also FPA1 */
7429e9d4 5603 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5604
7429e9d4 5605 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5606 case 5:
5607 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5608 break;
5609 case 7:
5610 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5611 break;
5612 case 10:
5613 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5614 break;
5615 case 14:
5616 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5617 break;
79e53945
JB		 5618 }
5619
43565a06
KH		 5620 if (is_sdvo && is_tv)
5621 dpll |= PLL_REF_INPUT_TVCLKINBC;
5622 else if (is_tv)
79e53945 5623 /* XXX: just matching BIOS for now */
43565a06 5624 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5625 dpll |= 3;
a7615030 5626 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5627 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5628 else
5629 dpll |= PLL_REF_INPUT_DREFCLK;
5630
de13a2e3
PZ		 5631 return dpll;
5632}
5633
5634static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5635 int x, int y,
5636 struct drm_framebuffer *fb)
5637{
5638 struct drm_device *dev = crtc->dev;
5639 struct drm_i915_private *dev_priv = dev->dev_private;
5640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5641 struct drm_display_mode *adjusted_mode =
5642 &intel_crtc->config.adjusted_mode;
5643 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5644 int pipe = intel_crtc->pipe;
5645 int plane = intel_crtc->plane;
5646 int num_connectors = 0;
5647 intel_clock_t clock, reduced_clock;
cbbab5bd 5648 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5649 bool ok, has_reduced_clock = false;
8b47047b 5650 bool is_lvds = false;
de13a2e3 5651 struct intel_encoder *encoder;
de13a2e3 5652 int ret;
d8b32247 5653 bool fdi_config_ok;
de13a2e3
PZ		 5654
5655 for_each_encoder_on_crtc(dev, crtc, encoder) {
5656 switch (encoder->type) {
5657 case INTEL_OUTPUT_LVDS:
5658 is_lvds = true;
5659 break;
de13a2e3
PZ		 5660 }
5661
5662 num_connectors++;
a07d6787 5663 }
79e53945 5664
5dc5298b
PZ		 5665 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5666 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5667
3b117c8f 5668 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5669
de13a2e3
PZ		 5670 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5671 &has_reduced_clock, &reduced_clock);
5672 if (!ok) {
5673 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5674 return -EINVAL;
79e53945 5675 }
f47709a9
DV		 5676 /* Compat-code for transition, will disappear. */
5677 if (!intel_crtc->config.clock_set) {
5678 intel_crtc->config.dpll.n = clock.n;
5679 intel_crtc->config.dpll.m1 = clock.m1;
5680 intel_crtc->config.dpll.m2 = clock.m2;
5681 intel_crtc->config.dpll.p1 = clock.p1;
5682 intel_crtc->config.dpll.p2 = clock.p2;
5683 }
79e53945 5684
de13a2e3
PZ		 5685 /* Ensure that the cursor is valid for the new mode before changing... */
5686 intel_crtc_update_cursor(crtc, true);
5687
84f44ce7 5688 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5689 drm_mode_debug_printmodeline(mode);
5690
5dc5298b 5691 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5692 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5693 struct intel_pch_pll *pll;
4b645f14 5694
7429e9d4 5695 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5696 if (has_reduced_clock)
7429e9d4 5697 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5698
7429e9d4 5699 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5700 &fp, &reduced_clock,
5701 has_reduced_clock ? &fp2 : NULL);
5702
ee7b9f93
JB		 5703 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5704 if (pll == NULL) {
84f44ce7
VS		 5705 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5706 pipe_name(pipe));
4b645f14
JB		 5707 return -EINVAL;
5708 }
ee7b9f93
JB		 5709 } else
5710 intel_put_pch_pll(intel_crtc);
79e53945 5711
03afc4a2
DV		 5712 if (intel_crtc->config.has_dp_encoder)
5713 intel_dp_set_m_n(intel_crtc);
79e53945 5714
dafd226c
DV		 5715 for_each_encoder_on_crtc(dev, crtc, encoder)
5716 if (encoder->pre_pll_enable)
5717 encoder->pre_pll_enable(encoder);
79e53945 5718
ee7b9f93
JB		 5719 if (intel_crtc->pch_pll) {
5720 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5721
32f9d658 5722 /* Wait for the clocks to stabilize. */
ee7b9f93 5723 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5724 udelay(150);
5725
8febb297
EA		 5726 /* The pixel multiplier can only be updated once the
5727 * DPLL is enabled and the clocks are stable.
5728 *
5729 * So write it again.
5730 */
ee7b9f93 5731 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5732 }
79e53945 5733
5eddb70b 5734 intel_crtc->lowfreq_avail = false;
ee7b9f93 5735 if (intel_crtc->pch_pll) {
4b645f14 5736 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5737 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5738 intel_crtc->lowfreq_avail = true;
4b645f14 5739 } else {
ee7b9f93 5740 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5741 }
5742 }
5743
b0e77b9c 5744 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5745
01a415fd
DV		 5746 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5747 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5748 intel_crtc->fdi_lanes = 0;
5749 if (intel_crtc->config.has_pch_encoder)
5750 ironlake_fdi_set_m_n(crtc);
2c07245f 5751
01a415fd 5752 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5753
6ff93609 5754 ironlake_set_pipeconf(crtc);
79e53945 5755
a1f9e77e
PZ		 5756 /* Set up the display plane register */
5757 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5758 POSTING_READ(DSPCNTR(plane));
79e53945 5759
94352cf9 5760 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5761
5762 intel_update_watermarks(dev);
5763
1f8eeabf
ED		 5764 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5765
01a415fd 5766 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5767}
5768
0e8ffe1b
DV		 5769static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5770 struct intel_crtc_config *pipe_config)
5771{
5772 struct drm_device *dev = crtc->base.dev;
5773 struct drm_i915_private *dev_priv = dev->dev_private;
5774 uint32_t tmp;
5775
5776 tmp = I915_READ(PIPECONF(crtc->pipe));
5777 if (!(tmp & PIPECONF_ENABLE))
5778 return false;
5779
88adfff1
DV		 5780 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5781 pipe_config->has_pch_encoder = true;
5782
0e8ffe1b
DV		 5783 return true;
5784}
5785
d6dd9eb1
DV		 5786static void haswell_modeset_global_resources(struct drm_device *dev)
5787{
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 bool enable = false;
5790 struct intel_crtc *crtc;
5791 struct intel_encoder *encoder;
5792
5793 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5794 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5795 enable = true;
5796 /* XXX: Should check for edp transcoder here, but thanks to init
5797 * sequence that's not yet available. Just in case desktop eDP
5798 * on PORT D is possible on haswell, too. */
b074cec8
JB		 5799 /* Even the eDP panel fitter is outside the always-on well. */
5800 if (I915_READ(PF_WIN_SZ(crtc->pipe)))
5801 enable = true;
d6dd9eb1
DV		 5802 }
5803
5804 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5805 base.head) {
5806 if (encoder->type != INTEL_OUTPUT_EDP &&
5807 encoder->connectors_active)
5808 enable = true;
5809 }
5810
d6dd9eb1
DV		 5811 intel_set_power_well(dev, enable);
5812}
5813
09b4ddf9 5814static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5815 int x, int y,
5816 struct drm_framebuffer *fb)
5817{
5818 struct drm_device *dev = crtc->dev;
5819 struct drm_i915_private *dev_priv = dev->dev_private;
5820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5821 struct drm_display_mode *adjusted_mode =
5822 &intel_crtc->config.adjusted_mode;
5823 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5824 int pipe = intel_crtc->pipe;
5825 int plane = intel_crtc->plane;
5826 int num_connectors = 0;
8b47047b 5827 bool is_cpu_edp = false;
09b4ddf9 5828 struct intel_encoder *encoder;
09b4ddf9 5829 int ret;
09b4ddf9
PZ		 5830
5831 for_each_encoder_on_crtc(dev, crtc, encoder) {
5832 switch (encoder->type) {
09b4ddf9 5833 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5834 if (!intel_encoder_is_pch_edp(&encoder->base))
5835 is_cpu_edp = true;
5836 break;
5837 }
5838
5839 num_connectors++;
5840 }
5841
bba2181c 5842 if (is_cpu_edp)
3b117c8f 5843 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5844 else
3b117c8f 5845 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5846
5dc5298b
PZ		 5847 /* We are not sure yet this won't happen. */
5848 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5849 INTEL_PCH_TYPE(dev));
5850
5851 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5852 num_connectors, pipe_name(pipe));
5853
3b117c8f 5854 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5855 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5856
5857 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5858
6441ab5f
PZ		 5859 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5860 return -EINVAL;
5861
09b4ddf9
PZ		 5862 /* Ensure that the cursor is valid for the new mode before changing... */
5863 intel_crtc_update_cursor(crtc, true);
5864
84f44ce7 5865 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5866 drm_mode_debug_printmodeline(mode);
5867
03afc4a2
DV		 5868 if (intel_crtc->config.has_dp_encoder)
5869 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5870
5871 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5872
5873 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5874
6cf86a5e
DV		 5875 if (intel_crtc->config.has_pch_encoder)
5876 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5877
6ff93609 5878 haswell_set_pipeconf(crtc);
09b4ddf9 5879
50f3b016 5880 intel_set_pipe_csc(crtc);
86d3efce 5881
09b4ddf9 5882 /* Set up the display plane register */
86d3efce 5883 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5884 POSTING_READ(DSPCNTR(plane));
5885
5886 ret = intel_pipe_set_base(crtc, x, y, fb);
5887
5888 intel_update_watermarks(dev);
5889
5890 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5891
1f803ee5 5892 return ret;
79e53945
JB		 5893}
5894
0e8ffe1b
DV		 5895static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5896 struct intel_crtc_config *pipe_config)
5897{
5898 struct drm_device *dev = crtc->base.dev;
5899 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5900 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5901 uint32_t tmp;
5902
2bfce950
PZ		 5903 if (!intel_using_power_well(dev_priv->dev) &&
5904 cpu_transcoder != TRANSCODER_EDP)
5905 return false;
5906
5907 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5908 if (!(tmp & PIPECONF_ENABLE))
5909 return false;
5910
88adfff1 5911 /*
f196e6be 5912 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5913 * DDI E. So just check whether this pipe is wired to DDI E and whether
5914 * the PCH transcoder is on.
5915 */
f196e6be 5916 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1
DV		 5917 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5918 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5919 pipe_config->has_pch_encoder = true;
5920
0e8ffe1b
DV		 5921 return true;
5922}
5923
f564048e 5924static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5925 int x, int y,
94352cf9 5926 struct drm_framebuffer *fb)
f564048e
EA		 5927{
5928 struct drm_device *dev = crtc->dev;
5929 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5930 struct drm_encoder_helper_funcs *encoder_funcs;
5931 struct intel_encoder *encoder;
0b701d27 5932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5933 struct drm_display_mode *adjusted_mode =
5934 &intel_crtc->config.adjusted_mode;
5935 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5936 int pipe = intel_crtc->pipe;
f564048e
EA		 5937 int ret;
5938
0b701d27 5939 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5940
b8cecdf5
DV		 5941 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5942
79e53945 5943 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5944
9256aa19
DV		 5945 if (ret != 0)
5946 return ret;
5947
5948 for_each_encoder_on_crtc(dev, crtc, encoder) {
5949 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5950 encoder->base.base.id,
5951 drm_get_encoder_name(&encoder->base),
5952 mode->base.id, mode->name);
6cc5f341
DV		 5953 if (encoder->mode_set) {
5954 encoder->mode_set(encoder);
5955 } else {
5956 encoder_funcs = encoder->base.helper_private;
5957 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5958 }
9256aa19
DV		 5959 }
5960
5961 return 0;
79e53945
JB		 5962}
5963
3a9627f4
WF		 5964static bool intel_eld_uptodate(struct drm_connector *connector,
5965 int reg_eldv, uint32_t bits_eldv,
5966 int reg_elda, uint32_t bits_elda,
5967 int reg_edid)
5968{
5969 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5970 uint8_t *eld = connector->eld;
5971 uint32_t i;
5972
5973 i = I915_READ(reg_eldv);
5974 i &= bits_eldv;
5975
5976 if (!eld[0])
5977 return !i;
5978
5979 if (!i)
5980 return false;
5981
5982 i = I915_READ(reg_elda);
5983 i &= ~bits_elda;
5984 I915_WRITE(reg_elda, i);
5985
5986 for (i = 0; i < eld[2]; i++)
5987 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5988 return false;
5989
5990 return true;
5991}
5992
e0dac65e
WF		 5993static void g4x_write_eld(struct drm_connector *connector,
5994 struct drm_crtc *crtc)
5995{
5996 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5997 uint8_t *eld = connector->eld;
5998 uint32_t eldv;
5999 uint32_t len;
6000 uint32_t i;
6001
6002 i = I915_READ(G4X_AUD_VID_DID);
6003
6004 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6005 eldv = G4X_ELDV_DEVCL_DEVBLC;
6006 else
6007 eldv = G4X_ELDV_DEVCTG;
6008
3a9627f4
WF		 6009 if (intel_eld_uptodate(connector,
6010 G4X_AUD_CNTL_ST, eldv,
6011 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6012 G4X_HDMIW_HDMIEDID))
6013 return;
6014
e0dac65e
WF		 6015 i = I915_READ(G4X_AUD_CNTL_ST);
6016 i &= ~(eldv | G4X_ELD_ADDR);
6017 len = (i >> 9) & 0x1f; /* ELD buffer size */
6018 I915_WRITE(G4X_AUD_CNTL_ST, i);
6019
6020 if (!eld[0])
6021 return;
6022
6023 len = min_t(uint8_t, eld[2], len);
6024 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6025 for (i = 0; i < len; i++)
6026 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6027
6028 i = I915_READ(G4X_AUD_CNTL_ST);
6029 i |= eldv;
6030 I915_WRITE(G4X_AUD_CNTL_ST, i);
6031}
6032
83358c85
WX		 6033static void haswell_write_eld(struct drm_connector *connector,
6034 struct drm_crtc *crtc)
6035{
6036 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6037 uint8_t *eld = connector->eld;
6038 struct drm_device *dev = crtc->dev;
7b9f35a6 6039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6040 uint32_t eldv;
6041 uint32_t i;
6042 int len;
6043 int pipe = to_intel_crtc(crtc)->pipe;
6044 int tmp;
6045
6046 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6047 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6048 int aud_config = HSW_AUD_CFG(pipe);
6049 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6050
6051
6052 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6053
6054 /* Audio output enable */
6055 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6056 tmp = I915_READ(aud_cntrl_st2);
6057 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6058 I915_WRITE(aud_cntrl_st2, tmp);
6059
6060 /* Wait for 1 vertical blank */
6061 intel_wait_for_vblank(dev, pipe);
6062
6063 /* Set ELD valid state */
6064 tmp = I915_READ(aud_cntrl_st2);
6065 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6066 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6067 I915_WRITE(aud_cntrl_st2, tmp);
6068 tmp = I915_READ(aud_cntrl_st2);
6069 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6070
6071 /* Enable HDMI mode */
6072 tmp = I915_READ(aud_config);
6073 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6074 /* clear N_programing_enable and N_value_index */
6075 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6076 I915_WRITE(aud_config, tmp);
6077
6078 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6079
6080 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6081 intel_crtc->eld_vld = true;
83358c85
WX		 6082
6083 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6084 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6085 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6086 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6087 } else
6088 I915_WRITE(aud_config, 0);
6089
6090 if (intel_eld_uptodate(connector,
6091 aud_cntrl_st2, eldv,
6092 aud_cntl_st, IBX_ELD_ADDRESS,
6093 hdmiw_hdmiedid))
6094 return;
6095
6096 i = I915_READ(aud_cntrl_st2);
6097 i &= ~eldv;
6098 I915_WRITE(aud_cntrl_st2, i);
6099
6100 if (!eld[0])
6101 return;
6102
6103 i = I915_READ(aud_cntl_st);
6104 i &= ~IBX_ELD_ADDRESS;
6105 I915_WRITE(aud_cntl_st, i);
6106 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6107 DRM_DEBUG_DRIVER("port num:%d\n", i);
6108
6109 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6110 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6111 for (i = 0; i < len; i++)
6112 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6113
6114 i = I915_READ(aud_cntrl_st2);
6115 i |= eldv;
6116 I915_WRITE(aud_cntrl_st2, i);
6117
6118}
6119
e0dac65e
WF		 6120static void ironlake_write_eld(struct drm_connector *connector,
6121 struct drm_crtc *crtc)
6122{
6123 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6124 uint8_t *eld = connector->eld;
6125 uint32_t eldv;
6126 uint32_t i;
6127 int len;
6128 int hdmiw_hdmiedid;
b6daa025 6129 int aud_config;
e0dac65e
WF		 6130 int aud_cntl_st;
6131 int aud_cntrl_st2;
9b138a83 6132 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6133
b3f33cbf 6134 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6135 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6136 aud_config = IBX_AUD_CFG(pipe);
6137 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6138 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6139 } else {
9b138a83
WX		 6140 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6141 aud_config = CPT_AUD_CFG(pipe);
6142 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6143 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6144 }
6145
9b138a83 6146 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6147
6148 i = I915_READ(aud_cntl_st);
9b138a83 6149 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6150 if (!i) {
6151 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6152 /* operate blindly on all ports */
1202b4c6
WF		 6153 eldv = IBX_ELD_VALIDB;
6154 eldv |= IBX_ELD_VALIDB << 4;
6155 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6156 } else {
2582a850 6157 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6158 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6159 }
6160
3a9627f4
WF		 6161 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6162 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6163 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6164 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6165 } else
6166 I915_WRITE(aud_config, 0);
e0dac65e 6167
3a9627f4
WF		 6168 if (intel_eld_uptodate(connector,
6169 aud_cntrl_st2, eldv,
6170 aud_cntl_st, IBX_ELD_ADDRESS,
6171 hdmiw_hdmiedid))
6172 return;
6173
e0dac65e
WF		 6174 i = I915_READ(aud_cntrl_st2);
6175 i &= ~eldv;
6176 I915_WRITE(aud_cntrl_st2, i);
6177
6178 if (!eld[0])
6179 return;
6180
e0dac65e 6181 i = I915_READ(aud_cntl_st);
1202b4c6 6182 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6183 I915_WRITE(aud_cntl_st, i);
6184
6185 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6186 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6187 for (i = 0; i < len; i++)
6188 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6189
6190 i = I915_READ(aud_cntrl_st2);
6191 i |= eldv;
6192 I915_WRITE(aud_cntrl_st2, i);
6193}
6194
6195void intel_write_eld(struct drm_encoder *encoder,
6196 struct drm_display_mode *mode)
6197{
6198 struct drm_crtc *crtc = encoder->crtc;
6199 struct drm_connector *connector;
6200 struct drm_device *dev = encoder->dev;
6201 struct drm_i915_private *dev_priv = dev->dev_private;
6202
6203 connector = drm_select_eld(encoder, mode);
6204 if (!connector)
6205 return;
6206
6207 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6208 connector->base.id,
6209 drm_get_connector_name(connector),
6210 connector->encoder->base.id,
6211 drm_get_encoder_name(connector->encoder));
6212
6213 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6214
6215 if (dev_priv->display.write_eld)
6216 dev_priv->display.write_eld(connector, crtc);
6217}
6218
79e53945
JB		 6219/** Loads the palette/gamma unit for the CRTC with the prepared values */
6220void intel_crtc_load_lut(struct drm_crtc *crtc)
6221{
6222 struct drm_device *dev = crtc->dev;
6223 struct drm_i915_private *dev_priv = dev->dev_private;
6224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6225 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6226 int i;
6227
6228 /* The clocks have to be on to load the palette. */
aed3f09d 6229 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6230 return;
6231
f2b115e6 6232 /* use legacy palette for Ironlake */
bad720ff 6233 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6234 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6235
79e53945
JB		 6236 for (i = 0; i < 256; i++) {
6237 I915_WRITE(palreg + 4 * i,
6238 (intel_crtc->lut_r[i] << 16) |
6239 (intel_crtc->lut_g[i] << 8) |
6240 intel_crtc->lut_b[i]);
6241 }
6242}
6243
560b85bb
CW		 6244static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6245{
6246 struct drm_device *dev = crtc->dev;
6247 struct drm_i915_private *dev_priv = dev->dev_private;
6248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249 bool visible = base != 0;
6250 u32 cntl;
6251
6252 if (intel_crtc->cursor_visible == visible)
6253 return;
6254
9db4a9c7 6255 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6256 if (visible) {
6257 /* On these chipsets we can only modify the base whilst
6258 * the cursor is disabled.
6259 */
9db4a9c7 6260 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6261
6262 cntl &= ~(CURSOR_FORMAT_MASK);
6263 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6264 cntl |= CURSOR_ENABLE |
6265 CURSOR_GAMMA_ENABLE |
6266 CURSOR_FORMAT_ARGB;
6267 } else
6268 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6269 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6270
6271 intel_crtc->cursor_visible = visible;
6272}
6273
6274static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6275{
6276 struct drm_device *dev = crtc->dev;
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279 int pipe = intel_crtc->pipe;
6280 bool visible = base != 0;
6281
6282 if (intel_crtc->cursor_visible != visible) {
548f245b 6283 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6284 if (base) {
6285 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6286 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6287 cntl |= pipe << 28; /* Connect to correct pipe */
6288 } else {
6289 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6290 cntl |= CURSOR_MODE_DISABLE;
6291 }
9db4a9c7 6292 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6293
6294 intel_crtc->cursor_visible = visible;
6295 }
6296 /* and commit changes on next vblank */
9db4a9c7 6297 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6298}
6299
65a21cd6
JB		 6300static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6301{
6302 struct drm_device *dev = crtc->dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6305 int pipe = intel_crtc->pipe;
6306 bool visible = base != 0;
6307
6308 if (intel_crtc->cursor_visible != visible) {
6309 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6310 if (base) {
6311 cntl &= ~CURSOR_MODE;
6312 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6313 } else {
6314 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6315 cntl |= CURSOR_MODE_DISABLE;
6316 }
86d3efce
VS		 6317 if (IS_HASWELL(dev))
6318 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6319 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6320
6321 intel_crtc->cursor_visible = visible;
6322 }
6323 /* and commit changes on next vblank */
6324 I915_WRITE(CURBASE_IVB(pipe), base);
6325}
6326
cda4b7d3 6327/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6328static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6329 bool on)
cda4b7d3
CW		 6330{
6331 struct drm_device *dev = crtc->dev;
6332 struct drm_i915_private *dev_priv = dev->dev_private;
6333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334 int pipe = intel_crtc->pipe;
6335 int x = intel_crtc->cursor_x;
6336 int y = intel_crtc->cursor_y;
560b85bb 6337 u32 base, pos;
cda4b7d3
CW		 6338 bool visible;
6339
6340 pos = 0;
6341
6b383a7f 6342 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6343 base = intel_crtc->cursor_addr;
6344 if (x > (int) crtc->fb->width)
6345 base = 0;
6346
6347 if (y > (int) crtc->fb->height)
6348 base = 0;
6349 } else
6350 base = 0;
6351
6352 if (x < 0) {
6353 if (x + intel_crtc->cursor_width < 0)
6354 base = 0;
6355
6356 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6357 x = -x;
6358 }
6359 pos |= x << CURSOR_X_SHIFT;
6360
6361 if (y < 0) {
6362 if (y + intel_crtc->cursor_height < 0)
6363 base = 0;
6364
6365 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6366 y = -y;
6367 }
6368 pos |= y << CURSOR_Y_SHIFT;
6369
6370 visible = base != 0;
560b85bb 6371 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6372 return;
6373
0cd83aa9 6374 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6375 I915_WRITE(CURPOS_IVB(pipe), pos);
6376 ivb_update_cursor(crtc, base);
6377 } else {
6378 I915_WRITE(CURPOS(pipe), pos);
6379 if (IS_845G(dev) || IS_I865G(dev))
6380 i845_update_cursor(crtc, base);
6381 else
6382 i9xx_update_cursor(crtc, base);
6383 }
cda4b7d3
CW		 6384}
6385
79e53945 6386static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6387 struct drm_file *file,
79e53945
JB		 6388 uint32_t handle,
6389 uint32_t width, uint32_t height)
6390{
6391 struct drm_device *dev = crtc->dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6394 struct drm_i915_gem_object *obj;
cda4b7d3 6395 uint32_t addr;
3f8bc370 6396 int ret;
79e53945 6397
79e53945
JB		 6398 /* if we want to turn off the cursor ignore width and height */
6399 if (!handle) {
28c97730 6400 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6401 addr = 0;
05394f39 6402 obj = NULL;
5004417d 6403 mutex_lock(&dev->struct_mutex);
3f8bc370 6404 goto finish;
79e53945
JB		 6405 }
6406
6407 /* Currently we only support 64x64 cursors */
6408 if (width != 64 || height != 64) {
6409 DRM_ERROR("we currently only support 64x64 cursors\n");
6410 return -EINVAL;
6411 }
6412
05394f39 6413 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6414 if (&obj->base == NULL)
79e53945
JB		 6415 return -ENOENT;
6416
05394f39 6417 if (obj->base.size < width * height * 4) {
79e53945 6418 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6419 ret = -ENOMEM;
6420 goto fail;
79e53945
JB		 6421 }
6422
71acb5eb 6423 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6424 mutex_lock(&dev->struct_mutex);
b295d1b6 6425 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6426 unsigned alignment;
6427
d9e86c0e
CW		 6428 if (obj->tiling_mode) {
6429 DRM_ERROR("cursor cannot be tiled\n");
6430 ret = -EINVAL;
6431 goto fail_locked;
6432 }
6433
693db184
CW		 6434 /* Note that the w/a also requires 2 PTE of padding following
6435 * the bo. We currently fill all unused PTE with the shadow
6436 * page and so we should always have valid PTE following the
6437 * cursor preventing the VT-d warning.
6438 */
6439 alignment = 0;
6440 if (need_vtd_wa(dev))
6441 alignment = 64*1024;
6442
6443 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6444 if (ret) {
6445 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6446 goto fail_locked;
e7b526bb
CW		 6447 }
6448
d9e86c0e
CW		 6449 ret = i915_gem_object_put_fence(obj);
6450 if (ret) {
2da3b9b9 6451 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6452 goto fail_unpin;
6453 }
6454
05394f39 6455 addr = obj->gtt_offset;
71acb5eb 6456 } else {
6eeefaf3 6457 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6458 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6459 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6460 align);
71acb5eb
DA		 6461 if (ret) {
6462 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6463 goto fail_locked;
71acb5eb 6464 }
05394f39 6465 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6466 }
6467
a6c45cf0 6468 if (IS_GEN2(dev))
14b60391
JB		 6469 I915_WRITE(CURSIZE, (height << 12) | width);
6470
3f8bc370 6471 finish:
3f8bc370 6472 if (intel_crtc->cursor_bo) {
b295d1b6 6473 if (dev_priv->info->cursor_needs_physical) {
05394f39 6474 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6475 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6476 } else
6477 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6478 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6479 }
80824003 6480
7f9872e0 6481 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6482
6483 intel_crtc->cursor_addr = addr;
05394f39 6484 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6485 intel_crtc->cursor_width = width;
6486 intel_crtc->cursor_height = height;
6487
6b383a7f 6488 intel_crtc_update_cursor(crtc, true);
3f8bc370 6489
79e53945 6490 return 0;
e7b526bb 6491fail_unpin:
05394f39 6492 i915_gem_object_unpin(obj);
7f9872e0 6493fail_locked:
34b8686e 6494 mutex_unlock(&dev->struct_mutex);
bc9025bd 6495fail:
05394f39 6496 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6497 return ret;
79e53945
JB		 6498}
6499
6500static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6501{
79e53945 6502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6503
cda4b7d3
CW		 6504 intel_crtc->cursor_x = x;
6505 intel_crtc->cursor_y = y;
652c393a 6506
6b383a7f 6507 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6508
6509 return 0;
6510}
6511
6512/** Sets the color ramps on behalf of RandR */
6513void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6514 u16 blue, int regno)
6515{
6516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6517
6518 intel_crtc->lut_r[regno] = red >> 8;
6519 intel_crtc->lut_g[regno] = green >> 8;
6520 intel_crtc->lut_b[regno] = blue >> 8;
6521}
6522
b8c00ac5
DA		 6523void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6524 u16 *blue, int regno)
6525{
6526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6527
6528 *red = intel_crtc->lut_r[regno] << 8;
6529 *green = intel_crtc->lut_g[regno] << 8;
6530 *blue = intel_crtc->lut_b[regno] << 8;
6531}
6532
79e53945 6533static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6534 u16 *blue, uint32_t start, uint32_t size)
79e53945 6535{
7203425a 6536 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6538
7203425a 6539 for (i = start; i < end; i++) {
79e53945
JB		 6540 intel_crtc->lut_r[i] = red[i] >> 8;
6541 intel_crtc->lut_g[i] = green[i] >> 8;
6542 intel_crtc->lut_b[i] = blue[i] >> 8;
6543 }
6544
6545 intel_crtc_load_lut(crtc);
6546}
6547
79e53945
JB		 6548/* VESA 640x480x72Hz mode to set on the pipe */
6549static struct drm_display_mode load_detect_mode = {
6550 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6551 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6552};
6553
d2dff872
CW		 6554static struct drm_framebuffer *
6555intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6556 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6557 struct drm_i915_gem_object *obj)
6558{
6559 struct intel_framebuffer *intel_fb;
6560 int ret;
6561
6562 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6563 if (!intel_fb) {
6564 drm_gem_object_unreference_unlocked(&obj->base);
6565 return ERR_PTR(-ENOMEM);
6566 }
6567
6568 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6569 if (ret) {
6570 drm_gem_object_unreference_unlocked(&obj->base);
6571 kfree(intel_fb);
6572 return ERR_PTR(ret);
6573 }
6574
6575 return &intel_fb->base;
6576}
6577
6578static u32
6579intel_framebuffer_pitch_for_width(int width, int bpp)
6580{
6581 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6582 return ALIGN(pitch, 64);
6583}
6584
6585static u32
6586intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6587{
6588 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6589 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6590}
6591
6592static struct drm_framebuffer *
6593intel_framebuffer_create_for_mode(struct drm_device *dev,
6594 struct drm_display_mode *mode,
6595 int depth, int bpp)
6596{
6597 struct drm_i915_gem_object *obj;
0fed39bd 6598 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6599
6600 obj = i915_gem_alloc_object(dev,
6601 intel_framebuffer_size_for_mode(mode, bpp));
6602 if (obj == NULL)
6603 return ERR_PTR(-ENOMEM);
6604
6605 mode_cmd.width = mode->hdisplay;
6606 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6607 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6608 bpp);
5ca0c34a 6609 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6610
6611 return intel_framebuffer_create(dev, &mode_cmd, obj);
6612}
6613
6614static struct drm_framebuffer *
6615mode_fits_in_fbdev(struct drm_device *dev,
6616 struct drm_display_mode *mode)
6617{
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619 struct drm_i915_gem_object *obj;
6620 struct drm_framebuffer *fb;
6621
6622 if (dev_priv->fbdev == NULL)
6623 return NULL;
6624
6625 obj = dev_priv->fbdev->ifb.obj;
6626 if (obj == NULL)
6627 return NULL;
6628
6629 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6630 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6631 fb->bits_per_pixel))
d2dff872
CW		 6632 return NULL;
6633
01f2c773 6634 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6635 return NULL;
6636
6637 return fb;
6638}
6639
d2434ab7 6640bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6641 struct drm_display_mode *mode,
8261b191 6642 struct intel_load_detect_pipe *old)
79e53945
JB		 6643{
6644 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6645 struct intel_encoder *intel_encoder =
6646 intel_attached_encoder(connector);
79e53945 6647 struct drm_crtc *possible_crtc;
4ef69c7a 6648 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6649 struct drm_crtc *crtc = NULL;
6650 struct drm_device *dev = encoder->dev;
94352cf9 6651 struct drm_framebuffer *fb;
79e53945
JB		 6652 int i = -1;
6653
d2dff872
CW		 6654 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6655 connector->base.id, drm_get_connector_name(connector),
6656 encoder->base.id, drm_get_encoder_name(encoder));
6657
79e53945
JB		 6658 /*
6659 * Algorithm gets a little messy:
7a5e4805 6660 *
79e53945
JB		 6661 * - if the connector already has an assigned crtc, use it (but make
6662 * sure it's on first)
7a5e4805 6663 *
79e53945
JB		 6664 * - try to find the first unused crtc that can drive this connector,
6665 * and use that if we find one
79e53945
JB		 6666 */
6667
6668 /* See if we already have a CRTC for this connector */
6669 if (encoder->crtc) {
6670 crtc = encoder->crtc;
8261b191 6671
7b24056b
DV		 6672 mutex_lock(&crtc->mutex);
6673
24218aac 6674 old->dpms_mode = connector->dpms;
8261b191
CW		 6675 old->load_detect_temp = false;
6676
6677 /* Make sure the crtc and connector are running */
24218aac
DV		 6678 if (connector->dpms != DRM_MODE_DPMS_ON)
6679 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6680
7173188d 6681 return true;
79e53945
JB		 6682 }
6683
6684 /* Find an unused one (if possible) */
6685 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6686 i++;
6687 if (!(encoder->possible_crtcs & (1 << i)))
6688 continue;
6689 if (!possible_crtc->enabled) {
6690 crtc = possible_crtc;
6691 break;
6692 }
79e53945
JB		 6693 }
6694
6695 /*
6696 * If we didn't find an unused CRTC, don't use any.
6697 */
6698 if (!crtc) {
7173188d
CW		 6699 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6700 return false;
79e53945
JB		 6701 }
6702
7b24056b 6703 mutex_lock(&crtc->mutex);
fc303101
DV		 6704 intel_encoder->new_crtc = to_intel_crtc(crtc);
6705 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6706
6707 intel_crtc = to_intel_crtc(crtc);
24218aac 6708 old->dpms_mode = connector->dpms;
8261b191 6709 old->load_detect_temp = true;
d2dff872 6710 old->release_fb = NULL;
79e53945 6711
6492711d
CW		 6712 if (!mode)
6713 mode = &load_detect_mode;
79e53945 6714
d2dff872
CW		 6715 /* We need a framebuffer large enough to accommodate all accesses
6716 * that the plane may generate whilst we perform load detection.
6717 * We can not rely on the fbcon either being present (we get called
6718 * during its initialisation to detect all boot displays, or it may
6719 * not even exist) or that it is large enough to satisfy the
6720 * requested mode.
6721 */
94352cf9
DV		 6722 fb = mode_fits_in_fbdev(dev, mode);
6723 if (fb == NULL) {
d2dff872 6724 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6725 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6726 old->release_fb = fb;
d2dff872
CW		 6727 } else
6728 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6729 if (IS_ERR(fb)) {
d2dff872 6730 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6731 mutex_unlock(&crtc->mutex);
0e8b3d3e 6732 return false;
79e53945 6733 }
79e53945 6734
c0c36b94 6735 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6736 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6737 if (old->release_fb)
6738 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6739 mutex_unlock(&crtc->mutex);
0e8b3d3e 6740 return false;
79e53945 6741 }
7173188d 6742
79e53945 6743 /* let the connector get through one full cycle before testing */
9d0498a2 6744 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6745 return true;
79e53945
JB		 6746}
6747
d2434ab7 6748void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6749 struct intel_load_detect_pipe *old)
79e53945 6750{
d2434ab7
DV		 6751 struct intel_encoder *intel_encoder =
6752 intel_attached_encoder(connector);
4ef69c7a 6753 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6754 struct drm_crtc *crtc = encoder->crtc;
79e53945 6755
d2dff872
CW		 6756 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6757 connector->base.id, drm_get_connector_name(connector),
6758 encoder->base.id, drm_get_encoder_name(encoder));
6759
8261b191 6760 if (old->load_detect_temp) {
fc303101
DV		 6761 to_intel_connector(connector)->new_encoder = NULL;
6762 intel_encoder->new_crtc = NULL;
6763 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6764
36206361
DV		 6765 if (old->release_fb) {
6766 drm_framebuffer_unregister_private(old->release_fb);
6767 drm_framebuffer_unreference(old->release_fb);
6768 }
d2dff872 6769
67c96400 6770 mutex_unlock(&crtc->mutex);
0622a53c 6771 return;
79e53945
JB		 6772 }
6773
c751ce4f 6774 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6775 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6776 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6777
6778 mutex_unlock(&crtc->mutex);
79e53945
JB		 6779}
6780
6781/* Returns the clock of the currently programmed mode of the given pipe. */
6782static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6783{
6784 struct drm_i915_private *dev_priv = dev->dev_private;
6785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6786 int pipe = intel_crtc->pipe;
548f245b 6787 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6788 u32 fp;
6789 intel_clock_t clock;
6790
6791 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6792 fp = I915_READ(FP0(pipe));
79e53945 6793 else
39adb7a5 6794 fp = I915_READ(FP1(pipe));
79e53945
JB		 6795
6796 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6797 if (IS_PINEVIEW(dev)) {
6798 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6799 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6800 } else {
6801 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6802 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6803 }
6804
a6c45cf0 6805 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6806 if (IS_PINEVIEW(dev))
6807 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6808 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6809 else
6810 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6811 DPLL_FPA01_P1_POST_DIV_SHIFT);
6812
6813 switch (dpll & DPLL_MODE_MASK) {
6814 case DPLLB_MODE_DAC_SERIAL:
6815 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6816 5 : 10;
6817 break;
6818 case DPLLB_MODE_LVDS:
6819 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6820 7 : 14;
6821 break;
6822 default:
28c97730 6823 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6824 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6825 return 0;
6826 }
6827
6828 /* XXX: Handle the 100Mhz refclk */
2177832f 6829 intel_clock(dev, 96000, &clock);
79e53945
JB		 6830 } else {
6831 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6832
6833 if (is_lvds) {
6834 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6835 DPLL_FPA01_P1_POST_DIV_SHIFT);
6836 clock.p2 = 14;
6837
6838 if ((dpll & PLL_REF_INPUT_MASK) ==
6839 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6840 /* XXX: might not be 66MHz */
2177832f 6841 intel_clock(dev, 66000, &clock);
79e53945 6842 } else
2177832f 6843 intel_clock(dev, 48000, &clock);
79e53945
JB		 6844 } else {
6845 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6846 clock.p1 = 2;
6847 else {
6848 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6849 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6850 }
6851 if (dpll & PLL_P2_DIVIDE_BY_4)
6852 clock.p2 = 4;
6853 else
6854 clock.p2 = 2;
6855
2177832f 6856 intel_clock(dev, 48000, &clock);
79e53945
JB		 6857 }
6858 }
6859
6860 /* XXX: It would be nice to validate the clocks, but we can't reuse
6861 * i830PllIsValid() because it relies on the xf86_config connector
6862 * configuration being accurate, which it isn't necessarily.
6863 */
6864
6865 return clock.dot;
6866}
6867
6868/** Returns the currently programmed mode of the given pipe. */
6869struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6870 struct drm_crtc *crtc)
6871{
548f245b 6872 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6874 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6875 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6876 int htot = I915_READ(HTOTAL(cpu_transcoder));
6877 int hsync = I915_READ(HSYNC(cpu_transcoder));
6878 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6879 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6880
6881 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6882 if (!mode)
6883 return NULL;
6884
6885 mode->clock = intel_crtc_clock_get(dev, crtc);
6886 mode->hdisplay = (htot & 0xffff) + 1;
6887 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6888 mode->hsync_start = (hsync & 0xffff) + 1;
6889 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6890 mode->vdisplay = (vtot & 0xffff) + 1;
6891 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6892 mode->vsync_start = (vsync & 0xffff) + 1;
6893 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6894
6895 drm_mode_set_name(mode);
79e53945
JB		 6896
6897 return mode;
6898}
6899
3dec0095 6900static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6901{
6902 struct drm_device *dev = crtc->dev;
6903 drm_i915_private_t *dev_priv = dev->dev_private;
6904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6905 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6906 int dpll_reg = DPLL(pipe);
6907 int dpll;
652c393a 6908
bad720ff 6909 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6910 return;
6911
6912 if (!dev_priv->lvds_downclock_avail)
6913 return;
6914
dbdc6479 6915 dpll = I915_READ(dpll_reg);
652c393a 6916 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6917 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6918
8ac5a6d5 6919 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6920
6921 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6922 I915_WRITE(dpll_reg, dpll);
9d0498a2 6923 intel_wait_for_vblank(dev, pipe);
dbdc6479 6924
652c393a
JB		 6925 dpll = I915_READ(dpll_reg);
6926 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6927 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6928 }
652c393a
JB		 6929}
6930
6931static void intel_decrease_pllclock(struct drm_crtc *crtc)
6932{
6933 struct drm_device *dev = crtc->dev;
6934 drm_i915_private_t *dev_priv = dev->dev_private;
6935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6936
bad720ff 6937 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6938 return;
6939
6940 if (!dev_priv->lvds_downclock_avail)
6941 return;
6942
6943 /*
6944 * Since this is called by a timer, we should never get here in
6945 * the manual case.
6946 */
6947 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6948 int pipe = intel_crtc->pipe;
6949 int dpll_reg = DPLL(pipe);
6950 int dpll;
f6e5b160 6951
44d98a61 6952 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6953
8ac5a6d5 6954 assert_panel_unlocked(dev_priv, pipe);
652c393a 6955
dc257cf1 6956 dpll = I915_READ(dpll_reg);
652c393a
JB		 6957 dpll |= DISPLAY_RATE_SELECT_FPA1;
6958 I915_WRITE(dpll_reg, dpll);
9d0498a2 6959 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6960 dpll = I915_READ(dpll_reg);
6961 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6962 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6963 }
6964
6965}
6966
f047e395
CW		 6967void intel_mark_busy(struct drm_device *dev)
6968{
f047e395
CW		 6969 i915_update_gfx_val(dev->dev_private);
6970}
6971
6972void intel_mark_idle(struct drm_device *dev)
652c393a 6973{
652c393a 6974 struct drm_crtc *crtc;
652c393a
JB		 6975
6976 if (!i915_powersave)
6977 return;
6978
652c393a 6979 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6980 if (!crtc->fb)
6981 continue;
6982
725a5b54 6983 intel_decrease_pllclock(crtc);
652c393a 6984 }
652c393a
JB		 6985}
6986
725a5b54 6987void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6988{
f047e395
CW		 6989 struct drm_device *dev = obj->base.dev;
6990 struct drm_crtc *crtc;
652c393a 6991
f047e395 6992 if (!i915_powersave)
acb87dfb
CW		 6993 return;
6994
652c393a
JB		 6995 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6996 if (!crtc->fb)
6997 continue;
6998
f047e395 6999 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7000 intel_increase_pllclock(crtc);
652c393a
JB		 7001 }
7002}
7003
79e53945
JB		 7004static void intel_crtc_destroy(struct drm_crtc *crtc)
7005{
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7007 struct drm_device *dev = crtc->dev;
7008 struct intel_unpin_work *work;
7009 unsigned long flags;
7010
7011 spin_lock_irqsave(&dev->event_lock, flags);
7012 work = intel_crtc->unpin_work;
7013 intel_crtc->unpin_work = NULL;
7014 spin_unlock_irqrestore(&dev->event_lock, flags);
7015
7016 if (work) {
7017 cancel_work_sync(&work->work);
7018 kfree(work);
7019 }
79e53945
JB		 7020
7021 drm_crtc_cleanup(crtc);
67e77c5a 7022
79e53945
JB		 7023 kfree(intel_crtc);
7024}
7025
6b95a207
KH		 7026static void intel_unpin_work_fn(struct work_struct *__work)
7027{
7028 struct intel_unpin_work *work =
7029 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7030 struct drm_device *dev = work->crtc->dev;
6b95a207 7031
b4a98e57 7032 mutex_lock(&dev->struct_mutex);
1690e1eb 7033 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7034 drm_gem_object_unreference(&work->pending_flip_obj->base);
7035 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7036
b4a98e57
CW		 7037 intel_update_fbc(dev);
7038 mutex_unlock(&dev->struct_mutex);
7039
7040 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7041 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7042
6b95a207
KH		 7043 kfree(work);
7044}
7045
1afe3e9d 7046static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7047 struct drm_crtc *crtc)
6b95a207
KH		 7048{
7049 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7051 struct intel_unpin_work *work;
6b95a207
KH		 7052 unsigned long flags;
7053
7054 /* Ignore early vblank irqs */
7055 if (intel_crtc == NULL)
7056 return;
7057
7058 spin_lock_irqsave(&dev->event_lock, flags);
7059 work = intel_crtc->unpin_work;
e7d841ca
CW		 7060
7061 /* Ensure we don't miss a work->pending update ... */
7062 smp_rmb();
7063
7064 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7065 spin_unlock_irqrestore(&dev->event_lock, flags);
7066 return;
7067 }
7068
e7d841ca
CW		 7069 /* and that the unpin work is consistent wrt ->pending. */
7070 smp_rmb();
7071
6b95a207 7072 intel_crtc->unpin_work = NULL;
6b95a207 7073
45a066eb
RC		 7074 if (work->event)
7075 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7076
0af7e4df
MK		 7077 drm_vblank_put(dev, intel_crtc->pipe);
7078
6b95a207
KH		 7079 spin_unlock_irqrestore(&dev->event_lock, flags);
7080
2c10d571 7081 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7082
7083 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7084
7085 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7086}
7087
1afe3e9d
JB		 7088void intel_finish_page_flip(struct drm_device *dev, int pipe)
7089{
7090 drm_i915_private_t *dev_priv = dev->dev_private;
7091 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7092
49b14a5c 7093 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7094}
7095
7096void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7097{
7098 drm_i915_private_t *dev_priv = dev->dev_private;
7099 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7100
49b14a5c 7101 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7102}
7103
6b95a207
KH		 7104void intel_prepare_page_flip(struct drm_device *dev, int plane)
7105{
7106 drm_i915_private_t *dev_priv = dev->dev_private;
7107 struct intel_crtc *intel_crtc =
7108 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7109 unsigned long flags;
7110
e7d841ca
CW		 7111 /* NB: An MMIO update of the plane base pointer will also
7112 * generate a page-flip completion irq, i.e. every modeset
7113 * is also accompanied by a spurious intel_prepare_page_flip().
7114 */
6b95a207 7115 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7116 if (intel_crtc->unpin_work)
7117 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7118 spin_unlock_irqrestore(&dev->event_lock, flags);
7119}
7120
e7d841ca
CW		 7121inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7122{
7123 /* Ensure that the work item is consistent when activating it ... */
7124 smp_wmb();
7125 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7126 /* and that it is marked active as soon as the irq could fire. */
7127 smp_wmb();
7128}
7129
8c9f3aaf
JB		 7130static int intel_gen2_queue_flip(struct drm_device *dev,
7131 struct drm_crtc *crtc,
7132 struct drm_framebuffer *fb,
7133 struct drm_i915_gem_object *obj)
7134{
7135 struct drm_i915_private *dev_priv = dev->dev_private;
7136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7137 u32 flip_mask;
6d90c952 7138 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7139 int ret;
7140
6d90c952 7141 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7142 if (ret)
83d4092b 7143 goto err;
8c9f3aaf 7144
6d90c952 7145 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7146 if (ret)
83d4092b 7147 goto err_unpin;
8c9f3aaf
JB		 7148
7149 /* Can't queue multiple flips, so wait for the previous
7150 * one to finish before executing the next.
7151 */
7152 if (intel_crtc->plane)
7153 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7154 else
7155 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7156 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7157 intel_ring_emit(ring, MI_NOOP);
7158 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7159 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7160 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7161 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7162 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7163
7164 intel_mark_page_flip_active(intel_crtc);
6d90c952 7165 intel_ring_advance(ring);
83d4092b
CW		 7166 return 0;
7167
7168err_unpin:
7169 intel_unpin_fb_obj(obj);
7170err:
8c9f3aaf
JB		 7171 return ret;
7172}
7173
7174static int intel_gen3_queue_flip(struct drm_device *dev,
7175 struct drm_crtc *crtc,
7176 struct drm_framebuffer *fb,
7177 struct drm_i915_gem_object *obj)
7178{
7179 struct drm_i915_private *dev_priv = dev->dev_private;
7180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7181 u32 flip_mask;
6d90c952 7182 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7183 int ret;
7184
6d90c952 7185 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7186 if (ret)
83d4092b 7187 goto err;
8c9f3aaf 7188
6d90c952 7189 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7190 if (ret)
83d4092b 7191 goto err_unpin;
8c9f3aaf
JB		 7192
7193 if (intel_crtc->plane)
7194 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7195 else
7196 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7197 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7198 intel_ring_emit(ring, MI_NOOP);
7199 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7200 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7201 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7202 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7203 intel_ring_emit(ring, MI_NOOP);
7204
e7d841ca 7205 intel_mark_page_flip_active(intel_crtc);
6d90c952 7206 intel_ring_advance(ring);
83d4092b
CW		 7207 return 0;
7208
7209err_unpin:
7210 intel_unpin_fb_obj(obj);
7211err:
8c9f3aaf
JB		 7212 return ret;
7213}
7214
7215static int intel_gen4_queue_flip(struct drm_device *dev,
7216 struct drm_crtc *crtc,
7217 struct drm_framebuffer *fb,
7218 struct drm_i915_gem_object *obj)
7219{
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7222 uint32_t pf, pipesrc;
6d90c952 7223 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7224 int ret;
7225
6d90c952 7226 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7227 if (ret)
83d4092b 7228 goto err;
8c9f3aaf 7229
6d90c952 7230 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7231 if (ret)
83d4092b 7232 goto err_unpin;
8c9f3aaf
JB		 7233
7234 /* i965+ uses the linear or tiled offsets from the
7235 * Display Registers (which do not change across a page-flip)
7236 * so we need only reprogram the base address.
7237 */
6d90c952
DV		 7238 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7239 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7240 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7241 intel_ring_emit(ring,
7242 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7243 obj->tiling_mode);
8c9f3aaf
JB		 7244
7245 /* XXX Enabling the panel-fitter across page-flip is so far
7246 * untested on non-native modes, so ignore it for now.
7247 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7248 */
7249 pf = 0;
7250 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7251 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7252
7253 intel_mark_page_flip_active(intel_crtc);
6d90c952 7254 intel_ring_advance(ring);
83d4092b
CW		 7255 return 0;
7256
7257err_unpin:
7258 intel_unpin_fb_obj(obj);
7259err:
8c9f3aaf
JB		 7260 return ret;
7261}
7262
7263static int intel_gen6_queue_flip(struct drm_device *dev,
7264 struct drm_crtc *crtc,
7265 struct drm_framebuffer *fb,
7266 struct drm_i915_gem_object *obj)
7267{
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7270 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7271 uint32_t pf, pipesrc;
7272 int ret;
7273
6d90c952 7274 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7275 if (ret)
83d4092b 7276 goto err;
8c9f3aaf 7277
6d90c952 7278 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7279 if (ret)
83d4092b 7280 goto err_unpin;
8c9f3aaf 7281
6d90c952
DV		 7282 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7283 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7284 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7285 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7286
dc257cf1
DV		 7287 /* Contrary to the suggestions in the documentation,
7288 * "Enable Panel Fitter" does not seem to be required when page
7289 * flipping with a non-native mode, and worse causes a normal
7290 * modeset to fail.
7291 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7292 */
7293 pf = 0;
8c9f3aaf 7294 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7295 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7296
7297 intel_mark_page_flip_active(intel_crtc);
6d90c952 7298 intel_ring_advance(ring);
83d4092b
CW		 7299 return 0;
7300
7301err_unpin:
7302 intel_unpin_fb_obj(obj);
7303err:
8c9f3aaf
JB		 7304 return ret;
7305}
7306
7c9017e5
JB		 7307/*
7308 * On gen7 we currently use the blit ring because (in early silicon at least)
7309 * the render ring doesn't give us interrpts for page flip completion, which
7310 * means clients will hang after the first flip is queued. Fortunately the
7311 * blit ring generates interrupts properly, so use it instead.
7312 */
7313static int intel_gen7_queue_flip(struct drm_device *dev,
7314 struct drm_crtc *crtc,
7315 struct drm_framebuffer *fb,
7316 struct drm_i915_gem_object *obj)
7317{
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7320 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7321 uint32_t plane_bit = 0;
7c9017e5
JB		 7322 int ret;
7323
7324 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7325 if (ret)
83d4092b 7326 goto err;
7c9017e5 7327
cb05d8de
DV		 7328 switch(intel_crtc->plane) {
7329 case PLANE_A:
7330 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7331 break;
7332 case PLANE_B:
7333 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7334 break;
7335 case PLANE_C:
7336 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7337 break;
7338 default:
7339 WARN_ONCE(1, "unknown plane in flip command\n");
7340 ret = -ENODEV;
ab3951eb 7341 goto err_unpin;
cb05d8de
DV		 7342 }
7343
7c9017e5
JB		 7344 ret = intel_ring_begin(ring, 4);
7345 if (ret)
83d4092b 7346 goto err_unpin;
7c9017e5 7347
cb05d8de 7348 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7349 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7350 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7351 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7352
7353 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7354 intel_ring_advance(ring);
83d4092b
CW		 7355 return 0;
7356
7357err_unpin:
7358 intel_unpin_fb_obj(obj);
7359err:
7c9017e5
JB		 7360 return ret;
7361}
7362
8c9f3aaf
JB		 7363static int intel_default_queue_flip(struct drm_device *dev,
7364 struct drm_crtc *crtc,
7365 struct drm_framebuffer *fb,
7366 struct drm_i915_gem_object *obj)
7367{
7368 return -ENODEV;
7369}
7370
6b95a207
KH		 7371static int intel_crtc_page_flip(struct drm_crtc *crtc,
7372 struct drm_framebuffer *fb,
7373 struct drm_pending_vblank_event *event)
7374{
7375 struct drm_device *dev = crtc->dev;
7376 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7377 struct drm_framebuffer *old_fb = crtc->fb;
7378 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7380 struct intel_unpin_work *work;
8c9f3aaf 7381 unsigned long flags;
52e68630 7382 int ret;
6b95a207 7383
e6a595d2
VS		 7384 /* Can't change pixel format via MI display flips. */
7385 if (fb->pixel_format != crtc->fb->pixel_format)
7386 return -EINVAL;
7387
7388 /*
7389 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7390 * Note that pitch changes could also affect these register.
7391 */
7392 if (INTEL_INFO(dev)->gen > 3 &&
7393 (fb->offsets[0] != crtc->fb->offsets[0] ||
7394 fb->pitches[0] != crtc->fb->pitches[0]))
7395 return -EINVAL;
7396
6b95a207
KH		 7397 work = kzalloc(sizeof *work, GFP_KERNEL);
7398 if (work == NULL)
7399 return -ENOMEM;
7400
6b95a207 7401 work->event = event;
b4a98e57 7402 work->crtc = crtc;
4a35f83b 7403 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7404 INIT_WORK(&work->work, intel_unpin_work_fn);
7405
7317c75e
JB		 7406 ret = drm_vblank_get(dev, intel_crtc->pipe);
7407 if (ret)
7408 goto free_work;
7409
6b95a207
KH		 7410 /* We borrow the event spin lock for protecting unpin_work */
7411 spin_lock_irqsave(&dev->event_lock, flags);
7412 if (intel_crtc->unpin_work) {
7413 spin_unlock_irqrestore(&dev->event_lock, flags);
7414 kfree(work);
7317c75e 7415 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7416
7417 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7418 return -EBUSY;
7419 }
7420 intel_crtc->unpin_work = work;
7421 spin_unlock_irqrestore(&dev->event_lock, flags);
7422
b4a98e57
CW		 7423 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7424 flush_workqueue(dev_priv->wq);
7425
79158103
CW		 7426 ret = i915_mutex_lock_interruptible(dev);
7427 if (ret)
7428 goto cleanup;
6b95a207 7429
75dfca80 7430 /* Reference the objects for the scheduled work. */
05394f39
CW		 7431 drm_gem_object_reference(&work->old_fb_obj->base);
7432 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7433
7434 crtc->fb = fb;
96b099fd 7435
e1f99ce6 7436 work->pending_flip_obj = obj;
e1f99ce6 7437
4e5359cd
SF		 7438 work->enable_stall_check = true;
7439
b4a98e57 7440 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7441 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7442
8c9f3aaf
JB		 7443 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7444 if (ret)
7445 goto cleanup_pending;
6b95a207 7446
7782de3b 7447 intel_disable_fbc(dev);
f047e395 7448 intel_mark_fb_busy(obj);
6b95a207
KH		 7449 mutex_unlock(&dev->struct_mutex);
7450
e5510fac
JB		 7451 trace_i915_flip_request(intel_crtc->plane, obj);
7452
6b95a207 7453 return 0;
96b099fd 7454
8c9f3aaf 7455cleanup_pending:
b4a98e57 7456 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7457 crtc->fb = old_fb;
05394f39
CW		 7458 drm_gem_object_unreference(&work->old_fb_obj->base);
7459 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7460 mutex_unlock(&dev->struct_mutex);
7461
79158103 7462cleanup:
96b099fd
CW		 7463 spin_lock_irqsave(&dev->event_lock, flags);
7464 intel_crtc->unpin_work = NULL;
7465 spin_unlock_irqrestore(&dev->event_lock, flags);
7466
7317c75e
JB		 7467 drm_vblank_put(dev, intel_crtc->pipe);
7468free_work:
96b099fd
CW		 7469 kfree(work);
7470
7471 return ret;
6b95a207
KH		 7472}
7473
f6e5b160 7474static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7475 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7476 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7477};
7478
6ed0f796 7479bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7480{
6ed0f796
DV		 7481 struct intel_encoder *other_encoder;
7482 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7483
6ed0f796
DV		 7484 if (WARN_ON(!crtc))
7485 return false;
7486
7487 list_for_each_entry(other_encoder,
7488 &crtc->dev->mode_config.encoder_list,
7489 base.head) {
7490
7491 if (&other_encoder->new_crtc->base != crtc ||
7492 encoder == other_encoder)
7493 continue;
7494 else
7495 return true;
f47166d2
CW		 7496 }
7497
6ed0f796
DV		 7498 return false;
7499}
47f1c6c9 7500
50f56119
DV		 7501static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7502 struct drm_crtc *crtc)
7503{
7504 struct drm_device *dev;
7505 struct drm_crtc *tmp;
7506 int crtc_mask = 1;
47f1c6c9 7507
50f56119 7508 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7509
50f56119 7510 dev = crtc->dev;
47f1c6c9 7511
50f56119
DV		 7512 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7513 if (tmp == crtc)
7514 break;
7515 crtc_mask <<= 1;
7516 }
47f1c6c9 7517
50f56119
DV		 7518 if (encoder->possible_crtcs & crtc_mask)
7519 return true;
7520 return false;
47f1c6c9 7521}
79e53945 7522
9a935856
DV		 7523/**
7524 * intel_modeset_update_staged_output_state
7525 *
7526 * Updates the staged output configuration state, e.g. after we've read out the
7527 * current hw state.
7528 */
7529static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7530{
9a935856
DV		 7531 struct intel_encoder *encoder;
7532 struct intel_connector *connector;
f6e5b160 7533
9a935856
DV		 7534 list_for_each_entry(connector, &dev->mode_config.connector_list,
7535 base.head) {
7536 connector->new_encoder =
7537 to_intel_encoder(connector->base.encoder);
7538 }
f6e5b160 7539
9a935856
DV		 7540 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7541 base.head) {
7542 encoder->new_crtc =
7543 to_intel_crtc(encoder->base.crtc);
7544 }
f6e5b160
CW		 7545}
7546
9a935856
DV		 7547/**
7548 * intel_modeset_commit_output_state
7549 *
7550 * This function copies the stage display pipe configuration to the real one.
7551 */
7552static void intel_modeset_commit_output_state(struct drm_device *dev)
7553{
7554 struct intel_encoder *encoder;
7555 struct intel_connector *connector;
f6e5b160 7556
9a935856
DV		 7557 list_for_each_entry(connector, &dev->mode_config.connector_list,
7558 base.head) {
7559 connector->base.encoder = &connector->new_encoder->base;
7560 }
f6e5b160 7561
9a935856
DV		 7562 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7563 base.head) {
7564 encoder->base.crtc = &encoder->new_crtc->base;
7565 }
7566}
7567
4e53c2e0
DV		 7568static int
7569pipe_config_set_bpp(struct drm_crtc *crtc,
7570 struct drm_framebuffer *fb,
7571 struct intel_crtc_config *pipe_config)
7572{
7573 struct drm_device *dev = crtc->dev;
7574 struct drm_connector *connector;
7575 int bpp;
7576
d42264b1
DV		 7577 switch (fb->pixel_format) {
7578 case DRM_FORMAT_C8:
4e53c2e0
DV		 7579 bpp = 8*3; /* since we go through a colormap */
7580 break;
d42264b1
DV		 7581 case DRM_FORMAT_XRGB1555:
7582 case DRM_FORMAT_ARGB1555:
7583 /* checked in intel_framebuffer_init already */
7584 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7585 return -EINVAL;
7586 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7587 bpp = 6*3; /* min is 18bpp */
7588 break;
d42264b1
DV		 7589 case DRM_FORMAT_XBGR8888:
7590 case DRM_FORMAT_ABGR8888:
7591 /* checked in intel_framebuffer_init already */
7592 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7593 return -EINVAL;
7594 case DRM_FORMAT_XRGB8888:
7595 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7596 bpp = 8*3;
7597 break;
d42264b1
DV		 7598 case DRM_FORMAT_XRGB2101010:
7599 case DRM_FORMAT_ARGB2101010:
7600 case DRM_FORMAT_XBGR2101010:
7601 case DRM_FORMAT_ABGR2101010:
7602 /* checked in intel_framebuffer_init already */
7603 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7604 return -EINVAL;
4e53c2e0
DV		 7605 bpp = 10*3;
7606 break;
baba133a 7607 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7608 default:
7609 DRM_DEBUG_KMS("unsupported depth\n");
7610 return -EINVAL;
7611 }
7612
4e53c2e0
DV		 7613 pipe_config->pipe_bpp = bpp;
7614
7615 /* Clamp display bpp to EDID value */
7616 list_for_each_entry(connector, &dev->mode_config.connector_list,
7617 head) {
7618 if (connector->encoder && connector->encoder->crtc != crtc)
7619 continue;
7620
7621 /* Don't use an invalid EDID bpc value */
7622 if (connector->display_info.bpc &&
7623 connector->display_info.bpc * 3 < bpp) {
7624 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7625 bpp, connector->display_info.bpc*3);
7626 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7627 }
996a2239
DV		 7628
7629 /* Clamp bpp to 8 on screens without EDID 1.4 */
7630 if (connector->display_info.bpc == 0 && bpp > 24) {
7631 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7632 bpp);
7633 pipe_config->pipe_bpp = 24;
7634 }
4e53c2e0
DV		 7635 }
7636
7637 return bpp;
7638}
7639
b8cecdf5
DV		 7640static struct intel_crtc_config *
7641intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7642 struct drm_framebuffer *fb,
b8cecdf5 7643 struct drm_display_mode *mode)
ee7b9f93 7644{
7758a113 7645 struct drm_device *dev = crtc->dev;
7758a113
DV		 7646 struct drm_encoder_helper_funcs *encoder_funcs;
7647 struct intel_encoder *encoder;
b8cecdf5 7648 struct intel_crtc_config *pipe_config;
4e53c2e0 7649 int plane_bpp;
ee7b9f93 7650
b8cecdf5
DV		 7651 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7652 if (!pipe_config)
7758a113
DV		 7653 return ERR_PTR(-ENOMEM);
7654
b8cecdf5
DV		 7655 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7656 drm_mode_copy(&pipe_config->requested_mode, mode);
7657
4e53c2e0
DV		 7658 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7659 if (plane_bpp < 0)
7660 goto fail;
7661
7758a113
DV		 7662 /* Pass our mode to the connectors and the CRTC to give them a chance to
7663 * adjust it according to limitations or connector properties, and also
7664 * a chance to reject the mode entirely.
47f1c6c9 7665 */
7758a113
DV		 7666 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7667 base.head) {
47f1c6c9 7668
7758a113
DV		 7669 if (&encoder->new_crtc->base != crtc)
7670 continue;
7ae89233
DV		 7671
7672 if (encoder->compute_config) {
7673 if (!(encoder->compute_config(encoder, pipe_config))) {
7674 DRM_DEBUG_KMS("Encoder config failure\n");
7675 goto fail;
7676 }
7677
7678 continue;
7679 }
7680
7758a113 7681 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7682 if (!(encoder_funcs->mode_fixup(&encoder->base,
7683 &pipe_config->requested_mode,
7684 &pipe_config->adjusted_mode))) {
7758a113
DV		 7685 DRM_DEBUG_KMS("Encoder fixup failed\n");
7686 goto fail;
7687 }
ee7b9f93 7688 }
47f1c6c9 7689
b8cecdf5 7690 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7691 DRM_DEBUG_KMS("CRTC fixup failed\n");
7692 goto fail;
ee7b9f93 7693 }
7758a113 7694 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7695
4e53c2e0
DV		 7696 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7697 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7698 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7699
b8cecdf5 7700 return pipe_config;
7758a113 7701fail:
b8cecdf5 7702 kfree(pipe_config);
7758a113 7703 return ERR_PTR(-EINVAL);
ee7b9f93 7704}
47f1c6c9 7705
e2e1ed41
DV		 7706/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7707 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7708static void
7709intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7710 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7711{
7712 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7713 struct drm_device *dev = crtc->dev;
7714 struct intel_encoder *encoder;
7715 struct intel_connector *connector;
7716 struct drm_crtc *tmp_crtc;
79e53945 7717
e2e1ed41 7718 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7719
e2e1ed41
DV		 7720 /* Check which crtcs have changed outputs connected to them, these need
7721 * to be part of the prepare_pipes mask. We don't (yet) support global
7722 * modeset across multiple crtcs, so modeset_pipes will only have one
7723 * bit set at most. */
7724 list_for_each_entry(connector, &dev->mode_config.connector_list,
7725 base.head) {
7726 if (connector->base.encoder == &connector->new_encoder->base)
7727 continue;
79e53945 7728
e2e1ed41
DV		 7729 if (connector->base.encoder) {
7730 tmp_crtc = connector->base.encoder->crtc;
7731
7732 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7733 }
7734
7735 if (connector->new_encoder)
7736 *prepare_pipes |=
7737 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7738 }
7739
e2e1ed41
DV		 7740 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7741 base.head) {
7742 if (encoder->base.crtc == &encoder->new_crtc->base)
7743 continue;
7744
7745 if (encoder->base.crtc) {
7746 tmp_crtc = encoder->base.crtc;
7747
7748 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7749 }
7750
7751 if (encoder->new_crtc)
7752 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7753 }
7754
e2e1ed41
DV		 7755 /* Check for any pipes that will be fully disabled ... */
7756 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7757 base.head) {
7758 bool used = false;
22fd0fab 7759
e2e1ed41
DV		 7760 /* Don't try to disable disabled crtcs. */
7761 if (!intel_crtc->base.enabled)
7762 continue;
7e7d76c3 7763
e2e1ed41
DV		 7764 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7765 base.head) {
7766 if (encoder->new_crtc == intel_crtc)
7767 used = true;
7768 }
7769
7770 if (!used)
7771 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7772 }
7773
e2e1ed41
DV		 7774
7775 /* set_mode is also used to update properties on life display pipes. */
7776 intel_crtc = to_intel_crtc(crtc);
7777 if (crtc->enabled)
7778 *prepare_pipes |= 1 << intel_crtc->pipe;
7779
b6c5164d
DV		 7780 /*
7781 * For simplicity do a full modeset on any pipe where the output routing
7782 * changed. We could be more clever, but that would require us to be
7783 * more careful with calling the relevant encoder->mode_set functions.
7784 */
e2e1ed41
DV		 7785 if (*prepare_pipes)
7786 *modeset_pipes = *prepare_pipes;
7787
7788 /* ... and mask these out. */
7789 *modeset_pipes &= ~(*disable_pipes);
7790 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7791
7792 /*
7793 * HACK: We don't (yet) fully support global modesets. intel_set_config
7794 * obies this rule, but the modeset restore mode of
7795 * intel_modeset_setup_hw_state does not.
7796 */
7797 *modeset_pipes &= 1 << intel_crtc->pipe;
7798 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7799
7800 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7801 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7802}
79e53945 7803
ea9d758d 7804static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7805{
ea9d758d 7806 struct drm_encoder *encoder;
f6e5b160 7807 struct drm_device *dev = crtc->dev;
f6e5b160 7808
ea9d758d
DV		 7809 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7810 if (encoder->crtc == crtc)
7811 return true;
7812
7813 return false;
7814}
7815
7816static void
7817intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7818{
7819 struct intel_encoder *intel_encoder;
7820 struct intel_crtc *intel_crtc;
7821 struct drm_connector *connector;
7822
7823 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7824 base.head) {
7825 if (!intel_encoder->base.crtc)
7826 continue;
7827
7828 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7829
7830 if (prepare_pipes & (1 << intel_crtc->pipe))
7831 intel_encoder->connectors_active = false;
7832 }
7833
7834 intel_modeset_commit_output_state(dev);
7835
7836 /* Update computed state. */
7837 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7838 base.head) {
7839 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7840 }
7841
7842 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7843 if (!connector->encoder || !connector->encoder->crtc)
7844 continue;
7845
7846 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7847
7848 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7849 struct drm_property *dpms_property =
7850 dev->mode_config.dpms_property;
7851
ea9d758d 7852 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7853 drm_object_property_set_value(&connector->base,
68d34720
DV		 7854 dpms_property,
7855 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7856
7857 intel_encoder = to_intel_encoder(connector->encoder);
7858 intel_encoder->connectors_active = true;
7859 }
7860 }
7861
7862}
7863
25c5b266
DV		 7864#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7865 list_for_each_entry((intel_crtc), \
7866 &(dev)->mode_config.crtc_list, \
7867 base.head) \
7868 if (mask & (1 <<(intel_crtc)->pipe)) \
7869
0e8ffe1b
DV		 7870static bool
7871intel_pipe_config_compare(struct intel_crtc_config *current_config,
7872 struct intel_crtc_config *pipe_config)
7873{
88adfff1
DV		 7874 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7875 DRM_ERROR("mismatch in has_pch_encoder "
7876 "(expected %i, found %i)\n",
7877 current_config->has_pch_encoder,
7878 pipe_config->has_pch_encoder);
7879 return false;
7880 }
7881
0e8ffe1b
DV		 7882 return true;
7883}
7884
b980514c 7885void
8af6cf88
DV		 7886intel_modeset_check_state(struct drm_device *dev)
7887{
0e8ffe1b 7888 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7889 struct intel_crtc *crtc;
7890 struct intel_encoder *encoder;
7891 struct intel_connector *connector;
0e8ffe1b 7892 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7893
7894 list_for_each_entry(connector, &dev->mode_config.connector_list,
7895 base.head) {
7896 /* This also checks the encoder/connector hw state with the
7897 * ->get_hw_state callbacks. */
7898 intel_connector_check_state(connector);
7899
7900 WARN(&connector->new_encoder->base != connector->base.encoder,
7901 "connector's staged encoder doesn't match current encoder\n");
7902 }
7903
7904 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7905 base.head) {
7906 bool enabled = false;
7907 bool active = false;
7908 enum pipe pipe, tracked_pipe;
7909
7910 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7911 encoder->base.base.id,
7912 drm_get_encoder_name(&encoder->base));
7913
7914 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7915 "encoder's stage crtc doesn't match current crtc\n");
7916 WARN(encoder->connectors_active && !encoder->base.crtc,
7917 "encoder's active_connectors set, but no crtc\n");
7918
7919 list_for_each_entry(connector, &dev->mode_config.connector_list,
7920 base.head) {
7921 if (connector->base.encoder != &encoder->base)
7922 continue;
7923 enabled = true;
7924 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7925 active = true;
7926 }
7927 WARN(!!encoder->base.crtc != enabled,
7928 "encoder's enabled state mismatch "
7929 "(expected %i, found %i)\n",
7930 !!encoder->base.crtc, enabled);
7931 WARN(active && !encoder->base.crtc,
7932 "active encoder with no crtc\n");
7933
7934 WARN(encoder->connectors_active != active,
7935 "encoder's computed active state doesn't match tracked active state "
7936 "(expected %i, found %i)\n", active, encoder->connectors_active);
7937
7938 active = encoder->get_hw_state(encoder, &pipe);
7939 WARN(active != encoder->connectors_active,
7940 "encoder's hw state doesn't match sw tracking "
7941 "(expected %i, found %i)\n",
7942 encoder->connectors_active, active);
7943
7944 if (!encoder->base.crtc)
7945 continue;
7946
7947 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7948 WARN(active && pipe != tracked_pipe,
7949 "active encoder's pipe doesn't match"
7950 "(expected %i, found %i)\n",
7951 tracked_pipe, pipe);
7952
7953 }
7954
7955 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7956 base.head) {
7957 bool enabled = false;
7958 bool active = false;
7959
7960 DRM_DEBUG_KMS("[CRTC:%d]\n",
7961 crtc->base.base.id);
7962
7963 WARN(crtc->active && !crtc->base.enabled,
7964 "active crtc, but not enabled in sw tracking\n");
7965
7966 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7967 base.head) {
7968 if (encoder->base.crtc != &crtc->base)
7969 continue;
7970 enabled = true;
7971 if (encoder->connectors_active)
7972 active = true;
7973 }
7974 WARN(active != crtc->active,
7975 "crtc's computed active state doesn't match tracked active state "
7976 "(expected %i, found %i)\n", active, crtc->active);
7977 WARN(enabled != crtc->base.enabled,
7978 "crtc's computed enabled state doesn't match tracked enabled state "
7979 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7980
88adfff1 7981 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 7982 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 7983 active = dev_priv->display.get_pipe_config(crtc,
7984 &pipe_config);
7985 WARN(crtc->active != active,
7986 "crtc active state doesn't match with hw state "
7987 "(expected %i, found %i)\n", crtc->active, active);
7988
7989 WARN(active &&
7990 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7991 "pipe state doesn't match!\n");
8af6cf88
DV		 7992 }
7993}
7994
f30da187
DV		 7995static int __intel_set_mode(struct drm_crtc *crtc,
7996 struct drm_display_mode *mode,
7997 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7998{
7999 struct drm_device *dev = crtc->dev;
dbf2b54e 8000 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8001 struct drm_display_mode *saved_mode, *saved_hwmode;
8002 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8003 struct intel_crtc *intel_crtc;
8004 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8005 int ret = 0;
a6778b3c 8006
3ac18232 8007 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8008 if (!saved_mode)
8009 return -ENOMEM;
3ac18232 8010 saved_hwmode = saved_mode + 1;
a6778b3c 8011
e2e1ed41 8012 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8013 &prepare_pipes, &disable_pipes);
8014
3ac18232
TG		 8015 *saved_hwmode = crtc->hwmode;
8016 *saved_mode = crtc->mode;
a6778b3c 8017
25c5b266
DV		 8018 /* Hack: Because we don't (yet) support global modeset on multiple
8019 * crtcs, we don't keep track of the new mode for more than one crtc.
8020 * Hence simply check whether any bit is set in modeset_pipes in all the
8021 * pieces of code that are not yet converted to deal with mutliple crtcs
8022 * changing their mode at the same time. */
25c5b266 8023 if (modeset_pipes) {
4e53c2e0 8024 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8025 if (IS_ERR(pipe_config)) {
8026 ret = PTR_ERR(pipe_config);
8027 pipe_config = NULL;
8028
3ac18232 8029 goto out;
25c5b266 8030 }
25c5b266 8031 }
a6778b3c 8032
460da916
DV		 8033 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8034 intel_crtc_disable(&intel_crtc->base);
8035
ea9d758d
DV		 8036 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8037 if (intel_crtc->base.enabled)
8038 dev_priv->display.crtc_disable(&intel_crtc->base);
8039 }
a6778b3c 8040
6c4c86f5
DV		 8041 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8042 * to set it here already despite that we pass it down the callchain.
f6e5b160 8043 */
b8cecdf5 8044 if (modeset_pipes) {
3b117c8f 8045 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8046 crtc->mode = *mode;
b8cecdf5
DV		 8047 /* mode_set/enable/disable functions rely on a correct pipe
8048 * config. */
8049 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8050 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8051 }
7758a113 8052
ea9d758d
DV		 8053 /* Only after disabling all output pipelines that will be changed can we
8054 * update the the output configuration. */
8055 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8056
47fab737
DV		 8057 if (dev_priv->display.modeset_global_resources)
8058 dev_priv->display.modeset_global_resources(dev);
8059
a6778b3c
DV		 8060 /* Set up the DPLL and any encoders state that needs to adjust or depend
8061 * on the DPLL.
f6e5b160 8062 */
25c5b266 8063 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8064 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8065 x, y, fb);
8066 if (ret)
8067 goto done;
a6778b3c
DV		 8068 }
8069
8070 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8071 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8072 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8073
25c5b266
DV		 8074 if (modeset_pipes) {
8075 /* Store real post-adjustment hardware mode. */
b8cecdf5 8076 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8077
25c5b266
DV		 8078 /* Calculate and store various constants which
8079 * are later needed by vblank and swap-completion
8080 * timestamping. They are derived from true hwmode.
8081 */
8082 drm_calc_timestamping_constants(crtc);
8083 }
a6778b3c
DV		 8084
8085 /* FIXME: add subpixel order */
8086done:
c0c36b94 8087 if (ret && crtc->enabled) {
3ac18232
TG		 8088 crtc->hwmode = *saved_hwmode;
8089 crtc->mode = *saved_mode;
a6778b3c
DV		 8090 }
8091
3ac18232 8092out:
b8cecdf5 8093 kfree(pipe_config);
3ac18232 8094 kfree(saved_mode);
a6778b3c 8095 return ret;
f6e5b160
CW		 8096}
8097
f30da187
DV		 8098int intel_set_mode(struct drm_crtc *crtc,
8099 struct drm_display_mode *mode,
8100 int x, int y, struct drm_framebuffer *fb)
8101{
8102 int ret;
8103
8104 ret = __intel_set_mode(crtc, mode, x, y, fb);
8105
8106 if (ret == 0)
8107 intel_modeset_check_state(crtc->dev);
8108
8109 return ret;
8110}
8111
c0c36b94
CW		 8112void intel_crtc_restore_mode(struct drm_crtc *crtc)
8113{
8114 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8115}
8116
25c5b266
DV		 8117#undef for_each_intel_crtc_masked
8118
d9e55608
DV		 8119static void intel_set_config_free(struct intel_set_config *config)
8120{
8121 if (!config)
8122 return;
8123
1aa4b628
DV		 8124 kfree(config->save_connector_encoders);
8125 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8126 kfree(config);
8127}
8128
85f9eb71
DV		 8129static int intel_set_config_save_state(struct drm_device *dev,
8130 struct intel_set_config *config)
8131{
85f9eb71
DV		 8132 struct drm_encoder *encoder;
8133 struct drm_connector *connector;
8134 int count;
8135
1aa4b628
DV		 8136 config->save_encoder_crtcs =
8137 kcalloc(dev->mode_config.num_encoder,
8138 sizeof(struct drm_crtc *), GFP_KERNEL);
8139 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8140 return -ENOMEM;
8141
1aa4b628
DV		 8142 config->save_connector_encoders =
8143 kcalloc(dev->mode_config.num_connector,
8144 sizeof(struct drm_encoder *), GFP_KERNEL);
8145 if (!config->save_connector_encoders)
85f9eb71
DV		 8146 return -ENOMEM;
8147
8148 /* Copy data. Note that driver private data is not affected.
8149 * Should anything bad happen only the expected state is
8150 * restored, not the drivers personal bookkeeping.
8151 */
85f9eb71
DV		 8152 count = 0;
8153 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8154 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8155 }
8156
8157 count = 0;
8158 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8159 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8160 }
8161
8162 return 0;
8163}
8164
8165static void intel_set_config_restore_state(struct drm_device *dev,
8166 struct intel_set_config *config)
8167{
9a935856
DV		 8168 struct intel_encoder *encoder;
8169 struct intel_connector *connector;
85f9eb71
DV		 8170 int count;
8171
85f9eb71 8172 count = 0;
9a935856
DV		 8173 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8174 encoder->new_crtc =
8175 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8176 }
8177
8178 count = 0;
9a935856
DV		 8179 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8180 connector->new_encoder =
8181 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8182 }
8183}
8184
5e2b584e
DV		 8185static void
8186intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8187 struct intel_set_config *config)
8188{
8189
8190 /* We should be able to check here if the fb has the same properties
8191 * and then just flip_or_move it */
8192 if (set->crtc->fb != set->fb) {
8193 /* If we have no fb then treat it as a full mode set */
8194 if (set->crtc->fb == NULL) {
8195 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8196 config->mode_changed = true;
8197 } else if (set->fb == NULL) {
8198 config->mode_changed = true;
72f4901e
DV		 8199 } else if (set->fb->pixel_format !=
8200 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8201 config->mode_changed = true;
8202 } else
8203 config->fb_changed = true;
8204 }
8205
835c5873 8206 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8207 config->fb_changed = true;
8208
8209 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8210 DRM_DEBUG_KMS("modes are different, full mode set\n");
8211 drm_mode_debug_printmodeline(&set->crtc->mode);
8212 drm_mode_debug_printmodeline(set->mode);
8213 config->mode_changed = true;
8214 }
8215}
8216
2e431051 8217static int
9a935856
DV		 8218intel_modeset_stage_output_state(struct drm_device *dev,
8219 struct drm_mode_set *set,
8220 struct intel_set_config *config)
50f56119 8221{
85f9eb71 8222 struct drm_crtc *new_crtc;
9a935856
DV		 8223 struct intel_connector *connector;
8224 struct intel_encoder *encoder;
2e431051 8225 int count, ro;
50f56119 8226
9abdda74 8227 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8228 * of connectors. For paranoia, double-check this. */
8229 WARN_ON(!set->fb && (set->num_connectors != 0));
8230 WARN_ON(set->fb && (set->num_connectors == 0));
8231
50f56119 8232 count = 0;
9a935856
DV		 8233 list_for_each_entry(connector, &dev->mode_config.connector_list,
8234 base.head) {
8235 /* Otherwise traverse passed in connector list and get encoders
8236 * for them. */
50f56119 8237 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8238 if (set->connectors[ro] == &connector->base) {
8239 connector->new_encoder = connector->encoder;
50f56119
DV		 8240 break;
8241 }
8242 }
8243
9a935856
DV		 8244 /* If we disable the crtc, disable all its connectors. Also, if
8245 * the connector is on the changing crtc but not on the new
8246 * connector list, disable it. */
8247 if ((!set->fb || ro == set->num_connectors) &&
8248 connector->base.encoder &&
8249 connector->base.encoder->crtc == set->crtc) {
8250 connector->new_encoder = NULL;
8251
8252 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8253 connector->base.base.id,
8254 drm_get_connector_name(&connector->base));
8255 }
8256
8257
8258 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8259 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8260 config->mode_changed = true;
50f56119
DV		 8261 }
8262 }
9a935856 8263 /* connector->new_encoder is now updated for all connectors. */
50f56119 8264
9a935856 8265 /* Update crtc of enabled connectors. */
50f56119 8266 count = 0;
9a935856
DV		 8267 list_for_each_entry(connector, &dev->mode_config.connector_list,
8268 base.head) {
8269 if (!connector->new_encoder)
50f56119
DV		 8270 continue;
8271
9a935856 8272 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8273
8274 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8275 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8276 new_crtc = set->crtc;
8277 }
8278
8279 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8280 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8281 new_crtc)) {
5e2b584e 8282 return -EINVAL;
50f56119 8283 }
9a935856
DV		 8284 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8285
8286 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8287 connector->base.base.id,
8288 drm_get_connector_name(&connector->base),
8289 new_crtc->base.id);
8290 }
8291
8292 /* Check for any encoders that needs to be disabled. */
8293 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8294 base.head) {
8295 list_for_each_entry(connector,
8296 &dev->mode_config.connector_list,
8297 base.head) {
8298 if (connector->new_encoder == encoder) {
8299 WARN_ON(!connector->new_encoder->new_crtc);
8300
8301 goto next_encoder;
8302 }
8303 }
8304 encoder->new_crtc = NULL;
8305next_encoder:
8306 /* Only now check for crtc changes so we don't miss encoders
8307 * that will be disabled. */
8308 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8309 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8310 config->mode_changed = true;
50f56119
DV		 8311 }
8312 }
9a935856 8313 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8314
2e431051
DV		 8315 return 0;
8316}
8317
8318static int intel_crtc_set_config(struct drm_mode_set *set)
8319{
8320 struct drm_device *dev;
2e431051
DV		 8321 struct drm_mode_set save_set;
8322 struct intel_set_config *config;
8323 int ret;
2e431051 8324
8d3e375e
DV		 8325 BUG_ON(!set);
8326 BUG_ON(!set->crtc);
8327 BUG_ON(!set->crtc->helper_private);
2e431051 8328
7e53f3a4
DV		 8329 /* Enforce sane interface api - has been abused by the fb helper. */
8330 BUG_ON(!set->mode && set->fb);
8331 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8332
2e431051
DV		 8333 if (set->fb) {
8334 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8335 set->crtc->base.id, set->fb->base.id,
8336 (int)set->num_connectors, set->x, set->y);
8337 } else {
8338 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8339 }
8340
8341 dev = set->crtc->dev;
8342
8343 ret = -ENOMEM;
8344 config = kzalloc(sizeof(*config), GFP_KERNEL);
8345 if (!config)
8346 goto out_config;
8347
8348 ret = intel_set_config_save_state(dev, config);
8349 if (ret)
8350 goto out_config;
8351
8352 save_set.crtc = set->crtc;
8353 save_set.mode = &set->crtc->mode;
8354 save_set.x = set->crtc->x;
8355 save_set.y = set->crtc->y;
8356 save_set.fb = set->crtc->fb;
8357
8358 /* Compute whether we need a full modeset, only an fb base update or no
8359 * change at all. In the future we might also check whether only the
8360 * mode changed, e.g. for LVDS where we only change the panel fitter in
8361 * such cases. */
8362 intel_set_config_compute_mode_changes(set, config);
8363
9a935856 8364 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8365 if (ret)
8366 goto fail;
8367
5e2b584e 8368 if (config->mode_changed) {
87f1faa6 8369 if (set->mode) {
50f56119
DV		 8370 DRM_DEBUG_KMS("attempting to set mode from"
8371 " userspace\n");
8372 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8373 }
8374
c0c36b94
CW		 8375 ret = intel_set_mode(set->crtc, set->mode,
8376 set->x, set->y, set->fb);
8377 if (ret) {
8378 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8379 set->crtc->base.id, ret);
87f1faa6
DV		 8380 goto fail;
8381 }
5e2b584e 8382 } else if (config->fb_changed) {
4878cae2
VS		 8383 intel_crtc_wait_for_pending_flips(set->crtc);
8384
4f660f49 8385 ret = intel_pipe_set_base(set->crtc,
94352cf9 8386 set->x, set->y, set->fb);
50f56119
DV		 8387 }
8388
d9e55608
DV		 8389 intel_set_config_free(config);
8390
50f56119
DV		 8391 return 0;
8392
8393fail:
85f9eb71 8394 intel_set_config_restore_state(dev, config);
50f56119
DV		 8395
8396 /* Try to restore the config */
5e2b584e 8397 if (config->mode_changed &&
c0c36b94
CW		 8398 intel_set_mode(save_set.crtc, save_set.mode,
8399 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8400 DRM_ERROR("failed to restore config after modeset failure\n");
8401
d9e55608
DV		 8402out_config:
8403 intel_set_config_free(config);
50f56119
DV		 8404 return ret;
8405}
f6e5b160
CW		 8406
8407static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8408 .cursor_set = intel_crtc_cursor_set,
8409 .cursor_move = intel_crtc_cursor_move,
8410 .gamma_set = intel_crtc_gamma_set,
50f56119 8411 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8412 .destroy = intel_crtc_destroy,
8413 .page_flip = intel_crtc_page_flip,
8414};
8415
79f689aa
PZ		 8416static void intel_cpu_pll_init(struct drm_device *dev)
8417{
affa9354 8418 if (HAS_DDI(dev))
79f689aa
PZ		 8419 intel_ddi_pll_init(dev);
8420}
8421
ee7b9f93
JB		 8422static void intel_pch_pll_init(struct drm_device *dev)
8423{
8424 drm_i915_private_t *dev_priv = dev->dev_private;
8425 int i;
8426
8427 if (dev_priv->num_pch_pll == 0) {
8428 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8429 return;
8430 }
8431
8432 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8433 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8434 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8435 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8436 }
8437}
8438
b358d0a6 8439static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8440{
22fd0fab 8441 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8442 struct intel_crtc *intel_crtc;
8443 int i;
8444
8445 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8446 if (intel_crtc == NULL)
8447 return;
8448
8449 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8450
8451 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8452 for (i = 0; i < 256; i++) {
8453 intel_crtc->lut_r[i] = i;
8454 intel_crtc->lut_g[i] = i;
8455 intel_crtc->lut_b[i] = i;
8456 }
8457
80824003
JB		 8458 /* Swap pipes & planes for FBC on pre-965 */
8459 intel_crtc->pipe = pipe;
8460 intel_crtc->plane = pipe;
3b117c8f 8461 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8462 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8463 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8464 intel_crtc->plane = !pipe;
80824003
JB		 8465 }
8466
22fd0fab
JB		 8467 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8468 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8469 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8470 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8471
79e53945 8472 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8473}
8474
08d7b3d1 8475int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8476 struct drm_file *file)
08d7b3d1 8477{
08d7b3d1 8478 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8479 struct drm_mode_object *drmmode_obj;
8480 struct intel_crtc *crtc;
08d7b3d1 8481
1cff8f6b
DV		 8482 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8483 return -ENODEV;
08d7b3d1 8484
c05422d5
DV		 8485 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8486 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8487
c05422d5 8488 if (!drmmode_obj) {
08d7b3d1
CW		 8489 DRM_ERROR("no such CRTC id\n");
8490 return -EINVAL;
8491 }
8492
c05422d5
DV		 8493 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8494 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8495
c05422d5 8496 return 0;
08d7b3d1
CW		 8497}
8498
66a9278e 8499static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8500{
66a9278e
DV		 8501 struct drm_device *dev = encoder->base.dev;
8502 struct intel_encoder *source_encoder;
79e53945 8503 int index_mask = 0;
79e53945
JB		 8504 int entry = 0;
8505
66a9278e
DV		 8506 list_for_each_entry(source_encoder,
8507 &dev->mode_config.encoder_list, base.head) {
8508
8509 if (encoder == source_encoder)
79e53945 8510 index_mask |= (1 << entry);
66a9278e
DV		 8511
8512 /* Intel hw has only one MUX where enocoders could be cloned. */
8513 if (encoder->cloneable && source_encoder->cloneable)
8514 index_mask |= (1 << entry);
8515
79e53945
JB		 8516 entry++;
8517 }
4ef69c7a 8518
79e53945
JB		 8519 return index_mask;
8520}
8521
4d302442
CW		 8522static bool has_edp_a(struct drm_device *dev)
8523{
8524 struct drm_i915_private *dev_priv = dev->dev_private;
8525
8526 if (!IS_MOBILE(dev))
8527 return false;
8528
8529 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8530 return false;
8531
8532 if (IS_GEN5(dev) &&
8533 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8534 return false;
8535
8536 return true;
8537}
8538
79e53945
JB		 8539static void intel_setup_outputs(struct drm_device *dev)
8540{
725e30ad 8541 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8542 struct intel_encoder *encoder;
cb0953d7 8543 bool dpd_is_edp = false;
f3cfcba6 8544 bool has_lvds;
79e53945 8545
f3cfcba6 8546 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8547 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8548 /* disable the panel fitter on everything but LVDS */
8549 I915_WRITE(PFIT_CONTROL, 0);
8550 }
79e53945 8551
c40c0f5b 8552 if (!IS_ULT(dev))
79935fca 8553 intel_crt_init(dev);
cb0953d7 8554
affa9354 8555 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8556 int found;
8557
8558 /* Haswell uses DDI functions to detect digital outputs */
8559 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8560 /* DDI A only supports eDP */
8561 if (found)
8562 intel_ddi_init(dev, PORT_A);
8563
8564 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8565 * register */
8566 found = I915_READ(SFUSE_STRAP);
8567
8568 if (found & SFUSE_STRAP_DDIB_DETECTED)
8569 intel_ddi_init(dev, PORT_B);
8570 if (found & SFUSE_STRAP_DDIC_DETECTED)
8571 intel_ddi_init(dev, PORT_C);
8572 if (found & SFUSE_STRAP_DDID_DETECTED)
8573 intel_ddi_init(dev, PORT_D);
8574 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8575 int found;
270b3042
DV		 8576 dpd_is_edp = intel_dpd_is_edp(dev);
8577
8578 if (has_edp_a(dev))
8579 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8580
dc0fa718 8581 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8582 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8583 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8584 if (!found)
e2debe91 8585 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8586 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8587 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8588 }
8589
dc0fa718 8590 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8591 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8592
dc0fa718 8593 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8594 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8595
5eb08b69 8596 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8597 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8598
270b3042 8599 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8600 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8601 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8602 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8603 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8604 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8605
dc0fa718 8606 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8607 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8608 PORT_B);
67cfc203
VS		 8609 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8610 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8611 }
103a196f 8612 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8613 bool found = false;
7d57382e 8614
e2debe91 8615 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8616 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8617 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8618 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8619 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8620 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8621 }
27185ae1 8622
b01f2c3a
JB		 8623 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8624 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8625 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8626 }
725e30ad 8627 }
13520b05
KH		 8628
8629 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8630
e2debe91 8631 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8632 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8633 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8634 }
27185ae1 8635
e2debe91 8636 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8637
b01f2c3a
JB		 8638 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8639 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8640 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8641 }
8642 if (SUPPORTS_INTEGRATED_DP(dev)) {
8643 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8644 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8645 }
725e30ad 8646 }
27185ae1 8647
b01f2c3a
JB		 8648 if (SUPPORTS_INTEGRATED_DP(dev) &&
8649 (I915_READ(DP_D) & DP_DETECTED)) {
8650 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8651 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8652 }
bad720ff 8653 } else if (IS_GEN2(dev))
79e53945
JB		 8654 intel_dvo_init(dev);
8655
103a196f 8656 if (SUPPORTS_TV(dev))
79e53945
JB		 8657 intel_tv_init(dev);
8658
4ef69c7a
CW		 8659 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8660 encoder->base.possible_crtcs = encoder->crtc_mask;
8661 encoder->base.possible_clones =
66a9278e 8662 intel_encoder_clones(encoder);
79e53945 8663 }
47356eb6 8664
dde86e2d 8665 intel_init_pch_refclk(dev);
270b3042
DV		 8666
8667 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8668}
8669
8670static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8671{
8672 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8673
8674 drm_framebuffer_cleanup(fb);
05394f39 8675 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8676
8677 kfree(intel_fb);
8678}
8679
8680static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8681 struct drm_file *file,
79e53945
JB		 8682 unsigned int *handle)
8683{
8684 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8685 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8686
05394f39 8687 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8688}
8689
8690static const struct drm_framebuffer_funcs intel_fb_funcs = {
8691 .destroy = intel_user_framebuffer_destroy,
8692 .create_handle = intel_user_framebuffer_create_handle,
8693};
8694
38651674
DA		 8695int intel_framebuffer_init(struct drm_device *dev,
8696 struct intel_framebuffer *intel_fb,
308e5bcb 8697 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8698 struct drm_i915_gem_object *obj)
79e53945 8699{
79e53945
JB		 8700 int ret;
8701
c16ed4be
CW		 8702 if (obj->tiling_mode == I915_TILING_Y) {
8703 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8704 return -EINVAL;
c16ed4be 8705 }
57cd6508 8706
c16ed4be
CW		 8707 if (mode_cmd->pitches[0] & 63) {
8708 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8709 mode_cmd->pitches[0]);
57cd6508 8710 return -EINVAL;
c16ed4be 8711 }
57cd6508 8712
5d7bd705 8713 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8714 if (mode_cmd->pitches[0] > 32768) {
8715 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8716 mode_cmd->pitches[0]);
5d7bd705 8717 return -EINVAL;
c16ed4be 8718 }
5d7bd705
VS		 8719
8720 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8721 mode_cmd->pitches[0] != obj->stride) {
8722 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8723 mode_cmd->pitches[0], obj->stride);
5d7bd705 8724 return -EINVAL;
c16ed4be 8725 }
5d7bd705 8726
57779d06 8727 /* Reject formats not supported by any plane early. */
308e5bcb 8728 switch (mode_cmd->pixel_format) {
57779d06 8729 case DRM_FORMAT_C8:
04b3924d
VS		 8730 case DRM_FORMAT_RGB565:
8731 case DRM_FORMAT_XRGB8888:
8732 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8733 break;
8734 case DRM_FORMAT_XRGB1555:
8735 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8736 if (INTEL_INFO(dev)->gen > 3) {
8737 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8738 return -EINVAL;
c16ed4be 8739 }
57779d06
VS		 8740 break;
8741 case DRM_FORMAT_XBGR8888:
8742 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8743 case DRM_FORMAT_XRGB2101010:
8744 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8745 case DRM_FORMAT_XBGR2101010:
8746 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8747 if (INTEL_INFO(dev)->gen < 4) {
8748 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8749 return -EINVAL;
c16ed4be 8750 }
b5626747 8751 break;
04b3924d
VS		 8752 case DRM_FORMAT_YUYV:
8753 case DRM_FORMAT_UYVY:
8754 case DRM_FORMAT_YVYU:
8755 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8756 if (INTEL_INFO(dev)->gen < 5) {
8757 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8758 return -EINVAL;
c16ed4be 8759 }
57cd6508
CW		 8760 break;
8761 default:
c16ed4be 8762 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8763 return -EINVAL;
8764 }
8765
90f9a336
VS		 8766 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8767 if (mode_cmd->offsets[0] != 0)
8768 return -EINVAL;
8769
c7d73f6a
DV		 8770 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8771 intel_fb->obj = obj;
8772
79e53945
JB		 8773 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8774 if (ret) {
8775 DRM_ERROR("framebuffer init failed %d\n", ret);
8776 return ret;
8777 }
8778
79e53945
JB		 8779 return 0;
8780}
8781
79e53945
JB		 8782static struct drm_framebuffer *
8783intel_user_framebuffer_create(struct drm_device *dev,
8784 struct drm_file *filp,
308e5bcb 8785 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8786{
05394f39 8787 struct drm_i915_gem_object *obj;
79e53945 8788
308e5bcb
JB		 8789 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8790 mode_cmd->handles[0]));
c8725226 8791 if (&obj->base == NULL)
cce13ff7 8792 return ERR_PTR(-ENOENT);
79e53945 8793
d2dff872 8794 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8795}
8796
79e53945 8797static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8798 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8799 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8800};
8801
e70236a8
JB		 8802/* Set up chip specific display functions */
8803static void intel_init_display(struct drm_device *dev)
8804{
8805 struct drm_i915_private *dev_priv = dev->dev_private;
8806
affa9354 8807 if (HAS_DDI(dev)) {
0e8ffe1b 8808 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8809 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8810 dev_priv->display.crtc_enable = haswell_crtc_enable;
8811 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8812 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8813 dev_priv->display.update_plane = ironlake_update_plane;
8814 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8815 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8816 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8817 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8818 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8819 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8820 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8821 } else if (IS_VALLEYVIEW(dev)) {
8822 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8823 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8824 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8825 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8826 dev_priv->display.off = i9xx_crtc_off;
8827 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8828 } else {
0e8ffe1b 8829 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8830 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8831 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8832 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8833 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8834 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8835 }
e70236a8 8836
e70236a8 8837 /* Returns the core display clock speed */
25eb05fc
JB		 8838 if (IS_VALLEYVIEW(dev))
8839 dev_priv->display.get_display_clock_speed =
8840 valleyview_get_display_clock_speed;
8841 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8842 dev_priv->display.get_display_clock_speed =
8843 i945_get_display_clock_speed;
8844 else if (IS_I915G(dev))
8845 dev_priv->display.get_display_clock_speed =
8846 i915_get_display_clock_speed;
f2b115e6 8847 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8848 dev_priv->display.get_display_clock_speed =
8849 i9xx_misc_get_display_clock_speed;
8850 else if (IS_I915GM(dev))
8851 dev_priv->display.get_display_clock_speed =
8852 i915gm_get_display_clock_speed;
8853 else if (IS_I865G(dev))
8854 dev_priv->display.get_display_clock_speed =
8855 i865_get_display_clock_speed;
f0f8a9ce 8856 else if (IS_I85X(dev))
e70236a8
JB		 8857 dev_priv->display.get_display_clock_speed =
8858 i855_get_display_clock_speed;
8859 else /* 852, 830 */
8860 dev_priv->display.get_display_clock_speed =
8861 i830_get_display_clock_speed;
8862
7f8a8569 8863 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8864 if (IS_GEN5(dev)) {
674cf967 8865 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8866 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8867 } else if (IS_GEN6(dev)) {
674cf967 8868 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8869 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8870 } else if (IS_IVYBRIDGE(dev)) {
8871 /* FIXME: detect B0+ stepping and use auto training */
8872 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8873 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8874 dev_priv->display.modeset_global_resources =
8875 ivb_modeset_global_resources;
c82e4d26
ED		 8876 } else if (IS_HASWELL(dev)) {
8877 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8878 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8879 dev_priv->display.modeset_global_resources =
8880 haswell_modeset_global_resources;
a0e63c22 8881 }
6067aaea 8882 } else if (IS_G4X(dev)) {
e0dac65e 8883 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8884 }
8c9f3aaf
JB		 8885
8886 /* Default just returns -ENODEV to indicate unsupported */
8887 dev_priv->display.queue_flip = intel_default_queue_flip;
8888
8889 switch (INTEL_INFO(dev)->gen) {
8890 case 2:
8891 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8892 break;
8893
8894 case 3:
8895 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8896 break;
8897
8898 case 4:
8899 case 5:
8900 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8901 break;
8902
8903 case 6:
8904 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8905 break;
7c9017e5
JB		 8906 case 7:
8907 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8908 break;
8c9f3aaf 8909 }
e70236a8
JB		 8910}
8911
b690e96c
JB		 8912/*
8913 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8914 * resume, or other times. This quirk makes sure that's the case for
8915 * affected systems.
8916 */
0206e353 8917static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8918{
8919 struct drm_i915_private *dev_priv = dev->dev_private;
8920
8921 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8922 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8923}
8924
435793df
KP		 8925/*
8926 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8927 */
8928static void quirk_ssc_force_disable(struct drm_device *dev)
8929{
8930 struct drm_i915_private *dev_priv = dev->dev_private;
8931 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8932 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8933}
8934
4dca20ef 8935/*
5a15ab5b
CE		 8936 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8937 * brightness value
4dca20ef
CE		 8938 */
8939static void quirk_invert_brightness(struct drm_device *dev)
8940{
8941 struct drm_i915_private *dev_priv = dev->dev_private;
8942 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8943 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8944}
8945
b690e96c
JB		 8946struct intel_quirk {
8947 int device;
8948 int subsystem_vendor;
8949 int subsystem_device;
8950 void (*hook)(struct drm_device *dev);
8951};
8952
5f85f176
EE		 8953/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8954struct intel_dmi_quirk {
8955 void (*hook)(struct drm_device *dev);
8956 const struct dmi_system_id (*dmi_id_list)[];
8957};
8958
8959static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8960{
8961 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8962 return 1;
8963}
8964
8965static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8966 {
8967 .dmi_id_list = &(const struct dmi_system_id[]) {
8968 {
8969 .callback = intel_dmi_reverse_brightness,
8970 .ident = "NCR Corporation",
8971 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8972 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8973 },
8974 },
8975 { } /* terminating entry */
8976 },
8977 .hook = quirk_invert_brightness,
8978 },
8979};
8980
c43b5634 8981static struct intel_quirk intel_quirks[] = {
b690e96c 8982 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8983 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8984
b690e96c
JB		 8985 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8986 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8987
b690e96c
JB		 8988 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8989 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8990
ccd0d36e 8991 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8992 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8993 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8994
8995 /* Lenovo U160 cannot use SSC on LVDS */
8996 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8997
8998 /* Sony Vaio Y cannot use SSC on LVDS */
8999 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9000
9001 /* Acer Aspire 5734Z must invert backlight brightness */
9002 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9003
9004 /* Acer/eMachines G725 */
9005 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9006
9007 /* Acer/eMachines e725 */
9008 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9009
9010 /* Acer/Packard Bell NCL20 */
9011 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9012
9013 /* Acer Aspire 4736Z */
9014 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9015};
9016
9017static void intel_init_quirks(struct drm_device *dev)
9018{
9019 struct pci_dev *d = dev->pdev;
9020 int i;
9021
9022 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9023 struct intel_quirk *q = &intel_quirks[i];
9024
9025 if (d->device == q->device &&
9026 (d->subsystem_vendor == q->subsystem_vendor ||
9027 q->subsystem_vendor == PCI_ANY_ID) &&
9028 (d->subsystem_device == q->subsystem_device ||
9029 q->subsystem_device == PCI_ANY_ID))
9030 q->hook(dev);
9031 }
5f85f176
EE		 9032 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9033 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9034 intel_dmi_quirks[i].hook(dev);
9035 }
b690e96c
JB		 9036}
9037
9cce37f4
JB		 9038/* Disable the VGA plane that we never use */
9039static void i915_disable_vga(struct drm_device *dev)
9040{
9041 struct drm_i915_private *dev_priv = dev->dev_private;
9042 u8 sr1;
766aa1c4 9043 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9044
9045 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9046 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9047 sr1 = inb(VGA_SR_DATA);
9048 outb(sr1 | 1<<5, VGA_SR_DATA);
9049 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9050 udelay(300);
9051
9052 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9053 POSTING_READ(vga_reg);
9054}
9055
f817586c
DV		 9056void intel_modeset_init_hw(struct drm_device *dev)
9057{
fa42e23c 9058 intel_init_power_well(dev);
0232e927 9059
a8f78b58
ED		 9060 intel_prepare_ddi(dev);
9061
f817586c
DV		 9062 intel_init_clock_gating(dev);
9063
79f5b2c7 9064 mutex_lock(&dev->struct_mutex);
8090c6b9 9065 intel_enable_gt_powersave(dev);
79f5b2c7 9066 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9067}
9068
79e53945
JB		 9069void intel_modeset_init(struct drm_device *dev)
9070{
652c393a 9071 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9072 int i, j, ret;
79e53945
JB		 9073
9074 drm_mode_config_init(dev);
9075
9076 dev->mode_config.min_width = 0;
9077 dev->mode_config.min_height = 0;
9078
019d96cb
DA		 9079 dev->mode_config.preferred_depth = 24;
9080 dev->mode_config.prefer_shadow = 1;
9081
e6ecefaa 9082 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9083
b690e96c
JB		 9084 intel_init_quirks(dev);
9085
1fa61106
ED		 9086 intel_init_pm(dev);
9087
e3c74757
BW		 9088 if (INTEL_INFO(dev)->num_pipes == 0)
9089 return;
9090
e70236a8
JB		 9091 intel_init_display(dev);
9092
a6c45cf0
CW		 9093 if (IS_GEN2(dev)) {
9094 dev->mode_config.max_width = 2048;
9095 dev->mode_config.max_height = 2048;
9096 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9097 dev->mode_config.max_width = 4096;
9098 dev->mode_config.max_height = 4096;
79e53945 9099 } else {
a6c45cf0
CW		 9100 dev->mode_config.max_width = 8192;
9101 dev->mode_config.max_height = 8192;
79e53945 9102 }
5d4545ae 9103 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9104
28c97730 9105 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9106 INTEL_INFO(dev)->num_pipes,
9107 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9108
7eb552ae 9109 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9110 intel_crtc_init(dev, i);
7f1f3851
JB		 9111 for (j = 0; j < dev_priv->num_plane; j++) {
9112 ret = intel_plane_init(dev, i, j);
9113 if (ret)
06da8da2
VS		 9114 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9115 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9116 }
79e53945
JB		 9117 }
9118
79f689aa 9119 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9120 intel_pch_pll_init(dev);
9121
9cce37f4
JB		 9122 /* Just disable it once at startup */
9123 i915_disable_vga(dev);
79e53945 9124 intel_setup_outputs(dev);
11be49eb
CW		 9125
9126 /* Just in case the BIOS is doing something questionable. */
9127 intel_disable_fbc(dev);
2c7111db
CW		 9128}
9129
24929352
DV		 9130static void
9131intel_connector_break_all_links(struct intel_connector *connector)
9132{
9133 connector->base.dpms = DRM_MODE_DPMS_OFF;
9134 connector->base.encoder = NULL;
9135 connector->encoder->connectors_active = false;
9136 connector->encoder->base.crtc = NULL;
9137}
9138
7fad798e
DV		 9139static void intel_enable_pipe_a(struct drm_device *dev)
9140{
9141 struct intel_connector *connector;
9142 struct drm_connector *crt = NULL;
9143 struct intel_load_detect_pipe load_detect_temp;
9144
9145 /* We can't just switch on the pipe A, we need to set things up with a
9146 * proper mode and output configuration. As a gross hack, enable pipe A
9147 * by enabling the load detect pipe once. */
9148 list_for_each_entry(connector,
9149 &dev->mode_config.connector_list,
9150 base.head) {
9151 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9152 crt = &connector->base;
9153 break;
9154 }
9155 }
9156
9157 if (!crt)
9158 return;
9159
9160 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9161 intel_release_load_detect_pipe(crt, &load_detect_temp);
9162
652c393a 9163
7fad798e
DV		 9164}
9165
fa555837
DV		 9166static bool
9167intel_check_plane_mapping(struct intel_crtc *crtc)
9168{
7eb552ae
BW		 9169 struct drm_device *dev = crtc->base.dev;
9170 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9171 u32 reg, val;
9172
7eb552ae 9173 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9174 return true;
9175
9176 reg = DSPCNTR(!crtc->plane);
9177 val = I915_READ(reg);
9178
9179 if ((val & DISPLAY_PLANE_ENABLE) &&
9180 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9181 return false;
9182
9183 return true;
9184}
9185
24929352
DV		 9186static void intel_sanitize_crtc(struct intel_crtc *crtc)
9187{
9188 struct drm_device *dev = crtc->base.dev;
9189 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9190 u32 reg;
24929352 9191
24929352 9192 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9193 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9194 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9195
9196 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9197 * disable the crtc (and hence change the state) if it is wrong. Note
9198 * that gen4+ has a fixed plane -> pipe mapping. */
9199 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9200 struct intel_connector *connector;
9201 bool plane;
9202
24929352
DV		 9203 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9204 crtc->base.base.id);
9205
9206 /* Pipe has the wrong plane attached and the plane is active.
9207 * Temporarily change the plane mapping and disable everything
9208 * ... */
9209 plane = crtc->plane;
9210 crtc->plane = !plane;
9211 dev_priv->display.crtc_disable(&crtc->base);
9212 crtc->plane = plane;
9213
9214 /* ... and break all links. */
9215 list_for_each_entry(connector, &dev->mode_config.connector_list,
9216 base.head) {
9217 if (connector->encoder->base.crtc != &crtc->base)
9218 continue;
9219
9220 intel_connector_break_all_links(connector);
9221 }
9222
9223 WARN_ON(crtc->active);
9224 crtc->base.enabled = false;
9225 }
24929352 9226
7fad798e
DV		 9227 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9228 crtc->pipe == PIPE_A && !crtc->active) {
9229 /* BIOS forgot to enable pipe A, this mostly happens after
9230 * resume. Force-enable the pipe to fix this, the update_dpms
9231 * call below we restore the pipe to the right state, but leave
9232 * the required bits on. */
9233 intel_enable_pipe_a(dev);
9234 }
9235
24929352
DV		 9236 /* Adjust the state of the output pipe according to whether we
9237 * have active connectors/encoders. */
9238 intel_crtc_update_dpms(&crtc->base);
9239
9240 if (crtc->active != crtc->base.enabled) {
9241 struct intel_encoder *encoder;
9242
9243 /* This can happen either due to bugs in the get_hw_state
9244 * functions or because the pipe is force-enabled due to the
9245 * pipe A quirk. */
9246 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9247 crtc->base.base.id,
9248 crtc->base.enabled ? "enabled" : "disabled",
9249 crtc->active ? "enabled" : "disabled");
9250
9251 crtc->base.enabled = crtc->active;
9252
9253 /* Because we only establish the connector -> encoder ->
9254 * crtc links if something is active, this means the
9255 * crtc is now deactivated. Break the links. connector
9256 * -> encoder links are only establish when things are
9257 * actually up, hence no need to break them. */
9258 WARN_ON(crtc->active);
9259
9260 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9261 WARN_ON(encoder->connectors_active);
9262 encoder->base.crtc = NULL;
9263 }
9264 }
9265}
9266
9267static void intel_sanitize_encoder(struct intel_encoder *encoder)
9268{
9269 struct intel_connector *connector;
9270 struct drm_device *dev = encoder->base.dev;
9271
9272 /* We need to check both for a crtc link (meaning that the
9273 * encoder is active and trying to read from a pipe) and the
9274 * pipe itself being active. */
9275 bool has_active_crtc = encoder->base.crtc &&
9276 to_intel_crtc(encoder->base.crtc)->active;
9277
9278 if (encoder->connectors_active && !has_active_crtc) {
9279 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9280 encoder->base.base.id,
9281 drm_get_encoder_name(&encoder->base));
9282
9283 /* Connector is active, but has no active pipe. This is
9284 * fallout from our resume register restoring. Disable
9285 * the encoder manually again. */
9286 if (encoder->base.crtc) {
9287 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9288 encoder->base.base.id,
9289 drm_get_encoder_name(&encoder->base));
9290 encoder->disable(encoder);
9291 }
9292
9293 /* Inconsistent output/port/pipe state happens presumably due to
9294 * a bug in one of the get_hw_state functions. Or someplace else
9295 * in our code, like the register restore mess on resume. Clamp
9296 * things to off as a safer default. */
9297 list_for_each_entry(connector,
9298 &dev->mode_config.connector_list,
9299 base.head) {
9300 if (connector->encoder != encoder)
9301 continue;
9302
9303 intel_connector_break_all_links(connector);
9304 }
9305 }
9306 /* Enabled encoders without active connectors will be fixed in
9307 * the crtc fixup. */
9308}
9309
44cec740 9310void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9311{
9312 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9313 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9314
9315 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9316 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9317 i915_disable_vga(dev);
0fde901f
KM		 9318 }
9319}
9320
24929352
DV		 9321/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9322 * and i915 state tracking structures. */
45e2b5f6
DV		 9323void intel_modeset_setup_hw_state(struct drm_device *dev,
9324 bool force_restore)
24929352
DV		 9325{
9326 struct drm_i915_private *dev_priv = dev->dev_private;
9327 enum pipe pipe;
9328 u32 tmp;
b5644d05 9329 struct drm_plane *plane;
24929352
DV		 9330 struct intel_crtc *crtc;
9331 struct intel_encoder *encoder;
9332 struct intel_connector *connector;
9333
affa9354 9334 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9335 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9336
9337 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9338 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9339 case TRANS_DDI_EDP_INPUT_A_ON:
9340 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9341 pipe = PIPE_A;
9342 break;
9343 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9344 pipe = PIPE_B;
9345 break;
9346 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9347 pipe = PIPE_C;
9348 break;
aaa148ec
DL		 9349 default:
9350 /* A bogus value has been programmed, disable
9351 * the transcoder */
9352 WARN(1, "Bogus eDP source %08x\n", tmp);
9353 intel_ddi_disable_transcoder_func(dev_priv,
9354 TRANSCODER_EDP);
9355 goto setup_pipes;
e28d54cb
PZ		 9356 }
9357
9358 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9359 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9360
9361 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9362 pipe_name(pipe));
9363 }
9364 }
9365
aaa148ec 9366setup_pipes:
0e8ffe1b
DV		 9367 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9368 base.head) {
3b117c8f 9369 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9370 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9371 crtc->config.cpu_transcoder = tmp;
9372
0e8ffe1b
DV		 9373 crtc->active = dev_priv->display.get_pipe_config(crtc,
9374 &crtc->config);
24929352
DV		 9375
9376 crtc->base.enabled = crtc->active;
9377
9378 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9379 crtc->base.base.id,
9380 crtc->active ? "enabled" : "disabled");
9381 }
9382
affa9354 9383 if (HAS_DDI(dev))
6441ab5f
PZ		 9384 intel_ddi_setup_hw_pll_state(dev);
9385
24929352
DV		 9386 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9387 base.head) {
9388 pipe = 0;
9389
9390 if (encoder->get_hw_state(encoder, &pipe)) {
9391 encoder->base.crtc =
9392 dev_priv->pipe_to_crtc_mapping[pipe];
9393 } else {
9394 encoder->base.crtc = NULL;
9395 }
9396
9397 encoder->connectors_active = false;
9398 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9399 encoder->base.base.id,
9400 drm_get_encoder_name(&encoder->base),
9401 encoder->base.crtc ? "enabled" : "disabled",
9402 pipe);
9403 }
9404
9405 list_for_each_entry(connector, &dev->mode_config.connector_list,
9406 base.head) {
9407 if (connector->get_hw_state(connector)) {
9408 connector->base.dpms = DRM_MODE_DPMS_ON;
9409 connector->encoder->connectors_active = true;
9410 connector->base.encoder = &connector->encoder->base;
9411 } else {
9412 connector->base.dpms = DRM_MODE_DPMS_OFF;
9413 connector->base.encoder = NULL;
9414 }
9415 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9416 connector->base.base.id,
9417 drm_get_connector_name(&connector->base),
9418 connector->base.encoder ? "enabled" : "disabled");
9419 }
9420
9421 /* HW state is read out, now we need to sanitize this mess. */
9422 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9423 base.head) {
9424 intel_sanitize_encoder(encoder);
9425 }
9426
9427 for_each_pipe(pipe) {
9428 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9429 intel_sanitize_crtc(crtc);
9430 }
9a935856 9431
45e2b5f6 9432 if (force_restore) {
f30da187
DV		 9433 /*
9434 * We need to use raw interfaces for restoring state to avoid
9435 * checking (bogus) intermediate states.
9436 */
45e2b5f6 9437 for_each_pipe(pipe) {
b5644d05
JB		 9438 struct drm_crtc *crtc =
9439 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9440
9441 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9442 crtc->fb);
45e2b5f6 9443 }
b5644d05
JB		 9444 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9445 intel_plane_restore(plane);
0fde901f
KM		 9446
9447 i915_redisable_vga(dev);
45e2b5f6
DV		 9448 } else {
9449 intel_modeset_update_staged_output_state(dev);
9450 }
8af6cf88
DV		 9451
9452 intel_modeset_check_state(dev);
2e938892
DV		 9453
9454 drm_mode_config_reset(dev);
2c7111db
CW		 9455}
9456
9457void intel_modeset_gem_init(struct drm_device *dev)
9458{
1833b134 9459 intel_modeset_init_hw(dev);
02e792fb
DV		 9460
9461 intel_setup_overlay(dev);
24929352 9462
45e2b5f6 9463 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9464}
9465
9466void intel_modeset_cleanup(struct drm_device *dev)
9467{
652c393a
JB		 9468 struct drm_i915_private *dev_priv = dev->dev_private;
9469 struct drm_crtc *crtc;
9470 struct intel_crtc *intel_crtc;
9471
fd0c0642
DV		 9472 /*
9473 * Interrupts and polling as the first thing to avoid creating havoc.
9474 * Too much stuff here (turning of rps, connectors, ...) would
9475 * experience fancy races otherwise.
9476 */
9477 drm_irq_uninstall(dev);
9478 cancel_work_sync(&dev_priv->hotplug_work);
9479 /*
9480 * Due to the hpd irq storm handling the hotplug work can re-arm the
9481 * poll handlers. Hence disable polling after hpd handling is shut down.
9482 */
f87ea761 9483 drm_kms_helper_poll_fini(dev);
fd0c0642 9484
652c393a
JB		 9485 mutex_lock(&dev->struct_mutex);
9486
723bfd70
JB		 9487 intel_unregister_dsm_handler();
9488
652c393a
JB		 9489 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9490 /* Skip inactive CRTCs */
9491 if (!crtc->fb)
9492 continue;
9493
9494 intel_crtc = to_intel_crtc(crtc);
3dec0095 9495 intel_increase_pllclock(crtc);
652c393a
JB		 9496 }
9497
973d04f9 9498 intel_disable_fbc(dev);
e70236a8 9499
8090c6b9 9500 intel_disable_gt_powersave(dev);
0cdab21f 9501
930ebb46
DV		 9502 ironlake_teardown_rc6(dev);
9503
69341a5e
KH		 9504 mutex_unlock(&dev->struct_mutex);
9505
1630fe75
CW		 9506 /* flush any delayed tasks or pending work */
9507 flush_scheduled_work();
9508
dc652f90
JN		 9509 /* destroy backlight, if any, before the connectors */
9510 intel_panel_destroy_backlight(dev);
9511
79e53945 9512 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9513
9514 intel_cleanup_overlay(dev);
79e53945
JB		 9515}
9516
f1c79df3
ZW		 9517/*
9518 * Return which encoder is currently attached for connector.
9519 */
df0e9248 9520struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9521{
df0e9248
CW		 9522 return &intel_attached_encoder(connector)->base;
9523}
f1c79df3 9524
df0e9248
CW		 9525void intel_connector_attach_encoder(struct intel_connector *connector,
9526 struct intel_encoder *encoder)
9527{
9528 connector->encoder = encoder;
9529 drm_mode_connector_attach_encoder(&connector->base,
9530 &encoder->base);
79e53945 9531}
28d52043
DA		 9532
9533/*
9534 * set vga decode state - true == enable VGA decode
9535 */
9536int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9537{
9538 struct drm_i915_private *dev_priv = dev->dev_private;
9539 u16 gmch_ctrl;
9540
9541 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9542 if (state)
9543 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9544 else
9545 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9546 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9547 return 0;
9548}
c4a1d9e4
CW		 9549
9550#ifdef CONFIG_DEBUG_FS
9551#include <linux/seq_file.h>
9552
9553struct intel_display_error_state {
9554 struct intel_cursor_error_state {
9555 u32 control;
9556 u32 position;
9557 u32 base;
9558 u32 size;
52331309 9559 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9560
9561 struct intel_pipe_error_state {
9562 u32 conf;
9563 u32 source;
9564
9565 u32 htotal;
9566 u32 hblank;
9567 u32 hsync;
9568 u32 vtotal;
9569 u32 vblank;
9570 u32 vsync;
52331309 9571 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9572
9573 struct intel_plane_error_state {
9574 u32 control;
9575 u32 stride;
9576 u32 size;
9577 u32 pos;
9578 u32 addr;
9579 u32 surface;
9580 u32 tile_offset;
52331309 9581 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9582};
9583
9584struct intel_display_error_state *
9585intel_display_capture_error_state(struct drm_device *dev)
9586{
0206e353 9587 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9588 struct intel_display_error_state *error;
702e7a56 9589 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9590 int i;
9591
9592 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9593 if (error == NULL)
9594 return NULL;
9595
52331309 9596 for_each_pipe(i) {
702e7a56
PZ		 9597 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9598
a18c4c3d
PZ		 9599 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9600 error->cursor[i].control = I915_READ(CURCNTR(i));
9601 error->cursor[i].position = I915_READ(CURPOS(i));
9602 error->cursor[i].base = I915_READ(CURBASE(i));
9603 } else {
9604 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9605 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9606 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9607 }
c4a1d9e4
CW		 9608
9609 error->plane[i].control = I915_READ(DSPCNTR(i));
9610 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9611 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9612 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9613 error->plane[i].pos = I915_READ(DSPPOS(i));
9614 }
ca291363
PZ		 9615 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9616 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9617 if (INTEL_INFO(dev)->gen >= 4) {
9618 error->plane[i].surface = I915_READ(DSPSURF(i));
9619 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9620 }
9621
702e7a56 9622 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9623 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9624 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9625 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9626 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9627 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9628 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9629 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9630 }
9631
9632 return error;
9633}
9634
9635void
9636intel_display_print_error_state(struct seq_file *m,
9637 struct drm_device *dev,
9638 struct intel_display_error_state *error)
9639{
9640 int i;
9641
7eb552ae 9642 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9643 for_each_pipe(i) {
c4a1d9e4
CW		 9644 seq_printf(m, "Pipe [%d]:\n", i);
9645 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9646 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9647 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9648 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9649 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9650 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9651 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9652 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9653
9654 seq_printf(m, "Plane [%d]:\n", i);
9655 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9656 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9657 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9658 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9659 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9660 }
4b71a570 9661 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9662 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9663 if (INTEL_INFO(dev)->gen >= 4) {
9664 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9665 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9666 }
9667
9668 seq_printf(m, "Cursor [%d]:\n", i);
9669 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9670 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9671 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9672 }
9673}
9674#endif
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