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drm/i915: shovel compute clock into crtc->config.dpll on ilk
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a4fc5ed6
KP		 104static bool
105intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
5eb08b69 108static bool
f2b115e6 109intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 110 int target, int refclk, intel_clock_t *match_clock,
111 intel_clock_t *best_clock);
a4fc5ed6 112
a0c4da24
JB		 113static bool
114intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
115 int target, int refclk, intel_clock_t *match_clock,
116 intel_clock_t *best_clock);
117
021357ac
CW		 118static inline u32 /* units of 100MHz */
119intel_fdi_link_freq(struct drm_device *dev)
120{
8b99e68c
CW		 121 if (IS_GEN5(dev)) {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
124 } else
125 return 27;
021357ac
CW		 126}
127
e4b36699 128static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 129 .dot = { .min = 25000, .max = 350000 },
130 .vco = { .min = 930000, .max = 1400000 },
131 .n = { .min = 3, .max = 16 },
132 .m = { .min = 96, .max = 140 },
133 .m1 = { .min = 18, .max = 26 },
134 .m2 = { .min = 6, .max = 16 },
135 .p = { .min = 4, .max = 128 },
136 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 137 .p2 = { .dot_limit = 165000,
138 .p2_slow = 4, .p2_fast = 2 },
d4906093 139 .find_pll = intel_find_best_PLL,
e4b36699
KP		 140};
141
142static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 143 .dot = { .min = 25000, .max = 350000 },
144 .vco = { .min = 930000, .max = 1400000 },
145 .n = { .min = 3, .max = 16 },
146 .m = { .min = 96, .max = 140 },
147 .m1 = { .min = 18, .max = 26 },
148 .m2 = { .min = 6, .max = 16 },
149 .p = { .min = 4, .max = 128 },
150 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 151 .p2 = { .dot_limit = 165000,
152 .p2_slow = 14, .p2_fast = 7 },
d4906093 153 .find_pll = intel_find_best_PLL,
e4b36699 154};
273e27ca 155
e4b36699 156static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 157 .dot = { .min = 20000, .max = 400000 },
158 .vco = { .min = 1400000, .max = 2800000 },
159 .n = { .min = 1, .max = 6 },
160 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 161 .m1 = { .min = 8, .max = 18 },
162 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 163 .p = { .min = 5, .max = 80 },
164 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 165 .p2 = { .dot_limit = 200000,
166 .p2_slow = 10, .p2_fast = 5 },
d4906093 167 .find_pll = intel_find_best_PLL,
e4b36699
KP		 168};
169
170static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 171 .dot = { .min = 20000, .max = 400000 },
172 .vco = { .min = 1400000, .max = 2800000 },
173 .n = { .min = 1, .max = 6 },
174 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 175 .m1 = { .min = 8, .max = 18 },
176 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 177 .p = { .min = 7, .max = 98 },
178 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 179 .p2 = { .dot_limit = 112000,
180 .p2_slow = 14, .p2_fast = 7 },
d4906093 181 .find_pll = intel_find_best_PLL,
e4b36699
KP		 182};
183
273e27ca 184
e4b36699 185static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 186 .dot = { .min = 25000, .max = 270000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 10, .max = 30 },
193 .p1 = { .min = 1, .max = 3},
194 .p2 = { .dot_limit = 270000,
195 .p2_slow = 10,
196 .p2_fast = 10
044c7c41 197 },
d4906093 198 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 199};
200
201static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 202 .dot = { .min = 22000, .max = 400000 },
203 .vco = { .min = 1750000, .max = 3500000},
204 .n = { .min = 1, .max = 4 },
205 .m = { .min = 104, .max = 138 },
206 .m1 = { .min = 16, .max = 23 },
207 .m2 = { .min = 5, .max = 11 },
208 .p = { .min = 5, .max = 80 },
209 .p1 = { .min = 1, .max = 8},
210 .p2 = { .dot_limit = 165000,
211 .p2_slow = 10, .p2_fast = 5 },
d4906093 212 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 213};
214
215static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 216 .dot = { .min = 20000, .max = 115000 },
217 .vco = { .min = 1750000, .max = 3500000 },
218 .n = { .min = 1, .max = 3 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 28, .max = 112 },
223 .p1 = { .min = 2, .max = 8 },
224 .p2 = { .dot_limit = 0,
225 .p2_slow = 14, .p2_fast = 14
044c7c41 226 },
d4906093 227 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 228};
229
230static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 231 .dot = { .min = 80000, .max = 224000 },
232 .vco = { .min = 1750000, .max = 3500000 },
233 .n = { .min = 1, .max = 3 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 17, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 14, .max = 42 },
238 .p1 = { .min = 2, .max = 6 },
239 .p2 = { .dot_limit = 0,
240 .p2_slow = 7, .p2_fast = 7
044c7c41 241 },
d4906093 242 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 243};
244
245static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 246 .dot = { .min = 161670, .max = 227000 },
247 .vco = { .min = 1750000, .max = 3500000},
248 .n = { .min = 1, .max = 2 },
249 .m = { .min = 97, .max = 108 },
250 .m1 = { .min = 0x10, .max = 0x12 },
251 .m2 = { .min = 0x05, .max = 0x06 },
252 .p = { .min = 10, .max = 20 },
253 .p1 = { .min = 1, .max = 2},
254 .p2 = { .dot_limit = 0,
273e27ca 255 .p2_slow = 10, .p2_fast = 10 },
0206e353 256 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000},
261 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 262 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 263 .n = { .min = 3, .max = 6 },
264 .m = { .min = 2, .max = 256 },
273e27ca 265 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 266 .m1 = { .min = 0, .max = 0 },
267 .m2 = { .min = 0, .max = 254 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 270 .p2 = { .dot_limit = 200000,
271 .p2_slow = 10, .p2_fast = 5 },
6115707b 272 .find_pll = intel_find_best_PLL,
e4b36699
KP		 273};
274
f2b115e6 275static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1700000, .max = 3500000 },
278 .n = { .min = 3, .max = 6 },
279 .m = { .min = 2, .max = 256 },
280 .m1 = { .min = 0, .max = 0 },
281 .m2 = { .min = 0, .max = 254 },
282 .p = { .min = 7, .max = 112 },
283 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 284 .p2 = { .dot_limit = 112000,
285 .p2_slow = 14, .p2_fast = 14 },
6115707b 286 .find_pll = intel_find_best_PLL,
e4b36699
KP		 287};
288
273e27ca
EA		 289/* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
b91ad0ec 294static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
4547668a 305 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 306};
307
b91ad0ec 308static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 309 .dot = { .min = 25000, .max = 350000 },
310 .vco = { .min = 1760000, .max = 3510000 },
311 .n = { .min = 1, .max = 3 },
312 .m = { .min = 79, .max = 118 },
313 .m1 = { .min = 12, .max = 22 },
314 .m2 = { .min = 5, .max = 9 },
315 .p = { .min = 28, .max = 112 },
316 .p1 = { .min = 2, .max = 8 },
317 .p2 = { .dot_limit = 225000,
318 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 319 .find_pll = intel_g4x_find_best_PLL,
320};
321
322static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 323 .dot = { .min = 25000, .max = 350000 },
324 .vco = { .min = 1760000, .max = 3510000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 79, .max = 127 },
327 .m1 = { .min = 12, .max = 22 },
328 .m2 = { .min = 5, .max = 9 },
329 .p = { .min = 14, .max = 56 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 225000,
332 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 333 .find_pll = intel_g4x_find_best_PLL,
334};
335
273e27ca 336/* LVDS 100mhz refclk limits. */
b91ad0ec 337static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 2 },
341 .m = { .min = 79, .max = 126 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 28, .max = 112 },
0206e353 345 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 348 .find_pll = intel_g4x_find_best_PLL,
349};
350
351static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 3 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 14, .max = 42 },
0206e353 359 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 362 .find_pll = intel_g4x_find_best_PLL,
363};
364
365static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 366 .dot = { .min = 25000, .max = 350000 },
367 .vco = { .min = 1760000, .max = 3510000},
368 .n = { .min = 1, .max = 2 },
369 .m = { .min = 81, .max = 90 },
370 .m1 = { .min = 12, .max = 22 },
371 .m2 = { .min = 5, .max = 9 },
372 .p = { .min = 10, .max = 20 },
373 .p1 = { .min = 1, .max = 2},
374 .p2 = { .dot_limit = 0,
273e27ca 375 .p2_slow = 10, .p2_fast = 10 },
0206e353 376 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 377};
378
a0c4da24
JB		 379static const intel_limit_t intel_limits_vlv_dac = {
380 .dot = { .min = 25000, .max = 270000 },
381 .vco = { .min = 4000000, .max = 6000000 },
382 .n = { .min = 1, .max = 7 },
383 .m = { .min = 22, .max = 450 }, /* guess */
384 .m1 = { .min = 2, .max = 3 },
385 .m2 = { .min = 11, .max = 156 },
386 .p = { .min = 10, .max = 30 },
75e53986 387 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 388 .p2 = { .dot_limit = 270000,
389 .p2_slow = 2, .p2_fast = 20 },
390 .find_pll = intel_vlv_find_best_pll,
391};
392
393static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 394 .dot = { .min = 25000, .max = 270000 },
395 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 396 .n = { .min = 1, .max = 7 },
397 .m = { .min = 60, .max = 300 }, /* guess */
398 .m1 = { .min = 2, .max = 3 },
399 .m2 = { .min = 11, .max = 156 },
400 .p = { .min = 10, .max = 30 },
401 .p1 = { .min = 2, .max = 3 },
402 .p2 = { .dot_limit = 270000,
403 .p2_slow = 2, .p2_fast = 20 },
404 .find_pll = intel_vlv_find_best_pll,
405};
406
407static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 408 .dot = { .min = 25000, .max = 270000 },
409 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 410 .n = { .min = 1, .max = 7 },
74a4dd2e 411 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 412 .m1 = { .min = 2, .max = 3 },
413 .m2 = { .min = 11, .max = 156 },
414 .p = { .min = 10, .max = 30 },
75e53986 415 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 416 .p2 = { .dot_limit = 270000,
417 .p2_slow = 2, .p2_fast = 20 },
418 .find_pll = intel_vlv_find_best_pll,
419};
420
57f350b6
JB		 421u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
422{
09153000 423 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 424
57f350b6
JB		 425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
09153000 427 return 0;
57f350b6
JB		 428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
09153000 435 return 0;
57f350b6 436 }
57f350b6 437
09153000 438 return I915_READ(DPIO_DATA);
57f350b6
JB		 439}
440
e2fa6fba 441void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 442{
09153000 443 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 444
a0c4da24
JB		 445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO idle wait timed out\n");
09153000 447 return;
a0c4da24
JB		 448 }
449
450 I915_WRITE(DPIO_DATA, val);
451 I915_WRITE(DPIO_REG, reg);
452 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
453 DPIO_BYTE);
454 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
455 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 456}
457
1b894b59
CW		 458static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
459 int refclk)
2c07245f 460{
b91ad0ec 461 struct drm_device *dev = crtc->dev;
2c07245f 462 const intel_limit_t *limit;
b91ad0ec
ZW		 463
464 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 465 if (intel_is_dual_link_lvds(dev)) {
1b894b59 466 if (refclk == 100000)
b91ad0ec
ZW		 467 limit = &intel_limits_ironlake_dual_lvds_100m;
468 else
469 limit = &intel_limits_ironlake_dual_lvds;
470 } else {
1b894b59 471 if (refclk == 100000)
b91ad0ec
ZW		 472 limit = &intel_limits_ironlake_single_lvds_100m;
473 else
474 limit = &intel_limits_ironlake_single_lvds;
475 }
476 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 477 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 478 limit = &intel_limits_ironlake_display_port;
2c07245f 479 else
b91ad0ec 480 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 481
482 return limit;
483}
484
044c7c41
ML		 485static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
486{
487 struct drm_device *dev = crtc->dev;
044c7c41
ML		 488 const intel_limit_t *limit;
489
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 491 if (intel_is_dual_link_lvds(dev))
e4b36699 492 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 493 else
e4b36699 494 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 495 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
496 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 497 limit = &intel_limits_g4x_hdmi;
044c7c41 498 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 499 limit = &intel_limits_g4x_sdvo;
0206e353 500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 501 limit = &intel_limits_g4x_display_port;
044c7c41 502 } else /* The option is for other outputs */
e4b36699 503 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 504
505 return limit;
506}
507
1b894b59 508static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 509{
510 struct drm_device *dev = crtc->dev;
511 const intel_limit_t *limit;
512
bad720ff 513 if (HAS_PCH_SPLIT(dev))
1b894b59 514 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 515 else if (IS_G4X(dev)) {
044c7c41 516 limit = intel_g4x_limit(crtc);
f2b115e6 517 } else if (IS_PINEVIEW(dev)) {
2177832f 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 519 limit = &intel_limits_pineview_lvds;
2177832f 520 else
f2b115e6 521 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 522 } else if (IS_VALLEYVIEW(dev)) {
523 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
524 limit = &intel_limits_vlv_dac;
525 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
526 limit = &intel_limits_vlv_hdmi;
527 else
528 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 529 } else if (!IS_GEN2(dev)) {
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
531 limit = &intel_limits_i9xx_lvds;
532 else
533 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 534 } else {
535 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 536 limit = &intel_limits_i8xx_lvds;
79e53945 537 else
e4b36699 538 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 539 }
540 return limit;
541}
542
f2b115e6
AJ		 543/* m1 is reserved as 0 in Pineview, n is a ring counter */
544static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 545{
2177832f
SL		 546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
548 clock->vco = refclk * clock->m / clock->n;
549 clock->dot = clock->vco / clock->p;
550}
551
7429e9d4
DV		 552static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
553{
554 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
555}
556
2177832f
SL		 557static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
558{
f2b115e6
AJ		 559 if (IS_PINEVIEW(dev)) {
560 pineview_clock(refclk, clock);
2177832f
SL		 561 return;
562 }
7429e9d4 563 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 564 clock->p = clock->p1 * clock->p2;
565 clock->vco = refclk * clock->m / (clock->n + 2);
566 clock->dot = clock->vco / clock->p;
567}
568
79e53945
JB		 569/**
570 * Returns whether any output on the specified pipe is of the specified type
571 */
4ef69c7a 572bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 573{
4ef69c7a 574 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 575 struct intel_encoder *encoder;
576
6c2b7c12
DV		 577 for_each_encoder_on_crtc(dev, crtc, encoder)
578 if (encoder->type == type)
4ef69c7a
CW		 579 return true;
580
581 return false;
79e53945
JB		 582}
583
7c04d1d9 584#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 585/**
586 * Returns whether the given set of divisors are valid for a given refclk with
587 * the given connectors.
588 */
589
1b894b59
CW		 590static bool intel_PLL_is_valid(struct drm_device *dev,
591 const intel_limit_t *limit,
592 const intel_clock_t *clock)
79e53945 593{
79e53945 594 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 595 INTELPllInvalid("p1 out of range\n");
79e53945 596 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 597 INTELPllInvalid("p out of range\n");
79e53945 598 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 599 INTELPllInvalid("m2 out of range\n");
79e53945 600 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 601 INTELPllInvalid("m1 out of range\n");
f2b115e6 602 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 603 INTELPllInvalid("m1 <= m2\n");
79e53945 604 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 605 INTELPllInvalid("m out of range\n");
79e53945 606 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 607 INTELPllInvalid("n out of range\n");
79e53945 608 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 609 INTELPllInvalid("vco out of range\n");
79e53945
JB		 610 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
611 * connector, etc., rather than just a single range.
612 */
613 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 614 INTELPllInvalid("dot out of range\n");
79e53945
JB		 615
616 return true;
617}
618
d4906093
ML		 619static bool
620intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 621 int target, int refclk, intel_clock_t *match_clock,
622 intel_clock_t *best_clock)
d4906093 623
79e53945
JB		 624{
625 struct drm_device *dev = crtc->dev;
79e53945 626 intel_clock_t clock;
79e53945
JB		 627 int err = target;
628
a210b028 629 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 630 /*
a210b028
DV		 631 * For LVDS just rely on its current settings for dual-channel.
632 * We haven't figured out how to reliably set up different
633 * single/dual channel state, if we even can.
79e53945 634 */
1974cad0 635 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 636 clock.p2 = limit->p2.p2_fast;
637 else
638 clock.p2 = limit->p2.p2_slow;
639 } else {
640 if (target < limit->p2.dot_limit)
641 clock.p2 = limit->p2.p2_slow;
642 else
643 clock.p2 = limit->p2.p2_fast;
644 }
645
0206e353 646 memset(best_clock, 0, sizeof(*best_clock));
79e53945 647
42158660
ZY		 648 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
649 clock.m1++) {
650 for (clock.m2 = limit->m2.min;
651 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 652 /* m1 is always 0 in Pineview */
653 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 654 break;
655 for (clock.n = limit->n.min;
656 clock.n <= limit->n.max; clock.n++) {
657 for (clock.p1 = limit->p1.min;
658 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 659 int this_err;
660
2177832f 661 intel_clock(dev, refclk, &clock);
1b894b59
CW		 662 if (!intel_PLL_is_valid(dev, limit,
663 &clock))
79e53945 664 continue;
cec2f356
SP		 665 if (match_clock &&
666 clock.p != match_clock->p)
667 continue;
79e53945
JB		 668
669 this_err = abs(clock.dot - target);
670 if (this_err < err) {
671 *best_clock = clock;
672 err = this_err;
673 }
674 }
675 }
676 }
677 }
678
679 return (err != target);
680}
681
d4906093
ML		 682static bool
683intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
d4906093
ML		 686{
687 struct drm_device *dev = crtc->dev;
d4906093
ML		 688 intel_clock_t clock;
689 int max_n;
690 bool found;
6ba770dc
AJ		 691 /* approximately equals target * 0.00585 */
692 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 693 found = false;
694
695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 696 int lvds_reg;
697
c619eed4 698 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 699 lvds_reg = PCH_LVDS;
700 else
701 lvds_reg = LVDS;
1974cad0 702 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 703 clock.p2 = limit->p2.p2_fast;
704 else
705 clock.p2 = limit->p2.p2_slow;
706 } else {
707 if (target < limit->p2.dot_limit)
708 clock.p2 = limit->p2.p2_slow;
709 else
710 clock.p2 = limit->p2.p2_fast;
711 }
712
713 memset(best_clock, 0, sizeof(*best_clock));
714 max_n = limit->n.max;
f77f13e2 715 /* based on hardware requirement, prefer smaller n to precision */
d4906093 716 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 717 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 718 for (clock.m1 = limit->m1.max;
719 clock.m1 >= limit->m1.min; clock.m1--) {
720 for (clock.m2 = limit->m2.max;
721 clock.m2 >= limit->m2.min; clock.m2--) {
722 for (clock.p1 = limit->p1.max;
723 clock.p1 >= limit->p1.min; clock.p1--) {
724 int this_err;
725
2177832f 726 intel_clock(dev, refclk, &clock);
1b894b59
CW		 727 if (!intel_PLL_is_valid(dev, limit,
728 &clock))
d4906093 729 continue;
cec2f356
SP		 730 if (match_clock &&
731 clock.p != match_clock->p)
732 continue;
1b894b59
CW		 733
734 this_err = abs(clock.dot - target);
d4906093
ML		 735 if (this_err < err_most) {
736 *best_clock = clock;
737 err_most = this_err;
738 max_n = clock.n;
739 found = true;
740 }
741 }
742 }
743 }
744 }
2c07245f
ZW		 745 return found;
746}
747
5eb08b69 748static bool
f2b115e6 749intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
5eb08b69
ZW		 752{
753 struct drm_device *dev = crtc->dev;
754 intel_clock_t clock;
4547668a 755
5eb08b69
ZW		 756 if (target < 200000) {
757 clock.n = 1;
758 clock.p1 = 2;
759 clock.p2 = 10;
760 clock.m1 = 12;
761 clock.m2 = 9;
762 } else {
763 clock.n = 2;
764 clock.p1 = 1;
765 clock.p2 = 10;
766 clock.m1 = 14;
767 clock.m2 = 8;
768 }
769 intel_clock(dev, refclk, &clock);
770 memcpy(best_clock, &clock, sizeof(intel_clock_t));
771 return true;
772}
773
a4fc5ed6
KP		 774/* DisplayPort has only two frequencies, 162MHz and 270MHz */
775static bool
776intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
a4fc5ed6 779{
5eddb70b
CW		 780 intel_clock_t clock;
781 if (target < 200000) {
782 clock.p1 = 2;
783 clock.p2 = 10;
784 clock.n = 2;
785 clock.m1 = 23;
786 clock.m2 = 8;
787 } else {
788 clock.p1 = 1;
789 clock.p2 = 10;
790 clock.n = 1;
791 clock.m1 = 14;
792 clock.m2 = 2;
793 }
794 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
795 clock.p = (clock.p1 * clock.p2);
796 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
797 clock.vco = 0;
798 memcpy(best_clock, &clock, sizeof(intel_clock_t));
799 return true;
a4fc5ed6 800}
a0c4da24
JB		 801static bool
802intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
803 int target, int refclk, intel_clock_t *match_clock,
804 intel_clock_t *best_clock)
805{
806 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
807 u32 m, n, fastclk;
808 u32 updrate, minupdate, fracbits, p;
809 unsigned long bestppm, ppm, absppm;
810 int dotclk, flag;
811
af447bd3 812 flag = 0;
a0c4da24
JB		 813 dotclk = target * 1000;
814 bestppm = 1000000;
815 ppm = absppm = 0;
816 fastclk = dotclk / (2*100);
817 updrate = 0;
818 minupdate = 19200;
819 fracbits = 1;
820 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
821 bestm1 = bestm2 = bestp1 = bestp2 = 0;
822
823 /* based on hardware requirement, prefer smaller n to precision */
824 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
825 updrate = refclk / n;
826 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
827 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
828 if (p2 > 10)
829 p2 = p2 - 1;
830 p = p1 * p2;
831 /* based on hardware requirement, prefer bigger m1,m2 values */
832 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
833 m2 = (((2*(fastclk * p * n / m1 )) +
834 refclk) / (2*refclk));
835 m = m1 * m2;
836 vco = updrate * m;
837 if (vco >= limit->vco.min && vco < limit->vco.max) {
838 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
839 absppm = (ppm > 0) ? ppm : (-ppm);
840 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
841 bestppm = 0;
842 flag = 1;
843 }
844 if (absppm < bestppm - 10) {
845 bestppm = absppm;
846 flag = 1;
847 }
848 if (flag) {
849 bestn = n;
850 bestm1 = m1;
851 bestm2 = m2;
852 bestp1 = p1;
853 bestp2 = p2;
854 flag = 0;
855 }
856 }
857 }
858 }
859 }
860 }
861 best_clock->n = bestn;
862 best_clock->m1 = bestm1;
863 best_clock->m2 = bestm2;
864 best_clock->p1 = bestp1;
865 best_clock->p2 = bestp2;
866
867 return true;
868}
a4fc5ed6 869
a5c961d1
PZ		 870enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
871 enum pipe pipe)
872{
873 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
875
3b117c8f 876 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 877}
878
a928d536
PZ		 879static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
880{
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 u32 frame, frame_reg = PIPEFRAME(pipe);
883
884 frame = I915_READ(frame_reg);
885
886 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
887 DRM_DEBUG_KMS("vblank wait timed out\n");
888}
889
9d0498a2
JB		 890/**
891 * intel_wait_for_vblank - wait for vblank on a given pipe
892 * @dev: drm device
893 * @pipe: pipe to wait for
894 *
895 * Wait for vblank to occur on a given pipe. Needed for various bits of
896 * mode setting code.
897 */
898void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 899{
9d0498a2 900 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 901 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 902
a928d536
PZ		 903 if (INTEL_INFO(dev)->gen >= 5) {
904 ironlake_wait_for_vblank(dev, pipe);
905 return;
906 }
907
300387c0
CW		 908 /* Clear existing vblank status. Note this will clear any other
909 * sticky status fields as well.
910 *
911 * This races with i915_driver_irq_handler() with the result
912 * that either function could miss a vblank event. Here it is not
913 * fatal, as we will either wait upon the next vblank interrupt or
914 * timeout. Generally speaking intel_wait_for_vblank() is only
915 * called during modeset at which time the GPU should be idle and
916 * should *not* be performing page flips and thus not waiting on
917 * vblanks...
918 * Currently, the result of us stealing a vblank from the irq
919 * handler is that a single frame will be skipped during swapbuffers.
920 */
921 I915_WRITE(pipestat_reg,
922 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
923
9d0498a2 924 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 925 if (wait_for(I915_READ(pipestat_reg) &
926 PIPE_VBLANK_INTERRUPT_STATUS,
927 50))
9d0498a2
JB		 928 DRM_DEBUG_KMS("vblank wait timed out\n");
929}
930
ab7ad7f6
KP		 931/*
932 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 933 * @dev: drm device
934 * @pipe: pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
ab7ad7f6
KP		 940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
58e10eb9 946 *
9d0498a2 947 */
58e10eb9 948void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 949{
950 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 951 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
952 pipe);
ab7ad7f6
KP		 953
954 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 955 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 956
957 /* Wait for the Pipe State to go off */
58e10eb9
CW		 958 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
959 100))
284637d9 960 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 961 } else {
837ba00f 962 u32 last_line, line_mask;
58e10eb9 963 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 964 unsigned long timeout = jiffies + msecs_to_jiffies(100);
965
837ba00f
PZ		 966 if (IS_GEN2(dev))
967 line_mask = DSL_LINEMASK_GEN2;
968 else
969 line_mask = DSL_LINEMASK_GEN3;
970
ab7ad7f6
KP		 971 /* Wait for the display line to settle */
972 do {
837ba00f 973 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 974 mdelay(5);
837ba00f 975 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 976 time_after(timeout, jiffies));
977 if (time_after(jiffies, timeout))
284637d9 978 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 979 }
79e53945
JB		 980}
981
b0ea7d37
DL		 982/*
983 * ibx_digital_port_connected - is the specified port connected?
984 * @dev_priv: i915 private structure
985 * @port: the port to test
986 *
987 * Returns true if @port is connected, false otherwise.
988 */
989bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
990 struct intel_digital_port *port)
991{
992 u32 bit;
993
c36346e3
DL		 994 if (HAS_PCH_IBX(dev_priv->dev)) {
995 switch(port->port) {
996 case PORT_B:
997 bit = SDE_PORTB_HOTPLUG;
998 break;
999 case PORT_C:
1000 bit = SDE_PORTC_HOTPLUG;
1001 break;
1002 case PORT_D:
1003 bit = SDE_PORTD_HOTPLUG;
1004 break;
1005 default:
1006 return true;
1007 }
1008 } else {
1009 switch(port->port) {
1010 case PORT_B:
1011 bit = SDE_PORTB_HOTPLUG_CPT;
1012 break;
1013 case PORT_C:
1014 bit = SDE_PORTC_HOTPLUG_CPT;
1015 break;
1016 case PORT_D:
1017 bit = SDE_PORTD_HOTPLUG_CPT;
1018 break;
1019 default:
1020 return true;
1021 }
b0ea7d37
DL		 1022 }
1023
1024 return I915_READ(SDEISR) & bit;
1025}
1026
b24e7179
JB		 1027static const char *state_string(bool enabled)
1028{
1029 return enabled ? "on" : "off";
1030}
1031
1032/* Only for pre-ILK configs */
1033static void assert_pll(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, bool state)
1035{
1036 int reg;
1037 u32 val;
1038 bool cur_state;
1039
1040 reg = DPLL(pipe);
1041 val = I915_READ(reg);
1042 cur_state = !!(val & DPLL_VCO_ENABLE);
1043 WARN(cur_state != state,
1044 "PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046}
1047#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1048#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1049
040484af
JB		 1050/* For ILK+ */
1051static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1052 struct intel_pch_pll *pll,
1053 struct intel_crtc *crtc,
1054 bool state)
040484af 1055{
040484af
JB		 1056 u32 val;
1057 bool cur_state;
1058
9d82aa17
ED		 1059 if (HAS_PCH_LPT(dev_priv->dev)) {
1060 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1061 return;
1062 }
1063
92b27b08
CW		 1064 if (WARN (!pll,
1065 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1066 return;
ee7b9f93 1067
92b27b08
CW		 1068 val = I915_READ(pll->pll_reg);
1069 cur_state = !!(val & DPLL_VCO_ENABLE);
1070 WARN(cur_state != state,
1071 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1072 pll->pll_reg, state_string(state), state_string(cur_state), val);
1073
1074 /* Make sure the selected PLL is correctly attached to the transcoder */
1075 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1076 u32 pch_dpll;
1077
1078 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1079 cur_state = pll->pll_reg == _PCH_DPLL_B;
1080 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 1081 "PLL[%d] not attached to this transcoder %c: %08x\n",
1082 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 1083 cur_state = !!(val >> (4*crtc->pipe + 3));
1084 WARN(cur_state != state,
4bb6f1f3 1085 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 1086 pll->pll_reg == _PCH_DPLL_B,
1087 state_string(state),
4bb6f1f3 1088 pipe_name(crtc->pipe),
92b27b08
CW		 1089 val);
1090 }
d3ccbe86 1091 }
040484af 1092}
92b27b08
CW		 1093#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1094#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1095
1096static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1097 enum pipe pipe, bool state)
1098{
1099 int reg;
1100 u32 val;
1101 bool cur_state;
ad80a810
PZ		 1102 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1103 pipe);
040484af 1104
affa9354
PZ		 1105 if (HAS_DDI(dev_priv->dev)) {
1106 /* DDI does not have a specific FDI_TX register */
ad80a810 1107 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1108 val = I915_READ(reg);
ad80a810 1109 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1110 } else {
1111 reg = FDI_TX_CTL(pipe);
1112 val = I915_READ(reg);
1113 cur_state = !!(val & FDI_TX_ENABLE);
1114 }
040484af
JB		 1115 WARN(cur_state != state,
1116 "FDI TX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118}
1119#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1120#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1121
1122static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
d63fa0dc
PZ		 1129 reg = FDI_RX_CTL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1132 WARN(cur_state != state,
1133 "FDI RX state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
1136#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1137#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1138
1139static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1140 enum pipe pipe)
1141{
1142 int reg;
1143 u32 val;
1144
1145 /* ILK FDI PLL is always enabled */
1146 if (dev_priv->info->gen == 5)
1147 return;
1148
bf507ef7 1149 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1150 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1151 return;
1152
040484af
JB		 1153 reg = FDI_TX_CTL(pipe);
1154 val = I915_READ(reg);
1155 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1156}
1157
1158static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 reg = FDI_RX_CTL(pipe);
1165 val = I915_READ(reg);
1166 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1167}
1168
ea0760cf
JB		 1169static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int pp_reg, lvds_reg;
1173 u32 val;
1174 enum pipe panel_pipe = PIPE_A;
0de3b485 1175 bool locked = true;
ea0760cf
JB		 1176
1177 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1178 pp_reg = PCH_PP_CONTROL;
1179 lvds_reg = PCH_LVDS;
1180 } else {
1181 pp_reg = PP_CONTROL;
1182 lvds_reg = LVDS;
1183 }
1184
1185 val = I915_READ(pp_reg);
1186 if (!(val & PANEL_POWER_ON) ||
1187 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1188 locked = false;
1189
1190 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1191 panel_pipe = PIPE_B;
1192
1193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1195 pipe_name(pipe));
ea0760cf
JB		 1196}
1197
b840d907
JB		 1198void assert_pipe(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
b24e7179
JB		 1200{
1201 int reg;
1202 u32 val;
63d7bbe9 1203 bool cur_state;
702e7a56
PZ		 1204 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205 pipe);
b24e7179 1206
8e636784
DV		 1207 /* if we need the pipe A quirk it must be always on */
1208 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1209 state = true;
1210
15d199ea
PZ		 1211 if (!intel_using_power_well(dev_priv->dev) &&
1212 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1213 cur_state = false;
1214 } else {
1215 reg = PIPECONF(cpu_transcoder);
1216 val = I915_READ(reg);
1217 cur_state = !!(val & PIPECONF_ENABLE);
1218 }
1219
63d7bbe9
JB		 1220 WARN(cur_state != state,
1221 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1222 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1223}
1224
931872fc
CW		 1225static void assert_plane(struct drm_i915_private *dev_priv,
1226 enum plane plane, bool state)
b24e7179
JB		 1227{
1228 int reg;
1229 u32 val;
931872fc 1230 bool cur_state;
b24e7179
JB		 1231
1232 reg = DSPCNTR(plane);
1233 val = I915_READ(reg);
931872fc
CW		 1234 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1235 WARN(cur_state != state,
1236 "plane %c assertion failure (expected %s, current %s)\n",
1237 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1238}
1239
931872fc
CW		 1240#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1241#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1242
b24e7179
JB		 1243static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1244 enum pipe pipe)
1245{
1246 int reg, i;
1247 u32 val;
1248 int cur_pipe;
1249
19ec1358 1250 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1251 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1252 reg = DSPCNTR(pipe);
1253 val = I915_READ(reg);
1254 WARN((val & DISPLAY_PLANE_ENABLE),
1255 "plane %c assertion failure, should be disabled but not\n",
1256 plane_name(pipe));
19ec1358 1257 return;
28c05794 1258 }
19ec1358 1259
b24e7179
JB		 1260 /* Need to check both planes against the pipe */
1261 for (i = 0; i < 2; i++) {
1262 reg = DSPCNTR(i);
1263 val = I915_READ(reg);
1264 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265 DISPPLANE_SEL_PIPE_SHIFT;
1266 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1267 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1269 }
1270}
1271
19332d7a
JB		 1272static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1273 enum pipe pipe)
1274{
1275 int reg, i;
1276 u32 val;
1277
1278 if (!IS_VALLEYVIEW(dev_priv->dev))
1279 return;
1280
1281 /* Need to check both planes against the pipe */
1282 for (i = 0; i < dev_priv->num_plane; i++) {
1283 reg = SPCNTR(pipe, i);
1284 val = I915_READ(reg);
1285 WARN((val & SP_ENABLE),
06da8da2
VS		 1286 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1287 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
dc0fa718 1343 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1348 return false;
1349 } else {
dc0fa718 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
dc0fa718 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
58c6eaa2
DV		 1458 assert_pipe_disabled(dev_priv, pipe);
1459
63d7bbe9 1460 /* No really, not for ILK+ */
a0c4da24 1461 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1462
1463 /* PLL is protected by panel, make sure we can write it */
1464 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1465 assert_panel_unlocked(dev_priv, pipe);
1466
1467 reg = DPLL(pipe);
1468 val = I915_READ(reg);
1469 val |= DPLL_VCO_ENABLE;
1470
1471 /* We do this three times for luck */
1472 I915_WRITE(reg, val);
1473 POSTING_READ(reg);
1474 udelay(150); /* wait for warmup */
1475 I915_WRITE(reg, val);
1476 POSTING_READ(reg);
1477 udelay(150); /* wait for warmup */
1478 I915_WRITE(reg, val);
1479 POSTING_READ(reg);
1480 udelay(150); /* wait for warmup */
1481}
1482
1483/**
1484 * intel_disable_pll - disable a PLL
1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to disable
1487 *
1488 * Disable the PLL for @pipe, making sure the pipe is off first.
1489 *
1490 * Note! This is for pre-ILK only.
1491 */
1492static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1493{
1494 int reg;
1495 u32 val;
1496
1497 /* Don't disable pipe A or pipe A PLLs if needed */
1498 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1499 return;
1500
1501 /* Make sure the pipe isn't still relying on us */
1502 assert_pipe_disabled(dev_priv, pipe);
1503
1504 reg = DPLL(pipe);
1505 val = I915_READ(reg);
1506 val &= ~DPLL_VCO_ENABLE;
1507 I915_WRITE(reg, val);
1508 POSTING_READ(reg);
1509}
1510
a416edef
ED		 1511/* SBI access */
1512static void
988d6ee8
PZ		 1513intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1514 enum intel_sbi_destination destination)
a416edef 1515{
988d6ee8 1516 u32 tmp;
a416edef 1517
09153000 1518 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1519
39fb50f6 1520 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1521 100)) {
1522 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1523 return;
a416edef
ED		 1524 }
1525
988d6ee8
PZ		 1526 I915_WRITE(SBI_ADDR, (reg << 16));
1527 I915_WRITE(SBI_DATA, value);
1528
1529 if (destination == SBI_ICLK)
1530 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1531 else
1532 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1533 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1534
39fb50f6 1535 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1536 100)) {
1537 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1538 return;
a416edef 1539 }
a416edef
ED		 1540}
1541
1542static u32
988d6ee8
PZ		 1543intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1544 enum intel_sbi_destination destination)
a416edef 1545{
39fb50f6 1546 u32 value = 0;
09153000 1547 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1548
39fb50f6 1549 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1550 100)) {
1551 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1552 return 0;
a416edef
ED		 1553 }
1554
988d6ee8
PZ		 1555 I915_WRITE(SBI_ADDR, (reg << 16));
1556
1557 if (destination == SBI_ICLK)
1558 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1559 else
1560 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1561 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1562
39fb50f6 1563 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1564 100)) {
1565 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1566 return 0;
a416edef
ED		 1567 }
1568
09153000 1569 return I915_READ(SBI_DATA);
a416edef
ED		 1570}
1571
89b667f8
JB		 1572void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1573{
1574 u32 port_mask;
1575
1576 if (!port)
1577 port_mask = DPLL_PORTB_READY_MASK;
1578 else
1579 port_mask = DPLL_PORTC_READY_MASK;
1580
1581 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1582 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1583 'B' + port, I915_READ(DPLL(0)));
1584}
1585
92f2584a 1586/**
b6b4e185 1587 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1588 * @dev_priv: i915 private structure
1589 * @pipe: pipe PLL to enable
1590 *
1591 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1592 * drives the transcoder clock.
1593 */
b6b4e185 1594static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1595{
ee7b9f93 1596 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1597 struct intel_pch_pll *pll;
92f2584a
JB		 1598 int reg;
1599 u32 val;
1600
48da64a8 1601 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1602 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1603 pll = intel_crtc->pch_pll;
1604 if (pll == NULL)
1605 return;
1606
1607 if (WARN_ON(pll->refcount == 0))
1608 return;
ee7b9f93
JB		 1609
1610 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1611 pll->pll_reg, pll->active, pll->on,
1612 intel_crtc->base.base.id);
92f2584a
JB		 1613
1614 /* PCH refclock must be enabled first */
1615 assert_pch_refclk_enabled(dev_priv);
1616
ee7b9f93 1617 if (pll->active++ && pll->on) {
92b27b08 1618 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1619 return;
1620 }
1621
1622 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1623
1624 reg = pll->pll_reg;
92f2584a
JB		 1625 val = I915_READ(reg);
1626 val |= DPLL_VCO_ENABLE;
1627 I915_WRITE(reg, val);
1628 POSTING_READ(reg);
1629 udelay(200);
ee7b9f93
JB		 1630
1631 pll->on = true;
92f2584a
JB		 1632}
1633
ee7b9f93 1634static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1635{
ee7b9f93
JB		 1636 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1637 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1638 int reg;
ee7b9f93 1639 u32 val;
4c609cb8 1640
92f2584a
JB		 1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1643 if (pll == NULL)
1644 return;
92f2584a 1645
48da64a8
CW		 1646 if (WARN_ON(pll->refcount == 0))
1647 return;
7a419866 1648
ee7b9f93
JB		 1649 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1650 pll->pll_reg, pll->active, pll->on,
1651 intel_crtc->base.base.id);
7a419866 1652
48da64a8 1653 if (WARN_ON(pll->active == 0)) {
92b27b08 1654 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1655 return;
1656 }
1657
ee7b9f93 1658 if (--pll->active) {
92b27b08 1659 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1660 return;
ee7b9f93
JB		 1661 }
1662
1663 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1664
1665 /* Make sure transcoder isn't still depending on us */
1666 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1667
ee7b9f93 1668 reg = pll->pll_reg;
92f2584a
JB		 1669 val = I915_READ(reg);
1670 val &= ~DPLL_VCO_ENABLE;
1671 I915_WRITE(reg, val);
1672 POSTING_READ(reg);
1673 udelay(200);
ee7b9f93
JB		 1674
1675 pll->on = false;
92f2584a
JB		 1676}
1677
b8a4f404
PZ		 1678static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1679 enum pipe pipe)
040484af 1680{
23670b32 1681 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1682 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1683 uint32_t reg, val, pipeconf_val;
040484af
JB		 1684
1685 /* PCH only available on ILK+ */
1686 BUG_ON(dev_priv->info->gen < 5);
1687
1688 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1689 assert_pch_pll_enabled(dev_priv,
1690 to_intel_crtc(crtc)->pch_pll,
1691 to_intel_crtc(crtc));
040484af
JB		 1692
1693 /* FDI must be feeding us bits for PCH ports */
1694 assert_fdi_tx_enabled(dev_priv, pipe);
1695 assert_fdi_rx_enabled(dev_priv, pipe);
1696
23670b32
DV		 1697 if (HAS_PCH_CPT(dev)) {
1698 /* Workaround: Set the timing override bit before enabling the
1699 * pch transcoder. */
1700 reg = TRANS_CHICKEN2(pipe);
1701 val = I915_READ(reg);
1702 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1703 I915_WRITE(reg, val);
59c859d6 1704 }
23670b32 1705
040484af
JB		 1706 reg = TRANSCONF(pipe);
1707 val = I915_READ(reg);
5f7f726d 1708 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1709
1710 if (HAS_PCH_IBX(dev_priv->dev)) {
1711 /*
1712 * make the BPC in transcoder be consistent with
1713 * that in pipeconf reg.
1714 */
dfd07d72
DV		 1715 val &= ~PIPECONF_BPC_MASK;
1716 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1717 }
5f7f726d
PZ		 1718
1719 val &= ~TRANS_INTERLACE_MASK;
1720 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1721 if (HAS_PCH_IBX(dev_priv->dev) &&
1722 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1723 val |= TRANS_LEGACY_INTERLACED_ILK;
1724 else
1725 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1726 else
1727 val |= TRANS_PROGRESSIVE;
1728
040484af
JB		 1729 I915_WRITE(reg, val | TRANS_ENABLE);
1730 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1731 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1732}
1733
8fb033d7 1734static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1735 enum transcoder cpu_transcoder)
040484af 1736{
8fb033d7 1737 u32 val, pipeconf_val;
8fb033d7
PZ		 1738
1739 /* PCH only available on ILK+ */
1740 BUG_ON(dev_priv->info->gen < 5);
1741
8fb033d7 1742 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1743 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1744 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1745
223a6fdf
PZ		 1746 /* Workaround: set timing override bit. */
1747 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1748 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1749 I915_WRITE(_TRANSA_CHICKEN2, val);
1750
25f3ef11 1751 val = TRANS_ENABLE;
937bb610 1752 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1753
9a76b1c6
PZ		 1754 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1755 PIPECONF_INTERLACED_ILK)
a35f2679 1756 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1757 else
1758 val |= TRANS_PROGRESSIVE;
1759
25f3ef11 1760 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1761 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1762 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1763}
1764
b8a4f404
PZ		 1765static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1766 enum pipe pipe)
040484af 1767{
23670b32
DV		 1768 struct drm_device *dev = dev_priv->dev;
1769 uint32_t reg, val;
040484af
JB		 1770
1771 /* FDI relies on the transcoder */
1772 assert_fdi_tx_disabled(dev_priv, pipe);
1773 assert_fdi_rx_disabled(dev_priv, pipe);
1774
291906f1
JB		 1775 /* Ports must be off as well */
1776 assert_pch_ports_disabled(dev_priv, pipe);
1777
040484af
JB		 1778 reg = TRANSCONF(pipe);
1779 val = I915_READ(reg);
1780 val &= ~TRANS_ENABLE;
1781 I915_WRITE(reg, val);
1782 /* wait for PCH transcoder off, transcoder state */
1783 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1784 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1785
1786 if (!HAS_PCH_IBX(dev)) {
1787 /* Workaround: Clear the timing override chicken bit again. */
1788 reg = TRANS_CHICKEN2(pipe);
1789 val = I915_READ(reg);
1790 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1791 I915_WRITE(reg, val);
1792 }
040484af
JB		 1793}
1794
ab4d966c 1795static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1796{
8fb033d7
PZ		 1797 u32 val;
1798
8a52fd9f 1799 val = I915_READ(_TRANSACONF);
8fb033d7 1800 val &= ~TRANS_ENABLE;
8a52fd9f 1801 I915_WRITE(_TRANSACONF, val);
8fb033d7 1802 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1803 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1804 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1805
1806 /* Workaround: clear timing override bit. */
1807 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1808 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1809 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1810}
1811
b24e7179 1812/**
309cfea8 1813 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1814 * @dev_priv: i915 private structure
1815 * @pipe: pipe to enable
040484af 1816 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1817 *
1818 * Enable @pipe, making sure that various hardware specific requirements
1819 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1820 *
1821 * @pipe should be %PIPE_A or %PIPE_B.
1822 *
1823 * Will wait until the pipe is actually running (i.e. first vblank) before
1824 * returning.
1825 */
040484af
JB		 1826static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1827 bool pch_port)
b24e7179 1828{
702e7a56
PZ		 1829 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1830 pipe);
1a240d4d 1831 enum pipe pch_transcoder;
b24e7179
JB		 1832 int reg;
1833 u32 val;
1834
58c6eaa2
DV		 1835 assert_planes_disabled(dev_priv, pipe);
1836 assert_sprites_disabled(dev_priv, pipe);
1837
681e5811 1838 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
b24e7179
JB		 1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
cc391bbb 1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
040484af
JB		 1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
b24e7179 1859
702e7a56 1860 reg = PIPECONF(cpu_transcoder);
b24e7179 1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
1869/**
309cfea8 1870 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883{
702e7a56
PZ		 1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
b24e7179
JB		 1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
19332d7a 1894 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
702e7a56 1900 reg = PIPECONF(cpu_transcoder);
b24e7179 1901 val = I915_READ(reg);
00d70b15
CW		 1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907}
1908
d74362c9
KP		 1909/*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
6f1d69b0 1913void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1914 enum plane plane)
1915{
14f86147
DL		 1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1920}
1921
b24e7179
JB		 1922/**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
00d70b15
CW		 1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1945 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
b24e7179
JB		 1949/**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959{
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
00d70b15
CW		 1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971}
1972
693db184
CW		 1973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
127bd2ac 1982int
48b956c5 1983intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1984 struct drm_i915_gem_object *obj,
919926ae 1985 struct intel_ring_buffer *pipelined)
6b95a207 1986{
ce453d81 1987 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1988 u32 alignment;
1989 int ret;
1990
05394f39 1991 switch (obj->tiling_mode) {
6b95a207 1992 case I915_TILING_NONE:
534843da
CW		 1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
a6c45cf0 1995 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
6b95a207
KH		 1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
8bb6e959
DV		 2005 /* Despite that we check this in framebuffer_init userspace can
2006 * screw us over and change the tiling after the fact. Only
2007 * pinned buffers can't change their tiling. */
2008 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 2009 return -EINVAL;
2010 default:
2011 BUG();
2012 }
2013
693db184
CW		 2014 /* Note that the w/a also requires 64 PTE of padding following the
2015 * bo. We currently fill all unused PTE with the shadow page and so
2016 * we should always have valid PTE following the scanout preventing
2017 * the VT-d warning.
2018 */
2019 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2020 alignment = 256 * 1024;
2021
ce453d81 2022 dev_priv->mm.interruptible = false;
2da3b9b9 2023 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2024 if (ret)
ce453d81 2025 goto err_interruptible;
6b95a207
KH		 2026
2027 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2028 * fence, whereas 965+ only requires a fence if using
2029 * framebuffer compression. For simplicity, we always install
2030 * a fence as the cost is not that onerous.
2031 */
06d98131 2032 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2033 if (ret)
2034 goto err_unpin;
1690e1eb 2035
9a5a53b3 2036 i915_gem_object_pin_fence(obj);
6b95a207 2037
ce453d81 2038 dev_priv->mm.interruptible = true;
6b95a207 2039 return 0;
48b956c5
CW		 2040
2041err_unpin:
2042 i915_gem_object_unpin(obj);
ce453d81
CW		 2043err_interruptible:
2044 dev_priv->mm.interruptible = true;
48b956c5 2045 return ret;
6b95a207
KH		 2046}
2047
1690e1eb
CW		 2048void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2049{
2050 i915_gem_object_unpin_fence(obj);
2051 i915_gem_object_unpin(obj);
2052}
2053
c2c75131
DV		 2054/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2055 * is assumed to be a power-of-two. */
bc752862
CW		 2056unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2057 unsigned int tiling_mode,
2058 unsigned int cpp,
2059 unsigned int pitch)
c2c75131 2060{
bc752862
CW		 2061 if (tiling_mode != I915_TILING_NONE) {
2062 unsigned int tile_rows, tiles;
c2c75131 2063
bc752862
CW		 2064 tile_rows = *y / 8;
2065 *y %= 8;
c2c75131 2066
bc752862
CW		 2067 tiles = *x / (512/cpp);
2068 *x %= 512/cpp;
2069
2070 return tile_rows * pitch * 8 + tiles * 4096;
2071 } else {
2072 unsigned int offset;
2073
2074 offset = *y * pitch + *x * cpp;
2075 *y = 0;
2076 *x = (offset & 4095) / cpp;
2077 return offset & -4096;
2078 }
c2c75131
DV		 2079}
2080
17638cd6
JB		 2081static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2082 int x, int y)
81255565
JB		 2083{
2084 struct drm_device *dev = crtc->dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 struct intel_framebuffer *intel_fb;
05394f39 2088 struct drm_i915_gem_object *obj;
81255565 2089 int plane = intel_crtc->plane;
e506a0c6 2090 unsigned long linear_offset;
81255565 2091 u32 dspcntr;
5eddb70b 2092 u32 reg;
81255565
JB		 2093
2094 switch (plane) {
2095 case 0:
2096 case 1:
2097 break;
2098 default:
84f44ce7 2099 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2100 return -EINVAL;
2101 }
2102
2103 intel_fb = to_intel_framebuffer(fb);
2104 obj = intel_fb->obj;
81255565 2105
5eddb70b
CW		 2106 reg = DSPCNTR(plane);
2107 dspcntr = I915_READ(reg);
81255565
JB		 2108 /* Mask out pixel format bits in case we change it */
2109 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2110 switch (fb->pixel_format) {
2111 case DRM_FORMAT_C8:
81255565
JB		 2112 dspcntr |= DISPPLANE_8BPP;
2113 break;
57779d06
VS		 2114 case DRM_FORMAT_XRGB1555:
2115 case DRM_FORMAT_ARGB1555:
2116 dspcntr |= DISPPLANE_BGRX555;
81255565 2117 break;
57779d06
VS		 2118 case DRM_FORMAT_RGB565:
2119 dspcntr |= DISPPLANE_BGRX565;
2120 break;
2121 case DRM_FORMAT_XRGB8888:
2122 case DRM_FORMAT_ARGB8888:
2123 dspcntr |= DISPPLANE_BGRX888;
2124 break;
2125 case DRM_FORMAT_XBGR8888:
2126 case DRM_FORMAT_ABGR8888:
2127 dspcntr |= DISPPLANE_RGBX888;
2128 break;
2129 case DRM_FORMAT_XRGB2101010:
2130 case DRM_FORMAT_ARGB2101010:
2131 dspcntr |= DISPPLANE_BGRX101010;
2132 break;
2133 case DRM_FORMAT_XBGR2101010:
2134 case DRM_FORMAT_ABGR2101010:
2135 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2136 break;
2137 default:
baba133a 2138 BUG();
81255565 2139 }
57779d06 2140
a6c45cf0 2141 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2142 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2143 dspcntr |= DISPPLANE_TILED;
2144 else
2145 dspcntr &= ~DISPPLANE_TILED;
2146 }
2147
5eddb70b 2148 I915_WRITE(reg, dspcntr);
81255565 2149
e506a0c6 2150 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2151
c2c75131
DV		 2152 if (INTEL_INFO(dev)->gen >= 4) {
2153 intel_crtc->dspaddr_offset =
bc752862
CW		 2154 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2155 fb->bits_per_pixel / 8,
2156 fb->pitches[0]);
c2c75131
DV		 2157 linear_offset -= intel_crtc->dspaddr_offset;
2158 } else {
e506a0c6 2159 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2160 }
e506a0c6
DV		 2161
2162 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2163 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2164 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2165 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2166 I915_MODIFY_DISPBASE(DSPSURF(plane),
2167 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2168 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2169 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2170 } else
e506a0c6 2171 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2172 POSTING_READ(reg);
81255565 2173
17638cd6
JB		 2174 return 0;
2175}
2176
2177static int ironlake_update_plane(struct drm_crtc *crtc,
2178 struct drm_framebuffer *fb, int x, int y)
2179{
2180 struct drm_device *dev = crtc->dev;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183 struct intel_framebuffer *intel_fb;
2184 struct drm_i915_gem_object *obj;
2185 int plane = intel_crtc->plane;
e506a0c6 2186 unsigned long linear_offset;
17638cd6
JB		 2187 u32 dspcntr;
2188 u32 reg;
2189
2190 switch (plane) {
2191 case 0:
2192 case 1:
27f8227b 2193 case 2:
17638cd6
JB		 2194 break;
2195 default:
84f44ce7 2196 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2197 return -EINVAL;
2198 }
2199
2200 intel_fb = to_intel_framebuffer(fb);
2201 obj = intel_fb->obj;
2202
2203 reg = DSPCNTR(plane);
2204 dspcntr = I915_READ(reg);
2205 /* Mask out pixel format bits in case we change it */
2206 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2207 switch (fb->pixel_format) {
2208 case DRM_FORMAT_C8:
17638cd6
JB		 2209 dspcntr |= DISPPLANE_8BPP;
2210 break;
57779d06
VS		 2211 case DRM_FORMAT_RGB565:
2212 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2213 break;
57779d06
VS		 2214 case DRM_FORMAT_XRGB8888:
2215 case DRM_FORMAT_ARGB8888:
2216 dspcntr |= DISPPLANE_BGRX888;
2217 break;
2218 case DRM_FORMAT_XBGR8888:
2219 case DRM_FORMAT_ABGR8888:
2220 dspcntr |= DISPPLANE_RGBX888;
2221 break;
2222 case DRM_FORMAT_XRGB2101010:
2223 case DRM_FORMAT_ARGB2101010:
2224 dspcntr |= DISPPLANE_BGRX101010;
2225 break;
2226 case DRM_FORMAT_XBGR2101010:
2227 case DRM_FORMAT_ABGR2101010:
2228 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2229 break;
2230 default:
baba133a 2231 BUG();
17638cd6
JB		 2232 }
2233
2234 if (obj->tiling_mode != I915_TILING_NONE)
2235 dspcntr |= DISPPLANE_TILED;
2236 else
2237 dspcntr &= ~DISPPLANE_TILED;
2238
2239 /* must disable */
2240 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2241
2242 I915_WRITE(reg, dspcntr);
2243
e506a0c6 2244 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2245 intel_crtc->dspaddr_offset =
bc752862
CW		 2246 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2247 fb->bits_per_pixel / 8,
2248 fb->pitches[0]);
c2c75131 2249 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2250
e506a0c6
DV		 2251 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2252 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2253 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2254 I915_MODIFY_DISPBASE(DSPSURF(plane),
2255 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2256 if (IS_HASWELL(dev)) {
2257 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2258 } else {
2259 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2260 I915_WRITE(DSPLINOFF(plane), linear_offset);
2261 }
17638cd6
JB		 2262 POSTING_READ(reg);
2263
2264 return 0;
2265}
2266
2267/* Assume fb object is pinned & idle & fenced and just update base pointers */
2268static int
2269intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2270 int x, int y, enum mode_set_atomic state)
2271{
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2274
6b8e6ed0
CW		 2275 if (dev_priv->display.disable_fbc)
2276 dev_priv->display.disable_fbc(dev);
3dec0095 2277 intel_increase_pllclock(crtc);
81255565 2278
6b8e6ed0 2279 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2280}
2281
96a02917
VS		 2282void intel_display_handle_reset(struct drm_device *dev)
2283{
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct drm_crtc *crtc;
2286
2287 /*
2288 * Flips in the rings have been nuked by the reset,
2289 * so complete all pending flips so that user space
2290 * will get its events and not get stuck.
2291 *
2292 * Also update the base address of all primary
2293 * planes to the the last fb to make sure we're
2294 * showing the correct fb after a reset.
2295 *
2296 * Need to make two loops over the crtcs so that we
2297 * don't try to grab a crtc mutex before the
2298 * pending_flip_queue really got woken up.
2299 */
2300
2301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303 enum plane plane = intel_crtc->plane;
2304
2305 intel_prepare_page_flip(dev, plane);
2306 intel_finish_page_flip_plane(dev, plane);
2307 }
2308
2309 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311
2312 mutex_lock(&crtc->mutex);
2313 if (intel_crtc->active)
2314 dev_priv->display.update_plane(crtc, crtc->fb,
2315 crtc->x, crtc->y);
2316 mutex_unlock(&crtc->mutex);
2317 }
2318}
2319
14667a4b
CW		 2320static int
2321intel_finish_fb(struct drm_framebuffer *old_fb)
2322{
2323 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2324 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2325 bool was_interruptible = dev_priv->mm.interruptible;
2326 int ret;
2327
14667a4b
CW		 2328 /* Big Hammer, we also need to ensure that any pending
2329 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2330 * current scanout is retired before unpinning the old
2331 * framebuffer.
2332 *
2333 * This should only fail upon a hung GPU, in which case we
2334 * can safely continue.
2335 */
2336 dev_priv->mm.interruptible = false;
2337 ret = i915_gem_object_finish_gpu(obj);
2338 dev_priv->mm.interruptible = was_interruptible;
2339
2340 return ret;
2341}
2342
198598d0
VS		 2343static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2344{
2345 struct drm_device *dev = crtc->dev;
2346 struct drm_i915_master_private *master_priv;
2347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2348
2349 if (!dev->primary->master)
2350 return;
2351
2352 master_priv = dev->primary->master->driver_priv;
2353 if (!master_priv->sarea_priv)
2354 return;
2355
2356 switch (intel_crtc->pipe) {
2357 case 0:
2358 master_priv->sarea_priv->pipeA_x = x;
2359 master_priv->sarea_priv->pipeA_y = y;
2360 break;
2361 case 1:
2362 master_priv->sarea_priv->pipeB_x = x;
2363 master_priv->sarea_priv->pipeB_y = y;
2364 break;
2365 default:
2366 break;
2367 }
2368}
2369
5c3b82e2 2370static int
3c4fdcfb 2371intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2372 struct drm_framebuffer *fb)
79e53945
JB		 2373{
2374 struct drm_device *dev = crtc->dev;
6b8e6ed0 2375 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2377 struct drm_framebuffer *old_fb;
5c3b82e2 2378 int ret;
79e53945
JB		 2379
2380 /* no fb bound */
94352cf9 2381 if (!fb) {
a5071c2f 2382 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2383 return 0;
2384 }
2385
7eb552ae 2386 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2387 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2388 plane_name(intel_crtc->plane),
2389 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2390 return -EINVAL;
79e53945
JB		 2391 }
2392
5c3b82e2 2393 mutex_lock(&dev->struct_mutex);
265db958 2394 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2395 to_intel_framebuffer(fb)->obj,
919926ae 2396 NULL);
5c3b82e2
CW		 2397 if (ret != 0) {
2398 mutex_unlock(&dev->struct_mutex);
a5071c2f 2399 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2400 return ret;
2401 }
79e53945 2402
94352cf9 2403 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2404 if (ret) {
94352cf9 2405 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2406 mutex_unlock(&dev->struct_mutex);
a5071c2f 2407 DRM_ERROR("failed to update base address\n");
4e6cfefc 2408 return ret;
79e53945 2409 }
3c4fdcfb 2410
94352cf9
DV		 2411 old_fb = crtc->fb;
2412 crtc->fb = fb;
6c4c86f5
DV		 2413 crtc->x = x;
2414 crtc->y = y;
94352cf9 2415
b7f1de28
CW		 2416 if (old_fb) {
2417 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2418 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2419 }
652c393a 2420
6b8e6ed0 2421 intel_update_fbc(dev);
5c3b82e2 2422 mutex_unlock(&dev->struct_mutex);
79e53945 2423
198598d0 2424 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2425
2426 return 0;
79e53945
JB		 2427}
2428
5e84e1a4
ZW		 2429static void intel_fdi_normal_train(struct drm_crtc *crtc)
2430{
2431 struct drm_device *dev = crtc->dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434 int pipe = intel_crtc->pipe;
2435 u32 reg, temp;
2436
2437 /* enable normal train */
2438 reg = FDI_TX_CTL(pipe);
2439 temp = I915_READ(reg);
61e499bf 2440 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2441 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2442 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2443 } else {
2444 temp &= ~FDI_LINK_TRAIN_NONE;
2445 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2446 }
5e84e1a4
ZW		 2447 I915_WRITE(reg, temp);
2448
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 if (HAS_PCH_CPT(dev)) {
2452 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2453 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2454 } else {
2455 temp &= ~FDI_LINK_TRAIN_NONE;
2456 temp |= FDI_LINK_TRAIN_NONE;
2457 }
2458 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2459
2460 /* wait one idle pattern time */
2461 POSTING_READ(reg);
2462 udelay(1000);
357555c0
JB		 2463
2464 /* IVB wants error correction enabled */
2465 if (IS_IVYBRIDGE(dev))
2466 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2467 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2468}
2469
01a415fd
DV		 2470static void ivb_modeset_global_resources(struct drm_device *dev)
2471{
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 struct intel_crtc *pipe_B_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2475 struct intel_crtc *pipe_C_crtc =
2476 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2477 uint32_t temp;
2478
2479 /* When everything is off disable fdi C so that we could enable fdi B
2480 * with all lanes. XXX: This misses the case where a pipe is not using
2481 * any pch resources and so doesn't need any fdi lanes. */
2482 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2485
2486 temp = I915_READ(SOUTH_CHICKEN1);
2487 temp &= ~FDI_BC_BIFURCATION_SELECT;
2488 DRM_DEBUG_KMS("disabling fdi C rx\n");
2489 I915_WRITE(SOUTH_CHICKEN1, temp);
2490 }
2491}
2492
8db9d77b
ZW		 2493/* The FDI link training functions for ILK/Ibexpeak. */
2494static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2495{
2496 struct drm_device *dev = crtc->dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2499 int pipe = intel_crtc->pipe;
0fc932b8 2500 int plane = intel_crtc->plane;
5eddb70b 2501 u32 reg, temp, tries;
8db9d77b 2502
0fc932b8
JB		 2503 /* FDI needs bits from pipe & plane first */
2504 assert_pipe_enabled(dev_priv, pipe);
2505 assert_plane_enabled(dev_priv, plane);
2506
e1a44743
AJ		 2507 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508 for train result */
5eddb70b
CW		 2509 reg = FDI_RX_IMR(pipe);
2510 temp = I915_READ(reg);
e1a44743
AJ		 2511 temp &= ~FDI_RX_SYMBOL_LOCK;
2512 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2513 I915_WRITE(reg, temp);
2514 I915_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597
AJ		 2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2524 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2525
5eddb70b
CW		 2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
8db9d77b
ZW		 2528 temp &= ~FDI_LINK_TRAIN_NONE;
2529 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2530 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531
2532 POSTING_READ(reg);
8db9d77b
ZW		 2533 udelay(150);
2534
5b2adf89 2535 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2536 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2538 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2539
5eddb70b 2540 reg = FDI_RX_IIR(pipe);
e1a44743 2541 for (tries = 0; tries < 5; tries++) {
5eddb70b 2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2544
2545 if ((temp & FDI_RX_BIT_LOCK)) {
2546 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2547 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2548 break;
2549 }
8db9d77b 2550 }
e1a44743 2551 if (tries == 5)
5eddb70b 2552 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2553
2554 /* Train 2 */
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_NONE;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2559 I915_WRITE(reg, temp);
8db9d77b 2560
5eddb70b
CW		 2561 reg = FDI_RX_CTL(pipe);
2562 temp = I915_READ(reg);
8db9d77b
ZW		 2563 temp &= ~FDI_LINK_TRAIN_NONE;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2565 I915_WRITE(reg, temp);
8db9d77b 2566
5eddb70b
CW		 2567 POSTING_READ(reg);
2568 udelay(150);
8db9d77b 2569
5eddb70b 2570 reg = FDI_RX_IIR(pipe);
e1a44743 2571 for (tries = 0; tries < 5; tries++) {
5eddb70b 2572 temp = I915_READ(reg);
8db9d77b
ZW		 2573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574
2575 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578 break;
2579 }
8db9d77b 2580 }
e1a44743 2581 if (tries == 5)
5eddb70b 2582 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2583
2584 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2585
8db9d77b
ZW		 2586}
2587
0206e353 2588static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2589 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2590 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2591 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2592 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2593};
2594
2595/* The FDI link training functions for SNB/Cougarpoint. */
2596static void gen6_fdi_link_train(struct drm_crtc *crtc)
2597{
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
fa37d39e 2602 u32 reg, temp, i, retry;
8db9d77b 2603
e1a44743
AJ		 2604 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605 for train result */
5eddb70b
CW		 2606 reg = FDI_RX_IMR(pipe);
2607 temp = I915_READ(reg);
e1a44743
AJ		 2608 temp &= ~FDI_RX_SYMBOL_LOCK;
2609 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
e1a44743
AJ		 2613 udelay(150);
2614
8db9d77b 2615 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
77ffb597
AJ		 2618 temp &= ~(7 << 19);
2619 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2620 temp &= ~FDI_LINK_TRAIN_NONE;
2621 temp |= FDI_LINK_TRAIN_PATTERN_1;
2622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2623 /* SNB-B */
2624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2625 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2626
d74cf324
DV		 2627 I915_WRITE(FDI_RX_MISC(pipe),
2628 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2629
5eddb70b
CW		 2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
8db9d77b
ZW		 2632 if (HAS_PCH_CPT(dev)) {
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 } else {
2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_1;
2638 }
5eddb70b
CW		 2639 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2640
2641 POSTING_READ(reg);
8db9d77b
ZW		 2642 udelay(150);
2643
0206e353 2644 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
8db9d77b
ZW		 2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
8db9d77b
ZW		 2652 udelay(500);
2653
fa37d39e
SP		 2654 for (retry = 0; retry < 5; retry++) {
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658 if (temp & FDI_RX_BIT_LOCK) {
2659 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660 DRM_DEBUG_KMS("FDI train 1 done.\n");
2661 break;
2662 }
2663 udelay(50);
8db9d77b 2664 }
fa37d39e
SP		 2665 if (retry < 5)
2666 break;
8db9d77b
ZW		 2667 }
2668 if (i == 4)
5eddb70b 2669 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2670
2671 /* Train 2 */
5eddb70b
CW		 2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
8db9d77b
ZW		 2674 temp &= ~FDI_LINK_TRAIN_NONE;
2675 temp |= FDI_LINK_TRAIN_PATTERN_2;
2676 if (IS_GEN6(dev)) {
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 /* SNB-B */
2679 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2680 }
5eddb70b 2681 I915_WRITE(reg, temp);
8db9d77b 2682
5eddb70b
CW		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
8db9d77b
ZW		 2685 if (HAS_PCH_CPT(dev)) {
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2688 } else {
2689 temp &= ~FDI_LINK_TRAIN_NONE;
2690 temp |= FDI_LINK_TRAIN_PATTERN_2;
2691 }
5eddb70b
CW		 2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
8db9d77b
ZW		 2695 udelay(150);
2696
0206e353 2697 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
8db9d77b
ZW		 2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
8db9d77b
ZW		 2705 udelay(500);
2706
fa37d39e
SP		 2707 for (retry = 0; retry < 5; retry++) {
2708 reg = FDI_RX_IIR(pipe);
2709 temp = I915_READ(reg);
2710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711 if (temp & FDI_RX_SYMBOL_LOCK) {
2712 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713 DRM_DEBUG_KMS("FDI train 2 done.\n");
2714 break;
2715 }
2716 udelay(50);
8db9d77b 2717 }
fa37d39e
SP		 2718 if (retry < 5)
2719 break;
8db9d77b
ZW		 2720 }
2721 if (i == 4)
5eddb70b 2722 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2723
2724 DRM_DEBUG_KMS("FDI train done.\n");
2725}
2726
357555c0
JB		 2727/* Manual link training for Ivy Bridge A0 parts */
2728static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2729{
2730 struct drm_device *dev = crtc->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp, i;
2735
2736 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2737 for train result */
2738 reg = FDI_RX_IMR(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_RX_SYMBOL_LOCK;
2741 temp &= ~FDI_RX_BIT_LOCK;
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(150);
2746
01a415fd
DV		 2747 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2748 I915_READ(FDI_RX_IIR(pipe)));
2749
357555c0
JB		 2750 /* enable CPU FDI TX and PCH FDI RX */
2751 reg = FDI_TX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 temp &= ~(7 << 19);
2754 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2755 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2759 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2760 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2761
d74cf324
DV		 2762 I915_WRITE(FDI_RX_MISC(pipe),
2763 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2764
357555c0
JB		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~FDI_LINK_TRAIN_AUTO;
2768 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2770 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2771 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(150);
2775
0206e353 2776 for (i = 0; i < 4; i++) {
357555c0
JB		 2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2780 temp |= snb_b_fdi_train_param[i];
2781 I915_WRITE(reg, temp);
2782
2783 POSTING_READ(reg);
2784 udelay(500);
2785
2786 reg = FDI_RX_IIR(pipe);
2787 temp = I915_READ(reg);
2788 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789
2790 if (temp & FDI_RX_BIT_LOCK ||
2791 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2792 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2793 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2794 break;
2795 }
2796 }
2797 if (i == 4)
2798 DRM_ERROR("FDI train 1 fail!\n");
2799
2800 /* Train 2 */
2801 reg = FDI_TX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2804 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2805 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2806 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2807 I915_WRITE(reg, temp);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2813 I915_WRITE(reg, temp);
2814
2815 POSTING_READ(reg);
2816 udelay(150);
2817
0206e353 2818 for (i = 0; i < 4; i++) {
357555c0
JB		 2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2822 temp |= snb_b_fdi_train_param[i];
2823 I915_WRITE(reg, temp);
2824
2825 POSTING_READ(reg);
2826 udelay(500);
2827
2828 reg = FDI_RX_IIR(pipe);
2829 temp = I915_READ(reg);
2830 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2831
2832 if (temp & FDI_RX_SYMBOL_LOCK) {
2833 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2834 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2835 break;
2836 }
2837 }
2838 if (i == 4)
2839 DRM_ERROR("FDI train 2 fail!\n");
2840
2841 DRM_DEBUG_KMS("FDI train done.\n");
2842}
2843
88cefb6c 2844static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2845{
88cefb6c 2846 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2847 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2848 int pipe = intel_crtc->pipe;
5eddb70b 2849 u32 reg, temp;
79e53945 2850
c64e311e 2851
c98e9dcf 2852 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2856 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2858 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2859
2860 POSTING_READ(reg);
c98e9dcf
JB		 2861 udelay(200);
2862
2863 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp | FDI_PCDCLK);
2866
2867 POSTING_READ(reg);
c98e9dcf
JB		 2868 udelay(200);
2869
20749730
PZ		 2870 /* Enable CPU FDI TX PLL, always on for Ironlake */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2874 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2875
20749730
PZ		 2876 POSTING_READ(reg);
2877 udelay(100);
6be4a607 2878 }
0e23b99d
JB		 2879}
2880
88cefb6c
DV		 2881static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2882{
2883 struct drm_device *dev = intel_crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 int pipe = intel_crtc->pipe;
2886 u32 reg, temp;
2887
2888 /* Switch from PCDclk to Rawclk */
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2892
2893 /* Disable CPU FDI TX PLL */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2897
2898 POSTING_READ(reg);
2899 udelay(100);
2900
2901 reg = FDI_RX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2904
2905 /* Wait for the clocks to turn off. */
2906 POSTING_READ(reg);
2907 udelay(100);
2908}
2909
0fc932b8
JB		 2910static void ironlake_fdi_disable(struct drm_crtc *crtc)
2911{
2912 struct drm_device *dev = crtc->dev;
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2915 int pipe = intel_crtc->pipe;
2916 u32 reg, temp;
2917
2918 /* disable CPU FDI tx and PCH FDI rx */
2919 reg = FDI_TX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2922 POSTING_READ(reg);
2923
2924 reg = FDI_RX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 temp &= ~(0x7 << 16);
dfd07d72 2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2928 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2929
2930 POSTING_READ(reg);
2931 udelay(100);
2932
2933 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2934 if (HAS_PCH_IBX(dev)) {
2935 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2936 }
0fc932b8
JB		 2937
2938 /* still set train pattern 1 */
2939 reg = FDI_TX_CTL(pipe);
2940 temp = I915_READ(reg);
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943 I915_WRITE(reg, temp);
2944
2945 reg = FDI_RX_CTL(pipe);
2946 temp = I915_READ(reg);
2947 if (HAS_PCH_CPT(dev)) {
2948 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2950 } else {
2951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1;
2953 }
2954 /* BPC in FDI rx is consistent with that in PIPECONF */
2955 temp &= ~(0x07 << 16);
dfd07d72 2956 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2957 I915_WRITE(reg, temp);
2958
2959 POSTING_READ(reg);
2960 udelay(100);
2961}
2962
5bb61643
CW		 2963static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2964{
2965 struct drm_device *dev = crtc->dev;
2966 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2968 unsigned long flags;
2969 bool pending;
2970
10d83730
VS		 2971 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2972 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2973 return false;
2974
2975 spin_lock_irqsave(&dev->event_lock, flags);
2976 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2977 spin_unlock_irqrestore(&dev->event_lock, flags);
2978
2979 return pending;
2980}
2981
e6c3a2a6
CW		 2982static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2983{
0f91128d 2984 struct drm_device *dev = crtc->dev;
5bb61643 2985 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2986
2987 if (crtc->fb == NULL)
2988 return;
2989
2c10d571
DV		 2990 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2991
5bb61643
CW		 2992 wait_event(dev_priv->pending_flip_queue,
2993 !intel_crtc_has_pending_flip(crtc));
2994
0f91128d
CW		 2995 mutex_lock(&dev->struct_mutex);
2996 intel_finish_fb(crtc->fb);
2997 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2998}
2999
e615efe4
ED		 3000/* Program iCLKIP clock to the desired frequency */
3001static void lpt_program_iclkip(struct drm_crtc *crtc)
3002{
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006 u32 temp;
3007
09153000
DV		 3008 mutex_lock(&dev_priv->dpio_lock);
3009
e615efe4
ED		 3010 /* It is necessary to ungate the pixclk gate prior to programming
3011 * the divisors, and gate it back when it is done.
3012 */
3013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3014
3015 /* Disable SSCCTL */
3016 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3017 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3018 SBI_SSCCTL_DISABLE,
3019 SBI_ICLK);
e615efe4
ED		 3020
3021 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022 if (crtc->mode.clock == 20000) {
3023 auxdiv = 1;
3024 divsel = 0x41;
3025 phaseinc = 0x20;
3026 } else {
3027 /* The iCLK virtual clock root frequency is in MHz,
3028 * but the crtc->mode.clock in in KHz. To get the divisors,
3029 * it is necessary to divide one by another, so we
3030 * convert the virtual clock precision to KHz here for higher
3031 * precision.
3032 */
3033 u32 iclk_virtual_root_freq = 172800 * 1000;
3034 u32 iclk_pi_range = 64;
3035 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038 msb_divisor_value = desired_divisor / iclk_pi_range;
3039 pi_value = desired_divisor % iclk_pi_range;
3040
3041 auxdiv = 0;
3042 divsel = msb_divisor_value - 2;
3043 phaseinc = pi_value;
3044 }
3045
3046 /* This should not happen with any sane values */
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053 crtc->mode.clock,
3054 auxdiv,
3055 divsel,
3056 phasedir,
3057 phaseinc);
3058
3059 /* Program SSCDIVINTPHASE6 */
988d6ee8 3060 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3061 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3067 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3068
3069 /* Program SSCAUXDIV */
988d6ee8 3070 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3071 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3073 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3074
3075 /* Enable modulator and associated divider */
988d6ee8 3076 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3077 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3078 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3079
3080 /* Wait for initialization time */
3081 udelay(24);
3082
3083 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3084
3085 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3086}
3087
f67a559d
JB		 3088/*
3089 * Enable PCH resources required for PCH ports:
3090 * - PCH PLLs
3091 * - FDI training & RX/TX
3092 * - update transcoder timings
3093 * - DP transcoding bits
3094 * - transcoder
3095 */
3096static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3097{
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
ee7b9f93 3102 u32 reg, temp;
2c07245f 3103
e7e164db
CW		 3104 assert_transcoder_disabled(dev_priv, pipe);
3105
cd986abb
DV		 3106 /* Write the TU size bits before fdi link training, so that error
3107 * detection works. */
3108 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3109 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3110
c98e9dcf 3111 /* For PCH output, training FDI link */
674cf967 3112 dev_priv->display.fdi_link_train(crtc);
2c07245f 3113
572deb37
DV		 3114 /* XXX: pch pll's can be enabled any time before we enable the PCH
3115 * transcoder, and we actually should do this to not upset any PCH
3116 * transcoder that already use the clock when we share it.
3117 *
3118 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3119 * unconditionally resets the pll - we need that to have the right LVDS
3120 * enable sequence. */
b6b4e185 3121 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3122
303b81e0 3123 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3124 u32 sel;
4b645f14 3125
c98e9dcf 3126 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3127 switch (pipe) {
3128 default:
3129 case 0:
3130 temp |= TRANSA_DPLL_ENABLE;
3131 sel = TRANSA_DPLLB_SEL;
3132 break;
3133 case 1:
3134 temp |= TRANSB_DPLL_ENABLE;
3135 sel = TRANSB_DPLLB_SEL;
3136 break;
3137 case 2:
3138 temp |= TRANSC_DPLL_ENABLE;
3139 sel = TRANSC_DPLLB_SEL;
3140 break;
d64311ab 3141 }
ee7b9f93
JB		 3142 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3143 temp |= sel;
3144 else
3145 temp &= ~sel;
c98e9dcf 3146 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3147 }
5eddb70b 3148
d9b6cb56
JB		 3149 /* set transcoder timing, panel must allow it */
3150 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3151 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3152 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3153 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3154
5eddb70b
CW		 3155 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3156 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3157 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3158 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3159
303b81e0 3160 intel_fdi_normal_train(crtc);
5e84e1a4 3161
c98e9dcf
JB		 3162 /* For PCH DP, enable TRANS_DP_CTL */
3163 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3164 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3165 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3166 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3167 reg = TRANS_DP_CTL(pipe);
3168 temp = I915_READ(reg);
3169 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3170 TRANS_DP_SYNC_MASK |
3171 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3172 temp |= (TRANS_DP_OUTPUT_ENABLE |
3173 TRANS_DP_ENH_FRAMING);
9325c9f0 3174 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3175
3176 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3177 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3178 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3179 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3180
3181 switch (intel_trans_dp_port_sel(crtc)) {
3182 case PCH_DP_B:
5eddb70b 3183 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3184 break;
3185 case PCH_DP_C:
5eddb70b 3186 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3187 break;
3188 case PCH_DP_D:
5eddb70b 3189 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3190 break;
3191 default:
e95d41e1 3192 BUG();
32f9d658 3193 }
2c07245f 3194
5eddb70b 3195 I915_WRITE(reg, temp);
6be4a607 3196 }
b52eb4dc 3197
b8a4f404 3198 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3199}
3200
1507e5bd
PZ		 3201static void lpt_pch_enable(struct drm_crtc *crtc)
3202{
3203 struct drm_device *dev = crtc->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3206 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3207
daed2dbb 3208 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3209
8c52b5e8 3210 lpt_program_iclkip(crtc);
1507e5bd 3211
0540e488 3212 /* Set transcoder timing. */
daed2dbb
PZ		 3213 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3214 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3215 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3216
daed2dbb
PZ		 3217 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3218 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3219 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3220 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3221
937bb610 3222 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3223}
3224
ee7b9f93
JB		 3225static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3226{
3227 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3228
3229 if (pll == NULL)
3230 return;
3231
3232 if (pll->refcount == 0) {
3233 WARN(1, "bad PCH PLL refcount\n");
3234 return;
3235 }
3236
3237 --pll->refcount;
3238 intel_crtc->pch_pll = NULL;
3239}
3240
3241static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3242{
3243 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3244 struct intel_pch_pll *pll;
3245 int i;
3246
3247 pll = intel_crtc->pch_pll;
3248 if (pll) {
3249 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3250 intel_crtc->base.base.id, pll->pll_reg);
3251 goto prepare;
3252 }
3253
98b6bd99
DV		 3254 if (HAS_PCH_IBX(dev_priv->dev)) {
3255 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3256 i = intel_crtc->pipe;
3257 pll = &dev_priv->pch_plls[i];
3258
3259 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3260 intel_crtc->base.base.id, pll->pll_reg);
3261
3262 goto found;
3263 }
3264
ee7b9f93
JB		 3265 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3266 pll = &dev_priv->pch_plls[i];
3267
3268 /* Only want to check enabled timings first */
3269 if (pll->refcount == 0)
3270 continue;
3271
3272 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3273 fp == I915_READ(pll->fp0_reg)) {
3274 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3275 intel_crtc->base.base.id,
3276 pll->pll_reg, pll->refcount, pll->active);
3277
3278 goto found;
3279 }
3280 }
3281
3282 /* Ok no matching timings, maybe there's a free one? */
3283 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3284 pll = &dev_priv->pch_plls[i];
3285 if (pll->refcount == 0) {
3286 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3287 intel_crtc->base.base.id, pll->pll_reg);
3288 goto found;
3289 }
3290 }
3291
3292 return NULL;
3293
3294found:
3295 intel_crtc->pch_pll = pll;
3296 pll->refcount++;
84f44ce7 3297 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3298prepare: /* separate function? */
3299 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3300
e04c7350
CW		 3301 /* Wait for the clocks to stabilize before rewriting the regs */
3302 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3303 POSTING_READ(pll->pll_reg);
3304 udelay(150);
e04c7350
CW		 3305
3306 I915_WRITE(pll->fp0_reg, fp);
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3308 pll->on = false;
3309 return pll;
3310}
3311
d4270e57
JB		 3312void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3313{
3314 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3315 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3316 u32 temp;
3317
3318 temp = I915_READ(dslreg);
3319 udelay(500);
3320 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3321 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3322 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3323 }
3324}
3325
f67a559d
JB		 3326static void ironlake_crtc_enable(struct drm_crtc *crtc)
3327{
3328 struct drm_device *dev = crtc->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3331 struct intel_encoder *encoder;
f67a559d
JB		 3332 int pipe = intel_crtc->pipe;
3333 int plane = intel_crtc->plane;
3334 u32 temp;
f67a559d 3335
08a48469
DV		 3336 WARN_ON(!crtc->enabled);
3337
f67a559d
JB		 3338 if (intel_crtc->active)
3339 return;
3340
3341 intel_crtc->active = true;
8664281b
PZ		 3342
3343 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3344 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3345
f67a559d
JB		 3346 intel_update_watermarks(dev);
3347
3348 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3349 temp = I915_READ(PCH_LVDS);
3350 if ((temp & LVDS_PORT_EN) == 0)
3351 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3352 }
3353
f67a559d 3354
5bfe2ac0 3355 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3356 /* Note: FDI PLL enabling _must_ be done before we enable the
3357 * cpu pipes, hence this is separate from all the other fdi/pch
3358 * enabling. */
88cefb6c 3359 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3360 } else {
3361 assert_fdi_tx_disabled(dev_priv, pipe);
3362 assert_fdi_rx_disabled(dev_priv, pipe);
3363 }
f67a559d 3364
bf49ec8c
DV		 3365 for_each_encoder_on_crtc(dev, crtc, encoder)
3366 if (encoder->pre_enable)
3367 encoder->pre_enable(encoder);
f67a559d
JB		 3368
3369 /* Enable panel fitting for LVDS */
3370 if (dev_priv->pch_pf_size &&
547dc041
JN		 3371 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3372 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3373 /* Force use of hard-coded filter coefficients
3374 * as some pre-programmed values are broken,
3375 * e.g. x201.
3376 */
13888d78
PZ		 3377 if (IS_IVYBRIDGE(dev))
3378 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3379 PF_PIPE_SEL_IVB(pipe));
3380 else
3381 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3382 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3383 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3384 }
3385
9c54c0dd
JB		 3386 /*
3387 * On ILK+ LUT must be loaded before the pipe is running but with
3388 * clocks enabled
3389 */
3390 intel_crtc_load_lut(crtc);
3391
5bfe2ac0
DV		 3392 intel_enable_pipe(dev_priv, pipe,
3393 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3394 intel_enable_plane(dev_priv, plane, pipe);
3395
5bfe2ac0 3396 if (intel_crtc->config.has_pch_encoder)
f67a559d 3397 ironlake_pch_enable(crtc);
c98e9dcf 3398
d1ebd816 3399 mutex_lock(&dev->struct_mutex);
bed4a673 3400 intel_update_fbc(dev);
d1ebd816
BW		 3401 mutex_unlock(&dev->struct_mutex);
3402
6b383a7f 3403 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3404
fa5c73b1
DV		 3405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->enable(encoder);
61b77ddd
DV		 3407
3408 if (HAS_PCH_CPT(dev))
3409 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3410
3411 /*
3412 * There seems to be a race in PCH platform hw (at least on some
3413 * outputs) where an enabled pipe still completes any pageflip right
3414 * away (as if the pipe is off) instead of waiting for vblank. As soon
3415 * as the first vblank happend, everything works as expected. Hence just
3416 * wait for one vblank before returning to avoid strange things
3417 * happening.
3418 */
3419 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3420}
3421
4f771f10
PZ		 3422static void haswell_crtc_enable(struct drm_crtc *crtc)
3423{
3424 struct drm_device *dev = crtc->dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3427 struct intel_encoder *encoder;
3428 int pipe = intel_crtc->pipe;
3429 int plane = intel_crtc->plane;
4f771f10
PZ		 3430
3431 WARN_ON(!crtc->enabled);
3432
3433 if (intel_crtc->active)
3434 return;
3435
3436 intel_crtc->active = true;
8664281b
PZ		 3437
3438 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3439 if (intel_crtc->config.has_pch_encoder)
3440 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3441
4f771f10
PZ		 3442 intel_update_watermarks(dev);
3443
5bfe2ac0 3444 if (intel_crtc->config.has_pch_encoder)
04945641 3445 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3446
3447 for_each_encoder_on_crtc(dev, crtc, encoder)
3448 if (encoder->pre_enable)
3449 encoder->pre_enable(encoder);
3450
1f544388 3451 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3452
1f544388 3453 /* Enable panel fitting for eDP */
547dc041
JN		 3454 if (dev_priv->pch_pf_size &&
3455 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3456 /* Force use of hard-coded filter coefficients
3457 * as some pre-programmed values are broken,
3458 * e.g. x201.
3459 */
54075a7d
PZ		 3460 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3461 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3462 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3463 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3464 }
3465
3466 /*
3467 * On ILK+ LUT must be loaded before the pipe is running but with
3468 * clocks enabled
3469 */
3470 intel_crtc_load_lut(crtc);
3471
1f544388 3472 intel_ddi_set_pipe_settings(crtc);
8228c251 3473 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3474
5bfe2ac0
DV		 3475 intel_enable_pipe(dev_priv, pipe,
3476 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3477 intel_enable_plane(dev_priv, plane, pipe);
3478
5bfe2ac0 3479 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3480 lpt_pch_enable(crtc);
4f771f10
PZ		 3481
3482 mutex_lock(&dev->struct_mutex);
3483 intel_update_fbc(dev);
3484 mutex_unlock(&dev->struct_mutex);
3485
3486 intel_crtc_update_cursor(crtc, true);
3487
3488 for_each_encoder_on_crtc(dev, crtc, encoder)
3489 encoder->enable(encoder);
3490
4f771f10
PZ		 3491 /*
3492 * There seems to be a race in PCH platform hw (at least on some
3493 * outputs) where an enabled pipe still completes any pageflip right
3494 * away (as if the pipe is off) instead of waiting for vblank. As soon
3495 * as the first vblank happend, everything works as expected. Hence just
3496 * wait for one vblank before returning to avoid strange things
3497 * happening.
3498 */
3499 intel_wait_for_vblank(dev, intel_crtc->pipe);
3500}
3501
6be4a607
JB		 3502static void ironlake_crtc_disable(struct drm_crtc *crtc)
3503{
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3507 struct intel_encoder *encoder;
6be4a607
JB		 3508 int pipe = intel_crtc->pipe;
3509 int plane = intel_crtc->plane;
5eddb70b 3510 u32 reg, temp;
b52eb4dc 3511
ef9c3aee 3512
f7abfe8b
CW		 3513 if (!intel_crtc->active)
3514 return;
3515
ea9d758d
DV		 3516 for_each_encoder_on_crtc(dev, crtc, encoder)
3517 encoder->disable(encoder);
3518
e6c3a2a6 3519 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3520 drm_vblank_off(dev, pipe);
6b383a7f 3521 intel_crtc_update_cursor(crtc, false);
5eddb70b 3522
b24e7179 3523 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3524
973d04f9
CW		 3525 if (dev_priv->cfb_plane == plane)
3526 intel_disable_fbc(dev);
2c07245f 3527
8664281b 3528 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3529 intel_disable_pipe(dev_priv, pipe);
32f9d658 3530
6be4a607 3531 /* Disable PF */
9db4a9c7
JB		 3532 I915_WRITE(PF_CTL(pipe), 0);
3533 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3534
bf49ec8c
DV		 3535 for_each_encoder_on_crtc(dev, crtc, encoder)
3536 if (encoder->post_disable)
3537 encoder->post_disable(encoder);
2c07245f 3538
0fc932b8 3539 ironlake_fdi_disable(crtc);
249c0e64 3540
b8a4f404 3541 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3542 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3543
6be4a607
JB		 3544 if (HAS_PCH_CPT(dev)) {
3545 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3546 reg = TRANS_DP_CTL(pipe);
3547 temp = I915_READ(reg);
3548 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3549 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3550 I915_WRITE(reg, temp);
6be4a607
JB		 3551
3552 /* disable DPLL_SEL */
3553 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3554 switch (pipe) {
3555 case 0:
d64311ab 3556 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3557 break;
3558 case 1:
6be4a607 3559 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3560 break;
3561 case 2:
4b645f14 3562 /* C shares PLL A or B */
d64311ab 3563 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3564 break;
3565 default:
3566 BUG(); /* wtf */
3567 }
6be4a607 3568 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3569 }
e3421a18 3570
6be4a607 3571 /* disable PCH DPLL */
ee7b9f93 3572 intel_disable_pch_pll(intel_crtc);
8db9d77b 3573
88cefb6c 3574 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3575
f7abfe8b 3576 intel_crtc->active = false;
6b383a7f 3577 intel_update_watermarks(dev);
d1ebd816
BW		 3578
3579 mutex_lock(&dev->struct_mutex);
6b383a7f 3580 intel_update_fbc(dev);
d1ebd816 3581 mutex_unlock(&dev->struct_mutex);
6be4a607 3582}
1b3c7a47 3583
4f771f10 3584static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3585{
4f771f10
PZ		 3586 struct drm_device *dev = crtc->dev;
3587 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3589 struct intel_encoder *encoder;
3590 int pipe = intel_crtc->pipe;
3591 int plane = intel_crtc->plane;
3b117c8f 3592 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3593
4f771f10
PZ		 3594 if (!intel_crtc->active)
3595 return;
3596
3597 for_each_encoder_on_crtc(dev, crtc, encoder)
3598 encoder->disable(encoder);
3599
3600 intel_crtc_wait_for_pending_flips(crtc);
3601 drm_vblank_off(dev, pipe);
3602 intel_crtc_update_cursor(crtc, false);
3603
3604 intel_disable_plane(dev_priv, plane, pipe);
3605
3606 if (dev_priv->cfb_plane == plane)
3607 intel_disable_fbc(dev);
3608
8664281b
PZ		 3609 if (intel_crtc->config.has_pch_encoder)
3610 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3611 intel_disable_pipe(dev_priv, pipe);
3612
ad80a810 3613 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3614
f7708f78
PZ		 3615 /* XXX: Once we have proper panel fitter state tracking implemented with
3616 * hardware state read/check support we should switch to only disable
3617 * the panel fitter when we know it's used. */
3618 if (intel_using_power_well(dev)) {
3619 I915_WRITE(PF_CTL(pipe), 0);
3620 I915_WRITE(PF_WIN_SZ(pipe), 0);
3621 }
4f771f10 3622
1f544388 3623 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3624
3625 for_each_encoder_on_crtc(dev, crtc, encoder)
3626 if (encoder->post_disable)
3627 encoder->post_disable(encoder);
3628
88adfff1 3629 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3630 lpt_disable_pch_transcoder(dev_priv);
8664281b 3631 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3632 intel_ddi_fdi_disable(crtc);
83616634 3633 }
4f771f10
PZ		 3634
3635 intel_crtc->active = false;
3636 intel_update_watermarks(dev);
3637
3638 mutex_lock(&dev->struct_mutex);
3639 intel_update_fbc(dev);
3640 mutex_unlock(&dev->struct_mutex);
3641}
3642
ee7b9f93
JB		 3643static void ironlake_crtc_off(struct drm_crtc *crtc)
3644{
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 intel_put_pch_pll(intel_crtc);
3647}
3648
6441ab5f
PZ		 3649static void haswell_crtc_off(struct drm_crtc *crtc)
3650{
a5c961d1
PZ		 3651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652
3653 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3654 * start using it. */
3b117c8f 3655 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3656
6441ab5f
PZ		 3657 intel_ddi_put_crtc_pll(crtc);
3658}
3659
02e792fb
DV		 3660static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3661{
02e792fb 3662 if (!enable && intel_crtc->overlay) {
23f09ce3 3663 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3664 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3665
23f09ce3 3666 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3667 dev_priv->mm.interruptible = false;
3668 (void) intel_overlay_switch_off(intel_crtc->overlay);
3669 dev_priv->mm.interruptible = true;
23f09ce3 3670 mutex_unlock(&dev->struct_mutex);
02e792fb 3671 }
02e792fb 3672
5dcdbcb0
CW		 3673 /* Let userspace switch the overlay on again. In most cases userspace
3674 * has to recompute where to put it anyway.
3675 */
02e792fb
DV		 3676}
3677
61bc95c1
EE		 3678/**
3679 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3680 * cursor plane briefly if not already running after enabling the display
3681 * plane.
3682 * This workaround avoids occasional blank screens when self refresh is
3683 * enabled.
3684 */
3685static void
3686g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3687{
3688 u32 cntl = I915_READ(CURCNTR(pipe));
3689
3690 if ((cntl & CURSOR_MODE) == 0) {
3691 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3692
3693 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3694 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3695 intel_wait_for_vblank(dev_priv->dev, pipe);
3696 I915_WRITE(CURCNTR(pipe), cntl);
3697 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3698 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3699 }
3700}
3701
89b667f8
JB		 3702static void valleyview_crtc_enable(struct drm_crtc *crtc)
3703{
3704 struct drm_device *dev = crtc->dev;
3705 struct drm_i915_private *dev_priv = dev->dev_private;
3706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3707 struct intel_encoder *encoder;
3708 int pipe = intel_crtc->pipe;
3709 int plane = intel_crtc->plane;
3710
3711 WARN_ON(!crtc->enabled);
3712
3713 if (intel_crtc->active)
3714 return;
3715
3716 intel_crtc->active = true;
3717 intel_update_watermarks(dev);
3718
3719 mutex_lock(&dev_priv->dpio_lock);
3720
3721 for_each_encoder_on_crtc(dev, crtc, encoder)
3722 if (encoder->pre_pll_enable)
3723 encoder->pre_pll_enable(encoder);
3724
3725 intel_enable_pll(dev_priv, pipe);
3726
3727 for_each_encoder_on_crtc(dev, crtc, encoder)
3728 if (encoder->pre_enable)
3729 encoder->pre_enable(encoder);
3730
3731 /* VLV wants encoder enabling _before_ the pipe is up. */
3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->enable(encoder);
3734
3735 intel_enable_pipe(dev_priv, pipe, false);
3736 intel_enable_plane(dev_priv, plane, pipe);
3737
3738 intel_crtc_load_lut(crtc);
3739 intel_update_fbc(dev);
3740
3741 /* Give the overlay scaler a chance to enable if it's on this pipe */
3742 intel_crtc_dpms_overlay(intel_crtc, true);
3743 intel_crtc_update_cursor(crtc, true);
3744
3745 mutex_unlock(&dev_priv->dpio_lock);
3746}
3747
0b8765c6 3748static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3749{
3750 struct drm_device *dev = crtc->dev;
79e53945
JB		 3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3753 struct intel_encoder *encoder;
79e53945 3754 int pipe = intel_crtc->pipe;
80824003 3755 int plane = intel_crtc->plane;
79e53945 3756
08a48469
DV		 3757 WARN_ON(!crtc->enabled);
3758
f7abfe8b
CW		 3759 if (intel_crtc->active)
3760 return;
3761
3762 intel_crtc->active = true;
6b383a7f
CW		 3763 intel_update_watermarks(dev);
3764
63d7bbe9 3765 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3766
3767 for_each_encoder_on_crtc(dev, crtc, encoder)
3768 if (encoder->pre_enable)
3769 encoder->pre_enable(encoder);
3770
040484af 3771 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3772 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3773 if (IS_G4X(dev))
3774 g4x_fixup_plane(dev_priv, pipe);
79e53945 3775
0b8765c6 3776 intel_crtc_load_lut(crtc);
bed4a673 3777 intel_update_fbc(dev);
79e53945 3778
0b8765c6
JB		 3779 /* Give the overlay scaler a chance to enable if it's on this pipe */
3780 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3781 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3782
fa5c73b1
DV		 3783 for_each_encoder_on_crtc(dev, crtc, encoder)
3784 encoder->enable(encoder);
0b8765c6 3785}
79e53945 3786
87476d63
DV		 3787static void i9xx_pfit_disable(struct intel_crtc *crtc)
3788{
3789 struct drm_device *dev = crtc->base.dev;
3790 struct drm_i915_private *dev_priv = dev->dev_private;
3791 enum pipe pipe;
3792 uint32_t pctl = I915_READ(PFIT_CONTROL);
3793
3794 assert_pipe_disabled(dev_priv, crtc->pipe);
3795
3796 if (INTEL_INFO(dev)->gen >= 4)
3797 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3798 else
3799 pipe = PIPE_B;
3800
3801 if (pipe == crtc->pipe) {
3802 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3803 I915_WRITE(PFIT_CONTROL, 0);
3804 }
3805}
3806
0b8765c6
JB		 3807static void i9xx_crtc_disable(struct drm_crtc *crtc)
3808{
3809 struct drm_device *dev = crtc->dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3812 struct intel_encoder *encoder;
0b8765c6
JB		 3813 int pipe = intel_crtc->pipe;
3814 int plane = intel_crtc->plane;
ef9c3aee 3815
f7abfe8b
CW		 3816 if (!intel_crtc->active)
3817 return;
3818
ea9d758d
DV		 3819 for_each_encoder_on_crtc(dev, crtc, encoder)
3820 encoder->disable(encoder);
3821
0b8765c6 3822 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3823 intel_crtc_wait_for_pending_flips(crtc);
3824 drm_vblank_off(dev, pipe);
0b8765c6 3825 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3826 intel_crtc_update_cursor(crtc, false);
0b8765c6 3827
973d04f9
CW		 3828 if (dev_priv->cfb_plane == plane)
3829 intel_disable_fbc(dev);
79e53945 3830
b24e7179 3831 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3832 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3833
87476d63 3834 i9xx_pfit_disable(intel_crtc);
24a1f16d 3835
89b667f8
JB		 3836 for_each_encoder_on_crtc(dev, crtc, encoder)
3837 if (encoder->post_disable)
3838 encoder->post_disable(encoder);
3839
63d7bbe9 3840 intel_disable_pll(dev_priv, pipe);
0b8765c6 3841
f7abfe8b 3842 intel_crtc->active = false;
6b383a7f
CW		 3843 intel_update_fbc(dev);
3844 intel_update_watermarks(dev);
0b8765c6
JB		 3845}
3846
ee7b9f93
JB		 3847static void i9xx_crtc_off(struct drm_crtc *crtc)
3848{
3849}
3850
976f8a20
DV		 3851static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3852 bool enabled)
2c07245f
ZW		 3853{
3854 struct drm_device *dev = crtc->dev;
3855 struct drm_i915_master_private *master_priv;
3856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3857 int pipe = intel_crtc->pipe;
79e53945
JB		 3858
3859 if (!dev->primary->master)
3860 return;
3861
3862 master_priv = dev->primary->master->driver_priv;
3863 if (!master_priv->sarea_priv)
3864 return;
3865
79e53945
JB		 3866 switch (pipe) {
3867 case 0:
3868 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3869 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3870 break;
3871 case 1:
3872 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3873 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3874 break;
3875 default:
9db4a9c7 3876 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3877 break;
3878 }
79e53945
JB		 3879}
3880
976f8a20
DV		 3881/**
3882 * Sets the power management mode of the pipe and plane.
3883 */
3884void intel_crtc_update_dpms(struct drm_crtc *crtc)
3885{
3886 struct drm_device *dev = crtc->dev;
3887 struct drm_i915_private *dev_priv = dev->dev_private;
3888 struct intel_encoder *intel_encoder;
3889 bool enable = false;
3890
3891 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3892 enable |= intel_encoder->connectors_active;
3893
3894 if (enable)
3895 dev_priv->display.crtc_enable(crtc);
3896 else
3897 dev_priv->display.crtc_disable(crtc);
3898
3899 intel_crtc_update_sarea(crtc, enable);
3900}
3901
cdd59983
CW		 3902static void intel_crtc_disable(struct drm_crtc *crtc)
3903{
cdd59983 3904 struct drm_device *dev = crtc->dev;
976f8a20 3905 struct drm_connector *connector;
ee7b9f93 3906 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3908
976f8a20
DV		 3909 /* crtc should still be enabled when we disable it. */
3910 WARN_ON(!crtc->enabled);
3911
7b9f35a6 3912 intel_crtc->eld_vld = false;
976f8a20
DV		 3913 dev_priv->display.crtc_disable(crtc);
3914 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3915 dev_priv->display.off(crtc);
3916
931872fc
CW		 3917 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3918 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3919
3920 if (crtc->fb) {
3921 mutex_lock(&dev->struct_mutex);
1690e1eb 3922 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3923 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3924 crtc->fb = NULL;
3925 }
3926
3927 /* Update computed state. */
3928 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3929 if (!connector->encoder || !connector->encoder->crtc)
3930 continue;
3931
3932 if (connector->encoder->crtc != crtc)
3933 continue;
3934
3935 connector->dpms = DRM_MODE_DPMS_OFF;
3936 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3937 }
3938}
3939
a261b246 3940void intel_modeset_disable(struct drm_device *dev)
79e53945 3941{
a261b246
DV		 3942 struct drm_crtc *crtc;
3943
3944 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3945 if (crtc->enabled)
3946 intel_crtc_disable(crtc);
3947 }
79e53945
JB		 3948}
3949
ea5b213a 3950void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3951{
4ef69c7a 3952 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3953
ea5b213a
CW		 3954 drm_encoder_cleanup(encoder);
3955 kfree(intel_encoder);
7e7d76c3
JB		 3956}
3957
5ab432ef
DV		 3958/* Simple dpms helper for encodres with just one connector, no cloning and only
3959 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3960 * state of the entire output pipe. */
3961void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3962{
5ab432ef
DV		 3963 if (mode == DRM_MODE_DPMS_ON) {
3964 encoder->connectors_active = true;
3965
b2cabb0e 3966 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3967 } else {
3968 encoder->connectors_active = false;
3969
b2cabb0e 3970 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3971 }
79e53945
JB		 3972}
3973
0a91ca29
DV		 3974/* Cross check the actual hw state with our own modeset state tracking (and it's
3975 * internal consistency). */
b980514c 3976static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3977{
0a91ca29
DV		 3978 if (connector->get_hw_state(connector)) {
3979 struct intel_encoder *encoder = connector->encoder;
3980 struct drm_crtc *crtc;
3981 bool encoder_enabled;
3982 enum pipe pipe;
3983
3984 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3985 connector->base.base.id,
3986 drm_get_connector_name(&connector->base));
3987
3988 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3989 "wrong connector dpms state\n");
3990 WARN(connector->base.encoder != &encoder->base,
3991 "active connector not linked to encoder\n");
3992 WARN(!encoder->connectors_active,
3993 "encoder->connectors_active not set\n");
3994
3995 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3996 WARN(!encoder_enabled, "encoder not enabled\n");
3997 if (WARN_ON(!encoder->base.crtc))
3998 return;
3999
4000 crtc = encoder->base.crtc;
4001
4002 WARN(!crtc->enabled, "crtc not enabled\n");
4003 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4004 WARN(pipe != to_intel_crtc(crtc)->pipe,
4005 "encoder active on the wrong pipe\n");
4006 }
79e53945
JB		 4007}
4008
5ab432ef
DV		 4009/* Even simpler default implementation, if there's really no special case to
4010 * consider. */
4011void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4012{
5ab432ef 4013 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4014
5ab432ef
DV		 4015 /* All the simple cases only support two dpms states. */
4016 if (mode != DRM_MODE_DPMS_ON)
4017 mode = DRM_MODE_DPMS_OFF;
d4270e57 4018
5ab432ef
DV		 4019 if (mode == connector->dpms)
4020 return;
4021
4022 connector->dpms = mode;
4023
4024 /* Only need to change hw state when actually enabled */
4025 if (encoder->base.crtc)
4026 intel_encoder_dpms(encoder, mode);
4027 else
8af6cf88 4028 WARN_ON(encoder->connectors_active != false);
0a91ca29 4029
b980514c 4030 intel_modeset_check_state(connector->dev);
79e53945
JB		 4031}
4032
f0947c37
DV		 4033/* Simple connector->get_hw_state implementation for encoders that support only
4034 * one connector and no cloning and hence the encoder state determines the state
4035 * of the connector. */
4036bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4037{
24929352 4038 enum pipe pipe = 0;
f0947c37 4039 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4040
f0947c37 4041 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4042}
4043
b8cecdf5
DV		 4044static bool intel_crtc_compute_config(struct drm_crtc *crtc,
4045 struct intel_crtc_config *pipe_config)
79e53945 4046{
2c07245f 4047 struct drm_device *dev = crtc->dev;
b8cecdf5 4048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4049
bad720ff 4050 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4051 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4052 if (pipe_config->requested_mode.clock * 3
4053 > IRONLAKE_FDI_FREQ * 4)
2377b741 4054 return false;
2c07245f 4055 }
89749350 4056
f9bef081
DV		 4057 /* All interlaced capable intel hw wants timings in frames. Note though
4058 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4059 * timings, so we need to be careful not to clobber these.*/
7ae89233 4060 if (!pipe_config->timings_set)
f9bef081 4061 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4062
44f46b42
CW		 4063 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4064 * with a hsync front porch of 0.
4065 */
4066 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4067 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4068 return false;
4069
bd080ee5 4070 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4071 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4072 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4073 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4074 * for lvds. */
4075 pipe_config->pipe_bpp = 8*3;
4076 }
4077
79e53945
JB		 4078 return true;
4079}
4080
25eb05fc
JB		 4081static int valleyview_get_display_clock_speed(struct drm_device *dev)
4082{
4083 return 400000; /* FIXME */
4084}
4085
e70236a8
JB		 4086static int i945_get_display_clock_speed(struct drm_device *dev)
4087{
4088 return 400000;
4089}
79e53945 4090
e70236a8 4091static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4092{
e70236a8
JB		 4093 return 333000;
4094}
79e53945 4095
e70236a8
JB		 4096static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4097{
4098 return 200000;
4099}
79e53945 4100
e70236a8
JB		 4101static int i915gm_get_display_clock_speed(struct drm_device *dev)
4102{
4103 u16 gcfgc = 0;
79e53945 4104
e70236a8
JB		 4105 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4106
4107 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4108 return 133000;
4109 else {
4110 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4111 case GC_DISPLAY_CLOCK_333_MHZ:
4112 return 333000;
4113 default:
4114 case GC_DISPLAY_CLOCK_190_200_MHZ:
4115 return 190000;
79e53945 4116 }
e70236a8
JB		 4117 }
4118}
4119
4120static int i865_get_display_clock_speed(struct drm_device *dev)
4121{
4122 return 266000;
4123}
4124
4125static int i855_get_display_clock_speed(struct drm_device *dev)
4126{
4127 u16 hpllcc = 0;
4128 /* Assume that the hardware is in the high speed state. This
4129 * should be the default.
4130 */
4131 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4132 case GC_CLOCK_133_200:
4133 case GC_CLOCK_100_200:
4134 return 200000;
4135 case GC_CLOCK_166_250:
4136 return 250000;
4137 case GC_CLOCK_100_133:
79e53945 4138 return 133000;
e70236a8 4139 }
79e53945 4140
e70236a8
JB		 4141 /* Shouldn't happen */
4142 return 0;
4143}
79e53945 4144
e70236a8
JB		 4145static int i830_get_display_clock_speed(struct drm_device *dev)
4146{
4147 return 133000;
79e53945
JB		 4148}
4149
2c07245f 4150static void
e69d0bc1 4151intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4152{
4153 while (*num > 0xffffff || *den > 0xffffff) {
4154 *num >>= 1;
4155 *den >>= 1;
4156 }
4157}
4158
e69d0bc1
DV		 4159void
4160intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4161 int pixel_clock, int link_clock,
4162 struct intel_link_m_n *m_n)
2c07245f 4163{
e69d0bc1 4164 m_n->tu = 64;
22ed1113
CW		 4165 m_n->gmch_m = bits_per_pixel * pixel_clock;
4166 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4167 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4168 m_n->link_m = pixel_clock;
4169 m_n->link_n = link_clock;
e69d0bc1 4170 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4171}
4172
a7615030
CW		 4173static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4174{
72bbe58c
KP		 4175 if (i915_panel_use_ssc >= 0)
4176 return i915_panel_use_ssc != 0;
4177 return dev_priv->lvds_use_ssc
435793df 4178 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4179}
4180
a0c4da24
JB		 4181static int vlv_get_refclk(struct drm_crtc *crtc)
4182{
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 int refclk = 27000; /* for DP & HDMI */
4186
4187 return 100000; /* only one validated so far */
4188
4189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4190 refclk = 96000;
4191 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4192 if (intel_panel_use_ssc(dev_priv))
4193 refclk = 100000;
4194 else
4195 refclk = 96000;
4196 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4197 refclk = 100000;
4198 }
4199
4200 return refclk;
4201}
4202
c65d77d8
JB		 4203static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4204{
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 int refclk;
4208
a0c4da24
JB		 4209 if (IS_VALLEYVIEW(dev)) {
4210 refclk = vlv_get_refclk(crtc);
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4212 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4213 refclk = dev_priv->lvds_ssc_freq * 1000;
4214 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4215 refclk / 1000);
4216 } else if (!IS_GEN2(dev)) {
4217 refclk = 96000;
4218 } else {
4219 refclk = 48000;
4220 }
4221
4222 return refclk;
4223}
4224
f47709a9 4225static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4226{
f47709a9
DV		 4227 unsigned dotclock = crtc->config.adjusted_mode.clock;
4228 struct dpll *clock = &crtc->config.dpll;
4229
c65d77d8
JB		 4230 /* SDVO TV has fixed PLL values depend on its clock range,
4231 this mirrors vbios setting. */
f47709a9 4232 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4233 clock->p1 = 2;
4234 clock->p2 = 10;
4235 clock->n = 3;
4236 clock->m1 = 16;
4237 clock->m2 = 8;
f47709a9 4238 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4239 clock->p1 = 1;
4240 clock->p2 = 10;
4241 clock->n = 6;
4242 clock->m1 = 12;
4243 clock->m2 = 8;
4244 }
f47709a9
DV		 4245
4246 crtc->config.clock_set = true;
c65d77d8
JB		 4247}
4248
7429e9d4
DV		 4249static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4250{
4251 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4252}
4253
4254static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4255{
4256 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4257}
4258
f47709a9 4259static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4260 intel_clock_t *reduced_clock)
4261{
f47709a9 4262 struct drm_device *dev = crtc->base.dev;
a7516a05 4263 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4264 int pipe = crtc->pipe;
a7516a05
JB		 4265 u32 fp, fp2 = 0;
4266
4267 if (IS_PINEVIEW(dev)) {
7429e9d4 4268 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4269 if (reduced_clock)
7429e9d4 4270 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4271 } else {
7429e9d4 4272 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4273 if (reduced_clock)
7429e9d4 4274 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4275 }
4276
4277 I915_WRITE(FP0(pipe), fp);
4278
f47709a9
DV		 4279 crtc->lowfreq_avail = false;
4280 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4281 reduced_clock && i915_powersave) {
4282 I915_WRITE(FP1(pipe), fp2);
f47709a9 4283 crtc->lowfreq_avail = true;
a7516a05
JB		 4284 } else {
4285 I915_WRITE(FP1(pipe), fp);
4286 }
4287}
4288
89b667f8
JB		 4289static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4290{
4291 u32 reg_val;
4292
4293 /*
4294 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4295 * and set it to a reasonable value instead.
4296 */
4297 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4298 reg_val &= 0xffffff00;
4299 reg_val |= 0x00000030;
4300 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4303 reg_val &= 0x8cffffff;
4304 reg_val = 0x8c000000;
4305 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306
4307 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4308 reg_val &= 0xffffff00;
4309 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4310
4311 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4312 reg_val &= 0x00ffffff;
4313 reg_val |= 0xb0000000;
4314 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4315}
4316
03afc4a2
DV		 4317static void intel_dp_set_m_n(struct intel_crtc *crtc)
4318{
4319 if (crtc->config.has_pch_encoder)
4320 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4321 else
4322 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4323}
4324
f47709a9 4325static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4326{
f47709a9 4327 struct drm_device *dev = crtc->base.dev;
a0c4da24 4328 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4329 struct drm_display_mode *adjusted_mode =
4330 &crtc->config.adjusted_mode;
4331 struct intel_encoder *encoder;
f47709a9 4332 int pipe = crtc->pipe;
89b667f8 4333 u32 dpll, mdiv;
a0c4da24 4334 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8
JB		 4335 bool is_hdmi;
4336 u32 coreclk, reg_val, temp;
a0c4da24 4337
09153000
DV		 4338 mutex_lock(&dev_priv->dpio_lock);
4339
89b667f8 4340 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4341
f47709a9
DV		 4342 bestn = crtc->config.dpll.n;
4343 bestm1 = crtc->config.dpll.m1;
4344 bestm2 = crtc->config.dpll.m2;
4345 bestp1 = crtc->config.dpll.p1;
4346 bestp2 = crtc->config.dpll.p2;
a0c4da24 4347
89b667f8
JB		 4348 /* See eDP HDMI DPIO driver vbios notes doc */
4349
4350 /* PLL B needs special handling */
4351 if (pipe)
4352 vlv_pllb_recal_opamp(dev_priv);
4353
4354 /* Set up Tx target for periodic Rcomp update */
4355 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4356
4357 /* Disable target IRef on PLL */
4358 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4359 reg_val &= 0x00ffffff;
4360 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4361
4362 /* Disable fast lock */
4363 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4364
4365 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4366 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4367 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4368 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4369 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4370 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4371 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4372 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4373 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4374 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4375
89b667f8
JB		 4376 mdiv |= DPIO_ENABLE_CALIBRATION;
4377 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4378
89b667f8
JB		 4379 /* Set HBR and RBR LPF coefficients */
4380 if (adjusted_mode->clock == 162000 ||
4381 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4382 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4383 0x005f0021);
4384 else
4385 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4386 0x00d0000f);
4387
4388 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4389 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4390 /* Use SSC source */
4391 if (!pipe)
4392 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4393 0x0df40000);
4394 else
4395 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4396 0x0df70000);
4397 } else { /* HDMI or VGA */
4398 /* Use bend source */
4399 if (!pipe)
4400 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4401 0x0df70000);
4402 else
4403 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4404 0x0df40000);
4405 }
a0c4da24 4406
89b667f8
JB		 4407 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4408 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4409 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4410 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4411 coreclk |= 0x01000000;
4412 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4413
89b667f8 4414 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4415
89b667f8
JB		 4416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4417 if (encoder->pre_pll_enable)
4418 encoder->pre_pll_enable(encoder);
2a8f64ca 4419
89b667f8
JB		 4420 /* Enable DPIO clock input */
4421 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4422 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4423 if (pipe)
4424 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4425
89b667f8 4426 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4427 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4428 POSTING_READ(DPLL(pipe));
4429 udelay(150);
a0c4da24 4430
89b667f8
JB		 4431 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4432 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4433
4434 if (is_hdmi) {
6cc5f341 4435 temp = 0;
f47709a9
DV		 4436 if (crtc->config.pixel_multiplier > 1) {
4437 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4438 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4439 }
a0c4da24 4440
89b667f8
JB		 4441 I915_WRITE(DPLL_MD(pipe), temp);
4442 POSTING_READ(DPLL_MD(pipe));
2a8f64ca 4443 }
f47709a9 4444
89b667f8
JB		 4445 if (crtc->config.has_dp_encoder)
4446 intel_dp_set_m_n(crtc);
09153000
DV		 4447
4448 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4449}
4450
f47709a9
DV		 4451static void i9xx_update_pll(struct intel_crtc *crtc,
4452 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4453 int num_connectors)
4454{
f47709a9 4455 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4456 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4457 struct intel_encoder *encoder;
f47709a9 4458 int pipe = crtc->pipe;
eb1cbe48
DV		 4459 u32 dpll;
4460 bool is_sdvo;
f47709a9 4461 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4462
f47709a9 4463 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4464
f47709a9
DV		 4465 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4466 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4467
4468 dpll = DPLL_VGA_MODE_DIS;
4469
f47709a9 4470 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4471 dpll |= DPLLB_MODE_LVDS;
4472 else
4473 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4474
eb1cbe48 4475 if (is_sdvo) {
f47709a9 4476 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4477 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4478 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4479 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4480 }
4481 dpll |= DPLL_DVO_HIGH_SPEED;
4482 }
f47709a9 4483 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4484 dpll |= DPLL_DVO_HIGH_SPEED;
4485
4486 /* compute bitmask from p1 value */
4487 if (IS_PINEVIEW(dev))
4488 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4489 else {
4490 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4491 if (IS_G4X(dev) && reduced_clock)
4492 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4493 }
4494 switch (clock->p2) {
4495 case 5:
4496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4497 break;
4498 case 7:
4499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4500 break;
4501 case 10:
4502 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4503 break;
4504 case 14:
4505 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4506 break;
4507 }
4508 if (INTEL_INFO(dev)->gen >= 4)
4509 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4510
f47709a9 4511 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4512 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4513 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4514 /* XXX: just matching BIOS for now */
4515 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4516 dpll |= 3;
f47709a9 4517 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4518 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4519 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4520 else
4521 dpll |= PLL_REF_INPUT_DREFCLK;
4522
4523 dpll |= DPLL_VCO_ENABLE;
4524 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4525 POSTING_READ(DPLL(pipe));
4526 udelay(150);
4527
f47709a9 4528 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4529 if (encoder->pre_pll_enable)
4530 encoder->pre_pll_enable(encoder);
eb1cbe48 4531
f47709a9
DV		 4532 if (crtc->config.has_dp_encoder)
4533 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4534
4535 I915_WRITE(DPLL(pipe), dpll);
4536
4537 /* Wait for the clocks to stabilize. */
4538 POSTING_READ(DPLL(pipe));
4539 udelay(150);
4540
4541 if (INTEL_INFO(dev)->gen >= 4) {
4542 u32 temp = 0;
4543 if (is_sdvo) {
6cc5f341 4544 temp = 0;
f47709a9
DV		 4545 if (crtc->config.pixel_multiplier > 1) {
4546 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4547 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4548 }
eb1cbe48
DV		 4549 }
4550 I915_WRITE(DPLL_MD(pipe), temp);
4551 } else {
4552 /* The pixel multiplier can only be updated once the
4553 * DPLL is enabled and the clocks are stable.
4554 *
4555 * So write it again.
4556 */
4557 I915_WRITE(DPLL(pipe), dpll);
4558 }
4559}
4560
f47709a9 4561static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4562 struct drm_display_mode *adjusted_mode,
f47709a9 4563 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4564 int num_connectors)
4565{
f47709a9 4566 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4567 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4568 struct intel_encoder *encoder;
f47709a9 4569 int pipe = crtc->pipe;
eb1cbe48 4570 u32 dpll;
f47709a9 4571 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4572
f47709a9 4573 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4574
eb1cbe48
DV		 4575 dpll = DPLL_VGA_MODE_DIS;
4576
f47709a9 4577 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4578 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4579 } else {
4580 if (clock->p1 == 2)
4581 dpll |= PLL_P1_DIVIDE_BY_TWO;
4582 else
4583 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4584 if (clock->p2 == 4)
4585 dpll |= PLL_P2_DIVIDE_BY_4;
4586 }
4587
f47709a9 4588 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4591 else
4592 dpll |= PLL_REF_INPUT_DREFCLK;
4593
4594 dpll |= DPLL_VCO_ENABLE;
4595 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4596 POSTING_READ(DPLL(pipe));
4597 udelay(150);
4598
f47709a9 4599 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4600 if (encoder->pre_pll_enable)
4601 encoder->pre_pll_enable(encoder);
eb1cbe48 4602
5b5896e4
DV		 4603 I915_WRITE(DPLL(pipe), dpll);
4604
4605 /* Wait for the clocks to stabilize. */
4606 POSTING_READ(DPLL(pipe));
4607 udelay(150);
4608
eb1cbe48
DV		 4609 /* The pixel multiplier can only be updated once the
4610 * DPLL is enabled and the clocks are stable.
4611 *
4612 * So write it again.
4613 */
4614 I915_WRITE(DPLL(pipe), dpll);
4615}
4616
b0e77b9c
PZ		 4617static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4618 struct drm_display_mode *mode,
4619 struct drm_display_mode *adjusted_mode)
4620{
4621 struct drm_device *dev = intel_crtc->base.dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4624 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4625 uint32_t vsyncshift;
4626
4627 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4628 /* the chip adds 2 halflines automatically */
4629 adjusted_mode->crtc_vtotal -= 1;
4630 adjusted_mode->crtc_vblank_end -= 1;
4631 vsyncshift = adjusted_mode->crtc_hsync_start
4632 - adjusted_mode->crtc_htotal / 2;
4633 } else {
4634 vsyncshift = 0;
4635 }
4636
4637 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4638 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4639
fe2b8f9d 4640 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4641 (adjusted_mode->crtc_hdisplay - 1) |
4642 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4643 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4644 (adjusted_mode->crtc_hblank_start - 1) |
4645 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4646 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4647 (adjusted_mode->crtc_hsync_start - 1) |
4648 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4649
fe2b8f9d 4650 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4651 (adjusted_mode->crtc_vdisplay - 1) |
4652 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4653 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4654 (adjusted_mode->crtc_vblank_start - 1) |
4655 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4656 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4657 (adjusted_mode->crtc_vsync_start - 1) |
4658 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4659
b5e508d4
PZ		 4660 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4661 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4662 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4663 * bits. */
4664 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4665 (pipe == PIPE_B || pipe == PIPE_C))
4666 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4667
b0e77b9c
PZ		 4668 /* pipesrc controls the size that is scaled from, which should
4669 * always be the user's requested size.
4670 */
4671 I915_WRITE(PIPESRC(pipe),
4672 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4673}
4674
84b046f3
DV		 4675static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4676{
4677 struct drm_device *dev = intel_crtc->base.dev;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 uint32_t pipeconf;
4680
4681 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4682
4683 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4684 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4685 * core speed.
4686 *
4687 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4688 * pipe == 0 check?
4689 */
4690 if (intel_crtc->config.requested_mode.clock >
4691 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4692 pipeconf |= PIPECONF_DOUBLE_WIDE;
4693 else
4694 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4695 }
4696
4697 /* default to 8bpc */
4698 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4699 if (intel_crtc->config.has_dp_encoder) {
4700 if (intel_crtc->config.dither) {
4701 pipeconf |= PIPECONF_6BPC |
4702 PIPECONF_DITHER_EN |
4703 PIPECONF_DITHER_TYPE_SP;
4704 }
4705 }
4706
4707 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4708 INTEL_OUTPUT_EDP)) {
4709 if (intel_crtc->config.dither) {
4710 pipeconf |= PIPECONF_6BPC |
4711 PIPECONF_ENABLE |
4712 I965_PIPECONF_ACTIVE;
4713 }
4714 }
4715
4716 if (HAS_PIPE_CXSR(dev)) {
4717 if (intel_crtc->lowfreq_avail) {
4718 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4719 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4720 } else {
4721 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4722 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4723 }
4724 }
4725
4726 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4727 if (!IS_GEN2(dev) &&
4728 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4729 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4730 else
4731 pipeconf |= PIPECONF_PROGRESSIVE;
4732
9c8e09b7
VS		 4733 if (IS_VALLEYVIEW(dev)) {
4734 if (intel_crtc->config.limited_color_range)
4735 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4736 else
4737 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4738 }
4739
84b046f3
DV		 4740 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4741 POSTING_READ(PIPECONF(intel_crtc->pipe));
4742}
4743
f564048e 4744static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4745 int x, int y,
94352cf9 4746 struct drm_framebuffer *fb)
79e53945
JB		 4747{
4748 struct drm_device *dev = crtc->dev;
4749 struct drm_i915_private *dev_priv = dev->dev_private;
4750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4751 struct drm_display_mode *adjusted_mode =
4752 &intel_crtc->config.adjusted_mode;
4753 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4754 int pipe = intel_crtc->pipe;
80824003 4755 int plane = intel_crtc->plane;
c751ce4f 4756 int refclk, num_connectors = 0;
652c393a 4757 intel_clock_t clock, reduced_clock;
84b046f3 4758 u32 dspcntr;
eb1cbe48 4759 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4760 bool is_lvds = false, is_tv = false;
5eddb70b 4761 struct intel_encoder *encoder;
d4906093 4762 const intel_limit_t *limit;
5c3b82e2 4763 int ret;
79e53945 4764
6c2b7c12 4765 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4766 switch (encoder->type) {
79e53945
JB		 4767 case INTEL_OUTPUT_LVDS:
4768 is_lvds = true;
4769 break;
4770 case INTEL_OUTPUT_SDVO:
7d57382e 4771 case INTEL_OUTPUT_HDMI:
79e53945 4772 is_sdvo = true;
5eddb70b 4773 if (encoder->needs_tv_clock)
e2f0ba97 4774 is_tv = true;
79e53945 4775 break;
79e53945
JB		 4776 case INTEL_OUTPUT_TVOUT:
4777 is_tv = true;
4778 break;
79e53945 4779 }
43565a06 4780
c751ce4f 4781 num_connectors++;
79e53945
JB		 4782 }
4783
c65d77d8 4784 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4785
d4906093
ML		 4786 /*
4787 * Returns a set of divisors for the desired target clock with the given
4788 * refclk, or FALSE. The returned values represent the clock equation:
4789 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4790 */
1b894b59 4791 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4792 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4793 &clock);
79e53945
JB		 4794 if (!ok) {
4795 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4796 return -EINVAL;
79e53945
JB		 4797 }
4798
cda4b7d3 4799 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4800 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4801
ddc9003c 4802 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4803 /*
4804 * Ensure we match the reduced clock's P to the target clock.
4805 * If the clocks don't match, we can't switch the display clock
4806 * by using the FP0/FP1. In such case we will disable the LVDS
4807 * downclock feature.
4808 */
ddc9003c 4809 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4810 dev_priv->lvds_downclock,
4811 refclk,
cec2f356 4812 &clock,
5eddb70b 4813 &reduced_clock);
7026d4ac 4814 }
f47709a9
DV		 4815 /* Compat-code for transition, will disappear. */
4816 if (!intel_crtc->config.clock_set) {
4817 intel_crtc->config.dpll.n = clock.n;
4818 intel_crtc->config.dpll.m1 = clock.m1;
4819 intel_crtc->config.dpll.m2 = clock.m2;
4820 intel_crtc->config.dpll.p1 = clock.p1;
4821 intel_crtc->config.dpll.p2 = clock.p2;
4822 }
7026d4ac 4823
c65d77d8 4824 if (is_sdvo && is_tv)
f47709a9 4825 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4826
eb1cbe48 4827 if (IS_GEN2(dev))
f47709a9 4828 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4829 has_reduced_clock ? &reduced_clock : NULL,
4830 num_connectors);
a0c4da24 4831 else if (IS_VALLEYVIEW(dev))
f47709a9 4832 vlv_update_pll(intel_crtc);
79e53945 4833 else
f47709a9 4834 i9xx_update_pll(intel_crtc,
eb1cbe48 4835 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4836 num_connectors);
79e53945 4837
79e53945
JB		 4838 /* Set up the display plane register */
4839 dspcntr = DISPPLANE_GAMMA_ENABLE;
4840
da6ecc5d
JB		 4841 if (!IS_VALLEYVIEW(dev)) {
4842 if (pipe == 0)
4843 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4844 else
4845 dspcntr |= DISPPLANE_SEL_PIPE_B;
4846 }
79e53945 4847
2582a850 4848 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4849 drm_mode_debug_printmodeline(mode);
4850
b0e77b9c 4851 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4852
4853 /* pipesrc and dspsize control the size that is scaled from,
4854 * which should always be the user's requested size.
79e53945 4855 */
929c77fb
EA		 4856 I915_WRITE(DSPSIZE(plane),
4857 ((mode->vdisplay - 1) << 16) |
4858 (mode->hdisplay - 1));
4859 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4860
84b046f3
DV		 4861 i9xx_set_pipeconf(intel_crtc);
4862
f564048e
EA		 4863 I915_WRITE(DSPCNTR(plane), dspcntr);
4864 POSTING_READ(DSPCNTR(plane));
4865
94352cf9 4866 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4867
4868 intel_update_watermarks(dev);
4869
f564048e
EA		 4870 return ret;
4871}
4872
0e8ffe1b
DV		 4873static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4874 struct intel_crtc_config *pipe_config)
4875{
4876 struct drm_device *dev = crtc->base.dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 uint32_t tmp;
4879
4880 tmp = I915_READ(PIPECONF(crtc->pipe));
4881 if (!(tmp & PIPECONF_ENABLE))
4882 return false;
4883
4884 return true;
4885}
4886
dde86e2d 4887static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4888{
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4891 struct intel_encoder *encoder;
74cfd7ac 4892 u32 val, final;
13d83a67 4893 bool has_lvds = false;
199e5d79
KP		 4894 bool has_cpu_edp = false;
4895 bool has_pch_edp = false;
4896 bool has_panel = false;
99eb6a01
KP		 4897 bool has_ck505 = false;
4898 bool can_ssc = false;
13d83a67
JB		 4899
4900 /* We need to take the global config into account */
199e5d79
KP		 4901 list_for_each_entry(encoder, &mode_config->encoder_list,
4902 base.head) {
4903 switch (encoder->type) {
4904 case INTEL_OUTPUT_LVDS:
4905 has_panel = true;
4906 has_lvds = true;
4907 break;
4908 case INTEL_OUTPUT_EDP:
4909 has_panel = true;
4910 if (intel_encoder_is_pch_edp(&encoder->base))
4911 has_pch_edp = true;
4912 else
4913 has_cpu_edp = true;
4914 break;
13d83a67
JB		 4915 }
4916 }
4917
99eb6a01
KP		 4918 if (HAS_PCH_IBX(dev)) {
4919 has_ck505 = dev_priv->display_clock_mode;
4920 can_ssc = has_ck505;
4921 } else {
4922 has_ck505 = false;
4923 can_ssc = true;
4924 }
4925
4926 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4927 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4928 has_ck505);
13d83a67
JB		 4929
4930 /* Ironlake: try to setup display ref clock before DPLL
4931 * enabling. This is only under driver's control after
4932 * PCH B stepping, previous chipset stepping should be
4933 * ignoring this setting.
4934 */
74cfd7ac
CW		 4935 val = I915_READ(PCH_DREF_CONTROL);
4936
4937 /* As we must carefully and slowly disable/enable each source in turn,
4938 * compute the final state we want first and check if we need to
4939 * make any changes at all.
4940 */
4941 final = val;
4942 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4943 if (has_ck505)
4944 final |= DREF_NONSPREAD_CK505_ENABLE;
4945 else
4946 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4947
4948 final &= ~DREF_SSC_SOURCE_MASK;
4949 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4950 final &= ~DREF_SSC1_ENABLE;
4951
4952 if (has_panel) {
4953 final |= DREF_SSC_SOURCE_ENABLE;
4954
4955 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4956 final |= DREF_SSC1_ENABLE;
4957
4958 if (has_cpu_edp) {
4959 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4960 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4961 else
4962 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4963 } else
4964 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4965 } else {
4966 final |= DREF_SSC_SOURCE_DISABLE;
4967 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4968 }
4969
4970 if (final == val)
4971 return;
4972
13d83a67 4973 /* Always enable nonspread source */
74cfd7ac 4974 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4975
99eb6a01 4976 if (has_ck505)
74cfd7ac 4977 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4978 else
74cfd7ac 4979 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4980
199e5d79 4981 if (has_panel) {
74cfd7ac
CW		 4982 val &= ~DREF_SSC_SOURCE_MASK;
4983 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4984
199e5d79 4985 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4986 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4987 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4988 val |= DREF_SSC1_ENABLE;
e77166b5 4989 } else
74cfd7ac 4990 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4991
4992 /* Get SSC going before enabling the outputs */
74cfd7ac 4993 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4994 POSTING_READ(PCH_DREF_CONTROL);
4995 udelay(200);
4996
74cfd7ac 4997 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4998
4999 /* Enable CPU source on CPU attached eDP */
199e5d79 5000 if (has_cpu_edp) {
99eb6a01 5001 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5002 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5003 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5004 }
13d83a67 5005 else
74cfd7ac 5006 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5007 } else
74cfd7ac 5008 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5009
74cfd7ac 5010 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5011 POSTING_READ(PCH_DREF_CONTROL);
5012 udelay(200);
5013 } else {
5014 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5015
74cfd7ac 5016 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5017
5018 /* Turn off CPU output */
74cfd7ac 5019 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5020
74cfd7ac 5021 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5022 POSTING_READ(PCH_DREF_CONTROL);
5023 udelay(200);
5024
5025 /* Turn off the SSC source */
74cfd7ac
CW		 5026 val &= ~DREF_SSC_SOURCE_MASK;
5027 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5028
5029 /* Turn off SSC1 */
74cfd7ac 5030 val &= ~DREF_SSC1_ENABLE;
199e5d79 5031
74cfd7ac 5032 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5033 POSTING_READ(PCH_DREF_CONTROL);
5034 udelay(200);
5035 }
74cfd7ac
CW		 5036
5037 BUG_ON(val != final);
13d83a67
JB		 5038}
5039
dde86e2d
PZ		 5040/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5041static void lpt_init_pch_refclk(struct drm_device *dev)
5042{
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044 struct drm_mode_config *mode_config = &dev->mode_config;
5045 struct intel_encoder *encoder;
5046 bool has_vga = false;
5047 bool is_sdv = false;
5048 u32 tmp;
5049
5050 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5051 switch (encoder->type) {
5052 case INTEL_OUTPUT_ANALOG:
5053 has_vga = true;
5054 break;
5055 }
5056 }
5057
5058 if (!has_vga)
5059 return;
5060
c00db246
DV		 5061 mutex_lock(&dev_priv->dpio_lock);
5062
dde86e2d
PZ		 5063 /* XXX: Rip out SDV support once Haswell ships for real. */
5064 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5065 is_sdv = true;
5066
5067 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5068 tmp &= ~SBI_SSCCTL_DISABLE;
5069 tmp |= SBI_SSCCTL_PATHALT;
5070 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5071
5072 udelay(24);
5073
5074 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5075 tmp &= ~SBI_SSCCTL_PATHALT;
5076 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5077
5078 if (!is_sdv) {
5079 tmp = I915_READ(SOUTH_CHICKEN2);
5080 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5081 I915_WRITE(SOUTH_CHICKEN2, tmp);
5082
5083 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5084 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5085 DRM_ERROR("FDI mPHY reset assert timeout\n");
5086
5087 tmp = I915_READ(SOUTH_CHICKEN2);
5088 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5089 I915_WRITE(SOUTH_CHICKEN2, tmp);
5090
5091 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5092 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5093 100))
5094 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5095 }
5096
5097 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5098 tmp &= ~(0xFF << 24);
5099 tmp |= (0x12 << 24);
5100 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5101
dde86e2d
PZ		 5102 if (is_sdv) {
5103 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5104 tmp |= 0x7FFF;
5105 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5106 }
5107
5108 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5109 tmp |= (1 << 11);
5110 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5111
5112 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5113 tmp |= (1 << 11);
5114 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5115
5116 if (is_sdv) {
5117 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5118 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5119 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5120
5121 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5122 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5123 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5124
5125 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5126 tmp |= (0x3F << 8);
5127 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5128
5129 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5130 tmp |= (0x3F << 8);
5131 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5132 }
5133
5134 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5135 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5136 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5137
5138 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5139 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5140 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5141
5142 if (!is_sdv) {
5143 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5144 tmp &= ~(7 << 13);
5145 tmp |= (5 << 13);
5146 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5147
5148 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5149 tmp &= ~(7 << 13);
5150 tmp |= (5 << 13);
5151 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5152 }
5153
5154 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5155 tmp &= ~0xFF;
5156 tmp |= 0x1C;
5157 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5158
5159 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5160 tmp &= ~0xFF;
5161 tmp |= 0x1C;
5162 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5163
5164 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5165 tmp &= ~(0xFF << 16);
5166 tmp |= (0x1C << 16);
5167 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5168
5169 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5170 tmp &= ~(0xFF << 16);
5171 tmp |= (0x1C << 16);
5172 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5173
5174 if (!is_sdv) {
5175 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5176 tmp |= (1 << 27);
5177 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5178
5179 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5180 tmp |= (1 << 27);
5181 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5182
5183 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5184 tmp &= ~(0xF << 28);
5185 tmp |= (4 << 28);
5186 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5187
5188 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5189 tmp &= ~(0xF << 28);
5190 tmp |= (4 << 28);
5191 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5192 }
5193
5194 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5195 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5196 tmp |= SBI_DBUFF0_ENABLE;
5197 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5198
5199 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5200}
5201
5202/*
5203 * Initialize reference clocks when the driver loads
5204 */
5205void intel_init_pch_refclk(struct drm_device *dev)
5206{
5207 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5208 ironlake_init_pch_refclk(dev);
5209 else if (HAS_PCH_LPT(dev))
5210 lpt_init_pch_refclk(dev);
5211}
5212
d9d444cb
JB		 5213static int ironlake_get_refclk(struct drm_crtc *crtc)
5214{
5215 struct drm_device *dev = crtc->dev;
5216 struct drm_i915_private *dev_priv = dev->dev_private;
5217 struct intel_encoder *encoder;
d9d444cb
JB		 5218 struct intel_encoder *edp_encoder = NULL;
5219 int num_connectors = 0;
5220 bool is_lvds = false;
5221
6c2b7c12 5222 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5223 switch (encoder->type) {
5224 case INTEL_OUTPUT_LVDS:
5225 is_lvds = true;
5226 break;
5227 case INTEL_OUTPUT_EDP:
5228 edp_encoder = encoder;
5229 break;
5230 }
5231 num_connectors++;
5232 }
5233
5234 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5235 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5236 dev_priv->lvds_ssc_freq);
5237 return dev_priv->lvds_ssc_freq * 1000;
5238 }
5239
5240 return 120000;
5241}
5242
c8203565 5243static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5244 struct drm_display_mode *adjusted_mode,
c8203565 5245 bool dither)
79e53945 5246{
c8203565 5247 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249 int pipe = intel_crtc->pipe;
c8203565
PZ		 5250 uint32_t val;
5251
5252 val = I915_READ(PIPECONF(pipe));
5253
dfd07d72 5254 val &= ~PIPECONF_BPC_MASK;
965e0c48 5255 switch (intel_crtc->config.pipe_bpp) {
c8203565 5256 case 18:
dfd07d72 5257 val |= PIPECONF_6BPC;
c8203565
PZ		 5258 break;
5259 case 24:
dfd07d72 5260 val |= PIPECONF_8BPC;
c8203565
PZ		 5261 break;
5262 case 30:
dfd07d72 5263 val |= PIPECONF_10BPC;
c8203565
PZ		 5264 break;
5265 case 36:
dfd07d72 5266 val |= PIPECONF_12BPC;
c8203565
PZ		 5267 break;
5268 default:
cc769b62
PZ		 5269 /* Case prevented by intel_choose_pipe_bpp_dither. */
5270 BUG();
c8203565
PZ		 5271 }
5272
5273 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5274 if (dither)
5275 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5276
5277 val &= ~PIPECONF_INTERLACE_MASK;
5278 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5279 val |= PIPECONF_INTERLACED_ILK;
5280 else
5281 val |= PIPECONF_PROGRESSIVE;
5282
50f3b016 5283 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5284 val |= PIPECONF_COLOR_RANGE_SELECT;
5285 else
5286 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5287
c8203565
PZ		 5288 I915_WRITE(PIPECONF(pipe), val);
5289 POSTING_READ(PIPECONF(pipe));
5290}
5291
86d3efce
VS		 5292/*
5293 * Set up the pipe CSC unit.
5294 *
5295 * Currently only full range RGB to limited range RGB conversion
5296 * is supported, but eventually this should handle various
5297 * RGB<->YCbCr scenarios as well.
5298 */
50f3b016 5299static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5300{
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304 int pipe = intel_crtc->pipe;
5305 uint16_t coeff = 0x7800; /* 1.0 */
5306
5307 /*
5308 * TODO: Check what kind of values actually come out of the pipe
5309 * with these coeff/postoff values and adjust to get the best
5310 * accuracy. Perhaps we even need to take the bpc value into
5311 * consideration.
5312 */
5313
50f3b016 5314 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5315 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5316
5317 /*
5318 * GY/GU and RY/RU should be the other way around according
5319 * to BSpec, but reality doesn't agree. Just set them up in
5320 * a way that results in the correct picture.
5321 */
5322 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5323 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5324
5325 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5326 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5327
5328 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5329 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5330
5331 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5332 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5333 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5334
5335 if (INTEL_INFO(dev)->gen > 6) {
5336 uint16_t postoff = 0;
5337
50f3b016 5338 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5339 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5340
5341 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5342 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5343 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5344
5345 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5346 } else {
5347 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5348
50f3b016 5349 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5350 mode |= CSC_BLACK_SCREEN_OFFSET;
5351
5352 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5353 }
5354}
5355
ee2b0b38
PZ		 5356static void haswell_set_pipeconf(struct drm_crtc *crtc,
5357 struct drm_display_mode *adjusted_mode,
5358 bool dither)
5359{
5360 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5362 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5363 uint32_t val;
5364
702e7a56 5365 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5366
5367 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5368 if (dither)
5369 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5370
5371 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5372 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5373 val |= PIPECONF_INTERLACED_ILK;
5374 else
5375 val |= PIPECONF_PROGRESSIVE;
5376
702e7a56
PZ		 5377 I915_WRITE(PIPECONF(cpu_transcoder), val);
5378 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5379}
5380
6591c6e4
PZ		 5381static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5382 struct drm_display_mode *adjusted_mode,
5383 intel_clock_t *clock,
5384 bool *has_reduced_clock,
5385 intel_clock_t *reduced_clock)
5386{
5387 struct drm_device *dev = crtc->dev;
5388 struct drm_i915_private *dev_priv = dev->dev_private;
5389 struct intel_encoder *intel_encoder;
5390 int refclk;
d4906093 5391 const intel_limit_t *limit;
6591c6e4 5392 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5393
6591c6e4
PZ		 5394 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5395 switch (intel_encoder->type) {
79e53945
JB		 5396 case INTEL_OUTPUT_LVDS:
5397 is_lvds = true;
5398 break;
5399 case INTEL_OUTPUT_SDVO:
7d57382e 5400 case INTEL_OUTPUT_HDMI:
79e53945 5401 is_sdvo = true;
6591c6e4 5402 if (intel_encoder->needs_tv_clock)
e2f0ba97 5403 is_tv = true;
79e53945 5404 break;
79e53945
JB		 5405 case INTEL_OUTPUT_TVOUT:
5406 is_tv = true;
5407 break;
79e53945
JB		 5408 }
5409 }
5410
d9d444cb 5411 refclk = ironlake_get_refclk(crtc);
79e53945 5412
d4906093
ML		 5413 /*
5414 * Returns a set of divisors for the desired target clock with the given
5415 * refclk, or FALSE. The returned values represent the clock equation:
5416 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5417 */
1b894b59 5418 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5419 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5420 clock);
5421 if (!ret)
5422 return false;
cda4b7d3 5423
ddc9003c 5424 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5425 /*
5426 * Ensure we match the reduced clock's P to the target clock.
5427 * If the clocks don't match, we can't switch the display clock
5428 * by using the FP0/FP1. In such case we will disable the LVDS
5429 * downclock feature.
5430 */
6591c6e4
PZ		 5431 *has_reduced_clock = limit->find_pll(limit, crtc,
5432 dev_priv->lvds_downclock,
5433 refclk,
5434 clock,
5435 reduced_clock);
652c393a 5436 }
61e9653f
DV		 5437
5438 if (is_sdvo && is_tv)
f47709a9 5439 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5440
5441 return true;
5442}
5443
01a415fd
DV		 5444static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5445{
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 uint32_t temp;
5448
5449 temp = I915_READ(SOUTH_CHICKEN1);
5450 if (temp & FDI_BC_BIFURCATION_SELECT)
5451 return;
5452
5453 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5454 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5455
5456 temp |= FDI_BC_BIFURCATION_SELECT;
5457 DRM_DEBUG_KMS("enabling fdi C rx\n");
5458 I915_WRITE(SOUTH_CHICKEN1, temp);
5459 POSTING_READ(SOUTH_CHICKEN1);
5460}
5461
5462static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5463{
5464 struct drm_device *dev = intel_crtc->base.dev;
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 struct intel_crtc *pipe_B_crtc =
5467 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5468
84f44ce7
VS		 5469 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5470 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd 5471 if (intel_crtc->fdi_lanes > 4) {
84f44ce7
VS		 5472 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5473 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5474 /* Clamp lanes to avoid programming the hw with bogus values. */
5475 intel_crtc->fdi_lanes = 4;
5476
5477 return false;
5478 }
5479
7eb552ae 5480 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5481 return true;
5482
5483 switch (intel_crtc->pipe) {
5484 case PIPE_A:
5485 return true;
5486 case PIPE_B:
5487 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5488 intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5489 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5490 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5491 /* Clamp lanes to avoid programming the hw with bogus values. */
5492 intel_crtc->fdi_lanes = 2;
5493
5494 return false;
5495 }
5496
5497 if (intel_crtc->fdi_lanes > 2)
5498 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5499 else
5500 cpt_enable_fdi_bc_bifurcation(dev);
5501
5502 return true;
5503 case PIPE_C:
5504 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5505 if (intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5506 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5507 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5508 /* Clamp lanes to avoid programming the hw with bogus values. */
5509 intel_crtc->fdi_lanes = 2;
5510
5511 return false;
5512 }
5513 } else {
5514 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5515 return false;
5516 }
5517
5518 cpt_enable_fdi_bc_bifurcation(dev);
5519
5520 return true;
5521 default:
5522 BUG();
5523 }
5524}
5525
d4b1931c
PZ		 5526int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5527{
5528 /*
5529 * Account for spread spectrum to avoid
5530 * oversubscribing the link. Max center spread
5531 * is 2.5%; use 5% for safety's sake.
5532 */
5533 u32 bps = target_clock * bpp * 21 / 20;
5534 return bps / (link_bw * 8) + 1;
5535}
5536
6cf86a5e
DV		 5537void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5538 struct intel_link_m_n *m_n)
79e53945 5539{
6cf86a5e
DV		 5540 struct drm_device *dev = crtc->base.dev;
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542 int pipe = crtc->pipe;
5543
5544 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5545 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5546 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5547 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5548}
5549
5550void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5551 struct intel_link_m_n *m_n)
5552{
5553 struct drm_device *dev = crtc->base.dev;
79e53945 5554 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5555 int pipe = crtc->pipe;
3b117c8f 5556 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5557
5558 if (INTEL_INFO(dev)->gen >= 5) {
5559 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5560 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5561 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5562 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5563 } else {
5564 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5565 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5566 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5567 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5568 }
5569}
5570
5571static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5572{
5573 struct drm_device *dev = crtc->dev;
79e53945 5574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5575 struct drm_display_mode *adjusted_mode =
5576 &intel_crtc->config.adjusted_mode;
e69d0bc1 5577 struct intel_link_m_n m_n = {0};
6cc5f341 5578 int target_clock, lane, link_bw;
61e9653f 5579
6cf86a5e
DV		 5580 /* FDI is a binary signal running at ~2.7GHz, encoding
5581 * each output octet as 10 bits. The actual frequency
5582 * is stored as a divider into a 100MHz clock, and the
5583 * mode pixel clock is stored in units of 1KHz.
5584 * Hence the bw of each lane in terms of the mode signal
5585 * is:
5586 */
5587 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5588
df92b1e6
DV		 5589 if (intel_crtc->config.pixel_target_clock)
5590 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5591 else
5592 target_clock = adjusted_mode->clock;
5593
6cf86a5e
DV		 5594 lane = ironlake_get_lanes_required(target_clock, link_bw,
5595 intel_crtc->config.pipe_bpp);
2c07245f 5596
8febb297
EA		 5597 intel_crtc->fdi_lanes = lane;
5598
6cc5f341
DV		 5599 if (intel_crtc->config.pixel_multiplier > 1)
5600 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5601 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5602 link_bw, &m_n);
8febb297 5603
6cf86a5e 5604 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5605}
5606
7429e9d4
DV		 5607static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5608{
5609 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5610}
5611
de13a2e3 5612static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5613 u32 *fp,
9a7c7890 5614 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5615{
de13a2e3 5616 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5617 struct drm_device *dev = crtc->dev;
5618 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5619 struct intel_encoder *intel_encoder;
5620 uint32_t dpll;
6cc5f341 5621 int factor, num_connectors = 0;
de13a2e3 5622 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5623
de13a2e3
PZ		 5624 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5625 switch (intel_encoder->type) {
79e53945
JB		 5626 case INTEL_OUTPUT_LVDS:
5627 is_lvds = true;
5628 break;
5629 case INTEL_OUTPUT_SDVO:
7d57382e 5630 case INTEL_OUTPUT_HDMI:
79e53945 5631 is_sdvo = true;
de13a2e3 5632 if (intel_encoder->needs_tv_clock)
e2f0ba97 5633 is_tv = true;
79e53945 5634 break;
79e53945
JB		 5635 case INTEL_OUTPUT_TVOUT:
5636 is_tv = true;
5637 break;
79e53945 5638 }
43565a06 5639
c751ce4f 5640 num_connectors++;
79e53945 5641 }
79e53945 5642
c1858123 5643 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5644 factor = 21;
5645 if (is_lvds) {
5646 if ((intel_panel_use_ssc(dev_priv) &&
5647 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5648 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5649 factor = 25;
5650 } else if (is_sdvo && is_tv)
5651 factor = 20;
c1858123 5652
7429e9d4 5653 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5654 *fp |= FP_CB_TUNE;
2c07245f 5655
9a7c7890
DV		 5656 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5657 *fp2 |= FP_CB_TUNE;
5658
5eddb70b 5659 dpll = 0;
2c07245f 5660
a07d6787
EA		 5661 if (is_lvds)
5662 dpll |= DPLLB_MODE_LVDS;
5663 else
5664 dpll |= DPLLB_MODE_DAC_SERIAL;
5665 if (is_sdvo) {
6cc5f341
DV		 5666 if (intel_crtc->config.pixel_multiplier > 1) {
5667 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5668 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5669 }
a07d6787
EA		 5670 dpll |= DPLL_DVO_HIGH_SPEED;
5671 }
8b47047b
DV		 5672 if (intel_crtc->config.has_dp_encoder &&
5673 intel_crtc->config.has_pch_encoder)
a07d6787 5674 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5675
a07d6787 5676 /* compute bitmask from p1 value */
7429e9d4 5677 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5678 /* also FPA1 */
7429e9d4 5679 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5680
7429e9d4 5681 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5682 case 5:
5683 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5684 break;
5685 case 7:
5686 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5687 break;
5688 case 10:
5689 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5690 break;
5691 case 14:
5692 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5693 break;
79e53945
JB		 5694 }
5695
43565a06
KH		 5696 if (is_sdvo && is_tv)
5697 dpll |= PLL_REF_INPUT_TVCLKINBC;
5698 else if (is_tv)
79e53945 5699 /* XXX: just matching BIOS for now */
43565a06 5700 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5701 dpll |= 3;
a7615030 5702 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5703 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5704 else
5705 dpll |= PLL_REF_INPUT_DREFCLK;
5706
de13a2e3
PZ		 5707 return dpll;
5708}
5709
5710static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5711 int x, int y,
5712 struct drm_framebuffer *fb)
5713{
5714 struct drm_device *dev = crtc->dev;
5715 struct drm_i915_private *dev_priv = dev->dev_private;
5716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5717 struct drm_display_mode *adjusted_mode =
5718 &intel_crtc->config.adjusted_mode;
5719 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5720 int pipe = intel_crtc->pipe;
5721 int plane = intel_crtc->plane;
5722 int num_connectors = 0;
5723 intel_clock_t clock, reduced_clock;
cbbab5bd 5724 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5725 bool ok, has_reduced_clock = false;
8b47047b 5726 bool is_lvds = false;
de13a2e3 5727 struct intel_encoder *encoder;
de13a2e3 5728 int ret;
01a415fd 5729 bool dither, fdi_config_ok;
de13a2e3
PZ		 5730
5731 for_each_encoder_on_crtc(dev, crtc, encoder) {
5732 switch (encoder->type) {
5733 case INTEL_OUTPUT_LVDS:
5734 is_lvds = true;
5735 break;
de13a2e3
PZ		 5736 }
5737
5738 num_connectors++;
a07d6787 5739 }
79e53945 5740
5dc5298b
PZ		 5741 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5742 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5743
3b117c8f 5744 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5745
de13a2e3
PZ		 5746 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5747 &has_reduced_clock, &reduced_clock);
5748 if (!ok) {
5749 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5750 return -EINVAL;
79e53945 5751 }
f47709a9
DV		 5752 /* Compat-code for transition, will disappear. */
5753 if (!intel_crtc->config.clock_set) {
5754 intel_crtc->config.dpll.n = clock.n;
5755 intel_crtc->config.dpll.m1 = clock.m1;
5756 intel_crtc->config.dpll.m2 = clock.m2;
5757 intel_crtc->config.dpll.p1 = clock.p1;
5758 intel_crtc->config.dpll.p2 = clock.p2;
5759 }
79e53945 5760
de13a2e3
PZ		 5761 /* Ensure that the cursor is valid for the new mode before changing... */
5762 intel_crtc_update_cursor(crtc, true);
5763
5764 /* determine panel color depth */
4e53c2e0 5765 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5766 if (is_lvds && dev_priv->lvds_dither)
5767 dither = true;
5768
84f44ce7 5769 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5770 drm_mode_debug_printmodeline(mode);
5771
5dc5298b 5772 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5773 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5774 struct intel_pch_pll *pll;
4b645f14 5775
7429e9d4 5776 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5777 if (has_reduced_clock)
7429e9d4 5778 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5779
7429e9d4 5780 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5781 &fp, &reduced_clock,
5782 has_reduced_clock ? &fp2 : NULL);
5783
ee7b9f93
JB		 5784 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5785 if (pll == NULL) {
84f44ce7
VS		 5786 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5787 pipe_name(pipe));
4b645f14
JB		 5788 return -EINVAL;
5789 }
ee7b9f93
JB		 5790 } else
5791 intel_put_pch_pll(intel_crtc);
79e53945 5792
03afc4a2
DV		 5793 if (intel_crtc->config.has_dp_encoder)
5794 intel_dp_set_m_n(intel_crtc);
79e53945 5795
dafd226c
DV		 5796 for_each_encoder_on_crtc(dev, crtc, encoder)
5797 if (encoder->pre_pll_enable)
5798 encoder->pre_pll_enable(encoder);
79e53945 5799
ee7b9f93
JB		 5800 if (intel_crtc->pch_pll) {
5801 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5802
32f9d658 5803 /* Wait for the clocks to stabilize. */
ee7b9f93 5804 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5805 udelay(150);
5806
8febb297
EA		 5807 /* The pixel multiplier can only be updated once the
5808 * DPLL is enabled and the clocks are stable.
5809 *
5810 * So write it again.
5811 */
ee7b9f93 5812 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5813 }
79e53945 5814
5eddb70b 5815 intel_crtc->lowfreq_avail = false;
ee7b9f93 5816 if (intel_crtc->pch_pll) {
4b645f14 5817 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5818 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5819 intel_crtc->lowfreq_avail = true;
4b645f14 5820 } else {
ee7b9f93 5821 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5822 }
5823 }
5824
b0e77b9c 5825 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5826
01a415fd
DV		 5827 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5828 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5829 intel_crtc->fdi_lanes = 0;
5830 if (intel_crtc->config.has_pch_encoder)
5831 ironlake_fdi_set_m_n(crtc);
2c07245f 5832
01a415fd 5833 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5834
c8203565 5835 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5836
a1f9e77e
PZ		 5837 /* Set up the display plane register */
5838 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5839 POSTING_READ(DSPCNTR(plane));
79e53945 5840
94352cf9 5841 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5842
5843 intel_update_watermarks(dev);
5844
1f8eeabf
ED		 5845 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5846
01a415fd 5847 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5848}
5849
0e8ffe1b
DV		 5850static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5851 struct intel_crtc_config *pipe_config)
5852{
5853 struct drm_device *dev = crtc->base.dev;
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 uint32_t tmp;
5856
5857 tmp = I915_READ(PIPECONF(crtc->pipe));
5858 if (!(tmp & PIPECONF_ENABLE))
5859 return false;
5860
88adfff1
DV		 5861 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5862 pipe_config->has_pch_encoder = true;
5863
0e8ffe1b
DV		 5864 return true;
5865}
5866
d6dd9eb1
DV		 5867static void haswell_modeset_global_resources(struct drm_device *dev)
5868{
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 bool enable = false;
5871 struct intel_crtc *crtc;
5872 struct intel_encoder *encoder;
5873
5874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5875 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5876 enable = true;
5877 /* XXX: Should check for edp transcoder here, but thanks to init
5878 * sequence that's not yet available. Just in case desktop eDP
5879 * on PORT D is possible on haswell, too. */
5880 }
5881
5882 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5883 base.head) {
5884 if (encoder->type != INTEL_OUTPUT_EDP &&
5885 encoder->connectors_active)
5886 enable = true;
5887 }
5888
5889 /* Even the eDP panel fitter is outside the always-on well. */
5890 if (dev_priv->pch_pf_size)
5891 enable = true;
5892
5893 intel_set_power_well(dev, enable);
5894}
5895
09b4ddf9 5896static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5897 int x, int y,
5898 struct drm_framebuffer *fb)
5899{
5900 struct drm_device *dev = crtc->dev;
5901 struct drm_i915_private *dev_priv = dev->dev_private;
5902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5903 struct drm_display_mode *adjusted_mode =
5904 &intel_crtc->config.adjusted_mode;
5905 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5906 int pipe = intel_crtc->pipe;
5907 int plane = intel_crtc->plane;
5908 int num_connectors = 0;
8b47047b 5909 bool is_cpu_edp = false;
09b4ddf9 5910 struct intel_encoder *encoder;
09b4ddf9
PZ		 5911 int ret;
5912 bool dither;
5913
5914 for_each_encoder_on_crtc(dev, crtc, encoder) {
5915 switch (encoder->type) {
09b4ddf9 5916 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5917 if (!intel_encoder_is_pch_edp(&encoder->base))
5918 is_cpu_edp = true;
5919 break;
5920 }
5921
5922 num_connectors++;
5923 }
5924
bba2181c 5925 if (is_cpu_edp)
3b117c8f 5926 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5927 else
3b117c8f 5928 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5929
5dc5298b
PZ		 5930 /* We are not sure yet this won't happen. */
5931 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5932 INTEL_PCH_TYPE(dev));
5933
5934 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5935 num_connectors, pipe_name(pipe));
5936
3b117c8f 5937 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5938 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5939
5940 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5941
6441ab5f
PZ		 5942 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5943 return -EINVAL;
5944
09b4ddf9
PZ		 5945 /* Ensure that the cursor is valid for the new mode before changing... */
5946 intel_crtc_update_cursor(crtc, true);
5947
5948 /* determine panel color depth */
4e53c2e0 5949 dither = intel_crtc->config.dither;
09b4ddf9 5950
84f44ce7 5951 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5952 drm_mode_debug_printmodeline(mode);
5953
03afc4a2
DV		 5954 if (intel_crtc->config.has_dp_encoder)
5955 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5956
5957 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5958
5959 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5960
6cf86a5e
DV		 5961 if (intel_crtc->config.has_pch_encoder)
5962 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5963
ee2b0b38 5964 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5965
50f3b016 5966 intel_set_pipe_csc(crtc);
86d3efce 5967
09b4ddf9 5968 /* Set up the display plane register */
86d3efce 5969 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5970 POSTING_READ(DSPCNTR(plane));
5971
5972 ret = intel_pipe_set_base(crtc, x, y, fb);
5973
5974 intel_update_watermarks(dev);
5975
5976 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5977
1f803ee5 5978 return ret;
79e53945
JB		 5979}
5980
0e8ffe1b
DV		 5981static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5982 struct intel_crtc_config *pipe_config)
5983{
5984 struct drm_device *dev = crtc->base.dev;
5985 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5986 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5987 uint32_t tmp;
5988
2bfce950
PZ		 5989 if (!intel_using_power_well(dev_priv->dev) &&
5990 cpu_transcoder != TRANSCODER_EDP)
5991 return false;
5992
5993 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5994 if (!(tmp & PIPECONF_ENABLE))
5995 return false;
5996
88adfff1 5997 /*
f196e6be 5998 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5999 * DDI E. So just check whether this pipe is wired to DDI E and whether
6000 * the PCH transcoder is on.
6001 */
f196e6be 6002 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1
DV		 6003 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6004 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
6005 pipe_config->has_pch_encoder = true;
6006
0e8ffe1b
DV		 6007 return true;
6008}
6009
f564048e 6010static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6011 int x, int y,
94352cf9 6012 struct drm_framebuffer *fb)
f564048e
EA		 6013{
6014 struct drm_device *dev = crtc->dev;
6015 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6016 struct drm_encoder_helper_funcs *encoder_funcs;
6017 struct intel_encoder *encoder;
0b701d27 6018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6019 struct drm_display_mode *adjusted_mode =
6020 &intel_crtc->config.adjusted_mode;
6021 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6022 int pipe = intel_crtc->pipe;
f564048e
EA		 6023 int ret;
6024
0b701d27 6025 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6026
b8cecdf5
DV		 6027 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6028
79e53945 6029 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6030
9256aa19
DV		 6031 if (ret != 0)
6032 return ret;
6033
6034 for_each_encoder_on_crtc(dev, crtc, encoder) {
6035 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6036 encoder->base.base.id,
6037 drm_get_encoder_name(&encoder->base),
6038 mode->base.id, mode->name);
6cc5f341
DV		 6039 if (encoder->mode_set) {
6040 encoder->mode_set(encoder);
6041 } else {
6042 encoder_funcs = encoder->base.helper_private;
6043 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6044 }
9256aa19
DV		 6045 }
6046
6047 return 0;
79e53945
JB		 6048}
6049
3a9627f4
WF		 6050static bool intel_eld_uptodate(struct drm_connector *connector,
6051 int reg_eldv, uint32_t bits_eldv,
6052 int reg_elda, uint32_t bits_elda,
6053 int reg_edid)
6054{
6055 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6056 uint8_t *eld = connector->eld;
6057 uint32_t i;
6058
6059 i = I915_READ(reg_eldv);
6060 i &= bits_eldv;
6061
6062 if (!eld[0])
6063 return !i;
6064
6065 if (!i)
6066 return false;
6067
6068 i = I915_READ(reg_elda);
6069 i &= ~bits_elda;
6070 I915_WRITE(reg_elda, i);
6071
6072 for (i = 0; i < eld[2]; i++)
6073 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6074 return false;
6075
6076 return true;
6077}
6078
e0dac65e
WF		 6079static void g4x_write_eld(struct drm_connector *connector,
6080 struct drm_crtc *crtc)
6081{
6082 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6083 uint8_t *eld = connector->eld;
6084 uint32_t eldv;
6085 uint32_t len;
6086 uint32_t i;
6087
6088 i = I915_READ(G4X_AUD_VID_DID);
6089
6090 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6091 eldv = G4X_ELDV_DEVCL_DEVBLC;
6092 else
6093 eldv = G4X_ELDV_DEVCTG;
6094
3a9627f4
WF		 6095 if (intel_eld_uptodate(connector,
6096 G4X_AUD_CNTL_ST, eldv,
6097 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6098 G4X_HDMIW_HDMIEDID))
6099 return;
6100
e0dac65e
WF		 6101 i = I915_READ(G4X_AUD_CNTL_ST);
6102 i &= ~(eldv | G4X_ELD_ADDR);
6103 len = (i >> 9) & 0x1f; /* ELD buffer size */
6104 I915_WRITE(G4X_AUD_CNTL_ST, i);
6105
6106 if (!eld[0])
6107 return;
6108
6109 len = min_t(uint8_t, eld[2], len);
6110 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6111 for (i = 0; i < len; i++)
6112 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6113
6114 i = I915_READ(G4X_AUD_CNTL_ST);
6115 i |= eldv;
6116 I915_WRITE(G4X_AUD_CNTL_ST, i);
6117}
6118
83358c85
WX		 6119static void haswell_write_eld(struct drm_connector *connector,
6120 struct drm_crtc *crtc)
6121{
6122 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6123 uint8_t *eld = connector->eld;
6124 struct drm_device *dev = crtc->dev;
7b9f35a6 6125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6126 uint32_t eldv;
6127 uint32_t i;
6128 int len;
6129 int pipe = to_intel_crtc(crtc)->pipe;
6130 int tmp;
6131
6132 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6133 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6134 int aud_config = HSW_AUD_CFG(pipe);
6135 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6136
6137
6138 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6139
6140 /* Audio output enable */
6141 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6142 tmp = I915_READ(aud_cntrl_st2);
6143 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6144 I915_WRITE(aud_cntrl_st2, tmp);
6145
6146 /* Wait for 1 vertical blank */
6147 intel_wait_for_vblank(dev, pipe);
6148
6149 /* Set ELD valid state */
6150 tmp = I915_READ(aud_cntrl_st2);
6151 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6152 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6153 I915_WRITE(aud_cntrl_st2, tmp);
6154 tmp = I915_READ(aud_cntrl_st2);
6155 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6156
6157 /* Enable HDMI mode */
6158 tmp = I915_READ(aud_config);
6159 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6160 /* clear N_programing_enable and N_value_index */
6161 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6162 I915_WRITE(aud_config, tmp);
6163
6164 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6165
6166 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6167 intel_crtc->eld_vld = true;
83358c85
WX		 6168
6169 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6170 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6171 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6172 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6173 } else
6174 I915_WRITE(aud_config, 0);
6175
6176 if (intel_eld_uptodate(connector,
6177 aud_cntrl_st2, eldv,
6178 aud_cntl_st, IBX_ELD_ADDRESS,
6179 hdmiw_hdmiedid))
6180 return;
6181
6182 i = I915_READ(aud_cntrl_st2);
6183 i &= ~eldv;
6184 I915_WRITE(aud_cntrl_st2, i);
6185
6186 if (!eld[0])
6187 return;
6188
6189 i = I915_READ(aud_cntl_st);
6190 i &= ~IBX_ELD_ADDRESS;
6191 I915_WRITE(aud_cntl_st, i);
6192 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6193 DRM_DEBUG_DRIVER("port num:%d\n", i);
6194
6195 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6196 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6197 for (i = 0; i < len; i++)
6198 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6199
6200 i = I915_READ(aud_cntrl_st2);
6201 i |= eldv;
6202 I915_WRITE(aud_cntrl_st2, i);
6203
6204}
6205
e0dac65e
WF		 6206static void ironlake_write_eld(struct drm_connector *connector,
6207 struct drm_crtc *crtc)
6208{
6209 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6210 uint8_t *eld = connector->eld;
6211 uint32_t eldv;
6212 uint32_t i;
6213 int len;
6214 int hdmiw_hdmiedid;
b6daa025 6215 int aud_config;
e0dac65e
WF		 6216 int aud_cntl_st;
6217 int aud_cntrl_st2;
9b138a83 6218 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6219
b3f33cbf 6220 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6221 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6222 aud_config = IBX_AUD_CFG(pipe);
6223 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6224 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6225 } else {
9b138a83
WX		 6226 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6227 aud_config = CPT_AUD_CFG(pipe);
6228 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6229 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6230 }
6231
9b138a83 6232 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6233
6234 i = I915_READ(aud_cntl_st);
9b138a83 6235 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6236 if (!i) {
6237 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6238 /* operate blindly on all ports */
1202b4c6
WF		 6239 eldv = IBX_ELD_VALIDB;
6240 eldv |= IBX_ELD_VALIDB << 4;
6241 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6242 } else {
2582a850 6243 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6244 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6245 }
6246
3a9627f4
WF		 6247 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6248 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6249 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6250 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6251 } else
6252 I915_WRITE(aud_config, 0);
e0dac65e 6253
3a9627f4
WF		 6254 if (intel_eld_uptodate(connector,
6255 aud_cntrl_st2, eldv,
6256 aud_cntl_st, IBX_ELD_ADDRESS,
6257 hdmiw_hdmiedid))
6258 return;
6259
e0dac65e
WF		 6260 i = I915_READ(aud_cntrl_st2);
6261 i &= ~eldv;
6262 I915_WRITE(aud_cntrl_st2, i);
6263
6264 if (!eld[0])
6265 return;
6266
e0dac65e 6267 i = I915_READ(aud_cntl_st);
1202b4c6 6268 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6269 I915_WRITE(aud_cntl_st, i);
6270
6271 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6272 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6273 for (i = 0; i < len; i++)
6274 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6275
6276 i = I915_READ(aud_cntrl_st2);
6277 i |= eldv;
6278 I915_WRITE(aud_cntrl_st2, i);
6279}
6280
6281void intel_write_eld(struct drm_encoder *encoder,
6282 struct drm_display_mode *mode)
6283{
6284 struct drm_crtc *crtc = encoder->crtc;
6285 struct drm_connector *connector;
6286 struct drm_device *dev = encoder->dev;
6287 struct drm_i915_private *dev_priv = dev->dev_private;
6288
6289 connector = drm_select_eld(encoder, mode);
6290 if (!connector)
6291 return;
6292
6293 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6294 connector->base.id,
6295 drm_get_connector_name(connector),
6296 connector->encoder->base.id,
6297 drm_get_encoder_name(connector->encoder));
6298
6299 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6300
6301 if (dev_priv->display.write_eld)
6302 dev_priv->display.write_eld(connector, crtc);
6303}
6304
79e53945
JB		 6305/** Loads the palette/gamma unit for the CRTC with the prepared values */
6306void intel_crtc_load_lut(struct drm_crtc *crtc)
6307{
6308 struct drm_device *dev = crtc->dev;
6309 struct drm_i915_private *dev_priv = dev->dev_private;
6310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6311 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6312 int i;
6313
6314 /* The clocks have to be on to load the palette. */
aed3f09d 6315 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6316 return;
6317
f2b115e6 6318 /* use legacy palette for Ironlake */
bad720ff 6319 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6320 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6321
79e53945
JB		 6322 for (i = 0; i < 256; i++) {
6323 I915_WRITE(palreg + 4 * i,
6324 (intel_crtc->lut_r[i] << 16) |
6325 (intel_crtc->lut_g[i] << 8) |
6326 intel_crtc->lut_b[i]);
6327 }
6328}
6329
560b85bb
CW		 6330static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6331{
6332 struct drm_device *dev = crtc->dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335 bool visible = base != 0;
6336 u32 cntl;
6337
6338 if (intel_crtc->cursor_visible == visible)
6339 return;
6340
9db4a9c7 6341 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6342 if (visible) {
6343 /* On these chipsets we can only modify the base whilst
6344 * the cursor is disabled.
6345 */
9db4a9c7 6346 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6347
6348 cntl &= ~(CURSOR_FORMAT_MASK);
6349 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6350 cntl |= CURSOR_ENABLE |
6351 CURSOR_GAMMA_ENABLE |
6352 CURSOR_FORMAT_ARGB;
6353 } else
6354 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6355 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6356
6357 intel_crtc->cursor_visible = visible;
6358}
6359
6360static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6361{
6362 struct drm_device *dev = crtc->dev;
6363 struct drm_i915_private *dev_priv = dev->dev_private;
6364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6365 int pipe = intel_crtc->pipe;
6366 bool visible = base != 0;
6367
6368 if (intel_crtc->cursor_visible != visible) {
548f245b 6369 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6370 if (base) {
6371 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6372 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6373 cntl |= pipe << 28; /* Connect to correct pipe */
6374 } else {
6375 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6376 cntl |= CURSOR_MODE_DISABLE;
6377 }
9db4a9c7 6378 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6379
6380 intel_crtc->cursor_visible = visible;
6381 }
6382 /* and commit changes on next vblank */
9db4a9c7 6383 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6384}
6385
65a21cd6
JB		 6386static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6387{
6388 struct drm_device *dev = crtc->dev;
6389 struct drm_i915_private *dev_priv = dev->dev_private;
6390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6391 int pipe = intel_crtc->pipe;
6392 bool visible = base != 0;
6393
6394 if (intel_crtc->cursor_visible != visible) {
6395 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6396 if (base) {
6397 cntl &= ~CURSOR_MODE;
6398 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6399 } else {
6400 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6401 cntl |= CURSOR_MODE_DISABLE;
6402 }
86d3efce
VS		 6403 if (IS_HASWELL(dev))
6404 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6405 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6406
6407 intel_crtc->cursor_visible = visible;
6408 }
6409 /* and commit changes on next vblank */
6410 I915_WRITE(CURBASE_IVB(pipe), base);
6411}
6412
cda4b7d3 6413/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6414static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6415 bool on)
cda4b7d3
CW		 6416{
6417 struct drm_device *dev = crtc->dev;
6418 struct drm_i915_private *dev_priv = dev->dev_private;
6419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420 int pipe = intel_crtc->pipe;
6421 int x = intel_crtc->cursor_x;
6422 int y = intel_crtc->cursor_y;
560b85bb 6423 u32 base, pos;
cda4b7d3
CW		 6424 bool visible;
6425
6426 pos = 0;
6427
6b383a7f 6428 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6429 base = intel_crtc->cursor_addr;
6430 if (x > (int) crtc->fb->width)
6431 base = 0;
6432
6433 if (y > (int) crtc->fb->height)
6434 base = 0;
6435 } else
6436 base = 0;
6437
6438 if (x < 0) {
6439 if (x + intel_crtc->cursor_width < 0)
6440 base = 0;
6441
6442 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6443 x = -x;
6444 }
6445 pos |= x << CURSOR_X_SHIFT;
6446
6447 if (y < 0) {
6448 if (y + intel_crtc->cursor_height < 0)
6449 base = 0;
6450
6451 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6452 y = -y;
6453 }
6454 pos |= y << CURSOR_Y_SHIFT;
6455
6456 visible = base != 0;
560b85bb 6457 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6458 return;
6459
0cd83aa9 6460 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6461 I915_WRITE(CURPOS_IVB(pipe), pos);
6462 ivb_update_cursor(crtc, base);
6463 } else {
6464 I915_WRITE(CURPOS(pipe), pos);
6465 if (IS_845G(dev) || IS_I865G(dev))
6466 i845_update_cursor(crtc, base);
6467 else
6468 i9xx_update_cursor(crtc, base);
6469 }
cda4b7d3
CW		 6470}
6471
79e53945 6472static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6473 struct drm_file *file,
79e53945
JB		 6474 uint32_t handle,
6475 uint32_t width, uint32_t height)
6476{
6477 struct drm_device *dev = crtc->dev;
6478 struct drm_i915_private *dev_priv = dev->dev_private;
6479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6480 struct drm_i915_gem_object *obj;
cda4b7d3 6481 uint32_t addr;
3f8bc370 6482 int ret;
79e53945 6483
79e53945
JB		 6484 /* if we want to turn off the cursor ignore width and height */
6485 if (!handle) {
28c97730 6486 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6487 addr = 0;
05394f39 6488 obj = NULL;
5004417d 6489 mutex_lock(&dev->struct_mutex);
3f8bc370 6490 goto finish;
79e53945
JB		 6491 }
6492
6493 /* Currently we only support 64x64 cursors */
6494 if (width != 64 || height != 64) {
6495 DRM_ERROR("we currently only support 64x64 cursors\n");
6496 return -EINVAL;
6497 }
6498
05394f39 6499 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6500 if (&obj->base == NULL)
79e53945
JB		 6501 return -ENOENT;
6502
05394f39 6503 if (obj->base.size < width * height * 4) {
79e53945 6504 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6505 ret = -ENOMEM;
6506 goto fail;
79e53945
JB		 6507 }
6508
71acb5eb 6509 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6510 mutex_lock(&dev->struct_mutex);
b295d1b6 6511 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6512 unsigned alignment;
6513
d9e86c0e
CW		 6514 if (obj->tiling_mode) {
6515 DRM_ERROR("cursor cannot be tiled\n");
6516 ret = -EINVAL;
6517 goto fail_locked;
6518 }
6519
693db184
CW		 6520 /* Note that the w/a also requires 2 PTE of padding following
6521 * the bo. We currently fill all unused PTE with the shadow
6522 * page and so we should always have valid PTE following the
6523 * cursor preventing the VT-d warning.
6524 */
6525 alignment = 0;
6526 if (need_vtd_wa(dev))
6527 alignment = 64*1024;
6528
6529 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6530 if (ret) {
6531 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6532 goto fail_locked;
e7b526bb
CW		 6533 }
6534
d9e86c0e
CW		 6535 ret = i915_gem_object_put_fence(obj);
6536 if (ret) {
2da3b9b9 6537 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6538 goto fail_unpin;
6539 }
6540
05394f39 6541 addr = obj->gtt_offset;
71acb5eb 6542 } else {
6eeefaf3 6543 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6544 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6545 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6546 align);
71acb5eb
DA		 6547 if (ret) {
6548 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6549 goto fail_locked;
71acb5eb 6550 }
05394f39 6551 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6552 }
6553
a6c45cf0 6554 if (IS_GEN2(dev))
14b60391
JB		 6555 I915_WRITE(CURSIZE, (height << 12) | width);
6556
3f8bc370 6557 finish:
3f8bc370 6558 if (intel_crtc->cursor_bo) {
b295d1b6 6559 if (dev_priv->info->cursor_needs_physical) {
05394f39 6560 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6561 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6562 } else
6563 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6564 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6565 }
80824003 6566
7f9872e0 6567 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6568
6569 intel_crtc->cursor_addr = addr;
05394f39 6570 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6571 intel_crtc->cursor_width = width;
6572 intel_crtc->cursor_height = height;
6573
6b383a7f 6574 intel_crtc_update_cursor(crtc, true);
3f8bc370 6575
79e53945 6576 return 0;
e7b526bb 6577fail_unpin:
05394f39 6578 i915_gem_object_unpin(obj);
7f9872e0 6579fail_locked:
34b8686e 6580 mutex_unlock(&dev->struct_mutex);
bc9025bd 6581fail:
05394f39 6582 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6583 return ret;
79e53945
JB		 6584}
6585
6586static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6587{
79e53945 6588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6589
cda4b7d3
CW		 6590 intel_crtc->cursor_x = x;
6591 intel_crtc->cursor_y = y;
652c393a 6592
6b383a7f 6593 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6594
6595 return 0;
6596}
6597
6598/** Sets the color ramps on behalf of RandR */
6599void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6600 u16 blue, int regno)
6601{
6602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6603
6604 intel_crtc->lut_r[regno] = red >> 8;
6605 intel_crtc->lut_g[regno] = green >> 8;
6606 intel_crtc->lut_b[regno] = blue >> 8;
6607}
6608
b8c00ac5
DA		 6609void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6610 u16 *blue, int regno)
6611{
6612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6613
6614 *red = intel_crtc->lut_r[regno] << 8;
6615 *green = intel_crtc->lut_g[regno] << 8;
6616 *blue = intel_crtc->lut_b[regno] << 8;
6617}
6618
79e53945 6619static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6620 u16 *blue, uint32_t start, uint32_t size)
79e53945 6621{
7203425a 6622 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6624
7203425a 6625 for (i = start; i < end; i++) {
79e53945
JB		 6626 intel_crtc->lut_r[i] = red[i] >> 8;
6627 intel_crtc->lut_g[i] = green[i] >> 8;
6628 intel_crtc->lut_b[i] = blue[i] >> 8;
6629 }
6630
6631 intel_crtc_load_lut(crtc);
6632}
6633
79e53945
JB		 6634/* VESA 640x480x72Hz mode to set on the pipe */
6635static struct drm_display_mode load_detect_mode = {
6636 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6637 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6638};
6639
d2dff872
CW		 6640static struct drm_framebuffer *
6641intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6642 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6643 struct drm_i915_gem_object *obj)
6644{
6645 struct intel_framebuffer *intel_fb;
6646 int ret;
6647
6648 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6649 if (!intel_fb) {
6650 drm_gem_object_unreference_unlocked(&obj->base);
6651 return ERR_PTR(-ENOMEM);
6652 }
6653
6654 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6655 if (ret) {
6656 drm_gem_object_unreference_unlocked(&obj->base);
6657 kfree(intel_fb);
6658 return ERR_PTR(ret);
6659 }
6660
6661 return &intel_fb->base;
6662}
6663
6664static u32
6665intel_framebuffer_pitch_for_width(int width, int bpp)
6666{
6667 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6668 return ALIGN(pitch, 64);
6669}
6670
6671static u32
6672intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6673{
6674 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6675 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6676}
6677
6678static struct drm_framebuffer *
6679intel_framebuffer_create_for_mode(struct drm_device *dev,
6680 struct drm_display_mode *mode,
6681 int depth, int bpp)
6682{
6683 struct drm_i915_gem_object *obj;
0fed39bd 6684 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6685
6686 obj = i915_gem_alloc_object(dev,
6687 intel_framebuffer_size_for_mode(mode, bpp));
6688 if (obj == NULL)
6689 return ERR_PTR(-ENOMEM);
6690
6691 mode_cmd.width = mode->hdisplay;
6692 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6693 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6694 bpp);
5ca0c34a 6695 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6696
6697 return intel_framebuffer_create(dev, &mode_cmd, obj);
6698}
6699
6700static struct drm_framebuffer *
6701mode_fits_in_fbdev(struct drm_device *dev,
6702 struct drm_display_mode *mode)
6703{
6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 struct drm_i915_gem_object *obj;
6706 struct drm_framebuffer *fb;
6707
6708 if (dev_priv->fbdev == NULL)
6709 return NULL;
6710
6711 obj = dev_priv->fbdev->ifb.obj;
6712 if (obj == NULL)
6713 return NULL;
6714
6715 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6716 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6717 fb->bits_per_pixel))
d2dff872
CW		 6718 return NULL;
6719
01f2c773 6720 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6721 return NULL;
6722
6723 return fb;
6724}
6725
d2434ab7 6726bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6727 struct drm_display_mode *mode,
8261b191 6728 struct intel_load_detect_pipe *old)
79e53945
JB		 6729{
6730 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6731 struct intel_encoder *intel_encoder =
6732 intel_attached_encoder(connector);
79e53945 6733 struct drm_crtc *possible_crtc;
4ef69c7a 6734 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6735 struct drm_crtc *crtc = NULL;
6736 struct drm_device *dev = encoder->dev;
94352cf9 6737 struct drm_framebuffer *fb;
79e53945
JB		 6738 int i = -1;
6739
d2dff872
CW		 6740 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6741 connector->base.id, drm_get_connector_name(connector),
6742 encoder->base.id, drm_get_encoder_name(encoder));
6743
79e53945
JB		 6744 /*
6745 * Algorithm gets a little messy:
7a5e4805 6746 *
79e53945
JB		 6747 * - if the connector already has an assigned crtc, use it (but make
6748 * sure it's on first)
7a5e4805 6749 *
79e53945
JB		 6750 * - try to find the first unused crtc that can drive this connector,
6751 * and use that if we find one
79e53945
JB		 6752 */
6753
6754 /* See if we already have a CRTC for this connector */
6755 if (encoder->crtc) {
6756 crtc = encoder->crtc;
8261b191 6757
7b24056b
DV		 6758 mutex_lock(&crtc->mutex);
6759
24218aac 6760 old->dpms_mode = connector->dpms;
8261b191
CW		 6761 old->load_detect_temp = false;
6762
6763 /* Make sure the crtc and connector are running */
24218aac
DV		 6764 if (connector->dpms != DRM_MODE_DPMS_ON)
6765 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6766
7173188d 6767 return true;
79e53945
JB		 6768 }
6769
6770 /* Find an unused one (if possible) */
6771 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6772 i++;
6773 if (!(encoder->possible_crtcs & (1 << i)))
6774 continue;
6775 if (!possible_crtc->enabled) {
6776 crtc = possible_crtc;
6777 break;
6778 }
79e53945
JB		 6779 }
6780
6781 /*
6782 * If we didn't find an unused CRTC, don't use any.
6783 */
6784 if (!crtc) {
7173188d
CW		 6785 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6786 return false;
79e53945
JB		 6787 }
6788
7b24056b 6789 mutex_lock(&crtc->mutex);
fc303101
DV		 6790 intel_encoder->new_crtc = to_intel_crtc(crtc);
6791 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6792
6793 intel_crtc = to_intel_crtc(crtc);
24218aac 6794 old->dpms_mode = connector->dpms;
8261b191 6795 old->load_detect_temp = true;
d2dff872 6796 old->release_fb = NULL;
79e53945 6797
6492711d
CW		 6798 if (!mode)
6799 mode = &load_detect_mode;
79e53945 6800
d2dff872
CW		 6801 /* We need a framebuffer large enough to accommodate all accesses
6802 * that the plane may generate whilst we perform load detection.
6803 * We can not rely on the fbcon either being present (we get called
6804 * during its initialisation to detect all boot displays, or it may
6805 * not even exist) or that it is large enough to satisfy the
6806 * requested mode.
6807 */
94352cf9
DV		 6808 fb = mode_fits_in_fbdev(dev, mode);
6809 if (fb == NULL) {
d2dff872 6810 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6811 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6812 old->release_fb = fb;
d2dff872
CW		 6813 } else
6814 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6815 if (IS_ERR(fb)) {
d2dff872 6816 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6817 mutex_unlock(&crtc->mutex);
0e8b3d3e 6818 return false;
79e53945 6819 }
79e53945 6820
c0c36b94 6821 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6822 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6823 if (old->release_fb)
6824 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6825 mutex_unlock(&crtc->mutex);
0e8b3d3e 6826 return false;
79e53945 6827 }
7173188d 6828
79e53945 6829 /* let the connector get through one full cycle before testing */
9d0498a2 6830 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6831 return true;
79e53945
JB		 6832}
6833
d2434ab7 6834void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6835 struct intel_load_detect_pipe *old)
79e53945 6836{
d2434ab7
DV		 6837 struct intel_encoder *intel_encoder =
6838 intel_attached_encoder(connector);
4ef69c7a 6839 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6840 struct drm_crtc *crtc = encoder->crtc;
79e53945 6841
d2dff872
CW		 6842 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6843 connector->base.id, drm_get_connector_name(connector),
6844 encoder->base.id, drm_get_encoder_name(encoder));
6845
8261b191 6846 if (old->load_detect_temp) {
fc303101
DV		 6847 to_intel_connector(connector)->new_encoder = NULL;
6848 intel_encoder->new_crtc = NULL;
6849 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6850
36206361
DV		 6851 if (old->release_fb) {
6852 drm_framebuffer_unregister_private(old->release_fb);
6853 drm_framebuffer_unreference(old->release_fb);
6854 }
d2dff872 6855
67c96400 6856 mutex_unlock(&crtc->mutex);
0622a53c 6857 return;
79e53945
JB		 6858 }
6859
c751ce4f 6860 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6861 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6862 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6863
6864 mutex_unlock(&crtc->mutex);
79e53945
JB		 6865}
6866
6867/* Returns the clock of the currently programmed mode of the given pipe. */
6868static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6869{
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6872 int pipe = intel_crtc->pipe;
548f245b 6873 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6874 u32 fp;
6875 intel_clock_t clock;
6876
6877 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6878 fp = I915_READ(FP0(pipe));
79e53945 6879 else
39adb7a5 6880 fp = I915_READ(FP1(pipe));
79e53945
JB		 6881
6882 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6883 if (IS_PINEVIEW(dev)) {
6884 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6885 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6886 } else {
6887 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6888 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6889 }
6890
a6c45cf0 6891 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6892 if (IS_PINEVIEW(dev))
6893 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6894 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6895 else
6896 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6897 DPLL_FPA01_P1_POST_DIV_SHIFT);
6898
6899 switch (dpll & DPLL_MODE_MASK) {
6900 case DPLLB_MODE_DAC_SERIAL:
6901 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6902 5 : 10;
6903 break;
6904 case DPLLB_MODE_LVDS:
6905 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6906 7 : 14;
6907 break;
6908 default:
28c97730 6909 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6910 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6911 return 0;
6912 }
6913
6914 /* XXX: Handle the 100Mhz refclk */
2177832f 6915 intel_clock(dev, 96000, &clock);
79e53945
JB		 6916 } else {
6917 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6918
6919 if (is_lvds) {
6920 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6921 DPLL_FPA01_P1_POST_DIV_SHIFT);
6922 clock.p2 = 14;
6923
6924 if ((dpll & PLL_REF_INPUT_MASK) ==
6925 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6926 /* XXX: might not be 66MHz */
2177832f 6927 intel_clock(dev, 66000, &clock);
79e53945 6928 } else
2177832f 6929 intel_clock(dev, 48000, &clock);
79e53945
JB		 6930 } else {
6931 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6932 clock.p1 = 2;
6933 else {
6934 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6935 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6936 }
6937 if (dpll & PLL_P2_DIVIDE_BY_4)
6938 clock.p2 = 4;
6939 else
6940 clock.p2 = 2;
6941
2177832f 6942 intel_clock(dev, 48000, &clock);
79e53945
JB		 6943 }
6944 }
6945
6946 /* XXX: It would be nice to validate the clocks, but we can't reuse
6947 * i830PllIsValid() because it relies on the xf86_config connector
6948 * configuration being accurate, which it isn't necessarily.
6949 */
6950
6951 return clock.dot;
6952}
6953
6954/** Returns the currently programmed mode of the given pipe. */
6955struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6956 struct drm_crtc *crtc)
6957{
548f245b 6958 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6960 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6961 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6962 int htot = I915_READ(HTOTAL(cpu_transcoder));
6963 int hsync = I915_READ(HSYNC(cpu_transcoder));
6964 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6965 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6966
6967 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6968 if (!mode)
6969 return NULL;
6970
6971 mode->clock = intel_crtc_clock_get(dev, crtc);
6972 mode->hdisplay = (htot & 0xffff) + 1;
6973 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6974 mode->hsync_start = (hsync & 0xffff) + 1;
6975 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6976 mode->vdisplay = (vtot & 0xffff) + 1;
6977 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6978 mode->vsync_start = (vsync & 0xffff) + 1;
6979 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6980
6981 drm_mode_set_name(mode);
79e53945
JB		 6982
6983 return mode;
6984}
6985
3dec0095 6986static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6987{
6988 struct drm_device *dev = crtc->dev;
6989 drm_i915_private_t *dev_priv = dev->dev_private;
6990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6991 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6992 int dpll_reg = DPLL(pipe);
6993 int dpll;
652c393a 6994
bad720ff 6995 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6996 return;
6997
6998 if (!dev_priv->lvds_downclock_avail)
6999 return;
7000
dbdc6479 7001 dpll = I915_READ(dpll_reg);
652c393a 7002 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7003 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7004
8ac5a6d5 7005 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7006
7007 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7008 I915_WRITE(dpll_reg, dpll);
9d0498a2 7009 intel_wait_for_vblank(dev, pipe);
dbdc6479 7010
652c393a
JB		 7011 dpll = I915_READ(dpll_reg);
7012 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7013 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7014 }
652c393a
JB		 7015}
7016
7017static void intel_decrease_pllclock(struct drm_crtc *crtc)
7018{
7019 struct drm_device *dev = crtc->dev;
7020 drm_i915_private_t *dev_priv = dev->dev_private;
7021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7022
bad720ff 7023 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7024 return;
7025
7026 if (!dev_priv->lvds_downclock_avail)
7027 return;
7028
7029 /*
7030 * Since this is called by a timer, we should never get here in
7031 * the manual case.
7032 */
7033 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7034 int pipe = intel_crtc->pipe;
7035 int dpll_reg = DPLL(pipe);
7036 int dpll;
f6e5b160 7037
44d98a61 7038 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7039
8ac5a6d5 7040 assert_panel_unlocked(dev_priv, pipe);
652c393a 7041
dc257cf1 7042 dpll = I915_READ(dpll_reg);
652c393a
JB		 7043 dpll |= DISPLAY_RATE_SELECT_FPA1;
7044 I915_WRITE(dpll_reg, dpll);
9d0498a2 7045 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7046 dpll = I915_READ(dpll_reg);
7047 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7048 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7049 }
7050
7051}
7052
f047e395
CW		 7053void intel_mark_busy(struct drm_device *dev)
7054{
f047e395
CW		 7055 i915_update_gfx_val(dev->dev_private);
7056}
7057
7058void intel_mark_idle(struct drm_device *dev)
652c393a 7059{
652c393a 7060 struct drm_crtc *crtc;
652c393a
JB		 7061
7062 if (!i915_powersave)
7063 return;
7064
652c393a 7065 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7066 if (!crtc->fb)
7067 continue;
7068
725a5b54 7069 intel_decrease_pllclock(crtc);
652c393a 7070 }
652c393a
JB		 7071}
7072
725a5b54 7073void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7074{
f047e395
CW		 7075 struct drm_device *dev = obj->base.dev;
7076 struct drm_crtc *crtc;
652c393a 7077
f047e395 7078 if (!i915_powersave)
acb87dfb
CW		 7079 return;
7080
652c393a
JB		 7081 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7082 if (!crtc->fb)
7083 continue;
7084
f047e395 7085 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7086 intel_increase_pllclock(crtc);
652c393a
JB		 7087 }
7088}
7089
79e53945
JB		 7090static void intel_crtc_destroy(struct drm_crtc *crtc)
7091{
7092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7093 struct drm_device *dev = crtc->dev;
7094 struct intel_unpin_work *work;
7095 unsigned long flags;
7096
7097 spin_lock_irqsave(&dev->event_lock, flags);
7098 work = intel_crtc->unpin_work;
7099 intel_crtc->unpin_work = NULL;
7100 spin_unlock_irqrestore(&dev->event_lock, flags);
7101
7102 if (work) {
7103 cancel_work_sync(&work->work);
7104 kfree(work);
7105 }
79e53945
JB		 7106
7107 drm_crtc_cleanup(crtc);
67e77c5a 7108
79e53945
JB		 7109 kfree(intel_crtc);
7110}
7111
6b95a207
KH		 7112static void intel_unpin_work_fn(struct work_struct *__work)
7113{
7114 struct intel_unpin_work *work =
7115 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7116 struct drm_device *dev = work->crtc->dev;
6b95a207 7117
b4a98e57 7118 mutex_lock(&dev->struct_mutex);
1690e1eb 7119 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7120 drm_gem_object_unreference(&work->pending_flip_obj->base);
7121 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7122
b4a98e57
CW		 7123 intel_update_fbc(dev);
7124 mutex_unlock(&dev->struct_mutex);
7125
7126 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7127 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7128
6b95a207
KH		 7129 kfree(work);
7130}
7131
1afe3e9d 7132static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7133 struct drm_crtc *crtc)
6b95a207
KH		 7134{
7135 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7137 struct intel_unpin_work *work;
6b95a207
KH		 7138 unsigned long flags;
7139
7140 /* Ignore early vblank irqs */
7141 if (intel_crtc == NULL)
7142 return;
7143
7144 spin_lock_irqsave(&dev->event_lock, flags);
7145 work = intel_crtc->unpin_work;
e7d841ca
CW		 7146
7147 /* Ensure we don't miss a work->pending update ... */
7148 smp_rmb();
7149
7150 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7151 spin_unlock_irqrestore(&dev->event_lock, flags);
7152 return;
7153 }
7154
e7d841ca
CW		 7155 /* and that the unpin work is consistent wrt ->pending. */
7156 smp_rmb();
7157
6b95a207 7158 intel_crtc->unpin_work = NULL;
6b95a207 7159
45a066eb
RC		 7160 if (work->event)
7161 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7162
0af7e4df
MK		 7163 drm_vblank_put(dev, intel_crtc->pipe);
7164
6b95a207
KH		 7165 spin_unlock_irqrestore(&dev->event_lock, flags);
7166
2c10d571 7167 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7168
7169 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7170
7171 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7172}
7173
1afe3e9d
JB		 7174void intel_finish_page_flip(struct drm_device *dev, int pipe)
7175{
7176 drm_i915_private_t *dev_priv = dev->dev_private;
7177 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7178
49b14a5c 7179 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7180}
7181
7182void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7183{
7184 drm_i915_private_t *dev_priv = dev->dev_private;
7185 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7186
49b14a5c 7187 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7188}
7189
6b95a207
KH		 7190void intel_prepare_page_flip(struct drm_device *dev, int plane)
7191{
7192 drm_i915_private_t *dev_priv = dev->dev_private;
7193 struct intel_crtc *intel_crtc =
7194 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7195 unsigned long flags;
7196
e7d841ca
CW		 7197 /* NB: An MMIO update of the plane base pointer will also
7198 * generate a page-flip completion irq, i.e. every modeset
7199 * is also accompanied by a spurious intel_prepare_page_flip().
7200 */
6b95a207 7201 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7202 if (intel_crtc->unpin_work)
7203 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7204 spin_unlock_irqrestore(&dev->event_lock, flags);
7205}
7206
e7d841ca
CW		 7207inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7208{
7209 /* Ensure that the work item is consistent when activating it ... */
7210 smp_wmb();
7211 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7212 /* and that it is marked active as soon as the irq could fire. */
7213 smp_wmb();
7214}
7215
8c9f3aaf
JB		 7216static int intel_gen2_queue_flip(struct drm_device *dev,
7217 struct drm_crtc *crtc,
7218 struct drm_framebuffer *fb,
7219 struct drm_i915_gem_object *obj)
7220{
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7223 u32 flip_mask;
6d90c952 7224 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7225 int ret;
7226
6d90c952 7227 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7228 if (ret)
83d4092b 7229 goto err;
8c9f3aaf 7230
6d90c952 7231 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7232 if (ret)
83d4092b 7233 goto err_unpin;
8c9f3aaf
JB		 7234
7235 /* Can't queue multiple flips, so wait for the previous
7236 * one to finish before executing the next.
7237 */
7238 if (intel_crtc->plane)
7239 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7240 else
7241 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7242 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7243 intel_ring_emit(ring, MI_NOOP);
7244 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7245 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7246 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7247 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7248 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7249
7250 intel_mark_page_flip_active(intel_crtc);
6d90c952 7251 intel_ring_advance(ring);
83d4092b
CW		 7252 return 0;
7253
7254err_unpin:
7255 intel_unpin_fb_obj(obj);
7256err:
8c9f3aaf
JB		 7257 return ret;
7258}
7259
7260static int intel_gen3_queue_flip(struct drm_device *dev,
7261 struct drm_crtc *crtc,
7262 struct drm_framebuffer *fb,
7263 struct drm_i915_gem_object *obj)
7264{
7265 struct drm_i915_private *dev_priv = dev->dev_private;
7266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7267 u32 flip_mask;
6d90c952 7268 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7269 int ret;
7270
6d90c952 7271 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7272 if (ret)
83d4092b 7273 goto err;
8c9f3aaf 7274
6d90c952 7275 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7276 if (ret)
83d4092b 7277 goto err_unpin;
8c9f3aaf
JB		 7278
7279 if (intel_crtc->plane)
7280 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7281 else
7282 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7283 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7284 intel_ring_emit(ring, MI_NOOP);
7285 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7286 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7287 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7288 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7289 intel_ring_emit(ring, MI_NOOP);
7290
e7d841ca 7291 intel_mark_page_flip_active(intel_crtc);
6d90c952 7292 intel_ring_advance(ring);
83d4092b
CW		 7293 return 0;
7294
7295err_unpin:
7296 intel_unpin_fb_obj(obj);
7297err:
8c9f3aaf
JB		 7298 return ret;
7299}
7300
7301static int intel_gen4_queue_flip(struct drm_device *dev,
7302 struct drm_crtc *crtc,
7303 struct drm_framebuffer *fb,
7304 struct drm_i915_gem_object *obj)
7305{
7306 struct drm_i915_private *dev_priv = dev->dev_private;
7307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7308 uint32_t pf, pipesrc;
6d90c952 7309 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7310 int ret;
7311
6d90c952 7312 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7313 if (ret)
83d4092b 7314 goto err;
8c9f3aaf 7315
6d90c952 7316 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7317 if (ret)
83d4092b 7318 goto err_unpin;
8c9f3aaf
JB		 7319
7320 /* i965+ uses the linear or tiled offsets from the
7321 * Display Registers (which do not change across a page-flip)
7322 * so we need only reprogram the base address.
7323 */
6d90c952
DV		 7324 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7326 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7327 intel_ring_emit(ring,
7328 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7329 obj->tiling_mode);
8c9f3aaf
JB		 7330
7331 /* XXX Enabling the panel-fitter across page-flip is so far
7332 * untested on non-native modes, so ignore it for now.
7333 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7334 */
7335 pf = 0;
7336 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7337 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7338
7339 intel_mark_page_flip_active(intel_crtc);
6d90c952 7340 intel_ring_advance(ring);
83d4092b
CW		 7341 return 0;
7342
7343err_unpin:
7344 intel_unpin_fb_obj(obj);
7345err:
8c9f3aaf
JB		 7346 return ret;
7347}
7348
7349static int intel_gen6_queue_flip(struct drm_device *dev,
7350 struct drm_crtc *crtc,
7351 struct drm_framebuffer *fb,
7352 struct drm_i915_gem_object *obj)
7353{
7354 struct drm_i915_private *dev_priv = dev->dev_private;
7355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7356 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7357 uint32_t pf, pipesrc;
7358 int ret;
7359
6d90c952 7360 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7361 if (ret)
83d4092b 7362 goto err;
8c9f3aaf 7363
6d90c952 7364 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7365 if (ret)
83d4092b 7366 goto err_unpin;
8c9f3aaf 7367
6d90c952
DV		 7368 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7369 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7370 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7371 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7372
dc257cf1
DV		 7373 /* Contrary to the suggestions in the documentation,
7374 * "Enable Panel Fitter" does not seem to be required when page
7375 * flipping with a non-native mode, and worse causes a normal
7376 * modeset to fail.
7377 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7378 */
7379 pf = 0;
8c9f3aaf 7380 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7381 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7382
7383 intel_mark_page_flip_active(intel_crtc);
6d90c952 7384 intel_ring_advance(ring);
83d4092b
CW		 7385 return 0;
7386
7387err_unpin:
7388 intel_unpin_fb_obj(obj);
7389err:
8c9f3aaf
JB		 7390 return ret;
7391}
7392
7c9017e5
JB		 7393/*
7394 * On gen7 we currently use the blit ring because (in early silicon at least)
7395 * the render ring doesn't give us interrpts for page flip completion, which
7396 * means clients will hang after the first flip is queued. Fortunately the
7397 * blit ring generates interrupts properly, so use it instead.
7398 */
7399static int intel_gen7_queue_flip(struct drm_device *dev,
7400 struct drm_crtc *crtc,
7401 struct drm_framebuffer *fb,
7402 struct drm_i915_gem_object *obj)
7403{
7404 struct drm_i915_private *dev_priv = dev->dev_private;
7405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7406 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7407 uint32_t plane_bit = 0;
7c9017e5
JB		 7408 int ret;
7409
7410 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7411 if (ret)
83d4092b 7412 goto err;
7c9017e5 7413
cb05d8de
DV		 7414 switch(intel_crtc->plane) {
7415 case PLANE_A:
7416 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7417 break;
7418 case PLANE_B:
7419 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7420 break;
7421 case PLANE_C:
7422 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7423 break;
7424 default:
7425 WARN_ONCE(1, "unknown plane in flip command\n");
7426 ret = -ENODEV;
ab3951eb 7427 goto err_unpin;
cb05d8de
DV		 7428 }
7429
7c9017e5
JB		 7430 ret = intel_ring_begin(ring, 4);
7431 if (ret)
83d4092b 7432 goto err_unpin;
7c9017e5 7433
cb05d8de 7434 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7435 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7436 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7437 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7438
7439 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7440 intel_ring_advance(ring);
83d4092b
CW		 7441 return 0;
7442
7443err_unpin:
7444 intel_unpin_fb_obj(obj);
7445err:
7c9017e5
JB		 7446 return ret;
7447}
7448
8c9f3aaf
JB		 7449static int intel_default_queue_flip(struct drm_device *dev,
7450 struct drm_crtc *crtc,
7451 struct drm_framebuffer *fb,
7452 struct drm_i915_gem_object *obj)
7453{
7454 return -ENODEV;
7455}
7456
6b95a207
KH		 7457static int intel_crtc_page_flip(struct drm_crtc *crtc,
7458 struct drm_framebuffer *fb,
7459 struct drm_pending_vblank_event *event)
7460{
7461 struct drm_device *dev = crtc->dev;
7462 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7463 struct drm_framebuffer *old_fb = crtc->fb;
7464 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7466 struct intel_unpin_work *work;
8c9f3aaf 7467 unsigned long flags;
52e68630 7468 int ret;
6b95a207 7469
e6a595d2
VS		 7470 /* Can't change pixel format via MI display flips. */
7471 if (fb->pixel_format != crtc->fb->pixel_format)
7472 return -EINVAL;
7473
7474 /*
7475 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7476 * Note that pitch changes could also affect these register.
7477 */
7478 if (INTEL_INFO(dev)->gen > 3 &&
7479 (fb->offsets[0] != crtc->fb->offsets[0] ||
7480 fb->pitches[0] != crtc->fb->pitches[0]))
7481 return -EINVAL;
7482
6b95a207
KH		 7483 work = kzalloc(sizeof *work, GFP_KERNEL);
7484 if (work == NULL)
7485 return -ENOMEM;
7486
6b95a207 7487 work->event = event;
b4a98e57 7488 work->crtc = crtc;
4a35f83b 7489 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7490 INIT_WORK(&work->work, intel_unpin_work_fn);
7491
7317c75e
JB		 7492 ret = drm_vblank_get(dev, intel_crtc->pipe);
7493 if (ret)
7494 goto free_work;
7495
6b95a207
KH		 7496 /* We borrow the event spin lock for protecting unpin_work */
7497 spin_lock_irqsave(&dev->event_lock, flags);
7498 if (intel_crtc->unpin_work) {
7499 spin_unlock_irqrestore(&dev->event_lock, flags);
7500 kfree(work);
7317c75e 7501 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7502
7503 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7504 return -EBUSY;
7505 }
7506 intel_crtc->unpin_work = work;
7507 spin_unlock_irqrestore(&dev->event_lock, flags);
7508
b4a98e57
CW		 7509 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7510 flush_workqueue(dev_priv->wq);
7511
79158103
CW		 7512 ret = i915_mutex_lock_interruptible(dev);
7513 if (ret)
7514 goto cleanup;
6b95a207 7515
75dfca80 7516 /* Reference the objects for the scheduled work. */
05394f39
CW		 7517 drm_gem_object_reference(&work->old_fb_obj->base);
7518 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7519
7520 crtc->fb = fb;
96b099fd 7521
e1f99ce6 7522 work->pending_flip_obj = obj;
e1f99ce6 7523
4e5359cd
SF		 7524 work->enable_stall_check = true;
7525
b4a98e57 7526 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7527 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7528
8c9f3aaf
JB		 7529 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7530 if (ret)
7531 goto cleanup_pending;
6b95a207 7532
7782de3b 7533 intel_disable_fbc(dev);
f047e395 7534 intel_mark_fb_busy(obj);
6b95a207
KH		 7535 mutex_unlock(&dev->struct_mutex);
7536
e5510fac
JB		 7537 trace_i915_flip_request(intel_crtc->plane, obj);
7538
6b95a207 7539 return 0;
96b099fd 7540
8c9f3aaf 7541cleanup_pending:
b4a98e57 7542 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7543 crtc->fb = old_fb;
05394f39
CW		 7544 drm_gem_object_unreference(&work->old_fb_obj->base);
7545 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7546 mutex_unlock(&dev->struct_mutex);
7547
79158103 7548cleanup:
96b099fd
CW		 7549 spin_lock_irqsave(&dev->event_lock, flags);
7550 intel_crtc->unpin_work = NULL;
7551 spin_unlock_irqrestore(&dev->event_lock, flags);
7552
7317c75e
JB		 7553 drm_vblank_put(dev, intel_crtc->pipe);
7554free_work:
96b099fd
CW		 7555 kfree(work);
7556
7557 return ret;
6b95a207
KH		 7558}
7559
f6e5b160 7560static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7561 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7562 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7563};
7564
6ed0f796 7565bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7566{
6ed0f796
DV		 7567 struct intel_encoder *other_encoder;
7568 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7569
6ed0f796
DV		 7570 if (WARN_ON(!crtc))
7571 return false;
7572
7573 list_for_each_entry(other_encoder,
7574 &crtc->dev->mode_config.encoder_list,
7575 base.head) {
7576
7577 if (&other_encoder->new_crtc->base != crtc ||
7578 encoder == other_encoder)
7579 continue;
7580 else
7581 return true;
f47166d2
CW		 7582 }
7583
6ed0f796
DV		 7584 return false;
7585}
47f1c6c9 7586
50f56119
DV		 7587static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7588 struct drm_crtc *crtc)
7589{
7590 struct drm_device *dev;
7591 struct drm_crtc *tmp;
7592 int crtc_mask = 1;
47f1c6c9 7593
50f56119 7594 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7595
50f56119 7596 dev = crtc->dev;
47f1c6c9 7597
50f56119
DV		 7598 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7599 if (tmp == crtc)
7600 break;
7601 crtc_mask <<= 1;
7602 }
47f1c6c9 7603
50f56119
DV		 7604 if (encoder->possible_crtcs & crtc_mask)
7605 return true;
7606 return false;
47f1c6c9 7607}
79e53945 7608
9a935856
DV		 7609/**
7610 * intel_modeset_update_staged_output_state
7611 *
7612 * Updates the staged output configuration state, e.g. after we've read out the
7613 * current hw state.
7614 */
7615static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7616{
9a935856
DV		 7617 struct intel_encoder *encoder;
7618 struct intel_connector *connector;
f6e5b160 7619
9a935856
DV		 7620 list_for_each_entry(connector, &dev->mode_config.connector_list,
7621 base.head) {
7622 connector->new_encoder =
7623 to_intel_encoder(connector->base.encoder);
7624 }
f6e5b160 7625
9a935856
DV		 7626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7627 base.head) {
7628 encoder->new_crtc =
7629 to_intel_crtc(encoder->base.crtc);
7630 }
f6e5b160
CW		 7631}
7632
9a935856
DV		 7633/**
7634 * intel_modeset_commit_output_state
7635 *
7636 * This function copies the stage display pipe configuration to the real one.
7637 */
7638static void intel_modeset_commit_output_state(struct drm_device *dev)
7639{
7640 struct intel_encoder *encoder;
7641 struct intel_connector *connector;
f6e5b160 7642
9a935856
DV		 7643 list_for_each_entry(connector, &dev->mode_config.connector_list,
7644 base.head) {
7645 connector->base.encoder = &connector->new_encoder->base;
7646 }
f6e5b160 7647
9a935856
DV		 7648 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649 base.head) {
7650 encoder->base.crtc = &encoder->new_crtc->base;
7651 }
7652}
7653
4e53c2e0
DV		 7654static int
7655pipe_config_set_bpp(struct drm_crtc *crtc,
7656 struct drm_framebuffer *fb,
7657 struct intel_crtc_config *pipe_config)
7658{
7659 struct drm_device *dev = crtc->dev;
7660 struct drm_connector *connector;
7661 int bpp;
7662
d42264b1
DV		 7663 switch (fb->pixel_format) {
7664 case DRM_FORMAT_C8:
4e53c2e0
DV		 7665 bpp = 8*3; /* since we go through a colormap */
7666 break;
d42264b1
DV		 7667 case DRM_FORMAT_XRGB1555:
7668 case DRM_FORMAT_ARGB1555:
7669 /* checked in intel_framebuffer_init already */
7670 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7671 return -EINVAL;
7672 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7673 bpp = 6*3; /* min is 18bpp */
7674 break;
d42264b1
DV		 7675 case DRM_FORMAT_XBGR8888:
7676 case DRM_FORMAT_ABGR8888:
7677 /* checked in intel_framebuffer_init already */
7678 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7679 return -EINVAL;
7680 case DRM_FORMAT_XRGB8888:
7681 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7682 bpp = 8*3;
7683 break;
d42264b1
DV		 7684 case DRM_FORMAT_XRGB2101010:
7685 case DRM_FORMAT_ARGB2101010:
7686 case DRM_FORMAT_XBGR2101010:
7687 case DRM_FORMAT_ABGR2101010:
7688 /* checked in intel_framebuffer_init already */
7689 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7690 return -EINVAL;
4e53c2e0
DV		 7691 bpp = 10*3;
7692 break;
baba133a 7693 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7694 default:
7695 DRM_DEBUG_KMS("unsupported depth\n");
7696 return -EINVAL;
7697 }
7698
4e53c2e0
DV		 7699 pipe_config->pipe_bpp = bpp;
7700
7701 /* Clamp display bpp to EDID value */
7702 list_for_each_entry(connector, &dev->mode_config.connector_list,
7703 head) {
7704 if (connector->encoder && connector->encoder->crtc != crtc)
7705 continue;
7706
7707 /* Don't use an invalid EDID bpc value */
7708 if (connector->display_info.bpc &&
7709 connector->display_info.bpc * 3 < bpp) {
7710 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7711 bpp, connector->display_info.bpc*3);
7712 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7713 }
996a2239
DV		 7714
7715 /* Clamp bpp to 8 on screens without EDID 1.4 */
7716 if (connector->display_info.bpc == 0 && bpp > 24) {
7717 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7718 bpp);
7719 pipe_config->pipe_bpp = 24;
7720 }
4e53c2e0
DV		 7721 }
7722
7723 return bpp;
7724}
7725
b8cecdf5
DV		 7726static struct intel_crtc_config *
7727intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7728 struct drm_framebuffer *fb,
b8cecdf5 7729 struct drm_display_mode *mode)
ee7b9f93 7730{
7758a113 7731 struct drm_device *dev = crtc->dev;
7758a113
DV		 7732 struct drm_encoder_helper_funcs *encoder_funcs;
7733 struct intel_encoder *encoder;
b8cecdf5 7734 struct intel_crtc_config *pipe_config;
4e53c2e0 7735 int plane_bpp;
ee7b9f93 7736
b8cecdf5
DV		 7737 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7738 if (!pipe_config)
7758a113
DV		 7739 return ERR_PTR(-ENOMEM);
7740
b8cecdf5
DV		 7741 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7742 drm_mode_copy(&pipe_config->requested_mode, mode);
7743
4e53c2e0
DV		 7744 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7745 if (plane_bpp < 0)
7746 goto fail;
7747
7758a113
DV		 7748 /* Pass our mode to the connectors and the CRTC to give them a chance to
7749 * adjust it according to limitations or connector properties, and also
7750 * a chance to reject the mode entirely.
47f1c6c9 7751 */
7758a113
DV		 7752 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7753 base.head) {
47f1c6c9 7754
7758a113
DV		 7755 if (&encoder->new_crtc->base != crtc)
7756 continue;
7ae89233
DV		 7757
7758 if (encoder->compute_config) {
7759 if (!(encoder->compute_config(encoder, pipe_config))) {
7760 DRM_DEBUG_KMS("Encoder config failure\n");
7761 goto fail;
7762 }
7763
7764 continue;
7765 }
7766
7758a113 7767 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7768 if (!(encoder_funcs->mode_fixup(&encoder->base,
7769 &pipe_config->requested_mode,
7770 &pipe_config->adjusted_mode))) {
7758a113
DV		 7771 DRM_DEBUG_KMS("Encoder fixup failed\n");
7772 goto fail;
7773 }
ee7b9f93 7774 }
47f1c6c9 7775
b8cecdf5 7776 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7777 DRM_DEBUG_KMS("CRTC fixup failed\n");
7778 goto fail;
ee7b9f93 7779 }
7758a113 7780 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7781
4e53c2e0
DV		 7782 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7783 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7784 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7785
b8cecdf5 7786 return pipe_config;
7758a113 7787fail:
b8cecdf5 7788 kfree(pipe_config);
7758a113 7789 return ERR_PTR(-EINVAL);
ee7b9f93 7790}
47f1c6c9 7791
e2e1ed41
DV		 7792/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7793 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7794static void
7795intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7796 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7797{
7798 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7799 struct drm_device *dev = crtc->dev;
7800 struct intel_encoder *encoder;
7801 struct intel_connector *connector;
7802 struct drm_crtc *tmp_crtc;
79e53945 7803
e2e1ed41 7804 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7805
e2e1ed41
DV		 7806 /* Check which crtcs have changed outputs connected to them, these need
7807 * to be part of the prepare_pipes mask. We don't (yet) support global
7808 * modeset across multiple crtcs, so modeset_pipes will only have one
7809 * bit set at most. */
7810 list_for_each_entry(connector, &dev->mode_config.connector_list,
7811 base.head) {
7812 if (connector->base.encoder == &connector->new_encoder->base)
7813 continue;
79e53945 7814
e2e1ed41
DV		 7815 if (connector->base.encoder) {
7816 tmp_crtc = connector->base.encoder->crtc;
7817
7818 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7819 }
7820
7821 if (connector->new_encoder)
7822 *prepare_pipes |=
7823 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7824 }
7825
e2e1ed41
DV		 7826 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7827 base.head) {
7828 if (encoder->base.crtc == &encoder->new_crtc->base)
7829 continue;
7830
7831 if (encoder->base.crtc) {
7832 tmp_crtc = encoder->base.crtc;
7833
7834 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7835 }
7836
7837 if (encoder->new_crtc)
7838 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7839 }
7840
e2e1ed41
DV		 7841 /* Check for any pipes that will be fully disabled ... */
7842 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7843 base.head) {
7844 bool used = false;
22fd0fab 7845
e2e1ed41
DV		 7846 /* Don't try to disable disabled crtcs. */
7847 if (!intel_crtc->base.enabled)
7848 continue;
7e7d76c3 7849
e2e1ed41
DV		 7850 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7851 base.head) {
7852 if (encoder->new_crtc == intel_crtc)
7853 used = true;
7854 }
7855
7856 if (!used)
7857 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7858 }
7859
e2e1ed41
DV		 7860
7861 /* set_mode is also used to update properties on life display pipes. */
7862 intel_crtc = to_intel_crtc(crtc);
7863 if (crtc->enabled)
7864 *prepare_pipes |= 1 << intel_crtc->pipe;
7865
b6c5164d
DV		 7866 /*
7867 * For simplicity do a full modeset on any pipe where the output routing
7868 * changed. We could be more clever, but that would require us to be
7869 * more careful with calling the relevant encoder->mode_set functions.
7870 */
e2e1ed41
DV		 7871 if (*prepare_pipes)
7872 *modeset_pipes = *prepare_pipes;
7873
7874 /* ... and mask these out. */
7875 *modeset_pipes &= ~(*disable_pipes);
7876 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7877
7878 /*
7879 * HACK: We don't (yet) fully support global modesets. intel_set_config
7880 * obies this rule, but the modeset restore mode of
7881 * intel_modeset_setup_hw_state does not.
7882 */
7883 *modeset_pipes &= 1 << intel_crtc->pipe;
7884 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7885
7886 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7887 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7888}
79e53945 7889
ea9d758d 7890static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7891{
ea9d758d 7892 struct drm_encoder *encoder;
f6e5b160 7893 struct drm_device *dev = crtc->dev;
f6e5b160 7894
ea9d758d
DV		 7895 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7896 if (encoder->crtc == crtc)
7897 return true;
7898
7899 return false;
7900}
7901
7902static void
7903intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7904{
7905 struct intel_encoder *intel_encoder;
7906 struct intel_crtc *intel_crtc;
7907 struct drm_connector *connector;
7908
7909 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7910 base.head) {
7911 if (!intel_encoder->base.crtc)
7912 continue;
7913
7914 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7915
7916 if (prepare_pipes & (1 << intel_crtc->pipe))
7917 intel_encoder->connectors_active = false;
7918 }
7919
7920 intel_modeset_commit_output_state(dev);
7921
7922 /* Update computed state. */
7923 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7924 base.head) {
7925 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7926 }
7927
7928 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7929 if (!connector->encoder || !connector->encoder->crtc)
7930 continue;
7931
7932 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7933
7934 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7935 struct drm_property *dpms_property =
7936 dev->mode_config.dpms_property;
7937
ea9d758d 7938 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7939 drm_object_property_set_value(&connector->base,
68d34720
DV		 7940 dpms_property,
7941 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7942
7943 intel_encoder = to_intel_encoder(connector->encoder);
7944 intel_encoder->connectors_active = true;
7945 }
7946 }
7947
7948}
7949
25c5b266
DV		 7950#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7951 list_for_each_entry((intel_crtc), \
7952 &(dev)->mode_config.crtc_list, \
7953 base.head) \
7954 if (mask & (1 <<(intel_crtc)->pipe)) \
7955
0e8ffe1b
DV		 7956static bool
7957intel_pipe_config_compare(struct intel_crtc_config *current_config,
7958 struct intel_crtc_config *pipe_config)
7959{
88adfff1
DV		 7960 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7961 DRM_ERROR("mismatch in has_pch_encoder "
7962 "(expected %i, found %i)\n",
7963 current_config->has_pch_encoder,
7964 pipe_config->has_pch_encoder);
7965 return false;
7966 }
7967
0e8ffe1b
DV		 7968 return true;
7969}
7970
b980514c 7971void
8af6cf88
DV		 7972intel_modeset_check_state(struct drm_device *dev)
7973{
0e8ffe1b 7974 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7975 struct intel_crtc *crtc;
7976 struct intel_encoder *encoder;
7977 struct intel_connector *connector;
0e8ffe1b 7978 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7979
7980 list_for_each_entry(connector, &dev->mode_config.connector_list,
7981 base.head) {
7982 /* This also checks the encoder/connector hw state with the
7983 * ->get_hw_state callbacks. */
7984 intel_connector_check_state(connector);
7985
7986 WARN(&connector->new_encoder->base != connector->base.encoder,
7987 "connector's staged encoder doesn't match current encoder\n");
7988 }
7989
7990 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7991 base.head) {
7992 bool enabled = false;
7993 bool active = false;
7994 enum pipe pipe, tracked_pipe;
7995
7996 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7997 encoder->base.base.id,
7998 drm_get_encoder_name(&encoder->base));
7999
8000 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8001 "encoder's stage crtc doesn't match current crtc\n");
8002 WARN(encoder->connectors_active && !encoder->base.crtc,
8003 "encoder's active_connectors set, but no crtc\n");
8004
8005 list_for_each_entry(connector, &dev->mode_config.connector_list,
8006 base.head) {
8007 if (connector->base.encoder != &encoder->base)
8008 continue;
8009 enabled = true;
8010 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8011 active = true;
8012 }
8013 WARN(!!encoder->base.crtc != enabled,
8014 "encoder's enabled state mismatch "
8015 "(expected %i, found %i)\n",
8016 !!encoder->base.crtc, enabled);
8017 WARN(active && !encoder->base.crtc,
8018 "active encoder with no crtc\n");
8019
8020 WARN(encoder->connectors_active != active,
8021 "encoder's computed active state doesn't match tracked active state "
8022 "(expected %i, found %i)\n", active, encoder->connectors_active);
8023
8024 active = encoder->get_hw_state(encoder, &pipe);
8025 WARN(active != encoder->connectors_active,
8026 "encoder's hw state doesn't match sw tracking "
8027 "(expected %i, found %i)\n",
8028 encoder->connectors_active, active);
8029
8030 if (!encoder->base.crtc)
8031 continue;
8032
8033 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8034 WARN(active && pipe != tracked_pipe,
8035 "active encoder's pipe doesn't match"
8036 "(expected %i, found %i)\n",
8037 tracked_pipe, pipe);
8038
8039 }
8040
8041 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8042 base.head) {
8043 bool enabled = false;
8044 bool active = false;
8045
8046 DRM_DEBUG_KMS("[CRTC:%d]\n",
8047 crtc->base.base.id);
8048
8049 WARN(crtc->active && !crtc->base.enabled,
8050 "active crtc, but not enabled in sw tracking\n");
8051
8052 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8053 base.head) {
8054 if (encoder->base.crtc != &crtc->base)
8055 continue;
8056 enabled = true;
8057 if (encoder->connectors_active)
8058 active = true;
8059 }
8060 WARN(active != crtc->active,
8061 "crtc's computed active state doesn't match tracked active state "
8062 "(expected %i, found %i)\n", active, crtc->active);
8063 WARN(enabled != crtc->base.enabled,
8064 "crtc's computed enabled state doesn't match tracked enabled state "
8065 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8066
88adfff1 8067 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 8068 active = dev_priv->display.get_pipe_config(crtc,
8069 &pipe_config);
8070 WARN(crtc->active != active,
8071 "crtc active state doesn't match with hw state "
8072 "(expected %i, found %i)\n", crtc->active, active);
8073
8074 WARN(active &&
8075 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8076 "pipe state doesn't match!\n");
8af6cf88
DV		 8077 }
8078}
8079
f30da187
DV		 8080static int __intel_set_mode(struct drm_crtc *crtc,
8081 struct drm_display_mode *mode,
8082 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8083{
8084 struct drm_device *dev = crtc->dev;
dbf2b54e 8085 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8086 struct drm_display_mode *saved_mode, *saved_hwmode;
8087 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8088 struct intel_crtc *intel_crtc;
8089 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8090 int ret = 0;
a6778b3c 8091
3ac18232 8092 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8093 if (!saved_mode)
8094 return -ENOMEM;
3ac18232 8095 saved_hwmode = saved_mode + 1;
a6778b3c 8096
e2e1ed41 8097 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8098 &prepare_pipes, &disable_pipes);
8099
3ac18232
TG		 8100 *saved_hwmode = crtc->hwmode;
8101 *saved_mode = crtc->mode;
a6778b3c 8102
25c5b266
DV		 8103 /* Hack: Because we don't (yet) support global modeset on multiple
8104 * crtcs, we don't keep track of the new mode for more than one crtc.
8105 * Hence simply check whether any bit is set in modeset_pipes in all the
8106 * pieces of code that are not yet converted to deal with mutliple crtcs
8107 * changing their mode at the same time. */
25c5b266 8108 if (modeset_pipes) {
4e53c2e0 8109 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8110 if (IS_ERR(pipe_config)) {
8111 ret = PTR_ERR(pipe_config);
8112 pipe_config = NULL;
8113
3ac18232 8114 goto out;
25c5b266 8115 }
25c5b266 8116 }
a6778b3c 8117
460da916
DV		 8118 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8119 intel_crtc_disable(&intel_crtc->base);
8120
ea9d758d
DV		 8121 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8122 if (intel_crtc->base.enabled)
8123 dev_priv->display.crtc_disable(&intel_crtc->base);
8124 }
a6778b3c 8125
6c4c86f5
DV		 8126 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8127 * to set it here already despite that we pass it down the callchain.
f6e5b160 8128 */
b8cecdf5 8129 if (modeset_pipes) {
3b117c8f 8130 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8131 crtc->mode = *mode;
b8cecdf5
DV		 8132 /* mode_set/enable/disable functions rely on a correct pipe
8133 * config. */
8134 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8135 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8136 }
7758a113 8137
ea9d758d
DV		 8138 /* Only after disabling all output pipelines that will be changed can we
8139 * update the the output configuration. */
8140 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8141
47fab737
DV		 8142 if (dev_priv->display.modeset_global_resources)
8143 dev_priv->display.modeset_global_resources(dev);
8144
a6778b3c
DV		 8145 /* Set up the DPLL and any encoders state that needs to adjust or depend
8146 * on the DPLL.
f6e5b160 8147 */
25c5b266 8148 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8149 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8150 x, y, fb);
8151 if (ret)
8152 goto done;
a6778b3c
DV		 8153 }
8154
8155 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8156 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8157 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8158
25c5b266
DV		 8159 if (modeset_pipes) {
8160 /* Store real post-adjustment hardware mode. */
b8cecdf5 8161 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8162
25c5b266
DV		 8163 /* Calculate and store various constants which
8164 * are later needed by vblank and swap-completion
8165 * timestamping. They are derived from true hwmode.
8166 */
8167 drm_calc_timestamping_constants(crtc);
8168 }
a6778b3c
DV		 8169
8170 /* FIXME: add subpixel order */
8171done:
c0c36b94 8172 if (ret && crtc->enabled) {
3ac18232
TG		 8173 crtc->hwmode = *saved_hwmode;
8174 crtc->mode = *saved_mode;
a6778b3c
DV		 8175 }
8176
3ac18232 8177out:
b8cecdf5 8178 kfree(pipe_config);
3ac18232 8179 kfree(saved_mode);
a6778b3c 8180 return ret;
f6e5b160
CW		 8181}
8182
f30da187
DV		 8183int intel_set_mode(struct drm_crtc *crtc,
8184 struct drm_display_mode *mode,
8185 int x, int y, struct drm_framebuffer *fb)
8186{
8187 int ret;
8188
8189 ret = __intel_set_mode(crtc, mode, x, y, fb);
8190
8191 if (ret == 0)
8192 intel_modeset_check_state(crtc->dev);
8193
8194 return ret;
8195}
8196
c0c36b94
CW		 8197void intel_crtc_restore_mode(struct drm_crtc *crtc)
8198{
8199 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8200}
8201
25c5b266
DV		 8202#undef for_each_intel_crtc_masked
8203
d9e55608
DV		 8204static void intel_set_config_free(struct intel_set_config *config)
8205{
8206 if (!config)
8207 return;
8208
1aa4b628
DV		 8209 kfree(config->save_connector_encoders);
8210 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8211 kfree(config);
8212}
8213
85f9eb71
DV		 8214static int intel_set_config_save_state(struct drm_device *dev,
8215 struct intel_set_config *config)
8216{
85f9eb71
DV		 8217 struct drm_encoder *encoder;
8218 struct drm_connector *connector;
8219 int count;
8220
1aa4b628
DV		 8221 config->save_encoder_crtcs =
8222 kcalloc(dev->mode_config.num_encoder,
8223 sizeof(struct drm_crtc *), GFP_KERNEL);
8224 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8225 return -ENOMEM;
8226
1aa4b628
DV		 8227 config->save_connector_encoders =
8228 kcalloc(dev->mode_config.num_connector,
8229 sizeof(struct drm_encoder *), GFP_KERNEL);
8230 if (!config->save_connector_encoders)
85f9eb71
DV		 8231 return -ENOMEM;
8232
8233 /* Copy data. Note that driver private data is not affected.
8234 * Should anything bad happen only the expected state is
8235 * restored, not the drivers personal bookkeeping.
8236 */
85f9eb71
DV		 8237 count = 0;
8238 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8239 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8240 }
8241
8242 count = 0;
8243 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8244 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8245 }
8246
8247 return 0;
8248}
8249
8250static void intel_set_config_restore_state(struct drm_device *dev,
8251 struct intel_set_config *config)
8252{
9a935856
DV		 8253 struct intel_encoder *encoder;
8254 struct intel_connector *connector;
85f9eb71
DV		 8255 int count;
8256
85f9eb71 8257 count = 0;
9a935856
DV		 8258 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8259 encoder->new_crtc =
8260 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8261 }
8262
8263 count = 0;
9a935856
DV		 8264 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8265 connector->new_encoder =
8266 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8267 }
8268}
8269
5e2b584e
DV		 8270static void
8271intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8272 struct intel_set_config *config)
8273{
8274
8275 /* We should be able to check here if the fb has the same properties
8276 * and then just flip_or_move it */
8277 if (set->crtc->fb != set->fb) {
8278 /* If we have no fb then treat it as a full mode set */
8279 if (set->crtc->fb == NULL) {
8280 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8281 config->mode_changed = true;
8282 } else if (set->fb == NULL) {
8283 config->mode_changed = true;
72f4901e
DV		 8284 } else if (set->fb->pixel_format !=
8285 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8286 config->mode_changed = true;
8287 } else
8288 config->fb_changed = true;
8289 }
8290
835c5873 8291 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8292 config->fb_changed = true;
8293
8294 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8295 DRM_DEBUG_KMS("modes are different, full mode set\n");
8296 drm_mode_debug_printmodeline(&set->crtc->mode);
8297 drm_mode_debug_printmodeline(set->mode);
8298 config->mode_changed = true;
8299 }
8300}
8301
2e431051 8302static int
9a935856
DV		 8303intel_modeset_stage_output_state(struct drm_device *dev,
8304 struct drm_mode_set *set,
8305 struct intel_set_config *config)
50f56119 8306{
85f9eb71 8307 struct drm_crtc *new_crtc;
9a935856
DV		 8308 struct intel_connector *connector;
8309 struct intel_encoder *encoder;
2e431051 8310 int count, ro;
50f56119 8311
9abdda74 8312 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8313 * of connectors. For paranoia, double-check this. */
8314 WARN_ON(!set->fb && (set->num_connectors != 0));
8315 WARN_ON(set->fb && (set->num_connectors == 0));
8316
50f56119 8317 count = 0;
9a935856
DV		 8318 list_for_each_entry(connector, &dev->mode_config.connector_list,
8319 base.head) {
8320 /* Otherwise traverse passed in connector list and get encoders
8321 * for them. */
50f56119 8322 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8323 if (set->connectors[ro] == &connector->base) {
8324 connector->new_encoder = connector->encoder;
50f56119
DV		 8325 break;
8326 }
8327 }
8328
9a935856
DV		 8329 /* If we disable the crtc, disable all its connectors. Also, if
8330 * the connector is on the changing crtc but not on the new
8331 * connector list, disable it. */
8332 if ((!set->fb || ro == set->num_connectors) &&
8333 connector->base.encoder &&
8334 connector->base.encoder->crtc == set->crtc) {
8335 connector->new_encoder = NULL;
8336
8337 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8338 connector->base.base.id,
8339 drm_get_connector_name(&connector->base));
8340 }
8341
8342
8343 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8344 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8345 config->mode_changed = true;
50f56119
DV		 8346 }
8347 }
9a935856 8348 /* connector->new_encoder is now updated for all connectors. */
50f56119 8349
9a935856 8350 /* Update crtc of enabled connectors. */
50f56119 8351 count = 0;
9a935856
DV		 8352 list_for_each_entry(connector, &dev->mode_config.connector_list,
8353 base.head) {
8354 if (!connector->new_encoder)
50f56119
DV		 8355 continue;
8356
9a935856 8357 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8358
8359 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8360 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8361 new_crtc = set->crtc;
8362 }
8363
8364 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8365 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8366 new_crtc)) {
5e2b584e 8367 return -EINVAL;
50f56119 8368 }
9a935856
DV		 8369 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8370
8371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8372 connector->base.base.id,
8373 drm_get_connector_name(&connector->base),
8374 new_crtc->base.id);
8375 }
8376
8377 /* Check for any encoders that needs to be disabled. */
8378 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8379 base.head) {
8380 list_for_each_entry(connector,
8381 &dev->mode_config.connector_list,
8382 base.head) {
8383 if (connector->new_encoder == encoder) {
8384 WARN_ON(!connector->new_encoder->new_crtc);
8385
8386 goto next_encoder;
8387 }
8388 }
8389 encoder->new_crtc = NULL;
8390next_encoder:
8391 /* Only now check for crtc changes so we don't miss encoders
8392 * that will be disabled. */
8393 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8394 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8395 config->mode_changed = true;
50f56119
DV		 8396 }
8397 }
9a935856 8398 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8399
2e431051
DV		 8400 return 0;
8401}
8402
8403static int intel_crtc_set_config(struct drm_mode_set *set)
8404{
8405 struct drm_device *dev;
2e431051
DV		 8406 struct drm_mode_set save_set;
8407 struct intel_set_config *config;
8408 int ret;
2e431051 8409
8d3e375e
DV		 8410 BUG_ON(!set);
8411 BUG_ON(!set->crtc);
8412 BUG_ON(!set->crtc->helper_private);
2e431051 8413
7e53f3a4
DV		 8414 /* Enforce sane interface api - has been abused by the fb helper. */
8415 BUG_ON(!set->mode && set->fb);
8416 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8417
2e431051
DV		 8418 if (set->fb) {
8419 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8420 set->crtc->base.id, set->fb->base.id,
8421 (int)set->num_connectors, set->x, set->y);
8422 } else {
8423 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8424 }
8425
8426 dev = set->crtc->dev;
8427
8428 ret = -ENOMEM;
8429 config = kzalloc(sizeof(*config), GFP_KERNEL);
8430 if (!config)
8431 goto out_config;
8432
8433 ret = intel_set_config_save_state(dev, config);
8434 if (ret)
8435 goto out_config;
8436
8437 save_set.crtc = set->crtc;
8438 save_set.mode = &set->crtc->mode;
8439 save_set.x = set->crtc->x;
8440 save_set.y = set->crtc->y;
8441 save_set.fb = set->crtc->fb;
8442
8443 /* Compute whether we need a full modeset, only an fb base update or no
8444 * change at all. In the future we might also check whether only the
8445 * mode changed, e.g. for LVDS where we only change the panel fitter in
8446 * such cases. */
8447 intel_set_config_compute_mode_changes(set, config);
8448
9a935856 8449 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8450 if (ret)
8451 goto fail;
8452
5e2b584e 8453 if (config->mode_changed) {
87f1faa6 8454 if (set->mode) {
50f56119
DV		 8455 DRM_DEBUG_KMS("attempting to set mode from"
8456 " userspace\n");
8457 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8458 }
8459
c0c36b94
CW		 8460 ret = intel_set_mode(set->crtc, set->mode,
8461 set->x, set->y, set->fb);
8462 if (ret) {
8463 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8464 set->crtc->base.id, ret);
87f1faa6
DV		 8465 goto fail;
8466 }
5e2b584e 8467 } else if (config->fb_changed) {
4878cae2
VS		 8468 intel_crtc_wait_for_pending_flips(set->crtc);
8469
4f660f49 8470 ret = intel_pipe_set_base(set->crtc,
94352cf9 8471 set->x, set->y, set->fb);
50f56119
DV		 8472 }
8473
d9e55608
DV		 8474 intel_set_config_free(config);
8475
50f56119
DV		 8476 return 0;
8477
8478fail:
85f9eb71 8479 intel_set_config_restore_state(dev, config);
50f56119
DV		 8480
8481 /* Try to restore the config */
5e2b584e 8482 if (config->mode_changed &&
c0c36b94
CW		 8483 intel_set_mode(save_set.crtc, save_set.mode,
8484 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8485 DRM_ERROR("failed to restore config after modeset failure\n");
8486
d9e55608
DV		 8487out_config:
8488 intel_set_config_free(config);
50f56119
DV		 8489 return ret;
8490}
f6e5b160
CW		 8491
8492static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8493 .cursor_set = intel_crtc_cursor_set,
8494 .cursor_move = intel_crtc_cursor_move,
8495 .gamma_set = intel_crtc_gamma_set,
50f56119 8496 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8497 .destroy = intel_crtc_destroy,
8498 .page_flip = intel_crtc_page_flip,
8499};
8500
79f689aa
PZ		 8501static void intel_cpu_pll_init(struct drm_device *dev)
8502{
affa9354 8503 if (HAS_DDI(dev))
79f689aa
PZ		 8504 intel_ddi_pll_init(dev);
8505}
8506
ee7b9f93
JB		 8507static void intel_pch_pll_init(struct drm_device *dev)
8508{
8509 drm_i915_private_t *dev_priv = dev->dev_private;
8510 int i;
8511
8512 if (dev_priv->num_pch_pll == 0) {
8513 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8514 return;
8515 }
8516
8517 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8518 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8519 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8520 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8521 }
8522}
8523
b358d0a6 8524static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8525{
22fd0fab 8526 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8527 struct intel_crtc *intel_crtc;
8528 int i;
8529
8530 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8531 if (intel_crtc == NULL)
8532 return;
8533
8534 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8535
8536 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8537 for (i = 0; i < 256; i++) {
8538 intel_crtc->lut_r[i] = i;
8539 intel_crtc->lut_g[i] = i;
8540 intel_crtc->lut_b[i] = i;
8541 }
8542
80824003
JB		 8543 /* Swap pipes & planes for FBC on pre-965 */
8544 intel_crtc->pipe = pipe;
8545 intel_crtc->plane = pipe;
3b117c8f 8546 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8547 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8548 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8549 intel_crtc->plane = !pipe;
80824003
JB		 8550 }
8551
22fd0fab
JB		 8552 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8553 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8554 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8555 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8556
79e53945 8557 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8558}
8559
08d7b3d1 8560int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8561 struct drm_file *file)
08d7b3d1 8562{
08d7b3d1 8563 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8564 struct drm_mode_object *drmmode_obj;
8565 struct intel_crtc *crtc;
08d7b3d1 8566
1cff8f6b
DV		 8567 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8568 return -ENODEV;
08d7b3d1 8569
c05422d5
DV		 8570 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8571 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8572
c05422d5 8573 if (!drmmode_obj) {
08d7b3d1
CW		 8574 DRM_ERROR("no such CRTC id\n");
8575 return -EINVAL;
8576 }
8577
c05422d5
DV		 8578 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8579 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8580
c05422d5 8581 return 0;
08d7b3d1
CW		 8582}
8583
66a9278e 8584static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8585{
66a9278e
DV		 8586 struct drm_device *dev = encoder->base.dev;
8587 struct intel_encoder *source_encoder;
79e53945 8588 int index_mask = 0;
79e53945
JB		 8589 int entry = 0;
8590
66a9278e
DV		 8591 list_for_each_entry(source_encoder,
8592 &dev->mode_config.encoder_list, base.head) {
8593
8594 if (encoder == source_encoder)
79e53945 8595 index_mask |= (1 << entry);
66a9278e
DV		 8596
8597 /* Intel hw has only one MUX where enocoders could be cloned. */
8598 if (encoder->cloneable && source_encoder->cloneable)
8599 index_mask |= (1 << entry);
8600
79e53945
JB		 8601 entry++;
8602 }
4ef69c7a 8603
79e53945
JB		 8604 return index_mask;
8605}
8606
4d302442
CW		 8607static bool has_edp_a(struct drm_device *dev)
8608{
8609 struct drm_i915_private *dev_priv = dev->dev_private;
8610
8611 if (!IS_MOBILE(dev))
8612 return false;
8613
8614 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8615 return false;
8616
8617 if (IS_GEN5(dev) &&
8618 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8619 return false;
8620
8621 return true;
8622}
8623
79e53945
JB		 8624static void intel_setup_outputs(struct drm_device *dev)
8625{
725e30ad 8626 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8627 struct intel_encoder *encoder;
cb0953d7 8628 bool dpd_is_edp = false;
f3cfcba6 8629 bool has_lvds;
79e53945 8630
f3cfcba6 8631 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8632 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8633 /* disable the panel fitter on everything but LVDS */
8634 I915_WRITE(PFIT_CONTROL, 0);
8635 }
79e53945 8636
c40c0f5b 8637 if (!IS_ULT(dev))
79935fca 8638 intel_crt_init(dev);
cb0953d7 8639
affa9354 8640 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8641 int found;
8642
8643 /* Haswell uses DDI functions to detect digital outputs */
8644 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8645 /* DDI A only supports eDP */
8646 if (found)
8647 intel_ddi_init(dev, PORT_A);
8648
8649 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8650 * register */
8651 found = I915_READ(SFUSE_STRAP);
8652
8653 if (found & SFUSE_STRAP_DDIB_DETECTED)
8654 intel_ddi_init(dev, PORT_B);
8655 if (found & SFUSE_STRAP_DDIC_DETECTED)
8656 intel_ddi_init(dev, PORT_C);
8657 if (found & SFUSE_STRAP_DDID_DETECTED)
8658 intel_ddi_init(dev, PORT_D);
8659 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8660 int found;
270b3042
DV		 8661 dpd_is_edp = intel_dpd_is_edp(dev);
8662
8663 if (has_edp_a(dev))
8664 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8665
dc0fa718 8666 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8667 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8668 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8669 if (!found)
e2debe91 8670 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8671 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8672 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8673 }
8674
dc0fa718 8675 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8676 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8677
dc0fa718 8678 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8679 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8680
5eb08b69 8681 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8682 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8683
270b3042 8684 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8685 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8686 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8687 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8688 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8689 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8690
dc0fa718 8691 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8692 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8693 PORT_B);
67cfc203
VS		 8694 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8695 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8696 }
103a196f 8697 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8698 bool found = false;
7d57382e 8699
e2debe91 8700 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8701 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8702 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8703 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8704 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8705 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8706 }
27185ae1 8707
b01f2c3a
JB		 8708 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8709 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8710 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8711 }
725e30ad 8712 }
13520b05
KH		 8713
8714 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8715
e2debe91 8716 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8717 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8718 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8719 }
27185ae1 8720
e2debe91 8721 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8722
b01f2c3a
JB		 8723 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8724 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8725 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8726 }
8727 if (SUPPORTS_INTEGRATED_DP(dev)) {
8728 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8729 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8730 }
725e30ad 8731 }
27185ae1 8732
b01f2c3a
JB		 8733 if (SUPPORTS_INTEGRATED_DP(dev) &&
8734 (I915_READ(DP_D) & DP_DETECTED)) {
8735 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8736 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8737 }
bad720ff 8738 } else if (IS_GEN2(dev))
79e53945
JB		 8739 intel_dvo_init(dev);
8740
103a196f 8741 if (SUPPORTS_TV(dev))
79e53945
JB		 8742 intel_tv_init(dev);
8743
4ef69c7a
CW		 8744 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8745 encoder->base.possible_crtcs = encoder->crtc_mask;
8746 encoder->base.possible_clones =
66a9278e 8747 intel_encoder_clones(encoder);
79e53945 8748 }
47356eb6 8749
dde86e2d 8750 intel_init_pch_refclk(dev);
270b3042
DV		 8751
8752 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8753}
8754
8755static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8756{
8757 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8758
8759 drm_framebuffer_cleanup(fb);
05394f39 8760 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8761
8762 kfree(intel_fb);
8763}
8764
8765static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8766 struct drm_file *file,
79e53945
JB		 8767 unsigned int *handle)
8768{
8769 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8770 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8771
05394f39 8772 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8773}
8774
8775static const struct drm_framebuffer_funcs intel_fb_funcs = {
8776 .destroy = intel_user_framebuffer_destroy,
8777 .create_handle = intel_user_framebuffer_create_handle,
8778};
8779
38651674
DA		 8780int intel_framebuffer_init(struct drm_device *dev,
8781 struct intel_framebuffer *intel_fb,
308e5bcb 8782 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8783 struct drm_i915_gem_object *obj)
79e53945 8784{
79e53945
JB		 8785 int ret;
8786
c16ed4be
CW		 8787 if (obj->tiling_mode == I915_TILING_Y) {
8788 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8789 return -EINVAL;
c16ed4be 8790 }
57cd6508 8791
c16ed4be
CW		 8792 if (mode_cmd->pitches[0] & 63) {
8793 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8794 mode_cmd->pitches[0]);
57cd6508 8795 return -EINVAL;
c16ed4be 8796 }
57cd6508 8797
5d7bd705 8798 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8799 if (mode_cmd->pitches[0] > 32768) {
8800 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8801 mode_cmd->pitches[0]);
5d7bd705 8802 return -EINVAL;
c16ed4be 8803 }
5d7bd705
VS		 8804
8805 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8806 mode_cmd->pitches[0] != obj->stride) {
8807 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8808 mode_cmd->pitches[0], obj->stride);
5d7bd705 8809 return -EINVAL;
c16ed4be 8810 }
5d7bd705 8811
57779d06 8812 /* Reject formats not supported by any plane early. */
308e5bcb 8813 switch (mode_cmd->pixel_format) {
57779d06 8814 case DRM_FORMAT_C8:
04b3924d
VS		 8815 case DRM_FORMAT_RGB565:
8816 case DRM_FORMAT_XRGB8888:
8817 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8818 break;
8819 case DRM_FORMAT_XRGB1555:
8820 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8821 if (INTEL_INFO(dev)->gen > 3) {
8822 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8823 return -EINVAL;
c16ed4be 8824 }
57779d06
VS		 8825 break;
8826 case DRM_FORMAT_XBGR8888:
8827 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8828 case DRM_FORMAT_XRGB2101010:
8829 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8830 case DRM_FORMAT_XBGR2101010:
8831 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8832 if (INTEL_INFO(dev)->gen < 4) {
8833 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8834 return -EINVAL;
c16ed4be 8835 }
b5626747 8836 break;
04b3924d
VS		 8837 case DRM_FORMAT_YUYV:
8838 case DRM_FORMAT_UYVY:
8839 case DRM_FORMAT_YVYU:
8840 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8841 if (INTEL_INFO(dev)->gen < 5) {
8842 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8843 return -EINVAL;
c16ed4be 8844 }
57cd6508
CW		 8845 break;
8846 default:
c16ed4be 8847 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8848 return -EINVAL;
8849 }
8850
90f9a336
VS		 8851 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8852 if (mode_cmd->offsets[0] != 0)
8853 return -EINVAL;
8854
c7d73f6a
DV		 8855 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8856 intel_fb->obj = obj;
8857
79e53945
JB		 8858 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8859 if (ret) {
8860 DRM_ERROR("framebuffer init failed %d\n", ret);
8861 return ret;
8862 }
8863
79e53945
JB		 8864 return 0;
8865}
8866
79e53945
JB		 8867static struct drm_framebuffer *
8868intel_user_framebuffer_create(struct drm_device *dev,
8869 struct drm_file *filp,
308e5bcb 8870 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8871{
05394f39 8872 struct drm_i915_gem_object *obj;
79e53945 8873
308e5bcb
JB		 8874 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8875 mode_cmd->handles[0]));
c8725226 8876 if (&obj->base == NULL)
cce13ff7 8877 return ERR_PTR(-ENOENT);
79e53945 8878
d2dff872 8879 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8880}
8881
79e53945 8882static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8883 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8884 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8885};
8886
e70236a8
JB		 8887/* Set up chip specific display functions */
8888static void intel_init_display(struct drm_device *dev)
8889{
8890 struct drm_i915_private *dev_priv = dev->dev_private;
8891
affa9354 8892 if (HAS_DDI(dev)) {
0e8ffe1b 8893 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8894 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8895 dev_priv->display.crtc_enable = haswell_crtc_enable;
8896 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8897 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8898 dev_priv->display.update_plane = ironlake_update_plane;
8899 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8900 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8901 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8902 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8903 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8904 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8905 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8906 } else if (IS_VALLEYVIEW(dev)) {
8907 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8908 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8909 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8910 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8911 dev_priv->display.off = i9xx_crtc_off;
8912 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8913 } else {
0e8ffe1b 8914 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8915 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8916 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8917 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8918 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8919 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8920 }
e70236a8 8921
e70236a8 8922 /* Returns the core display clock speed */
25eb05fc
JB		 8923 if (IS_VALLEYVIEW(dev))
8924 dev_priv->display.get_display_clock_speed =
8925 valleyview_get_display_clock_speed;
8926 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8927 dev_priv->display.get_display_clock_speed =
8928 i945_get_display_clock_speed;
8929 else if (IS_I915G(dev))
8930 dev_priv->display.get_display_clock_speed =
8931 i915_get_display_clock_speed;
f2b115e6 8932 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8933 dev_priv->display.get_display_clock_speed =
8934 i9xx_misc_get_display_clock_speed;
8935 else if (IS_I915GM(dev))
8936 dev_priv->display.get_display_clock_speed =
8937 i915gm_get_display_clock_speed;
8938 else if (IS_I865G(dev))
8939 dev_priv->display.get_display_clock_speed =
8940 i865_get_display_clock_speed;
f0f8a9ce 8941 else if (IS_I85X(dev))
e70236a8
JB		 8942 dev_priv->display.get_display_clock_speed =
8943 i855_get_display_clock_speed;
8944 else /* 852, 830 */
8945 dev_priv->display.get_display_clock_speed =
8946 i830_get_display_clock_speed;
8947
7f8a8569 8948 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8949 if (IS_GEN5(dev)) {
674cf967 8950 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8951 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8952 } else if (IS_GEN6(dev)) {
674cf967 8953 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8954 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8955 } else if (IS_IVYBRIDGE(dev)) {
8956 /* FIXME: detect B0+ stepping and use auto training */
8957 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8958 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8959 dev_priv->display.modeset_global_resources =
8960 ivb_modeset_global_resources;
c82e4d26
ED		 8961 } else if (IS_HASWELL(dev)) {
8962 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8963 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8964 dev_priv->display.modeset_global_resources =
8965 haswell_modeset_global_resources;
a0e63c22 8966 }
6067aaea 8967 } else if (IS_G4X(dev)) {
e0dac65e 8968 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8969 }
8c9f3aaf
JB		 8970
8971 /* Default just returns -ENODEV to indicate unsupported */
8972 dev_priv->display.queue_flip = intel_default_queue_flip;
8973
8974 switch (INTEL_INFO(dev)->gen) {
8975 case 2:
8976 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8977 break;
8978
8979 case 3:
8980 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8981 break;
8982
8983 case 4:
8984 case 5:
8985 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8986 break;
8987
8988 case 6:
8989 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8990 break;
7c9017e5
JB		 8991 case 7:
8992 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8993 break;
8c9f3aaf 8994 }
e70236a8
JB		 8995}
8996
b690e96c
JB		 8997/*
8998 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8999 * resume, or other times. This quirk makes sure that's the case for
9000 * affected systems.
9001 */
0206e353 9002static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9003{
9004 struct drm_i915_private *dev_priv = dev->dev_private;
9005
9006 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9007 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9008}
9009
435793df
KP		 9010/*
9011 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9012 */
9013static void quirk_ssc_force_disable(struct drm_device *dev)
9014{
9015 struct drm_i915_private *dev_priv = dev->dev_private;
9016 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9017 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9018}
9019
4dca20ef 9020/*
5a15ab5b
CE		 9021 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9022 * brightness value
4dca20ef
CE		 9023 */
9024static void quirk_invert_brightness(struct drm_device *dev)
9025{
9026 struct drm_i915_private *dev_priv = dev->dev_private;
9027 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9028 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9029}
9030
b690e96c
JB		 9031struct intel_quirk {
9032 int device;
9033 int subsystem_vendor;
9034 int subsystem_device;
9035 void (*hook)(struct drm_device *dev);
9036};
9037
5f85f176
EE		 9038/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9039struct intel_dmi_quirk {
9040 void (*hook)(struct drm_device *dev);
9041 const struct dmi_system_id (*dmi_id_list)[];
9042};
9043
9044static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9045{
9046 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9047 return 1;
9048}
9049
9050static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9051 {
9052 .dmi_id_list = &(const struct dmi_system_id[]) {
9053 {
9054 .callback = intel_dmi_reverse_brightness,
9055 .ident = "NCR Corporation",
9056 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9057 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9058 },
9059 },
9060 { } /* terminating entry */
9061 },
9062 .hook = quirk_invert_brightness,
9063 },
9064};
9065
c43b5634 9066static struct intel_quirk intel_quirks[] = {
b690e96c 9067 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9068 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9069
b690e96c
JB		 9070 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9071 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9072
b690e96c
JB		 9073 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9074 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9075
ccd0d36e 9076 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9077 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9078 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9079
9080 /* Lenovo U160 cannot use SSC on LVDS */
9081 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9082
9083 /* Sony Vaio Y cannot use SSC on LVDS */
9084 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9085
9086 /* Acer Aspire 5734Z must invert backlight brightness */
9087 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9088
9089 /* Acer/eMachines G725 */
9090 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9091
9092 /* Acer/eMachines e725 */
9093 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9094
9095 /* Acer/Packard Bell NCL20 */
9096 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9097
9098 /* Acer Aspire 4736Z */
9099 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9100};
9101
9102static void intel_init_quirks(struct drm_device *dev)
9103{
9104 struct pci_dev *d = dev->pdev;
9105 int i;
9106
9107 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9108 struct intel_quirk *q = &intel_quirks[i];
9109
9110 if (d->device == q->device &&
9111 (d->subsystem_vendor == q->subsystem_vendor ||
9112 q->subsystem_vendor == PCI_ANY_ID) &&
9113 (d->subsystem_device == q->subsystem_device ||
9114 q->subsystem_device == PCI_ANY_ID))
9115 q->hook(dev);
9116 }
5f85f176
EE		 9117 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9118 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9119 intel_dmi_quirks[i].hook(dev);
9120 }
b690e96c
JB		 9121}
9122
9cce37f4
JB		 9123/* Disable the VGA plane that we never use */
9124static void i915_disable_vga(struct drm_device *dev)
9125{
9126 struct drm_i915_private *dev_priv = dev->dev_private;
9127 u8 sr1;
766aa1c4 9128 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9129
9130 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9131 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9132 sr1 = inb(VGA_SR_DATA);
9133 outb(sr1 | 1<<5, VGA_SR_DATA);
9134 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9135 udelay(300);
9136
9137 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9138 POSTING_READ(vga_reg);
9139}
9140
f817586c
DV		 9141void intel_modeset_init_hw(struct drm_device *dev)
9142{
fa42e23c 9143 intel_init_power_well(dev);
0232e927 9144
a8f78b58
ED		 9145 intel_prepare_ddi(dev);
9146
f817586c
DV		 9147 intel_init_clock_gating(dev);
9148
79f5b2c7 9149 mutex_lock(&dev->struct_mutex);
8090c6b9 9150 intel_enable_gt_powersave(dev);
79f5b2c7 9151 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9152}
9153
79e53945
JB		 9154void intel_modeset_init(struct drm_device *dev)
9155{
652c393a 9156 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9157 int i, j, ret;
79e53945
JB		 9158
9159 drm_mode_config_init(dev);
9160
9161 dev->mode_config.min_width = 0;
9162 dev->mode_config.min_height = 0;
9163
019d96cb
DA		 9164 dev->mode_config.preferred_depth = 24;
9165 dev->mode_config.prefer_shadow = 1;
9166
e6ecefaa 9167 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9168
b690e96c
JB		 9169 intel_init_quirks(dev);
9170
1fa61106
ED		 9171 intel_init_pm(dev);
9172
e3c74757
BW		 9173 if (INTEL_INFO(dev)->num_pipes == 0)
9174 return;
9175
e70236a8
JB		 9176 intel_init_display(dev);
9177
a6c45cf0
CW		 9178 if (IS_GEN2(dev)) {
9179 dev->mode_config.max_width = 2048;
9180 dev->mode_config.max_height = 2048;
9181 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9182 dev->mode_config.max_width = 4096;
9183 dev->mode_config.max_height = 4096;
79e53945 9184 } else {
a6c45cf0
CW		 9185 dev->mode_config.max_width = 8192;
9186 dev->mode_config.max_height = 8192;
79e53945 9187 }
5d4545ae 9188 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9189
28c97730 9190 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9191 INTEL_INFO(dev)->num_pipes,
9192 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9193
7eb552ae 9194 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9195 intel_crtc_init(dev, i);
7f1f3851
JB		 9196 for (j = 0; j < dev_priv->num_plane; j++) {
9197 ret = intel_plane_init(dev, i, j);
9198 if (ret)
06da8da2
VS		 9199 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9200 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9201 }
79e53945
JB		 9202 }
9203
79f689aa 9204 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9205 intel_pch_pll_init(dev);
9206
9cce37f4
JB		 9207 /* Just disable it once at startup */
9208 i915_disable_vga(dev);
79e53945 9209 intel_setup_outputs(dev);
11be49eb
CW		 9210
9211 /* Just in case the BIOS is doing something questionable. */
9212 intel_disable_fbc(dev);
2c7111db
CW		 9213}
9214
24929352
DV		 9215static void
9216intel_connector_break_all_links(struct intel_connector *connector)
9217{
9218 connector->base.dpms = DRM_MODE_DPMS_OFF;
9219 connector->base.encoder = NULL;
9220 connector->encoder->connectors_active = false;
9221 connector->encoder->base.crtc = NULL;
9222}
9223
7fad798e
DV		 9224static void intel_enable_pipe_a(struct drm_device *dev)
9225{
9226 struct intel_connector *connector;
9227 struct drm_connector *crt = NULL;
9228 struct intel_load_detect_pipe load_detect_temp;
9229
9230 /* We can't just switch on the pipe A, we need to set things up with a
9231 * proper mode and output configuration. As a gross hack, enable pipe A
9232 * by enabling the load detect pipe once. */
9233 list_for_each_entry(connector,
9234 &dev->mode_config.connector_list,
9235 base.head) {
9236 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9237 crt = &connector->base;
9238 break;
9239 }
9240 }
9241
9242 if (!crt)
9243 return;
9244
9245 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9246 intel_release_load_detect_pipe(crt, &load_detect_temp);
9247
652c393a 9248
7fad798e
DV		 9249}
9250
fa555837
DV		 9251static bool
9252intel_check_plane_mapping(struct intel_crtc *crtc)
9253{
7eb552ae
BW		 9254 struct drm_device *dev = crtc->base.dev;
9255 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9256 u32 reg, val;
9257
7eb552ae 9258 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9259 return true;
9260
9261 reg = DSPCNTR(!crtc->plane);
9262 val = I915_READ(reg);
9263
9264 if ((val & DISPLAY_PLANE_ENABLE) &&
9265 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9266 return false;
9267
9268 return true;
9269}
9270
24929352
DV		 9271static void intel_sanitize_crtc(struct intel_crtc *crtc)
9272{
9273 struct drm_device *dev = crtc->base.dev;
9274 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9275 u32 reg;
24929352 9276
24929352 9277 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9278 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9279 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9280
9281 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9282 * disable the crtc (and hence change the state) if it is wrong. Note
9283 * that gen4+ has a fixed plane -> pipe mapping. */
9284 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9285 struct intel_connector *connector;
9286 bool plane;
9287
24929352
DV		 9288 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9289 crtc->base.base.id);
9290
9291 /* Pipe has the wrong plane attached and the plane is active.
9292 * Temporarily change the plane mapping and disable everything
9293 * ... */
9294 plane = crtc->plane;
9295 crtc->plane = !plane;
9296 dev_priv->display.crtc_disable(&crtc->base);
9297 crtc->plane = plane;
9298
9299 /* ... and break all links. */
9300 list_for_each_entry(connector, &dev->mode_config.connector_list,
9301 base.head) {
9302 if (connector->encoder->base.crtc != &crtc->base)
9303 continue;
9304
9305 intel_connector_break_all_links(connector);
9306 }
9307
9308 WARN_ON(crtc->active);
9309 crtc->base.enabled = false;
9310 }
24929352 9311
7fad798e
DV		 9312 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9313 crtc->pipe == PIPE_A && !crtc->active) {
9314 /* BIOS forgot to enable pipe A, this mostly happens after
9315 * resume. Force-enable the pipe to fix this, the update_dpms
9316 * call below we restore the pipe to the right state, but leave
9317 * the required bits on. */
9318 intel_enable_pipe_a(dev);
9319 }
9320
24929352
DV		 9321 /* Adjust the state of the output pipe according to whether we
9322 * have active connectors/encoders. */
9323 intel_crtc_update_dpms(&crtc->base);
9324
9325 if (crtc->active != crtc->base.enabled) {
9326 struct intel_encoder *encoder;
9327
9328 /* This can happen either due to bugs in the get_hw_state
9329 * functions or because the pipe is force-enabled due to the
9330 * pipe A quirk. */
9331 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9332 crtc->base.base.id,
9333 crtc->base.enabled ? "enabled" : "disabled",
9334 crtc->active ? "enabled" : "disabled");
9335
9336 crtc->base.enabled = crtc->active;
9337
9338 /* Because we only establish the connector -> encoder ->
9339 * crtc links if something is active, this means the
9340 * crtc is now deactivated. Break the links. connector
9341 * -> encoder links are only establish when things are
9342 * actually up, hence no need to break them. */
9343 WARN_ON(crtc->active);
9344
9345 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9346 WARN_ON(encoder->connectors_active);
9347 encoder->base.crtc = NULL;
9348 }
9349 }
9350}
9351
9352static void intel_sanitize_encoder(struct intel_encoder *encoder)
9353{
9354 struct intel_connector *connector;
9355 struct drm_device *dev = encoder->base.dev;
9356
9357 /* We need to check both for a crtc link (meaning that the
9358 * encoder is active and trying to read from a pipe) and the
9359 * pipe itself being active. */
9360 bool has_active_crtc = encoder->base.crtc &&
9361 to_intel_crtc(encoder->base.crtc)->active;
9362
9363 if (encoder->connectors_active && !has_active_crtc) {
9364 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9365 encoder->base.base.id,
9366 drm_get_encoder_name(&encoder->base));
9367
9368 /* Connector is active, but has no active pipe. This is
9369 * fallout from our resume register restoring. Disable
9370 * the encoder manually again. */
9371 if (encoder->base.crtc) {
9372 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9373 encoder->base.base.id,
9374 drm_get_encoder_name(&encoder->base));
9375 encoder->disable(encoder);
9376 }
9377
9378 /* Inconsistent output/port/pipe state happens presumably due to
9379 * a bug in one of the get_hw_state functions. Or someplace else
9380 * in our code, like the register restore mess on resume. Clamp
9381 * things to off as a safer default. */
9382 list_for_each_entry(connector,
9383 &dev->mode_config.connector_list,
9384 base.head) {
9385 if (connector->encoder != encoder)
9386 continue;
9387
9388 intel_connector_break_all_links(connector);
9389 }
9390 }
9391 /* Enabled encoders without active connectors will be fixed in
9392 * the crtc fixup. */
9393}
9394
44cec740 9395void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9396{
9397 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9398 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9399
9400 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9401 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9402 i915_disable_vga(dev);
0fde901f
KM		 9403 }
9404}
9405
24929352
DV		 9406/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9407 * and i915 state tracking structures. */
45e2b5f6
DV		 9408void intel_modeset_setup_hw_state(struct drm_device *dev,
9409 bool force_restore)
24929352
DV		 9410{
9411 struct drm_i915_private *dev_priv = dev->dev_private;
9412 enum pipe pipe;
9413 u32 tmp;
b5644d05 9414 struct drm_plane *plane;
24929352
DV		 9415 struct intel_crtc *crtc;
9416 struct intel_encoder *encoder;
9417 struct intel_connector *connector;
9418
affa9354 9419 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9420 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9421
9422 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9423 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9424 case TRANS_DDI_EDP_INPUT_A_ON:
9425 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9426 pipe = PIPE_A;
9427 break;
9428 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9429 pipe = PIPE_B;
9430 break;
9431 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9432 pipe = PIPE_C;
9433 break;
aaa148ec
DL		 9434 default:
9435 /* A bogus value has been programmed, disable
9436 * the transcoder */
9437 WARN(1, "Bogus eDP source %08x\n", tmp);
9438 intel_ddi_disable_transcoder_func(dev_priv,
9439 TRANSCODER_EDP);
9440 goto setup_pipes;
e28d54cb
PZ		 9441 }
9442
9443 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9444 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9445
9446 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9447 pipe_name(pipe));
9448 }
9449 }
9450
aaa148ec 9451setup_pipes:
0e8ffe1b
DV		 9452 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9453 base.head) {
3b117c8f 9454 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9455 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9456 crtc->config.cpu_transcoder = tmp;
9457
0e8ffe1b
DV		 9458 crtc->active = dev_priv->display.get_pipe_config(crtc,
9459 &crtc->config);
24929352
DV		 9460
9461 crtc->base.enabled = crtc->active;
9462
9463 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9464 crtc->base.base.id,
9465 crtc->active ? "enabled" : "disabled");
9466 }
9467
affa9354 9468 if (HAS_DDI(dev))
6441ab5f
PZ		 9469 intel_ddi_setup_hw_pll_state(dev);
9470
24929352
DV		 9471 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9472 base.head) {
9473 pipe = 0;
9474
9475 if (encoder->get_hw_state(encoder, &pipe)) {
9476 encoder->base.crtc =
9477 dev_priv->pipe_to_crtc_mapping[pipe];
9478 } else {
9479 encoder->base.crtc = NULL;
9480 }
9481
9482 encoder->connectors_active = false;
9483 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9484 encoder->base.base.id,
9485 drm_get_encoder_name(&encoder->base),
9486 encoder->base.crtc ? "enabled" : "disabled",
9487 pipe);
9488 }
9489
9490 list_for_each_entry(connector, &dev->mode_config.connector_list,
9491 base.head) {
9492 if (connector->get_hw_state(connector)) {
9493 connector->base.dpms = DRM_MODE_DPMS_ON;
9494 connector->encoder->connectors_active = true;
9495 connector->base.encoder = &connector->encoder->base;
9496 } else {
9497 connector->base.dpms = DRM_MODE_DPMS_OFF;
9498 connector->base.encoder = NULL;
9499 }
9500 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9501 connector->base.base.id,
9502 drm_get_connector_name(&connector->base),
9503 connector->base.encoder ? "enabled" : "disabled");
9504 }
9505
9506 /* HW state is read out, now we need to sanitize this mess. */
9507 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9508 base.head) {
9509 intel_sanitize_encoder(encoder);
9510 }
9511
9512 for_each_pipe(pipe) {
9513 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9514 intel_sanitize_crtc(crtc);
9515 }
9a935856 9516
45e2b5f6 9517 if (force_restore) {
f30da187
DV		 9518 /*
9519 * We need to use raw interfaces for restoring state to avoid
9520 * checking (bogus) intermediate states.
9521 */
45e2b5f6 9522 for_each_pipe(pipe) {
b5644d05
JB		 9523 struct drm_crtc *crtc =
9524 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9525
9526 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9527 crtc->fb);
45e2b5f6 9528 }
b5644d05
JB		 9529 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9530 intel_plane_restore(plane);
0fde901f
KM		 9531
9532 i915_redisable_vga(dev);
45e2b5f6
DV		 9533 } else {
9534 intel_modeset_update_staged_output_state(dev);
9535 }
8af6cf88
DV		 9536
9537 intel_modeset_check_state(dev);
2e938892
DV		 9538
9539 drm_mode_config_reset(dev);
2c7111db
CW		 9540}
9541
9542void intel_modeset_gem_init(struct drm_device *dev)
9543{
1833b134 9544 intel_modeset_init_hw(dev);
02e792fb
DV		 9545
9546 intel_setup_overlay(dev);
24929352 9547
45e2b5f6 9548 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9549}
9550
9551void intel_modeset_cleanup(struct drm_device *dev)
9552{
652c393a
JB		 9553 struct drm_i915_private *dev_priv = dev->dev_private;
9554 struct drm_crtc *crtc;
9555 struct intel_crtc *intel_crtc;
9556
fd0c0642
DV		 9557 /*
9558 * Interrupts and polling as the first thing to avoid creating havoc.
9559 * Too much stuff here (turning of rps, connectors, ...) would
9560 * experience fancy races otherwise.
9561 */
9562 drm_irq_uninstall(dev);
9563 cancel_work_sync(&dev_priv->hotplug_work);
9564 /*
9565 * Due to the hpd irq storm handling the hotplug work can re-arm the
9566 * poll handlers. Hence disable polling after hpd handling is shut down.
9567 */
f87ea761 9568 drm_kms_helper_poll_fini(dev);
fd0c0642 9569
652c393a
JB		 9570 mutex_lock(&dev->struct_mutex);
9571
723bfd70
JB		 9572 intel_unregister_dsm_handler();
9573
652c393a
JB		 9574 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9575 /* Skip inactive CRTCs */
9576 if (!crtc->fb)
9577 continue;
9578
9579 intel_crtc = to_intel_crtc(crtc);
3dec0095 9580 intel_increase_pllclock(crtc);
652c393a
JB		 9581 }
9582
973d04f9 9583 intel_disable_fbc(dev);
e70236a8 9584
8090c6b9 9585 intel_disable_gt_powersave(dev);
0cdab21f 9586
930ebb46
DV		 9587 ironlake_teardown_rc6(dev);
9588
69341a5e
KH		 9589 mutex_unlock(&dev->struct_mutex);
9590
1630fe75
CW		 9591 /* flush any delayed tasks or pending work */
9592 flush_scheduled_work();
9593
dc652f90
JN		 9594 /* destroy backlight, if any, before the connectors */
9595 intel_panel_destroy_backlight(dev);
9596
79e53945 9597 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9598
9599 intel_cleanup_overlay(dev);
79e53945
JB		 9600}
9601
f1c79df3
ZW		 9602/*
9603 * Return which encoder is currently attached for connector.
9604 */
df0e9248 9605struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9606{
df0e9248
CW		 9607 return &intel_attached_encoder(connector)->base;
9608}
f1c79df3 9609
df0e9248
CW		 9610void intel_connector_attach_encoder(struct intel_connector *connector,
9611 struct intel_encoder *encoder)
9612{
9613 connector->encoder = encoder;
9614 drm_mode_connector_attach_encoder(&connector->base,
9615 &encoder->base);
79e53945 9616}
28d52043
DA		 9617
9618/*
9619 * set vga decode state - true == enable VGA decode
9620 */
9621int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9622{
9623 struct drm_i915_private *dev_priv = dev->dev_private;
9624 u16 gmch_ctrl;
9625
9626 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9627 if (state)
9628 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9629 else
9630 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9631 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9632 return 0;
9633}
c4a1d9e4
CW		 9634
9635#ifdef CONFIG_DEBUG_FS
9636#include <linux/seq_file.h>
9637
9638struct intel_display_error_state {
9639 struct intel_cursor_error_state {
9640 u32 control;
9641 u32 position;
9642 u32 base;
9643 u32 size;
52331309 9644 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9645
9646 struct intel_pipe_error_state {
9647 u32 conf;
9648 u32 source;
9649
9650 u32 htotal;
9651 u32 hblank;
9652 u32 hsync;
9653 u32 vtotal;
9654 u32 vblank;
9655 u32 vsync;
52331309 9656 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9657
9658 struct intel_plane_error_state {
9659 u32 control;
9660 u32 stride;
9661 u32 size;
9662 u32 pos;
9663 u32 addr;
9664 u32 surface;
9665 u32 tile_offset;
52331309 9666 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9667};
9668
9669struct intel_display_error_state *
9670intel_display_capture_error_state(struct drm_device *dev)
9671{
0206e353 9672 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9673 struct intel_display_error_state *error;
702e7a56 9674 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9675 int i;
9676
9677 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9678 if (error == NULL)
9679 return NULL;
9680
52331309 9681 for_each_pipe(i) {
702e7a56
PZ		 9682 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9683
a18c4c3d
PZ		 9684 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9685 error->cursor[i].control = I915_READ(CURCNTR(i));
9686 error->cursor[i].position = I915_READ(CURPOS(i));
9687 error->cursor[i].base = I915_READ(CURBASE(i));
9688 } else {
9689 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9690 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9691 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9692 }
c4a1d9e4
CW		 9693
9694 error->plane[i].control = I915_READ(DSPCNTR(i));
9695 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9696 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9697 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9698 error->plane[i].pos = I915_READ(DSPPOS(i));
9699 }
ca291363
PZ		 9700 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9701 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9702 if (INTEL_INFO(dev)->gen >= 4) {
9703 error->plane[i].surface = I915_READ(DSPSURF(i));
9704 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9705 }
9706
702e7a56 9707 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9708 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9709 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9710 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9711 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9712 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9713 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9714 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9715 }
9716
9717 return error;
9718}
9719
9720void
9721intel_display_print_error_state(struct seq_file *m,
9722 struct drm_device *dev,
9723 struct intel_display_error_state *error)
9724{
9725 int i;
9726
7eb552ae 9727 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9728 for_each_pipe(i) {
c4a1d9e4
CW		 9729 seq_printf(m, "Pipe [%d]:\n", i);
9730 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9731 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9732 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9733 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9734 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9735 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9736 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9737 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9738
9739 seq_printf(m, "Plane [%d]:\n", i);
9740 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9741 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9742 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9743 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9744 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9745 }
4b71a570 9746 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9747 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9748 if (INTEL_INFO(dev)->gen >= 4) {
9749 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9750 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9751 }
9752
9753 seq_printf(m, "Cursor [%d]:\n", i);
9754 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9755 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9756 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9757 }
9758}
9759#endif
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