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drm/i915: Fix SDVO connector and encoder get_hw_state functions
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
19332d7a
JB		 1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
92f2584a
JB		 1310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311{
1312 u32 val;
1313 bool enabled;
1314
9d82aa17
ED		 1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
92f2584a
JB		 1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324}
1325
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
92f2584a
JB		 1339}
1340
4e634389
KP		 1341static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1343{
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357}
1358
1519b995
KP		 1359static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
dc0fa718 1362 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1367 return false;
1368 } else {
dc0fa718 1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1370 return false;
1371 }
1372 return true;
1373}
1374
1375static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377{
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389}
1390
1391static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393{
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
291906f1 1406static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
291906f1 1408{
47a05eca 1409 u32 val = I915_READ(reg);
4e634389 1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1412 reg, pipe_name(pipe));
de9a35ab 1413
75c5da27
DV		 1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
de9a35ab 1416 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1417}
1418
1419static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421{
47a05eca 1422 u32 val = I915_READ(reg);
b70ad586 1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 reg, pipe_name(pipe));
de9a35ab 1426
dc0fa718 1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1428 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1429 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1430}
1431
1432static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
291906f1 1437
f0575e92
KP		 1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
b70ad586 1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1446 pipe_name(pipe));
291906f1
JB		 1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
b70ad586 1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1452 pipe_name(pipe));
291906f1 1453
e2debe91
PZ		 1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1457}
1458
63d7bbe9
JB		 1459/**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
7434a255
TR		 1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1471 */
1472static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
a0c4da24 1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498}
1499
1500/**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510{
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526}
1527
a416edef
ED		 1528/* SBI access */
1529static void
988d6ee8
PZ		 1530intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
a416edef 1532{
988d6ee8 1533 u32 tmp;
a416edef 1534
09153000 1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1536
39fb50f6 1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1540 return;
a416edef
ED		 1541 }
1542
988d6ee8
PZ		 1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1551
39fb50f6 1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1555 return;
a416edef 1556 }
a416edef
ED		 1557}
1558
1559static u32
988d6ee8
PZ		 1560intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
a416edef 1562{
39fb50f6 1563 u32 value = 0;
09153000 1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1565
39fb50f6 1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1569 return 0;
a416edef
ED		 1570 }
1571
988d6ee8
PZ		 1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1579
39fb50f6 1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1583 return 0;
a416edef
ED		 1584 }
1585
09153000 1586 return I915_READ(SBI_DATA);
a416edef
ED		 1587}
1588
92f2584a 1589/**
b6b4e185 1590 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
b6b4e185 1597static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1598{
ee7b9f93 1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1600 struct intel_pch_pll *pll;
92f2584a
JB		 1601 int reg;
1602 u32 val;
1603
48da64a8 1604 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1605 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
ee7b9f93
JB		 1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
92f2584a
JB		 1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
ee7b9f93 1620 if (pll->active++ && pll->on) {
92b27b08 1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
92f2584a
JB		 1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
ee7b9f93
JB		 1633
1634 pll->on = true;
92f2584a
JB		 1635}
1636
ee7b9f93 1637static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1638{
ee7b9f93
JB		 1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1641 int reg;
ee7b9f93 1642 u32 val;
4c609cb8 1643
92f2584a
JB		 1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1646 if (pll == NULL)
1647 return;
92f2584a 1648
48da64a8
CW		 1649 if (WARN_ON(pll->refcount == 0))
1650 return;
7a419866 1651
ee7b9f93
JB		 1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
7a419866 1655
48da64a8 1656 if (WARN_ON(pll->active == 0)) {
92b27b08 1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1658 return;
1659 }
1660
ee7b9f93 1661 if (--pll->active) {
92b27b08 1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1663 return;
ee7b9f93
JB		 1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1670
ee7b9f93 1671 reg = pll->pll_reg;
92f2584a
JB		 1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
ee7b9f93
JB		 1677
1678 pll->on = false;
92f2584a
JB		 1679}
1680
b8a4f404
PZ		 1681static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
040484af 1683{
23670b32 1684 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1686 uint32_t reg, val, pipeconf_val;
040484af
JB		 1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
040484af
JB		 1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
23670b32
DV		 1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
59c859d6 1707 }
23670b32 1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
5f7f726d 1711 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
dfd07d72
DV		 1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1720 }
5f7f726d
PZ		 1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
040484af
JB		 1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735}
1736
8fb033d7 1737static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1738 enum transcoder cpu_transcoder)
040484af 1739{
8fb033d7 1740 u32 val, pipeconf_val;
8fb033d7
PZ		 1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
8fb033d7 1745 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1748
223a6fdf
PZ		 1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
25f3ef11 1754 val = TRANS_ENABLE;
937bb610 1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1756
9a76b1c6
PZ		 1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
a35f2679 1759 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
25f3ef11 1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1766}
1767
b8a4f404
PZ		 1768static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
040484af 1770{
23670b32
DV		 1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
040484af
JB		 1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
291906f1
JB		 1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
040484af
JB		 1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
040484af
JB		 1796}
1797
ab4d966c 1798static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1799{
8fb033d7
PZ		 1800 u32 val;
1801
8a52fd9f 1802 val = I915_READ(_TRANSACONF);
8fb033d7 1803 val &= ~TRANS_ENABLE;
8a52fd9f 1804 I915_WRITE(_TRANSACONF, val);
8fb033d7 1805 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1812 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1813}
1814
b24e7179 1815/**
309cfea8 1816 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
040484af 1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
040484af
JB		 1829static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
b24e7179 1831{
702e7a56
PZ		 1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1a240d4d 1834 enum pipe pch_transcoder;
b24e7179
JB		 1835 int reg;
1836 u32 val;
1837
681e5811 1838 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
b24e7179
JB		 1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
cc391bbb 1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
040484af
JB		 1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
b24e7179 1859
702e7a56 1860 reg = PIPECONF(cpu_transcoder);
b24e7179 1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
1869/**
309cfea8 1870 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883{
702e7a56
PZ		 1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
b24e7179
JB		 1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
19332d7a 1894 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
702e7a56 1900 reg = PIPECONF(cpu_transcoder);
b24e7179 1901 val = I915_READ(reg);
00d70b15
CW		 1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907}
1908
d74362c9
KP		 1909/*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
6f1d69b0 1913void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1914 enum plane plane)
1915{
14f86147
DL		 1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1920}
1921
b24e7179
JB		 1922/**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
00d70b15
CW		 1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1945 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
b24e7179
JB		 1949/**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959{
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
00d70b15
CW		 1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971}
1972
693db184
CW		 1973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
127bd2ac 1982int
48b956c5 1983intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1984 struct drm_i915_gem_object *obj,
919926ae 1985 struct intel_ring_buffer *pipelined)
6b95a207 1986{
ce453d81 1987 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1988 u32 alignment;
1989 int ret;
1990
05394f39 1991 switch (obj->tiling_mode) {
6b95a207 1992 case I915_TILING_NONE:
534843da
CW		 1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
a6c45cf0 1995 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
6b95a207
KH		 1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
2005 /* FIXME: Is this true? */
2006 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007 return -EINVAL;
2008 default:
2009 BUG();
2010 }
2011
693db184
CW		 2012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2015 * the VT-d warning.
2016 */
2017 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018 alignment = 256 * 1024;
2019
ce453d81 2020 dev_priv->mm.interruptible = false;
2da3b9b9 2021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2022 if (ret)
ce453d81 2023 goto err_interruptible;
6b95a207
KH		 2024
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2029 */
06d98131 2030 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2031 if (ret)
2032 goto err_unpin;
1690e1eb 2033
9a5a53b3 2034 i915_gem_object_pin_fence(obj);
6b95a207 2035
ce453d81 2036 dev_priv->mm.interruptible = true;
6b95a207 2037 return 0;
48b956c5
CW		 2038
2039err_unpin:
2040 i915_gem_object_unpin(obj);
ce453d81
CW		 2041err_interruptible:
2042 dev_priv->mm.interruptible = true;
48b956c5 2043 return ret;
6b95a207
KH		 2044}
2045
1690e1eb
CW		 2046void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2047{
2048 i915_gem_object_unpin_fence(obj);
2049 i915_gem_object_unpin(obj);
2050}
2051
c2c75131
DV		 2052/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053 * is assumed to be a power-of-two. */
bc752862
CW		 2054unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2055 unsigned int tiling_mode,
2056 unsigned int cpp,
2057 unsigned int pitch)
c2c75131 2058{
bc752862
CW		 2059 if (tiling_mode != I915_TILING_NONE) {
2060 unsigned int tile_rows, tiles;
c2c75131 2061
bc752862
CW		 2062 tile_rows = *y / 8;
2063 *y %= 8;
c2c75131 2064
bc752862
CW		 2065 tiles = *x / (512/cpp);
2066 *x %= 512/cpp;
2067
2068 return tile_rows * pitch * 8 + tiles * 4096;
2069 } else {
2070 unsigned int offset;
2071
2072 offset = *y * pitch + *x * cpp;
2073 *y = 0;
2074 *x = (offset & 4095) / cpp;
2075 return offset & -4096;
2076 }
c2c75131
DV		 2077}
2078
17638cd6
JB		 2079static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
81255565
JB		 2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
05394f39 2086 struct drm_i915_gem_object *obj;
81255565 2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
81255565 2089 u32 dspcntr;
5eddb70b 2090 u32 reg;
81255565
JB		 2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
81255565 2103
5eddb70b
CW		 2104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
81255565
JB		 2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2108 switch (fb->pixel_format) {
2109 case DRM_FORMAT_C8:
81255565
JB		 2110 dspcntr |= DISPPLANE_8BPP;
2111 break;
57779d06
VS		 2112 case DRM_FORMAT_XRGB1555:
2113 case DRM_FORMAT_ARGB1555:
2114 dspcntr |= DISPPLANE_BGRX555;
81255565 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
2118 break;
2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2134 break;
2135 default:
baba133a 2136 BUG();
81255565 2137 }
57779d06 2138
a6c45cf0 2139 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2140 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2141 dspcntr |= DISPPLANE_TILED;
2142 else
2143 dspcntr &= ~DISPPLANE_TILED;
2144 }
2145
5eddb70b 2146 I915_WRITE(reg, dspcntr);
81255565 2147
e506a0c6 2148 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2149
c2c75131
DV		 2150 if (INTEL_INFO(dev)->gen >= 4) {
2151 intel_crtc->dspaddr_offset =
bc752862
CW		 2152 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2153 fb->bits_per_pixel / 8,
2154 fb->pitches[0]);
c2c75131
DV		 2155 linear_offset -= intel_crtc->dspaddr_offset;
2156 } else {
e506a0c6 2157 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2158 }
e506a0c6
DV		 2159
2160 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2162 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2163 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2164 I915_MODIFY_DISPBASE(DSPSURF(plane),
2165 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2166 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2167 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2168 } else
e506a0c6 2169 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2170 POSTING_READ(reg);
81255565 2171
17638cd6
JB		 2172 return 0;
2173}
2174
2175static int ironlake_update_plane(struct drm_crtc *crtc,
2176 struct drm_framebuffer *fb, int x, int y)
2177{
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 struct intel_framebuffer *intel_fb;
2182 struct drm_i915_gem_object *obj;
2183 int plane = intel_crtc->plane;
e506a0c6 2184 unsigned long linear_offset;
17638cd6
JB		 2185 u32 dspcntr;
2186 u32 reg;
2187
2188 switch (plane) {
2189 case 0:
2190 case 1:
27f8227b 2191 case 2:
17638cd6
JB		 2192 break;
2193 default:
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 return -EINVAL;
2196 }
2197
2198 intel_fb = to_intel_framebuffer(fb);
2199 obj = intel_fb->obj;
2200
2201 reg = DSPCNTR(plane);
2202 dspcntr = I915_READ(reg);
2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2205 switch (fb->pixel_format) {
2206 case DRM_FORMAT_C8:
17638cd6
JB		 2207 dspcntr |= DISPPLANE_8BPP;
2208 break;
57779d06
VS		 2209 case DRM_FORMAT_RGB565:
2210 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2211 break;
57779d06
VS		 2212 case DRM_FORMAT_XRGB8888:
2213 case DRM_FORMAT_ARGB8888:
2214 dspcntr |= DISPPLANE_BGRX888;
2215 break;
2216 case DRM_FORMAT_XBGR8888:
2217 case DRM_FORMAT_ABGR8888:
2218 dspcntr |= DISPPLANE_RGBX888;
2219 break;
2220 case DRM_FORMAT_XRGB2101010:
2221 case DRM_FORMAT_ARGB2101010:
2222 dspcntr |= DISPPLANE_BGRX101010;
2223 break;
2224 case DRM_FORMAT_XBGR2101010:
2225 case DRM_FORMAT_ABGR2101010:
2226 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2227 break;
2228 default:
baba133a 2229 BUG();
17638cd6
JB		 2230 }
2231
2232 if (obj->tiling_mode != I915_TILING_NONE)
2233 dspcntr |= DISPPLANE_TILED;
2234 else
2235 dspcntr &= ~DISPPLANE_TILED;
2236
2237 /* must disable */
2238 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2239
2240 I915_WRITE(reg, dspcntr);
2241
e506a0c6 2242 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2243 intel_crtc->dspaddr_offset =
bc752862
CW		 2244 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2245 fb->bits_per_pixel / 8,
2246 fb->pitches[0]);
c2c75131 2247 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2248
e506a0c6
DV		 2249 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2251 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2252 I915_MODIFY_DISPBASE(DSPSURF(plane),
2253 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2254 if (IS_HASWELL(dev)) {
2255 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2256 } else {
2257 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2258 I915_WRITE(DSPLINOFF(plane), linear_offset);
2259 }
17638cd6
JB		 2260 POSTING_READ(reg);
2261
2262 return 0;
2263}
2264
2265/* Assume fb object is pinned & idle & fenced and just update base pointers */
2266static int
2267intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2268 int x, int y, enum mode_set_atomic state)
2269{
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2272
6b8e6ed0
CW		 2273 if (dev_priv->display.disable_fbc)
2274 dev_priv->display.disable_fbc(dev);
3dec0095 2275 intel_increase_pllclock(crtc);
81255565 2276
6b8e6ed0 2277 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2278}
2279
96a02917
VS		 2280void intel_display_handle_reset(struct drm_device *dev)
2281{
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_crtc *crtc;
2284
2285 /*
2286 * Flips in the rings have been nuked by the reset,
2287 * so complete all pending flips so that user space
2288 * will get its events and not get stuck.
2289 *
2290 * Also update the base address of all primary
2291 * planes to the the last fb to make sure we're
2292 * showing the correct fb after a reset.
2293 *
2294 * Need to make two loops over the crtcs so that we
2295 * don't try to grab a crtc mutex before the
2296 * pending_flip_queue really got woken up.
2297 */
2298
2299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 enum plane plane = intel_crtc->plane;
2302
2303 intel_prepare_page_flip(dev, plane);
2304 intel_finish_page_flip_plane(dev, plane);
2305 }
2306
2307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
2310 mutex_lock(&crtc->mutex);
2311 if (intel_crtc->active)
2312 dev_priv->display.update_plane(crtc, crtc->fb,
2313 crtc->x, crtc->y);
2314 mutex_unlock(&crtc->mutex);
2315 }
2316}
2317
14667a4b
CW		 2318static int
2319intel_finish_fb(struct drm_framebuffer *old_fb)
2320{
2321 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323 bool was_interruptible = dev_priv->mm.interruptible;
2324 int ret;
2325
14667a4b
CW		 2326 /* Big Hammer, we also need to ensure that any pending
2327 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328 * current scanout is retired before unpinning the old
2329 * framebuffer.
2330 *
2331 * This should only fail upon a hung GPU, in which case we
2332 * can safely continue.
2333 */
2334 dev_priv->mm.interruptible = false;
2335 ret = i915_gem_object_finish_gpu(obj);
2336 dev_priv->mm.interruptible = was_interruptible;
2337
2338 return ret;
2339}
2340
198598d0
VS		 2341static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2342{
2343 struct drm_device *dev = crtc->dev;
2344 struct drm_i915_master_private *master_priv;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346
2347 if (!dev->primary->master)
2348 return;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return;
2353
2354 switch (intel_crtc->pipe) {
2355 case 0:
2356 master_priv->sarea_priv->pipeA_x = x;
2357 master_priv->sarea_priv->pipeA_y = y;
2358 break;
2359 case 1:
2360 master_priv->sarea_priv->pipeB_x = x;
2361 master_priv->sarea_priv->pipeB_y = y;
2362 break;
2363 default:
2364 break;
2365 }
2366}
2367
5c3b82e2 2368static int
3c4fdcfb 2369intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2370 struct drm_framebuffer *fb)
79e53945
JB		 2371{
2372 struct drm_device *dev = crtc->dev;
6b8e6ed0 2373 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2375 struct drm_framebuffer *old_fb;
5c3b82e2 2376 int ret;
79e53945
JB		 2377
2378 /* no fb bound */
94352cf9 2379 if (!fb) {
a5071c2f 2380 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2381 return 0;
2382 }
2383
7eb552ae 2384 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2385 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2386 intel_crtc->plane,
7eb552ae 2387 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2388 return -EINVAL;
79e53945
JB		 2389 }
2390
5c3b82e2 2391 mutex_lock(&dev->struct_mutex);
265db958 2392 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2393 to_intel_framebuffer(fb)->obj,
919926ae 2394 NULL);
5c3b82e2
CW		 2395 if (ret != 0) {
2396 mutex_unlock(&dev->struct_mutex);
a5071c2f 2397 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2398 return ret;
2399 }
79e53945 2400
94352cf9 2401 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2402 if (ret) {
94352cf9 2403 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2404 mutex_unlock(&dev->struct_mutex);
a5071c2f 2405 DRM_ERROR("failed to update base address\n");
4e6cfefc 2406 return ret;
79e53945 2407 }
3c4fdcfb 2408
94352cf9
DV		 2409 old_fb = crtc->fb;
2410 crtc->fb = fb;
6c4c86f5
DV		 2411 crtc->x = x;
2412 crtc->y = y;
94352cf9 2413
b7f1de28
CW		 2414 if (old_fb) {
2415 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2417 }
652c393a 2418
6b8e6ed0 2419 intel_update_fbc(dev);
5c3b82e2 2420 mutex_unlock(&dev->struct_mutex);
79e53945 2421
198598d0 2422 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2423
2424 return 0;
79e53945
JB		 2425}
2426
5e84e1a4
ZW		 2427static void intel_fdi_normal_train(struct drm_crtc *crtc)
2428{
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 int pipe = intel_crtc->pipe;
2433 u32 reg, temp;
2434
2435 /* enable normal train */
2436 reg = FDI_TX_CTL(pipe);
2437 temp = I915_READ(reg);
61e499bf 2438 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2439 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2440 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2441 } else {
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2444 }
5e84e1a4
ZW		 2445 I915_WRITE(reg, temp);
2446
2447 reg = FDI_RX_CTL(pipe);
2448 temp = I915_READ(reg);
2449 if (HAS_PCH_CPT(dev)) {
2450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2452 } else {
2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_NONE;
2455 }
2456 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2457
2458 /* wait one idle pattern time */
2459 POSTING_READ(reg);
2460 udelay(1000);
357555c0
JB		 2461
2462 /* IVB wants error correction enabled */
2463 if (IS_IVYBRIDGE(dev))
2464 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2465 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2466}
2467
01a415fd
DV		 2468static void ivb_modeset_global_resources(struct drm_device *dev)
2469{
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
2477 /* When everything is off disable fdi C so that we could enable fdi B
2478 * with all lanes. XXX: This misses the case where a pipe is not using
2479 * any pch resources and so doesn't need any fdi lanes. */
2480 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2482 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2483
2484 temp = I915_READ(SOUTH_CHICKEN1);
2485 temp &= ~FDI_BC_BIFURCATION_SELECT;
2486 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487 I915_WRITE(SOUTH_CHICKEN1, temp);
2488 }
2489}
2490
8db9d77b
ZW		 2491/* The FDI link training functions for ILK/Ibexpeak. */
2492static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2493{
2494 struct drm_device *dev = crtc->dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497 int pipe = intel_crtc->pipe;
0fc932b8 2498 int plane = intel_crtc->plane;
5eddb70b 2499 u32 reg, temp, tries;
8db9d77b 2500
0fc932b8
JB		 2501 /* FDI needs bits from pipe & plane first */
2502 assert_pipe_enabled(dev_priv, pipe);
2503 assert_plane_enabled(dev_priv, plane);
2504
e1a44743
AJ		 2505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506 for train result */
5eddb70b
CW		 2507 reg = FDI_RX_IMR(pipe);
2508 temp = I915_READ(reg);
e1a44743
AJ		 2509 temp &= ~FDI_RX_SYMBOL_LOCK;
2510 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2511 I915_WRITE(reg, temp);
2512 I915_READ(reg);
e1a44743
AJ		 2513 udelay(150);
2514
8db9d77b 2515 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
77ffb597
AJ		 2518 temp &= ~(7 << 19);
2519 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2523
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(150);
2532
5b2adf89 2533 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2534 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2535 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2536 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2537
5eddb70b 2538 reg = FDI_RX_IIR(pipe);
e1a44743 2539 for (tries = 0; tries < 5; tries++) {
5eddb70b 2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2542
2543 if ((temp & FDI_RX_BIT_LOCK)) {
2544 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2545 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2546 break;
2547 }
8db9d77b 2548 }
e1a44743 2549 if (tries == 5)
5eddb70b 2550 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2551
2552 /* Train 2 */
5eddb70b
CW		 2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
8db9d77b
ZW		 2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2557 I915_WRITE(reg, temp);
8db9d77b 2558
5eddb70b
CW		 2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2563 I915_WRITE(reg, temp);
8db9d77b 2564
5eddb70b
CW		 2565 POSTING_READ(reg);
2566 udelay(150);
8db9d77b 2567
5eddb70b 2568 reg = FDI_RX_IIR(pipe);
e1a44743 2569 for (tries = 0; tries < 5; tries++) {
5eddb70b 2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2576 break;
2577 }
8db9d77b 2578 }
e1a44743 2579 if (tries == 5)
5eddb70b 2580 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2581
2582 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2583
8db9d77b
ZW		 2584}
2585
0206e353 2586static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2587 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2588 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2589 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2590 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2591};
2592
2593/* The FDI link training functions for SNB/Cougarpoint. */
2594static void gen6_fdi_link_train(struct drm_crtc *crtc)
2595{
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
fa37d39e 2600 u32 reg, temp, i, retry;
8db9d77b 2601
e1a44743
AJ		 2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603 for train result */
5eddb70b
CW		 2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
e1a44743
AJ		 2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
e1a44743
AJ		 2611 udelay(150);
2612
8db9d77b 2613 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2614 reg = FDI_TX_CTL(pipe);
2615 temp = I915_READ(reg);
77ffb597
AJ		 2616 temp &= ~(7 << 19);
2617 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_1;
2620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621 /* SNB-B */
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2624
d74cf324
DV		 2625 I915_WRITE(FDI_RX_MISC(pipe),
2626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
5eddb70b
CW		 2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
8db9d77b
ZW		 2630 if (HAS_PCH_CPT(dev)) {
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633 } else {
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1;
2636 }
5eddb70b
CW		 2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
8db9d77b
ZW		 2640 udelay(150);
2641
0206e353 2642 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
8db9d77b
ZW		 2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
8db9d77b
ZW		 2650 udelay(500);
2651
fa37d39e
SP		 2652 for (retry = 0; retry < 5; retry++) {
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656 if (temp & FDI_RX_BIT_LOCK) {
2657 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2659 break;
2660 }
2661 udelay(50);
8db9d77b 2662 }
fa37d39e
SP		 2663 if (retry < 5)
2664 break;
8db9d77b
ZW		 2665 }
2666 if (i == 4)
5eddb70b 2667 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2668
2669 /* Train 2 */
5eddb70b
CW		 2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
8db9d77b
ZW		 2672 temp &= ~FDI_LINK_TRAIN_NONE;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2;
2674 if (IS_GEN6(dev)) {
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 /* SNB-B */
2677 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678 }
5eddb70b 2679 I915_WRITE(reg, temp);
8db9d77b 2680
5eddb70b
CW		 2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
8db9d77b
ZW		 2683 if (HAS_PCH_CPT(dev)) {
2684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2686 } else {
2687 temp &= ~FDI_LINK_TRAIN_NONE;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2;
2689 }
5eddb70b
CW		 2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
8db9d77b
ZW		 2693 udelay(150);
2694
0206e353 2695 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
8db9d77b
ZW		 2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2700 I915_WRITE(reg, temp);
2701
2702 POSTING_READ(reg);
8db9d77b
ZW		 2703 udelay(500);
2704
fa37d39e
SP		 2705 for (retry = 0; retry < 5; retry++) {
2706 reg = FDI_RX_IIR(pipe);
2707 temp = I915_READ(reg);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712 break;
2713 }
2714 udelay(50);
8db9d77b 2715 }
fa37d39e
SP		 2716 if (retry < 5)
2717 break;
8db9d77b
ZW		 2718 }
2719 if (i == 4)
5eddb70b 2720 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2721
2722 DRM_DEBUG_KMS("FDI train done.\n");
2723}
2724
357555c0
JB		 2725/* Manual link training for Ivy Bridge A0 parts */
2726static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2727{
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp, i;
2733
2734 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2735 for train result */
2736 reg = FDI_RX_IMR(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_RX_SYMBOL_LOCK;
2739 temp &= ~FDI_RX_BIT_LOCK;
2740 I915_WRITE(reg, temp);
2741
2742 POSTING_READ(reg);
2743 udelay(150);
2744
01a415fd
DV		 2745 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746 I915_READ(FDI_RX_IIR(pipe)));
2747
357555c0
JB		 2748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(7 << 19);
2752 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2753 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2754 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2757 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2758 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759
d74cf324
DV		 2760 I915_WRITE(FDI_RX_MISC(pipe),
2761 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762
357555c0
JB		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~FDI_LINK_TRAIN_AUTO;
2766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2768 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2769 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(150);
2773
0206e353 2774 for (i = 0; i < 4; i++) {
357555c0
JB		 2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778 temp |= snb_b_fdi_train_param[i];
2779 I915_WRITE(reg, temp);
2780
2781 POSTING_READ(reg);
2782 udelay(500);
2783
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788 if (temp & FDI_RX_BIT_LOCK ||
2789 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2792 break;
2793 }
2794 }
2795 if (i == 4)
2796 DRM_ERROR("FDI train 1 fail!\n");
2797
2798 /* Train 2 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2802 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2803 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2804 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2805 I915_WRITE(reg, temp);
2806
2807 reg = FDI_RX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2811 I915_WRITE(reg, temp);
2812
2813 POSTING_READ(reg);
2814 udelay(150);
2815
0206e353 2816 for (i = 0; i < 4; i++) {
357555c0
JB		 2817 reg = FDI_TX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2820 temp |= snb_b_fdi_train_param[i];
2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(500);
2825
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830 if (temp & FDI_RX_SYMBOL_LOCK) {
2831 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2832 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2833 break;
2834 }
2835 }
2836 if (i == 4)
2837 DRM_ERROR("FDI train 2 fail!\n");
2838
2839 DRM_DEBUG_KMS("FDI train done.\n");
2840}
2841
88cefb6c 2842static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2843{
88cefb6c 2844 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2845 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2846 int pipe = intel_crtc->pipe;
5eddb70b 2847 u32 reg, temp;
79e53945 2848
c64e311e 2849
c98e9dcf 2850 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2854 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2856 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2857
2858 POSTING_READ(reg);
c98e9dcf
JB		 2859 udelay(200);
2860
2861 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2862 temp = I915_READ(reg);
2863 I915_WRITE(reg, temp | FDI_PCDCLK);
2864
2865 POSTING_READ(reg);
c98e9dcf
JB		 2866 udelay(200);
2867
20749730
PZ		 2868 /* Enable CPU FDI TX PLL, always on for Ironlake */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2872 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2873
20749730
PZ		 2874 POSTING_READ(reg);
2875 udelay(100);
6be4a607 2876 }
0e23b99d
JB		 2877}
2878
88cefb6c
DV		 2879static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880{
2881 struct drm_device *dev = intel_crtc->base.dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 int pipe = intel_crtc->pipe;
2884 u32 reg, temp;
2885
2886 /* Switch from PCDclk to Rawclk */
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890
2891 /* Disable CPU FDI TX PLL */
2892 reg = FDI_TX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2895
2896 POSTING_READ(reg);
2897 udelay(100);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902
2903 /* Wait for the clocks to turn off. */
2904 POSTING_READ(reg);
2905 udelay(100);
2906}
2907
0fc932b8
JB		 2908static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909{
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913 int pipe = intel_crtc->pipe;
2914 u32 reg, temp;
2915
2916 /* disable CPU FDI tx and PCH FDI rx */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2920 POSTING_READ(reg);
2921
2922 reg = FDI_RX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~(0x7 << 16);
dfd07d72 2925 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2926 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2927
2928 POSTING_READ(reg);
2929 udelay(100);
2930
2931 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2932 if (HAS_PCH_IBX(dev)) {
2933 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2934 }
0fc932b8
JB		 2935
2936 /* still set train pattern 1 */
2937 reg = FDI_TX_CTL(pipe);
2938 temp = I915_READ(reg);
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 I915_WRITE(reg, temp);
2942
2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 if (HAS_PCH_CPT(dev)) {
2946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 } else {
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 }
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp &= ~(0x07 << 16);
dfd07d72 2954 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959}
2960
5bb61643
CW		 2961static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962{
2963 struct drm_device *dev = crtc->dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2966 unsigned long flags;
2967 bool pending;
2968
10d83730
VS		 2969 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2970 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2971 return false;
2972
2973 spin_lock_irqsave(&dev->event_lock, flags);
2974 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2975 spin_unlock_irqrestore(&dev->event_lock, flags);
2976
2977 return pending;
2978}
2979
e6c3a2a6
CW		 2980static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981{
0f91128d 2982 struct drm_device *dev = crtc->dev;
5bb61643 2983 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2984
2985 if (crtc->fb == NULL)
2986 return;
2987
2c10d571
DV		 2988 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989
5bb61643
CW		 2990 wait_event(dev_priv->pending_flip_queue,
2991 !intel_crtc_has_pending_flip(crtc));
2992
0f91128d
CW		 2993 mutex_lock(&dev->struct_mutex);
2994 intel_finish_fb(crtc->fb);
2995 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2996}
2997
e615efe4
ED		 2998/* Program iCLKIP clock to the desired frequency */
2999static void lpt_program_iclkip(struct drm_crtc *crtc)
3000{
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3004 u32 temp;
3005
09153000
DV		 3006 mutex_lock(&dev_priv->dpio_lock);
3007
e615efe4
ED		 3008 /* It is necessary to ungate the pixclk gate prior to programming
3009 * the divisors, and gate it back when it is done.
3010 */
3011 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3012
3013 /* Disable SSCCTL */
3014 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3015 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3016 SBI_SSCCTL_DISABLE,
3017 SBI_ICLK);
e615efe4
ED		 3018
3019 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3020 if (crtc->mode.clock == 20000) {
3021 auxdiv = 1;
3022 divsel = 0x41;
3023 phaseinc = 0x20;
3024 } else {
3025 /* The iCLK virtual clock root frequency is in MHz,
3026 * but the crtc->mode.clock in in KHz. To get the divisors,
3027 * it is necessary to divide one by another, so we
3028 * convert the virtual clock precision to KHz here for higher
3029 * precision.
3030 */
3031 u32 iclk_virtual_root_freq = 172800 * 1000;
3032 u32 iclk_pi_range = 64;
3033 u32 desired_divisor, msb_divisor_value, pi_value;
3034
3035 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3036 msb_divisor_value = desired_divisor / iclk_pi_range;
3037 pi_value = desired_divisor % iclk_pi_range;
3038
3039 auxdiv = 0;
3040 divsel = msb_divisor_value - 2;
3041 phaseinc = pi_value;
3042 }
3043
3044 /* This should not happen with any sane values */
3045 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3046 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3048 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3049
3050 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3051 crtc->mode.clock,
3052 auxdiv,
3053 divsel,
3054 phasedir,
3055 phaseinc);
3056
3057 /* Program SSCDIVINTPHASE6 */
988d6ee8 3058 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3059 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3060 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3061 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3063 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3064 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3065 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3066
3067 /* Program SSCAUXDIV */
988d6ee8 3068 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3069 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3070 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3071 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3072
3073 /* Enable modulator and associated divider */
988d6ee8 3074 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3075 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3076 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3077
3078 /* Wait for initialization time */
3079 udelay(24);
3080
3081 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3082
3083 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3084}
3085
f67a559d
JB		 3086/*
3087 * Enable PCH resources required for PCH ports:
3088 * - PCH PLLs
3089 * - FDI training & RX/TX
3090 * - update transcoder timings
3091 * - DP transcoding bits
3092 * - transcoder
3093 */
3094static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3095{
3096 struct drm_device *dev = crtc->dev;
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3099 int pipe = intel_crtc->pipe;
ee7b9f93 3100 u32 reg, temp;
2c07245f 3101
e7e164db
CW		 3102 assert_transcoder_disabled(dev_priv, pipe);
3103
cd986abb
DV		 3104 /* Write the TU size bits before fdi link training, so that error
3105 * detection works. */
3106 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3107 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3108
c98e9dcf 3109 /* For PCH output, training FDI link */
674cf967 3110 dev_priv->display.fdi_link_train(crtc);
2c07245f 3111
572deb37
DV		 3112 /* XXX: pch pll's can be enabled any time before we enable the PCH
3113 * transcoder, and we actually should do this to not upset any PCH
3114 * transcoder that already use the clock when we share it.
3115 *
3116 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3117 * unconditionally resets the pll - we need that to have the right LVDS
3118 * enable sequence. */
b6b4e185 3119 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3120
303b81e0 3121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3122 u32 sel;
4b645f14 3123
c98e9dcf 3124 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3125 switch (pipe) {
3126 default:
3127 case 0:
3128 temp |= TRANSA_DPLL_ENABLE;
3129 sel = TRANSA_DPLLB_SEL;
3130 break;
3131 case 1:
3132 temp |= TRANSB_DPLL_ENABLE;
3133 sel = TRANSB_DPLLB_SEL;
3134 break;
3135 case 2:
3136 temp |= TRANSC_DPLL_ENABLE;
3137 sel = TRANSC_DPLLB_SEL;
3138 break;
d64311ab 3139 }
ee7b9f93
JB		 3140 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3141 temp |= sel;
3142 else
3143 temp &= ~sel;
c98e9dcf 3144 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3145 }
5eddb70b 3146
d9b6cb56
JB		 3147 /* set transcoder timing, panel must allow it */
3148 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3149 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3150 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3151 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3152
5eddb70b
CW		 3153 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3154 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3155 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3156 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3157
303b81e0 3158 intel_fdi_normal_train(crtc);
5e84e1a4 3159
c98e9dcf
JB		 3160 /* For PCH DP, enable TRANS_DP_CTL */
3161 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3162 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3163 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3164 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3165 reg = TRANS_DP_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3168 TRANS_DP_SYNC_MASK |
3169 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3170 temp |= (TRANS_DP_OUTPUT_ENABLE |
3171 TRANS_DP_ENH_FRAMING);
9325c9f0 3172 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3173
3174 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3175 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3176 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3177 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3178
3179 switch (intel_trans_dp_port_sel(crtc)) {
3180 case PCH_DP_B:
5eddb70b 3181 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3182 break;
3183 case PCH_DP_C:
5eddb70b 3184 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3185 break;
3186 case PCH_DP_D:
5eddb70b 3187 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3188 break;
3189 default:
e95d41e1 3190 BUG();
32f9d658 3191 }
2c07245f 3192
5eddb70b 3193 I915_WRITE(reg, temp);
6be4a607 3194 }
b52eb4dc 3195
b8a4f404 3196 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3197}
3198
1507e5bd
PZ		 3199static void lpt_pch_enable(struct drm_crtc *crtc)
3200{
3201 struct drm_device *dev = crtc->dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3204 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3205
daed2dbb 3206 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3207
8c52b5e8 3208 lpt_program_iclkip(crtc);
1507e5bd 3209
0540e488 3210 /* Set transcoder timing. */
daed2dbb
PZ		 3211 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3212 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3213 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3214
daed2dbb
PZ		 3215 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3216 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3217 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3218 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3219
937bb610 3220 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3221}
3222
ee7b9f93
JB		 3223static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3224{
3225 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3226
3227 if (pll == NULL)
3228 return;
3229
3230 if (pll->refcount == 0) {
3231 WARN(1, "bad PCH PLL refcount\n");
3232 return;
3233 }
3234
3235 --pll->refcount;
3236 intel_crtc->pch_pll = NULL;
3237}
3238
3239static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3240{
3241 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3242 struct intel_pch_pll *pll;
3243 int i;
3244
3245 pll = intel_crtc->pch_pll;
3246 if (pll) {
3247 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3248 intel_crtc->base.base.id, pll->pll_reg);
3249 goto prepare;
3250 }
3251
98b6bd99
DV		 3252 if (HAS_PCH_IBX(dev_priv->dev)) {
3253 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3254 i = intel_crtc->pipe;
3255 pll = &dev_priv->pch_plls[i];
3256
3257 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3258 intel_crtc->base.base.id, pll->pll_reg);
3259
3260 goto found;
3261 }
3262
ee7b9f93
JB		 3263 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3264 pll = &dev_priv->pch_plls[i];
3265
3266 /* Only want to check enabled timings first */
3267 if (pll->refcount == 0)
3268 continue;
3269
3270 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3271 fp == I915_READ(pll->fp0_reg)) {
3272 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3273 intel_crtc->base.base.id,
3274 pll->pll_reg, pll->refcount, pll->active);
3275
3276 goto found;
3277 }
3278 }
3279
3280 /* Ok no matching timings, maybe there's a free one? */
3281 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3282 pll = &dev_priv->pch_plls[i];
3283 if (pll->refcount == 0) {
3284 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3285 intel_crtc->base.base.id, pll->pll_reg);
3286 goto found;
3287 }
3288 }
3289
3290 return NULL;
3291
3292found:
3293 intel_crtc->pch_pll = pll;
3294 pll->refcount++;
3295 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3296prepare: /* separate function? */
3297 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3298
e04c7350
CW		 3299 /* Wait for the clocks to stabilize before rewriting the regs */
3300 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3301 POSTING_READ(pll->pll_reg);
3302 udelay(150);
e04c7350
CW		 3303
3304 I915_WRITE(pll->fp0_reg, fp);
3305 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3306 pll->on = false;
3307 return pll;
3308}
3309
d4270e57
JB		 3310void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3311{
3312 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3313 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3314 u32 temp;
3315
3316 temp = I915_READ(dslreg);
3317 udelay(500);
3318 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3319 if (wait_for(I915_READ(dslreg) != temp, 5))
3320 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3321 }
3322}
3323
f67a559d
JB		 3324static void ironlake_crtc_enable(struct drm_crtc *crtc)
3325{
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3329 struct intel_encoder *encoder;
f67a559d
JB		 3330 int pipe = intel_crtc->pipe;
3331 int plane = intel_crtc->plane;
3332 u32 temp;
f67a559d 3333
08a48469
DV		 3334 WARN_ON(!crtc->enabled);
3335
f67a559d
JB		 3336 if (intel_crtc->active)
3337 return;
3338
3339 intel_crtc->active = true;
3340 intel_update_watermarks(dev);
3341
3342 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3343 temp = I915_READ(PCH_LVDS);
3344 if ((temp & LVDS_PORT_EN) == 0)
3345 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3346 }
3347
f67a559d 3348
5bfe2ac0 3349 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3350 /* Note: FDI PLL enabling _must_ be done before we enable the
3351 * cpu pipes, hence this is separate from all the other fdi/pch
3352 * enabling. */
88cefb6c 3353 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3354 } else {
3355 assert_fdi_tx_disabled(dev_priv, pipe);
3356 assert_fdi_rx_disabled(dev_priv, pipe);
3357 }
f67a559d 3358
bf49ec8c
DV		 3359 for_each_encoder_on_crtc(dev, crtc, encoder)
3360 if (encoder->pre_enable)
3361 encoder->pre_enable(encoder);
f67a559d
JB		 3362
3363 /* Enable panel fitting for LVDS */
3364 if (dev_priv->pch_pf_size &&
547dc041
JN		 3365 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3366 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3367 /* Force use of hard-coded filter coefficients
3368 * as some pre-programmed values are broken,
3369 * e.g. x201.
3370 */
13888d78
PZ		 3371 if (IS_IVYBRIDGE(dev))
3372 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3373 PF_PIPE_SEL_IVB(pipe));
3374 else
3375 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3376 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3377 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3378 }
3379
9c54c0dd
JB		 3380 /*
3381 * On ILK+ LUT must be loaded before the pipe is running but with
3382 * clocks enabled
3383 */
3384 intel_crtc_load_lut(crtc);
3385
5bfe2ac0
DV		 3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3388 intel_enable_plane(dev_priv, plane, pipe);
3389
5bfe2ac0 3390 if (intel_crtc->config.has_pch_encoder)
f67a559d 3391 ironlake_pch_enable(crtc);
c98e9dcf 3392
d1ebd816 3393 mutex_lock(&dev->struct_mutex);
bed4a673 3394 intel_update_fbc(dev);
d1ebd816
BW		 3395 mutex_unlock(&dev->struct_mutex);
3396
6b383a7f 3397 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3398
fa5c73b1
DV		 3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 encoder->enable(encoder);
61b77ddd
DV		 3401
3402 if (HAS_PCH_CPT(dev))
3403 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3404
3405 /*
3406 * There seems to be a race in PCH platform hw (at least on some
3407 * outputs) where an enabled pipe still completes any pageflip right
3408 * away (as if the pipe is off) instead of waiting for vblank. As soon
3409 * as the first vblank happend, everything works as expected. Hence just
3410 * wait for one vblank before returning to avoid strange things
3411 * happening.
3412 */
3413 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3414}
3415
4f771f10
PZ		 3416static void haswell_crtc_enable(struct drm_crtc *crtc)
3417{
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 struct intel_encoder *encoder;
3422 int pipe = intel_crtc->pipe;
3423 int plane = intel_crtc->plane;
4f771f10
PZ		 3424
3425 WARN_ON(!crtc->enabled);
3426
3427 if (intel_crtc->active)
3428 return;
3429
3430 intel_crtc->active = true;
3431 intel_update_watermarks(dev);
3432
5bfe2ac0 3433 if (intel_crtc->config.has_pch_encoder)
04945641 3434 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3435
3436 for_each_encoder_on_crtc(dev, crtc, encoder)
3437 if (encoder->pre_enable)
3438 encoder->pre_enable(encoder);
3439
1f544388 3440 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3441
1f544388 3442 /* Enable panel fitting for eDP */
547dc041
JN		 3443 if (dev_priv->pch_pf_size &&
3444 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3445 /* Force use of hard-coded filter coefficients
3446 * as some pre-programmed values are broken,
3447 * e.g. x201.
3448 */
54075a7d
PZ		 3449 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3450 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3451 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3452 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3453 }
3454
3455 /*
3456 * On ILK+ LUT must be loaded before the pipe is running but with
3457 * clocks enabled
3458 */
3459 intel_crtc_load_lut(crtc);
3460
1f544388 3461 intel_ddi_set_pipe_settings(crtc);
8228c251 3462 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3463
5bfe2ac0
DV		 3464 intel_enable_pipe(dev_priv, pipe,
3465 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3466 intel_enable_plane(dev_priv, plane, pipe);
3467
5bfe2ac0 3468 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3469 lpt_pch_enable(crtc);
4f771f10
PZ		 3470
3471 mutex_lock(&dev->struct_mutex);
3472 intel_update_fbc(dev);
3473 mutex_unlock(&dev->struct_mutex);
3474
3475 intel_crtc_update_cursor(crtc, true);
3476
3477 for_each_encoder_on_crtc(dev, crtc, encoder)
3478 encoder->enable(encoder);
3479
4f771f10
PZ		 3480 /*
3481 * There seems to be a race in PCH platform hw (at least on some
3482 * outputs) where an enabled pipe still completes any pageflip right
3483 * away (as if the pipe is off) instead of waiting for vblank. As soon
3484 * as the first vblank happend, everything works as expected. Hence just
3485 * wait for one vblank before returning to avoid strange things
3486 * happening.
3487 */
3488 intel_wait_for_vblank(dev, intel_crtc->pipe);
3489}
3490
6be4a607
JB		 3491static void ironlake_crtc_disable(struct drm_crtc *crtc)
3492{
3493 struct drm_device *dev = crtc->dev;
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3496 struct intel_encoder *encoder;
6be4a607
JB		 3497 int pipe = intel_crtc->pipe;
3498 int plane = intel_crtc->plane;
5eddb70b 3499 u32 reg, temp;
b52eb4dc 3500
ef9c3aee 3501
f7abfe8b
CW		 3502 if (!intel_crtc->active)
3503 return;
3504
ea9d758d
DV		 3505 for_each_encoder_on_crtc(dev, crtc, encoder)
3506 encoder->disable(encoder);
3507
e6c3a2a6 3508 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3509 drm_vblank_off(dev, pipe);
6b383a7f 3510 intel_crtc_update_cursor(crtc, false);
5eddb70b 3511
b24e7179 3512 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3513
973d04f9
CW		 3514 if (dev_priv->cfb_plane == plane)
3515 intel_disable_fbc(dev);
2c07245f 3516
b24e7179 3517 intel_disable_pipe(dev_priv, pipe);
32f9d658 3518
6be4a607 3519 /* Disable PF */
9db4a9c7
JB		 3520 I915_WRITE(PF_CTL(pipe), 0);
3521 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3522
bf49ec8c
DV		 3523 for_each_encoder_on_crtc(dev, crtc, encoder)
3524 if (encoder->post_disable)
3525 encoder->post_disable(encoder);
2c07245f 3526
0fc932b8 3527 ironlake_fdi_disable(crtc);
249c0e64 3528
b8a4f404 3529 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3530
6be4a607
JB		 3531 if (HAS_PCH_CPT(dev)) {
3532 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3533 reg = TRANS_DP_CTL(pipe);
3534 temp = I915_READ(reg);
3535 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3536 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3537 I915_WRITE(reg, temp);
6be4a607
JB		 3538
3539 /* disable DPLL_SEL */
3540 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3541 switch (pipe) {
3542 case 0:
d64311ab 3543 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3544 break;
3545 case 1:
6be4a607 3546 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3547 break;
3548 case 2:
4b645f14 3549 /* C shares PLL A or B */
d64311ab 3550 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3551 break;
3552 default:
3553 BUG(); /* wtf */
3554 }
6be4a607 3555 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3556 }
e3421a18 3557
6be4a607 3558 /* disable PCH DPLL */
ee7b9f93 3559 intel_disable_pch_pll(intel_crtc);
8db9d77b 3560
88cefb6c 3561 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3562
f7abfe8b 3563 intel_crtc->active = false;
6b383a7f 3564 intel_update_watermarks(dev);
d1ebd816
BW		 3565
3566 mutex_lock(&dev->struct_mutex);
6b383a7f 3567 intel_update_fbc(dev);
d1ebd816 3568 mutex_unlock(&dev->struct_mutex);
6be4a607 3569}
1b3c7a47 3570
4f771f10 3571static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3572{
4f771f10
PZ		 3573 struct drm_device *dev = crtc->dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3576 struct intel_encoder *encoder;
3577 int pipe = intel_crtc->pipe;
3578 int plane = intel_crtc->plane;
ad80a810 3579 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee7b9f93 3580
4f771f10
PZ		 3581 if (!intel_crtc->active)
3582 return;
3583
3584 for_each_encoder_on_crtc(dev, crtc, encoder)
3585 encoder->disable(encoder);
3586
3587 intel_crtc_wait_for_pending_flips(crtc);
3588 drm_vblank_off(dev, pipe);
3589 intel_crtc_update_cursor(crtc, false);
3590
3591 intel_disable_plane(dev_priv, plane, pipe);
3592
3593 if (dev_priv->cfb_plane == plane)
3594 intel_disable_fbc(dev);
3595
3596 intel_disable_pipe(dev_priv, pipe);
3597
ad80a810 3598 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3599
3600 /* Disable PF */
3601 I915_WRITE(PF_CTL(pipe), 0);
3602 I915_WRITE(PF_WIN_SZ(pipe), 0);
3603
1f544388 3604 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3605
3606 for_each_encoder_on_crtc(dev, crtc, encoder)
3607 if (encoder->post_disable)
3608 encoder->post_disable(encoder);
3609
88adfff1 3610 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3611 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3612 intel_ddi_fdi_disable(crtc);
83616634 3613 }
4f771f10
PZ		 3614
3615 intel_crtc->active = false;
3616 intel_update_watermarks(dev);
3617
3618 mutex_lock(&dev->struct_mutex);
3619 intel_update_fbc(dev);
3620 mutex_unlock(&dev->struct_mutex);
3621}
3622
ee7b9f93
JB		 3623static void ironlake_crtc_off(struct drm_crtc *crtc)
3624{
3625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626 intel_put_pch_pll(intel_crtc);
3627}
3628
6441ab5f
PZ		 3629static void haswell_crtc_off(struct drm_crtc *crtc)
3630{
a5c961d1
PZ		 3631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632
3633 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3634 * start using it. */
1a240d4d 3635 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3636
6441ab5f
PZ		 3637 intel_ddi_put_crtc_pll(crtc);
3638}
3639
02e792fb
DV		 3640static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3641{
02e792fb 3642 if (!enable && intel_crtc->overlay) {
23f09ce3 3643 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3644 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3645
23f09ce3 3646 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3647 dev_priv->mm.interruptible = false;
3648 (void) intel_overlay_switch_off(intel_crtc->overlay);
3649 dev_priv->mm.interruptible = true;
23f09ce3 3650 mutex_unlock(&dev->struct_mutex);
02e792fb 3651 }
02e792fb 3652
5dcdbcb0
CW		 3653 /* Let userspace switch the overlay on again. In most cases userspace
3654 * has to recompute where to put it anyway.
3655 */
02e792fb
DV		 3656}
3657
61bc95c1
EE		 3658/**
3659 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3660 * cursor plane briefly if not already running after enabling the display
3661 * plane.
3662 * This workaround avoids occasional blank screens when self refresh is
3663 * enabled.
3664 */
3665static void
3666g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3667{
3668 u32 cntl = I915_READ(CURCNTR(pipe));
3669
3670 if ((cntl & CURSOR_MODE) == 0) {
3671 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3672
3673 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3674 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3675 intel_wait_for_vblank(dev_priv->dev, pipe);
3676 I915_WRITE(CURCNTR(pipe), cntl);
3677 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3678 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3679 }
3680}
3681
0b8765c6 3682static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3683{
3684 struct drm_device *dev = crtc->dev;
79e53945
JB		 3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3687 struct intel_encoder *encoder;
79e53945 3688 int pipe = intel_crtc->pipe;
80824003 3689 int plane = intel_crtc->plane;
79e53945 3690
08a48469
DV		 3691 WARN_ON(!crtc->enabled);
3692
f7abfe8b
CW		 3693 if (intel_crtc->active)
3694 return;
3695
3696 intel_crtc->active = true;
6b383a7f
CW		 3697 intel_update_watermarks(dev);
3698
63d7bbe9 3699 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3700
3701 for_each_encoder_on_crtc(dev, crtc, encoder)
3702 if (encoder->pre_enable)
3703 encoder->pre_enable(encoder);
3704
040484af 3705 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3706 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3707 if (IS_G4X(dev))
3708 g4x_fixup_plane(dev_priv, pipe);
79e53945 3709
0b8765c6 3710 intel_crtc_load_lut(crtc);
bed4a673 3711 intel_update_fbc(dev);
79e53945 3712
0b8765c6
JB		 3713 /* Give the overlay scaler a chance to enable if it's on this pipe */
3714 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3715 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3716
fa5c73b1
DV		 3717 for_each_encoder_on_crtc(dev, crtc, encoder)
3718 encoder->enable(encoder);
0b8765c6 3719}
79e53945 3720
0b8765c6
JB		 3721static void i9xx_crtc_disable(struct drm_crtc *crtc)
3722{
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3726 struct intel_encoder *encoder;
0b8765c6
JB		 3727 int pipe = intel_crtc->pipe;
3728 int plane = intel_crtc->plane;
24a1f16d 3729 u32 pctl;
b690e96c 3730
ef9c3aee 3731
f7abfe8b
CW		 3732 if (!intel_crtc->active)
3733 return;
3734
ea9d758d
DV		 3735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 encoder->disable(encoder);
3737
0b8765c6 3738 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3739 intel_crtc_wait_for_pending_flips(crtc);
3740 drm_vblank_off(dev, pipe);
0b8765c6 3741 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3742 intel_crtc_update_cursor(crtc, false);
0b8765c6 3743
973d04f9
CW		 3744 if (dev_priv->cfb_plane == plane)
3745 intel_disable_fbc(dev);
79e53945 3746
b24e7179 3747 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3748 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3749
3750 /* Disable pannel fitter if it is on this pipe. */
3751 pctl = I915_READ(PFIT_CONTROL);
3752 if ((pctl & PFIT_ENABLE) &&
3753 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3754 I915_WRITE(PFIT_CONTROL, 0);
3755
63d7bbe9 3756 intel_disable_pll(dev_priv, pipe);
0b8765c6 3757
f7abfe8b 3758 intel_crtc->active = false;
6b383a7f
CW		 3759 intel_update_fbc(dev);
3760 intel_update_watermarks(dev);
0b8765c6
JB		 3761}
3762
ee7b9f93
JB		 3763static void i9xx_crtc_off(struct drm_crtc *crtc)
3764{
3765}
3766
976f8a20
DV		 3767static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3768 bool enabled)
2c07245f
ZW		 3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_master_private *master_priv;
3772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773 int pipe = intel_crtc->pipe;
79e53945
JB		 3774
3775 if (!dev->primary->master)
3776 return;
3777
3778 master_priv = dev->primary->master->driver_priv;
3779 if (!master_priv->sarea_priv)
3780 return;
3781
79e53945
JB		 3782 switch (pipe) {
3783 case 0:
3784 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3785 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3786 break;
3787 case 1:
3788 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3789 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3790 break;
3791 default:
9db4a9c7 3792 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3793 break;
3794 }
79e53945
JB		 3795}
3796
976f8a20
DV		 3797/**
3798 * Sets the power management mode of the pipe and plane.
3799 */
3800void intel_crtc_update_dpms(struct drm_crtc *crtc)
3801{
3802 struct drm_device *dev = crtc->dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct intel_encoder *intel_encoder;
3805 bool enable = false;
3806
3807 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3808 enable |= intel_encoder->connectors_active;
3809
3810 if (enable)
3811 dev_priv->display.crtc_enable(crtc);
3812 else
3813 dev_priv->display.crtc_disable(crtc);
3814
3815 intel_crtc_update_sarea(crtc, enable);
3816}
3817
cdd59983
CW		 3818static void intel_crtc_disable(struct drm_crtc *crtc)
3819{
cdd59983 3820 struct drm_device *dev = crtc->dev;
976f8a20 3821 struct drm_connector *connector;
ee7b9f93 3822 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3824
976f8a20
DV		 3825 /* crtc should still be enabled when we disable it. */
3826 WARN_ON(!crtc->enabled);
3827
7b9f35a6 3828 intel_crtc->eld_vld = false;
976f8a20
DV		 3829 dev_priv->display.crtc_disable(crtc);
3830 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3831 dev_priv->display.off(crtc);
3832
931872fc
CW		 3833 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3834 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3835
3836 if (crtc->fb) {
3837 mutex_lock(&dev->struct_mutex);
1690e1eb 3838 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3839 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3840 crtc->fb = NULL;
3841 }
3842
3843 /* Update computed state. */
3844 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3845 if (!connector->encoder || !connector->encoder->crtc)
3846 continue;
3847
3848 if (connector->encoder->crtc != crtc)
3849 continue;
3850
3851 connector->dpms = DRM_MODE_DPMS_OFF;
3852 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3853 }
3854}
3855
a261b246 3856void intel_modeset_disable(struct drm_device *dev)
79e53945 3857{
a261b246
DV		 3858 struct drm_crtc *crtc;
3859
3860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3861 if (crtc->enabled)
3862 intel_crtc_disable(crtc);
3863 }
79e53945
JB		 3864}
3865
ea5b213a 3866void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3867{
4ef69c7a 3868 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3869
ea5b213a
CW		 3870 drm_encoder_cleanup(encoder);
3871 kfree(intel_encoder);
7e7d76c3
JB		 3872}
3873
5ab432ef
DV		 3874/* Simple dpms helper for encodres with just one connector, no cloning and only
3875 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3876 * state of the entire output pipe. */
3877void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3878{
5ab432ef
DV		 3879 if (mode == DRM_MODE_DPMS_ON) {
3880 encoder->connectors_active = true;
3881
b2cabb0e 3882 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3883 } else {
3884 encoder->connectors_active = false;
3885
b2cabb0e 3886 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3887 }
79e53945
JB		 3888}
3889
0a91ca29
DV		 3890/* Cross check the actual hw state with our own modeset state tracking (and it's
3891 * internal consistency). */
b980514c 3892static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3893{
0a91ca29
DV		 3894 if (connector->get_hw_state(connector)) {
3895 struct intel_encoder *encoder = connector->encoder;
3896 struct drm_crtc *crtc;
3897 bool encoder_enabled;
3898 enum pipe pipe;
3899
3900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3901 connector->base.base.id,
3902 drm_get_connector_name(&connector->base));
3903
3904 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3905 "wrong connector dpms state\n");
3906 WARN(connector->base.encoder != &encoder->base,
3907 "active connector not linked to encoder\n");
3908 WARN(!encoder->connectors_active,
3909 "encoder->connectors_active not set\n");
3910
3911 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3912 WARN(!encoder_enabled, "encoder not enabled\n");
3913 if (WARN_ON(!encoder->base.crtc))
3914 return;
3915
3916 crtc = encoder->base.crtc;
3917
3918 WARN(!crtc->enabled, "crtc not enabled\n");
3919 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3920 WARN(pipe != to_intel_crtc(crtc)->pipe,
3921 "encoder active on the wrong pipe\n");
3922 }
79e53945
JB		 3923}
3924
5ab432ef
DV		 3925/* Even simpler default implementation, if there's really no special case to
3926 * consider. */
3927void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3928{
5ab432ef 3929 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3930
5ab432ef
DV		 3931 /* All the simple cases only support two dpms states. */
3932 if (mode != DRM_MODE_DPMS_ON)
3933 mode = DRM_MODE_DPMS_OFF;
d4270e57 3934
5ab432ef
DV		 3935 if (mode == connector->dpms)
3936 return;
3937
3938 connector->dpms = mode;
3939
3940 /* Only need to change hw state when actually enabled */
3941 if (encoder->base.crtc)
3942 intel_encoder_dpms(encoder, mode);
3943 else
8af6cf88 3944 WARN_ON(encoder->connectors_active != false);
0a91ca29 3945
b980514c 3946 intel_modeset_check_state(connector->dev);
79e53945
JB		 3947}
3948
f0947c37
DV		 3949/* Simple connector->get_hw_state implementation for encoders that support only
3950 * one connector and no cloning and hence the encoder state determines the state
3951 * of the connector. */
3952bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3953{
24929352 3954 enum pipe pipe = 0;
f0947c37 3955 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3956
f0947c37 3957 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3958}
3959
b8cecdf5
DV		 3960static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3961 struct intel_crtc_config *pipe_config)
79e53945 3962{
2c07245f 3963 struct drm_device *dev = crtc->dev;
b8cecdf5 3964 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3965
bad720ff 3966 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3967 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3968 if (pipe_config->requested_mode.clock * 3
3969 > IRONLAKE_FDI_FREQ * 4)
2377b741 3970 return false;
2c07245f 3971 }
89749350 3972
f9bef081
DV		 3973 /* All interlaced capable intel hw wants timings in frames. Note though
3974 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3975 * timings, so we need to be careful not to clobber these.*/
7ae89233 3976 if (!pipe_config->timings_set)
f9bef081 3977 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3978
44f46b42
CW		 3979 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3980 * with a hsync front porch of 0.
3981 */
3982 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3983 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3984 return false;
3985
5d2d38dd
DV		 3986 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3987 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3988 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3989 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3990 * for lvds. */
3991 pipe_config->pipe_bpp = 8*3;
3992 }
3993
79e53945
JB		 3994 return true;
3995}
3996
25eb05fc
JB		 3997static int valleyview_get_display_clock_speed(struct drm_device *dev)
3998{
3999 return 400000; /* FIXME */
4000}
4001
e70236a8
JB		 4002static int i945_get_display_clock_speed(struct drm_device *dev)
4003{
4004 return 400000;
4005}
79e53945 4006
e70236a8 4007static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4008{
e70236a8
JB		 4009 return 333000;
4010}
79e53945 4011
e70236a8
JB		 4012static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4013{
4014 return 200000;
4015}
79e53945 4016
e70236a8
JB		 4017static int i915gm_get_display_clock_speed(struct drm_device *dev)
4018{
4019 u16 gcfgc = 0;
79e53945 4020
e70236a8
JB		 4021 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4022
4023 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4024 return 133000;
4025 else {
4026 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4027 case GC_DISPLAY_CLOCK_333_MHZ:
4028 return 333000;
4029 default:
4030 case GC_DISPLAY_CLOCK_190_200_MHZ:
4031 return 190000;
79e53945 4032 }
e70236a8
JB		 4033 }
4034}
4035
4036static int i865_get_display_clock_speed(struct drm_device *dev)
4037{
4038 return 266000;
4039}
4040
4041static int i855_get_display_clock_speed(struct drm_device *dev)
4042{
4043 u16 hpllcc = 0;
4044 /* Assume that the hardware is in the high speed state. This
4045 * should be the default.
4046 */
4047 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4048 case GC_CLOCK_133_200:
4049 case GC_CLOCK_100_200:
4050 return 200000;
4051 case GC_CLOCK_166_250:
4052 return 250000;
4053 case GC_CLOCK_100_133:
79e53945 4054 return 133000;
e70236a8 4055 }
79e53945 4056
e70236a8
JB		 4057 /* Shouldn't happen */
4058 return 0;
4059}
79e53945 4060
e70236a8
JB		 4061static int i830_get_display_clock_speed(struct drm_device *dev)
4062{
4063 return 133000;
79e53945
JB		 4064}
4065
2c07245f 4066static void
e69d0bc1 4067intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4068{
4069 while (*num > 0xffffff || *den > 0xffffff) {
4070 *num >>= 1;
4071 *den >>= 1;
4072 }
4073}
4074
e69d0bc1
DV		 4075void
4076intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4077 int pixel_clock, int link_clock,
4078 struct intel_link_m_n *m_n)
2c07245f 4079{
e69d0bc1 4080 m_n->tu = 64;
22ed1113
CW		 4081 m_n->gmch_m = bits_per_pixel * pixel_clock;
4082 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4083 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4084 m_n->link_m = pixel_clock;
4085 m_n->link_n = link_clock;
e69d0bc1 4086 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4087}
4088
a7615030
CW		 4089static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4090{
72bbe58c
KP		 4091 if (i915_panel_use_ssc >= 0)
4092 return i915_panel_use_ssc != 0;
4093 return dev_priv->lvds_use_ssc
435793df 4094 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4095}
4096
a0c4da24
JB		 4097static int vlv_get_refclk(struct drm_crtc *crtc)
4098{
4099 struct drm_device *dev = crtc->dev;
4100 struct drm_i915_private *dev_priv = dev->dev_private;
4101 int refclk = 27000; /* for DP & HDMI */
4102
4103 return 100000; /* only one validated so far */
4104
4105 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4106 refclk = 96000;
4107 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4108 if (intel_panel_use_ssc(dev_priv))
4109 refclk = 100000;
4110 else
4111 refclk = 96000;
4112 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4113 refclk = 100000;
4114 }
4115
4116 return refclk;
4117}
4118
c65d77d8
JB		 4119static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4120{
4121 struct drm_device *dev = crtc->dev;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 int refclk;
4124
a0c4da24
JB		 4125 if (IS_VALLEYVIEW(dev)) {
4126 refclk = vlv_get_refclk(crtc);
4127 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4128 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4129 refclk = dev_priv->lvds_ssc_freq * 1000;
4130 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4131 refclk / 1000);
4132 } else if (!IS_GEN2(dev)) {
4133 refclk = 96000;
4134 } else {
4135 refclk = 48000;
4136 }
4137
4138 return refclk;
4139}
4140
f47709a9 4141static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4142{
f47709a9
DV		 4143 unsigned dotclock = crtc->config.adjusted_mode.clock;
4144 struct dpll *clock = &crtc->config.dpll;
4145
c65d77d8
JB		 4146 /* SDVO TV has fixed PLL values depend on its clock range,
4147 this mirrors vbios setting. */
f47709a9 4148 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4149 clock->p1 = 2;
4150 clock->p2 = 10;
4151 clock->n = 3;
4152 clock->m1 = 16;
4153 clock->m2 = 8;
f47709a9 4154 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4155 clock->p1 = 1;
4156 clock->p2 = 10;
4157 clock->n = 6;
4158 clock->m1 = 12;
4159 clock->m2 = 8;
4160 }
f47709a9
DV		 4161
4162 crtc->config.clock_set = true;
c65d77d8
JB		 4163}
4164
f47709a9 4165static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4166 intel_clock_t *reduced_clock)
4167{
f47709a9 4168 struct drm_device *dev = crtc->base.dev;
a7516a05 4169 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4170 int pipe = crtc->pipe;
a7516a05 4171 u32 fp, fp2 = 0;
f47709a9 4172 struct dpll *clock = &crtc->config.dpll;
a7516a05
JB		 4173
4174 if (IS_PINEVIEW(dev)) {
4175 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4176 if (reduced_clock)
4177 fp2 = (1 << reduced_clock->n) << 16 |
4178 reduced_clock->m1 << 8 | reduced_clock->m2;
4179 } else {
4180 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4181 if (reduced_clock)
4182 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4183 reduced_clock->m2;
4184 }
4185
4186 I915_WRITE(FP0(pipe), fp);
4187
f47709a9
DV		 4188 crtc->lowfreq_avail = false;
4189 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4190 reduced_clock && i915_powersave) {
4191 I915_WRITE(FP1(pipe), fp2);
f47709a9 4192 crtc->lowfreq_avail = true;
a7516a05
JB		 4193 } else {
4194 I915_WRITE(FP1(pipe), fp);
4195 }
4196}
4197
03afc4a2
DV		 4198static void intel_dp_set_m_n(struct intel_crtc *crtc)
4199{
4200 if (crtc->config.has_pch_encoder)
4201 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4202 else
4203 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4204}
4205
f47709a9 4206static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4207{
f47709a9 4208 struct drm_device *dev = crtc->base.dev;
a0c4da24 4209 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4210 int pipe = crtc->pipe;
a0c4da24
JB		 4211 u32 dpll, mdiv, pdiv;
4212 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4213 bool is_sdvo;
4214 u32 temp;
a0c4da24 4215
09153000
DV		 4216 mutex_lock(&dev_priv->dpio_lock);
4217
f47709a9
DV		 4218 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4219 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4220
2a8f64ca
VP		 4221 dpll = DPLL_VGA_MODE_DIS;
4222 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4223 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4224 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4225
4226 I915_WRITE(DPLL(pipe), dpll);
4227 POSTING_READ(DPLL(pipe));
a0c4da24 4228
f47709a9
DV		 4229 bestn = crtc->config.dpll.n;
4230 bestm1 = crtc->config.dpll.m1;
4231 bestm2 = crtc->config.dpll.m2;
4232 bestp1 = crtc->config.dpll.p1;
4233 bestp2 = crtc->config.dpll.p2;
a0c4da24 4234
2a8f64ca
VP		 4235 /*
4236 * In Valleyview PLL and program lane counter registers are exposed
4237 * through DPIO interface
4238 */
a0c4da24
JB		 4239 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4240 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4241 mdiv |= ((bestn << DPIO_N_SHIFT));
4242 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4243 mdiv |= (1 << DPIO_K_SHIFT);
4244 mdiv |= DPIO_ENABLE_CALIBRATION;
4245 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4246
4247 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4248
2a8f64ca 4249 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4250 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4251 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4252 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4253 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4254
2a8f64ca 4255 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4256
4257 dpll |= DPLL_VCO_ENABLE;
4258 I915_WRITE(DPLL(pipe), dpll);
4259 POSTING_READ(DPLL(pipe));
4260 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4261 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4262
2a8f64ca
VP		 4263 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4264
f47709a9
DV		 4265 if (crtc->config.has_dp_encoder)
4266 intel_dp_set_m_n(crtc);
2a8f64ca
VP		 4267
4268 I915_WRITE(DPLL(pipe), dpll);
4269
4270 /* Wait for the clocks to stabilize. */
4271 POSTING_READ(DPLL(pipe));
4272 udelay(150);
a0c4da24 4273
2a8f64ca
VP		 4274 temp = 0;
4275 if (is_sdvo) {
6cc5f341 4276 temp = 0;
f47709a9
DV		 4277 if (crtc->config.pixel_multiplier > 1) {
4278 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4279 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4280 }
a0c4da24 4281 }
2a8f64ca
VP		 4282 I915_WRITE(DPLL_MD(pipe), temp);
4283 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4284
2a8f64ca 4285 /* Now program lane control registers */
f47709a9
DV		 4286 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4287 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
2a8f64ca
VP		 4288 temp = 0x1000C4;
4289 if(pipe == 1)
4290 temp |= (1 << 21);
4291 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4292 }
f47709a9
DV		 4293
4294 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
2a8f64ca
VP		 4295 temp = 0x1000C4;
4296 if(pipe == 1)
4297 temp |= (1 << 21);
4298 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4299 }
09153000
DV		 4300
4301 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4302}
4303
f47709a9
DV		 4304static void i9xx_update_pll(struct intel_crtc *crtc,
4305 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4306 int num_connectors)
4307{
f47709a9 4308 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4309 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4310 struct intel_encoder *encoder;
f47709a9 4311 int pipe = crtc->pipe;
eb1cbe48
DV		 4312 u32 dpll;
4313 bool is_sdvo;
f47709a9 4314 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4315
f47709a9 4316 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4317
f47709a9
DV		 4318 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4319 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4320
4321 dpll = DPLL_VGA_MODE_DIS;
4322
f47709a9 4323 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4324 dpll |= DPLLB_MODE_LVDS;
4325 else
4326 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4327
eb1cbe48 4328 if (is_sdvo) {
f47709a9 4329 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4330 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4331 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4332 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4333 }
4334 dpll |= DPLL_DVO_HIGH_SPEED;
4335 }
f47709a9 4336 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4337 dpll |= DPLL_DVO_HIGH_SPEED;
4338
4339 /* compute bitmask from p1 value */
4340 if (IS_PINEVIEW(dev))
4341 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4342 else {
4343 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4344 if (IS_G4X(dev) && reduced_clock)
4345 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4346 }
4347 switch (clock->p2) {
4348 case 5:
4349 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4350 break;
4351 case 7:
4352 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4353 break;
4354 case 10:
4355 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4356 break;
4357 case 14:
4358 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4359 break;
4360 }
4361 if (INTEL_INFO(dev)->gen >= 4)
4362 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4363
f47709a9 4364 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4365 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4366 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4367 /* XXX: just matching BIOS for now */
4368 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4369 dpll |= 3;
f47709a9 4370 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4371 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4372 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4373 else
4374 dpll |= PLL_REF_INPUT_DREFCLK;
4375
4376 dpll |= DPLL_VCO_ENABLE;
4377 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4378 POSTING_READ(DPLL(pipe));
4379 udelay(150);
4380
f47709a9 4381 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4382 if (encoder->pre_pll_enable)
4383 encoder->pre_pll_enable(encoder);
eb1cbe48 4384
f47709a9
DV		 4385 if (crtc->config.has_dp_encoder)
4386 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4387
4388 I915_WRITE(DPLL(pipe), dpll);
4389
4390 /* Wait for the clocks to stabilize. */
4391 POSTING_READ(DPLL(pipe));
4392 udelay(150);
4393
4394 if (INTEL_INFO(dev)->gen >= 4) {
4395 u32 temp = 0;
4396 if (is_sdvo) {
6cc5f341 4397 temp = 0;
f47709a9
DV		 4398 if (crtc->config.pixel_multiplier > 1) {
4399 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4400 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4401 }
eb1cbe48
DV		 4402 }
4403 I915_WRITE(DPLL_MD(pipe), temp);
4404 } else {
4405 /* The pixel multiplier can only be updated once the
4406 * DPLL is enabled and the clocks are stable.
4407 *
4408 * So write it again.
4409 */
4410 I915_WRITE(DPLL(pipe), dpll);
4411 }
4412}
4413
f47709a9 4414static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4415 struct drm_display_mode *adjusted_mode,
f47709a9 4416 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4417 int num_connectors)
4418{
f47709a9 4419 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4420 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4421 struct intel_encoder *encoder;
f47709a9 4422 int pipe = crtc->pipe;
eb1cbe48 4423 u32 dpll;
f47709a9 4424 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4425
f47709a9 4426 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4427
eb1cbe48
DV		 4428 dpll = DPLL_VGA_MODE_DIS;
4429
f47709a9 4430 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4431 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4432 } else {
4433 if (clock->p1 == 2)
4434 dpll |= PLL_P1_DIVIDE_BY_TWO;
4435 else
4436 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4437 if (clock->p2 == 4)
4438 dpll |= PLL_P2_DIVIDE_BY_4;
4439 }
4440
f47709a9 4441 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4442 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4443 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4444 else
4445 dpll |= PLL_REF_INPUT_DREFCLK;
4446
4447 dpll |= DPLL_VCO_ENABLE;
4448 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4449 POSTING_READ(DPLL(pipe));
4450 udelay(150);
4451
f47709a9 4452 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4453 if (encoder->pre_pll_enable)
4454 encoder->pre_pll_enable(encoder);
eb1cbe48 4455
5b5896e4
DV		 4456 I915_WRITE(DPLL(pipe), dpll);
4457
4458 /* Wait for the clocks to stabilize. */
4459 POSTING_READ(DPLL(pipe));
4460 udelay(150);
4461
eb1cbe48
DV		 4462 /* The pixel multiplier can only be updated once the
4463 * DPLL is enabled and the clocks are stable.
4464 *
4465 * So write it again.
4466 */
4467 I915_WRITE(DPLL(pipe), dpll);
4468}
4469
b0e77b9c
PZ		 4470static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4471 struct drm_display_mode *mode,
4472 struct drm_display_mode *adjusted_mode)
4473{
4474 struct drm_device *dev = intel_crtc->base.dev;
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4477 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4478 uint32_t vsyncshift;
4479
4480 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4481 /* the chip adds 2 halflines automatically */
4482 adjusted_mode->crtc_vtotal -= 1;
4483 adjusted_mode->crtc_vblank_end -= 1;
4484 vsyncshift = adjusted_mode->crtc_hsync_start
4485 - adjusted_mode->crtc_htotal / 2;
4486 } else {
4487 vsyncshift = 0;
4488 }
4489
4490 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4491 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4492
fe2b8f9d 4493 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4494 (adjusted_mode->crtc_hdisplay - 1) |
4495 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4496 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4497 (adjusted_mode->crtc_hblank_start - 1) |
4498 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4499 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4500 (adjusted_mode->crtc_hsync_start - 1) |
4501 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4502
fe2b8f9d 4503 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4504 (adjusted_mode->crtc_vdisplay - 1) |
4505 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4506 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4507 (adjusted_mode->crtc_vblank_start - 1) |
4508 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4509 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4510 (adjusted_mode->crtc_vsync_start - 1) |
4511 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4512
b5e508d4
PZ		 4513 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4514 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4515 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4516 * bits. */
4517 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4518 (pipe == PIPE_B || pipe == PIPE_C))
4519 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4520
b0e77b9c
PZ		 4521 /* pipesrc controls the size that is scaled from, which should
4522 * always be the user's requested size.
4523 */
4524 I915_WRITE(PIPESRC(pipe),
4525 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4526}
4527
84b046f3
DV		 4528static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4529{
4530 struct drm_device *dev = intel_crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 uint32_t pipeconf;
4533
4534 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4535
4536 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4537 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4538 * core speed.
4539 *
4540 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4541 * pipe == 0 check?
4542 */
4543 if (intel_crtc->config.requested_mode.clock >
4544 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4545 pipeconf |= PIPECONF_DOUBLE_WIDE;
4546 else
4547 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4548 }
4549
4550 /* default to 8bpc */
4551 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4552 if (intel_crtc->config.has_dp_encoder) {
4553 if (intel_crtc->config.dither) {
4554 pipeconf |= PIPECONF_6BPC |
4555 PIPECONF_DITHER_EN |
4556 PIPECONF_DITHER_TYPE_SP;
4557 }
4558 }
4559
4560 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4561 INTEL_OUTPUT_EDP)) {
4562 if (intel_crtc->config.dither) {
4563 pipeconf |= PIPECONF_6BPC |
4564 PIPECONF_ENABLE |
4565 I965_PIPECONF_ACTIVE;
4566 }
4567 }
4568
4569 if (HAS_PIPE_CXSR(dev)) {
4570 if (intel_crtc->lowfreq_avail) {
4571 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4572 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4573 } else {
4574 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4575 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4576 }
4577 }
4578
4579 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4580 if (!IS_GEN2(dev) &&
4581 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4582 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4583 else
4584 pipeconf |= PIPECONF_PROGRESSIVE;
4585
9c8e09b7
VS		 4586 if (IS_VALLEYVIEW(dev)) {
4587 if (intel_crtc->config.limited_color_range)
4588 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4589 else
4590 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4591 }
4592
84b046f3
DV		 4593 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4594 POSTING_READ(PIPECONF(intel_crtc->pipe));
4595}
4596
f564048e 4597static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4598 int x, int y,
94352cf9 4599 struct drm_framebuffer *fb)
79e53945
JB		 4600{
4601 struct drm_device *dev = crtc->dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4604 struct drm_display_mode *adjusted_mode =
4605 &intel_crtc->config.adjusted_mode;
4606 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4607 int pipe = intel_crtc->pipe;
80824003 4608 int plane = intel_crtc->plane;
c751ce4f 4609 int refclk, num_connectors = 0;
652c393a 4610 intel_clock_t clock, reduced_clock;
84b046f3 4611 u32 dspcntr;
eb1cbe48 4612 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4613 bool is_lvds = false, is_tv = false;
5eddb70b 4614 struct intel_encoder *encoder;
d4906093 4615 const intel_limit_t *limit;
5c3b82e2 4616 int ret;
79e53945 4617
6c2b7c12 4618 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4619 switch (encoder->type) {
79e53945
JB		 4620 case INTEL_OUTPUT_LVDS:
4621 is_lvds = true;
4622 break;
4623 case INTEL_OUTPUT_SDVO:
7d57382e 4624 case INTEL_OUTPUT_HDMI:
79e53945 4625 is_sdvo = true;
5eddb70b 4626 if (encoder->needs_tv_clock)
e2f0ba97 4627 is_tv = true;
79e53945 4628 break;
79e53945
JB		 4629 case INTEL_OUTPUT_TVOUT:
4630 is_tv = true;
4631 break;
79e53945 4632 }
43565a06 4633
c751ce4f 4634 num_connectors++;
79e53945
JB		 4635 }
4636
c65d77d8 4637 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4638
d4906093
ML		 4639 /*
4640 * Returns a set of divisors for the desired target clock with the given
4641 * refclk, or FALSE. The returned values represent the clock equation:
4642 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4643 */
1b894b59 4644 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4645 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4646 &clock);
79e53945
JB		 4647 if (!ok) {
4648 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4649 return -EINVAL;
79e53945
JB		 4650 }
4651
cda4b7d3 4652 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4653 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4654
ddc9003c 4655 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4656 /*
4657 * Ensure we match the reduced clock's P to the target clock.
4658 * If the clocks don't match, we can't switch the display clock
4659 * by using the FP0/FP1. In such case we will disable the LVDS
4660 * downclock feature.
4661 */
ddc9003c 4662 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4663 dev_priv->lvds_downclock,
4664 refclk,
cec2f356 4665 &clock,
5eddb70b 4666 &reduced_clock);
7026d4ac 4667 }
f47709a9
DV		 4668 /* Compat-code for transition, will disappear. */
4669 if (!intel_crtc->config.clock_set) {
4670 intel_crtc->config.dpll.n = clock.n;
4671 intel_crtc->config.dpll.m1 = clock.m1;
4672 intel_crtc->config.dpll.m2 = clock.m2;
4673 intel_crtc->config.dpll.p1 = clock.p1;
4674 intel_crtc->config.dpll.p2 = clock.p2;
4675 }
7026d4ac 4676
c65d77d8 4677 if (is_sdvo && is_tv)
f47709a9 4678 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4679
eb1cbe48 4680 if (IS_GEN2(dev))
f47709a9 4681 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4682 has_reduced_clock ? &reduced_clock : NULL,
4683 num_connectors);
a0c4da24 4684 else if (IS_VALLEYVIEW(dev))
f47709a9 4685 vlv_update_pll(intel_crtc);
79e53945 4686 else
f47709a9 4687 i9xx_update_pll(intel_crtc,
eb1cbe48
DV		 4688 has_reduced_clock ? &reduced_clock : NULL,
4689 num_connectors);
79e53945 4690
79e53945
JB		 4691 /* Set up the display plane register */
4692 dspcntr = DISPPLANE_GAMMA_ENABLE;
4693
da6ecc5d
JB		 4694 if (!IS_VALLEYVIEW(dev)) {
4695 if (pipe == 0)
4696 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4697 else
4698 dspcntr |= DISPPLANE_SEL_PIPE_B;
4699 }
79e53945 4700
28c97730 4701 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4702 drm_mode_debug_printmodeline(mode);
4703
b0e77b9c 4704 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4705
4706 /* pipesrc and dspsize control the size that is scaled from,
4707 * which should always be the user's requested size.
79e53945 4708 */
929c77fb
EA		 4709 I915_WRITE(DSPSIZE(plane),
4710 ((mode->vdisplay - 1) << 16) |
4711 (mode->hdisplay - 1));
4712 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4713
84b046f3
DV		 4714 i9xx_set_pipeconf(intel_crtc);
4715
929c77fb 4716 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4717
4718 intel_wait_for_vblank(dev, pipe);
4719
f564048e
EA		 4720 I915_WRITE(DSPCNTR(plane), dspcntr);
4721 POSTING_READ(DSPCNTR(plane));
4722
94352cf9 4723 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4724
4725 intel_update_watermarks(dev);
4726
f564048e
EA		 4727 return ret;
4728}
4729
0e8ffe1b
DV		 4730static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4731 struct intel_crtc_config *pipe_config)
4732{
4733 struct drm_device *dev = crtc->base.dev;
4734 struct drm_i915_private *dev_priv = dev->dev_private;
4735 uint32_t tmp;
4736
4737 tmp = I915_READ(PIPECONF(crtc->pipe));
4738 if (!(tmp & PIPECONF_ENABLE))
4739 return false;
4740
4741 return true;
4742}
4743
dde86e2d 4744static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4745{
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4748 struct intel_encoder *encoder;
74cfd7ac 4749 u32 val, final;
13d83a67 4750 bool has_lvds = false;
199e5d79
KP		 4751 bool has_cpu_edp = false;
4752 bool has_pch_edp = false;
4753 bool has_panel = false;
99eb6a01
KP		 4754 bool has_ck505 = false;
4755 bool can_ssc = false;
13d83a67
JB		 4756
4757 /* We need to take the global config into account */
199e5d79
KP		 4758 list_for_each_entry(encoder, &mode_config->encoder_list,
4759 base.head) {
4760 switch (encoder->type) {
4761 case INTEL_OUTPUT_LVDS:
4762 has_panel = true;
4763 has_lvds = true;
4764 break;
4765 case INTEL_OUTPUT_EDP:
4766 has_panel = true;
4767 if (intel_encoder_is_pch_edp(&encoder->base))
4768 has_pch_edp = true;
4769 else
4770 has_cpu_edp = true;
4771 break;
13d83a67
JB		 4772 }
4773 }
4774
99eb6a01
KP		 4775 if (HAS_PCH_IBX(dev)) {
4776 has_ck505 = dev_priv->display_clock_mode;
4777 can_ssc = has_ck505;
4778 } else {
4779 has_ck505 = false;
4780 can_ssc = true;
4781 }
4782
4783 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4784 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4785 has_ck505);
13d83a67
JB		 4786
4787 /* Ironlake: try to setup display ref clock before DPLL
4788 * enabling. This is only under driver's control after
4789 * PCH B stepping, previous chipset stepping should be
4790 * ignoring this setting.
4791 */
74cfd7ac
CW		 4792 val = I915_READ(PCH_DREF_CONTROL);
4793
4794 /* As we must carefully and slowly disable/enable each source in turn,
4795 * compute the final state we want first and check if we need to
4796 * make any changes at all.
4797 */
4798 final = val;
4799 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4800 if (has_ck505)
4801 final |= DREF_NONSPREAD_CK505_ENABLE;
4802 else
4803 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4804
4805 final &= ~DREF_SSC_SOURCE_MASK;
4806 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4807 final &= ~DREF_SSC1_ENABLE;
4808
4809 if (has_panel) {
4810 final |= DREF_SSC_SOURCE_ENABLE;
4811
4812 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4813 final |= DREF_SSC1_ENABLE;
4814
4815 if (has_cpu_edp) {
4816 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4817 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4818 else
4819 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4820 } else
4821 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4822 } else {
4823 final |= DREF_SSC_SOURCE_DISABLE;
4824 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4825 }
4826
4827 if (final == val)
4828 return;
4829
13d83a67 4830 /* Always enable nonspread source */
74cfd7ac 4831 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4832
99eb6a01 4833 if (has_ck505)
74cfd7ac 4834 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4835 else
74cfd7ac 4836 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4837
199e5d79 4838 if (has_panel) {
74cfd7ac
CW		 4839 val &= ~DREF_SSC_SOURCE_MASK;
4840 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4841
199e5d79 4842 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4843 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4844 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4845 val |= DREF_SSC1_ENABLE;
e77166b5 4846 } else
74cfd7ac 4847 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4848
4849 /* Get SSC going before enabling the outputs */
74cfd7ac 4850 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4851 POSTING_READ(PCH_DREF_CONTROL);
4852 udelay(200);
4853
74cfd7ac 4854 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4855
4856 /* Enable CPU source on CPU attached eDP */
199e5d79 4857 if (has_cpu_edp) {
99eb6a01 4858 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4859 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4860 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4861 }
13d83a67 4862 else
74cfd7ac 4863 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4864 } else
74cfd7ac 4865 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4866
74cfd7ac 4867 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4868 POSTING_READ(PCH_DREF_CONTROL);
4869 udelay(200);
4870 } else {
4871 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4872
74cfd7ac 4873 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4874
4875 /* Turn off CPU output */
74cfd7ac 4876 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4877
74cfd7ac 4878 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4879 POSTING_READ(PCH_DREF_CONTROL);
4880 udelay(200);
4881
4882 /* Turn off the SSC source */
74cfd7ac
CW		 4883 val &= ~DREF_SSC_SOURCE_MASK;
4884 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4885
4886 /* Turn off SSC1 */
74cfd7ac 4887 val &= ~DREF_SSC1_ENABLE;
199e5d79 4888
74cfd7ac 4889 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4890 POSTING_READ(PCH_DREF_CONTROL);
4891 udelay(200);
4892 }
74cfd7ac
CW		 4893
4894 BUG_ON(val != final);
13d83a67
JB		 4895}
4896
dde86e2d
PZ		 4897/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4898static void lpt_init_pch_refclk(struct drm_device *dev)
4899{
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4901 struct drm_mode_config *mode_config = &dev->mode_config;
4902 struct intel_encoder *encoder;
4903 bool has_vga = false;
4904 bool is_sdv = false;
4905 u32 tmp;
4906
4907 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4908 switch (encoder->type) {
4909 case INTEL_OUTPUT_ANALOG:
4910 has_vga = true;
4911 break;
4912 }
4913 }
4914
4915 if (!has_vga)
4916 return;
4917
c00db246
DV		 4918 mutex_lock(&dev_priv->dpio_lock);
4919
dde86e2d
PZ		 4920 /* XXX: Rip out SDV support once Haswell ships for real. */
4921 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4922 is_sdv = true;
4923
4924 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4925 tmp &= ~SBI_SSCCTL_DISABLE;
4926 tmp |= SBI_SSCCTL_PATHALT;
4927 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4928
4929 udelay(24);
4930
4931 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4932 tmp &= ~SBI_SSCCTL_PATHALT;
4933 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4934
4935 if (!is_sdv) {
4936 tmp = I915_READ(SOUTH_CHICKEN2);
4937 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4938 I915_WRITE(SOUTH_CHICKEN2, tmp);
4939
4940 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4941 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4942 DRM_ERROR("FDI mPHY reset assert timeout\n");
4943
4944 tmp = I915_READ(SOUTH_CHICKEN2);
4945 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4946 I915_WRITE(SOUTH_CHICKEN2, tmp);
4947
4948 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4949 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4950 100))
4951 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4952 }
4953
4954 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4955 tmp &= ~(0xFF << 24);
4956 tmp |= (0x12 << 24);
4957 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4958
4959 if (!is_sdv) {
4960 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4961 tmp &= ~(0x3 << 6);
4962 tmp |= (1 << 6) | (1 << 0);
4963 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4964 }
4965
4966 if (is_sdv) {
4967 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4968 tmp |= 0x7FFF;
4969 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4970 }
4971
4972 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4973 tmp |= (1 << 11);
4974 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4975
4976 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4977 tmp |= (1 << 11);
4978 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4979
4980 if (is_sdv) {
4981 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4982 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4983 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4984
4985 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4986 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4987 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4988
4989 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4990 tmp |= (0x3F << 8);
4991 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4992
4993 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4994 tmp |= (0x3F << 8);
4995 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4996 }
4997
4998 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4999 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5000 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5001
5002 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5003 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5004 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5005
5006 if (!is_sdv) {
5007 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5008 tmp &= ~(7 << 13);
5009 tmp |= (5 << 13);
5010 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5011
5012 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5013 tmp &= ~(7 << 13);
5014 tmp |= (5 << 13);
5015 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5016 }
5017
5018 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5019 tmp &= ~0xFF;
5020 tmp |= 0x1C;
5021 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5022
5023 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5024 tmp &= ~0xFF;
5025 tmp |= 0x1C;
5026 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5027
5028 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5029 tmp &= ~(0xFF << 16);
5030 tmp |= (0x1C << 16);
5031 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5032
5033 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5034 tmp &= ~(0xFF << 16);
5035 tmp |= (0x1C << 16);
5036 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5037
5038 if (!is_sdv) {
5039 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5040 tmp |= (1 << 27);
5041 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5042
5043 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5044 tmp |= (1 << 27);
5045 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5046
5047 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5048 tmp &= ~(0xF << 28);
5049 tmp |= (4 << 28);
5050 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5051
5052 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5053 tmp &= ~(0xF << 28);
5054 tmp |= (4 << 28);
5055 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5056 }
5057
5058 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5059 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5060 tmp |= SBI_DBUFF0_ENABLE;
5061 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5062
5063 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5064}
5065
5066/*
5067 * Initialize reference clocks when the driver loads
5068 */
5069void intel_init_pch_refclk(struct drm_device *dev)
5070{
5071 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5072 ironlake_init_pch_refclk(dev);
5073 else if (HAS_PCH_LPT(dev))
5074 lpt_init_pch_refclk(dev);
5075}
5076
d9d444cb
JB		 5077static int ironlake_get_refclk(struct drm_crtc *crtc)
5078{
5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_encoder *encoder;
d9d444cb
JB		 5082 struct intel_encoder *edp_encoder = NULL;
5083 int num_connectors = 0;
5084 bool is_lvds = false;
5085
6c2b7c12 5086 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5087 switch (encoder->type) {
5088 case INTEL_OUTPUT_LVDS:
5089 is_lvds = true;
5090 break;
5091 case INTEL_OUTPUT_EDP:
5092 edp_encoder = encoder;
5093 break;
5094 }
5095 num_connectors++;
5096 }
5097
5098 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5099 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5100 dev_priv->lvds_ssc_freq);
5101 return dev_priv->lvds_ssc_freq * 1000;
5102 }
5103
5104 return 120000;
5105}
5106
c8203565 5107static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5108 struct drm_display_mode *adjusted_mode,
c8203565 5109 bool dither)
79e53945 5110{
c8203565 5111 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5113 int pipe = intel_crtc->pipe;
c8203565
PZ		 5114 uint32_t val;
5115
5116 val = I915_READ(PIPECONF(pipe));
5117
dfd07d72 5118 val &= ~PIPECONF_BPC_MASK;
965e0c48 5119 switch (intel_crtc->config.pipe_bpp) {
c8203565 5120 case 18:
dfd07d72 5121 val |= PIPECONF_6BPC;
c8203565
PZ		 5122 break;
5123 case 24:
dfd07d72 5124 val |= PIPECONF_8BPC;
c8203565
PZ		 5125 break;
5126 case 30:
dfd07d72 5127 val |= PIPECONF_10BPC;
c8203565
PZ		 5128 break;
5129 case 36:
dfd07d72 5130 val |= PIPECONF_12BPC;
c8203565
PZ		 5131 break;
5132 default:
cc769b62
PZ		 5133 /* Case prevented by intel_choose_pipe_bpp_dither. */
5134 BUG();
c8203565
PZ		 5135 }
5136
5137 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5138 if (dither)
5139 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5140
5141 val &= ~PIPECONF_INTERLACE_MASK;
5142 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5143 val |= PIPECONF_INTERLACED_ILK;
5144 else
5145 val |= PIPECONF_PROGRESSIVE;
5146
50f3b016 5147 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5148 val |= PIPECONF_COLOR_RANGE_SELECT;
5149 else
5150 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5151
c8203565
PZ		 5152 I915_WRITE(PIPECONF(pipe), val);
5153 POSTING_READ(PIPECONF(pipe));
5154}
5155
86d3efce
VS		 5156/*
5157 * Set up the pipe CSC unit.
5158 *
5159 * Currently only full range RGB to limited range RGB conversion
5160 * is supported, but eventually this should handle various
5161 * RGB<->YCbCr scenarios as well.
5162 */
50f3b016 5163static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5164{
5165 struct drm_device *dev = crtc->dev;
5166 struct drm_i915_private *dev_priv = dev->dev_private;
5167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168 int pipe = intel_crtc->pipe;
5169 uint16_t coeff = 0x7800; /* 1.0 */
5170
5171 /*
5172 * TODO: Check what kind of values actually come out of the pipe
5173 * with these coeff/postoff values and adjust to get the best
5174 * accuracy. Perhaps we even need to take the bpc value into
5175 * consideration.
5176 */
5177
50f3b016 5178 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5179 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5180
5181 /*
5182 * GY/GU and RY/RU should be the other way around according
5183 * to BSpec, but reality doesn't agree. Just set them up in
5184 * a way that results in the correct picture.
5185 */
5186 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5187 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5188
5189 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5190 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5191
5192 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5193 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5194
5195 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5196 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5197 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5198
5199 if (INTEL_INFO(dev)->gen > 6) {
5200 uint16_t postoff = 0;
5201
50f3b016 5202 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5203 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5204
5205 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5206 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5207 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5208
5209 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5210 } else {
5211 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5212
50f3b016 5213 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5214 mode |= CSC_BLACK_SCREEN_OFFSET;
5215
5216 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5217 }
5218}
5219
ee2b0b38
PZ		 5220static void haswell_set_pipeconf(struct drm_crtc *crtc,
5221 struct drm_display_mode *adjusted_mode,
5222 bool dither)
5223{
5224 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5226 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5227 uint32_t val;
5228
702e7a56 5229 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5230
5231 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5232 if (dither)
5233 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5234
5235 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5236 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5237 val |= PIPECONF_INTERLACED_ILK;
5238 else
5239 val |= PIPECONF_PROGRESSIVE;
5240
702e7a56
PZ		 5241 I915_WRITE(PIPECONF(cpu_transcoder), val);
5242 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5243}
5244
6591c6e4
PZ		 5245static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5246 struct drm_display_mode *adjusted_mode,
5247 intel_clock_t *clock,
5248 bool *has_reduced_clock,
5249 intel_clock_t *reduced_clock)
5250{
5251 struct drm_device *dev = crtc->dev;
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253 struct intel_encoder *intel_encoder;
5254 int refclk;
d4906093 5255 const intel_limit_t *limit;
6591c6e4 5256 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5257
6591c6e4
PZ		 5258 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5259 switch (intel_encoder->type) {
79e53945
JB		 5260 case INTEL_OUTPUT_LVDS:
5261 is_lvds = true;
5262 break;
5263 case INTEL_OUTPUT_SDVO:
7d57382e 5264 case INTEL_OUTPUT_HDMI:
79e53945 5265 is_sdvo = true;
6591c6e4 5266 if (intel_encoder->needs_tv_clock)
e2f0ba97 5267 is_tv = true;
79e53945 5268 break;
79e53945
JB		 5269 case INTEL_OUTPUT_TVOUT:
5270 is_tv = true;
5271 break;
79e53945
JB		 5272 }
5273 }
5274
d9d444cb 5275 refclk = ironlake_get_refclk(crtc);
79e53945 5276
d4906093
ML		 5277 /*
5278 * Returns a set of divisors for the desired target clock with the given
5279 * refclk, or FALSE. The returned values represent the clock equation:
5280 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5281 */
1b894b59 5282 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5283 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5284 clock);
5285 if (!ret)
5286 return false;
cda4b7d3 5287
ddc9003c 5288 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5289 /*
5290 * Ensure we match the reduced clock's P to the target clock.
5291 * If the clocks don't match, we can't switch the display clock
5292 * by using the FP0/FP1. In such case we will disable the LVDS
5293 * downclock feature.
5294 */
6591c6e4
PZ		 5295 *has_reduced_clock = limit->find_pll(limit, crtc,
5296 dev_priv->lvds_downclock,
5297 refclk,
5298 clock,
5299 reduced_clock);
652c393a 5300 }
61e9653f
DV		 5301
5302 if (is_sdvo && is_tv)
f47709a9 5303 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5304
5305 return true;
5306}
5307
01a415fd
DV		 5308static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5309{
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311 uint32_t temp;
5312
5313 temp = I915_READ(SOUTH_CHICKEN1);
5314 if (temp & FDI_BC_BIFURCATION_SELECT)
5315 return;
5316
5317 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5318 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5319
5320 temp |= FDI_BC_BIFURCATION_SELECT;
5321 DRM_DEBUG_KMS("enabling fdi C rx\n");
5322 I915_WRITE(SOUTH_CHICKEN1, temp);
5323 POSTING_READ(SOUTH_CHICKEN1);
5324}
5325
5326static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5327{
5328 struct drm_device *dev = intel_crtc->base.dev;
5329 struct drm_i915_private *dev_priv = dev->dev_private;
5330 struct intel_crtc *pipe_B_crtc =
5331 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5332
5333 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5334 intel_crtc->pipe, intel_crtc->fdi_lanes);
5335 if (intel_crtc->fdi_lanes > 4) {
5336 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5337 intel_crtc->pipe, intel_crtc->fdi_lanes);
5338 /* Clamp lanes to avoid programming the hw with bogus values. */
5339 intel_crtc->fdi_lanes = 4;
5340
5341 return false;
5342 }
5343
7eb552ae 5344 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5345 return true;
5346
5347 switch (intel_crtc->pipe) {
5348 case PIPE_A:
5349 return true;
5350 case PIPE_B:
5351 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5352 intel_crtc->fdi_lanes > 2) {
5353 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5354 intel_crtc->pipe, intel_crtc->fdi_lanes);
5355 /* Clamp lanes to avoid programming the hw with bogus values. */
5356 intel_crtc->fdi_lanes = 2;
5357
5358 return false;
5359 }
5360
5361 if (intel_crtc->fdi_lanes > 2)
5362 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5363 else
5364 cpt_enable_fdi_bc_bifurcation(dev);
5365
5366 return true;
5367 case PIPE_C:
5368 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5369 if (intel_crtc->fdi_lanes > 2) {
5370 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5371 intel_crtc->pipe, intel_crtc->fdi_lanes);
5372 /* Clamp lanes to avoid programming the hw with bogus values. */
5373 intel_crtc->fdi_lanes = 2;
5374
5375 return false;
5376 }
5377 } else {
5378 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5379 return false;
5380 }
5381
5382 cpt_enable_fdi_bc_bifurcation(dev);
5383
5384 return true;
5385 default:
5386 BUG();
5387 }
5388}
5389
d4b1931c
PZ		 5390int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5391{
5392 /*
5393 * Account for spread spectrum to avoid
5394 * oversubscribing the link. Max center spread
5395 * is 2.5%; use 5% for safety's sake.
5396 */
5397 u32 bps = target_clock * bpp * 21 / 20;
5398 return bps / (link_bw * 8) + 1;
5399}
5400
6cf86a5e
DV		 5401void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5402 struct intel_link_m_n *m_n)
79e53945 5403{
6cf86a5e
DV		 5404 struct drm_device *dev = crtc->base.dev;
5405 struct drm_i915_private *dev_priv = dev->dev_private;
5406 int pipe = crtc->pipe;
5407
5408 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5409 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5410 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5411 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5412}
5413
5414void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5415 struct intel_link_m_n *m_n)
5416{
5417 struct drm_device *dev = crtc->base.dev;
79e53945 5418 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e
DV		 5419 int pipe = crtc->pipe;
5420 enum transcoder transcoder = crtc->cpu_transcoder;
5421
5422 if (INTEL_INFO(dev)->gen >= 5) {
5423 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5424 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5425 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5426 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5427 } else {
5428 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5429 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5430 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5431 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5432 }
5433}
5434
5435static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5436{
5437 struct drm_device *dev = crtc->dev;
79e53945 5438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5439 struct drm_display_mode *adjusted_mode =
5440 &intel_crtc->config.adjusted_mode;
e69d0bc1 5441 struct intel_link_m_n m_n = {0};
6cc5f341 5442 int target_clock, lane, link_bw;
61e9653f 5443
6cf86a5e
DV		 5444 /* FDI is a binary signal running at ~2.7GHz, encoding
5445 * each output octet as 10 bits. The actual frequency
5446 * is stored as a divider into a 100MHz clock, and the
5447 * mode pixel clock is stored in units of 1KHz.
5448 * Hence the bw of each lane in terms of the mode signal
5449 * is:
5450 */
5451 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5452
df92b1e6
DV		 5453 if (intel_crtc->config.pixel_target_clock)
5454 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5455 else
5456 target_clock = adjusted_mode->clock;
5457
6cf86a5e
DV		 5458 lane = ironlake_get_lanes_required(target_clock, link_bw,
5459 intel_crtc->config.pipe_bpp);
2c07245f 5460
8febb297
EA		 5461 intel_crtc->fdi_lanes = lane;
5462
6cc5f341
DV		 5463 if (intel_crtc->config.pixel_multiplier > 1)
5464 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5465 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5466 link_bw, &m_n);
8febb297 5467
6cf86a5e 5468 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5469}
5470
de13a2e3 5471static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
de13a2e3 5472 intel_clock_t *clock, u32 fp)
79e53945 5473{
de13a2e3 5474 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5477 struct intel_encoder *intel_encoder;
5478 uint32_t dpll;
6cc5f341 5479 int factor, num_connectors = 0;
de13a2e3 5480 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5481
de13a2e3
PZ		 5482 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5483 switch (intel_encoder->type) {
79e53945
JB		 5484 case INTEL_OUTPUT_LVDS:
5485 is_lvds = true;
5486 break;
5487 case INTEL_OUTPUT_SDVO:
7d57382e 5488 case INTEL_OUTPUT_HDMI:
79e53945 5489 is_sdvo = true;
de13a2e3 5490 if (intel_encoder->needs_tv_clock)
e2f0ba97 5491 is_tv = true;
79e53945 5492 break;
79e53945
JB		 5493 case INTEL_OUTPUT_TVOUT:
5494 is_tv = true;
5495 break;
79e53945 5496 }
43565a06 5497
c751ce4f 5498 num_connectors++;
79e53945 5499 }
79e53945 5500
c1858123 5501 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5502 factor = 21;
5503 if (is_lvds) {
5504 if ((intel_panel_use_ssc(dev_priv) &&
5505 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5506 intel_is_dual_link_lvds(dev))
8febb297
EA		 5507 factor = 25;
5508 } else if (is_sdvo && is_tv)
5509 factor = 20;
c1858123 5510
de13a2e3 5511 if (clock->m < factor * clock->n)
8febb297 5512 fp |= FP_CB_TUNE;
2c07245f 5513
5eddb70b 5514 dpll = 0;
2c07245f 5515
a07d6787
EA		 5516 if (is_lvds)
5517 dpll |= DPLLB_MODE_LVDS;
5518 else
5519 dpll |= DPLLB_MODE_DAC_SERIAL;
5520 if (is_sdvo) {
6cc5f341
DV		 5521 if (intel_crtc->config.pixel_multiplier > 1) {
5522 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5523 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5524 }
a07d6787
EA		 5525 dpll |= DPLL_DVO_HIGH_SPEED;
5526 }
8b47047b
DV		 5527 if (intel_crtc->config.has_dp_encoder &&
5528 intel_crtc->config.has_pch_encoder)
a07d6787 5529 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5530
a07d6787 5531 /* compute bitmask from p1 value */
de13a2e3 5532 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5533 /* also FPA1 */
de13a2e3 5534 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5535
de13a2e3 5536 switch (clock->p2) {
a07d6787
EA		 5537 case 5:
5538 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5539 break;
5540 case 7:
5541 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5542 break;
5543 case 10:
5544 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5545 break;
5546 case 14:
5547 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5548 break;
79e53945
JB		 5549 }
5550
43565a06
KH		 5551 if (is_sdvo && is_tv)
5552 dpll |= PLL_REF_INPUT_TVCLKINBC;
5553 else if (is_tv)
79e53945 5554 /* XXX: just matching BIOS for now */
43565a06 5555 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5556 dpll |= 3;
a7615030 5557 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5558 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5559 else
5560 dpll |= PLL_REF_INPUT_DREFCLK;
5561
de13a2e3
PZ		 5562 return dpll;
5563}
5564
5565static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5566 int x, int y,
5567 struct drm_framebuffer *fb)
5568{
5569 struct drm_device *dev = crtc->dev;
5570 struct drm_i915_private *dev_priv = dev->dev_private;
5571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5572 struct drm_display_mode *adjusted_mode =
5573 &intel_crtc->config.adjusted_mode;
5574 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5575 int pipe = intel_crtc->pipe;
5576 int plane = intel_crtc->plane;
5577 int num_connectors = 0;
5578 intel_clock_t clock, reduced_clock;
5579 u32 dpll, fp = 0, fp2 = 0;
e2f12b07 5580 bool ok, has_reduced_clock = false;
8b47047b 5581 bool is_lvds = false;
de13a2e3 5582 struct intel_encoder *encoder;
de13a2e3 5583 int ret;
01a415fd 5584 bool dither, fdi_config_ok;
de13a2e3
PZ		 5585
5586 for_each_encoder_on_crtc(dev, crtc, encoder) {
5587 switch (encoder->type) {
5588 case INTEL_OUTPUT_LVDS:
5589 is_lvds = true;
5590 break;
de13a2e3
PZ		 5591 }
5592
5593 num_connectors++;
a07d6787 5594 }
79e53945 5595
5dc5298b
PZ		 5596 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5597 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5598
6cf86a5e
DV		 5599 intel_crtc->cpu_transcoder = pipe;
5600
de13a2e3
PZ		 5601 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5602 &has_reduced_clock, &reduced_clock);
5603 if (!ok) {
5604 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5605 return -EINVAL;
79e53945 5606 }
f47709a9
DV		 5607 /* Compat-code for transition, will disappear. */
5608 if (!intel_crtc->config.clock_set) {
5609 intel_crtc->config.dpll.n = clock.n;
5610 intel_crtc->config.dpll.m1 = clock.m1;
5611 intel_crtc->config.dpll.m2 = clock.m2;
5612 intel_crtc->config.dpll.p1 = clock.p1;
5613 intel_crtc->config.dpll.p2 = clock.p2;
5614 }
79e53945 5615
de13a2e3
PZ		 5616 /* Ensure that the cursor is valid for the new mode before changing... */
5617 intel_crtc_update_cursor(crtc, true);
5618
5619 /* determine panel color depth */
4e53c2e0 5620 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5621 if (is_lvds && dev_priv->lvds_dither)
5622 dither = true;
5623
5624 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5625 if (has_reduced_clock)
5626 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5627 reduced_clock.m2;
5628
6cc5f341 5629 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
79e53945 5630
f7cb34d4 5631 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5632 drm_mode_debug_printmodeline(mode);
5633
5dc5298b 5634 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5635 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5636 struct intel_pch_pll *pll;
4b645f14 5637
ee7b9f93
JB		 5638 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5639 if (pll == NULL) {
5640 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5641 pipe);
4b645f14
JB		 5642 return -EINVAL;
5643 }
ee7b9f93
JB		 5644 } else
5645 intel_put_pch_pll(intel_crtc);
79e53945 5646
03afc4a2
DV		 5647 if (intel_crtc->config.has_dp_encoder)
5648 intel_dp_set_m_n(intel_crtc);
79e53945 5649
dafd226c
DV		 5650 for_each_encoder_on_crtc(dev, crtc, encoder)
5651 if (encoder->pre_pll_enable)
5652 encoder->pre_pll_enable(encoder);
79e53945 5653
ee7b9f93
JB		 5654 if (intel_crtc->pch_pll) {
5655 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5656
32f9d658 5657 /* Wait for the clocks to stabilize. */
ee7b9f93 5658 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5659 udelay(150);
5660
8febb297
EA		 5661 /* The pixel multiplier can only be updated once the
5662 * DPLL is enabled and the clocks are stable.
5663 *
5664 * So write it again.
5665 */
ee7b9f93 5666 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5667 }
79e53945 5668
5eddb70b 5669 intel_crtc->lowfreq_avail = false;
ee7b9f93 5670 if (intel_crtc->pch_pll) {
4b645f14 5671 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5672 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5673 intel_crtc->lowfreq_avail = true;
4b645f14 5674 } else {
ee7b9f93 5675 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5676 }
5677 }
5678
b0e77b9c 5679 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5680
01a415fd
DV		 5681 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5682 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5683 intel_crtc->fdi_lanes = 0;
5684 if (intel_crtc->config.has_pch_encoder)
5685 ironlake_fdi_set_m_n(crtc);
2c07245f 5686
01a415fd 5687 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5688
c8203565 5689 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5690
9d0498a2 5691 intel_wait_for_vblank(dev, pipe);
79e53945 5692
a1f9e77e
PZ		 5693 /* Set up the display plane register */
5694 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5695 POSTING_READ(DSPCNTR(plane));
79e53945 5696
94352cf9 5697 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5698
5699 intel_update_watermarks(dev);
5700
1f8eeabf
ED		 5701 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5702
01a415fd 5703 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5704}
5705
0e8ffe1b
DV		 5706static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5707 struct intel_crtc_config *pipe_config)
5708{
5709 struct drm_device *dev = crtc->base.dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 uint32_t tmp;
5712
5713 tmp = I915_READ(PIPECONF(crtc->pipe));
5714 if (!(tmp & PIPECONF_ENABLE))
5715 return false;
5716
88adfff1
DV		 5717 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5718 pipe_config->has_pch_encoder = true;
5719
0e8ffe1b
DV		 5720 return true;
5721}
5722
d6dd9eb1
DV		 5723static void haswell_modeset_global_resources(struct drm_device *dev)
5724{
5725 struct drm_i915_private *dev_priv = dev->dev_private;
5726 bool enable = false;
5727 struct intel_crtc *crtc;
5728 struct intel_encoder *encoder;
5729
5730 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5731 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5732 enable = true;
5733 /* XXX: Should check for edp transcoder here, but thanks to init
5734 * sequence that's not yet available. Just in case desktop eDP
5735 * on PORT D is possible on haswell, too. */
5736 }
5737
5738 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5739 base.head) {
5740 if (encoder->type != INTEL_OUTPUT_EDP &&
5741 encoder->connectors_active)
5742 enable = true;
5743 }
5744
5745 /* Even the eDP panel fitter is outside the always-on well. */
5746 if (dev_priv->pch_pf_size)
5747 enable = true;
5748
5749 intel_set_power_well(dev, enable);
5750}
5751
09b4ddf9 5752static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5753 int x, int y,
5754 struct drm_framebuffer *fb)
5755{
5756 struct drm_device *dev = crtc->dev;
5757 struct drm_i915_private *dev_priv = dev->dev_private;
5758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5759 struct drm_display_mode *adjusted_mode =
5760 &intel_crtc->config.adjusted_mode;
5761 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5762 int pipe = intel_crtc->pipe;
5763 int plane = intel_crtc->plane;
5764 int num_connectors = 0;
8b47047b 5765 bool is_cpu_edp = false;
09b4ddf9 5766 struct intel_encoder *encoder;
09b4ddf9
PZ		 5767 int ret;
5768 bool dither;
5769
5770 for_each_encoder_on_crtc(dev, crtc, encoder) {
5771 switch (encoder->type) {
09b4ddf9 5772 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5773 if (!intel_encoder_is_pch_edp(&encoder->base))
5774 is_cpu_edp = true;
5775 break;
5776 }
5777
5778 num_connectors++;
5779 }
5780
bba2181c
DV		 5781 if (is_cpu_edp)
5782 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5783 else
5784 intel_crtc->cpu_transcoder = pipe;
5785
5dc5298b
PZ		 5786 /* We are not sure yet this won't happen. */
5787 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5788 INTEL_PCH_TYPE(dev));
5789
5790 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5791 num_connectors, pipe_name(pipe));
5792
702e7a56 5793 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5794 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5795
5796 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5797
6441ab5f
PZ		 5798 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5799 return -EINVAL;
5800
09b4ddf9
PZ		 5801 /* Ensure that the cursor is valid for the new mode before changing... */
5802 intel_crtc_update_cursor(crtc, true);
5803
5804 /* determine panel color depth */
4e53c2e0 5805 dither = intel_crtc->config.dither;
09b4ddf9 5806
09b4ddf9
PZ		 5807 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5808 drm_mode_debug_printmodeline(mode);
5809
03afc4a2
DV		 5810 if (intel_crtc->config.has_dp_encoder)
5811 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5812
5813 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5814
5815 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5816
6cf86a5e
DV		 5817 if (intel_crtc->config.has_pch_encoder)
5818 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5819
ee2b0b38 5820 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5821
50f3b016 5822 intel_set_pipe_csc(crtc);
86d3efce 5823
09b4ddf9 5824 /* Set up the display plane register */
86d3efce 5825 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5826 POSTING_READ(DSPCNTR(plane));
5827
5828 ret = intel_pipe_set_base(crtc, x, y, fb);
5829
5830 intel_update_watermarks(dev);
5831
5832 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5833
1f803ee5 5834 return ret;
79e53945
JB		 5835}
5836
0e8ffe1b
DV		 5837static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5838 struct intel_crtc_config *pipe_config)
5839{
5840 struct drm_device *dev = crtc->base.dev;
5841 struct drm_i915_private *dev_priv = dev->dev_private;
5842 uint32_t tmp;
5843
5844 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
5845 if (!(tmp & PIPECONF_ENABLE))
5846 return false;
5847
88adfff1
DV		 5848 /*
5849 * aswell has only FDI/PCH transcoder A. It is which is connected to
5850 * DDI E. So just check whether this pipe is wired to DDI E and whether
5851 * the PCH transcoder is on.
5852 */
5853 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5854 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5855 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5856 pipe_config->has_pch_encoder = true;
5857
5858
0e8ffe1b
DV		 5859 return true;
5860}
5861
f564048e 5862static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5863 int x, int y,
94352cf9 5864 struct drm_framebuffer *fb)
f564048e
EA		 5865{
5866 struct drm_device *dev = crtc->dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5868 struct drm_encoder_helper_funcs *encoder_funcs;
5869 struct intel_encoder *encoder;
0b701d27 5870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5871 struct drm_display_mode *adjusted_mode =
5872 &intel_crtc->config.adjusted_mode;
5873 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5874 int pipe = intel_crtc->pipe;
f564048e
EA		 5875 int ret;
5876
0b701d27 5877 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5878
b8cecdf5
DV		 5879 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5880
79e53945 5881 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5882
9256aa19
DV		 5883 if (ret != 0)
5884 return ret;
5885
5886 for_each_encoder_on_crtc(dev, crtc, encoder) {
5887 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5888 encoder->base.base.id,
5889 drm_get_encoder_name(&encoder->base),
5890 mode->base.id, mode->name);
6cc5f341
DV		 5891 if (encoder->mode_set) {
5892 encoder->mode_set(encoder);
5893 } else {
5894 encoder_funcs = encoder->base.helper_private;
5895 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5896 }
9256aa19
DV		 5897 }
5898
5899 return 0;
79e53945
JB		 5900}
5901
3a9627f4
WF		 5902static bool intel_eld_uptodate(struct drm_connector *connector,
5903 int reg_eldv, uint32_t bits_eldv,
5904 int reg_elda, uint32_t bits_elda,
5905 int reg_edid)
5906{
5907 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5908 uint8_t *eld = connector->eld;
5909 uint32_t i;
5910
5911 i = I915_READ(reg_eldv);
5912 i &= bits_eldv;
5913
5914 if (!eld[0])
5915 return !i;
5916
5917 if (!i)
5918 return false;
5919
5920 i = I915_READ(reg_elda);
5921 i &= ~bits_elda;
5922 I915_WRITE(reg_elda, i);
5923
5924 for (i = 0; i < eld[2]; i++)
5925 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5926 return false;
5927
5928 return true;
5929}
5930
e0dac65e
WF		 5931static void g4x_write_eld(struct drm_connector *connector,
5932 struct drm_crtc *crtc)
5933{
5934 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5935 uint8_t *eld = connector->eld;
5936 uint32_t eldv;
5937 uint32_t len;
5938 uint32_t i;
5939
5940 i = I915_READ(G4X_AUD_VID_DID);
5941
5942 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5943 eldv = G4X_ELDV_DEVCL_DEVBLC;
5944 else
5945 eldv = G4X_ELDV_DEVCTG;
5946
3a9627f4
WF		 5947 if (intel_eld_uptodate(connector,
5948 G4X_AUD_CNTL_ST, eldv,
5949 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5950 G4X_HDMIW_HDMIEDID))
5951 return;
5952
e0dac65e
WF		 5953 i = I915_READ(G4X_AUD_CNTL_ST);
5954 i &= ~(eldv | G4X_ELD_ADDR);
5955 len = (i >> 9) & 0x1f; /* ELD buffer size */
5956 I915_WRITE(G4X_AUD_CNTL_ST, i);
5957
5958 if (!eld[0])
5959 return;
5960
5961 len = min_t(uint8_t, eld[2], len);
5962 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5963 for (i = 0; i < len; i++)
5964 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5965
5966 i = I915_READ(G4X_AUD_CNTL_ST);
5967 i |= eldv;
5968 I915_WRITE(G4X_AUD_CNTL_ST, i);
5969}
5970
83358c85
WX		 5971static void haswell_write_eld(struct drm_connector *connector,
5972 struct drm_crtc *crtc)
5973{
5974 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5975 uint8_t *eld = connector->eld;
5976 struct drm_device *dev = crtc->dev;
7b9f35a6 5977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5978 uint32_t eldv;
5979 uint32_t i;
5980 int len;
5981 int pipe = to_intel_crtc(crtc)->pipe;
5982 int tmp;
5983
5984 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5985 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5986 int aud_config = HSW_AUD_CFG(pipe);
5987 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5988
5989
5990 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5991
5992 /* Audio output enable */
5993 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5994 tmp = I915_READ(aud_cntrl_st2);
5995 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5996 I915_WRITE(aud_cntrl_st2, tmp);
5997
5998 /* Wait for 1 vertical blank */
5999 intel_wait_for_vblank(dev, pipe);
6000
6001 /* Set ELD valid state */
6002 tmp = I915_READ(aud_cntrl_st2);
6003 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6004 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6005 I915_WRITE(aud_cntrl_st2, tmp);
6006 tmp = I915_READ(aud_cntrl_st2);
6007 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6008
6009 /* Enable HDMI mode */
6010 tmp = I915_READ(aud_config);
6011 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6012 /* clear N_programing_enable and N_value_index */
6013 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6014 I915_WRITE(aud_config, tmp);
6015
6016 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6017
6018 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6019 intel_crtc->eld_vld = true;
83358c85
WX		 6020
6021 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6022 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6023 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6024 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6025 } else
6026 I915_WRITE(aud_config, 0);
6027
6028 if (intel_eld_uptodate(connector,
6029 aud_cntrl_st2, eldv,
6030 aud_cntl_st, IBX_ELD_ADDRESS,
6031 hdmiw_hdmiedid))
6032 return;
6033
6034 i = I915_READ(aud_cntrl_st2);
6035 i &= ~eldv;
6036 I915_WRITE(aud_cntrl_st2, i);
6037
6038 if (!eld[0])
6039 return;
6040
6041 i = I915_READ(aud_cntl_st);
6042 i &= ~IBX_ELD_ADDRESS;
6043 I915_WRITE(aud_cntl_st, i);
6044 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6045 DRM_DEBUG_DRIVER("port num:%d\n", i);
6046
6047 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6048 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6049 for (i = 0; i < len; i++)
6050 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6051
6052 i = I915_READ(aud_cntrl_st2);
6053 i |= eldv;
6054 I915_WRITE(aud_cntrl_st2, i);
6055
6056}
6057
e0dac65e
WF		 6058static void ironlake_write_eld(struct drm_connector *connector,
6059 struct drm_crtc *crtc)
6060{
6061 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6062 uint8_t *eld = connector->eld;
6063 uint32_t eldv;
6064 uint32_t i;
6065 int len;
6066 int hdmiw_hdmiedid;
b6daa025 6067 int aud_config;
e0dac65e
WF		 6068 int aud_cntl_st;
6069 int aud_cntrl_st2;
9b138a83 6070 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6071
b3f33cbf 6072 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6073 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6074 aud_config = IBX_AUD_CFG(pipe);
6075 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6076 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6077 } else {
9b138a83
WX		 6078 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6079 aud_config = CPT_AUD_CFG(pipe);
6080 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6081 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6082 }
6083
9b138a83 6084 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6085
6086 i = I915_READ(aud_cntl_st);
9b138a83 6087 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6088 if (!i) {
6089 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6090 /* operate blindly on all ports */
1202b4c6
WF		 6091 eldv = IBX_ELD_VALIDB;
6092 eldv |= IBX_ELD_VALIDB << 4;
6093 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6094 } else {
6095 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6096 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6097 }
6098
3a9627f4
WF		 6099 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6100 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6101 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6102 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6103 } else
6104 I915_WRITE(aud_config, 0);
e0dac65e 6105
3a9627f4
WF		 6106 if (intel_eld_uptodate(connector,
6107 aud_cntrl_st2, eldv,
6108 aud_cntl_st, IBX_ELD_ADDRESS,
6109 hdmiw_hdmiedid))
6110 return;
6111
e0dac65e
WF		 6112 i = I915_READ(aud_cntrl_st2);
6113 i &= ~eldv;
6114 I915_WRITE(aud_cntrl_st2, i);
6115
6116 if (!eld[0])
6117 return;
6118
e0dac65e 6119 i = I915_READ(aud_cntl_st);
1202b4c6 6120 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6121 I915_WRITE(aud_cntl_st, i);
6122
6123 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6124 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6125 for (i = 0; i < len; i++)
6126 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6127
6128 i = I915_READ(aud_cntrl_st2);
6129 i |= eldv;
6130 I915_WRITE(aud_cntrl_st2, i);
6131}
6132
6133void intel_write_eld(struct drm_encoder *encoder,
6134 struct drm_display_mode *mode)
6135{
6136 struct drm_crtc *crtc = encoder->crtc;
6137 struct drm_connector *connector;
6138 struct drm_device *dev = encoder->dev;
6139 struct drm_i915_private *dev_priv = dev->dev_private;
6140
6141 connector = drm_select_eld(encoder, mode);
6142 if (!connector)
6143 return;
6144
6145 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6146 connector->base.id,
6147 drm_get_connector_name(connector),
6148 connector->encoder->base.id,
6149 drm_get_encoder_name(connector->encoder));
6150
6151 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6152
6153 if (dev_priv->display.write_eld)
6154 dev_priv->display.write_eld(connector, crtc);
6155}
6156
79e53945
JB		 6157/** Loads the palette/gamma unit for the CRTC with the prepared values */
6158void intel_crtc_load_lut(struct drm_crtc *crtc)
6159{
6160 struct drm_device *dev = crtc->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6163 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6164 int i;
6165
6166 /* The clocks have to be on to load the palette. */
aed3f09d 6167 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6168 return;
6169
f2b115e6 6170 /* use legacy palette for Ironlake */
bad720ff 6171 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6172 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6173
79e53945
JB		 6174 for (i = 0; i < 256; i++) {
6175 I915_WRITE(palreg + 4 * i,
6176 (intel_crtc->lut_r[i] << 16) |
6177 (intel_crtc->lut_g[i] << 8) |
6178 intel_crtc->lut_b[i]);
6179 }
6180}
6181
560b85bb
CW		 6182static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6183{
6184 struct drm_device *dev = crtc->dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187 bool visible = base != 0;
6188 u32 cntl;
6189
6190 if (intel_crtc->cursor_visible == visible)
6191 return;
6192
9db4a9c7 6193 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6194 if (visible) {
6195 /* On these chipsets we can only modify the base whilst
6196 * the cursor is disabled.
6197 */
9db4a9c7 6198 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6199
6200 cntl &= ~(CURSOR_FORMAT_MASK);
6201 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6202 cntl |= CURSOR_ENABLE |
6203 CURSOR_GAMMA_ENABLE |
6204 CURSOR_FORMAT_ARGB;
6205 } else
6206 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6207 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6208
6209 intel_crtc->cursor_visible = visible;
6210}
6211
6212static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6213{
6214 struct drm_device *dev = crtc->dev;
6215 struct drm_i915_private *dev_priv = dev->dev_private;
6216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6217 int pipe = intel_crtc->pipe;
6218 bool visible = base != 0;
6219
6220 if (intel_crtc->cursor_visible != visible) {
548f245b 6221 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6222 if (base) {
6223 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6224 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6225 cntl |= pipe << 28; /* Connect to correct pipe */
6226 } else {
6227 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6228 cntl |= CURSOR_MODE_DISABLE;
6229 }
9db4a9c7 6230 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6231
6232 intel_crtc->cursor_visible = visible;
6233 }
6234 /* and commit changes on next vblank */
9db4a9c7 6235 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6236}
6237
65a21cd6
JB		 6238static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6239{
6240 struct drm_device *dev = crtc->dev;
6241 struct drm_i915_private *dev_priv = dev->dev_private;
6242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6243 int pipe = intel_crtc->pipe;
6244 bool visible = base != 0;
6245
6246 if (intel_crtc->cursor_visible != visible) {
6247 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6248 if (base) {
6249 cntl &= ~CURSOR_MODE;
6250 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6251 } else {
6252 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6253 cntl |= CURSOR_MODE_DISABLE;
6254 }
86d3efce
VS		 6255 if (IS_HASWELL(dev))
6256 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6257 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6258
6259 intel_crtc->cursor_visible = visible;
6260 }
6261 /* and commit changes on next vblank */
6262 I915_WRITE(CURBASE_IVB(pipe), base);
6263}
6264
cda4b7d3 6265/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6266static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6267 bool on)
cda4b7d3
CW		 6268{
6269 struct drm_device *dev = crtc->dev;
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272 int pipe = intel_crtc->pipe;
6273 int x = intel_crtc->cursor_x;
6274 int y = intel_crtc->cursor_y;
560b85bb 6275 u32 base, pos;
cda4b7d3
CW		 6276 bool visible;
6277
6278 pos = 0;
6279
6b383a7f 6280 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6281 base = intel_crtc->cursor_addr;
6282 if (x > (int) crtc->fb->width)
6283 base = 0;
6284
6285 if (y > (int) crtc->fb->height)
6286 base = 0;
6287 } else
6288 base = 0;
6289
6290 if (x < 0) {
6291 if (x + intel_crtc->cursor_width < 0)
6292 base = 0;
6293
6294 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6295 x = -x;
6296 }
6297 pos |= x << CURSOR_X_SHIFT;
6298
6299 if (y < 0) {
6300 if (y + intel_crtc->cursor_height < 0)
6301 base = 0;
6302
6303 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6304 y = -y;
6305 }
6306 pos |= y << CURSOR_Y_SHIFT;
6307
6308 visible = base != 0;
560b85bb 6309 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6310 return;
6311
0cd83aa9 6312 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6313 I915_WRITE(CURPOS_IVB(pipe), pos);
6314 ivb_update_cursor(crtc, base);
6315 } else {
6316 I915_WRITE(CURPOS(pipe), pos);
6317 if (IS_845G(dev) || IS_I865G(dev))
6318 i845_update_cursor(crtc, base);
6319 else
6320 i9xx_update_cursor(crtc, base);
6321 }
cda4b7d3
CW		 6322}
6323
79e53945 6324static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6325 struct drm_file *file,
79e53945
JB		 6326 uint32_t handle,
6327 uint32_t width, uint32_t height)
6328{
6329 struct drm_device *dev = crtc->dev;
6330 struct drm_i915_private *dev_priv = dev->dev_private;
6331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6332 struct drm_i915_gem_object *obj;
cda4b7d3 6333 uint32_t addr;
3f8bc370 6334 int ret;
79e53945 6335
79e53945
JB		 6336 /* if we want to turn off the cursor ignore width and height */
6337 if (!handle) {
28c97730 6338 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6339 addr = 0;
05394f39 6340 obj = NULL;
5004417d 6341 mutex_lock(&dev->struct_mutex);
3f8bc370 6342 goto finish;
79e53945
JB		 6343 }
6344
6345 /* Currently we only support 64x64 cursors */
6346 if (width != 64 || height != 64) {
6347 DRM_ERROR("we currently only support 64x64 cursors\n");
6348 return -EINVAL;
6349 }
6350
05394f39 6351 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6352 if (&obj->base == NULL)
79e53945
JB		 6353 return -ENOENT;
6354
05394f39 6355 if (obj->base.size < width * height * 4) {
79e53945 6356 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6357 ret = -ENOMEM;
6358 goto fail;
79e53945
JB		 6359 }
6360
71acb5eb 6361 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6362 mutex_lock(&dev->struct_mutex);
b295d1b6 6363 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6364 unsigned alignment;
6365
d9e86c0e
CW		 6366 if (obj->tiling_mode) {
6367 DRM_ERROR("cursor cannot be tiled\n");
6368 ret = -EINVAL;
6369 goto fail_locked;
6370 }
6371
693db184
CW		 6372 /* Note that the w/a also requires 2 PTE of padding following
6373 * the bo. We currently fill all unused PTE with the shadow
6374 * page and so we should always have valid PTE following the
6375 * cursor preventing the VT-d warning.
6376 */
6377 alignment = 0;
6378 if (need_vtd_wa(dev))
6379 alignment = 64*1024;
6380
6381 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6382 if (ret) {
6383 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6384 goto fail_locked;
e7b526bb
CW		 6385 }
6386
d9e86c0e
CW		 6387 ret = i915_gem_object_put_fence(obj);
6388 if (ret) {
2da3b9b9 6389 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6390 goto fail_unpin;
6391 }
6392
05394f39 6393 addr = obj->gtt_offset;
71acb5eb 6394 } else {
6eeefaf3 6395 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6396 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6397 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6398 align);
71acb5eb
DA		 6399 if (ret) {
6400 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6401 goto fail_locked;
71acb5eb 6402 }
05394f39 6403 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6404 }
6405
a6c45cf0 6406 if (IS_GEN2(dev))
14b60391
JB		 6407 I915_WRITE(CURSIZE, (height << 12) | width);
6408
3f8bc370 6409 finish:
3f8bc370 6410 if (intel_crtc->cursor_bo) {
b295d1b6 6411 if (dev_priv->info->cursor_needs_physical) {
05394f39 6412 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6413 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6414 } else
6415 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6416 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6417 }
80824003 6418
7f9872e0 6419 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6420
6421 intel_crtc->cursor_addr = addr;
05394f39 6422 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6423 intel_crtc->cursor_width = width;
6424 intel_crtc->cursor_height = height;
6425
6b383a7f 6426 intel_crtc_update_cursor(crtc, true);
3f8bc370 6427
79e53945 6428 return 0;
e7b526bb 6429fail_unpin:
05394f39 6430 i915_gem_object_unpin(obj);
7f9872e0 6431fail_locked:
34b8686e 6432 mutex_unlock(&dev->struct_mutex);
bc9025bd 6433fail:
05394f39 6434 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6435 return ret;
79e53945
JB		 6436}
6437
6438static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6439{
79e53945 6440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6441
cda4b7d3
CW		 6442 intel_crtc->cursor_x = x;
6443 intel_crtc->cursor_y = y;
652c393a 6444
6b383a7f 6445 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6446
6447 return 0;
6448}
6449
6450/** Sets the color ramps on behalf of RandR */
6451void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6452 u16 blue, int regno)
6453{
6454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6455
6456 intel_crtc->lut_r[regno] = red >> 8;
6457 intel_crtc->lut_g[regno] = green >> 8;
6458 intel_crtc->lut_b[regno] = blue >> 8;
6459}
6460
b8c00ac5
DA		 6461void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6462 u16 *blue, int regno)
6463{
6464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6465
6466 *red = intel_crtc->lut_r[regno] << 8;
6467 *green = intel_crtc->lut_g[regno] << 8;
6468 *blue = intel_crtc->lut_b[regno] << 8;
6469}
6470
79e53945 6471static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6472 u16 *blue, uint32_t start, uint32_t size)
79e53945 6473{
7203425a 6474 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6476
7203425a 6477 for (i = start; i < end; i++) {
79e53945
JB		 6478 intel_crtc->lut_r[i] = red[i] >> 8;
6479 intel_crtc->lut_g[i] = green[i] >> 8;
6480 intel_crtc->lut_b[i] = blue[i] >> 8;
6481 }
6482
6483 intel_crtc_load_lut(crtc);
6484}
6485
79e53945
JB		 6486/* VESA 640x480x72Hz mode to set on the pipe */
6487static struct drm_display_mode load_detect_mode = {
6488 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6489 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6490};
6491
d2dff872
CW		 6492static struct drm_framebuffer *
6493intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6494 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6495 struct drm_i915_gem_object *obj)
6496{
6497 struct intel_framebuffer *intel_fb;
6498 int ret;
6499
6500 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6501 if (!intel_fb) {
6502 drm_gem_object_unreference_unlocked(&obj->base);
6503 return ERR_PTR(-ENOMEM);
6504 }
6505
6506 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6507 if (ret) {
6508 drm_gem_object_unreference_unlocked(&obj->base);
6509 kfree(intel_fb);
6510 return ERR_PTR(ret);
6511 }
6512
6513 return &intel_fb->base;
6514}
6515
6516static u32
6517intel_framebuffer_pitch_for_width(int width, int bpp)
6518{
6519 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6520 return ALIGN(pitch, 64);
6521}
6522
6523static u32
6524intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6525{
6526 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6527 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6528}
6529
6530static struct drm_framebuffer *
6531intel_framebuffer_create_for_mode(struct drm_device *dev,
6532 struct drm_display_mode *mode,
6533 int depth, int bpp)
6534{
6535 struct drm_i915_gem_object *obj;
0fed39bd 6536 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6537
6538 obj = i915_gem_alloc_object(dev,
6539 intel_framebuffer_size_for_mode(mode, bpp));
6540 if (obj == NULL)
6541 return ERR_PTR(-ENOMEM);
6542
6543 mode_cmd.width = mode->hdisplay;
6544 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6545 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6546 bpp);
5ca0c34a 6547 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6548
6549 return intel_framebuffer_create(dev, &mode_cmd, obj);
6550}
6551
6552static struct drm_framebuffer *
6553mode_fits_in_fbdev(struct drm_device *dev,
6554 struct drm_display_mode *mode)
6555{
6556 struct drm_i915_private *dev_priv = dev->dev_private;
6557 struct drm_i915_gem_object *obj;
6558 struct drm_framebuffer *fb;
6559
6560 if (dev_priv->fbdev == NULL)
6561 return NULL;
6562
6563 obj = dev_priv->fbdev->ifb.obj;
6564 if (obj == NULL)
6565 return NULL;
6566
6567 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6568 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6569 fb->bits_per_pixel))
d2dff872
CW		 6570 return NULL;
6571
01f2c773 6572 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6573 return NULL;
6574
6575 return fb;
6576}
6577
d2434ab7 6578bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6579 struct drm_display_mode *mode,
8261b191 6580 struct intel_load_detect_pipe *old)
79e53945
JB		 6581{
6582 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6583 struct intel_encoder *intel_encoder =
6584 intel_attached_encoder(connector);
79e53945 6585 struct drm_crtc *possible_crtc;
4ef69c7a 6586 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6587 struct drm_crtc *crtc = NULL;
6588 struct drm_device *dev = encoder->dev;
94352cf9 6589 struct drm_framebuffer *fb;
79e53945
JB		 6590 int i = -1;
6591
d2dff872
CW		 6592 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6593 connector->base.id, drm_get_connector_name(connector),
6594 encoder->base.id, drm_get_encoder_name(encoder));
6595
79e53945
JB		 6596 /*
6597 * Algorithm gets a little messy:
7a5e4805 6598 *
79e53945
JB		 6599 * - if the connector already has an assigned crtc, use it (but make
6600 * sure it's on first)
7a5e4805 6601 *
79e53945
JB		 6602 * - try to find the first unused crtc that can drive this connector,
6603 * and use that if we find one
79e53945
JB		 6604 */
6605
6606 /* See if we already have a CRTC for this connector */
6607 if (encoder->crtc) {
6608 crtc = encoder->crtc;
8261b191 6609
7b24056b
DV		 6610 mutex_lock(&crtc->mutex);
6611
24218aac 6612 old->dpms_mode = connector->dpms;
8261b191
CW		 6613 old->load_detect_temp = false;
6614
6615 /* Make sure the crtc and connector are running */
24218aac
DV		 6616 if (connector->dpms != DRM_MODE_DPMS_ON)
6617 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6618
7173188d 6619 return true;
79e53945
JB		 6620 }
6621
6622 /* Find an unused one (if possible) */
6623 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6624 i++;
6625 if (!(encoder->possible_crtcs & (1 << i)))
6626 continue;
6627 if (!possible_crtc->enabled) {
6628 crtc = possible_crtc;
6629 break;
6630 }
79e53945
JB		 6631 }
6632
6633 /*
6634 * If we didn't find an unused CRTC, don't use any.
6635 */
6636 if (!crtc) {
7173188d
CW		 6637 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6638 return false;
79e53945
JB		 6639 }
6640
7b24056b 6641 mutex_lock(&crtc->mutex);
fc303101
DV		 6642 intel_encoder->new_crtc = to_intel_crtc(crtc);
6643 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6644
6645 intel_crtc = to_intel_crtc(crtc);
24218aac 6646 old->dpms_mode = connector->dpms;
8261b191 6647 old->load_detect_temp = true;
d2dff872 6648 old->release_fb = NULL;
79e53945 6649
6492711d
CW		 6650 if (!mode)
6651 mode = &load_detect_mode;
79e53945 6652
d2dff872
CW		 6653 /* We need a framebuffer large enough to accommodate all accesses
6654 * that the plane may generate whilst we perform load detection.
6655 * We can not rely on the fbcon either being present (we get called
6656 * during its initialisation to detect all boot displays, or it may
6657 * not even exist) or that it is large enough to satisfy the
6658 * requested mode.
6659 */
94352cf9
DV		 6660 fb = mode_fits_in_fbdev(dev, mode);
6661 if (fb == NULL) {
d2dff872 6662 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6663 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6664 old->release_fb = fb;
d2dff872
CW		 6665 } else
6666 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6667 if (IS_ERR(fb)) {
d2dff872 6668 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6669 mutex_unlock(&crtc->mutex);
0e8b3d3e 6670 return false;
79e53945 6671 }
79e53945 6672
c0c36b94 6673 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6674 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6675 if (old->release_fb)
6676 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6677 mutex_unlock(&crtc->mutex);
0e8b3d3e 6678 return false;
79e53945 6679 }
7173188d 6680
79e53945 6681 /* let the connector get through one full cycle before testing */
9d0498a2 6682 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6683 return true;
79e53945
JB		 6684}
6685
d2434ab7 6686void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6687 struct intel_load_detect_pipe *old)
79e53945 6688{
d2434ab7
DV		 6689 struct intel_encoder *intel_encoder =
6690 intel_attached_encoder(connector);
4ef69c7a 6691 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6692 struct drm_crtc *crtc = encoder->crtc;
79e53945 6693
d2dff872
CW		 6694 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6695 connector->base.id, drm_get_connector_name(connector),
6696 encoder->base.id, drm_get_encoder_name(encoder));
6697
8261b191 6698 if (old->load_detect_temp) {
fc303101
DV		 6699 to_intel_connector(connector)->new_encoder = NULL;
6700 intel_encoder->new_crtc = NULL;
6701 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6702
36206361
DV		 6703 if (old->release_fb) {
6704 drm_framebuffer_unregister_private(old->release_fb);
6705 drm_framebuffer_unreference(old->release_fb);
6706 }
d2dff872 6707
67c96400 6708 mutex_unlock(&crtc->mutex);
0622a53c 6709 return;
79e53945
JB		 6710 }
6711
c751ce4f 6712 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6713 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6714 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6715
6716 mutex_unlock(&crtc->mutex);
79e53945
JB		 6717}
6718
6719/* Returns the clock of the currently programmed mode of the given pipe. */
6720static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6721{
6722 struct drm_i915_private *dev_priv = dev->dev_private;
6723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6724 int pipe = intel_crtc->pipe;
548f245b 6725 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6726 u32 fp;
6727 intel_clock_t clock;
6728
6729 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6730 fp = I915_READ(FP0(pipe));
79e53945 6731 else
39adb7a5 6732 fp = I915_READ(FP1(pipe));
79e53945
JB		 6733
6734 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6735 if (IS_PINEVIEW(dev)) {
6736 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6737 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6738 } else {
6739 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6740 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6741 }
6742
a6c45cf0 6743 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6744 if (IS_PINEVIEW(dev))
6745 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6746 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6747 else
6748 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6749 DPLL_FPA01_P1_POST_DIV_SHIFT);
6750
6751 switch (dpll & DPLL_MODE_MASK) {
6752 case DPLLB_MODE_DAC_SERIAL:
6753 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6754 5 : 10;
6755 break;
6756 case DPLLB_MODE_LVDS:
6757 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6758 7 : 14;
6759 break;
6760 default:
28c97730 6761 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6762 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6763 return 0;
6764 }
6765
6766 /* XXX: Handle the 100Mhz refclk */
2177832f 6767 intel_clock(dev, 96000, &clock);
79e53945
JB		 6768 } else {
6769 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6770
6771 if (is_lvds) {
6772 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6773 DPLL_FPA01_P1_POST_DIV_SHIFT);
6774 clock.p2 = 14;
6775
6776 if ((dpll & PLL_REF_INPUT_MASK) ==
6777 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6778 /* XXX: might not be 66MHz */
2177832f 6779 intel_clock(dev, 66000, &clock);
79e53945 6780 } else
2177832f 6781 intel_clock(dev, 48000, &clock);
79e53945
JB		 6782 } else {
6783 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6784 clock.p1 = 2;
6785 else {
6786 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6787 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6788 }
6789 if (dpll & PLL_P2_DIVIDE_BY_4)
6790 clock.p2 = 4;
6791 else
6792 clock.p2 = 2;
6793
2177832f 6794 intel_clock(dev, 48000, &clock);
79e53945
JB		 6795 }
6796 }
6797
6798 /* XXX: It would be nice to validate the clocks, but we can't reuse
6799 * i830PllIsValid() because it relies on the xf86_config connector
6800 * configuration being accurate, which it isn't necessarily.
6801 */
6802
6803 return clock.dot;
6804}
6805
6806/** Returns the currently programmed mode of the given pipe. */
6807struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6808 struct drm_crtc *crtc)
6809{
548f245b 6810 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6812 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6813 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6814 int htot = I915_READ(HTOTAL(cpu_transcoder));
6815 int hsync = I915_READ(HSYNC(cpu_transcoder));
6816 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6817 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6818
6819 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6820 if (!mode)
6821 return NULL;
6822
6823 mode->clock = intel_crtc_clock_get(dev, crtc);
6824 mode->hdisplay = (htot & 0xffff) + 1;
6825 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6826 mode->hsync_start = (hsync & 0xffff) + 1;
6827 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6828 mode->vdisplay = (vtot & 0xffff) + 1;
6829 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6830 mode->vsync_start = (vsync & 0xffff) + 1;
6831 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6832
6833 drm_mode_set_name(mode);
79e53945
JB		 6834
6835 return mode;
6836}
6837
3dec0095 6838static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6839{
6840 struct drm_device *dev = crtc->dev;
6841 drm_i915_private_t *dev_priv = dev->dev_private;
6842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6843 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6844 int dpll_reg = DPLL(pipe);
6845 int dpll;
652c393a 6846
bad720ff 6847 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6848 return;
6849
6850 if (!dev_priv->lvds_downclock_avail)
6851 return;
6852
dbdc6479 6853 dpll = I915_READ(dpll_reg);
652c393a 6854 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6855 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6856
8ac5a6d5 6857 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6858
6859 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6860 I915_WRITE(dpll_reg, dpll);
9d0498a2 6861 intel_wait_for_vblank(dev, pipe);
dbdc6479 6862
652c393a
JB		 6863 dpll = I915_READ(dpll_reg);
6864 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6865 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6866 }
652c393a
JB		 6867}
6868
6869static void intel_decrease_pllclock(struct drm_crtc *crtc)
6870{
6871 struct drm_device *dev = crtc->dev;
6872 drm_i915_private_t *dev_priv = dev->dev_private;
6873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6874
bad720ff 6875 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6876 return;
6877
6878 if (!dev_priv->lvds_downclock_avail)
6879 return;
6880
6881 /*
6882 * Since this is called by a timer, we should never get here in
6883 * the manual case.
6884 */
6885 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6886 int pipe = intel_crtc->pipe;
6887 int dpll_reg = DPLL(pipe);
6888 int dpll;
f6e5b160 6889
44d98a61 6890 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6891
8ac5a6d5 6892 assert_panel_unlocked(dev_priv, pipe);
652c393a 6893
dc257cf1 6894 dpll = I915_READ(dpll_reg);
652c393a
JB		 6895 dpll |= DISPLAY_RATE_SELECT_FPA1;
6896 I915_WRITE(dpll_reg, dpll);
9d0498a2 6897 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6898 dpll = I915_READ(dpll_reg);
6899 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6900 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6901 }
6902
6903}
6904
f047e395
CW		 6905void intel_mark_busy(struct drm_device *dev)
6906{
f047e395
CW		 6907 i915_update_gfx_val(dev->dev_private);
6908}
6909
6910void intel_mark_idle(struct drm_device *dev)
652c393a 6911{
652c393a 6912 struct drm_crtc *crtc;
652c393a
JB		 6913
6914 if (!i915_powersave)
6915 return;
6916
652c393a 6917 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6918 if (!crtc->fb)
6919 continue;
6920
725a5b54 6921 intel_decrease_pllclock(crtc);
652c393a 6922 }
652c393a
JB		 6923}
6924
725a5b54 6925void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6926{
f047e395
CW		 6927 struct drm_device *dev = obj->base.dev;
6928 struct drm_crtc *crtc;
652c393a 6929
f047e395 6930 if (!i915_powersave)
acb87dfb
CW		 6931 return;
6932
652c393a
JB		 6933 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6934 if (!crtc->fb)
6935 continue;
6936
f047e395 6937 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6938 intel_increase_pllclock(crtc);
652c393a
JB		 6939 }
6940}
6941
79e53945
JB		 6942static void intel_crtc_destroy(struct drm_crtc *crtc)
6943{
6944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6945 struct drm_device *dev = crtc->dev;
6946 struct intel_unpin_work *work;
6947 unsigned long flags;
6948
6949 spin_lock_irqsave(&dev->event_lock, flags);
6950 work = intel_crtc->unpin_work;
6951 intel_crtc->unpin_work = NULL;
6952 spin_unlock_irqrestore(&dev->event_lock, flags);
6953
6954 if (work) {
6955 cancel_work_sync(&work->work);
6956 kfree(work);
6957 }
79e53945
JB		 6958
6959 drm_crtc_cleanup(crtc);
67e77c5a 6960
79e53945
JB		 6961 kfree(intel_crtc);
6962}
6963
6b95a207
KH		 6964static void intel_unpin_work_fn(struct work_struct *__work)
6965{
6966 struct intel_unpin_work *work =
6967 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6968 struct drm_device *dev = work->crtc->dev;
6b95a207 6969
b4a98e57 6970 mutex_lock(&dev->struct_mutex);
1690e1eb 6971 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6972 drm_gem_object_unreference(&work->pending_flip_obj->base);
6973 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6974
b4a98e57
CW		 6975 intel_update_fbc(dev);
6976 mutex_unlock(&dev->struct_mutex);
6977
6978 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6979 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6980
6b95a207
KH		 6981 kfree(work);
6982}
6983
1afe3e9d 6984static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6985 struct drm_crtc *crtc)
6b95a207
KH		 6986{
6987 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6989 struct intel_unpin_work *work;
6b95a207
KH		 6990 unsigned long flags;
6991
6992 /* Ignore early vblank irqs */
6993 if (intel_crtc == NULL)
6994 return;
6995
6996 spin_lock_irqsave(&dev->event_lock, flags);
6997 work = intel_crtc->unpin_work;
e7d841ca
CW		 6998
6999 /* Ensure we don't miss a work->pending update ... */
7000 smp_rmb();
7001
7002 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7003 spin_unlock_irqrestore(&dev->event_lock, flags);
7004 return;
7005 }
7006
e7d841ca
CW		 7007 /* and that the unpin work is consistent wrt ->pending. */
7008 smp_rmb();
7009
6b95a207 7010 intel_crtc->unpin_work = NULL;
6b95a207 7011
45a066eb
RC		 7012 if (work->event)
7013 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7014
0af7e4df
MK		 7015 drm_vblank_put(dev, intel_crtc->pipe);
7016
6b95a207
KH		 7017 spin_unlock_irqrestore(&dev->event_lock, flags);
7018
2c10d571 7019 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7020
7021 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7022
7023 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7024}
7025
1afe3e9d
JB		 7026void intel_finish_page_flip(struct drm_device *dev, int pipe)
7027{
7028 drm_i915_private_t *dev_priv = dev->dev_private;
7029 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7030
49b14a5c 7031 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7032}
7033
7034void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7035{
7036 drm_i915_private_t *dev_priv = dev->dev_private;
7037 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7038
49b14a5c 7039 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7040}
7041
6b95a207
KH		 7042void intel_prepare_page_flip(struct drm_device *dev, int plane)
7043{
7044 drm_i915_private_t *dev_priv = dev->dev_private;
7045 struct intel_crtc *intel_crtc =
7046 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7047 unsigned long flags;
7048
e7d841ca
CW		 7049 /* NB: An MMIO update of the plane base pointer will also
7050 * generate a page-flip completion irq, i.e. every modeset
7051 * is also accompanied by a spurious intel_prepare_page_flip().
7052 */
6b95a207 7053 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7054 if (intel_crtc->unpin_work)
7055 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7056 spin_unlock_irqrestore(&dev->event_lock, flags);
7057}
7058
e7d841ca
CW		 7059inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7060{
7061 /* Ensure that the work item is consistent when activating it ... */
7062 smp_wmb();
7063 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7064 /* and that it is marked active as soon as the irq could fire. */
7065 smp_wmb();
7066}
7067
8c9f3aaf
JB		 7068static int intel_gen2_queue_flip(struct drm_device *dev,
7069 struct drm_crtc *crtc,
7070 struct drm_framebuffer *fb,
7071 struct drm_i915_gem_object *obj)
7072{
7073 struct drm_i915_private *dev_priv = dev->dev_private;
7074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7075 u32 flip_mask;
6d90c952 7076 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7077 int ret;
7078
6d90c952 7079 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7080 if (ret)
83d4092b 7081 goto err;
8c9f3aaf 7082
6d90c952 7083 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7084 if (ret)
83d4092b 7085 goto err_unpin;
8c9f3aaf
JB		 7086
7087 /* Can't queue multiple flips, so wait for the previous
7088 * one to finish before executing the next.
7089 */
7090 if (intel_crtc->plane)
7091 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7092 else
7093 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7094 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7095 intel_ring_emit(ring, MI_NOOP);
7096 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7097 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7098 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7099 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7100 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7101
7102 intel_mark_page_flip_active(intel_crtc);
6d90c952 7103 intel_ring_advance(ring);
83d4092b
CW		 7104 return 0;
7105
7106err_unpin:
7107 intel_unpin_fb_obj(obj);
7108err:
8c9f3aaf
JB		 7109 return ret;
7110}
7111
7112static int intel_gen3_queue_flip(struct drm_device *dev,
7113 struct drm_crtc *crtc,
7114 struct drm_framebuffer *fb,
7115 struct drm_i915_gem_object *obj)
7116{
7117 struct drm_i915_private *dev_priv = dev->dev_private;
7118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7119 u32 flip_mask;
6d90c952 7120 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7121 int ret;
7122
6d90c952 7123 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7124 if (ret)
83d4092b 7125 goto err;
8c9f3aaf 7126
6d90c952 7127 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7128 if (ret)
83d4092b 7129 goto err_unpin;
8c9f3aaf
JB		 7130
7131 if (intel_crtc->plane)
7132 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7133 else
7134 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7135 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7136 intel_ring_emit(ring, MI_NOOP);
7137 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7139 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7140 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7141 intel_ring_emit(ring, MI_NOOP);
7142
e7d841ca 7143 intel_mark_page_flip_active(intel_crtc);
6d90c952 7144 intel_ring_advance(ring);
83d4092b
CW		 7145 return 0;
7146
7147err_unpin:
7148 intel_unpin_fb_obj(obj);
7149err:
8c9f3aaf
JB		 7150 return ret;
7151}
7152
7153static int intel_gen4_queue_flip(struct drm_device *dev,
7154 struct drm_crtc *crtc,
7155 struct drm_framebuffer *fb,
7156 struct drm_i915_gem_object *obj)
7157{
7158 struct drm_i915_private *dev_priv = dev->dev_private;
7159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7160 uint32_t pf, pipesrc;
6d90c952 7161 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7162 int ret;
7163
6d90c952 7164 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7165 if (ret)
83d4092b 7166 goto err;
8c9f3aaf 7167
6d90c952 7168 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7169 if (ret)
83d4092b 7170 goto err_unpin;
8c9f3aaf
JB		 7171
7172 /* i965+ uses the linear or tiled offsets from the
7173 * Display Registers (which do not change across a page-flip)
7174 * so we need only reprogram the base address.
7175 */
6d90c952
DV		 7176 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7177 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7178 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7179 intel_ring_emit(ring,
7180 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7181 obj->tiling_mode);
8c9f3aaf
JB		 7182
7183 /* XXX Enabling the panel-fitter across page-flip is so far
7184 * untested on non-native modes, so ignore it for now.
7185 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7186 */
7187 pf = 0;
7188 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7189 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7190
7191 intel_mark_page_flip_active(intel_crtc);
6d90c952 7192 intel_ring_advance(ring);
83d4092b
CW		 7193 return 0;
7194
7195err_unpin:
7196 intel_unpin_fb_obj(obj);
7197err:
8c9f3aaf
JB		 7198 return ret;
7199}
7200
7201static int intel_gen6_queue_flip(struct drm_device *dev,
7202 struct drm_crtc *crtc,
7203 struct drm_framebuffer *fb,
7204 struct drm_i915_gem_object *obj)
7205{
7206 struct drm_i915_private *dev_priv = dev->dev_private;
7207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7208 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7209 uint32_t pf, pipesrc;
7210 int ret;
7211
6d90c952 7212 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7213 if (ret)
83d4092b 7214 goto err;
8c9f3aaf 7215
6d90c952 7216 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7217 if (ret)
83d4092b 7218 goto err_unpin;
8c9f3aaf 7219
6d90c952
DV		 7220 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7221 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7222 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7223 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7224
dc257cf1
DV		 7225 /* Contrary to the suggestions in the documentation,
7226 * "Enable Panel Fitter" does not seem to be required when page
7227 * flipping with a non-native mode, and worse causes a normal
7228 * modeset to fail.
7229 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7230 */
7231 pf = 0;
8c9f3aaf 7232 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7233 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7234
7235 intel_mark_page_flip_active(intel_crtc);
6d90c952 7236 intel_ring_advance(ring);
83d4092b
CW		 7237 return 0;
7238
7239err_unpin:
7240 intel_unpin_fb_obj(obj);
7241err:
8c9f3aaf
JB		 7242 return ret;
7243}
7244
7c9017e5
JB		 7245/*
7246 * On gen7 we currently use the blit ring because (in early silicon at least)
7247 * the render ring doesn't give us interrpts for page flip completion, which
7248 * means clients will hang after the first flip is queued. Fortunately the
7249 * blit ring generates interrupts properly, so use it instead.
7250 */
7251static int intel_gen7_queue_flip(struct drm_device *dev,
7252 struct drm_crtc *crtc,
7253 struct drm_framebuffer *fb,
7254 struct drm_i915_gem_object *obj)
7255{
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7258 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7259 uint32_t plane_bit = 0;
7c9017e5
JB		 7260 int ret;
7261
7262 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7263 if (ret)
83d4092b 7264 goto err;
7c9017e5 7265
cb05d8de
DV		 7266 switch(intel_crtc->plane) {
7267 case PLANE_A:
7268 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7269 break;
7270 case PLANE_B:
7271 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7272 break;
7273 case PLANE_C:
7274 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7275 break;
7276 default:
7277 WARN_ONCE(1, "unknown plane in flip command\n");
7278 ret = -ENODEV;
ab3951eb 7279 goto err_unpin;
cb05d8de
DV		 7280 }
7281
7c9017e5
JB		 7282 ret = intel_ring_begin(ring, 4);
7283 if (ret)
83d4092b 7284 goto err_unpin;
7c9017e5 7285
cb05d8de 7286 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7287 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7288 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7289 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7290
7291 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7292 intel_ring_advance(ring);
83d4092b
CW		 7293 return 0;
7294
7295err_unpin:
7296 intel_unpin_fb_obj(obj);
7297err:
7c9017e5
JB		 7298 return ret;
7299}
7300
8c9f3aaf
JB		 7301static int intel_default_queue_flip(struct drm_device *dev,
7302 struct drm_crtc *crtc,
7303 struct drm_framebuffer *fb,
7304 struct drm_i915_gem_object *obj)
7305{
7306 return -ENODEV;
7307}
7308
6b95a207
KH		 7309static int intel_crtc_page_flip(struct drm_crtc *crtc,
7310 struct drm_framebuffer *fb,
7311 struct drm_pending_vblank_event *event)
7312{
7313 struct drm_device *dev = crtc->dev;
7314 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7315 struct drm_framebuffer *old_fb = crtc->fb;
7316 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7318 struct intel_unpin_work *work;
8c9f3aaf 7319 unsigned long flags;
52e68630 7320 int ret;
6b95a207 7321
e6a595d2
VS		 7322 /* Can't change pixel format via MI display flips. */
7323 if (fb->pixel_format != crtc->fb->pixel_format)
7324 return -EINVAL;
7325
7326 /*
7327 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7328 * Note that pitch changes could also affect these register.
7329 */
7330 if (INTEL_INFO(dev)->gen > 3 &&
7331 (fb->offsets[0] != crtc->fb->offsets[0] ||
7332 fb->pitches[0] != crtc->fb->pitches[0]))
7333 return -EINVAL;
7334
6b95a207
KH		 7335 work = kzalloc(sizeof *work, GFP_KERNEL);
7336 if (work == NULL)
7337 return -ENOMEM;
7338
6b95a207 7339 work->event = event;
b4a98e57 7340 work->crtc = crtc;
4a35f83b 7341 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7342 INIT_WORK(&work->work, intel_unpin_work_fn);
7343
7317c75e
JB		 7344 ret = drm_vblank_get(dev, intel_crtc->pipe);
7345 if (ret)
7346 goto free_work;
7347
6b95a207
KH		 7348 /* We borrow the event spin lock for protecting unpin_work */
7349 spin_lock_irqsave(&dev->event_lock, flags);
7350 if (intel_crtc->unpin_work) {
7351 spin_unlock_irqrestore(&dev->event_lock, flags);
7352 kfree(work);
7317c75e 7353 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7354
7355 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7356 return -EBUSY;
7357 }
7358 intel_crtc->unpin_work = work;
7359 spin_unlock_irqrestore(&dev->event_lock, flags);
7360
b4a98e57
CW		 7361 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7362 flush_workqueue(dev_priv->wq);
7363
79158103
CW		 7364 ret = i915_mutex_lock_interruptible(dev);
7365 if (ret)
7366 goto cleanup;
6b95a207 7367
75dfca80 7368 /* Reference the objects for the scheduled work. */
05394f39
CW		 7369 drm_gem_object_reference(&work->old_fb_obj->base);
7370 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7371
7372 crtc->fb = fb;
96b099fd 7373
e1f99ce6 7374 work->pending_flip_obj = obj;
e1f99ce6 7375
4e5359cd
SF		 7376 work->enable_stall_check = true;
7377
b4a98e57 7378 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7379 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7380
8c9f3aaf
JB		 7381 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7382 if (ret)
7383 goto cleanup_pending;
6b95a207 7384
7782de3b 7385 intel_disable_fbc(dev);
f047e395 7386 intel_mark_fb_busy(obj);
6b95a207
KH		 7387 mutex_unlock(&dev->struct_mutex);
7388
e5510fac
JB		 7389 trace_i915_flip_request(intel_crtc->plane, obj);
7390
6b95a207 7391 return 0;
96b099fd 7392
8c9f3aaf 7393cleanup_pending:
b4a98e57 7394 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7395 crtc->fb = old_fb;
05394f39
CW		 7396 drm_gem_object_unreference(&work->old_fb_obj->base);
7397 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7398 mutex_unlock(&dev->struct_mutex);
7399
79158103 7400cleanup:
96b099fd
CW		 7401 spin_lock_irqsave(&dev->event_lock, flags);
7402 intel_crtc->unpin_work = NULL;
7403 spin_unlock_irqrestore(&dev->event_lock, flags);
7404
7317c75e
JB		 7405 drm_vblank_put(dev, intel_crtc->pipe);
7406free_work:
96b099fd
CW		 7407 kfree(work);
7408
7409 return ret;
6b95a207
KH		 7410}
7411
f6e5b160 7412static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7413 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7414 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7415};
7416
6ed0f796 7417bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7418{
6ed0f796
DV		 7419 struct intel_encoder *other_encoder;
7420 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7421
6ed0f796
DV		 7422 if (WARN_ON(!crtc))
7423 return false;
7424
7425 list_for_each_entry(other_encoder,
7426 &crtc->dev->mode_config.encoder_list,
7427 base.head) {
7428
7429 if (&other_encoder->new_crtc->base != crtc ||
7430 encoder == other_encoder)
7431 continue;
7432 else
7433 return true;
f47166d2
CW		 7434 }
7435
6ed0f796
DV		 7436 return false;
7437}
47f1c6c9 7438
50f56119
DV		 7439static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7440 struct drm_crtc *crtc)
7441{
7442 struct drm_device *dev;
7443 struct drm_crtc *tmp;
7444 int crtc_mask = 1;
47f1c6c9 7445
50f56119 7446 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7447
50f56119 7448 dev = crtc->dev;
47f1c6c9 7449
50f56119
DV		 7450 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7451 if (tmp == crtc)
7452 break;
7453 crtc_mask <<= 1;
7454 }
47f1c6c9 7455
50f56119
DV		 7456 if (encoder->possible_crtcs & crtc_mask)
7457 return true;
7458 return false;
47f1c6c9 7459}
79e53945 7460
9a935856
DV		 7461/**
7462 * intel_modeset_update_staged_output_state
7463 *
7464 * Updates the staged output configuration state, e.g. after we've read out the
7465 * current hw state.
7466 */
7467static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7468{
9a935856
DV		 7469 struct intel_encoder *encoder;
7470 struct intel_connector *connector;
f6e5b160 7471
9a935856
DV		 7472 list_for_each_entry(connector, &dev->mode_config.connector_list,
7473 base.head) {
7474 connector->new_encoder =
7475 to_intel_encoder(connector->base.encoder);
7476 }
f6e5b160 7477
9a935856
DV		 7478 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7479 base.head) {
7480 encoder->new_crtc =
7481 to_intel_crtc(encoder->base.crtc);
7482 }
f6e5b160
CW		 7483}
7484
9a935856
DV		 7485/**
7486 * intel_modeset_commit_output_state
7487 *
7488 * This function copies the stage display pipe configuration to the real one.
7489 */
7490static void intel_modeset_commit_output_state(struct drm_device *dev)
7491{
7492 struct intel_encoder *encoder;
7493 struct intel_connector *connector;
f6e5b160 7494
9a935856
DV		 7495 list_for_each_entry(connector, &dev->mode_config.connector_list,
7496 base.head) {
7497 connector->base.encoder = &connector->new_encoder->base;
7498 }
f6e5b160 7499
9a935856
DV		 7500 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7501 base.head) {
7502 encoder->base.crtc = &encoder->new_crtc->base;
7503 }
7504}
7505
4e53c2e0
DV		 7506static int
7507pipe_config_set_bpp(struct drm_crtc *crtc,
7508 struct drm_framebuffer *fb,
7509 struct intel_crtc_config *pipe_config)
7510{
7511 struct drm_device *dev = crtc->dev;
7512 struct drm_connector *connector;
7513 int bpp;
7514
d42264b1
DV		 7515 switch (fb->pixel_format) {
7516 case DRM_FORMAT_C8:
4e53c2e0
DV		 7517 bpp = 8*3; /* since we go through a colormap */
7518 break;
d42264b1
DV		 7519 case DRM_FORMAT_XRGB1555:
7520 case DRM_FORMAT_ARGB1555:
7521 /* checked in intel_framebuffer_init already */
7522 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7523 return -EINVAL;
7524 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7525 bpp = 6*3; /* min is 18bpp */
7526 break;
d42264b1
DV		 7527 case DRM_FORMAT_XBGR8888:
7528 case DRM_FORMAT_ABGR8888:
7529 /* checked in intel_framebuffer_init already */
7530 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7531 return -EINVAL;
7532 case DRM_FORMAT_XRGB8888:
7533 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7534 bpp = 8*3;
7535 break;
d42264b1
DV		 7536 case DRM_FORMAT_XRGB2101010:
7537 case DRM_FORMAT_ARGB2101010:
7538 case DRM_FORMAT_XBGR2101010:
7539 case DRM_FORMAT_ABGR2101010:
7540 /* checked in intel_framebuffer_init already */
7541 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7542 return -EINVAL;
4e53c2e0
DV		 7543 bpp = 10*3;
7544 break;
baba133a 7545 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7546 default:
7547 DRM_DEBUG_KMS("unsupported depth\n");
7548 return -EINVAL;
7549 }
7550
4e53c2e0
DV		 7551 pipe_config->pipe_bpp = bpp;
7552
7553 /* Clamp display bpp to EDID value */
7554 list_for_each_entry(connector, &dev->mode_config.connector_list,
7555 head) {
7556 if (connector->encoder && connector->encoder->crtc != crtc)
7557 continue;
7558
7559 /* Don't use an invalid EDID bpc value */
7560 if (connector->display_info.bpc &&
7561 connector->display_info.bpc * 3 < bpp) {
7562 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7563 bpp, connector->display_info.bpc*3);
7564 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7565 }
7566 }
7567
7568 return bpp;
7569}
7570
b8cecdf5
DV		 7571static struct intel_crtc_config *
7572intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7573 struct drm_framebuffer *fb,
b8cecdf5 7574 struct drm_display_mode *mode)
ee7b9f93 7575{
7758a113 7576 struct drm_device *dev = crtc->dev;
7758a113
DV		 7577 struct drm_encoder_helper_funcs *encoder_funcs;
7578 struct intel_encoder *encoder;
b8cecdf5 7579 struct intel_crtc_config *pipe_config;
4e53c2e0 7580 int plane_bpp;
ee7b9f93 7581
b8cecdf5
DV		 7582 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7583 if (!pipe_config)
7758a113
DV		 7584 return ERR_PTR(-ENOMEM);
7585
b8cecdf5
DV		 7586 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7587 drm_mode_copy(&pipe_config->requested_mode, mode);
7588
4e53c2e0
DV		 7589 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7590 if (plane_bpp < 0)
7591 goto fail;
7592
7758a113
DV		 7593 /* Pass our mode to the connectors and the CRTC to give them a chance to
7594 * adjust it according to limitations or connector properties, and also
7595 * a chance to reject the mode entirely.
47f1c6c9 7596 */
7758a113
DV		 7597 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7598 base.head) {
47f1c6c9 7599
7758a113
DV		 7600 if (&encoder->new_crtc->base != crtc)
7601 continue;
7ae89233
DV		 7602
7603 if (encoder->compute_config) {
7604 if (!(encoder->compute_config(encoder, pipe_config))) {
7605 DRM_DEBUG_KMS("Encoder config failure\n");
7606 goto fail;
7607 }
7608
7609 continue;
7610 }
7611
7758a113 7612 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7613 if (!(encoder_funcs->mode_fixup(&encoder->base,
7614 &pipe_config->requested_mode,
7615 &pipe_config->adjusted_mode))) {
7758a113
DV		 7616 DRM_DEBUG_KMS("Encoder fixup failed\n");
7617 goto fail;
7618 }
ee7b9f93 7619 }
47f1c6c9 7620
b8cecdf5 7621 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7622 DRM_DEBUG_KMS("CRTC fixup failed\n");
7623 goto fail;
ee7b9f93 7624 }
7758a113 7625 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7626
4e53c2e0
DV		 7627 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7628 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7629 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7630
b8cecdf5 7631 return pipe_config;
7758a113 7632fail:
b8cecdf5 7633 kfree(pipe_config);
7758a113 7634 return ERR_PTR(-EINVAL);
ee7b9f93 7635}
47f1c6c9 7636
e2e1ed41
DV		 7637/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7638 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7639static void
7640intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7641 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7642{
7643 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7644 struct drm_device *dev = crtc->dev;
7645 struct intel_encoder *encoder;
7646 struct intel_connector *connector;
7647 struct drm_crtc *tmp_crtc;
79e53945 7648
e2e1ed41 7649 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7650
e2e1ed41
DV		 7651 /* Check which crtcs have changed outputs connected to them, these need
7652 * to be part of the prepare_pipes mask. We don't (yet) support global
7653 * modeset across multiple crtcs, so modeset_pipes will only have one
7654 * bit set at most. */
7655 list_for_each_entry(connector, &dev->mode_config.connector_list,
7656 base.head) {
7657 if (connector->base.encoder == &connector->new_encoder->base)
7658 continue;
79e53945 7659
e2e1ed41
DV		 7660 if (connector->base.encoder) {
7661 tmp_crtc = connector->base.encoder->crtc;
7662
7663 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7664 }
7665
7666 if (connector->new_encoder)
7667 *prepare_pipes |=
7668 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7669 }
7670
e2e1ed41
DV		 7671 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7672 base.head) {
7673 if (encoder->base.crtc == &encoder->new_crtc->base)
7674 continue;
7675
7676 if (encoder->base.crtc) {
7677 tmp_crtc = encoder->base.crtc;
7678
7679 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7680 }
7681
7682 if (encoder->new_crtc)
7683 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7684 }
7685
e2e1ed41
DV		 7686 /* Check for any pipes that will be fully disabled ... */
7687 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7688 base.head) {
7689 bool used = false;
22fd0fab 7690
e2e1ed41
DV		 7691 /* Don't try to disable disabled crtcs. */
7692 if (!intel_crtc->base.enabled)
7693 continue;
7e7d76c3 7694
e2e1ed41
DV		 7695 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7696 base.head) {
7697 if (encoder->new_crtc == intel_crtc)
7698 used = true;
7699 }
7700
7701 if (!used)
7702 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7703 }
7704
e2e1ed41
DV		 7705
7706 /* set_mode is also used to update properties on life display pipes. */
7707 intel_crtc = to_intel_crtc(crtc);
7708 if (crtc->enabled)
7709 *prepare_pipes |= 1 << intel_crtc->pipe;
7710
7711 /* We only support modeset on one single crtc, hence we need to do that
7712 * only for the passed in crtc iff we change anything else than just
7713 * disable crtcs.
7714 *
7715 * This is actually not true, to be fully compatible with the old crtc
7716 * helper we automatically disable _any_ output (i.e. doesn't need to be
7717 * connected to the crtc we're modesetting on) if it's disconnected.
7718 * Which is a rather nutty api (since changed the output configuration
7719 * without userspace's explicit request can lead to confusion), but
7720 * alas. Hence we currently need to modeset on all pipes we prepare. */
7721 if (*prepare_pipes)
7722 *modeset_pipes = *prepare_pipes;
7723
7724 /* ... and mask these out. */
7725 *modeset_pipes &= ~(*disable_pipes);
7726 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7727}
79e53945 7728
ea9d758d 7729static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7730{
ea9d758d 7731 struct drm_encoder *encoder;
f6e5b160 7732 struct drm_device *dev = crtc->dev;
f6e5b160 7733
ea9d758d
DV		 7734 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7735 if (encoder->crtc == crtc)
7736 return true;
7737
7738 return false;
7739}
7740
7741static void
7742intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7743{
7744 struct intel_encoder *intel_encoder;
7745 struct intel_crtc *intel_crtc;
7746 struct drm_connector *connector;
7747
7748 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7749 base.head) {
7750 if (!intel_encoder->base.crtc)
7751 continue;
7752
7753 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7754
7755 if (prepare_pipes & (1 << intel_crtc->pipe))
7756 intel_encoder->connectors_active = false;
7757 }
7758
7759 intel_modeset_commit_output_state(dev);
7760
7761 /* Update computed state. */
7762 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7763 base.head) {
7764 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7765 }
7766
7767 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7768 if (!connector->encoder || !connector->encoder->crtc)
7769 continue;
7770
7771 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7772
7773 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7774 struct drm_property *dpms_property =
7775 dev->mode_config.dpms_property;
7776
ea9d758d 7777 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7778 drm_object_property_set_value(&connector->base,
68d34720
DV		 7779 dpms_property,
7780 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7781
7782 intel_encoder = to_intel_encoder(connector->encoder);
7783 intel_encoder->connectors_active = true;
7784 }
7785 }
7786
7787}
7788
25c5b266
DV		 7789#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7790 list_for_each_entry((intel_crtc), \
7791 &(dev)->mode_config.crtc_list, \
7792 base.head) \
7793 if (mask & (1 <<(intel_crtc)->pipe)) \
7794
0e8ffe1b
DV		 7795static bool
7796intel_pipe_config_compare(struct intel_crtc_config *current_config,
7797 struct intel_crtc_config *pipe_config)
7798{
88adfff1
DV		 7799 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7800 DRM_ERROR("mismatch in has_pch_encoder "
7801 "(expected %i, found %i)\n",
7802 current_config->has_pch_encoder,
7803 pipe_config->has_pch_encoder);
7804 return false;
7805 }
7806
0e8ffe1b
DV		 7807 return true;
7808}
7809
b980514c 7810void
8af6cf88
DV		 7811intel_modeset_check_state(struct drm_device *dev)
7812{
0e8ffe1b 7813 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7814 struct intel_crtc *crtc;
7815 struct intel_encoder *encoder;
7816 struct intel_connector *connector;
0e8ffe1b 7817 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7818
7819 list_for_each_entry(connector, &dev->mode_config.connector_list,
7820 base.head) {
7821 /* This also checks the encoder/connector hw state with the
7822 * ->get_hw_state callbacks. */
7823 intel_connector_check_state(connector);
7824
7825 WARN(&connector->new_encoder->base != connector->base.encoder,
7826 "connector's staged encoder doesn't match current encoder\n");
7827 }
7828
7829 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7830 base.head) {
7831 bool enabled = false;
7832 bool active = false;
7833 enum pipe pipe, tracked_pipe;
7834
7835 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7836 encoder->base.base.id,
7837 drm_get_encoder_name(&encoder->base));
7838
7839 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7840 "encoder's stage crtc doesn't match current crtc\n");
7841 WARN(encoder->connectors_active && !encoder->base.crtc,
7842 "encoder's active_connectors set, but no crtc\n");
7843
7844 list_for_each_entry(connector, &dev->mode_config.connector_list,
7845 base.head) {
7846 if (connector->base.encoder != &encoder->base)
7847 continue;
7848 enabled = true;
7849 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7850 active = true;
7851 }
7852 WARN(!!encoder->base.crtc != enabled,
7853 "encoder's enabled state mismatch "
7854 "(expected %i, found %i)\n",
7855 !!encoder->base.crtc, enabled);
7856 WARN(active && !encoder->base.crtc,
7857 "active encoder with no crtc\n");
7858
7859 WARN(encoder->connectors_active != active,
7860 "encoder's computed active state doesn't match tracked active state "
7861 "(expected %i, found %i)\n", active, encoder->connectors_active);
7862
7863 active = encoder->get_hw_state(encoder, &pipe);
7864 WARN(active != encoder->connectors_active,
7865 "encoder's hw state doesn't match sw tracking "
7866 "(expected %i, found %i)\n",
7867 encoder->connectors_active, active);
7868
7869 if (!encoder->base.crtc)
7870 continue;
7871
7872 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7873 WARN(active && pipe != tracked_pipe,
7874 "active encoder's pipe doesn't match"
7875 "(expected %i, found %i)\n",
7876 tracked_pipe, pipe);
7877
7878 }
7879
7880 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7881 base.head) {
7882 bool enabled = false;
7883 bool active = false;
7884
7885 DRM_DEBUG_KMS("[CRTC:%d]\n",
7886 crtc->base.base.id);
7887
7888 WARN(crtc->active && !crtc->base.enabled,
7889 "active crtc, but not enabled in sw tracking\n");
7890
7891 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7892 base.head) {
7893 if (encoder->base.crtc != &crtc->base)
7894 continue;
7895 enabled = true;
7896 if (encoder->connectors_active)
7897 active = true;
7898 }
7899 WARN(active != crtc->active,
7900 "crtc's computed active state doesn't match tracked active state "
7901 "(expected %i, found %i)\n", active, crtc->active);
7902 WARN(enabled != crtc->base.enabled,
7903 "crtc's computed enabled state doesn't match tracked enabled state "
7904 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7905
88adfff1 7906 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 7907 active = dev_priv->display.get_pipe_config(crtc,
7908 &pipe_config);
7909 WARN(crtc->active != active,
7910 "crtc active state doesn't match with hw state "
7911 "(expected %i, found %i)\n", crtc->active, active);
7912
7913 WARN(active &&
7914 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7915 "pipe state doesn't match!\n");
8af6cf88
DV		 7916 }
7917}
7918
c0c36b94
CW		 7919int intel_set_mode(struct drm_crtc *crtc,
7920 struct drm_display_mode *mode,
7921 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7922{
7923 struct drm_device *dev = crtc->dev;
dbf2b54e 7924 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7925 struct drm_display_mode *saved_mode, *saved_hwmode;
7926 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7927 struct intel_crtc *intel_crtc;
7928 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7929 int ret = 0;
a6778b3c 7930
3ac18232 7931 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7932 if (!saved_mode)
7933 return -ENOMEM;
3ac18232 7934 saved_hwmode = saved_mode + 1;
a6778b3c 7935
e2e1ed41 7936 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7937 &prepare_pipes, &disable_pipes);
7938
3ac18232
TG		 7939 *saved_hwmode = crtc->hwmode;
7940 *saved_mode = crtc->mode;
a6778b3c 7941
25c5b266
DV		 7942 /* Hack: Because we don't (yet) support global modeset on multiple
7943 * crtcs, we don't keep track of the new mode for more than one crtc.
7944 * Hence simply check whether any bit is set in modeset_pipes in all the
7945 * pieces of code that are not yet converted to deal with mutliple crtcs
7946 * changing their mode at the same time. */
25c5b266 7947 if (modeset_pipes) {
4e53c2e0 7948 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7949 if (IS_ERR(pipe_config)) {
7950 ret = PTR_ERR(pipe_config);
7951 pipe_config = NULL;
7952
3ac18232 7953 goto out;
25c5b266 7954 }
25c5b266 7955 }
a6778b3c 7956
460da916
DV		 7957 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7958 modeset_pipes, prepare_pipes, disable_pipes);
7959
7960 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7961 intel_crtc_disable(&intel_crtc->base);
7962
ea9d758d
DV		 7963 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7964 if (intel_crtc->base.enabled)
7965 dev_priv->display.crtc_disable(&intel_crtc->base);
7966 }
a6778b3c 7967
6c4c86f5
DV		 7968 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7969 * to set it here already despite that we pass it down the callchain.
f6e5b160 7970 */
b8cecdf5 7971 if (modeset_pipes) {
25c5b266 7972 crtc->mode = *mode;
b8cecdf5
DV		 7973 /* mode_set/enable/disable functions rely on a correct pipe
7974 * config. */
7975 to_intel_crtc(crtc)->config = *pipe_config;
7976 }
7758a113 7977
ea9d758d
DV		 7978 /* Only after disabling all output pipelines that will be changed can we
7979 * update the the output configuration. */
7980 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7981
47fab737
DV		 7982 if (dev_priv->display.modeset_global_resources)
7983 dev_priv->display.modeset_global_resources(dev);
7984
a6778b3c
DV		 7985 /* Set up the DPLL and any encoders state that needs to adjust or depend
7986 * on the DPLL.
f6e5b160 7987 */
25c5b266 7988 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 7989 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 7990 x, y, fb);
7991 if (ret)
7992 goto done;
a6778b3c
DV		 7993 }
7994
7995 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7996 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7997 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7998
25c5b266
DV		 7999 if (modeset_pipes) {
8000 /* Store real post-adjustment hardware mode. */
b8cecdf5 8001 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8002
25c5b266
DV		 8003 /* Calculate and store various constants which
8004 * are later needed by vblank and swap-completion
8005 * timestamping. They are derived from true hwmode.
8006 */
8007 drm_calc_timestamping_constants(crtc);
8008 }
a6778b3c
DV		 8009
8010 /* FIXME: add subpixel order */
8011done:
c0c36b94 8012 if (ret && crtc->enabled) {
3ac18232
TG		 8013 crtc->hwmode = *saved_hwmode;
8014 crtc->mode = *saved_mode;
8af6cf88
DV		 8015 } else {
8016 intel_modeset_check_state(dev);
a6778b3c
DV		 8017 }
8018
3ac18232 8019out:
b8cecdf5 8020 kfree(pipe_config);
3ac18232 8021 kfree(saved_mode);
a6778b3c 8022 return ret;
f6e5b160
CW		 8023}
8024
c0c36b94
CW		 8025void intel_crtc_restore_mode(struct drm_crtc *crtc)
8026{
8027 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8028}
8029
25c5b266
DV		 8030#undef for_each_intel_crtc_masked
8031
d9e55608
DV		 8032static void intel_set_config_free(struct intel_set_config *config)
8033{
8034 if (!config)
8035 return;
8036
1aa4b628
DV		 8037 kfree(config->save_connector_encoders);
8038 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8039 kfree(config);
8040}
8041
85f9eb71
DV		 8042static int intel_set_config_save_state(struct drm_device *dev,
8043 struct intel_set_config *config)
8044{
85f9eb71
DV		 8045 struct drm_encoder *encoder;
8046 struct drm_connector *connector;
8047 int count;
8048
1aa4b628
DV		 8049 config->save_encoder_crtcs =
8050 kcalloc(dev->mode_config.num_encoder,
8051 sizeof(struct drm_crtc *), GFP_KERNEL);
8052 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8053 return -ENOMEM;
8054
1aa4b628
DV		 8055 config->save_connector_encoders =
8056 kcalloc(dev->mode_config.num_connector,
8057 sizeof(struct drm_encoder *), GFP_KERNEL);
8058 if (!config->save_connector_encoders)
85f9eb71
DV		 8059 return -ENOMEM;
8060
8061 /* Copy data. Note that driver private data is not affected.
8062 * Should anything bad happen only the expected state is
8063 * restored, not the drivers personal bookkeeping.
8064 */
85f9eb71
DV		 8065 count = 0;
8066 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8067 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8068 }
8069
8070 count = 0;
8071 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8072 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8073 }
8074
8075 return 0;
8076}
8077
8078static void intel_set_config_restore_state(struct drm_device *dev,
8079 struct intel_set_config *config)
8080{
9a935856
DV		 8081 struct intel_encoder *encoder;
8082 struct intel_connector *connector;
85f9eb71
DV		 8083 int count;
8084
85f9eb71 8085 count = 0;
9a935856
DV		 8086 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8087 encoder->new_crtc =
8088 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8089 }
8090
8091 count = 0;
9a935856
DV		 8092 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8093 connector->new_encoder =
8094 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8095 }
8096}
8097
5e2b584e
DV		 8098static void
8099intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8100 struct intel_set_config *config)
8101{
8102
8103 /* We should be able to check here if the fb has the same properties
8104 * and then just flip_or_move it */
8105 if (set->crtc->fb != set->fb) {
8106 /* If we have no fb then treat it as a full mode set */
8107 if (set->crtc->fb == NULL) {
8108 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8109 config->mode_changed = true;
8110 } else if (set->fb == NULL) {
8111 config->mode_changed = true;
72f4901e
DV		 8112 } else if (set->fb->pixel_format !=
8113 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8114 config->mode_changed = true;
8115 } else
8116 config->fb_changed = true;
8117 }
8118
835c5873 8119 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8120 config->fb_changed = true;
8121
8122 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8123 DRM_DEBUG_KMS("modes are different, full mode set\n");
8124 drm_mode_debug_printmodeline(&set->crtc->mode);
8125 drm_mode_debug_printmodeline(set->mode);
8126 config->mode_changed = true;
8127 }
8128}
8129
2e431051 8130static int
9a935856
DV		 8131intel_modeset_stage_output_state(struct drm_device *dev,
8132 struct drm_mode_set *set,
8133 struct intel_set_config *config)
50f56119 8134{
85f9eb71 8135 struct drm_crtc *new_crtc;
9a935856
DV		 8136 struct intel_connector *connector;
8137 struct intel_encoder *encoder;
2e431051 8138 int count, ro;
50f56119 8139
9abdda74 8140 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8141 * of connectors. For paranoia, double-check this. */
8142 WARN_ON(!set->fb && (set->num_connectors != 0));
8143 WARN_ON(set->fb && (set->num_connectors == 0));
8144
50f56119 8145 count = 0;
9a935856
DV		 8146 list_for_each_entry(connector, &dev->mode_config.connector_list,
8147 base.head) {
8148 /* Otherwise traverse passed in connector list and get encoders
8149 * for them. */
50f56119 8150 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8151 if (set->connectors[ro] == &connector->base) {
8152 connector->new_encoder = connector->encoder;
50f56119
DV		 8153 break;
8154 }
8155 }
8156
9a935856
DV		 8157 /* If we disable the crtc, disable all its connectors. Also, if
8158 * the connector is on the changing crtc but not on the new
8159 * connector list, disable it. */
8160 if ((!set->fb || ro == set->num_connectors) &&
8161 connector->base.encoder &&
8162 connector->base.encoder->crtc == set->crtc) {
8163 connector->new_encoder = NULL;
8164
8165 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8166 connector->base.base.id,
8167 drm_get_connector_name(&connector->base));
8168 }
8169
8170
8171 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8172 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8173 config->mode_changed = true;
50f56119
DV		 8174 }
8175 }
9a935856 8176 /* connector->new_encoder is now updated for all connectors. */
50f56119 8177
9a935856 8178 /* Update crtc of enabled connectors. */
50f56119 8179 count = 0;
9a935856
DV		 8180 list_for_each_entry(connector, &dev->mode_config.connector_list,
8181 base.head) {
8182 if (!connector->new_encoder)
50f56119
DV		 8183 continue;
8184
9a935856 8185 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8186
8187 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8188 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8189 new_crtc = set->crtc;
8190 }
8191
8192 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8193 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8194 new_crtc)) {
5e2b584e 8195 return -EINVAL;
50f56119 8196 }
9a935856
DV		 8197 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8198
8199 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8200 connector->base.base.id,
8201 drm_get_connector_name(&connector->base),
8202 new_crtc->base.id);
8203 }
8204
8205 /* Check for any encoders that needs to be disabled. */
8206 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8207 base.head) {
8208 list_for_each_entry(connector,
8209 &dev->mode_config.connector_list,
8210 base.head) {
8211 if (connector->new_encoder == encoder) {
8212 WARN_ON(!connector->new_encoder->new_crtc);
8213
8214 goto next_encoder;
8215 }
8216 }
8217 encoder->new_crtc = NULL;
8218next_encoder:
8219 /* Only now check for crtc changes so we don't miss encoders
8220 * that will be disabled. */
8221 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8222 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8223 config->mode_changed = true;
50f56119
DV		 8224 }
8225 }
9a935856 8226 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8227
2e431051
DV		 8228 return 0;
8229}
8230
8231static int intel_crtc_set_config(struct drm_mode_set *set)
8232{
8233 struct drm_device *dev;
2e431051
DV		 8234 struct drm_mode_set save_set;
8235 struct intel_set_config *config;
8236 int ret;
2e431051 8237
8d3e375e
DV		 8238 BUG_ON(!set);
8239 BUG_ON(!set->crtc);
8240 BUG_ON(!set->crtc->helper_private);
2e431051 8241
7e53f3a4
DV		 8242 /* Enforce sane interface api - has been abused by the fb helper. */
8243 BUG_ON(!set->mode && set->fb);
8244 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8245
2e431051
DV		 8246 if (set->fb) {
8247 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8248 set->crtc->base.id, set->fb->base.id,
8249 (int)set->num_connectors, set->x, set->y);
8250 } else {
8251 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8252 }
8253
8254 dev = set->crtc->dev;
8255
8256 ret = -ENOMEM;
8257 config = kzalloc(sizeof(*config), GFP_KERNEL);
8258 if (!config)
8259 goto out_config;
8260
8261 ret = intel_set_config_save_state(dev, config);
8262 if (ret)
8263 goto out_config;
8264
8265 save_set.crtc = set->crtc;
8266 save_set.mode = &set->crtc->mode;
8267 save_set.x = set->crtc->x;
8268 save_set.y = set->crtc->y;
8269 save_set.fb = set->crtc->fb;
8270
8271 /* Compute whether we need a full modeset, only an fb base update or no
8272 * change at all. In the future we might also check whether only the
8273 * mode changed, e.g. for LVDS where we only change the panel fitter in
8274 * such cases. */
8275 intel_set_config_compute_mode_changes(set, config);
8276
9a935856 8277 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8278 if (ret)
8279 goto fail;
8280
5e2b584e 8281 if (config->mode_changed) {
87f1faa6 8282 if (set->mode) {
50f56119
DV		 8283 DRM_DEBUG_KMS("attempting to set mode from"
8284 " userspace\n");
8285 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8286 }
8287
c0c36b94
CW		 8288 ret = intel_set_mode(set->crtc, set->mode,
8289 set->x, set->y, set->fb);
8290 if (ret) {
8291 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8292 set->crtc->base.id, ret);
87f1faa6
DV		 8293 goto fail;
8294 }
5e2b584e 8295 } else if (config->fb_changed) {
4878cae2
VS		 8296 intel_crtc_wait_for_pending_flips(set->crtc);
8297
4f660f49 8298 ret = intel_pipe_set_base(set->crtc,
94352cf9 8299 set->x, set->y, set->fb);
50f56119
DV		 8300 }
8301
d9e55608
DV		 8302 intel_set_config_free(config);
8303
50f56119
DV		 8304 return 0;
8305
8306fail:
85f9eb71 8307 intel_set_config_restore_state(dev, config);
50f56119
DV		 8308
8309 /* Try to restore the config */
5e2b584e 8310 if (config->mode_changed &&
c0c36b94
CW		 8311 intel_set_mode(save_set.crtc, save_set.mode,
8312 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8313 DRM_ERROR("failed to restore config after modeset failure\n");
8314
d9e55608
DV		 8315out_config:
8316 intel_set_config_free(config);
50f56119
DV		 8317 return ret;
8318}
f6e5b160
CW		 8319
8320static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8321 .cursor_set = intel_crtc_cursor_set,
8322 .cursor_move = intel_crtc_cursor_move,
8323 .gamma_set = intel_crtc_gamma_set,
50f56119 8324 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8325 .destroy = intel_crtc_destroy,
8326 .page_flip = intel_crtc_page_flip,
8327};
8328
79f689aa
PZ		 8329static void intel_cpu_pll_init(struct drm_device *dev)
8330{
affa9354 8331 if (HAS_DDI(dev))
79f689aa
PZ		 8332 intel_ddi_pll_init(dev);
8333}
8334
ee7b9f93
JB		 8335static void intel_pch_pll_init(struct drm_device *dev)
8336{
8337 drm_i915_private_t *dev_priv = dev->dev_private;
8338 int i;
8339
8340 if (dev_priv->num_pch_pll == 0) {
8341 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8342 return;
8343 }
8344
8345 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8346 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8347 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8348 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8349 }
8350}
8351
b358d0a6 8352static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8353{
22fd0fab 8354 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8355 struct intel_crtc *intel_crtc;
8356 int i;
8357
8358 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8359 if (intel_crtc == NULL)
8360 return;
8361
8362 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8363
8364 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8365 for (i = 0; i < 256; i++) {
8366 intel_crtc->lut_r[i] = i;
8367 intel_crtc->lut_g[i] = i;
8368 intel_crtc->lut_b[i] = i;
8369 }
8370
80824003
JB		 8371 /* Swap pipes & planes for FBC on pre-965 */
8372 intel_crtc->pipe = pipe;
8373 intel_crtc->plane = pipe;
a5c961d1 8374 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8375 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8376 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8377 intel_crtc->plane = !pipe;
80824003
JB		 8378 }
8379
22fd0fab
JB		 8380 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8381 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8382 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8383 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8384
79e53945 8385 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8386}
8387
08d7b3d1 8388int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8389 struct drm_file *file)
08d7b3d1 8390{
08d7b3d1 8391 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8392 struct drm_mode_object *drmmode_obj;
8393 struct intel_crtc *crtc;
08d7b3d1 8394
1cff8f6b
DV		 8395 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8396 return -ENODEV;
08d7b3d1 8397
c05422d5
DV		 8398 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8399 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8400
c05422d5 8401 if (!drmmode_obj) {
08d7b3d1
CW		 8402 DRM_ERROR("no such CRTC id\n");
8403 return -EINVAL;
8404 }
8405
c05422d5
DV		 8406 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8407 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8408
c05422d5 8409 return 0;
08d7b3d1
CW		 8410}
8411
66a9278e 8412static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8413{
66a9278e
DV		 8414 struct drm_device *dev = encoder->base.dev;
8415 struct intel_encoder *source_encoder;
79e53945 8416 int index_mask = 0;
79e53945
JB		 8417 int entry = 0;
8418
66a9278e
DV		 8419 list_for_each_entry(source_encoder,
8420 &dev->mode_config.encoder_list, base.head) {
8421
8422 if (encoder == source_encoder)
79e53945 8423 index_mask |= (1 << entry);
66a9278e
DV		 8424
8425 /* Intel hw has only one MUX where enocoders could be cloned. */
8426 if (encoder->cloneable && source_encoder->cloneable)
8427 index_mask |= (1 << entry);
8428
79e53945
JB		 8429 entry++;
8430 }
4ef69c7a 8431
79e53945
JB		 8432 return index_mask;
8433}
8434
4d302442
CW		 8435static bool has_edp_a(struct drm_device *dev)
8436{
8437 struct drm_i915_private *dev_priv = dev->dev_private;
8438
8439 if (!IS_MOBILE(dev))
8440 return false;
8441
8442 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8443 return false;
8444
8445 if (IS_GEN5(dev) &&
8446 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8447 return false;
8448
8449 return true;
8450}
8451
79e53945
JB		 8452static void intel_setup_outputs(struct drm_device *dev)
8453{
725e30ad 8454 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8455 struct intel_encoder *encoder;
cb0953d7 8456 bool dpd_is_edp = false;
f3cfcba6 8457 bool has_lvds;
79e53945 8458
f3cfcba6 8459 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8460 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8461 /* disable the panel fitter on everything but LVDS */
8462 I915_WRITE(PFIT_CONTROL, 0);
8463 }
79e53945 8464
affa9354 8465 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8466 intel_crt_init(dev);
cb0953d7 8467
affa9354 8468 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8469 int found;
8470
8471 /* Haswell uses DDI functions to detect digital outputs */
8472 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8473 /* DDI A only supports eDP */
8474 if (found)
8475 intel_ddi_init(dev, PORT_A);
8476
8477 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8478 * register */
8479 found = I915_READ(SFUSE_STRAP);
8480
8481 if (found & SFUSE_STRAP_DDIB_DETECTED)
8482 intel_ddi_init(dev, PORT_B);
8483 if (found & SFUSE_STRAP_DDIC_DETECTED)
8484 intel_ddi_init(dev, PORT_C);
8485 if (found & SFUSE_STRAP_DDID_DETECTED)
8486 intel_ddi_init(dev, PORT_D);
8487 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8488 int found;
270b3042
DV		 8489 dpd_is_edp = intel_dpd_is_edp(dev);
8490
8491 if (has_edp_a(dev))
8492 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8493
dc0fa718 8494 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8495 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8496 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8497 if (!found)
e2debe91 8498 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8499 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8500 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8501 }
8502
dc0fa718 8503 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8504 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8505
dc0fa718 8506 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8507 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8508
5eb08b69 8509 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8510 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8511
270b3042 8512 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8513 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8514 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8515 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8516 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8517 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8518
dc0fa718 8519 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8520 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8521 PORT_B);
67cfc203
VS		 8522 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8523 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8524 }
103a196f 8525 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8526 bool found = false;
7d57382e 8527
e2debe91 8528 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8529 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8530 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8531 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8532 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8533 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8534 }
27185ae1 8535
b01f2c3a
JB		 8536 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8537 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8538 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8539 }
725e30ad 8540 }
13520b05
KH		 8541
8542 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8543
e2debe91 8544 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8545 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8546 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8547 }
27185ae1 8548
e2debe91 8549 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8550
b01f2c3a
JB		 8551 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8552 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8553 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8554 }
8555 if (SUPPORTS_INTEGRATED_DP(dev)) {
8556 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8557 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8558 }
725e30ad 8559 }
27185ae1 8560
b01f2c3a
JB		 8561 if (SUPPORTS_INTEGRATED_DP(dev) &&
8562 (I915_READ(DP_D) & DP_DETECTED)) {
8563 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8564 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8565 }
bad720ff 8566 } else if (IS_GEN2(dev))
79e53945
JB		 8567 intel_dvo_init(dev);
8568
103a196f 8569 if (SUPPORTS_TV(dev))
79e53945
JB		 8570 intel_tv_init(dev);
8571
4ef69c7a
CW		 8572 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8573 encoder->base.possible_crtcs = encoder->crtc_mask;
8574 encoder->base.possible_clones =
66a9278e 8575 intel_encoder_clones(encoder);
79e53945 8576 }
47356eb6 8577
dde86e2d 8578 intel_init_pch_refclk(dev);
270b3042
DV		 8579
8580 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8581}
8582
8583static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8584{
8585 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8586
8587 drm_framebuffer_cleanup(fb);
05394f39 8588 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8589
8590 kfree(intel_fb);
8591}
8592
8593static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8594 struct drm_file *file,
79e53945
JB		 8595 unsigned int *handle)
8596{
8597 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8598 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8599
05394f39 8600 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8601}
8602
8603static const struct drm_framebuffer_funcs intel_fb_funcs = {
8604 .destroy = intel_user_framebuffer_destroy,
8605 .create_handle = intel_user_framebuffer_create_handle,
8606};
8607
38651674
DA		 8608int intel_framebuffer_init(struct drm_device *dev,
8609 struct intel_framebuffer *intel_fb,
308e5bcb 8610 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8611 struct drm_i915_gem_object *obj)
79e53945 8612{
79e53945
JB		 8613 int ret;
8614
c16ed4be
CW		 8615 if (obj->tiling_mode == I915_TILING_Y) {
8616 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8617 return -EINVAL;
c16ed4be 8618 }
57cd6508 8619
c16ed4be
CW		 8620 if (mode_cmd->pitches[0] & 63) {
8621 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8622 mode_cmd->pitches[0]);
57cd6508 8623 return -EINVAL;
c16ed4be 8624 }
57cd6508 8625
5d7bd705 8626 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8627 if (mode_cmd->pitches[0] > 32768) {
8628 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8629 mode_cmd->pitches[0]);
5d7bd705 8630 return -EINVAL;
c16ed4be 8631 }
5d7bd705
VS		 8632
8633 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8634 mode_cmd->pitches[0] != obj->stride) {
8635 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8636 mode_cmd->pitches[0], obj->stride);
5d7bd705 8637 return -EINVAL;
c16ed4be 8638 }
5d7bd705 8639
57779d06 8640 /* Reject formats not supported by any plane early. */
308e5bcb 8641 switch (mode_cmd->pixel_format) {
57779d06 8642 case DRM_FORMAT_C8:
04b3924d
VS		 8643 case DRM_FORMAT_RGB565:
8644 case DRM_FORMAT_XRGB8888:
8645 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8646 break;
8647 case DRM_FORMAT_XRGB1555:
8648 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8649 if (INTEL_INFO(dev)->gen > 3) {
8650 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8651 return -EINVAL;
c16ed4be 8652 }
57779d06
VS		 8653 break;
8654 case DRM_FORMAT_XBGR8888:
8655 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8656 case DRM_FORMAT_XRGB2101010:
8657 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8658 case DRM_FORMAT_XBGR2101010:
8659 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8660 if (INTEL_INFO(dev)->gen < 4) {
8661 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8662 return -EINVAL;
c16ed4be 8663 }
b5626747 8664 break;
04b3924d
VS		 8665 case DRM_FORMAT_YUYV:
8666 case DRM_FORMAT_UYVY:
8667 case DRM_FORMAT_YVYU:
8668 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8669 if (INTEL_INFO(dev)->gen < 5) {
8670 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8671 return -EINVAL;
c16ed4be 8672 }
57cd6508
CW		 8673 break;
8674 default:
c16ed4be 8675 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8676 return -EINVAL;
8677 }
8678
90f9a336
VS		 8679 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8680 if (mode_cmd->offsets[0] != 0)
8681 return -EINVAL;
8682
c7d73f6a
DV		 8683 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8684 intel_fb->obj = obj;
8685
79e53945
JB		 8686 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8687 if (ret) {
8688 DRM_ERROR("framebuffer init failed %d\n", ret);
8689 return ret;
8690 }
8691
79e53945
JB		 8692 return 0;
8693}
8694
79e53945
JB		 8695static struct drm_framebuffer *
8696intel_user_framebuffer_create(struct drm_device *dev,
8697 struct drm_file *filp,
308e5bcb 8698 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8699{
05394f39 8700 struct drm_i915_gem_object *obj;
79e53945 8701
308e5bcb
JB		 8702 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8703 mode_cmd->handles[0]));
c8725226 8704 if (&obj->base == NULL)
cce13ff7 8705 return ERR_PTR(-ENOENT);
79e53945 8706
d2dff872 8707 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8708}
8709
79e53945 8710static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8711 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8712 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8713};
8714
e70236a8
JB		 8715/* Set up chip specific display functions */
8716static void intel_init_display(struct drm_device *dev)
8717{
8718 struct drm_i915_private *dev_priv = dev->dev_private;
8719
affa9354 8720 if (HAS_DDI(dev)) {
0e8ffe1b 8721 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8722 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8723 dev_priv->display.crtc_enable = haswell_crtc_enable;
8724 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8725 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8726 dev_priv->display.update_plane = ironlake_update_plane;
8727 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8728 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8729 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8730 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8731 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8732 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8733 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8734 } else {
0e8ffe1b 8735 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8736 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8737 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8738 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8739 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8740 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8741 }
e70236a8 8742
e70236a8 8743 /* Returns the core display clock speed */
25eb05fc
JB		 8744 if (IS_VALLEYVIEW(dev))
8745 dev_priv->display.get_display_clock_speed =
8746 valleyview_get_display_clock_speed;
8747 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8748 dev_priv->display.get_display_clock_speed =
8749 i945_get_display_clock_speed;
8750 else if (IS_I915G(dev))
8751 dev_priv->display.get_display_clock_speed =
8752 i915_get_display_clock_speed;
f2b115e6 8753 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8754 dev_priv->display.get_display_clock_speed =
8755 i9xx_misc_get_display_clock_speed;
8756 else if (IS_I915GM(dev))
8757 dev_priv->display.get_display_clock_speed =
8758 i915gm_get_display_clock_speed;
8759 else if (IS_I865G(dev))
8760 dev_priv->display.get_display_clock_speed =
8761 i865_get_display_clock_speed;
f0f8a9ce 8762 else if (IS_I85X(dev))
e70236a8
JB		 8763 dev_priv->display.get_display_clock_speed =
8764 i855_get_display_clock_speed;
8765 else /* 852, 830 */
8766 dev_priv->display.get_display_clock_speed =
8767 i830_get_display_clock_speed;
8768
7f8a8569 8769 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8770 if (IS_GEN5(dev)) {
674cf967 8771 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8772 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8773 } else if (IS_GEN6(dev)) {
674cf967 8774 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8775 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8776 } else if (IS_IVYBRIDGE(dev)) {
8777 /* FIXME: detect B0+ stepping and use auto training */
8778 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8779 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8780 dev_priv->display.modeset_global_resources =
8781 ivb_modeset_global_resources;
c82e4d26
ED		 8782 } else if (IS_HASWELL(dev)) {
8783 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8784 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8785 dev_priv->display.modeset_global_resources =
8786 haswell_modeset_global_resources;
a0e63c22 8787 }
6067aaea 8788 } else if (IS_G4X(dev)) {
e0dac65e 8789 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8790 }
8c9f3aaf
JB		 8791
8792 /* Default just returns -ENODEV to indicate unsupported */
8793 dev_priv->display.queue_flip = intel_default_queue_flip;
8794
8795 switch (INTEL_INFO(dev)->gen) {
8796 case 2:
8797 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8798 break;
8799
8800 case 3:
8801 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8802 break;
8803
8804 case 4:
8805 case 5:
8806 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8807 break;
8808
8809 case 6:
8810 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8811 break;
7c9017e5
JB		 8812 case 7:
8813 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8814 break;
8c9f3aaf 8815 }
e70236a8
JB		 8816}
8817
b690e96c
JB		 8818/*
8819 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8820 * resume, or other times. This quirk makes sure that's the case for
8821 * affected systems.
8822 */
0206e353 8823static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8824{
8825 struct drm_i915_private *dev_priv = dev->dev_private;
8826
8827 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8828 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8829}
8830
435793df
KP		 8831/*
8832 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8833 */
8834static void quirk_ssc_force_disable(struct drm_device *dev)
8835{
8836 struct drm_i915_private *dev_priv = dev->dev_private;
8837 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8838 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8839}
8840
4dca20ef 8841/*
5a15ab5b
CE		 8842 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8843 * brightness value
4dca20ef
CE		 8844 */
8845static void quirk_invert_brightness(struct drm_device *dev)
8846{
8847 struct drm_i915_private *dev_priv = dev->dev_private;
8848 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8849 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8850}
8851
b690e96c
JB		 8852struct intel_quirk {
8853 int device;
8854 int subsystem_vendor;
8855 int subsystem_device;
8856 void (*hook)(struct drm_device *dev);
8857};
8858
5f85f176
EE		 8859/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8860struct intel_dmi_quirk {
8861 void (*hook)(struct drm_device *dev);
8862 const struct dmi_system_id (*dmi_id_list)[];
8863};
8864
8865static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8866{
8867 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8868 return 1;
8869}
8870
8871static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8872 {
8873 .dmi_id_list = &(const struct dmi_system_id[]) {
8874 {
8875 .callback = intel_dmi_reverse_brightness,
8876 .ident = "NCR Corporation",
8877 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8878 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8879 },
8880 },
8881 { } /* terminating entry */
8882 },
8883 .hook = quirk_invert_brightness,
8884 },
8885};
8886
c43b5634 8887static struct intel_quirk intel_quirks[] = {
b690e96c 8888 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8889 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8890
b690e96c
JB		 8891 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8892 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8893
b690e96c
JB		 8894 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8895 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8896
ccd0d36e 8897 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8898 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8899 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8900
8901 /* Lenovo U160 cannot use SSC on LVDS */
8902 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8903
8904 /* Sony Vaio Y cannot use SSC on LVDS */
8905 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8906
8907 /* Acer Aspire 5734Z must invert backlight brightness */
8908 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8909
8910 /* Acer/eMachines G725 */
8911 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8912
8913 /* Acer/eMachines e725 */
8914 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8915
8916 /* Acer/Packard Bell NCL20 */
8917 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8918
8919 /* Acer Aspire 4736Z */
8920 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8921};
8922
8923static void intel_init_quirks(struct drm_device *dev)
8924{
8925 struct pci_dev *d = dev->pdev;
8926 int i;
8927
8928 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8929 struct intel_quirk *q = &intel_quirks[i];
8930
8931 if (d->device == q->device &&
8932 (d->subsystem_vendor == q->subsystem_vendor ||
8933 q->subsystem_vendor == PCI_ANY_ID) &&
8934 (d->subsystem_device == q->subsystem_device ||
8935 q->subsystem_device == PCI_ANY_ID))
8936 q->hook(dev);
8937 }
5f85f176
EE		 8938 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8939 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8940 intel_dmi_quirks[i].hook(dev);
8941 }
b690e96c
JB		 8942}
8943
9cce37f4
JB		 8944/* Disable the VGA plane that we never use */
8945static void i915_disable_vga(struct drm_device *dev)
8946{
8947 struct drm_i915_private *dev_priv = dev->dev_private;
8948 u8 sr1;
766aa1c4 8949 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8950
8951 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8952 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8953 sr1 = inb(VGA_SR_DATA);
8954 outb(sr1 | 1<<5, VGA_SR_DATA);
8955 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8956 udelay(300);
8957
8958 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8959 POSTING_READ(vga_reg);
8960}
8961
f817586c
DV		 8962void intel_modeset_init_hw(struct drm_device *dev)
8963{
fa42e23c 8964 intel_init_power_well(dev);
0232e927 8965
a8f78b58
ED		 8966 intel_prepare_ddi(dev);
8967
f817586c
DV		 8968 intel_init_clock_gating(dev);
8969
79f5b2c7 8970 mutex_lock(&dev->struct_mutex);
8090c6b9 8971 intel_enable_gt_powersave(dev);
79f5b2c7 8972 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8973}
8974
79e53945
JB		 8975void intel_modeset_init(struct drm_device *dev)
8976{
652c393a 8977 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 8978 int i, j, ret;
79e53945
JB		 8979
8980 drm_mode_config_init(dev);
8981
8982 dev->mode_config.min_width = 0;
8983 dev->mode_config.min_height = 0;
8984
019d96cb
DA		 8985 dev->mode_config.preferred_depth = 24;
8986 dev->mode_config.prefer_shadow = 1;
8987
e6ecefaa 8988 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8989
b690e96c
JB		 8990 intel_init_quirks(dev);
8991
1fa61106
ED		 8992 intel_init_pm(dev);
8993
e3c74757
BW		 8994 if (INTEL_INFO(dev)->num_pipes == 0)
8995 return;
8996
e70236a8
JB		 8997 intel_init_display(dev);
8998
a6c45cf0
CW		 8999 if (IS_GEN2(dev)) {
9000 dev->mode_config.max_width = 2048;
9001 dev->mode_config.max_height = 2048;
9002 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9003 dev->mode_config.max_width = 4096;
9004 dev->mode_config.max_height = 4096;
79e53945 9005 } else {
a6c45cf0
CW		 9006 dev->mode_config.max_width = 8192;
9007 dev->mode_config.max_height = 8192;
79e53945 9008 }
5d4545ae 9009 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9010
28c97730 9011 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9012 INTEL_INFO(dev)->num_pipes,
9013 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9014
7eb552ae 9015 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9016 intel_crtc_init(dev, i);
7f1f3851
JB		 9017 for (j = 0; j < dev_priv->num_plane; j++) {
9018 ret = intel_plane_init(dev, i, j);
9019 if (ret)
9020 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9021 i, j, ret);
9022 }
79e53945
JB		 9023 }
9024
79f689aa 9025 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9026 intel_pch_pll_init(dev);
9027
9cce37f4
JB		 9028 /* Just disable it once at startup */
9029 i915_disable_vga(dev);
79e53945 9030 intel_setup_outputs(dev);
11be49eb
CW		 9031
9032 /* Just in case the BIOS is doing something questionable. */
9033 intel_disable_fbc(dev);
2c7111db
CW		 9034}
9035
24929352
DV		 9036static void
9037intel_connector_break_all_links(struct intel_connector *connector)
9038{
9039 connector->base.dpms = DRM_MODE_DPMS_OFF;
9040 connector->base.encoder = NULL;
9041 connector->encoder->connectors_active = false;
9042 connector->encoder->base.crtc = NULL;
9043}
9044
7fad798e
DV		 9045static void intel_enable_pipe_a(struct drm_device *dev)
9046{
9047 struct intel_connector *connector;
9048 struct drm_connector *crt = NULL;
9049 struct intel_load_detect_pipe load_detect_temp;
9050
9051 /* We can't just switch on the pipe A, we need to set things up with a
9052 * proper mode and output configuration. As a gross hack, enable pipe A
9053 * by enabling the load detect pipe once. */
9054 list_for_each_entry(connector,
9055 &dev->mode_config.connector_list,
9056 base.head) {
9057 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9058 crt = &connector->base;
9059 break;
9060 }
9061 }
9062
9063 if (!crt)
9064 return;
9065
9066 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9067 intel_release_load_detect_pipe(crt, &load_detect_temp);
9068
652c393a 9069
7fad798e
DV		 9070}
9071
fa555837
DV		 9072static bool
9073intel_check_plane_mapping(struct intel_crtc *crtc)
9074{
7eb552ae
BW		 9075 struct drm_device *dev = crtc->base.dev;
9076 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9077 u32 reg, val;
9078
7eb552ae 9079 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9080 return true;
9081
9082 reg = DSPCNTR(!crtc->plane);
9083 val = I915_READ(reg);
9084
9085 if ((val & DISPLAY_PLANE_ENABLE) &&
9086 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9087 return false;
9088
9089 return true;
9090}
9091
24929352
DV		 9092static void intel_sanitize_crtc(struct intel_crtc *crtc)
9093{
9094 struct drm_device *dev = crtc->base.dev;
9095 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9096 u32 reg;
24929352 9097
24929352 9098 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 9099 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 9100 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9101
9102 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9103 * disable the crtc (and hence change the state) if it is wrong. Note
9104 * that gen4+ has a fixed plane -> pipe mapping. */
9105 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9106 struct intel_connector *connector;
9107 bool plane;
9108
24929352
DV		 9109 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9110 crtc->base.base.id);
9111
9112 /* Pipe has the wrong plane attached and the plane is active.
9113 * Temporarily change the plane mapping and disable everything
9114 * ... */
9115 plane = crtc->plane;
9116 crtc->plane = !plane;
9117 dev_priv->display.crtc_disable(&crtc->base);
9118 crtc->plane = plane;
9119
9120 /* ... and break all links. */
9121 list_for_each_entry(connector, &dev->mode_config.connector_list,
9122 base.head) {
9123 if (connector->encoder->base.crtc != &crtc->base)
9124 continue;
9125
9126 intel_connector_break_all_links(connector);
9127 }
9128
9129 WARN_ON(crtc->active);
9130 crtc->base.enabled = false;
9131 }
24929352 9132
7fad798e
DV		 9133 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9134 crtc->pipe == PIPE_A && !crtc->active) {
9135 /* BIOS forgot to enable pipe A, this mostly happens after
9136 * resume. Force-enable the pipe to fix this, the update_dpms
9137 * call below we restore the pipe to the right state, but leave
9138 * the required bits on. */
9139 intel_enable_pipe_a(dev);
9140 }
9141
24929352
DV		 9142 /* Adjust the state of the output pipe according to whether we
9143 * have active connectors/encoders. */
9144 intel_crtc_update_dpms(&crtc->base);
9145
9146 if (crtc->active != crtc->base.enabled) {
9147 struct intel_encoder *encoder;
9148
9149 /* This can happen either due to bugs in the get_hw_state
9150 * functions or because the pipe is force-enabled due to the
9151 * pipe A quirk. */
9152 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9153 crtc->base.base.id,
9154 crtc->base.enabled ? "enabled" : "disabled",
9155 crtc->active ? "enabled" : "disabled");
9156
9157 crtc->base.enabled = crtc->active;
9158
9159 /* Because we only establish the connector -> encoder ->
9160 * crtc links if something is active, this means the
9161 * crtc is now deactivated. Break the links. connector
9162 * -> encoder links are only establish when things are
9163 * actually up, hence no need to break them. */
9164 WARN_ON(crtc->active);
9165
9166 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9167 WARN_ON(encoder->connectors_active);
9168 encoder->base.crtc = NULL;
9169 }
9170 }
9171}
9172
9173static void intel_sanitize_encoder(struct intel_encoder *encoder)
9174{
9175 struct intel_connector *connector;
9176 struct drm_device *dev = encoder->base.dev;
9177
9178 /* We need to check both for a crtc link (meaning that the
9179 * encoder is active and trying to read from a pipe) and the
9180 * pipe itself being active. */
9181 bool has_active_crtc = encoder->base.crtc &&
9182 to_intel_crtc(encoder->base.crtc)->active;
9183
9184 if (encoder->connectors_active && !has_active_crtc) {
9185 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9186 encoder->base.base.id,
9187 drm_get_encoder_name(&encoder->base));
9188
9189 /* Connector is active, but has no active pipe. This is
9190 * fallout from our resume register restoring. Disable
9191 * the encoder manually again. */
9192 if (encoder->base.crtc) {
9193 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9194 encoder->base.base.id,
9195 drm_get_encoder_name(&encoder->base));
9196 encoder->disable(encoder);
9197 }
9198
9199 /* Inconsistent output/port/pipe state happens presumably due to
9200 * a bug in one of the get_hw_state functions. Or someplace else
9201 * in our code, like the register restore mess on resume. Clamp
9202 * things to off as a safer default. */
9203 list_for_each_entry(connector,
9204 &dev->mode_config.connector_list,
9205 base.head) {
9206 if (connector->encoder != encoder)
9207 continue;
9208
9209 intel_connector_break_all_links(connector);
9210 }
9211 }
9212 /* Enabled encoders without active connectors will be fixed in
9213 * the crtc fixup. */
9214}
9215
44cec740 9216void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9217{
9218 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9219 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9220
9221 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9222 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9223 i915_disable_vga(dev);
0fde901f
KM		 9224 }
9225}
9226
24929352
DV		 9227/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9228 * and i915 state tracking structures. */
45e2b5f6
DV		 9229void intel_modeset_setup_hw_state(struct drm_device *dev,
9230 bool force_restore)
24929352
DV		 9231{
9232 struct drm_i915_private *dev_priv = dev->dev_private;
9233 enum pipe pipe;
9234 u32 tmp;
b5644d05 9235 struct drm_plane *plane;
24929352
DV		 9236 struct intel_crtc *crtc;
9237 struct intel_encoder *encoder;
9238 struct intel_connector *connector;
9239
affa9354 9240 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9241 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9242
9243 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9244 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9245 case TRANS_DDI_EDP_INPUT_A_ON:
9246 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9247 pipe = PIPE_A;
9248 break;
9249 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9250 pipe = PIPE_B;
9251 break;
9252 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9253 pipe = PIPE_C;
9254 break;
aaa148ec
DL		 9255 default:
9256 /* A bogus value has been programmed, disable
9257 * the transcoder */
9258 WARN(1, "Bogus eDP source %08x\n", tmp);
9259 intel_ddi_disable_transcoder_func(dev_priv,
9260 TRANSCODER_EDP);
9261 goto setup_pipes;
e28d54cb
PZ		 9262 }
9263
9264 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9265 crtc->cpu_transcoder = TRANSCODER_EDP;
9266
9267 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9268 pipe_name(pipe));
9269 }
9270 }
9271
aaa148ec 9272setup_pipes:
0e8ffe1b
DV		 9273 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9274 base.head) {
88adfff1 9275 memset(&crtc->config, 0, sizeof(crtc->config));
0e8ffe1b
DV		 9276 crtc->active = dev_priv->display.get_pipe_config(crtc,
9277 &crtc->config);
24929352
DV		 9278
9279 crtc->base.enabled = crtc->active;
9280
9281 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9282 crtc->base.base.id,
9283 crtc->active ? "enabled" : "disabled");
9284 }
9285
affa9354 9286 if (HAS_DDI(dev))
6441ab5f
PZ		 9287 intel_ddi_setup_hw_pll_state(dev);
9288
24929352
DV		 9289 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9290 base.head) {
9291 pipe = 0;
9292
9293 if (encoder->get_hw_state(encoder, &pipe)) {
9294 encoder->base.crtc =
9295 dev_priv->pipe_to_crtc_mapping[pipe];
9296 } else {
9297 encoder->base.crtc = NULL;
9298 }
9299
9300 encoder->connectors_active = false;
9301 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9302 encoder->base.base.id,
9303 drm_get_encoder_name(&encoder->base),
9304 encoder->base.crtc ? "enabled" : "disabled",
9305 pipe);
9306 }
9307
9308 list_for_each_entry(connector, &dev->mode_config.connector_list,
9309 base.head) {
9310 if (connector->get_hw_state(connector)) {
9311 connector->base.dpms = DRM_MODE_DPMS_ON;
9312 connector->encoder->connectors_active = true;
9313 connector->base.encoder = &connector->encoder->base;
9314 } else {
9315 connector->base.dpms = DRM_MODE_DPMS_OFF;
9316 connector->base.encoder = NULL;
9317 }
9318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9319 connector->base.base.id,
9320 drm_get_connector_name(&connector->base),
9321 connector->base.encoder ? "enabled" : "disabled");
9322 }
9323
9324 /* HW state is read out, now we need to sanitize this mess. */
9325 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9326 base.head) {
9327 intel_sanitize_encoder(encoder);
9328 }
9329
9330 for_each_pipe(pipe) {
9331 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9332 intel_sanitize_crtc(crtc);
9333 }
9a935856 9334
45e2b5f6
DV		 9335 if (force_restore) {
9336 for_each_pipe(pipe) {
b5644d05
JB		 9337 struct drm_crtc *crtc =
9338 dev_priv->pipe_to_crtc_mapping[pipe];
9339 intel_crtc_restore_mode(crtc);
45e2b5f6 9340 }
b5644d05
JB		 9341 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9342 intel_plane_restore(plane);
0fde901f
KM		 9343
9344 i915_redisable_vga(dev);
45e2b5f6
DV		 9345 } else {
9346 intel_modeset_update_staged_output_state(dev);
9347 }
8af6cf88
DV		 9348
9349 intel_modeset_check_state(dev);
2e938892
DV		 9350
9351 drm_mode_config_reset(dev);
2c7111db
CW		 9352}
9353
9354void intel_modeset_gem_init(struct drm_device *dev)
9355{
1833b134 9356 intel_modeset_init_hw(dev);
02e792fb
DV		 9357
9358 intel_setup_overlay(dev);
24929352 9359
45e2b5f6 9360 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9361}
9362
9363void intel_modeset_cleanup(struct drm_device *dev)
9364{
652c393a
JB		 9365 struct drm_i915_private *dev_priv = dev->dev_private;
9366 struct drm_crtc *crtc;
9367 struct intel_crtc *intel_crtc;
9368
f87ea761 9369 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9370 mutex_lock(&dev->struct_mutex);
9371
723bfd70
JB		 9372 intel_unregister_dsm_handler();
9373
9374
652c393a
JB		 9375 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9376 /* Skip inactive CRTCs */
9377 if (!crtc->fb)
9378 continue;
9379
9380 intel_crtc = to_intel_crtc(crtc);
3dec0095 9381 intel_increase_pllclock(crtc);
652c393a
JB		 9382 }
9383
973d04f9 9384 intel_disable_fbc(dev);
e70236a8 9385
8090c6b9 9386 intel_disable_gt_powersave(dev);
0cdab21f 9387
930ebb46
DV		 9388 ironlake_teardown_rc6(dev);
9389
57f350b6
JB		 9390 if (IS_VALLEYVIEW(dev))
9391 vlv_init_dpio(dev);
9392
69341a5e
KH		 9393 mutex_unlock(&dev->struct_mutex);
9394
6c0d9350
DV		 9395 /* Disable the irq before mode object teardown, for the irq might
9396 * enqueue unpin/hotplug work. */
9397 drm_irq_uninstall(dev);
9398 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9399 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9400
1630fe75
CW		 9401 /* flush any delayed tasks or pending work */
9402 flush_scheduled_work();
9403
79e53945 9404 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9405
9406 intel_cleanup_overlay(dev);
79e53945
JB		 9407}
9408
f1c79df3
ZW		 9409/*
9410 * Return which encoder is currently attached for connector.
9411 */
df0e9248 9412struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9413{
df0e9248
CW		 9414 return &intel_attached_encoder(connector)->base;
9415}
f1c79df3 9416
df0e9248
CW		 9417void intel_connector_attach_encoder(struct intel_connector *connector,
9418 struct intel_encoder *encoder)
9419{
9420 connector->encoder = encoder;
9421 drm_mode_connector_attach_encoder(&connector->base,
9422 &encoder->base);
79e53945 9423}
28d52043
DA		 9424
9425/*
9426 * set vga decode state - true == enable VGA decode
9427 */
9428int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9429{
9430 struct drm_i915_private *dev_priv = dev->dev_private;
9431 u16 gmch_ctrl;
9432
9433 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9434 if (state)
9435 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9436 else
9437 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9438 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9439 return 0;
9440}
c4a1d9e4
CW		 9441
9442#ifdef CONFIG_DEBUG_FS
9443#include <linux/seq_file.h>
9444
9445struct intel_display_error_state {
9446 struct intel_cursor_error_state {
9447 u32 control;
9448 u32 position;
9449 u32 base;
9450 u32 size;
52331309 9451 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9452
9453 struct intel_pipe_error_state {
9454 u32 conf;
9455 u32 source;
9456
9457 u32 htotal;
9458 u32 hblank;
9459 u32 hsync;
9460 u32 vtotal;
9461 u32 vblank;
9462 u32 vsync;
52331309 9463 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9464
9465 struct intel_plane_error_state {
9466 u32 control;
9467 u32 stride;
9468 u32 size;
9469 u32 pos;
9470 u32 addr;
9471 u32 surface;
9472 u32 tile_offset;
52331309 9473 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9474};
9475
9476struct intel_display_error_state *
9477intel_display_capture_error_state(struct drm_device *dev)
9478{
0206e353 9479 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9480 struct intel_display_error_state *error;
702e7a56 9481 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9482 int i;
9483
9484 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9485 if (error == NULL)
9486 return NULL;
9487
52331309 9488 for_each_pipe(i) {
702e7a56
PZ		 9489 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9490
a18c4c3d
PZ		 9491 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9492 error->cursor[i].control = I915_READ(CURCNTR(i));
9493 error->cursor[i].position = I915_READ(CURPOS(i));
9494 error->cursor[i].base = I915_READ(CURBASE(i));
9495 } else {
9496 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9497 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9498 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9499 }
c4a1d9e4
CW		 9500
9501 error->plane[i].control = I915_READ(DSPCNTR(i));
9502 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9503 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9504 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9505 error->plane[i].pos = I915_READ(DSPPOS(i));
9506 }
ca291363
PZ		 9507 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9508 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9509 if (INTEL_INFO(dev)->gen >= 4) {
9510 error->plane[i].surface = I915_READ(DSPSURF(i));
9511 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9512 }
9513
702e7a56 9514 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9515 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9516 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9517 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9518 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9519 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9520 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9521 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9522 }
9523
9524 return error;
9525}
9526
9527void
9528intel_display_print_error_state(struct seq_file *m,
9529 struct drm_device *dev,
9530 struct intel_display_error_state *error)
9531{
9532 int i;
9533
7eb552ae 9534 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9535 for_each_pipe(i) {
c4a1d9e4
CW		 9536 seq_printf(m, "Pipe [%d]:\n", i);
9537 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9538 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9539 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9540 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9541 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9542 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9543 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9544 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9545
9546 seq_printf(m, "Plane [%d]:\n", i);
9547 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9548 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9549 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9550 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9551 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9552 }
4b71a570 9553 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9554 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9555 if (INTEL_INFO(dev)->gen >= 4) {
9556 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9557 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9558 }
9559
9560 seq_printf(m, "Cursor [%d]:\n", i);
9561 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9562 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9563 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9564 }
9565}
9566#endif
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