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drm/i915: Fix spurious -EIO/SIGBUS on wedged gpus
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
3b117c8f 895 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
15d199ea
PZ		 1230 if (!intel_using_power_well(dev_priv->dev) &&
1231 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
19332d7a
JB		 1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
92f2584a
JB		 1310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311{
1312 u32 val;
1313 bool enabled;
1314
9d82aa17
ED		 1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
92f2584a
JB		 1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324}
1325
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
92f2584a
JB		 1339}
1340
4e634389
KP		 1341static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1343{
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357}
1358
1519b995
KP		 1359static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
dc0fa718 1362 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1367 return false;
1368 } else {
dc0fa718 1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1370 return false;
1371 }
1372 return true;
1373}
1374
1375static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377{
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389}
1390
1391static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393{
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
291906f1 1406static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
291906f1 1408{
47a05eca 1409 u32 val = I915_READ(reg);
4e634389 1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1412 reg, pipe_name(pipe));
de9a35ab 1413
75c5da27
DV		 1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
de9a35ab 1416 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1417}
1418
1419static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421{
47a05eca 1422 u32 val = I915_READ(reg);
b70ad586 1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 reg, pipe_name(pipe));
de9a35ab 1426
dc0fa718 1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1428 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1429 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1430}
1431
1432static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
291906f1 1437
f0575e92
KP		 1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
b70ad586 1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1446 pipe_name(pipe));
291906f1
JB		 1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
b70ad586 1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1452 pipe_name(pipe));
291906f1 1453
e2debe91
PZ		 1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1457}
1458
63d7bbe9
JB		 1459/**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
7434a255
TR		 1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1471 */
1472static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
a0c4da24 1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498}
1499
1500/**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510{
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526}
1527
a416edef
ED		 1528/* SBI access */
1529static void
988d6ee8
PZ		 1530intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
a416edef 1532{
988d6ee8 1533 u32 tmp;
a416edef 1534
09153000 1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1536
39fb50f6 1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1540 return;
a416edef
ED		 1541 }
1542
988d6ee8
PZ		 1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1551
39fb50f6 1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1555 return;
a416edef 1556 }
a416edef
ED		 1557}
1558
1559static u32
988d6ee8
PZ		 1560intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
a416edef 1562{
39fb50f6 1563 u32 value = 0;
09153000 1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1565
39fb50f6 1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1569 return 0;
a416edef
ED		 1570 }
1571
988d6ee8
PZ		 1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1579
39fb50f6 1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1583 return 0;
a416edef
ED		 1584 }
1585
09153000 1586 return I915_READ(SBI_DATA);
a416edef
ED		 1587}
1588
92f2584a 1589/**
b6b4e185 1590 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
b6b4e185 1597static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1598{
ee7b9f93 1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1600 struct intel_pch_pll *pll;
92f2584a
JB		 1601 int reg;
1602 u32 val;
1603
48da64a8 1604 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1605 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
ee7b9f93
JB		 1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
92f2584a
JB		 1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
ee7b9f93 1620 if (pll->active++ && pll->on) {
92b27b08 1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
92f2584a
JB		 1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
ee7b9f93
JB		 1633
1634 pll->on = true;
92f2584a
JB		 1635}
1636
ee7b9f93 1637static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1638{
ee7b9f93
JB		 1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1641 int reg;
ee7b9f93 1642 u32 val;
4c609cb8 1643
92f2584a
JB		 1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1646 if (pll == NULL)
1647 return;
92f2584a 1648
48da64a8
CW		 1649 if (WARN_ON(pll->refcount == 0))
1650 return;
7a419866 1651
ee7b9f93
JB		 1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
7a419866 1655
48da64a8 1656 if (WARN_ON(pll->active == 0)) {
92b27b08 1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1658 return;
1659 }
1660
ee7b9f93 1661 if (--pll->active) {
92b27b08 1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1663 return;
ee7b9f93
JB		 1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1670
ee7b9f93 1671 reg = pll->pll_reg;
92f2584a
JB		 1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
ee7b9f93
JB		 1677
1678 pll->on = false;
92f2584a
JB		 1679}
1680
b8a4f404
PZ		 1681static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
040484af 1683{
23670b32 1684 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1686 uint32_t reg, val, pipeconf_val;
040484af
JB		 1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
040484af
JB		 1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
23670b32
DV		 1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
59c859d6 1707 }
23670b32 1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
5f7f726d 1711 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
dfd07d72
DV		 1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1720 }
5f7f726d
PZ		 1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
040484af
JB		 1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735}
1736
8fb033d7 1737static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1738 enum transcoder cpu_transcoder)
040484af 1739{
8fb033d7 1740 u32 val, pipeconf_val;
8fb033d7
PZ		 1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
8fb033d7 1745 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1748
223a6fdf
PZ		 1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
25f3ef11 1754 val = TRANS_ENABLE;
937bb610 1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1756
9a76b1c6
PZ		 1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
a35f2679 1759 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
25f3ef11 1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1766}
1767
b8a4f404
PZ		 1768static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
040484af 1770{
23670b32
DV		 1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
040484af
JB		 1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
291906f1
JB		 1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
040484af
JB		 1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
040484af
JB		 1796}
1797
ab4d966c 1798static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1799{
8fb033d7
PZ		 1800 u32 val;
1801
8a52fd9f 1802 val = I915_READ(_TRANSACONF);
8fb033d7 1803 val &= ~TRANS_ENABLE;
8a52fd9f 1804 I915_WRITE(_TRANSACONF, val);
8fb033d7 1805 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1812 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1813}
1814
b24e7179 1815/**
309cfea8 1816 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
040484af 1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
040484af
JB		 1829static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
b24e7179 1831{
702e7a56
PZ		 1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1a240d4d 1834 enum pipe pch_transcoder;
b24e7179
JB		 1835 int reg;
1836 u32 val;
1837
681e5811 1838 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
b24e7179
JB		 1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
cc391bbb 1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
040484af
JB		 1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
b24e7179 1859
702e7a56 1860 reg = PIPECONF(cpu_transcoder);
b24e7179 1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
1869/**
309cfea8 1870 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883{
702e7a56
PZ		 1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
b24e7179
JB		 1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
19332d7a 1894 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
702e7a56 1900 reg = PIPECONF(cpu_transcoder);
b24e7179 1901 val = I915_READ(reg);
00d70b15
CW		 1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907}
1908
d74362c9
KP		 1909/*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
6f1d69b0 1913void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1914 enum plane plane)
1915{
14f86147
DL		 1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1920}
1921
b24e7179
JB		 1922/**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
00d70b15
CW		 1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1945 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
b24e7179
JB		 1949/**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959{
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
00d70b15
CW		 1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971}
1972
693db184
CW		 1973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
127bd2ac 1982int
48b956c5 1983intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1984 struct drm_i915_gem_object *obj,
919926ae 1985 struct intel_ring_buffer *pipelined)
6b95a207 1986{
ce453d81 1987 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1988 u32 alignment;
1989 int ret;
1990
05394f39 1991 switch (obj->tiling_mode) {
6b95a207 1992 case I915_TILING_NONE:
534843da
CW		 1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
a6c45cf0 1995 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
6b95a207
KH		 1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
8bb6e959
DV		 2005 /* Despite that we check this in framebuffer_init userspace can
2006 * screw us over and change the tiling after the fact. Only
2007 * pinned buffers can't change their tiling. */
2008 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 2009 return -EINVAL;
2010 default:
2011 BUG();
2012 }
2013
693db184
CW		 2014 /* Note that the w/a also requires 64 PTE of padding following the
2015 * bo. We currently fill all unused PTE with the shadow page and so
2016 * we should always have valid PTE following the scanout preventing
2017 * the VT-d warning.
2018 */
2019 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2020 alignment = 256 * 1024;
2021
ce453d81 2022 dev_priv->mm.interruptible = false;
2da3b9b9 2023 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2024 if (ret)
ce453d81 2025 goto err_interruptible;
6b95a207
KH		 2026
2027 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2028 * fence, whereas 965+ only requires a fence if using
2029 * framebuffer compression. For simplicity, we always install
2030 * a fence as the cost is not that onerous.
2031 */
06d98131 2032 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2033 if (ret)
2034 goto err_unpin;
1690e1eb 2035
9a5a53b3 2036 i915_gem_object_pin_fence(obj);
6b95a207 2037
ce453d81 2038 dev_priv->mm.interruptible = true;
6b95a207 2039 return 0;
48b956c5
CW		 2040
2041err_unpin:
2042 i915_gem_object_unpin(obj);
ce453d81
CW		 2043err_interruptible:
2044 dev_priv->mm.interruptible = true;
48b956c5 2045 return ret;
6b95a207
KH		 2046}
2047
1690e1eb
CW		 2048void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2049{
2050 i915_gem_object_unpin_fence(obj);
2051 i915_gem_object_unpin(obj);
2052}
2053
c2c75131
DV		 2054/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2055 * is assumed to be a power-of-two. */
bc752862
CW		 2056unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2057 unsigned int tiling_mode,
2058 unsigned int cpp,
2059 unsigned int pitch)
c2c75131 2060{
bc752862
CW		 2061 if (tiling_mode != I915_TILING_NONE) {
2062 unsigned int tile_rows, tiles;
c2c75131 2063
bc752862
CW		 2064 tile_rows = *y / 8;
2065 *y %= 8;
c2c75131 2066
bc752862
CW		 2067 tiles = *x / (512/cpp);
2068 *x %= 512/cpp;
2069
2070 return tile_rows * pitch * 8 + tiles * 4096;
2071 } else {
2072 unsigned int offset;
2073
2074 offset = *y * pitch + *x * cpp;
2075 *y = 0;
2076 *x = (offset & 4095) / cpp;
2077 return offset & -4096;
2078 }
c2c75131
DV		 2079}
2080
17638cd6
JB		 2081static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2082 int x, int y)
81255565
JB		 2083{
2084 struct drm_device *dev = crtc->dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 struct intel_framebuffer *intel_fb;
05394f39 2088 struct drm_i915_gem_object *obj;
81255565 2089 int plane = intel_crtc->plane;
e506a0c6 2090 unsigned long linear_offset;
81255565 2091 u32 dspcntr;
5eddb70b 2092 u32 reg;
81255565
JB		 2093
2094 switch (plane) {
2095 case 0:
2096 case 1:
2097 break;
2098 default:
2099 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2100 return -EINVAL;
2101 }
2102
2103 intel_fb = to_intel_framebuffer(fb);
2104 obj = intel_fb->obj;
81255565 2105
5eddb70b
CW		 2106 reg = DSPCNTR(plane);
2107 dspcntr = I915_READ(reg);
81255565
JB		 2108 /* Mask out pixel format bits in case we change it */
2109 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2110 switch (fb->pixel_format) {
2111 case DRM_FORMAT_C8:
81255565
JB		 2112 dspcntr |= DISPPLANE_8BPP;
2113 break;
57779d06
VS		 2114 case DRM_FORMAT_XRGB1555:
2115 case DRM_FORMAT_ARGB1555:
2116 dspcntr |= DISPPLANE_BGRX555;
81255565 2117 break;
57779d06
VS		 2118 case DRM_FORMAT_RGB565:
2119 dspcntr |= DISPPLANE_BGRX565;
2120 break;
2121 case DRM_FORMAT_XRGB8888:
2122 case DRM_FORMAT_ARGB8888:
2123 dspcntr |= DISPPLANE_BGRX888;
2124 break;
2125 case DRM_FORMAT_XBGR8888:
2126 case DRM_FORMAT_ABGR8888:
2127 dspcntr |= DISPPLANE_RGBX888;
2128 break;
2129 case DRM_FORMAT_XRGB2101010:
2130 case DRM_FORMAT_ARGB2101010:
2131 dspcntr |= DISPPLANE_BGRX101010;
2132 break;
2133 case DRM_FORMAT_XBGR2101010:
2134 case DRM_FORMAT_ABGR2101010:
2135 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2136 break;
2137 default:
baba133a 2138 BUG();
81255565 2139 }
57779d06 2140
a6c45cf0 2141 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2142 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2143 dspcntr |= DISPPLANE_TILED;
2144 else
2145 dspcntr &= ~DISPPLANE_TILED;
2146 }
2147
5eddb70b 2148 I915_WRITE(reg, dspcntr);
81255565 2149
e506a0c6 2150 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2151
c2c75131
DV		 2152 if (INTEL_INFO(dev)->gen >= 4) {
2153 intel_crtc->dspaddr_offset =
bc752862
CW		 2154 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2155 fb->bits_per_pixel / 8,
2156 fb->pitches[0]);
c2c75131
DV		 2157 linear_offset -= intel_crtc->dspaddr_offset;
2158 } else {
e506a0c6 2159 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2160 }
e506a0c6
DV		 2161
2162 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2163 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2164 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2165 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2166 I915_MODIFY_DISPBASE(DSPSURF(plane),
2167 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2168 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2169 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2170 } else
e506a0c6 2171 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2172 POSTING_READ(reg);
81255565 2173
17638cd6
JB		 2174 return 0;
2175}
2176
2177static int ironlake_update_plane(struct drm_crtc *crtc,
2178 struct drm_framebuffer *fb, int x, int y)
2179{
2180 struct drm_device *dev = crtc->dev;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183 struct intel_framebuffer *intel_fb;
2184 struct drm_i915_gem_object *obj;
2185 int plane = intel_crtc->plane;
e506a0c6 2186 unsigned long linear_offset;
17638cd6
JB		 2187 u32 dspcntr;
2188 u32 reg;
2189
2190 switch (plane) {
2191 case 0:
2192 case 1:
27f8227b 2193 case 2:
17638cd6
JB		 2194 break;
2195 default:
2196 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2197 return -EINVAL;
2198 }
2199
2200 intel_fb = to_intel_framebuffer(fb);
2201 obj = intel_fb->obj;
2202
2203 reg = DSPCNTR(plane);
2204 dspcntr = I915_READ(reg);
2205 /* Mask out pixel format bits in case we change it */
2206 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2207 switch (fb->pixel_format) {
2208 case DRM_FORMAT_C8:
17638cd6
JB		 2209 dspcntr |= DISPPLANE_8BPP;
2210 break;
57779d06
VS		 2211 case DRM_FORMAT_RGB565:
2212 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2213 break;
57779d06
VS		 2214 case DRM_FORMAT_XRGB8888:
2215 case DRM_FORMAT_ARGB8888:
2216 dspcntr |= DISPPLANE_BGRX888;
2217 break;
2218 case DRM_FORMAT_XBGR8888:
2219 case DRM_FORMAT_ABGR8888:
2220 dspcntr |= DISPPLANE_RGBX888;
2221 break;
2222 case DRM_FORMAT_XRGB2101010:
2223 case DRM_FORMAT_ARGB2101010:
2224 dspcntr |= DISPPLANE_BGRX101010;
2225 break;
2226 case DRM_FORMAT_XBGR2101010:
2227 case DRM_FORMAT_ABGR2101010:
2228 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2229 break;
2230 default:
baba133a 2231 BUG();
17638cd6
JB		 2232 }
2233
2234 if (obj->tiling_mode != I915_TILING_NONE)
2235 dspcntr |= DISPPLANE_TILED;
2236 else
2237 dspcntr &= ~DISPPLANE_TILED;
2238
2239 /* must disable */
2240 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2241
2242 I915_WRITE(reg, dspcntr);
2243
e506a0c6 2244 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2245 intel_crtc->dspaddr_offset =
bc752862
CW		 2246 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2247 fb->bits_per_pixel / 8,
2248 fb->pitches[0]);
c2c75131 2249 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2250
e506a0c6
DV		 2251 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2252 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2253 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2254 I915_MODIFY_DISPBASE(DSPSURF(plane),
2255 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2256 if (IS_HASWELL(dev)) {
2257 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2258 } else {
2259 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2260 I915_WRITE(DSPLINOFF(plane), linear_offset);
2261 }
17638cd6
JB		 2262 POSTING_READ(reg);
2263
2264 return 0;
2265}
2266
2267/* Assume fb object is pinned & idle & fenced and just update base pointers */
2268static int
2269intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2270 int x, int y, enum mode_set_atomic state)
2271{
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2274
6b8e6ed0
CW		 2275 if (dev_priv->display.disable_fbc)
2276 dev_priv->display.disable_fbc(dev);
3dec0095 2277 intel_increase_pllclock(crtc);
81255565 2278
6b8e6ed0 2279 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2280}
2281
96a02917
VS		 2282void intel_display_handle_reset(struct drm_device *dev)
2283{
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct drm_crtc *crtc;
2286
2287 /*
2288 * Flips in the rings have been nuked by the reset,
2289 * so complete all pending flips so that user space
2290 * will get its events and not get stuck.
2291 *
2292 * Also update the base address of all primary
2293 * planes to the the last fb to make sure we're
2294 * showing the correct fb after a reset.
2295 *
2296 * Need to make two loops over the crtcs so that we
2297 * don't try to grab a crtc mutex before the
2298 * pending_flip_queue really got woken up.
2299 */
2300
2301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303 enum plane plane = intel_crtc->plane;
2304
2305 intel_prepare_page_flip(dev, plane);
2306 intel_finish_page_flip_plane(dev, plane);
2307 }
2308
2309 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311
2312 mutex_lock(&crtc->mutex);
2313 if (intel_crtc->active)
2314 dev_priv->display.update_plane(crtc, crtc->fb,
2315 crtc->x, crtc->y);
2316 mutex_unlock(&crtc->mutex);
2317 }
2318}
2319
14667a4b
CW		 2320static int
2321intel_finish_fb(struct drm_framebuffer *old_fb)
2322{
2323 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2324 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2325 bool was_interruptible = dev_priv->mm.interruptible;
2326 int ret;
2327
14667a4b
CW		 2328 /* Big Hammer, we also need to ensure that any pending
2329 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2330 * current scanout is retired before unpinning the old
2331 * framebuffer.
2332 *
2333 * This should only fail upon a hung GPU, in which case we
2334 * can safely continue.
2335 */
2336 dev_priv->mm.interruptible = false;
2337 ret = i915_gem_object_finish_gpu(obj);
2338 dev_priv->mm.interruptible = was_interruptible;
2339
2340 return ret;
2341}
2342
198598d0
VS		 2343static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2344{
2345 struct drm_device *dev = crtc->dev;
2346 struct drm_i915_master_private *master_priv;
2347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2348
2349 if (!dev->primary->master)
2350 return;
2351
2352 master_priv = dev->primary->master->driver_priv;
2353 if (!master_priv->sarea_priv)
2354 return;
2355
2356 switch (intel_crtc->pipe) {
2357 case 0:
2358 master_priv->sarea_priv->pipeA_x = x;
2359 master_priv->sarea_priv->pipeA_y = y;
2360 break;
2361 case 1:
2362 master_priv->sarea_priv->pipeB_x = x;
2363 master_priv->sarea_priv->pipeB_y = y;
2364 break;
2365 default:
2366 break;
2367 }
2368}
2369
5c3b82e2 2370static int
3c4fdcfb 2371intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2372 struct drm_framebuffer *fb)
79e53945
JB		 2373{
2374 struct drm_device *dev = crtc->dev;
6b8e6ed0 2375 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2377 struct drm_framebuffer *old_fb;
5c3b82e2 2378 int ret;
79e53945
JB		 2379
2380 /* no fb bound */
94352cf9 2381 if (!fb) {
a5071c2f 2382 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2383 return 0;
2384 }
2385
7eb552ae 2386 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2387 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2388 intel_crtc->plane,
7eb552ae 2389 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2390 return -EINVAL;
79e53945
JB		 2391 }
2392
5c3b82e2 2393 mutex_lock(&dev->struct_mutex);
265db958 2394 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2395 to_intel_framebuffer(fb)->obj,
919926ae 2396 NULL);
5c3b82e2
CW		 2397 if (ret != 0) {
2398 mutex_unlock(&dev->struct_mutex);
a5071c2f 2399 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2400 return ret;
2401 }
79e53945 2402
94352cf9 2403 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2404 if (ret) {
94352cf9 2405 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2406 mutex_unlock(&dev->struct_mutex);
a5071c2f 2407 DRM_ERROR("failed to update base address\n");
4e6cfefc 2408 return ret;
79e53945 2409 }
3c4fdcfb 2410
94352cf9
DV		 2411 old_fb = crtc->fb;
2412 crtc->fb = fb;
6c4c86f5
DV		 2413 crtc->x = x;
2414 crtc->y = y;
94352cf9 2415
b7f1de28
CW		 2416 if (old_fb) {
2417 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2418 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2419 }
652c393a 2420
6b8e6ed0 2421 intel_update_fbc(dev);
5c3b82e2 2422 mutex_unlock(&dev->struct_mutex);
79e53945 2423
198598d0 2424 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2425
2426 return 0;
79e53945
JB		 2427}
2428
5e84e1a4
ZW		 2429static void intel_fdi_normal_train(struct drm_crtc *crtc)
2430{
2431 struct drm_device *dev = crtc->dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434 int pipe = intel_crtc->pipe;
2435 u32 reg, temp;
2436
2437 /* enable normal train */
2438 reg = FDI_TX_CTL(pipe);
2439 temp = I915_READ(reg);
61e499bf 2440 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2441 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2442 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2443 } else {
2444 temp &= ~FDI_LINK_TRAIN_NONE;
2445 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2446 }
5e84e1a4
ZW		 2447 I915_WRITE(reg, temp);
2448
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 if (HAS_PCH_CPT(dev)) {
2452 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2453 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2454 } else {
2455 temp &= ~FDI_LINK_TRAIN_NONE;
2456 temp |= FDI_LINK_TRAIN_NONE;
2457 }
2458 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2459
2460 /* wait one idle pattern time */
2461 POSTING_READ(reg);
2462 udelay(1000);
357555c0
JB		 2463
2464 /* IVB wants error correction enabled */
2465 if (IS_IVYBRIDGE(dev))
2466 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2467 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2468}
2469
01a415fd
DV		 2470static void ivb_modeset_global_resources(struct drm_device *dev)
2471{
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 struct intel_crtc *pipe_B_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2475 struct intel_crtc *pipe_C_crtc =
2476 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2477 uint32_t temp;
2478
2479 /* When everything is off disable fdi C so that we could enable fdi B
2480 * with all lanes. XXX: This misses the case where a pipe is not using
2481 * any pch resources and so doesn't need any fdi lanes. */
2482 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2485
2486 temp = I915_READ(SOUTH_CHICKEN1);
2487 temp &= ~FDI_BC_BIFURCATION_SELECT;
2488 DRM_DEBUG_KMS("disabling fdi C rx\n");
2489 I915_WRITE(SOUTH_CHICKEN1, temp);
2490 }
2491}
2492
8db9d77b
ZW		 2493/* The FDI link training functions for ILK/Ibexpeak. */
2494static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2495{
2496 struct drm_device *dev = crtc->dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2499 int pipe = intel_crtc->pipe;
0fc932b8 2500 int plane = intel_crtc->plane;
5eddb70b 2501 u32 reg, temp, tries;
8db9d77b 2502
0fc932b8
JB		 2503 /* FDI needs bits from pipe & plane first */
2504 assert_pipe_enabled(dev_priv, pipe);
2505 assert_plane_enabled(dev_priv, plane);
2506
e1a44743
AJ		 2507 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508 for train result */
5eddb70b
CW		 2509 reg = FDI_RX_IMR(pipe);
2510 temp = I915_READ(reg);
e1a44743
AJ		 2511 temp &= ~FDI_RX_SYMBOL_LOCK;
2512 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2513 I915_WRITE(reg, temp);
2514 I915_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597
AJ		 2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2524 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2525
5eddb70b
CW		 2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
8db9d77b
ZW		 2528 temp &= ~FDI_LINK_TRAIN_NONE;
2529 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2530 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531
2532 POSTING_READ(reg);
8db9d77b
ZW		 2533 udelay(150);
2534
5b2adf89 2535 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2536 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2538 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2539
5eddb70b 2540 reg = FDI_RX_IIR(pipe);
e1a44743 2541 for (tries = 0; tries < 5; tries++) {
5eddb70b 2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2544
2545 if ((temp & FDI_RX_BIT_LOCK)) {
2546 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2547 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2548 break;
2549 }
8db9d77b 2550 }
e1a44743 2551 if (tries == 5)
5eddb70b 2552 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2553
2554 /* Train 2 */
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_NONE;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2559 I915_WRITE(reg, temp);
8db9d77b 2560
5eddb70b
CW		 2561 reg = FDI_RX_CTL(pipe);
2562 temp = I915_READ(reg);
8db9d77b
ZW		 2563 temp &= ~FDI_LINK_TRAIN_NONE;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2565 I915_WRITE(reg, temp);
8db9d77b 2566
5eddb70b
CW		 2567 POSTING_READ(reg);
2568 udelay(150);
8db9d77b 2569
5eddb70b 2570 reg = FDI_RX_IIR(pipe);
e1a44743 2571 for (tries = 0; tries < 5; tries++) {
5eddb70b 2572 temp = I915_READ(reg);
8db9d77b
ZW		 2573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574
2575 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578 break;
2579 }
8db9d77b 2580 }
e1a44743 2581 if (tries == 5)
5eddb70b 2582 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2583
2584 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2585
8db9d77b
ZW		 2586}
2587
0206e353 2588static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2589 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2590 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2591 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2592 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2593};
2594
2595/* The FDI link training functions for SNB/Cougarpoint. */
2596static void gen6_fdi_link_train(struct drm_crtc *crtc)
2597{
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
fa37d39e 2602 u32 reg, temp, i, retry;
8db9d77b 2603
e1a44743
AJ		 2604 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605 for train result */
5eddb70b
CW		 2606 reg = FDI_RX_IMR(pipe);
2607 temp = I915_READ(reg);
e1a44743
AJ		 2608 temp &= ~FDI_RX_SYMBOL_LOCK;
2609 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
e1a44743
AJ		 2613 udelay(150);
2614
8db9d77b 2615 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
77ffb597
AJ		 2618 temp &= ~(7 << 19);
2619 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2620 temp &= ~FDI_LINK_TRAIN_NONE;
2621 temp |= FDI_LINK_TRAIN_PATTERN_1;
2622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2623 /* SNB-B */
2624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2625 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2626
d74cf324
DV		 2627 I915_WRITE(FDI_RX_MISC(pipe),
2628 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2629
5eddb70b
CW		 2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
8db9d77b
ZW		 2632 if (HAS_PCH_CPT(dev)) {
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 } else {
2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_1;
2638 }
5eddb70b
CW		 2639 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2640
2641 POSTING_READ(reg);
8db9d77b
ZW		 2642 udelay(150);
2643
0206e353 2644 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
8db9d77b
ZW		 2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
8db9d77b
ZW		 2652 udelay(500);
2653
fa37d39e
SP		 2654 for (retry = 0; retry < 5; retry++) {
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658 if (temp & FDI_RX_BIT_LOCK) {
2659 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660 DRM_DEBUG_KMS("FDI train 1 done.\n");
2661 break;
2662 }
2663 udelay(50);
8db9d77b 2664 }
fa37d39e
SP		 2665 if (retry < 5)
2666 break;
8db9d77b
ZW		 2667 }
2668 if (i == 4)
5eddb70b 2669 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2670
2671 /* Train 2 */
5eddb70b
CW		 2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
8db9d77b
ZW		 2674 temp &= ~FDI_LINK_TRAIN_NONE;
2675 temp |= FDI_LINK_TRAIN_PATTERN_2;
2676 if (IS_GEN6(dev)) {
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 /* SNB-B */
2679 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2680 }
5eddb70b 2681 I915_WRITE(reg, temp);
8db9d77b 2682
5eddb70b
CW		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
8db9d77b
ZW		 2685 if (HAS_PCH_CPT(dev)) {
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2688 } else {
2689 temp &= ~FDI_LINK_TRAIN_NONE;
2690 temp |= FDI_LINK_TRAIN_PATTERN_2;
2691 }
5eddb70b
CW		 2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
8db9d77b
ZW		 2695 udelay(150);
2696
0206e353 2697 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
8db9d77b
ZW		 2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
8db9d77b
ZW		 2705 udelay(500);
2706
fa37d39e
SP		 2707 for (retry = 0; retry < 5; retry++) {
2708 reg = FDI_RX_IIR(pipe);
2709 temp = I915_READ(reg);
2710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711 if (temp & FDI_RX_SYMBOL_LOCK) {
2712 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713 DRM_DEBUG_KMS("FDI train 2 done.\n");
2714 break;
2715 }
2716 udelay(50);
8db9d77b 2717 }
fa37d39e
SP		 2718 if (retry < 5)
2719 break;
8db9d77b
ZW		 2720 }
2721 if (i == 4)
5eddb70b 2722 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2723
2724 DRM_DEBUG_KMS("FDI train done.\n");
2725}
2726
357555c0
JB		 2727/* Manual link training for Ivy Bridge A0 parts */
2728static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2729{
2730 struct drm_device *dev = crtc->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp, i;
2735
2736 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2737 for train result */
2738 reg = FDI_RX_IMR(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_RX_SYMBOL_LOCK;
2741 temp &= ~FDI_RX_BIT_LOCK;
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(150);
2746
01a415fd
DV		 2747 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2748 I915_READ(FDI_RX_IIR(pipe)));
2749
357555c0
JB		 2750 /* enable CPU FDI TX and PCH FDI RX */
2751 reg = FDI_TX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 temp &= ~(7 << 19);
2754 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2755 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2759 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2760 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2761
d74cf324
DV		 2762 I915_WRITE(FDI_RX_MISC(pipe),
2763 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2764
357555c0
JB		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~FDI_LINK_TRAIN_AUTO;
2768 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2770 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2771 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(150);
2775
0206e353 2776 for (i = 0; i < 4; i++) {
357555c0
JB		 2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2780 temp |= snb_b_fdi_train_param[i];
2781 I915_WRITE(reg, temp);
2782
2783 POSTING_READ(reg);
2784 udelay(500);
2785
2786 reg = FDI_RX_IIR(pipe);
2787 temp = I915_READ(reg);
2788 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789
2790 if (temp & FDI_RX_BIT_LOCK ||
2791 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2792 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2793 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2794 break;
2795 }
2796 }
2797 if (i == 4)
2798 DRM_ERROR("FDI train 1 fail!\n");
2799
2800 /* Train 2 */
2801 reg = FDI_TX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2804 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2805 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2806 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2807 I915_WRITE(reg, temp);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2813 I915_WRITE(reg, temp);
2814
2815 POSTING_READ(reg);
2816 udelay(150);
2817
0206e353 2818 for (i = 0; i < 4; i++) {
357555c0
JB		 2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2822 temp |= snb_b_fdi_train_param[i];
2823 I915_WRITE(reg, temp);
2824
2825 POSTING_READ(reg);
2826 udelay(500);
2827
2828 reg = FDI_RX_IIR(pipe);
2829 temp = I915_READ(reg);
2830 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2831
2832 if (temp & FDI_RX_SYMBOL_LOCK) {
2833 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2834 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2835 break;
2836 }
2837 }
2838 if (i == 4)
2839 DRM_ERROR("FDI train 2 fail!\n");
2840
2841 DRM_DEBUG_KMS("FDI train done.\n");
2842}
2843
88cefb6c 2844static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2845{
88cefb6c 2846 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2847 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2848 int pipe = intel_crtc->pipe;
5eddb70b 2849 u32 reg, temp;
79e53945 2850
c64e311e 2851
c98e9dcf 2852 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2856 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2858 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2859
2860 POSTING_READ(reg);
c98e9dcf
JB		 2861 udelay(200);
2862
2863 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp | FDI_PCDCLK);
2866
2867 POSTING_READ(reg);
c98e9dcf
JB		 2868 udelay(200);
2869
20749730
PZ		 2870 /* Enable CPU FDI TX PLL, always on for Ironlake */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2874 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2875
20749730
PZ		 2876 POSTING_READ(reg);
2877 udelay(100);
6be4a607 2878 }
0e23b99d
JB		 2879}
2880
88cefb6c
DV		 2881static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2882{
2883 struct drm_device *dev = intel_crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 int pipe = intel_crtc->pipe;
2886 u32 reg, temp;
2887
2888 /* Switch from PCDclk to Rawclk */
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2892
2893 /* Disable CPU FDI TX PLL */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2897
2898 POSTING_READ(reg);
2899 udelay(100);
2900
2901 reg = FDI_RX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2904
2905 /* Wait for the clocks to turn off. */
2906 POSTING_READ(reg);
2907 udelay(100);
2908}
2909
0fc932b8
JB		 2910static void ironlake_fdi_disable(struct drm_crtc *crtc)
2911{
2912 struct drm_device *dev = crtc->dev;
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2915 int pipe = intel_crtc->pipe;
2916 u32 reg, temp;
2917
2918 /* disable CPU FDI tx and PCH FDI rx */
2919 reg = FDI_TX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2922 POSTING_READ(reg);
2923
2924 reg = FDI_RX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 temp &= ~(0x7 << 16);
dfd07d72 2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2928 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2929
2930 POSTING_READ(reg);
2931 udelay(100);
2932
2933 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2934 if (HAS_PCH_IBX(dev)) {
2935 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2936 }
0fc932b8
JB		 2937
2938 /* still set train pattern 1 */
2939 reg = FDI_TX_CTL(pipe);
2940 temp = I915_READ(reg);
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943 I915_WRITE(reg, temp);
2944
2945 reg = FDI_RX_CTL(pipe);
2946 temp = I915_READ(reg);
2947 if (HAS_PCH_CPT(dev)) {
2948 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2950 } else {
2951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1;
2953 }
2954 /* BPC in FDI rx is consistent with that in PIPECONF */
2955 temp &= ~(0x07 << 16);
dfd07d72 2956 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2957 I915_WRITE(reg, temp);
2958
2959 POSTING_READ(reg);
2960 udelay(100);
2961}
2962
5bb61643
CW		 2963static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2964{
2965 struct drm_device *dev = crtc->dev;
2966 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2968 unsigned long flags;
2969 bool pending;
2970
10d83730
VS		 2971 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2972 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2973 return false;
2974
2975 spin_lock_irqsave(&dev->event_lock, flags);
2976 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2977 spin_unlock_irqrestore(&dev->event_lock, flags);
2978
2979 return pending;
2980}
2981
e6c3a2a6
CW		 2982static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2983{
0f91128d 2984 struct drm_device *dev = crtc->dev;
5bb61643 2985 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2986
2987 if (crtc->fb == NULL)
2988 return;
2989
2c10d571
DV		 2990 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2991
5bb61643
CW		 2992 wait_event(dev_priv->pending_flip_queue,
2993 !intel_crtc_has_pending_flip(crtc));
2994
0f91128d
CW		 2995 mutex_lock(&dev->struct_mutex);
2996 intel_finish_fb(crtc->fb);
2997 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2998}
2999
e615efe4
ED		 3000/* Program iCLKIP clock to the desired frequency */
3001static void lpt_program_iclkip(struct drm_crtc *crtc)
3002{
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006 u32 temp;
3007
09153000
DV		 3008 mutex_lock(&dev_priv->dpio_lock);
3009
e615efe4
ED		 3010 /* It is necessary to ungate the pixclk gate prior to programming
3011 * the divisors, and gate it back when it is done.
3012 */
3013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3014
3015 /* Disable SSCCTL */
3016 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3017 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3018 SBI_SSCCTL_DISABLE,
3019 SBI_ICLK);
e615efe4
ED		 3020
3021 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022 if (crtc->mode.clock == 20000) {
3023 auxdiv = 1;
3024 divsel = 0x41;
3025 phaseinc = 0x20;
3026 } else {
3027 /* The iCLK virtual clock root frequency is in MHz,
3028 * but the crtc->mode.clock in in KHz. To get the divisors,
3029 * it is necessary to divide one by another, so we
3030 * convert the virtual clock precision to KHz here for higher
3031 * precision.
3032 */
3033 u32 iclk_virtual_root_freq = 172800 * 1000;
3034 u32 iclk_pi_range = 64;
3035 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038 msb_divisor_value = desired_divisor / iclk_pi_range;
3039 pi_value = desired_divisor % iclk_pi_range;
3040
3041 auxdiv = 0;
3042 divsel = msb_divisor_value - 2;
3043 phaseinc = pi_value;
3044 }
3045
3046 /* This should not happen with any sane values */
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053 crtc->mode.clock,
3054 auxdiv,
3055 divsel,
3056 phasedir,
3057 phaseinc);
3058
3059 /* Program SSCDIVINTPHASE6 */
988d6ee8 3060 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3061 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3067 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3068
3069 /* Program SSCAUXDIV */
988d6ee8 3070 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3071 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3073 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3074
3075 /* Enable modulator and associated divider */
988d6ee8 3076 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3077 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3078 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3079
3080 /* Wait for initialization time */
3081 udelay(24);
3082
3083 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3084
3085 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3086}
3087
f67a559d
JB		 3088/*
3089 * Enable PCH resources required for PCH ports:
3090 * - PCH PLLs
3091 * - FDI training & RX/TX
3092 * - update transcoder timings
3093 * - DP transcoding bits
3094 * - transcoder
3095 */
3096static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3097{
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
ee7b9f93 3102 u32 reg, temp;
2c07245f 3103
e7e164db
CW		 3104 assert_transcoder_disabled(dev_priv, pipe);
3105
cd986abb
DV		 3106 /* Write the TU size bits before fdi link training, so that error
3107 * detection works. */
3108 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3109 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3110
c98e9dcf 3111 /* For PCH output, training FDI link */
674cf967 3112 dev_priv->display.fdi_link_train(crtc);
2c07245f 3113
572deb37
DV		 3114 /* XXX: pch pll's can be enabled any time before we enable the PCH
3115 * transcoder, and we actually should do this to not upset any PCH
3116 * transcoder that already use the clock when we share it.
3117 *
3118 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3119 * unconditionally resets the pll - we need that to have the right LVDS
3120 * enable sequence. */
b6b4e185 3121 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3122
303b81e0 3123 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3124 u32 sel;
4b645f14 3125
c98e9dcf 3126 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3127 switch (pipe) {
3128 default:
3129 case 0:
3130 temp |= TRANSA_DPLL_ENABLE;
3131 sel = TRANSA_DPLLB_SEL;
3132 break;
3133 case 1:
3134 temp |= TRANSB_DPLL_ENABLE;
3135 sel = TRANSB_DPLLB_SEL;
3136 break;
3137 case 2:
3138 temp |= TRANSC_DPLL_ENABLE;
3139 sel = TRANSC_DPLLB_SEL;
3140 break;
d64311ab 3141 }
ee7b9f93
JB		 3142 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3143 temp |= sel;
3144 else
3145 temp &= ~sel;
c98e9dcf 3146 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3147 }
5eddb70b 3148
d9b6cb56
JB		 3149 /* set transcoder timing, panel must allow it */
3150 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3151 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3152 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3153 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3154
5eddb70b
CW		 3155 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3156 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3157 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3158 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3159
303b81e0 3160 intel_fdi_normal_train(crtc);
5e84e1a4 3161
c98e9dcf
JB		 3162 /* For PCH DP, enable TRANS_DP_CTL */
3163 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3164 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3165 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3166 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3167 reg = TRANS_DP_CTL(pipe);
3168 temp = I915_READ(reg);
3169 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3170 TRANS_DP_SYNC_MASK |
3171 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3172 temp |= (TRANS_DP_OUTPUT_ENABLE |
3173 TRANS_DP_ENH_FRAMING);
9325c9f0 3174 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3175
3176 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3177 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3178 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3179 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3180
3181 switch (intel_trans_dp_port_sel(crtc)) {
3182 case PCH_DP_B:
5eddb70b 3183 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3184 break;
3185 case PCH_DP_C:
5eddb70b 3186 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3187 break;
3188 case PCH_DP_D:
5eddb70b 3189 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3190 break;
3191 default:
e95d41e1 3192 BUG();
32f9d658 3193 }
2c07245f 3194
5eddb70b 3195 I915_WRITE(reg, temp);
6be4a607 3196 }
b52eb4dc 3197
b8a4f404 3198 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3199}
3200
1507e5bd
PZ		 3201static void lpt_pch_enable(struct drm_crtc *crtc)
3202{
3203 struct drm_device *dev = crtc->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3206 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3207
daed2dbb 3208 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3209
8c52b5e8 3210 lpt_program_iclkip(crtc);
1507e5bd 3211
0540e488 3212 /* Set transcoder timing. */
daed2dbb
PZ		 3213 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3214 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3215 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3216
daed2dbb
PZ		 3217 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3218 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3219 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3220 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3221
937bb610 3222 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3223}
3224
ee7b9f93
JB		 3225static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3226{
3227 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3228
3229 if (pll == NULL)
3230 return;
3231
3232 if (pll->refcount == 0) {
3233 WARN(1, "bad PCH PLL refcount\n");
3234 return;
3235 }
3236
3237 --pll->refcount;
3238 intel_crtc->pch_pll = NULL;
3239}
3240
3241static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3242{
3243 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3244 struct intel_pch_pll *pll;
3245 int i;
3246
3247 pll = intel_crtc->pch_pll;
3248 if (pll) {
3249 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3250 intel_crtc->base.base.id, pll->pll_reg);
3251 goto prepare;
3252 }
3253
98b6bd99
DV		 3254 if (HAS_PCH_IBX(dev_priv->dev)) {
3255 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3256 i = intel_crtc->pipe;
3257 pll = &dev_priv->pch_plls[i];
3258
3259 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3260 intel_crtc->base.base.id, pll->pll_reg);
3261
3262 goto found;
3263 }
3264
ee7b9f93
JB		 3265 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3266 pll = &dev_priv->pch_plls[i];
3267
3268 /* Only want to check enabled timings first */
3269 if (pll->refcount == 0)
3270 continue;
3271
3272 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3273 fp == I915_READ(pll->fp0_reg)) {
3274 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3275 intel_crtc->base.base.id,
3276 pll->pll_reg, pll->refcount, pll->active);
3277
3278 goto found;
3279 }
3280 }
3281
3282 /* Ok no matching timings, maybe there's a free one? */
3283 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3284 pll = &dev_priv->pch_plls[i];
3285 if (pll->refcount == 0) {
3286 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3287 intel_crtc->base.base.id, pll->pll_reg);
3288 goto found;
3289 }
3290 }
3291
3292 return NULL;
3293
3294found:
3295 intel_crtc->pch_pll = pll;
3296 pll->refcount++;
3297 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3298prepare: /* separate function? */
3299 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3300
e04c7350
CW		 3301 /* Wait for the clocks to stabilize before rewriting the regs */
3302 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3303 POSTING_READ(pll->pll_reg);
3304 udelay(150);
e04c7350
CW		 3305
3306 I915_WRITE(pll->fp0_reg, fp);
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3308 pll->on = false;
3309 return pll;
3310}
3311
d4270e57
JB		 3312void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3313{
3314 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3315 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3316 u32 temp;
3317
3318 temp = I915_READ(dslreg);
3319 udelay(500);
3320 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3321 if (wait_for(I915_READ(dslreg) != temp, 5))
3322 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3323 }
3324}
3325
f67a559d
JB		 3326static void ironlake_crtc_enable(struct drm_crtc *crtc)
3327{
3328 struct drm_device *dev = crtc->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3331 struct intel_encoder *encoder;
f67a559d
JB		 3332 int pipe = intel_crtc->pipe;
3333 int plane = intel_crtc->plane;
3334 u32 temp;
f67a559d 3335
08a48469
DV		 3336 WARN_ON(!crtc->enabled);
3337
f67a559d
JB		 3338 if (intel_crtc->active)
3339 return;
3340
3341 intel_crtc->active = true;
3342 intel_update_watermarks(dev);
3343
3344 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3345 temp = I915_READ(PCH_LVDS);
3346 if ((temp & LVDS_PORT_EN) == 0)
3347 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3348 }
3349
f67a559d 3350
5bfe2ac0 3351 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3352 /* Note: FDI PLL enabling _must_ be done before we enable the
3353 * cpu pipes, hence this is separate from all the other fdi/pch
3354 * enabling. */
88cefb6c 3355 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3356 } else {
3357 assert_fdi_tx_disabled(dev_priv, pipe);
3358 assert_fdi_rx_disabled(dev_priv, pipe);
3359 }
f67a559d 3360
bf49ec8c
DV		 3361 for_each_encoder_on_crtc(dev, crtc, encoder)
3362 if (encoder->pre_enable)
3363 encoder->pre_enable(encoder);
f67a559d
JB		 3364
3365 /* Enable panel fitting for LVDS */
3366 if (dev_priv->pch_pf_size &&
547dc041
JN		 3367 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3368 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3369 /* Force use of hard-coded filter coefficients
3370 * as some pre-programmed values are broken,
3371 * e.g. x201.
3372 */
13888d78
PZ		 3373 if (IS_IVYBRIDGE(dev))
3374 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3375 PF_PIPE_SEL_IVB(pipe));
3376 else
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3378 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3379 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3380 }
3381
9c54c0dd
JB		 3382 /*
3383 * On ILK+ LUT must be loaded before the pipe is running but with
3384 * clocks enabled
3385 */
3386 intel_crtc_load_lut(crtc);
3387
5bfe2ac0
DV		 3388 intel_enable_pipe(dev_priv, pipe,
3389 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3390 intel_enable_plane(dev_priv, plane, pipe);
3391
5bfe2ac0 3392 if (intel_crtc->config.has_pch_encoder)
f67a559d 3393 ironlake_pch_enable(crtc);
c98e9dcf 3394
d1ebd816 3395 mutex_lock(&dev->struct_mutex);
bed4a673 3396 intel_update_fbc(dev);
d1ebd816
BW		 3397 mutex_unlock(&dev->struct_mutex);
3398
6b383a7f 3399 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3400
fa5c73b1
DV		 3401 for_each_encoder_on_crtc(dev, crtc, encoder)
3402 encoder->enable(encoder);
61b77ddd
DV		 3403
3404 if (HAS_PCH_CPT(dev))
3405 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3406
3407 /*
3408 * There seems to be a race in PCH platform hw (at least on some
3409 * outputs) where an enabled pipe still completes any pageflip right
3410 * away (as if the pipe is off) instead of waiting for vblank. As soon
3411 * as the first vblank happend, everything works as expected. Hence just
3412 * wait for one vblank before returning to avoid strange things
3413 * happening.
3414 */
3415 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3416}
3417
4f771f10
PZ		 3418static void haswell_crtc_enable(struct drm_crtc *crtc)
3419{
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 struct intel_encoder *encoder;
3424 int pipe = intel_crtc->pipe;
3425 int plane = intel_crtc->plane;
4f771f10
PZ		 3426
3427 WARN_ON(!crtc->enabled);
3428
3429 if (intel_crtc->active)
3430 return;
3431
3432 intel_crtc->active = true;
3433 intel_update_watermarks(dev);
3434
5bfe2ac0 3435 if (intel_crtc->config.has_pch_encoder)
04945641 3436 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3437
3438 for_each_encoder_on_crtc(dev, crtc, encoder)
3439 if (encoder->pre_enable)
3440 encoder->pre_enable(encoder);
3441
1f544388 3442 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3443
1f544388 3444 /* Enable panel fitting for eDP */
547dc041
JN		 3445 if (dev_priv->pch_pf_size &&
3446 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3447 /* Force use of hard-coded filter coefficients
3448 * as some pre-programmed values are broken,
3449 * e.g. x201.
3450 */
54075a7d
PZ		 3451 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3452 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3453 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3454 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3455 }
3456
3457 /*
3458 * On ILK+ LUT must be loaded before the pipe is running but with
3459 * clocks enabled
3460 */
3461 intel_crtc_load_lut(crtc);
3462
1f544388 3463 intel_ddi_set_pipe_settings(crtc);
8228c251 3464 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3465
5bfe2ac0
DV		 3466 intel_enable_pipe(dev_priv, pipe,
3467 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3468 intel_enable_plane(dev_priv, plane, pipe);
3469
5bfe2ac0 3470 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3471 lpt_pch_enable(crtc);
4f771f10
PZ		 3472
3473 mutex_lock(&dev->struct_mutex);
3474 intel_update_fbc(dev);
3475 mutex_unlock(&dev->struct_mutex);
3476
3477 intel_crtc_update_cursor(crtc, true);
3478
3479 for_each_encoder_on_crtc(dev, crtc, encoder)
3480 encoder->enable(encoder);
3481
4f771f10
PZ		 3482 /*
3483 * There seems to be a race in PCH platform hw (at least on some
3484 * outputs) where an enabled pipe still completes any pageflip right
3485 * away (as if the pipe is off) instead of waiting for vblank. As soon
3486 * as the first vblank happend, everything works as expected. Hence just
3487 * wait for one vblank before returning to avoid strange things
3488 * happening.
3489 */
3490 intel_wait_for_vblank(dev, intel_crtc->pipe);
3491}
3492
6be4a607
JB		 3493static void ironlake_crtc_disable(struct drm_crtc *crtc)
3494{
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3498 struct intel_encoder *encoder;
6be4a607
JB		 3499 int pipe = intel_crtc->pipe;
3500 int plane = intel_crtc->plane;
5eddb70b 3501 u32 reg, temp;
b52eb4dc 3502
ef9c3aee 3503
f7abfe8b
CW		 3504 if (!intel_crtc->active)
3505 return;
3506
ea9d758d
DV		 3507 for_each_encoder_on_crtc(dev, crtc, encoder)
3508 encoder->disable(encoder);
3509
e6c3a2a6 3510 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3511 drm_vblank_off(dev, pipe);
6b383a7f 3512 intel_crtc_update_cursor(crtc, false);
5eddb70b 3513
b24e7179 3514 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3515
973d04f9
CW		 3516 if (dev_priv->cfb_plane == plane)
3517 intel_disable_fbc(dev);
2c07245f 3518
b24e7179 3519 intel_disable_pipe(dev_priv, pipe);
32f9d658 3520
6be4a607 3521 /* Disable PF */
9db4a9c7
JB		 3522 I915_WRITE(PF_CTL(pipe), 0);
3523 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3524
bf49ec8c
DV		 3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 if (encoder->post_disable)
3527 encoder->post_disable(encoder);
2c07245f 3528
0fc932b8 3529 ironlake_fdi_disable(crtc);
249c0e64 3530
b8a4f404 3531 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3532
6be4a607
JB		 3533 if (HAS_PCH_CPT(dev)) {
3534 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3535 reg = TRANS_DP_CTL(pipe);
3536 temp = I915_READ(reg);
3537 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3538 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3539 I915_WRITE(reg, temp);
6be4a607
JB		 3540
3541 /* disable DPLL_SEL */
3542 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3543 switch (pipe) {
3544 case 0:
d64311ab 3545 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3546 break;
3547 case 1:
6be4a607 3548 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3549 break;
3550 case 2:
4b645f14 3551 /* C shares PLL A or B */
d64311ab 3552 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3553 break;
3554 default:
3555 BUG(); /* wtf */
3556 }
6be4a607 3557 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3558 }
e3421a18 3559
6be4a607 3560 /* disable PCH DPLL */
ee7b9f93 3561 intel_disable_pch_pll(intel_crtc);
8db9d77b 3562
88cefb6c 3563 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3564
f7abfe8b 3565 intel_crtc->active = false;
6b383a7f 3566 intel_update_watermarks(dev);
d1ebd816
BW		 3567
3568 mutex_lock(&dev->struct_mutex);
6b383a7f 3569 intel_update_fbc(dev);
d1ebd816 3570 mutex_unlock(&dev->struct_mutex);
6be4a607 3571}
1b3c7a47 3572
4f771f10 3573static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3574{
4f771f10
PZ		 3575 struct drm_device *dev = crtc->dev;
3576 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3578 struct intel_encoder *encoder;
3579 int pipe = intel_crtc->pipe;
3580 int plane = intel_crtc->plane;
3b117c8f 3581 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3582
4f771f10
PZ		 3583 if (!intel_crtc->active)
3584 return;
3585
3586 for_each_encoder_on_crtc(dev, crtc, encoder)
3587 encoder->disable(encoder);
3588
3589 intel_crtc_wait_for_pending_flips(crtc);
3590 drm_vblank_off(dev, pipe);
3591 intel_crtc_update_cursor(crtc, false);
3592
3593 intel_disable_plane(dev_priv, plane, pipe);
3594
3595 if (dev_priv->cfb_plane == plane)
3596 intel_disable_fbc(dev);
3597
3598 intel_disable_pipe(dev_priv, pipe);
3599
ad80a810 3600 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3601
f7708f78
PZ		 3602 /* XXX: Once we have proper panel fitter state tracking implemented with
3603 * hardware state read/check support we should switch to only disable
3604 * the panel fitter when we know it's used. */
3605 if (intel_using_power_well(dev)) {
3606 I915_WRITE(PF_CTL(pipe), 0);
3607 I915_WRITE(PF_WIN_SZ(pipe), 0);
3608 }
4f771f10 3609
1f544388 3610 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3611
3612 for_each_encoder_on_crtc(dev, crtc, encoder)
3613 if (encoder->post_disable)
3614 encoder->post_disable(encoder);
3615
88adfff1 3616 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3617 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3618 intel_ddi_fdi_disable(crtc);
83616634 3619 }
4f771f10
PZ		 3620
3621 intel_crtc->active = false;
3622 intel_update_watermarks(dev);
3623
3624 mutex_lock(&dev->struct_mutex);
3625 intel_update_fbc(dev);
3626 mutex_unlock(&dev->struct_mutex);
3627}
3628
ee7b9f93
JB		 3629static void ironlake_crtc_off(struct drm_crtc *crtc)
3630{
3631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632 intel_put_pch_pll(intel_crtc);
3633}
3634
6441ab5f
PZ		 3635static void haswell_crtc_off(struct drm_crtc *crtc)
3636{
a5c961d1
PZ		 3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638
3639 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3640 * start using it. */
3b117c8f 3641 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3642
6441ab5f
PZ		 3643 intel_ddi_put_crtc_pll(crtc);
3644}
3645
02e792fb
DV		 3646static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3647{
02e792fb 3648 if (!enable && intel_crtc->overlay) {
23f09ce3 3649 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3650 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3651
23f09ce3 3652 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3653 dev_priv->mm.interruptible = false;
3654 (void) intel_overlay_switch_off(intel_crtc->overlay);
3655 dev_priv->mm.interruptible = true;
23f09ce3 3656 mutex_unlock(&dev->struct_mutex);
02e792fb 3657 }
02e792fb 3658
5dcdbcb0
CW		 3659 /* Let userspace switch the overlay on again. In most cases userspace
3660 * has to recompute where to put it anyway.
3661 */
02e792fb
DV		 3662}
3663
61bc95c1
EE		 3664/**
3665 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3666 * cursor plane briefly if not already running after enabling the display
3667 * plane.
3668 * This workaround avoids occasional blank screens when self refresh is
3669 * enabled.
3670 */
3671static void
3672g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3673{
3674 u32 cntl = I915_READ(CURCNTR(pipe));
3675
3676 if ((cntl & CURSOR_MODE) == 0) {
3677 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3678
3679 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3680 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3681 intel_wait_for_vblank(dev_priv->dev, pipe);
3682 I915_WRITE(CURCNTR(pipe), cntl);
3683 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3684 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3685 }
3686}
3687
0b8765c6 3688static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3689{
3690 struct drm_device *dev = crtc->dev;
79e53945
JB		 3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3693 struct intel_encoder *encoder;
79e53945 3694 int pipe = intel_crtc->pipe;
80824003 3695 int plane = intel_crtc->plane;
79e53945 3696
08a48469
DV		 3697 WARN_ON(!crtc->enabled);
3698
f7abfe8b
CW		 3699 if (intel_crtc->active)
3700 return;
3701
3702 intel_crtc->active = true;
6b383a7f
CW		 3703 intel_update_watermarks(dev);
3704
63d7bbe9 3705 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3706
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_enable)
3709 encoder->pre_enable(encoder);
3710
040484af 3711 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3712 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3713 if (IS_G4X(dev))
3714 g4x_fixup_plane(dev_priv, pipe);
79e53945 3715
0b8765c6 3716 intel_crtc_load_lut(crtc);
bed4a673 3717 intel_update_fbc(dev);
79e53945 3718
0b8765c6
JB		 3719 /* Give the overlay scaler a chance to enable if it's on this pipe */
3720 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3721 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3722
fa5c73b1
DV		 3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->enable(encoder);
0b8765c6 3725}
79e53945 3726
87476d63
DV		 3727static void i9xx_pfit_disable(struct intel_crtc *crtc)
3728{
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 enum pipe pipe;
3732 uint32_t pctl = I915_READ(PFIT_CONTROL);
3733
3734 assert_pipe_disabled(dev_priv, crtc->pipe);
3735
3736 if (INTEL_INFO(dev)->gen >= 4)
3737 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3738 else
3739 pipe = PIPE_B;
3740
3741 if (pipe == crtc->pipe) {
3742 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3743 I915_WRITE(PFIT_CONTROL, 0);
3744 }
3745}
3746
0b8765c6
JB		 3747static void i9xx_crtc_disable(struct drm_crtc *crtc)
3748{
3749 struct drm_device *dev = crtc->dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3752 struct intel_encoder *encoder;
0b8765c6
JB		 3753 int pipe = intel_crtc->pipe;
3754 int plane = intel_crtc->plane;
ef9c3aee 3755
f7abfe8b
CW		 3756 if (!intel_crtc->active)
3757 return;
3758
ea9d758d
DV		 3759 for_each_encoder_on_crtc(dev, crtc, encoder)
3760 encoder->disable(encoder);
3761
0b8765c6 3762 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3763 intel_crtc_wait_for_pending_flips(crtc);
3764 drm_vblank_off(dev, pipe);
0b8765c6 3765 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3766 intel_crtc_update_cursor(crtc, false);
0b8765c6 3767
973d04f9
CW		 3768 if (dev_priv->cfb_plane == plane)
3769 intel_disable_fbc(dev);
79e53945 3770
b24e7179 3771 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3772 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3773
87476d63 3774 i9xx_pfit_disable(intel_crtc);
24a1f16d 3775
63d7bbe9 3776 intel_disable_pll(dev_priv, pipe);
0b8765c6 3777
f7abfe8b 3778 intel_crtc->active = false;
6b383a7f
CW		 3779 intel_update_fbc(dev);
3780 intel_update_watermarks(dev);
0b8765c6
JB		 3781}
3782
ee7b9f93
JB		 3783static void i9xx_crtc_off(struct drm_crtc *crtc)
3784{
3785}
3786
976f8a20
DV		 3787static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3788 bool enabled)
2c07245f
ZW		 3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_master_private *master_priv;
3792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3793 int pipe = intel_crtc->pipe;
79e53945
JB		 3794
3795 if (!dev->primary->master)
3796 return;
3797
3798 master_priv = dev->primary->master->driver_priv;
3799 if (!master_priv->sarea_priv)
3800 return;
3801
79e53945
JB		 3802 switch (pipe) {
3803 case 0:
3804 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3805 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3806 break;
3807 case 1:
3808 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3809 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3810 break;
3811 default:
9db4a9c7 3812 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3813 break;
3814 }
79e53945
JB		 3815}
3816
976f8a20
DV		 3817/**
3818 * Sets the power management mode of the pipe and plane.
3819 */
3820void intel_crtc_update_dpms(struct drm_crtc *crtc)
3821{
3822 struct drm_device *dev = crtc->dev;
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 struct intel_encoder *intel_encoder;
3825 bool enable = false;
3826
3827 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3828 enable |= intel_encoder->connectors_active;
3829
3830 if (enable)
3831 dev_priv->display.crtc_enable(crtc);
3832 else
3833 dev_priv->display.crtc_disable(crtc);
3834
3835 intel_crtc_update_sarea(crtc, enable);
3836}
3837
cdd59983
CW		 3838static void intel_crtc_disable(struct drm_crtc *crtc)
3839{
cdd59983 3840 struct drm_device *dev = crtc->dev;
976f8a20 3841 struct drm_connector *connector;
ee7b9f93 3842 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3844
976f8a20
DV		 3845 /* crtc should still be enabled when we disable it. */
3846 WARN_ON(!crtc->enabled);
3847
7b9f35a6 3848 intel_crtc->eld_vld = false;
976f8a20
DV		 3849 dev_priv->display.crtc_disable(crtc);
3850 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3851 dev_priv->display.off(crtc);
3852
931872fc
CW		 3853 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3854 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3855
3856 if (crtc->fb) {
3857 mutex_lock(&dev->struct_mutex);
1690e1eb 3858 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3859 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3860 crtc->fb = NULL;
3861 }
3862
3863 /* Update computed state. */
3864 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3865 if (!connector->encoder || !connector->encoder->crtc)
3866 continue;
3867
3868 if (connector->encoder->crtc != crtc)
3869 continue;
3870
3871 connector->dpms = DRM_MODE_DPMS_OFF;
3872 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3873 }
3874}
3875
a261b246 3876void intel_modeset_disable(struct drm_device *dev)
79e53945 3877{
a261b246
DV		 3878 struct drm_crtc *crtc;
3879
3880 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3881 if (crtc->enabled)
3882 intel_crtc_disable(crtc);
3883 }
79e53945
JB		 3884}
3885
ea5b213a 3886void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3887{
4ef69c7a 3888 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3889
ea5b213a
CW		 3890 drm_encoder_cleanup(encoder);
3891 kfree(intel_encoder);
7e7d76c3
JB		 3892}
3893
5ab432ef
DV		 3894/* Simple dpms helper for encodres with just one connector, no cloning and only
3895 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3896 * state of the entire output pipe. */
3897void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3898{
5ab432ef
DV		 3899 if (mode == DRM_MODE_DPMS_ON) {
3900 encoder->connectors_active = true;
3901
b2cabb0e 3902 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3903 } else {
3904 encoder->connectors_active = false;
3905
b2cabb0e 3906 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3907 }
79e53945
JB		 3908}
3909
0a91ca29
DV		 3910/* Cross check the actual hw state with our own modeset state tracking (and it's
3911 * internal consistency). */
b980514c 3912static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3913{
0a91ca29
DV		 3914 if (connector->get_hw_state(connector)) {
3915 struct intel_encoder *encoder = connector->encoder;
3916 struct drm_crtc *crtc;
3917 bool encoder_enabled;
3918 enum pipe pipe;
3919
3920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3921 connector->base.base.id,
3922 drm_get_connector_name(&connector->base));
3923
3924 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3925 "wrong connector dpms state\n");
3926 WARN(connector->base.encoder != &encoder->base,
3927 "active connector not linked to encoder\n");
3928 WARN(!encoder->connectors_active,
3929 "encoder->connectors_active not set\n");
3930
3931 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3932 WARN(!encoder_enabled, "encoder not enabled\n");
3933 if (WARN_ON(!encoder->base.crtc))
3934 return;
3935
3936 crtc = encoder->base.crtc;
3937
3938 WARN(!crtc->enabled, "crtc not enabled\n");
3939 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3940 WARN(pipe != to_intel_crtc(crtc)->pipe,
3941 "encoder active on the wrong pipe\n");
3942 }
79e53945
JB		 3943}
3944
5ab432ef
DV		 3945/* Even simpler default implementation, if there's really no special case to
3946 * consider. */
3947void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3948{
5ab432ef 3949 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3950
5ab432ef
DV		 3951 /* All the simple cases only support two dpms states. */
3952 if (mode != DRM_MODE_DPMS_ON)
3953 mode = DRM_MODE_DPMS_OFF;
d4270e57 3954
5ab432ef
DV		 3955 if (mode == connector->dpms)
3956 return;
3957
3958 connector->dpms = mode;
3959
3960 /* Only need to change hw state when actually enabled */
3961 if (encoder->base.crtc)
3962 intel_encoder_dpms(encoder, mode);
3963 else
8af6cf88 3964 WARN_ON(encoder->connectors_active != false);
0a91ca29 3965
b980514c 3966 intel_modeset_check_state(connector->dev);
79e53945
JB		 3967}
3968
f0947c37
DV		 3969/* Simple connector->get_hw_state implementation for encoders that support only
3970 * one connector and no cloning and hence the encoder state determines the state
3971 * of the connector. */
3972bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3973{
24929352 3974 enum pipe pipe = 0;
f0947c37 3975 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3976
f0947c37 3977 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3978}
3979
b8cecdf5
DV		 3980static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3981 struct intel_crtc_config *pipe_config)
79e53945 3982{
2c07245f 3983 struct drm_device *dev = crtc->dev;
b8cecdf5 3984 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3985
bad720ff 3986 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3987 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3988 if (pipe_config->requested_mode.clock * 3
3989 > IRONLAKE_FDI_FREQ * 4)
2377b741 3990 return false;
2c07245f 3991 }
89749350 3992
f9bef081
DV		 3993 /* All interlaced capable intel hw wants timings in frames. Note though
3994 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3995 * timings, so we need to be careful not to clobber these.*/
7ae89233 3996 if (!pipe_config->timings_set)
f9bef081 3997 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3998
44f46b42
CW		 3999 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4000 * with a hsync front porch of 0.
4001 */
4002 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4003 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4004 return false;
4005
bd080ee5 4006 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4007 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4008 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4009 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4010 * for lvds. */
4011 pipe_config->pipe_bpp = 8*3;
4012 }
4013
79e53945
JB		 4014 return true;
4015}
4016
25eb05fc
JB		 4017static int valleyview_get_display_clock_speed(struct drm_device *dev)
4018{
4019 return 400000; /* FIXME */
4020}
4021
e70236a8
JB		 4022static int i945_get_display_clock_speed(struct drm_device *dev)
4023{
4024 return 400000;
4025}
79e53945 4026
e70236a8 4027static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4028{
e70236a8
JB		 4029 return 333000;
4030}
79e53945 4031
e70236a8
JB		 4032static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4033{
4034 return 200000;
4035}
79e53945 4036
e70236a8
JB		 4037static int i915gm_get_display_clock_speed(struct drm_device *dev)
4038{
4039 u16 gcfgc = 0;
79e53945 4040
e70236a8
JB		 4041 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4042
4043 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4044 return 133000;
4045 else {
4046 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4047 case GC_DISPLAY_CLOCK_333_MHZ:
4048 return 333000;
4049 default:
4050 case GC_DISPLAY_CLOCK_190_200_MHZ:
4051 return 190000;
79e53945 4052 }
e70236a8
JB		 4053 }
4054}
4055
4056static int i865_get_display_clock_speed(struct drm_device *dev)
4057{
4058 return 266000;
4059}
4060
4061static int i855_get_display_clock_speed(struct drm_device *dev)
4062{
4063 u16 hpllcc = 0;
4064 /* Assume that the hardware is in the high speed state. This
4065 * should be the default.
4066 */
4067 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4068 case GC_CLOCK_133_200:
4069 case GC_CLOCK_100_200:
4070 return 200000;
4071 case GC_CLOCK_166_250:
4072 return 250000;
4073 case GC_CLOCK_100_133:
79e53945 4074 return 133000;
e70236a8 4075 }
79e53945 4076
e70236a8
JB		 4077 /* Shouldn't happen */
4078 return 0;
4079}
79e53945 4080
e70236a8
JB		 4081static int i830_get_display_clock_speed(struct drm_device *dev)
4082{
4083 return 133000;
79e53945
JB		 4084}
4085
2c07245f 4086static void
a65851af 4087intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4088{
a65851af
VS		 4089 while (*num > DATA_LINK_M_N_MASK ||
4090 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4091 *num >>= 1;
4092 *den >>= 1;
4093 }
4094}
4095
a65851af
VS		 4096static void compute_m_n(unsigned int m, unsigned int n,
4097 uint32_t *ret_m, uint32_t *ret_n)
4098{
4099 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4100 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4101 intel_reduce_m_n_ratio(ret_m, ret_n);
4102}
4103
e69d0bc1
DV		 4104void
4105intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4106 int pixel_clock, int link_clock,
4107 struct intel_link_m_n *m_n)
2c07245f 4108{
e69d0bc1 4109 m_n->tu = 64;
a65851af
VS		 4110
4111 compute_m_n(bits_per_pixel * pixel_clock,
4112 link_clock * nlanes * 8,
4113 &m_n->gmch_m, &m_n->gmch_n);
4114
4115 compute_m_n(pixel_clock, link_clock,
4116 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4117}
4118
a7615030
CW		 4119static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4120{
72bbe58c
KP		 4121 if (i915_panel_use_ssc >= 0)
4122 return i915_panel_use_ssc != 0;
4123 return dev_priv->lvds_use_ssc
435793df 4124 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4125}
4126
a0c4da24
JB		 4127static int vlv_get_refclk(struct drm_crtc *crtc)
4128{
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 int refclk = 27000; /* for DP & HDMI */
4132
4133 return 100000; /* only one validated so far */
4134
4135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4136 refclk = 96000;
4137 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4138 if (intel_panel_use_ssc(dev_priv))
4139 refclk = 100000;
4140 else
4141 refclk = 96000;
4142 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4143 refclk = 100000;
4144 }
4145
4146 return refclk;
4147}
4148
c65d77d8
JB		 4149static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4150{
4151 struct drm_device *dev = crtc->dev;
4152 struct drm_i915_private *dev_priv = dev->dev_private;
4153 int refclk;
4154
a0c4da24
JB		 4155 if (IS_VALLEYVIEW(dev)) {
4156 refclk = vlv_get_refclk(crtc);
4157 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4158 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4159 refclk = dev_priv->lvds_ssc_freq * 1000;
4160 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4161 refclk / 1000);
4162 } else if (!IS_GEN2(dev)) {
4163 refclk = 96000;
4164 } else {
4165 refclk = 48000;
4166 }
4167
4168 return refclk;
4169}
4170
f47709a9 4171static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4172{
f47709a9
DV		 4173 unsigned dotclock = crtc->config.adjusted_mode.clock;
4174 struct dpll *clock = &crtc->config.dpll;
4175
c65d77d8
JB		 4176 /* SDVO TV has fixed PLL values depend on its clock range,
4177 this mirrors vbios setting. */
f47709a9 4178 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4179 clock->p1 = 2;
4180 clock->p2 = 10;
4181 clock->n = 3;
4182 clock->m1 = 16;
4183 clock->m2 = 8;
f47709a9 4184 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4185 clock->p1 = 1;
4186 clock->p2 = 10;
4187 clock->n = 6;
4188 clock->m1 = 12;
4189 clock->m2 = 8;
4190 }
f47709a9
DV		 4191
4192 crtc->config.clock_set = true;
c65d77d8
JB		 4193}
4194
f47709a9 4195static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4196 intel_clock_t *reduced_clock)
4197{
f47709a9 4198 struct drm_device *dev = crtc->base.dev;
a7516a05 4199 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4200 int pipe = crtc->pipe;
a7516a05 4201 u32 fp, fp2 = 0;
f47709a9 4202 struct dpll *clock = &crtc->config.dpll;
a7516a05
JB		 4203
4204 if (IS_PINEVIEW(dev)) {
4205 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4206 if (reduced_clock)
4207 fp2 = (1 << reduced_clock->n) << 16 |
4208 reduced_clock->m1 << 8 | reduced_clock->m2;
4209 } else {
4210 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4211 if (reduced_clock)
4212 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4213 reduced_clock->m2;
4214 }
4215
4216 I915_WRITE(FP0(pipe), fp);
4217
f47709a9
DV		 4218 crtc->lowfreq_avail = false;
4219 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4220 reduced_clock && i915_powersave) {
4221 I915_WRITE(FP1(pipe), fp2);
f47709a9 4222 crtc->lowfreq_avail = true;
a7516a05
JB		 4223 } else {
4224 I915_WRITE(FP1(pipe), fp);
4225 }
4226}
4227
03afc4a2
DV		 4228static void intel_dp_set_m_n(struct intel_crtc *crtc)
4229{
4230 if (crtc->config.has_pch_encoder)
4231 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4232 else
4233 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4234}
4235
f47709a9 4236static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4237{
f47709a9 4238 struct drm_device *dev = crtc->base.dev;
a0c4da24 4239 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4240 int pipe = crtc->pipe;
a0c4da24
JB		 4241 u32 dpll, mdiv, pdiv;
4242 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4243 bool is_sdvo;
4244 u32 temp;
a0c4da24 4245
09153000
DV		 4246 mutex_lock(&dev_priv->dpio_lock);
4247
f47709a9
DV		 4248 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4249 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4250
2a8f64ca
VP		 4251 dpll = DPLL_VGA_MODE_DIS;
4252 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4253 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4254 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4255
4256 I915_WRITE(DPLL(pipe), dpll);
4257 POSTING_READ(DPLL(pipe));
a0c4da24 4258
f47709a9
DV		 4259 bestn = crtc->config.dpll.n;
4260 bestm1 = crtc->config.dpll.m1;
4261 bestm2 = crtc->config.dpll.m2;
4262 bestp1 = crtc->config.dpll.p1;
4263 bestp2 = crtc->config.dpll.p2;
a0c4da24 4264
2a8f64ca
VP		 4265 /*
4266 * In Valleyview PLL and program lane counter registers are exposed
4267 * through DPIO interface
4268 */
a0c4da24
JB		 4269 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4270 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4271 mdiv |= ((bestn << DPIO_N_SHIFT));
4272 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4273 mdiv |= (1 << DPIO_K_SHIFT);
4274 mdiv |= DPIO_ENABLE_CALIBRATION;
4275 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4276
4277 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4278
2a8f64ca 4279 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4280 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4281 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4282 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4283 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4284
2a8f64ca 4285 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4286
4287 dpll |= DPLL_VCO_ENABLE;
4288 I915_WRITE(DPLL(pipe), dpll);
4289 POSTING_READ(DPLL(pipe));
4290 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4291 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4292
2a8f64ca
VP		 4293 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4294
f47709a9
DV		 4295 if (crtc->config.has_dp_encoder)
4296 intel_dp_set_m_n(crtc);
2a8f64ca
VP		 4297
4298 I915_WRITE(DPLL(pipe), dpll);
4299
4300 /* Wait for the clocks to stabilize. */
4301 POSTING_READ(DPLL(pipe));
4302 udelay(150);
a0c4da24 4303
2a8f64ca
VP		 4304 temp = 0;
4305 if (is_sdvo) {
6cc5f341 4306 temp = 0;
f47709a9
DV		 4307 if (crtc->config.pixel_multiplier > 1) {
4308 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4309 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4310 }
a0c4da24 4311 }
2a8f64ca
VP		 4312 I915_WRITE(DPLL_MD(pipe), temp);
4313 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4314
2a8f64ca 4315 /* Now program lane control registers */
f47709a9
DV		 4316 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4317 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
2a8f64ca
VP		 4318 temp = 0x1000C4;
4319 if(pipe == 1)
4320 temp |= (1 << 21);
4321 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4322 }
f47709a9
DV		 4323
4324 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
2a8f64ca
VP		 4325 temp = 0x1000C4;
4326 if(pipe == 1)
4327 temp |= (1 << 21);
4328 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4329 }
09153000
DV		 4330
4331 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4332}
4333
f47709a9
DV		 4334static void i9xx_update_pll(struct intel_crtc *crtc,
4335 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4336 int num_connectors)
4337{
f47709a9 4338 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4339 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4340 struct intel_encoder *encoder;
f47709a9 4341 int pipe = crtc->pipe;
eb1cbe48
DV		 4342 u32 dpll;
4343 bool is_sdvo;
f47709a9 4344 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4345
f47709a9 4346 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4347
f47709a9
DV		 4348 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4349 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4350
4351 dpll = DPLL_VGA_MODE_DIS;
4352
f47709a9 4353 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4354 dpll |= DPLLB_MODE_LVDS;
4355 else
4356 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4357
eb1cbe48 4358 if (is_sdvo) {
f47709a9 4359 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4360 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4361 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4362 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4363 }
4364 dpll |= DPLL_DVO_HIGH_SPEED;
4365 }
f47709a9 4366 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4367 dpll |= DPLL_DVO_HIGH_SPEED;
4368
4369 /* compute bitmask from p1 value */
4370 if (IS_PINEVIEW(dev))
4371 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4372 else {
4373 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4374 if (IS_G4X(dev) && reduced_clock)
4375 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4376 }
4377 switch (clock->p2) {
4378 case 5:
4379 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4380 break;
4381 case 7:
4382 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4383 break;
4384 case 10:
4385 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4386 break;
4387 case 14:
4388 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4389 break;
4390 }
4391 if (INTEL_INFO(dev)->gen >= 4)
4392 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4393
f47709a9 4394 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4395 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4396 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4397 /* XXX: just matching BIOS for now */
4398 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4399 dpll |= 3;
f47709a9 4400 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4401 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4402 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4403 else
4404 dpll |= PLL_REF_INPUT_DREFCLK;
4405
4406 dpll |= DPLL_VCO_ENABLE;
4407 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4408 POSTING_READ(DPLL(pipe));
4409 udelay(150);
4410
f47709a9 4411 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4412 if (encoder->pre_pll_enable)
4413 encoder->pre_pll_enable(encoder);
eb1cbe48 4414
f47709a9
DV		 4415 if (crtc->config.has_dp_encoder)
4416 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4417
4418 I915_WRITE(DPLL(pipe), dpll);
4419
4420 /* Wait for the clocks to stabilize. */
4421 POSTING_READ(DPLL(pipe));
4422 udelay(150);
4423
4424 if (INTEL_INFO(dev)->gen >= 4) {
4425 u32 temp = 0;
4426 if (is_sdvo) {
6cc5f341 4427 temp = 0;
f47709a9
DV		 4428 if (crtc->config.pixel_multiplier > 1) {
4429 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4430 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4431 }
eb1cbe48
DV		 4432 }
4433 I915_WRITE(DPLL_MD(pipe), temp);
4434 } else {
4435 /* The pixel multiplier can only be updated once the
4436 * DPLL is enabled and the clocks are stable.
4437 *
4438 * So write it again.
4439 */
4440 I915_WRITE(DPLL(pipe), dpll);
4441 }
4442}
4443
f47709a9 4444static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4445 struct drm_display_mode *adjusted_mode,
f47709a9 4446 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4447 int num_connectors)
4448{
f47709a9 4449 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4450 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4451 struct intel_encoder *encoder;
f47709a9 4452 int pipe = crtc->pipe;
eb1cbe48 4453 u32 dpll;
f47709a9 4454 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4455
f47709a9 4456 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4457
eb1cbe48
DV		 4458 dpll = DPLL_VGA_MODE_DIS;
4459
f47709a9 4460 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4461 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4462 } else {
4463 if (clock->p1 == 2)
4464 dpll |= PLL_P1_DIVIDE_BY_TWO;
4465 else
4466 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4467 if (clock->p2 == 4)
4468 dpll |= PLL_P2_DIVIDE_BY_4;
4469 }
4470
f47709a9 4471 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4472 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4473 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4474 else
4475 dpll |= PLL_REF_INPUT_DREFCLK;
4476
4477 dpll |= DPLL_VCO_ENABLE;
4478 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4479 POSTING_READ(DPLL(pipe));
4480 udelay(150);
4481
f47709a9 4482 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4483 if (encoder->pre_pll_enable)
4484 encoder->pre_pll_enable(encoder);
eb1cbe48 4485
5b5896e4
DV		 4486 I915_WRITE(DPLL(pipe), dpll);
4487
4488 /* Wait for the clocks to stabilize. */
4489 POSTING_READ(DPLL(pipe));
4490 udelay(150);
4491
eb1cbe48
DV		 4492 /* The pixel multiplier can only be updated once the
4493 * DPLL is enabled and the clocks are stable.
4494 *
4495 * So write it again.
4496 */
4497 I915_WRITE(DPLL(pipe), dpll);
4498}
4499
b0e77b9c
PZ		 4500static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4501 struct drm_display_mode *mode,
4502 struct drm_display_mode *adjusted_mode)
4503{
4504 struct drm_device *dev = intel_crtc->base.dev;
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4507 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4508 uint32_t vsyncshift;
4509
4510 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4511 /* the chip adds 2 halflines automatically */
4512 adjusted_mode->crtc_vtotal -= 1;
4513 adjusted_mode->crtc_vblank_end -= 1;
4514 vsyncshift = adjusted_mode->crtc_hsync_start
4515 - adjusted_mode->crtc_htotal / 2;
4516 } else {
4517 vsyncshift = 0;
4518 }
4519
4520 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4521 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4522
fe2b8f9d 4523 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4524 (adjusted_mode->crtc_hdisplay - 1) |
4525 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4526 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4527 (adjusted_mode->crtc_hblank_start - 1) |
4528 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4529 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4530 (adjusted_mode->crtc_hsync_start - 1) |
4531 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4532
fe2b8f9d 4533 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4534 (adjusted_mode->crtc_vdisplay - 1) |
4535 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4536 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4537 (adjusted_mode->crtc_vblank_start - 1) |
4538 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4539 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4540 (adjusted_mode->crtc_vsync_start - 1) |
4541 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4542
b5e508d4
PZ		 4543 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4544 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4545 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4546 * bits. */
4547 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4548 (pipe == PIPE_B || pipe == PIPE_C))
4549 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4550
b0e77b9c
PZ		 4551 /* pipesrc controls the size that is scaled from, which should
4552 * always be the user's requested size.
4553 */
4554 I915_WRITE(PIPESRC(pipe),
4555 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4556}
4557
84b046f3
DV		 4558static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4559{
4560 struct drm_device *dev = intel_crtc->base.dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 uint32_t pipeconf;
4563
4564 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4565
4566 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4567 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4568 * core speed.
4569 *
4570 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4571 * pipe == 0 check?
4572 */
4573 if (intel_crtc->config.requested_mode.clock >
4574 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4575 pipeconf |= PIPECONF_DOUBLE_WIDE;
4576 else
4577 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4578 }
4579
4580 /* default to 8bpc */
4581 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4582 if (intel_crtc->config.has_dp_encoder) {
4583 if (intel_crtc->config.dither) {
4584 pipeconf |= PIPECONF_6BPC |
4585 PIPECONF_DITHER_EN |
4586 PIPECONF_DITHER_TYPE_SP;
4587 }
4588 }
4589
4590 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4591 INTEL_OUTPUT_EDP)) {
4592 if (intel_crtc->config.dither) {
4593 pipeconf |= PIPECONF_6BPC |
4594 PIPECONF_ENABLE |
4595 I965_PIPECONF_ACTIVE;
4596 }
4597 }
4598
4599 if (HAS_PIPE_CXSR(dev)) {
4600 if (intel_crtc->lowfreq_avail) {
4601 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4602 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4603 } else {
4604 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4605 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4606 }
4607 }
4608
4609 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4610 if (!IS_GEN2(dev) &&
4611 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4612 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4613 else
4614 pipeconf |= PIPECONF_PROGRESSIVE;
4615
9c8e09b7
VS		 4616 if (IS_VALLEYVIEW(dev)) {
4617 if (intel_crtc->config.limited_color_range)
4618 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4619 else
4620 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4621 }
4622
84b046f3
DV		 4623 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4624 POSTING_READ(PIPECONF(intel_crtc->pipe));
4625}
4626
f564048e 4627static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4628 int x, int y,
94352cf9 4629 struct drm_framebuffer *fb)
79e53945
JB		 4630{
4631 struct drm_device *dev = crtc->dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4634 struct drm_display_mode *adjusted_mode =
4635 &intel_crtc->config.adjusted_mode;
4636 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4637 int pipe = intel_crtc->pipe;
80824003 4638 int plane = intel_crtc->plane;
c751ce4f 4639 int refclk, num_connectors = 0;
652c393a 4640 intel_clock_t clock, reduced_clock;
84b046f3 4641 u32 dspcntr;
eb1cbe48 4642 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4643 bool is_lvds = false, is_tv = false;
5eddb70b 4644 struct intel_encoder *encoder;
d4906093 4645 const intel_limit_t *limit;
5c3b82e2 4646 int ret;
79e53945 4647
6c2b7c12 4648 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4649 switch (encoder->type) {
79e53945
JB		 4650 case INTEL_OUTPUT_LVDS:
4651 is_lvds = true;
4652 break;
4653 case INTEL_OUTPUT_SDVO:
7d57382e 4654 case INTEL_OUTPUT_HDMI:
79e53945 4655 is_sdvo = true;
5eddb70b 4656 if (encoder->needs_tv_clock)
e2f0ba97 4657 is_tv = true;
79e53945 4658 break;
79e53945
JB		 4659 case INTEL_OUTPUT_TVOUT:
4660 is_tv = true;
4661 break;
79e53945 4662 }
43565a06 4663
c751ce4f 4664 num_connectors++;
79e53945
JB		 4665 }
4666
c65d77d8 4667 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4668
d4906093
ML		 4669 /*
4670 * Returns a set of divisors for the desired target clock with the given
4671 * refclk, or FALSE. The returned values represent the clock equation:
4672 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4673 */
1b894b59 4674 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4675 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4676 &clock);
79e53945
JB		 4677 if (!ok) {
4678 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4679 return -EINVAL;
79e53945
JB		 4680 }
4681
cda4b7d3 4682 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4683 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4684
ddc9003c 4685 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4686 /*
4687 * Ensure we match the reduced clock's P to the target clock.
4688 * If the clocks don't match, we can't switch the display clock
4689 * by using the FP0/FP1. In such case we will disable the LVDS
4690 * downclock feature.
4691 */
ddc9003c 4692 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4693 dev_priv->lvds_downclock,
4694 refclk,
cec2f356 4695 &clock,
5eddb70b 4696 &reduced_clock);
7026d4ac 4697 }
f47709a9
DV		 4698 /* Compat-code for transition, will disappear. */
4699 if (!intel_crtc->config.clock_set) {
4700 intel_crtc->config.dpll.n = clock.n;
4701 intel_crtc->config.dpll.m1 = clock.m1;
4702 intel_crtc->config.dpll.m2 = clock.m2;
4703 intel_crtc->config.dpll.p1 = clock.p1;
4704 intel_crtc->config.dpll.p2 = clock.p2;
4705 }
7026d4ac 4706
c65d77d8 4707 if (is_sdvo && is_tv)
f47709a9 4708 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4709
eb1cbe48 4710 if (IS_GEN2(dev))
f47709a9 4711 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4712 has_reduced_clock ? &reduced_clock : NULL,
4713 num_connectors);
a0c4da24 4714 else if (IS_VALLEYVIEW(dev))
f47709a9 4715 vlv_update_pll(intel_crtc);
79e53945 4716 else
f47709a9 4717 i9xx_update_pll(intel_crtc,
eb1cbe48
DV		 4718 has_reduced_clock ? &reduced_clock : NULL,
4719 num_connectors);
79e53945 4720
79e53945
JB		 4721 /* Set up the display plane register */
4722 dspcntr = DISPPLANE_GAMMA_ENABLE;
4723
da6ecc5d
JB		 4724 if (!IS_VALLEYVIEW(dev)) {
4725 if (pipe == 0)
4726 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4727 else
4728 dspcntr |= DISPPLANE_SEL_PIPE_B;
4729 }
79e53945 4730
28c97730 4731 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4732 drm_mode_debug_printmodeline(mode);
4733
b0e77b9c 4734 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4735
4736 /* pipesrc and dspsize control the size that is scaled from,
4737 * which should always be the user's requested size.
79e53945 4738 */
929c77fb
EA		 4739 I915_WRITE(DSPSIZE(plane),
4740 ((mode->vdisplay - 1) << 16) |
4741 (mode->hdisplay - 1));
4742 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4743
84b046f3
DV		 4744 i9xx_set_pipeconf(intel_crtc);
4745
929c77fb 4746 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4747
4748 intel_wait_for_vblank(dev, pipe);
4749
f564048e
EA		 4750 I915_WRITE(DSPCNTR(plane), dspcntr);
4751 POSTING_READ(DSPCNTR(plane));
4752
94352cf9 4753 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4754
4755 intel_update_watermarks(dev);
4756
f564048e
EA		 4757 return ret;
4758}
4759
0e8ffe1b
DV		 4760static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4761 struct intel_crtc_config *pipe_config)
4762{
4763 struct drm_device *dev = crtc->base.dev;
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 uint32_t tmp;
4766
4767 tmp = I915_READ(PIPECONF(crtc->pipe));
4768 if (!(tmp & PIPECONF_ENABLE))
4769 return false;
4770
4771 return true;
4772}
4773
dde86e2d 4774static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4775{
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4778 struct intel_encoder *encoder;
74cfd7ac 4779 u32 val, final;
13d83a67 4780 bool has_lvds = false;
199e5d79
KP		 4781 bool has_cpu_edp = false;
4782 bool has_pch_edp = false;
4783 bool has_panel = false;
99eb6a01
KP		 4784 bool has_ck505 = false;
4785 bool can_ssc = false;
13d83a67
JB		 4786
4787 /* We need to take the global config into account */
199e5d79
KP		 4788 list_for_each_entry(encoder, &mode_config->encoder_list,
4789 base.head) {
4790 switch (encoder->type) {
4791 case INTEL_OUTPUT_LVDS:
4792 has_panel = true;
4793 has_lvds = true;
4794 break;
4795 case INTEL_OUTPUT_EDP:
4796 has_panel = true;
4797 if (intel_encoder_is_pch_edp(&encoder->base))
4798 has_pch_edp = true;
4799 else
4800 has_cpu_edp = true;
4801 break;
13d83a67
JB		 4802 }
4803 }
4804
99eb6a01
KP		 4805 if (HAS_PCH_IBX(dev)) {
4806 has_ck505 = dev_priv->display_clock_mode;
4807 can_ssc = has_ck505;
4808 } else {
4809 has_ck505 = false;
4810 can_ssc = true;
4811 }
4812
4813 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4814 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4815 has_ck505);
13d83a67
JB		 4816
4817 /* Ironlake: try to setup display ref clock before DPLL
4818 * enabling. This is only under driver's control after
4819 * PCH B stepping, previous chipset stepping should be
4820 * ignoring this setting.
4821 */
74cfd7ac
CW		 4822 val = I915_READ(PCH_DREF_CONTROL);
4823
4824 /* As we must carefully and slowly disable/enable each source in turn,
4825 * compute the final state we want first and check if we need to
4826 * make any changes at all.
4827 */
4828 final = val;
4829 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4830 if (has_ck505)
4831 final |= DREF_NONSPREAD_CK505_ENABLE;
4832 else
4833 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4834
4835 final &= ~DREF_SSC_SOURCE_MASK;
4836 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4837 final &= ~DREF_SSC1_ENABLE;
4838
4839 if (has_panel) {
4840 final |= DREF_SSC_SOURCE_ENABLE;
4841
4842 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4843 final |= DREF_SSC1_ENABLE;
4844
4845 if (has_cpu_edp) {
4846 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4847 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4848 else
4849 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4850 } else
4851 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4852 } else {
4853 final |= DREF_SSC_SOURCE_DISABLE;
4854 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4855 }
4856
4857 if (final == val)
4858 return;
4859
13d83a67 4860 /* Always enable nonspread source */
74cfd7ac 4861 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4862
99eb6a01 4863 if (has_ck505)
74cfd7ac 4864 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4865 else
74cfd7ac 4866 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4867
199e5d79 4868 if (has_panel) {
74cfd7ac
CW		 4869 val &= ~DREF_SSC_SOURCE_MASK;
4870 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4871
199e5d79 4872 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4873 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4874 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4875 val |= DREF_SSC1_ENABLE;
e77166b5 4876 } else
74cfd7ac 4877 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4878
4879 /* Get SSC going before enabling the outputs */
74cfd7ac 4880 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4881 POSTING_READ(PCH_DREF_CONTROL);
4882 udelay(200);
4883
74cfd7ac 4884 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4885
4886 /* Enable CPU source on CPU attached eDP */
199e5d79 4887 if (has_cpu_edp) {
99eb6a01 4888 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4889 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4890 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4891 }
13d83a67 4892 else
74cfd7ac 4893 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4894 } else
74cfd7ac 4895 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4896
74cfd7ac 4897 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4898 POSTING_READ(PCH_DREF_CONTROL);
4899 udelay(200);
4900 } else {
4901 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4902
74cfd7ac 4903 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4904
4905 /* Turn off CPU output */
74cfd7ac 4906 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4907
74cfd7ac 4908 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4909 POSTING_READ(PCH_DREF_CONTROL);
4910 udelay(200);
4911
4912 /* Turn off the SSC source */
74cfd7ac
CW		 4913 val &= ~DREF_SSC_SOURCE_MASK;
4914 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4915
4916 /* Turn off SSC1 */
74cfd7ac 4917 val &= ~DREF_SSC1_ENABLE;
199e5d79 4918
74cfd7ac 4919 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4920 POSTING_READ(PCH_DREF_CONTROL);
4921 udelay(200);
4922 }
74cfd7ac
CW		 4923
4924 BUG_ON(val != final);
13d83a67
JB		 4925}
4926
dde86e2d
PZ		 4927/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4928static void lpt_init_pch_refclk(struct drm_device *dev)
4929{
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 struct drm_mode_config *mode_config = &dev->mode_config;
4932 struct intel_encoder *encoder;
4933 bool has_vga = false;
4934 bool is_sdv = false;
4935 u32 tmp;
4936
4937 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4938 switch (encoder->type) {
4939 case INTEL_OUTPUT_ANALOG:
4940 has_vga = true;
4941 break;
4942 }
4943 }
4944
4945 if (!has_vga)
4946 return;
4947
c00db246
DV		 4948 mutex_lock(&dev_priv->dpio_lock);
4949
dde86e2d
PZ		 4950 /* XXX: Rip out SDV support once Haswell ships for real. */
4951 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4952 is_sdv = true;
4953
4954 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4955 tmp &= ~SBI_SSCCTL_DISABLE;
4956 tmp |= SBI_SSCCTL_PATHALT;
4957 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4958
4959 udelay(24);
4960
4961 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4962 tmp &= ~SBI_SSCCTL_PATHALT;
4963 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4964
4965 if (!is_sdv) {
4966 tmp = I915_READ(SOUTH_CHICKEN2);
4967 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4968 I915_WRITE(SOUTH_CHICKEN2, tmp);
4969
4970 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4971 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4972 DRM_ERROR("FDI mPHY reset assert timeout\n");
4973
4974 tmp = I915_READ(SOUTH_CHICKEN2);
4975 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4976 I915_WRITE(SOUTH_CHICKEN2, tmp);
4977
4978 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4979 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4980 100))
4981 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4982 }
4983
4984 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4985 tmp &= ~(0xFF << 24);
4986 tmp |= (0x12 << 24);
4987 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4988
dde86e2d
PZ		 4989 if (is_sdv) {
4990 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4991 tmp |= 0x7FFF;
4992 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4993 }
4994
4995 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4996 tmp |= (1 << 11);
4997 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4998
4999 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5000 tmp |= (1 << 11);
5001 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5002
5003 if (is_sdv) {
5004 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5005 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5006 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5007
5008 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5009 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5010 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5011
5012 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5013 tmp |= (0x3F << 8);
5014 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5015
5016 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5017 tmp |= (0x3F << 8);
5018 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5019 }
5020
5021 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5022 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5023 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5024
5025 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5026 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5027 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5028
5029 if (!is_sdv) {
5030 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5031 tmp &= ~(7 << 13);
5032 tmp |= (5 << 13);
5033 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5034
5035 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5036 tmp &= ~(7 << 13);
5037 tmp |= (5 << 13);
5038 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5039 }
5040
5041 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5042 tmp &= ~0xFF;
5043 tmp |= 0x1C;
5044 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5045
5046 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5047 tmp &= ~0xFF;
5048 tmp |= 0x1C;
5049 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5050
5051 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5052 tmp &= ~(0xFF << 16);
5053 tmp |= (0x1C << 16);
5054 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5055
5056 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5057 tmp &= ~(0xFF << 16);
5058 tmp |= (0x1C << 16);
5059 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5060
5061 if (!is_sdv) {
5062 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5063 tmp |= (1 << 27);
5064 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5065
5066 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5067 tmp |= (1 << 27);
5068 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5069
5070 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5071 tmp &= ~(0xF << 28);
5072 tmp |= (4 << 28);
5073 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5074
5075 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5076 tmp &= ~(0xF << 28);
5077 tmp |= (4 << 28);
5078 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5079 }
5080
5081 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5082 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5083 tmp |= SBI_DBUFF0_ENABLE;
5084 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5085
5086 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5087}
5088
5089/*
5090 * Initialize reference clocks when the driver loads
5091 */
5092void intel_init_pch_refclk(struct drm_device *dev)
5093{
5094 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5095 ironlake_init_pch_refclk(dev);
5096 else if (HAS_PCH_LPT(dev))
5097 lpt_init_pch_refclk(dev);
5098}
5099
d9d444cb
JB		 5100static int ironlake_get_refclk(struct drm_crtc *crtc)
5101{
5102 struct drm_device *dev = crtc->dev;
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5104 struct intel_encoder *encoder;
d9d444cb
JB		 5105 struct intel_encoder *edp_encoder = NULL;
5106 int num_connectors = 0;
5107 bool is_lvds = false;
5108
6c2b7c12 5109 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5110 switch (encoder->type) {
5111 case INTEL_OUTPUT_LVDS:
5112 is_lvds = true;
5113 break;
5114 case INTEL_OUTPUT_EDP:
5115 edp_encoder = encoder;
5116 break;
5117 }
5118 num_connectors++;
5119 }
5120
5121 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5122 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5123 dev_priv->lvds_ssc_freq);
5124 return dev_priv->lvds_ssc_freq * 1000;
5125 }
5126
5127 return 120000;
5128}
5129
c8203565 5130static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5131 struct drm_display_mode *adjusted_mode,
c8203565 5132 bool dither)
79e53945 5133{
c8203565 5134 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5136 int pipe = intel_crtc->pipe;
c8203565
PZ		 5137 uint32_t val;
5138
5139 val = I915_READ(PIPECONF(pipe));
5140
dfd07d72 5141 val &= ~PIPECONF_BPC_MASK;
965e0c48 5142 switch (intel_crtc->config.pipe_bpp) {
c8203565 5143 case 18:
dfd07d72 5144 val |= PIPECONF_6BPC;
c8203565
PZ		 5145 break;
5146 case 24:
dfd07d72 5147 val |= PIPECONF_8BPC;
c8203565
PZ		 5148 break;
5149 case 30:
dfd07d72 5150 val |= PIPECONF_10BPC;
c8203565
PZ		 5151 break;
5152 case 36:
dfd07d72 5153 val |= PIPECONF_12BPC;
c8203565
PZ		 5154 break;
5155 default:
cc769b62
PZ		 5156 /* Case prevented by intel_choose_pipe_bpp_dither. */
5157 BUG();
c8203565
PZ		 5158 }
5159
5160 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5161 if (dither)
5162 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5163
5164 val &= ~PIPECONF_INTERLACE_MASK;
5165 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5166 val |= PIPECONF_INTERLACED_ILK;
5167 else
5168 val |= PIPECONF_PROGRESSIVE;
5169
50f3b016 5170 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5171 val |= PIPECONF_COLOR_RANGE_SELECT;
5172 else
5173 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5174
c8203565
PZ		 5175 I915_WRITE(PIPECONF(pipe), val);
5176 POSTING_READ(PIPECONF(pipe));
5177}
5178
86d3efce
VS		 5179/*
5180 * Set up the pipe CSC unit.
5181 *
5182 * Currently only full range RGB to limited range RGB conversion
5183 * is supported, but eventually this should handle various
5184 * RGB<->YCbCr scenarios as well.
5185 */
50f3b016 5186static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5187{
5188 struct drm_device *dev = crtc->dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191 int pipe = intel_crtc->pipe;
5192 uint16_t coeff = 0x7800; /* 1.0 */
5193
5194 /*
5195 * TODO: Check what kind of values actually come out of the pipe
5196 * with these coeff/postoff values and adjust to get the best
5197 * accuracy. Perhaps we even need to take the bpc value into
5198 * consideration.
5199 */
5200
50f3b016 5201 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5202 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5203
5204 /*
5205 * GY/GU and RY/RU should be the other way around according
5206 * to BSpec, but reality doesn't agree. Just set them up in
5207 * a way that results in the correct picture.
5208 */
5209 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5210 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5211
5212 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5213 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5214
5215 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5216 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5217
5218 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5219 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5220 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5221
5222 if (INTEL_INFO(dev)->gen > 6) {
5223 uint16_t postoff = 0;
5224
50f3b016 5225 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5226 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5227
5228 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5229 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5230 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5231
5232 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5233 } else {
5234 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5235
50f3b016 5236 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5237 mode |= CSC_BLACK_SCREEN_OFFSET;
5238
5239 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5240 }
5241}
5242
ee2b0b38
PZ		 5243static void haswell_set_pipeconf(struct drm_crtc *crtc,
5244 struct drm_display_mode *adjusted_mode,
5245 bool dither)
5246{
5247 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5249 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5250 uint32_t val;
5251
702e7a56 5252 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5253
5254 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5255 if (dither)
5256 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5257
5258 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5259 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5260 val |= PIPECONF_INTERLACED_ILK;
5261 else
5262 val |= PIPECONF_PROGRESSIVE;
5263
702e7a56
PZ		 5264 I915_WRITE(PIPECONF(cpu_transcoder), val);
5265 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5266}
5267
6591c6e4
PZ		 5268static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5269 struct drm_display_mode *adjusted_mode,
5270 intel_clock_t *clock,
5271 bool *has_reduced_clock,
5272 intel_clock_t *reduced_clock)
5273{
5274 struct drm_device *dev = crtc->dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 struct intel_encoder *intel_encoder;
5277 int refclk;
d4906093 5278 const intel_limit_t *limit;
6591c6e4 5279 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5280
6591c6e4
PZ		 5281 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5282 switch (intel_encoder->type) {
79e53945
JB		 5283 case INTEL_OUTPUT_LVDS:
5284 is_lvds = true;
5285 break;
5286 case INTEL_OUTPUT_SDVO:
7d57382e 5287 case INTEL_OUTPUT_HDMI:
79e53945 5288 is_sdvo = true;
6591c6e4 5289 if (intel_encoder->needs_tv_clock)
e2f0ba97 5290 is_tv = true;
79e53945 5291 break;
79e53945
JB		 5292 case INTEL_OUTPUT_TVOUT:
5293 is_tv = true;
5294 break;
79e53945
JB		 5295 }
5296 }
5297
d9d444cb 5298 refclk = ironlake_get_refclk(crtc);
79e53945 5299
d4906093
ML		 5300 /*
5301 * Returns a set of divisors for the desired target clock with the given
5302 * refclk, or FALSE. The returned values represent the clock equation:
5303 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5304 */
1b894b59 5305 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5306 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5307 clock);
5308 if (!ret)
5309 return false;
cda4b7d3 5310
ddc9003c 5311 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5312 /*
5313 * Ensure we match the reduced clock's P to the target clock.
5314 * If the clocks don't match, we can't switch the display clock
5315 * by using the FP0/FP1. In such case we will disable the LVDS
5316 * downclock feature.
5317 */
6591c6e4
PZ		 5318 *has_reduced_clock = limit->find_pll(limit, crtc,
5319 dev_priv->lvds_downclock,
5320 refclk,
5321 clock,
5322 reduced_clock);
652c393a 5323 }
61e9653f
DV		 5324
5325 if (is_sdvo && is_tv)
f47709a9 5326 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5327
5328 return true;
5329}
5330
01a415fd
DV		 5331static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5332{
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 uint32_t temp;
5335
5336 temp = I915_READ(SOUTH_CHICKEN1);
5337 if (temp & FDI_BC_BIFURCATION_SELECT)
5338 return;
5339
5340 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5341 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5342
5343 temp |= FDI_BC_BIFURCATION_SELECT;
5344 DRM_DEBUG_KMS("enabling fdi C rx\n");
5345 I915_WRITE(SOUTH_CHICKEN1, temp);
5346 POSTING_READ(SOUTH_CHICKEN1);
5347}
5348
5349static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5350{
5351 struct drm_device *dev = intel_crtc->base.dev;
5352 struct drm_i915_private *dev_priv = dev->dev_private;
5353 struct intel_crtc *pipe_B_crtc =
5354 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5355
5356 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5357 intel_crtc->pipe, intel_crtc->fdi_lanes);
5358 if (intel_crtc->fdi_lanes > 4) {
5359 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5360 intel_crtc->pipe, intel_crtc->fdi_lanes);
5361 /* Clamp lanes to avoid programming the hw with bogus values. */
5362 intel_crtc->fdi_lanes = 4;
5363
5364 return false;
5365 }
5366
7eb552ae 5367 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5368 return true;
5369
5370 switch (intel_crtc->pipe) {
5371 case PIPE_A:
5372 return true;
5373 case PIPE_B:
5374 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5375 intel_crtc->fdi_lanes > 2) {
5376 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5377 intel_crtc->pipe, intel_crtc->fdi_lanes);
5378 /* Clamp lanes to avoid programming the hw with bogus values. */
5379 intel_crtc->fdi_lanes = 2;
5380
5381 return false;
5382 }
5383
5384 if (intel_crtc->fdi_lanes > 2)
5385 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5386 else
5387 cpt_enable_fdi_bc_bifurcation(dev);
5388
5389 return true;
5390 case PIPE_C:
5391 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5392 if (intel_crtc->fdi_lanes > 2) {
5393 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5394 intel_crtc->pipe, intel_crtc->fdi_lanes);
5395 /* Clamp lanes to avoid programming the hw with bogus values. */
5396 intel_crtc->fdi_lanes = 2;
5397
5398 return false;
5399 }
5400 } else {
5401 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5402 return false;
5403 }
5404
5405 cpt_enable_fdi_bc_bifurcation(dev);
5406
5407 return true;
5408 default:
5409 BUG();
5410 }
5411}
5412
d4b1931c
PZ		 5413int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5414{
5415 /*
5416 * Account for spread spectrum to avoid
5417 * oversubscribing the link. Max center spread
5418 * is 2.5%; use 5% for safety's sake.
5419 */
5420 u32 bps = target_clock * bpp * 21 / 20;
5421 return bps / (link_bw * 8) + 1;
5422}
5423
6cf86a5e
DV		 5424void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5425 struct intel_link_m_n *m_n)
79e53945 5426{
6cf86a5e
DV		 5427 struct drm_device *dev = crtc->base.dev;
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5429 int pipe = crtc->pipe;
5430
5431 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5432 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5433 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5434 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5435}
5436
5437void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5438 struct intel_link_m_n *m_n)
5439{
5440 struct drm_device *dev = crtc->base.dev;
79e53945 5441 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5442 int pipe = crtc->pipe;
3b117c8f 5443 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5444
5445 if (INTEL_INFO(dev)->gen >= 5) {
5446 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5447 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5448 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5449 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5450 } else {
5451 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5452 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5453 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5454 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5455 }
5456}
5457
5458static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5459{
5460 struct drm_device *dev = crtc->dev;
79e53945 5461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5462 struct drm_display_mode *adjusted_mode =
5463 &intel_crtc->config.adjusted_mode;
e69d0bc1 5464 struct intel_link_m_n m_n = {0};
6cc5f341 5465 int target_clock, lane, link_bw;
61e9653f 5466
6cf86a5e
DV		 5467 /* FDI is a binary signal running at ~2.7GHz, encoding
5468 * each output octet as 10 bits. The actual frequency
5469 * is stored as a divider into a 100MHz clock, and the
5470 * mode pixel clock is stored in units of 1KHz.
5471 * Hence the bw of each lane in terms of the mode signal
5472 * is:
5473 */
5474 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5475
df92b1e6
DV		 5476 if (intel_crtc->config.pixel_target_clock)
5477 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5478 else
5479 target_clock = adjusted_mode->clock;
5480
6cf86a5e
DV		 5481 lane = ironlake_get_lanes_required(target_clock, link_bw,
5482 intel_crtc->config.pipe_bpp);
2c07245f 5483
8febb297
EA		 5484 intel_crtc->fdi_lanes = lane;
5485
6cc5f341
DV		 5486 if (intel_crtc->config.pixel_multiplier > 1)
5487 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5488 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5489 link_bw, &m_n);
8febb297 5490
6cf86a5e 5491 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5492}
5493
de13a2e3 5494static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9a7c7890
DV		 5495 intel_clock_t *clock, u32 *fp,
5496 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5497{
de13a2e3 5498 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5499 struct drm_device *dev = crtc->dev;
5500 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5501 struct intel_encoder *intel_encoder;
5502 uint32_t dpll;
6cc5f341 5503 int factor, num_connectors = 0;
de13a2e3 5504 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5505
de13a2e3
PZ		 5506 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5507 switch (intel_encoder->type) {
79e53945
JB		 5508 case INTEL_OUTPUT_LVDS:
5509 is_lvds = true;
5510 break;
5511 case INTEL_OUTPUT_SDVO:
7d57382e 5512 case INTEL_OUTPUT_HDMI:
79e53945 5513 is_sdvo = true;
de13a2e3 5514 if (intel_encoder->needs_tv_clock)
e2f0ba97 5515 is_tv = true;
79e53945 5516 break;
79e53945
JB		 5517 case INTEL_OUTPUT_TVOUT:
5518 is_tv = true;
5519 break;
79e53945 5520 }
43565a06 5521
c751ce4f 5522 num_connectors++;
79e53945 5523 }
79e53945 5524
c1858123 5525 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5526 factor = 21;
5527 if (is_lvds) {
5528 if ((intel_panel_use_ssc(dev_priv) &&
5529 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5530 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5531 factor = 25;
5532 } else if (is_sdvo && is_tv)
5533 factor = 20;
c1858123 5534
de13a2e3 5535 if (clock->m < factor * clock->n)
7d0ac5b7 5536 *fp |= FP_CB_TUNE;
2c07245f 5537
9a7c7890
DV		 5538 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5539 *fp2 |= FP_CB_TUNE;
5540
5eddb70b 5541 dpll = 0;
2c07245f 5542
a07d6787
EA		 5543 if (is_lvds)
5544 dpll |= DPLLB_MODE_LVDS;
5545 else
5546 dpll |= DPLLB_MODE_DAC_SERIAL;
5547 if (is_sdvo) {
6cc5f341
DV		 5548 if (intel_crtc->config.pixel_multiplier > 1) {
5549 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5550 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5551 }
a07d6787
EA		 5552 dpll |= DPLL_DVO_HIGH_SPEED;
5553 }
8b47047b
DV		 5554 if (intel_crtc->config.has_dp_encoder &&
5555 intel_crtc->config.has_pch_encoder)
a07d6787 5556 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5557
a07d6787 5558 /* compute bitmask from p1 value */
de13a2e3 5559 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5560 /* also FPA1 */
de13a2e3 5561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5562
de13a2e3 5563 switch (clock->p2) {
a07d6787
EA		 5564 case 5:
5565 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5566 break;
5567 case 7:
5568 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5569 break;
5570 case 10:
5571 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5572 break;
5573 case 14:
5574 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5575 break;
79e53945
JB		 5576 }
5577
43565a06
KH		 5578 if (is_sdvo && is_tv)
5579 dpll |= PLL_REF_INPUT_TVCLKINBC;
5580 else if (is_tv)
79e53945 5581 /* XXX: just matching BIOS for now */
43565a06 5582 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5583 dpll |= 3;
a7615030 5584 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5585 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5586 else
5587 dpll |= PLL_REF_INPUT_DREFCLK;
5588
de13a2e3
PZ		 5589 return dpll;
5590}
5591
5592static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5593 int x, int y,
5594 struct drm_framebuffer *fb)
5595{
5596 struct drm_device *dev = crtc->dev;
5597 struct drm_i915_private *dev_priv = dev->dev_private;
5598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5599 struct drm_display_mode *adjusted_mode =
5600 &intel_crtc->config.adjusted_mode;
5601 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5602 int pipe = intel_crtc->pipe;
5603 int plane = intel_crtc->plane;
5604 int num_connectors = 0;
5605 intel_clock_t clock, reduced_clock;
5606 u32 dpll, fp = 0, fp2 = 0;
e2f12b07 5607 bool ok, has_reduced_clock = false;
8b47047b 5608 bool is_lvds = false;
de13a2e3 5609 struct intel_encoder *encoder;
de13a2e3 5610 int ret;
01a415fd 5611 bool dither, fdi_config_ok;
de13a2e3
PZ		 5612
5613 for_each_encoder_on_crtc(dev, crtc, encoder) {
5614 switch (encoder->type) {
5615 case INTEL_OUTPUT_LVDS:
5616 is_lvds = true;
5617 break;
de13a2e3
PZ		 5618 }
5619
5620 num_connectors++;
a07d6787 5621 }
79e53945 5622
5dc5298b
PZ		 5623 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5624 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5625
3b117c8f 5626 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5627
de13a2e3
PZ		 5628 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5629 &has_reduced_clock, &reduced_clock);
5630 if (!ok) {
5631 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5632 return -EINVAL;
79e53945 5633 }
f47709a9
DV		 5634 /* Compat-code for transition, will disappear. */
5635 if (!intel_crtc->config.clock_set) {
5636 intel_crtc->config.dpll.n = clock.n;
5637 intel_crtc->config.dpll.m1 = clock.m1;
5638 intel_crtc->config.dpll.m2 = clock.m2;
5639 intel_crtc->config.dpll.p1 = clock.p1;
5640 intel_crtc->config.dpll.p2 = clock.p2;
5641 }
79e53945 5642
de13a2e3
PZ		 5643 /* Ensure that the cursor is valid for the new mode before changing... */
5644 intel_crtc_update_cursor(crtc, true);
5645
5646 /* determine panel color depth */
4e53c2e0 5647 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5648 if (is_lvds && dev_priv->lvds_dither)
5649 dither = true;
5650
5651 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5652 if (has_reduced_clock)
5653 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5654 reduced_clock.m2;
5655
9a7c7890
DV		 5656 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5657 has_reduced_clock ? &fp2 : NULL);
79e53945 5658
f7cb34d4 5659 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5660 drm_mode_debug_printmodeline(mode);
5661
5dc5298b 5662 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5663 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5664 struct intel_pch_pll *pll;
4b645f14 5665
ee7b9f93
JB		 5666 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5667 if (pll == NULL) {
5668 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5669 pipe);
4b645f14
JB		 5670 return -EINVAL;
5671 }
ee7b9f93
JB		 5672 } else
5673 intel_put_pch_pll(intel_crtc);
79e53945 5674
03afc4a2
DV		 5675 if (intel_crtc->config.has_dp_encoder)
5676 intel_dp_set_m_n(intel_crtc);
79e53945 5677
dafd226c
DV		 5678 for_each_encoder_on_crtc(dev, crtc, encoder)
5679 if (encoder->pre_pll_enable)
5680 encoder->pre_pll_enable(encoder);
79e53945 5681
ee7b9f93
JB		 5682 if (intel_crtc->pch_pll) {
5683 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5684
32f9d658 5685 /* Wait for the clocks to stabilize. */
ee7b9f93 5686 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5687 udelay(150);
5688
8febb297
EA		 5689 /* The pixel multiplier can only be updated once the
5690 * DPLL is enabled and the clocks are stable.
5691 *
5692 * So write it again.
5693 */
ee7b9f93 5694 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5695 }
79e53945 5696
5eddb70b 5697 intel_crtc->lowfreq_avail = false;
ee7b9f93 5698 if (intel_crtc->pch_pll) {
4b645f14 5699 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5700 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5701 intel_crtc->lowfreq_avail = true;
4b645f14 5702 } else {
ee7b9f93 5703 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5704 }
5705 }
5706
b0e77b9c 5707 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5708
01a415fd
DV		 5709 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5710 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5711 intel_crtc->fdi_lanes = 0;
5712 if (intel_crtc->config.has_pch_encoder)
5713 ironlake_fdi_set_m_n(crtc);
2c07245f 5714
01a415fd 5715 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5716
c8203565 5717 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5718
9d0498a2 5719 intel_wait_for_vblank(dev, pipe);
79e53945 5720
a1f9e77e
PZ		 5721 /* Set up the display plane register */
5722 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5723 POSTING_READ(DSPCNTR(plane));
79e53945 5724
94352cf9 5725 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5726
5727 intel_update_watermarks(dev);
5728
1f8eeabf
ED		 5729 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5730
01a415fd 5731 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5732}
5733
0e8ffe1b
DV		 5734static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5735 struct intel_crtc_config *pipe_config)
5736{
5737 struct drm_device *dev = crtc->base.dev;
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5739 uint32_t tmp;
5740
5741 tmp = I915_READ(PIPECONF(crtc->pipe));
5742 if (!(tmp & PIPECONF_ENABLE))
5743 return false;
5744
88adfff1
DV		 5745 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5746 pipe_config->has_pch_encoder = true;
5747
0e8ffe1b
DV		 5748 return true;
5749}
5750
d6dd9eb1
DV		 5751static void haswell_modeset_global_resources(struct drm_device *dev)
5752{
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754 bool enable = false;
5755 struct intel_crtc *crtc;
5756 struct intel_encoder *encoder;
5757
5758 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5759 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5760 enable = true;
5761 /* XXX: Should check for edp transcoder here, but thanks to init
5762 * sequence that's not yet available. Just in case desktop eDP
5763 * on PORT D is possible on haswell, too. */
5764 }
5765
5766 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5767 base.head) {
5768 if (encoder->type != INTEL_OUTPUT_EDP &&
5769 encoder->connectors_active)
5770 enable = true;
5771 }
5772
5773 /* Even the eDP panel fitter is outside the always-on well. */
5774 if (dev_priv->pch_pf_size)
5775 enable = true;
5776
5777 intel_set_power_well(dev, enable);
5778}
5779
09b4ddf9 5780static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5781 int x, int y,
5782 struct drm_framebuffer *fb)
5783{
5784 struct drm_device *dev = crtc->dev;
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5787 struct drm_display_mode *adjusted_mode =
5788 &intel_crtc->config.adjusted_mode;
5789 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5790 int pipe = intel_crtc->pipe;
5791 int plane = intel_crtc->plane;
5792 int num_connectors = 0;
8b47047b 5793 bool is_cpu_edp = false;
09b4ddf9 5794 struct intel_encoder *encoder;
09b4ddf9
PZ		 5795 int ret;
5796 bool dither;
5797
5798 for_each_encoder_on_crtc(dev, crtc, encoder) {
5799 switch (encoder->type) {
09b4ddf9 5800 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5801 if (!intel_encoder_is_pch_edp(&encoder->base))
5802 is_cpu_edp = true;
5803 break;
5804 }
5805
5806 num_connectors++;
5807 }
5808
bba2181c 5809 if (is_cpu_edp)
3b117c8f 5810 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5811 else
3b117c8f 5812 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5813
5dc5298b
PZ		 5814 /* We are not sure yet this won't happen. */
5815 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5816 INTEL_PCH_TYPE(dev));
5817
5818 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5819 num_connectors, pipe_name(pipe));
5820
3b117c8f 5821 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5822 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5823
5824 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5825
6441ab5f
PZ		 5826 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5827 return -EINVAL;
5828
09b4ddf9
PZ		 5829 /* Ensure that the cursor is valid for the new mode before changing... */
5830 intel_crtc_update_cursor(crtc, true);
5831
5832 /* determine panel color depth */
4e53c2e0 5833 dither = intel_crtc->config.dither;
09b4ddf9 5834
09b4ddf9
PZ		 5835 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5836 drm_mode_debug_printmodeline(mode);
5837
03afc4a2
DV		 5838 if (intel_crtc->config.has_dp_encoder)
5839 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5840
5841 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5842
5843 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5844
6cf86a5e
DV		 5845 if (intel_crtc->config.has_pch_encoder)
5846 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5847
ee2b0b38 5848 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5849
50f3b016 5850 intel_set_pipe_csc(crtc);
86d3efce 5851
09b4ddf9 5852 /* Set up the display plane register */
86d3efce 5853 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5854 POSTING_READ(DSPCNTR(plane));
5855
5856 ret = intel_pipe_set_base(crtc, x, y, fb);
5857
5858 intel_update_watermarks(dev);
5859
5860 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5861
1f803ee5 5862 return ret;
79e53945
JB		 5863}
5864
0e8ffe1b
DV		 5865static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5866 struct intel_crtc_config *pipe_config)
5867{
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 uint32_t tmp;
5871
3b117c8f 5872 tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
0e8ffe1b
DV		 5873 if (!(tmp & PIPECONF_ENABLE))
5874 return false;
5875
88adfff1
DV		 5876 /*
5877 * aswell has only FDI/PCH transcoder A. It is which is connected to
5878 * DDI E. So just check whether this pipe is wired to DDI E and whether
5879 * the PCH transcoder is on.
5880 */
5881 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5882 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5883 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5884 pipe_config->has_pch_encoder = true;
5885
5886
0e8ffe1b
DV		 5887 return true;
5888}
5889
f564048e 5890static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5891 int x, int y,
94352cf9 5892 struct drm_framebuffer *fb)
f564048e
EA		 5893{
5894 struct drm_device *dev = crtc->dev;
5895 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5896 struct drm_encoder_helper_funcs *encoder_funcs;
5897 struct intel_encoder *encoder;
0b701d27 5898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5899 struct drm_display_mode *adjusted_mode =
5900 &intel_crtc->config.adjusted_mode;
5901 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5902 int pipe = intel_crtc->pipe;
f564048e
EA		 5903 int ret;
5904
0b701d27 5905 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5906
b8cecdf5
DV		 5907 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5908
79e53945 5909 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5910
9256aa19
DV		 5911 if (ret != 0)
5912 return ret;
5913
5914 for_each_encoder_on_crtc(dev, crtc, encoder) {
5915 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5916 encoder->base.base.id,
5917 drm_get_encoder_name(&encoder->base),
5918 mode->base.id, mode->name);
6cc5f341
DV		 5919 if (encoder->mode_set) {
5920 encoder->mode_set(encoder);
5921 } else {
5922 encoder_funcs = encoder->base.helper_private;
5923 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5924 }
9256aa19
DV		 5925 }
5926
5927 return 0;
79e53945
JB		 5928}
5929
3a9627f4
WF		 5930static bool intel_eld_uptodate(struct drm_connector *connector,
5931 int reg_eldv, uint32_t bits_eldv,
5932 int reg_elda, uint32_t bits_elda,
5933 int reg_edid)
5934{
5935 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5936 uint8_t *eld = connector->eld;
5937 uint32_t i;
5938
5939 i = I915_READ(reg_eldv);
5940 i &= bits_eldv;
5941
5942 if (!eld[0])
5943 return !i;
5944
5945 if (!i)
5946 return false;
5947
5948 i = I915_READ(reg_elda);
5949 i &= ~bits_elda;
5950 I915_WRITE(reg_elda, i);
5951
5952 for (i = 0; i < eld[2]; i++)
5953 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5954 return false;
5955
5956 return true;
5957}
5958
e0dac65e
WF		 5959static void g4x_write_eld(struct drm_connector *connector,
5960 struct drm_crtc *crtc)
5961{
5962 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5963 uint8_t *eld = connector->eld;
5964 uint32_t eldv;
5965 uint32_t len;
5966 uint32_t i;
5967
5968 i = I915_READ(G4X_AUD_VID_DID);
5969
5970 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5971 eldv = G4X_ELDV_DEVCL_DEVBLC;
5972 else
5973 eldv = G4X_ELDV_DEVCTG;
5974
3a9627f4
WF		 5975 if (intel_eld_uptodate(connector,
5976 G4X_AUD_CNTL_ST, eldv,
5977 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5978 G4X_HDMIW_HDMIEDID))
5979 return;
5980
e0dac65e
WF		 5981 i = I915_READ(G4X_AUD_CNTL_ST);
5982 i &= ~(eldv | G4X_ELD_ADDR);
5983 len = (i >> 9) & 0x1f; /* ELD buffer size */
5984 I915_WRITE(G4X_AUD_CNTL_ST, i);
5985
5986 if (!eld[0])
5987 return;
5988
5989 len = min_t(uint8_t, eld[2], len);
5990 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5991 for (i = 0; i < len; i++)
5992 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5993
5994 i = I915_READ(G4X_AUD_CNTL_ST);
5995 i |= eldv;
5996 I915_WRITE(G4X_AUD_CNTL_ST, i);
5997}
5998
83358c85
WX		 5999static void haswell_write_eld(struct drm_connector *connector,
6000 struct drm_crtc *crtc)
6001{
6002 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6003 uint8_t *eld = connector->eld;
6004 struct drm_device *dev = crtc->dev;
7b9f35a6 6005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6006 uint32_t eldv;
6007 uint32_t i;
6008 int len;
6009 int pipe = to_intel_crtc(crtc)->pipe;
6010 int tmp;
6011
6012 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6013 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6014 int aud_config = HSW_AUD_CFG(pipe);
6015 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6016
6017
6018 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6019
6020 /* Audio output enable */
6021 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6022 tmp = I915_READ(aud_cntrl_st2);
6023 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6024 I915_WRITE(aud_cntrl_st2, tmp);
6025
6026 /* Wait for 1 vertical blank */
6027 intel_wait_for_vblank(dev, pipe);
6028
6029 /* Set ELD valid state */
6030 tmp = I915_READ(aud_cntrl_st2);
6031 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6032 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6033 I915_WRITE(aud_cntrl_st2, tmp);
6034 tmp = I915_READ(aud_cntrl_st2);
6035 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6036
6037 /* Enable HDMI mode */
6038 tmp = I915_READ(aud_config);
6039 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6040 /* clear N_programing_enable and N_value_index */
6041 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6042 I915_WRITE(aud_config, tmp);
6043
6044 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6045
6046 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6047 intel_crtc->eld_vld = true;
83358c85
WX		 6048
6049 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6050 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6051 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6052 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6053 } else
6054 I915_WRITE(aud_config, 0);
6055
6056 if (intel_eld_uptodate(connector,
6057 aud_cntrl_st2, eldv,
6058 aud_cntl_st, IBX_ELD_ADDRESS,
6059 hdmiw_hdmiedid))
6060 return;
6061
6062 i = I915_READ(aud_cntrl_st2);
6063 i &= ~eldv;
6064 I915_WRITE(aud_cntrl_st2, i);
6065
6066 if (!eld[0])
6067 return;
6068
6069 i = I915_READ(aud_cntl_st);
6070 i &= ~IBX_ELD_ADDRESS;
6071 I915_WRITE(aud_cntl_st, i);
6072 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6073 DRM_DEBUG_DRIVER("port num:%d\n", i);
6074
6075 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6076 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6077 for (i = 0; i < len; i++)
6078 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6079
6080 i = I915_READ(aud_cntrl_st2);
6081 i |= eldv;
6082 I915_WRITE(aud_cntrl_st2, i);
6083
6084}
6085
e0dac65e
WF		 6086static void ironlake_write_eld(struct drm_connector *connector,
6087 struct drm_crtc *crtc)
6088{
6089 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6090 uint8_t *eld = connector->eld;
6091 uint32_t eldv;
6092 uint32_t i;
6093 int len;
6094 int hdmiw_hdmiedid;
b6daa025 6095 int aud_config;
e0dac65e
WF		 6096 int aud_cntl_st;
6097 int aud_cntrl_st2;
9b138a83 6098 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6099
b3f33cbf 6100 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6101 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6102 aud_config = IBX_AUD_CFG(pipe);
6103 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6104 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6105 } else {
9b138a83
WX		 6106 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6107 aud_config = CPT_AUD_CFG(pipe);
6108 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6109 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6110 }
6111
9b138a83 6112 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6113
6114 i = I915_READ(aud_cntl_st);
9b138a83 6115 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6116 if (!i) {
6117 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6118 /* operate blindly on all ports */
1202b4c6
WF		 6119 eldv = IBX_ELD_VALIDB;
6120 eldv |= IBX_ELD_VALIDB << 4;
6121 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6122 } else {
6123 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6124 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6125 }
6126
3a9627f4
WF		 6127 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6128 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6129 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6130 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6131 } else
6132 I915_WRITE(aud_config, 0);
e0dac65e 6133
3a9627f4
WF		 6134 if (intel_eld_uptodate(connector,
6135 aud_cntrl_st2, eldv,
6136 aud_cntl_st, IBX_ELD_ADDRESS,
6137 hdmiw_hdmiedid))
6138 return;
6139
e0dac65e
WF		 6140 i = I915_READ(aud_cntrl_st2);
6141 i &= ~eldv;
6142 I915_WRITE(aud_cntrl_st2, i);
6143
6144 if (!eld[0])
6145 return;
6146
e0dac65e 6147 i = I915_READ(aud_cntl_st);
1202b4c6 6148 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6149 I915_WRITE(aud_cntl_st, i);
6150
6151 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6152 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6153 for (i = 0; i < len; i++)
6154 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6155
6156 i = I915_READ(aud_cntrl_st2);
6157 i |= eldv;
6158 I915_WRITE(aud_cntrl_st2, i);
6159}
6160
6161void intel_write_eld(struct drm_encoder *encoder,
6162 struct drm_display_mode *mode)
6163{
6164 struct drm_crtc *crtc = encoder->crtc;
6165 struct drm_connector *connector;
6166 struct drm_device *dev = encoder->dev;
6167 struct drm_i915_private *dev_priv = dev->dev_private;
6168
6169 connector = drm_select_eld(encoder, mode);
6170 if (!connector)
6171 return;
6172
6173 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6174 connector->base.id,
6175 drm_get_connector_name(connector),
6176 connector->encoder->base.id,
6177 drm_get_encoder_name(connector->encoder));
6178
6179 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6180
6181 if (dev_priv->display.write_eld)
6182 dev_priv->display.write_eld(connector, crtc);
6183}
6184
79e53945
JB		 6185/** Loads the palette/gamma unit for the CRTC with the prepared values */
6186void intel_crtc_load_lut(struct drm_crtc *crtc)
6187{
6188 struct drm_device *dev = crtc->dev;
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6191 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6192 int i;
6193
6194 /* The clocks have to be on to load the palette. */
aed3f09d 6195 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6196 return;
6197
f2b115e6 6198 /* use legacy palette for Ironlake */
bad720ff 6199 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6200 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6201
79e53945
JB		 6202 for (i = 0; i < 256; i++) {
6203 I915_WRITE(palreg + 4 * i,
6204 (intel_crtc->lut_r[i] << 16) |
6205 (intel_crtc->lut_g[i] << 8) |
6206 intel_crtc->lut_b[i]);
6207 }
6208}
6209
560b85bb
CW		 6210static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6211{
6212 struct drm_device *dev = crtc->dev;
6213 struct drm_i915_private *dev_priv = dev->dev_private;
6214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6215 bool visible = base != 0;
6216 u32 cntl;
6217
6218 if (intel_crtc->cursor_visible == visible)
6219 return;
6220
9db4a9c7 6221 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6222 if (visible) {
6223 /* On these chipsets we can only modify the base whilst
6224 * the cursor is disabled.
6225 */
9db4a9c7 6226 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6227
6228 cntl &= ~(CURSOR_FORMAT_MASK);
6229 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6230 cntl |= CURSOR_ENABLE |
6231 CURSOR_GAMMA_ENABLE |
6232 CURSOR_FORMAT_ARGB;
6233 } else
6234 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6235 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6236
6237 intel_crtc->cursor_visible = visible;
6238}
6239
6240static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6241{
6242 struct drm_device *dev = crtc->dev;
6243 struct drm_i915_private *dev_priv = dev->dev_private;
6244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6245 int pipe = intel_crtc->pipe;
6246 bool visible = base != 0;
6247
6248 if (intel_crtc->cursor_visible != visible) {
548f245b 6249 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6250 if (base) {
6251 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6252 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6253 cntl |= pipe << 28; /* Connect to correct pipe */
6254 } else {
6255 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6256 cntl |= CURSOR_MODE_DISABLE;
6257 }
9db4a9c7 6258 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6259
6260 intel_crtc->cursor_visible = visible;
6261 }
6262 /* and commit changes on next vblank */
9db4a9c7 6263 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6264}
6265
65a21cd6
JB		 6266static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6267{
6268 struct drm_device *dev = crtc->dev;
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6271 int pipe = intel_crtc->pipe;
6272 bool visible = base != 0;
6273
6274 if (intel_crtc->cursor_visible != visible) {
6275 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6276 if (base) {
6277 cntl &= ~CURSOR_MODE;
6278 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6279 } else {
6280 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6281 cntl |= CURSOR_MODE_DISABLE;
6282 }
86d3efce
VS		 6283 if (IS_HASWELL(dev))
6284 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6285 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6286
6287 intel_crtc->cursor_visible = visible;
6288 }
6289 /* and commit changes on next vblank */
6290 I915_WRITE(CURBASE_IVB(pipe), base);
6291}
6292
cda4b7d3 6293/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6294static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6295 bool on)
cda4b7d3
CW		 6296{
6297 struct drm_device *dev = crtc->dev;
6298 struct drm_i915_private *dev_priv = dev->dev_private;
6299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6300 int pipe = intel_crtc->pipe;
6301 int x = intel_crtc->cursor_x;
6302 int y = intel_crtc->cursor_y;
560b85bb 6303 u32 base, pos;
cda4b7d3
CW		 6304 bool visible;
6305
6306 pos = 0;
6307
6b383a7f 6308 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6309 base = intel_crtc->cursor_addr;
6310 if (x > (int) crtc->fb->width)
6311 base = 0;
6312
6313 if (y > (int) crtc->fb->height)
6314 base = 0;
6315 } else
6316 base = 0;
6317
6318 if (x < 0) {
6319 if (x + intel_crtc->cursor_width < 0)
6320 base = 0;
6321
6322 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6323 x = -x;
6324 }
6325 pos |= x << CURSOR_X_SHIFT;
6326
6327 if (y < 0) {
6328 if (y + intel_crtc->cursor_height < 0)
6329 base = 0;
6330
6331 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6332 y = -y;
6333 }
6334 pos |= y << CURSOR_Y_SHIFT;
6335
6336 visible = base != 0;
560b85bb 6337 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6338 return;
6339
0cd83aa9 6340 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6341 I915_WRITE(CURPOS_IVB(pipe), pos);
6342 ivb_update_cursor(crtc, base);
6343 } else {
6344 I915_WRITE(CURPOS(pipe), pos);
6345 if (IS_845G(dev) || IS_I865G(dev))
6346 i845_update_cursor(crtc, base);
6347 else
6348 i9xx_update_cursor(crtc, base);
6349 }
cda4b7d3
CW		 6350}
6351
79e53945 6352static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6353 struct drm_file *file,
79e53945
JB		 6354 uint32_t handle,
6355 uint32_t width, uint32_t height)
6356{
6357 struct drm_device *dev = crtc->dev;
6358 struct drm_i915_private *dev_priv = dev->dev_private;
6359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6360 struct drm_i915_gem_object *obj;
cda4b7d3 6361 uint32_t addr;
3f8bc370 6362 int ret;
79e53945 6363
79e53945
JB		 6364 /* if we want to turn off the cursor ignore width and height */
6365 if (!handle) {
28c97730 6366 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6367 addr = 0;
05394f39 6368 obj = NULL;
5004417d 6369 mutex_lock(&dev->struct_mutex);
3f8bc370 6370 goto finish;
79e53945
JB		 6371 }
6372
6373 /* Currently we only support 64x64 cursors */
6374 if (width != 64 || height != 64) {
6375 DRM_ERROR("we currently only support 64x64 cursors\n");
6376 return -EINVAL;
6377 }
6378
05394f39 6379 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6380 if (&obj->base == NULL)
79e53945
JB		 6381 return -ENOENT;
6382
05394f39 6383 if (obj->base.size < width * height * 4) {
79e53945 6384 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6385 ret = -ENOMEM;
6386 goto fail;
79e53945
JB		 6387 }
6388
71acb5eb 6389 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6390 mutex_lock(&dev->struct_mutex);
b295d1b6 6391 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6392 unsigned alignment;
6393
d9e86c0e
CW		 6394 if (obj->tiling_mode) {
6395 DRM_ERROR("cursor cannot be tiled\n");
6396 ret = -EINVAL;
6397 goto fail_locked;
6398 }
6399
693db184
CW		 6400 /* Note that the w/a also requires 2 PTE of padding following
6401 * the bo. We currently fill all unused PTE with the shadow
6402 * page and so we should always have valid PTE following the
6403 * cursor preventing the VT-d warning.
6404 */
6405 alignment = 0;
6406 if (need_vtd_wa(dev))
6407 alignment = 64*1024;
6408
6409 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6410 if (ret) {
6411 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6412 goto fail_locked;
e7b526bb
CW		 6413 }
6414
d9e86c0e
CW		 6415 ret = i915_gem_object_put_fence(obj);
6416 if (ret) {
2da3b9b9 6417 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6418 goto fail_unpin;
6419 }
6420
05394f39 6421 addr = obj->gtt_offset;
71acb5eb 6422 } else {
6eeefaf3 6423 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6424 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6425 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6426 align);
71acb5eb
DA		 6427 if (ret) {
6428 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6429 goto fail_locked;
71acb5eb 6430 }
05394f39 6431 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6432 }
6433
a6c45cf0 6434 if (IS_GEN2(dev))
14b60391
JB		 6435 I915_WRITE(CURSIZE, (height << 12) | width);
6436
3f8bc370 6437 finish:
3f8bc370 6438 if (intel_crtc->cursor_bo) {
b295d1b6 6439 if (dev_priv->info->cursor_needs_physical) {
05394f39 6440 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6441 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6442 } else
6443 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6444 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6445 }
80824003 6446
7f9872e0 6447 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6448
6449 intel_crtc->cursor_addr = addr;
05394f39 6450 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6451 intel_crtc->cursor_width = width;
6452 intel_crtc->cursor_height = height;
6453
6b383a7f 6454 intel_crtc_update_cursor(crtc, true);
3f8bc370 6455
79e53945 6456 return 0;
e7b526bb 6457fail_unpin:
05394f39 6458 i915_gem_object_unpin(obj);
7f9872e0 6459fail_locked:
34b8686e 6460 mutex_unlock(&dev->struct_mutex);
bc9025bd 6461fail:
05394f39 6462 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6463 return ret;
79e53945
JB		 6464}
6465
6466static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6467{
79e53945 6468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6469
cda4b7d3
CW		 6470 intel_crtc->cursor_x = x;
6471 intel_crtc->cursor_y = y;
652c393a 6472
6b383a7f 6473 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6474
6475 return 0;
6476}
6477
6478/** Sets the color ramps on behalf of RandR */
6479void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6480 u16 blue, int regno)
6481{
6482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6483
6484 intel_crtc->lut_r[regno] = red >> 8;
6485 intel_crtc->lut_g[regno] = green >> 8;
6486 intel_crtc->lut_b[regno] = blue >> 8;
6487}
6488
b8c00ac5
DA		 6489void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6490 u16 *blue, int regno)
6491{
6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6493
6494 *red = intel_crtc->lut_r[regno] << 8;
6495 *green = intel_crtc->lut_g[regno] << 8;
6496 *blue = intel_crtc->lut_b[regno] << 8;
6497}
6498
79e53945 6499static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6500 u16 *blue, uint32_t start, uint32_t size)
79e53945 6501{
7203425a 6502 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6504
7203425a 6505 for (i = start; i < end; i++) {
79e53945
JB		 6506 intel_crtc->lut_r[i] = red[i] >> 8;
6507 intel_crtc->lut_g[i] = green[i] >> 8;
6508 intel_crtc->lut_b[i] = blue[i] >> 8;
6509 }
6510
6511 intel_crtc_load_lut(crtc);
6512}
6513
79e53945
JB		 6514/* VESA 640x480x72Hz mode to set on the pipe */
6515static struct drm_display_mode load_detect_mode = {
6516 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6517 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6518};
6519
d2dff872
CW		 6520static struct drm_framebuffer *
6521intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6522 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6523 struct drm_i915_gem_object *obj)
6524{
6525 struct intel_framebuffer *intel_fb;
6526 int ret;
6527
6528 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6529 if (!intel_fb) {
6530 drm_gem_object_unreference_unlocked(&obj->base);
6531 return ERR_PTR(-ENOMEM);
6532 }
6533
6534 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6535 if (ret) {
6536 drm_gem_object_unreference_unlocked(&obj->base);
6537 kfree(intel_fb);
6538 return ERR_PTR(ret);
6539 }
6540
6541 return &intel_fb->base;
6542}
6543
6544static u32
6545intel_framebuffer_pitch_for_width(int width, int bpp)
6546{
6547 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6548 return ALIGN(pitch, 64);
6549}
6550
6551static u32
6552intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6553{
6554 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6555 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6556}
6557
6558static struct drm_framebuffer *
6559intel_framebuffer_create_for_mode(struct drm_device *dev,
6560 struct drm_display_mode *mode,
6561 int depth, int bpp)
6562{
6563 struct drm_i915_gem_object *obj;
0fed39bd 6564 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6565
6566 obj = i915_gem_alloc_object(dev,
6567 intel_framebuffer_size_for_mode(mode, bpp));
6568 if (obj == NULL)
6569 return ERR_PTR(-ENOMEM);
6570
6571 mode_cmd.width = mode->hdisplay;
6572 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6573 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6574 bpp);
5ca0c34a 6575 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6576
6577 return intel_framebuffer_create(dev, &mode_cmd, obj);
6578}
6579
6580static struct drm_framebuffer *
6581mode_fits_in_fbdev(struct drm_device *dev,
6582 struct drm_display_mode *mode)
6583{
6584 struct drm_i915_private *dev_priv = dev->dev_private;
6585 struct drm_i915_gem_object *obj;
6586 struct drm_framebuffer *fb;
6587
6588 if (dev_priv->fbdev == NULL)
6589 return NULL;
6590
6591 obj = dev_priv->fbdev->ifb.obj;
6592 if (obj == NULL)
6593 return NULL;
6594
6595 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6596 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6597 fb->bits_per_pixel))
d2dff872
CW		 6598 return NULL;
6599
01f2c773 6600 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6601 return NULL;
6602
6603 return fb;
6604}
6605
d2434ab7 6606bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6607 struct drm_display_mode *mode,
8261b191 6608 struct intel_load_detect_pipe *old)
79e53945
JB		 6609{
6610 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6611 struct intel_encoder *intel_encoder =
6612 intel_attached_encoder(connector);
79e53945 6613 struct drm_crtc *possible_crtc;
4ef69c7a 6614 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6615 struct drm_crtc *crtc = NULL;
6616 struct drm_device *dev = encoder->dev;
94352cf9 6617 struct drm_framebuffer *fb;
79e53945
JB		 6618 int i = -1;
6619
d2dff872
CW		 6620 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6621 connector->base.id, drm_get_connector_name(connector),
6622 encoder->base.id, drm_get_encoder_name(encoder));
6623
79e53945
JB		 6624 /*
6625 * Algorithm gets a little messy:
7a5e4805 6626 *
79e53945
JB		 6627 * - if the connector already has an assigned crtc, use it (but make
6628 * sure it's on first)
7a5e4805 6629 *
79e53945
JB		 6630 * - try to find the first unused crtc that can drive this connector,
6631 * and use that if we find one
79e53945
JB		 6632 */
6633
6634 /* See if we already have a CRTC for this connector */
6635 if (encoder->crtc) {
6636 crtc = encoder->crtc;
8261b191 6637
7b24056b
DV		 6638 mutex_lock(&crtc->mutex);
6639
24218aac 6640 old->dpms_mode = connector->dpms;
8261b191
CW		 6641 old->load_detect_temp = false;
6642
6643 /* Make sure the crtc and connector are running */
24218aac
DV		 6644 if (connector->dpms != DRM_MODE_DPMS_ON)
6645 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6646
7173188d 6647 return true;
79e53945
JB		 6648 }
6649
6650 /* Find an unused one (if possible) */
6651 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6652 i++;
6653 if (!(encoder->possible_crtcs & (1 << i)))
6654 continue;
6655 if (!possible_crtc->enabled) {
6656 crtc = possible_crtc;
6657 break;
6658 }
79e53945
JB		 6659 }
6660
6661 /*
6662 * If we didn't find an unused CRTC, don't use any.
6663 */
6664 if (!crtc) {
7173188d
CW		 6665 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6666 return false;
79e53945
JB		 6667 }
6668
7b24056b 6669 mutex_lock(&crtc->mutex);
fc303101
DV		 6670 intel_encoder->new_crtc = to_intel_crtc(crtc);
6671 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6672
6673 intel_crtc = to_intel_crtc(crtc);
24218aac 6674 old->dpms_mode = connector->dpms;
8261b191 6675 old->load_detect_temp = true;
d2dff872 6676 old->release_fb = NULL;
79e53945 6677
6492711d
CW		 6678 if (!mode)
6679 mode = &load_detect_mode;
79e53945 6680
d2dff872
CW		 6681 /* We need a framebuffer large enough to accommodate all accesses
6682 * that the plane may generate whilst we perform load detection.
6683 * We can not rely on the fbcon either being present (we get called
6684 * during its initialisation to detect all boot displays, or it may
6685 * not even exist) or that it is large enough to satisfy the
6686 * requested mode.
6687 */
94352cf9
DV		 6688 fb = mode_fits_in_fbdev(dev, mode);
6689 if (fb == NULL) {
d2dff872 6690 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6691 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6692 old->release_fb = fb;
d2dff872
CW		 6693 } else
6694 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6695 if (IS_ERR(fb)) {
d2dff872 6696 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6697 mutex_unlock(&crtc->mutex);
0e8b3d3e 6698 return false;
79e53945 6699 }
79e53945 6700
c0c36b94 6701 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6702 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6703 if (old->release_fb)
6704 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6705 mutex_unlock(&crtc->mutex);
0e8b3d3e 6706 return false;
79e53945 6707 }
7173188d 6708
79e53945 6709 /* let the connector get through one full cycle before testing */
9d0498a2 6710 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6711 return true;
79e53945
JB		 6712}
6713
d2434ab7 6714void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6715 struct intel_load_detect_pipe *old)
79e53945 6716{
d2434ab7
DV		 6717 struct intel_encoder *intel_encoder =
6718 intel_attached_encoder(connector);
4ef69c7a 6719 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6720 struct drm_crtc *crtc = encoder->crtc;
79e53945 6721
d2dff872
CW		 6722 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6723 connector->base.id, drm_get_connector_name(connector),
6724 encoder->base.id, drm_get_encoder_name(encoder));
6725
8261b191 6726 if (old->load_detect_temp) {
fc303101
DV		 6727 to_intel_connector(connector)->new_encoder = NULL;
6728 intel_encoder->new_crtc = NULL;
6729 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6730
36206361
DV		 6731 if (old->release_fb) {
6732 drm_framebuffer_unregister_private(old->release_fb);
6733 drm_framebuffer_unreference(old->release_fb);
6734 }
d2dff872 6735
67c96400 6736 mutex_unlock(&crtc->mutex);
0622a53c 6737 return;
79e53945
JB		 6738 }
6739
c751ce4f 6740 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6741 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6742 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6743
6744 mutex_unlock(&crtc->mutex);
79e53945
JB		 6745}
6746
6747/* Returns the clock of the currently programmed mode of the given pipe. */
6748static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6749{
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6752 int pipe = intel_crtc->pipe;
548f245b 6753 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6754 u32 fp;
6755 intel_clock_t clock;
6756
6757 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6758 fp = I915_READ(FP0(pipe));
79e53945 6759 else
39adb7a5 6760 fp = I915_READ(FP1(pipe));
79e53945
JB		 6761
6762 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6763 if (IS_PINEVIEW(dev)) {
6764 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6765 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6766 } else {
6767 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6768 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6769 }
6770
a6c45cf0 6771 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6772 if (IS_PINEVIEW(dev))
6773 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6774 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6775 else
6776 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6777 DPLL_FPA01_P1_POST_DIV_SHIFT);
6778
6779 switch (dpll & DPLL_MODE_MASK) {
6780 case DPLLB_MODE_DAC_SERIAL:
6781 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6782 5 : 10;
6783 break;
6784 case DPLLB_MODE_LVDS:
6785 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6786 7 : 14;
6787 break;
6788 default:
28c97730 6789 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6790 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6791 return 0;
6792 }
6793
6794 /* XXX: Handle the 100Mhz refclk */
2177832f 6795 intel_clock(dev, 96000, &clock);
79e53945
JB		 6796 } else {
6797 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6798
6799 if (is_lvds) {
6800 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6801 DPLL_FPA01_P1_POST_DIV_SHIFT);
6802 clock.p2 = 14;
6803
6804 if ((dpll & PLL_REF_INPUT_MASK) ==
6805 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6806 /* XXX: might not be 66MHz */
2177832f 6807 intel_clock(dev, 66000, &clock);
79e53945 6808 } else
2177832f 6809 intel_clock(dev, 48000, &clock);
79e53945
JB		 6810 } else {
6811 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6812 clock.p1 = 2;
6813 else {
6814 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6815 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6816 }
6817 if (dpll & PLL_P2_DIVIDE_BY_4)
6818 clock.p2 = 4;
6819 else
6820 clock.p2 = 2;
6821
2177832f 6822 intel_clock(dev, 48000, &clock);
79e53945
JB		 6823 }
6824 }
6825
6826 /* XXX: It would be nice to validate the clocks, but we can't reuse
6827 * i830PllIsValid() because it relies on the xf86_config connector
6828 * configuration being accurate, which it isn't necessarily.
6829 */
6830
6831 return clock.dot;
6832}
6833
6834/** Returns the currently programmed mode of the given pipe. */
6835struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6836 struct drm_crtc *crtc)
6837{
548f245b 6838 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6840 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6841 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6842 int htot = I915_READ(HTOTAL(cpu_transcoder));
6843 int hsync = I915_READ(HSYNC(cpu_transcoder));
6844 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6845 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6846
6847 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6848 if (!mode)
6849 return NULL;
6850
6851 mode->clock = intel_crtc_clock_get(dev, crtc);
6852 mode->hdisplay = (htot & 0xffff) + 1;
6853 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6854 mode->hsync_start = (hsync & 0xffff) + 1;
6855 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6856 mode->vdisplay = (vtot & 0xffff) + 1;
6857 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6858 mode->vsync_start = (vsync & 0xffff) + 1;
6859 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6860
6861 drm_mode_set_name(mode);
79e53945
JB		 6862
6863 return mode;
6864}
6865
3dec0095 6866static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6867{
6868 struct drm_device *dev = crtc->dev;
6869 drm_i915_private_t *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6872 int dpll_reg = DPLL(pipe);
6873 int dpll;
652c393a 6874
bad720ff 6875 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6876 return;
6877
6878 if (!dev_priv->lvds_downclock_avail)
6879 return;
6880
dbdc6479 6881 dpll = I915_READ(dpll_reg);
652c393a 6882 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6883 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6884
8ac5a6d5 6885 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6886
6887 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6888 I915_WRITE(dpll_reg, dpll);
9d0498a2 6889 intel_wait_for_vblank(dev, pipe);
dbdc6479 6890
652c393a
JB		 6891 dpll = I915_READ(dpll_reg);
6892 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6893 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6894 }
652c393a
JB		 6895}
6896
6897static void intel_decrease_pllclock(struct drm_crtc *crtc)
6898{
6899 struct drm_device *dev = crtc->dev;
6900 drm_i915_private_t *dev_priv = dev->dev_private;
6901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6902
bad720ff 6903 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6904 return;
6905
6906 if (!dev_priv->lvds_downclock_avail)
6907 return;
6908
6909 /*
6910 * Since this is called by a timer, we should never get here in
6911 * the manual case.
6912 */
6913 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6914 int pipe = intel_crtc->pipe;
6915 int dpll_reg = DPLL(pipe);
6916 int dpll;
f6e5b160 6917
44d98a61 6918 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6919
8ac5a6d5 6920 assert_panel_unlocked(dev_priv, pipe);
652c393a 6921
dc257cf1 6922 dpll = I915_READ(dpll_reg);
652c393a
JB		 6923 dpll |= DISPLAY_RATE_SELECT_FPA1;
6924 I915_WRITE(dpll_reg, dpll);
9d0498a2 6925 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6926 dpll = I915_READ(dpll_reg);
6927 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6928 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6929 }
6930
6931}
6932
f047e395
CW		 6933void intel_mark_busy(struct drm_device *dev)
6934{
f047e395
CW		 6935 i915_update_gfx_val(dev->dev_private);
6936}
6937
6938void intel_mark_idle(struct drm_device *dev)
652c393a 6939{
652c393a 6940 struct drm_crtc *crtc;
652c393a
JB		 6941
6942 if (!i915_powersave)
6943 return;
6944
652c393a 6945 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6946 if (!crtc->fb)
6947 continue;
6948
725a5b54 6949 intel_decrease_pllclock(crtc);
652c393a 6950 }
652c393a
JB		 6951}
6952
725a5b54 6953void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6954{
f047e395
CW		 6955 struct drm_device *dev = obj->base.dev;
6956 struct drm_crtc *crtc;
652c393a 6957
f047e395 6958 if (!i915_powersave)
acb87dfb
CW		 6959 return;
6960
652c393a
JB		 6961 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6962 if (!crtc->fb)
6963 continue;
6964
f047e395 6965 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6966 intel_increase_pllclock(crtc);
652c393a
JB		 6967 }
6968}
6969
79e53945
JB		 6970static void intel_crtc_destroy(struct drm_crtc *crtc)
6971{
6972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6973 struct drm_device *dev = crtc->dev;
6974 struct intel_unpin_work *work;
6975 unsigned long flags;
6976
6977 spin_lock_irqsave(&dev->event_lock, flags);
6978 work = intel_crtc->unpin_work;
6979 intel_crtc->unpin_work = NULL;
6980 spin_unlock_irqrestore(&dev->event_lock, flags);
6981
6982 if (work) {
6983 cancel_work_sync(&work->work);
6984 kfree(work);
6985 }
79e53945
JB		 6986
6987 drm_crtc_cleanup(crtc);
67e77c5a 6988
79e53945
JB		 6989 kfree(intel_crtc);
6990}
6991
6b95a207
KH		 6992static void intel_unpin_work_fn(struct work_struct *__work)
6993{
6994 struct intel_unpin_work *work =
6995 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6996 struct drm_device *dev = work->crtc->dev;
6b95a207 6997
b4a98e57 6998 mutex_lock(&dev->struct_mutex);
1690e1eb 6999 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7000 drm_gem_object_unreference(&work->pending_flip_obj->base);
7001 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7002
b4a98e57
CW		 7003 intel_update_fbc(dev);
7004 mutex_unlock(&dev->struct_mutex);
7005
7006 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7007 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7008
6b95a207
KH		 7009 kfree(work);
7010}
7011
1afe3e9d 7012static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7013 struct drm_crtc *crtc)
6b95a207
KH		 7014{
7015 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017 struct intel_unpin_work *work;
6b95a207
KH		 7018 unsigned long flags;
7019
7020 /* Ignore early vblank irqs */
7021 if (intel_crtc == NULL)
7022 return;
7023
7024 spin_lock_irqsave(&dev->event_lock, flags);
7025 work = intel_crtc->unpin_work;
e7d841ca
CW		 7026
7027 /* Ensure we don't miss a work->pending update ... */
7028 smp_rmb();
7029
7030 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7031 spin_unlock_irqrestore(&dev->event_lock, flags);
7032 return;
7033 }
7034
e7d841ca
CW		 7035 /* and that the unpin work is consistent wrt ->pending. */
7036 smp_rmb();
7037
6b95a207 7038 intel_crtc->unpin_work = NULL;
6b95a207 7039
45a066eb
RC		 7040 if (work->event)
7041 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7042
0af7e4df
MK		 7043 drm_vblank_put(dev, intel_crtc->pipe);
7044
6b95a207
KH		 7045 spin_unlock_irqrestore(&dev->event_lock, flags);
7046
2c10d571 7047 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7048
7049 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7050
7051 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7052}
7053
1afe3e9d
JB		 7054void intel_finish_page_flip(struct drm_device *dev, int pipe)
7055{
7056 drm_i915_private_t *dev_priv = dev->dev_private;
7057 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7058
49b14a5c 7059 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7060}
7061
7062void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7063{
7064 drm_i915_private_t *dev_priv = dev->dev_private;
7065 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7066
49b14a5c 7067 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7068}
7069
6b95a207
KH		 7070void intel_prepare_page_flip(struct drm_device *dev, int plane)
7071{
7072 drm_i915_private_t *dev_priv = dev->dev_private;
7073 struct intel_crtc *intel_crtc =
7074 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7075 unsigned long flags;
7076
e7d841ca
CW		 7077 /* NB: An MMIO update of the plane base pointer will also
7078 * generate a page-flip completion irq, i.e. every modeset
7079 * is also accompanied by a spurious intel_prepare_page_flip().
7080 */
6b95a207 7081 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7082 if (intel_crtc->unpin_work)
7083 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7084 spin_unlock_irqrestore(&dev->event_lock, flags);
7085}
7086
e7d841ca
CW		 7087inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7088{
7089 /* Ensure that the work item is consistent when activating it ... */
7090 smp_wmb();
7091 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7092 /* and that it is marked active as soon as the irq could fire. */
7093 smp_wmb();
7094}
7095
8c9f3aaf
JB		 7096static int intel_gen2_queue_flip(struct drm_device *dev,
7097 struct drm_crtc *crtc,
7098 struct drm_framebuffer *fb,
7099 struct drm_i915_gem_object *obj)
7100{
7101 struct drm_i915_private *dev_priv = dev->dev_private;
7102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7103 u32 flip_mask;
6d90c952 7104 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7105 int ret;
7106
6d90c952 7107 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7108 if (ret)
83d4092b 7109 goto err;
8c9f3aaf 7110
6d90c952 7111 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7112 if (ret)
83d4092b 7113 goto err_unpin;
8c9f3aaf
JB		 7114
7115 /* Can't queue multiple flips, so wait for the previous
7116 * one to finish before executing the next.
7117 */
7118 if (intel_crtc->plane)
7119 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7120 else
7121 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7122 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7123 intel_ring_emit(ring, MI_NOOP);
7124 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7125 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7126 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7127 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7128 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7129
7130 intel_mark_page_flip_active(intel_crtc);
6d90c952 7131 intel_ring_advance(ring);
83d4092b
CW		 7132 return 0;
7133
7134err_unpin:
7135 intel_unpin_fb_obj(obj);
7136err:
8c9f3aaf
JB		 7137 return ret;
7138}
7139
7140static int intel_gen3_queue_flip(struct drm_device *dev,
7141 struct drm_crtc *crtc,
7142 struct drm_framebuffer *fb,
7143 struct drm_i915_gem_object *obj)
7144{
7145 struct drm_i915_private *dev_priv = dev->dev_private;
7146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7147 u32 flip_mask;
6d90c952 7148 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7149 int ret;
7150
6d90c952 7151 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7152 if (ret)
83d4092b 7153 goto err;
8c9f3aaf 7154
6d90c952 7155 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7156 if (ret)
83d4092b 7157 goto err_unpin;
8c9f3aaf
JB		 7158
7159 if (intel_crtc->plane)
7160 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7161 else
7162 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7163 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7164 intel_ring_emit(ring, MI_NOOP);
7165 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7166 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7167 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7168 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7169 intel_ring_emit(ring, MI_NOOP);
7170
e7d841ca 7171 intel_mark_page_flip_active(intel_crtc);
6d90c952 7172 intel_ring_advance(ring);
83d4092b
CW		 7173 return 0;
7174
7175err_unpin:
7176 intel_unpin_fb_obj(obj);
7177err:
8c9f3aaf
JB		 7178 return ret;
7179}
7180
7181static int intel_gen4_queue_flip(struct drm_device *dev,
7182 struct drm_crtc *crtc,
7183 struct drm_framebuffer *fb,
7184 struct drm_i915_gem_object *obj)
7185{
7186 struct drm_i915_private *dev_priv = dev->dev_private;
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188 uint32_t pf, pipesrc;
6d90c952 7189 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7190 int ret;
7191
6d90c952 7192 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7193 if (ret)
83d4092b 7194 goto err;
8c9f3aaf 7195
6d90c952 7196 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7197 if (ret)
83d4092b 7198 goto err_unpin;
8c9f3aaf
JB		 7199
7200 /* i965+ uses the linear or tiled offsets from the
7201 * Display Registers (which do not change across a page-flip)
7202 * so we need only reprogram the base address.
7203 */
6d90c952
DV		 7204 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7205 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7206 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7207 intel_ring_emit(ring,
7208 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7209 obj->tiling_mode);
8c9f3aaf
JB		 7210
7211 /* XXX Enabling the panel-fitter across page-flip is so far
7212 * untested on non-native modes, so ignore it for now.
7213 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7214 */
7215 pf = 0;
7216 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7217 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7218
7219 intel_mark_page_flip_active(intel_crtc);
6d90c952 7220 intel_ring_advance(ring);
83d4092b
CW		 7221 return 0;
7222
7223err_unpin:
7224 intel_unpin_fb_obj(obj);
7225err:
8c9f3aaf
JB		 7226 return ret;
7227}
7228
7229static int intel_gen6_queue_flip(struct drm_device *dev,
7230 struct drm_crtc *crtc,
7231 struct drm_framebuffer *fb,
7232 struct drm_i915_gem_object *obj)
7233{
7234 struct drm_i915_private *dev_priv = dev->dev_private;
7235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7236 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7237 uint32_t pf, pipesrc;
7238 int ret;
7239
6d90c952 7240 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7241 if (ret)
83d4092b 7242 goto err;
8c9f3aaf 7243
6d90c952 7244 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7245 if (ret)
83d4092b 7246 goto err_unpin;
8c9f3aaf 7247
6d90c952
DV		 7248 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7249 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7250 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7251 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7252
dc257cf1
DV		 7253 /* Contrary to the suggestions in the documentation,
7254 * "Enable Panel Fitter" does not seem to be required when page
7255 * flipping with a non-native mode, and worse causes a normal
7256 * modeset to fail.
7257 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7258 */
7259 pf = 0;
8c9f3aaf 7260 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7261 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7262
7263 intel_mark_page_flip_active(intel_crtc);
6d90c952 7264 intel_ring_advance(ring);
83d4092b
CW		 7265 return 0;
7266
7267err_unpin:
7268 intel_unpin_fb_obj(obj);
7269err:
8c9f3aaf
JB		 7270 return ret;
7271}
7272
7c9017e5
JB		 7273/*
7274 * On gen7 we currently use the blit ring because (in early silicon at least)
7275 * the render ring doesn't give us interrpts for page flip completion, which
7276 * means clients will hang after the first flip is queued. Fortunately the
7277 * blit ring generates interrupts properly, so use it instead.
7278 */
7279static int intel_gen7_queue_flip(struct drm_device *dev,
7280 struct drm_crtc *crtc,
7281 struct drm_framebuffer *fb,
7282 struct drm_i915_gem_object *obj)
7283{
7284 struct drm_i915_private *dev_priv = dev->dev_private;
7285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7286 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7287 uint32_t plane_bit = 0;
7c9017e5
JB		 7288 int ret;
7289
7290 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7291 if (ret)
83d4092b 7292 goto err;
7c9017e5 7293
cb05d8de
DV		 7294 switch(intel_crtc->plane) {
7295 case PLANE_A:
7296 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7297 break;
7298 case PLANE_B:
7299 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7300 break;
7301 case PLANE_C:
7302 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7303 break;
7304 default:
7305 WARN_ONCE(1, "unknown plane in flip command\n");
7306 ret = -ENODEV;
ab3951eb 7307 goto err_unpin;
cb05d8de
DV		 7308 }
7309
7c9017e5
JB		 7310 ret = intel_ring_begin(ring, 4);
7311 if (ret)
83d4092b 7312 goto err_unpin;
7c9017e5 7313
cb05d8de 7314 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7315 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7316 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7317 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7318
7319 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7320 intel_ring_advance(ring);
83d4092b
CW		 7321 return 0;
7322
7323err_unpin:
7324 intel_unpin_fb_obj(obj);
7325err:
7c9017e5
JB		 7326 return ret;
7327}
7328
8c9f3aaf
JB		 7329static int intel_default_queue_flip(struct drm_device *dev,
7330 struct drm_crtc *crtc,
7331 struct drm_framebuffer *fb,
7332 struct drm_i915_gem_object *obj)
7333{
7334 return -ENODEV;
7335}
7336
6b95a207
KH		 7337static int intel_crtc_page_flip(struct drm_crtc *crtc,
7338 struct drm_framebuffer *fb,
7339 struct drm_pending_vblank_event *event)
7340{
7341 struct drm_device *dev = crtc->dev;
7342 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7343 struct drm_framebuffer *old_fb = crtc->fb;
7344 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7346 struct intel_unpin_work *work;
8c9f3aaf 7347 unsigned long flags;
52e68630 7348 int ret;
6b95a207 7349
e6a595d2
VS		 7350 /* Can't change pixel format via MI display flips. */
7351 if (fb->pixel_format != crtc->fb->pixel_format)
7352 return -EINVAL;
7353
7354 /*
7355 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7356 * Note that pitch changes could also affect these register.
7357 */
7358 if (INTEL_INFO(dev)->gen > 3 &&
7359 (fb->offsets[0] != crtc->fb->offsets[0] ||
7360 fb->pitches[0] != crtc->fb->pitches[0]))
7361 return -EINVAL;
7362
6b95a207
KH		 7363 work = kzalloc(sizeof *work, GFP_KERNEL);
7364 if (work == NULL)
7365 return -ENOMEM;
7366
6b95a207 7367 work->event = event;
b4a98e57 7368 work->crtc = crtc;
4a35f83b 7369 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7370 INIT_WORK(&work->work, intel_unpin_work_fn);
7371
7317c75e
JB		 7372 ret = drm_vblank_get(dev, intel_crtc->pipe);
7373 if (ret)
7374 goto free_work;
7375
6b95a207
KH		 7376 /* We borrow the event spin lock for protecting unpin_work */
7377 spin_lock_irqsave(&dev->event_lock, flags);
7378 if (intel_crtc->unpin_work) {
7379 spin_unlock_irqrestore(&dev->event_lock, flags);
7380 kfree(work);
7317c75e 7381 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7382
7383 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7384 return -EBUSY;
7385 }
7386 intel_crtc->unpin_work = work;
7387 spin_unlock_irqrestore(&dev->event_lock, flags);
7388
b4a98e57
CW		 7389 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7390 flush_workqueue(dev_priv->wq);
7391
79158103
CW		 7392 ret = i915_mutex_lock_interruptible(dev);
7393 if (ret)
7394 goto cleanup;
6b95a207 7395
75dfca80 7396 /* Reference the objects for the scheduled work. */
05394f39
CW		 7397 drm_gem_object_reference(&work->old_fb_obj->base);
7398 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7399
7400 crtc->fb = fb;
96b099fd 7401
e1f99ce6 7402 work->pending_flip_obj = obj;
e1f99ce6 7403
4e5359cd
SF		 7404 work->enable_stall_check = true;
7405
b4a98e57 7406 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7407 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7408
8c9f3aaf
JB		 7409 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7410 if (ret)
7411 goto cleanup_pending;
6b95a207 7412
7782de3b 7413 intel_disable_fbc(dev);
f047e395 7414 intel_mark_fb_busy(obj);
6b95a207
KH		 7415 mutex_unlock(&dev->struct_mutex);
7416
e5510fac
JB		 7417 trace_i915_flip_request(intel_crtc->plane, obj);
7418
6b95a207 7419 return 0;
96b099fd 7420
8c9f3aaf 7421cleanup_pending:
b4a98e57 7422 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7423 crtc->fb = old_fb;
05394f39
CW		 7424 drm_gem_object_unreference(&work->old_fb_obj->base);
7425 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7426 mutex_unlock(&dev->struct_mutex);
7427
79158103 7428cleanup:
96b099fd
CW		 7429 spin_lock_irqsave(&dev->event_lock, flags);
7430 intel_crtc->unpin_work = NULL;
7431 spin_unlock_irqrestore(&dev->event_lock, flags);
7432
7317c75e
JB		 7433 drm_vblank_put(dev, intel_crtc->pipe);
7434free_work:
96b099fd
CW		 7435 kfree(work);
7436
7437 return ret;
6b95a207
KH		 7438}
7439
f6e5b160 7440static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7441 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7442 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7443};
7444
6ed0f796 7445bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7446{
6ed0f796
DV		 7447 struct intel_encoder *other_encoder;
7448 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7449
6ed0f796
DV		 7450 if (WARN_ON(!crtc))
7451 return false;
7452
7453 list_for_each_entry(other_encoder,
7454 &crtc->dev->mode_config.encoder_list,
7455 base.head) {
7456
7457 if (&other_encoder->new_crtc->base != crtc ||
7458 encoder == other_encoder)
7459 continue;
7460 else
7461 return true;
f47166d2
CW		 7462 }
7463
6ed0f796
DV		 7464 return false;
7465}
47f1c6c9 7466
50f56119
DV		 7467static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7468 struct drm_crtc *crtc)
7469{
7470 struct drm_device *dev;
7471 struct drm_crtc *tmp;
7472 int crtc_mask = 1;
47f1c6c9 7473
50f56119 7474 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7475
50f56119 7476 dev = crtc->dev;
47f1c6c9 7477
50f56119
DV		 7478 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7479 if (tmp == crtc)
7480 break;
7481 crtc_mask <<= 1;
7482 }
47f1c6c9 7483
50f56119
DV		 7484 if (encoder->possible_crtcs & crtc_mask)
7485 return true;
7486 return false;
47f1c6c9 7487}
79e53945 7488
9a935856
DV		 7489/**
7490 * intel_modeset_update_staged_output_state
7491 *
7492 * Updates the staged output configuration state, e.g. after we've read out the
7493 * current hw state.
7494 */
7495static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7496{
9a935856
DV		 7497 struct intel_encoder *encoder;
7498 struct intel_connector *connector;
f6e5b160 7499
9a935856
DV		 7500 list_for_each_entry(connector, &dev->mode_config.connector_list,
7501 base.head) {
7502 connector->new_encoder =
7503 to_intel_encoder(connector->base.encoder);
7504 }
f6e5b160 7505
9a935856
DV		 7506 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7507 base.head) {
7508 encoder->new_crtc =
7509 to_intel_crtc(encoder->base.crtc);
7510 }
f6e5b160
CW		 7511}
7512
9a935856
DV		 7513/**
7514 * intel_modeset_commit_output_state
7515 *
7516 * This function copies the stage display pipe configuration to the real one.
7517 */
7518static void intel_modeset_commit_output_state(struct drm_device *dev)
7519{
7520 struct intel_encoder *encoder;
7521 struct intel_connector *connector;
f6e5b160 7522
9a935856
DV		 7523 list_for_each_entry(connector, &dev->mode_config.connector_list,
7524 base.head) {
7525 connector->base.encoder = &connector->new_encoder->base;
7526 }
f6e5b160 7527
9a935856
DV		 7528 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7529 base.head) {
7530 encoder->base.crtc = &encoder->new_crtc->base;
7531 }
7532}
7533
4e53c2e0
DV		 7534static int
7535pipe_config_set_bpp(struct drm_crtc *crtc,
7536 struct drm_framebuffer *fb,
7537 struct intel_crtc_config *pipe_config)
7538{
7539 struct drm_device *dev = crtc->dev;
7540 struct drm_connector *connector;
7541 int bpp;
7542
d42264b1
DV		 7543 switch (fb->pixel_format) {
7544 case DRM_FORMAT_C8:
4e53c2e0
DV		 7545 bpp = 8*3; /* since we go through a colormap */
7546 break;
d42264b1
DV		 7547 case DRM_FORMAT_XRGB1555:
7548 case DRM_FORMAT_ARGB1555:
7549 /* checked in intel_framebuffer_init already */
7550 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7551 return -EINVAL;
7552 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7553 bpp = 6*3; /* min is 18bpp */
7554 break;
d42264b1
DV		 7555 case DRM_FORMAT_XBGR8888:
7556 case DRM_FORMAT_ABGR8888:
7557 /* checked in intel_framebuffer_init already */
7558 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7559 return -EINVAL;
7560 case DRM_FORMAT_XRGB8888:
7561 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7562 bpp = 8*3;
7563 break;
d42264b1
DV		 7564 case DRM_FORMAT_XRGB2101010:
7565 case DRM_FORMAT_ARGB2101010:
7566 case DRM_FORMAT_XBGR2101010:
7567 case DRM_FORMAT_ABGR2101010:
7568 /* checked in intel_framebuffer_init already */
7569 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7570 return -EINVAL;
4e53c2e0
DV		 7571 bpp = 10*3;
7572 break;
baba133a 7573 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7574 default:
7575 DRM_DEBUG_KMS("unsupported depth\n");
7576 return -EINVAL;
7577 }
7578
4e53c2e0
DV		 7579 pipe_config->pipe_bpp = bpp;
7580
7581 /* Clamp display bpp to EDID value */
7582 list_for_each_entry(connector, &dev->mode_config.connector_list,
7583 head) {
7584 if (connector->encoder && connector->encoder->crtc != crtc)
7585 continue;
7586
7587 /* Don't use an invalid EDID bpc value */
7588 if (connector->display_info.bpc &&
7589 connector->display_info.bpc * 3 < bpp) {
7590 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7591 bpp, connector->display_info.bpc*3);
7592 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7593 }
7594 }
7595
7596 return bpp;
7597}
7598
b8cecdf5
DV		 7599static struct intel_crtc_config *
7600intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7601 struct drm_framebuffer *fb,
b8cecdf5 7602 struct drm_display_mode *mode)
ee7b9f93 7603{
7758a113 7604 struct drm_device *dev = crtc->dev;
7758a113
DV		 7605 struct drm_encoder_helper_funcs *encoder_funcs;
7606 struct intel_encoder *encoder;
b8cecdf5 7607 struct intel_crtc_config *pipe_config;
4e53c2e0 7608 int plane_bpp;
ee7b9f93 7609
b8cecdf5
DV		 7610 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7611 if (!pipe_config)
7758a113
DV		 7612 return ERR_PTR(-ENOMEM);
7613
b8cecdf5
DV		 7614 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7615 drm_mode_copy(&pipe_config->requested_mode, mode);
7616
4e53c2e0
DV		 7617 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7618 if (plane_bpp < 0)
7619 goto fail;
7620
7758a113
DV		 7621 /* Pass our mode to the connectors and the CRTC to give them a chance to
7622 * adjust it according to limitations or connector properties, and also
7623 * a chance to reject the mode entirely.
47f1c6c9 7624 */
7758a113
DV		 7625 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7626 base.head) {
47f1c6c9 7627
7758a113
DV		 7628 if (&encoder->new_crtc->base != crtc)
7629 continue;
7ae89233
DV		 7630
7631 if (encoder->compute_config) {
7632 if (!(encoder->compute_config(encoder, pipe_config))) {
7633 DRM_DEBUG_KMS("Encoder config failure\n");
7634 goto fail;
7635 }
7636
7637 continue;
7638 }
7639
7758a113 7640 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7641 if (!(encoder_funcs->mode_fixup(&encoder->base,
7642 &pipe_config->requested_mode,
7643 &pipe_config->adjusted_mode))) {
7758a113
DV		 7644 DRM_DEBUG_KMS("Encoder fixup failed\n");
7645 goto fail;
7646 }
ee7b9f93 7647 }
47f1c6c9 7648
b8cecdf5 7649 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7650 DRM_DEBUG_KMS("CRTC fixup failed\n");
7651 goto fail;
ee7b9f93 7652 }
7758a113 7653 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7654
4e53c2e0
DV		 7655 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7656 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7657 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7658
b8cecdf5 7659 return pipe_config;
7758a113 7660fail:
b8cecdf5 7661 kfree(pipe_config);
7758a113 7662 return ERR_PTR(-EINVAL);
ee7b9f93 7663}
47f1c6c9 7664
e2e1ed41
DV		 7665/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7666 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7667static void
7668intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7669 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7670{
7671 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7672 struct drm_device *dev = crtc->dev;
7673 struct intel_encoder *encoder;
7674 struct intel_connector *connector;
7675 struct drm_crtc *tmp_crtc;
79e53945 7676
e2e1ed41 7677 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7678
e2e1ed41
DV		 7679 /* Check which crtcs have changed outputs connected to them, these need
7680 * to be part of the prepare_pipes mask. We don't (yet) support global
7681 * modeset across multiple crtcs, so modeset_pipes will only have one
7682 * bit set at most. */
7683 list_for_each_entry(connector, &dev->mode_config.connector_list,
7684 base.head) {
7685 if (connector->base.encoder == &connector->new_encoder->base)
7686 continue;
79e53945 7687
e2e1ed41
DV		 7688 if (connector->base.encoder) {
7689 tmp_crtc = connector->base.encoder->crtc;
7690
7691 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7692 }
7693
7694 if (connector->new_encoder)
7695 *prepare_pipes |=
7696 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7697 }
7698
e2e1ed41
DV		 7699 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7700 base.head) {
7701 if (encoder->base.crtc == &encoder->new_crtc->base)
7702 continue;
7703
7704 if (encoder->base.crtc) {
7705 tmp_crtc = encoder->base.crtc;
7706
7707 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7708 }
7709
7710 if (encoder->new_crtc)
7711 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7712 }
7713
e2e1ed41
DV		 7714 /* Check for any pipes that will be fully disabled ... */
7715 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7716 base.head) {
7717 bool used = false;
22fd0fab 7718
e2e1ed41
DV		 7719 /* Don't try to disable disabled crtcs. */
7720 if (!intel_crtc->base.enabled)
7721 continue;
7e7d76c3 7722
e2e1ed41
DV		 7723 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7724 base.head) {
7725 if (encoder->new_crtc == intel_crtc)
7726 used = true;
7727 }
7728
7729 if (!used)
7730 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7731 }
7732
e2e1ed41
DV		 7733
7734 /* set_mode is also used to update properties on life display pipes. */
7735 intel_crtc = to_intel_crtc(crtc);
7736 if (crtc->enabled)
7737 *prepare_pipes |= 1 << intel_crtc->pipe;
7738
b6c5164d
DV		 7739 /*
7740 * For simplicity do a full modeset on any pipe where the output routing
7741 * changed. We could be more clever, but that would require us to be
7742 * more careful with calling the relevant encoder->mode_set functions.
7743 */
e2e1ed41
DV		 7744 if (*prepare_pipes)
7745 *modeset_pipes = *prepare_pipes;
7746
7747 /* ... and mask these out. */
7748 *modeset_pipes &= ~(*disable_pipes);
7749 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7750
7751 /*
7752 * HACK: We don't (yet) fully support global modesets. intel_set_config
7753 * obies this rule, but the modeset restore mode of
7754 * intel_modeset_setup_hw_state does not.
7755 */
7756 *modeset_pipes &= 1 << intel_crtc->pipe;
7757 *prepare_pipes &= 1 << intel_crtc->pipe;
47f1c6c9 7758}
79e53945 7759
ea9d758d 7760static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7761{
ea9d758d 7762 struct drm_encoder *encoder;
f6e5b160 7763 struct drm_device *dev = crtc->dev;
f6e5b160 7764
ea9d758d
DV		 7765 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7766 if (encoder->crtc == crtc)
7767 return true;
7768
7769 return false;
7770}
7771
7772static void
7773intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7774{
7775 struct intel_encoder *intel_encoder;
7776 struct intel_crtc *intel_crtc;
7777 struct drm_connector *connector;
7778
7779 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7780 base.head) {
7781 if (!intel_encoder->base.crtc)
7782 continue;
7783
7784 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7785
7786 if (prepare_pipes & (1 << intel_crtc->pipe))
7787 intel_encoder->connectors_active = false;
7788 }
7789
7790 intel_modeset_commit_output_state(dev);
7791
7792 /* Update computed state. */
7793 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7794 base.head) {
7795 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7796 }
7797
7798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7799 if (!connector->encoder || !connector->encoder->crtc)
7800 continue;
7801
7802 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7803
7804 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7805 struct drm_property *dpms_property =
7806 dev->mode_config.dpms_property;
7807
ea9d758d 7808 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7809 drm_object_property_set_value(&connector->base,
68d34720
DV		 7810 dpms_property,
7811 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7812
7813 intel_encoder = to_intel_encoder(connector->encoder);
7814 intel_encoder->connectors_active = true;
7815 }
7816 }
7817
7818}
7819
25c5b266
DV		 7820#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7821 list_for_each_entry((intel_crtc), \
7822 &(dev)->mode_config.crtc_list, \
7823 base.head) \
7824 if (mask & (1 <<(intel_crtc)->pipe)) \
7825
0e8ffe1b
DV		 7826static bool
7827intel_pipe_config_compare(struct intel_crtc_config *current_config,
7828 struct intel_crtc_config *pipe_config)
7829{
88adfff1
DV		 7830 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7831 DRM_ERROR("mismatch in has_pch_encoder "
7832 "(expected %i, found %i)\n",
7833 current_config->has_pch_encoder,
7834 pipe_config->has_pch_encoder);
7835 return false;
7836 }
7837
0e8ffe1b
DV		 7838 return true;
7839}
7840
b980514c 7841void
8af6cf88
DV		 7842intel_modeset_check_state(struct drm_device *dev)
7843{
0e8ffe1b 7844 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7845 struct intel_crtc *crtc;
7846 struct intel_encoder *encoder;
7847 struct intel_connector *connector;
0e8ffe1b 7848 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7849
7850 list_for_each_entry(connector, &dev->mode_config.connector_list,
7851 base.head) {
7852 /* This also checks the encoder/connector hw state with the
7853 * ->get_hw_state callbacks. */
7854 intel_connector_check_state(connector);
7855
7856 WARN(&connector->new_encoder->base != connector->base.encoder,
7857 "connector's staged encoder doesn't match current encoder\n");
7858 }
7859
7860 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7861 base.head) {
7862 bool enabled = false;
7863 bool active = false;
7864 enum pipe pipe, tracked_pipe;
7865
7866 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7867 encoder->base.base.id,
7868 drm_get_encoder_name(&encoder->base));
7869
7870 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7871 "encoder's stage crtc doesn't match current crtc\n");
7872 WARN(encoder->connectors_active && !encoder->base.crtc,
7873 "encoder's active_connectors set, but no crtc\n");
7874
7875 list_for_each_entry(connector, &dev->mode_config.connector_list,
7876 base.head) {
7877 if (connector->base.encoder != &encoder->base)
7878 continue;
7879 enabled = true;
7880 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7881 active = true;
7882 }
7883 WARN(!!encoder->base.crtc != enabled,
7884 "encoder's enabled state mismatch "
7885 "(expected %i, found %i)\n",
7886 !!encoder->base.crtc, enabled);
7887 WARN(active && !encoder->base.crtc,
7888 "active encoder with no crtc\n");
7889
7890 WARN(encoder->connectors_active != active,
7891 "encoder's computed active state doesn't match tracked active state "
7892 "(expected %i, found %i)\n", active, encoder->connectors_active);
7893
7894 active = encoder->get_hw_state(encoder, &pipe);
7895 WARN(active != encoder->connectors_active,
7896 "encoder's hw state doesn't match sw tracking "
7897 "(expected %i, found %i)\n",
7898 encoder->connectors_active, active);
7899
7900 if (!encoder->base.crtc)
7901 continue;
7902
7903 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7904 WARN(active && pipe != tracked_pipe,
7905 "active encoder's pipe doesn't match"
7906 "(expected %i, found %i)\n",
7907 tracked_pipe, pipe);
7908
7909 }
7910
7911 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7912 base.head) {
7913 bool enabled = false;
7914 bool active = false;
7915
7916 DRM_DEBUG_KMS("[CRTC:%d]\n",
7917 crtc->base.base.id);
7918
7919 WARN(crtc->active && !crtc->base.enabled,
7920 "active crtc, but not enabled in sw tracking\n");
7921
7922 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7923 base.head) {
7924 if (encoder->base.crtc != &crtc->base)
7925 continue;
7926 enabled = true;
7927 if (encoder->connectors_active)
7928 active = true;
7929 }
7930 WARN(active != crtc->active,
7931 "crtc's computed active state doesn't match tracked active state "
7932 "(expected %i, found %i)\n", active, crtc->active);
7933 WARN(enabled != crtc->base.enabled,
7934 "crtc's computed enabled state doesn't match tracked enabled state "
7935 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7936
88adfff1 7937 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 7938 active = dev_priv->display.get_pipe_config(crtc,
7939 &pipe_config);
7940 WARN(crtc->active != active,
7941 "crtc active state doesn't match with hw state "
7942 "(expected %i, found %i)\n", crtc->active, active);
7943
7944 WARN(active &&
7945 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7946 "pipe state doesn't match!\n");
8af6cf88
DV		 7947 }
7948}
7949
f30da187
DV		 7950static int __intel_set_mode(struct drm_crtc *crtc,
7951 struct drm_display_mode *mode,
7952 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7953{
7954 struct drm_device *dev = crtc->dev;
dbf2b54e 7955 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7956 struct drm_display_mode *saved_mode, *saved_hwmode;
7957 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7958 struct intel_crtc *intel_crtc;
7959 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7960 int ret = 0;
a6778b3c 7961
3ac18232 7962 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7963 if (!saved_mode)
7964 return -ENOMEM;
3ac18232 7965 saved_hwmode = saved_mode + 1;
a6778b3c 7966
e2e1ed41 7967 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7968 &prepare_pipes, &disable_pipes);
7969
3ac18232
TG		 7970 *saved_hwmode = crtc->hwmode;
7971 *saved_mode = crtc->mode;
a6778b3c 7972
25c5b266
DV		 7973 /* Hack: Because we don't (yet) support global modeset on multiple
7974 * crtcs, we don't keep track of the new mode for more than one crtc.
7975 * Hence simply check whether any bit is set in modeset_pipes in all the
7976 * pieces of code that are not yet converted to deal with mutliple crtcs
7977 * changing their mode at the same time. */
25c5b266 7978 if (modeset_pipes) {
4e53c2e0 7979 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7980 if (IS_ERR(pipe_config)) {
7981 ret = PTR_ERR(pipe_config);
7982 pipe_config = NULL;
7983
3ac18232 7984 goto out;
25c5b266 7985 }
25c5b266 7986 }
a6778b3c 7987
460da916
DV		 7988 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7989 modeset_pipes, prepare_pipes, disable_pipes);
7990
7991 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7992 intel_crtc_disable(&intel_crtc->base);
7993
ea9d758d
DV		 7994 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7995 if (intel_crtc->base.enabled)
7996 dev_priv->display.crtc_disable(&intel_crtc->base);
7997 }
a6778b3c 7998
6c4c86f5
DV		 7999 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8000 * to set it here already despite that we pass it down the callchain.
f6e5b160 8001 */
b8cecdf5 8002 if (modeset_pipes) {
3b117c8f 8003 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8004 crtc->mode = *mode;
b8cecdf5
DV		 8005 /* mode_set/enable/disable functions rely on a correct pipe
8006 * config. */
8007 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8008 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8009 }
7758a113 8010
ea9d758d
DV		 8011 /* Only after disabling all output pipelines that will be changed can we
8012 * update the the output configuration. */
8013 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8014
47fab737
DV		 8015 if (dev_priv->display.modeset_global_resources)
8016 dev_priv->display.modeset_global_resources(dev);
8017
a6778b3c
DV		 8018 /* Set up the DPLL and any encoders state that needs to adjust or depend
8019 * on the DPLL.
f6e5b160 8020 */
25c5b266 8021 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8022 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8023 x, y, fb);
8024 if (ret)
8025 goto done;
a6778b3c
DV		 8026 }
8027
8028 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8029 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8030 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8031
25c5b266
DV		 8032 if (modeset_pipes) {
8033 /* Store real post-adjustment hardware mode. */
b8cecdf5 8034 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8035
25c5b266
DV		 8036 /* Calculate and store various constants which
8037 * are later needed by vblank and swap-completion
8038 * timestamping. They are derived from true hwmode.
8039 */
8040 drm_calc_timestamping_constants(crtc);
8041 }
a6778b3c
DV		 8042
8043 /* FIXME: add subpixel order */
8044done:
c0c36b94 8045 if (ret && crtc->enabled) {
3ac18232
TG		 8046 crtc->hwmode = *saved_hwmode;
8047 crtc->mode = *saved_mode;
a6778b3c
DV		 8048 }
8049
3ac18232 8050out:
b8cecdf5 8051 kfree(pipe_config);
3ac18232 8052 kfree(saved_mode);
a6778b3c 8053 return ret;
f6e5b160
CW		 8054}
8055
f30da187
DV		 8056int intel_set_mode(struct drm_crtc *crtc,
8057 struct drm_display_mode *mode,
8058 int x, int y, struct drm_framebuffer *fb)
8059{
8060 int ret;
8061
8062 ret = __intel_set_mode(crtc, mode, x, y, fb);
8063
8064 if (ret == 0)
8065 intel_modeset_check_state(crtc->dev);
8066
8067 return ret;
8068}
8069
c0c36b94
CW		 8070void intel_crtc_restore_mode(struct drm_crtc *crtc)
8071{
8072 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8073}
8074
25c5b266
DV		 8075#undef for_each_intel_crtc_masked
8076
d9e55608
DV		 8077static void intel_set_config_free(struct intel_set_config *config)
8078{
8079 if (!config)
8080 return;
8081
1aa4b628
DV		 8082 kfree(config->save_connector_encoders);
8083 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8084 kfree(config);
8085}
8086
85f9eb71
DV		 8087static int intel_set_config_save_state(struct drm_device *dev,
8088 struct intel_set_config *config)
8089{
85f9eb71
DV		 8090 struct drm_encoder *encoder;
8091 struct drm_connector *connector;
8092 int count;
8093
1aa4b628
DV		 8094 config->save_encoder_crtcs =
8095 kcalloc(dev->mode_config.num_encoder,
8096 sizeof(struct drm_crtc *), GFP_KERNEL);
8097 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8098 return -ENOMEM;
8099
1aa4b628
DV		 8100 config->save_connector_encoders =
8101 kcalloc(dev->mode_config.num_connector,
8102 sizeof(struct drm_encoder *), GFP_KERNEL);
8103 if (!config->save_connector_encoders)
85f9eb71
DV		 8104 return -ENOMEM;
8105
8106 /* Copy data. Note that driver private data is not affected.
8107 * Should anything bad happen only the expected state is
8108 * restored, not the drivers personal bookkeeping.
8109 */
85f9eb71
DV		 8110 count = 0;
8111 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8112 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8113 }
8114
8115 count = 0;
8116 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8117 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8118 }
8119
8120 return 0;
8121}
8122
8123static void intel_set_config_restore_state(struct drm_device *dev,
8124 struct intel_set_config *config)
8125{
9a935856
DV		 8126 struct intel_encoder *encoder;
8127 struct intel_connector *connector;
85f9eb71
DV		 8128 int count;
8129
85f9eb71 8130 count = 0;
9a935856
DV		 8131 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8132 encoder->new_crtc =
8133 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8134 }
8135
8136 count = 0;
9a935856
DV		 8137 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8138 connector->new_encoder =
8139 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8140 }
8141}
8142
e3de42b6
ID		 8143static bool
8144is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8145 int num_connectors)
8146{
8147 int i;
8148
8149 for (i = 0; i < num_connectors; i++)
8150 if (connectors[i].encoder &&
8151 connectors[i].encoder->crtc == crtc &&
8152 connectors[i].dpms != DRM_MODE_DPMS_ON)
8153 return true;
8154
8155 return false;
8156}
8157
5e2b584e
DV		 8158static void
8159intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8160 struct intel_set_config *config)
8161{
8162
8163 /* We should be able to check here if the fb has the same properties
8164 * and then just flip_or_move it */
e3de42b6
ID		 8165 if (set->connectors != NULL &&
8166 is_crtc_connector_off(set->crtc, *set->connectors,
8167 set->num_connectors)) {
8168 config->mode_changed = true;
8169 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8170 /* If we have no fb then treat it as a full mode set */
8171 if (set->crtc->fb == NULL) {
8172 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8173 config->mode_changed = true;
8174 } else if (set->fb == NULL) {
8175 config->mode_changed = true;
72f4901e
DV		 8176 } else if (set->fb->pixel_format !=
8177 set->crtc->fb->pixel_format) {
5e2b584e 8178 config->mode_changed = true;
e3de42b6 8179 } else {
5e2b584e 8180 config->fb_changed = true;
e3de42b6 8181 }
5e2b584e
DV		 8182 }
8183
835c5873 8184 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8185 config->fb_changed = true;
8186
8187 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8188 DRM_DEBUG_KMS("modes are different, full mode set\n");
8189 drm_mode_debug_printmodeline(&set->crtc->mode);
8190 drm_mode_debug_printmodeline(set->mode);
8191 config->mode_changed = true;
8192 }
8193}
8194
2e431051 8195static int
9a935856
DV		 8196intel_modeset_stage_output_state(struct drm_device *dev,
8197 struct drm_mode_set *set,
8198 struct intel_set_config *config)
50f56119 8199{
85f9eb71 8200 struct drm_crtc *new_crtc;
9a935856
DV		 8201 struct intel_connector *connector;
8202 struct intel_encoder *encoder;
2e431051 8203 int count, ro;
50f56119 8204
9abdda74 8205 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8206 * of connectors. For paranoia, double-check this. */
8207 WARN_ON(!set->fb && (set->num_connectors != 0));
8208 WARN_ON(set->fb && (set->num_connectors == 0));
8209
50f56119 8210 count = 0;
9a935856
DV		 8211 list_for_each_entry(connector, &dev->mode_config.connector_list,
8212 base.head) {
8213 /* Otherwise traverse passed in connector list and get encoders
8214 * for them. */
50f56119 8215 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8216 if (set->connectors[ro] == &connector->base) {
8217 connector->new_encoder = connector->encoder;
50f56119
DV		 8218 break;
8219 }
8220 }
8221
9a935856
DV		 8222 /* If we disable the crtc, disable all its connectors. Also, if
8223 * the connector is on the changing crtc but not on the new
8224 * connector list, disable it. */
8225 if ((!set->fb || ro == set->num_connectors) &&
8226 connector->base.encoder &&
8227 connector->base.encoder->crtc == set->crtc) {
8228 connector->new_encoder = NULL;
8229
8230 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8231 connector->base.base.id,
8232 drm_get_connector_name(&connector->base));
8233 }
8234
8235
8236 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8237 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8238 config->mode_changed = true;
50f56119
DV		 8239 }
8240 }
9a935856 8241 /* connector->new_encoder is now updated for all connectors. */
50f56119 8242
9a935856 8243 /* Update crtc of enabled connectors. */
50f56119 8244 count = 0;
9a935856
DV		 8245 list_for_each_entry(connector, &dev->mode_config.connector_list,
8246 base.head) {
8247 if (!connector->new_encoder)
50f56119
DV		 8248 continue;
8249
9a935856 8250 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8251
8252 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8253 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8254 new_crtc = set->crtc;
8255 }
8256
8257 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8258 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8259 new_crtc)) {
5e2b584e 8260 return -EINVAL;
50f56119 8261 }
9a935856
DV		 8262 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8263
8264 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8265 connector->base.base.id,
8266 drm_get_connector_name(&connector->base),
8267 new_crtc->base.id);
8268 }
8269
8270 /* Check for any encoders that needs to be disabled. */
8271 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8272 base.head) {
8273 list_for_each_entry(connector,
8274 &dev->mode_config.connector_list,
8275 base.head) {
8276 if (connector->new_encoder == encoder) {
8277 WARN_ON(!connector->new_encoder->new_crtc);
8278
8279 goto next_encoder;
8280 }
8281 }
8282 encoder->new_crtc = NULL;
8283next_encoder:
8284 /* Only now check for crtc changes so we don't miss encoders
8285 * that will be disabled. */
8286 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8287 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8288 config->mode_changed = true;
50f56119
DV		 8289 }
8290 }
9a935856 8291 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8292
2e431051
DV		 8293 return 0;
8294}
8295
8296static int intel_crtc_set_config(struct drm_mode_set *set)
8297{
8298 struct drm_device *dev;
2e431051
DV		 8299 struct drm_mode_set save_set;
8300 struct intel_set_config *config;
8301 int ret;
2e431051 8302
8d3e375e
DV		 8303 BUG_ON(!set);
8304 BUG_ON(!set->crtc);
8305 BUG_ON(!set->crtc->helper_private);
2e431051 8306
7e53f3a4
DV		 8307 /* Enforce sane interface api - has been abused by the fb helper. */
8308 BUG_ON(!set->mode && set->fb);
8309 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8310
2e431051
DV		 8311 if (set->fb) {
8312 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8313 set->crtc->base.id, set->fb->base.id,
8314 (int)set->num_connectors, set->x, set->y);
8315 } else {
8316 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8317 }
8318
8319 dev = set->crtc->dev;
8320
8321 ret = -ENOMEM;
8322 config = kzalloc(sizeof(*config), GFP_KERNEL);
8323 if (!config)
8324 goto out_config;
8325
8326 ret = intel_set_config_save_state(dev, config);
8327 if (ret)
8328 goto out_config;
8329
8330 save_set.crtc = set->crtc;
8331 save_set.mode = &set->crtc->mode;
8332 save_set.x = set->crtc->x;
8333 save_set.y = set->crtc->y;
8334 save_set.fb = set->crtc->fb;
8335
8336 /* Compute whether we need a full modeset, only an fb base update or no
8337 * change at all. In the future we might also check whether only the
8338 * mode changed, e.g. for LVDS where we only change the panel fitter in
8339 * such cases. */
8340 intel_set_config_compute_mode_changes(set, config);
8341
9a935856 8342 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8343 if (ret)
8344 goto fail;
8345
5e2b584e 8346 if (config->mode_changed) {
87f1faa6 8347 if (set->mode) {
50f56119
DV		 8348 DRM_DEBUG_KMS("attempting to set mode from"
8349 " userspace\n");
8350 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8351 }
8352
c0c36b94
CW		 8353 ret = intel_set_mode(set->crtc, set->mode,
8354 set->x, set->y, set->fb);
5e2b584e 8355 } else if (config->fb_changed) {
4878cae2
VS		 8356 intel_crtc_wait_for_pending_flips(set->crtc);
8357
4f660f49 8358 ret = intel_pipe_set_base(set->crtc,
94352cf9 8359 set->x, set->y, set->fb);
50f56119
DV		 8360 }
8361
2d05eae1
CW		 8362 if (ret) {
8363 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8364 set->crtc->base.id, ret);
50f56119 8365fail:
2d05eae1 8366 intel_set_config_restore_state(dev, config);
50f56119 8367
2d05eae1
CW		 8368 /* Try to restore the config */
8369 if (config->mode_changed &&
8370 intel_set_mode(save_set.crtc, save_set.mode,
8371 save_set.x, save_set.y, save_set.fb))
8372 DRM_ERROR("failed to restore config after modeset failure\n");
8373 }
50f56119 8374
d9e55608
DV		 8375out_config:
8376 intel_set_config_free(config);
50f56119
DV		 8377 return ret;
8378}
f6e5b160
CW		 8379
8380static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8381 .cursor_set = intel_crtc_cursor_set,
8382 .cursor_move = intel_crtc_cursor_move,
8383 .gamma_set = intel_crtc_gamma_set,
50f56119 8384 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8385 .destroy = intel_crtc_destroy,
8386 .page_flip = intel_crtc_page_flip,
8387};
8388
79f689aa
PZ		 8389static void intel_cpu_pll_init(struct drm_device *dev)
8390{
affa9354 8391 if (HAS_DDI(dev))
79f689aa
PZ		 8392 intel_ddi_pll_init(dev);
8393}
8394
ee7b9f93
JB		 8395static void intel_pch_pll_init(struct drm_device *dev)
8396{
8397 drm_i915_private_t *dev_priv = dev->dev_private;
8398 int i;
8399
8400 if (dev_priv->num_pch_pll == 0) {
8401 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8402 return;
8403 }
8404
8405 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8406 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8407 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8408 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8409 }
8410}
8411
b358d0a6 8412static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8413{
22fd0fab 8414 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8415 struct intel_crtc *intel_crtc;
8416 int i;
8417
8418 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8419 if (intel_crtc == NULL)
8420 return;
8421
8422 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8423
8424 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8425 for (i = 0; i < 256; i++) {
8426 intel_crtc->lut_r[i] = i;
8427 intel_crtc->lut_g[i] = i;
8428 intel_crtc->lut_b[i] = i;
8429 }
8430
80824003
JB		 8431 /* Swap pipes & planes for FBC on pre-965 */
8432 intel_crtc->pipe = pipe;
8433 intel_crtc->plane = pipe;
3b117c8f 8434 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8435 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8436 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8437 intel_crtc->plane = !pipe;
80824003
JB		 8438 }
8439
22fd0fab
JB		 8440 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8441 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8442 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8443 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8444
79e53945 8445 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8446}
8447
08d7b3d1 8448int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8449 struct drm_file *file)
08d7b3d1 8450{
08d7b3d1 8451 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8452 struct drm_mode_object *drmmode_obj;
8453 struct intel_crtc *crtc;
08d7b3d1 8454
1cff8f6b
DV		 8455 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8456 return -ENODEV;
08d7b3d1 8457
c05422d5
DV		 8458 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8459 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8460
c05422d5 8461 if (!drmmode_obj) {
08d7b3d1
CW		 8462 DRM_ERROR("no such CRTC id\n");
8463 return -EINVAL;
8464 }
8465
c05422d5
DV		 8466 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8467 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8468
c05422d5 8469 return 0;
08d7b3d1
CW		 8470}
8471
66a9278e 8472static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8473{
66a9278e
DV		 8474 struct drm_device *dev = encoder->base.dev;
8475 struct intel_encoder *source_encoder;
79e53945 8476 int index_mask = 0;
79e53945
JB		 8477 int entry = 0;
8478
66a9278e
DV		 8479 list_for_each_entry(source_encoder,
8480 &dev->mode_config.encoder_list, base.head) {
8481
8482 if (encoder == source_encoder)
79e53945 8483 index_mask |= (1 << entry);
66a9278e
DV		 8484
8485 /* Intel hw has only one MUX where enocoders could be cloned. */
8486 if (encoder->cloneable && source_encoder->cloneable)
8487 index_mask |= (1 << entry);
8488
79e53945
JB		 8489 entry++;
8490 }
4ef69c7a 8491
79e53945
JB		 8492 return index_mask;
8493}
8494
4d302442
CW		 8495static bool has_edp_a(struct drm_device *dev)
8496{
8497 struct drm_i915_private *dev_priv = dev->dev_private;
8498
8499 if (!IS_MOBILE(dev))
8500 return false;
8501
8502 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8503 return false;
8504
8505 if (IS_GEN5(dev) &&
8506 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8507 return false;
8508
8509 return true;
8510}
8511
79e53945
JB		 8512static void intel_setup_outputs(struct drm_device *dev)
8513{
725e30ad 8514 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8515 struct intel_encoder *encoder;
cb0953d7 8516 bool dpd_is_edp = false;
f3cfcba6 8517 bool has_lvds;
79e53945 8518
f3cfcba6 8519 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8520 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8521 /* disable the panel fitter on everything but LVDS */
8522 I915_WRITE(PFIT_CONTROL, 0);
8523 }
79e53945 8524
c40c0f5b 8525 if (!IS_ULT(dev))
79935fca 8526 intel_crt_init(dev);
cb0953d7 8527
affa9354 8528 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8529 int found;
8530
8531 /* Haswell uses DDI functions to detect digital outputs */
8532 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8533 /* DDI A only supports eDP */
8534 if (found)
8535 intel_ddi_init(dev, PORT_A);
8536
8537 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8538 * register */
8539 found = I915_READ(SFUSE_STRAP);
8540
8541 if (found & SFUSE_STRAP_DDIB_DETECTED)
8542 intel_ddi_init(dev, PORT_B);
8543 if (found & SFUSE_STRAP_DDIC_DETECTED)
8544 intel_ddi_init(dev, PORT_C);
8545 if (found & SFUSE_STRAP_DDID_DETECTED)
8546 intel_ddi_init(dev, PORT_D);
8547 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8548 int found;
270b3042
DV		 8549 dpd_is_edp = intel_dpd_is_edp(dev);
8550
8551 if (has_edp_a(dev))
8552 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8553
dc0fa718 8554 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8555 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8556 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8557 if (!found)
e2debe91 8558 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8559 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8560 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8561 }
8562
dc0fa718 8563 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8564 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8565
dc0fa718 8566 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8567 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8568
5eb08b69 8569 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8570 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8571
270b3042 8572 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8573 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8574 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8575 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8576 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8577 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8578
dc0fa718 8579 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8580 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8581 PORT_B);
67cfc203
VS		 8582 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8583 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8584 }
103a196f 8585 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8586 bool found = false;
7d57382e 8587
e2debe91 8588 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8589 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8590 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8591 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8592 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8593 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8594 }
27185ae1 8595
b01f2c3a
JB		 8596 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8597 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8598 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8599 }
725e30ad 8600 }
13520b05
KH		 8601
8602 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8603
e2debe91 8604 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8605 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8606 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8607 }
27185ae1 8608
e2debe91 8609 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8610
b01f2c3a
JB		 8611 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8612 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8613 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8614 }
8615 if (SUPPORTS_INTEGRATED_DP(dev)) {
8616 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8617 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8618 }
725e30ad 8619 }
27185ae1 8620
b01f2c3a
JB		 8621 if (SUPPORTS_INTEGRATED_DP(dev) &&
8622 (I915_READ(DP_D) & DP_DETECTED)) {
8623 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8624 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8625 }
bad720ff 8626 } else if (IS_GEN2(dev))
79e53945
JB		 8627 intel_dvo_init(dev);
8628
103a196f 8629 if (SUPPORTS_TV(dev))
79e53945
JB		 8630 intel_tv_init(dev);
8631
4ef69c7a
CW		 8632 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8633 encoder->base.possible_crtcs = encoder->crtc_mask;
8634 encoder->base.possible_clones =
66a9278e 8635 intel_encoder_clones(encoder);
79e53945 8636 }
47356eb6 8637
dde86e2d 8638 intel_init_pch_refclk(dev);
270b3042
DV		 8639
8640 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8641}
8642
8643static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8644{
8645 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8646
8647 drm_framebuffer_cleanup(fb);
05394f39 8648 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8649
8650 kfree(intel_fb);
8651}
8652
8653static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8654 struct drm_file *file,
79e53945
JB		 8655 unsigned int *handle)
8656{
8657 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8658 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8659
05394f39 8660 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8661}
8662
8663static const struct drm_framebuffer_funcs intel_fb_funcs = {
8664 .destroy = intel_user_framebuffer_destroy,
8665 .create_handle = intel_user_framebuffer_create_handle,
8666};
8667
38651674
DA		 8668int intel_framebuffer_init(struct drm_device *dev,
8669 struct intel_framebuffer *intel_fb,
308e5bcb 8670 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8671 struct drm_i915_gem_object *obj)
79e53945 8672{
79e53945
JB		 8673 int ret;
8674
c16ed4be
CW		 8675 if (obj->tiling_mode == I915_TILING_Y) {
8676 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8677 return -EINVAL;
c16ed4be 8678 }
57cd6508 8679
c16ed4be
CW		 8680 if (mode_cmd->pitches[0] & 63) {
8681 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8682 mode_cmd->pitches[0]);
57cd6508 8683 return -EINVAL;
c16ed4be 8684 }
57cd6508 8685
5d7bd705 8686 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8687 if (mode_cmd->pitches[0] > 32768) {
8688 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8689 mode_cmd->pitches[0]);
5d7bd705 8690 return -EINVAL;
c16ed4be 8691 }
5d7bd705
VS		 8692
8693 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8694 mode_cmd->pitches[0] != obj->stride) {
8695 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8696 mode_cmd->pitches[0], obj->stride);
5d7bd705 8697 return -EINVAL;
c16ed4be 8698 }
5d7bd705 8699
57779d06 8700 /* Reject formats not supported by any plane early. */
308e5bcb 8701 switch (mode_cmd->pixel_format) {
57779d06 8702 case DRM_FORMAT_C8:
04b3924d
VS		 8703 case DRM_FORMAT_RGB565:
8704 case DRM_FORMAT_XRGB8888:
8705 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8706 break;
8707 case DRM_FORMAT_XRGB1555:
8708 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8709 if (INTEL_INFO(dev)->gen > 3) {
8710 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8711 return -EINVAL;
c16ed4be 8712 }
57779d06
VS		 8713 break;
8714 case DRM_FORMAT_XBGR8888:
8715 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8716 case DRM_FORMAT_XRGB2101010:
8717 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8718 case DRM_FORMAT_XBGR2101010:
8719 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8720 if (INTEL_INFO(dev)->gen < 4) {
8721 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8722 return -EINVAL;
c16ed4be 8723 }
b5626747 8724 break;
04b3924d
VS		 8725 case DRM_FORMAT_YUYV:
8726 case DRM_FORMAT_UYVY:
8727 case DRM_FORMAT_YVYU:
8728 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8729 if (INTEL_INFO(dev)->gen < 5) {
8730 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8731 return -EINVAL;
c16ed4be 8732 }
57cd6508
CW		 8733 break;
8734 default:
c16ed4be 8735 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8736 return -EINVAL;
8737 }
8738
90f9a336
VS		 8739 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8740 if (mode_cmd->offsets[0] != 0)
8741 return -EINVAL;
8742
c7d73f6a
DV		 8743 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8744 intel_fb->obj = obj;
8745
79e53945
JB		 8746 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8747 if (ret) {
8748 DRM_ERROR("framebuffer init failed %d\n", ret);
8749 return ret;
8750 }
8751
79e53945
JB		 8752 return 0;
8753}
8754
79e53945
JB		 8755static struct drm_framebuffer *
8756intel_user_framebuffer_create(struct drm_device *dev,
8757 struct drm_file *filp,
308e5bcb 8758 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8759{
05394f39 8760 struct drm_i915_gem_object *obj;
79e53945 8761
308e5bcb
JB		 8762 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8763 mode_cmd->handles[0]));
c8725226 8764 if (&obj->base == NULL)
cce13ff7 8765 return ERR_PTR(-ENOENT);
79e53945 8766
d2dff872 8767 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8768}
8769
79e53945 8770static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8771 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8772 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8773};
8774
e70236a8
JB		 8775/* Set up chip specific display functions */
8776static void intel_init_display(struct drm_device *dev)
8777{
8778 struct drm_i915_private *dev_priv = dev->dev_private;
8779
affa9354 8780 if (HAS_DDI(dev)) {
0e8ffe1b 8781 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8782 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8783 dev_priv->display.crtc_enable = haswell_crtc_enable;
8784 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8785 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8786 dev_priv->display.update_plane = ironlake_update_plane;
8787 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8788 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8789 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8790 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8791 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8792 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8793 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8794 } else {
0e8ffe1b 8795 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8796 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8797 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8798 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8799 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8800 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8801 }
e70236a8 8802
e70236a8 8803 /* Returns the core display clock speed */
25eb05fc
JB		 8804 if (IS_VALLEYVIEW(dev))
8805 dev_priv->display.get_display_clock_speed =
8806 valleyview_get_display_clock_speed;
8807 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8808 dev_priv->display.get_display_clock_speed =
8809 i945_get_display_clock_speed;
8810 else if (IS_I915G(dev))
8811 dev_priv->display.get_display_clock_speed =
8812 i915_get_display_clock_speed;
f2b115e6 8813 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8814 dev_priv->display.get_display_clock_speed =
8815 i9xx_misc_get_display_clock_speed;
8816 else if (IS_I915GM(dev))
8817 dev_priv->display.get_display_clock_speed =
8818 i915gm_get_display_clock_speed;
8819 else if (IS_I865G(dev))
8820 dev_priv->display.get_display_clock_speed =
8821 i865_get_display_clock_speed;
f0f8a9ce 8822 else if (IS_I85X(dev))
e70236a8
JB		 8823 dev_priv->display.get_display_clock_speed =
8824 i855_get_display_clock_speed;
8825 else /* 852, 830 */
8826 dev_priv->display.get_display_clock_speed =
8827 i830_get_display_clock_speed;
8828
7f8a8569 8829 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8830 if (IS_GEN5(dev)) {
674cf967 8831 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8832 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8833 } else if (IS_GEN6(dev)) {
674cf967 8834 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8835 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8836 } else if (IS_IVYBRIDGE(dev)) {
8837 /* FIXME: detect B0+ stepping and use auto training */
8838 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8839 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8840 dev_priv->display.modeset_global_resources =
8841 ivb_modeset_global_resources;
c82e4d26
ED		 8842 } else if (IS_HASWELL(dev)) {
8843 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8844 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8845 dev_priv->display.modeset_global_resources =
8846 haswell_modeset_global_resources;
a0e63c22 8847 }
6067aaea 8848 } else if (IS_G4X(dev)) {
e0dac65e 8849 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8850 }
8c9f3aaf
JB		 8851
8852 /* Default just returns -ENODEV to indicate unsupported */
8853 dev_priv->display.queue_flip = intel_default_queue_flip;
8854
8855 switch (INTEL_INFO(dev)->gen) {
8856 case 2:
8857 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8858 break;
8859
8860 case 3:
8861 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8862 break;
8863
8864 case 4:
8865 case 5:
8866 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8867 break;
8868
8869 case 6:
8870 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8871 break;
7c9017e5
JB		 8872 case 7:
8873 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8874 break;
8c9f3aaf 8875 }
e70236a8
JB		 8876}
8877
b690e96c
JB		 8878/*
8879 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8880 * resume, or other times. This quirk makes sure that's the case for
8881 * affected systems.
8882 */
0206e353 8883static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8884{
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886
8887 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8888 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8889}
8890
435793df
KP		 8891/*
8892 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8893 */
8894static void quirk_ssc_force_disable(struct drm_device *dev)
8895{
8896 struct drm_i915_private *dev_priv = dev->dev_private;
8897 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8898 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8899}
8900
4dca20ef 8901/*
5a15ab5b
CE		 8902 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8903 * brightness value
4dca20ef
CE		 8904 */
8905static void quirk_invert_brightness(struct drm_device *dev)
8906{
8907 struct drm_i915_private *dev_priv = dev->dev_private;
8908 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8909 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8910}
8911
b690e96c
JB		 8912struct intel_quirk {
8913 int device;
8914 int subsystem_vendor;
8915 int subsystem_device;
8916 void (*hook)(struct drm_device *dev);
8917};
8918
5f85f176
EE		 8919/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8920struct intel_dmi_quirk {
8921 void (*hook)(struct drm_device *dev);
8922 const struct dmi_system_id (*dmi_id_list)[];
8923};
8924
8925static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8926{
8927 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8928 return 1;
8929}
8930
8931static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8932 {
8933 .dmi_id_list = &(const struct dmi_system_id[]) {
8934 {
8935 .callback = intel_dmi_reverse_brightness,
8936 .ident = "NCR Corporation",
8937 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8938 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8939 },
8940 },
8941 { } /* terminating entry */
8942 },
8943 .hook = quirk_invert_brightness,
8944 },
8945};
8946
c43b5634 8947static struct intel_quirk intel_quirks[] = {
b690e96c 8948 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8949 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8950
b690e96c
JB		 8951 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8952 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8953
b690e96c
JB		 8954 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8955 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8956
ccd0d36e 8957 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8958 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8959 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8960
8961 /* Lenovo U160 cannot use SSC on LVDS */
8962 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8963
8964 /* Sony Vaio Y cannot use SSC on LVDS */
8965 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8966
8967 /* Acer Aspire 5734Z must invert backlight brightness */
8968 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8969
8970 /* Acer/eMachines G725 */
8971 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8972
8973 /* Acer/eMachines e725 */
8974 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8975
8976 /* Acer/Packard Bell NCL20 */
8977 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8978
8979 /* Acer Aspire 4736Z */
8980 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8981};
8982
8983static void intel_init_quirks(struct drm_device *dev)
8984{
8985 struct pci_dev *d = dev->pdev;
8986 int i;
8987
8988 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8989 struct intel_quirk *q = &intel_quirks[i];
8990
8991 if (d->device == q->device &&
8992 (d->subsystem_vendor == q->subsystem_vendor ||
8993 q->subsystem_vendor == PCI_ANY_ID) &&
8994 (d->subsystem_device == q->subsystem_device ||
8995 q->subsystem_device == PCI_ANY_ID))
8996 q->hook(dev);
8997 }
5f85f176
EE		 8998 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8999 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9000 intel_dmi_quirks[i].hook(dev);
9001 }
b690e96c
JB		 9002}
9003
9cce37f4
JB		 9004/* Disable the VGA plane that we never use */
9005static void i915_disable_vga(struct drm_device *dev)
9006{
9007 struct drm_i915_private *dev_priv = dev->dev_private;
9008 u8 sr1;
766aa1c4 9009 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9010
9011 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9012 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9013 sr1 = inb(VGA_SR_DATA);
9014 outb(sr1 | 1<<5, VGA_SR_DATA);
9015 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9016 udelay(300);
9017
9018 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9019 POSTING_READ(vga_reg);
9020}
9021
f817586c
DV		 9022void intel_modeset_init_hw(struct drm_device *dev)
9023{
fa42e23c 9024 intel_init_power_well(dev);
0232e927 9025
a8f78b58
ED		 9026 intel_prepare_ddi(dev);
9027
f817586c
DV		 9028 intel_init_clock_gating(dev);
9029
79f5b2c7 9030 mutex_lock(&dev->struct_mutex);
8090c6b9 9031 intel_enable_gt_powersave(dev);
79f5b2c7 9032 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9033}
9034
79e53945
JB		 9035void intel_modeset_init(struct drm_device *dev)
9036{
652c393a 9037 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9038 int i, j, ret;
79e53945
JB		 9039
9040 drm_mode_config_init(dev);
9041
9042 dev->mode_config.min_width = 0;
9043 dev->mode_config.min_height = 0;
9044
019d96cb
DA		 9045 dev->mode_config.preferred_depth = 24;
9046 dev->mode_config.prefer_shadow = 1;
9047
e6ecefaa 9048 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9049
b690e96c
JB		 9050 intel_init_quirks(dev);
9051
1fa61106
ED		 9052 intel_init_pm(dev);
9053
e3c74757
BW		 9054 if (INTEL_INFO(dev)->num_pipes == 0)
9055 return;
9056
e70236a8
JB		 9057 intel_init_display(dev);
9058
a6c45cf0
CW		 9059 if (IS_GEN2(dev)) {
9060 dev->mode_config.max_width = 2048;
9061 dev->mode_config.max_height = 2048;
9062 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9063 dev->mode_config.max_width = 4096;
9064 dev->mode_config.max_height = 4096;
79e53945 9065 } else {
a6c45cf0
CW		 9066 dev->mode_config.max_width = 8192;
9067 dev->mode_config.max_height = 8192;
79e53945 9068 }
5d4545ae 9069 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9070
28c97730 9071 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9072 INTEL_INFO(dev)->num_pipes,
9073 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9074
7eb552ae 9075 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9076 intel_crtc_init(dev, i);
7f1f3851
JB		 9077 for (j = 0; j < dev_priv->num_plane; j++) {
9078 ret = intel_plane_init(dev, i, j);
9079 if (ret)
9080 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9081 i, j, ret);
9082 }
79e53945
JB		 9083 }
9084
79f689aa 9085 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9086 intel_pch_pll_init(dev);
9087
9cce37f4
JB		 9088 /* Just disable it once at startup */
9089 i915_disable_vga(dev);
79e53945 9090 intel_setup_outputs(dev);
11be49eb
CW		 9091
9092 /* Just in case the BIOS is doing something questionable. */
9093 intel_disable_fbc(dev);
2c7111db
CW		 9094}
9095
24929352
DV		 9096static void
9097intel_connector_break_all_links(struct intel_connector *connector)
9098{
9099 connector->base.dpms = DRM_MODE_DPMS_OFF;
9100 connector->base.encoder = NULL;
9101 connector->encoder->connectors_active = false;
9102 connector->encoder->base.crtc = NULL;
9103}
9104
7fad798e
DV		 9105static void intel_enable_pipe_a(struct drm_device *dev)
9106{
9107 struct intel_connector *connector;
9108 struct drm_connector *crt = NULL;
9109 struct intel_load_detect_pipe load_detect_temp;
9110
9111 /* We can't just switch on the pipe A, we need to set things up with a
9112 * proper mode and output configuration. As a gross hack, enable pipe A
9113 * by enabling the load detect pipe once. */
9114 list_for_each_entry(connector,
9115 &dev->mode_config.connector_list,
9116 base.head) {
9117 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9118 crt = &connector->base;
9119 break;
9120 }
9121 }
9122
9123 if (!crt)
9124 return;
9125
9126 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9127 intel_release_load_detect_pipe(crt, &load_detect_temp);
9128
652c393a 9129
7fad798e
DV		 9130}
9131
fa555837
DV		 9132static bool
9133intel_check_plane_mapping(struct intel_crtc *crtc)
9134{
7eb552ae
BW		 9135 struct drm_device *dev = crtc->base.dev;
9136 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9137 u32 reg, val;
9138
7eb552ae 9139 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9140 return true;
9141
9142 reg = DSPCNTR(!crtc->plane);
9143 val = I915_READ(reg);
9144
9145 if ((val & DISPLAY_PLANE_ENABLE) &&
9146 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9147 return false;
9148
9149 return true;
9150}
9151
24929352
DV		 9152static void intel_sanitize_crtc(struct intel_crtc *crtc)
9153{
9154 struct drm_device *dev = crtc->base.dev;
9155 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9156 u32 reg;
24929352 9157
24929352 9158 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9159 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9160 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9161
9162 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9163 * disable the crtc (and hence change the state) if it is wrong. Note
9164 * that gen4+ has a fixed plane -> pipe mapping. */
9165 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9166 struct intel_connector *connector;
9167 bool plane;
9168
24929352
DV		 9169 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9170 crtc->base.base.id);
9171
9172 /* Pipe has the wrong plane attached and the plane is active.
9173 * Temporarily change the plane mapping and disable everything
9174 * ... */
9175 plane = crtc->plane;
9176 crtc->plane = !plane;
9177 dev_priv->display.crtc_disable(&crtc->base);
9178 crtc->plane = plane;
9179
9180 /* ... and break all links. */
9181 list_for_each_entry(connector, &dev->mode_config.connector_list,
9182 base.head) {
9183 if (connector->encoder->base.crtc != &crtc->base)
9184 continue;
9185
9186 intel_connector_break_all_links(connector);
9187 }
9188
9189 WARN_ON(crtc->active);
9190 crtc->base.enabled = false;
9191 }
24929352 9192
7fad798e
DV		 9193 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9194 crtc->pipe == PIPE_A && !crtc->active) {
9195 /* BIOS forgot to enable pipe A, this mostly happens after
9196 * resume. Force-enable the pipe to fix this, the update_dpms
9197 * call below we restore the pipe to the right state, but leave
9198 * the required bits on. */
9199 intel_enable_pipe_a(dev);
9200 }
9201
24929352
DV		 9202 /* Adjust the state of the output pipe according to whether we
9203 * have active connectors/encoders. */
9204 intel_crtc_update_dpms(&crtc->base);
9205
9206 if (crtc->active != crtc->base.enabled) {
9207 struct intel_encoder *encoder;
9208
9209 /* This can happen either due to bugs in the get_hw_state
9210 * functions or because the pipe is force-enabled due to the
9211 * pipe A quirk. */
9212 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9213 crtc->base.base.id,
9214 crtc->base.enabled ? "enabled" : "disabled",
9215 crtc->active ? "enabled" : "disabled");
9216
9217 crtc->base.enabled = crtc->active;
9218
9219 /* Because we only establish the connector -> encoder ->
9220 * crtc links if something is active, this means the
9221 * crtc is now deactivated. Break the links. connector
9222 * -> encoder links are only establish when things are
9223 * actually up, hence no need to break them. */
9224 WARN_ON(crtc->active);
9225
9226 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9227 WARN_ON(encoder->connectors_active);
9228 encoder->base.crtc = NULL;
9229 }
9230 }
9231}
9232
9233static void intel_sanitize_encoder(struct intel_encoder *encoder)
9234{
9235 struct intel_connector *connector;
9236 struct drm_device *dev = encoder->base.dev;
9237
9238 /* We need to check both for a crtc link (meaning that the
9239 * encoder is active and trying to read from a pipe) and the
9240 * pipe itself being active. */
9241 bool has_active_crtc = encoder->base.crtc &&
9242 to_intel_crtc(encoder->base.crtc)->active;
9243
9244 if (encoder->connectors_active && !has_active_crtc) {
9245 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9246 encoder->base.base.id,
9247 drm_get_encoder_name(&encoder->base));
9248
9249 /* Connector is active, but has no active pipe. This is
9250 * fallout from our resume register restoring. Disable
9251 * the encoder manually again. */
9252 if (encoder->base.crtc) {
9253 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9254 encoder->base.base.id,
9255 drm_get_encoder_name(&encoder->base));
9256 encoder->disable(encoder);
9257 }
9258
9259 /* Inconsistent output/port/pipe state happens presumably due to
9260 * a bug in one of the get_hw_state functions. Or someplace else
9261 * in our code, like the register restore mess on resume. Clamp
9262 * things to off as a safer default. */
9263 list_for_each_entry(connector,
9264 &dev->mode_config.connector_list,
9265 base.head) {
9266 if (connector->encoder != encoder)
9267 continue;
9268
9269 intel_connector_break_all_links(connector);
9270 }
9271 }
9272 /* Enabled encoders without active connectors will be fixed in
9273 * the crtc fixup. */
9274}
9275
44cec740 9276void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9277{
9278 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9279 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9280
9281 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9282 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9283 i915_disable_vga(dev);
0fde901f
KM		 9284 }
9285}
9286
24929352
DV		 9287/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9288 * and i915 state tracking structures. */
45e2b5f6
DV		 9289void intel_modeset_setup_hw_state(struct drm_device *dev,
9290 bool force_restore)
24929352
DV		 9291{
9292 struct drm_i915_private *dev_priv = dev->dev_private;
9293 enum pipe pipe;
9294 u32 tmp;
b5644d05 9295 struct drm_plane *plane;
24929352
DV		 9296 struct intel_crtc *crtc;
9297 struct intel_encoder *encoder;
9298 struct intel_connector *connector;
9299
affa9354 9300 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9301 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9302
9303 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9304 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9305 case TRANS_DDI_EDP_INPUT_A_ON:
9306 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9307 pipe = PIPE_A;
9308 break;
9309 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9310 pipe = PIPE_B;
9311 break;
9312 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9313 pipe = PIPE_C;
9314 break;
aaa148ec
DL		 9315 default:
9316 /* A bogus value has been programmed, disable
9317 * the transcoder */
9318 WARN(1, "Bogus eDP source %08x\n", tmp);
9319 intel_ddi_disable_transcoder_func(dev_priv,
9320 TRANSCODER_EDP);
9321 goto setup_pipes;
e28d54cb
PZ		 9322 }
9323
9324 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9325 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9326
9327 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9328 pipe_name(pipe));
9329 }
9330 }
9331
aaa148ec 9332setup_pipes:
0e8ffe1b
DV		 9333 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9334 base.head) {
3b117c8f 9335 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9336 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9337 crtc->config.cpu_transcoder = tmp;
9338
0e8ffe1b
DV		 9339 crtc->active = dev_priv->display.get_pipe_config(crtc,
9340 &crtc->config);
24929352
DV		 9341
9342 crtc->base.enabled = crtc->active;
9343
9344 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9345 crtc->base.base.id,
9346 crtc->active ? "enabled" : "disabled");
9347 }
9348
affa9354 9349 if (HAS_DDI(dev))
6441ab5f
PZ		 9350 intel_ddi_setup_hw_pll_state(dev);
9351
24929352
DV		 9352 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9353 base.head) {
9354 pipe = 0;
9355
9356 if (encoder->get_hw_state(encoder, &pipe)) {
9357 encoder->base.crtc =
9358 dev_priv->pipe_to_crtc_mapping[pipe];
9359 } else {
9360 encoder->base.crtc = NULL;
9361 }
9362
9363 encoder->connectors_active = false;
9364 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9365 encoder->base.base.id,
9366 drm_get_encoder_name(&encoder->base),
9367 encoder->base.crtc ? "enabled" : "disabled",
9368 pipe);
9369 }
9370
9371 list_for_each_entry(connector, &dev->mode_config.connector_list,
9372 base.head) {
9373 if (connector->get_hw_state(connector)) {
9374 connector->base.dpms = DRM_MODE_DPMS_ON;
9375 connector->encoder->connectors_active = true;
9376 connector->base.encoder = &connector->encoder->base;
9377 } else {
9378 connector->base.dpms = DRM_MODE_DPMS_OFF;
9379 connector->base.encoder = NULL;
9380 }
9381 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9382 connector->base.base.id,
9383 drm_get_connector_name(&connector->base),
9384 connector->base.encoder ? "enabled" : "disabled");
9385 }
9386
9387 /* HW state is read out, now we need to sanitize this mess. */
9388 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9389 base.head) {
9390 intel_sanitize_encoder(encoder);
9391 }
9392
9393 for_each_pipe(pipe) {
9394 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9395 intel_sanitize_crtc(crtc);
9396 }
9a935856 9397
45e2b5f6 9398 if (force_restore) {
f30da187
DV		 9399 /*
9400 * We need to use raw interfaces for restoring state to avoid
9401 * checking (bogus) intermediate states.
9402 */
45e2b5f6 9403 for_each_pipe(pipe) {
b5644d05
JB		 9404 struct drm_crtc *crtc =
9405 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9406
9407 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9408 crtc->fb);
45e2b5f6 9409 }
b5644d05
JB		 9410 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9411 intel_plane_restore(plane);
0fde901f
KM		 9412
9413 i915_redisable_vga(dev);
45e2b5f6
DV		 9414 } else {
9415 intel_modeset_update_staged_output_state(dev);
9416 }
8af6cf88
DV		 9417
9418 intel_modeset_check_state(dev);
2e938892
DV		 9419
9420 drm_mode_config_reset(dev);
2c7111db
CW		 9421}
9422
9423void intel_modeset_gem_init(struct drm_device *dev)
9424{
1833b134 9425 intel_modeset_init_hw(dev);
02e792fb
DV		 9426
9427 intel_setup_overlay(dev);
24929352 9428
45e2b5f6 9429 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9430}
9431
9432void intel_modeset_cleanup(struct drm_device *dev)
9433{
652c393a
JB		 9434 struct drm_i915_private *dev_priv = dev->dev_private;
9435 struct drm_crtc *crtc;
9436 struct intel_crtc *intel_crtc;
9437
f87ea761 9438 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9439 mutex_lock(&dev->struct_mutex);
9440
723bfd70
JB		 9441 intel_unregister_dsm_handler();
9442
9443
652c393a
JB		 9444 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9445 /* Skip inactive CRTCs */
9446 if (!crtc->fb)
9447 continue;
9448
9449 intel_crtc = to_intel_crtc(crtc);
3dec0095 9450 intel_increase_pllclock(crtc);
652c393a
JB		 9451 }
9452
973d04f9 9453 intel_disable_fbc(dev);
e70236a8 9454
8090c6b9 9455 intel_disable_gt_powersave(dev);
0cdab21f 9456
930ebb46
DV		 9457 ironlake_teardown_rc6(dev);
9458
57f350b6
JB		 9459 if (IS_VALLEYVIEW(dev))
9460 vlv_init_dpio(dev);
9461
69341a5e
KH		 9462 mutex_unlock(&dev->struct_mutex);
9463
6c0d9350
DV		 9464 /* Disable the irq before mode object teardown, for the irq might
9465 * enqueue unpin/hotplug work. */
9466 drm_irq_uninstall(dev);
9467 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9468 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9469
1630fe75
CW		 9470 /* flush any delayed tasks or pending work */
9471 flush_scheduled_work();
9472
dc652f90
JN		 9473 /* destroy backlight, if any, before the connectors */
9474 intel_panel_destroy_backlight(dev);
9475
79e53945 9476 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9477
9478 intel_cleanup_overlay(dev);
79e53945
JB		 9479}
9480
f1c79df3
ZW		 9481/*
9482 * Return which encoder is currently attached for connector.
9483 */
df0e9248 9484struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9485{
df0e9248
CW		 9486 return &intel_attached_encoder(connector)->base;
9487}
f1c79df3 9488
df0e9248
CW		 9489void intel_connector_attach_encoder(struct intel_connector *connector,
9490 struct intel_encoder *encoder)
9491{
9492 connector->encoder = encoder;
9493 drm_mode_connector_attach_encoder(&connector->base,
9494 &encoder->base);
79e53945 9495}
28d52043
DA		 9496
9497/*
9498 * set vga decode state - true == enable VGA decode
9499 */
9500int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9501{
9502 struct drm_i915_private *dev_priv = dev->dev_private;
9503 u16 gmch_ctrl;
9504
9505 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9506 if (state)
9507 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9508 else
9509 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9510 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9511 return 0;
9512}
c4a1d9e4
CW		 9513
9514#ifdef CONFIG_DEBUG_FS
9515#include <linux/seq_file.h>
9516
9517struct intel_display_error_state {
9518 struct intel_cursor_error_state {
9519 u32 control;
9520 u32 position;
9521 u32 base;
9522 u32 size;
52331309 9523 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9524
9525 struct intel_pipe_error_state {
9526 u32 conf;
9527 u32 source;
9528
9529 u32 htotal;
9530 u32 hblank;
9531 u32 hsync;
9532 u32 vtotal;
9533 u32 vblank;
9534 u32 vsync;
52331309 9535 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9536
9537 struct intel_plane_error_state {
9538 u32 control;
9539 u32 stride;
9540 u32 size;
9541 u32 pos;
9542 u32 addr;
9543 u32 surface;
9544 u32 tile_offset;
52331309 9545 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9546};
9547
9548struct intel_display_error_state *
9549intel_display_capture_error_state(struct drm_device *dev)
9550{
0206e353 9551 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9552 struct intel_display_error_state *error;
702e7a56 9553 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9554 int i;
9555
9556 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9557 if (error == NULL)
9558 return NULL;
9559
52331309 9560 for_each_pipe(i) {
702e7a56
PZ		 9561 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9562
a18c4c3d
PZ		 9563 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9564 error->cursor[i].control = I915_READ(CURCNTR(i));
9565 error->cursor[i].position = I915_READ(CURPOS(i));
9566 error->cursor[i].base = I915_READ(CURBASE(i));
9567 } else {
9568 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9569 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9570 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9571 }
c4a1d9e4
CW		 9572
9573 error->plane[i].control = I915_READ(DSPCNTR(i));
9574 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9575 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9576 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9577 error->plane[i].pos = I915_READ(DSPPOS(i));
9578 }
ca291363
PZ		 9579 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9580 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9581 if (INTEL_INFO(dev)->gen >= 4) {
9582 error->plane[i].surface = I915_READ(DSPSURF(i));
9583 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9584 }
9585
702e7a56 9586 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9587 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9588 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9589 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9590 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9591 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9592 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9593 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9594 }
9595
9596 return error;
9597}
9598
9599void
9600intel_display_print_error_state(struct seq_file *m,
9601 struct drm_device *dev,
9602 struct intel_display_error_state *error)
9603{
9604 int i;
9605
7eb552ae 9606 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9607 for_each_pipe(i) {
c4a1d9e4
CW		 9608 seq_printf(m, "Pipe [%d]:\n", i);
9609 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9610 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9611 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9612 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9613 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9614 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9615 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9616 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9617
9618 seq_printf(m, "Plane [%d]:\n", i);
9619 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9620 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9621 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9622 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9623 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9624 }
4b71a570 9625 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9626 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9627 if (INTEL_INFO(dev)->gen >= 4) {
9628 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9629 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9630 }
9631
9632 seq_printf(m, "Cursor [%d]:\n", i);
9633 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9634 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9635 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9636 }
9637}
9638#endif
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