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drm/i915: consolidate ->num_shared_dplls assignement
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
e2b78267
DV		 912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
a43f6e0f 917 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 918 return NULL;
919
a43f6e0f 920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 921}
922
040484af 923/* For ILK+ */
e72f9fbf
DV		 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
926 struct intel_crtc *crtc,
927 bool state)
040484af 928{
040484af
JB		 929 u32 val;
930 bool cur_state;
931
9d82aa17
ED		 932 if (HAS_PCH_LPT(dev_priv->dev)) {
933 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
934 return;
935 }
936
92b27b08
CW		 937 if (WARN (!pll,
938 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 939 return;
ee7b9f93 940
92b27b08
CW		 941 val = I915_READ(pll->pll_reg);
942 cur_state = !!(val & DPLL_VCO_ENABLE);
943 WARN(cur_state != state,
944 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
945 pll->pll_reg, state_string(state), state_string(cur_state), val);
946
947 /* Make sure the selected PLL is correctly attached to the transcoder */
948 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 949 u32 pch_dpll;
950
951 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 952 cur_state = pll->pll_reg == _PCH_DPLL_B;
953 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 954 "PLL[%d] not attached to this transcoder %c: %08x\n",
955 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 956 cur_state = !!(val >> (4*crtc->pipe + 3));
957 WARN(cur_state != state,
4bb6f1f3 958 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 959 pll->pll_reg == _PCH_DPLL_B,
960 state_string(state),
4bb6f1f3 961 pipe_name(crtc->pipe),
92b27b08
CW		 962 val);
963 }
d3ccbe86 964 }
040484af 965}
e72f9fbf
DV		 966#define assert_shared_dpll_enabled(d, p, c) assert_shared_dpll(d, p, c, true)
967#define assert_shared_dpll_disabled(d, p, c) assert_shared_dpll(d, p, c, false)
040484af
JB		 968
969static void assert_fdi_tx(struct drm_i915_private *dev_priv,
970 enum pipe pipe, bool state)
971{
972 int reg;
973 u32 val;
974 bool cur_state;
ad80a810
PZ		 975 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
976 pipe);
040484af 977
affa9354
PZ		 978 if (HAS_DDI(dev_priv->dev)) {
979 /* DDI does not have a specific FDI_TX register */
ad80a810 980 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 981 val = I915_READ(reg);
ad80a810 982 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 983 } else {
984 reg = FDI_TX_CTL(pipe);
985 val = I915_READ(reg);
986 cur_state = !!(val & FDI_TX_ENABLE);
987 }
040484af
JB		 988 WARN(cur_state != state,
989 "FDI TX state assertion failure (expected %s, current %s)\n",
990 state_string(state), state_string(cur_state));
991}
992#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
993#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
994
995static void assert_fdi_rx(struct drm_i915_private *dev_priv,
996 enum pipe pipe, bool state)
997{
998 int reg;
999 u32 val;
1000 bool cur_state;
1001
d63fa0dc
PZ		 1002 reg = FDI_RX_CTL(pipe);
1003 val = I915_READ(reg);
1004 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1005 WARN(cur_state != state,
1006 "FDI RX state assertion failure (expected %s, current %s)\n",
1007 state_string(state), state_string(cur_state));
1008}
1009#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1010#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1011
1012static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1013 enum pipe pipe)
1014{
1015 int reg;
1016 u32 val;
1017
1018 /* ILK FDI PLL is always enabled */
1019 if (dev_priv->info->gen == 5)
1020 return;
1021
bf507ef7 1022 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1023 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1024 return;
1025
040484af
JB		 1026 reg = FDI_TX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1029}
1030
1031static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int reg;
1035 u32 val;
1036
1037 reg = FDI_RX_CTL(pipe);
1038 val = I915_READ(reg);
1039 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1040}
1041
ea0760cf
JB		 1042static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1043 enum pipe pipe)
1044{
1045 int pp_reg, lvds_reg;
1046 u32 val;
1047 enum pipe panel_pipe = PIPE_A;
0de3b485 1048 bool locked = true;
ea0760cf
JB		 1049
1050 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1051 pp_reg = PCH_PP_CONTROL;
1052 lvds_reg = PCH_LVDS;
1053 } else {
1054 pp_reg = PP_CONTROL;
1055 lvds_reg = LVDS;
1056 }
1057
1058 val = I915_READ(pp_reg);
1059 if (!(val & PANEL_POWER_ON) ||
1060 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1061 locked = false;
1062
1063 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1064 panel_pipe = PIPE_B;
1065
1066 WARN(panel_pipe == pipe && locked,
1067 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1068 pipe_name(pipe));
ea0760cf
JB		 1069}
1070
b840d907
JB		 1071void assert_pipe(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, bool state)
b24e7179
JB		 1073{
1074 int reg;
1075 u32 val;
63d7bbe9 1076 bool cur_state;
702e7a56
PZ		 1077 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1078 pipe);
b24e7179 1079
8e636784
DV		 1080 /* if we need the pipe A quirk it must be always on */
1081 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1082 state = true;
1083
b97186f0
PZ		 1084 if (!intel_display_power_enabled(dev_priv->dev,
1085 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1086 cur_state = false;
1087 } else {
1088 reg = PIPECONF(cpu_transcoder);
1089 val = I915_READ(reg);
1090 cur_state = !!(val & PIPECONF_ENABLE);
1091 }
1092
63d7bbe9
JB		 1093 WARN(cur_state != state,
1094 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1095 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1096}
1097
931872fc
CW		 1098static void assert_plane(struct drm_i915_private *dev_priv,
1099 enum plane plane, bool state)
b24e7179
JB		 1100{
1101 int reg;
1102 u32 val;
931872fc 1103 bool cur_state;
b24e7179
JB		 1104
1105 reg = DSPCNTR(plane);
1106 val = I915_READ(reg);
931872fc
CW		 1107 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1108 WARN(cur_state != state,
1109 "plane %c assertion failure (expected %s, current %s)\n",
1110 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1111}
1112
931872fc
CW		 1113#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1114#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1115
b24e7179
JB		 1116static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1117 enum pipe pipe)
1118{
653e1026 1119 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1120 int reg, i;
1121 u32 val;
1122 int cur_pipe;
1123
653e1026
VS		 1124 /* Primary planes are fixed to pipes on gen4+ */
1125 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1126 reg = DSPCNTR(pipe);
1127 val = I915_READ(reg);
1128 WARN((val & DISPLAY_PLANE_ENABLE),
1129 "plane %c assertion failure, should be disabled but not\n",
1130 plane_name(pipe));
19ec1358 1131 return;
28c05794 1132 }
19ec1358 1133
b24e7179 1134 /* Need to check both planes against the pipe */
653e1026 1135 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1136 reg = DSPCNTR(i);
1137 val = I915_READ(reg);
1138 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1139 DISPPLANE_SEL_PIPE_SHIFT;
1140 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1141 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1142 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1143 }
1144}
1145
19332d7a
JB		 1146static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
20674eef 1149 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1150 int reg, i;
1151 u32 val;
1152
20674eef
VS		 1153 if (IS_VALLEYVIEW(dev)) {
1154 for (i = 0; i < dev_priv->num_plane; i++) {
1155 reg = SPCNTR(pipe, i);
1156 val = I915_READ(reg);
1157 WARN((val & SP_ENABLE),
1158 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1159 sprite_name(pipe, i), pipe_name(pipe));
1160 }
1161 } else if (INTEL_INFO(dev)->gen >= 7) {
1162 reg = SPRCTL(pipe);
1163 val = I915_READ(reg);
1164 WARN((val & SPRITE_ENABLE),
1165 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1166 plane_name(pipe), pipe_name(pipe));
1167 } else if (INTEL_INFO(dev)->gen >= 5) {
1168 reg = DVSCNTR(pipe);
19332d7a 1169 val = I915_READ(reg);
20674eef 1170 WARN((val & DVS_ENABLE),
06da8da2 1171 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1172 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1173 }
1174}
1175
92f2584a
JB		 1176static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1177{
1178 u32 val;
1179 bool enabled;
1180
9d82aa17
ED		 1181 if (HAS_PCH_LPT(dev_priv->dev)) {
1182 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1183 return;
1184 }
1185
92f2584a
JB		 1186 val = I915_READ(PCH_DREF_CONTROL);
1187 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1188 DREF_SUPERSPREAD_SOURCE_MASK));
1189 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1190}
1191
ab9412ba
DV		 1192static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
92f2584a
JB		 1194{
1195 int reg;
1196 u32 val;
1197 bool enabled;
1198
ab9412ba 1199 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1200 val = I915_READ(reg);
1201 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1202 WARN(enabled,
1203 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1204 pipe_name(pipe));
92f2584a
JB		 1205}
1206
4e634389
KP		 1207static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1208 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1209{
1210 if ((val & DP_PORT_EN) == 0)
1211 return false;
1212
1213 if (HAS_PCH_CPT(dev_priv->dev)) {
1214 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1215 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1216 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1217 return false;
1218 } else {
1219 if ((val & DP_PIPE_MASK) != (pipe << 30))
1220 return false;
1221 }
1222 return true;
1223}
1224
1519b995
KP		 1225static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227{
dc0fa718 1228 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1232 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1233 return false;
1234 } else {
dc0fa718 1235 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1236 return false;
1237 }
1238 return true;
1239}
1240
1241static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243{
1244 if ((val & LVDS_PORT_EN) == 0)
1245 return false;
1246
1247 if (HAS_PCH_CPT(dev_priv->dev)) {
1248 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1249 return false;
1250 } else {
1251 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1252 return false;
1253 }
1254 return true;
1255}
1256
1257static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1259{
1260 if ((val & ADPA_DAC_ENABLE) == 0)
1261 return false;
1262 if (HAS_PCH_CPT(dev_priv->dev)) {
1263 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1264 return false;
1265 } else {
1266 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1267 return false;
1268 }
1269 return true;
1270}
1271
291906f1 1272static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1273 enum pipe pipe, int reg, u32 port_sel)
291906f1 1274{
47a05eca 1275 u32 val = I915_READ(reg);
4e634389 1276 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1277 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1278 reg, pipe_name(pipe));
de9a35ab 1279
75c5da27
DV		 1280 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1281 && (val & DP_PIPEB_SELECT),
de9a35ab 1282 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1283}
1284
1285static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe, int reg)
1287{
47a05eca 1288 u32 val = I915_READ(reg);
b70ad586 1289 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1290 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 reg, pipe_name(pipe));
de9a35ab 1292
dc0fa718 1293 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1294 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1295 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1296}
1297
1298static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1299 enum pipe pipe)
1300{
1301 int reg;
1302 u32 val;
291906f1 1303
f0575e92
KP		 1304 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1307
1308 reg = PCH_ADPA;
1309 val = I915_READ(reg);
b70ad586 1310 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1311 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1312 pipe_name(pipe));
291906f1
JB		 1313
1314 reg = PCH_LVDS;
1315 val = I915_READ(reg);
b70ad586 1316 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1317 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1318 pipe_name(pipe));
291906f1 1319
e2debe91
PZ		 1320 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1323}
1324
63d7bbe9
JB		 1325/**
1326 * intel_enable_pll - enable a PLL
1327 * @dev_priv: i915 private structure
1328 * @pipe: pipe PLL to enable
1329 *
1330 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1331 * make sure the PLL reg is writable first though, since the panel write
1332 * protect mechanism may be enabled.
1333 *
1334 * Note! This is for pre-ILK only.
7434a255
TR		 1335 *
1336 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1337 */
1338static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1339{
1340 int reg;
1341 u32 val;
1342
58c6eaa2
DV		 1343 assert_pipe_disabled(dev_priv, pipe);
1344
63d7bbe9 1345 /* No really, not for ILK+ */
a0c4da24 1346 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1347
1348 /* PLL is protected by panel, make sure we can write it */
1349 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1350 assert_panel_unlocked(dev_priv, pipe);
1351
1352 reg = DPLL(pipe);
1353 val = I915_READ(reg);
1354 val |= DPLL_VCO_ENABLE;
1355
1356 /* We do this three times for luck */
1357 I915_WRITE(reg, val);
1358 POSTING_READ(reg);
1359 udelay(150); /* wait for warmup */
1360 I915_WRITE(reg, val);
1361 POSTING_READ(reg);
1362 udelay(150); /* wait for warmup */
1363 I915_WRITE(reg, val);
1364 POSTING_READ(reg);
1365 udelay(150); /* wait for warmup */
1366}
1367
1368/**
1369 * intel_disable_pll - disable a PLL
1370 * @dev_priv: i915 private structure
1371 * @pipe: pipe PLL to disable
1372 *
1373 * Disable the PLL for @pipe, making sure the pipe is off first.
1374 *
1375 * Note! This is for pre-ILK only.
1376 */
1377static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1378{
1379 int reg;
1380 u32 val;
1381
1382 /* Don't disable pipe A or pipe A PLLs if needed */
1383 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1384 return;
1385
1386 /* Make sure the pipe isn't still relying on us */
1387 assert_pipe_disabled(dev_priv, pipe);
1388
1389 reg = DPLL(pipe);
1390 val = I915_READ(reg);
1391 val &= ~DPLL_VCO_ENABLE;
1392 I915_WRITE(reg, val);
1393 POSTING_READ(reg);
1394}
1395
89b667f8
JB		 1396void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1397{
1398 u32 port_mask;
1399
1400 if (!port)
1401 port_mask = DPLL_PORTB_READY_MASK;
1402 else
1403 port_mask = DPLL_PORTC_READY_MASK;
1404
1405 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1406 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1407 'B' + port, I915_READ(DPLL(0)));
1408}
1409
92f2584a 1410/**
e72f9fbf 1411 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to enable
1414 *
1415 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1416 * drives the transcoder clock.
1417 */
e2b78267 1418static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1419{
e2b78267
DV		 1420 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1421 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a
JB		 1422 int reg;
1423 u32 val;
1424
48da64a8 1425 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1426 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1427 if (pll == NULL)
1428 return;
1429
1430 if (WARN_ON(pll->refcount == 0))
1431 return;
ee7b9f93
JB		 1432
1433 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1434 pll->pll_reg, pll->active, pll->on,
e2b78267 1435 crtc->base.base.id);
92f2584a
JB		 1436
1437 /* PCH refclock must be enabled first */
1438 assert_pch_refclk_enabled(dev_priv);
1439
cdbd2316
DV		 1440 if (pll->active++) {
1441 WARN_ON(!pll->on);
e72f9fbf 1442 assert_shared_dpll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1443 return;
1444 }
f4a091c7 1445 WARN_ON(pll->on);
ee7b9f93
JB		 1446
1447 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1448
1449 reg = pll->pll_reg;
92f2584a
JB		 1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(200);
ee7b9f93
JB		 1455
1456 pll->on = true;
92f2584a
JB		 1457}
1458
e2b78267 1459static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1460{
e2b78267
DV		 1461 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1462 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1463 int reg;
ee7b9f93 1464 u32 val;
4c609cb8 1465
92f2584a
JB		 1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1468 if (pll == NULL)
1469 return;
92f2584a 1470
48da64a8
CW		 1471 if (WARN_ON(pll->refcount == 0))
1472 return;
7a419866 1473
ee7b9f93
JB		 1474 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1475 pll->pll_reg, pll->active, pll->on,
e2b78267 1476 crtc->base.base.id);
7a419866 1477
48da64a8 1478 if (WARN_ON(pll->active == 0)) {
e72f9fbf 1479 assert_shared_dpll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1480 return;
1481 }
1482
e72f9fbf 1483 assert_shared_dpll_enabled(dev_priv, pll, NULL);
f4a091c7 1484 WARN_ON(!pll->on);
cdbd2316 1485 if (--pll->active)
7a419866 1486 return;
ee7b9f93
JB		 1487
1488 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1489
1490 /* Make sure transcoder isn't still depending on us */
e2b78267 1491 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
7a419866 1492
ee7b9f93 1493 reg = pll->pll_reg;
92f2584a
JB		 1494 val = I915_READ(reg);
1495 val &= ~DPLL_VCO_ENABLE;
1496 I915_WRITE(reg, val);
1497 POSTING_READ(reg);
1498 udelay(200);
ee7b9f93
JB		 1499
1500 pll->on = false;
92f2584a
JB		 1501}
1502
b8a4f404
PZ		 1503static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1504 enum pipe pipe)
040484af 1505{
23670b32 1506 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1507 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1509 uint32_t reg, val, pipeconf_val;
040484af
JB		 1510
1511 /* PCH only available on ILK+ */
1512 BUG_ON(dev_priv->info->gen < 5);
1513
1514 /* Make sure PCH DPLL is enabled */
e72f9fbf 1515 assert_shared_dpll_enabled(dev_priv,
e2b78267
DV		 1516 intel_crtc_to_shared_dpll(intel_crtc),
1517 intel_crtc);
040484af
JB		 1518
1519 /* FDI must be feeding us bits for PCH ports */
1520 assert_fdi_tx_enabled(dev_priv, pipe);
1521 assert_fdi_rx_enabled(dev_priv, pipe);
1522
23670b32
DV		 1523 if (HAS_PCH_CPT(dev)) {
1524 /* Workaround: Set the timing override bit before enabling the
1525 * pch transcoder. */
1526 reg = TRANS_CHICKEN2(pipe);
1527 val = I915_READ(reg);
1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1529 I915_WRITE(reg, val);
59c859d6 1530 }
23670b32 1531
ab9412ba 1532 reg = PCH_TRANSCONF(pipe);
040484af 1533 val = I915_READ(reg);
5f7f726d 1534 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1535
1536 if (HAS_PCH_IBX(dev_priv->dev)) {
1537 /*
1538 * make the BPC in transcoder be consistent with
1539 * that in pipeconf reg.
1540 */
dfd07d72
DV		 1541 val &= ~PIPECONF_BPC_MASK;
1542 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1543 }
5f7f726d
PZ		 1544
1545 val &= ~TRANS_INTERLACE_MASK;
1546 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1547 if (HAS_PCH_IBX(dev_priv->dev) &&
1548 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1549 val |= TRANS_LEGACY_INTERLACED_ILK;
1550 else
1551 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1552 else
1553 val |= TRANS_PROGRESSIVE;
1554
040484af
JB		 1555 I915_WRITE(reg, val | TRANS_ENABLE);
1556 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1557 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1558}
1559
8fb033d7 1560static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1561 enum transcoder cpu_transcoder)
040484af 1562{
8fb033d7 1563 u32 val, pipeconf_val;
8fb033d7
PZ		 1564
1565 /* PCH only available on ILK+ */
1566 BUG_ON(dev_priv->info->gen < 5);
1567
8fb033d7 1568 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1569 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1570 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1571
223a6fdf
PZ		 1572 /* Workaround: set timing override bit. */
1573 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1574 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1575 I915_WRITE(_TRANSA_CHICKEN2, val);
1576
25f3ef11 1577 val = TRANS_ENABLE;
937bb610 1578 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1579
9a76b1c6
PZ		 1580 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1581 PIPECONF_INTERLACED_ILK)
a35f2679 1582 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1583 else
1584 val |= TRANS_PROGRESSIVE;
1585
ab9412ba
DV		 1586 I915_WRITE(LPT_TRANSCONF, val);
1587 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1588 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1589}
1590
b8a4f404
PZ		 1591static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1592 enum pipe pipe)
040484af 1593{
23670b32
DV		 1594 struct drm_device *dev = dev_priv->dev;
1595 uint32_t reg, val;
040484af
JB		 1596
1597 /* FDI relies on the transcoder */
1598 assert_fdi_tx_disabled(dev_priv, pipe);
1599 assert_fdi_rx_disabled(dev_priv, pipe);
1600
291906f1
JB		 1601 /* Ports must be off as well */
1602 assert_pch_ports_disabled(dev_priv, pipe);
1603
ab9412ba 1604 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1605 val = I915_READ(reg);
1606 val &= ~TRANS_ENABLE;
1607 I915_WRITE(reg, val);
1608 /* wait for PCH transcoder off, transcoder state */
1609 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1610 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1611
1612 if (!HAS_PCH_IBX(dev)) {
1613 /* Workaround: Clear the timing override chicken bit again. */
1614 reg = TRANS_CHICKEN2(pipe);
1615 val = I915_READ(reg);
1616 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1617 I915_WRITE(reg, val);
1618 }
040484af
JB		 1619}
1620
ab4d966c 1621static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1622{
8fb033d7
PZ		 1623 u32 val;
1624
ab9412ba 1625 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1626 val &= ~TRANS_ENABLE;
ab9412ba 1627 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1628 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1629 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1630 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1631
1632 /* Workaround: clear timing override bit. */
1633 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1634 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1635 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1636}
1637
b24e7179 1638/**
309cfea8 1639 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1640 * @dev_priv: i915 private structure
1641 * @pipe: pipe to enable
040484af 1642 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1643 *
1644 * Enable @pipe, making sure that various hardware specific requirements
1645 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1646 *
1647 * @pipe should be %PIPE_A or %PIPE_B.
1648 *
1649 * Will wait until the pipe is actually running (i.e. first vblank) before
1650 * returning.
1651 */
040484af
JB		 1652static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1653 bool pch_port)
b24e7179 1654{
702e7a56
PZ		 1655 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1656 pipe);
1a240d4d 1657 enum pipe pch_transcoder;
b24e7179
JB		 1658 int reg;
1659 u32 val;
1660
58c6eaa2
DV		 1661 assert_planes_disabled(dev_priv, pipe);
1662 assert_sprites_disabled(dev_priv, pipe);
1663
681e5811 1664 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1665 pch_transcoder = TRANSCODER_A;
1666 else
1667 pch_transcoder = pipe;
1668
b24e7179
JB		 1669 /*
1670 * A pipe without a PLL won't actually be able to drive bits from
1671 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1672 * need the check.
1673 */
1674 if (!HAS_PCH_SPLIT(dev_priv->dev))
1675 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1676 else {
1677 if (pch_port) {
1678 /* if driving the PCH, we need FDI enabled */
cc391bbb 1679 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1680 assert_fdi_tx_pll_enabled(dev_priv,
1681 (enum pipe) cpu_transcoder);
040484af
JB		 1682 }
1683 /* FIXME: assert CPU port conditions for SNB+ */
1684 }
b24e7179 1685
702e7a56 1686 reg = PIPECONF(cpu_transcoder);
b24e7179 1687 val = I915_READ(reg);
00d70b15
CW		 1688 if (val & PIPECONF_ENABLE)
1689 return;
1690
1691 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1692 intel_wait_for_vblank(dev_priv->dev, pipe);
1693}
1694
1695/**
309cfea8 1696 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1697 * @dev_priv: i915 private structure
1698 * @pipe: pipe to disable
1699 *
1700 * Disable @pipe, making sure that various hardware specific requirements
1701 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1702 *
1703 * @pipe should be %PIPE_A or %PIPE_B.
1704 *
1705 * Will wait until the pipe has shut down before returning.
1706 */
1707static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1708 enum pipe pipe)
1709{
702e7a56
PZ		 1710 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1711 pipe);
b24e7179
JB		 1712 int reg;
1713 u32 val;
1714
1715 /*
1716 * Make sure planes won't keep trying to pump pixels to us,
1717 * or we might hang the display.
1718 */
1719 assert_planes_disabled(dev_priv, pipe);
19332d7a 1720 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1721
1722 /* Don't disable pipe A or pipe A PLLs if needed */
1723 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1724 return;
1725
702e7a56 1726 reg = PIPECONF(cpu_transcoder);
b24e7179 1727 val = I915_READ(reg);
00d70b15
CW		 1728 if ((val & PIPECONF_ENABLE) == 0)
1729 return;
1730
1731 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1732 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1733}
1734
d74362c9
KP		 1735/*
1736 * Plane regs are double buffered, going from enabled->disabled needs a
1737 * trigger in order to latch. The display address reg provides this.
1738 */
6f1d69b0 1739void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1740 enum plane plane)
1741{
14f86147
DL		 1742 if (dev_priv->info->gen >= 4)
1743 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1744 else
1745 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1746}
1747
b24e7179
JB		 1748/**
1749 * intel_enable_plane - enable a display plane on a given pipe
1750 * @dev_priv: i915 private structure
1751 * @plane: plane to enable
1752 * @pipe: pipe being fed
1753 *
1754 * Enable @plane on @pipe, making sure that @pipe is running first.
1755 */
1756static void intel_enable_plane(struct drm_i915_private *dev_priv,
1757 enum plane plane, enum pipe pipe)
1758{
1759 int reg;
1760 u32 val;
1761
1762 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1763 assert_pipe_enabled(dev_priv, pipe);
1764
1765 reg = DSPCNTR(plane);
1766 val = I915_READ(reg);
00d70b15
CW		 1767 if (val & DISPLAY_PLANE_ENABLE)
1768 return;
1769
1770 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1771 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1772 intel_wait_for_vblank(dev_priv->dev, pipe);
1773}
1774
b24e7179
JB		 1775/**
1776 * intel_disable_plane - disable a display plane
1777 * @dev_priv: i915 private structure
1778 * @plane: plane to disable
1779 * @pipe: pipe consuming the data
1780 *
1781 * Disable @plane; should be an independent operation.
1782 */
1783static void intel_disable_plane(struct drm_i915_private *dev_priv,
1784 enum plane plane, enum pipe pipe)
1785{
1786 int reg;
1787 u32 val;
1788
1789 reg = DSPCNTR(plane);
1790 val = I915_READ(reg);
00d70b15
CW		 1791 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1792 return;
1793
1794 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1795 intel_flush_display_plane(dev_priv, plane);
1796 intel_wait_for_vblank(dev_priv->dev, pipe);
1797}
1798
693db184
CW		 1799static bool need_vtd_wa(struct drm_device *dev)
1800{
1801#ifdef CONFIG_INTEL_IOMMU
1802 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1803 return true;
1804#endif
1805 return false;
1806}
1807
127bd2ac 1808int
48b956c5 1809intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1810 struct drm_i915_gem_object *obj,
919926ae 1811 struct intel_ring_buffer *pipelined)
6b95a207 1812{
ce453d81 1813 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1814 u32 alignment;
1815 int ret;
1816
05394f39 1817 switch (obj->tiling_mode) {
6b95a207 1818 case I915_TILING_NONE:
534843da
CW		 1819 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1820 alignment = 128 * 1024;
a6c45cf0 1821 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1822 alignment = 4 * 1024;
1823 else
1824 alignment = 64 * 1024;
6b95a207
KH		 1825 break;
1826 case I915_TILING_X:
1827 /* pin() will align the object as required by fence */
1828 alignment = 0;
1829 break;
1830 case I915_TILING_Y:
8bb6e959
DV		 1831 /* Despite that we check this in framebuffer_init userspace can
1832 * screw us over and change the tiling after the fact. Only
1833 * pinned buffers can't change their tiling. */
1834 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1835 return -EINVAL;
1836 default:
1837 BUG();
1838 }
1839
693db184
CW		 1840 /* Note that the w/a also requires 64 PTE of padding following the
1841 * bo. We currently fill all unused PTE with the shadow page and so
1842 * we should always have valid PTE following the scanout preventing
1843 * the VT-d warning.
1844 */
1845 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1846 alignment = 256 * 1024;
1847
ce453d81 1848 dev_priv->mm.interruptible = false;
2da3b9b9 1849 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1850 if (ret)
ce453d81 1851 goto err_interruptible;
6b95a207
KH		 1852
1853 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1854 * fence, whereas 965+ only requires a fence if using
1855 * framebuffer compression. For simplicity, we always install
1856 * a fence as the cost is not that onerous.
1857 */
06d98131 1858 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1859 if (ret)
1860 goto err_unpin;
1690e1eb 1861
9a5a53b3 1862 i915_gem_object_pin_fence(obj);
6b95a207 1863
ce453d81 1864 dev_priv->mm.interruptible = true;
6b95a207 1865 return 0;
48b956c5
CW		 1866
1867err_unpin:
1868 i915_gem_object_unpin(obj);
ce453d81
CW		 1869err_interruptible:
1870 dev_priv->mm.interruptible = true;
48b956c5 1871 return ret;
6b95a207
KH		 1872}
1873
1690e1eb
CW		 1874void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1875{
1876 i915_gem_object_unpin_fence(obj);
1877 i915_gem_object_unpin(obj);
1878}
1879
c2c75131
DV		 1880/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1881 * is assumed to be a power-of-two. */
bc752862
CW		 1882unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1883 unsigned int tiling_mode,
1884 unsigned int cpp,
1885 unsigned int pitch)
c2c75131 1886{
bc752862
CW		 1887 if (tiling_mode != I915_TILING_NONE) {
1888 unsigned int tile_rows, tiles;
c2c75131 1889
bc752862
CW		 1890 tile_rows = *y / 8;
1891 *y %= 8;
c2c75131 1892
bc752862
CW		 1893 tiles = *x / (512/cpp);
1894 *x %= 512/cpp;
1895
1896 return tile_rows * pitch * 8 + tiles * 4096;
1897 } else {
1898 unsigned int offset;
1899
1900 offset = *y * pitch + *x * cpp;
1901 *y = 0;
1902 *x = (offset & 4095) / cpp;
1903 return offset & -4096;
1904 }
c2c75131
DV		 1905}
1906
17638cd6
JB		 1907static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1908 int x, int y)
81255565
JB		 1909{
1910 struct drm_device *dev = crtc->dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1913 struct intel_framebuffer *intel_fb;
05394f39 1914 struct drm_i915_gem_object *obj;
81255565 1915 int plane = intel_crtc->plane;
e506a0c6 1916 unsigned long linear_offset;
81255565 1917 u32 dspcntr;
5eddb70b 1918 u32 reg;
81255565
JB		 1919
1920 switch (plane) {
1921 case 0:
1922 case 1:
1923 break;
1924 default:
84f44ce7 1925 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1926 return -EINVAL;
1927 }
1928
1929 intel_fb = to_intel_framebuffer(fb);
1930 obj = intel_fb->obj;
81255565 1931
5eddb70b
CW		 1932 reg = DSPCNTR(plane);
1933 dspcntr = I915_READ(reg);
81255565
JB		 1934 /* Mask out pixel format bits in case we change it */
1935 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1936 switch (fb->pixel_format) {
1937 case DRM_FORMAT_C8:
81255565
JB		 1938 dspcntr |= DISPPLANE_8BPP;
1939 break;
57779d06
VS		 1940 case DRM_FORMAT_XRGB1555:
1941 case DRM_FORMAT_ARGB1555:
1942 dspcntr |= DISPPLANE_BGRX555;
81255565 1943 break;
57779d06
VS		 1944 case DRM_FORMAT_RGB565:
1945 dspcntr |= DISPPLANE_BGRX565;
1946 break;
1947 case DRM_FORMAT_XRGB8888:
1948 case DRM_FORMAT_ARGB8888:
1949 dspcntr |= DISPPLANE_BGRX888;
1950 break;
1951 case DRM_FORMAT_XBGR8888:
1952 case DRM_FORMAT_ABGR8888:
1953 dspcntr |= DISPPLANE_RGBX888;
1954 break;
1955 case DRM_FORMAT_XRGB2101010:
1956 case DRM_FORMAT_ARGB2101010:
1957 dspcntr |= DISPPLANE_BGRX101010;
1958 break;
1959 case DRM_FORMAT_XBGR2101010:
1960 case DRM_FORMAT_ABGR2101010:
1961 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1962 break;
1963 default:
baba133a 1964 BUG();
81255565 1965 }
57779d06 1966
a6c45cf0 1967 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1968 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1969 dspcntr |= DISPPLANE_TILED;
1970 else
1971 dspcntr &= ~DISPPLANE_TILED;
1972 }
1973
de1aa629
VS		 1974 if (IS_G4X(dev))
1975 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1976
5eddb70b 1977 I915_WRITE(reg, dspcntr);
81255565 1978
e506a0c6 1979 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1980
c2c75131
DV		 1981 if (INTEL_INFO(dev)->gen >= 4) {
1982 intel_crtc->dspaddr_offset =
bc752862
CW		 1983 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1984 fb->bits_per_pixel / 8,
1985 fb->pitches[0]);
c2c75131
DV		 1986 linear_offset -= intel_crtc->dspaddr_offset;
1987 } else {
e506a0c6 1988 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1989 }
e506a0c6
DV		 1990
1991 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1992 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1993 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1994 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1995 I915_MODIFY_DISPBASE(DSPSURF(plane),
1996 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1997 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1998 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1999 } else
e506a0c6 2000 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2001 POSTING_READ(reg);
81255565 2002
17638cd6
JB		 2003 return 0;
2004}
2005
2006static int ironlake_update_plane(struct drm_crtc *crtc,
2007 struct drm_framebuffer *fb, int x, int y)
2008{
2009 struct drm_device *dev = crtc->dev;
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2012 struct intel_framebuffer *intel_fb;
2013 struct drm_i915_gem_object *obj;
2014 int plane = intel_crtc->plane;
e506a0c6 2015 unsigned long linear_offset;
17638cd6
JB		 2016 u32 dspcntr;
2017 u32 reg;
2018
2019 switch (plane) {
2020 case 0:
2021 case 1:
27f8227b 2022 case 2:
17638cd6
JB		 2023 break;
2024 default:
84f44ce7 2025 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2026 return -EINVAL;
2027 }
2028
2029 intel_fb = to_intel_framebuffer(fb);
2030 obj = intel_fb->obj;
2031
2032 reg = DSPCNTR(plane);
2033 dspcntr = I915_READ(reg);
2034 /* Mask out pixel format bits in case we change it */
2035 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2036 switch (fb->pixel_format) {
2037 case DRM_FORMAT_C8:
17638cd6
JB		 2038 dspcntr |= DISPPLANE_8BPP;
2039 break;
57779d06
VS		 2040 case DRM_FORMAT_RGB565:
2041 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2042 break;
57779d06
VS		 2043 case DRM_FORMAT_XRGB8888:
2044 case DRM_FORMAT_ARGB8888:
2045 dspcntr |= DISPPLANE_BGRX888;
2046 break;
2047 case DRM_FORMAT_XBGR8888:
2048 case DRM_FORMAT_ABGR8888:
2049 dspcntr |= DISPPLANE_RGBX888;
2050 break;
2051 case DRM_FORMAT_XRGB2101010:
2052 case DRM_FORMAT_ARGB2101010:
2053 dspcntr |= DISPPLANE_BGRX101010;
2054 break;
2055 case DRM_FORMAT_XBGR2101010:
2056 case DRM_FORMAT_ABGR2101010:
2057 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2058 break;
2059 default:
baba133a 2060 BUG();
17638cd6
JB		 2061 }
2062
2063 if (obj->tiling_mode != I915_TILING_NONE)
2064 dspcntr |= DISPPLANE_TILED;
2065 else
2066 dspcntr &= ~DISPPLANE_TILED;
2067
2068 /* must disable */
2069 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2070
2071 I915_WRITE(reg, dspcntr);
2072
e506a0c6 2073 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2074 intel_crtc->dspaddr_offset =
bc752862
CW		 2075 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2076 fb->bits_per_pixel / 8,
2077 fb->pitches[0]);
c2c75131 2078 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2079
e506a0c6
DV		 2080 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2081 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2082 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2083 I915_MODIFY_DISPBASE(DSPSURF(plane),
2084 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2085 if (IS_HASWELL(dev)) {
2086 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2087 } else {
2088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089 I915_WRITE(DSPLINOFF(plane), linear_offset);
2090 }
17638cd6
JB		 2091 POSTING_READ(reg);
2092
2093 return 0;
2094}
2095
2096/* Assume fb object is pinned & idle & fenced and just update base pointers */
2097static int
2098intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2099 int x, int y, enum mode_set_atomic state)
2100{
2101 struct drm_device *dev = crtc->dev;
2102 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2103
6b8e6ed0
CW		 2104 if (dev_priv->display.disable_fbc)
2105 dev_priv->display.disable_fbc(dev);
3dec0095 2106 intel_increase_pllclock(crtc);
81255565 2107
6b8e6ed0 2108 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2109}
2110
96a02917
VS		 2111void intel_display_handle_reset(struct drm_device *dev)
2112{
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct drm_crtc *crtc;
2115
2116 /*
2117 * Flips in the rings have been nuked by the reset,
2118 * so complete all pending flips so that user space
2119 * will get its events and not get stuck.
2120 *
2121 * Also update the base address of all primary
2122 * planes to the the last fb to make sure we're
2123 * showing the correct fb after a reset.
2124 *
2125 * Need to make two loops over the crtcs so that we
2126 * don't try to grab a crtc mutex before the
2127 * pending_flip_queue really got woken up.
2128 */
2129
2130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132 enum plane plane = intel_crtc->plane;
2133
2134 intel_prepare_page_flip(dev, plane);
2135 intel_finish_page_flip_plane(dev, plane);
2136 }
2137
2138 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140
2141 mutex_lock(&crtc->mutex);
2142 if (intel_crtc->active)
2143 dev_priv->display.update_plane(crtc, crtc->fb,
2144 crtc->x, crtc->y);
2145 mutex_unlock(&crtc->mutex);
2146 }
2147}
2148
14667a4b
CW		 2149static int
2150intel_finish_fb(struct drm_framebuffer *old_fb)
2151{
2152 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2153 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2154 bool was_interruptible = dev_priv->mm.interruptible;
2155 int ret;
2156
14667a4b
CW		 2157 /* Big Hammer, we also need to ensure that any pending
2158 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2159 * current scanout is retired before unpinning the old
2160 * framebuffer.
2161 *
2162 * This should only fail upon a hung GPU, in which case we
2163 * can safely continue.
2164 */
2165 dev_priv->mm.interruptible = false;
2166 ret = i915_gem_object_finish_gpu(obj);
2167 dev_priv->mm.interruptible = was_interruptible;
2168
2169 return ret;
2170}
2171
198598d0
VS		 2172static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_master_private *master_priv;
2176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2177
2178 if (!dev->primary->master)
2179 return;
2180
2181 master_priv = dev->primary->master->driver_priv;
2182 if (!master_priv->sarea_priv)
2183 return;
2184
2185 switch (intel_crtc->pipe) {
2186 case 0:
2187 master_priv->sarea_priv->pipeA_x = x;
2188 master_priv->sarea_priv->pipeA_y = y;
2189 break;
2190 case 1:
2191 master_priv->sarea_priv->pipeB_x = x;
2192 master_priv->sarea_priv->pipeB_y = y;
2193 break;
2194 default:
2195 break;
2196 }
2197}
2198
5c3b82e2 2199static int
3c4fdcfb 2200intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2201 struct drm_framebuffer *fb)
79e53945
JB		 2202{
2203 struct drm_device *dev = crtc->dev;
6b8e6ed0 2204 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2206 struct drm_framebuffer *old_fb;
5c3b82e2 2207 int ret;
79e53945
JB		 2208
2209 /* no fb bound */
94352cf9 2210 if (!fb) {
a5071c2f 2211 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2212 return 0;
2213 }
2214
7eb552ae 2215 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2216 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2217 plane_name(intel_crtc->plane),
2218 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2219 return -EINVAL;
79e53945
JB		 2220 }
2221
5c3b82e2 2222 mutex_lock(&dev->struct_mutex);
265db958 2223 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2224 to_intel_framebuffer(fb)->obj,
919926ae 2225 NULL);
5c3b82e2
CW		 2226 if (ret != 0) {
2227 mutex_unlock(&dev->struct_mutex);
a5071c2f 2228 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2229 return ret;
2230 }
79e53945 2231
94352cf9 2232 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2233 if (ret) {
94352cf9 2234 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2235 mutex_unlock(&dev->struct_mutex);
a5071c2f 2236 DRM_ERROR("failed to update base address\n");
4e6cfefc 2237 return ret;
79e53945 2238 }
3c4fdcfb 2239
94352cf9
DV		 2240 old_fb = crtc->fb;
2241 crtc->fb = fb;
6c4c86f5
DV		 2242 crtc->x = x;
2243 crtc->y = y;
94352cf9 2244
b7f1de28 2245 if (old_fb) {
d7697eea
DV		 2246 if (intel_crtc->active && old_fb != fb)
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2249 }
652c393a 2250
6b8e6ed0 2251 intel_update_fbc(dev);
5c3b82e2 2252 mutex_unlock(&dev->struct_mutex);
79e53945 2253
198598d0 2254 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2255
2256 return 0;
79e53945
JB		 2257}
2258
5e84e1a4
ZW		 2259static void intel_fdi_normal_train(struct drm_crtc *crtc)
2260{
2261 struct drm_device *dev = crtc->dev;
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2264 int pipe = intel_crtc->pipe;
2265 u32 reg, temp;
2266
2267 /* enable normal train */
2268 reg = FDI_TX_CTL(pipe);
2269 temp = I915_READ(reg);
61e499bf 2270 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2271 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2272 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2273 } else {
2274 temp &= ~FDI_LINK_TRAIN_NONE;
2275 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2276 }
5e84e1a4
ZW		 2277 I915_WRITE(reg, temp);
2278
2279 reg = FDI_RX_CTL(pipe);
2280 temp = I915_READ(reg);
2281 if (HAS_PCH_CPT(dev)) {
2282 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2283 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2284 } else {
2285 temp &= ~FDI_LINK_TRAIN_NONE;
2286 temp |= FDI_LINK_TRAIN_NONE;
2287 }
2288 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2289
2290 /* wait one idle pattern time */
2291 POSTING_READ(reg);
2292 udelay(1000);
357555c0
JB		 2293
2294 /* IVB wants error correction enabled */
2295 if (IS_IVYBRIDGE(dev))
2296 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2297 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2298}
2299
1e833f40
DV		 2300static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2301{
2302 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2303}
2304
01a415fd
DV		 2305static void ivb_modeset_global_resources(struct drm_device *dev)
2306{
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_crtc *pipe_B_crtc =
2309 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2310 struct intel_crtc *pipe_C_crtc =
2311 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2312 uint32_t temp;
2313
1e833f40
DV		 2314 /*
2315 * When everything is off disable fdi C so that we could enable fdi B
2316 * with all lanes. Note that we don't care about enabled pipes without
2317 * an enabled pch encoder.
2318 */
2319 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2320 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2321 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2322 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2323
2324 temp = I915_READ(SOUTH_CHICKEN1);
2325 temp &= ~FDI_BC_BIFURCATION_SELECT;
2326 DRM_DEBUG_KMS("disabling fdi C rx\n");
2327 I915_WRITE(SOUTH_CHICKEN1, temp);
2328 }
2329}
2330
8db9d77b
ZW		 2331/* The FDI link training functions for ILK/Ibexpeak. */
2332static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2333{
2334 struct drm_device *dev = crtc->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2337 int pipe = intel_crtc->pipe;
0fc932b8 2338 int plane = intel_crtc->plane;
5eddb70b 2339 u32 reg, temp, tries;
8db9d77b 2340
0fc932b8
JB		 2341 /* FDI needs bits from pipe & plane first */
2342 assert_pipe_enabled(dev_priv, pipe);
2343 assert_plane_enabled(dev_priv, plane);
2344
e1a44743
AJ		 2345 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2346 for train result */
5eddb70b
CW		 2347 reg = FDI_RX_IMR(pipe);
2348 temp = I915_READ(reg);
e1a44743
AJ		 2349 temp &= ~FDI_RX_SYMBOL_LOCK;
2350 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2351 I915_WRITE(reg, temp);
2352 I915_READ(reg);
e1a44743
AJ		 2353 udelay(150);
2354
8db9d77b 2355 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
627eb5a3
DV		 2358 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2359 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2362 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2363
5eddb70b
CW		 2364 reg = FDI_RX_CTL(pipe);
2365 temp = I915_READ(reg);
8db9d77b
ZW		 2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2368 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2369
2370 POSTING_READ(reg);
8db9d77b
ZW		 2371 udelay(150);
2372
5b2adf89 2373 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2374 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2375 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2376 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2377
5eddb70b 2378 reg = FDI_RX_IIR(pipe);
e1a44743 2379 for (tries = 0; tries < 5; tries++) {
5eddb70b 2380 temp = I915_READ(reg);
8db9d77b
ZW		 2381 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2382
2383 if ((temp & FDI_RX_BIT_LOCK)) {
2384 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2385 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2386 break;
2387 }
8db9d77b 2388 }
e1a44743 2389 if (tries == 5)
5eddb70b 2390 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2391
2392 /* Train 2 */
5eddb70b
CW		 2393 reg = FDI_TX_CTL(pipe);
2394 temp = I915_READ(reg);
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2397 I915_WRITE(reg, temp);
8db9d77b 2398
5eddb70b
CW		 2399 reg = FDI_RX_CTL(pipe);
2400 temp = I915_READ(reg);
8db9d77b
ZW		 2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2403 I915_WRITE(reg, temp);
8db9d77b 2404
5eddb70b
CW		 2405 POSTING_READ(reg);
2406 udelay(150);
8db9d77b 2407
5eddb70b 2408 reg = FDI_RX_IIR(pipe);
e1a44743 2409 for (tries = 0; tries < 5; tries++) {
5eddb70b 2410 temp = I915_READ(reg);
8db9d77b
ZW		 2411 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412
2413 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2414 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2415 DRM_DEBUG_KMS("FDI train 2 done.\n");
2416 break;
2417 }
8db9d77b 2418 }
e1a44743 2419 if (tries == 5)
5eddb70b 2420 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2421
2422 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2423
8db9d77b
ZW		 2424}
2425
0206e353 2426static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2427 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2428 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2429 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2430 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2431};
2432
2433/* The FDI link training functions for SNB/Cougarpoint. */
2434static void gen6_fdi_link_train(struct drm_crtc *crtc)
2435{
2436 struct drm_device *dev = crtc->dev;
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2439 int pipe = intel_crtc->pipe;
fa37d39e 2440 u32 reg, temp, i, retry;
8db9d77b 2441
e1a44743
AJ		 2442 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2443 for train result */
5eddb70b
CW		 2444 reg = FDI_RX_IMR(pipe);
2445 temp = I915_READ(reg);
e1a44743
AJ		 2446 temp &= ~FDI_RX_SYMBOL_LOCK;
2447 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2448 I915_WRITE(reg, temp);
2449
2450 POSTING_READ(reg);
e1a44743
AJ		 2451 udelay(150);
2452
8db9d77b 2453 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
627eb5a3
DV		 2456 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2457 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2458 temp &= ~FDI_LINK_TRAIN_NONE;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1;
2460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2461 /* SNB-B */
2462 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2464
d74cf324
DV		 2465 I915_WRITE(FDI_RX_MISC(pipe),
2466 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2467
5eddb70b
CW		 2468 reg = FDI_RX_CTL(pipe);
2469 temp = I915_READ(reg);
8db9d77b
ZW		 2470 if (HAS_PCH_CPT(dev)) {
2471 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2472 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2473 } else {
2474 temp &= ~FDI_LINK_TRAIN_NONE;
2475 temp |= FDI_LINK_TRAIN_PATTERN_1;
2476 }
5eddb70b
CW		 2477 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2478
2479 POSTING_READ(reg);
8db9d77b
ZW		 2480 udelay(150);
2481
0206e353 2482 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2483 reg = FDI_TX_CTL(pipe);
2484 temp = I915_READ(reg);
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2487 I915_WRITE(reg, temp);
2488
2489 POSTING_READ(reg);
8db9d77b
ZW		 2490 udelay(500);
2491
fa37d39e
SP		 2492 for (retry = 0; retry < 5; retry++) {
2493 reg = FDI_RX_IIR(pipe);
2494 temp = I915_READ(reg);
2495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2496 if (temp & FDI_RX_BIT_LOCK) {
2497 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2498 DRM_DEBUG_KMS("FDI train 1 done.\n");
2499 break;
2500 }
2501 udelay(50);
8db9d77b 2502 }
fa37d39e
SP		 2503 if (retry < 5)
2504 break;
8db9d77b
ZW		 2505 }
2506 if (i == 4)
5eddb70b 2507 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2508
2509 /* Train 2 */
5eddb70b
CW		 2510 reg = FDI_TX_CTL(pipe);
2511 temp = I915_READ(reg);
8db9d77b
ZW		 2512 temp &= ~FDI_LINK_TRAIN_NONE;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2;
2514 if (IS_GEN6(dev)) {
2515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516 /* SNB-B */
2517 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2518 }
5eddb70b 2519 I915_WRITE(reg, temp);
8db9d77b 2520
5eddb70b
CW		 2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
8db9d77b
ZW		 2523 if (HAS_PCH_CPT(dev)) {
2524 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2525 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2526 } else {
2527 temp &= ~FDI_LINK_TRAIN_NONE;
2528 temp |= FDI_LINK_TRAIN_PATTERN_2;
2529 }
5eddb70b
CW		 2530 I915_WRITE(reg, temp);
2531
2532 POSTING_READ(reg);
8db9d77b
ZW		 2533 udelay(150);
2534
0206e353 2535 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2536 reg = FDI_TX_CTL(pipe);
2537 temp = I915_READ(reg);
8db9d77b
ZW		 2538 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2540 I915_WRITE(reg, temp);
2541
2542 POSTING_READ(reg);
8db9d77b
ZW		 2543 udelay(500);
2544
fa37d39e
SP		 2545 for (retry = 0; retry < 5; retry++) {
2546 reg = FDI_RX_IIR(pipe);
2547 temp = I915_READ(reg);
2548 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2549 if (temp & FDI_RX_SYMBOL_LOCK) {
2550 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2551 DRM_DEBUG_KMS("FDI train 2 done.\n");
2552 break;
2553 }
2554 udelay(50);
8db9d77b 2555 }
fa37d39e
SP		 2556 if (retry < 5)
2557 break;
8db9d77b
ZW		 2558 }
2559 if (i == 4)
5eddb70b 2560 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2561
2562 DRM_DEBUG_KMS("FDI train done.\n");
2563}
2564
357555c0
JB		 2565/* Manual link training for Ivy Bridge A0 parts */
2566static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2567{
2568 struct drm_device *dev = crtc->dev;
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2571 int pipe = intel_crtc->pipe;
2572 u32 reg, temp, i;
2573
2574 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2575 for train result */
2576 reg = FDI_RX_IMR(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_RX_SYMBOL_LOCK;
2579 temp &= ~FDI_RX_BIT_LOCK;
2580 I915_WRITE(reg, temp);
2581
2582 POSTING_READ(reg);
2583 udelay(150);
2584
01a415fd
DV		 2585 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2586 I915_READ(FDI_RX_IIR(pipe)));
2587
357555c0
JB		 2588 /* enable CPU FDI TX and PCH FDI RX */
2589 reg = FDI_TX_CTL(pipe);
2590 temp = I915_READ(reg);
627eb5a3
DV		 2591 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2592 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2593 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2597 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2598 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2599
d74cf324
DV		 2600 I915_WRITE(FDI_RX_MISC(pipe),
2601 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2602
357555c0
JB		 2603 reg = FDI_RX_CTL(pipe);
2604 temp = I915_READ(reg);
2605 temp &= ~FDI_LINK_TRAIN_AUTO;
2606 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2607 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2608 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2609 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2610
2611 POSTING_READ(reg);
2612 udelay(150);
2613
0206e353 2614 for (i = 0; i < 4; i++) {
357555c0
JB		 2615 reg = FDI_TX_CTL(pipe);
2616 temp = I915_READ(reg);
2617 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2618 temp |= snb_b_fdi_train_param[i];
2619 I915_WRITE(reg, temp);
2620
2621 POSTING_READ(reg);
2622 udelay(500);
2623
2624 reg = FDI_RX_IIR(pipe);
2625 temp = I915_READ(reg);
2626 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2627
2628 if (temp & FDI_RX_BIT_LOCK ||
2629 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2630 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2631 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2632 break;
2633 }
2634 }
2635 if (i == 4)
2636 DRM_ERROR("FDI train 1 fail!\n");
2637
2638 /* Train 2 */
2639 reg = FDI_TX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2643 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2645 I915_WRITE(reg, temp);
2646
2647 reg = FDI_RX_CTL(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 I915_WRITE(reg, temp);
2652
2653 POSTING_READ(reg);
2654 udelay(150);
2655
0206e353 2656 for (i = 0; i < 4; i++) {
357555c0
JB		 2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= snb_b_fdi_train_param[i];
2661 I915_WRITE(reg, temp);
2662
2663 POSTING_READ(reg);
2664 udelay(500);
2665
2666 reg = FDI_RX_IIR(pipe);
2667 temp = I915_READ(reg);
2668 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2669
2670 if (temp & FDI_RX_SYMBOL_LOCK) {
2671 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2672 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2673 break;
2674 }
2675 }
2676 if (i == 4)
2677 DRM_ERROR("FDI train 2 fail!\n");
2678
2679 DRM_DEBUG_KMS("FDI train done.\n");
2680}
2681
88cefb6c 2682static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2683{
88cefb6c 2684 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2685 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2686 int pipe = intel_crtc->pipe;
5eddb70b 2687 u32 reg, temp;
79e53945 2688
c64e311e 2689
c98e9dcf 2690 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2691 reg = FDI_RX_CTL(pipe);
2692 temp = I915_READ(reg);
627eb5a3
DV		 2693 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2694 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2695 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2696 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2697
2698 POSTING_READ(reg);
c98e9dcf
JB		 2699 udelay(200);
2700
2701 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2702 temp = I915_READ(reg);
2703 I915_WRITE(reg, temp | FDI_PCDCLK);
2704
2705 POSTING_READ(reg);
c98e9dcf
JB		 2706 udelay(200);
2707
20749730
PZ		 2708 /* Enable CPU FDI TX PLL, always on for Ironlake */
2709 reg = FDI_TX_CTL(pipe);
2710 temp = I915_READ(reg);
2711 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2712 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2713
20749730
PZ		 2714 POSTING_READ(reg);
2715 udelay(100);
6be4a607 2716 }
0e23b99d
JB		 2717}
2718
88cefb6c
DV		 2719static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2720{
2721 struct drm_device *dev = intel_crtc->base.dev;
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 int pipe = intel_crtc->pipe;
2724 u32 reg, temp;
2725
2726 /* Switch from PCDclk to Rawclk */
2727 reg = FDI_RX_CTL(pipe);
2728 temp = I915_READ(reg);
2729 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2730
2731 /* Disable CPU FDI TX PLL */
2732 reg = FDI_TX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2735
2736 POSTING_READ(reg);
2737 udelay(100);
2738
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2742
2743 /* Wait for the clocks to turn off. */
2744 POSTING_READ(reg);
2745 udelay(100);
2746}
2747
0fc932b8
JB		 2748static void ironlake_fdi_disable(struct drm_crtc *crtc)
2749{
2750 struct drm_device *dev = crtc->dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2753 int pipe = intel_crtc->pipe;
2754 u32 reg, temp;
2755
2756 /* disable CPU FDI tx and PCH FDI rx */
2757 reg = FDI_TX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2760 POSTING_READ(reg);
2761
2762 reg = FDI_RX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~(0x7 << 16);
dfd07d72 2765 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2766 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2767
2768 POSTING_READ(reg);
2769 udelay(100);
2770
2771 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2772 if (HAS_PCH_IBX(dev)) {
2773 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2774 }
0fc932b8
JB		 2775
2776 /* still set train pattern 1 */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_NONE;
2780 temp |= FDI_LINK_TRAIN_PATTERN_1;
2781 I915_WRITE(reg, temp);
2782
2783 reg = FDI_RX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if (HAS_PCH_CPT(dev)) {
2786 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2787 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2788 } else {
2789 temp &= ~FDI_LINK_TRAIN_NONE;
2790 temp |= FDI_LINK_TRAIN_PATTERN_1;
2791 }
2792 /* BPC in FDI rx is consistent with that in PIPECONF */
2793 temp &= ~(0x07 << 16);
dfd07d72 2794 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2795 I915_WRITE(reg, temp);
2796
2797 POSTING_READ(reg);
2798 udelay(100);
2799}
2800
5bb61643
CW		 2801static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2802{
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2806 unsigned long flags;
2807 bool pending;
2808
10d83730
VS		 2809 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2810 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2811 return false;
2812
2813 spin_lock_irqsave(&dev->event_lock, flags);
2814 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2815 spin_unlock_irqrestore(&dev->event_lock, flags);
2816
2817 return pending;
2818}
2819
e6c3a2a6
CW		 2820static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2821{
0f91128d 2822 struct drm_device *dev = crtc->dev;
5bb61643 2823 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2824
2825 if (crtc->fb == NULL)
2826 return;
2827
2c10d571
DV		 2828 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2829
5bb61643
CW		 2830 wait_event(dev_priv->pending_flip_queue,
2831 !intel_crtc_has_pending_flip(crtc));
2832
0f91128d
CW		 2833 mutex_lock(&dev->struct_mutex);
2834 intel_finish_fb(crtc->fb);
2835 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2836}
2837
e615efe4
ED		 2838/* Program iCLKIP clock to the desired frequency */
2839static void lpt_program_iclkip(struct drm_crtc *crtc)
2840{
2841 struct drm_device *dev = crtc->dev;
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2844 u32 temp;
2845
09153000
DV		 2846 mutex_lock(&dev_priv->dpio_lock);
2847
e615efe4
ED		 2848 /* It is necessary to ungate the pixclk gate prior to programming
2849 * the divisors, and gate it back when it is done.
2850 */
2851 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2852
2853 /* Disable SSCCTL */
2854 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2855 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2856 SBI_SSCCTL_DISABLE,
2857 SBI_ICLK);
e615efe4
ED		 2858
2859 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2860 if (crtc->mode.clock == 20000) {
2861 auxdiv = 1;
2862 divsel = 0x41;
2863 phaseinc = 0x20;
2864 } else {
2865 /* The iCLK virtual clock root frequency is in MHz,
2866 * but the crtc->mode.clock in in KHz. To get the divisors,
2867 * it is necessary to divide one by another, so we
2868 * convert the virtual clock precision to KHz here for higher
2869 * precision.
2870 */
2871 u32 iclk_virtual_root_freq = 172800 * 1000;
2872 u32 iclk_pi_range = 64;
2873 u32 desired_divisor, msb_divisor_value, pi_value;
2874
2875 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2876 msb_divisor_value = desired_divisor / iclk_pi_range;
2877 pi_value = desired_divisor % iclk_pi_range;
2878
2879 auxdiv = 0;
2880 divsel = msb_divisor_value - 2;
2881 phaseinc = pi_value;
2882 }
2883
2884 /* This should not happen with any sane values */
2885 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2886 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2887 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2888 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2889
2890 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2891 crtc->mode.clock,
2892 auxdiv,
2893 divsel,
2894 phasedir,
2895 phaseinc);
2896
2897 /* Program SSCDIVINTPHASE6 */
988d6ee8 2898 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2899 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2900 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2901 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2902 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2903 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2904 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2905 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2906
2907 /* Program SSCAUXDIV */
988d6ee8 2908 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2909 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2910 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2911 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2912
2913 /* Enable modulator and associated divider */
988d6ee8 2914 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2915 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2916 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2917
2918 /* Wait for initialization time */
2919 udelay(24);
2920
2921 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2922
2923 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2924}
2925
275f01b2
DV		 2926static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2927 enum pipe pch_transcoder)
2928{
2929 struct drm_device *dev = crtc->base.dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2932
2933 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2934 I915_READ(HTOTAL(cpu_transcoder)));
2935 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2936 I915_READ(HBLANK(cpu_transcoder)));
2937 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2938 I915_READ(HSYNC(cpu_transcoder)));
2939
2940 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2941 I915_READ(VTOTAL(cpu_transcoder)));
2942 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2943 I915_READ(VBLANK(cpu_transcoder)));
2944 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2945 I915_READ(VSYNC(cpu_transcoder)));
2946 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2947 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2948}
2949
f67a559d
JB		 2950/*
2951 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2956 * - transcoder
2957 */
2958static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
ee7b9f93 2964 u32 reg, temp;
2c07245f 2965
ab9412ba 2966 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2967
cd986abb
DV		 2968 /* Write the TU size bits before fdi link training, so that error
2969 * detection works. */
2970 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2971 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2972
c98e9dcf 2973 /* For PCH output, training FDI link */
674cf967 2974 dev_priv->display.fdi_link_train(crtc);
2c07245f 2975
572deb37
DV		 2976 /* XXX: pch pll's can be enabled any time before we enable the PCH
2977 * transcoder, and we actually should do this to not upset any PCH
2978 * transcoder that already use the clock when we share it.
2979 *
e72f9fbf
DV		 2980 * Note that enable_shared_dpll tries to do the right thing, but
2981 * get_shared_dpll unconditionally resets the pll - we need that to have
2982 * the right LVDS enable sequence. */
2983 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2984
303b81e0 2985 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2986 u32 sel;
4b645f14 2987
c98e9dcf 2988 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2989 temp |= TRANS_DPLL_ENABLE(pipe);
2990 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2991 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2992 temp |= sel;
2993 else
2994 temp &= ~sel;
c98e9dcf 2995 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2996 }
5eddb70b 2997
d9b6cb56
JB		 2998 /* set transcoder timing, panel must allow it */
2999 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3000 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3001
303b81e0 3002 intel_fdi_normal_train(crtc);
5e84e1a4 3003
c98e9dcf
JB		 3004 /* For PCH DP, enable TRANS_DP_CTL */
3005 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3006 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3007 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3008 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3009 reg = TRANS_DP_CTL(pipe);
3010 temp = I915_READ(reg);
3011 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3012 TRANS_DP_SYNC_MASK |
3013 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3014 temp |= (TRANS_DP_OUTPUT_ENABLE |
3015 TRANS_DP_ENH_FRAMING);
9325c9f0 3016 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3017
3018 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3019 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3020 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3021 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3022
3023 switch (intel_trans_dp_port_sel(crtc)) {
3024 case PCH_DP_B:
5eddb70b 3025 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3026 break;
3027 case PCH_DP_C:
5eddb70b 3028 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3029 break;
3030 case PCH_DP_D:
5eddb70b 3031 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3032 break;
3033 default:
e95d41e1 3034 BUG();
32f9d658 3035 }
2c07245f 3036
5eddb70b 3037 I915_WRITE(reg, temp);
6be4a607 3038 }
b52eb4dc 3039
b8a4f404 3040 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3041}
3042
1507e5bd
PZ		 3043static void lpt_pch_enable(struct drm_crtc *crtc)
3044{
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3048 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3049
ab9412ba 3050 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3051
8c52b5e8 3052 lpt_program_iclkip(crtc);
1507e5bd 3053
0540e488 3054 /* Set transcoder timing. */
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3056
937bb610 3057 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3058}
3059
e2b78267 3060static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3061{
e2b78267 3062 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3063
3064 if (pll == NULL)
3065 return;
3066
3067 if (pll->refcount == 0) {
3068 WARN(1, "bad PCH PLL refcount\n");
3069 return;
3070 }
3071
f4a091c7
DV		 3072 if (--pll->refcount == 0) {
3073 WARN_ON(pll->on);
3074 WARN_ON(pll->active);
3075 }
3076
a43f6e0f 3077 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3078}
3079
e2b78267 3080static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
ee7b9f93 3081{
e2b78267
DV		 3082 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3083 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3084 enum intel_dpll_id i;
ee7b9f93 3085
ee7b9f93 3086 if (pll) {
cdbd2316 3087 DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
e2b78267
DV		 3088 crtc->base.base.id, pll->pll_reg);
3089 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3090 }
3091
98b6bd99
DV		 3092 if (HAS_PCH_IBX(dev_priv->dev)) {
3093 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3094 i = crtc->pipe;
e72f9fbf 3095 pll = &dev_priv->shared_dplls[i];
98b6bd99
DV		 3096
3097 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
e2b78267 3098 crtc->base.base.id, pll->pll_reg);
98b6bd99
DV		 3099
3100 goto found;
3101 }
3102
e72f9fbf
DV		 3103 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3104 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3105
3106 /* Only want to check enabled timings first */
3107 if (pll->refcount == 0)
3108 continue;
3109
3110 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3111 fp == I915_READ(pll->fp0_reg)) {
3112 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
e2b78267 3113 crtc->base.base.id,
ee7b9f93
JB		 3114 pll->pll_reg, pll->refcount, pll->active);
3115
3116 goto found;
3117 }
3118 }
3119
3120 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3121 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3122 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3123 if (pll->refcount == 0) {
3124 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
e2b78267 3125 crtc->base.base.id, pll->pll_reg);
ee7b9f93
JB		 3126 goto found;
3127 }
3128 }
3129
3130 return NULL;
3131
3132found:
a43f6e0f 3133 crtc->config.shared_dpll = i;
e2b78267 3134 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(crtc->pipe));
cdbd2316
DV		 3135 if (pll->active == 0) {
3136 DRM_DEBUG_DRIVER("setting up pll %d\n", i);
3137 WARN_ON(pll->on);
e72f9fbf 3138 assert_shared_dpll_disabled(dev_priv, pll, NULL);
ee7b9f93 3139
cdbd2316
DV		 3140 /* Wait for the clocks to stabilize before rewriting the regs */
3141 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3142 POSTING_READ(pll->pll_reg);
3143 udelay(150);
3144
3145 I915_WRITE(pll->fp0_reg, fp);
3146 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3147 }
3148 pll->refcount++;
e04c7350 3149
ee7b9f93
JB		 3150 return pll;
3151}
3152
a1520318 3153static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3154{
3155 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3156 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3157 u32 temp;
3158
3159 temp = I915_READ(dslreg);
3160 udelay(500);
3161 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3162 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3163 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3164 }
3165}
3166
b074cec8
JB		 3167static void ironlake_pfit_enable(struct intel_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->base.dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 int pipe = crtc->pipe;
3172
0ef37f3f 3173 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3174 /* Force use of hard-coded filter coefficients
3175 * as some pre-programmed values are broken,
3176 * e.g. x201.
3177 */
3178 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3179 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3180 PF_PIPE_SEL_IVB(pipe));
3181 else
3182 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3183 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3184 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3185 }
3186}
3187
bb53d4ae
VS		 3188static void intel_enable_planes(struct drm_crtc *crtc)
3189{
3190 struct drm_device *dev = crtc->dev;
3191 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3192 struct intel_plane *intel_plane;
3193
3194 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3195 if (intel_plane->pipe == pipe)
3196 intel_plane_restore(&intel_plane->base);
3197}
3198
3199static void intel_disable_planes(struct drm_crtc *crtc)
3200{
3201 struct drm_device *dev = crtc->dev;
3202 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3203 struct intel_plane *intel_plane;
3204
3205 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3206 if (intel_plane->pipe == pipe)
3207 intel_plane_disable(&intel_plane->base);
3208}
3209
f67a559d
JB		 3210static void ironlake_crtc_enable(struct drm_crtc *crtc)
3211{
3212 struct drm_device *dev = crtc->dev;
3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3215 struct intel_encoder *encoder;
f67a559d
JB		 3216 int pipe = intel_crtc->pipe;
3217 int plane = intel_crtc->plane;
3218 u32 temp;
f67a559d 3219
08a48469
DV		 3220 WARN_ON(!crtc->enabled);
3221
f67a559d
JB		 3222 if (intel_crtc->active)
3223 return;
3224
3225 intel_crtc->active = true;
8664281b
PZ		 3226
3227 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3228 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3229
f67a559d
JB		 3230 intel_update_watermarks(dev);
3231
3232 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3233 temp = I915_READ(PCH_LVDS);
3234 if ((temp & LVDS_PORT_EN) == 0)
3235 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3236 }
3237
f67a559d 3238
5bfe2ac0 3239 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3240 /* Note: FDI PLL enabling _must_ be done before we enable the
3241 * cpu pipes, hence this is separate from all the other fdi/pch
3242 * enabling. */
88cefb6c 3243 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3244 } else {
3245 assert_fdi_tx_disabled(dev_priv, pipe);
3246 assert_fdi_rx_disabled(dev_priv, pipe);
3247 }
f67a559d 3248
bf49ec8c
DV		 3249 for_each_encoder_on_crtc(dev, crtc, encoder)
3250 if (encoder->pre_enable)
3251 encoder->pre_enable(encoder);
f67a559d
JB		 3252
3253 /* Enable panel fitting for LVDS */
b074cec8 3254 ironlake_pfit_enable(intel_crtc);
f67a559d 3255
9c54c0dd
JB		 3256 /*
3257 * On ILK+ LUT must be loaded before the pipe is running but with
3258 * clocks enabled
3259 */
3260 intel_crtc_load_lut(crtc);
3261
5bfe2ac0
DV		 3262 intel_enable_pipe(dev_priv, pipe,
3263 intel_crtc->config.has_pch_encoder);
f67a559d 3264 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3265 intel_enable_planes(crtc);
5c38d48c 3266 intel_crtc_update_cursor(crtc, true);
f67a559d 3267
5bfe2ac0 3268 if (intel_crtc->config.has_pch_encoder)
f67a559d 3269 ironlake_pch_enable(crtc);
c98e9dcf 3270
d1ebd816 3271 mutex_lock(&dev->struct_mutex);
bed4a673 3272 intel_update_fbc(dev);
d1ebd816
BW		 3273 mutex_unlock(&dev->struct_mutex);
3274
fa5c73b1
DV		 3275 for_each_encoder_on_crtc(dev, crtc, encoder)
3276 encoder->enable(encoder);
61b77ddd
DV		 3277
3278 if (HAS_PCH_CPT(dev))
a1520318 3279 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3280
3281 /*
3282 * There seems to be a race in PCH platform hw (at least on some
3283 * outputs) where an enabled pipe still completes any pageflip right
3284 * away (as if the pipe is off) instead of waiting for vblank. As soon
3285 * as the first vblank happend, everything works as expected. Hence just
3286 * wait for one vblank before returning to avoid strange things
3287 * happening.
3288 */
3289 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3290}
3291
42db64ef
PZ		 3292/* IPS only exists on ULT machines and is tied to pipe A. */
3293static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3294{
3295 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3296}
3297
3298static void hsw_enable_ips(struct intel_crtc *crtc)
3299{
3300 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3301
3302 if (!crtc->config.ips_enabled)
3303 return;
3304
3305 /* We can only enable IPS after we enable a plane and wait for a vblank.
3306 * We guarantee that the plane is enabled by calling intel_enable_ips
3307 * only after intel_enable_plane. And intel_enable_plane already waits
3308 * for a vblank, so all we need to do here is to enable the IPS bit. */
3309 assert_plane_enabled(dev_priv, crtc->plane);
3310 I915_WRITE(IPS_CTL, IPS_ENABLE);
3311}
3312
3313static void hsw_disable_ips(struct intel_crtc *crtc)
3314{
3315 struct drm_device *dev = crtc->base.dev;
3316 struct drm_i915_private *dev_priv = dev->dev_private;
3317
3318 if (!crtc->config.ips_enabled)
3319 return;
3320
3321 assert_plane_enabled(dev_priv, crtc->plane);
3322 I915_WRITE(IPS_CTL, 0);
3323
3324 /* We need to wait for a vblank before we can disable the plane. */
3325 intel_wait_for_vblank(dev, crtc->pipe);
3326}
3327
4f771f10
PZ		 3328static void haswell_crtc_enable(struct drm_crtc *crtc)
3329{
3330 struct drm_device *dev = crtc->dev;
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333 struct intel_encoder *encoder;
3334 int pipe = intel_crtc->pipe;
3335 int plane = intel_crtc->plane;
4f771f10
PZ		 3336
3337 WARN_ON(!crtc->enabled);
3338
3339 if (intel_crtc->active)
3340 return;
3341
3342 intel_crtc->active = true;
8664281b
PZ		 3343
3344 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3345 if (intel_crtc->config.has_pch_encoder)
3346 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3347
4f771f10
PZ		 3348 intel_update_watermarks(dev);
3349
5bfe2ac0 3350 if (intel_crtc->config.has_pch_encoder)
04945641 3351 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3352
3353 for_each_encoder_on_crtc(dev, crtc, encoder)
3354 if (encoder->pre_enable)
3355 encoder->pre_enable(encoder);
3356
1f544388 3357 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3358
1f544388 3359 /* Enable panel fitting for eDP */
b074cec8 3360 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3361
3362 /*
3363 * On ILK+ LUT must be loaded before the pipe is running but with
3364 * clocks enabled
3365 */
3366 intel_crtc_load_lut(crtc);
3367
1f544388 3368 intel_ddi_set_pipe_settings(crtc);
8228c251 3369 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3370
5bfe2ac0
DV		 3371 intel_enable_pipe(dev_priv, pipe,
3372 intel_crtc->config.has_pch_encoder);
4f771f10 3373 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3374 intel_enable_planes(crtc);
5c38d48c 3375 intel_crtc_update_cursor(crtc, true);
4f771f10 3376
42db64ef
PZ		 3377 hsw_enable_ips(intel_crtc);
3378
5bfe2ac0 3379 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3380 lpt_pch_enable(crtc);
4f771f10
PZ		 3381
3382 mutex_lock(&dev->struct_mutex);
3383 intel_update_fbc(dev);
3384 mutex_unlock(&dev->struct_mutex);
3385
4f771f10
PZ		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->enable(encoder);
3388
4f771f10
PZ		 3389 /*
3390 * There seems to be a race in PCH platform hw (at least on some
3391 * outputs) where an enabled pipe still completes any pageflip right
3392 * away (as if the pipe is off) instead of waiting for vblank. As soon
3393 * as the first vblank happend, everything works as expected. Hence just
3394 * wait for one vblank before returning to avoid strange things
3395 * happening.
3396 */
3397 intel_wait_for_vblank(dev, intel_crtc->pipe);
3398}
3399
3f8dce3a
DV		 3400static void ironlake_pfit_disable(struct intel_crtc *crtc)
3401{
3402 struct drm_device *dev = crtc->base.dev;
3403 struct drm_i915_private *dev_priv = dev->dev_private;
3404 int pipe = crtc->pipe;
3405
3406 /* To avoid upsetting the power well on haswell only disable the pfit if
3407 * it's in use. The hw state code will make sure we get this right. */
3408 if (crtc->config.pch_pfit.size) {
3409 I915_WRITE(PF_CTL(pipe), 0);
3410 I915_WRITE(PF_WIN_POS(pipe), 0);
3411 I915_WRITE(PF_WIN_SZ(pipe), 0);
3412 }
3413}
3414
6be4a607
JB		 3415static void ironlake_crtc_disable(struct drm_crtc *crtc)
3416{
3417 struct drm_device *dev = crtc->dev;
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3420 struct intel_encoder *encoder;
6be4a607
JB		 3421 int pipe = intel_crtc->pipe;
3422 int plane = intel_crtc->plane;
5eddb70b 3423 u32 reg, temp;
b52eb4dc 3424
ef9c3aee 3425
f7abfe8b
CW		 3426 if (!intel_crtc->active)
3427 return;
3428
ea9d758d
DV		 3429 for_each_encoder_on_crtc(dev, crtc, encoder)
3430 encoder->disable(encoder);
3431
e6c3a2a6 3432 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3433 drm_vblank_off(dev, pipe);
913d8d11 3434
973d04f9
CW		 3435 if (dev_priv->cfb_plane == plane)
3436 intel_disable_fbc(dev);
2c07245f 3437
0d5b8c61 3438 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3439 intel_disable_planes(crtc);
0d5b8c61
VS		 3440 intel_disable_plane(dev_priv, plane, pipe);
3441
d925c59a
DV		 3442 if (intel_crtc->config.has_pch_encoder)
3443 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3444
b24e7179 3445 intel_disable_pipe(dev_priv, pipe);
32f9d658 3446
3f8dce3a 3447 ironlake_pfit_disable(intel_crtc);
2c07245f 3448
bf49ec8c
DV		 3449 for_each_encoder_on_crtc(dev, crtc, encoder)
3450 if (encoder->post_disable)
3451 encoder->post_disable(encoder);
2c07245f 3452
d925c59a
DV		 3453 if (intel_crtc->config.has_pch_encoder) {
3454 ironlake_fdi_disable(crtc);
249c0e64 3455
d925c59a
DV		 3456 ironlake_disable_pch_transcoder(dev_priv, pipe);
3457 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3458
d925c59a
DV		 3459 if (HAS_PCH_CPT(dev)) {
3460 /* disable TRANS_DP_CTL */
3461 reg = TRANS_DP_CTL(pipe);
3462 temp = I915_READ(reg);
3463 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3464 TRANS_DP_PORT_SEL_MASK);
3465 temp |= TRANS_DP_PORT_SEL_NONE;
3466 I915_WRITE(reg, temp);
3467
3468 /* disable DPLL_SEL */
3469 temp = I915_READ(PCH_DPLL_SEL);
11887397 3470 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3471 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3472 }
e3421a18 3473
d925c59a 3474 /* disable PCH DPLL */
e72f9fbf 3475 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3476
d925c59a
DV		 3477 ironlake_fdi_pll_disable(intel_crtc);
3478 }
6b383a7f 3479
f7abfe8b 3480 intel_crtc->active = false;
6b383a7f 3481 intel_update_watermarks(dev);
d1ebd816
BW		 3482
3483 mutex_lock(&dev->struct_mutex);
6b383a7f 3484 intel_update_fbc(dev);
d1ebd816 3485 mutex_unlock(&dev->struct_mutex);
6be4a607 3486}
1b3c7a47 3487
4f771f10 3488static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3489{
4f771f10
PZ		 3490 struct drm_device *dev = crtc->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3493 struct intel_encoder *encoder;
3494 int pipe = intel_crtc->pipe;
3495 int plane = intel_crtc->plane;
3b117c8f 3496 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3497
4f771f10
PZ		 3498 if (!intel_crtc->active)
3499 return;
3500
3501 for_each_encoder_on_crtc(dev, crtc, encoder)
3502 encoder->disable(encoder);
3503
3504 intel_crtc_wait_for_pending_flips(crtc);
3505 drm_vblank_off(dev, pipe);
4f771f10 3506
891348b2 3507 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3508 if (dev_priv->cfb_plane == plane)
3509 intel_disable_fbc(dev);
3510
42db64ef
PZ		 3511 hsw_disable_ips(intel_crtc);
3512
0d5b8c61 3513 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3514 intel_disable_planes(crtc);
891348b2
RV		 3515 intel_disable_plane(dev_priv, plane, pipe);
3516
8664281b
PZ		 3517 if (intel_crtc->config.has_pch_encoder)
3518 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3519 intel_disable_pipe(dev_priv, pipe);
3520
ad80a810 3521 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3522
3f8dce3a 3523 ironlake_pfit_disable(intel_crtc);
4f771f10 3524
1f544388 3525 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3526
3527 for_each_encoder_on_crtc(dev, crtc, encoder)
3528 if (encoder->post_disable)
3529 encoder->post_disable(encoder);
3530
88adfff1 3531 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3532 lpt_disable_pch_transcoder(dev_priv);
8664281b 3533 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3534 intel_ddi_fdi_disable(crtc);
83616634 3535 }
4f771f10
PZ		 3536
3537 intel_crtc->active = false;
3538 intel_update_watermarks(dev);
3539
3540 mutex_lock(&dev->struct_mutex);
3541 intel_update_fbc(dev);
3542 mutex_unlock(&dev->struct_mutex);
3543}
3544
ee7b9f93
JB		 3545static void ironlake_crtc_off(struct drm_crtc *crtc)
3546{
3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3548 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3549}
3550
6441ab5f
PZ		 3551static void haswell_crtc_off(struct drm_crtc *crtc)
3552{
3553 intel_ddi_put_crtc_pll(crtc);
3554}
3555
02e792fb
DV		 3556static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3557{
02e792fb 3558 if (!enable && intel_crtc->overlay) {
23f09ce3 3559 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3560 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3561
23f09ce3 3562 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3563 dev_priv->mm.interruptible = false;
3564 (void) intel_overlay_switch_off(intel_crtc->overlay);
3565 dev_priv->mm.interruptible = true;
23f09ce3 3566 mutex_unlock(&dev->struct_mutex);
02e792fb 3567 }
02e792fb 3568
5dcdbcb0
CW		 3569 /* Let userspace switch the overlay on again. In most cases userspace
3570 * has to recompute where to put it anyway.
3571 */
02e792fb
DV		 3572}
3573
61bc95c1
EE		 3574/**
3575 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3576 * cursor plane briefly if not already running after enabling the display
3577 * plane.
3578 * This workaround avoids occasional blank screens when self refresh is
3579 * enabled.
3580 */
3581static void
3582g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3583{
3584 u32 cntl = I915_READ(CURCNTR(pipe));
3585
3586 if ((cntl & CURSOR_MODE) == 0) {
3587 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3588
3589 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3590 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3591 intel_wait_for_vblank(dev_priv->dev, pipe);
3592 I915_WRITE(CURCNTR(pipe), cntl);
3593 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3594 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3595 }
3596}
3597
2dd24552
JB		 3598static void i9xx_pfit_enable(struct intel_crtc *crtc)
3599{
3600 struct drm_device *dev = crtc->base.dev;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 struct intel_crtc_config *pipe_config = &crtc->config;
3603
328d8e82 3604 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3605 return;
3606
2dd24552 3607 /*
c0b03411
DV		 3608 * The panel fitter should only be adjusted whilst the pipe is disabled,
3609 * according to register description and PRM.
2dd24552 3610 */
c0b03411
DV		 3611 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3612 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3613
b074cec8
JB		 3614 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3615 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3616
3617 /* Border color in case we don't scale up to the full screen. Black by
3618 * default, change to something else for debugging. */
3619 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3620}
3621
89b667f8
JB		 3622static void valleyview_crtc_enable(struct drm_crtc *crtc)
3623{
3624 struct drm_device *dev = crtc->dev;
3625 struct drm_i915_private *dev_priv = dev->dev_private;
3626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3627 struct intel_encoder *encoder;
3628 int pipe = intel_crtc->pipe;
3629 int plane = intel_crtc->plane;
3630
3631 WARN_ON(!crtc->enabled);
3632
3633 if (intel_crtc->active)
3634 return;
3635
3636 intel_crtc->active = true;
3637 intel_update_watermarks(dev);
3638
3639 mutex_lock(&dev_priv->dpio_lock);
3640
3641 for_each_encoder_on_crtc(dev, crtc, encoder)
3642 if (encoder->pre_pll_enable)
3643 encoder->pre_pll_enable(encoder);
3644
3645 intel_enable_pll(dev_priv, pipe);
3646
3647 for_each_encoder_on_crtc(dev, crtc, encoder)
3648 if (encoder->pre_enable)
3649 encoder->pre_enable(encoder);
3650
3651 /* VLV wants encoder enabling _before_ the pipe is up. */
3652 for_each_encoder_on_crtc(dev, crtc, encoder)
3653 encoder->enable(encoder);
3654
2dd24552
JB		 3655 /* Enable panel fitting for eDP */
3656 i9xx_pfit_enable(intel_crtc);
3657
63cbb074
VS		 3658 intel_crtc_load_lut(crtc);
3659
89b667f8
JB		 3660 intel_enable_pipe(dev_priv, pipe, false);
3661 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3662 intel_enable_planes(crtc);
5c38d48c 3663 intel_crtc_update_cursor(crtc, true);
89b667f8 3664
f440eb13
VS		 3665 intel_update_fbc(dev);
3666
89b667f8
JB		 3667 mutex_unlock(&dev_priv->dpio_lock);
3668}
3669
0b8765c6 3670static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3671{
3672 struct drm_device *dev = crtc->dev;
79e53945
JB		 3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3675 struct intel_encoder *encoder;
79e53945 3676 int pipe = intel_crtc->pipe;
80824003 3677 int plane = intel_crtc->plane;
79e53945 3678
08a48469
DV		 3679 WARN_ON(!crtc->enabled);
3680
f7abfe8b
CW		 3681 if (intel_crtc->active)
3682 return;
3683
3684 intel_crtc->active = true;
6b383a7f
CW		 3685 intel_update_watermarks(dev);
3686
63d7bbe9 3687 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3688
3689 for_each_encoder_on_crtc(dev, crtc, encoder)
3690 if (encoder->pre_enable)
3691 encoder->pre_enable(encoder);
3692
2dd24552
JB		 3693 /* Enable panel fitting for LVDS */
3694 i9xx_pfit_enable(intel_crtc);
3695
63cbb074
VS		 3696 intel_crtc_load_lut(crtc);
3697
040484af 3698 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3699 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3700 intel_enable_planes(crtc);
22e407d7 3701 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3702 if (IS_G4X(dev))
3703 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3704 intel_crtc_update_cursor(crtc, true);
79e53945 3705
0b8765c6
JB		 3706 /* Give the overlay scaler a chance to enable if it's on this pipe */
3707 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3708
f440eb13
VS		 3709 intel_update_fbc(dev);
3710
fa5c73b1
DV		 3711 for_each_encoder_on_crtc(dev, crtc, encoder)
3712 encoder->enable(encoder);
0b8765c6 3713}
79e53945 3714
87476d63
DV		 3715static void i9xx_pfit_disable(struct intel_crtc *crtc)
3716{
3717 struct drm_device *dev = crtc->base.dev;
3718 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3719
328d8e82
DV		 3720 if (!crtc->config.gmch_pfit.control)
3721 return;
87476d63 3722
328d8e82 3723 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3724
328d8e82
DV		 3725 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3726 I915_READ(PFIT_CONTROL));
3727 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3728}
3729
0b8765c6
JB		 3730static void i9xx_crtc_disable(struct drm_crtc *crtc)
3731{
3732 struct drm_device *dev = crtc->dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3735 struct intel_encoder *encoder;
0b8765c6
JB		 3736 int pipe = intel_crtc->pipe;
3737 int plane = intel_crtc->plane;
ef9c3aee 3738
f7abfe8b
CW		 3739 if (!intel_crtc->active)
3740 return;
3741
ea9d758d
DV		 3742 for_each_encoder_on_crtc(dev, crtc, encoder)
3743 encoder->disable(encoder);
3744
0b8765c6 3745 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3746 intel_crtc_wait_for_pending_flips(crtc);
3747 drm_vblank_off(dev, pipe);
0b8765c6 3748
973d04f9
CW		 3749 if (dev_priv->cfb_plane == plane)
3750 intel_disable_fbc(dev);
79e53945 3751
0d5b8c61
VS		 3752 intel_crtc_dpms_overlay(intel_crtc, false);
3753 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3754 intel_disable_planes(crtc);
b24e7179 3755 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3756
b24e7179 3757 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3758
87476d63 3759 i9xx_pfit_disable(intel_crtc);
24a1f16d 3760
89b667f8
JB		 3761 for_each_encoder_on_crtc(dev, crtc, encoder)
3762 if (encoder->post_disable)
3763 encoder->post_disable(encoder);
3764
63d7bbe9 3765 intel_disable_pll(dev_priv, pipe);
0b8765c6 3766
f7abfe8b 3767 intel_crtc->active = false;
6b383a7f
CW		 3768 intel_update_fbc(dev);
3769 intel_update_watermarks(dev);
0b8765c6
JB		 3770}
3771
ee7b9f93
JB		 3772static void i9xx_crtc_off(struct drm_crtc *crtc)
3773{
3774}
3775
976f8a20
DV		 3776static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3777 bool enabled)
2c07245f
ZW		 3778{
3779 struct drm_device *dev = crtc->dev;
3780 struct drm_i915_master_private *master_priv;
3781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3782 int pipe = intel_crtc->pipe;
79e53945
JB		 3783
3784 if (!dev->primary->master)
3785 return;
3786
3787 master_priv = dev->primary->master->driver_priv;
3788 if (!master_priv->sarea_priv)
3789 return;
3790
79e53945
JB		 3791 switch (pipe) {
3792 case 0:
3793 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3794 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3795 break;
3796 case 1:
3797 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3798 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3799 break;
3800 default:
9db4a9c7 3801 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3802 break;
3803 }
79e53945
JB		 3804}
3805
976f8a20
DV		 3806/**
3807 * Sets the power management mode of the pipe and plane.
3808 */
3809void intel_crtc_update_dpms(struct drm_crtc *crtc)
3810{
3811 struct drm_device *dev = crtc->dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct intel_encoder *intel_encoder;
3814 bool enable = false;
3815
3816 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3817 enable |= intel_encoder->connectors_active;
3818
3819 if (enable)
3820 dev_priv->display.crtc_enable(crtc);
3821 else
3822 dev_priv->display.crtc_disable(crtc);
3823
3824 intel_crtc_update_sarea(crtc, enable);
3825}
3826
cdd59983
CW		 3827static void intel_crtc_disable(struct drm_crtc *crtc)
3828{
cdd59983 3829 struct drm_device *dev = crtc->dev;
976f8a20 3830 struct drm_connector *connector;
ee7b9f93 3831 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3833
976f8a20
DV		 3834 /* crtc should still be enabled when we disable it. */
3835 WARN_ON(!crtc->enabled);
3836
3837 dev_priv->display.crtc_disable(crtc);
c77bf565 3838 intel_crtc->eld_vld = false;
976f8a20 3839 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3840 dev_priv->display.off(crtc);
3841
931872fc
CW		 3842 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3843 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3844
3845 if (crtc->fb) {
3846 mutex_lock(&dev->struct_mutex);
1690e1eb 3847 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3848 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3849 crtc->fb = NULL;
3850 }
3851
3852 /* Update computed state. */
3853 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3854 if (!connector->encoder || !connector->encoder->crtc)
3855 continue;
3856
3857 if (connector->encoder->crtc != crtc)
3858 continue;
3859
3860 connector->dpms = DRM_MODE_DPMS_OFF;
3861 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3862 }
3863}
3864
a261b246 3865void intel_modeset_disable(struct drm_device *dev)
79e53945 3866{
a261b246
DV		 3867 struct drm_crtc *crtc;
3868
3869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3870 if (crtc->enabled)
3871 intel_crtc_disable(crtc);
3872 }
79e53945
JB		 3873}
3874
ea5b213a 3875void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3876{
4ef69c7a 3877 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3878
ea5b213a
CW		 3879 drm_encoder_cleanup(encoder);
3880 kfree(intel_encoder);
7e7d76c3
JB		 3881}
3882
5ab432ef
DV		 3883/* Simple dpms helper for encodres with just one connector, no cloning and only
3884 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3885 * state of the entire output pipe. */
3886void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3887{
5ab432ef
DV		 3888 if (mode == DRM_MODE_DPMS_ON) {
3889 encoder->connectors_active = true;
3890
b2cabb0e 3891 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3892 } else {
3893 encoder->connectors_active = false;
3894
b2cabb0e 3895 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3896 }
79e53945
JB		 3897}
3898
0a91ca29
DV		 3899/* Cross check the actual hw state with our own modeset state tracking (and it's
3900 * internal consistency). */
b980514c 3901static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3902{
0a91ca29
DV		 3903 if (connector->get_hw_state(connector)) {
3904 struct intel_encoder *encoder = connector->encoder;
3905 struct drm_crtc *crtc;
3906 bool encoder_enabled;
3907 enum pipe pipe;
3908
3909 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3910 connector->base.base.id,
3911 drm_get_connector_name(&connector->base));
3912
3913 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3914 "wrong connector dpms state\n");
3915 WARN(connector->base.encoder != &encoder->base,
3916 "active connector not linked to encoder\n");
3917 WARN(!encoder->connectors_active,
3918 "encoder->connectors_active not set\n");
3919
3920 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3921 WARN(!encoder_enabled, "encoder not enabled\n");
3922 if (WARN_ON(!encoder->base.crtc))
3923 return;
3924
3925 crtc = encoder->base.crtc;
3926
3927 WARN(!crtc->enabled, "crtc not enabled\n");
3928 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3929 WARN(pipe != to_intel_crtc(crtc)->pipe,
3930 "encoder active on the wrong pipe\n");
3931 }
79e53945
JB		 3932}
3933
5ab432ef
DV		 3934/* Even simpler default implementation, if there's really no special case to
3935 * consider. */
3936void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3937{
5ab432ef 3938 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3939
5ab432ef
DV		 3940 /* All the simple cases only support two dpms states. */
3941 if (mode != DRM_MODE_DPMS_ON)
3942 mode = DRM_MODE_DPMS_OFF;
d4270e57 3943
5ab432ef
DV		 3944 if (mode == connector->dpms)
3945 return;
3946
3947 connector->dpms = mode;
3948
3949 /* Only need to change hw state when actually enabled */
3950 if (encoder->base.crtc)
3951 intel_encoder_dpms(encoder, mode);
3952 else
8af6cf88 3953 WARN_ON(encoder->connectors_active != false);
0a91ca29 3954
b980514c 3955 intel_modeset_check_state(connector->dev);
79e53945
JB		 3956}
3957
f0947c37
DV		 3958/* Simple connector->get_hw_state implementation for encoders that support only
3959 * one connector and no cloning and hence the encoder state determines the state
3960 * of the connector. */
3961bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3962{
24929352 3963 enum pipe pipe = 0;
f0947c37 3964 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3965
f0947c37 3966 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3967}
3968
1857e1da
DV		 3969static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3970 struct intel_crtc_config *pipe_config)
3971{
3972 struct drm_i915_private *dev_priv = dev->dev_private;
3973 struct intel_crtc *pipe_B_crtc =
3974 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3975
3976 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3977 pipe_name(pipe), pipe_config->fdi_lanes);
3978 if (pipe_config->fdi_lanes > 4) {
3979 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3980 pipe_name(pipe), pipe_config->fdi_lanes);
3981 return false;
3982 }
3983
3984 if (IS_HASWELL(dev)) {
3985 if (pipe_config->fdi_lanes > 2) {
3986 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3987 pipe_config->fdi_lanes);
3988 return false;
3989 } else {
3990 return true;
3991 }
3992 }
3993
3994 if (INTEL_INFO(dev)->num_pipes == 2)
3995 return true;
3996
3997 /* Ivybridge 3 pipe is really complicated */
3998 switch (pipe) {
3999 case PIPE_A:
4000 return true;
4001 case PIPE_B:
4002 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4003 pipe_config->fdi_lanes > 2) {
4004 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4005 pipe_name(pipe), pipe_config->fdi_lanes);
4006 return false;
4007 }
4008 return true;
4009 case PIPE_C:
1e833f40 4010 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4011 pipe_B_crtc->config.fdi_lanes <= 2) {
4012 if (pipe_config->fdi_lanes > 2) {
4013 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4014 pipe_name(pipe), pipe_config->fdi_lanes);
4015 return false;
4016 }
4017 } else {
4018 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4019 return false;
4020 }
4021 return true;
4022 default:
4023 BUG();
4024 }
4025}
4026
e29c22c0
DV		 4027#define RETRY 1
4028static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4029 struct intel_crtc_config *pipe_config)
877d48d5 4030{
1857e1da 4031 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4032 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4033 int lane, link_bw, fdi_dotclock;
e29c22c0 4034 bool setup_ok, needs_recompute = false;
877d48d5 4035
e29c22c0 4036retry:
877d48d5
DV		 4037 /* FDI is a binary signal running at ~2.7GHz, encoding
4038 * each output octet as 10 bits. The actual frequency
4039 * is stored as a divider into a 100MHz clock, and the
4040 * mode pixel clock is stored in units of 1KHz.
4041 * Hence the bw of each lane in terms of the mode signal
4042 * is:
4043 */
4044 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4045
ff9a6750 4046 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4047 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4048
4049 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4050 pipe_config->pipe_bpp);
4051
4052 pipe_config->fdi_lanes = lane;
4053
2bd89a07 4054 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4055 link_bw, &pipe_config->fdi_m_n);
1857e1da 4056
e29c22c0
DV		 4057 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4058 intel_crtc->pipe, pipe_config);
4059 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4060 pipe_config->pipe_bpp -= 2*3;
4061 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4062 pipe_config->pipe_bpp);
4063 needs_recompute = true;
4064 pipe_config->bw_constrained = true;
4065
4066 goto retry;
4067 }
4068
4069 if (needs_recompute)
4070 return RETRY;
4071
4072 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4073}
4074
42db64ef
PZ		 4075static void hsw_compute_ips_config(struct intel_crtc *crtc,
4076 struct intel_crtc_config *pipe_config)
4077{
3c4ca58c
PZ		 4078 pipe_config->ips_enabled = i915_enable_ips &&
4079 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4080 pipe_config->pipe_bpp == 24;
4081}
4082
a43f6e0f 4083static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4084 struct intel_crtc_config *pipe_config)
79e53945 4085{
a43f6e0f 4086 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4087 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4088
bad720ff 4089 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4090 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4091 if (pipe_config->requested_mode.clock * 3
4092 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4093 return -EINVAL;
2c07245f 4094 }
89749350 4095
f9bef081
DV		 4096 /* All interlaced capable intel hw wants timings in frames. Note though
4097 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4098 * timings, so we need to be careful not to clobber these.*/
7ae89233 4099 if (!pipe_config->timings_set)
f9bef081 4100 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4101
8693a824
DL		 4102 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4103 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4104 */
4105 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4106 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4107 return -EINVAL;
44f46b42 4108
bd080ee5 4109 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4110 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4111 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4112 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4113 * for lvds. */
4114 pipe_config->pipe_bpp = 8*3;
4115 }
4116
42db64ef 4117 if (IS_HASWELL(dev))
a43f6e0f
DV		 4118 hsw_compute_ips_config(crtc, pipe_config);
4119
4120 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4121 * clock survives for now. */
4122 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4123 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4124
877d48d5 4125 if (pipe_config->has_pch_encoder)
a43f6e0f 4126 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4127
e29c22c0 4128 return 0;
79e53945
JB		 4129}
4130
25eb05fc
JB		 4131static int valleyview_get_display_clock_speed(struct drm_device *dev)
4132{
4133 return 400000; /* FIXME */
4134}
4135
e70236a8
JB		 4136static int i945_get_display_clock_speed(struct drm_device *dev)
4137{
4138 return 400000;
4139}
79e53945 4140
e70236a8 4141static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4142{
e70236a8
JB		 4143 return 333000;
4144}
79e53945 4145
e70236a8
JB		 4146static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4147{
4148 return 200000;
4149}
79e53945 4150
e70236a8
JB		 4151static int i915gm_get_display_clock_speed(struct drm_device *dev)
4152{
4153 u16 gcfgc = 0;
79e53945 4154
e70236a8
JB		 4155 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4156
4157 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4158 return 133000;
4159 else {
4160 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4161 case GC_DISPLAY_CLOCK_333_MHZ:
4162 return 333000;
4163 default:
4164 case GC_DISPLAY_CLOCK_190_200_MHZ:
4165 return 190000;
79e53945 4166 }
e70236a8
JB		 4167 }
4168}
4169
4170static int i865_get_display_clock_speed(struct drm_device *dev)
4171{
4172 return 266000;
4173}
4174
4175static int i855_get_display_clock_speed(struct drm_device *dev)
4176{
4177 u16 hpllcc = 0;
4178 /* Assume that the hardware is in the high speed state. This
4179 * should be the default.
4180 */
4181 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4182 case GC_CLOCK_133_200:
4183 case GC_CLOCK_100_200:
4184 return 200000;
4185 case GC_CLOCK_166_250:
4186 return 250000;
4187 case GC_CLOCK_100_133:
79e53945 4188 return 133000;
e70236a8 4189 }
79e53945 4190
e70236a8
JB		 4191 /* Shouldn't happen */
4192 return 0;
4193}
79e53945 4194
e70236a8
JB		 4195static int i830_get_display_clock_speed(struct drm_device *dev)
4196{
4197 return 133000;
79e53945
JB		 4198}
4199
2c07245f 4200static void
a65851af 4201intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4202{
a65851af
VS		 4203 while (*num > DATA_LINK_M_N_MASK ||
4204 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4205 *num >>= 1;
4206 *den >>= 1;
4207 }
4208}
4209
a65851af
VS		 4210static void compute_m_n(unsigned int m, unsigned int n,
4211 uint32_t *ret_m, uint32_t *ret_n)
4212{
4213 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4214 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4215 intel_reduce_m_n_ratio(ret_m, ret_n);
4216}
4217
e69d0bc1
DV		 4218void
4219intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4220 int pixel_clock, int link_clock,
4221 struct intel_link_m_n *m_n)
2c07245f 4222{
e69d0bc1 4223 m_n->tu = 64;
a65851af
VS		 4224
4225 compute_m_n(bits_per_pixel * pixel_clock,
4226 link_clock * nlanes * 8,
4227 &m_n->gmch_m, &m_n->gmch_n);
4228
4229 compute_m_n(pixel_clock, link_clock,
4230 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4231}
4232
a7615030
CW		 4233static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4234{
72bbe58c
KP		 4235 if (i915_panel_use_ssc >= 0)
4236 return i915_panel_use_ssc != 0;
41aa3448 4237 return dev_priv->vbt.lvds_use_ssc
435793df 4238 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4239}
4240
a0c4da24
JB		 4241static int vlv_get_refclk(struct drm_crtc *crtc)
4242{
4243 struct drm_device *dev = crtc->dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 int refclk = 27000; /* for DP & HDMI */
4246
4247 return 100000; /* only one validated so far */
4248
4249 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4250 refclk = 96000;
4251 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4252 if (intel_panel_use_ssc(dev_priv))
4253 refclk = 100000;
4254 else
4255 refclk = 96000;
4256 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4257 refclk = 100000;
4258 }
4259
4260 return refclk;
4261}
4262
c65d77d8
JB		 4263static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4264{
4265 struct drm_device *dev = crtc->dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 int refclk;
4268
a0c4da24
JB		 4269 if (IS_VALLEYVIEW(dev)) {
4270 refclk = vlv_get_refclk(crtc);
4271 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4272 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4273 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4274 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4275 refclk / 1000);
4276 } else if (!IS_GEN2(dev)) {
4277 refclk = 96000;
4278 } else {
4279 refclk = 48000;
4280 }
4281
4282 return refclk;
4283}
4284
7429e9d4
DV		 4285static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4286{
4287 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4288}
4289
4290static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4291{
4292 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4293}
4294
f47709a9 4295static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4296 intel_clock_t *reduced_clock)
4297{
f47709a9 4298 struct drm_device *dev = crtc->base.dev;
a7516a05 4299 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4300 int pipe = crtc->pipe;
a7516a05
JB		 4301 u32 fp, fp2 = 0;
4302
4303 if (IS_PINEVIEW(dev)) {
7429e9d4 4304 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4305 if (reduced_clock)
7429e9d4 4306 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4307 } else {
7429e9d4 4308 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4309 if (reduced_clock)
7429e9d4 4310 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4311 }
4312
4313 I915_WRITE(FP0(pipe), fp);
4314
f47709a9
DV		 4315 crtc->lowfreq_avail = false;
4316 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4317 reduced_clock && i915_powersave) {
4318 I915_WRITE(FP1(pipe), fp2);
f47709a9 4319 crtc->lowfreq_avail = true;
a7516a05
JB		 4320 } else {
4321 I915_WRITE(FP1(pipe), fp);
4322 }
4323}
4324
89b667f8
JB		 4325static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4326{
4327 u32 reg_val;
4328
4329 /*
4330 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4331 * and set it to a reasonable value instead.
4332 */
ae99258f 4333 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4334 reg_val &= 0xffffff00;
4335 reg_val |= 0x00000030;
ae99258f 4336 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4337
ae99258f 4338 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4339 reg_val &= 0x8cffffff;
4340 reg_val = 0x8c000000;
ae99258f 4341 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4342
ae99258f 4343 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4344 reg_val &= 0xffffff00;
ae99258f 4345 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4346
ae99258f 4347 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4348 reg_val &= 0x00ffffff;
4349 reg_val |= 0xb0000000;
ae99258f 4350 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4351}
4352
b551842d
DV		 4353static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4354 struct intel_link_m_n *m_n)
4355{
4356 struct drm_device *dev = crtc->base.dev;
4357 struct drm_i915_private *dev_priv = dev->dev_private;
4358 int pipe = crtc->pipe;
4359
e3b95f1e
DV		 4360 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4361 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4362 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4363 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4364}
4365
4366static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4367 struct intel_link_m_n *m_n)
4368{
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 int pipe = crtc->pipe;
4372 enum transcoder transcoder = crtc->config.cpu_transcoder;
4373
4374 if (INTEL_INFO(dev)->gen >= 5) {
4375 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4376 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4377 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4378 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4379 } else {
e3b95f1e
DV		 4380 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4381 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4382 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4383 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4384 }
4385}
4386
03afc4a2
DV		 4387static void intel_dp_set_m_n(struct intel_crtc *crtc)
4388{
4389 if (crtc->config.has_pch_encoder)
4390 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4391 else
4392 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4393}
4394
f47709a9 4395static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4396{
f47709a9 4397 struct drm_device *dev = crtc->base.dev;
a0c4da24 4398 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4399 struct intel_encoder *encoder;
f47709a9 4400 int pipe = crtc->pipe;
89b667f8 4401 u32 dpll, mdiv;
a0c4da24 4402 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4403 bool is_hdmi;
198a037f 4404 u32 coreclk, reg_val, dpll_md;
a0c4da24 4405
09153000
DV		 4406 mutex_lock(&dev_priv->dpio_lock);
4407
89b667f8 4408 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4409
f47709a9
DV		 4410 bestn = crtc->config.dpll.n;
4411 bestm1 = crtc->config.dpll.m1;
4412 bestm2 = crtc->config.dpll.m2;
4413 bestp1 = crtc->config.dpll.p1;
4414 bestp2 = crtc->config.dpll.p2;
a0c4da24 4415
89b667f8
JB		 4416 /* See eDP HDMI DPIO driver vbios notes doc */
4417
4418 /* PLL B needs special handling */
4419 if (pipe)
4420 vlv_pllb_recal_opamp(dev_priv);
4421
4422 /* Set up Tx target for periodic Rcomp update */
ae99258f 4423 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4424
4425 /* Disable target IRef on PLL */
ae99258f 4426 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4427 reg_val &= 0x00ffffff;
ae99258f 4428 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4429
4430 /* Disable fast lock */
ae99258f 4431 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4432
4433 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4434 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4435 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4436 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4437 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4438
4439 /*
4440 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4441 * but we don't support that).
4442 * Note: don't use the DAC post divider as it seems unstable.
4443 */
4444 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4445 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4446
89b667f8 4447 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4448 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4449
89b667f8 4450 /* Set HBR and RBR LPF coefficients */
ff9a6750 4451 if (crtc->config.port_clock == 162000 ||
89b667f8 4452 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4453 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4454 0x005f0021);
4455 else
ae99258f 4456 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4457 0x00d0000f);
4458
4459 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4460 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4461 /* Use SSC source */
4462 if (!pipe)
ae99258f 4463 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4464 0x0df40000);
4465 else
ae99258f 4466 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4467 0x0df70000);
4468 } else { /* HDMI or VGA */
4469 /* Use bend source */
4470 if (!pipe)
ae99258f 4471 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4472 0x0df70000);
4473 else
ae99258f 4474 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4475 0x0df40000);
4476 }
a0c4da24 4477
ae99258f 4478 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4479 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4480 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4481 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4482 coreclk |= 0x01000000;
ae99258f 4483 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4484
ae99258f 4485 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4486
89b667f8
JB		 4487 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4488 if (encoder->pre_pll_enable)
4489 encoder->pre_pll_enable(encoder);
2a8f64ca 4490
89b667f8
JB		 4491 /* Enable DPIO clock input */
4492 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4493 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4494 if (pipe)
4495 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4496
89b667f8 4497 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4498 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4499 POSTING_READ(DPLL(pipe));
4500 udelay(150);
a0c4da24 4501
89b667f8
JB		 4502 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4503 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4504
ef1b460d
DV		 4505 dpll_md = (crtc->config.pixel_multiplier - 1)
4506 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4507 I915_WRITE(DPLL_MD(pipe), dpll_md);
4508 POSTING_READ(DPLL_MD(pipe));
f47709a9 4509
89b667f8
JB		 4510 if (crtc->config.has_dp_encoder)
4511 intel_dp_set_m_n(crtc);
09153000
DV		 4512
4513 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4514}
4515
f47709a9
DV		 4516static void i9xx_update_pll(struct intel_crtc *crtc,
4517 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4518 int num_connectors)
4519{
f47709a9 4520 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4521 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4522 struct intel_encoder *encoder;
f47709a9 4523 int pipe = crtc->pipe;
eb1cbe48
DV		 4524 u32 dpll;
4525 bool is_sdvo;
f47709a9 4526 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4527
f47709a9 4528 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4529
f47709a9
DV		 4530 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4531 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4532
4533 dpll = DPLL_VGA_MODE_DIS;
4534
f47709a9 4535 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4536 dpll |= DPLLB_MODE_LVDS;
4537 else
4538 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4539
ef1b460d 4540 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4541 dpll |= (crtc->config.pixel_multiplier - 1)
4542 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4543 }
198a037f
DV		 4544
4545 if (is_sdvo)
4546 dpll |= DPLL_DVO_HIGH_SPEED;
4547
f47709a9 4548 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4549 dpll |= DPLL_DVO_HIGH_SPEED;
4550
4551 /* compute bitmask from p1 value */
4552 if (IS_PINEVIEW(dev))
4553 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4554 else {
4555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4556 if (IS_G4X(dev) && reduced_clock)
4557 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4558 }
4559 switch (clock->p2) {
4560 case 5:
4561 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4562 break;
4563 case 7:
4564 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4565 break;
4566 case 10:
4567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4568 break;
4569 case 14:
4570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4571 break;
4572 }
4573 if (INTEL_INFO(dev)->gen >= 4)
4574 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4575
09ede541 4576 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4577 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4578 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4579 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4580 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4581 else
4582 dpll |= PLL_REF_INPUT_DREFCLK;
4583
4584 dpll |= DPLL_VCO_ENABLE;
4585 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4586 POSTING_READ(DPLL(pipe));
4587 udelay(150);
4588
f47709a9 4589 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4590 if (encoder->pre_pll_enable)
4591 encoder->pre_pll_enable(encoder);
eb1cbe48 4592
f47709a9
DV		 4593 if (crtc->config.has_dp_encoder)
4594 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4595
4596 I915_WRITE(DPLL(pipe), dpll);
4597
4598 /* Wait for the clocks to stabilize. */
4599 POSTING_READ(DPLL(pipe));
4600 udelay(150);
4601
4602 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4603 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4604 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4605 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4606 } else {
4607 /* The pixel multiplier can only be updated once the
4608 * DPLL is enabled and the clocks are stable.
4609 *
4610 * So write it again.
4611 */
4612 I915_WRITE(DPLL(pipe), dpll);
4613 }
4614}
4615
f47709a9 4616static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4617 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4618 int num_connectors)
4619{
f47709a9 4620 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4621 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4622 struct intel_encoder *encoder;
f47709a9 4623 int pipe = crtc->pipe;
eb1cbe48 4624 u32 dpll;
f47709a9 4625 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4626
f47709a9 4627 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4628
eb1cbe48
DV		 4629 dpll = DPLL_VGA_MODE_DIS;
4630
f47709a9 4631 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4632 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4633 } else {
4634 if (clock->p1 == 2)
4635 dpll |= PLL_P1_DIVIDE_BY_TWO;
4636 else
4637 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4638 if (clock->p2 == 4)
4639 dpll |= PLL_P2_DIVIDE_BY_4;
4640 }
4641
f47709a9 4642 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4643 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4644 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4645 else
4646 dpll |= PLL_REF_INPUT_DREFCLK;
4647
4648 dpll |= DPLL_VCO_ENABLE;
4649 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4650 POSTING_READ(DPLL(pipe));
4651 udelay(150);
4652
f47709a9 4653 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4654 if (encoder->pre_pll_enable)
4655 encoder->pre_pll_enable(encoder);
eb1cbe48 4656
5b5896e4
DV		 4657 I915_WRITE(DPLL(pipe), dpll);
4658
4659 /* Wait for the clocks to stabilize. */
4660 POSTING_READ(DPLL(pipe));
4661 udelay(150);
4662
eb1cbe48
DV		 4663 /* The pixel multiplier can only be updated once the
4664 * DPLL is enabled and the clocks are stable.
4665 *
4666 * So write it again.
4667 */
4668 I915_WRITE(DPLL(pipe), dpll);
4669}
4670
8a654f3b 4671static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4672{
4673 struct drm_device *dev = intel_crtc->base.dev;
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4676 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4677 struct drm_display_mode *adjusted_mode =
4678 &intel_crtc->config.adjusted_mode;
4679 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4680 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4681
4682 /* We need to be careful not to changed the adjusted mode, for otherwise
4683 * the hw state checker will get angry at the mismatch. */
4684 crtc_vtotal = adjusted_mode->crtc_vtotal;
4685 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4686
4687 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4688 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4689 crtc_vtotal -= 1;
4690 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4691 vsyncshift = adjusted_mode->crtc_hsync_start
4692 - adjusted_mode->crtc_htotal / 2;
4693 } else {
4694 vsyncshift = 0;
4695 }
4696
4697 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4698 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4699
fe2b8f9d 4700 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4701 (adjusted_mode->crtc_hdisplay - 1) |
4702 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4703 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4704 (adjusted_mode->crtc_hblank_start - 1) |
4705 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4706 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4707 (adjusted_mode->crtc_hsync_start - 1) |
4708 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4709
fe2b8f9d 4710 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4711 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4712 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4713 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4714 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4715 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4716 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4717 (adjusted_mode->crtc_vsync_start - 1) |
4718 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4719
b5e508d4
PZ		 4720 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4721 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4722 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4723 * bits. */
4724 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4725 (pipe == PIPE_B || pipe == PIPE_C))
4726 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4727
b0e77b9c
PZ		 4728 /* pipesrc controls the size that is scaled from, which should
4729 * always be the user's requested size.
4730 */
4731 I915_WRITE(PIPESRC(pipe),
4732 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4733}
4734
1bd1bd80
DV		 4735static void intel_get_pipe_timings(struct intel_crtc *crtc,
4736 struct intel_crtc_config *pipe_config)
4737{
4738 struct drm_device *dev = crtc->base.dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4741 uint32_t tmp;
4742
4743 tmp = I915_READ(HTOTAL(cpu_transcoder));
4744 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4745 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4746 tmp = I915_READ(HBLANK(cpu_transcoder));
4747 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4748 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4749 tmp = I915_READ(HSYNC(cpu_transcoder));
4750 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4751 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4752
4753 tmp = I915_READ(VTOTAL(cpu_transcoder));
4754 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4755 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4756 tmp = I915_READ(VBLANK(cpu_transcoder));
4757 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4758 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4759 tmp = I915_READ(VSYNC(cpu_transcoder));
4760 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4761 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4762
4763 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4764 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4765 pipe_config->adjusted_mode.crtc_vtotal += 1;
4766 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4767 }
4768
4769 tmp = I915_READ(PIPESRC(crtc->pipe));
4770 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4771 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4772}
4773
84b046f3
DV		 4774static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4775{
4776 struct drm_device *dev = intel_crtc->base.dev;
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4778 uint32_t pipeconf;
4779
4780 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4781
4782 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4783 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4784 * core speed.
4785 *
4786 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4787 * pipe == 0 check?
4788 */
4789 if (intel_crtc->config.requested_mode.clock >
4790 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4791 pipeconf |= PIPECONF_DOUBLE_WIDE;
4792 else
4793 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4794 }
4795
ff9ce46e
DV		 4796 /* only g4x and later have fancy bpc/dither controls */
4797 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4798 pipeconf &= ~(PIPECONF_BPC_MASK |
4799 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4800
4801 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4802 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4803 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4804 PIPECONF_DITHER_TYPE_SP;
84b046f3 4805
ff9ce46e
DV		 4806 switch (intel_crtc->config.pipe_bpp) {
4807 case 18:
4808 pipeconf |= PIPECONF_6BPC;
4809 break;
4810 case 24:
4811 pipeconf |= PIPECONF_8BPC;
4812 break;
4813 case 30:
4814 pipeconf |= PIPECONF_10BPC;
4815 break;
4816 default:
4817 /* Case prevented by intel_choose_pipe_bpp_dither. */
4818 BUG();
84b046f3
DV		 4819 }
4820 }
4821
4822 if (HAS_PIPE_CXSR(dev)) {
4823 if (intel_crtc->lowfreq_avail) {
4824 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4825 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4826 } else {
4827 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4828 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4829 }
4830 }
4831
4832 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4833 if (!IS_GEN2(dev) &&
4834 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4835 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4836 else
4837 pipeconf |= PIPECONF_PROGRESSIVE;
4838
9c8e09b7
VS		 4839 if (IS_VALLEYVIEW(dev)) {
4840 if (intel_crtc->config.limited_color_range)
4841 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4842 else
4843 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4844 }
4845
84b046f3
DV		 4846 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4847 POSTING_READ(PIPECONF(intel_crtc->pipe));
4848}
4849
f564048e 4850static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4851 int x, int y,
94352cf9 4852 struct drm_framebuffer *fb)
79e53945
JB		 4853{
4854 struct drm_device *dev = crtc->dev;
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4857 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4858 int pipe = intel_crtc->pipe;
80824003 4859 int plane = intel_crtc->plane;
c751ce4f 4860 int refclk, num_connectors = 0;
652c393a 4861 intel_clock_t clock, reduced_clock;
84b046f3 4862 u32 dspcntr;
a16af721
DV		 4863 bool ok, has_reduced_clock = false;
4864 bool is_lvds = false;
5eddb70b 4865 struct intel_encoder *encoder;
d4906093 4866 const intel_limit_t *limit;
5c3b82e2 4867 int ret;
79e53945 4868
6c2b7c12 4869 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4870 switch (encoder->type) {
79e53945
JB		 4871 case INTEL_OUTPUT_LVDS:
4872 is_lvds = true;
4873 break;
79e53945 4874 }
43565a06 4875
c751ce4f 4876 num_connectors++;
79e53945
JB		 4877 }
4878
c65d77d8 4879 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4880
d4906093
ML		 4881 /*
4882 * Returns a set of divisors for the desired target clock with the given
4883 * refclk, or FALSE. The returned values represent the clock equation:
4884 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4885 */
1b894b59 4886 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4887 ok = dev_priv->display.find_dpll(limit, crtc,
4888 intel_crtc->config.port_clock,
ee9300bb
DV		 4889 refclk, NULL, &clock);
4890 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4891 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4892 return -EINVAL;
79e53945
JB		 4893 }
4894
cda4b7d3 4895 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4896 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4897
ddc9003c 4898 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4899 /*
4900 * Ensure we match the reduced clock's P to the target clock.
4901 * If the clocks don't match, we can't switch the display clock
4902 * by using the FP0/FP1. In such case we will disable the LVDS
4903 * downclock feature.
4904 */
ee9300bb
DV		 4905 has_reduced_clock =
4906 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4907 dev_priv->lvds_downclock,
ee9300bb 4908 refclk, &clock,
5eddb70b 4909 &reduced_clock);
7026d4ac 4910 }
f47709a9
DV		 4911 /* Compat-code for transition, will disappear. */
4912 if (!intel_crtc->config.clock_set) {
4913 intel_crtc->config.dpll.n = clock.n;
4914 intel_crtc->config.dpll.m1 = clock.m1;
4915 intel_crtc->config.dpll.m2 = clock.m2;
4916 intel_crtc->config.dpll.p1 = clock.p1;
4917 intel_crtc->config.dpll.p2 = clock.p2;
4918 }
7026d4ac 4919
eb1cbe48 4920 if (IS_GEN2(dev))
8a654f3b 4921 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4922 has_reduced_clock ? &reduced_clock : NULL,
4923 num_connectors);
a0c4da24 4924 else if (IS_VALLEYVIEW(dev))
f47709a9 4925 vlv_update_pll(intel_crtc);
79e53945 4926 else
f47709a9 4927 i9xx_update_pll(intel_crtc,
eb1cbe48 4928 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4929 num_connectors);
79e53945 4930
79e53945
JB		 4931 /* Set up the display plane register */
4932 dspcntr = DISPPLANE_GAMMA_ENABLE;
4933
da6ecc5d
JB		 4934 if (!IS_VALLEYVIEW(dev)) {
4935 if (pipe == 0)
4936 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4937 else
4938 dspcntr |= DISPPLANE_SEL_PIPE_B;
4939 }
79e53945 4940
8a654f3b 4941 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4942
4943 /* pipesrc and dspsize control the size that is scaled from,
4944 * which should always be the user's requested size.
79e53945 4945 */
929c77fb
EA		 4946 I915_WRITE(DSPSIZE(plane),
4947 ((mode->vdisplay - 1) << 16) |
4948 (mode->hdisplay - 1));
4949 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4950
84b046f3
DV		 4951 i9xx_set_pipeconf(intel_crtc);
4952
f564048e
EA		 4953 I915_WRITE(DSPCNTR(plane), dspcntr);
4954 POSTING_READ(DSPCNTR(plane));
4955
94352cf9 4956 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4957
4958 intel_update_watermarks(dev);
4959
f564048e
EA		 4960 return ret;
4961}
4962
2fa2fe9a
DV		 4963static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4964 struct intel_crtc_config *pipe_config)
4965{
4966 struct drm_device *dev = crtc->base.dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 uint32_t tmp;
4969
4970 tmp = I915_READ(PFIT_CONTROL);
4971
4972 if (INTEL_INFO(dev)->gen < 4) {
4973 if (crtc->pipe != PIPE_B)
4974 return;
4975
4976 /* gen2/3 store dither state in pfit control, needs to match */
4977 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4978 } else {
4979 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4980 return;
4981 }
4982
4983 if (!(tmp & PFIT_ENABLE))
4984 return;
4985
4986 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4987 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4988 if (INTEL_INFO(dev)->gen < 5)
4989 pipe_config->gmch_pfit.lvds_border_bits =
4990 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4991}
4992
0e8ffe1b
DV		 4993static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4994 struct intel_crtc_config *pipe_config)
4995{
4996 struct drm_device *dev = crtc->base.dev;
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 uint32_t tmp;
4999
eccb140b 5000 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5001 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5002
0e8ffe1b
DV		 5003 tmp = I915_READ(PIPECONF(crtc->pipe));
5004 if (!(tmp & PIPECONF_ENABLE))
5005 return false;
5006
1bd1bd80
DV		 5007 intel_get_pipe_timings(crtc, pipe_config);
5008
2fa2fe9a
DV		 5009 i9xx_get_pfit_config(crtc, pipe_config);
5010
6c49f241
DV		 5011 if (INTEL_INFO(dev)->gen >= 4) {
5012 tmp = I915_READ(DPLL_MD(crtc->pipe));
5013 pipe_config->pixel_multiplier =
5014 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5015 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5016 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5017 tmp = I915_READ(DPLL(crtc->pipe));
5018 pipe_config->pixel_multiplier =
5019 ((tmp & SDVO_MULTIPLIER_MASK)
5020 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5021 } else {
5022 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5023 * port and will be fixed up in the encoder->get_config
5024 * function. */
5025 pipe_config->pixel_multiplier = 1;
5026 }
5027
0e8ffe1b
DV		 5028 return true;
5029}
5030
dde86e2d 5031static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5032{
5033 struct drm_i915_private *dev_priv = dev->dev_private;
5034 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5035 struct intel_encoder *encoder;
74cfd7ac 5036 u32 val, final;
13d83a67 5037 bool has_lvds = false;
199e5d79 5038 bool has_cpu_edp = false;
199e5d79 5039 bool has_panel = false;
99eb6a01
KP		 5040 bool has_ck505 = false;
5041 bool can_ssc = false;
13d83a67
JB		 5042
5043 /* We need to take the global config into account */
199e5d79
KP		 5044 list_for_each_entry(encoder, &mode_config->encoder_list,
5045 base.head) {
5046 switch (encoder->type) {
5047 case INTEL_OUTPUT_LVDS:
5048 has_panel = true;
5049 has_lvds = true;
5050 break;
5051 case INTEL_OUTPUT_EDP:
5052 has_panel = true;
2de6905f 5053 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5054 has_cpu_edp = true;
5055 break;
13d83a67
JB		 5056 }
5057 }
5058
99eb6a01 5059 if (HAS_PCH_IBX(dev)) {
41aa3448 5060 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5061 can_ssc = has_ck505;
5062 } else {
5063 has_ck505 = false;
5064 can_ssc = true;
5065 }
5066
2de6905f
ID		 5067 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5068 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5069
5070 /* Ironlake: try to setup display ref clock before DPLL
5071 * enabling. This is only under driver's control after
5072 * PCH B stepping, previous chipset stepping should be
5073 * ignoring this setting.
5074 */
74cfd7ac
CW		 5075 val = I915_READ(PCH_DREF_CONTROL);
5076
5077 /* As we must carefully and slowly disable/enable each source in turn,
5078 * compute the final state we want first and check if we need to
5079 * make any changes at all.
5080 */
5081 final = val;
5082 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5083 if (has_ck505)
5084 final |= DREF_NONSPREAD_CK505_ENABLE;
5085 else
5086 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5087
5088 final &= ~DREF_SSC_SOURCE_MASK;
5089 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5090 final &= ~DREF_SSC1_ENABLE;
5091
5092 if (has_panel) {
5093 final |= DREF_SSC_SOURCE_ENABLE;
5094
5095 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5096 final |= DREF_SSC1_ENABLE;
5097
5098 if (has_cpu_edp) {
5099 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5100 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5101 else
5102 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5103 } else
5104 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5105 } else {
5106 final |= DREF_SSC_SOURCE_DISABLE;
5107 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5108 }
5109
5110 if (final == val)
5111 return;
5112
13d83a67 5113 /* Always enable nonspread source */
74cfd7ac 5114 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5115
99eb6a01 5116 if (has_ck505)
74cfd7ac 5117 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5118 else
74cfd7ac 5119 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5120
199e5d79 5121 if (has_panel) {
74cfd7ac
CW		 5122 val &= ~DREF_SSC_SOURCE_MASK;
5123 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5124
199e5d79 5125 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5126 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5127 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5128 val |= DREF_SSC1_ENABLE;
e77166b5 5129 } else
74cfd7ac 5130 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5131
5132 /* Get SSC going before enabling the outputs */
74cfd7ac 5133 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5134 POSTING_READ(PCH_DREF_CONTROL);
5135 udelay(200);
5136
74cfd7ac 5137 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5138
5139 /* Enable CPU source on CPU attached eDP */
199e5d79 5140 if (has_cpu_edp) {
99eb6a01 5141 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5142 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5143 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5144 }
13d83a67 5145 else
74cfd7ac 5146 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5147 } else
74cfd7ac 5148 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5149
74cfd7ac 5150 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5151 POSTING_READ(PCH_DREF_CONTROL);
5152 udelay(200);
5153 } else {
5154 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5155
74cfd7ac 5156 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5157
5158 /* Turn off CPU output */
74cfd7ac 5159 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5160
74cfd7ac 5161 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5162 POSTING_READ(PCH_DREF_CONTROL);
5163 udelay(200);
5164
5165 /* Turn off the SSC source */
74cfd7ac
CW		 5166 val &= ~DREF_SSC_SOURCE_MASK;
5167 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5168
5169 /* Turn off SSC1 */
74cfd7ac 5170 val &= ~DREF_SSC1_ENABLE;
199e5d79 5171
74cfd7ac 5172 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5173 POSTING_READ(PCH_DREF_CONTROL);
5174 udelay(200);
5175 }
74cfd7ac
CW		 5176
5177 BUG_ON(val != final);
13d83a67
JB		 5178}
5179
dde86e2d
PZ		 5180/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5181static void lpt_init_pch_refclk(struct drm_device *dev)
5182{
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184 struct drm_mode_config *mode_config = &dev->mode_config;
5185 struct intel_encoder *encoder;
5186 bool has_vga = false;
5187 bool is_sdv = false;
5188 u32 tmp;
5189
5190 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5191 switch (encoder->type) {
5192 case INTEL_OUTPUT_ANALOG:
5193 has_vga = true;
5194 break;
5195 }
5196 }
5197
5198 if (!has_vga)
5199 return;
5200
c00db246
DV		 5201 mutex_lock(&dev_priv->dpio_lock);
5202
dde86e2d
PZ		 5203 /* XXX: Rip out SDV support once Haswell ships for real. */
5204 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5205 is_sdv = true;
5206
5207 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5208 tmp &= ~SBI_SSCCTL_DISABLE;
5209 tmp |= SBI_SSCCTL_PATHALT;
5210 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5211
5212 udelay(24);
5213
5214 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5215 tmp &= ~SBI_SSCCTL_PATHALT;
5216 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5217
5218 if (!is_sdv) {
5219 tmp = I915_READ(SOUTH_CHICKEN2);
5220 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5221 I915_WRITE(SOUTH_CHICKEN2, tmp);
5222
5223 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5224 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5225 DRM_ERROR("FDI mPHY reset assert timeout\n");
5226
5227 tmp = I915_READ(SOUTH_CHICKEN2);
5228 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5229 I915_WRITE(SOUTH_CHICKEN2, tmp);
5230
5231 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5232 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5233 100))
5234 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5235 }
5236
5237 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5238 tmp &= ~(0xFF << 24);
5239 tmp |= (0x12 << 24);
5240 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5241
dde86e2d
PZ		 5242 if (is_sdv) {
5243 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5244 tmp |= 0x7FFF;
5245 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5246 }
5247
5248 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5249 tmp |= (1 << 11);
5250 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5253 tmp |= (1 << 11);
5254 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5255
5256 if (is_sdv) {
5257 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5258 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5259 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5260
5261 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5262 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5263 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5266 tmp |= (0x3F << 8);
5267 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5270 tmp |= (0x3F << 8);
5271 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5272 }
5273
5274 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5275 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5276 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5279 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5280 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5281
5282 if (!is_sdv) {
5283 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5284 tmp &= ~(7 << 13);
5285 tmp |= (5 << 13);
5286 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5287
5288 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5289 tmp &= ~(7 << 13);
5290 tmp |= (5 << 13);
5291 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5292 }
5293
5294 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5295 tmp &= ~0xFF;
5296 tmp |= 0x1C;
5297 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5298
5299 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5300 tmp &= ~0xFF;
5301 tmp |= 0x1C;
5302 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5303
5304 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5305 tmp &= ~(0xFF << 16);
5306 tmp |= (0x1C << 16);
5307 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5308
5309 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5310 tmp &= ~(0xFF << 16);
5311 tmp |= (0x1C << 16);
5312 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5313
5314 if (!is_sdv) {
5315 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5316 tmp |= (1 << 27);
5317 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5318
5319 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5320 tmp |= (1 << 27);
5321 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5322
5323 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5324 tmp &= ~(0xF << 28);
5325 tmp |= (4 << 28);
5326 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5327
5328 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5329 tmp &= ~(0xF << 28);
5330 tmp |= (4 << 28);
5331 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5332 }
5333
5334 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5335 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5336 tmp |= SBI_DBUFF0_ENABLE;
5337 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5338
5339 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5340}
5341
5342/*
5343 * Initialize reference clocks when the driver loads
5344 */
5345void intel_init_pch_refclk(struct drm_device *dev)
5346{
5347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5348 ironlake_init_pch_refclk(dev);
5349 else if (HAS_PCH_LPT(dev))
5350 lpt_init_pch_refclk(dev);
5351}
5352
d9d444cb
JB		 5353static int ironlake_get_refclk(struct drm_crtc *crtc)
5354{
5355 struct drm_device *dev = crtc->dev;
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5357 struct intel_encoder *encoder;
d9d444cb
JB		 5358 int num_connectors = 0;
5359 bool is_lvds = false;
5360
6c2b7c12 5361 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5362 switch (encoder->type) {
5363 case INTEL_OUTPUT_LVDS:
5364 is_lvds = true;
5365 break;
d9d444cb
JB		 5366 }
5367 num_connectors++;
5368 }
5369
5370 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5371 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5372 dev_priv->vbt.lvds_ssc_freq);
5373 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5374 }
5375
5376 return 120000;
5377}
5378
6ff93609 5379static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5380{
c8203565 5381 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383 int pipe = intel_crtc->pipe;
c8203565
PZ		 5384 uint32_t val;
5385
5386 val = I915_READ(PIPECONF(pipe));
5387
dfd07d72 5388 val &= ~PIPECONF_BPC_MASK;
965e0c48 5389 switch (intel_crtc->config.pipe_bpp) {
c8203565 5390 case 18:
dfd07d72 5391 val |= PIPECONF_6BPC;
c8203565
PZ		 5392 break;
5393 case 24:
dfd07d72 5394 val |= PIPECONF_8BPC;
c8203565
PZ		 5395 break;
5396 case 30:
dfd07d72 5397 val |= PIPECONF_10BPC;
c8203565
PZ		 5398 break;
5399 case 36:
dfd07d72 5400 val |= PIPECONF_12BPC;
c8203565
PZ		 5401 break;
5402 default:
cc769b62
PZ		 5403 /* Case prevented by intel_choose_pipe_bpp_dither. */
5404 BUG();
c8203565
PZ		 5405 }
5406
5407 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5408 if (intel_crtc->config.dither)
c8203565
PZ		 5409 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5410
5411 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5412 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5413 val |= PIPECONF_INTERLACED_ILK;
5414 else
5415 val |= PIPECONF_PROGRESSIVE;
5416
50f3b016 5417 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5418 val |= PIPECONF_COLOR_RANGE_SELECT;
5419 else
5420 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5421
c8203565
PZ		 5422 I915_WRITE(PIPECONF(pipe), val);
5423 POSTING_READ(PIPECONF(pipe));
5424}
5425
86d3efce
VS		 5426/*
5427 * Set up the pipe CSC unit.
5428 *
5429 * Currently only full range RGB to limited range RGB conversion
5430 * is supported, but eventually this should handle various
5431 * RGB<->YCbCr scenarios as well.
5432 */
50f3b016 5433static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5434{
5435 struct drm_device *dev = crtc->dev;
5436 struct drm_i915_private *dev_priv = dev->dev_private;
5437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5438 int pipe = intel_crtc->pipe;
5439 uint16_t coeff = 0x7800; /* 1.0 */
5440
5441 /*
5442 * TODO: Check what kind of values actually come out of the pipe
5443 * with these coeff/postoff values and adjust to get the best
5444 * accuracy. Perhaps we even need to take the bpc value into
5445 * consideration.
5446 */
5447
50f3b016 5448 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5449 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5450
5451 /*
5452 * GY/GU and RY/RU should be the other way around according
5453 * to BSpec, but reality doesn't agree. Just set them up in
5454 * a way that results in the correct picture.
5455 */
5456 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5457 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5458
5459 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5460 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5461
5462 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5463 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5464
5465 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5466 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5467 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5468
5469 if (INTEL_INFO(dev)->gen > 6) {
5470 uint16_t postoff = 0;
5471
50f3b016 5472 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5473 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5474
5475 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5476 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5477 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5478
5479 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5480 } else {
5481 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5482
50f3b016 5483 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5484 mode |= CSC_BLACK_SCREEN_OFFSET;
5485
5486 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5487 }
5488}
5489
6ff93609 5490static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5491{
5492 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5494 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5495 uint32_t val;
5496
702e7a56 5497 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5498
5499 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5500 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5501 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5502
5503 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5504 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5505 val |= PIPECONF_INTERLACED_ILK;
5506 else
5507 val |= PIPECONF_PROGRESSIVE;
5508
702e7a56
PZ		 5509 I915_WRITE(PIPECONF(cpu_transcoder), val);
5510 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5511}
5512
6591c6e4 5513static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5514 intel_clock_t *clock,
5515 bool *has_reduced_clock,
5516 intel_clock_t *reduced_clock)
5517{
5518 struct drm_device *dev = crtc->dev;
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 struct intel_encoder *intel_encoder;
5521 int refclk;
d4906093 5522 const intel_limit_t *limit;
a16af721 5523 bool ret, is_lvds = false;
79e53945 5524
6591c6e4
PZ		 5525 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5526 switch (intel_encoder->type) {
79e53945
JB		 5527 case INTEL_OUTPUT_LVDS:
5528 is_lvds = true;
5529 break;
79e53945
JB		 5530 }
5531 }
5532
d9d444cb 5533 refclk = ironlake_get_refclk(crtc);
79e53945 5534
d4906093
ML		 5535 /*
5536 * Returns a set of divisors for the desired target clock with the given
5537 * refclk, or FALSE. The returned values represent the clock equation:
5538 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5539 */
1b894b59 5540 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5541 ret = dev_priv->display.find_dpll(limit, crtc,
5542 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5543 refclk, NULL, clock);
6591c6e4
PZ		 5544 if (!ret)
5545 return false;
cda4b7d3 5546
ddc9003c 5547 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5548 /*
5549 * Ensure we match the reduced clock's P to the target clock.
5550 * If the clocks don't match, we can't switch the display clock
5551 * by using the FP0/FP1. In such case we will disable the LVDS
5552 * downclock feature.
5553 */
ee9300bb
DV		 5554 *has_reduced_clock =
5555 dev_priv->display.find_dpll(limit, crtc,
5556 dev_priv->lvds_downclock,
5557 refclk, clock,
5558 reduced_clock);
652c393a 5559 }
61e9653f 5560
6591c6e4
PZ		 5561 return true;
5562}
5563
01a415fd
DV		 5564static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5565{
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 uint32_t temp;
5568
5569 temp = I915_READ(SOUTH_CHICKEN1);
5570 if (temp & FDI_BC_BIFURCATION_SELECT)
5571 return;
5572
5573 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5574 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5575
5576 temp |= FDI_BC_BIFURCATION_SELECT;
5577 DRM_DEBUG_KMS("enabling fdi C rx\n");
5578 I915_WRITE(SOUTH_CHICKEN1, temp);
5579 POSTING_READ(SOUTH_CHICKEN1);
5580}
5581
ebfd86fd
DV		 5582static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5583{
5584 struct drm_device *dev = intel_crtc->base.dev;
5585 struct drm_i915_private *dev_priv = dev->dev_private;
5586
5587 switch (intel_crtc->pipe) {
5588 case PIPE_A:
5589 break;
5590 case PIPE_B:
5591 if (intel_crtc->config.fdi_lanes > 2)
5592 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5593 else
5594 cpt_enable_fdi_bc_bifurcation(dev);
5595
5596 break;
5597 case PIPE_C:
01a415fd
DV		 5598 cpt_enable_fdi_bc_bifurcation(dev);
5599
ebfd86fd 5600 break;
01a415fd
DV		 5601 default:
5602 BUG();
5603 }
5604}
5605
d4b1931c
PZ		 5606int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5607{
5608 /*
5609 * Account for spread spectrum to avoid
5610 * oversubscribing the link. Max center spread
5611 * is 2.5%; use 5% for safety's sake.
5612 */
5613 u32 bps = target_clock * bpp * 21 / 20;
5614 return bps / (link_bw * 8) + 1;
5615}
5616
7429e9d4
DV		 5617static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5618{
5619 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5620}
5621
de13a2e3 5622static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5623 u32 *fp,
9a7c7890 5624 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5625{
de13a2e3 5626 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5627 struct drm_device *dev = crtc->dev;
5628 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5629 struct intel_encoder *intel_encoder;
5630 uint32_t dpll;
6cc5f341 5631 int factor, num_connectors = 0;
09ede541 5632 bool is_lvds = false, is_sdvo = false;
79e53945 5633
de13a2e3
PZ		 5634 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5635 switch (intel_encoder->type) {
79e53945
JB		 5636 case INTEL_OUTPUT_LVDS:
5637 is_lvds = true;
5638 break;
5639 case INTEL_OUTPUT_SDVO:
7d57382e 5640 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5641 is_sdvo = true;
5642 break;
79e53945 5643 }
43565a06 5644
c751ce4f 5645 num_connectors++;
79e53945 5646 }
79e53945 5647
c1858123 5648 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5649 factor = 21;
5650 if (is_lvds) {
5651 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5652 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5653 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5654 factor = 25;
09ede541 5655 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5656 factor = 20;
c1858123 5657
7429e9d4 5658 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5659 *fp |= FP_CB_TUNE;
2c07245f 5660
9a7c7890
DV		 5661 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5662 *fp2 |= FP_CB_TUNE;
5663
5eddb70b 5664 dpll = 0;
2c07245f 5665
a07d6787
EA		 5666 if (is_lvds)
5667 dpll |= DPLLB_MODE_LVDS;
5668 else
5669 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5670
ef1b460d
DV		 5671 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5672 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5673
5674 if (is_sdvo)
5675 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5676 if (intel_crtc->config.has_dp_encoder)
a07d6787 5677 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5678
a07d6787 5679 /* compute bitmask from p1 value */
7429e9d4 5680 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5681 /* also FPA1 */
7429e9d4 5682 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5683
7429e9d4 5684 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5685 case 5:
5686 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5687 break;
5688 case 7:
5689 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5690 break;
5691 case 10:
5692 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5693 break;
5694 case 14:
5695 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5696 break;
79e53945
JB		 5697 }
5698
b4c09f3b 5699 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5700 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5701 else
5702 dpll |= PLL_REF_INPUT_DREFCLK;
5703
de13a2e3
PZ		 5704 return dpll;
5705}
5706
5707static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5708 int x, int y,
5709 struct drm_framebuffer *fb)
5710{
5711 struct drm_device *dev = crtc->dev;
5712 struct drm_i915_private *dev_priv = dev->dev_private;
5713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5714 int pipe = intel_crtc->pipe;
5715 int plane = intel_crtc->plane;
5716 int num_connectors = 0;
5717 intel_clock_t clock, reduced_clock;
cbbab5bd 5718 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5719 bool ok, has_reduced_clock = false;
8b47047b 5720 bool is_lvds = false;
de13a2e3 5721 struct intel_encoder *encoder;
e2b78267 5722 struct intel_shared_dpll *pll;
de13a2e3 5723 int ret;
de13a2e3
PZ		 5724
5725 for_each_encoder_on_crtc(dev, crtc, encoder) {
5726 switch (encoder->type) {
5727 case INTEL_OUTPUT_LVDS:
5728 is_lvds = true;
5729 break;
de13a2e3
PZ		 5730 }
5731
5732 num_connectors++;
a07d6787 5733 }
79e53945 5734
5dc5298b
PZ		 5735 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5736 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5737
ff9a6750 5738 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5739 &has_reduced_clock, &reduced_clock);
ee9300bb 5740 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5741 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5742 return -EINVAL;
79e53945 5743 }
f47709a9
DV		 5744 /* Compat-code for transition, will disappear. */
5745 if (!intel_crtc->config.clock_set) {
5746 intel_crtc->config.dpll.n = clock.n;
5747 intel_crtc->config.dpll.m1 = clock.m1;
5748 intel_crtc->config.dpll.m2 = clock.m2;
5749 intel_crtc->config.dpll.p1 = clock.p1;
5750 intel_crtc->config.dpll.p2 = clock.p2;
5751 }
79e53945 5752
de13a2e3
PZ		 5753 /* Ensure that the cursor is valid for the new mode before changing... */
5754 intel_crtc_update_cursor(crtc, true);
5755
5dc5298b 5756 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5757 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5758 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5759 if (has_reduced_clock)
7429e9d4 5760 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5761
7429e9d4 5762 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5763 &fp, &reduced_clock,
5764 has_reduced_clock ? &fp2 : NULL);
5765
e72f9fbf 5766 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
ee7b9f93 5767 if (pll == NULL) {
84f44ce7
VS		 5768 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5769 pipe_name(pipe));
4b645f14
JB		 5770 return -EINVAL;
5771 }
ee7b9f93 5772 } else
e72f9fbf 5773 intel_put_shared_dpll(intel_crtc);
79e53945 5774
03afc4a2
DV		 5775 if (intel_crtc->config.has_dp_encoder)
5776 intel_dp_set_m_n(intel_crtc);
79e53945 5777
dafd226c
DV		 5778 for_each_encoder_on_crtc(dev, crtc, encoder)
5779 if (encoder->pre_pll_enable)
5780 encoder->pre_pll_enable(encoder);
79e53945 5781
e2b78267
DV		 5782 intel_crtc->lowfreq_avail = false;
5783
5784 if (intel_crtc->config.has_pch_encoder) {
5785 pll = intel_crtc_to_shared_dpll(intel_crtc);
5786
5787 I915_WRITE(pll->pll_reg, dpll);
5eddb70b 5788
32f9d658 5789 /* Wait for the clocks to stabilize. */
e2b78267 5790 POSTING_READ(pll->pll_reg);
32f9d658
ZW		 5791 udelay(150);
5792
8febb297
EA		 5793 /* The pixel multiplier can only be updated once the
5794 * DPLL is enabled and the clocks are stable.
5795 *
5796 * So write it again.
5797 */
e2b78267 5798 I915_WRITE(pll->pll_reg, dpll);
79e53945 5799
4b645f14 5800 if (is_lvds && has_reduced_clock && i915_powersave) {
e2b78267 5801 I915_WRITE(pll->fp1_reg, fp2);
4b645f14 5802 intel_crtc->lowfreq_avail = true;
4b645f14 5803 } else {
e2b78267 5804 I915_WRITE(pll->fp1_reg, fp);
652c393a
JB		 5805 }
5806 }
5807
8a654f3b 5808 intel_set_pipe_timings(intel_crtc);
5eddb70b 5809
ca3a0ff8 5810 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5811 intel_cpu_transcoder_set_m_n(intel_crtc,
5812 &intel_crtc->config.fdi_m_n);
5813 }
2c07245f 5814
ebfd86fd
DV		 5815 if (IS_IVYBRIDGE(dev))
5816 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5817
6ff93609 5818 ironlake_set_pipeconf(crtc);
79e53945 5819
a1f9e77e
PZ		 5820 /* Set up the display plane register */
5821 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5822 POSTING_READ(DSPCNTR(plane));
79e53945 5823
94352cf9 5824 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5825
5826 intel_update_watermarks(dev);
5827
1857e1da 5828 return ret;
79e53945
JB		 5829}
5830
72419203
DV		 5831static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5832 struct intel_crtc_config *pipe_config)
5833{
5834 struct drm_device *dev = crtc->base.dev;
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 enum transcoder transcoder = pipe_config->cpu_transcoder;
5837
5838 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5839 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5840 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5841 & ~TU_SIZE_MASK;
5842 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5843 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5844 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5845}
5846
2fa2fe9a
DV		 5847static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5848 struct intel_crtc_config *pipe_config)
5849{
5850 struct drm_device *dev = crtc->base.dev;
5851 struct drm_i915_private *dev_priv = dev->dev_private;
5852 uint32_t tmp;
5853
5854 tmp = I915_READ(PF_CTL(crtc->pipe));
5855
5856 if (tmp & PF_ENABLE) {
5857 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5858 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5859
5860 /* We currently do not free assignements of panel fitters on
5861 * ivb/hsw (since we don't use the higher upscaling modes which
5862 * differentiates them) so just WARN about this case for now. */
5863 if (IS_GEN7(dev)) {
5864 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5865 PF_PIPE_SEL_IVB(crtc->pipe));
5866 }
2fa2fe9a
DV		 5867 }
5868}
5869
0e8ffe1b
DV		 5870static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5871 struct intel_crtc_config *pipe_config)
5872{
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 uint32_t tmp;
5876
eccb140b 5877 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5878 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5879
0e8ffe1b
DV		 5880 tmp = I915_READ(PIPECONF(crtc->pipe));
5881 if (!(tmp & PIPECONF_ENABLE))
5882 return false;
5883
ab9412ba 5884 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5885 pipe_config->has_pch_encoder = true;
5886
627eb5a3
DV		 5887 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5888 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5889 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5890
5891 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5892
5893 /* XXX: Can't properly read out the pch dpll pixel multiplier
5894 * since we don't have state tracking for pch clocks yet. */
5895 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5896
5897 if (HAS_PCH_IBX(dev_priv->dev)) {
5898 pipe_config->shared_dpll = crtc->pipe;
5899 } else {
5900 tmp = I915_READ(PCH_DPLL_SEL);
5901 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5902 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5903 else
5904 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5905 }
6c49f241
DV		 5906 } else {
5907 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5908 }
5909
1bd1bd80
DV		 5910 intel_get_pipe_timings(crtc, pipe_config);
5911
2fa2fe9a
DV		 5912 ironlake_get_pfit_config(crtc, pipe_config);
5913
0e8ffe1b
DV		 5914 return true;
5915}
5916
d6dd9eb1
DV		 5917static void haswell_modeset_global_resources(struct drm_device *dev)
5918{
d6dd9eb1
DV		 5919 bool enable = false;
5920 struct intel_crtc *crtc;
d6dd9eb1
DV		 5921
5922 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5923 if (!crtc->base.enabled)
5924 continue;
d6dd9eb1 5925
e7a639c4
DV		 5926 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5927 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5928 enable = true;
5929 }
5930
d6dd9eb1
DV		 5931 intel_set_power_well(dev, enable);
5932}
5933
09b4ddf9 5934static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5935 int x, int y,
5936 struct drm_framebuffer *fb)
5937{
5938 struct drm_device *dev = crtc->dev;
5939 struct drm_i915_private *dev_priv = dev->dev_private;
5940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5941 int plane = intel_crtc->plane;
09b4ddf9 5942 int ret;
09b4ddf9 5943
ff9a6750 5944 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5945 return -EINVAL;
5946
09b4ddf9
PZ		 5947 /* Ensure that the cursor is valid for the new mode before changing... */
5948 intel_crtc_update_cursor(crtc, true);
5949
03afc4a2
DV		 5950 if (intel_crtc->config.has_dp_encoder)
5951 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5952
5953 intel_crtc->lowfreq_avail = false;
09b4ddf9 5954
8a654f3b 5955 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5956
ca3a0ff8 5957 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5958 intel_cpu_transcoder_set_m_n(intel_crtc,
5959 &intel_crtc->config.fdi_m_n);
5960 }
09b4ddf9 5961
6ff93609 5962 haswell_set_pipeconf(crtc);
09b4ddf9 5963
50f3b016 5964 intel_set_pipe_csc(crtc);
86d3efce 5965
09b4ddf9 5966 /* Set up the display plane register */
86d3efce 5967 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5968 POSTING_READ(DSPCNTR(plane));
5969
5970 ret = intel_pipe_set_base(crtc, x, y, fb);
5971
5972 intel_update_watermarks(dev);
5973
1f803ee5 5974 return ret;
79e53945
JB		 5975}
5976
0e8ffe1b
DV		 5977static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5978 struct intel_crtc_config *pipe_config)
5979{
5980 struct drm_device *dev = crtc->base.dev;
5981 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5982 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5983 uint32_t tmp;
5984
eccb140b 5985 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5986 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5987
eccb140b
DV		 5988 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5989 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5990 enum pipe trans_edp_pipe;
5991 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5992 default:
5993 WARN(1, "unknown pipe linked to edp transcoder\n");
5994 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5995 case TRANS_DDI_EDP_INPUT_A_ON:
5996 trans_edp_pipe = PIPE_A;
5997 break;
5998 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5999 trans_edp_pipe = PIPE_B;
6000 break;
6001 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6002 trans_edp_pipe = PIPE_C;
6003 break;
6004 }
6005
6006 if (trans_edp_pipe == crtc->pipe)
6007 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6008 }
6009
b97186f0 6010 if (!intel_display_power_enabled(dev,
eccb140b 6011 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6012 return false;
6013
eccb140b 6014 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6015 if (!(tmp & PIPECONF_ENABLE))
6016 return false;
6017
88adfff1 6018 /*
f196e6be 6019 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6020 * DDI E. So just check whether this pipe is wired to DDI E and whether
6021 * the PCH transcoder is on.
6022 */
eccb140b 6023 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6024 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6025 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6026 pipe_config->has_pch_encoder = true;
6027
627eb5a3
DV		 6028 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6029 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6030 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6031
6032 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6033 }
6034
1bd1bd80
DV		 6035 intel_get_pipe_timings(crtc, pipe_config);
6036
2fa2fe9a
DV		 6037 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6038 if (intel_display_power_enabled(dev, pfit_domain))
6039 ironlake_get_pfit_config(crtc, pipe_config);
6040
42db64ef
PZ		 6041 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6042 (I915_READ(IPS_CTL) & IPS_ENABLE);
6043
6c49f241
DV		 6044 pipe_config->pixel_multiplier = 1;
6045
0e8ffe1b
DV		 6046 return true;
6047}
6048
f564048e 6049static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6050 int x, int y,
94352cf9 6051 struct drm_framebuffer *fb)
f564048e
EA		 6052{
6053 struct drm_device *dev = crtc->dev;
6054 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6055 struct drm_encoder_helper_funcs *encoder_funcs;
6056 struct intel_encoder *encoder;
0b701d27 6057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6058 struct drm_display_mode *adjusted_mode =
6059 &intel_crtc->config.adjusted_mode;
6060 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6061 int pipe = intel_crtc->pipe;
f564048e
EA		 6062 int ret;
6063
0b701d27 6064 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6065
b8cecdf5
DV		 6066 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6067
79e53945 6068 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6069
9256aa19
DV		 6070 if (ret != 0)
6071 return ret;
6072
6073 for_each_encoder_on_crtc(dev, crtc, encoder) {
6074 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6075 encoder->base.base.id,
6076 drm_get_encoder_name(&encoder->base),
6077 mode->base.id, mode->name);
6cc5f341
DV		 6078 if (encoder->mode_set) {
6079 encoder->mode_set(encoder);
6080 } else {
6081 encoder_funcs = encoder->base.helper_private;
6082 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6083 }
9256aa19
DV		 6084 }
6085
6086 return 0;
79e53945
JB		 6087}
6088
3a9627f4
WF		 6089static bool intel_eld_uptodate(struct drm_connector *connector,
6090 int reg_eldv, uint32_t bits_eldv,
6091 int reg_elda, uint32_t bits_elda,
6092 int reg_edid)
6093{
6094 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6095 uint8_t *eld = connector->eld;
6096 uint32_t i;
6097
6098 i = I915_READ(reg_eldv);
6099 i &= bits_eldv;
6100
6101 if (!eld[0])
6102 return !i;
6103
6104 if (!i)
6105 return false;
6106
6107 i = I915_READ(reg_elda);
6108 i &= ~bits_elda;
6109 I915_WRITE(reg_elda, i);
6110
6111 for (i = 0; i < eld[2]; i++)
6112 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6113 return false;
6114
6115 return true;
6116}
6117
e0dac65e
WF		 6118static void g4x_write_eld(struct drm_connector *connector,
6119 struct drm_crtc *crtc)
6120{
6121 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6122 uint8_t *eld = connector->eld;
6123 uint32_t eldv;
6124 uint32_t len;
6125 uint32_t i;
6126
6127 i = I915_READ(G4X_AUD_VID_DID);
6128
6129 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6130 eldv = G4X_ELDV_DEVCL_DEVBLC;
6131 else
6132 eldv = G4X_ELDV_DEVCTG;
6133
3a9627f4
WF		 6134 if (intel_eld_uptodate(connector,
6135 G4X_AUD_CNTL_ST, eldv,
6136 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6137 G4X_HDMIW_HDMIEDID))
6138 return;
6139
e0dac65e
WF		 6140 i = I915_READ(G4X_AUD_CNTL_ST);
6141 i &= ~(eldv | G4X_ELD_ADDR);
6142 len = (i >> 9) & 0x1f; /* ELD buffer size */
6143 I915_WRITE(G4X_AUD_CNTL_ST, i);
6144
6145 if (!eld[0])
6146 return;
6147
6148 len = min_t(uint8_t, eld[2], len);
6149 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6150 for (i = 0; i < len; i++)
6151 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6152
6153 i = I915_READ(G4X_AUD_CNTL_ST);
6154 i |= eldv;
6155 I915_WRITE(G4X_AUD_CNTL_ST, i);
6156}
6157
83358c85
WX		 6158static void haswell_write_eld(struct drm_connector *connector,
6159 struct drm_crtc *crtc)
6160{
6161 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6162 uint8_t *eld = connector->eld;
6163 struct drm_device *dev = crtc->dev;
7b9f35a6 6164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6165 uint32_t eldv;
6166 uint32_t i;
6167 int len;
6168 int pipe = to_intel_crtc(crtc)->pipe;
6169 int tmp;
6170
6171 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6172 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6173 int aud_config = HSW_AUD_CFG(pipe);
6174 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6175
6176
6177 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6178
6179 /* Audio output enable */
6180 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6181 tmp = I915_READ(aud_cntrl_st2);
6182 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6183 I915_WRITE(aud_cntrl_st2, tmp);
6184
6185 /* Wait for 1 vertical blank */
6186 intel_wait_for_vblank(dev, pipe);
6187
6188 /* Set ELD valid state */
6189 tmp = I915_READ(aud_cntrl_st2);
6190 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6191 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6192 I915_WRITE(aud_cntrl_st2, tmp);
6193 tmp = I915_READ(aud_cntrl_st2);
6194 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6195
6196 /* Enable HDMI mode */
6197 tmp = I915_READ(aud_config);
6198 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6199 /* clear N_programing_enable and N_value_index */
6200 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6201 I915_WRITE(aud_config, tmp);
6202
6203 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6204
6205 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6206 intel_crtc->eld_vld = true;
83358c85
WX		 6207
6208 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6209 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6210 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6211 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6212 } else
6213 I915_WRITE(aud_config, 0);
6214
6215 if (intel_eld_uptodate(connector,
6216 aud_cntrl_st2, eldv,
6217 aud_cntl_st, IBX_ELD_ADDRESS,
6218 hdmiw_hdmiedid))
6219 return;
6220
6221 i = I915_READ(aud_cntrl_st2);
6222 i &= ~eldv;
6223 I915_WRITE(aud_cntrl_st2, i);
6224
6225 if (!eld[0])
6226 return;
6227
6228 i = I915_READ(aud_cntl_st);
6229 i &= ~IBX_ELD_ADDRESS;
6230 I915_WRITE(aud_cntl_st, i);
6231 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6232 DRM_DEBUG_DRIVER("port num:%d\n", i);
6233
6234 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6235 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6236 for (i = 0; i < len; i++)
6237 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6238
6239 i = I915_READ(aud_cntrl_st2);
6240 i |= eldv;
6241 I915_WRITE(aud_cntrl_st2, i);
6242
6243}
6244
e0dac65e
WF		 6245static void ironlake_write_eld(struct drm_connector *connector,
6246 struct drm_crtc *crtc)
6247{
6248 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6249 uint8_t *eld = connector->eld;
6250 uint32_t eldv;
6251 uint32_t i;
6252 int len;
6253 int hdmiw_hdmiedid;
b6daa025 6254 int aud_config;
e0dac65e
WF		 6255 int aud_cntl_st;
6256 int aud_cntrl_st2;
9b138a83 6257 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6258
b3f33cbf 6259 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6260 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6261 aud_config = IBX_AUD_CFG(pipe);
6262 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6263 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6264 } else {
9b138a83
WX		 6265 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6266 aud_config = CPT_AUD_CFG(pipe);
6267 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6268 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6269 }
6270
9b138a83 6271 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6272
6273 i = I915_READ(aud_cntl_st);
9b138a83 6274 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6275 if (!i) {
6276 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6277 /* operate blindly on all ports */
1202b4c6
WF		 6278 eldv = IBX_ELD_VALIDB;
6279 eldv |= IBX_ELD_VALIDB << 4;
6280 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6281 } else {
2582a850 6282 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6283 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6284 }
6285
3a9627f4
WF		 6286 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6287 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6288 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6289 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6290 } else
6291 I915_WRITE(aud_config, 0);
e0dac65e 6292
3a9627f4
WF		 6293 if (intel_eld_uptodate(connector,
6294 aud_cntrl_st2, eldv,
6295 aud_cntl_st, IBX_ELD_ADDRESS,
6296 hdmiw_hdmiedid))
6297 return;
6298
e0dac65e
WF		 6299 i = I915_READ(aud_cntrl_st2);
6300 i &= ~eldv;
6301 I915_WRITE(aud_cntrl_st2, i);
6302
6303 if (!eld[0])
6304 return;
6305
e0dac65e 6306 i = I915_READ(aud_cntl_st);
1202b4c6 6307 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6308 I915_WRITE(aud_cntl_st, i);
6309
6310 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6311 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6312 for (i = 0; i < len; i++)
6313 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6314
6315 i = I915_READ(aud_cntrl_st2);
6316 i |= eldv;
6317 I915_WRITE(aud_cntrl_st2, i);
6318}
6319
6320void intel_write_eld(struct drm_encoder *encoder,
6321 struct drm_display_mode *mode)
6322{
6323 struct drm_crtc *crtc = encoder->crtc;
6324 struct drm_connector *connector;
6325 struct drm_device *dev = encoder->dev;
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327
6328 connector = drm_select_eld(encoder, mode);
6329 if (!connector)
6330 return;
6331
6332 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6333 connector->base.id,
6334 drm_get_connector_name(connector),
6335 connector->encoder->base.id,
6336 drm_get_encoder_name(connector->encoder));
6337
6338 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6339
6340 if (dev_priv->display.write_eld)
6341 dev_priv->display.write_eld(connector, crtc);
6342}
6343
79e53945
JB		 6344/** Loads the palette/gamma unit for the CRTC with the prepared values */
6345void intel_crtc_load_lut(struct drm_crtc *crtc)
6346{
6347 struct drm_device *dev = crtc->dev;
6348 struct drm_i915_private *dev_priv = dev->dev_private;
6349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6350 enum pipe pipe = intel_crtc->pipe;
6351 int palreg = PALETTE(pipe);
79e53945 6352 int i;
42db64ef 6353 bool reenable_ips = false;
79e53945
JB		 6354
6355 /* The clocks have to be on to load the palette. */
aed3f09d 6356 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6357 return;
6358
14420bd0
VS		 6359 if (!HAS_PCH_SPLIT(dev_priv->dev))
6360 assert_pll_enabled(dev_priv, pipe);
6361
f2b115e6 6362 /* use legacy palette for Ironlake */
bad720ff 6363 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6364 palreg = LGC_PALETTE(pipe);
6365
6366 /* Workaround : Do not read or write the pipe palette/gamma data while
6367 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6368 */
6369 if (intel_crtc->config.ips_enabled &&
6370 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6371 GAMMA_MODE_MODE_SPLIT)) {
6372 hsw_disable_ips(intel_crtc);
6373 reenable_ips = true;
6374 }
2c07245f 6375
79e53945
JB		 6376 for (i = 0; i < 256; i++) {
6377 I915_WRITE(palreg + 4 * i,
6378 (intel_crtc->lut_r[i] << 16) |
6379 (intel_crtc->lut_g[i] << 8) |
6380 intel_crtc->lut_b[i]);
6381 }
42db64ef
PZ		 6382
6383 if (reenable_ips)
6384 hsw_enable_ips(intel_crtc);
79e53945
JB		 6385}
6386
560b85bb
CW		 6387static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6388{
6389 struct drm_device *dev = crtc->dev;
6390 struct drm_i915_private *dev_priv = dev->dev_private;
6391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6392 bool visible = base != 0;
6393 u32 cntl;
6394
6395 if (intel_crtc->cursor_visible == visible)
6396 return;
6397
9db4a9c7 6398 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6399 if (visible) {
6400 /* On these chipsets we can only modify the base whilst
6401 * the cursor is disabled.
6402 */
9db4a9c7 6403 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6404
6405 cntl &= ~(CURSOR_FORMAT_MASK);
6406 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6407 cntl |= CURSOR_ENABLE |
6408 CURSOR_GAMMA_ENABLE |
6409 CURSOR_FORMAT_ARGB;
6410 } else
6411 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6412 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6413
6414 intel_crtc->cursor_visible = visible;
6415}
6416
6417static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6418{
6419 struct drm_device *dev = crtc->dev;
6420 struct drm_i915_private *dev_priv = dev->dev_private;
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422 int pipe = intel_crtc->pipe;
6423 bool visible = base != 0;
6424
6425 if (intel_crtc->cursor_visible != visible) {
548f245b 6426 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6427 if (base) {
6428 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6429 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6430 cntl |= pipe << 28; /* Connect to correct pipe */
6431 } else {
6432 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6433 cntl |= CURSOR_MODE_DISABLE;
6434 }
9db4a9c7 6435 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6436
6437 intel_crtc->cursor_visible = visible;
6438 }
6439 /* and commit changes on next vblank */
9db4a9c7 6440 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6441}
6442
65a21cd6
JB		 6443static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6444{
6445 struct drm_device *dev = crtc->dev;
6446 struct drm_i915_private *dev_priv = dev->dev_private;
6447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6448 int pipe = intel_crtc->pipe;
6449 bool visible = base != 0;
6450
6451 if (intel_crtc->cursor_visible != visible) {
6452 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6453 if (base) {
6454 cntl &= ~CURSOR_MODE;
6455 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6456 } else {
6457 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6458 cntl |= CURSOR_MODE_DISABLE;
6459 }
86d3efce
VS		 6460 if (IS_HASWELL(dev))
6461 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6462 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6463
6464 intel_crtc->cursor_visible = visible;
6465 }
6466 /* and commit changes on next vblank */
6467 I915_WRITE(CURBASE_IVB(pipe), base);
6468}
6469
cda4b7d3 6470/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6471static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6472 bool on)
cda4b7d3
CW		 6473{
6474 struct drm_device *dev = crtc->dev;
6475 struct drm_i915_private *dev_priv = dev->dev_private;
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477 int pipe = intel_crtc->pipe;
6478 int x = intel_crtc->cursor_x;
6479 int y = intel_crtc->cursor_y;
560b85bb 6480 u32 base, pos;
cda4b7d3
CW		 6481 bool visible;
6482
6483 pos = 0;
6484
6b383a7f 6485 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6486 base = intel_crtc->cursor_addr;
6487 if (x > (int) crtc->fb->width)
6488 base = 0;
6489
6490 if (y > (int) crtc->fb->height)
6491 base = 0;
6492 } else
6493 base = 0;
6494
6495 if (x < 0) {
6496 if (x + intel_crtc->cursor_width < 0)
6497 base = 0;
6498
6499 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6500 x = -x;
6501 }
6502 pos |= x << CURSOR_X_SHIFT;
6503
6504 if (y < 0) {
6505 if (y + intel_crtc->cursor_height < 0)
6506 base = 0;
6507
6508 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6509 y = -y;
6510 }
6511 pos |= y << CURSOR_Y_SHIFT;
6512
6513 visible = base != 0;
560b85bb 6514 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6515 return;
6516
0cd83aa9 6517 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6518 I915_WRITE(CURPOS_IVB(pipe), pos);
6519 ivb_update_cursor(crtc, base);
6520 } else {
6521 I915_WRITE(CURPOS(pipe), pos);
6522 if (IS_845G(dev) || IS_I865G(dev))
6523 i845_update_cursor(crtc, base);
6524 else
6525 i9xx_update_cursor(crtc, base);
6526 }
cda4b7d3
CW		 6527}
6528
79e53945 6529static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6530 struct drm_file *file,
79e53945
JB		 6531 uint32_t handle,
6532 uint32_t width, uint32_t height)
6533{
6534 struct drm_device *dev = crtc->dev;
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6537 struct drm_i915_gem_object *obj;
cda4b7d3 6538 uint32_t addr;
3f8bc370 6539 int ret;
79e53945 6540
79e53945
JB		 6541 /* if we want to turn off the cursor ignore width and height */
6542 if (!handle) {
28c97730 6543 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6544 addr = 0;
05394f39 6545 obj = NULL;
5004417d 6546 mutex_lock(&dev->struct_mutex);
3f8bc370 6547 goto finish;
79e53945
JB		 6548 }
6549
6550 /* Currently we only support 64x64 cursors */
6551 if (width != 64 || height != 64) {
6552 DRM_ERROR("we currently only support 64x64 cursors\n");
6553 return -EINVAL;
6554 }
6555
05394f39 6556 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6557 if (&obj->base == NULL)
79e53945
JB		 6558 return -ENOENT;
6559
05394f39 6560 if (obj->base.size < width * height * 4) {
79e53945 6561 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6562 ret = -ENOMEM;
6563 goto fail;
79e53945
JB		 6564 }
6565
71acb5eb 6566 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6567 mutex_lock(&dev->struct_mutex);
b295d1b6 6568 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6569 unsigned alignment;
6570
d9e86c0e
CW		 6571 if (obj->tiling_mode) {
6572 DRM_ERROR("cursor cannot be tiled\n");
6573 ret = -EINVAL;
6574 goto fail_locked;
6575 }
6576
693db184
CW		 6577 /* Note that the w/a also requires 2 PTE of padding following
6578 * the bo. We currently fill all unused PTE with the shadow
6579 * page and so we should always have valid PTE following the
6580 * cursor preventing the VT-d warning.
6581 */
6582 alignment = 0;
6583 if (need_vtd_wa(dev))
6584 alignment = 64*1024;
6585
6586 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6587 if (ret) {
6588 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6589 goto fail_locked;
e7b526bb
CW		 6590 }
6591
d9e86c0e
CW		 6592 ret = i915_gem_object_put_fence(obj);
6593 if (ret) {
2da3b9b9 6594 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6595 goto fail_unpin;
6596 }
6597
05394f39 6598 addr = obj->gtt_offset;
71acb5eb 6599 } else {
6eeefaf3 6600 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6601 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6602 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6603 align);
71acb5eb
DA		 6604 if (ret) {
6605 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6606 goto fail_locked;
71acb5eb 6607 }
05394f39 6608 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6609 }
6610
a6c45cf0 6611 if (IS_GEN2(dev))
14b60391
JB		 6612 I915_WRITE(CURSIZE, (height << 12) | width);
6613
3f8bc370 6614 finish:
3f8bc370 6615 if (intel_crtc->cursor_bo) {
b295d1b6 6616 if (dev_priv->info->cursor_needs_physical) {
05394f39 6617 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6618 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6619 } else
6620 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6621 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6622 }
80824003 6623
7f9872e0 6624 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6625
6626 intel_crtc->cursor_addr = addr;
05394f39 6627 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6628 intel_crtc->cursor_width = width;
6629 intel_crtc->cursor_height = height;
6630
40ccc72b 6631 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6632
79e53945 6633 return 0;
e7b526bb 6634fail_unpin:
05394f39 6635 i915_gem_object_unpin(obj);
7f9872e0 6636fail_locked:
34b8686e 6637 mutex_unlock(&dev->struct_mutex);
bc9025bd 6638fail:
05394f39 6639 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6640 return ret;
79e53945
JB		 6641}
6642
6643static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6644{
79e53945 6645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6646
cda4b7d3
CW		 6647 intel_crtc->cursor_x = x;
6648 intel_crtc->cursor_y = y;
652c393a 6649
40ccc72b 6650 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6651
6652 return 0;
6653}
6654
6655/** Sets the color ramps on behalf of RandR */
6656void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6657 u16 blue, int regno)
6658{
6659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6660
6661 intel_crtc->lut_r[regno] = red >> 8;
6662 intel_crtc->lut_g[regno] = green >> 8;
6663 intel_crtc->lut_b[regno] = blue >> 8;
6664}
6665
b8c00ac5
DA		 6666void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6667 u16 *blue, int regno)
6668{
6669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6670
6671 *red = intel_crtc->lut_r[regno] << 8;
6672 *green = intel_crtc->lut_g[regno] << 8;
6673 *blue = intel_crtc->lut_b[regno] << 8;
6674}
6675
79e53945 6676static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6677 u16 *blue, uint32_t start, uint32_t size)
79e53945 6678{
7203425a 6679 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6681
7203425a 6682 for (i = start; i < end; i++) {
79e53945
JB		 6683 intel_crtc->lut_r[i] = red[i] >> 8;
6684 intel_crtc->lut_g[i] = green[i] >> 8;
6685 intel_crtc->lut_b[i] = blue[i] >> 8;
6686 }
6687
6688 intel_crtc_load_lut(crtc);
6689}
6690
79e53945
JB		 6691/* VESA 640x480x72Hz mode to set on the pipe */
6692static struct drm_display_mode load_detect_mode = {
6693 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6694 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6695};
6696
d2dff872
CW		 6697static struct drm_framebuffer *
6698intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6699 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6700 struct drm_i915_gem_object *obj)
6701{
6702 struct intel_framebuffer *intel_fb;
6703 int ret;
6704
6705 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6706 if (!intel_fb) {
6707 drm_gem_object_unreference_unlocked(&obj->base);
6708 return ERR_PTR(-ENOMEM);
6709 }
6710
6711 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6712 if (ret) {
6713 drm_gem_object_unreference_unlocked(&obj->base);
6714 kfree(intel_fb);
6715 return ERR_PTR(ret);
6716 }
6717
6718 return &intel_fb->base;
6719}
6720
6721static u32
6722intel_framebuffer_pitch_for_width(int width, int bpp)
6723{
6724 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6725 return ALIGN(pitch, 64);
6726}
6727
6728static u32
6729intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6730{
6731 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6732 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6733}
6734
6735static struct drm_framebuffer *
6736intel_framebuffer_create_for_mode(struct drm_device *dev,
6737 struct drm_display_mode *mode,
6738 int depth, int bpp)
6739{
6740 struct drm_i915_gem_object *obj;
0fed39bd 6741 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6742
6743 obj = i915_gem_alloc_object(dev,
6744 intel_framebuffer_size_for_mode(mode, bpp));
6745 if (obj == NULL)
6746 return ERR_PTR(-ENOMEM);
6747
6748 mode_cmd.width = mode->hdisplay;
6749 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6750 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6751 bpp);
5ca0c34a 6752 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6753
6754 return intel_framebuffer_create(dev, &mode_cmd, obj);
6755}
6756
6757static struct drm_framebuffer *
6758mode_fits_in_fbdev(struct drm_device *dev,
6759 struct drm_display_mode *mode)
6760{
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 struct drm_i915_gem_object *obj;
6763 struct drm_framebuffer *fb;
6764
6765 if (dev_priv->fbdev == NULL)
6766 return NULL;
6767
6768 obj = dev_priv->fbdev->ifb.obj;
6769 if (obj == NULL)
6770 return NULL;
6771
6772 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6773 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6774 fb->bits_per_pixel))
d2dff872
CW		 6775 return NULL;
6776
01f2c773 6777 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6778 return NULL;
6779
6780 return fb;
6781}
6782
d2434ab7 6783bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6784 struct drm_display_mode *mode,
8261b191 6785 struct intel_load_detect_pipe *old)
79e53945
JB		 6786{
6787 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6788 struct intel_encoder *intel_encoder =
6789 intel_attached_encoder(connector);
79e53945 6790 struct drm_crtc *possible_crtc;
4ef69c7a 6791 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6792 struct drm_crtc *crtc = NULL;
6793 struct drm_device *dev = encoder->dev;
94352cf9 6794 struct drm_framebuffer *fb;
79e53945
JB		 6795 int i = -1;
6796
d2dff872
CW		 6797 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6798 connector->base.id, drm_get_connector_name(connector),
6799 encoder->base.id, drm_get_encoder_name(encoder));
6800
79e53945
JB		 6801 /*
6802 * Algorithm gets a little messy:
7a5e4805 6803 *
79e53945
JB		 6804 * - if the connector already has an assigned crtc, use it (but make
6805 * sure it's on first)
7a5e4805 6806 *
79e53945
JB		 6807 * - try to find the first unused crtc that can drive this connector,
6808 * and use that if we find one
79e53945
JB		 6809 */
6810
6811 /* See if we already have a CRTC for this connector */
6812 if (encoder->crtc) {
6813 crtc = encoder->crtc;
8261b191 6814
7b24056b
DV		 6815 mutex_lock(&crtc->mutex);
6816
24218aac 6817 old->dpms_mode = connector->dpms;
8261b191
CW		 6818 old->load_detect_temp = false;
6819
6820 /* Make sure the crtc and connector are running */
24218aac
DV		 6821 if (connector->dpms != DRM_MODE_DPMS_ON)
6822 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6823
7173188d 6824 return true;
79e53945
JB		 6825 }
6826
6827 /* Find an unused one (if possible) */
6828 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6829 i++;
6830 if (!(encoder->possible_crtcs & (1 << i)))
6831 continue;
6832 if (!possible_crtc->enabled) {
6833 crtc = possible_crtc;
6834 break;
6835 }
79e53945
JB		 6836 }
6837
6838 /*
6839 * If we didn't find an unused CRTC, don't use any.
6840 */
6841 if (!crtc) {
7173188d
CW		 6842 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6843 return false;
79e53945
JB		 6844 }
6845
7b24056b 6846 mutex_lock(&crtc->mutex);
fc303101
DV		 6847 intel_encoder->new_crtc = to_intel_crtc(crtc);
6848 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6849
6850 intel_crtc = to_intel_crtc(crtc);
24218aac 6851 old->dpms_mode = connector->dpms;
8261b191 6852 old->load_detect_temp = true;
d2dff872 6853 old->release_fb = NULL;
79e53945 6854
6492711d
CW		 6855 if (!mode)
6856 mode = &load_detect_mode;
79e53945 6857
d2dff872
CW		 6858 /* We need a framebuffer large enough to accommodate all accesses
6859 * that the plane may generate whilst we perform load detection.
6860 * We can not rely on the fbcon either being present (we get called
6861 * during its initialisation to detect all boot displays, or it may
6862 * not even exist) or that it is large enough to satisfy the
6863 * requested mode.
6864 */
94352cf9
DV		 6865 fb = mode_fits_in_fbdev(dev, mode);
6866 if (fb == NULL) {
d2dff872 6867 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6868 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6869 old->release_fb = fb;
d2dff872
CW		 6870 } else
6871 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6872 if (IS_ERR(fb)) {
d2dff872 6873 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6874 mutex_unlock(&crtc->mutex);
0e8b3d3e 6875 return false;
79e53945 6876 }
79e53945 6877
c0c36b94 6878 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6879 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6880 if (old->release_fb)
6881 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6882 mutex_unlock(&crtc->mutex);
0e8b3d3e 6883 return false;
79e53945 6884 }
7173188d 6885
79e53945 6886 /* let the connector get through one full cycle before testing */
9d0498a2 6887 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6888 return true;
79e53945
JB		 6889}
6890
d2434ab7 6891void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6892 struct intel_load_detect_pipe *old)
79e53945 6893{
d2434ab7
DV		 6894 struct intel_encoder *intel_encoder =
6895 intel_attached_encoder(connector);
4ef69c7a 6896 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6897 struct drm_crtc *crtc = encoder->crtc;
79e53945 6898
d2dff872
CW		 6899 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6900 connector->base.id, drm_get_connector_name(connector),
6901 encoder->base.id, drm_get_encoder_name(encoder));
6902
8261b191 6903 if (old->load_detect_temp) {
fc303101
DV		 6904 to_intel_connector(connector)->new_encoder = NULL;
6905 intel_encoder->new_crtc = NULL;
6906 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6907
36206361
DV		 6908 if (old->release_fb) {
6909 drm_framebuffer_unregister_private(old->release_fb);
6910 drm_framebuffer_unreference(old->release_fb);
6911 }
d2dff872 6912
67c96400 6913 mutex_unlock(&crtc->mutex);
0622a53c 6914 return;
79e53945
JB		 6915 }
6916
c751ce4f 6917 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6918 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6919 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6920
6921 mutex_unlock(&crtc->mutex);
79e53945
JB		 6922}
6923
6924/* Returns the clock of the currently programmed mode of the given pipe. */
6925static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6926{
6927 struct drm_i915_private *dev_priv = dev->dev_private;
6928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6929 int pipe = intel_crtc->pipe;
548f245b 6930 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6931 u32 fp;
6932 intel_clock_t clock;
6933
6934 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6935 fp = I915_READ(FP0(pipe));
79e53945 6936 else
39adb7a5 6937 fp = I915_READ(FP1(pipe));
79e53945
JB		 6938
6939 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6940 if (IS_PINEVIEW(dev)) {
6941 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6942 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6943 } else {
6944 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6945 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6946 }
6947
a6c45cf0 6948 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6949 if (IS_PINEVIEW(dev))
6950 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6951 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6952 else
6953 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6954 DPLL_FPA01_P1_POST_DIV_SHIFT);
6955
6956 switch (dpll & DPLL_MODE_MASK) {
6957 case DPLLB_MODE_DAC_SERIAL:
6958 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6959 5 : 10;
6960 break;
6961 case DPLLB_MODE_LVDS:
6962 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6963 7 : 14;
6964 break;
6965 default:
28c97730 6966 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6967 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6968 return 0;
6969 }
6970
ac58c3f0
DV		 6971 if (IS_PINEVIEW(dev))
6972 pineview_clock(96000, &clock);
6973 else
6974 i9xx_clock(96000, &clock);
79e53945
JB		 6975 } else {
6976 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6977
6978 if (is_lvds) {
6979 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6980 DPLL_FPA01_P1_POST_DIV_SHIFT);
6981 clock.p2 = 14;
6982
6983 if ((dpll & PLL_REF_INPUT_MASK) ==
6984 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6985 /* XXX: might not be 66MHz */
ac58c3f0 6986 i9xx_clock(66000, &clock);
79e53945 6987 } else
ac58c3f0 6988 i9xx_clock(48000, &clock);
79e53945
JB		 6989 } else {
6990 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6991 clock.p1 = 2;
6992 else {
6993 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6994 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6995 }
6996 if (dpll & PLL_P2_DIVIDE_BY_4)
6997 clock.p2 = 4;
6998 else
6999 clock.p2 = 2;
7000
ac58c3f0 7001 i9xx_clock(48000, &clock);
79e53945
JB		 7002 }
7003 }
7004
7005 /* XXX: It would be nice to validate the clocks, but we can't reuse
7006 * i830PllIsValid() because it relies on the xf86_config connector
7007 * configuration being accurate, which it isn't necessarily.
7008 */
7009
7010 return clock.dot;
7011}
7012
7013/** Returns the currently programmed mode of the given pipe. */
7014struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7015 struct drm_crtc *crtc)
7016{
548f245b 7017 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7019 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7020 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7021 int htot = I915_READ(HTOTAL(cpu_transcoder));
7022 int hsync = I915_READ(HSYNC(cpu_transcoder));
7023 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7024 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7025
7026 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7027 if (!mode)
7028 return NULL;
7029
7030 mode->clock = intel_crtc_clock_get(dev, crtc);
7031 mode->hdisplay = (htot & 0xffff) + 1;
7032 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7033 mode->hsync_start = (hsync & 0xffff) + 1;
7034 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7035 mode->vdisplay = (vtot & 0xffff) + 1;
7036 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7037 mode->vsync_start = (vsync & 0xffff) + 1;
7038 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7039
7040 drm_mode_set_name(mode);
79e53945
JB		 7041
7042 return mode;
7043}
7044
3dec0095 7045static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7046{
7047 struct drm_device *dev = crtc->dev;
7048 drm_i915_private_t *dev_priv = dev->dev_private;
7049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7051 int dpll_reg = DPLL(pipe);
7052 int dpll;
652c393a 7053
bad720ff 7054 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7055 return;
7056
7057 if (!dev_priv->lvds_downclock_avail)
7058 return;
7059
dbdc6479 7060 dpll = I915_READ(dpll_reg);
652c393a 7061 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7062 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7063
8ac5a6d5 7064 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7065
7066 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7067 I915_WRITE(dpll_reg, dpll);
9d0498a2 7068 intel_wait_for_vblank(dev, pipe);
dbdc6479 7069
652c393a
JB		 7070 dpll = I915_READ(dpll_reg);
7071 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7072 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7073 }
652c393a
JB		 7074}
7075
7076static void intel_decrease_pllclock(struct drm_crtc *crtc)
7077{
7078 struct drm_device *dev = crtc->dev;
7079 drm_i915_private_t *dev_priv = dev->dev_private;
7080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7081
bad720ff 7082 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7083 return;
7084
7085 if (!dev_priv->lvds_downclock_avail)
7086 return;
7087
7088 /*
7089 * Since this is called by a timer, we should never get here in
7090 * the manual case.
7091 */
7092 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7093 int pipe = intel_crtc->pipe;
7094 int dpll_reg = DPLL(pipe);
7095 int dpll;
f6e5b160 7096
44d98a61 7097 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7098
8ac5a6d5 7099 assert_panel_unlocked(dev_priv, pipe);
652c393a 7100
dc257cf1 7101 dpll = I915_READ(dpll_reg);
652c393a
JB		 7102 dpll |= DISPLAY_RATE_SELECT_FPA1;
7103 I915_WRITE(dpll_reg, dpll);
9d0498a2 7104 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7105 dpll = I915_READ(dpll_reg);
7106 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7107 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7108 }
7109
7110}
7111
f047e395
CW		 7112void intel_mark_busy(struct drm_device *dev)
7113{
f047e395
CW		 7114 i915_update_gfx_val(dev->dev_private);
7115}
7116
7117void intel_mark_idle(struct drm_device *dev)
652c393a 7118{
652c393a 7119 struct drm_crtc *crtc;
652c393a
JB		 7120
7121 if (!i915_powersave)
7122 return;
7123
652c393a 7124 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7125 if (!crtc->fb)
7126 continue;
7127
725a5b54 7128 intel_decrease_pllclock(crtc);
652c393a 7129 }
652c393a
JB		 7130}
7131
c65355bb
CW		 7132void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7133 struct intel_ring_buffer *ring)
652c393a 7134{
f047e395
CW		 7135 struct drm_device *dev = obj->base.dev;
7136 struct drm_crtc *crtc;
652c393a 7137
f047e395 7138 if (!i915_powersave)
acb87dfb
CW		 7139 return;
7140
652c393a
JB		 7141 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7142 if (!crtc->fb)
7143 continue;
7144
c65355bb
CW		 7145 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7146 continue;
7147
7148 intel_increase_pllclock(crtc);
7149 if (ring && intel_fbc_enabled(dev))
7150 ring->fbc_dirty = true;
652c393a
JB		 7151 }
7152}
7153
79e53945
JB		 7154static void intel_crtc_destroy(struct drm_crtc *crtc)
7155{
7156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7157 struct drm_device *dev = crtc->dev;
7158 struct intel_unpin_work *work;
7159 unsigned long flags;
7160
7161 spin_lock_irqsave(&dev->event_lock, flags);
7162 work = intel_crtc->unpin_work;
7163 intel_crtc->unpin_work = NULL;
7164 spin_unlock_irqrestore(&dev->event_lock, flags);
7165
7166 if (work) {
7167 cancel_work_sync(&work->work);
7168 kfree(work);
7169 }
79e53945 7170
40ccc72b
MK		 7171 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7172
79e53945 7173 drm_crtc_cleanup(crtc);
67e77c5a 7174
79e53945
JB		 7175 kfree(intel_crtc);
7176}
7177
6b95a207
KH		 7178static void intel_unpin_work_fn(struct work_struct *__work)
7179{
7180 struct intel_unpin_work *work =
7181 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7182 struct drm_device *dev = work->crtc->dev;
6b95a207 7183
b4a98e57 7184 mutex_lock(&dev->struct_mutex);
1690e1eb 7185 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7186 drm_gem_object_unreference(&work->pending_flip_obj->base);
7187 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7188
b4a98e57
CW		 7189 intel_update_fbc(dev);
7190 mutex_unlock(&dev->struct_mutex);
7191
7192 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7193 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7194
6b95a207
KH		 7195 kfree(work);
7196}
7197
1afe3e9d 7198static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7199 struct drm_crtc *crtc)
6b95a207
KH		 7200{
7201 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7203 struct intel_unpin_work *work;
6b95a207
KH		 7204 unsigned long flags;
7205
7206 /* Ignore early vblank irqs */
7207 if (intel_crtc == NULL)
7208 return;
7209
7210 spin_lock_irqsave(&dev->event_lock, flags);
7211 work = intel_crtc->unpin_work;
e7d841ca
CW		 7212
7213 /* Ensure we don't miss a work->pending update ... */
7214 smp_rmb();
7215
7216 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7217 spin_unlock_irqrestore(&dev->event_lock, flags);
7218 return;
7219 }
7220
e7d841ca
CW		 7221 /* and that the unpin work is consistent wrt ->pending. */
7222 smp_rmb();
7223
6b95a207 7224 intel_crtc->unpin_work = NULL;
6b95a207 7225
45a066eb
RC		 7226 if (work->event)
7227 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7228
0af7e4df
MK		 7229 drm_vblank_put(dev, intel_crtc->pipe);
7230
6b95a207
KH		 7231 spin_unlock_irqrestore(&dev->event_lock, flags);
7232
2c10d571 7233 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7234
7235 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7236
7237 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7238}
7239
1afe3e9d
JB		 7240void intel_finish_page_flip(struct drm_device *dev, int pipe)
7241{
7242 drm_i915_private_t *dev_priv = dev->dev_private;
7243 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7244
49b14a5c 7245 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7246}
7247
7248void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7249{
7250 drm_i915_private_t *dev_priv = dev->dev_private;
7251 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7252
49b14a5c 7253 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7254}
7255
6b95a207
KH		 7256void intel_prepare_page_flip(struct drm_device *dev, int plane)
7257{
7258 drm_i915_private_t *dev_priv = dev->dev_private;
7259 struct intel_crtc *intel_crtc =
7260 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7261 unsigned long flags;
7262
e7d841ca
CW		 7263 /* NB: An MMIO update of the plane base pointer will also
7264 * generate a page-flip completion irq, i.e. every modeset
7265 * is also accompanied by a spurious intel_prepare_page_flip().
7266 */
6b95a207 7267 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7268 if (intel_crtc->unpin_work)
7269 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7270 spin_unlock_irqrestore(&dev->event_lock, flags);
7271}
7272
e7d841ca
CW		 7273inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7274{
7275 /* Ensure that the work item is consistent when activating it ... */
7276 smp_wmb();
7277 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7278 /* and that it is marked active as soon as the irq could fire. */
7279 smp_wmb();
7280}
7281
8c9f3aaf
JB		 7282static int intel_gen2_queue_flip(struct drm_device *dev,
7283 struct drm_crtc *crtc,
7284 struct drm_framebuffer *fb,
7285 struct drm_i915_gem_object *obj)
7286{
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7289 u32 flip_mask;
6d90c952 7290 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7291 int ret;
7292
6d90c952 7293 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7294 if (ret)
83d4092b 7295 goto err;
8c9f3aaf 7296
6d90c952 7297 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7298 if (ret)
83d4092b 7299 goto err_unpin;
8c9f3aaf
JB		 7300
7301 /* Can't queue multiple flips, so wait for the previous
7302 * one to finish before executing the next.
7303 */
7304 if (intel_crtc->plane)
7305 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7306 else
7307 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7308 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7309 intel_ring_emit(ring, MI_NOOP);
7310 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7311 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7312 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7313 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7314 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7315
7316 intel_mark_page_flip_active(intel_crtc);
6d90c952 7317 intel_ring_advance(ring);
83d4092b
CW		 7318 return 0;
7319
7320err_unpin:
7321 intel_unpin_fb_obj(obj);
7322err:
8c9f3aaf
JB		 7323 return ret;
7324}
7325
7326static int intel_gen3_queue_flip(struct drm_device *dev,
7327 struct drm_crtc *crtc,
7328 struct drm_framebuffer *fb,
7329 struct drm_i915_gem_object *obj)
7330{
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7333 u32 flip_mask;
6d90c952 7334 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7335 int ret;
7336
6d90c952 7337 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7338 if (ret)
83d4092b 7339 goto err;
8c9f3aaf 7340
6d90c952 7341 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7342 if (ret)
83d4092b 7343 goto err_unpin;
8c9f3aaf
JB		 7344
7345 if (intel_crtc->plane)
7346 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7347 else
7348 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7349 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7350 intel_ring_emit(ring, MI_NOOP);
7351 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7352 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7353 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7354 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7355 intel_ring_emit(ring, MI_NOOP);
7356
e7d841ca 7357 intel_mark_page_flip_active(intel_crtc);
6d90c952 7358 intel_ring_advance(ring);
83d4092b
CW		 7359 return 0;
7360
7361err_unpin:
7362 intel_unpin_fb_obj(obj);
7363err:
8c9f3aaf
JB		 7364 return ret;
7365}
7366
7367static int intel_gen4_queue_flip(struct drm_device *dev,
7368 struct drm_crtc *crtc,
7369 struct drm_framebuffer *fb,
7370 struct drm_i915_gem_object *obj)
7371{
7372 struct drm_i915_private *dev_priv = dev->dev_private;
7373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7374 uint32_t pf, pipesrc;
6d90c952 7375 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7376 int ret;
7377
6d90c952 7378 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7379 if (ret)
83d4092b 7380 goto err;
8c9f3aaf 7381
6d90c952 7382 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7383 if (ret)
83d4092b 7384 goto err_unpin;
8c9f3aaf
JB		 7385
7386 /* i965+ uses the linear or tiled offsets from the
7387 * Display Registers (which do not change across a page-flip)
7388 * so we need only reprogram the base address.
7389 */
6d90c952
DV		 7390 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7391 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7392 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7393 intel_ring_emit(ring,
7394 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7395 obj->tiling_mode);
8c9f3aaf
JB		 7396
7397 /* XXX Enabling the panel-fitter across page-flip is so far
7398 * untested on non-native modes, so ignore it for now.
7399 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7400 */
7401 pf = 0;
7402 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7403 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7404
7405 intel_mark_page_flip_active(intel_crtc);
6d90c952 7406 intel_ring_advance(ring);
83d4092b
CW		 7407 return 0;
7408
7409err_unpin:
7410 intel_unpin_fb_obj(obj);
7411err:
8c9f3aaf
JB		 7412 return ret;
7413}
7414
7415static int intel_gen6_queue_flip(struct drm_device *dev,
7416 struct drm_crtc *crtc,
7417 struct drm_framebuffer *fb,
7418 struct drm_i915_gem_object *obj)
7419{
7420 struct drm_i915_private *dev_priv = dev->dev_private;
7421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7422 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7423 uint32_t pf, pipesrc;
7424 int ret;
7425
6d90c952 7426 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7427 if (ret)
83d4092b 7428 goto err;
8c9f3aaf 7429
6d90c952 7430 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7431 if (ret)
83d4092b 7432 goto err_unpin;
8c9f3aaf 7433
6d90c952
DV		 7434 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7435 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7436 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7437 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7438
dc257cf1
DV		 7439 /* Contrary to the suggestions in the documentation,
7440 * "Enable Panel Fitter" does not seem to be required when page
7441 * flipping with a non-native mode, and worse causes a normal
7442 * modeset to fail.
7443 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7444 */
7445 pf = 0;
8c9f3aaf 7446 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7447 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7448
7449 intel_mark_page_flip_active(intel_crtc);
6d90c952 7450 intel_ring_advance(ring);
83d4092b
CW		 7451 return 0;
7452
7453err_unpin:
7454 intel_unpin_fb_obj(obj);
7455err:
8c9f3aaf
JB		 7456 return ret;
7457}
7458
7c9017e5
JB		 7459/*
7460 * On gen7 we currently use the blit ring because (in early silicon at least)
7461 * the render ring doesn't give us interrpts for page flip completion, which
7462 * means clients will hang after the first flip is queued. Fortunately the
7463 * blit ring generates interrupts properly, so use it instead.
7464 */
7465static int intel_gen7_queue_flip(struct drm_device *dev,
7466 struct drm_crtc *crtc,
7467 struct drm_framebuffer *fb,
7468 struct drm_i915_gem_object *obj)
7469{
7470 struct drm_i915_private *dev_priv = dev->dev_private;
7471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7472 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7473 uint32_t plane_bit = 0;
7c9017e5
JB		 7474 int ret;
7475
7476 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7477 if (ret)
83d4092b 7478 goto err;
7c9017e5 7479
cb05d8de
DV		 7480 switch(intel_crtc->plane) {
7481 case PLANE_A:
7482 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7483 break;
7484 case PLANE_B:
7485 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7486 break;
7487 case PLANE_C:
7488 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7489 break;
7490 default:
7491 WARN_ONCE(1, "unknown plane in flip command\n");
7492 ret = -ENODEV;
ab3951eb 7493 goto err_unpin;
cb05d8de
DV		 7494 }
7495
7c9017e5
JB		 7496 ret = intel_ring_begin(ring, 4);
7497 if (ret)
83d4092b 7498 goto err_unpin;
7c9017e5 7499
cb05d8de 7500 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7501 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7502 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7503 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7504
7505 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7506 intel_ring_advance(ring);
83d4092b
CW		 7507 return 0;
7508
7509err_unpin:
7510 intel_unpin_fb_obj(obj);
7511err:
7c9017e5
JB		 7512 return ret;
7513}
7514
8c9f3aaf
JB		 7515static int intel_default_queue_flip(struct drm_device *dev,
7516 struct drm_crtc *crtc,
7517 struct drm_framebuffer *fb,
7518 struct drm_i915_gem_object *obj)
7519{
7520 return -ENODEV;
7521}
7522
6b95a207
KH		 7523static int intel_crtc_page_flip(struct drm_crtc *crtc,
7524 struct drm_framebuffer *fb,
7525 struct drm_pending_vblank_event *event)
7526{
7527 struct drm_device *dev = crtc->dev;
7528 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7529 struct drm_framebuffer *old_fb = crtc->fb;
7530 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7532 struct intel_unpin_work *work;
8c9f3aaf 7533 unsigned long flags;
52e68630 7534 int ret;
6b95a207 7535
e6a595d2
VS		 7536 /* Can't change pixel format via MI display flips. */
7537 if (fb->pixel_format != crtc->fb->pixel_format)
7538 return -EINVAL;
7539
7540 /*
7541 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7542 * Note that pitch changes could also affect these register.
7543 */
7544 if (INTEL_INFO(dev)->gen > 3 &&
7545 (fb->offsets[0] != crtc->fb->offsets[0] ||
7546 fb->pitches[0] != crtc->fb->pitches[0]))
7547 return -EINVAL;
7548
6b95a207
KH		 7549 work = kzalloc(sizeof *work, GFP_KERNEL);
7550 if (work == NULL)
7551 return -ENOMEM;
7552
6b95a207 7553 work->event = event;
b4a98e57 7554 work->crtc = crtc;
4a35f83b 7555 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7556 INIT_WORK(&work->work, intel_unpin_work_fn);
7557
7317c75e
JB		 7558 ret = drm_vblank_get(dev, intel_crtc->pipe);
7559 if (ret)
7560 goto free_work;
7561
6b95a207
KH		 7562 /* We borrow the event spin lock for protecting unpin_work */
7563 spin_lock_irqsave(&dev->event_lock, flags);
7564 if (intel_crtc->unpin_work) {
7565 spin_unlock_irqrestore(&dev->event_lock, flags);
7566 kfree(work);
7317c75e 7567 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7568
7569 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7570 return -EBUSY;
7571 }
7572 intel_crtc->unpin_work = work;
7573 spin_unlock_irqrestore(&dev->event_lock, flags);
7574
b4a98e57
CW		 7575 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7576 flush_workqueue(dev_priv->wq);
7577
79158103
CW		 7578 ret = i915_mutex_lock_interruptible(dev);
7579 if (ret)
7580 goto cleanup;
6b95a207 7581
75dfca80 7582 /* Reference the objects for the scheduled work. */
05394f39
CW		 7583 drm_gem_object_reference(&work->old_fb_obj->base);
7584 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7585
7586 crtc->fb = fb;
96b099fd 7587
e1f99ce6 7588 work->pending_flip_obj = obj;
e1f99ce6 7589
4e5359cd
SF		 7590 work->enable_stall_check = true;
7591
b4a98e57 7592 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7593 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7594
8c9f3aaf
JB		 7595 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7596 if (ret)
7597 goto cleanup_pending;
6b95a207 7598
7782de3b 7599 intel_disable_fbc(dev);
c65355bb 7600 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7601 mutex_unlock(&dev->struct_mutex);
7602
e5510fac
JB		 7603 trace_i915_flip_request(intel_crtc->plane, obj);
7604
6b95a207 7605 return 0;
96b099fd 7606
8c9f3aaf 7607cleanup_pending:
b4a98e57 7608 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7609 crtc->fb = old_fb;
05394f39
CW		 7610 drm_gem_object_unreference(&work->old_fb_obj->base);
7611 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7612 mutex_unlock(&dev->struct_mutex);
7613
79158103 7614cleanup:
96b099fd
CW		 7615 spin_lock_irqsave(&dev->event_lock, flags);
7616 intel_crtc->unpin_work = NULL;
7617 spin_unlock_irqrestore(&dev->event_lock, flags);
7618
7317c75e
JB		 7619 drm_vblank_put(dev, intel_crtc->pipe);
7620free_work:
96b099fd
CW		 7621 kfree(work);
7622
7623 return ret;
6b95a207
KH		 7624}
7625
f6e5b160 7626static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7627 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7628 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7629};
7630
50f56119
DV		 7631static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7632 struct drm_crtc *crtc)
7633{
7634 struct drm_device *dev;
7635 struct drm_crtc *tmp;
7636 int crtc_mask = 1;
47f1c6c9 7637
50f56119 7638 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7639
50f56119 7640 dev = crtc->dev;
47f1c6c9 7641
50f56119
DV		 7642 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7643 if (tmp == crtc)
7644 break;
7645 crtc_mask <<= 1;
7646 }
47f1c6c9 7647
50f56119
DV		 7648 if (encoder->possible_crtcs & crtc_mask)
7649 return true;
7650 return false;
47f1c6c9 7651}
79e53945 7652
9a935856
DV		 7653/**
7654 * intel_modeset_update_staged_output_state
7655 *
7656 * Updates the staged output configuration state, e.g. after we've read out the
7657 * current hw state.
7658 */
7659static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7660{
9a935856
DV		 7661 struct intel_encoder *encoder;
7662 struct intel_connector *connector;
f6e5b160 7663
9a935856
DV		 7664 list_for_each_entry(connector, &dev->mode_config.connector_list,
7665 base.head) {
7666 connector->new_encoder =
7667 to_intel_encoder(connector->base.encoder);
7668 }
f6e5b160 7669
9a935856
DV		 7670 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7671 base.head) {
7672 encoder->new_crtc =
7673 to_intel_crtc(encoder->base.crtc);
7674 }
f6e5b160
CW		 7675}
7676
9a935856
DV		 7677/**
7678 * intel_modeset_commit_output_state
7679 *
7680 * This function copies the stage display pipe configuration to the real one.
7681 */
7682static void intel_modeset_commit_output_state(struct drm_device *dev)
7683{
7684 struct intel_encoder *encoder;
7685 struct intel_connector *connector;
f6e5b160 7686
9a935856
DV		 7687 list_for_each_entry(connector, &dev->mode_config.connector_list,
7688 base.head) {
7689 connector->base.encoder = &connector->new_encoder->base;
7690 }
f6e5b160 7691
9a935856
DV		 7692 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7693 base.head) {
7694 encoder->base.crtc = &encoder->new_crtc->base;
7695 }
7696}
7697
050f7aeb
DV		 7698static void
7699connected_sink_compute_bpp(struct intel_connector * connector,
7700 struct intel_crtc_config *pipe_config)
7701{
7702 int bpp = pipe_config->pipe_bpp;
7703
7704 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7705 connector->base.base.id,
7706 drm_get_connector_name(&connector->base));
7707
7708 /* Don't use an invalid EDID bpc value */
7709 if (connector->base.display_info.bpc &&
7710 connector->base.display_info.bpc * 3 < bpp) {
7711 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7712 bpp, connector->base.display_info.bpc*3);
7713 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7714 }
7715
7716 /* Clamp bpp to 8 on screens without EDID 1.4 */
7717 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7718 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7719 bpp);
7720 pipe_config->pipe_bpp = 24;
7721 }
7722}
7723
4e53c2e0 7724static int
050f7aeb
DV		 7725compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7726 struct drm_framebuffer *fb,
7727 struct intel_crtc_config *pipe_config)
4e53c2e0 7728{
050f7aeb
DV		 7729 struct drm_device *dev = crtc->base.dev;
7730 struct intel_connector *connector;
4e53c2e0
DV		 7731 int bpp;
7732
d42264b1
DV		 7733 switch (fb->pixel_format) {
7734 case DRM_FORMAT_C8:
4e53c2e0
DV		 7735 bpp = 8*3; /* since we go through a colormap */
7736 break;
d42264b1
DV		 7737 case DRM_FORMAT_XRGB1555:
7738 case DRM_FORMAT_ARGB1555:
7739 /* checked in intel_framebuffer_init already */
7740 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7741 return -EINVAL;
7742 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7743 bpp = 6*3; /* min is 18bpp */
7744 break;
d42264b1
DV		 7745 case DRM_FORMAT_XBGR8888:
7746 case DRM_FORMAT_ABGR8888:
7747 /* checked in intel_framebuffer_init already */
7748 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7749 return -EINVAL;
7750 case DRM_FORMAT_XRGB8888:
7751 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7752 bpp = 8*3;
7753 break;
d42264b1
DV		 7754 case DRM_FORMAT_XRGB2101010:
7755 case DRM_FORMAT_ARGB2101010:
7756 case DRM_FORMAT_XBGR2101010:
7757 case DRM_FORMAT_ABGR2101010:
7758 /* checked in intel_framebuffer_init already */
7759 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7760 return -EINVAL;
4e53c2e0
DV		 7761 bpp = 10*3;
7762 break;
baba133a 7763 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7764 default:
7765 DRM_DEBUG_KMS("unsupported depth\n");
7766 return -EINVAL;
7767 }
7768
4e53c2e0
DV		 7769 pipe_config->pipe_bpp = bpp;
7770
7771 /* Clamp display bpp to EDID value */
7772 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7773 base.head) {
1b829e05
DV		 7774 if (!connector->new_encoder ||
7775 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7776 continue;
7777
050f7aeb 7778 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7779 }
7780
7781 return bpp;
7782}
7783
c0b03411
DV		 7784static void intel_dump_pipe_config(struct intel_crtc *crtc,
7785 struct intel_crtc_config *pipe_config,
7786 const char *context)
7787{
7788 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7789 context, pipe_name(crtc->pipe));
7790
7791 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7792 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7793 pipe_config->pipe_bpp, pipe_config->dither);
7794 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7795 pipe_config->has_pch_encoder,
7796 pipe_config->fdi_lanes,
7797 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7798 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7799 pipe_config->fdi_m_n.tu);
7800 DRM_DEBUG_KMS("requested mode:\n");
7801 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7802 DRM_DEBUG_KMS("adjusted mode:\n");
7803 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7804 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7805 pipe_config->gmch_pfit.control,
7806 pipe_config->gmch_pfit.pgm_ratios,
7807 pipe_config->gmch_pfit.lvds_border_bits);
7808 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7809 pipe_config->pch_pfit.pos,
7810 pipe_config->pch_pfit.size);
42db64ef 7811 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7812}
7813
accfc0c5
DV		 7814static bool check_encoder_cloning(struct drm_crtc *crtc)
7815{
7816 int num_encoders = 0;
7817 bool uncloneable_encoders = false;
7818 struct intel_encoder *encoder;
7819
7820 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7821 base.head) {
7822 if (&encoder->new_crtc->base != crtc)
7823 continue;
7824
7825 num_encoders++;
7826 if (!encoder->cloneable)
7827 uncloneable_encoders = true;
7828 }
7829
7830 return !(num_encoders > 1 && uncloneable_encoders);
7831}
7832
b8cecdf5
DV		 7833static struct intel_crtc_config *
7834intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7835 struct drm_framebuffer *fb,
b8cecdf5 7836 struct drm_display_mode *mode)
ee7b9f93 7837{
7758a113 7838 struct drm_device *dev = crtc->dev;
7758a113
DV		 7839 struct drm_encoder_helper_funcs *encoder_funcs;
7840 struct intel_encoder *encoder;
b8cecdf5 7841 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7842 int plane_bpp, ret = -EINVAL;
7843 bool retry = true;
ee7b9f93 7844
accfc0c5
DV		 7845 if (!check_encoder_cloning(crtc)) {
7846 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7847 return ERR_PTR(-EINVAL);
7848 }
7849
b8cecdf5
DV		 7850 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7851 if (!pipe_config)
7758a113
DV		 7852 return ERR_PTR(-ENOMEM);
7853
b8cecdf5
DV		 7854 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7855 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7856 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7857 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7858
050f7aeb
DV		 7859 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7860 * plane pixel format and any sink constraints into account. Returns the
7861 * source plane bpp so that dithering can be selected on mismatches
7862 * after encoders and crtc also have had their say. */
7863 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7864 fb, pipe_config);
4e53c2e0
DV		 7865 if (plane_bpp < 0)
7866 goto fail;
7867
e29c22c0 7868encoder_retry:
ef1b460d 7869 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7870 pipe_config->port_clock = 0;
ef1b460d 7871 pipe_config->pixel_multiplier = 1;
ff9a6750 7872
7758a113
DV		 7873 /* Pass our mode to the connectors and the CRTC to give them a chance to
7874 * adjust it according to limitations or connector properties, and also
7875 * a chance to reject the mode entirely.
47f1c6c9 7876 */
7758a113
DV		 7877 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7878 base.head) {
47f1c6c9 7879
7758a113
DV		 7880 if (&encoder->new_crtc->base != crtc)
7881 continue;
7ae89233
DV		 7882
7883 if (encoder->compute_config) {
7884 if (!(encoder->compute_config(encoder, pipe_config))) {
7885 DRM_DEBUG_KMS("Encoder config failure\n");
7886 goto fail;
7887 }
7888
7889 continue;
7890 }
7891
7758a113 7892 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7893 if (!(encoder_funcs->mode_fixup(&encoder->base,
7894 &pipe_config->requested_mode,
7895 &pipe_config->adjusted_mode))) {
7758a113
DV		 7896 DRM_DEBUG_KMS("Encoder fixup failed\n");
7897 goto fail;
7898 }
ee7b9f93 7899 }
47f1c6c9 7900
ff9a6750
DV		 7901 /* Set default port clock if not overwritten by the encoder. Needs to be
7902 * done afterwards in case the encoder adjusts the mode. */
7903 if (!pipe_config->port_clock)
7904 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7905
a43f6e0f 7906 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7907 if (ret < 0) {
7758a113
DV		 7908 DRM_DEBUG_KMS("CRTC fixup failed\n");
7909 goto fail;
ee7b9f93 7910 }
e29c22c0
DV		 7911
7912 if (ret == RETRY) {
7913 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7914 ret = -EINVAL;
7915 goto fail;
7916 }
7917
7918 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7919 retry = false;
7920 goto encoder_retry;
7921 }
7922
4e53c2e0
DV		 7923 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7924 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7925 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7926
b8cecdf5 7927 return pipe_config;
7758a113 7928fail:
b8cecdf5 7929 kfree(pipe_config);
e29c22c0 7930 return ERR_PTR(ret);
ee7b9f93 7931}
47f1c6c9 7932
e2e1ed41
DV		 7933/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7934 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7935static void
7936intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7937 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7938{
7939 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7940 struct drm_device *dev = crtc->dev;
7941 struct intel_encoder *encoder;
7942 struct intel_connector *connector;
7943 struct drm_crtc *tmp_crtc;
79e53945 7944
e2e1ed41 7945 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7946
e2e1ed41
DV		 7947 /* Check which crtcs have changed outputs connected to them, these need
7948 * to be part of the prepare_pipes mask. We don't (yet) support global
7949 * modeset across multiple crtcs, so modeset_pipes will only have one
7950 * bit set at most. */
7951 list_for_each_entry(connector, &dev->mode_config.connector_list,
7952 base.head) {
7953 if (connector->base.encoder == &connector->new_encoder->base)
7954 continue;
79e53945 7955
e2e1ed41
DV		 7956 if (connector->base.encoder) {
7957 tmp_crtc = connector->base.encoder->crtc;
7958
7959 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7960 }
7961
7962 if (connector->new_encoder)
7963 *prepare_pipes |=
7964 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7965 }
7966
e2e1ed41
DV		 7967 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7968 base.head) {
7969 if (encoder->base.crtc == &encoder->new_crtc->base)
7970 continue;
7971
7972 if (encoder->base.crtc) {
7973 tmp_crtc = encoder->base.crtc;
7974
7975 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7976 }
7977
7978 if (encoder->new_crtc)
7979 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7980 }
7981
e2e1ed41
DV		 7982 /* Check for any pipes that will be fully disabled ... */
7983 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7984 base.head) {
7985 bool used = false;
22fd0fab 7986
e2e1ed41
DV		 7987 /* Don't try to disable disabled crtcs. */
7988 if (!intel_crtc->base.enabled)
7989 continue;
7e7d76c3 7990
e2e1ed41
DV		 7991 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7992 base.head) {
7993 if (encoder->new_crtc == intel_crtc)
7994 used = true;
7995 }
7996
7997 if (!used)
7998 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7999 }
8000
e2e1ed41
DV		 8001
8002 /* set_mode is also used to update properties on life display pipes. */
8003 intel_crtc = to_intel_crtc(crtc);
8004 if (crtc->enabled)
8005 *prepare_pipes |= 1 << intel_crtc->pipe;
8006
b6c5164d
DV		 8007 /*
8008 * For simplicity do a full modeset on any pipe where the output routing
8009 * changed. We could be more clever, but that would require us to be
8010 * more careful with calling the relevant encoder->mode_set functions.
8011 */
e2e1ed41
DV		 8012 if (*prepare_pipes)
8013 *modeset_pipes = *prepare_pipes;
8014
8015 /* ... and mask these out. */
8016 *modeset_pipes &= ~(*disable_pipes);
8017 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8018
8019 /*
8020 * HACK: We don't (yet) fully support global modesets. intel_set_config
8021 * obies this rule, but the modeset restore mode of
8022 * intel_modeset_setup_hw_state does not.
8023 */
8024 *modeset_pipes &= 1 << intel_crtc->pipe;
8025 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8026
8027 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8028 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8029}
79e53945 8030
ea9d758d 8031static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8032{
ea9d758d 8033 struct drm_encoder *encoder;
f6e5b160 8034 struct drm_device *dev = crtc->dev;
f6e5b160 8035
ea9d758d
DV		 8036 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8037 if (encoder->crtc == crtc)
8038 return true;
8039
8040 return false;
8041}
8042
8043static void
8044intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8045{
8046 struct intel_encoder *intel_encoder;
8047 struct intel_crtc *intel_crtc;
8048 struct drm_connector *connector;
8049
8050 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8051 base.head) {
8052 if (!intel_encoder->base.crtc)
8053 continue;
8054
8055 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8056
8057 if (prepare_pipes & (1 << intel_crtc->pipe))
8058 intel_encoder->connectors_active = false;
8059 }
8060
8061 intel_modeset_commit_output_state(dev);
8062
8063 /* Update computed state. */
8064 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8065 base.head) {
8066 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8067 }
8068
8069 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8070 if (!connector->encoder || !connector->encoder->crtc)
8071 continue;
8072
8073 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8074
8075 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8076 struct drm_property *dpms_property =
8077 dev->mode_config.dpms_property;
8078
ea9d758d 8079 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8080 drm_object_property_set_value(&connector->base,
68d34720
DV		 8081 dpms_property,
8082 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8083
8084 intel_encoder = to_intel_encoder(connector->encoder);
8085 intel_encoder->connectors_active = true;
8086 }
8087 }
8088
8089}
8090
25c5b266
DV		 8091#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8092 list_for_each_entry((intel_crtc), \
8093 &(dev)->mode_config.crtc_list, \
8094 base.head) \
0973f18f 8095 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8096
0e8ffe1b 8097static bool
2fa2fe9a
DV		 8098intel_pipe_config_compare(struct drm_device *dev,
8099 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8100 struct intel_crtc_config *pipe_config)
8101{
08a24034
DV		 8102#define PIPE_CONF_CHECK_I(name) \
8103 if (current_config->name != pipe_config->name) { \
8104 DRM_ERROR("mismatch in " #name " " \
8105 "(expected %i, found %i)\n", \
8106 current_config->name, \
8107 pipe_config->name); \
8108 return false; \
88adfff1
DV		 8109 }
8110
1bd1bd80
DV		 8111#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8112 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8113 DRM_ERROR("mismatch in " #name " " \
8114 "(expected %i, found %i)\n", \
8115 current_config->name & (mask), \
8116 pipe_config->name & (mask)); \
8117 return false; \
8118 }
8119
bb760063
DV		 8120#define PIPE_CONF_QUIRK(quirk) \
8121 ((current_config->quirks | pipe_config->quirks) & (quirk))
8122
eccb140b
DV		 8123 PIPE_CONF_CHECK_I(cpu_transcoder);
8124
08a24034
DV		 8125 PIPE_CONF_CHECK_I(has_pch_encoder);
8126 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8127 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8128 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8129 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8130 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8131 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8132
1bd1bd80
DV		 8133 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8134 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8135 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8136 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8137 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8138 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8139
8140 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8141 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8142 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8143 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8144 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8145 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8146
6c49f241
DV		 8147 if (!HAS_PCH_SPLIT(dev))
8148 PIPE_CONF_CHECK_I(pixel_multiplier);
8149
1bd1bd80
DV		 8150 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8151 DRM_MODE_FLAG_INTERLACE);
8152
bb760063
DV		 8153 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8154 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8155 DRM_MODE_FLAG_PHSYNC);
8156 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8157 DRM_MODE_FLAG_NHSYNC);
8158 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8159 DRM_MODE_FLAG_PVSYNC);
8160 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8161 DRM_MODE_FLAG_NVSYNC);
8162 }
045ac3b5 8163
1bd1bd80
DV		 8164 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8165 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8166
2fa2fe9a
DV		 8167 PIPE_CONF_CHECK_I(gmch_pfit.control);
8168 /* pfit ratios are autocomputed by the hw on gen4+ */
8169 if (INTEL_INFO(dev)->gen < 4)
8170 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8171 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8172 PIPE_CONF_CHECK_I(pch_pfit.pos);
8173 PIPE_CONF_CHECK_I(pch_pfit.size);
8174
42db64ef
PZ		 8175 PIPE_CONF_CHECK_I(ips_enabled);
8176
c0d43d62
DV		 8177 PIPE_CONF_CHECK_I(shared_dpll);
8178
08a24034 8179#undef PIPE_CONF_CHECK_I
1bd1bd80 8180#undef PIPE_CONF_CHECK_FLAGS
bb760063 8181#undef PIPE_CONF_QUIRK
627eb5a3 8182
0e8ffe1b
DV		 8183 return true;
8184}
8185
b980514c 8186void
8af6cf88
DV		 8187intel_modeset_check_state(struct drm_device *dev)
8188{
0e8ffe1b 8189 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8190 struct intel_crtc *crtc;
8191 struct intel_encoder *encoder;
8192 struct intel_connector *connector;
0e8ffe1b 8193 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8194
8195 list_for_each_entry(connector, &dev->mode_config.connector_list,
8196 base.head) {
8197 /* This also checks the encoder/connector hw state with the
8198 * ->get_hw_state callbacks. */
8199 intel_connector_check_state(connector);
8200
8201 WARN(&connector->new_encoder->base != connector->base.encoder,
8202 "connector's staged encoder doesn't match current encoder\n");
8203 }
8204
8205 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8206 base.head) {
8207 bool enabled = false;
8208 bool active = false;
8209 enum pipe pipe, tracked_pipe;
8210
8211 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8212 encoder->base.base.id,
8213 drm_get_encoder_name(&encoder->base));
8214
8215 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8216 "encoder's stage crtc doesn't match current crtc\n");
8217 WARN(encoder->connectors_active && !encoder->base.crtc,
8218 "encoder's active_connectors set, but no crtc\n");
8219
8220 list_for_each_entry(connector, &dev->mode_config.connector_list,
8221 base.head) {
8222 if (connector->base.encoder != &encoder->base)
8223 continue;
8224 enabled = true;
8225 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8226 active = true;
8227 }
8228 WARN(!!encoder->base.crtc != enabled,
8229 "encoder's enabled state mismatch "
8230 "(expected %i, found %i)\n",
8231 !!encoder->base.crtc, enabled);
8232 WARN(active && !encoder->base.crtc,
8233 "active encoder with no crtc\n");
8234
8235 WARN(encoder->connectors_active != active,
8236 "encoder's computed active state doesn't match tracked active state "
8237 "(expected %i, found %i)\n", active, encoder->connectors_active);
8238
8239 active = encoder->get_hw_state(encoder, &pipe);
8240 WARN(active != encoder->connectors_active,
8241 "encoder's hw state doesn't match sw tracking "
8242 "(expected %i, found %i)\n",
8243 encoder->connectors_active, active);
8244
8245 if (!encoder->base.crtc)
8246 continue;
8247
8248 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8249 WARN(active && pipe != tracked_pipe,
8250 "active encoder's pipe doesn't match"
8251 "(expected %i, found %i)\n",
8252 tracked_pipe, pipe);
8253
8254 }
8255
8256 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8257 base.head) {
8258 bool enabled = false;
8259 bool active = false;
8260
045ac3b5
JB		 8261 memset(&pipe_config, 0, sizeof(pipe_config));
8262
8af6cf88
DV		 8263 DRM_DEBUG_KMS("[CRTC:%d]\n",
8264 crtc->base.base.id);
8265
8266 WARN(crtc->active && !crtc->base.enabled,
8267 "active crtc, but not enabled in sw tracking\n");
8268
8269 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8270 base.head) {
8271 if (encoder->base.crtc != &crtc->base)
8272 continue;
8273 enabled = true;
8274 if (encoder->connectors_active)
8275 active = true;
8276 }
6c49f241 8277
8af6cf88
DV		 8278 WARN(active != crtc->active,
8279 "crtc's computed active state doesn't match tracked active state "
8280 "(expected %i, found %i)\n", active, crtc->active);
8281 WARN(enabled != crtc->base.enabled,
8282 "crtc's computed enabled state doesn't match tracked enabled state "
8283 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8284
0e8ffe1b
DV		 8285 active = dev_priv->display.get_pipe_config(crtc,
8286 &pipe_config);
6c49f241
DV		 8287 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8288 base.head) {
8289 if (encoder->base.crtc != &crtc->base)
8290 continue;
8291 if (encoder->get_config)
8292 encoder->get_config(encoder, &pipe_config);
8293 }
8294
0e8ffe1b
DV		 8295 WARN(crtc->active != active,
8296 "crtc active state doesn't match with hw state "
8297 "(expected %i, found %i)\n", crtc->active, active);
8298
c0b03411
DV		 8299 if (active &&
8300 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8301 WARN(1, "pipe state doesn't match!\n");
8302 intel_dump_pipe_config(crtc, &pipe_config,
8303 "[hw state]");
8304 intel_dump_pipe_config(crtc, &crtc->config,
8305 "[sw state]");
8306 }
8af6cf88
DV		 8307 }
8308}
8309
f30da187
DV		 8310static int __intel_set_mode(struct drm_crtc *crtc,
8311 struct drm_display_mode *mode,
8312 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8313{
8314 struct drm_device *dev = crtc->dev;
dbf2b54e 8315 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8316 struct drm_display_mode *saved_mode, *saved_hwmode;
8317 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8318 struct intel_crtc *intel_crtc;
8319 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8320 int ret = 0;
a6778b3c 8321
3ac18232 8322 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8323 if (!saved_mode)
8324 return -ENOMEM;
3ac18232 8325 saved_hwmode = saved_mode + 1;
a6778b3c 8326
e2e1ed41 8327 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8328 &prepare_pipes, &disable_pipes);
8329
3ac18232
TG		 8330 *saved_hwmode = crtc->hwmode;
8331 *saved_mode = crtc->mode;
a6778b3c 8332
25c5b266
DV		 8333 /* Hack: Because we don't (yet) support global modeset on multiple
8334 * crtcs, we don't keep track of the new mode for more than one crtc.
8335 * Hence simply check whether any bit is set in modeset_pipes in all the
8336 * pieces of code that are not yet converted to deal with mutliple crtcs
8337 * changing their mode at the same time. */
25c5b266 8338 if (modeset_pipes) {
4e53c2e0 8339 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8340 if (IS_ERR(pipe_config)) {
8341 ret = PTR_ERR(pipe_config);
8342 pipe_config = NULL;
8343
3ac18232 8344 goto out;
25c5b266 8345 }
c0b03411
DV		 8346 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8347 "[modeset]");
25c5b266 8348 }
a6778b3c 8349
460da916
DV		 8350 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8351 intel_crtc_disable(&intel_crtc->base);
8352
ea9d758d
DV		 8353 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8354 if (intel_crtc->base.enabled)
8355 dev_priv->display.crtc_disable(&intel_crtc->base);
8356 }
a6778b3c 8357
6c4c86f5
DV		 8358 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8359 * to set it here already despite that we pass it down the callchain.
f6e5b160 8360 */
b8cecdf5 8361 if (modeset_pipes) {
25c5b266 8362 crtc->mode = *mode;
b8cecdf5
DV		 8363 /* mode_set/enable/disable functions rely on a correct pipe
8364 * config. */
8365 to_intel_crtc(crtc)->config = *pipe_config;
8366 }
7758a113 8367
ea9d758d
DV		 8368 /* Only after disabling all output pipelines that will be changed can we
8369 * update the the output configuration. */
8370 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8371
47fab737
DV		 8372 if (dev_priv->display.modeset_global_resources)
8373 dev_priv->display.modeset_global_resources(dev);
8374
a6778b3c
DV		 8375 /* Set up the DPLL and any encoders state that needs to adjust or depend
8376 * on the DPLL.
f6e5b160 8377 */
25c5b266 8378 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8379 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8380 x, y, fb);
8381 if (ret)
8382 goto done;
a6778b3c
DV		 8383 }
8384
8385 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8386 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8387 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8388
25c5b266
DV		 8389 if (modeset_pipes) {
8390 /* Store real post-adjustment hardware mode. */
b8cecdf5 8391 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8392
25c5b266
DV		 8393 /* Calculate and store various constants which
8394 * are later needed by vblank and swap-completion
8395 * timestamping. They are derived from true hwmode.
8396 */
8397 drm_calc_timestamping_constants(crtc);
8398 }
a6778b3c
DV		 8399
8400 /* FIXME: add subpixel order */
8401done:
c0c36b94 8402 if (ret && crtc->enabled) {
3ac18232
TG		 8403 crtc->hwmode = *saved_hwmode;
8404 crtc->mode = *saved_mode;
a6778b3c
DV		 8405 }
8406
3ac18232 8407out:
b8cecdf5 8408 kfree(pipe_config);
3ac18232 8409 kfree(saved_mode);
a6778b3c 8410 return ret;
f6e5b160
CW		 8411}
8412
f30da187
DV		 8413int intel_set_mode(struct drm_crtc *crtc,
8414 struct drm_display_mode *mode,
8415 int x, int y, struct drm_framebuffer *fb)
8416{
8417 int ret;
8418
8419 ret = __intel_set_mode(crtc, mode, x, y, fb);
8420
8421 if (ret == 0)
8422 intel_modeset_check_state(crtc->dev);
8423
8424 return ret;
8425}
8426
c0c36b94
CW		 8427void intel_crtc_restore_mode(struct drm_crtc *crtc)
8428{
8429 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8430}
8431
25c5b266
DV		 8432#undef for_each_intel_crtc_masked
8433
d9e55608
DV		 8434static void intel_set_config_free(struct intel_set_config *config)
8435{
8436 if (!config)
8437 return;
8438
1aa4b628
DV		 8439 kfree(config->save_connector_encoders);
8440 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8441 kfree(config);
8442}
8443
85f9eb71
DV		 8444static int intel_set_config_save_state(struct drm_device *dev,
8445 struct intel_set_config *config)
8446{
85f9eb71
DV		 8447 struct drm_encoder *encoder;
8448 struct drm_connector *connector;
8449 int count;
8450
1aa4b628
DV		 8451 config->save_encoder_crtcs =
8452 kcalloc(dev->mode_config.num_encoder,
8453 sizeof(struct drm_crtc *), GFP_KERNEL);
8454 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8455 return -ENOMEM;
8456
1aa4b628
DV		 8457 config->save_connector_encoders =
8458 kcalloc(dev->mode_config.num_connector,
8459 sizeof(struct drm_encoder *), GFP_KERNEL);
8460 if (!config->save_connector_encoders)
85f9eb71
DV		 8461 return -ENOMEM;
8462
8463 /* Copy data. Note that driver private data is not affected.
8464 * Should anything bad happen only the expected state is
8465 * restored, not the drivers personal bookkeeping.
8466 */
85f9eb71
DV		 8467 count = 0;
8468 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8469 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8470 }
8471
8472 count = 0;
8473 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8474 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8475 }
8476
8477 return 0;
8478}
8479
8480static void intel_set_config_restore_state(struct drm_device *dev,
8481 struct intel_set_config *config)
8482{
9a935856
DV		 8483 struct intel_encoder *encoder;
8484 struct intel_connector *connector;
85f9eb71
DV		 8485 int count;
8486
85f9eb71 8487 count = 0;
9a935856
DV		 8488 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8489 encoder->new_crtc =
8490 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8491 }
8492
8493 count = 0;
9a935856
DV		 8494 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8495 connector->new_encoder =
8496 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8497 }
8498}
8499
5e2b584e
DV		 8500static void
8501intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8502 struct intel_set_config *config)
8503{
8504
8505 /* We should be able to check here if the fb has the same properties
8506 * and then just flip_or_move it */
8507 if (set->crtc->fb != set->fb) {
8508 /* If we have no fb then treat it as a full mode set */
8509 if (set->crtc->fb == NULL) {
8510 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8511 config->mode_changed = true;
8512 } else if (set->fb == NULL) {
8513 config->mode_changed = true;
72f4901e
DV		 8514 } else if (set->fb->pixel_format !=
8515 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8516 config->mode_changed = true;
8517 } else
8518 config->fb_changed = true;
8519 }
8520
835c5873 8521 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8522 config->fb_changed = true;
8523
8524 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8525 DRM_DEBUG_KMS("modes are different, full mode set\n");
8526 drm_mode_debug_printmodeline(&set->crtc->mode);
8527 drm_mode_debug_printmodeline(set->mode);
8528 config->mode_changed = true;
8529 }
8530}
8531
2e431051 8532static int
9a935856
DV		 8533intel_modeset_stage_output_state(struct drm_device *dev,
8534 struct drm_mode_set *set,
8535 struct intel_set_config *config)
50f56119 8536{
85f9eb71 8537 struct drm_crtc *new_crtc;
9a935856
DV		 8538 struct intel_connector *connector;
8539 struct intel_encoder *encoder;
2e431051 8540 int count, ro;
50f56119 8541
9abdda74 8542 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8543 * of connectors. For paranoia, double-check this. */
8544 WARN_ON(!set->fb && (set->num_connectors != 0));
8545 WARN_ON(set->fb && (set->num_connectors == 0));
8546
50f56119 8547 count = 0;
9a935856
DV		 8548 list_for_each_entry(connector, &dev->mode_config.connector_list,
8549 base.head) {
8550 /* Otherwise traverse passed in connector list and get encoders
8551 * for them. */
50f56119 8552 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8553 if (set->connectors[ro] == &connector->base) {
8554 connector->new_encoder = connector->encoder;
50f56119
DV		 8555 break;
8556 }
8557 }
8558
9a935856
DV		 8559 /* If we disable the crtc, disable all its connectors. Also, if
8560 * the connector is on the changing crtc but not on the new
8561 * connector list, disable it. */
8562 if ((!set->fb || ro == set->num_connectors) &&
8563 connector->base.encoder &&
8564 connector->base.encoder->crtc == set->crtc) {
8565 connector->new_encoder = NULL;
8566
8567 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8568 connector->base.base.id,
8569 drm_get_connector_name(&connector->base));
8570 }
8571
8572
8573 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8574 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8575 config->mode_changed = true;
50f56119
DV		 8576 }
8577 }
9a935856 8578 /* connector->new_encoder is now updated for all connectors. */
50f56119 8579
9a935856 8580 /* Update crtc of enabled connectors. */
50f56119 8581 count = 0;
9a935856
DV		 8582 list_for_each_entry(connector, &dev->mode_config.connector_list,
8583 base.head) {
8584 if (!connector->new_encoder)
50f56119
DV		 8585 continue;
8586
9a935856 8587 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8588
8589 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8590 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8591 new_crtc = set->crtc;
8592 }
8593
8594 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8595 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8596 new_crtc)) {
5e2b584e 8597 return -EINVAL;
50f56119 8598 }
9a935856
DV		 8599 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8600
8601 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8602 connector->base.base.id,
8603 drm_get_connector_name(&connector->base),
8604 new_crtc->base.id);
8605 }
8606
8607 /* Check for any encoders that needs to be disabled. */
8608 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8609 base.head) {
8610 list_for_each_entry(connector,
8611 &dev->mode_config.connector_list,
8612 base.head) {
8613 if (connector->new_encoder == encoder) {
8614 WARN_ON(!connector->new_encoder->new_crtc);
8615
8616 goto next_encoder;
8617 }
8618 }
8619 encoder->new_crtc = NULL;
8620next_encoder:
8621 /* Only now check for crtc changes so we don't miss encoders
8622 * that will be disabled. */
8623 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8624 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8625 config->mode_changed = true;
50f56119
DV		 8626 }
8627 }
9a935856 8628 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8629
2e431051
DV		 8630 return 0;
8631}
8632
8633static int intel_crtc_set_config(struct drm_mode_set *set)
8634{
8635 struct drm_device *dev;
2e431051
DV		 8636 struct drm_mode_set save_set;
8637 struct intel_set_config *config;
8638 int ret;
2e431051 8639
8d3e375e
DV		 8640 BUG_ON(!set);
8641 BUG_ON(!set->crtc);
8642 BUG_ON(!set->crtc->helper_private);
2e431051 8643
7e53f3a4
DV		 8644 /* Enforce sane interface api - has been abused by the fb helper. */
8645 BUG_ON(!set->mode && set->fb);
8646 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8647
2e431051
DV		 8648 if (set->fb) {
8649 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8650 set->crtc->base.id, set->fb->base.id,
8651 (int)set->num_connectors, set->x, set->y);
8652 } else {
8653 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8654 }
8655
8656 dev = set->crtc->dev;
8657
8658 ret = -ENOMEM;
8659 config = kzalloc(sizeof(*config), GFP_KERNEL);
8660 if (!config)
8661 goto out_config;
8662
8663 ret = intel_set_config_save_state(dev, config);
8664 if (ret)
8665 goto out_config;
8666
8667 save_set.crtc = set->crtc;
8668 save_set.mode = &set->crtc->mode;
8669 save_set.x = set->crtc->x;
8670 save_set.y = set->crtc->y;
8671 save_set.fb = set->crtc->fb;
8672
8673 /* Compute whether we need a full modeset, only an fb base update or no
8674 * change at all. In the future we might also check whether only the
8675 * mode changed, e.g. for LVDS where we only change the panel fitter in
8676 * such cases. */
8677 intel_set_config_compute_mode_changes(set, config);
8678
9a935856 8679 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8680 if (ret)
8681 goto fail;
8682
5e2b584e 8683 if (config->mode_changed) {
c0c36b94
CW		 8684 ret = intel_set_mode(set->crtc, set->mode,
8685 set->x, set->y, set->fb);
8686 if (ret) {
8687 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8688 set->crtc->base.id, ret);
87f1faa6
DV		 8689 goto fail;
8690 }
5e2b584e 8691 } else if (config->fb_changed) {
4878cae2
VS		 8692 intel_crtc_wait_for_pending_flips(set->crtc);
8693
4f660f49 8694 ret = intel_pipe_set_base(set->crtc,
94352cf9 8695 set->x, set->y, set->fb);
50f56119
DV		 8696 }
8697
d9e55608
DV		 8698 intel_set_config_free(config);
8699
50f56119
DV		 8700 return 0;
8701
8702fail:
85f9eb71 8703 intel_set_config_restore_state(dev, config);
50f56119
DV		 8704
8705 /* Try to restore the config */
5e2b584e 8706 if (config->mode_changed &&
c0c36b94
CW		 8707 intel_set_mode(save_set.crtc, save_set.mode,
8708 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8709 DRM_ERROR("failed to restore config after modeset failure\n");
8710
d9e55608
DV		 8711out_config:
8712 intel_set_config_free(config);
50f56119
DV		 8713 return ret;
8714}
f6e5b160
CW		 8715
8716static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8717 .cursor_set = intel_crtc_cursor_set,
8718 .cursor_move = intel_crtc_cursor_move,
8719 .gamma_set = intel_crtc_gamma_set,
50f56119 8720 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8721 .destroy = intel_crtc_destroy,
8722 .page_flip = intel_crtc_page_flip,
8723};
8724
79f689aa
PZ		 8725static void intel_cpu_pll_init(struct drm_device *dev)
8726{
affa9354 8727 if (HAS_DDI(dev))
79f689aa
PZ		 8728 intel_ddi_pll_init(dev);
8729}
8730
7c74ade1 8731static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93
JB		 8732{
8733 drm_i915_private_t *dev_priv = dev->dev_private;
8734 int i;
8735
7c74ade1 8736 dev_priv->num_shared_dpll = 2;
ee7b9f93 8737
e72f9fbf
DV		 8738 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8739 dev_priv->shared_dplls[i].pll_reg = _PCH_DPLL(i);
8740 dev_priv->shared_dplls[i].fp0_reg = _PCH_FP0(i);
8741 dev_priv->shared_dplls[i].fp1_reg = _PCH_FP1(i);
ee7b9f93
JB		 8742 }
8743}
8744
7c74ade1
DV		 8745static void intel_shared_dpll_init(struct drm_device *dev)
8746{
8747 drm_i915_private_t *dev_priv = dev->dev_private;
8748
8749 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8750 ibx_pch_dpll_init(dev);
8751 else
8752 dev_priv->num_shared_dpll = 0;
8753
8754 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8755 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8756 dev_priv->num_shared_dpll);
8757}
8758
b358d0a6 8759static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8760{
22fd0fab 8761 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8762 struct intel_crtc *intel_crtc;
8763 int i;
8764
8765 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8766 if (intel_crtc == NULL)
8767 return;
8768
8769 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8770
8771 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8772 for (i = 0; i < 256; i++) {
8773 intel_crtc->lut_r[i] = i;
8774 intel_crtc->lut_g[i] = i;
8775 intel_crtc->lut_b[i] = i;
8776 }
8777
80824003
JB		 8778 /* Swap pipes & planes for FBC on pre-965 */
8779 intel_crtc->pipe = pipe;
8780 intel_crtc->plane = pipe;
e2e767ab 8781 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8782 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8783 intel_crtc->plane = !pipe;
80824003
JB		 8784 }
8785
22fd0fab
JB		 8786 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8787 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8788 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8789 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8790
79e53945 8791 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8792}
8793
08d7b3d1 8794int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8795 struct drm_file *file)
08d7b3d1 8796{
08d7b3d1 8797 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8798 struct drm_mode_object *drmmode_obj;
8799 struct intel_crtc *crtc;
08d7b3d1 8800
1cff8f6b
DV		 8801 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8802 return -ENODEV;
08d7b3d1 8803
c05422d5
DV		 8804 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8805 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8806
c05422d5 8807 if (!drmmode_obj) {
08d7b3d1
CW		 8808 DRM_ERROR("no such CRTC id\n");
8809 return -EINVAL;
8810 }
8811
c05422d5
DV		 8812 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8813 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8814
c05422d5 8815 return 0;
08d7b3d1
CW		 8816}
8817
66a9278e 8818static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8819{
66a9278e
DV		 8820 struct drm_device *dev = encoder->base.dev;
8821 struct intel_encoder *source_encoder;
79e53945 8822 int index_mask = 0;
79e53945
JB		 8823 int entry = 0;
8824
66a9278e
DV		 8825 list_for_each_entry(source_encoder,
8826 &dev->mode_config.encoder_list, base.head) {
8827
8828 if (encoder == source_encoder)
79e53945 8829 index_mask |= (1 << entry);
66a9278e
DV		 8830
8831 /* Intel hw has only one MUX where enocoders could be cloned. */
8832 if (encoder->cloneable && source_encoder->cloneable)
8833 index_mask |= (1 << entry);
8834
79e53945
JB		 8835 entry++;
8836 }
4ef69c7a 8837
79e53945
JB		 8838 return index_mask;
8839}
8840
4d302442
CW		 8841static bool has_edp_a(struct drm_device *dev)
8842{
8843 struct drm_i915_private *dev_priv = dev->dev_private;
8844
8845 if (!IS_MOBILE(dev))
8846 return false;
8847
8848 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8849 return false;
8850
8851 if (IS_GEN5(dev) &&
8852 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8853 return false;
8854
8855 return true;
8856}
8857
79e53945
JB		 8858static void intel_setup_outputs(struct drm_device *dev)
8859{
725e30ad 8860 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8861 struct intel_encoder *encoder;
cb0953d7 8862 bool dpd_is_edp = false;
f3cfcba6 8863 bool has_lvds;
79e53945 8864
f3cfcba6 8865 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8866 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8867 /* disable the panel fitter on everything but LVDS */
8868 I915_WRITE(PFIT_CONTROL, 0);
8869 }
79e53945 8870
c40c0f5b 8871 if (!IS_ULT(dev))
79935fca 8872 intel_crt_init(dev);
cb0953d7 8873
affa9354 8874 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8875 int found;
8876
8877 /* Haswell uses DDI functions to detect digital outputs */
8878 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8879 /* DDI A only supports eDP */
8880 if (found)
8881 intel_ddi_init(dev, PORT_A);
8882
8883 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8884 * register */
8885 found = I915_READ(SFUSE_STRAP);
8886
8887 if (found & SFUSE_STRAP_DDIB_DETECTED)
8888 intel_ddi_init(dev, PORT_B);
8889 if (found & SFUSE_STRAP_DDIC_DETECTED)
8890 intel_ddi_init(dev, PORT_C);
8891 if (found & SFUSE_STRAP_DDID_DETECTED)
8892 intel_ddi_init(dev, PORT_D);
8893 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8894 int found;
270b3042
DV		 8895 dpd_is_edp = intel_dpd_is_edp(dev);
8896
8897 if (has_edp_a(dev))
8898 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8899
dc0fa718 8900 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8901 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8902 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8903 if (!found)
e2debe91 8904 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8905 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8906 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8907 }
8908
dc0fa718 8909 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8910 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8911
dc0fa718 8912 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8913 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8914
5eb08b69 8915 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8916 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8917
270b3042 8918 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8919 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8920 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8921 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8922 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8923 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8924
dc0fa718 8925 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8926 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8927 PORT_B);
67cfc203
VS		 8928 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8929 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8930 }
103a196f 8931 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8932 bool found = false;
7d57382e 8933
e2debe91 8934 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8935 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8936 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8937 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8938 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8939 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8940 }
27185ae1 8941
e7281eab 8942 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8943 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8944 }
13520b05
KH		 8945
8946 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8947
e2debe91 8948 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8949 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8950 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8951 }
27185ae1 8952
e2debe91 8953 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8954
b01f2c3a
JB		 8955 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8956 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8957 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8958 }
e7281eab 8959 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8960 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8961 }
27185ae1 8962
b01f2c3a 8963 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8964 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8965 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8966 } else if (IS_GEN2(dev))
79e53945
JB		 8967 intel_dvo_init(dev);
8968
103a196f 8969 if (SUPPORTS_TV(dev))
79e53945
JB		 8970 intel_tv_init(dev);
8971
4ef69c7a
CW		 8972 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8973 encoder->base.possible_crtcs = encoder->crtc_mask;
8974 encoder->base.possible_clones =
66a9278e 8975 intel_encoder_clones(encoder);
79e53945 8976 }
47356eb6 8977
dde86e2d 8978 intel_init_pch_refclk(dev);
270b3042
DV		 8979
8980 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8981}
8982
8983static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8984{
8985 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8986
8987 drm_framebuffer_cleanup(fb);
05394f39 8988 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8989
8990 kfree(intel_fb);
8991}
8992
8993static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8994 struct drm_file *file,
79e53945
JB		 8995 unsigned int *handle)
8996{
8997 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8998 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8999
05394f39 9000 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9001}
9002
9003static const struct drm_framebuffer_funcs intel_fb_funcs = {
9004 .destroy = intel_user_framebuffer_destroy,
9005 .create_handle = intel_user_framebuffer_create_handle,
9006};
9007
38651674
DA		 9008int intel_framebuffer_init(struct drm_device *dev,
9009 struct intel_framebuffer *intel_fb,
308e5bcb 9010 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9011 struct drm_i915_gem_object *obj)
79e53945 9012{
79e53945
JB		 9013 int ret;
9014
c16ed4be
CW		 9015 if (obj->tiling_mode == I915_TILING_Y) {
9016 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9017 return -EINVAL;
c16ed4be 9018 }
57cd6508 9019
c16ed4be
CW		 9020 if (mode_cmd->pitches[0] & 63) {
9021 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9022 mode_cmd->pitches[0]);
57cd6508 9023 return -EINVAL;
c16ed4be 9024 }
57cd6508 9025
5d7bd705 9026 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 9027 if (mode_cmd->pitches[0] > 32768) {
9028 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9029 mode_cmd->pitches[0]);
5d7bd705 9030 return -EINVAL;
c16ed4be 9031 }
5d7bd705
VS		 9032
9033 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9034 mode_cmd->pitches[0] != obj->stride) {
9035 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9036 mode_cmd->pitches[0], obj->stride);
5d7bd705 9037 return -EINVAL;
c16ed4be 9038 }
5d7bd705 9039
57779d06 9040 /* Reject formats not supported by any plane early. */
308e5bcb 9041 switch (mode_cmd->pixel_format) {
57779d06 9042 case DRM_FORMAT_C8:
04b3924d
VS		 9043 case DRM_FORMAT_RGB565:
9044 case DRM_FORMAT_XRGB8888:
9045 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9046 break;
9047 case DRM_FORMAT_XRGB1555:
9048 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9049 if (INTEL_INFO(dev)->gen > 3) {
9050 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9051 return -EINVAL;
c16ed4be 9052 }
57779d06
VS		 9053 break;
9054 case DRM_FORMAT_XBGR8888:
9055 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9056 case DRM_FORMAT_XRGB2101010:
9057 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9058 case DRM_FORMAT_XBGR2101010:
9059 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9060 if (INTEL_INFO(dev)->gen < 4) {
9061 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9062 return -EINVAL;
c16ed4be 9063 }
b5626747 9064 break;
04b3924d
VS		 9065 case DRM_FORMAT_YUYV:
9066 case DRM_FORMAT_UYVY:
9067 case DRM_FORMAT_YVYU:
9068 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9069 if (INTEL_INFO(dev)->gen < 5) {
9070 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9071 return -EINVAL;
c16ed4be 9072 }
57cd6508
CW		 9073 break;
9074 default:
c16ed4be 9075 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9076 return -EINVAL;
9077 }
9078
90f9a336
VS		 9079 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9080 if (mode_cmd->offsets[0] != 0)
9081 return -EINVAL;
9082
c7d73f6a
DV		 9083 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9084 intel_fb->obj = obj;
9085
79e53945
JB		 9086 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9087 if (ret) {
9088 DRM_ERROR("framebuffer init failed %d\n", ret);
9089 return ret;
9090 }
9091
79e53945
JB		 9092 return 0;
9093}
9094
79e53945
JB		 9095static struct drm_framebuffer *
9096intel_user_framebuffer_create(struct drm_device *dev,
9097 struct drm_file *filp,
308e5bcb 9098 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9099{
05394f39 9100 struct drm_i915_gem_object *obj;
79e53945 9101
308e5bcb
JB		 9102 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9103 mode_cmd->handles[0]));
c8725226 9104 if (&obj->base == NULL)
cce13ff7 9105 return ERR_PTR(-ENOENT);
79e53945 9106
d2dff872 9107 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9108}
9109
79e53945 9110static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9111 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9112 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9113};
9114
e70236a8
JB		 9115/* Set up chip specific display functions */
9116static void intel_init_display(struct drm_device *dev)
9117{
9118 struct drm_i915_private *dev_priv = dev->dev_private;
9119
ee9300bb
DV		 9120 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9121 dev_priv->display.find_dpll = g4x_find_best_dpll;
9122 else if (IS_VALLEYVIEW(dev))
9123 dev_priv->display.find_dpll = vlv_find_best_dpll;
9124 else if (IS_PINEVIEW(dev))
9125 dev_priv->display.find_dpll = pnv_find_best_dpll;
9126 else
9127 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9128
affa9354 9129 if (HAS_DDI(dev)) {
0e8ffe1b 9130 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9131 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9132 dev_priv->display.crtc_enable = haswell_crtc_enable;
9133 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9134 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9135 dev_priv->display.update_plane = ironlake_update_plane;
9136 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9137 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9138 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9139 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9140 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9141 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9142 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9143 } else if (IS_VALLEYVIEW(dev)) {
9144 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9145 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9146 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9147 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9148 dev_priv->display.off = i9xx_crtc_off;
9149 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9150 } else {
0e8ffe1b 9151 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9152 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9153 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9154 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9155 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9156 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9157 }
e70236a8 9158
e70236a8 9159 /* Returns the core display clock speed */
25eb05fc
JB		 9160 if (IS_VALLEYVIEW(dev))
9161 dev_priv->display.get_display_clock_speed =
9162 valleyview_get_display_clock_speed;
9163 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9164 dev_priv->display.get_display_clock_speed =
9165 i945_get_display_clock_speed;
9166 else if (IS_I915G(dev))
9167 dev_priv->display.get_display_clock_speed =
9168 i915_get_display_clock_speed;
f2b115e6 9169 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9170 dev_priv->display.get_display_clock_speed =
9171 i9xx_misc_get_display_clock_speed;
9172 else if (IS_I915GM(dev))
9173 dev_priv->display.get_display_clock_speed =
9174 i915gm_get_display_clock_speed;
9175 else if (IS_I865G(dev))
9176 dev_priv->display.get_display_clock_speed =
9177 i865_get_display_clock_speed;
f0f8a9ce 9178 else if (IS_I85X(dev))
e70236a8
JB		 9179 dev_priv->display.get_display_clock_speed =
9180 i855_get_display_clock_speed;
9181 else /* 852, 830 */
9182 dev_priv->display.get_display_clock_speed =
9183 i830_get_display_clock_speed;
9184
7f8a8569 9185 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9186 if (IS_GEN5(dev)) {
674cf967 9187 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9188 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9189 } else if (IS_GEN6(dev)) {
674cf967 9190 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9191 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9192 } else if (IS_IVYBRIDGE(dev)) {
9193 /* FIXME: detect B0+ stepping and use auto training */
9194 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9195 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9196 dev_priv->display.modeset_global_resources =
9197 ivb_modeset_global_resources;
c82e4d26
ED		 9198 } else if (IS_HASWELL(dev)) {
9199 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9200 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9201 dev_priv->display.modeset_global_resources =
9202 haswell_modeset_global_resources;
a0e63c22 9203 }
6067aaea 9204 } else if (IS_G4X(dev)) {
e0dac65e 9205 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9206 }
8c9f3aaf
JB		 9207
9208 /* Default just returns -ENODEV to indicate unsupported */
9209 dev_priv->display.queue_flip = intel_default_queue_flip;
9210
9211 switch (INTEL_INFO(dev)->gen) {
9212 case 2:
9213 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9214 break;
9215
9216 case 3:
9217 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9218 break;
9219
9220 case 4:
9221 case 5:
9222 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9223 break;
9224
9225 case 6:
9226 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9227 break;
7c9017e5
JB		 9228 case 7:
9229 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9230 break;
8c9f3aaf 9231 }
e70236a8
JB		 9232}
9233
b690e96c
JB		 9234/*
9235 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9236 * resume, or other times. This quirk makes sure that's the case for
9237 * affected systems.
9238 */
0206e353 9239static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9240{
9241 struct drm_i915_private *dev_priv = dev->dev_private;
9242
9243 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9244 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9245}
9246
435793df
KP		 9247/*
9248 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9249 */
9250static void quirk_ssc_force_disable(struct drm_device *dev)
9251{
9252 struct drm_i915_private *dev_priv = dev->dev_private;
9253 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9254 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9255}
9256
4dca20ef 9257/*
5a15ab5b
CE		 9258 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9259 * brightness value
4dca20ef
CE		 9260 */
9261static void quirk_invert_brightness(struct drm_device *dev)
9262{
9263 struct drm_i915_private *dev_priv = dev->dev_private;
9264 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9265 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9266}
9267
b690e96c
JB		 9268struct intel_quirk {
9269 int device;
9270 int subsystem_vendor;
9271 int subsystem_device;
9272 void (*hook)(struct drm_device *dev);
9273};
9274
5f85f176
EE		 9275/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9276struct intel_dmi_quirk {
9277 void (*hook)(struct drm_device *dev);
9278 const struct dmi_system_id (*dmi_id_list)[];
9279};
9280
9281static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9282{
9283 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9284 return 1;
9285}
9286
9287static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9288 {
9289 .dmi_id_list = &(const struct dmi_system_id[]) {
9290 {
9291 .callback = intel_dmi_reverse_brightness,
9292 .ident = "NCR Corporation",
9293 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9294 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9295 },
9296 },
9297 { } /* terminating entry */
9298 },
9299 .hook = quirk_invert_brightness,
9300 },
9301};
9302
c43b5634 9303static struct intel_quirk intel_quirks[] = {
b690e96c 9304 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9305 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9306
b690e96c
JB		 9307 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9308 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9309
b690e96c
JB		 9310 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9311 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9312
ccd0d36e 9313 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9314 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9315 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9316
9317 /* Lenovo U160 cannot use SSC on LVDS */
9318 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9319
9320 /* Sony Vaio Y cannot use SSC on LVDS */
9321 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9322
9323 /* Acer Aspire 5734Z must invert backlight brightness */
9324 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9325
9326 /* Acer/eMachines G725 */
9327 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9328
9329 /* Acer/eMachines e725 */
9330 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9331
9332 /* Acer/Packard Bell NCL20 */
9333 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9334
9335 /* Acer Aspire 4736Z */
9336 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9337};
9338
9339static void intel_init_quirks(struct drm_device *dev)
9340{
9341 struct pci_dev *d = dev->pdev;
9342 int i;
9343
9344 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9345 struct intel_quirk *q = &intel_quirks[i];
9346
9347 if (d->device == q->device &&
9348 (d->subsystem_vendor == q->subsystem_vendor ||
9349 q->subsystem_vendor == PCI_ANY_ID) &&
9350 (d->subsystem_device == q->subsystem_device ||
9351 q->subsystem_device == PCI_ANY_ID))
9352 q->hook(dev);
9353 }
5f85f176
EE		 9354 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9355 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9356 intel_dmi_quirks[i].hook(dev);
9357 }
b690e96c
JB		 9358}
9359
9cce37f4
JB		 9360/* Disable the VGA plane that we never use */
9361static void i915_disable_vga(struct drm_device *dev)
9362{
9363 struct drm_i915_private *dev_priv = dev->dev_private;
9364 u8 sr1;
766aa1c4 9365 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9366
9367 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9368 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9369 sr1 = inb(VGA_SR_DATA);
9370 outb(sr1 | 1<<5, VGA_SR_DATA);
9371 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9372 udelay(300);
9373
9374 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9375 POSTING_READ(vga_reg);
9376}
9377
f817586c
DV		 9378void intel_modeset_init_hw(struct drm_device *dev)
9379{
fa42e23c 9380 intel_init_power_well(dev);
0232e927 9381
a8f78b58
ED		 9382 intel_prepare_ddi(dev);
9383
f817586c
DV		 9384 intel_init_clock_gating(dev);
9385
79f5b2c7 9386 mutex_lock(&dev->struct_mutex);
8090c6b9 9387 intel_enable_gt_powersave(dev);
79f5b2c7 9388 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9389}
9390
7d708ee4
ID		 9391void intel_modeset_suspend_hw(struct drm_device *dev)
9392{
9393 intel_suspend_hw(dev);
9394}
9395
79e53945
JB		 9396void intel_modeset_init(struct drm_device *dev)
9397{
652c393a 9398 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9399 int i, j, ret;
79e53945
JB		 9400
9401 drm_mode_config_init(dev);
9402
9403 dev->mode_config.min_width = 0;
9404 dev->mode_config.min_height = 0;
9405
019d96cb
DA		 9406 dev->mode_config.preferred_depth = 24;
9407 dev->mode_config.prefer_shadow = 1;
9408
e6ecefaa 9409 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9410
b690e96c
JB		 9411 intel_init_quirks(dev);
9412
1fa61106
ED		 9413 intel_init_pm(dev);
9414
e3c74757
BW		 9415 if (INTEL_INFO(dev)->num_pipes == 0)
9416 return;
9417
e70236a8
JB		 9418 intel_init_display(dev);
9419
a6c45cf0
CW		 9420 if (IS_GEN2(dev)) {
9421 dev->mode_config.max_width = 2048;
9422 dev->mode_config.max_height = 2048;
9423 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9424 dev->mode_config.max_width = 4096;
9425 dev->mode_config.max_height = 4096;
79e53945 9426 } else {
a6c45cf0
CW		 9427 dev->mode_config.max_width = 8192;
9428 dev->mode_config.max_height = 8192;
79e53945 9429 }
5d4545ae 9430 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9431
28c97730 9432 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9433 INTEL_INFO(dev)->num_pipes,
9434 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9435
7eb552ae 9436 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9437 intel_crtc_init(dev, i);
7f1f3851
JB		 9438 for (j = 0; j < dev_priv->num_plane; j++) {
9439 ret = intel_plane_init(dev, i, j);
9440 if (ret)
06da8da2
VS		 9441 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9442 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9443 }
79e53945
JB		 9444 }
9445
79f689aa 9446 intel_cpu_pll_init(dev);
e72f9fbf 9447 intel_shared_dpll_init(dev);
ee7b9f93 9448
9cce37f4
JB		 9449 /* Just disable it once at startup */
9450 i915_disable_vga(dev);
79e53945 9451 intel_setup_outputs(dev);
11be49eb
CW		 9452
9453 /* Just in case the BIOS is doing something questionable. */
9454 intel_disable_fbc(dev);
2c7111db
CW		 9455}
9456
24929352
DV		 9457static void
9458intel_connector_break_all_links(struct intel_connector *connector)
9459{
9460 connector->base.dpms = DRM_MODE_DPMS_OFF;
9461 connector->base.encoder = NULL;
9462 connector->encoder->connectors_active = false;
9463 connector->encoder->base.crtc = NULL;
9464}
9465
7fad798e
DV		 9466static void intel_enable_pipe_a(struct drm_device *dev)
9467{
9468 struct intel_connector *connector;
9469 struct drm_connector *crt = NULL;
9470 struct intel_load_detect_pipe load_detect_temp;
9471
9472 /* We can't just switch on the pipe A, we need to set things up with a
9473 * proper mode and output configuration. As a gross hack, enable pipe A
9474 * by enabling the load detect pipe once. */
9475 list_for_each_entry(connector,
9476 &dev->mode_config.connector_list,
9477 base.head) {
9478 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9479 crt = &connector->base;
9480 break;
9481 }
9482 }
9483
9484 if (!crt)
9485 return;
9486
9487 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9488 intel_release_load_detect_pipe(crt, &load_detect_temp);
9489
652c393a 9490
7fad798e
DV		 9491}
9492
fa555837
DV		 9493static bool
9494intel_check_plane_mapping(struct intel_crtc *crtc)
9495{
7eb552ae
BW		 9496 struct drm_device *dev = crtc->base.dev;
9497 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9498 u32 reg, val;
9499
7eb552ae 9500 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9501 return true;
9502
9503 reg = DSPCNTR(!crtc->plane);
9504 val = I915_READ(reg);
9505
9506 if ((val & DISPLAY_PLANE_ENABLE) &&
9507 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9508 return false;
9509
9510 return true;
9511}
9512
24929352
DV		 9513static void intel_sanitize_crtc(struct intel_crtc *crtc)
9514{
9515 struct drm_device *dev = crtc->base.dev;
9516 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9517 u32 reg;
24929352 9518
24929352 9519 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9520 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9521 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9522
9523 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9524 * disable the crtc (and hence change the state) if it is wrong. Note
9525 * that gen4+ has a fixed plane -> pipe mapping. */
9526 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9527 struct intel_connector *connector;
9528 bool plane;
9529
24929352
DV		 9530 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9531 crtc->base.base.id);
9532
9533 /* Pipe has the wrong plane attached and the plane is active.
9534 * Temporarily change the plane mapping and disable everything
9535 * ... */
9536 plane = crtc->plane;
9537 crtc->plane = !plane;
9538 dev_priv->display.crtc_disable(&crtc->base);
9539 crtc->plane = plane;
9540
9541 /* ... and break all links. */
9542 list_for_each_entry(connector, &dev->mode_config.connector_list,
9543 base.head) {
9544 if (connector->encoder->base.crtc != &crtc->base)
9545 continue;
9546
9547 intel_connector_break_all_links(connector);
9548 }
9549
9550 WARN_ON(crtc->active);
9551 crtc->base.enabled = false;
9552 }
24929352 9553
7fad798e
DV		 9554 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9555 crtc->pipe == PIPE_A && !crtc->active) {
9556 /* BIOS forgot to enable pipe A, this mostly happens after
9557 * resume. Force-enable the pipe to fix this, the update_dpms
9558 * call below we restore the pipe to the right state, but leave
9559 * the required bits on. */
9560 intel_enable_pipe_a(dev);
9561 }
9562
24929352
DV		 9563 /* Adjust the state of the output pipe according to whether we
9564 * have active connectors/encoders. */
9565 intel_crtc_update_dpms(&crtc->base);
9566
9567 if (crtc->active != crtc->base.enabled) {
9568 struct intel_encoder *encoder;
9569
9570 /* This can happen either due to bugs in the get_hw_state
9571 * functions or because the pipe is force-enabled due to the
9572 * pipe A quirk. */
9573 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9574 crtc->base.base.id,
9575 crtc->base.enabled ? "enabled" : "disabled",
9576 crtc->active ? "enabled" : "disabled");
9577
9578 crtc->base.enabled = crtc->active;
9579
9580 /* Because we only establish the connector -> encoder ->
9581 * crtc links if something is active, this means the
9582 * crtc is now deactivated. Break the links. connector
9583 * -> encoder links are only establish when things are
9584 * actually up, hence no need to break them. */
9585 WARN_ON(crtc->active);
9586
9587 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9588 WARN_ON(encoder->connectors_active);
9589 encoder->base.crtc = NULL;
9590 }
9591 }
9592}
9593
9594static void intel_sanitize_encoder(struct intel_encoder *encoder)
9595{
9596 struct intel_connector *connector;
9597 struct drm_device *dev = encoder->base.dev;
9598
9599 /* We need to check both for a crtc link (meaning that the
9600 * encoder is active and trying to read from a pipe) and the
9601 * pipe itself being active. */
9602 bool has_active_crtc = encoder->base.crtc &&
9603 to_intel_crtc(encoder->base.crtc)->active;
9604
9605 if (encoder->connectors_active && !has_active_crtc) {
9606 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9607 encoder->base.base.id,
9608 drm_get_encoder_name(&encoder->base));
9609
9610 /* Connector is active, but has no active pipe. This is
9611 * fallout from our resume register restoring. Disable
9612 * the encoder manually again. */
9613 if (encoder->base.crtc) {
9614 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9615 encoder->base.base.id,
9616 drm_get_encoder_name(&encoder->base));
9617 encoder->disable(encoder);
9618 }
9619
9620 /* Inconsistent output/port/pipe state happens presumably due to
9621 * a bug in one of the get_hw_state functions. Or someplace else
9622 * in our code, like the register restore mess on resume. Clamp
9623 * things to off as a safer default. */
9624 list_for_each_entry(connector,
9625 &dev->mode_config.connector_list,
9626 base.head) {
9627 if (connector->encoder != encoder)
9628 continue;
9629
9630 intel_connector_break_all_links(connector);
9631 }
9632 }
9633 /* Enabled encoders without active connectors will be fixed in
9634 * the crtc fixup. */
9635}
9636
44cec740 9637void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9638{
9639 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9640 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9641
9642 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9643 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9644 i915_disable_vga(dev);
0fde901f
KM		 9645 }
9646}
9647
24929352
DV		 9648/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9649 * and i915 state tracking structures. */
45e2b5f6
DV		 9650void intel_modeset_setup_hw_state(struct drm_device *dev,
9651 bool force_restore)
24929352
DV		 9652{
9653 struct drm_i915_private *dev_priv = dev->dev_private;
9654 enum pipe pipe;
b5644d05 9655 struct drm_plane *plane;
24929352
DV		 9656 struct intel_crtc *crtc;
9657 struct intel_encoder *encoder;
9658 struct intel_connector *connector;
9659
0e8ffe1b
DV		 9660 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9661 base.head) {
88adfff1 9662 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9663
0e8ffe1b
DV		 9664 crtc->active = dev_priv->display.get_pipe_config(crtc,
9665 &crtc->config);
24929352
DV		 9666
9667 crtc->base.enabled = crtc->active;
9668
9669 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9670 crtc->base.base.id,
9671 crtc->active ? "enabled" : "disabled");
9672 }
9673
affa9354 9674 if (HAS_DDI(dev))
6441ab5f
PZ		 9675 intel_ddi_setup_hw_pll_state(dev);
9676
24929352
DV		 9677 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9678 base.head) {
9679 pipe = 0;
9680
9681 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9682 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9683 encoder->base.crtc = &crtc->base;
9684 if (encoder->get_config)
9685 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9686 } else {
9687 encoder->base.crtc = NULL;
9688 }
9689
9690 encoder->connectors_active = false;
9691 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9692 encoder->base.base.id,
9693 drm_get_encoder_name(&encoder->base),
9694 encoder->base.crtc ? "enabled" : "disabled",
9695 pipe);
9696 }
9697
9698 list_for_each_entry(connector, &dev->mode_config.connector_list,
9699 base.head) {
9700 if (connector->get_hw_state(connector)) {
9701 connector->base.dpms = DRM_MODE_DPMS_ON;
9702 connector->encoder->connectors_active = true;
9703 connector->base.encoder = &connector->encoder->base;
9704 } else {
9705 connector->base.dpms = DRM_MODE_DPMS_OFF;
9706 connector->base.encoder = NULL;
9707 }
9708 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9709 connector->base.base.id,
9710 drm_get_connector_name(&connector->base),
9711 connector->base.encoder ? "enabled" : "disabled");
9712 }
9713
9714 /* HW state is read out, now we need to sanitize this mess. */
9715 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9716 base.head) {
9717 intel_sanitize_encoder(encoder);
9718 }
9719
9720 for_each_pipe(pipe) {
9721 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9722 intel_sanitize_crtc(crtc);
c0b03411 9723 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9724 }
9a935856 9725
45e2b5f6 9726 if (force_restore) {
f30da187
DV		 9727 /*
9728 * We need to use raw interfaces for restoring state to avoid
9729 * checking (bogus) intermediate states.
9730 */
45e2b5f6 9731 for_each_pipe(pipe) {
b5644d05
JB		 9732 struct drm_crtc *crtc =
9733 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9734
9735 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9736 crtc->fb);
45e2b5f6 9737 }
b5644d05
JB		 9738 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9739 intel_plane_restore(plane);
0fde901f
KM		 9740
9741 i915_redisable_vga(dev);
45e2b5f6
DV		 9742 } else {
9743 intel_modeset_update_staged_output_state(dev);
9744 }
8af6cf88
DV		 9745
9746 intel_modeset_check_state(dev);
2e938892
DV		 9747
9748 drm_mode_config_reset(dev);
2c7111db
CW		 9749}
9750
9751void intel_modeset_gem_init(struct drm_device *dev)
9752{
1833b134 9753 intel_modeset_init_hw(dev);
02e792fb
DV		 9754
9755 intel_setup_overlay(dev);
24929352 9756
45e2b5f6 9757 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9758}
9759
9760void intel_modeset_cleanup(struct drm_device *dev)
9761{
652c393a
JB		 9762 struct drm_i915_private *dev_priv = dev->dev_private;
9763 struct drm_crtc *crtc;
9764 struct intel_crtc *intel_crtc;
9765
fd0c0642
DV		 9766 /*
9767 * Interrupts and polling as the first thing to avoid creating havoc.
9768 * Too much stuff here (turning of rps, connectors, ...) would
9769 * experience fancy races otherwise.
9770 */
9771 drm_irq_uninstall(dev);
9772 cancel_work_sync(&dev_priv->hotplug_work);
9773 /*
9774 * Due to the hpd irq storm handling the hotplug work can re-arm the
9775 * poll handlers. Hence disable polling after hpd handling is shut down.
9776 */
f87ea761 9777 drm_kms_helper_poll_fini(dev);
fd0c0642 9778
652c393a
JB		 9779 mutex_lock(&dev->struct_mutex);
9780
723bfd70
JB		 9781 intel_unregister_dsm_handler();
9782
652c393a
JB		 9783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9784 /* Skip inactive CRTCs */
9785 if (!crtc->fb)
9786 continue;
9787
9788 intel_crtc = to_intel_crtc(crtc);
3dec0095 9789 intel_increase_pllclock(crtc);
652c393a
JB		 9790 }
9791
973d04f9 9792 intel_disable_fbc(dev);
e70236a8 9793
8090c6b9 9794 intel_disable_gt_powersave(dev);
0cdab21f 9795
930ebb46
DV		 9796 ironlake_teardown_rc6(dev);
9797
69341a5e
KH		 9798 mutex_unlock(&dev->struct_mutex);
9799
1630fe75
CW		 9800 /* flush any delayed tasks or pending work */
9801 flush_scheduled_work();
9802
dc652f90
JN		 9803 /* destroy backlight, if any, before the connectors */
9804 intel_panel_destroy_backlight(dev);
9805
79e53945 9806 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9807
9808 intel_cleanup_overlay(dev);
79e53945
JB		 9809}
9810
f1c79df3
ZW		 9811/*
9812 * Return which encoder is currently attached for connector.
9813 */
df0e9248 9814struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9815{
df0e9248
CW		 9816 return &intel_attached_encoder(connector)->base;
9817}
f1c79df3 9818
df0e9248
CW		 9819void intel_connector_attach_encoder(struct intel_connector *connector,
9820 struct intel_encoder *encoder)
9821{
9822 connector->encoder = encoder;
9823 drm_mode_connector_attach_encoder(&connector->base,
9824 &encoder->base);
79e53945 9825}
28d52043
DA		 9826
9827/*
9828 * set vga decode state - true == enable VGA decode
9829 */
9830int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9831{
9832 struct drm_i915_private *dev_priv = dev->dev_private;
9833 u16 gmch_ctrl;
9834
9835 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9836 if (state)
9837 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9838 else
9839 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9840 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9841 return 0;
9842}
c4a1d9e4
CW		 9843
9844#ifdef CONFIG_DEBUG_FS
9845#include <linux/seq_file.h>
9846
9847struct intel_display_error_state {
ff57f1b0
PZ		 9848
9849 u32 power_well_driver;
9850
c4a1d9e4
CW		 9851 struct intel_cursor_error_state {
9852 u32 control;
9853 u32 position;
9854 u32 base;
9855 u32 size;
52331309 9856 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9857
9858 struct intel_pipe_error_state {
ff57f1b0 9859 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9860 u32 conf;
9861 u32 source;
9862
9863 u32 htotal;
9864 u32 hblank;
9865 u32 hsync;
9866 u32 vtotal;
9867 u32 vblank;
9868 u32 vsync;
52331309 9869 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9870
9871 struct intel_plane_error_state {
9872 u32 control;
9873 u32 stride;
9874 u32 size;
9875 u32 pos;
9876 u32 addr;
9877 u32 surface;
9878 u32 tile_offset;
52331309 9879 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9880};
9881
9882struct intel_display_error_state *
9883intel_display_capture_error_state(struct drm_device *dev)
9884{
0206e353 9885 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9886 struct intel_display_error_state *error;
702e7a56 9887 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9888 int i;
9889
9890 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9891 if (error == NULL)
9892 return NULL;
9893
ff57f1b0
PZ		 9894 if (HAS_POWER_WELL(dev))
9895 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9896
52331309 9897 for_each_pipe(i) {
702e7a56 9898 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9899 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9900
a18c4c3d
PZ		 9901 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9902 error->cursor[i].control = I915_READ(CURCNTR(i));
9903 error->cursor[i].position = I915_READ(CURPOS(i));
9904 error->cursor[i].base = I915_READ(CURBASE(i));
9905 } else {
9906 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9907 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9908 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9909 }
c4a1d9e4
CW		 9910
9911 error->plane[i].control = I915_READ(DSPCNTR(i));
9912 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9913 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9914 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9915 error->plane[i].pos = I915_READ(DSPPOS(i));
9916 }
ca291363
PZ		 9917 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9918 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9919 if (INTEL_INFO(dev)->gen >= 4) {
9920 error->plane[i].surface = I915_READ(DSPSURF(i));
9921 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9922 }
9923
702e7a56 9924 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9925 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9926 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9927 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9928 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9929 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9930 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9931 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9932 }
9933
12d217c7
PZ		 9934 /* In the code above we read the registers without checking if the power
9935 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9936 * prevent the next I915_WRITE from detecting it and printing an error
9937 * message. */
9938 if (HAS_POWER_WELL(dev))
9939 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9940
c4a1d9e4
CW		 9941 return error;
9942}
9943
edc3d884
MK		 9944#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9945
c4a1d9e4 9946void
edc3d884 9947intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9948 struct drm_device *dev,
9949 struct intel_display_error_state *error)
9950{
9951 int i;
9952
edc3d884 9953 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9954 if (HAS_POWER_WELL(dev))
edc3d884 9955 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9956 error->power_well_driver);
52331309 9957 for_each_pipe(i) {
edc3d884
MK		 9958 err_printf(m, "Pipe [%d]:\n", i);
9959 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9960 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9961 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9962 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9963 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9964 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9965 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9966 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9967 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9968 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9969
9970 err_printf(m, "Plane [%d]:\n", i);
9971 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9972 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9973 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9974 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9975 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9976 }
4b71a570 9977 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9978 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9979 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9980 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9981 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9982 }
9983
edc3d884
MK		 9984 err_printf(m, "Cursor [%d]:\n", i);
9985 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9986 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9987 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9988 }
9989}
9990#endif
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