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drm/i915: sprite support for ValleyView v4
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
dc0fa718 1343 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1348 return false;
1349 } else {
dc0fa718 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
dc0fa718 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
a0c4da24 1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507}
1508
a416edef
ED		 1509/* SBI access */
1510static void
988d6ee8
PZ		 1511intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
a416edef 1513{
988d6ee8 1514 u32 tmp;
a416edef 1515
09153000 1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1517
39fb50f6 1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1521 return;
a416edef
ED		 1522 }
1523
988d6ee8
PZ		 1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1532
39fb50f6 1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1536 return;
a416edef 1537 }
a416edef
ED		 1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef 1543{
39fb50f6 1544 u32 value = 0;
09153000 1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1546
39fb50f6 1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1550 return 0;
a416edef
ED		 1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1564 return 0;
a416edef
ED		 1565 }
1566
09153000 1567 return I915_READ(SBI_DATA);
a416edef
ED		 1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
dfd07d72
DV		 1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1a240d4d 1815 enum pipe pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
681e5811 1819 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
040484af
JB		 1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
b24e7179 1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
1850/**
309cfea8 1851 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
702e7a56
PZ		 1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
b24e7179
JB		 1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
702e7a56 1880 reg = PIPECONF(cpu_transcoder);
b24e7179 1881 val = I915_READ(reg);
00d70b15
CW		 1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887}
1888
d74362c9
KP		 1889/*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
6f1d69b0 1893void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1894 enum plane plane)
1895{
14f86147
DL		 1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1900}
1901
b24e7179
JB		 1902/**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
00d70b15
CW		 1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1925 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927}
1928
b24e7179
JB		 1929/**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
00d70b15
CW		 1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951}
1952
693db184
CW		 1953static bool need_vtd_wa(struct drm_device *dev)
1954{
1955#ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1957 return true;
1958#endif
1959 return false;
1960}
1961
127bd2ac 1962int
48b956c5 1963intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1964 struct drm_i915_gem_object *obj,
919926ae 1965 struct intel_ring_buffer *pipelined)
6b95a207 1966{
ce453d81 1967 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1968 u32 alignment;
1969 int ret;
1970
05394f39 1971 switch (obj->tiling_mode) {
6b95a207 1972 case I915_TILING_NONE:
534843da
CW		 1973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974 alignment = 128 * 1024;
a6c45cf0 1975 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1976 alignment = 4 * 1024;
1977 else
1978 alignment = 64 * 1024;
6b95a207
KH		 1979 break;
1980 case I915_TILING_X:
1981 /* pin() will align the object as required by fence */
1982 alignment = 0;
1983 break;
1984 case I915_TILING_Y:
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1987 return -EINVAL;
1988 default:
1989 BUG();
1990 }
1991
693db184
CW		 1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1995 * the VT-d warning.
1996 */
1997 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998 alignment = 256 * 1024;
1999
ce453d81 2000 dev_priv->mm.interruptible = false;
2da3b9b9 2001 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2002 if (ret)
ce453d81 2003 goto err_interruptible;
6b95a207
KH		 2004
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2009 */
06d98131 2010 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2011 if (ret)
2012 goto err_unpin;
1690e1eb 2013
9a5a53b3 2014 i915_gem_object_pin_fence(obj);
6b95a207 2015
ce453d81 2016 dev_priv->mm.interruptible = true;
6b95a207 2017 return 0;
48b956c5
CW		 2018
2019err_unpin:
2020 i915_gem_object_unpin(obj);
ce453d81
CW		 2021err_interruptible:
2022 dev_priv->mm.interruptible = true;
48b956c5 2023 return ret;
6b95a207
KH		 2024}
2025
1690e1eb
CW		 2026void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2027{
2028 i915_gem_object_unpin_fence(obj);
2029 i915_gem_object_unpin(obj);
2030}
2031
c2c75131
DV		 2032/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
bc752862
CW		 2034unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035 unsigned int tiling_mode,
2036 unsigned int cpp,
2037 unsigned int pitch)
c2c75131 2038{
bc752862
CW		 2039 if (tiling_mode != I915_TILING_NONE) {
2040 unsigned int tile_rows, tiles;
c2c75131 2041
bc752862
CW		 2042 tile_rows = *y / 8;
2043 *y %= 8;
c2c75131 2044
bc752862
CW		 2045 tiles = *x / (512/cpp);
2046 *x %= 512/cpp;
2047
2048 return tile_rows * pitch * 8 + tiles * 4096;
2049 } else {
2050 unsigned int offset;
2051
2052 offset = *y * pitch + *x * cpp;
2053 *y = 0;
2054 *x = (offset & 4095) / cpp;
2055 return offset & -4096;
2056 }
c2c75131
DV		 2057}
2058
17638cd6
JB		 2059static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2060 int x, int y)
81255565
JB		 2061{
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
05394f39 2066 struct drm_i915_gem_object *obj;
81255565 2067 int plane = intel_crtc->plane;
e506a0c6 2068 unsigned long linear_offset;
81255565 2069 u32 dspcntr;
5eddb70b 2070 u32 reg;
81255565
JB		 2071
2072 switch (plane) {
2073 case 0:
2074 case 1:
2075 break;
2076 default:
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2078 return -EINVAL;
2079 }
2080
2081 intel_fb = to_intel_framebuffer(fb);
2082 obj = intel_fb->obj;
81255565 2083
5eddb70b
CW		 2084 reg = DSPCNTR(plane);
2085 dspcntr = I915_READ(reg);
81255565
JB		 2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2088 switch (fb->pixel_format) {
2089 case DRM_FORMAT_C8:
81255565
JB		 2090 dspcntr |= DISPPLANE_8BPP;
2091 break;
57779d06
VS		 2092 case DRM_FORMAT_XRGB1555:
2093 case DRM_FORMAT_ARGB1555:
2094 dspcntr |= DISPPLANE_BGRX555;
81255565 2095 break;
57779d06
VS		 2096 case DRM_FORMAT_RGB565:
2097 dspcntr |= DISPPLANE_BGRX565;
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 dspcntr |= DISPPLANE_BGRX888;
2102 break;
2103 case DRM_FORMAT_XBGR8888:
2104 case DRM_FORMAT_ABGR8888:
2105 dspcntr |= DISPPLANE_RGBX888;
2106 break;
2107 case DRM_FORMAT_XRGB2101010:
2108 case DRM_FORMAT_ARGB2101010:
2109 dspcntr |= DISPPLANE_BGRX101010;
2110 break;
2111 case DRM_FORMAT_XBGR2101010:
2112 case DRM_FORMAT_ABGR2101010:
2113 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2114 break;
2115 default:
baba133a 2116 BUG();
81255565 2117 }
57779d06 2118
a6c45cf0 2119 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2120 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2121 dspcntr |= DISPPLANE_TILED;
2122 else
2123 dspcntr &= ~DISPPLANE_TILED;
2124 }
2125
5eddb70b 2126 I915_WRITE(reg, dspcntr);
81255565 2127
e506a0c6 2128 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2129
c2c75131
DV		 2130 if (INTEL_INFO(dev)->gen >= 4) {
2131 intel_crtc->dspaddr_offset =
bc752862
CW		 2132 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2133 fb->bits_per_pixel / 8,
2134 fb->pitches[0]);
c2c75131
DV		 2135 linear_offset -= intel_crtc->dspaddr_offset;
2136 } else {
e506a0c6 2137 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2138 }
e506a0c6
DV		 2139
2140 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2141 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2142 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2143 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2144 I915_MODIFY_DISPBASE(DSPSURF(plane),
2145 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2146 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2147 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2148 } else
e506a0c6 2149 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2150 POSTING_READ(reg);
81255565 2151
17638cd6
JB		 2152 return 0;
2153}
2154
2155static int ironlake_update_plane(struct drm_crtc *crtc,
2156 struct drm_framebuffer *fb, int x, int y)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161 struct intel_framebuffer *intel_fb;
2162 struct drm_i915_gem_object *obj;
2163 int plane = intel_crtc->plane;
e506a0c6 2164 unsigned long linear_offset;
17638cd6
JB		 2165 u32 dspcntr;
2166 u32 reg;
2167
2168 switch (plane) {
2169 case 0:
2170 case 1:
27f8227b 2171 case 2:
17638cd6
JB		 2172 break;
2173 default:
2174 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2175 return -EINVAL;
2176 }
2177
2178 intel_fb = to_intel_framebuffer(fb);
2179 obj = intel_fb->obj;
2180
2181 reg = DSPCNTR(plane);
2182 dspcntr = I915_READ(reg);
2183 /* Mask out pixel format bits in case we change it */
2184 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2185 switch (fb->pixel_format) {
2186 case DRM_FORMAT_C8:
17638cd6
JB		 2187 dspcntr |= DISPPLANE_8BPP;
2188 break;
57779d06
VS		 2189 case DRM_FORMAT_RGB565:
2190 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2191 break;
57779d06
VS		 2192 case DRM_FORMAT_XRGB8888:
2193 case DRM_FORMAT_ARGB8888:
2194 dspcntr |= DISPPLANE_BGRX888;
2195 break;
2196 case DRM_FORMAT_XBGR8888:
2197 case DRM_FORMAT_ABGR8888:
2198 dspcntr |= DISPPLANE_RGBX888;
2199 break;
2200 case DRM_FORMAT_XRGB2101010:
2201 case DRM_FORMAT_ARGB2101010:
2202 dspcntr |= DISPPLANE_BGRX101010;
2203 break;
2204 case DRM_FORMAT_XBGR2101010:
2205 case DRM_FORMAT_ABGR2101010:
2206 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2207 break;
2208 default:
baba133a 2209 BUG();
17638cd6
JB		 2210 }
2211
2212 if (obj->tiling_mode != I915_TILING_NONE)
2213 dspcntr |= DISPPLANE_TILED;
2214 else
2215 dspcntr &= ~DISPPLANE_TILED;
2216
2217 /* must disable */
2218 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2219
2220 I915_WRITE(reg, dspcntr);
2221
e506a0c6 2222 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2223 intel_crtc->dspaddr_offset =
bc752862
CW		 2224 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2225 fb->bits_per_pixel / 8,
2226 fb->pitches[0]);
c2c75131 2227 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2228
e506a0c6
DV		 2229 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2230 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2231 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2232 I915_MODIFY_DISPBASE(DSPSURF(plane),
2233 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2234 if (IS_HASWELL(dev)) {
2235 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2236 } else {
2237 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2238 I915_WRITE(DSPLINOFF(plane), linear_offset);
2239 }
17638cd6
JB		 2240 POSTING_READ(reg);
2241
2242 return 0;
2243}
2244
2245/* Assume fb object is pinned & idle & fenced and just update base pointers */
2246static int
2247intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2248 int x, int y, enum mode_set_atomic state)
2249{
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2252
6b8e6ed0
CW		 2253 if (dev_priv->display.disable_fbc)
2254 dev_priv->display.disable_fbc(dev);
3dec0095 2255 intel_increase_pllclock(crtc);
81255565 2256
6b8e6ed0 2257 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2258}
2259
96a02917
VS		 2260void intel_display_handle_reset(struct drm_device *dev)
2261{
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct drm_crtc *crtc;
2264
2265 /*
2266 * Flips in the rings have been nuked by the reset,
2267 * so complete all pending flips so that user space
2268 * will get its events and not get stuck.
2269 *
2270 * Also update the base address of all primary
2271 * planes to the the last fb to make sure we're
2272 * showing the correct fb after a reset.
2273 *
2274 * Need to make two loops over the crtcs so that we
2275 * don't try to grab a crtc mutex before the
2276 * pending_flip_queue really got woken up.
2277 */
2278
2279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281 enum plane plane = intel_crtc->plane;
2282
2283 intel_prepare_page_flip(dev, plane);
2284 intel_finish_page_flip_plane(dev, plane);
2285 }
2286
2287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289
2290 mutex_lock(&crtc->mutex);
2291 if (intel_crtc->active)
2292 dev_priv->display.update_plane(crtc, crtc->fb,
2293 crtc->x, crtc->y);
2294 mutex_unlock(&crtc->mutex);
2295 }
2296}
2297
14667a4b
CW		 2298static int
2299intel_finish_fb(struct drm_framebuffer *old_fb)
2300{
2301 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2303 bool was_interruptible = dev_priv->mm.interruptible;
2304 int ret;
2305
14667a4b
CW		 2306 /* Big Hammer, we also need to ensure that any pending
2307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2308 * current scanout is retired before unpinning the old
2309 * framebuffer.
2310 *
2311 * This should only fail upon a hung GPU, in which case we
2312 * can safely continue.
2313 */
2314 dev_priv->mm.interruptible = false;
2315 ret = i915_gem_object_finish_gpu(obj);
2316 dev_priv->mm.interruptible = was_interruptible;
2317
2318 return ret;
2319}
2320
198598d0
VS		 2321static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2322{
2323 struct drm_device *dev = crtc->dev;
2324 struct drm_i915_master_private *master_priv;
2325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2326
2327 if (!dev->primary->master)
2328 return;
2329
2330 master_priv = dev->primary->master->driver_priv;
2331 if (!master_priv->sarea_priv)
2332 return;
2333
2334 switch (intel_crtc->pipe) {
2335 case 0:
2336 master_priv->sarea_priv->pipeA_x = x;
2337 master_priv->sarea_priv->pipeA_y = y;
2338 break;
2339 case 1:
2340 master_priv->sarea_priv->pipeB_x = x;
2341 master_priv->sarea_priv->pipeB_y = y;
2342 break;
2343 default:
2344 break;
2345 }
2346}
2347
5c3b82e2 2348static int
3c4fdcfb 2349intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2350 struct drm_framebuffer *fb)
79e53945
JB		 2351{
2352 struct drm_device *dev = crtc->dev;
6b8e6ed0 2353 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2355 struct drm_framebuffer *old_fb;
5c3b82e2 2356 int ret;
79e53945
JB		 2357
2358 /* no fb bound */
94352cf9 2359 if (!fb) {
a5071c2f 2360 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2361 return 0;
2362 }
2363
7eb552ae 2364 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2365 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2366 intel_crtc->plane,
7eb552ae 2367 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2368 return -EINVAL;
79e53945
JB		 2369 }
2370
5c3b82e2 2371 mutex_lock(&dev->struct_mutex);
265db958 2372 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2373 to_intel_framebuffer(fb)->obj,
919926ae 2374 NULL);
5c3b82e2
CW		 2375 if (ret != 0) {
2376 mutex_unlock(&dev->struct_mutex);
a5071c2f 2377 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2378 return ret;
2379 }
79e53945 2380
94352cf9 2381 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2382 if (ret) {
94352cf9 2383 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2384 mutex_unlock(&dev->struct_mutex);
a5071c2f 2385 DRM_ERROR("failed to update base address\n");
4e6cfefc 2386 return ret;
79e53945 2387 }
3c4fdcfb 2388
94352cf9
DV		 2389 old_fb = crtc->fb;
2390 crtc->fb = fb;
6c4c86f5
DV		 2391 crtc->x = x;
2392 crtc->y = y;
94352cf9 2393
b7f1de28
CW		 2394 if (old_fb) {
2395 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2396 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2397 }
652c393a 2398
6b8e6ed0 2399 intel_update_fbc(dev);
5c3b82e2 2400 mutex_unlock(&dev->struct_mutex);
79e53945 2401
198598d0 2402 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2403
2404 return 0;
79e53945
JB		 2405}
2406
5e84e1a4
ZW		 2407static void intel_fdi_normal_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
2413 u32 reg, temp;
2414
2415 /* enable normal train */
2416 reg = FDI_TX_CTL(pipe);
2417 temp = I915_READ(reg);
61e499bf 2418 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2419 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2420 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2421 } else {
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2424 }
5e84e1a4
ZW		 2425 I915_WRITE(reg, temp);
2426
2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
2429 if (HAS_PCH_CPT(dev)) {
2430 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2431 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2432 } else {
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_NONE;
2435 }
2436 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2437
2438 /* wait one idle pattern time */
2439 POSTING_READ(reg);
2440 udelay(1000);
357555c0
JB		 2441
2442 /* IVB wants error correction enabled */
2443 if (IS_IVYBRIDGE(dev))
2444 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2445 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2446}
2447
01a415fd
DV		 2448static void ivb_modeset_global_resources(struct drm_device *dev)
2449{
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct intel_crtc *pipe_B_crtc =
2452 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2453 struct intel_crtc *pipe_C_crtc =
2454 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2455 uint32_t temp;
2456
2457 /* When everything is off disable fdi C so that we could enable fdi B
2458 * with all lanes. XXX: This misses the case where a pipe is not using
2459 * any pch resources and so doesn't need any fdi lanes. */
2460 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2461 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2462 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2463
2464 temp = I915_READ(SOUTH_CHICKEN1);
2465 temp &= ~FDI_BC_BIFURCATION_SELECT;
2466 DRM_DEBUG_KMS("disabling fdi C rx\n");
2467 I915_WRITE(SOUTH_CHICKEN1, temp);
2468 }
2469}
2470
8db9d77b
ZW		 2471/* The FDI link training functions for ILK/Ibexpeak. */
2472static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2473{
2474 struct drm_device *dev = crtc->dev;
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2477 int pipe = intel_crtc->pipe;
0fc932b8 2478 int plane = intel_crtc->plane;
5eddb70b 2479 u32 reg, temp, tries;
8db9d77b 2480
0fc932b8
JB		 2481 /* FDI needs bits from pipe & plane first */
2482 assert_pipe_enabled(dev_priv, pipe);
2483 assert_plane_enabled(dev_priv, plane);
2484
e1a44743
AJ		 2485 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2486 for train result */
5eddb70b
CW		 2487 reg = FDI_RX_IMR(pipe);
2488 temp = I915_READ(reg);
e1a44743
AJ		 2489 temp &= ~FDI_RX_SYMBOL_LOCK;
2490 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2491 I915_WRITE(reg, temp);
2492 I915_READ(reg);
e1a44743
AJ		 2493 udelay(150);
2494
8db9d77b 2495 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
77ffb597
AJ		 2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2502 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2503
5eddb70b
CW		 2504 reg = FDI_RX_CTL(pipe);
2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 temp &= ~FDI_LINK_TRAIN_NONE;
2507 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2508 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2509
2510 POSTING_READ(reg);
8db9d77b
ZW		 2511 udelay(150);
2512
5b2adf89 2513 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2514 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2515 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2516 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2517
5eddb70b 2518 reg = FDI_RX_IIR(pipe);
e1a44743 2519 for (tries = 0; tries < 5; tries++) {
5eddb70b 2520 temp = I915_READ(reg);
8db9d77b
ZW		 2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523 if ((temp & FDI_RX_BIT_LOCK)) {
2524 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2526 break;
2527 }
8db9d77b 2528 }
e1a44743 2529 if (tries == 5)
5eddb70b 2530 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2531
2532 /* Train 2 */
5eddb70b
CW		 2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2537 I915_WRITE(reg, temp);
8db9d77b 2538
5eddb70b
CW		 2539 reg = FDI_RX_CTL(pipe);
2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2543 I915_WRITE(reg, temp);
8db9d77b 2544
5eddb70b
CW		 2545 POSTING_READ(reg);
2546 udelay(150);
8db9d77b 2547
5eddb70b 2548 reg = FDI_RX_IIR(pipe);
e1a44743 2549 for (tries = 0; tries < 5; tries++) {
5eddb70b 2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2552
2553 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2554 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2555 DRM_DEBUG_KMS("FDI train 2 done.\n");
2556 break;
2557 }
8db9d77b 2558 }
e1a44743 2559 if (tries == 5)
5eddb70b 2560 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2561
2562 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2563
8db9d77b
ZW		 2564}
2565
0206e353 2566static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2567 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2568 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2569 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2570 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2571};
2572
2573/* The FDI link training functions for SNB/Cougarpoint. */
2574static void gen6_fdi_link_train(struct drm_crtc *crtc)
2575{
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579 int pipe = intel_crtc->pipe;
fa37d39e 2580 u32 reg, temp, i, retry;
8db9d77b 2581
e1a44743
AJ		 2582 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2583 for train result */
5eddb70b
CW		 2584 reg = FDI_RX_IMR(pipe);
2585 temp = I915_READ(reg);
e1a44743
AJ		 2586 temp &= ~FDI_RX_SYMBOL_LOCK;
2587 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
e1a44743
AJ		 2591 udelay(150);
2592
8db9d77b 2593 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2594 reg = FDI_TX_CTL(pipe);
2595 temp = I915_READ(reg);
77ffb597
AJ		 2596 temp &= ~(7 << 19);
2597 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2601 /* SNB-B */
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2603 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2604
d74cf324
DV		 2605 I915_WRITE(FDI_RX_MISC(pipe),
2606 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2607
5eddb70b
CW		 2608 reg = FDI_RX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 if (HAS_PCH_CPT(dev)) {
2611 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2612 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2613 } else {
2614 temp &= ~FDI_LINK_TRAIN_NONE;
2615 temp |= FDI_LINK_TRAIN_PATTERN_1;
2616 }
5eddb70b
CW		 2617 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2618
2619 POSTING_READ(reg);
8db9d77b
ZW		 2620 udelay(150);
2621
0206e353 2622 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
8db9d77b
ZW		 2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2627 I915_WRITE(reg, temp);
2628
2629 POSTING_READ(reg);
8db9d77b
ZW		 2630 udelay(500);
2631
fa37d39e
SP		 2632 for (retry = 0; retry < 5; retry++) {
2633 reg = FDI_RX_IIR(pipe);
2634 temp = I915_READ(reg);
2635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2636 if (temp & FDI_RX_BIT_LOCK) {
2637 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2638 DRM_DEBUG_KMS("FDI train 1 done.\n");
2639 break;
2640 }
2641 udelay(50);
8db9d77b 2642 }
fa37d39e
SP		 2643 if (retry < 5)
2644 break;
8db9d77b
ZW		 2645 }
2646 if (i == 4)
5eddb70b 2647 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2648
2649 /* Train 2 */
5eddb70b
CW		 2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
8db9d77b
ZW		 2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 if (IS_GEN6(dev)) {
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656 /* SNB-B */
2657 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2658 }
5eddb70b 2659 I915_WRITE(reg, temp);
8db9d77b 2660
5eddb70b
CW		 2661 reg = FDI_RX_CTL(pipe);
2662 temp = I915_READ(reg);
8db9d77b
ZW		 2663 if (HAS_PCH_CPT(dev)) {
2664 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2665 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2666 } else {
2667 temp &= ~FDI_LINK_TRAIN_NONE;
2668 temp |= FDI_LINK_TRAIN_PATTERN_2;
2669 }
5eddb70b
CW		 2670 I915_WRITE(reg, temp);
2671
2672 POSTING_READ(reg);
8db9d77b
ZW		 2673 udelay(150);
2674
0206e353 2675 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2676 reg = FDI_TX_CTL(pipe);
2677 temp = I915_READ(reg);
8db9d77b
ZW		 2678 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2680 I915_WRITE(reg, temp);
2681
2682 POSTING_READ(reg);
8db9d77b
ZW		 2683 udelay(500);
2684
fa37d39e
SP		 2685 for (retry = 0; retry < 5; retry++) {
2686 reg = FDI_RX_IIR(pipe);
2687 temp = I915_READ(reg);
2688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689 if (temp & FDI_RX_SYMBOL_LOCK) {
2690 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2691 DRM_DEBUG_KMS("FDI train 2 done.\n");
2692 break;
2693 }
2694 udelay(50);
8db9d77b 2695 }
fa37d39e
SP		 2696 if (retry < 5)
2697 break;
8db9d77b
ZW		 2698 }
2699 if (i == 4)
5eddb70b 2700 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2701
2702 DRM_DEBUG_KMS("FDI train done.\n");
2703}
2704
357555c0
JB		 2705/* Manual link training for Ivy Bridge A0 parts */
2706static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2707{
2708 struct drm_device *dev = crtc->dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711 int pipe = intel_crtc->pipe;
2712 u32 reg, temp, i;
2713
2714 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2715 for train result */
2716 reg = FDI_RX_IMR(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_RX_SYMBOL_LOCK;
2719 temp &= ~FDI_RX_BIT_LOCK;
2720 I915_WRITE(reg, temp);
2721
2722 POSTING_READ(reg);
2723 udelay(150);
2724
01a415fd
DV		 2725 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2726 I915_READ(FDI_RX_IIR(pipe)));
2727
357555c0
JB		 2728 /* enable CPU FDI TX and PCH FDI RX */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~(7 << 19);
2732 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2733 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2737 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2739
d74cf324
DV		 2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2742
357555c0
JB		 2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp &= ~FDI_LINK_TRAIN_AUTO;
2746 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2747 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2748 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2749 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750
2751 POSTING_READ(reg);
2752 udelay(150);
2753
0206e353 2754 for (i = 0; i < 4; i++) {
357555c0
JB		 2755 reg = FDI_TX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= snb_b_fdi_train_param[i];
2759 I915_WRITE(reg, temp);
2760
2761 POSTING_READ(reg);
2762 udelay(500);
2763
2764 reg = FDI_RX_IIR(pipe);
2765 temp = I915_READ(reg);
2766 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2767
2768 if (temp & FDI_RX_BIT_LOCK ||
2769 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2770 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2771 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2772 break;
2773 }
2774 }
2775 if (i == 4)
2776 DRM_ERROR("FDI train 1 fail!\n");
2777
2778 /* Train 2 */
2779 reg = FDI_TX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2782 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2783 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2784 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2785 I915_WRITE(reg, temp);
2786
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2790 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2791 I915_WRITE(reg, temp);
2792
2793 POSTING_READ(reg);
2794 udelay(150);
2795
0206e353 2796 for (i = 0; i < 4; i++) {
357555c0
JB		 2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2800 temp |= snb_b_fdi_train_param[i];
2801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(500);
2805
2806 reg = FDI_RX_IIR(pipe);
2807 temp = I915_READ(reg);
2808 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2809
2810 if (temp & FDI_RX_SYMBOL_LOCK) {
2811 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2812 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2813 break;
2814 }
2815 }
2816 if (i == 4)
2817 DRM_ERROR("FDI train 2 fail!\n");
2818
2819 DRM_DEBUG_KMS("FDI train done.\n");
2820}
2821
88cefb6c 2822static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2823{
88cefb6c 2824 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2825 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2826 int pipe = intel_crtc->pipe;
5eddb70b 2827 u32 reg, temp;
79e53945 2828
c64e311e 2829
c98e9dcf 2830 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2831 reg = FDI_RX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2834 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2836 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2837
2838 POSTING_READ(reg);
c98e9dcf
JB		 2839 udelay(200);
2840
2841 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp | FDI_PCDCLK);
2844
2845 POSTING_READ(reg);
c98e9dcf
JB		 2846 udelay(200);
2847
20749730
PZ		 2848 /* Enable CPU FDI TX PLL, always on for Ironlake */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2852 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2853
20749730
PZ		 2854 POSTING_READ(reg);
2855 udelay(100);
6be4a607 2856 }
0e23b99d
JB		 2857}
2858
88cefb6c
DV		 2859static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2860{
2861 struct drm_device *dev = intel_crtc->base.dev;
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 int pipe = intel_crtc->pipe;
2864 u32 reg, temp;
2865
2866 /* Switch from PCDclk to Rawclk */
2867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2870
2871 /* Disable CPU FDI TX PLL */
2872 reg = FDI_TX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2875
2876 POSTING_READ(reg);
2877 udelay(100);
2878
2879 reg = FDI_RX_CTL(pipe);
2880 temp = I915_READ(reg);
2881 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2882
2883 /* Wait for the clocks to turn off. */
2884 POSTING_READ(reg);
2885 udelay(100);
2886}
2887
0fc932b8
JB		 2888static void ironlake_fdi_disable(struct drm_crtc *crtc)
2889{
2890 struct drm_device *dev = crtc->dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893 int pipe = intel_crtc->pipe;
2894 u32 reg, temp;
2895
2896 /* disable CPU FDI tx and PCH FDI rx */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2900 POSTING_READ(reg);
2901
2902 reg = FDI_RX_CTL(pipe);
2903 temp = I915_READ(reg);
2904 temp &= ~(0x7 << 16);
dfd07d72 2905 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2906 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2907
2908 POSTING_READ(reg);
2909 udelay(100);
2910
2911 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2912 if (HAS_PCH_IBX(dev)) {
2913 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2914 }
0fc932b8
JB		 2915
2916 /* still set train pattern 1 */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~FDI_LINK_TRAIN_NONE;
2920 temp |= FDI_LINK_TRAIN_PATTERN_1;
2921 I915_WRITE(reg, temp);
2922
2923 reg = FDI_RX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 if (HAS_PCH_CPT(dev)) {
2926 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2928 } else {
2929 temp &= ~FDI_LINK_TRAIN_NONE;
2930 temp |= FDI_LINK_TRAIN_PATTERN_1;
2931 }
2932 /* BPC in FDI rx is consistent with that in PIPECONF */
2933 temp &= ~(0x07 << 16);
dfd07d72 2934 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2935 I915_WRITE(reg, temp);
2936
2937 POSTING_READ(reg);
2938 udelay(100);
2939}
2940
5bb61643
CW		 2941static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2942{
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2946 unsigned long flags;
2947 bool pending;
2948
10d83730
VS		 2949 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2950 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2951 return false;
2952
2953 spin_lock_irqsave(&dev->event_lock, flags);
2954 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2955 spin_unlock_irqrestore(&dev->event_lock, flags);
2956
2957 return pending;
2958}
2959
e6c3a2a6
CW		 2960static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2961{
0f91128d 2962 struct drm_device *dev = crtc->dev;
5bb61643 2963 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2964
2965 if (crtc->fb == NULL)
2966 return;
2967
2c10d571
DV		 2968 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2969
5bb61643
CW		 2970 wait_event(dev_priv->pending_flip_queue,
2971 !intel_crtc_has_pending_flip(crtc));
2972
0f91128d
CW		 2973 mutex_lock(&dev->struct_mutex);
2974 intel_finish_fb(crtc->fb);
2975 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2976}
2977
fc316cbe
PZ		 2978static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2979{
2980 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2981}
2982
e615efe4
ED		 2983/* Program iCLKIP clock to the desired frequency */
2984static void lpt_program_iclkip(struct drm_crtc *crtc)
2985{
2986 struct drm_device *dev = crtc->dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2989 u32 temp;
2990
09153000
DV		 2991 mutex_lock(&dev_priv->dpio_lock);
2992
e615efe4
ED		 2993 /* It is necessary to ungate the pixclk gate prior to programming
2994 * the divisors, and gate it back when it is done.
2995 */
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2997
2998 /* Disable SSCCTL */
2999 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3000 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3001 SBI_SSCCTL_DISABLE,
3002 SBI_ICLK);
e615efe4
ED		 3003
3004 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3005 if (crtc->mode.clock == 20000) {
3006 auxdiv = 1;
3007 divsel = 0x41;
3008 phaseinc = 0x20;
3009 } else {
3010 /* The iCLK virtual clock root frequency is in MHz,
3011 * but the crtc->mode.clock in in KHz. To get the divisors,
3012 * it is necessary to divide one by another, so we
3013 * convert the virtual clock precision to KHz here for higher
3014 * precision.
3015 */
3016 u32 iclk_virtual_root_freq = 172800 * 1000;
3017 u32 iclk_pi_range = 64;
3018 u32 desired_divisor, msb_divisor_value, pi_value;
3019
3020 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3021 msb_divisor_value = desired_divisor / iclk_pi_range;
3022 pi_value = desired_divisor % iclk_pi_range;
3023
3024 auxdiv = 0;
3025 divsel = msb_divisor_value - 2;
3026 phaseinc = pi_value;
3027 }
3028
3029 /* This should not happen with any sane values */
3030 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3031 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3033 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3034
3035 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3036 crtc->mode.clock,
3037 auxdiv,
3038 divsel,
3039 phasedir,
3040 phaseinc);
3041
3042 /* Program SSCDIVINTPHASE6 */
988d6ee8 3043 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3044 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3045 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3046 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3048 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3049 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3050 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3051
3052 /* Program SSCAUXDIV */
988d6ee8 3053 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3054 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3055 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3056 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3057
3058 /* Enable modulator and associated divider */
988d6ee8 3059 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3060 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3061 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3062
3063 /* Wait for initialization time */
3064 udelay(24);
3065
3066 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3067
3068 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3069}
3070
f67a559d
JB		 3071/*
3072 * Enable PCH resources required for PCH ports:
3073 * - PCH PLLs
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3077 * - transcoder
3078 */
3079static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3080{
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
ee7b9f93 3085 u32 reg, temp;
2c07245f 3086
e7e164db
CW		 3087 assert_transcoder_disabled(dev_priv, pipe);
3088
cd986abb
DV		 3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
c98e9dcf 3094 /* For PCH output, training FDI link */
674cf967 3095 dev_priv->display.fdi_link_train(crtc);
2c07245f 3096
572deb37
DV		 3097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3100 *
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
b6b4e185 3104 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3105
303b81e0 3106 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3107 u32 sel;
4b645f14 3108
c98e9dcf 3109 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3110 switch (pipe) {
3111 default:
3112 case 0:
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3115 break;
3116 case 1:
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3119 break;
3120 case 2:
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3123 break;
d64311ab 3124 }
ee7b9f93
JB		 3125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126 temp |= sel;
3127 else
3128 temp &= ~sel;
c98e9dcf 3129 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3130 }
5eddb70b 3131
d9b6cb56
JB		 3132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3137
5eddb70b
CW		 3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3142
303b81e0 3143 intel_fdi_normal_train(crtc);
5e84e1a4 3144
c98e9dcf
JB		 3145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3153 TRANS_DP_SYNC_MASK |
3154 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
9325c9f0 3157 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3158
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3163
3164 switch (intel_trans_dp_port_sel(crtc)) {
3165 case PCH_DP_B:
5eddb70b 3166 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3167 break;
3168 case PCH_DP_C:
5eddb70b 3169 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3170 break;
3171 case PCH_DP_D:
5eddb70b 3172 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3173 break;
3174 default:
e95d41e1 3175 BUG();
32f9d658 3176 }
2c07245f 3177
5eddb70b 3178 I915_WRITE(reg, temp);
6be4a607 3179 }
b52eb4dc 3180
b8a4f404 3181 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3182}
3183
1507e5bd
PZ		 3184static void lpt_pch_enable(struct drm_crtc *crtc)
3185{
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3190
daed2dbb 3191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3192
8c52b5e8 3193 lpt_program_iclkip(crtc);
1507e5bd 3194
0540e488 3195 /* Set transcoder timing. */
daed2dbb
PZ		 3196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3199
daed2dbb
PZ		 3200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3204
937bb610 3205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3206}
3207
ee7b9f93
JB		 3208static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3209{
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3211
3212 if (pll == NULL)
3213 return;
3214
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3217 return;
3218 }
3219
3220 --pll->refcount;
3221 intel_crtc->pch_pll = NULL;
3222}
3223
3224static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3225{
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3228 int i;
3229
3230 pll = intel_crtc->pch_pll;
3231 if (pll) {
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3234 goto prepare;
3235 }
3236
98b6bd99
DV		 3237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3241
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3244
3245 goto found;
3246 }
3247
ee7b9f93
JB		 3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3253 continue;
3254
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3260
3261 goto found;
3262 }
3263 }
3264
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3271 goto found;
3272 }
3273 }
3274
3275 return NULL;
3276
3277found:
3278 intel_crtc->pch_pll = pll;
3279 pll->refcount++;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3283
e04c7350
CW		 3284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3286 POSTING_READ(pll->pll_reg);
3287 udelay(150);
e04c7350
CW		 3288
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3291 pll->on = false;
3292 return pll;
3293}
3294
d4270e57
JB		 3295void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3296{
3297 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3298 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3299 u32 temp;
3300
3301 temp = I915_READ(dslreg);
3302 udelay(500);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3306 }
3307}
3308
f67a559d
JB		 3309static void ironlake_crtc_enable(struct drm_crtc *crtc)
3310{
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3314 struct intel_encoder *encoder;
f67a559d
JB		 3315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3317 u32 temp;
f67a559d 3318
08a48469
DV		 3319 WARN_ON(!crtc->enabled);
3320
f67a559d
JB		 3321 if (intel_crtc->active)
3322 return;
3323
3324 intel_crtc->active = true;
3325 intel_update_watermarks(dev);
3326
3327 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3328 temp = I915_READ(PCH_LVDS);
3329 if ((temp & LVDS_PORT_EN) == 0)
3330 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3331 }
3332
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3335 /* Note: FDI PLL enabling _must_ be done before we enable the
3336 * cpu pipes, hence this is separate from all the other fdi/pch
3337 * enabling. */
88cefb6c 3338 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3339 } else {
3340 assert_fdi_tx_disabled(dev_priv, pipe);
3341 assert_fdi_rx_disabled(dev_priv, pipe);
3342 }
f67a559d 3343
bf49ec8c
DV		 3344 for_each_encoder_on_crtc(dev, crtc, encoder)
3345 if (encoder->pre_enable)
3346 encoder->pre_enable(encoder);
f67a559d
JB		 3347
3348 /* Enable panel fitting for LVDS */
3349 if (dev_priv->pch_pf_size &&
547dc041
JN		 3350 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3352 /* Force use of hard-coded filter coefficients
3353 * as some pre-programmed values are broken,
3354 * e.g. x201.
3355 */
13888d78
PZ		 3356 if (IS_IVYBRIDGE(dev))
3357 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3358 PF_PIPE_SEL_IVB(pipe));
3359 else
3360 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3361 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3362 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3363 }
3364
9c54c0dd
JB		 3365 /*
3366 * On ILK+ LUT must be loaded before the pipe is running but with
3367 * clocks enabled
3368 */
3369 intel_crtc_load_lut(crtc);
3370
5bfe2ac0
DV		 3371 intel_enable_pipe(dev_priv, pipe,
3372 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3373 intel_enable_plane(dev_priv, plane, pipe);
3374
5bfe2ac0 3375 if (intel_crtc->config.has_pch_encoder)
f67a559d 3376 ironlake_pch_enable(crtc);
c98e9dcf 3377
d1ebd816 3378 mutex_lock(&dev->struct_mutex);
bed4a673 3379 intel_update_fbc(dev);
d1ebd816
BW		 3380 mutex_unlock(&dev->struct_mutex);
3381
6b383a7f 3382 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3383
fa5c73b1
DV		 3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 encoder->enable(encoder);
61b77ddd
DV		 3386
3387 if (HAS_PCH_CPT(dev))
3388 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3389
3390 /*
3391 * There seems to be a race in PCH platform hw (at least on some
3392 * outputs) where an enabled pipe still completes any pageflip right
3393 * away (as if the pipe is off) instead of waiting for vblank. As soon
3394 * as the first vblank happend, everything works as expected. Hence just
3395 * wait for one vblank before returning to avoid strange things
3396 * happening.
3397 */
3398 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3399}
3400
4f771f10
PZ		 3401static void haswell_crtc_enable(struct drm_crtc *crtc)
3402{
3403 struct drm_device *dev = crtc->dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3406 struct intel_encoder *encoder;
3407 int pipe = intel_crtc->pipe;
3408 int plane = intel_crtc->plane;
4f771f10
PZ		 3409
3410 WARN_ON(!crtc->enabled);
3411
3412 if (intel_crtc->active)
3413 return;
3414
3415 intel_crtc->active = true;
3416 intel_update_watermarks(dev);
3417
5bfe2ac0 3418 if (intel_crtc->config.has_pch_encoder)
04945641 3419 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3420
3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3422 if (encoder->pre_enable)
3423 encoder->pre_enable(encoder);
3424
1f544388 3425 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3426
1f544388 3427 /* Enable panel fitting for eDP */
547dc041
JN		 3428 if (dev_priv->pch_pf_size &&
3429 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3430 /* Force use of hard-coded filter coefficients
3431 * as some pre-programmed values are broken,
3432 * e.g. x201.
3433 */
54075a7d
PZ		 3434 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3435 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3436 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3437 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3438 }
3439
3440 /*
3441 * On ILK+ LUT must be loaded before the pipe is running but with
3442 * clocks enabled
3443 */
3444 intel_crtc_load_lut(crtc);
3445
1f544388 3446 intel_ddi_set_pipe_settings(crtc);
8228c251 3447 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3448
5bfe2ac0
DV		 3449 intel_enable_pipe(dev_priv, pipe,
3450 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3451 intel_enable_plane(dev_priv, plane, pipe);
3452
5bfe2ac0 3453 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3454 lpt_pch_enable(crtc);
4f771f10
PZ		 3455
3456 mutex_lock(&dev->struct_mutex);
3457 intel_update_fbc(dev);
3458 mutex_unlock(&dev->struct_mutex);
3459
3460 intel_crtc_update_cursor(crtc, true);
3461
3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 encoder->enable(encoder);
3464
4f771f10
PZ		 3465 /*
3466 * There seems to be a race in PCH platform hw (at least on some
3467 * outputs) where an enabled pipe still completes any pageflip right
3468 * away (as if the pipe is off) instead of waiting for vblank. As soon
3469 * as the first vblank happend, everything works as expected. Hence just
3470 * wait for one vblank before returning to avoid strange things
3471 * happening.
3472 */
3473 intel_wait_for_vblank(dev, intel_crtc->pipe);
3474}
3475
6be4a607
JB		 3476static void ironlake_crtc_disable(struct drm_crtc *crtc)
3477{
3478 struct drm_device *dev = crtc->dev;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3481 struct intel_encoder *encoder;
6be4a607
JB		 3482 int pipe = intel_crtc->pipe;
3483 int plane = intel_crtc->plane;
5eddb70b 3484 u32 reg, temp;
b52eb4dc 3485
ef9c3aee 3486
f7abfe8b
CW		 3487 if (!intel_crtc->active)
3488 return;
3489
ea9d758d
DV		 3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 encoder->disable(encoder);
3492
e6c3a2a6 3493 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3494 drm_vblank_off(dev, pipe);
6b383a7f 3495 intel_crtc_update_cursor(crtc, false);
5eddb70b 3496
b24e7179 3497 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3498
973d04f9
CW		 3499 if (dev_priv->cfb_plane == plane)
3500 intel_disable_fbc(dev);
2c07245f 3501
b24e7179 3502 intel_disable_pipe(dev_priv, pipe);
32f9d658 3503
6be4a607 3504 /* Disable PF */
9db4a9c7
JB		 3505 I915_WRITE(PF_CTL(pipe), 0);
3506 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3507
bf49ec8c
DV		 3508 for_each_encoder_on_crtc(dev, crtc, encoder)
3509 if (encoder->post_disable)
3510 encoder->post_disable(encoder);
2c07245f 3511
0fc932b8 3512 ironlake_fdi_disable(crtc);
249c0e64 3513
b8a4f404 3514 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3515
6be4a607
JB		 3516 if (HAS_PCH_CPT(dev)) {
3517 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3518 reg = TRANS_DP_CTL(pipe);
3519 temp = I915_READ(reg);
3520 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3521 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3522 I915_WRITE(reg, temp);
6be4a607
JB		 3523
3524 /* disable DPLL_SEL */
3525 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3526 switch (pipe) {
3527 case 0:
d64311ab 3528 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3529 break;
3530 case 1:
6be4a607 3531 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3532 break;
3533 case 2:
4b645f14 3534 /* C shares PLL A or B */
d64311ab 3535 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3536 break;
3537 default:
3538 BUG(); /* wtf */
3539 }
6be4a607 3540 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3541 }
e3421a18 3542
6be4a607 3543 /* disable PCH DPLL */
ee7b9f93 3544 intel_disable_pch_pll(intel_crtc);
8db9d77b 3545
88cefb6c 3546 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3547
f7abfe8b 3548 intel_crtc->active = false;
6b383a7f 3549 intel_update_watermarks(dev);
d1ebd816
BW		 3550
3551 mutex_lock(&dev->struct_mutex);
6b383a7f 3552 intel_update_fbc(dev);
d1ebd816 3553 mutex_unlock(&dev->struct_mutex);
6be4a607 3554}
1b3c7a47 3555
4f771f10 3556static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3557{
4f771f10
PZ		 3558 struct drm_device *dev = crtc->dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3561 struct intel_encoder *encoder;
3562 int pipe = intel_crtc->pipe;
3563 int plane = intel_crtc->plane;
ad80a810 3564 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3565 bool is_pch_port;
ee7b9f93 3566
4f771f10
PZ		 3567 if (!intel_crtc->active)
3568 return;
3569
83616634
PZ		 3570 is_pch_port = haswell_crtc_driving_pch(crtc);
3571
4f771f10
PZ		 3572 for_each_encoder_on_crtc(dev, crtc, encoder)
3573 encoder->disable(encoder);
3574
3575 intel_crtc_wait_for_pending_flips(crtc);
3576 drm_vblank_off(dev, pipe);
3577 intel_crtc_update_cursor(crtc, false);
3578
3579 intel_disable_plane(dev_priv, plane, pipe);
3580
3581 if (dev_priv->cfb_plane == plane)
3582 intel_disable_fbc(dev);
3583
3584 intel_disable_pipe(dev_priv, pipe);
3585
ad80a810 3586 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3587
3588 /* Disable PF */
3589 I915_WRITE(PF_CTL(pipe), 0);
3590 I915_WRITE(PF_WIN_SZ(pipe), 0);
3591
1f544388 3592 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3593
3594 for_each_encoder_on_crtc(dev, crtc, encoder)
3595 if (encoder->post_disable)
3596 encoder->post_disable(encoder);
3597
83616634 3598 if (is_pch_port) {
ab4d966c 3599 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3600 intel_ddi_fdi_disable(crtc);
83616634 3601 }
4f771f10
PZ		 3602
3603 intel_crtc->active = false;
3604 intel_update_watermarks(dev);
3605
3606 mutex_lock(&dev->struct_mutex);
3607 intel_update_fbc(dev);
3608 mutex_unlock(&dev->struct_mutex);
3609}
3610
ee7b9f93
JB		 3611static void ironlake_crtc_off(struct drm_crtc *crtc)
3612{
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614 intel_put_pch_pll(intel_crtc);
3615}
3616
6441ab5f
PZ		 3617static void haswell_crtc_off(struct drm_crtc *crtc)
3618{
a5c961d1
PZ		 3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620
3621 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3622 * start using it. */
1a240d4d 3623 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3624
6441ab5f
PZ		 3625 intel_ddi_put_crtc_pll(crtc);
3626}
3627
02e792fb
DV		 3628static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3629{
02e792fb 3630 if (!enable && intel_crtc->overlay) {
23f09ce3 3631 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3632 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3633
23f09ce3 3634 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3635 dev_priv->mm.interruptible = false;
3636 (void) intel_overlay_switch_off(intel_crtc->overlay);
3637 dev_priv->mm.interruptible = true;
23f09ce3 3638 mutex_unlock(&dev->struct_mutex);
02e792fb 3639 }
02e792fb 3640
5dcdbcb0
CW		 3641 /* Let userspace switch the overlay on again. In most cases userspace
3642 * has to recompute where to put it anyway.
3643 */
02e792fb
DV		 3644}
3645
61bc95c1
EE		 3646/**
3647 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3648 * cursor plane briefly if not already running after enabling the display
3649 * plane.
3650 * This workaround avoids occasional blank screens when self refresh is
3651 * enabled.
3652 */
3653static void
3654g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3655{
3656 u32 cntl = I915_READ(CURCNTR(pipe));
3657
3658 if ((cntl & CURSOR_MODE) == 0) {
3659 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3660
3661 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3662 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3663 intel_wait_for_vblank(dev_priv->dev, pipe);
3664 I915_WRITE(CURCNTR(pipe), cntl);
3665 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3666 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3667 }
3668}
3669
0b8765c6 3670static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3671{
3672 struct drm_device *dev = crtc->dev;
79e53945
JB		 3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3675 struct intel_encoder *encoder;
79e53945 3676 int pipe = intel_crtc->pipe;
80824003 3677 int plane = intel_crtc->plane;
79e53945 3678
08a48469
DV		 3679 WARN_ON(!crtc->enabled);
3680
f7abfe8b
CW		 3681 if (intel_crtc->active)
3682 return;
3683
3684 intel_crtc->active = true;
6b383a7f
CW		 3685 intel_update_watermarks(dev);
3686
63d7bbe9 3687 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3688
3689 for_each_encoder_on_crtc(dev, crtc, encoder)
3690 if (encoder->pre_enable)
3691 encoder->pre_enable(encoder);
3692
040484af 3693 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3694 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3695 if (IS_G4X(dev))
3696 g4x_fixup_plane(dev_priv, pipe);
79e53945 3697
0b8765c6 3698 intel_crtc_load_lut(crtc);
bed4a673 3699 intel_update_fbc(dev);
79e53945 3700
0b8765c6
JB		 3701 /* Give the overlay scaler a chance to enable if it's on this pipe */
3702 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3703 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3704
fa5c73b1
DV		 3705 for_each_encoder_on_crtc(dev, crtc, encoder)
3706 encoder->enable(encoder);
0b8765c6 3707}
79e53945 3708
0b8765c6
JB		 3709static void i9xx_crtc_disable(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3714 struct intel_encoder *encoder;
0b8765c6
JB		 3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
24a1f16d 3717 u32 pctl;
b690e96c 3718
ef9c3aee 3719
f7abfe8b
CW		 3720 if (!intel_crtc->active)
3721 return;
3722
ea9d758d
DV		 3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->disable(encoder);
3725
0b8765c6 3726 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3727 intel_crtc_wait_for_pending_flips(crtc);
3728 drm_vblank_off(dev, pipe);
0b8765c6 3729 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3730 intel_crtc_update_cursor(crtc, false);
0b8765c6 3731
973d04f9
CW		 3732 if (dev_priv->cfb_plane == plane)
3733 intel_disable_fbc(dev);
79e53945 3734
b24e7179 3735 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3736 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3737
3738 /* Disable pannel fitter if it is on this pipe. */
3739 pctl = I915_READ(PFIT_CONTROL);
3740 if ((pctl & PFIT_ENABLE) &&
3741 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3742 I915_WRITE(PFIT_CONTROL, 0);
3743
63d7bbe9 3744 intel_disable_pll(dev_priv, pipe);
0b8765c6 3745
f7abfe8b 3746 intel_crtc->active = false;
6b383a7f
CW		 3747 intel_update_fbc(dev);
3748 intel_update_watermarks(dev);
0b8765c6
JB		 3749}
3750
ee7b9f93
JB		 3751static void i9xx_crtc_off(struct drm_crtc *crtc)
3752{
3753}
3754
976f8a20
DV		 3755static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3756 bool enabled)
2c07245f
ZW		 3757{
3758 struct drm_device *dev = crtc->dev;
3759 struct drm_i915_master_private *master_priv;
3760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3761 int pipe = intel_crtc->pipe;
79e53945
JB		 3762
3763 if (!dev->primary->master)
3764 return;
3765
3766 master_priv = dev->primary->master->driver_priv;
3767 if (!master_priv->sarea_priv)
3768 return;
3769
79e53945
JB		 3770 switch (pipe) {
3771 case 0:
3772 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3774 break;
3775 case 1:
3776 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3777 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3778 break;
3779 default:
9db4a9c7 3780 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3781 break;
3782 }
79e53945
JB		 3783}
3784
976f8a20
DV		 3785/**
3786 * Sets the power management mode of the pipe and plane.
3787 */
3788void intel_crtc_update_dpms(struct drm_crtc *crtc)
3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_encoder *intel_encoder;
3793 bool enable = false;
3794
3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3796 enable |= intel_encoder->connectors_active;
3797
3798 if (enable)
3799 dev_priv->display.crtc_enable(crtc);
3800 else
3801 dev_priv->display.crtc_disable(crtc);
3802
3803 intel_crtc_update_sarea(crtc, enable);
3804}
3805
cdd59983
CW		 3806static void intel_crtc_disable(struct drm_crtc *crtc)
3807{
cdd59983 3808 struct drm_device *dev = crtc->dev;
976f8a20 3809 struct drm_connector *connector;
ee7b9f93 3810 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3812
976f8a20
DV		 3813 /* crtc should still be enabled when we disable it. */
3814 WARN_ON(!crtc->enabled);
3815
7b9f35a6 3816 intel_crtc->eld_vld = false;
976f8a20
DV		 3817 dev_priv->display.crtc_disable(crtc);
3818 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3819 dev_priv->display.off(crtc);
3820
931872fc
CW		 3821 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3823
3824 if (crtc->fb) {
3825 mutex_lock(&dev->struct_mutex);
1690e1eb 3826 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3827 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3828 crtc->fb = NULL;
3829 }
3830
3831 /* Update computed state. */
3832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833 if (!connector->encoder || !connector->encoder->crtc)
3834 continue;
3835
3836 if (connector->encoder->crtc != crtc)
3837 continue;
3838
3839 connector->dpms = DRM_MODE_DPMS_OFF;
3840 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3841 }
3842}
3843
a261b246 3844void intel_modeset_disable(struct drm_device *dev)
79e53945 3845{
a261b246
DV		 3846 struct drm_crtc *crtc;
3847
3848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3849 if (crtc->enabled)
3850 intel_crtc_disable(crtc);
3851 }
79e53945
JB		 3852}
3853
ea5b213a 3854void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3855{
4ef69c7a 3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3857
ea5b213a
CW		 3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
7e7d76c3
JB		 3860}
3861
5ab432ef
DV		 3862/* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3866{
5ab432ef
DV		 3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3869
b2cabb0e 3870 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3871 } else {
3872 encoder->connectors_active = false;
3873
b2cabb0e 3874 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3875 }
79e53945
JB		 3876}
3877
0a91ca29
DV		 3878/* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
b980514c 3880static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3881{
0a91ca29
DV		 3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3886 enum pipe pipe;
3887
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3891
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3898
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3902 return;
3903
3904 crtc = encoder->base.crtc;
3905
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3910 }
79e53945
JB		 3911}
3912
5ab432ef
DV		 3913/* Even simpler default implementation, if there's really no special case to
3914 * consider. */
3915void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3916{
5ab432ef 3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3918
5ab432ef
DV		 3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
d4270e57 3922
5ab432ef
DV		 3923 if (mode == connector->dpms)
3924 return;
3925
3926 connector->dpms = mode;
3927
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3931 else
8af6cf88 3932 WARN_ON(encoder->connectors_active != false);
0a91ca29 3933
b980514c 3934 intel_modeset_check_state(connector->dev);
79e53945
JB		 3935}
3936
f0947c37
DV		 3937/* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3941{
24929352 3942 enum pipe pipe = 0;
f0947c37 3943 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3944
f0947c37 3945 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3946}
3947
b8cecdf5
DV		 3948static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3949 struct intel_crtc_config *pipe_config)
79e53945 3950{
2c07245f 3951 struct drm_device *dev = crtc->dev;
b8cecdf5 3952 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3953
bad720ff 3954 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3955 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3956 if (pipe_config->requested_mode.clock * 3
3957 > IRONLAKE_FDI_FREQ * 4)
2377b741 3958 return false;
2c07245f 3959 }
89749350 3960
f9bef081
DV		 3961 /* All interlaced capable intel hw wants timings in frames. Note though
3962 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3963 * timings, so we need to be careful not to clobber these.*/
7ae89233 3964 if (!pipe_config->timings_set)
f9bef081 3965 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3966
44f46b42
CW		 3967 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3968 * with a hsync front porch of 0.
3969 */
3970 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3971 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3972 return false;
3973
5d2d38dd
DV		 3974 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3975 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3976 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3977 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3978 * for lvds. */
3979 pipe_config->pipe_bpp = 8*3;
3980 }
3981
79e53945
JB		 3982 return true;
3983}
3984
25eb05fc
JB		 3985static int valleyview_get_display_clock_speed(struct drm_device *dev)
3986{
3987 return 400000; /* FIXME */
3988}
3989
e70236a8
JB		 3990static int i945_get_display_clock_speed(struct drm_device *dev)
3991{
3992 return 400000;
3993}
79e53945 3994
e70236a8 3995static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3996{
e70236a8
JB		 3997 return 333000;
3998}
79e53945 3999
e70236a8
JB		 4000static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4001{
4002 return 200000;
4003}
79e53945 4004
e70236a8
JB		 4005static int i915gm_get_display_clock_speed(struct drm_device *dev)
4006{
4007 u16 gcfgc = 0;
79e53945 4008
e70236a8
JB		 4009 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4010
4011 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4012 return 133000;
4013 else {
4014 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4015 case GC_DISPLAY_CLOCK_333_MHZ:
4016 return 333000;
4017 default:
4018 case GC_DISPLAY_CLOCK_190_200_MHZ:
4019 return 190000;
79e53945 4020 }
e70236a8
JB		 4021 }
4022}
4023
4024static int i865_get_display_clock_speed(struct drm_device *dev)
4025{
4026 return 266000;
4027}
4028
4029static int i855_get_display_clock_speed(struct drm_device *dev)
4030{
4031 u16 hpllcc = 0;
4032 /* Assume that the hardware is in the high speed state. This
4033 * should be the default.
4034 */
4035 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4036 case GC_CLOCK_133_200:
4037 case GC_CLOCK_100_200:
4038 return 200000;
4039 case GC_CLOCK_166_250:
4040 return 250000;
4041 case GC_CLOCK_100_133:
79e53945 4042 return 133000;
e70236a8 4043 }
79e53945 4044
e70236a8
JB		 4045 /* Shouldn't happen */
4046 return 0;
4047}
79e53945 4048
e70236a8
JB		 4049static int i830_get_display_clock_speed(struct drm_device *dev)
4050{
4051 return 133000;
79e53945
JB		 4052}
4053
2c07245f 4054static void
e69d0bc1 4055intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4056{
4057 while (*num > 0xffffff || *den > 0xffffff) {
4058 *num >>= 1;
4059 *den >>= 1;
4060 }
4061}
4062
e69d0bc1
DV		 4063void
4064intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4065 int pixel_clock, int link_clock,
4066 struct intel_link_m_n *m_n)
2c07245f 4067{
e69d0bc1 4068 m_n->tu = 64;
22ed1113
CW		 4069 m_n->gmch_m = bits_per_pixel * pixel_clock;
4070 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4071 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4072 m_n->link_m = pixel_clock;
4073 m_n->link_n = link_clock;
e69d0bc1 4074 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4075}
4076
a7615030
CW		 4077static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4078{
72bbe58c
KP		 4079 if (i915_panel_use_ssc >= 0)
4080 return i915_panel_use_ssc != 0;
4081 return dev_priv->lvds_use_ssc
435793df 4082 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4083}
4084
a0c4da24
JB		 4085static int vlv_get_refclk(struct drm_crtc *crtc)
4086{
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 int refclk = 27000; /* for DP & HDMI */
4090
4091 return 100000; /* only one validated so far */
4092
4093 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4094 refclk = 96000;
4095 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4096 if (intel_panel_use_ssc(dev_priv))
4097 refclk = 100000;
4098 else
4099 refclk = 96000;
4100 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4101 refclk = 100000;
4102 }
4103
4104 return refclk;
4105}
4106
c65d77d8
JB		 4107static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4108{
4109 struct drm_device *dev = crtc->dev;
4110 struct drm_i915_private *dev_priv = dev->dev_private;
4111 int refclk;
4112
a0c4da24
JB		 4113 if (IS_VALLEYVIEW(dev)) {
4114 refclk = vlv_get_refclk(crtc);
4115 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4116 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4117 refclk = dev_priv->lvds_ssc_freq * 1000;
4118 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4119 refclk / 1000);
4120 } else if (!IS_GEN2(dev)) {
4121 refclk = 96000;
4122 } else {
4123 refclk = 48000;
4124 }
4125
4126 return refclk;
4127}
4128
4129static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4130 intel_clock_t *clock)
4131{
4132 /* SDVO TV has fixed PLL values depend on its clock range,
4133 this mirrors vbios setting. */
4134 if (adjusted_mode->clock >= 100000
4135 && adjusted_mode->clock < 140500) {
4136 clock->p1 = 2;
4137 clock->p2 = 10;
4138 clock->n = 3;
4139 clock->m1 = 16;
4140 clock->m2 = 8;
4141 } else if (adjusted_mode->clock >= 140500
4142 && adjusted_mode->clock <= 200000) {
4143 clock->p1 = 1;
4144 clock->p2 = 10;
4145 clock->n = 6;
4146 clock->m1 = 12;
4147 clock->m2 = 8;
4148 }
4149}
4150
a7516a05
JB		 4151static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4152 intel_clock_t *clock,
4153 intel_clock_t *reduced_clock)
4154{
4155 struct drm_device *dev = crtc->dev;
4156 struct drm_i915_private *dev_priv = dev->dev_private;
4157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4158 int pipe = intel_crtc->pipe;
4159 u32 fp, fp2 = 0;
4160
4161 if (IS_PINEVIEW(dev)) {
4162 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4163 if (reduced_clock)
4164 fp2 = (1 << reduced_clock->n) << 16 |
4165 reduced_clock->m1 << 8 | reduced_clock->m2;
4166 } else {
4167 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4168 if (reduced_clock)
4169 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4170 reduced_clock->m2;
4171 }
4172
4173 I915_WRITE(FP0(pipe), fp);
4174
4175 intel_crtc->lowfreq_avail = false;
4176 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4177 reduced_clock && i915_powersave) {
4178 I915_WRITE(FP1(pipe), fp2);
4179 intel_crtc->lowfreq_avail = true;
4180 } else {
4181 I915_WRITE(FP1(pipe), fp);
4182 }
4183}
4184
a0c4da24 4185static void vlv_update_pll(struct drm_crtc *crtc,
a0c4da24 4186 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4187 int num_connectors)
a0c4da24
JB		 4188{
4189 struct drm_device *dev = crtc->dev;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4192 struct drm_display_mode *adjusted_mode =
4193 &intel_crtc->config.adjusted_mode;
4194 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
a0c4da24
JB		 4195 int pipe = intel_crtc->pipe;
4196 u32 dpll, mdiv, pdiv;
4197 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4198 bool is_sdvo;
4199 u32 temp;
a0c4da24 4200
09153000
DV		 4201 mutex_lock(&dev_priv->dpio_lock);
4202
2a8f64ca
VP		 4203 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4204 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4205
2a8f64ca
VP		 4206 dpll = DPLL_VGA_MODE_DIS;
4207 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4208 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4209 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4210
4211 I915_WRITE(DPLL(pipe), dpll);
4212 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4213
4214 bestn = clock->n;
4215 bestm1 = clock->m1;
4216 bestm2 = clock->m2;
4217 bestp1 = clock->p1;
4218 bestp2 = clock->p2;
4219
2a8f64ca
VP		 4220 /*
4221 * In Valleyview PLL and program lane counter registers are exposed
4222 * through DPIO interface
4223 */
a0c4da24
JB		 4224 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4225 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4226 mdiv |= ((bestn << DPIO_N_SHIFT));
4227 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4228 mdiv |= (1 << DPIO_K_SHIFT);
4229 mdiv |= DPIO_ENABLE_CALIBRATION;
4230 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4231
4232 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4233
2a8f64ca 4234 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4235 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4236 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4237 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4238 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4239
2a8f64ca 4240 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4241
4242 dpll |= DPLL_VCO_ENABLE;
4243 I915_WRITE(DPLL(pipe), dpll);
4244 POSTING_READ(DPLL(pipe));
4245 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4246 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4247
2a8f64ca
VP		 4248 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4249
4250 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4251 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4252
4253 I915_WRITE(DPLL(pipe), dpll);
4254
4255 /* Wait for the clocks to stabilize. */
4256 POSTING_READ(DPLL(pipe));
4257 udelay(150);
a0c4da24 4258
2a8f64ca
VP		 4259 temp = 0;
4260 if (is_sdvo) {
6cc5f341
DV		 4261 temp = 0;
4262 if (intel_crtc->config.pixel_multiplier > 1) {
4263 temp = (intel_crtc->config.pixel_multiplier - 1)
4264 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4265 }
a0c4da24 4266 }
2a8f64ca
VP		 4267 I915_WRITE(DPLL_MD(pipe), temp);
4268 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4269
2a8f64ca
VP		 4270 /* Now program lane control registers */
4271 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4272 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4273 {
4274 temp = 0x1000C4;
4275 if(pipe == 1)
4276 temp |= (1 << 21);
4277 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4278 }
4279 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4280 {
4281 temp = 0x1000C4;
4282 if(pipe == 1)
4283 temp |= (1 << 21);
4284 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4285 }
09153000
DV		 4286
4287 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4288}
4289
eb1cbe48 4290static void i9xx_update_pll(struct drm_crtc *crtc,
eb1cbe48
DV		 4291 intel_clock_t *clock, intel_clock_t *reduced_clock,
4292 int num_connectors)
4293{
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4297 struct drm_display_mode *adjusted_mode =
4298 &intel_crtc->config.adjusted_mode;
4299 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
dafd226c 4300 struct intel_encoder *encoder;
eb1cbe48
DV		 4301 int pipe = intel_crtc->pipe;
4302 u32 dpll;
4303 bool is_sdvo;
4304
2a8f64ca
VP		 4305 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4306
eb1cbe48
DV		 4307 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4308 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4309
4310 dpll = DPLL_VGA_MODE_DIS;
4311
4312 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4313 dpll |= DPLLB_MODE_LVDS;
4314 else
4315 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4316
eb1cbe48 4317 if (is_sdvo) {
6cc5f341
DV		 4318 if ((intel_crtc->config.pixel_multiplier > 1) &&
4319 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4320 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4321 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4322 }
4323 dpll |= DPLL_DVO_HIGH_SPEED;
4324 }
4325 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4326 dpll |= DPLL_DVO_HIGH_SPEED;
4327
4328 /* compute bitmask from p1 value */
4329 if (IS_PINEVIEW(dev))
4330 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4331 else {
4332 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4333 if (IS_G4X(dev) && reduced_clock)
4334 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4335 }
4336 switch (clock->p2) {
4337 case 5:
4338 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4339 break;
4340 case 7:
4341 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4342 break;
4343 case 10:
4344 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4345 break;
4346 case 14:
4347 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4348 break;
4349 }
4350 if (INTEL_INFO(dev)->gen >= 4)
4351 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4352
4353 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4354 dpll |= PLL_REF_INPUT_TVCLKINBC;
4355 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4356 /* XXX: just matching BIOS for now */
4357 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4358 dpll |= 3;
4359 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4360 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4361 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4362 else
4363 dpll |= PLL_REF_INPUT_DREFCLK;
4364
4365 dpll |= DPLL_VCO_ENABLE;
4366 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4367 POSTING_READ(DPLL(pipe));
4368 udelay(150);
4369
dafd226c
DV		 4370 for_each_encoder_on_crtc(dev, crtc, encoder)
4371 if (encoder->pre_pll_enable)
4372 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4373
4374 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4375 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4376
4377 I915_WRITE(DPLL(pipe), dpll);
4378
4379 /* Wait for the clocks to stabilize. */
4380 POSTING_READ(DPLL(pipe));
4381 udelay(150);
4382
4383 if (INTEL_INFO(dev)->gen >= 4) {
4384 u32 temp = 0;
4385 if (is_sdvo) {
6cc5f341
DV		 4386 temp = 0;
4387 if (intel_crtc->config.pixel_multiplier > 1) {
4388 temp = (intel_crtc->config.pixel_multiplier - 1)
4389 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4390 }
eb1cbe48
DV		 4391 }
4392 I915_WRITE(DPLL_MD(pipe), temp);
4393 } else {
4394 /* The pixel multiplier can only be updated once the
4395 * DPLL is enabled and the clocks are stable.
4396 *
4397 * So write it again.
4398 */
4399 I915_WRITE(DPLL(pipe), dpll);
4400 }
4401}
4402
4403static void i8xx_update_pll(struct drm_crtc *crtc,
4404 struct drm_display_mode *adjusted_mode,
2a8f64ca 4405 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4406 int num_connectors)
4407{
4408 struct drm_device *dev = crtc->dev;
4409 struct drm_i915_private *dev_priv = dev->dev_private;
4410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4411 struct intel_encoder *encoder;
eb1cbe48
DV		 4412 int pipe = intel_crtc->pipe;
4413 u32 dpll;
4414
2a8f64ca
VP		 4415 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4416
eb1cbe48
DV		 4417 dpll = DPLL_VGA_MODE_DIS;
4418
4419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4420 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4421 } else {
4422 if (clock->p1 == 2)
4423 dpll |= PLL_P1_DIVIDE_BY_TWO;
4424 else
4425 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4426 if (clock->p2 == 4)
4427 dpll |= PLL_P2_DIVIDE_BY_4;
4428 }
4429
83f377ab 4430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4431 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4432 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4433 else
4434 dpll |= PLL_REF_INPUT_DREFCLK;
4435
4436 dpll |= DPLL_VCO_ENABLE;
4437 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4438 POSTING_READ(DPLL(pipe));
4439 udelay(150);
4440
dafd226c
DV		 4441 for_each_encoder_on_crtc(dev, crtc, encoder)
4442 if (encoder->pre_pll_enable)
4443 encoder->pre_pll_enable(encoder);
eb1cbe48 4444
5b5896e4
DV		 4445 I915_WRITE(DPLL(pipe), dpll);
4446
4447 /* Wait for the clocks to stabilize. */
4448 POSTING_READ(DPLL(pipe));
4449 udelay(150);
4450
eb1cbe48
DV		 4451 /* The pixel multiplier can only be updated once the
4452 * DPLL is enabled and the clocks are stable.
4453 *
4454 * So write it again.
4455 */
4456 I915_WRITE(DPLL(pipe), dpll);
4457}
4458
b0e77b9c
PZ		 4459static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4460 struct drm_display_mode *mode,
4461 struct drm_display_mode *adjusted_mode)
4462{
4463 struct drm_device *dev = intel_crtc->base.dev;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
4465 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4466 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4467 uint32_t vsyncshift;
4468
4469 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4470 /* the chip adds 2 halflines automatically */
4471 adjusted_mode->crtc_vtotal -= 1;
4472 adjusted_mode->crtc_vblank_end -= 1;
4473 vsyncshift = adjusted_mode->crtc_hsync_start
4474 - adjusted_mode->crtc_htotal / 2;
4475 } else {
4476 vsyncshift = 0;
4477 }
4478
4479 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4480 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4481
fe2b8f9d 4482 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4483 (adjusted_mode->crtc_hdisplay - 1) |
4484 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4485 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4486 (adjusted_mode->crtc_hblank_start - 1) |
4487 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4488 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4489 (adjusted_mode->crtc_hsync_start - 1) |
4490 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4491
fe2b8f9d 4492 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4493 (adjusted_mode->crtc_vdisplay - 1) |
4494 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4495 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4496 (adjusted_mode->crtc_vblank_start - 1) |
4497 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4498 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4499 (adjusted_mode->crtc_vsync_start - 1) |
4500 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4501
b5e508d4
PZ		 4502 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4503 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4504 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4505 * bits. */
4506 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4507 (pipe == PIPE_B || pipe == PIPE_C))
4508 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4509
b0e77b9c
PZ		 4510 /* pipesrc controls the size that is scaled from, which should
4511 * always be the user's requested size.
4512 */
4513 I915_WRITE(PIPESRC(pipe),
4514 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4515}
4516
f564048e 4517static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4518 int x, int y,
94352cf9 4519 struct drm_framebuffer *fb)
79e53945
JB		 4520{
4521 struct drm_device *dev = crtc->dev;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4524 struct drm_display_mode *adjusted_mode =
4525 &intel_crtc->config.adjusted_mode;
4526 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4527 int pipe = intel_crtc->pipe;
80824003 4528 int plane = intel_crtc->plane;
c751ce4f 4529 int refclk, num_connectors = 0;
652c393a 4530 intel_clock_t clock, reduced_clock;
b0e77b9c 4531 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4532 bool ok, has_reduced_clock = false, is_sdvo = false;
4533 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4534 struct intel_encoder *encoder;
d4906093 4535 const intel_limit_t *limit;
5c3b82e2 4536 int ret;
79e53945 4537
6c2b7c12 4538 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4539 switch (encoder->type) {
79e53945
JB		 4540 case INTEL_OUTPUT_LVDS:
4541 is_lvds = true;
4542 break;
4543 case INTEL_OUTPUT_SDVO:
7d57382e 4544 case INTEL_OUTPUT_HDMI:
79e53945 4545 is_sdvo = true;
5eddb70b 4546 if (encoder->needs_tv_clock)
e2f0ba97 4547 is_tv = true;
79e53945 4548 break;
79e53945
JB		 4549 case INTEL_OUTPUT_TVOUT:
4550 is_tv = true;
4551 break;
a4fc5ed6
KP		 4552 case INTEL_OUTPUT_DISPLAYPORT:
4553 is_dp = true;
4554 break;
79e53945 4555 }
43565a06 4556
c751ce4f 4557 num_connectors++;
79e53945
JB		 4558 }
4559
c65d77d8 4560 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4561
d4906093
ML		 4562 /*
4563 * Returns a set of divisors for the desired target clock with the given
4564 * refclk, or FALSE. The returned values represent the clock equation:
4565 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4566 */
1b894b59 4567 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4568 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4569 &clock);
79e53945
JB		 4570 if (!ok) {
4571 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4572 return -EINVAL;
79e53945
JB		 4573 }
4574
cda4b7d3 4575 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4576 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4577
ddc9003c 4578 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4579 /*
4580 * Ensure we match the reduced clock's P to the target clock.
4581 * If the clocks don't match, we can't switch the display clock
4582 * by using the FP0/FP1. In such case we will disable the LVDS
4583 * downclock feature.
4584 */
ddc9003c 4585 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4586 dev_priv->lvds_downclock,
4587 refclk,
cec2f356 4588 &clock,
5eddb70b 4589 &reduced_clock);
7026d4ac
ZW		 4590 }
4591
c65d77d8
JB		 4592 if (is_sdvo && is_tv)
4593 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4594
eb1cbe48 4595 if (IS_GEN2(dev))
2a8f64ca
VP		 4596 i8xx_update_pll(crtc, adjusted_mode, &clock,
4597 has_reduced_clock ? &reduced_clock : NULL,
4598 num_connectors);
a0c4da24 4599 else if (IS_VALLEYVIEW(dev))
6cc5f341 4600 vlv_update_pll(crtc, &clock,
2a8f64ca
VP		 4601 has_reduced_clock ? &reduced_clock : NULL,
4602 num_connectors);
79e53945 4603 else
6cc5f341 4604 i9xx_update_pll(crtc, &clock,
eb1cbe48
DV		 4605 has_reduced_clock ? &reduced_clock : NULL,
4606 num_connectors);
79e53945
JB		 4607
4608 /* setup pipeconf */
5eddb70b 4609 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4610
4611 /* Set up the display plane register */
4612 dspcntr = DISPPLANE_GAMMA_ENABLE;
4613
da6ecc5d
JB		 4614 if (!IS_VALLEYVIEW(dev)) {
4615 if (pipe == 0)
4616 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4617 else
4618 dspcntr |= DISPPLANE_SEL_PIPE_B;
4619 }
79e53945 4620
a6c45cf0 4621 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4622 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4623 * core speed.
4624 *
4625 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4626 * pipe == 0 check?
4627 */
e70236a8
JB		 4628 if (mode->clock >
4629 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4630 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4631 else
5eddb70b 4632 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4633 }
4634
3b5c78a3 4635 /* default to 8bpc */
dfd07d72 4636 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4637 if (is_dp) {
965e0c48 4638 if (intel_crtc->config.dither) {
dfd07d72 4639 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4640 PIPECONF_DITHER_EN |
4641 PIPECONF_DITHER_TYPE_SP;
4642 }
4643 }
4644
19c03924 4645 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
965e0c48 4646 if (intel_crtc->config.dither) {
dfd07d72 4647 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4648 PIPECONF_ENABLE |
4649 I965_PIPECONF_ACTIVE;
4650 }
4651 }
4652
28c97730 4653 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4654 drm_mode_debug_printmodeline(mode);
4655
a7516a05
JB		 4656 if (HAS_PIPE_CXSR(dev)) {
4657 if (intel_crtc->lowfreq_avail) {
28c97730 4658 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4659 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4660 } else {
28c97730 4661 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4662 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4663 }
4664 }
4665
617cf884 4666 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4667 if (!IS_GEN2(dev) &&
b0e77b9c 4668 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4669 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4670 else
617cf884 4671 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4672
b0e77b9c 4673 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4674
4675 /* pipesrc and dspsize control the size that is scaled from,
4676 * which should always be the user's requested size.
79e53945 4677 */
929c77fb
EA		 4678 I915_WRITE(DSPSIZE(plane),
4679 ((mode->vdisplay - 1) << 16) |
4680 (mode->hdisplay - 1));
4681 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4682
f564048e
EA		 4683 I915_WRITE(PIPECONF(pipe), pipeconf);
4684 POSTING_READ(PIPECONF(pipe));
929c77fb 4685 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4686
4687 intel_wait_for_vblank(dev, pipe);
4688
f564048e
EA		 4689 I915_WRITE(DSPCNTR(plane), dspcntr);
4690 POSTING_READ(DSPCNTR(plane));
4691
94352cf9 4692 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4693
4694 intel_update_watermarks(dev);
4695
f564048e
EA		 4696 return ret;
4697}
4698
dde86e2d 4699static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4700{
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4703 struct intel_encoder *encoder;
74cfd7ac 4704 u32 val, final;
13d83a67 4705 bool has_lvds = false;
199e5d79
KP		 4706 bool has_cpu_edp = false;
4707 bool has_pch_edp = false;
4708 bool has_panel = false;
99eb6a01
KP		 4709 bool has_ck505 = false;
4710 bool can_ssc = false;
13d83a67
JB		 4711
4712 /* We need to take the global config into account */
199e5d79
KP		 4713 list_for_each_entry(encoder, &mode_config->encoder_list,
4714 base.head) {
4715 switch (encoder->type) {
4716 case INTEL_OUTPUT_LVDS:
4717 has_panel = true;
4718 has_lvds = true;
4719 break;
4720 case INTEL_OUTPUT_EDP:
4721 has_panel = true;
4722 if (intel_encoder_is_pch_edp(&encoder->base))
4723 has_pch_edp = true;
4724 else
4725 has_cpu_edp = true;
4726 break;
13d83a67
JB		 4727 }
4728 }
4729
99eb6a01
KP		 4730 if (HAS_PCH_IBX(dev)) {
4731 has_ck505 = dev_priv->display_clock_mode;
4732 can_ssc = has_ck505;
4733 } else {
4734 has_ck505 = false;
4735 can_ssc = true;
4736 }
4737
4738 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4739 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4740 has_ck505);
13d83a67
JB		 4741
4742 /* Ironlake: try to setup display ref clock before DPLL
4743 * enabling. This is only under driver's control after
4744 * PCH B stepping, previous chipset stepping should be
4745 * ignoring this setting.
4746 */
74cfd7ac
CW		 4747 val = I915_READ(PCH_DREF_CONTROL);
4748
4749 /* As we must carefully and slowly disable/enable each source in turn,
4750 * compute the final state we want first and check if we need to
4751 * make any changes at all.
4752 */
4753 final = val;
4754 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4755 if (has_ck505)
4756 final |= DREF_NONSPREAD_CK505_ENABLE;
4757 else
4758 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4759
4760 final &= ~DREF_SSC_SOURCE_MASK;
4761 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4762 final &= ~DREF_SSC1_ENABLE;
4763
4764 if (has_panel) {
4765 final |= DREF_SSC_SOURCE_ENABLE;
4766
4767 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4768 final |= DREF_SSC1_ENABLE;
4769
4770 if (has_cpu_edp) {
4771 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4772 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4773 else
4774 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4775 } else
4776 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4777 } else {
4778 final |= DREF_SSC_SOURCE_DISABLE;
4779 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4780 }
4781
4782 if (final == val)
4783 return;
4784
13d83a67 4785 /* Always enable nonspread source */
74cfd7ac 4786 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4787
99eb6a01 4788 if (has_ck505)
74cfd7ac 4789 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4790 else
74cfd7ac 4791 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4792
199e5d79 4793 if (has_panel) {
74cfd7ac
CW		 4794 val &= ~DREF_SSC_SOURCE_MASK;
4795 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4796
199e5d79 4797 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4798 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4799 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4800 val |= DREF_SSC1_ENABLE;
e77166b5 4801 } else
74cfd7ac 4802 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4803
4804 /* Get SSC going before enabling the outputs */
74cfd7ac 4805 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4806 POSTING_READ(PCH_DREF_CONTROL);
4807 udelay(200);
4808
74cfd7ac 4809 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4810
4811 /* Enable CPU source on CPU attached eDP */
199e5d79 4812 if (has_cpu_edp) {
99eb6a01 4813 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4814 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4815 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4816 }
13d83a67 4817 else
74cfd7ac 4818 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4819 } else
74cfd7ac 4820 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4821
74cfd7ac 4822 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4823 POSTING_READ(PCH_DREF_CONTROL);
4824 udelay(200);
4825 } else {
4826 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4827
74cfd7ac 4828 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4829
4830 /* Turn off CPU output */
74cfd7ac 4831 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4832
74cfd7ac 4833 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4834 POSTING_READ(PCH_DREF_CONTROL);
4835 udelay(200);
4836
4837 /* Turn off the SSC source */
74cfd7ac
CW		 4838 val &= ~DREF_SSC_SOURCE_MASK;
4839 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4840
4841 /* Turn off SSC1 */
74cfd7ac 4842 val &= ~DREF_SSC1_ENABLE;
199e5d79 4843
74cfd7ac 4844 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4845 POSTING_READ(PCH_DREF_CONTROL);
4846 udelay(200);
4847 }
74cfd7ac
CW		 4848
4849 BUG_ON(val != final);
13d83a67
JB		 4850}
4851
dde86e2d
PZ		 4852/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4853static void lpt_init_pch_refclk(struct drm_device *dev)
4854{
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856 struct drm_mode_config *mode_config = &dev->mode_config;
4857 struct intel_encoder *encoder;
4858 bool has_vga = false;
4859 bool is_sdv = false;
4860 u32 tmp;
4861
4862 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4863 switch (encoder->type) {
4864 case INTEL_OUTPUT_ANALOG:
4865 has_vga = true;
4866 break;
4867 }
4868 }
4869
4870 if (!has_vga)
4871 return;
4872
c00db246
DV		 4873 mutex_lock(&dev_priv->dpio_lock);
4874
dde86e2d
PZ		 4875 /* XXX: Rip out SDV support once Haswell ships for real. */
4876 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4877 is_sdv = true;
4878
4879 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4880 tmp &= ~SBI_SSCCTL_DISABLE;
4881 tmp |= SBI_SSCCTL_PATHALT;
4882 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4883
4884 udelay(24);
4885
4886 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4887 tmp &= ~SBI_SSCCTL_PATHALT;
4888 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4889
4890 if (!is_sdv) {
4891 tmp = I915_READ(SOUTH_CHICKEN2);
4892 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4893 I915_WRITE(SOUTH_CHICKEN2, tmp);
4894
4895 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4896 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4897 DRM_ERROR("FDI mPHY reset assert timeout\n");
4898
4899 tmp = I915_READ(SOUTH_CHICKEN2);
4900 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4901 I915_WRITE(SOUTH_CHICKEN2, tmp);
4902
4903 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4904 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4905 100))
4906 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4907 }
4908
4909 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4910 tmp &= ~(0xFF << 24);
4911 tmp |= (0x12 << 24);
4912 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4913
4914 if (!is_sdv) {
4915 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4916 tmp &= ~(0x3 << 6);
4917 tmp |= (1 << 6) | (1 << 0);
4918 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4919 }
4920
4921 if (is_sdv) {
4922 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4923 tmp |= 0x7FFF;
4924 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4925 }
4926
4927 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4928 tmp |= (1 << 11);
4929 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4930
4931 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4932 tmp |= (1 << 11);
4933 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4934
4935 if (is_sdv) {
4936 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4937 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4938 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4939
4940 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4941 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4942 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4943
4944 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4945 tmp |= (0x3F << 8);
4946 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4947
4948 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4949 tmp |= (0x3F << 8);
4950 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4951 }
4952
4953 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4954 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4955 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4956
4957 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4958 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4959 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4960
4961 if (!is_sdv) {
4962 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4963 tmp &= ~(7 << 13);
4964 tmp |= (5 << 13);
4965 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4966
4967 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4968 tmp &= ~(7 << 13);
4969 tmp |= (5 << 13);
4970 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4971 }
4972
4973 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4974 tmp &= ~0xFF;
4975 tmp |= 0x1C;
4976 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4977
4978 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4979 tmp &= ~0xFF;
4980 tmp |= 0x1C;
4981 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4982
4983 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4984 tmp &= ~(0xFF << 16);
4985 tmp |= (0x1C << 16);
4986 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4987
4988 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4989 tmp &= ~(0xFF << 16);
4990 tmp |= (0x1C << 16);
4991 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4992
4993 if (!is_sdv) {
4994 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4995 tmp |= (1 << 27);
4996 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4997
4998 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
4999 tmp |= (1 << 27);
5000 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5001
5002 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5003 tmp &= ~(0xF << 28);
5004 tmp |= (4 << 28);
5005 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5006
5007 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5008 tmp &= ~(0xF << 28);
5009 tmp |= (4 << 28);
5010 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5011 }
5012
5013 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5014 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5015 tmp |= SBI_DBUFF0_ENABLE;
5016 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5017
5018 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5019}
5020
5021/*
5022 * Initialize reference clocks when the driver loads
5023 */
5024void intel_init_pch_refclk(struct drm_device *dev)
5025{
5026 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5027 ironlake_init_pch_refclk(dev);
5028 else if (HAS_PCH_LPT(dev))
5029 lpt_init_pch_refclk(dev);
5030}
5031
d9d444cb
JB		 5032static int ironlake_get_refclk(struct drm_crtc *crtc)
5033{
5034 struct drm_device *dev = crtc->dev;
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 struct intel_encoder *encoder;
d9d444cb
JB		 5037 struct intel_encoder *edp_encoder = NULL;
5038 int num_connectors = 0;
5039 bool is_lvds = false;
5040
6c2b7c12 5041 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5042 switch (encoder->type) {
5043 case INTEL_OUTPUT_LVDS:
5044 is_lvds = true;
5045 break;
5046 case INTEL_OUTPUT_EDP:
5047 edp_encoder = encoder;
5048 break;
5049 }
5050 num_connectors++;
5051 }
5052
5053 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5054 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5055 dev_priv->lvds_ssc_freq);
5056 return dev_priv->lvds_ssc_freq * 1000;
5057 }
5058
5059 return 120000;
5060}
5061
c8203565 5062static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5063 struct drm_display_mode *adjusted_mode,
c8203565 5064 bool dither)
79e53945 5065{
c8203565 5066 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068 int pipe = intel_crtc->pipe;
c8203565
PZ		 5069 uint32_t val;
5070
5071 val = I915_READ(PIPECONF(pipe));
5072
dfd07d72 5073 val &= ~PIPECONF_BPC_MASK;
965e0c48 5074 switch (intel_crtc->config.pipe_bpp) {
c8203565 5075 case 18:
dfd07d72 5076 val |= PIPECONF_6BPC;
c8203565
PZ		 5077 break;
5078 case 24:
dfd07d72 5079 val |= PIPECONF_8BPC;
c8203565
PZ		 5080 break;
5081 case 30:
dfd07d72 5082 val |= PIPECONF_10BPC;
c8203565
PZ		 5083 break;
5084 case 36:
dfd07d72 5085 val |= PIPECONF_12BPC;
c8203565
PZ		 5086 break;
5087 default:
cc769b62
PZ		 5088 /* Case prevented by intel_choose_pipe_bpp_dither. */
5089 BUG();
c8203565
PZ		 5090 }
5091
5092 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5093 if (dither)
5094 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5095
5096 val &= ~PIPECONF_INTERLACE_MASK;
5097 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5098 val |= PIPECONF_INTERLACED_ILK;
5099 else
5100 val |= PIPECONF_PROGRESSIVE;
5101
50f3b016 5102 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5103 val |= PIPECONF_COLOR_RANGE_SELECT;
5104 else
5105 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5106
c8203565
PZ		 5107 I915_WRITE(PIPECONF(pipe), val);
5108 POSTING_READ(PIPECONF(pipe));
5109}
5110
86d3efce
VS		 5111/*
5112 * Set up the pipe CSC unit.
5113 *
5114 * Currently only full range RGB to limited range RGB conversion
5115 * is supported, but eventually this should handle various
5116 * RGB<->YCbCr scenarios as well.
5117 */
50f3b016 5118static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5119{
5120 struct drm_device *dev = crtc->dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5123 int pipe = intel_crtc->pipe;
5124 uint16_t coeff = 0x7800; /* 1.0 */
5125
5126 /*
5127 * TODO: Check what kind of values actually come out of the pipe
5128 * with these coeff/postoff values and adjust to get the best
5129 * accuracy. Perhaps we even need to take the bpc value into
5130 * consideration.
5131 */
5132
50f3b016 5133 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5134 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5135
5136 /*
5137 * GY/GU and RY/RU should be the other way around according
5138 * to BSpec, but reality doesn't agree. Just set them up in
5139 * a way that results in the correct picture.
5140 */
5141 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5142 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5143
5144 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5145 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5146
5147 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5148 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5149
5150 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5151 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5152 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5153
5154 if (INTEL_INFO(dev)->gen > 6) {
5155 uint16_t postoff = 0;
5156
50f3b016 5157 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5158 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5159
5160 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5161 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5162 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5163
5164 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5165 } else {
5166 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5167
50f3b016 5168 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5169 mode |= CSC_BLACK_SCREEN_OFFSET;
5170
5171 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5172 }
5173}
5174
ee2b0b38
PZ		 5175static void haswell_set_pipeconf(struct drm_crtc *crtc,
5176 struct drm_display_mode *adjusted_mode,
5177 bool dither)
5178{
5179 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5181 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5182 uint32_t val;
5183
702e7a56 5184 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5185
5186 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5187 if (dither)
5188 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5189
5190 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5191 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5192 val |= PIPECONF_INTERLACED_ILK;
5193 else
5194 val |= PIPECONF_PROGRESSIVE;
5195
702e7a56
PZ		 5196 I915_WRITE(PIPECONF(cpu_transcoder), val);
5197 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5198}
5199
6591c6e4
PZ		 5200static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5201 struct drm_display_mode *adjusted_mode,
5202 intel_clock_t *clock,
5203 bool *has_reduced_clock,
5204 intel_clock_t *reduced_clock)
5205{
5206 struct drm_device *dev = crtc->dev;
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208 struct intel_encoder *intel_encoder;
5209 int refclk;
d4906093 5210 const intel_limit_t *limit;
6591c6e4 5211 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5212
6591c6e4
PZ		 5213 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5214 switch (intel_encoder->type) {
79e53945
JB		 5215 case INTEL_OUTPUT_LVDS:
5216 is_lvds = true;
5217 break;
5218 case INTEL_OUTPUT_SDVO:
7d57382e 5219 case INTEL_OUTPUT_HDMI:
79e53945 5220 is_sdvo = true;
6591c6e4 5221 if (intel_encoder->needs_tv_clock)
e2f0ba97 5222 is_tv = true;
79e53945 5223 break;
79e53945
JB		 5224 case INTEL_OUTPUT_TVOUT:
5225 is_tv = true;
5226 break;
79e53945
JB		 5227 }
5228 }
5229
d9d444cb 5230 refclk = ironlake_get_refclk(crtc);
79e53945 5231
d4906093
ML		 5232 /*
5233 * Returns a set of divisors for the desired target clock with the given
5234 * refclk, or FALSE. The returned values represent the clock equation:
5235 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5236 */
1b894b59 5237 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5238 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5239 clock);
5240 if (!ret)
5241 return false;
cda4b7d3 5242
ddc9003c 5243 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5244 /*
5245 * Ensure we match the reduced clock's P to the target clock.
5246 * If the clocks don't match, we can't switch the display clock
5247 * by using the FP0/FP1. In such case we will disable the LVDS
5248 * downclock feature.
5249 */
6591c6e4
PZ		 5250 *has_reduced_clock = limit->find_pll(limit, crtc,
5251 dev_priv->lvds_downclock,
5252 refclk,
5253 clock,
5254 reduced_clock);
652c393a 5255 }
61e9653f
DV		 5256
5257 if (is_sdvo && is_tv)
6591c6e4
PZ		 5258 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5259
5260 return true;
5261}
5262
01a415fd
DV		 5263static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5264{
5265 struct drm_i915_private *dev_priv = dev->dev_private;
5266 uint32_t temp;
5267
5268 temp = I915_READ(SOUTH_CHICKEN1);
5269 if (temp & FDI_BC_BIFURCATION_SELECT)
5270 return;
5271
5272 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5273 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5274
5275 temp |= FDI_BC_BIFURCATION_SELECT;
5276 DRM_DEBUG_KMS("enabling fdi C rx\n");
5277 I915_WRITE(SOUTH_CHICKEN1, temp);
5278 POSTING_READ(SOUTH_CHICKEN1);
5279}
5280
5281static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5282{
5283 struct drm_device *dev = intel_crtc->base.dev;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 struct intel_crtc *pipe_B_crtc =
5286 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5287
5288 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5289 intel_crtc->pipe, intel_crtc->fdi_lanes);
5290 if (intel_crtc->fdi_lanes > 4) {
5291 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5292 intel_crtc->pipe, intel_crtc->fdi_lanes);
5293 /* Clamp lanes to avoid programming the hw with bogus values. */
5294 intel_crtc->fdi_lanes = 4;
5295
5296 return false;
5297 }
5298
7eb552ae 5299 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5300 return true;
5301
5302 switch (intel_crtc->pipe) {
5303 case PIPE_A:
5304 return true;
5305 case PIPE_B:
5306 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5307 intel_crtc->fdi_lanes > 2) {
5308 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5309 intel_crtc->pipe, intel_crtc->fdi_lanes);
5310 /* Clamp lanes to avoid programming the hw with bogus values. */
5311 intel_crtc->fdi_lanes = 2;
5312
5313 return false;
5314 }
5315
5316 if (intel_crtc->fdi_lanes > 2)
5317 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5318 else
5319 cpt_enable_fdi_bc_bifurcation(dev);
5320
5321 return true;
5322 case PIPE_C:
5323 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5324 if (intel_crtc->fdi_lanes > 2) {
5325 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5326 intel_crtc->pipe, intel_crtc->fdi_lanes);
5327 /* Clamp lanes to avoid programming the hw with bogus values. */
5328 intel_crtc->fdi_lanes = 2;
5329
5330 return false;
5331 }
5332 } else {
5333 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5334 return false;
5335 }
5336
5337 cpt_enable_fdi_bc_bifurcation(dev);
5338
5339 return true;
5340 default:
5341 BUG();
5342 }
5343}
5344
d4b1931c
PZ		 5345int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5346{
5347 /*
5348 * Account for spread spectrum to avoid
5349 * oversubscribing the link. Max center spread
5350 * is 2.5%; use 5% for safety's sake.
5351 */
5352 u32 bps = target_clock * bpp * 21 / 20;
5353 return bps / (link_bw * 8) + 1;
5354}
5355
6cc5f341 5356static void ironlake_set_m_n(struct drm_crtc *crtc)
79e53945
JB		 5357{
5358 struct drm_device *dev = crtc->dev;
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5361 struct drm_display_mode *adjusted_mode =
5362 &intel_crtc->config.adjusted_mode;
5363 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
afe2fcf5 5364 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5365 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5366 struct intel_link_m_n m_n = {0};
6cc5f341 5367 int target_clock, lane, link_bw;
f48d8f23 5368 bool is_dp = false, is_cpu_edp = false;
79e53945 5369
f48d8f23
PZ		 5370 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5371 switch (intel_encoder->type) {
a4fc5ed6
KP		 5372 case INTEL_OUTPUT_DISPLAYPORT:
5373 is_dp = true;
5374 break;
32f9d658 5375 case INTEL_OUTPUT_EDP:
e3aef172 5376 is_dp = true;
f48d8f23 5377 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5378 is_cpu_edp = true;
f48d8f23 5379 edp_encoder = intel_encoder;
32f9d658 5380 break;
79e53945 5381 }
79e53945 5382 }
61e9653f 5383
2c07245f 5384 /* FDI link */
8febb297
EA		 5385 lane = 0;
5386 /* CPU eDP doesn't require FDI link, so just set DP M/N
5387 according to current link config */
e3aef172 5388 if (is_cpu_edp) {
e3aef172 5389 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5390 } else {
8febb297
EA		 5391 /* FDI is a binary signal running at ~2.7GHz, encoding
5392 * each output octet as 10 bits. The actual frequency
5393 * is stored as a divider into a 100MHz clock, and the
5394 * mode pixel clock is stored in units of 1KHz.
5395 * Hence the bw of each lane in terms of the mode signal
5396 * is:
5397 */
5398 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5399 }
58a27471 5400
94bf2ced
DV		 5401 /* [e]DP over FDI requires target mode clock instead of link clock. */
5402 if (edp_encoder)
5403 target_clock = intel_edp_target_clock(edp_encoder, mode);
5404 else if (is_dp)
5405 target_clock = mode->clock;
5406 else
5407 target_clock = adjusted_mode->clock;
5408
d4b1931c
PZ		 5409 if (!lane)
5410 lane = ironlake_get_lanes_required(target_clock, link_bw,
965e0c48 5411 intel_crtc->config.pipe_bpp);
2c07245f 5412
8febb297
EA		 5413 intel_crtc->fdi_lanes = lane;
5414
6cc5f341
DV		 5415 if (intel_crtc->config.pixel_multiplier > 1)
5416 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5417 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5418 link_bw, &m_n);
8febb297 5419
afe2fcf5
PZ		 5420 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5421 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5422 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5423 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5424}
5425
de13a2e3 5426static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
de13a2e3 5427 intel_clock_t *clock, u32 fp)
79e53945 5428{
de13a2e3 5429 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5430 struct drm_device *dev = crtc->dev;
5431 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5432 struct intel_encoder *intel_encoder;
5433 uint32_t dpll;
6cc5f341 5434 int factor, num_connectors = 0;
de13a2e3
PZ		 5435 bool is_lvds = false, is_sdvo = false, is_tv = false;
5436 bool is_dp = false, is_cpu_edp = false;
79e53945 5437
de13a2e3
PZ		 5438 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5439 switch (intel_encoder->type) {
79e53945
JB		 5440 case INTEL_OUTPUT_LVDS:
5441 is_lvds = true;
5442 break;
5443 case INTEL_OUTPUT_SDVO:
7d57382e 5444 case INTEL_OUTPUT_HDMI:
79e53945 5445 is_sdvo = true;
de13a2e3 5446 if (intel_encoder->needs_tv_clock)
e2f0ba97 5447 is_tv = true;
79e53945 5448 break;
79e53945
JB		 5449 case INTEL_OUTPUT_TVOUT:
5450 is_tv = true;
5451 break;
a4fc5ed6
KP		 5452 case INTEL_OUTPUT_DISPLAYPORT:
5453 is_dp = true;
5454 break;
32f9d658 5455 case INTEL_OUTPUT_EDP:
e3aef172 5456 is_dp = true;
de13a2e3 5457 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5458 is_cpu_edp = true;
32f9d658 5459 break;
79e53945 5460 }
43565a06 5461
c751ce4f 5462 num_connectors++;
79e53945 5463 }
79e53945 5464
c1858123 5465 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5466 factor = 21;
5467 if (is_lvds) {
5468 if ((intel_panel_use_ssc(dev_priv) &&
5469 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5470 intel_is_dual_link_lvds(dev))
8febb297
EA		 5471 factor = 25;
5472 } else if (is_sdvo && is_tv)
5473 factor = 20;
c1858123 5474
de13a2e3 5475 if (clock->m < factor * clock->n)
8febb297 5476 fp |= FP_CB_TUNE;
2c07245f 5477
5eddb70b 5478 dpll = 0;
2c07245f 5479
a07d6787
EA		 5480 if (is_lvds)
5481 dpll |= DPLLB_MODE_LVDS;
5482 else
5483 dpll |= DPLLB_MODE_DAC_SERIAL;
5484 if (is_sdvo) {
6cc5f341
DV		 5485 if (intel_crtc->config.pixel_multiplier > 1) {
5486 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5487 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5488 }
a07d6787
EA		 5489 dpll |= DPLL_DVO_HIGH_SPEED;
5490 }
e3aef172 5491 if (is_dp && !is_cpu_edp)
a07d6787 5492 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5493
a07d6787 5494 /* compute bitmask from p1 value */
de13a2e3 5495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5496 /* also FPA1 */
de13a2e3 5497 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5498
de13a2e3 5499 switch (clock->p2) {
a07d6787
EA		 5500 case 5:
5501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5502 break;
5503 case 7:
5504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5505 break;
5506 case 10:
5507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5508 break;
5509 case 14:
5510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5511 break;
79e53945
JB		 5512 }
5513
43565a06
KH		 5514 if (is_sdvo && is_tv)
5515 dpll |= PLL_REF_INPUT_TVCLKINBC;
5516 else if (is_tv)
79e53945 5517 /* XXX: just matching BIOS for now */
43565a06 5518 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5519 dpll |= 3;
a7615030 5520 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5521 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5522 else
5523 dpll |= PLL_REF_INPUT_DREFCLK;
5524
de13a2e3
PZ		 5525 return dpll;
5526}
5527
5528static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5529 int x, int y,
5530 struct drm_framebuffer *fb)
5531{
5532 struct drm_device *dev = crtc->dev;
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5535 struct drm_display_mode *adjusted_mode =
5536 &intel_crtc->config.adjusted_mode;
5537 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5538 int pipe = intel_crtc->pipe;
5539 int plane = intel_crtc->plane;
5540 int num_connectors = 0;
5541 intel_clock_t clock, reduced_clock;
5542 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5543 bool ok, has_reduced_clock = false;
5544 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5545 struct intel_encoder *encoder;
de13a2e3 5546 int ret;
01a415fd 5547 bool dither, fdi_config_ok;
de13a2e3
PZ		 5548
5549 for_each_encoder_on_crtc(dev, crtc, encoder) {
5550 switch (encoder->type) {
5551 case INTEL_OUTPUT_LVDS:
5552 is_lvds = true;
5553 break;
de13a2e3
PZ		 5554 case INTEL_OUTPUT_DISPLAYPORT:
5555 is_dp = true;
5556 break;
5557 case INTEL_OUTPUT_EDP:
5558 is_dp = true;
e2f12b07 5559 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5560 is_cpu_edp = true;
5561 break;
5562 }
5563
5564 num_connectors++;
a07d6787 5565 }
79e53945 5566
5dc5298b
PZ		 5567 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5568 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5569
de13a2e3
PZ		 5570 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5571 &has_reduced_clock, &reduced_clock);
5572 if (!ok) {
5573 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5574 return -EINVAL;
79e53945
JB		 5575 }
5576
de13a2e3
PZ		 5577 /* Ensure that the cursor is valid for the new mode before changing... */
5578 intel_crtc_update_cursor(crtc, true);
5579
5580 /* determine panel color depth */
4e53c2e0 5581 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5582 if (is_lvds && dev_priv->lvds_dither)
5583 dither = true;
5584
5585 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5586 if (has_reduced_clock)
5587 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5588 reduced_clock.m2;
5589
6cc5f341 5590 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
79e53945 5591
f7cb34d4 5592 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5593 drm_mode_debug_printmodeline(mode);
5594
5dc5298b
PZ		 5595 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5596 if (!is_cpu_edp) {
ee7b9f93 5597 struct intel_pch_pll *pll;
4b645f14 5598
ee7b9f93
JB		 5599 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5600 if (pll == NULL) {
5601 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5602 pipe);
4b645f14
JB		 5603 return -EINVAL;
5604 }
ee7b9f93
JB		 5605 } else
5606 intel_put_pch_pll(intel_crtc);
79e53945 5607
2f0c2ad1 5608 if (is_dp && !is_cpu_edp)
a4fc5ed6 5609 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5610
dafd226c
DV		 5611 for_each_encoder_on_crtc(dev, crtc, encoder)
5612 if (encoder->pre_pll_enable)
5613 encoder->pre_pll_enable(encoder);
79e53945 5614
ee7b9f93
JB		 5615 if (intel_crtc->pch_pll) {
5616 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5617
32f9d658 5618 /* Wait for the clocks to stabilize. */
ee7b9f93 5619 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5620 udelay(150);
5621
8febb297
EA		 5622 /* The pixel multiplier can only be updated once the
5623 * DPLL is enabled and the clocks are stable.
5624 *
5625 * So write it again.
5626 */
ee7b9f93 5627 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5628 }
79e53945 5629
5eddb70b 5630 intel_crtc->lowfreq_avail = false;
ee7b9f93 5631 if (intel_crtc->pch_pll) {
4b645f14 5632 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5633 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5634 intel_crtc->lowfreq_avail = true;
4b645f14 5635 } else {
ee7b9f93 5636 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5637 }
5638 }
5639
b0e77b9c 5640 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5641
01a415fd
DV		 5642 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5643 * ironlake_check_fdi_lanes. */
6cc5f341 5644 ironlake_set_m_n(crtc);
2c07245f 5645
01a415fd 5646 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5647
c8203565 5648 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5649
9d0498a2 5650 intel_wait_for_vblank(dev, pipe);
79e53945 5651
a1f9e77e
PZ		 5652 /* Set up the display plane register */
5653 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5654 POSTING_READ(DSPCNTR(plane));
79e53945 5655
94352cf9 5656 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5657
5658 intel_update_watermarks(dev);
5659
1f8eeabf
ED		 5660 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5661
01a415fd 5662 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5663}
5664
d6dd9eb1
DV		 5665static void haswell_modeset_global_resources(struct drm_device *dev)
5666{
5667 struct drm_i915_private *dev_priv = dev->dev_private;
5668 bool enable = false;
5669 struct intel_crtc *crtc;
5670 struct intel_encoder *encoder;
5671
5672 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5673 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5674 enable = true;
5675 /* XXX: Should check for edp transcoder here, but thanks to init
5676 * sequence that's not yet available. Just in case desktop eDP
5677 * on PORT D is possible on haswell, too. */
5678 }
5679
5680 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5681 base.head) {
5682 if (encoder->type != INTEL_OUTPUT_EDP &&
5683 encoder->connectors_active)
5684 enable = true;
5685 }
5686
5687 /* Even the eDP panel fitter is outside the always-on well. */
5688 if (dev_priv->pch_pf_size)
5689 enable = true;
5690
5691 intel_set_power_well(dev, enable);
5692}
5693
09b4ddf9 5694static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5695 int x, int y,
5696 struct drm_framebuffer *fb)
5697{
5698 struct drm_device *dev = crtc->dev;
5699 struct drm_i915_private *dev_priv = dev->dev_private;
5700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5701 struct drm_display_mode *adjusted_mode =
5702 &intel_crtc->config.adjusted_mode;
5703 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5704 int pipe = intel_crtc->pipe;
5705 int plane = intel_crtc->plane;
5706 int num_connectors = 0;
ed7ef439 5707 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5708 struct intel_encoder *encoder;
09b4ddf9
PZ		 5709 int ret;
5710 bool dither;
5711
5712 for_each_encoder_on_crtc(dev, crtc, encoder) {
5713 switch (encoder->type) {
09b4ddf9
PZ		 5714 case INTEL_OUTPUT_DISPLAYPORT:
5715 is_dp = true;
5716 break;
5717 case INTEL_OUTPUT_EDP:
5718 is_dp = true;
5719 if (!intel_encoder_is_pch_edp(&encoder->base))
5720 is_cpu_edp = true;
5721 break;
5722 }
5723
5724 num_connectors++;
5725 }
5726
5dc5298b
PZ		 5727 /* We are not sure yet this won't happen. */
5728 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5729 INTEL_PCH_TYPE(dev));
5730
5731 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5732 num_connectors, pipe_name(pipe));
5733
702e7a56 5734 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5735 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5736
5737 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5738
6441ab5f
PZ		 5739 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5740 return -EINVAL;
5741
09b4ddf9
PZ		 5742 /* Ensure that the cursor is valid for the new mode before changing... */
5743 intel_crtc_update_cursor(crtc, true);
5744
5745 /* determine panel color depth */
4e53c2e0 5746 dither = intel_crtc->config.dither;
09b4ddf9 5747
09b4ddf9
PZ		 5748 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5749 drm_mode_debug_printmodeline(mode);
5750
ed7ef439 5751 if (is_dp && !is_cpu_edp)
09b4ddf9 5752 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5753
5754 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5755
5756 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5757
1eb8dfec 5758 if (!is_dp || is_cpu_edp)
6cc5f341 5759 ironlake_set_m_n(crtc);
09b4ddf9 5760
ee2b0b38 5761 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5762
50f3b016 5763 intel_set_pipe_csc(crtc);
86d3efce 5764
09b4ddf9 5765 /* Set up the display plane register */
86d3efce 5766 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5767 POSTING_READ(DSPCNTR(plane));
5768
5769 ret = intel_pipe_set_base(crtc, x, y, fb);
5770
5771 intel_update_watermarks(dev);
5772
5773 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5774
1f803ee5 5775 return ret;
79e53945
JB		 5776}
5777
f564048e 5778static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5779 int x, int y,
94352cf9 5780 struct drm_framebuffer *fb)
f564048e
EA		 5781{
5782 struct drm_device *dev = crtc->dev;
5783 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5784 struct drm_encoder_helper_funcs *encoder_funcs;
5785 struct intel_encoder *encoder;
0b701d27 5786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5787 struct drm_display_mode *adjusted_mode =
5788 &intel_crtc->config.adjusted_mode;
5789 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5790 int pipe = intel_crtc->pipe;
f564048e
EA		 5791 int ret;
5792
cc464b2a
PZ		 5793 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5794 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5795 else
5796 intel_crtc->cpu_transcoder = pipe;
5797
0b701d27 5798 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5799
b8cecdf5
DV		 5800 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5801
79e53945 5802 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5803
9256aa19
DV		 5804 if (ret != 0)
5805 return ret;
5806
5807 for_each_encoder_on_crtc(dev, crtc, encoder) {
5808 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5809 encoder->base.base.id,
5810 drm_get_encoder_name(&encoder->base),
5811 mode->base.id, mode->name);
6cc5f341
DV		 5812 if (encoder->mode_set) {
5813 encoder->mode_set(encoder);
5814 } else {
5815 encoder_funcs = encoder->base.helper_private;
5816 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5817 }
9256aa19
DV		 5818 }
5819
5820 return 0;
79e53945
JB		 5821}
5822
3a9627f4
WF		 5823static bool intel_eld_uptodate(struct drm_connector *connector,
5824 int reg_eldv, uint32_t bits_eldv,
5825 int reg_elda, uint32_t bits_elda,
5826 int reg_edid)
5827{
5828 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5829 uint8_t *eld = connector->eld;
5830 uint32_t i;
5831
5832 i = I915_READ(reg_eldv);
5833 i &= bits_eldv;
5834
5835 if (!eld[0])
5836 return !i;
5837
5838 if (!i)
5839 return false;
5840
5841 i = I915_READ(reg_elda);
5842 i &= ~bits_elda;
5843 I915_WRITE(reg_elda, i);
5844
5845 for (i = 0; i < eld[2]; i++)
5846 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5847 return false;
5848
5849 return true;
5850}
5851
e0dac65e
WF		 5852static void g4x_write_eld(struct drm_connector *connector,
5853 struct drm_crtc *crtc)
5854{
5855 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5856 uint8_t *eld = connector->eld;
5857 uint32_t eldv;
5858 uint32_t len;
5859 uint32_t i;
5860
5861 i = I915_READ(G4X_AUD_VID_DID);
5862
5863 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5864 eldv = G4X_ELDV_DEVCL_DEVBLC;
5865 else
5866 eldv = G4X_ELDV_DEVCTG;
5867
3a9627f4
WF		 5868 if (intel_eld_uptodate(connector,
5869 G4X_AUD_CNTL_ST, eldv,
5870 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5871 G4X_HDMIW_HDMIEDID))
5872 return;
5873
e0dac65e
WF		 5874 i = I915_READ(G4X_AUD_CNTL_ST);
5875 i &= ~(eldv | G4X_ELD_ADDR);
5876 len = (i >> 9) & 0x1f; /* ELD buffer size */
5877 I915_WRITE(G4X_AUD_CNTL_ST, i);
5878
5879 if (!eld[0])
5880 return;
5881
5882 len = min_t(uint8_t, eld[2], len);
5883 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5884 for (i = 0; i < len; i++)
5885 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5886
5887 i = I915_READ(G4X_AUD_CNTL_ST);
5888 i |= eldv;
5889 I915_WRITE(G4X_AUD_CNTL_ST, i);
5890}
5891
83358c85
WX		 5892static void haswell_write_eld(struct drm_connector *connector,
5893 struct drm_crtc *crtc)
5894{
5895 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5896 uint8_t *eld = connector->eld;
5897 struct drm_device *dev = crtc->dev;
7b9f35a6 5898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5899 uint32_t eldv;
5900 uint32_t i;
5901 int len;
5902 int pipe = to_intel_crtc(crtc)->pipe;
5903 int tmp;
5904
5905 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5906 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5907 int aud_config = HSW_AUD_CFG(pipe);
5908 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5909
5910
5911 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5912
5913 /* Audio output enable */
5914 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5915 tmp = I915_READ(aud_cntrl_st2);
5916 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5917 I915_WRITE(aud_cntrl_st2, tmp);
5918
5919 /* Wait for 1 vertical blank */
5920 intel_wait_for_vblank(dev, pipe);
5921
5922 /* Set ELD valid state */
5923 tmp = I915_READ(aud_cntrl_st2);
5924 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5925 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5926 I915_WRITE(aud_cntrl_st2, tmp);
5927 tmp = I915_READ(aud_cntrl_st2);
5928 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5929
5930 /* Enable HDMI mode */
5931 tmp = I915_READ(aud_config);
5932 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5933 /* clear N_programing_enable and N_value_index */
5934 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5935 I915_WRITE(aud_config, tmp);
5936
5937 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5938
5939 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5940 intel_crtc->eld_vld = true;
83358c85
WX		 5941
5942 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5943 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5944 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5945 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5946 } else
5947 I915_WRITE(aud_config, 0);
5948
5949 if (intel_eld_uptodate(connector,
5950 aud_cntrl_st2, eldv,
5951 aud_cntl_st, IBX_ELD_ADDRESS,
5952 hdmiw_hdmiedid))
5953 return;
5954
5955 i = I915_READ(aud_cntrl_st2);
5956 i &= ~eldv;
5957 I915_WRITE(aud_cntrl_st2, i);
5958
5959 if (!eld[0])
5960 return;
5961
5962 i = I915_READ(aud_cntl_st);
5963 i &= ~IBX_ELD_ADDRESS;
5964 I915_WRITE(aud_cntl_st, i);
5965 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5966 DRM_DEBUG_DRIVER("port num:%d\n", i);
5967
5968 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5969 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5970 for (i = 0; i < len; i++)
5971 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5972
5973 i = I915_READ(aud_cntrl_st2);
5974 i |= eldv;
5975 I915_WRITE(aud_cntrl_st2, i);
5976
5977}
5978
e0dac65e
WF		 5979static void ironlake_write_eld(struct drm_connector *connector,
5980 struct drm_crtc *crtc)
5981{
5982 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5983 uint8_t *eld = connector->eld;
5984 uint32_t eldv;
5985 uint32_t i;
5986 int len;
5987 int hdmiw_hdmiedid;
b6daa025 5988 int aud_config;
e0dac65e
WF		 5989 int aud_cntl_st;
5990 int aud_cntrl_st2;
9b138a83 5991 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5992
b3f33cbf 5993 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5994 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5995 aud_config = IBX_AUD_CFG(pipe);
5996 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5997 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5998 } else {
9b138a83
WX		 5999 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6000 aud_config = CPT_AUD_CFG(pipe);
6001 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6002 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6003 }
6004
9b138a83 6005 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6006
6007 i = I915_READ(aud_cntl_st);
9b138a83 6008 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6009 if (!i) {
6010 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6011 /* operate blindly on all ports */
1202b4c6
WF		 6012 eldv = IBX_ELD_VALIDB;
6013 eldv |= IBX_ELD_VALIDB << 4;
6014 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6015 } else {
6016 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6017 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6018 }
6019
3a9627f4
WF		 6020 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6021 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6022 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6023 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6024 } else
6025 I915_WRITE(aud_config, 0);
e0dac65e 6026
3a9627f4
WF		 6027 if (intel_eld_uptodate(connector,
6028 aud_cntrl_st2, eldv,
6029 aud_cntl_st, IBX_ELD_ADDRESS,
6030 hdmiw_hdmiedid))
6031 return;
6032
e0dac65e
WF		 6033 i = I915_READ(aud_cntrl_st2);
6034 i &= ~eldv;
6035 I915_WRITE(aud_cntrl_st2, i);
6036
6037 if (!eld[0])
6038 return;
6039
e0dac65e 6040 i = I915_READ(aud_cntl_st);
1202b4c6 6041 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6042 I915_WRITE(aud_cntl_st, i);
6043
6044 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6045 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6046 for (i = 0; i < len; i++)
6047 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6048
6049 i = I915_READ(aud_cntrl_st2);
6050 i |= eldv;
6051 I915_WRITE(aud_cntrl_st2, i);
6052}
6053
6054void intel_write_eld(struct drm_encoder *encoder,
6055 struct drm_display_mode *mode)
6056{
6057 struct drm_crtc *crtc = encoder->crtc;
6058 struct drm_connector *connector;
6059 struct drm_device *dev = encoder->dev;
6060 struct drm_i915_private *dev_priv = dev->dev_private;
6061
6062 connector = drm_select_eld(encoder, mode);
6063 if (!connector)
6064 return;
6065
6066 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6067 connector->base.id,
6068 drm_get_connector_name(connector),
6069 connector->encoder->base.id,
6070 drm_get_encoder_name(connector->encoder));
6071
6072 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6073
6074 if (dev_priv->display.write_eld)
6075 dev_priv->display.write_eld(connector, crtc);
6076}
6077
79e53945
JB		 6078/** Loads the palette/gamma unit for the CRTC with the prepared values */
6079void intel_crtc_load_lut(struct drm_crtc *crtc)
6080{
6081 struct drm_device *dev = crtc->dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6084 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6085 int i;
6086
6087 /* The clocks have to be on to load the palette. */
aed3f09d 6088 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6089 return;
6090
f2b115e6 6091 /* use legacy palette for Ironlake */
bad720ff 6092 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6093 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6094
79e53945
JB		 6095 for (i = 0; i < 256; i++) {
6096 I915_WRITE(palreg + 4 * i,
6097 (intel_crtc->lut_r[i] << 16) |
6098 (intel_crtc->lut_g[i] << 8) |
6099 intel_crtc->lut_b[i]);
6100 }
6101}
6102
560b85bb
CW		 6103static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6104{
6105 struct drm_device *dev = crtc->dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6108 bool visible = base != 0;
6109 u32 cntl;
6110
6111 if (intel_crtc->cursor_visible == visible)
6112 return;
6113
9db4a9c7 6114 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6115 if (visible) {
6116 /* On these chipsets we can only modify the base whilst
6117 * the cursor is disabled.
6118 */
9db4a9c7 6119 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6120
6121 cntl &= ~(CURSOR_FORMAT_MASK);
6122 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6123 cntl |= CURSOR_ENABLE |
6124 CURSOR_GAMMA_ENABLE |
6125 CURSOR_FORMAT_ARGB;
6126 } else
6127 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6128 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6129
6130 intel_crtc->cursor_visible = visible;
6131}
6132
6133static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6134{
6135 struct drm_device *dev = crtc->dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6138 int pipe = intel_crtc->pipe;
6139 bool visible = base != 0;
6140
6141 if (intel_crtc->cursor_visible != visible) {
548f245b 6142 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6143 if (base) {
6144 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6145 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6146 cntl |= pipe << 28; /* Connect to correct pipe */
6147 } else {
6148 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6149 cntl |= CURSOR_MODE_DISABLE;
6150 }
9db4a9c7 6151 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6152
6153 intel_crtc->cursor_visible = visible;
6154 }
6155 /* and commit changes on next vblank */
9db4a9c7 6156 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6157}
6158
65a21cd6
JB		 6159static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6160{
6161 struct drm_device *dev = crtc->dev;
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164 int pipe = intel_crtc->pipe;
6165 bool visible = base != 0;
6166
6167 if (intel_crtc->cursor_visible != visible) {
6168 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6169 if (base) {
6170 cntl &= ~CURSOR_MODE;
6171 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6172 } else {
6173 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6174 cntl |= CURSOR_MODE_DISABLE;
6175 }
86d3efce
VS		 6176 if (IS_HASWELL(dev))
6177 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6178 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6179
6180 intel_crtc->cursor_visible = visible;
6181 }
6182 /* and commit changes on next vblank */
6183 I915_WRITE(CURBASE_IVB(pipe), base);
6184}
6185
cda4b7d3 6186/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6187static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6188 bool on)
cda4b7d3
CW		 6189{
6190 struct drm_device *dev = crtc->dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6193 int pipe = intel_crtc->pipe;
6194 int x = intel_crtc->cursor_x;
6195 int y = intel_crtc->cursor_y;
560b85bb 6196 u32 base, pos;
cda4b7d3
CW		 6197 bool visible;
6198
6199 pos = 0;
6200
6b383a7f 6201 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6202 base = intel_crtc->cursor_addr;
6203 if (x > (int) crtc->fb->width)
6204 base = 0;
6205
6206 if (y > (int) crtc->fb->height)
6207 base = 0;
6208 } else
6209 base = 0;
6210
6211 if (x < 0) {
6212 if (x + intel_crtc->cursor_width < 0)
6213 base = 0;
6214
6215 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6216 x = -x;
6217 }
6218 pos |= x << CURSOR_X_SHIFT;
6219
6220 if (y < 0) {
6221 if (y + intel_crtc->cursor_height < 0)
6222 base = 0;
6223
6224 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6225 y = -y;
6226 }
6227 pos |= y << CURSOR_Y_SHIFT;
6228
6229 visible = base != 0;
560b85bb 6230 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6231 return;
6232
0cd83aa9 6233 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6234 I915_WRITE(CURPOS_IVB(pipe), pos);
6235 ivb_update_cursor(crtc, base);
6236 } else {
6237 I915_WRITE(CURPOS(pipe), pos);
6238 if (IS_845G(dev) || IS_I865G(dev))
6239 i845_update_cursor(crtc, base);
6240 else
6241 i9xx_update_cursor(crtc, base);
6242 }
cda4b7d3
CW		 6243}
6244
79e53945 6245static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6246 struct drm_file *file,
79e53945
JB		 6247 uint32_t handle,
6248 uint32_t width, uint32_t height)
6249{
6250 struct drm_device *dev = crtc->dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6253 struct drm_i915_gem_object *obj;
cda4b7d3 6254 uint32_t addr;
3f8bc370 6255 int ret;
79e53945 6256
79e53945
JB		 6257 /* if we want to turn off the cursor ignore width and height */
6258 if (!handle) {
28c97730 6259 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6260 addr = 0;
05394f39 6261 obj = NULL;
5004417d 6262 mutex_lock(&dev->struct_mutex);
3f8bc370 6263 goto finish;
79e53945
JB		 6264 }
6265
6266 /* Currently we only support 64x64 cursors */
6267 if (width != 64 || height != 64) {
6268 DRM_ERROR("we currently only support 64x64 cursors\n");
6269 return -EINVAL;
6270 }
6271
05394f39 6272 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6273 if (&obj->base == NULL)
79e53945
JB		 6274 return -ENOENT;
6275
05394f39 6276 if (obj->base.size < width * height * 4) {
79e53945 6277 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6278 ret = -ENOMEM;
6279 goto fail;
79e53945
JB		 6280 }
6281
71acb5eb 6282 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6283 mutex_lock(&dev->struct_mutex);
b295d1b6 6284 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6285 unsigned alignment;
6286
d9e86c0e
CW		 6287 if (obj->tiling_mode) {
6288 DRM_ERROR("cursor cannot be tiled\n");
6289 ret = -EINVAL;
6290 goto fail_locked;
6291 }
6292
693db184
CW		 6293 /* Note that the w/a also requires 2 PTE of padding following
6294 * the bo. We currently fill all unused PTE with the shadow
6295 * page and so we should always have valid PTE following the
6296 * cursor preventing the VT-d warning.
6297 */
6298 alignment = 0;
6299 if (need_vtd_wa(dev))
6300 alignment = 64*1024;
6301
6302 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6303 if (ret) {
6304 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6305 goto fail_locked;
e7b526bb
CW		 6306 }
6307
d9e86c0e
CW		 6308 ret = i915_gem_object_put_fence(obj);
6309 if (ret) {
2da3b9b9 6310 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6311 goto fail_unpin;
6312 }
6313
05394f39 6314 addr = obj->gtt_offset;
71acb5eb 6315 } else {
6eeefaf3 6316 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6317 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6318 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6319 align);
71acb5eb
DA		 6320 if (ret) {
6321 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6322 goto fail_locked;
71acb5eb 6323 }
05394f39 6324 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6325 }
6326
a6c45cf0 6327 if (IS_GEN2(dev))
14b60391
JB		 6328 I915_WRITE(CURSIZE, (height << 12) | width);
6329
3f8bc370 6330 finish:
3f8bc370 6331 if (intel_crtc->cursor_bo) {
b295d1b6 6332 if (dev_priv->info->cursor_needs_physical) {
05394f39 6333 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6334 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6335 } else
6336 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6337 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6338 }
80824003 6339
7f9872e0 6340 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6341
6342 intel_crtc->cursor_addr = addr;
05394f39 6343 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6344 intel_crtc->cursor_width = width;
6345 intel_crtc->cursor_height = height;
6346
6b383a7f 6347 intel_crtc_update_cursor(crtc, true);
3f8bc370 6348
79e53945 6349 return 0;
e7b526bb 6350fail_unpin:
05394f39 6351 i915_gem_object_unpin(obj);
7f9872e0 6352fail_locked:
34b8686e 6353 mutex_unlock(&dev->struct_mutex);
bc9025bd 6354fail:
05394f39 6355 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6356 return ret;
79e53945
JB		 6357}
6358
6359static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6360{
79e53945 6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6362
cda4b7d3
CW		 6363 intel_crtc->cursor_x = x;
6364 intel_crtc->cursor_y = y;
652c393a 6365
6b383a7f 6366 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6367
6368 return 0;
6369}
6370
6371/** Sets the color ramps on behalf of RandR */
6372void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6373 u16 blue, int regno)
6374{
6375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376
6377 intel_crtc->lut_r[regno] = red >> 8;
6378 intel_crtc->lut_g[regno] = green >> 8;
6379 intel_crtc->lut_b[regno] = blue >> 8;
6380}
6381
b8c00ac5
DA		 6382void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6383 u16 *blue, int regno)
6384{
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386
6387 *red = intel_crtc->lut_r[regno] << 8;
6388 *green = intel_crtc->lut_g[regno] << 8;
6389 *blue = intel_crtc->lut_b[regno] << 8;
6390}
6391
79e53945 6392static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6393 u16 *blue, uint32_t start, uint32_t size)
79e53945 6394{
7203425a 6395 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6397
7203425a 6398 for (i = start; i < end; i++) {
79e53945
JB		 6399 intel_crtc->lut_r[i] = red[i] >> 8;
6400 intel_crtc->lut_g[i] = green[i] >> 8;
6401 intel_crtc->lut_b[i] = blue[i] >> 8;
6402 }
6403
6404 intel_crtc_load_lut(crtc);
6405}
6406
79e53945
JB		 6407/* VESA 640x480x72Hz mode to set on the pipe */
6408static struct drm_display_mode load_detect_mode = {
6409 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6410 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6411};
6412
d2dff872
CW		 6413static struct drm_framebuffer *
6414intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6415 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6416 struct drm_i915_gem_object *obj)
6417{
6418 struct intel_framebuffer *intel_fb;
6419 int ret;
6420
6421 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6422 if (!intel_fb) {
6423 drm_gem_object_unreference_unlocked(&obj->base);
6424 return ERR_PTR(-ENOMEM);
6425 }
6426
6427 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6428 if (ret) {
6429 drm_gem_object_unreference_unlocked(&obj->base);
6430 kfree(intel_fb);
6431 return ERR_PTR(ret);
6432 }
6433
6434 return &intel_fb->base;
6435}
6436
6437static u32
6438intel_framebuffer_pitch_for_width(int width, int bpp)
6439{
6440 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6441 return ALIGN(pitch, 64);
6442}
6443
6444static u32
6445intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6446{
6447 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6448 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6449}
6450
6451static struct drm_framebuffer *
6452intel_framebuffer_create_for_mode(struct drm_device *dev,
6453 struct drm_display_mode *mode,
6454 int depth, int bpp)
6455{
6456 struct drm_i915_gem_object *obj;
0fed39bd 6457 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6458
6459 obj = i915_gem_alloc_object(dev,
6460 intel_framebuffer_size_for_mode(mode, bpp));
6461 if (obj == NULL)
6462 return ERR_PTR(-ENOMEM);
6463
6464 mode_cmd.width = mode->hdisplay;
6465 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6466 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6467 bpp);
5ca0c34a 6468 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6469
6470 return intel_framebuffer_create(dev, &mode_cmd, obj);
6471}
6472
6473static struct drm_framebuffer *
6474mode_fits_in_fbdev(struct drm_device *dev,
6475 struct drm_display_mode *mode)
6476{
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 struct drm_i915_gem_object *obj;
6479 struct drm_framebuffer *fb;
6480
6481 if (dev_priv->fbdev == NULL)
6482 return NULL;
6483
6484 obj = dev_priv->fbdev->ifb.obj;
6485 if (obj == NULL)
6486 return NULL;
6487
6488 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6489 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6490 fb->bits_per_pixel))
d2dff872
CW		 6491 return NULL;
6492
01f2c773 6493 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6494 return NULL;
6495
6496 return fb;
6497}
6498
d2434ab7 6499bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6500 struct drm_display_mode *mode,
8261b191 6501 struct intel_load_detect_pipe *old)
79e53945
JB		 6502{
6503 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6504 struct intel_encoder *intel_encoder =
6505 intel_attached_encoder(connector);
79e53945 6506 struct drm_crtc *possible_crtc;
4ef69c7a 6507 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6508 struct drm_crtc *crtc = NULL;
6509 struct drm_device *dev = encoder->dev;
94352cf9 6510 struct drm_framebuffer *fb;
79e53945
JB		 6511 int i = -1;
6512
d2dff872
CW		 6513 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6514 connector->base.id, drm_get_connector_name(connector),
6515 encoder->base.id, drm_get_encoder_name(encoder));
6516
79e53945
JB		 6517 /*
6518 * Algorithm gets a little messy:
7a5e4805 6519 *
79e53945
JB		 6520 * - if the connector already has an assigned crtc, use it (but make
6521 * sure it's on first)
7a5e4805 6522 *
79e53945
JB		 6523 * - try to find the first unused crtc that can drive this connector,
6524 * and use that if we find one
79e53945
JB		 6525 */
6526
6527 /* See if we already have a CRTC for this connector */
6528 if (encoder->crtc) {
6529 crtc = encoder->crtc;
8261b191 6530
7b24056b
DV		 6531 mutex_lock(&crtc->mutex);
6532
24218aac 6533 old->dpms_mode = connector->dpms;
8261b191
CW		 6534 old->load_detect_temp = false;
6535
6536 /* Make sure the crtc and connector are running */
24218aac
DV		 6537 if (connector->dpms != DRM_MODE_DPMS_ON)
6538 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6539
7173188d 6540 return true;
79e53945
JB		 6541 }
6542
6543 /* Find an unused one (if possible) */
6544 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6545 i++;
6546 if (!(encoder->possible_crtcs & (1 << i)))
6547 continue;
6548 if (!possible_crtc->enabled) {
6549 crtc = possible_crtc;
6550 break;
6551 }
79e53945
JB		 6552 }
6553
6554 /*
6555 * If we didn't find an unused CRTC, don't use any.
6556 */
6557 if (!crtc) {
7173188d
CW		 6558 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6559 return false;
79e53945
JB		 6560 }
6561
7b24056b 6562 mutex_lock(&crtc->mutex);
fc303101
DV		 6563 intel_encoder->new_crtc = to_intel_crtc(crtc);
6564 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6565
6566 intel_crtc = to_intel_crtc(crtc);
24218aac 6567 old->dpms_mode = connector->dpms;
8261b191 6568 old->load_detect_temp = true;
d2dff872 6569 old->release_fb = NULL;
79e53945 6570
6492711d
CW		 6571 if (!mode)
6572 mode = &load_detect_mode;
79e53945 6573
d2dff872
CW		 6574 /* We need a framebuffer large enough to accommodate all accesses
6575 * that the plane may generate whilst we perform load detection.
6576 * We can not rely on the fbcon either being present (we get called
6577 * during its initialisation to detect all boot displays, or it may
6578 * not even exist) or that it is large enough to satisfy the
6579 * requested mode.
6580 */
94352cf9
DV		 6581 fb = mode_fits_in_fbdev(dev, mode);
6582 if (fb == NULL) {
d2dff872 6583 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6584 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6585 old->release_fb = fb;
d2dff872
CW		 6586 } else
6587 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6588 if (IS_ERR(fb)) {
d2dff872 6589 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6590 mutex_unlock(&crtc->mutex);
0e8b3d3e 6591 return false;
79e53945 6592 }
79e53945 6593
c0c36b94 6594 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6595 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6596 if (old->release_fb)
6597 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6598 mutex_unlock(&crtc->mutex);
0e8b3d3e 6599 return false;
79e53945 6600 }
7173188d 6601
79e53945 6602 /* let the connector get through one full cycle before testing */
9d0498a2 6603 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6604 return true;
79e53945
JB		 6605}
6606
d2434ab7 6607void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6608 struct intel_load_detect_pipe *old)
79e53945 6609{
d2434ab7
DV		 6610 struct intel_encoder *intel_encoder =
6611 intel_attached_encoder(connector);
4ef69c7a 6612 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6613 struct drm_crtc *crtc = encoder->crtc;
79e53945 6614
d2dff872
CW		 6615 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6616 connector->base.id, drm_get_connector_name(connector),
6617 encoder->base.id, drm_get_encoder_name(encoder));
6618
8261b191 6619 if (old->load_detect_temp) {
fc303101
DV		 6620 to_intel_connector(connector)->new_encoder = NULL;
6621 intel_encoder->new_crtc = NULL;
6622 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6623
36206361
DV		 6624 if (old->release_fb) {
6625 drm_framebuffer_unregister_private(old->release_fb);
6626 drm_framebuffer_unreference(old->release_fb);
6627 }
d2dff872 6628
67c96400 6629 mutex_unlock(&crtc->mutex);
0622a53c 6630 return;
79e53945
JB		 6631 }
6632
c751ce4f 6633 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6634 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6635 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6636
6637 mutex_unlock(&crtc->mutex);
79e53945
JB		 6638}
6639
6640/* Returns the clock of the currently programmed mode of the given pipe. */
6641static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6642{
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645 int pipe = intel_crtc->pipe;
548f245b 6646 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6647 u32 fp;
6648 intel_clock_t clock;
6649
6650 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6651 fp = I915_READ(FP0(pipe));
79e53945 6652 else
39adb7a5 6653 fp = I915_READ(FP1(pipe));
79e53945
JB		 6654
6655 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6656 if (IS_PINEVIEW(dev)) {
6657 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6658 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6659 } else {
6660 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6661 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6662 }
6663
a6c45cf0 6664 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6665 if (IS_PINEVIEW(dev))
6666 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6667 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6668 else
6669 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6670 DPLL_FPA01_P1_POST_DIV_SHIFT);
6671
6672 switch (dpll & DPLL_MODE_MASK) {
6673 case DPLLB_MODE_DAC_SERIAL:
6674 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6675 5 : 10;
6676 break;
6677 case DPLLB_MODE_LVDS:
6678 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6679 7 : 14;
6680 break;
6681 default:
28c97730 6682 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6683 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6684 return 0;
6685 }
6686
6687 /* XXX: Handle the 100Mhz refclk */
2177832f 6688 intel_clock(dev, 96000, &clock);
79e53945
JB		 6689 } else {
6690 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6691
6692 if (is_lvds) {
6693 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6694 DPLL_FPA01_P1_POST_DIV_SHIFT);
6695 clock.p2 = 14;
6696
6697 if ((dpll & PLL_REF_INPUT_MASK) ==
6698 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6699 /* XXX: might not be 66MHz */
2177832f 6700 intel_clock(dev, 66000, &clock);
79e53945 6701 } else
2177832f 6702 intel_clock(dev, 48000, &clock);
79e53945
JB		 6703 } else {
6704 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6705 clock.p1 = 2;
6706 else {
6707 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6708 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6709 }
6710 if (dpll & PLL_P2_DIVIDE_BY_4)
6711 clock.p2 = 4;
6712 else
6713 clock.p2 = 2;
6714
2177832f 6715 intel_clock(dev, 48000, &clock);
79e53945
JB		 6716 }
6717 }
6718
6719 /* XXX: It would be nice to validate the clocks, but we can't reuse
6720 * i830PllIsValid() because it relies on the xf86_config connector
6721 * configuration being accurate, which it isn't necessarily.
6722 */
6723
6724 return clock.dot;
6725}
6726
6727/** Returns the currently programmed mode of the given pipe. */
6728struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6729 struct drm_crtc *crtc)
6730{
548f245b 6731 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6733 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6734 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6735 int htot = I915_READ(HTOTAL(cpu_transcoder));
6736 int hsync = I915_READ(HSYNC(cpu_transcoder));
6737 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6738 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6739
6740 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6741 if (!mode)
6742 return NULL;
6743
6744 mode->clock = intel_crtc_clock_get(dev, crtc);
6745 mode->hdisplay = (htot & 0xffff) + 1;
6746 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6747 mode->hsync_start = (hsync & 0xffff) + 1;
6748 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6749 mode->vdisplay = (vtot & 0xffff) + 1;
6750 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6751 mode->vsync_start = (vsync & 0xffff) + 1;
6752 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6753
6754 drm_mode_set_name(mode);
79e53945
JB		 6755
6756 return mode;
6757}
6758
3dec0095 6759static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6760{
6761 struct drm_device *dev = crtc->dev;
6762 drm_i915_private_t *dev_priv = dev->dev_private;
6763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6764 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6765 int dpll_reg = DPLL(pipe);
6766 int dpll;
652c393a 6767
bad720ff 6768 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6769 return;
6770
6771 if (!dev_priv->lvds_downclock_avail)
6772 return;
6773
dbdc6479 6774 dpll = I915_READ(dpll_reg);
652c393a 6775 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6776 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6777
8ac5a6d5 6778 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6779
6780 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6781 I915_WRITE(dpll_reg, dpll);
9d0498a2 6782 intel_wait_for_vblank(dev, pipe);
dbdc6479 6783
652c393a
JB		 6784 dpll = I915_READ(dpll_reg);
6785 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6786 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6787 }
652c393a
JB		 6788}
6789
6790static void intel_decrease_pllclock(struct drm_crtc *crtc)
6791{
6792 struct drm_device *dev = crtc->dev;
6793 drm_i915_private_t *dev_priv = dev->dev_private;
6794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6795
bad720ff 6796 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6797 return;
6798
6799 if (!dev_priv->lvds_downclock_avail)
6800 return;
6801
6802 /*
6803 * Since this is called by a timer, we should never get here in
6804 * the manual case.
6805 */
6806 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6807 int pipe = intel_crtc->pipe;
6808 int dpll_reg = DPLL(pipe);
6809 int dpll;
f6e5b160 6810
44d98a61 6811 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6812
8ac5a6d5 6813 assert_panel_unlocked(dev_priv, pipe);
652c393a 6814
dc257cf1 6815 dpll = I915_READ(dpll_reg);
652c393a
JB		 6816 dpll |= DISPLAY_RATE_SELECT_FPA1;
6817 I915_WRITE(dpll_reg, dpll);
9d0498a2 6818 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6819 dpll = I915_READ(dpll_reg);
6820 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6821 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6822 }
6823
6824}
6825
f047e395
CW		 6826void intel_mark_busy(struct drm_device *dev)
6827{
f047e395
CW		 6828 i915_update_gfx_val(dev->dev_private);
6829}
6830
6831void intel_mark_idle(struct drm_device *dev)
652c393a 6832{
652c393a 6833 struct drm_crtc *crtc;
652c393a
JB		 6834
6835 if (!i915_powersave)
6836 return;
6837
652c393a 6838 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6839 if (!crtc->fb)
6840 continue;
6841
725a5b54 6842 intel_decrease_pllclock(crtc);
652c393a 6843 }
652c393a
JB		 6844}
6845
725a5b54 6846void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6847{
f047e395
CW		 6848 struct drm_device *dev = obj->base.dev;
6849 struct drm_crtc *crtc;
652c393a 6850
f047e395 6851 if (!i915_powersave)
acb87dfb
CW		 6852 return;
6853
652c393a
JB		 6854 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6855 if (!crtc->fb)
6856 continue;
6857
f047e395 6858 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6859 intel_increase_pllclock(crtc);
652c393a
JB		 6860 }
6861}
6862
79e53945
JB		 6863static void intel_crtc_destroy(struct drm_crtc *crtc)
6864{
6865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6866 struct drm_device *dev = crtc->dev;
6867 struct intel_unpin_work *work;
6868 unsigned long flags;
6869
6870 spin_lock_irqsave(&dev->event_lock, flags);
6871 work = intel_crtc->unpin_work;
6872 intel_crtc->unpin_work = NULL;
6873 spin_unlock_irqrestore(&dev->event_lock, flags);
6874
6875 if (work) {
6876 cancel_work_sync(&work->work);
6877 kfree(work);
6878 }
79e53945
JB		 6879
6880 drm_crtc_cleanup(crtc);
67e77c5a 6881
79e53945
JB		 6882 kfree(intel_crtc);
6883}
6884
6b95a207
KH		 6885static void intel_unpin_work_fn(struct work_struct *__work)
6886{
6887 struct intel_unpin_work *work =
6888 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6889 struct drm_device *dev = work->crtc->dev;
6b95a207 6890
b4a98e57 6891 mutex_lock(&dev->struct_mutex);
1690e1eb 6892 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6893 drm_gem_object_unreference(&work->pending_flip_obj->base);
6894 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6895
b4a98e57
CW		 6896 intel_update_fbc(dev);
6897 mutex_unlock(&dev->struct_mutex);
6898
6899 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6900 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6901
6b95a207
KH		 6902 kfree(work);
6903}
6904
1afe3e9d 6905static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6906 struct drm_crtc *crtc)
6b95a207
KH		 6907{
6908 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6910 struct intel_unpin_work *work;
6b95a207
KH		 6911 unsigned long flags;
6912
6913 /* Ignore early vblank irqs */
6914 if (intel_crtc == NULL)
6915 return;
6916
6917 spin_lock_irqsave(&dev->event_lock, flags);
6918 work = intel_crtc->unpin_work;
e7d841ca
CW		 6919
6920 /* Ensure we don't miss a work->pending update ... */
6921 smp_rmb();
6922
6923 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6924 spin_unlock_irqrestore(&dev->event_lock, flags);
6925 return;
6926 }
6927
e7d841ca
CW		 6928 /* and that the unpin work is consistent wrt ->pending. */
6929 smp_rmb();
6930
6b95a207 6931 intel_crtc->unpin_work = NULL;
6b95a207 6932
45a066eb
RC		 6933 if (work->event)
6934 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6935
0af7e4df
MK		 6936 drm_vblank_put(dev, intel_crtc->pipe);
6937
6b95a207
KH		 6938 spin_unlock_irqrestore(&dev->event_lock, flags);
6939
2c10d571 6940 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6941
6942 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6943
6944 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6945}
6946
1afe3e9d
JB		 6947void intel_finish_page_flip(struct drm_device *dev, int pipe)
6948{
6949 drm_i915_private_t *dev_priv = dev->dev_private;
6950 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6951
49b14a5c 6952 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6953}
6954
6955void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6956{
6957 drm_i915_private_t *dev_priv = dev->dev_private;
6958 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6959
49b14a5c 6960 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6961}
6962
6b95a207
KH		 6963void intel_prepare_page_flip(struct drm_device *dev, int plane)
6964{
6965 drm_i915_private_t *dev_priv = dev->dev_private;
6966 struct intel_crtc *intel_crtc =
6967 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6968 unsigned long flags;
6969
e7d841ca
CW		 6970 /* NB: An MMIO update of the plane base pointer will also
6971 * generate a page-flip completion irq, i.e. every modeset
6972 * is also accompanied by a spurious intel_prepare_page_flip().
6973 */
6b95a207 6974 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6975 if (intel_crtc->unpin_work)
6976 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6977 spin_unlock_irqrestore(&dev->event_lock, flags);
6978}
6979
e7d841ca
CW		 6980inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6981{
6982 /* Ensure that the work item is consistent when activating it ... */
6983 smp_wmb();
6984 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6985 /* and that it is marked active as soon as the irq could fire. */
6986 smp_wmb();
6987}
6988
8c9f3aaf
JB		 6989static int intel_gen2_queue_flip(struct drm_device *dev,
6990 struct drm_crtc *crtc,
6991 struct drm_framebuffer *fb,
6992 struct drm_i915_gem_object *obj)
6993{
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6996 u32 flip_mask;
6d90c952 6997 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6998 int ret;
6999
6d90c952 7000 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7001 if (ret)
83d4092b 7002 goto err;
8c9f3aaf 7003
6d90c952 7004 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7005 if (ret)
83d4092b 7006 goto err_unpin;
8c9f3aaf
JB		 7007
7008 /* Can't queue multiple flips, so wait for the previous
7009 * one to finish before executing the next.
7010 */
7011 if (intel_crtc->plane)
7012 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7013 else
7014 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7015 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7016 intel_ring_emit(ring, MI_NOOP);
7017 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7018 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7019 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7020 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7021 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7022
7023 intel_mark_page_flip_active(intel_crtc);
6d90c952 7024 intel_ring_advance(ring);
83d4092b
CW		 7025 return 0;
7026
7027err_unpin:
7028 intel_unpin_fb_obj(obj);
7029err:
8c9f3aaf
JB		 7030 return ret;
7031}
7032
7033static int intel_gen3_queue_flip(struct drm_device *dev,
7034 struct drm_crtc *crtc,
7035 struct drm_framebuffer *fb,
7036 struct drm_i915_gem_object *obj)
7037{
7038 struct drm_i915_private *dev_priv = dev->dev_private;
7039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7040 u32 flip_mask;
6d90c952 7041 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7042 int ret;
7043
6d90c952 7044 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7045 if (ret)
83d4092b 7046 goto err;
8c9f3aaf 7047
6d90c952 7048 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7049 if (ret)
83d4092b 7050 goto err_unpin;
8c9f3aaf
JB		 7051
7052 if (intel_crtc->plane)
7053 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7054 else
7055 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7056 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7057 intel_ring_emit(ring, MI_NOOP);
7058 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7059 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7060 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7061 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7062 intel_ring_emit(ring, MI_NOOP);
7063
e7d841ca 7064 intel_mark_page_flip_active(intel_crtc);
6d90c952 7065 intel_ring_advance(ring);
83d4092b
CW		 7066 return 0;
7067
7068err_unpin:
7069 intel_unpin_fb_obj(obj);
7070err:
8c9f3aaf
JB		 7071 return ret;
7072}
7073
7074static int intel_gen4_queue_flip(struct drm_device *dev,
7075 struct drm_crtc *crtc,
7076 struct drm_framebuffer *fb,
7077 struct drm_i915_gem_object *obj)
7078{
7079 struct drm_i915_private *dev_priv = dev->dev_private;
7080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7081 uint32_t pf, pipesrc;
6d90c952 7082 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7083 int ret;
7084
6d90c952 7085 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7086 if (ret)
83d4092b 7087 goto err;
8c9f3aaf 7088
6d90c952 7089 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7090 if (ret)
83d4092b 7091 goto err_unpin;
8c9f3aaf
JB		 7092
7093 /* i965+ uses the linear or tiled offsets from the
7094 * Display Registers (which do not change across a page-flip)
7095 * so we need only reprogram the base address.
7096 */
6d90c952
DV		 7097 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7098 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7099 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7100 intel_ring_emit(ring,
7101 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7102 obj->tiling_mode);
8c9f3aaf
JB		 7103
7104 /* XXX Enabling the panel-fitter across page-flip is so far
7105 * untested on non-native modes, so ignore it for now.
7106 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7107 */
7108 pf = 0;
7109 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7110 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7111
7112 intel_mark_page_flip_active(intel_crtc);
6d90c952 7113 intel_ring_advance(ring);
83d4092b
CW		 7114 return 0;
7115
7116err_unpin:
7117 intel_unpin_fb_obj(obj);
7118err:
8c9f3aaf
JB		 7119 return ret;
7120}
7121
7122static int intel_gen6_queue_flip(struct drm_device *dev,
7123 struct drm_crtc *crtc,
7124 struct drm_framebuffer *fb,
7125 struct drm_i915_gem_object *obj)
7126{
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7129 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7130 uint32_t pf, pipesrc;
7131 int ret;
7132
6d90c952 7133 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7134 if (ret)
83d4092b 7135 goto err;
8c9f3aaf 7136
6d90c952 7137 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7138 if (ret)
83d4092b 7139 goto err_unpin;
8c9f3aaf 7140
6d90c952
DV		 7141 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7142 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7143 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7144 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7145
dc257cf1
DV		 7146 /* Contrary to the suggestions in the documentation,
7147 * "Enable Panel Fitter" does not seem to be required when page
7148 * flipping with a non-native mode, and worse causes a normal
7149 * modeset to fail.
7150 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7151 */
7152 pf = 0;
8c9f3aaf 7153 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7154 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7155
7156 intel_mark_page_flip_active(intel_crtc);
6d90c952 7157 intel_ring_advance(ring);
83d4092b
CW		 7158 return 0;
7159
7160err_unpin:
7161 intel_unpin_fb_obj(obj);
7162err:
8c9f3aaf
JB		 7163 return ret;
7164}
7165
7c9017e5
JB		 7166/*
7167 * On gen7 we currently use the blit ring because (in early silicon at least)
7168 * the render ring doesn't give us interrpts for page flip completion, which
7169 * means clients will hang after the first flip is queued. Fortunately the
7170 * blit ring generates interrupts properly, so use it instead.
7171 */
7172static int intel_gen7_queue_flip(struct drm_device *dev,
7173 struct drm_crtc *crtc,
7174 struct drm_framebuffer *fb,
7175 struct drm_i915_gem_object *obj)
7176{
7177 struct drm_i915_private *dev_priv = dev->dev_private;
7178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7179 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7180 uint32_t plane_bit = 0;
7c9017e5
JB		 7181 int ret;
7182
7183 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7184 if (ret)
83d4092b 7185 goto err;
7c9017e5 7186
cb05d8de
DV		 7187 switch(intel_crtc->plane) {
7188 case PLANE_A:
7189 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7190 break;
7191 case PLANE_B:
7192 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7193 break;
7194 case PLANE_C:
7195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7196 break;
7197 default:
7198 WARN_ONCE(1, "unknown plane in flip command\n");
7199 ret = -ENODEV;
ab3951eb 7200 goto err_unpin;
cb05d8de
DV		 7201 }
7202
7c9017e5
JB		 7203 ret = intel_ring_begin(ring, 4);
7204 if (ret)
83d4092b 7205 goto err_unpin;
7c9017e5 7206
cb05d8de 7207 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7208 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7209 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7210 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7211
7212 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7213 intel_ring_advance(ring);
83d4092b
CW		 7214 return 0;
7215
7216err_unpin:
7217 intel_unpin_fb_obj(obj);
7218err:
7c9017e5
JB		 7219 return ret;
7220}
7221
8c9f3aaf
JB		 7222static int intel_default_queue_flip(struct drm_device *dev,
7223 struct drm_crtc *crtc,
7224 struct drm_framebuffer *fb,
7225 struct drm_i915_gem_object *obj)
7226{
7227 return -ENODEV;
7228}
7229
6b95a207
KH		 7230static int intel_crtc_page_flip(struct drm_crtc *crtc,
7231 struct drm_framebuffer *fb,
7232 struct drm_pending_vblank_event *event)
7233{
7234 struct drm_device *dev = crtc->dev;
7235 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7236 struct drm_framebuffer *old_fb = crtc->fb;
7237 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7239 struct intel_unpin_work *work;
8c9f3aaf 7240 unsigned long flags;
52e68630 7241 int ret;
6b95a207 7242
e6a595d2
VS		 7243 /* Can't change pixel format via MI display flips. */
7244 if (fb->pixel_format != crtc->fb->pixel_format)
7245 return -EINVAL;
7246
7247 /*
7248 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7249 * Note that pitch changes could also affect these register.
7250 */
7251 if (INTEL_INFO(dev)->gen > 3 &&
7252 (fb->offsets[0] != crtc->fb->offsets[0] ||
7253 fb->pitches[0] != crtc->fb->pitches[0]))
7254 return -EINVAL;
7255
6b95a207
KH		 7256 work = kzalloc(sizeof *work, GFP_KERNEL);
7257 if (work == NULL)
7258 return -ENOMEM;
7259
6b95a207 7260 work->event = event;
b4a98e57 7261 work->crtc = crtc;
4a35f83b 7262 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7263 INIT_WORK(&work->work, intel_unpin_work_fn);
7264
7317c75e
JB		 7265 ret = drm_vblank_get(dev, intel_crtc->pipe);
7266 if (ret)
7267 goto free_work;
7268
6b95a207
KH		 7269 /* We borrow the event spin lock for protecting unpin_work */
7270 spin_lock_irqsave(&dev->event_lock, flags);
7271 if (intel_crtc->unpin_work) {
7272 spin_unlock_irqrestore(&dev->event_lock, flags);
7273 kfree(work);
7317c75e 7274 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7275
7276 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7277 return -EBUSY;
7278 }
7279 intel_crtc->unpin_work = work;
7280 spin_unlock_irqrestore(&dev->event_lock, flags);
7281
b4a98e57
CW		 7282 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7283 flush_workqueue(dev_priv->wq);
7284
79158103
CW		 7285 ret = i915_mutex_lock_interruptible(dev);
7286 if (ret)
7287 goto cleanup;
6b95a207 7288
75dfca80 7289 /* Reference the objects for the scheduled work. */
05394f39
CW		 7290 drm_gem_object_reference(&work->old_fb_obj->base);
7291 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7292
7293 crtc->fb = fb;
96b099fd 7294
e1f99ce6 7295 work->pending_flip_obj = obj;
e1f99ce6 7296
4e5359cd
SF		 7297 work->enable_stall_check = true;
7298
b4a98e57 7299 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7300 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7301
8c9f3aaf
JB		 7302 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7303 if (ret)
7304 goto cleanup_pending;
6b95a207 7305
7782de3b 7306 intel_disable_fbc(dev);
f047e395 7307 intel_mark_fb_busy(obj);
6b95a207
KH		 7308 mutex_unlock(&dev->struct_mutex);
7309
e5510fac
JB		 7310 trace_i915_flip_request(intel_crtc->plane, obj);
7311
6b95a207 7312 return 0;
96b099fd 7313
8c9f3aaf 7314cleanup_pending:
b4a98e57 7315 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7316 crtc->fb = old_fb;
05394f39
CW		 7317 drm_gem_object_unreference(&work->old_fb_obj->base);
7318 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7319 mutex_unlock(&dev->struct_mutex);
7320
79158103 7321cleanup:
96b099fd
CW		 7322 spin_lock_irqsave(&dev->event_lock, flags);
7323 intel_crtc->unpin_work = NULL;
7324 spin_unlock_irqrestore(&dev->event_lock, flags);
7325
7317c75e
JB		 7326 drm_vblank_put(dev, intel_crtc->pipe);
7327free_work:
96b099fd
CW		 7328 kfree(work);
7329
7330 return ret;
6b95a207
KH		 7331}
7332
f6e5b160 7333static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7334 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7335 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7336};
7337
6ed0f796 7338bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7339{
6ed0f796
DV		 7340 struct intel_encoder *other_encoder;
7341 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7342
6ed0f796
DV		 7343 if (WARN_ON(!crtc))
7344 return false;
7345
7346 list_for_each_entry(other_encoder,
7347 &crtc->dev->mode_config.encoder_list,
7348 base.head) {
7349
7350 if (&other_encoder->new_crtc->base != crtc ||
7351 encoder == other_encoder)
7352 continue;
7353 else
7354 return true;
f47166d2
CW		 7355 }
7356
6ed0f796
DV		 7357 return false;
7358}
47f1c6c9 7359
50f56119
DV		 7360static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7361 struct drm_crtc *crtc)
7362{
7363 struct drm_device *dev;
7364 struct drm_crtc *tmp;
7365 int crtc_mask = 1;
47f1c6c9 7366
50f56119 7367 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7368
50f56119 7369 dev = crtc->dev;
47f1c6c9 7370
50f56119
DV		 7371 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7372 if (tmp == crtc)
7373 break;
7374 crtc_mask <<= 1;
7375 }
47f1c6c9 7376
50f56119
DV		 7377 if (encoder->possible_crtcs & crtc_mask)
7378 return true;
7379 return false;
47f1c6c9 7380}
79e53945 7381
9a935856
DV		 7382/**
7383 * intel_modeset_update_staged_output_state
7384 *
7385 * Updates the staged output configuration state, e.g. after we've read out the
7386 * current hw state.
7387 */
7388static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7389{
9a935856
DV		 7390 struct intel_encoder *encoder;
7391 struct intel_connector *connector;
f6e5b160 7392
9a935856
DV		 7393 list_for_each_entry(connector, &dev->mode_config.connector_list,
7394 base.head) {
7395 connector->new_encoder =
7396 to_intel_encoder(connector->base.encoder);
7397 }
f6e5b160 7398
9a935856
DV		 7399 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7400 base.head) {
7401 encoder->new_crtc =
7402 to_intel_crtc(encoder->base.crtc);
7403 }
f6e5b160
CW		 7404}
7405
9a935856
DV		 7406/**
7407 * intel_modeset_commit_output_state
7408 *
7409 * This function copies the stage display pipe configuration to the real one.
7410 */
7411static void intel_modeset_commit_output_state(struct drm_device *dev)
7412{
7413 struct intel_encoder *encoder;
7414 struct intel_connector *connector;
f6e5b160 7415
9a935856
DV		 7416 list_for_each_entry(connector, &dev->mode_config.connector_list,
7417 base.head) {
7418 connector->base.encoder = &connector->new_encoder->base;
7419 }
f6e5b160 7420
9a935856
DV		 7421 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7422 base.head) {
7423 encoder->base.crtc = &encoder->new_crtc->base;
7424 }
7425}
7426
4e53c2e0
DV		 7427static int
7428pipe_config_set_bpp(struct drm_crtc *crtc,
7429 struct drm_framebuffer *fb,
7430 struct intel_crtc_config *pipe_config)
7431{
7432 struct drm_device *dev = crtc->dev;
7433 struct drm_connector *connector;
7434 int bpp;
7435
d42264b1
DV		 7436 switch (fb->pixel_format) {
7437 case DRM_FORMAT_C8:
4e53c2e0
DV		 7438 bpp = 8*3; /* since we go through a colormap */
7439 break;
d42264b1
DV		 7440 case DRM_FORMAT_XRGB1555:
7441 case DRM_FORMAT_ARGB1555:
7442 /* checked in intel_framebuffer_init already */
7443 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7444 return -EINVAL;
7445 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7446 bpp = 6*3; /* min is 18bpp */
7447 break;
d42264b1
DV		 7448 case DRM_FORMAT_XBGR8888:
7449 case DRM_FORMAT_ABGR8888:
7450 /* checked in intel_framebuffer_init already */
7451 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7452 return -EINVAL;
7453 case DRM_FORMAT_XRGB8888:
7454 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7455 bpp = 8*3;
7456 break;
d42264b1
DV		 7457 case DRM_FORMAT_XRGB2101010:
7458 case DRM_FORMAT_ARGB2101010:
7459 case DRM_FORMAT_XBGR2101010:
7460 case DRM_FORMAT_ABGR2101010:
7461 /* checked in intel_framebuffer_init already */
7462 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7463 return -EINVAL;
4e53c2e0
DV		 7464 bpp = 10*3;
7465 break;
baba133a 7466 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7467 default:
7468 DRM_DEBUG_KMS("unsupported depth\n");
7469 return -EINVAL;
7470 }
7471
4e53c2e0
DV		 7472 pipe_config->pipe_bpp = bpp;
7473
7474 /* Clamp display bpp to EDID value */
7475 list_for_each_entry(connector, &dev->mode_config.connector_list,
7476 head) {
7477 if (connector->encoder && connector->encoder->crtc != crtc)
7478 continue;
7479
7480 /* Don't use an invalid EDID bpc value */
7481 if (connector->display_info.bpc &&
7482 connector->display_info.bpc * 3 < bpp) {
7483 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7484 bpp, connector->display_info.bpc*3);
7485 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7486 }
7487 }
7488
7489 return bpp;
7490}
7491
b8cecdf5
DV		 7492static struct intel_crtc_config *
7493intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7494 struct drm_framebuffer *fb,
b8cecdf5 7495 struct drm_display_mode *mode)
ee7b9f93 7496{
7758a113 7497 struct drm_device *dev = crtc->dev;
7758a113
DV		 7498 struct drm_encoder_helper_funcs *encoder_funcs;
7499 struct intel_encoder *encoder;
b8cecdf5 7500 struct intel_crtc_config *pipe_config;
4e53c2e0 7501 int plane_bpp;
ee7b9f93 7502
b8cecdf5
DV		 7503 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7504 if (!pipe_config)
7758a113
DV		 7505 return ERR_PTR(-ENOMEM);
7506
b8cecdf5
DV		 7507 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7508 drm_mode_copy(&pipe_config->requested_mode, mode);
7509
4e53c2e0
DV		 7510 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7511 if (plane_bpp < 0)
7512 goto fail;
7513
7758a113
DV		 7514 /* Pass our mode to the connectors and the CRTC to give them a chance to
7515 * adjust it according to limitations or connector properties, and also
7516 * a chance to reject the mode entirely.
47f1c6c9 7517 */
7758a113
DV		 7518 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7519 base.head) {
47f1c6c9 7520
7758a113
DV		 7521 if (&encoder->new_crtc->base != crtc)
7522 continue;
7ae89233
DV		 7523
7524 if (encoder->compute_config) {
7525 if (!(encoder->compute_config(encoder, pipe_config))) {
7526 DRM_DEBUG_KMS("Encoder config failure\n");
7527 goto fail;
7528 }
7529
7530 continue;
7531 }
7532
7758a113 7533 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7534 if (!(encoder_funcs->mode_fixup(&encoder->base,
7535 &pipe_config->requested_mode,
7536 &pipe_config->adjusted_mode))) {
7758a113
DV		 7537 DRM_DEBUG_KMS("Encoder fixup failed\n");
7538 goto fail;
7539 }
ee7b9f93 7540 }
47f1c6c9 7541
b8cecdf5 7542 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7543 DRM_DEBUG_KMS("CRTC fixup failed\n");
7544 goto fail;
ee7b9f93 7545 }
7758a113 7546 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7547
4e53c2e0
DV		 7548 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7549 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7550 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7551
b8cecdf5 7552 return pipe_config;
7758a113 7553fail:
b8cecdf5 7554 kfree(pipe_config);
7758a113 7555 return ERR_PTR(-EINVAL);
ee7b9f93 7556}
47f1c6c9 7557
e2e1ed41
DV		 7558/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7559 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7560static void
7561intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7562 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7563{
7564 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7565 struct drm_device *dev = crtc->dev;
7566 struct intel_encoder *encoder;
7567 struct intel_connector *connector;
7568 struct drm_crtc *tmp_crtc;
79e53945 7569
e2e1ed41 7570 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7571
e2e1ed41
DV		 7572 /* Check which crtcs have changed outputs connected to them, these need
7573 * to be part of the prepare_pipes mask. We don't (yet) support global
7574 * modeset across multiple crtcs, so modeset_pipes will only have one
7575 * bit set at most. */
7576 list_for_each_entry(connector, &dev->mode_config.connector_list,
7577 base.head) {
7578 if (connector->base.encoder == &connector->new_encoder->base)
7579 continue;
79e53945 7580
e2e1ed41
DV		 7581 if (connector->base.encoder) {
7582 tmp_crtc = connector->base.encoder->crtc;
7583
7584 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7585 }
7586
7587 if (connector->new_encoder)
7588 *prepare_pipes |=
7589 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7590 }
7591
e2e1ed41
DV		 7592 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7593 base.head) {
7594 if (encoder->base.crtc == &encoder->new_crtc->base)
7595 continue;
7596
7597 if (encoder->base.crtc) {
7598 tmp_crtc = encoder->base.crtc;
7599
7600 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7601 }
7602
7603 if (encoder->new_crtc)
7604 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7605 }
7606
e2e1ed41
DV		 7607 /* Check for any pipes that will be fully disabled ... */
7608 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7609 base.head) {
7610 bool used = false;
22fd0fab 7611
e2e1ed41
DV		 7612 /* Don't try to disable disabled crtcs. */
7613 if (!intel_crtc->base.enabled)
7614 continue;
7e7d76c3 7615
e2e1ed41
DV		 7616 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7617 base.head) {
7618 if (encoder->new_crtc == intel_crtc)
7619 used = true;
7620 }
7621
7622 if (!used)
7623 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7624 }
7625
e2e1ed41
DV		 7626
7627 /* set_mode is also used to update properties on life display pipes. */
7628 intel_crtc = to_intel_crtc(crtc);
7629 if (crtc->enabled)
7630 *prepare_pipes |= 1 << intel_crtc->pipe;
7631
7632 /* We only support modeset on one single crtc, hence we need to do that
7633 * only for the passed in crtc iff we change anything else than just
7634 * disable crtcs.
7635 *
7636 * This is actually not true, to be fully compatible with the old crtc
7637 * helper we automatically disable _any_ output (i.e. doesn't need to be
7638 * connected to the crtc we're modesetting on) if it's disconnected.
7639 * Which is a rather nutty api (since changed the output configuration
7640 * without userspace's explicit request can lead to confusion), but
7641 * alas. Hence we currently need to modeset on all pipes we prepare. */
7642 if (*prepare_pipes)
7643 *modeset_pipes = *prepare_pipes;
7644
7645 /* ... and mask these out. */
7646 *modeset_pipes &= ~(*disable_pipes);
7647 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7648}
79e53945 7649
ea9d758d 7650static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7651{
ea9d758d 7652 struct drm_encoder *encoder;
f6e5b160 7653 struct drm_device *dev = crtc->dev;
f6e5b160 7654
ea9d758d
DV		 7655 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7656 if (encoder->crtc == crtc)
7657 return true;
7658
7659 return false;
7660}
7661
7662static void
7663intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7664{
7665 struct intel_encoder *intel_encoder;
7666 struct intel_crtc *intel_crtc;
7667 struct drm_connector *connector;
7668
7669 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7670 base.head) {
7671 if (!intel_encoder->base.crtc)
7672 continue;
7673
7674 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7675
7676 if (prepare_pipes & (1 << intel_crtc->pipe))
7677 intel_encoder->connectors_active = false;
7678 }
7679
7680 intel_modeset_commit_output_state(dev);
7681
7682 /* Update computed state. */
7683 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7684 base.head) {
7685 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7686 }
7687
7688 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7689 if (!connector->encoder || !connector->encoder->crtc)
7690 continue;
7691
7692 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7693
7694 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7695 struct drm_property *dpms_property =
7696 dev->mode_config.dpms_property;
7697
ea9d758d 7698 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7699 drm_object_property_set_value(&connector->base,
68d34720
DV		 7700 dpms_property,
7701 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7702
7703 intel_encoder = to_intel_encoder(connector->encoder);
7704 intel_encoder->connectors_active = true;
7705 }
7706 }
7707
7708}
7709
25c5b266
DV		 7710#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7711 list_for_each_entry((intel_crtc), \
7712 &(dev)->mode_config.crtc_list, \
7713 base.head) \
7714 if (mask & (1 <<(intel_crtc)->pipe)) \
7715
b980514c 7716void
8af6cf88
DV		 7717intel_modeset_check_state(struct drm_device *dev)
7718{
7719 struct intel_crtc *crtc;
7720 struct intel_encoder *encoder;
7721 struct intel_connector *connector;
7722
7723 list_for_each_entry(connector, &dev->mode_config.connector_list,
7724 base.head) {
7725 /* This also checks the encoder/connector hw state with the
7726 * ->get_hw_state callbacks. */
7727 intel_connector_check_state(connector);
7728
7729 WARN(&connector->new_encoder->base != connector->base.encoder,
7730 "connector's staged encoder doesn't match current encoder\n");
7731 }
7732
7733 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7734 base.head) {
7735 bool enabled = false;
7736 bool active = false;
7737 enum pipe pipe, tracked_pipe;
7738
7739 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7740 encoder->base.base.id,
7741 drm_get_encoder_name(&encoder->base));
7742
7743 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7744 "encoder's stage crtc doesn't match current crtc\n");
7745 WARN(encoder->connectors_active && !encoder->base.crtc,
7746 "encoder's active_connectors set, but no crtc\n");
7747
7748 list_for_each_entry(connector, &dev->mode_config.connector_list,
7749 base.head) {
7750 if (connector->base.encoder != &encoder->base)
7751 continue;
7752 enabled = true;
7753 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7754 active = true;
7755 }
7756 WARN(!!encoder->base.crtc != enabled,
7757 "encoder's enabled state mismatch "
7758 "(expected %i, found %i)\n",
7759 !!encoder->base.crtc, enabled);
7760 WARN(active && !encoder->base.crtc,
7761 "active encoder with no crtc\n");
7762
7763 WARN(encoder->connectors_active != active,
7764 "encoder's computed active state doesn't match tracked active state "
7765 "(expected %i, found %i)\n", active, encoder->connectors_active);
7766
7767 active = encoder->get_hw_state(encoder, &pipe);
7768 WARN(active != encoder->connectors_active,
7769 "encoder's hw state doesn't match sw tracking "
7770 "(expected %i, found %i)\n",
7771 encoder->connectors_active, active);
7772
7773 if (!encoder->base.crtc)
7774 continue;
7775
7776 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7777 WARN(active && pipe != tracked_pipe,
7778 "active encoder's pipe doesn't match"
7779 "(expected %i, found %i)\n",
7780 tracked_pipe, pipe);
7781
7782 }
7783
7784 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7785 base.head) {
7786 bool enabled = false;
7787 bool active = false;
7788
7789 DRM_DEBUG_KMS("[CRTC:%d]\n",
7790 crtc->base.base.id);
7791
7792 WARN(crtc->active && !crtc->base.enabled,
7793 "active crtc, but not enabled in sw tracking\n");
7794
7795 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7796 base.head) {
7797 if (encoder->base.crtc != &crtc->base)
7798 continue;
7799 enabled = true;
7800 if (encoder->connectors_active)
7801 active = true;
7802 }
7803 WARN(active != crtc->active,
7804 "crtc's computed active state doesn't match tracked active state "
7805 "(expected %i, found %i)\n", active, crtc->active);
7806 WARN(enabled != crtc->base.enabled,
7807 "crtc's computed enabled state doesn't match tracked enabled state "
7808 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7809
7810 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7811 }
7812}
7813
c0c36b94
CW		 7814int intel_set_mode(struct drm_crtc *crtc,
7815 struct drm_display_mode *mode,
7816 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7817{
7818 struct drm_device *dev = crtc->dev;
dbf2b54e 7819 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7820 struct drm_display_mode *saved_mode, *saved_hwmode;
7821 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7822 struct intel_crtc *intel_crtc;
7823 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7824 int ret = 0;
a6778b3c 7825
3ac18232 7826 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7827 if (!saved_mode)
7828 return -ENOMEM;
3ac18232 7829 saved_hwmode = saved_mode + 1;
a6778b3c 7830
e2e1ed41 7831 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7832 &prepare_pipes, &disable_pipes);
7833
3ac18232
TG		 7834 *saved_hwmode = crtc->hwmode;
7835 *saved_mode = crtc->mode;
a6778b3c 7836
25c5b266
DV		 7837 /* Hack: Because we don't (yet) support global modeset on multiple
7838 * crtcs, we don't keep track of the new mode for more than one crtc.
7839 * Hence simply check whether any bit is set in modeset_pipes in all the
7840 * pieces of code that are not yet converted to deal with mutliple crtcs
7841 * changing their mode at the same time. */
25c5b266 7842 if (modeset_pipes) {
4e53c2e0 7843 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7844 if (IS_ERR(pipe_config)) {
7845 ret = PTR_ERR(pipe_config);
7846 pipe_config = NULL;
7847
3ac18232 7848 goto out;
25c5b266 7849 }
25c5b266 7850 }
a6778b3c 7851
460da916
DV		 7852 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7853 modeset_pipes, prepare_pipes, disable_pipes);
7854
7855 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7856 intel_crtc_disable(&intel_crtc->base);
7857
ea9d758d
DV		 7858 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7859 if (intel_crtc->base.enabled)
7860 dev_priv->display.crtc_disable(&intel_crtc->base);
7861 }
a6778b3c 7862
6c4c86f5
DV		 7863 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7864 * to set it here already despite that we pass it down the callchain.
f6e5b160 7865 */
b8cecdf5 7866 if (modeset_pipes) {
25c5b266 7867 crtc->mode = *mode;
b8cecdf5
DV		 7868 /* mode_set/enable/disable functions rely on a correct pipe
7869 * config. */
7870 to_intel_crtc(crtc)->config = *pipe_config;
7871 }
7758a113 7872
ea9d758d
DV		 7873 /* Only after disabling all output pipelines that will be changed can we
7874 * update the the output configuration. */
7875 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7876
47fab737
DV		 7877 if (dev_priv->display.modeset_global_resources)
7878 dev_priv->display.modeset_global_resources(dev);
7879
a6778b3c
DV		 7880 /* Set up the DPLL and any encoders state that needs to adjust or depend
7881 * on the DPLL.
f6e5b160 7882 */
25c5b266 7883 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 7884 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 7885 x, y, fb);
7886 if (ret)
7887 goto done;
a6778b3c
DV		 7888 }
7889
7890 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7891 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7892 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7893
25c5b266
DV		 7894 if (modeset_pipes) {
7895 /* Store real post-adjustment hardware mode. */
b8cecdf5 7896 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 7897
25c5b266
DV		 7898 /* Calculate and store various constants which
7899 * are later needed by vblank and swap-completion
7900 * timestamping. They are derived from true hwmode.
7901 */
7902 drm_calc_timestamping_constants(crtc);
7903 }
a6778b3c
DV		 7904
7905 /* FIXME: add subpixel order */
7906done:
c0c36b94 7907 if (ret && crtc->enabled) {
3ac18232
TG		 7908 crtc->hwmode = *saved_hwmode;
7909 crtc->mode = *saved_mode;
8af6cf88
DV		 7910 } else {
7911 intel_modeset_check_state(dev);
a6778b3c
DV		 7912 }
7913
3ac18232 7914out:
b8cecdf5 7915 kfree(pipe_config);
3ac18232 7916 kfree(saved_mode);
a6778b3c 7917 return ret;
f6e5b160
CW		 7918}
7919
c0c36b94
CW		 7920void intel_crtc_restore_mode(struct drm_crtc *crtc)
7921{
7922 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7923}
7924
25c5b266
DV		 7925#undef for_each_intel_crtc_masked
7926
d9e55608
DV		 7927static void intel_set_config_free(struct intel_set_config *config)
7928{
7929 if (!config)
7930 return;
7931
1aa4b628
DV		 7932 kfree(config->save_connector_encoders);
7933 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7934 kfree(config);
7935}
7936
85f9eb71
DV		 7937static int intel_set_config_save_state(struct drm_device *dev,
7938 struct intel_set_config *config)
7939{
85f9eb71
DV		 7940 struct drm_encoder *encoder;
7941 struct drm_connector *connector;
7942 int count;
7943
1aa4b628
DV		 7944 config->save_encoder_crtcs =
7945 kcalloc(dev->mode_config.num_encoder,
7946 sizeof(struct drm_crtc *), GFP_KERNEL);
7947 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7948 return -ENOMEM;
7949
1aa4b628
DV		 7950 config->save_connector_encoders =
7951 kcalloc(dev->mode_config.num_connector,
7952 sizeof(struct drm_encoder *), GFP_KERNEL);
7953 if (!config->save_connector_encoders)
85f9eb71
DV		 7954 return -ENOMEM;
7955
7956 /* Copy data. Note that driver private data is not affected.
7957 * Should anything bad happen only the expected state is
7958 * restored, not the drivers personal bookkeeping.
7959 */
85f9eb71
DV		 7960 count = 0;
7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7962 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7963 }
7964
7965 count = 0;
7966 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7967 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7968 }
7969
7970 return 0;
7971}
7972
7973static void intel_set_config_restore_state(struct drm_device *dev,
7974 struct intel_set_config *config)
7975{
9a935856
DV		 7976 struct intel_encoder *encoder;
7977 struct intel_connector *connector;
85f9eb71
DV		 7978 int count;
7979
85f9eb71 7980 count = 0;
9a935856
DV		 7981 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7982 encoder->new_crtc =
7983 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7984 }
7985
7986 count = 0;
9a935856
DV		 7987 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7988 connector->new_encoder =
7989 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7990 }
7991}
7992
5e2b584e
DV		 7993static void
7994intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7995 struct intel_set_config *config)
7996{
7997
7998 /* We should be able to check here if the fb has the same properties
7999 * and then just flip_or_move it */
8000 if (set->crtc->fb != set->fb) {
8001 /* If we have no fb then treat it as a full mode set */
8002 if (set->crtc->fb == NULL) {
8003 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8004 config->mode_changed = true;
8005 } else if (set->fb == NULL) {
8006 config->mode_changed = true;
72f4901e
DV		 8007 } else if (set->fb->pixel_format !=
8008 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8009 config->mode_changed = true;
8010 } else
8011 config->fb_changed = true;
8012 }
8013
835c5873 8014 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8015 config->fb_changed = true;
8016
8017 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8018 DRM_DEBUG_KMS("modes are different, full mode set\n");
8019 drm_mode_debug_printmodeline(&set->crtc->mode);
8020 drm_mode_debug_printmodeline(set->mode);
8021 config->mode_changed = true;
8022 }
8023}
8024
2e431051 8025static int
9a935856
DV		 8026intel_modeset_stage_output_state(struct drm_device *dev,
8027 struct drm_mode_set *set,
8028 struct intel_set_config *config)
50f56119 8029{
85f9eb71 8030 struct drm_crtc *new_crtc;
9a935856
DV		 8031 struct intel_connector *connector;
8032 struct intel_encoder *encoder;
2e431051 8033 int count, ro;
50f56119 8034
9abdda74 8035 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8036 * of connectors. For paranoia, double-check this. */
8037 WARN_ON(!set->fb && (set->num_connectors != 0));
8038 WARN_ON(set->fb && (set->num_connectors == 0));
8039
50f56119 8040 count = 0;
9a935856
DV		 8041 list_for_each_entry(connector, &dev->mode_config.connector_list,
8042 base.head) {
8043 /* Otherwise traverse passed in connector list and get encoders
8044 * for them. */
50f56119 8045 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8046 if (set->connectors[ro] == &connector->base) {
8047 connector->new_encoder = connector->encoder;
50f56119
DV		 8048 break;
8049 }
8050 }
8051
9a935856
DV		 8052 /* If we disable the crtc, disable all its connectors. Also, if
8053 * the connector is on the changing crtc but not on the new
8054 * connector list, disable it. */
8055 if ((!set->fb || ro == set->num_connectors) &&
8056 connector->base.encoder &&
8057 connector->base.encoder->crtc == set->crtc) {
8058 connector->new_encoder = NULL;
8059
8060 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8061 connector->base.base.id,
8062 drm_get_connector_name(&connector->base));
8063 }
8064
8065
8066 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8067 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8068 config->mode_changed = true;
50f56119
DV		 8069 }
8070 }
9a935856 8071 /* connector->new_encoder is now updated for all connectors. */
50f56119 8072
9a935856 8073 /* Update crtc of enabled connectors. */
50f56119 8074 count = 0;
9a935856
DV		 8075 list_for_each_entry(connector, &dev->mode_config.connector_list,
8076 base.head) {
8077 if (!connector->new_encoder)
50f56119
DV		 8078 continue;
8079
9a935856 8080 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8081
8082 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8083 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8084 new_crtc = set->crtc;
8085 }
8086
8087 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8088 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8089 new_crtc)) {
5e2b584e 8090 return -EINVAL;
50f56119 8091 }
9a935856
DV		 8092 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8093
8094 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8095 connector->base.base.id,
8096 drm_get_connector_name(&connector->base),
8097 new_crtc->base.id);
8098 }
8099
8100 /* Check for any encoders that needs to be disabled. */
8101 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8102 base.head) {
8103 list_for_each_entry(connector,
8104 &dev->mode_config.connector_list,
8105 base.head) {
8106 if (connector->new_encoder == encoder) {
8107 WARN_ON(!connector->new_encoder->new_crtc);
8108
8109 goto next_encoder;
8110 }
8111 }
8112 encoder->new_crtc = NULL;
8113next_encoder:
8114 /* Only now check for crtc changes so we don't miss encoders
8115 * that will be disabled. */
8116 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8117 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8118 config->mode_changed = true;
50f56119
DV		 8119 }
8120 }
9a935856 8121 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8122
2e431051
DV		 8123 return 0;
8124}
8125
8126static int intel_crtc_set_config(struct drm_mode_set *set)
8127{
8128 struct drm_device *dev;
2e431051
DV		 8129 struct drm_mode_set save_set;
8130 struct intel_set_config *config;
8131 int ret;
2e431051 8132
8d3e375e
DV		 8133 BUG_ON(!set);
8134 BUG_ON(!set->crtc);
8135 BUG_ON(!set->crtc->helper_private);
2e431051 8136
7e53f3a4
DV		 8137 /* Enforce sane interface api - has been abused by the fb helper. */
8138 BUG_ON(!set->mode && set->fb);
8139 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8140
2e431051
DV		 8141 if (set->fb) {
8142 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8143 set->crtc->base.id, set->fb->base.id,
8144 (int)set->num_connectors, set->x, set->y);
8145 } else {
8146 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8147 }
8148
8149 dev = set->crtc->dev;
8150
8151 ret = -ENOMEM;
8152 config = kzalloc(sizeof(*config), GFP_KERNEL);
8153 if (!config)
8154 goto out_config;
8155
8156 ret = intel_set_config_save_state(dev, config);
8157 if (ret)
8158 goto out_config;
8159
8160 save_set.crtc = set->crtc;
8161 save_set.mode = &set->crtc->mode;
8162 save_set.x = set->crtc->x;
8163 save_set.y = set->crtc->y;
8164 save_set.fb = set->crtc->fb;
8165
8166 /* Compute whether we need a full modeset, only an fb base update or no
8167 * change at all. In the future we might also check whether only the
8168 * mode changed, e.g. for LVDS where we only change the panel fitter in
8169 * such cases. */
8170 intel_set_config_compute_mode_changes(set, config);
8171
9a935856 8172 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8173 if (ret)
8174 goto fail;
8175
5e2b584e 8176 if (config->mode_changed) {
87f1faa6 8177 if (set->mode) {
50f56119
DV		 8178 DRM_DEBUG_KMS("attempting to set mode from"
8179 " userspace\n");
8180 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8181 }
8182
c0c36b94
CW		 8183 ret = intel_set_mode(set->crtc, set->mode,
8184 set->x, set->y, set->fb);
8185 if (ret) {
8186 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8187 set->crtc->base.id, ret);
87f1faa6
DV		 8188 goto fail;
8189 }
5e2b584e 8190 } else if (config->fb_changed) {
4878cae2
VS		 8191 intel_crtc_wait_for_pending_flips(set->crtc);
8192
4f660f49 8193 ret = intel_pipe_set_base(set->crtc,
94352cf9 8194 set->x, set->y, set->fb);
50f56119
DV		 8195 }
8196
d9e55608
DV		 8197 intel_set_config_free(config);
8198
50f56119
DV		 8199 return 0;
8200
8201fail:
85f9eb71 8202 intel_set_config_restore_state(dev, config);
50f56119
DV		 8203
8204 /* Try to restore the config */
5e2b584e 8205 if (config->mode_changed &&
c0c36b94
CW		 8206 intel_set_mode(save_set.crtc, save_set.mode,
8207 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8208 DRM_ERROR("failed to restore config after modeset failure\n");
8209
d9e55608
DV		 8210out_config:
8211 intel_set_config_free(config);
50f56119
DV		 8212 return ret;
8213}
f6e5b160
CW		 8214
8215static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8216 .cursor_set = intel_crtc_cursor_set,
8217 .cursor_move = intel_crtc_cursor_move,
8218 .gamma_set = intel_crtc_gamma_set,
50f56119 8219 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8220 .destroy = intel_crtc_destroy,
8221 .page_flip = intel_crtc_page_flip,
8222};
8223
79f689aa
PZ		 8224static void intel_cpu_pll_init(struct drm_device *dev)
8225{
affa9354 8226 if (HAS_DDI(dev))
79f689aa
PZ		 8227 intel_ddi_pll_init(dev);
8228}
8229
ee7b9f93
JB		 8230static void intel_pch_pll_init(struct drm_device *dev)
8231{
8232 drm_i915_private_t *dev_priv = dev->dev_private;
8233 int i;
8234
8235 if (dev_priv->num_pch_pll == 0) {
8236 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8237 return;
8238 }
8239
8240 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8241 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8242 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8243 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8244 }
8245}
8246
b358d0a6 8247static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8248{
22fd0fab 8249 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8250 struct intel_crtc *intel_crtc;
8251 int i;
8252
8253 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8254 if (intel_crtc == NULL)
8255 return;
8256
8257 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8258
8259 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8260 for (i = 0; i < 256; i++) {
8261 intel_crtc->lut_r[i] = i;
8262 intel_crtc->lut_g[i] = i;
8263 intel_crtc->lut_b[i] = i;
8264 }
8265
80824003
JB		 8266 /* Swap pipes & planes for FBC on pre-965 */
8267 intel_crtc->pipe = pipe;
8268 intel_crtc->plane = pipe;
a5c961d1 8269 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8270 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8271 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8272 intel_crtc->plane = !pipe;
80824003
JB		 8273 }
8274
22fd0fab
JB		 8275 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8276 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8277 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8278 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8279
79e53945 8280 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8281}
8282
08d7b3d1 8283int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8284 struct drm_file *file)
08d7b3d1 8285{
08d7b3d1 8286 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8287 struct drm_mode_object *drmmode_obj;
8288 struct intel_crtc *crtc;
08d7b3d1 8289
1cff8f6b
DV		 8290 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8291 return -ENODEV;
08d7b3d1 8292
c05422d5
DV		 8293 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8294 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8295
c05422d5 8296 if (!drmmode_obj) {
08d7b3d1
CW		 8297 DRM_ERROR("no such CRTC id\n");
8298 return -EINVAL;
8299 }
8300
c05422d5
DV		 8301 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8302 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8303
c05422d5 8304 return 0;
08d7b3d1
CW		 8305}
8306
66a9278e 8307static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8308{
66a9278e
DV		 8309 struct drm_device *dev = encoder->base.dev;
8310 struct intel_encoder *source_encoder;
79e53945 8311 int index_mask = 0;
79e53945
JB		 8312 int entry = 0;
8313
66a9278e
DV		 8314 list_for_each_entry(source_encoder,
8315 &dev->mode_config.encoder_list, base.head) {
8316
8317 if (encoder == source_encoder)
79e53945 8318 index_mask |= (1 << entry);
66a9278e
DV		 8319
8320 /* Intel hw has only one MUX where enocoders could be cloned. */
8321 if (encoder->cloneable && source_encoder->cloneable)
8322 index_mask |= (1 << entry);
8323
79e53945
JB		 8324 entry++;
8325 }
4ef69c7a 8326
79e53945
JB		 8327 return index_mask;
8328}
8329
4d302442
CW		 8330static bool has_edp_a(struct drm_device *dev)
8331{
8332 struct drm_i915_private *dev_priv = dev->dev_private;
8333
8334 if (!IS_MOBILE(dev))
8335 return false;
8336
8337 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8338 return false;
8339
8340 if (IS_GEN5(dev) &&
8341 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8342 return false;
8343
8344 return true;
8345}
8346
79e53945
JB		 8347static void intel_setup_outputs(struct drm_device *dev)
8348{
725e30ad 8349 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8350 struct intel_encoder *encoder;
cb0953d7 8351 bool dpd_is_edp = false;
f3cfcba6 8352 bool has_lvds;
79e53945 8353
f3cfcba6 8354 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8355 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8356 /* disable the panel fitter on everything but LVDS */
8357 I915_WRITE(PFIT_CONTROL, 0);
8358 }
79e53945 8359
affa9354 8360 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8361 intel_crt_init(dev);
cb0953d7 8362
affa9354 8363 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8364 int found;
8365
8366 /* Haswell uses DDI functions to detect digital outputs */
8367 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8368 /* DDI A only supports eDP */
8369 if (found)
8370 intel_ddi_init(dev, PORT_A);
8371
8372 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8373 * register */
8374 found = I915_READ(SFUSE_STRAP);
8375
8376 if (found & SFUSE_STRAP_DDIB_DETECTED)
8377 intel_ddi_init(dev, PORT_B);
8378 if (found & SFUSE_STRAP_DDIC_DETECTED)
8379 intel_ddi_init(dev, PORT_C);
8380 if (found & SFUSE_STRAP_DDID_DETECTED)
8381 intel_ddi_init(dev, PORT_D);
8382 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8383 int found;
270b3042
DV		 8384 dpd_is_edp = intel_dpd_is_edp(dev);
8385
8386 if (has_edp_a(dev))
8387 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8388
dc0fa718 8389 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8390 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8391 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8392 if (!found)
e2debe91 8393 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8394 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8395 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8396 }
8397
dc0fa718 8398 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8399 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8400
dc0fa718 8401 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8402 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8403
5eb08b69 8404 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8405 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8406
270b3042 8407 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8408 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8409 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8410 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8411 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8412 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8413
dc0fa718 8414 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8415 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8416 PORT_B);
67cfc203
VS		 8417 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8418 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8419 }
103a196f 8420 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8421 bool found = false;
7d57382e 8422
e2debe91 8423 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8424 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8425 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8426 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8427 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8428 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8429 }
27185ae1 8430
b01f2c3a
JB		 8431 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8432 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8433 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8434 }
725e30ad 8435 }
13520b05
KH		 8436
8437 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8438
e2debe91 8439 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8440 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8441 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8442 }
27185ae1 8443
e2debe91 8444 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8445
b01f2c3a
JB		 8446 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8447 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8448 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8449 }
8450 if (SUPPORTS_INTEGRATED_DP(dev)) {
8451 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8452 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8453 }
725e30ad 8454 }
27185ae1 8455
b01f2c3a
JB		 8456 if (SUPPORTS_INTEGRATED_DP(dev) &&
8457 (I915_READ(DP_D) & DP_DETECTED)) {
8458 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8459 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8460 }
bad720ff 8461 } else if (IS_GEN2(dev))
79e53945
JB		 8462 intel_dvo_init(dev);
8463
103a196f 8464 if (SUPPORTS_TV(dev))
79e53945
JB		 8465 intel_tv_init(dev);
8466
4ef69c7a
CW		 8467 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8468 encoder->base.possible_crtcs = encoder->crtc_mask;
8469 encoder->base.possible_clones =
66a9278e 8470 intel_encoder_clones(encoder);
79e53945 8471 }
47356eb6 8472
dde86e2d 8473 intel_init_pch_refclk(dev);
270b3042
DV		 8474
8475 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8476}
8477
8478static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8479{
8480 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8481
8482 drm_framebuffer_cleanup(fb);
05394f39 8483 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8484
8485 kfree(intel_fb);
8486}
8487
8488static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8489 struct drm_file *file,
79e53945
JB		 8490 unsigned int *handle)
8491{
8492 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8493 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8494
05394f39 8495 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8496}
8497
8498static const struct drm_framebuffer_funcs intel_fb_funcs = {
8499 .destroy = intel_user_framebuffer_destroy,
8500 .create_handle = intel_user_framebuffer_create_handle,
8501};
8502
38651674
DA		 8503int intel_framebuffer_init(struct drm_device *dev,
8504 struct intel_framebuffer *intel_fb,
308e5bcb 8505 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8506 struct drm_i915_gem_object *obj)
79e53945 8507{
79e53945
JB		 8508 int ret;
8509
c16ed4be
CW		 8510 if (obj->tiling_mode == I915_TILING_Y) {
8511 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8512 return -EINVAL;
c16ed4be 8513 }
57cd6508 8514
c16ed4be
CW		 8515 if (mode_cmd->pitches[0] & 63) {
8516 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8517 mode_cmd->pitches[0]);
57cd6508 8518 return -EINVAL;
c16ed4be 8519 }
57cd6508 8520
5d7bd705 8521 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8522 if (mode_cmd->pitches[0] > 32768) {
8523 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8524 mode_cmd->pitches[0]);
5d7bd705 8525 return -EINVAL;
c16ed4be 8526 }
5d7bd705
VS		 8527
8528 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8529 mode_cmd->pitches[0] != obj->stride) {
8530 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8531 mode_cmd->pitches[0], obj->stride);
5d7bd705 8532 return -EINVAL;
c16ed4be 8533 }
5d7bd705 8534
57779d06 8535 /* Reject formats not supported by any plane early. */
308e5bcb 8536 switch (mode_cmd->pixel_format) {
57779d06 8537 case DRM_FORMAT_C8:
04b3924d
VS		 8538 case DRM_FORMAT_RGB565:
8539 case DRM_FORMAT_XRGB8888:
8540 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8541 break;
8542 case DRM_FORMAT_XRGB1555:
8543 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8544 if (INTEL_INFO(dev)->gen > 3) {
8545 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8546 return -EINVAL;
c16ed4be 8547 }
57779d06
VS		 8548 break;
8549 case DRM_FORMAT_XBGR8888:
8550 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8551 case DRM_FORMAT_XRGB2101010:
8552 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8553 case DRM_FORMAT_XBGR2101010:
8554 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8555 if (INTEL_INFO(dev)->gen < 4) {
8556 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8557 return -EINVAL;
c16ed4be 8558 }
b5626747 8559 break;
04b3924d
VS		 8560 case DRM_FORMAT_YUYV:
8561 case DRM_FORMAT_UYVY:
8562 case DRM_FORMAT_YVYU:
8563 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8564 if (INTEL_INFO(dev)->gen < 5) {
8565 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8566 return -EINVAL;
c16ed4be 8567 }
57cd6508
CW		 8568 break;
8569 default:
c16ed4be 8570 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8571 return -EINVAL;
8572 }
8573
90f9a336
VS		 8574 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8575 if (mode_cmd->offsets[0] != 0)
8576 return -EINVAL;
8577
c7d73f6a
DV		 8578 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8579 intel_fb->obj = obj;
8580
79e53945
JB		 8581 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8582 if (ret) {
8583 DRM_ERROR("framebuffer init failed %d\n", ret);
8584 return ret;
8585 }
8586
79e53945
JB		 8587 return 0;
8588}
8589
79e53945
JB		 8590static struct drm_framebuffer *
8591intel_user_framebuffer_create(struct drm_device *dev,
8592 struct drm_file *filp,
308e5bcb 8593 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8594{
05394f39 8595 struct drm_i915_gem_object *obj;
79e53945 8596
308e5bcb
JB		 8597 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8598 mode_cmd->handles[0]));
c8725226 8599 if (&obj->base == NULL)
cce13ff7 8600 return ERR_PTR(-ENOENT);
79e53945 8601
d2dff872 8602 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8603}
8604
79e53945 8605static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8606 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8607 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8608};
8609
e70236a8
JB		 8610/* Set up chip specific display functions */
8611static void intel_init_display(struct drm_device *dev)
8612{
8613 struct drm_i915_private *dev_priv = dev->dev_private;
8614
affa9354 8615 if (HAS_DDI(dev)) {
09b4ddf9 8616 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8617 dev_priv->display.crtc_enable = haswell_crtc_enable;
8618 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8619 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8620 dev_priv->display.update_plane = ironlake_update_plane;
8621 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8622 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8623 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8624 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8625 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8626 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8627 } else {
f564048e 8628 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8629 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8630 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8631 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8632 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8633 }
e70236a8 8634
e70236a8 8635 /* Returns the core display clock speed */
25eb05fc
JB		 8636 if (IS_VALLEYVIEW(dev))
8637 dev_priv->display.get_display_clock_speed =
8638 valleyview_get_display_clock_speed;
8639 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8640 dev_priv->display.get_display_clock_speed =
8641 i945_get_display_clock_speed;
8642 else if (IS_I915G(dev))
8643 dev_priv->display.get_display_clock_speed =
8644 i915_get_display_clock_speed;
f2b115e6 8645 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8646 dev_priv->display.get_display_clock_speed =
8647 i9xx_misc_get_display_clock_speed;
8648 else if (IS_I915GM(dev))
8649 dev_priv->display.get_display_clock_speed =
8650 i915gm_get_display_clock_speed;
8651 else if (IS_I865G(dev))
8652 dev_priv->display.get_display_clock_speed =
8653 i865_get_display_clock_speed;
f0f8a9ce 8654 else if (IS_I85X(dev))
e70236a8
JB		 8655 dev_priv->display.get_display_clock_speed =
8656 i855_get_display_clock_speed;
8657 else /* 852, 830 */
8658 dev_priv->display.get_display_clock_speed =
8659 i830_get_display_clock_speed;
8660
7f8a8569 8661 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8662 if (IS_GEN5(dev)) {
674cf967 8663 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8664 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8665 } else if (IS_GEN6(dev)) {
674cf967 8666 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8667 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8668 } else if (IS_IVYBRIDGE(dev)) {
8669 /* FIXME: detect B0+ stepping and use auto training */
8670 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8671 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8672 dev_priv->display.modeset_global_resources =
8673 ivb_modeset_global_resources;
c82e4d26
ED		 8674 } else if (IS_HASWELL(dev)) {
8675 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8676 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8677 dev_priv->display.modeset_global_resources =
8678 haswell_modeset_global_resources;
a0e63c22 8679 }
6067aaea 8680 } else if (IS_G4X(dev)) {
e0dac65e 8681 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8682 }
8c9f3aaf
JB		 8683
8684 /* Default just returns -ENODEV to indicate unsupported */
8685 dev_priv->display.queue_flip = intel_default_queue_flip;
8686
8687 switch (INTEL_INFO(dev)->gen) {
8688 case 2:
8689 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8690 break;
8691
8692 case 3:
8693 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8694 break;
8695
8696 case 4:
8697 case 5:
8698 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8699 break;
8700
8701 case 6:
8702 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8703 break;
7c9017e5
JB		 8704 case 7:
8705 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8706 break;
8c9f3aaf 8707 }
e70236a8
JB		 8708}
8709
b690e96c
JB		 8710/*
8711 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8712 * resume, or other times. This quirk makes sure that's the case for
8713 * affected systems.
8714 */
0206e353 8715static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8716{
8717 struct drm_i915_private *dev_priv = dev->dev_private;
8718
8719 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8720 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8721}
8722
435793df
KP		 8723/*
8724 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8725 */
8726static void quirk_ssc_force_disable(struct drm_device *dev)
8727{
8728 struct drm_i915_private *dev_priv = dev->dev_private;
8729 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8730 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8731}
8732
4dca20ef 8733/*
5a15ab5b
CE		 8734 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8735 * brightness value
4dca20ef
CE		 8736 */
8737static void quirk_invert_brightness(struct drm_device *dev)
8738{
8739 struct drm_i915_private *dev_priv = dev->dev_private;
8740 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8741 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8742}
8743
b690e96c
JB		 8744struct intel_quirk {
8745 int device;
8746 int subsystem_vendor;
8747 int subsystem_device;
8748 void (*hook)(struct drm_device *dev);
8749};
8750
5f85f176
EE		 8751/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8752struct intel_dmi_quirk {
8753 void (*hook)(struct drm_device *dev);
8754 const struct dmi_system_id (*dmi_id_list)[];
8755};
8756
8757static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8758{
8759 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8760 return 1;
8761}
8762
8763static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8764 {
8765 .dmi_id_list = &(const struct dmi_system_id[]) {
8766 {
8767 .callback = intel_dmi_reverse_brightness,
8768 .ident = "NCR Corporation",
8769 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8770 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8771 },
8772 },
8773 { } /* terminating entry */
8774 },
8775 .hook = quirk_invert_brightness,
8776 },
8777};
8778
c43b5634 8779static struct intel_quirk intel_quirks[] = {
b690e96c 8780 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8781 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8782
b690e96c
JB		 8783 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8784 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8785
b690e96c
JB		 8786 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8787 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8788
ccd0d36e 8789 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8790 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8791 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8792
8793 /* Lenovo U160 cannot use SSC on LVDS */
8794 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8795
8796 /* Sony Vaio Y cannot use SSC on LVDS */
8797 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8798
8799 /* Acer Aspire 5734Z must invert backlight brightness */
8800 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8801
8802 /* Acer/eMachines G725 */
8803 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8804
8805 /* Acer/eMachines e725 */
8806 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8807
8808 /* Acer/Packard Bell NCL20 */
8809 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8810
8811 /* Acer Aspire 4736Z */
8812 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8813};
8814
8815static void intel_init_quirks(struct drm_device *dev)
8816{
8817 struct pci_dev *d = dev->pdev;
8818 int i;
8819
8820 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8821 struct intel_quirk *q = &intel_quirks[i];
8822
8823 if (d->device == q->device &&
8824 (d->subsystem_vendor == q->subsystem_vendor ||
8825 q->subsystem_vendor == PCI_ANY_ID) &&
8826 (d->subsystem_device == q->subsystem_device ||
8827 q->subsystem_device == PCI_ANY_ID))
8828 q->hook(dev);
8829 }
5f85f176
EE		 8830 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8831 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8832 intel_dmi_quirks[i].hook(dev);
8833 }
b690e96c
JB		 8834}
8835
9cce37f4
JB		 8836/* Disable the VGA plane that we never use */
8837static void i915_disable_vga(struct drm_device *dev)
8838{
8839 struct drm_i915_private *dev_priv = dev->dev_private;
8840 u8 sr1;
766aa1c4 8841 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8842
8843 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8844 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8845 sr1 = inb(VGA_SR_DATA);
8846 outb(sr1 | 1<<5, VGA_SR_DATA);
8847 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8848 udelay(300);
8849
8850 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8851 POSTING_READ(vga_reg);
8852}
8853
f817586c
DV		 8854void intel_modeset_init_hw(struct drm_device *dev)
8855{
fa42e23c 8856 intel_init_power_well(dev);
0232e927 8857
a8f78b58
ED		 8858 intel_prepare_ddi(dev);
8859
f817586c
DV		 8860 intel_init_clock_gating(dev);
8861
79f5b2c7 8862 mutex_lock(&dev->struct_mutex);
8090c6b9 8863 intel_enable_gt_powersave(dev);
79f5b2c7 8864 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8865}
8866
79e53945
JB		 8867void intel_modeset_init(struct drm_device *dev)
8868{
652c393a 8869 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 8870 int i, j, ret;
79e53945
JB		 8871
8872 drm_mode_config_init(dev);
8873
8874 dev->mode_config.min_width = 0;
8875 dev->mode_config.min_height = 0;
8876
019d96cb
DA		 8877 dev->mode_config.preferred_depth = 24;
8878 dev->mode_config.prefer_shadow = 1;
8879
e6ecefaa 8880 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8881
b690e96c
JB		 8882 intel_init_quirks(dev);
8883
1fa61106
ED		 8884 intel_init_pm(dev);
8885
e70236a8
JB		 8886 intel_init_display(dev);
8887
a6c45cf0
CW		 8888 if (IS_GEN2(dev)) {
8889 dev->mode_config.max_width = 2048;
8890 dev->mode_config.max_height = 2048;
8891 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8892 dev->mode_config.max_width = 4096;
8893 dev->mode_config.max_height = 4096;
79e53945 8894 } else {
a6c45cf0
CW		 8895 dev->mode_config.max_width = 8192;
8896 dev->mode_config.max_height = 8192;
79e53945 8897 }
5d4545ae 8898 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8899
28c97730 8900 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 8901 INTEL_INFO(dev)->num_pipes,
8902 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 8903
7eb552ae 8904 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 8905 intel_crtc_init(dev, i);
7f1f3851
JB		 8906 for (j = 0; j < dev_priv->num_plane; j++) {
8907 ret = intel_plane_init(dev, i, j);
8908 if (ret)
8909 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
8910 i, j, ret);
8911 }
79e53945
JB		 8912 }
8913
79f689aa 8914 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8915 intel_pch_pll_init(dev);
8916
9cce37f4
JB		 8917 /* Just disable it once at startup */
8918 i915_disable_vga(dev);
79e53945 8919 intel_setup_outputs(dev);
11be49eb
CW		 8920
8921 /* Just in case the BIOS is doing something questionable. */
8922 intel_disable_fbc(dev);
2c7111db
CW		 8923}
8924
24929352
DV		 8925static void
8926intel_connector_break_all_links(struct intel_connector *connector)
8927{
8928 connector->base.dpms = DRM_MODE_DPMS_OFF;
8929 connector->base.encoder = NULL;
8930 connector->encoder->connectors_active = false;
8931 connector->encoder->base.crtc = NULL;
8932}
8933
7fad798e
DV		 8934static void intel_enable_pipe_a(struct drm_device *dev)
8935{
8936 struct intel_connector *connector;
8937 struct drm_connector *crt = NULL;
8938 struct intel_load_detect_pipe load_detect_temp;
8939
8940 /* We can't just switch on the pipe A, we need to set things up with a
8941 * proper mode and output configuration. As a gross hack, enable pipe A
8942 * by enabling the load detect pipe once. */
8943 list_for_each_entry(connector,
8944 &dev->mode_config.connector_list,
8945 base.head) {
8946 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8947 crt = &connector->base;
8948 break;
8949 }
8950 }
8951
8952 if (!crt)
8953 return;
8954
8955 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8956 intel_release_load_detect_pipe(crt, &load_detect_temp);
8957
652c393a 8958
7fad798e
DV		 8959}
8960
fa555837
DV		 8961static bool
8962intel_check_plane_mapping(struct intel_crtc *crtc)
8963{
7eb552ae
BW		 8964 struct drm_device *dev = crtc->base.dev;
8965 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 8966 u32 reg, val;
8967
7eb552ae 8968 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 8969 return true;
8970
8971 reg = DSPCNTR(!crtc->plane);
8972 val = I915_READ(reg);
8973
8974 if ((val & DISPLAY_PLANE_ENABLE) &&
8975 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8976 return false;
8977
8978 return true;
8979}
8980
24929352
DV		 8981static void intel_sanitize_crtc(struct intel_crtc *crtc)
8982{
8983 struct drm_device *dev = crtc->base.dev;
8984 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8985 u32 reg;
24929352 8986
24929352 8987 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8988 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8989 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8990
8991 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8992 * disable the crtc (and hence change the state) if it is wrong. Note
8993 * that gen4+ has a fixed plane -> pipe mapping. */
8994 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8995 struct intel_connector *connector;
8996 bool plane;
8997
24929352
DV		 8998 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8999 crtc->base.base.id);
9000
9001 /* Pipe has the wrong plane attached and the plane is active.
9002 * Temporarily change the plane mapping and disable everything
9003 * ... */
9004 plane = crtc->plane;
9005 crtc->plane = !plane;
9006 dev_priv->display.crtc_disable(&crtc->base);
9007 crtc->plane = plane;
9008
9009 /* ... and break all links. */
9010 list_for_each_entry(connector, &dev->mode_config.connector_list,
9011 base.head) {
9012 if (connector->encoder->base.crtc != &crtc->base)
9013 continue;
9014
9015 intel_connector_break_all_links(connector);
9016 }
9017
9018 WARN_ON(crtc->active);
9019 crtc->base.enabled = false;
9020 }
24929352 9021
7fad798e
DV		 9022 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9023 crtc->pipe == PIPE_A && !crtc->active) {
9024 /* BIOS forgot to enable pipe A, this mostly happens after
9025 * resume. Force-enable the pipe to fix this, the update_dpms
9026 * call below we restore the pipe to the right state, but leave
9027 * the required bits on. */
9028 intel_enable_pipe_a(dev);
9029 }
9030
24929352
DV		 9031 /* Adjust the state of the output pipe according to whether we
9032 * have active connectors/encoders. */
9033 intel_crtc_update_dpms(&crtc->base);
9034
9035 if (crtc->active != crtc->base.enabled) {
9036 struct intel_encoder *encoder;
9037
9038 /* This can happen either due to bugs in the get_hw_state
9039 * functions or because the pipe is force-enabled due to the
9040 * pipe A quirk. */
9041 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9042 crtc->base.base.id,
9043 crtc->base.enabled ? "enabled" : "disabled",
9044 crtc->active ? "enabled" : "disabled");
9045
9046 crtc->base.enabled = crtc->active;
9047
9048 /* Because we only establish the connector -> encoder ->
9049 * crtc links if something is active, this means the
9050 * crtc is now deactivated. Break the links. connector
9051 * -> encoder links are only establish when things are
9052 * actually up, hence no need to break them. */
9053 WARN_ON(crtc->active);
9054
9055 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9056 WARN_ON(encoder->connectors_active);
9057 encoder->base.crtc = NULL;
9058 }
9059 }
9060}
9061
9062static void intel_sanitize_encoder(struct intel_encoder *encoder)
9063{
9064 struct intel_connector *connector;
9065 struct drm_device *dev = encoder->base.dev;
9066
9067 /* We need to check both for a crtc link (meaning that the
9068 * encoder is active and trying to read from a pipe) and the
9069 * pipe itself being active. */
9070 bool has_active_crtc = encoder->base.crtc &&
9071 to_intel_crtc(encoder->base.crtc)->active;
9072
9073 if (encoder->connectors_active && !has_active_crtc) {
9074 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9075 encoder->base.base.id,
9076 drm_get_encoder_name(&encoder->base));
9077
9078 /* Connector is active, but has no active pipe. This is
9079 * fallout from our resume register restoring. Disable
9080 * the encoder manually again. */
9081 if (encoder->base.crtc) {
9082 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9083 encoder->base.base.id,
9084 drm_get_encoder_name(&encoder->base));
9085 encoder->disable(encoder);
9086 }
9087
9088 /* Inconsistent output/port/pipe state happens presumably due to
9089 * a bug in one of the get_hw_state functions. Or someplace else
9090 * in our code, like the register restore mess on resume. Clamp
9091 * things to off as a safer default. */
9092 list_for_each_entry(connector,
9093 &dev->mode_config.connector_list,
9094 base.head) {
9095 if (connector->encoder != encoder)
9096 continue;
9097
9098 intel_connector_break_all_links(connector);
9099 }
9100 }
9101 /* Enabled encoders without active connectors will be fixed in
9102 * the crtc fixup. */
9103}
9104
44cec740 9105void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9106{
9107 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9108 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9109
9110 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9111 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9112 i915_disable_vga(dev);
0fde901f
KM		 9113 }
9114}
9115
24929352
DV		 9116/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9117 * and i915 state tracking structures. */
45e2b5f6
DV		 9118void intel_modeset_setup_hw_state(struct drm_device *dev,
9119 bool force_restore)
24929352
DV		 9120{
9121 struct drm_i915_private *dev_priv = dev->dev_private;
9122 enum pipe pipe;
9123 u32 tmp;
b5644d05 9124 struct drm_plane *plane;
24929352
DV		 9125 struct intel_crtc *crtc;
9126 struct intel_encoder *encoder;
9127 struct intel_connector *connector;
9128
affa9354 9129 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9130 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9131
9132 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9133 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9134 case TRANS_DDI_EDP_INPUT_A_ON:
9135 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9136 pipe = PIPE_A;
9137 break;
9138 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9139 pipe = PIPE_B;
9140 break;
9141 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9142 pipe = PIPE_C;
9143 break;
aaa148ec
DL		 9144 default:
9145 /* A bogus value has been programmed, disable
9146 * the transcoder */
9147 WARN(1, "Bogus eDP source %08x\n", tmp);
9148 intel_ddi_disable_transcoder_func(dev_priv,
9149 TRANSCODER_EDP);
9150 goto setup_pipes;
e28d54cb
PZ		 9151 }
9152
9153 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9154 crtc->cpu_transcoder = TRANSCODER_EDP;
9155
9156 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9157 pipe_name(pipe));
9158 }
9159 }
9160
aaa148ec 9161setup_pipes:
24929352
DV		 9162 for_each_pipe(pipe) {
9163 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9164
702e7a56 9165 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9166 if (tmp & PIPECONF_ENABLE)
9167 crtc->active = true;
9168 else
9169 crtc->active = false;
9170
9171 crtc->base.enabled = crtc->active;
9172
9173 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9174 crtc->base.base.id,
9175 crtc->active ? "enabled" : "disabled");
9176 }
9177
affa9354 9178 if (HAS_DDI(dev))
6441ab5f
PZ		 9179 intel_ddi_setup_hw_pll_state(dev);
9180
24929352
DV		 9181 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9182 base.head) {
9183 pipe = 0;
9184
9185 if (encoder->get_hw_state(encoder, &pipe)) {
9186 encoder->base.crtc =
9187 dev_priv->pipe_to_crtc_mapping[pipe];
9188 } else {
9189 encoder->base.crtc = NULL;
9190 }
9191
9192 encoder->connectors_active = false;
9193 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9194 encoder->base.base.id,
9195 drm_get_encoder_name(&encoder->base),
9196 encoder->base.crtc ? "enabled" : "disabled",
9197 pipe);
9198 }
9199
9200 list_for_each_entry(connector, &dev->mode_config.connector_list,
9201 base.head) {
9202 if (connector->get_hw_state(connector)) {
9203 connector->base.dpms = DRM_MODE_DPMS_ON;
9204 connector->encoder->connectors_active = true;
9205 connector->base.encoder = &connector->encoder->base;
9206 } else {
9207 connector->base.dpms = DRM_MODE_DPMS_OFF;
9208 connector->base.encoder = NULL;
9209 }
9210 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9211 connector->base.base.id,
9212 drm_get_connector_name(&connector->base),
9213 connector->base.encoder ? "enabled" : "disabled");
9214 }
9215
9216 /* HW state is read out, now we need to sanitize this mess. */
9217 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9218 base.head) {
9219 intel_sanitize_encoder(encoder);
9220 }
9221
9222 for_each_pipe(pipe) {
9223 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9224 intel_sanitize_crtc(crtc);
9225 }
9a935856 9226
45e2b5f6
DV		 9227 if (force_restore) {
9228 for_each_pipe(pipe) {
b5644d05
JB		 9229 struct drm_crtc *crtc =
9230 dev_priv->pipe_to_crtc_mapping[pipe];
9231 intel_crtc_restore_mode(crtc);
45e2b5f6 9232 }
b5644d05
JB		 9233 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9234 intel_plane_restore(plane);
0fde901f
KM		 9235
9236 i915_redisable_vga(dev);
45e2b5f6
DV		 9237 } else {
9238 intel_modeset_update_staged_output_state(dev);
9239 }
8af6cf88
DV		 9240
9241 intel_modeset_check_state(dev);
2e938892
DV		 9242
9243 drm_mode_config_reset(dev);
2c7111db
CW		 9244}
9245
9246void intel_modeset_gem_init(struct drm_device *dev)
9247{
1833b134 9248 intel_modeset_init_hw(dev);
02e792fb
DV		 9249
9250 intel_setup_overlay(dev);
24929352 9251
45e2b5f6 9252 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9253}
9254
9255void intel_modeset_cleanup(struct drm_device *dev)
9256{
652c393a
JB		 9257 struct drm_i915_private *dev_priv = dev->dev_private;
9258 struct drm_crtc *crtc;
9259 struct intel_crtc *intel_crtc;
9260
f87ea761 9261 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9262 mutex_lock(&dev->struct_mutex);
9263
723bfd70
JB		 9264 intel_unregister_dsm_handler();
9265
9266
652c393a
JB		 9267 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9268 /* Skip inactive CRTCs */
9269 if (!crtc->fb)
9270 continue;
9271
9272 intel_crtc = to_intel_crtc(crtc);
3dec0095 9273 intel_increase_pllclock(crtc);
652c393a
JB		 9274 }
9275
973d04f9 9276 intel_disable_fbc(dev);
e70236a8 9277
8090c6b9 9278 intel_disable_gt_powersave(dev);
0cdab21f 9279
930ebb46
DV		 9280 ironlake_teardown_rc6(dev);
9281
57f350b6
JB		 9282 if (IS_VALLEYVIEW(dev))
9283 vlv_init_dpio(dev);
9284
69341a5e
KH		 9285 mutex_unlock(&dev->struct_mutex);
9286
6c0d9350
DV		 9287 /* Disable the irq before mode object teardown, for the irq might
9288 * enqueue unpin/hotplug work. */
9289 drm_irq_uninstall(dev);
9290 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9291 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9292
1630fe75
CW		 9293 /* flush any delayed tasks or pending work */
9294 flush_scheduled_work();
9295
79e53945 9296 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9297
9298 intel_cleanup_overlay(dev);
79e53945
JB		 9299}
9300
f1c79df3
ZW		 9301/*
9302 * Return which encoder is currently attached for connector.
9303 */
df0e9248 9304struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9305{
df0e9248
CW		 9306 return &intel_attached_encoder(connector)->base;
9307}
f1c79df3 9308
df0e9248
CW		 9309void intel_connector_attach_encoder(struct intel_connector *connector,
9310 struct intel_encoder *encoder)
9311{
9312 connector->encoder = encoder;
9313 drm_mode_connector_attach_encoder(&connector->base,
9314 &encoder->base);
79e53945 9315}
28d52043
DA		 9316
9317/*
9318 * set vga decode state - true == enable VGA decode
9319 */
9320int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9321{
9322 struct drm_i915_private *dev_priv = dev->dev_private;
9323 u16 gmch_ctrl;
9324
9325 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9326 if (state)
9327 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9328 else
9329 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9330 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9331 return 0;
9332}
c4a1d9e4
CW		 9333
9334#ifdef CONFIG_DEBUG_FS
9335#include <linux/seq_file.h>
9336
9337struct intel_display_error_state {
9338 struct intel_cursor_error_state {
9339 u32 control;
9340 u32 position;
9341 u32 base;
9342 u32 size;
52331309 9343 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9344
9345 struct intel_pipe_error_state {
9346 u32 conf;
9347 u32 source;
9348
9349 u32 htotal;
9350 u32 hblank;
9351 u32 hsync;
9352 u32 vtotal;
9353 u32 vblank;
9354 u32 vsync;
52331309 9355 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9356
9357 struct intel_plane_error_state {
9358 u32 control;
9359 u32 stride;
9360 u32 size;
9361 u32 pos;
9362 u32 addr;
9363 u32 surface;
9364 u32 tile_offset;
52331309 9365 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9366};
9367
9368struct intel_display_error_state *
9369intel_display_capture_error_state(struct drm_device *dev)
9370{
0206e353 9371 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9372 struct intel_display_error_state *error;
702e7a56 9373 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9374 int i;
9375
9376 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9377 if (error == NULL)
9378 return NULL;
9379
52331309 9380 for_each_pipe(i) {
702e7a56
PZ		 9381 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9382
a18c4c3d
PZ		 9383 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9384 error->cursor[i].control = I915_READ(CURCNTR(i));
9385 error->cursor[i].position = I915_READ(CURPOS(i));
9386 error->cursor[i].base = I915_READ(CURBASE(i));
9387 } else {
9388 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9389 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9390 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9391 }
c4a1d9e4
CW		 9392
9393 error->plane[i].control = I915_READ(DSPCNTR(i));
9394 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9395 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9396 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9397 error->plane[i].pos = I915_READ(DSPPOS(i));
9398 }
ca291363
PZ		 9399 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9400 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9401 if (INTEL_INFO(dev)->gen >= 4) {
9402 error->plane[i].surface = I915_READ(DSPSURF(i));
9403 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9404 }
9405
702e7a56 9406 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9407 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9408 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9409 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9410 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9411 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9412 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9413 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9414 }
9415
9416 return error;
9417}
9418
9419void
9420intel_display_print_error_state(struct seq_file *m,
9421 struct drm_device *dev,
9422 struct intel_display_error_state *error)
9423{
9424 int i;
9425
7eb552ae 9426 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9427 for_each_pipe(i) {
c4a1d9e4
CW		 9428 seq_printf(m, "Pipe [%d]:\n", i);
9429 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9430 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9431 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9432 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9433 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9434 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9435 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9436 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9437
9438 seq_printf(m, "Plane [%d]:\n", i);
9439 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9440 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9441 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9442 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9443 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9444 }
4b71a570 9445 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9446 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9447 if (INTEL_INFO(dev)->gen >= 4) {
9448 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9449 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9450 }
9451
9452 seq_printf(m, "Cursor [%d]:\n", i);
9453 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9454 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9455 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9456 }
9457}
9458#endif
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