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drm/i915: Fix Haswell/CRW PCI IDs.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 157 .m1 = { .min = 8, .max = 18 },
158 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 171 .m1 = { .min = 8, .max = 18 },
172 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
69310161
PZ		 1217 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219 cur_state = false;
1220 } else {
1221 reg = PIPECONF(cpu_transcoder);
1222 val = I915_READ(reg);
1223 cur_state = !!(val & PIPECONF_ENABLE);
1224 }
1225
63d7bbe9
JB		 1226 WARN(cur_state != state,
1227 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1228 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1229}
1230
931872fc
CW		 1231static void assert_plane(struct drm_i915_private *dev_priv,
1232 enum plane plane, bool state)
b24e7179
JB		 1233{
1234 int reg;
1235 u32 val;
931872fc 1236 bool cur_state;
b24e7179
JB		 1237
1238 reg = DSPCNTR(plane);
1239 val = I915_READ(reg);
931872fc
CW		 1240 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241 WARN(cur_state != state,
1242 "plane %c assertion failure (expected %s, current %s)\n",
1243 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1244}
1245
931872fc
CW		 1246#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
b24e7179
JB		 1249static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
1251{
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
19ec1358 1256 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1257 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN((val & DISPLAY_PLANE_ENABLE),
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
19ec1358 1263 return;
28c05794 1264 }
19ec1358 1265
b24e7179
JB		 1266 /* Need to check both planes against the pipe */
1267 for (i = 0; i < 2; i++) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1275 }
1276}
1277
92f2584a
JB		 1278static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279{
1280 u32 val;
1281 bool enabled;
1282
9d82aa17
ED		 1283 if (HAS_PCH_LPT(dev_priv->dev)) {
1284 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 return;
1286 }
1287
92f2584a
JB		 1288 val = I915_READ(PCH_DREF_CONTROL);
1289 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290 DREF_SUPERSPREAD_SOURCE_MASK));
1291 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292}
1293
1294static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296{
1297 int reg;
1298 u32 val;
1299 bool enabled;
1300
1301 reg = TRANSCONF(pipe);
1302 val = I915_READ(reg);
1303 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1304 WARN(enabled,
1305 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 pipe_name(pipe));
92f2584a
JB		 1307}
1308
4e634389
KP		 1309static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1311{
1312 if ((val & DP_PORT_EN) == 0)
1313 return false;
1314
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325}
1326
1519b995
KP		 1327static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329{
1330 if ((val & PORT_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv->dev)) {
1334 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335 return false;
1336 } else {
1337 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338 return false;
1339 }
1340 return true;
1341}
1342
1343static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1345{
1346 if ((val & LVDS_PORT_EN) == 0)
1347 return false;
1348
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351 return false;
1352 } else {
1353 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354 return false;
1355 }
1356 return true;
1357}
1358
1359static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
1362 if ((val & ADPA_DAC_ENABLE) == 0)
1363 return false;
1364 if (HAS_PCH_CPT(dev_priv->dev)) {
1365 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366 return false;
1367 } else {
1368 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369 return false;
1370 }
1371 return true;
1372}
1373
291906f1 1374static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1375 enum pipe pipe, int reg, u32 port_sel)
291906f1 1376{
47a05eca 1377 u32 val = I915_READ(reg);
4e634389 1378 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1379 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1380 reg, pipe_name(pipe));
de9a35ab 1381
75c5da27
DV		 1382 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383 && (val & DP_PIPEB_SELECT),
de9a35ab 1384 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1385}
1386
1387static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg)
1389{
47a05eca 1390 u32 val = I915_READ(reg);
b70ad586 1391 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1392 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1397 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402{
1403 int reg;
1404 u32 val;
291906f1 1405
f0575e92
KP		 1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1409
1410 reg = PCH_ADPA;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 reg = PCH_LVDS;
1417 val = I915_READ(reg);
b70ad586 1418 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1420 pipe_name(pipe));
291906f1
JB		 1421
1422 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425}
1426
63d7bbe9
JB		 1427/**
1428 * intel_enable_pll - enable a PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1433 * make sure the PLL reg is writable first though, since the panel write
1434 * protect mechanism may be enabled.
1435 *
1436 * Note! This is for pre-ILK only.
7434a255
TR		 1437 *
1438 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1439 */
1440static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441{
1442 int reg;
1443 u32 val;
1444
1445 /* No really, not for ILK+ */
a0c4da24 1446 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1447
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 reg = DPLL(pipe);
1453 val = I915_READ(reg);
1454 val |= DPLL_VCO_ENABLE;
1455
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1464 POSTING_READ(reg);
1465 udelay(150); /* wait for warmup */
1466}
1467
1468/**
1469 * intel_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1472 *
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1474 *
1475 * Note! This is for pre-ILK only.
1476 */
1477static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478{
1479 int reg;
1480 u32 val;
1481
1482 /* Don't disable pipe A or pipe A PLLs if needed */
1483 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484 return;
1485
1486 /* Make sure the pipe isn't still relying on us */
1487 assert_pipe_disabled(dev_priv, pipe);
1488
1489 reg = DPLL(pipe);
1490 val = I915_READ(reg);
1491 val &= ~DPLL_VCO_ENABLE;
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494}
1495
a416edef
ED		 1496/* SBI access */
1497static void
988d6ee8
PZ		 1498intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499 enum intel_sbi_destination destination)
a416edef 1500{
988d6ee8 1501 u32 tmp;
a416edef 1502
09153000 1503 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1504
39fb50f6 1505 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1506 100)) {
1507 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1508 return;
a416edef
ED		 1509 }
1510
988d6ee8
PZ		 1511 I915_WRITE(SBI_ADDR, (reg << 16));
1512 I915_WRITE(SBI_DATA, value);
1513
1514 if (destination == SBI_ICLK)
1515 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516 else
1517 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1519
39fb50f6 1520 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1521 100)) {
1522 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1523 return;
a416edef 1524 }
a416edef
ED		 1525}
1526
1527static u32
988d6ee8
PZ		 1528intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529 enum intel_sbi_destination destination)
a416edef 1530{
39fb50f6 1531 u32 value = 0;
09153000 1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1533
39fb50f6 1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1535 100)) {
1536 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1537 return 0;
a416edef
ED		 1538 }
1539
988d6ee8
PZ		 1540 I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542 if (destination == SBI_ICLK)
1543 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544 else
1545 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1547
39fb50f6 1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1549 100)) {
1550 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1551 return 0;
a416edef
ED		 1552 }
1553
09153000 1554 return I915_READ(SBI_DATA);
a416edef
ED		 1555}
1556
92f2584a 1557/**
b6b4e185 1558 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1559 * @dev_priv: i915 private structure
1560 * @pipe: pipe PLL to enable
1561 *
1562 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563 * drives the transcoder clock.
1564 */
b6b4e185 1565static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1566{
ee7b9f93 1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1568 struct intel_pch_pll *pll;
92f2584a
JB		 1569 int reg;
1570 u32 val;
1571
48da64a8 1572 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1573 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1574 pll = intel_crtc->pch_pll;
1575 if (pll == NULL)
1576 return;
1577
1578 if (WARN_ON(pll->refcount == 0))
1579 return;
ee7b9f93
JB		 1580
1581 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582 pll->pll_reg, pll->active, pll->on,
1583 intel_crtc->base.base.id);
92f2584a
JB		 1584
1585 /* PCH refclock must be enabled first */
1586 assert_pch_refclk_enabled(dev_priv);
1587
ee7b9f93 1588 if (pll->active++ && pll->on) {
92b27b08 1589 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1590 return;
1591 }
1592
1593 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595 reg = pll->pll_reg;
92f2584a
JB		 1596 val = I915_READ(reg);
1597 val |= DPLL_VCO_ENABLE;
1598 I915_WRITE(reg, val);
1599 POSTING_READ(reg);
1600 udelay(200);
ee7b9f93
JB		 1601
1602 pll->on = true;
92f2584a
JB		 1603}
1604
ee7b9f93 1605static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1606{
ee7b9f93
JB		 1607 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1609 int reg;
ee7b9f93 1610 u32 val;
4c609cb8 1611
92f2584a
JB		 1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1614 if (pll == NULL)
1615 return;
92f2584a 1616
48da64a8
CW		 1617 if (WARN_ON(pll->refcount == 0))
1618 return;
7a419866 1619
ee7b9f93
JB		 1620 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621 pll->pll_reg, pll->active, pll->on,
1622 intel_crtc->base.base.id);
7a419866 1623
48da64a8 1624 if (WARN_ON(pll->active == 0)) {
92b27b08 1625 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1626 return;
1627 }
1628
ee7b9f93 1629 if (--pll->active) {
92b27b08 1630 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1631 return;
ee7b9f93
JB		 1632 }
1633
1634 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636 /* Make sure transcoder isn't still depending on us */
1637 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1638
ee7b9f93 1639 reg = pll->pll_reg;
92f2584a
JB		 1640 val = I915_READ(reg);
1641 val &= ~DPLL_VCO_ENABLE;
1642 I915_WRITE(reg, val);
1643 POSTING_READ(reg);
1644 udelay(200);
ee7b9f93
JB		 1645
1646 pll->on = false;
92f2584a
JB		 1647}
1648
b8a4f404
PZ		 1649static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650 enum pipe pipe)
040484af 1651{
23670b32 1652 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1654 uint32_t reg, val, pipeconf_val;
040484af
JB		 1655
1656 /* PCH only available on ILK+ */
1657 BUG_ON(dev_priv->info->gen < 5);
1658
1659 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1660 assert_pch_pll_enabled(dev_priv,
1661 to_intel_crtc(crtc)->pch_pll,
1662 to_intel_crtc(crtc));
040484af
JB		 1663
1664 /* FDI must be feeding us bits for PCH ports */
1665 assert_fdi_tx_enabled(dev_priv, pipe);
1666 assert_fdi_rx_enabled(dev_priv, pipe);
1667
23670b32
DV		 1668 if (HAS_PCH_CPT(dev)) {
1669 /* Workaround: Set the timing override bit before enabling the
1670 * pch transcoder. */
1671 reg = TRANS_CHICKEN2(pipe);
1672 val = I915_READ(reg);
1673 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674 I915_WRITE(reg, val);
59c859d6 1675 }
23670b32 1676
040484af
JB		 1677 reg = TRANSCONF(pipe);
1678 val = I915_READ(reg);
5f7f726d 1679 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1680
1681 if (HAS_PCH_IBX(dev_priv->dev)) {
1682 /*
1683 * make the BPC in transcoder be consistent with
1684 * that in pipeconf reg.
1685 */
dfd07d72
DV		 1686 val &= ~PIPECONF_BPC_MASK;
1687 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1688 }
5f7f726d
PZ		 1689
1690 val &= ~TRANS_INTERLACE_MASK;
1691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1692 if (HAS_PCH_IBX(dev_priv->dev) &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694 val |= TRANS_LEGACY_INTERLACED_ILK;
1695 else
1696 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1697 else
1698 val |= TRANS_PROGRESSIVE;
1699
040484af
JB		 1700 I915_WRITE(reg, val | TRANS_ENABLE);
1701 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703}
1704
8fb033d7 1705static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1706 enum transcoder cpu_transcoder)
040484af 1707{
8fb033d7 1708 u32 val, pipeconf_val;
8fb033d7
PZ		 1709
1710 /* PCH only available on ILK+ */
1711 BUG_ON(dev_priv->info->gen < 5);
1712
8fb033d7 1713 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1714 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1715 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1716
223a6fdf
PZ		 1717 /* Workaround: set timing override bit. */
1718 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1719 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1720 I915_WRITE(_TRANSA_CHICKEN2, val);
1721
25f3ef11 1722 val = TRANS_ENABLE;
937bb610 1723 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1724
9a76b1c6
PZ		 1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726 PIPECONF_INTERLACED_ILK)
a35f2679 1727 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1728 else
1729 val |= TRANS_PROGRESSIVE;
1730
25f3ef11 1731 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1732 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1734}
1735
b8a4f404
PZ		 1736static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737 enum pipe pipe)
040484af 1738{
23670b32
DV		 1739 struct drm_device *dev = dev_priv->dev;
1740 uint32_t reg, val;
040484af
JB		 1741
1742 /* FDI relies on the transcoder */
1743 assert_fdi_tx_disabled(dev_priv, pipe);
1744 assert_fdi_rx_disabled(dev_priv, pipe);
1745
291906f1
JB		 1746 /* Ports must be off as well */
1747 assert_pch_ports_disabled(dev_priv, pipe);
1748
040484af
JB		 1749 reg = TRANSCONF(pipe);
1750 val = I915_READ(reg);
1751 val &= ~TRANS_ENABLE;
1752 I915_WRITE(reg, val);
1753 /* wait for PCH transcoder off, transcoder state */
1754 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1755 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1756
1757 if (!HAS_PCH_IBX(dev)) {
1758 /* Workaround: Clear the timing override chicken bit again. */
1759 reg = TRANS_CHICKEN2(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762 I915_WRITE(reg, val);
1763 }
040484af
JB		 1764}
1765
ab4d966c 1766static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1767{
8fb033d7
PZ		 1768 u32 val;
1769
8a52fd9f 1770 val = I915_READ(_TRANSACONF);
8fb033d7 1771 val &= ~TRANS_ENABLE;
8a52fd9f 1772 I915_WRITE(_TRANSACONF, val);
8fb033d7 1773 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1774 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1776
1777 /* Workaround: clear timing override bit. */
1778 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1779 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1780 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1781}
1782
b24e7179 1783/**
309cfea8 1784 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to enable
040484af 1787 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1788 *
1789 * Enable @pipe, making sure that various hardware specific requirements
1790 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791 *
1792 * @pipe should be %PIPE_A or %PIPE_B.
1793 *
1794 * Will wait until the pipe is actually running (i.e. first vblank) before
1795 * returning.
1796 */
040484af
JB		 1797static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798 bool pch_port)
b24e7179 1799{
702e7a56
PZ		 1800 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801 pipe);
1a240d4d 1802 enum pipe pch_transcoder;
b24e7179
JB		 1803 int reg;
1804 u32 val;
1805
681e5811 1806 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1807 pch_transcoder = TRANSCODER_A;
1808 else
1809 pch_transcoder = pipe;
1810
b24e7179
JB		 1811 /*
1812 * A pipe without a PLL won't actually be able to drive bits from
1813 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1814 * need the check.
1815 */
1816 if (!HAS_PCH_SPLIT(dev_priv->dev))
1817 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1818 else {
1819 if (pch_port) {
1820 /* if driving the PCH, we need FDI enabled */
cc391bbb 1821 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1822 assert_fdi_tx_pll_enabled(dev_priv,
1823 (enum pipe) cpu_transcoder);
040484af
JB		 1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
b24e7179 1827
702e7a56 1828 reg = PIPECONF(cpu_transcoder);
b24e7179 1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
1837/**
309cfea8 1838 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851{
702e7a56
PZ		 1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
b24e7179
JB		 1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874}
1875
d74362c9
KP		 1876/*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
6f1d69b0 1880void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1881 enum plane plane)
1882{
14f86147
DL		 1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1887}
1888
b24e7179
JB		 1889/**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899{
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
00d70b15
CW		 1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1912 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914}
1915
b24e7179
JB		 1916/**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926{
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
00d70b15
CW		 1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938}
1939
127bd2ac 1940int
48b956c5 1941intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1942 struct drm_i915_gem_object *obj,
919926ae 1943 struct intel_ring_buffer *pipelined)
6b95a207 1944{
ce453d81 1945 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1946 u32 alignment;
1947 int ret;
1948
05394f39 1949 switch (obj->tiling_mode) {
6b95a207 1950 case I915_TILING_NONE:
534843da
CW		 1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
a6c45cf0 1953 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
6b95a207
KH		 1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
ce453d81 1970 dev_priv->mm.interruptible = false;
2da3b9b9 1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1972 if (ret)
ce453d81 1973 goto err_interruptible;
6b95a207
KH		 1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
06d98131 1980 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1981 if (ret)
1982 goto err_unpin;
1690e1eb 1983
9a5a53b3 1984 i915_gem_object_pin_fence(obj);
6b95a207 1985
ce453d81 1986 dev_priv->mm.interruptible = true;
6b95a207 1987 return 0;
48b956c5
CW		 1988
1989err_unpin:
1990 i915_gem_object_unpin(obj);
ce453d81
CW		 1991err_interruptible:
1992 dev_priv->mm.interruptible = true;
48b956c5 1993 return ret;
6b95a207
KH		 1994}
1995
1690e1eb
CW		 1996void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997{
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000}
2001
c2c75131
DV		 2002/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
bc752862
CW		 2004unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2005 unsigned int tiling_mode,
2006 unsigned int cpp,
2007 unsigned int pitch)
c2c75131 2008{
bc752862
CW		 2009 if (tiling_mode != I915_TILING_NONE) {
2010 unsigned int tile_rows, tiles;
c2c75131 2011
bc752862
CW		 2012 tile_rows = *y / 8;
2013 *y %= 8;
c2c75131 2014
bc752862
CW		 2015 tiles = *x / (512/cpp);
2016 *x %= 512/cpp;
2017
2018 return tile_rows * pitch * 8 + tiles * 4096;
2019 } else {
2020 unsigned int offset;
2021
2022 offset = *y * pitch + *x * cpp;
2023 *y = 0;
2024 *x = (offset & 4095) / cpp;
2025 return offset & -4096;
2026 }
c2c75131
DV		 2027}
2028
17638cd6
JB		 2029static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2030 int x, int y)
81255565
JB		 2031{
2032 struct drm_device *dev = crtc->dev;
2033 struct drm_i915_private *dev_priv = dev->dev_private;
2034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2035 struct intel_framebuffer *intel_fb;
05394f39 2036 struct drm_i915_gem_object *obj;
81255565 2037 int plane = intel_crtc->plane;
e506a0c6 2038 unsigned long linear_offset;
81255565 2039 u32 dspcntr;
5eddb70b 2040 u32 reg;
81255565
JB		 2041
2042 switch (plane) {
2043 case 0:
2044 case 1:
2045 break;
2046 default:
2047 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2048 return -EINVAL;
2049 }
2050
2051 intel_fb = to_intel_framebuffer(fb);
2052 obj = intel_fb->obj;
81255565 2053
5eddb70b
CW		 2054 reg = DSPCNTR(plane);
2055 dspcntr = I915_READ(reg);
81255565
JB		 2056 /* Mask out pixel format bits in case we change it */
2057 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2058 switch (fb->pixel_format) {
2059 case DRM_FORMAT_C8:
81255565
JB		 2060 dspcntr |= DISPPLANE_8BPP;
2061 break;
57779d06
VS		 2062 case DRM_FORMAT_XRGB1555:
2063 case DRM_FORMAT_ARGB1555:
2064 dspcntr |= DISPPLANE_BGRX555;
81255565 2065 break;
57779d06
VS		 2066 case DRM_FORMAT_RGB565:
2067 dspcntr |= DISPPLANE_BGRX565;
2068 break;
2069 case DRM_FORMAT_XRGB8888:
2070 case DRM_FORMAT_ARGB8888:
2071 dspcntr |= DISPPLANE_BGRX888;
2072 break;
2073 case DRM_FORMAT_XBGR8888:
2074 case DRM_FORMAT_ABGR8888:
2075 dspcntr |= DISPPLANE_RGBX888;
2076 break;
2077 case DRM_FORMAT_XRGB2101010:
2078 case DRM_FORMAT_ARGB2101010:
2079 dspcntr |= DISPPLANE_BGRX101010;
2080 break;
2081 case DRM_FORMAT_XBGR2101010:
2082 case DRM_FORMAT_ABGR2101010:
2083 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2084 break;
2085 default:
57779d06 2086 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2087 return -EINVAL;
2088 }
57779d06 2089
a6c45cf0 2090 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2091 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2092 dspcntr |= DISPPLANE_TILED;
2093 else
2094 dspcntr &= ~DISPPLANE_TILED;
2095 }
2096
5eddb70b 2097 I915_WRITE(reg, dspcntr);
81255565 2098
e506a0c6 2099 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2100
c2c75131
DV		 2101 if (INTEL_INFO(dev)->gen >= 4) {
2102 intel_crtc->dspaddr_offset =
bc752862
CW		 2103 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2104 fb->bits_per_pixel / 8,
2105 fb->pitches[0]);
c2c75131
DV		 2106 linear_offset -= intel_crtc->dspaddr_offset;
2107 } else {
e506a0c6 2108 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2109 }
e506a0c6
DV		 2110
2111 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2112 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2113 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2114 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2115 I915_MODIFY_DISPBASE(DSPSURF(plane),
2116 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2117 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2118 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2119 } else
e506a0c6 2120 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2121 POSTING_READ(reg);
81255565 2122
17638cd6
JB		 2123 return 0;
2124}
2125
2126static int ironlake_update_plane(struct drm_crtc *crtc,
2127 struct drm_framebuffer *fb, int x, int y)
2128{
2129 struct drm_device *dev = crtc->dev;
2130 struct drm_i915_private *dev_priv = dev->dev_private;
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132 struct intel_framebuffer *intel_fb;
2133 struct drm_i915_gem_object *obj;
2134 int plane = intel_crtc->plane;
e506a0c6 2135 unsigned long linear_offset;
17638cd6
JB		 2136 u32 dspcntr;
2137 u32 reg;
2138
2139 switch (plane) {
2140 case 0:
2141 case 1:
27f8227b 2142 case 2:
17638cd6
JB		 2143 break;
2144 default:
2145 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2146 return -EINVAL;
2147 }
2148
2149 intel_fb = to_intel_framebuffer(fb);
2150 obj = intel_fb->obj;
2151
2152 reg = DSPCNTR(plane);
2153 dspcntr = I915_READ(reg);
2154 /* Mask out pixel format bits in case we change it */
2155 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2156 switch (fb->pixel_format) {
2157 case DRM_FORMAT_C8:
17638cd6
JB		 2158 dspcntr |= DISPPLANE_8BPP;
2159 break;
57779d06
VS		 2160 case DRM_FORMAT_RGB565:
2161 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2162 break;
57779d06
VS		 2163 case DRM_FORMAT_XRGB8888:
2164 case DRM_FORMAT_ARGB8888:
2165 dspcntr |= DISPPLANE_BGRX888;
2166 break;
2167 case DRM_FORMAT_XBGR8888:
2168 case DRM_FORMAT_ABGR8888:
2169 dspcntr |= DISPPLANE_RGBX888;
2170 break;
2171 case DRM_FORMAT_XRGB2101010:
2172 case DRM_FORMAT_ARGB2101010:
2173 dspcntr |= DISPPLANE_BGRX101010;
2174 break;
2175 case DRM_FORMAT_XBGR2101010:
2176 case DRM_FORMAT_ABGR2101010:
2177 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2178 break;
2179 default:
57779d06 2180 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2181 return -EINVAL;
2182 }
2183
2184 if (obj->tiling_mode != I915_TILING_NONE)
2185 dspcntr |= DISPPLANE_TILED;
2186 else
2187 dspcntr &= ~DISPPLANE_TILED;
2188
2189 /* must disable */
2190 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2191
2192 I915_WRITE(reg, dspcntr);
2193
e506a0c6 2194 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2195 intel_crtc->dspaddr_offset =
bc752862
CW		 2196 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2197 fb->bits_per_pixel / 8,
2198 fb->pitches[0]);
c2c75131 2199 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2200
e506a0c6
DV		 2201 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2202 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2203 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2204 I915_MODIFY_DISPBASE(DSPSURF(plane),
2205 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2206 if (IS_HASWELL(dev)) {
2207 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2208 } else {
2209 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211 }
17638cd6
JB		 2212 POSTING_READ(reg);
2213
2214 return 0;
2215}
2216
2217/* Assume fb object is pinned & idle & fenced and just update base pointers */
2218static int
2219intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220 int x, int y, enum mode_set_atomic state)
2221{
2222 struct drm_device *dev = crtc->dev;
2223 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2224
6b8e6ed0
CW		 2225 if (dev_priv->display.disable_fbc)
2226 dev_priv->display.disable_fbc(dev);
3dec0095 2227 intel_increase_pllclock(crtc);
81255565 2228
6b8e6ed0 2229 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2230}
2231
14667a4b
CW		 2232static int
2233intel_finish_fb(struct drm_framebuffer *old_fb)
2234{
2235 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2236 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2237 bool was_interruptible = dev_priv->mm.interruptible;
2238 int ret;
2239
14667a4b
CW		 2240 /* Big Hammer, we also need to ensure that any pending
2241 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2242 * current scanout is retired before unpinning the old
2243 * framebuffer.
2244 *
2245 * This should only fail upon a hung GPU, in which case we
2246 * can safely continue.
2247 */
2248 dev_priv->mm.interruptible = false;
2249 ret = i915_gem_object_finish_gpu(obj);
2250 dev_priv->mm.interruptible = was_interruptible;
2251
2252 return ret;
2253}
2254
198598d0
VS		 2255static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2256{
2257 struct drm_device *dev = crtc->dev;
2258 struct drm_i915_master_private *master_priv;
2259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260
2261 if (!dev->primary->master)
2262 return;
2263
2264 master_priv = dev->primary->master->driver_priv;
2265 if (!master_priv->sarea_priv)
2266 return;
2267
2268 switch (intel_crtc->pipe) {
2269 case 0:
2270 master_priv->sarea_priv->pipeA_x = x;
2271 master_priv->sarea_priv->pipeA_y = y;
2272 break;
2273 case 1:
2274 master_priv->sarea_priv->pipeB_x = x;
2275 master_priv->sarea_priv->pipeB_y = y;
2276 break;
2277 default:
2278 break;
2279 }
2280}
2281
5c3b82e2 2282static int
3c4fdcfb 2283intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2284 struct drm_framebuffer *fb)
79e53945
JB		 2285{
2286 struct drm_device *dev = crtc->dev;
6b8e6ed0 2287 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2289 struct drm_framebuffer *old_fb;
5c3b82e2 2290 int ret;
79e53945
JB		 2291
2292 /* no fb bound */
94352cf9 2293 if (!fb) {
a5071c2f 2294 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2295 return 0;
2296 }
2297
5826eca5
ED		 2298 if(intel_crtc->plane > dev_priv->num_pipe) {
2299 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2300 intel_crtc->plane,
2301 dev_priv->num_pipe);
5c3b82e2 2302 return -EINVAL;
79e53945
JB		 2303 }
2304
5c3b82e2 2305 mutex_lock(&dev->struct_mutex);
265db958 2306 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2307 to_intel_framebuffer(fb)->obj,
919926ae 2308 NULL);
5c3b82e2
CW		 2309 if (ret != 0) {
2310 mutex_unlock(&dev->struct_mutex);
a5071c2f 2311 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2312 return ret;
2313 }
79e53945 2314
94352cf9
DV		 2315 if (crtc->fb)
2316 intel_finish_fb(crtc->fb);
265db958 2317
94352cf9 2318 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2319 if (ret) {
94352cf9 2320 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2321 mutex_unlock(&dev->struct_mutex);
a5071c2f 2322 DRM_ERROR("failed to update base address\n");
4e6cfefc 2323 return ret;
79e53945 2324 }
3c4fdcfb 2325
94352cf9
DV		 2326 old_fb = crtc->fb;
2327 crtc->fb = fb;
6c4c86f5
DV		 2328 crtc->x = x;
2329 crtc->y = y;
94352cf9 2330
b7f1de28
CW		 2331 if (old_fb) {
2332 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2333 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2334 }
652c393a 2335
6b8e6ed0 2336 intel_update_fbc(dev);
5c3b82e2 2337 mutex_unlock(&dev->struct_mutex);
79e53945 2338
198598d0 2339 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2340
2341 return 0;
79e53945
JB		 2342}
2343
5e84e1a4
ZW		 2344static void intel_fdi_normal_train(struct drm_crtc *crtc)
2345{
2346 struct drm_device *dev = crtc->dev;
2347 struct drm_i915_private *dev_priv = dev->dev_private;
2348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2349 int pipe = intel_crtc->pipe;
2350 u32 reg, temp;
2351
2352 /* enable normal train */
2353 reg = FDI_TX_CTL(pipe);
2354 temp = I915_READ(reg);
61e499bf 2355 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2356 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2357 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2358 } else {
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2361 }
5e84e1a4
ZW		 2362 I915_WRITE(reg, temp);
2363
2364 reg = FDI_RX_CTL(pipe);
2365 temp = I915_READ(reg);
2366 if (HAS_PCH_CPT(dev)) {
2367 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2368 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2369 } else {
2370 temp &= ~FDI_LINK_TRAIN_NONE;
2371 temp |= FDI_LINK_TRAIN_NONE;
2372 }
2373 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2374
2375 /* wait one idle pattern time */
2376 POSTING_READ(reg);
2377 udelay(1000);
357555c0
JB		 2378
2379 /* IVB wants error correction enabled */
2380 if (IS_IVYBRIDGE(dev))
2381 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2382 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2383}
2384
01a415fd
DV		 2385static void ivb_modeset_global_resources(struct drm_device *dev)
2386{
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 struct intel_crtc *pipe_B_crtc =
2389 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2390 struct intel_crtc *pipe_C_crtc =
2391 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2392 uint32_t temp;
2393
2394 /* When everything is off disable fdi C so that we could enable fdi B
2395 * with all lanes. XXX: This misses the case where a pipe is not using
2396 * any pch resources and so doesn't need any fdi lanes. */
2397 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2398 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2399 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2400
2401 temp = I915_READ(SOUTH_CHICKEN1);
2402 temp &= ~FDI_BC_BIFURCATION_SELECT;
2403 DRM_DEBUG_KMS("disabling fdi C rx\n");
2404 I915_WRITE(SOUTH_CHICKEN1, temp);
2405 }
2406}
2407
8db9d77b
ZW		 2408/* The FDI link training functions for ILK/Ibexpeak. */
2409static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2410{
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 int pipe = intel_crtc->pipe;
0fc932b8 2415 int plane = intel_crtc->plane;
5eddb70b 2416 u32 reg, temp, tries;
8db9d77b 2417
0fc932b8
JB		 2418 /* FDI needs bits from pipe & plane first */
2419 assert_pipe_enabled(dev_priv, pipe);
2420 assert_plane_enabled(dev_priv, plane);
2421
e1a44743
AJ		 2422 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2423 for train result */
5eddb70b
CW		 2424 reg = FDI_RX_IMR(pipe);
2425 temp = I915_READ(reg);
e1a44743
AJ		 2426 temp &= ~FDI_RX_SYMBOL_LOCK;
2427 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2428 I915_WRITE(reg, temp);
2429 I915_READ(reg);
e1a44743
AJ		 2430 udelay(150);
2431
8db9d77b 2432 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2433 reg = FDI_TX_CTL(pipe);
2434 temp = I915_READ(reg);
77ffb597
AJ		 2435 temp &= ~(7 << 19);
2436 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2439 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2440
5eddb70b
CW		 2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
8db9d77b
ZW		 2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2445 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447 POSTING_READ(reg);
8db9d77b
ZW		 2448 udelay(150);
2449
5b2adf89 2450 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2451 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2452 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2453 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2454
5eddb70b 2455 reg = FDI_RX_IIR(pipe);
e1a44743 2456 for (tries = 0; tries < 5; tries++) {
5eddb70b 2457 temp = I915_READ(reg);
8db9d77b
ZW		 2458 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460 if ((temp & FDI_RX_BIT_LOCK)) {
2461 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2462 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2463 break;
2464 }
8db9d77b 2465 }
e1a44743 2466 if (tries == 5)
5eddb70b 2467 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2468
2469 /* Train 2 */
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_NONE;
2473 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2474 I915_WRITE(reg, temp);
8db9d77b 2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 temp &= ~FDI_LINK_TRAIN_NONE;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2480 I915_WRITE(reg, temp);
8db9d77b 2481
5eddb70b
CW		 2482 POSTING_READ(reg);
2483 udelay(150);
8db9d77b 2484
5eddb70b 2485 reg = FDI_RX_IIR(pipe);
e1a44743 2486 for (tries = 0; tries < 5; tries++) {
5eddb70b 2487 temp = I915_READ(reg);
8db9d77b
ZW		 2488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2491 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2492 DRM_DEBUG_KMS("FDI train 2 done.\n");
2493 break;
2494 }
8db9d77b 2495 }
e1a44743 2496 if (tries == 5)
5eddb70b 2497 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2498
2499 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2500
8db9d77b
ZW		 2501}
2502
0206e353 2503static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2504 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508};
2509
2510/* The FDI link training functions for SNB/Cougarpoint. */
2511static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512{
2513 struct drm_device *dev = crtc->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516 int pipe = intel_crtc->pipe;
fa37d39e 2517 u32 reg, temp, i, retry;
8db9d77b 2518
e1a44743
AJ		 2519 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520 for train result */
5eddb70b
CW		 2521 reg = FDI_RX_IMR(pipe);
2522 temp = I915_READ(reg);
e1a44743
AJ		 2523 temp &= ~FDI_RX_SYMBOL_LOCK;
2524 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2525 I915_WRITE(reg, temp);
2526
2527 POSTING_READ(reg);
e1a44743
AJ		 2528 udelay(150);
2529
8db9d77b 2530 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
77ffb597
AJ		 2533 temp &= ~(7 << 19);
2534 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538 /* SNB-B */
2539 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2540 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2541
d74cf324
DV		 2542 I915_WRITE(FDI_RX_MISC(pipe),
2543 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
5eddb70b
CW		 2545 reg = FDI_RX_CTL(pipe);
2546 temp = I915_READ(reg);
8db9d77b
ZW		 2547 if (HAS_PCH_CPT(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550 } else {
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553 }
5eddb70b
CW		 2554 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556 POSTING_READ(reg);
8db9d77b
ZW		 2557 udelay(150);
2558
0206e353 2559 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
8db9d77b
ZW		 2562 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2564 I915_WRITE(reg, temp);
2565
2566 POSTING_READ(reg);
8db9d77b
ZW		 2567 udelay(500);
2568
fa37d39e
SP		 2569 for (retry = 0; retry < 5; retry++) {
2570 reg = FDI_RX_IIR(pipe);
2571 temp = I915_READ(reg);
2572 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2573 if (temp & FDI_RX_BIT_LOCK) {
2574 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2575 DRM_DEBUG_KMS("FDI train 1 done.\n");
2576 break;
2577 }
2578 udelay(50);
8db9d77b 2579 }
fa37d39e
SP		 2580 if (retry < 5)
2581 break;
8db9d77b
ZW		 2582 }
2583 if (i == 4)
5eddb70b 2584 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2585
2586 /* Train 2 */
5eddb70b
CW		 2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 temp &= ~FDI_LINK_TRAIN_NONE;
2590 temp |= FDI_LINK_TRAIN_PATTERN_2;
2591 if (IS_GEN6(dev)) {
2592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2593 /* SNB-B */
2594 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2595 }
5eddb70b 2596 I915_WRITE(reg, temp);
8db9d77b 2597
5eddb70b
CW		 2598 reg = FDI_RX_CTL(pipe);
2599 temp = I915_READ(reg);
8db9d77b
ZW		 2600 if (HAS_PCH_CPT(dev)) {
2601 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2602 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2603 } else {
2604 temp &= ~FDI_LINK_TRAIN_NONE;
2605 temp |= FDI_LINK_TRAIN_PATTERN_2;
2606 }
5eddb70b
CW		 2607 I915_WRITE(reg, temp);
2608
2609 POSTING_READ(reg);
8db9d77b
ZW		 2610 udelay(150);
2611
0206e353 2612 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2613 reg = FDI_TX_CTL(pipe);
2614 temp = I915_READ(reg);
8db9d77b
ZW		 2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2617 I915_WRITE(reg, temp);
2618
2619 POSTING_READ(reg);
8db9d77b
ZW		 2620 udelay(500);
2621
fa37d39e
SP		 2622 for (retry = 0; retry < 5; retry++) {
2623 reg = FDI_RX_IIR(pipe);
2624 temp = I915_READ(reg);
2625 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2626 if (temp & FDI_RX_SYMBOL_LOCK) {
2627 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2628 DRM_DEBUG_KMS("FDI train 2 done.\n");
2629 break;
2630 }
2631 udelay(50);
8db9d77b 2632 }
fa37d39e
SP		 2633 if (retry < 5)
2634 break;
8db9d77b
ZW		 2635 }
2636 if (i == 4)
5eddb70b 2637 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2638
2639 DRM_DEBUG_KMS("FDI train done.\n");
2640}
2641
357555c0
JB		 2642/* Manual link training for Ivy Bridge A0 parts */
2643static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2644{
2645 struct drm_device *dev = crtc->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648 int pipe = intel_crtc->pipe;
2649 u32 reg, temp, i;
2650
2651 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2652 for train result */
2653 reg = FDI_RX_IMR(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_RX_SYMBOL_LOCK;
2656 temp &= ~FDI_RX_BIT_LOCK;
2657 I915_WRITE(reg, temp);
2658
2659 POSTING_READ(reg);
2660 udelay(150);
2661
01a415fd
DV		 2662 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2663 I915_READ(FDI_RX_IIR(pipe)));
2664
357555c0
JB		 2665 /* enable CPU FDI TX and PCH FDI RX */
2666 reg = FDI_TX_CTL(pipe);
2667 temp = I915_READ(reg);
2668 temp &= ~(7 << 19);
2669 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2670 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2671 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2672 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2674 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2675 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2676
d74cf324
DV		 2677 I915_WRITE(FDI_RX_MISC(pipe),
2678 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2679
357555c0
JB		 2680 reg = FDI_RX_CTL(pipe);
2681 temp = I915_READ(reg);
2682 temp &= ~FDI_LINK_TRAIN_AUTO;
2683 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2685 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2686 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2687
2688 POSTING_READ(reg);
2689 udelay(150);
2690
0206e353 2691 for (i = 0; i < 4; i++) {
357555c0
JB		 2692 reg = FDI_TX_CTL(pipe);
2693 temp = I915_READ(reg);
2694 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695 temp |= snb_b_fdi_train_param[i];
2696 I915_WRITE(reg, temp);
2697
2698 POSTING_READ(reg);
2699 udelay(500);
2700
2701 reg = FDI_RX_IIR(pipe);
2702 temp = I915_READ(reg);
2703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2704
2705 if (temp & FDI_RX_BIT_LOCK ||
2706 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2707 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2708 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2709 break;
2710 }
2711 }
2712 if (i == 4)
2713 DRM_ERROR("FDI train 1 fail!\n");
2714
2715 /* Train 2 */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2719 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2720 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2721 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2722 I915_WRITE(reg, temp);
2723
2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2727 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2728 I915_WRITE(reg, temp);
2729
2730 POSTING_READ(reg);
2731 udelay(150);
2732
0206e353 2733 for (i = 0; i < 4; i++) {
357555c0
JB		 2734 reg = FDI_TX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737 temp |= snb_b_fdi_train_param[i];
2738 I915_WRITE(reg, temp);
2739
2740 POSTING_READ(reg);
2741 udelay(500);
2742
2743 reg = FDI_RX_IIR(pipe);
2744 temp = I915_READ(reg);
2745 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2746
2747 if (temp & FDI_RX_SYMBOL_LOCK) {
2748 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2749 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2750 break;
2751 }
2752 }
2753 if (i == 4)
2754 DRM_ERROR("FDI train 2 fail!\n");
2755
2756 DRM_DEBUG_KMS("FDI train done.\n");
2757}
2758
88cefb6c 2759static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2760{
88cefb6c 2761 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2762 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2763 int pipe = intel_crtc->pipe;
5eddb70b 2764 u32 reg, temp;
79e53945 2765
c64e311e 2766
c98e9dcf 2767 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2771 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2772 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2773 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2774
2775 POSTING_READ(reg);
c98e9dcf
JB		 2776 udelay(200);
2777
2778 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2779 temp = I915_READ(reg);
2780 I915_WRITE(reg, temp | FDI_PCDCLK);
2781
2782 POSTING_READ(reg);
c98e9dcf
JB		 2783 udelay(200);
2784
20749730
PZ		 2785 /* Enable CPU FDI TX PLL, always on for Ironlake */
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2789 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2790
20749730
PZ		 2791 POSTING_READ(reg);
2792 udelay(100);
6be4a607 2793 }
0e23b99d
JB		 2794}
2795
88cefb6c
DV		 2796static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2797{
2798 struct drm_device *dev = intel_crtc->base.dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 int pipe = intel_crtc->pipe;
2801 u32 reg, temp;
2802
2803 /* Switch from PCDclk to Rawclk */
2804 reg = FDI_RX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2807
2808 /* Disable CPU FDI TX PLL */
2809 reg = FDI_TX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2812
2813 POSTING_READ(reg);
2814 udelay(100);
2815
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2819
2820 /* Wait for the clocks to turn off. */
2821 POSTING_READ(reg);
2822 udelay(100);
2823}
2824
0fc932b8
JB		 2825static void ironlake_fdi_disable(struct drm_crtc *crtc)
2826{
2827 struct drm_device *dev = crtc->dev;
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830 int pipe = intel_crtc->pipe;
2831 u32 reg, temp;
2832
2833 /* disable CPU FDI tx and PCH FDI rx */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2837 POSTING_READ(reg);
2838
2839 reg = FDI_RX_CTL(pipe);
2840 temp = I915_READ(reg);
2841 temp &= ~(0x7 << 16);
dfd07d72 2842 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2843 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2844
2845 POSTING_READ(reg);
2846 udelay(100);
2847
2848 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2849 if (HAS_PCH_IBX(dev)) {
2850 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2851 }
0fc932b8
JB		 2852
2853 /* still set train pattern 1 */
2854 reg = FDI_TX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 temp &= ~FDI_LINK_TRAIN_NONE;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 I915_WRITE(reg, temp);
2859
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 if (HAS_PCH_CPT(dev)) {
2863 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2865 } else {
2866 temp &= ~FDI_LINK_TRAIN_NONE;
2867 temp |= FDI_LINK_TRAIN_PATTERN_1;
2868 }
2869 /* BPC in FDI rx is consistent with that in PIPECONF */
2870 temp &= ~(0x07 << 16);
dfd07d72 2871 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2872 I915_WRITE(reg, temp);
2873
2874 POSTING_READ(reg);
2875 udelay(100);
2876}
2877
5bb61643
CW		 2878static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2879{
2880 struct drm_device *dev = crtc->dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2883 unsigned long flags;
2884 bool pending;
2885
10d83730
VS		 2886 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2887 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2888 return false;
2889
2890 spin_lock_irqsave(&dev->event_lock, flags);
2891 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2892 spin_unlock_irqrestore(&dev->event_lock, flags);
2893
2894 return pending;
2895}
2896
e6c3a2a6
CW		 2897static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2898{
0f91128d 2899 struct drm_device *dev = crtc->dev;
5bb61643 2900 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2901
2902 if (crtc->fb == NULL)
2903 return;
2904
2c10d571
DV		 2905 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2906
5bb61643
CW		 2907 wait_event(dev_priv->pending_flip_queue,
2908 !intel_crtc_has_pending_flip(crtc));
2909
0f91128d
CW		 2910 mutex_lock(&dev->struct_mutex);
2911 intel_finish_fb(crtc->fb);
2912 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2913}
2914
fc316cbe 2915static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2916{
2917 struct drm_device *dev = crtc->dev;
228d3e36 2918 struct intel_encoder *intel_encoder;
040484af
JB		 2919
2920 /*
2921 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2922 * must be driven by its own crtc; no sharing is possible.
2923 */
228d3e36 2924 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2925 switch (intel_encoder->type) {
040484af 2926 case INTEL_OUTPUT_EDP:
228d3e36 2927 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2928 return false;
2929 continue;
2930 }
2931 }
2932
2933 return true;
2934}
2935
fc316cbe
PZ		 2936static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2937{
2938 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2939}
2940
e615efe4
ED		 2941/* Program iCLKIP clock to the desired frequency */
2942static void lpt_program_iclkip(struct drm_crtc *crtc)
2943{
2944 struct drm_device *dev = crtc->dev;
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2946 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2947 u32 temp;
2948
09153000
DV		 2949 mutex_lock(&dev_priv->dpio_lock);
2950
e615efe4
ED		 2951 /* It is necessary to ungate the pixclk gate prior to programming
2952 * the divisors, and gate it back when it is done.
2953 */
2954 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2955
2956 /* Disable SSCCTL */
2957 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2958 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2959 SBI_SSCCTL_DISABLE,
2960 SBI_ICLK);
e615efe4
ED		 2961
2962 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2963 if (crtc->mode.clock == 20000) {
2964 auxdiv = 1;
2965 divsel = 0x41;
2966 phaseinc = 0x20;
2967 } else {
2968 /* The iCLK virtual clock root frequency is in MHz,
2969 * but the crtc->mode.clock in in KHz. To get the divisors,
2970 * it is necessary to divide one by another, so we
2971 * convert the virtual clock precision to KHz here for higher
2972 * precision.
2973 */
2974 u32 iclk_virtual_root_freq = 172800 * 1000;
2975 u32 iclk_pi_range = 64;
2976 u32 desired_divisor, msb_divisor_value, pi_value;
2977
2978 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2979 msb_divisor_value = desired_divisor / iclk_pi_range;
2980 pi_value = desired_divisor % iclk_pi_range;
2981
2982 auxdiv = 0;
2983 divsel = msb_divisor_value - 2;
2984 phaseinc = pi_value;
2985 }
2986
2987 /* This should not happen with any sane values */
2988 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2989 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2990 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2991 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2992
2993 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2994 crtc->mode.clock,
2995 auxdiv,
2996 divsel,
2997 phasedir,
2998 phaseinc);
2999
3000 /* Program SSCDIVINTPHASE6 */
988d6ee8 3001 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3002 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3003 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3004 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3005 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3006 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3007 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3008 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3009
3010 /* Program SSCAUXDIV */
988d6ee8 3011 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3012 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3013 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3014 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3015
3016 /* Enable modulator and associated divider */
988d6ee8 3017 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3018 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3019 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3020
3021 /* Wait for initialization time */
3022 udelay(24);
3023
3024 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3025
3026 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3027}
3028
f67a559d
JB		 3029/*
3030 * Enable PCH resources required for PCH ports:
3031 * - PCH PLLs
3032 * - FDI training & RX/TX
3033 * - update transcoder timings
3034 * - DP transcoding bits
3035 * - transcoder
3036 */
3037static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3038{
3039 struct drm_device *dev = crtc->dev;
3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042 int pipe = intel_crtc->pipe;
ee7b9f93 3043 u32 reg, temp;
2c07245f 3044
e7e164db
CW		 3045 assert_transcoder_disabled(dev_priv, pipe);
3046
cd986abb
DV		 3047 /* Write the TU size bits before fdi link training, so that error
3048 * detection works. */
3049 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3050 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3051
c98e9dcf 3052 /* For PCH output, training FDI link */
674cf967 3053 dev_priv->display.fdi_link_train(crtc);
2c07245f 3054
572deb37
DV		 3055 /* XXX: pch pll's can be enabled any time before we enable the PCH
3056 * transcoder, and we actually should do this to not upset any PCH
3057 * transcoder that already use the clock when we share it.
3058 *
3059 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3060 * unconditionally resets the pll - we need that to have the right LVDS
3061 * enable sequence. */
b6b4e185 3062 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3063
303b81e0 3064 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3065 u32 sel;
4b645f14 3066
c98e9dcf 3067 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3068 switch (pipe) {
3069 default:
3070 case 0:
3071 temp |= TRANSA_DPLL_ENABLE;
3072 sel = TRANSA_DPLLB_SEL;
3073 break;
3074 case 1:
3075 temp |= TRANSB_DPLL_ENABLE;
3076 sel = TRANSB_DPLLB_SEL;
3077 break;
3078 case 2:
3079 temp |= TRANSC_DPLL_ENABLE;
3080 sel = TRANSC_DPLLB_SEL;
3081 break;
d64311ab 3082 }
ee7b9f93
JB		 3083 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3084 temp |= sel;
3085 else
3086 temp &= ~sel;
c98e9dcf 3087 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3088 }
5eddb70b 3089
d9b6cb56
JB		 3090 /* set transcoder timing, panel must allow it */
3091 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3092 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3093 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3094 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3095
5eddb70b
CW		 3096 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3097 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3098 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3099 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3100
303b81e0 3101 intel_fdi_normal_train(crtc);
5e84e1a4 3102
c98e9dcf
JB		 3103 /* For PCH DP, enable TRANS_DP_CTL */
3104 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3105 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3106 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3107 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3108 reg = TRANS_DP_CTL(pipe);
3109 temp = I915_READ(reg);
3110 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3111 TRANS_DP_SYNC_MASK |
3112 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3113 temp |= (TRANS_DP_OUTPUT_ENABLE |
3114 TRANS_DP_ENH_FRAMING);
9325c9f0 3115 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3116
3117 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3118 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3119 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3120 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3121
3122 switch (intel_trans_dp_port_sel(crtc)) {
3123 case PCH_DP_B:
5eddb70b 3124 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3125 break;
3126 case PCH_DP_C:
5eddb70b 3127 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3128 break;
3129 case PCH_DP_D:
5eddb70b 3130 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3131 break;
3132 default:
e95d41e1 3133 BUG();
32f9d658 3134 }
2c07245f 3135
5eddb70b 3136 I915_WRITE(reg, temp);
6be4a607 3137 }
b52eb4dc 3138
b8a4f404 3139 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3140}
3141
1507e5bd
PZ		 3142static void lpt_pch_enable(struct drm_crtc *crtc)
3143{
3144 struct drm_device *dev = crtc->dev;
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3147 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3148
daed2dbb 3149 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3150
8c52b5e8 3151 lpt_program_iclkip(crtc);
1507e5bd 3152
0540e488 3153 /* Set transcoder timing. */
daed2dbb
PZ		 3154 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3155 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3156 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3157
daed2dbb
PZ		 3158 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3159 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3160 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3161 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3162
937bb610 3163 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3164}
3165
ee7b9f93
JB		 3166static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3167{
3168 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3169
3170 if (pll == NULL)
3171 return;
3172
3173 if (pll->refcount == 0) {
3174 WARN(1, "bad PCH PLL refcount\n");
3175 return;
3176 }
3177
3178 --pll->refcount;
3179 intel_crtc->pch_pll = NULL;
3180}
3181
3182static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3183{
3184 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3185 struct intel_pch_pll *pll;
3186 int i;
3187
3188 pll = intel_crtc->pch_pll;
3189 if (pll) {
3190 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3191 intel_crtc->base.base.id, pll->pll_reg);
3192 goto prepare;
3193 }
3194
98b6bd99
DV		 3195 if (HAS_PCH_IBX(dev_priv->dev)) {
3196 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3197 i = intel_crtc->pipe;
3198 pll = &dev_priv->pch_plls[i];
3199
3200 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3201 intel_crtc->base.base.id, pll->pll_reg);
3202
3203 goto found;
3204 }
3205
ee7b9f93
JB		 3206 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3207 pll = &dev_priv->pch_plls[i];
3208
3209 /* Only want to check enabled timings first */
3210 if (pll->refcount == 0)
3211 continue;
3212
3213 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3214 fp == I915_READ(pll->fp0_reg)) {
3215 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3216 intel_crtc->base.base.id,
3217 pll->pll_reg, pll->refcount, pll->active);
3218
3219 goto found;
3220 }
3221 }
3222
3223 /* Ok no matching timings, maybe there's a free one? */
3224 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3225 pll = &dev_priv->pch_plls[i];
3226 if (pll->refcount == 0) {
3227 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3228 intel_crtc->base.base.id, pll->pll_reg);
3229 goto found;
3230 }
3231 }
3232
3233 return NULL;
3234
3235found:
3236 intel_crtc->pch_pll = pll;
3237 pll->refcount++;
3238 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3239prepare: /* separate function? */
3240 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3241
e04c7350
CW		 3242 /* Wait for the clocks to stabilize before rewriting the regs */
3243 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3244 POSTING_READ(pll->pll_reg);
3245 udelay(150);
e04c7350
CW		 3246
3247 I915_WRITE(pll->fp0_reg, fp);
3248 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3249 pll->on = false;
3250 return pll;
3251}
3252
d4270e57
JB		 3253void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3254{
3255 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3256 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3257 u32 temp;
3258
3259 temp = I915_READ(dslreg);
3260 udelay(500);
3261 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3262 if (wait_for(I915_READ(dslreg) != temp, 5))
3263 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3264 }
3265}
3266
f67a559d
JB		 3267static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268{
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3272 struct intel_encoder *encoder;
f67a559d
JB		 3273 int pipe = intel_crtc->pipe;
3274 int plane = intel_crtc->plane;
3275 u32 temp;
3276 bool is_pch_port;
3277
08a48469
DV		 3278 WARN_ON(!crtc->enabled);
3279
f67a559d
JB		 3280 if (intel_crtc->active)
3281 return;
3282
3283 intel_crtc->active = true;
3284 intel_update_watermarks(dev);
3285
3286 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3287 temp = I915_READ(PCH_LVDS);
3288 if ((temp & LVDS_PORT_EN) == 0)
3289 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3290 }
3291
fc316cbe 3292 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3293
46b6f814 3294 if (is_pch_port) {
fff367c7
DV		 3295 /* Note: FDI PLL enabling _must_ be done before we enable the
3296 * cpu pipes, hence this is separate from all the other fdi/pch
3297 * enabling. */
88cefb6c 3298 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3299 } else {
3300 assert_fdi_tx_disabled(dev_priv, pipe);
3301 assert_fdi_rx_disabled(dev_priv, pipe);
3302 }
f67a559d 3303
bf49ec8c
DV		 3304 for_each_encoder_on_crtc(dev, crtc, encoder)
3305 if (encoder->pre_enable)
3306 encoder->pre_enable(encoder);
f67a559d
JB		 3307
3308 /* Enable panel fitting for LVDS */
3309 if (dev_priv->pch_pf_size &&
547dc041
JN		 3310 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3311 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3312 /* Force use of hard-coded filter coefficients
3313 * as some pre-programmed values are broken,
3314 * e.g. x201.
3315 */
13888d78
PZ		 3316 if (IS_IVYBRIDGE(dev))
3317 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3318 PF_PIPE_SEL_IVB(pipe));
3319 else
3320 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3321 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3322 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3323 }
3324
9c54c0dd
JB		 3325 /*
3326 * On ILK+ LUT must be loaded before the pipe is running but with
3327 * clocks enabled
3328 */
3329 intel_crtc_load_lut(crtc);
3330
f67a559d
JB		 3331 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3332 intel_enable_plane(dev_priv, plane, pipe);
3333
3334 if (is_pch_port)
3335 ironlake_pch_enable(crtc);
c98e9dcf 3336
d1ebd816 3337 mutex_lock(&dev->struct_mutex);
bed4a673 3338 intel_update_fbc(dev);
d1ebd816
BW		 3339 mutex_unlock(&dev->struct_mutex);
3340
6b383a7f 3341 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3342
fa5c73b1
DV		 3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
61b77ddd
DV		 3345
3346 if (HAS_PCH_CPT(dev))
3347 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3348
3349 /*
3350 * There seems to be a race in PCH platform hw (at least on some
3351 * outputs) where an enabled pipe still completes any pageflip right
3352 * away (as if the pipe is off) instead of waiting for vblank. As soon
3353 * as the first vblank happend, everything works as expected. Hence just
3354 * wait for one vblank before returning to avoid strange things
3355 * happening.
3356 */
3357 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3358}
3359
4f771f10
PZ		 3360static void haswell_crtc_enable(struct drm_crtc *crtc)
3361{
3362 struct drm_device *dev = crtc->dev;
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365 struct intel_encoder *encoder;
3366 int pipe = intel_crtc->pipe;
3367 int plane = intel_crtc->plane;
4f771f10
PZ		 3368 bool is_pch_port;
3369
3370 WARN_ON(!crtc->enabled);
3371
3372 if (intel_crtc->active)
3373 return;
3374
3375 intel_crtc->active = true;
3376 intel_update_watermarks(dev);
3377
fc316cbe 3378 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3379
83616634 3380 if (is_pch_port)
04945641 3381 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3382
3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 if (encoder->pre_enable)
3385 encoder->pre_enable(encoder);
3386
1f544388 3387 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3388
1f544388 3389 /* Enable panel fitting for eDP */
547dc041
JN		 3390 if (dev_priv->pch_pf_size &&
3391 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3392 /* Force use of hard-coded filter coefficients
3393 * as some pre-programmed values are broken,
3394 * e.g. x201.
3395 */
54075a7d
PZ		 3396 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3397 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3398 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3399 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3400 }
3401
3402 /*
3403 * On ILK+ LUT must be loaded before the pipe is running but with
3404 * clocks enabled
3405 */
3406 intel_crtc_load_lut(crtc);
3407
1f544388
PZ		 3408 intel_ddi_set_pipe_settings(crtc);
3409 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3410
3411 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3412 intel_enable_plane(dev_priv, plane, pipe);
3413
3414 if (is_pch_port)
1507e5bd 3415 lpt_pch_enable(crtc);
4f771f10
PZ		 3416
3417 mutex_lock(&dev->struct_mutex);
3418 intel_update_fbc(dev);
3419 mutex_unlock(&dev->struct_mutex);
3420
3421 intel_crtc_update_cursor(crtc, true);
3422
3423 for_each_encoder_on_crtc(dev, crtc, encoder)
3424 encoder->enable(encoder);
3425
4f771f10
PZ		 3426 /*
3427 * There seems to be a race in PCH platform hw (at least on some
3428 * outputs) where an enabled pipe still completes any pageflip right
3429 * away (as if the pipe is off) instead of waiting for vblank. As soon
3430 * as the first vblank happend, everything works as expected. Hence just
3431 * wait for one vblank before returning to avoid strange things
3432 * happening.
3433 */
3434 intel_wait_for_vblank(dev, intel_crtc->pipe);
3435}
3436
6be4a607
JB		 3437static void ironlake_crtc_disable(struct drm_crtc *crtc)
3438{
3439 struct drm_device *dev = crtc->dev;
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3442 struct intel_encoder *encoder;
6be4a607
JB		 3443 int pipe = intel_crtc->pipe;
3444 int plane = intel_crtc->plane;
5eddb70b 3445 u32 reg, temp;
b52eb4dc 3446
ef9c3aee 3447
f7abfe8b
CW		 3448 if (!intel_crtc->active)
3449 return;
3450
ea9d758d
DV		 3451 for_each_encoder_on_crtc(dev, crtc, encoder)
3452 encoder->disable(encoder);
3453
e6c3a2a6 3454 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3455 drm_vblank_off(dev, pipe);
6b383a7f 3456 intel_crtc_update_cursor(crtc, false);
5eddb70b 3457
b24e7179 3458 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3459
973d04f9
CW		 3460 if (dev_priv->cfb_plane == plane)
3461 intel_disable_fbc(dev);
2c07245f 3462
b24e7179 3463 intel_disable_pipe(dev_priv, pipe);
32f9d658 3464
6be4a607 3465 /* Disable PF */
9db4a9c7
JB		 3466 I915_WRITE(PF_CTL(pipe), 0);
3467 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3468
bf49ec8c
DV		 3469 for_each_encoder_on_crtc(dev, crtc, encoder)
3470 if (encoder->post_disable)
3471 encoder->post_disable(encoder);
2c07245f 3472
0fc932b8 3473 ironlake_fdi_disable(crtc);
249c0e64 3474
b8a4f404 3475 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3476
6be4a607
JB		 3477 if (HAS_PCH_CPT(dev)) {
3478 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3479 reg = TRANS_DP_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3482 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3483 I915_WRITE(reg, temp);
6be4a607
JB		 3484
3485 /* disable DPLL_SEL */
3486 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3487 switch (pipe) {
3488 case 0:
d64311ab 3489 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3490 break;
3491 case 1:
6be4a607 3492 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3493 break;
3494 case 2:
4b645f14 3495 /* C shares PLL A or B */
d64311ab 3496 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3497 break;
3498 default:
3499 BUG(); /* wtf */
3500 }
6be4a607 3501 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3502 }
e3421a18 3503
6be4a607 3504 /* disable PCH DPLL */
ee7b9f93 3505 intel_disable_pch_pll(intel_crtc);
8db9d77b 3506
88cefb6c 3507 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3508
f7abfe8b 3509 intel_crtc->active = false;
6b383a7f 3510 intel_update_watermarks(dev);
d1ebd816
BW		 3511
3512 mutex_lock(&dev->struct_mutex);
6b383a7f 3513 intel_update_fbc(dev);
d1ebd816 3514 mutex_unlock(&dev->struct_mutex);
6be4a607 3515}
1b3c7a47 3516
4f771f10 3517static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3518{
4f771f10
PZ		 3519 struct drm_device *dev = crtc->dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3522 struct intel_encoder *encoder;
3523 int pipe = intel_crtc->pipe;
3524 int plane = intel_crtc->plane;
ad80a810 3525 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3526 bool is_pch_port;
ee7b9f93 3527
4f771f10
PZ		 3528 if (!intel_crtc->active)
3529 return;
3530
83616634
PZ		 3531 is_pch_port = haswell_crtc_driving_pch(crtc);
3532
4f771f10
PZ		 3533 for_each_encoder_on_crtc(dev, crtc, encoder)
3534 encoder->disable(encoder);
3535
3536 intel_crtc_wait_for_pending_flips(crtc);
3537 drm_vblank_off(dev, pipe);
3538 intel_crtc_update_cursor(crtc, false);
3539
3540 intel_disable_plane(dev_priv, plane, pipe);
3541
3542 if (dev_priv->cfb_plane == plane)
3543 intel_disable_fbc(dev);
3544
3545 intel_disable_pipe(dev_priv, pipe);
3546
ad80a810 3547 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3548
3549 /* Disable PF */
3550 I915_WRITE(PF_CTL(pipe), 0);
3551 I915_WRITE(PF_WIN_SZ(pipe), 0);
3552
1f544388 3553 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3554
3555 for_each_encoder_on_crtc(dev, crtc, encoder)
3556 if (encoder->post_disable)
3557 encoder->post_disable(encoder);
3558
83616634 3559 if (is_pch_port) {
ab4d966c 3560 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3561 intel_ddi_fdi_disable(crtc);
83616634 3562 }
4f771f10
PZ		 3563
3564 intel_crtc->active = false;
3565 intel_update_watermarks(dev);
3566
3567 mutex_lock(&dev->struct_mutex);
3568 intel_update_fbc(dev);
3569 mutex_unlock(&dev->struct_mutex);
3570}
3571
ee7b9f93
JB		 3572static void ironlake_crtc_off(struct drm_crtc *crtc)
3573{
3574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3575 intel_put_pch_pll(intel_crtc);
3576}
3577
6441ab5f
PZ		 3578static void haswell_crtc_off(struct drm_crtc *crtc)
3579{
a5c961d1
PZ		 3580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581
3582 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3583 * start using it. */
1a240d4d 3584 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3585
6441ab5f
PZ		 3586 intel_ddi_put_crtc_pll(crtc);
3587}
3588
02e792fb
DV		 3589static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3590{
02e792fb 3591 if (!enable && intel_crtc->overlay) {
23f09ce3 3592 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3593 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3594
23f09ce3 3595 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3596 dev_priv->mm.interruptible = false;
3597 (void) intel_overlay_switch_off(intel_crtc->overlay);
3598 dev_priv->mm.interruptible = true;
23f09ce3 3599 mutex_unlock(&dev->struct_mutex);
02e792fb 3600 }
02e792fb 3601
5dcdbcb0
CW		 3602 /* Let userspace switch the overlay on again. In most cases userspace
3603 * has to recompute where to put it anyway.
3604 */
02e792fb
DV		 3605}
3606
0b8765c6 3607static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3608{
3609 struct drm_device *dev = crtc->dev;
79e53945
JB		 3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3612 struct intel_encoder *encoder;
79e53945 3613 int pipe = intel_crtc->pipe;
80824003 3614 int plane = intel_crtc->plane;
79e53945 3615
08a48469
DV		 3616 WARN_ON(!crtc->enabled);
3617
f7abfe8b
CW		 3618 if (intel_crtc->active)
3619 return;
3620
3621 intel_crtc->active = true;
6b383a7f
CW		 3622 intel_update_watermarks(dev);
3623
63d7bbe9 3624 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3625
3626 for_each_encoder_on_crtc(dev, crtc, encoder)
3627 if (encoder->pre_enable)
3628 encoder->pre_enable(encoder);
3629
040484af 3630 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3631 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3632
0b8765c6 3633 intel_crtc_load_lut(crtc);
bed4a673 3634 intel_update_fbc(dev);
79e53945 3635
0b8765c6
JB		 3636 /* Give the overlay scaler a chance to enable if it's on this pipe */
3637 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3638 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3639
fa5c73b1
DV		 3640 for_each_encoder_on_crtc(dev, crtc, encoder)
3641 encoder->enable(encoder);
0b8765c6 3642}
79e53945 3643
0b8765c6
JB		 3644static void i9xx_crtc_disable(struct drm_crtc *crtc)
3645{
3646 struct drm_device *dev = crtc->dev;
3647 struct drm_i915_private *dev_priv = dev->dev_private;
3648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3649 struct intel_encoder *encoder;
0b8765c6
JB		 3650 int pipe = intel_crtc->pipe;
3651 int plane = intel_crtc->plane;
24a1f16d 3652 u32 pctl;
b690e96c 3653
ef9c3aee 3654
f7abfe8b
CW		 3655 if (!intel_crtc->active)
3656 return;
3657
ea9d758d
DV		 3658 for_each_encoder_on_crtc(dev, crtc, encoder)
3659 encoder->disable(encoder);
3660
0b8765c6 3661 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3662 intel_crtc_wait_for_pending_flips(crtc);
3663 drm_vblank_off(dev, pipe);
0b8765c6 3664 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3665 intel_crtc_update_cursor(crtc, false);
0b8765c6 3666
973d04f9
CW		 3667 if (dev_priv->cfb_plane == plane)
3668 intel_disable_fbc(dev);
79e53945 3669
b24e7179 3670 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3671 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3672
3673 /* Disable pannel fitter if it is on this pipe. */
3674 pctl = I915_READ(PFIT_CONTROL);
3675 if ((pctl & PFIT_ENABLE) &&
3676 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3677 I915_WRITE(PFIT_CONTROL, 0);
3678
63d7bbe9 3679 intel_disable_pll(dev_priv, pipe);
0b8765c6 3680
f7abfe8b 3681 intel_crtc->active = false;
6b383a7f
CW		 3682 intel_update_fbc(dev);
3683 intel_update_watermarks(dev);
0b8765c6
JB		 3684}
3685
ee7b9f93
JB		 3686static void i9xx_crtc_off(struct drm_crtc *crtc)
3687{
3688}
3689
976f8a20
DV		 3690static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3691 bool enabled)
2c07245f
ZW		 3692{
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_master_private *master_priv;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696 int pipe = intel_crtc->pipe;
79e53945
JB		 3697
3698 if (!dev->primary->master)
3699 return;
3700
3701 master_priv = dev->primary->master->driver_priv;
3702 if (!master_priv->sarea_priv)
3703 return;
3704
79e53945
JB		 3705 switch (pipe) {
3706 case 0:
3707 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3708 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3709 break;
3710 case 1:
3711 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3712 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3713 break;
3714 default:
9db4a9c7 3715 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3716 break;
3717 }
79e53945
JB		 3718}
3719
976f8a20
DV		 3720/**
3721 * Sets the power management mode of the pipe and plane.
3722 */
3723void intel_crtc_update_dpms(struct drm_crtc *crtc)
3724{
3725 struct drm_device *dev = crtc->dev;
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 struct intel_encoder *intel_encoder;
3728 bool enable = false;
3729
3730 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3731 enable |= intel_encoder->connectors_active;
3732
3733 if (enable)
3734 dev_priv->display.crtc_enable(crtc);
3735 else
3736 dev_priv->display.crtc_disable(crtc);
3737
3738 intel_crtc_update_sarea(crtc, enable);
3739}
3740
3741static void intel_crtc_noop(struct drm_crtc *crtc)
3742{
3743}
3744
cdd59983
CW		 3745static void intel_crtc_disable(struct drm_crtc *crtc)
3746{
cdd59983 3747 struct drm_device *dev = crtc->dev;
976f8a20 3748 struct drm_connector *connector;
ee7b9f93 3749 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3751
976f8a20
DV		 3752 /* crtc should still be enabled when we disable it. */
3753 WARN_ON(!crtc->enabled);
3754
7b9f35a6 3755 intel_crtc->eld_vld = false;
976f8a20
DV		 3756 dev_priv->display.crtc_disable(crtc);
3757 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3758 dev_priv->display.off(crtc);
3759
931872fc
CW		 3760 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3761 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3762
3763 if (crtc->fb) {
3764 mutex_lock(&dev->struct_mutex);
1690e1eb 3765 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3766 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3767 crtc->fb = NULL;
3768 }
3769
3770 /* Update computed state. */
3771 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3772 if (!connector->encoder || !connector->encoder->crtc)
3773 continue;
3774
3775 if (connector->encoder->crtc != crtc)
3776 continue;
3777
3778 connector->dpms = DRM_MODE_DPMS_OFF;
3779 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3780 }
3781}
3782
a261b246 3783void intel_modeset_disable(struct drm_device *dev)
79e53945 3784{
a261b246
DV		 3785 struct drm_crtc *crtc;
3786
3787 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3788 if (crtc->enabled)
3789 intel_crtc_disable(crtc);
3790 }
79e53945
JB		 3791}
3792
1f703855 3793void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3794{
7e7d76c3
JB		 3795}
3796
ea5b213a 3797void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3798{
4ef69c7a 3799 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3800
ea5b213a
CW		 3801 drm_encoder_cleanup(encoder);
3802 kfree(intel_encoder);
7e7d76c3
JB		 3803}
3804
5ab432ef
DV		 3805/* Simple dpms helper for encodres with just one connector, no cloning and only
3806 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3807 * state of the entire output pipe. */
3808void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3809{
5ab432ef
DV		 3810 if (mode == DRM_MODE_DPMS_ON) {
3811 encoder->connectors_active = true;
3812
b2cabb0e 3813 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3814 } else {
3815 encoder->connectors_active = false;
3816
b2cabb0e 3817 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3818 }
79e53945
JB		 3819}
3820
0a91ca29
DV		 3821/* Cross check the actual hw state with our own modeset state tracking (and it's
3822 * internal consistency). */
b980514c 3823static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3824{
0a91ca29
DV		 3825 if (connector->get_hw_state(connector)) {
3826 struct intel_encoder *encoder = connector->encoder;
3827 struct drm_crtc *crtc;
3828 bool encoder_enabled;
3829 enum pipe pipe;
3830
3831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3832 connector->base.base.id,
3833 drm_get_connector_name(&connector->base));
3834
3835 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3836 "wrong connector dpms state\n");
3837 WARN(connector->base.encoder != &encoder->base,
3838 "active connector not linked to encoder\n");
3839 WARN(!encoder->connectors_active,
3840 "encoder->connectors_active not set\n");
3841
3842 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3843 WARN(!encoder_enabled, "encoder not enabled\n");
3844 if (WARN_ON(!encoder->base.crtc))
3845 return;
3846
3847 crtc = encoder->base.crtc;
3848
3849 WARN(!crtc->enabled, "crtc not enabled\n");
3850 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3851 WARN(pipe != to_intel_crtc(crtc)->pipe,
3852 "encoder active on the wrong pipe\n");
3853 }
79e53945
JB		 3854}
3855
5ab432ef
DV		 3856/* Even simpler default implementation, if there's really no special case to
3857 * consider. */
3858void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3859{
5ab432ef 3860 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3861
5ab432ef
DV		 3862 /* All the simple cases only support two dpms states. */
3863 if (mode != DRM_MODE_DPMS_ON)
3864 mode = DRM_MODE_DPMS_OFF;
d4270e57 3865
5ab432ef
DV		 3866 if (mode == connector->dpms)
3867 return;
3868
3869 connector->dpms = mode;
3870
3871 /* Only need to change hw state when actually enabled */
3872 if (encoder->base.crtc)
3873 intel_encoder_dpms(encoder, mode);
3874 else
8af6cf88 3875 WARN_ON(encoder->connectors_active != false);
0a91ca29 3876
b980514c 3877 intel_modeset_check_state(connector->dev);
79e53945
JB		 3878}
3879
f0947c37
DV		 3880/* Simple connector->get_hw_state implementation for encoders that support only
3881 * one connector and no cloning and hence the encoder state determines the state
3882 * of the connector. */
3883bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3884{
24929352 3885 enum pipe pipe = 0;
f0947c37 3886 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3887
f0947c37 3888 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3889}
3890
79e53945 3891static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3892 const struct drm_display_mode *mode,
79e53945
JB		 3893 struct drm_display_mode *adjusted_mode)
3894{
2c07245f 3895 struct drm_device *dev = crtc->dev;
89749350 3896
bad720ff 3897 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3898 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3899 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3900 return false;
2c07245f 3901 }
89749350 3902
f9bef081
DV		 3903 /* All interlaced capable intel hw wants timings in frames. Note though
3904 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3905 * timings, so we need to be careful not to clobber these.*/
3906 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3907 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3908
44f46b42
CW		 3909 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3910 * with a hsync front porch of 0.
3911 */
3912 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3913 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3914 return false;
3915
79e53945
JB		 3916 return true;
3917}
3918
25eb05fc
JB		 3919static int valleyview_get_display_clock_speed(struct drm_device *dev)
3920{
3921 return 400000; /* FIXME */
3922}
3923
e70236a8
JB		 3924static int i945_get_display_clock_speed(struct drm_device *dev)
3925{
3926 return 400000;
3927}
79e53945 3928
e70236a8 3929static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3930{
e70236a8
JB		 3931 return 333000;
3932}
79e53945 3933
e70236a8
JB		 3934static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3935{
3936 return 200000;
3937}
79e53945 3938
e70236a8
JB		 3939static int i915gm_get_display_clock_speed(struct drm_device *dev)
3940{
3941 u16 gcfgc = 0;
79e53945 3942
e70236a8
JB		 3943 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3944
3945 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3946 return 133000;
3947 else {
3948 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3949 case GC_DISPLAY_CLOCK_333_MHZ:
3950 return 333000;
3951 default:
3952 case GC_DISPLAY_CLOCK_190_200_MHZ:
3953 return 190000;
79e53945 3954 }
e70236a8
JB		 3955 }
3956}
3957
3958static int i865_get_display_clock_speed(struct drm_device *dev)
3959{
3960 return 266000;
3961}
3962
3963static int i855_get_display_clock_speed(struct drm_device *dev)
3964{
3965 u16 hpllcc = 0;
3966 /* Assume that the hardware is in the high speed state. This
3967 * should be the default.
3968 */
3969 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3970 case GC_CLOCK_133_200:
3971 case GC_CLOCK_100_200:
3972 return 200000;
3973 case GC_CLOCK_166_250:
3974 return 250000;
3975 case GC_CLOCK_100_133:
79e53945 3976 return 133000;
e70236a8 3977 }
79e53945 3978
e70236a8
JB		 3979 /* Shouldn't happen */
3980 return 0;
3981}
79e53945 3982
e70236a8
JB		 3983static int i830_get_display_clock_speed(struct drm_device *dev)
3984{
3985 return 133000;
79e53945
JB		 3986}
3987
2c07245f 3988static void
e69d0bc1 3989intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3990{
3991 while (*num > 0xffffff || *den > 0xffffff) {
3992 *num >>= 1;
3993 *den >>= 1;
3994 }
3995}
3996
e69d0bc1
DV		 3997void
3998intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3999 int pixel_clock, int link_clock,
4000 struct intel_link_m_n *m_n)
2c07245f 4001{
e69d0bc1 4002 m_n->tu = 64;
22ed1113
CW		 4003 m_n->gmch_m = bits_per_pixel * pixel_clock;
4004 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4005 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4006 m_n->link_m = pixel_clock;
4007 m_n->link_n = link_clock;
e69d0bc1 4008 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4009}
4010
a7615030
CW		 4011static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4012{
72bbe58c
KP		 4013 if (i915_panel_use_ssc >= 0)
4014 return i915_panel_use_ssc != 0;
4015 return dev_priv->lvds_use_ssc
435793df 4016 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4017}
4018
5a354204
JB		 4019/**
4020 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4021 * @crtc: CRTC structure
3b5c78a3 4022 * @mode: requested mode
5a354204
JB		 4023 *
4024 * A pipe may be connected to one or more outputs. Based on the depth of the
4025 * attached framebuffer, choose a good color depth to use on the pipe.
4026 *
4027 * If possible, match the pipe depth to the fb depth. In some cases, this
4028 * isn't ideal, because the connected output supports a lesser or restricted
4029 * set of depths. Resolve that here:
4030 * LVDS typically supports only 6bpc, so clamp down in that case
4031 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4032 * Displays may support a restricted set as well, check EDID and clamp as
4033 * appropriate.
3b5c78a3 4034 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4035 *
4036 * RETURNS:
4037 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4038 * true if they don't match).
4039 */
4040static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4041 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4042 unsigned int *pipe_bpp,
4043 struct drm_display_mode *mode)
5a354204
JB		 4044{
4045 struct drm_device *dev = crtc->dev;
4046 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4047 struct drm_connector *connector;
6c2b7c12 4048 struct intel_encoder *intel_encoder;
5a354204
JB		 4049 unsigned int display_bpc = UINT_MAX, bpc;
4050
4051 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4052 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4053
4054 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4055 unsigned int lvds_bpc;
4056
4057 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4058 LVDS_A3_POWER_UP)
4059 lvds_bpc = 8;
4060 else
4061 lvds_bpc = 6;
4062
4063 if (lvds_bpc < display_bpc) {
82820490 4064 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4065 display_bpc = lvds_bpc;
4066 }
4067 continue;
4068 }
4069
5a354204
JB		 4070 /* Not one of the known troublemakers, check the EDID */
4071 list_for_each_entry(connector, &dev->mode_config.connector_list,
4072 head) {
6c2b7c12 4073 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4074 continue;
4075
62ac41a6
JB		 4076 /* Don't use an invalid EDID bpc value */
4077 if (connector->display_info.bpc &&
4078 connector->display_info.bpc < display_bpc) {
82820490 4079 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4080 display_bpc = connector->display_info.bpc;
4081 }
4082 }
4083
2f4f649a
JN		 4084 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4085 /* Use VBT settings if we have an eDP panel */
4086 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4087
9a30a61f 4088 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4089 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4090 display_bpc = edp_bpc;
4091 }
4092 continue;
4093 }
4094
5a354204
JB		 4095 /*
4096 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4097 * through, clamp it down. (Note: >12bpc will be caught below.)
4098 */
4099 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4100 if (display_bpc > 8 && display_bpc < 12) {
82820490 4101 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4102 display_bpc = 12;
4103 } else {
82820490 4104 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4105 display_bpc = 8;
4106 }
4107 }
4108 }
4109
3b5c78a3
AJ		 4110 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4111 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4112 display_bpc = 6;
4113 }
4114
5a354204
JB		 4115 /*
4116 * We could just drive the pipe at the highest bpc all the time and
4117 * enable dithering as needed, but that costs bandwidth. So choose
4118 * the minimum value that expresses the full color range of the fb but
4119 * also stays within the max display bpc discovered above.
4120 */
4121
94352cf9 4122 switch (fb->depth) {
5a354204
JB		 4123 case 8:
4124 bpc = 8; /* since we go through a colormap */
4125 break;
4126 case 15:
4127 case 16:
4128 bpc = 6; /* min is 18bpp */
4129 break;
4130 case 24:
578393cd 4131 bpc = 8;
5a354204
JB		 4132 break;
4133 case 30:
578393cd 4134 bpc = 10;
5a354204
JB		 4135 break;
4136 case 48:
578393cd 4137 bpc = 12;
5a354204
JB		 4138 break;
4139 default:
4140 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4141 bpc = min((unsigned int)8, display_bpc);
4142 break;
4143 }
4144
578393cd
KP		 4145 display_bpc = min(display_bpc, bpc);
4146
82820490
AJ		 4147 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4148 bpc, display_bpc);
5a354204 4149
578393cd 4150 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4151
4152 return display_bpc != bpc;
4153}
4154
a0c4da24
JB		 4155static int vlv_get_refclk(struct drm_crtc *crtc)
4156{
4157 struct drm_device *dev = crtc->dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159 int refclk = 27000; /* for DP & HDMI */
4160
4161 return 100000; /* only one validated so far */
4162
4163 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4164 refclk = 96000;
4165 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4166 if (intel_panel_use_ssc(dev_priv))
4167 refclk = 100000;
4168 else
4169 refclk = 96000;
4170 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4171 refclk = 100000;
4172 }
4173
4174 return refclk;
4175}
4176
c65d77d8
JB		 4177static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4178{
4179 struct drm_device *dev = crtc->dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181 int refclk;
4182
a0c4da24
JB		 4183 if (IS_VALLEYVIEW(dev)) {
4184 refclk = vlv_get_refclk(crtc);
4185 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4186 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4187 refclk = dev_priv->lvds_ssc_freq * 1000;
4188 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4189 refclk / 1000);
4190 } else if (!IS_GEN2(dev)) {
4191 refclk = 96000;
4192 } else {
4193 refclk = 48000;
4194 }
4195
4196 return refclk;
4197}
4198
4199static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4200 intel_clock_t *clock)
4201{
4202 /* SDVO TV has fixed PLL values depend on its clock range,
4203 this mirrors vbios setting. */
4204 if (adjusted_mode->clock >= 100000
4205 && adjusted_mode->clock < 140500) {
4206 clock->p1 = 2;
4207 clock->p2 = 10;
4208 clock->n = 3;
4209 clock->m1 = 16;
4210 clock->m2 = 8;
4211 } else if (adjusted_mode->clock >= 140500
4212 && adjusted_mode->clock <= 200000) {
4213 clock->p1 = 1;
4214 clock->p2 = 10;
4215 clock->n = 6;
4216 clock->m1 = 12;
4217 clock->m2 = 8;
4218 }
4219}
4220
a7516a05
JB		 4221static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4222 intel_clock_t *clock,
4223 intel_clock_t *reduced_clock)
4224{
4225 struct drm_device *dev = crtc->dev;
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4228 int pipe = intel_crtc->pipe;
4229 u32 fp, fp2 = 0;
4230
4231 if (IS_PINEVIEW(dev)) {
4232 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4233 if (reduced_clock)
4234 fp2 = (1 << reduced_clock->n) << 16 |
4235 reduced_clock->m1 << 8 | reduced_clock->m2;
4236 } else {
4237 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4238 if (reduced_clock)
4239 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4240 reduced_clock->m2;
4241 }
4242
4243 I915_WRITE(FP0(pipe), fp);
4244
4245 intel_crtc->lowfreq_avail = false;
4246 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4247 reduced_clock && i915_powersave) {
4248 I915_WRITE(FP1(pipe), fp2);
4249 intel_crtc->lowfreq_avail = true;
4250 } else {
4251 I915_WRITE(FP1(pipe), fp);
4252 }
4253}
4254
a0c4da24
JB		 4255static void vlv_update_pll(struct drm_crtc *crtc,
4256 struct drm_display_mode *mode,
4257 struct drm_display_mode *adjusted_mode,
4258 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4259 int num_connectors)
a0c4da24
JB		 4260{
4261 struct drm_device *dev = crtc->dev;
4262 struct drm_i915_private *dev_priv = dev->dev_private;
4263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4264 int pipe = intel_crtc->pipe;
4265 u32 dpll, mdiv, pdiv;
4266 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4267 bool is_sdvo;
4268 u32 temp;
a0c4da24 4269
09153000
DV		 4270 mutex_lock(&dev_priv->dpio_lock);
4271
2a8f64ca
VP		 4272 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4273 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4274
2a8f64ca
VP		 4275 dpll = DPLL_VGA_MODE_DIS;
4276 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4277 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4278 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4279
4280 I915_WRITE(DPLL(pipe), dpll);
4281 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4282
4283 bestn = clock->n;
4284 bestm1 = clock->m1;
4285 bestm2 = clock->m2;
4286 bestp1 = clock->p1;
4287 bestp2 = clock->p2;
4288
2a8f64ca
VP		 4289 /*
4290 * In Valleyview PLL and program lane counter registers are exposed
4291 * through DPIO interface
4292 */
a0c4da24
JB		 4293 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4294 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4295 mdiv |= ((bestn << DPIO_N_SHIFT));
4296 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4297 mdiv |= (1 << DPIO_K_SHIFT);
4298 mdiv |= DPIO_ENABLE_CALIBRATION;
4299 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4300
4301 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4302
2a8f64ca 4303 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4304 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4305 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4306 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4307 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4308
2a8f64ca 4309 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4310
4311 dpll |= DPLL_VCO_ENABLE;
4312 I915_WRITE(DPLL(pipe), dpll);
4313 POSTING_READ(DPLL(pipe));
4314 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4315 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4316
2a8f64ca
VP		 4317 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4318
4319 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4320 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4321
4322 I915_WRITE(DPLL(pipe), dpll);
4323
4324 /* Wait for the clocks to stabilize. */
4325 POSTING_READ(DPLL(pipe));
4326 udelay(150);
a0c4da24 4327
2a8f64ca
VP		 4328 temp = 0;
4329 if (is_sdvo) {
4330 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4331 if (temp > 1)
4332 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4333 else
4334 temp = 0;
a0c4da24 4335 }
2a8f64ca
VP		 4336 I915_WRITE(DPLL_MD(pipe), temp);
4337 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4338
2a8f64ca
VP		 4339 /* Now program lane control registers */
4340 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4341 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4342 {
4343 temp = 0x1000C4;
4344 if(pipe == 1)
4345 temp |= (1 << 21);
4346 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4347 }
4348 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4349 {
4350 temp = 0x1000C4;
4351 if(pipe == 1)
4352 temp |= (1 << 21);
4353 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4354 }
09153000
DV		 4355
4356 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4357}
4358
eb1cbe48
DV		 4359static void i9xx_update_pll(struct drm_crtc *crtc,
4360 struct drm_display_mode *mode,
4361 struct drm_display_mode *adjusted_mode,
4362 intel_clock_t *clock, intel_clock_t *reduced_clock,
4363 int num_connectors)
4364{
4365 struct drm_device *dev = crtc->dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4368 struct intel_encoder *encoder;
eb1cbe48
DV		 4369 int pipe = intel_crtc->pipe;
4370 u32 dpll;
4371 bool is_sdvo;
4372
2a8f64ca
VP		 4373 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4374
eb1cbe48
DV		 4375 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4376 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4377
4378 dpll = DPLL_VGA_MODE_DIS;
4379
4380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4381 dpll |= DPLLB_MODE_LVDS;
4382 else
4383 dpll |= DPLLB_MODE_DAC_SERIAL;
4384 if (is_sdvo) {
4385 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4386 if (pixel_multiplier > 1) {
4387 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4388 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4389 }
4390 dpll |= DPLL_DVO_HIGH_SPEED;
4391 }
4392 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4393 dpll |= DPLL_DVO_HIGH_SPEED;
4394
4395 /* compute bitmask from p1 value */
4396 if (IS_PINEVIEW(dev))
4397 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4398 else {
4399 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4400 if (IS_G4X(dev) && reduced_clock)
4401 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4402 }
4403 switch (clock->p2) {
4404 case 5:
4405 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4406 break;
4407 case 7:
4408 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4409 break;
4410 case 10:
4411 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4412 break;
4413 case 14:
4414 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4415 break;
4416 }
4417 if (INTEL_INFO(dev)->gen >= 4)
4418 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4419
4420 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4421 dpll |= PLL_REF_INPUT_TVCLKINBC;
4422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4423 /* XXX: just matching BIOS for now */
4424 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4425 dpll |= 3;
4426 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4427 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4428 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4429 else
4430 dpll |= PLL_REF_INPUT_DREFCLK;
4431
4432 dpll |= DPLL_VCO_ENABLE;
4433 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4434 POSTING_READ(DPLL(pipe));
4435 udelay(150);
4436
dafd226c
DV		 4437 for_each_encoder_on_crtc(dev, crtc, encoder)
4438 if (encoder->pre_pll_enable)
4439 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4440
4441 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4442 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4443
4444 I915_WRITE(DPLL(pipe), dpll);
4445
4446 /* Wait for the clocks to stabilize. */
4447 POSTING_READ(DPLL(pipe));
4448 udelay(150);
4449
4450 if (INTEL_INFO(dev)->gen >= 4) {
4451 u32 temp = 0;
4452 if (is_sdvo) {
4453 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4454 if (temp > 1)
4455 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4456 else
4457 temp = 0;
4458 }
4459 I915_WRITE(DPLL_MD(pipe), temp);
4460 } else {
4461 /* The pixel multiplier can only be updated once the
4462 * DPLL is enabled and the clocks are stable.
4463 *
4464 * So write it again.
4465 */
4466 I915_WRITE(DPLL(pipe), dpll);
4467 }
4468}
4469
4470static void i8xx_update_pll(struct drm_crtc *crtc,
4471 struct drm_display_mode *adjusted_mode,
2a8f64ca 4472 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4473 int num_connectors)
4474{
4475 struct drm_device *dev = crtc->dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4478 struct intel_encoder *encoder;
eb1cbe48
DV		 4479 int pipe = intel_crtc->pipe;
4480 u32 dpll;
4481
2a8f64ca
VP		 4482 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4483
eb1cbe48
DV		 4484 dpll = DPLL_VGA_MODE_DIS;
4485
4486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4487 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4488 } else {
4489 if (clock->p1 == 2)
4490 dpll |= PLL_P1_DIVIDE_BY_TWO;
4491 else
4492 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4493 if (clock->p2 == 4)
4494 dpll |= PLL_P2_DIVIDE_BY_4;
4495 }
4496
4497 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4498 /* XXX: just matching BIOS for now */
4499 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4500 dpll |= 3;
4501 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4502 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4503 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4504 else
4505 dpll |= PLL_REF_INPUT_DREFCLK;
4506
4507 dpll |= DPLL_VCO_ENABLE;
4508 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4509 POSTING_READ(DPLL(pipe));
4510 udelay(150);
4511
dafd226c
DV		 4512 for_each_encoder_on_crtc(dev, crtc, encoder)
4513 if (encoder->pre_pll_enable)
4514 encoder->pre_pll_enable(encoder);
eb1cbe48 4515
5b5896e4
DV		 4516 I915_WRITE(DPLL(pipe), dpll);
4517
4518 /* Wait for the clocks to stabilize. */
4519 POSTING_READ(DPLL(pipe));
4520 udelay(150);
4521
eb1cbe48
DV		 4522 /* The pixel multiplier can only be updated once the
4523 * DPLL is enabled and the clocks are stable.
4524 *
4525 * So write it again.
4526 */
4527 I915_WRITE(DPLL(pipe), dpll);
4528}
4529
b0e77b9c
PZ		 4530static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4531 struct drm_display_mode *mode,
4532 struct drm_display_mode *adjusted_mode)
4533{
4534 struct drm_device *dev = intel_crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4537 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4538 uint32_t vsyncshift;
4539
4540 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4541 /* the chip adds 2 halflines automatically */
4542 adjusted_mode->crtc_vtotal -= 1;
4543 adjusted_mode->crtc_vblank_end -= 1;
4544 vsyncshift = adjusted_mode->crtc_hsync_start
4545 - adjusted_mode->crtc_htotal / 2;
4546 } else {
4547 vsyncshift = 0;
4548 }
4549
4550 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4551 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4552
fe2b8f9d 4553 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4554 (adjusted_mode->crtc_hdisplay - 1) |
4555 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4556 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4557 (adjusted_mode->crtc_hblank_start - 1) |
4558 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4559 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4560 (adjusted_mode->crtc_hsync_start - 1) |
4561 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4562
fe2b8f9d 4563 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4564 (adjusted_mode->crtc_vdisplay - 1) |
4565 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4566 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4567 (adjusted_mode->crtc_vblank_start - 1) |
4568 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4569 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4570 (adjusted_mode->crtc_vsync_start - 1) |
4571 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4572
b5e508d4
PZ		 4573 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4574 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4575 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4576 * bits. */
4577 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4578 (pipe == PIPE_B || pipe == PIPE_C))
4579 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4580
b0e77b9c
PZ		 4581 /* pipesrc controls the size that is scaled from, which should
4582 * always be the user's requested size.
4583 */
4584 I915_WRITE(PIPESRC(pipe),
4585 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4586}
4587
f564048e
EA		 4588static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4589 struct drm_display_mode *mode,
4590 struct drm_display_mode *adjusted_mode,
4591 int x, int y,
94352cf9 4592 struct drm_framebuffer *fb)
79e53945
JB		 4593{
4594 struct drm_device *dev = crtc->dev;
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597 int pipe = intel_crtc->pipe;
80824003 4598 int plane = intel_crtc->plane;
c751ce4f 4599 int refclk, num_connectors = 0;
652c393a 4600 intel_clock_t clock, reduced_clock;
b0e77b9c 4601 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4602 bool ok, has_reduced_clock = false, is_sdvo = false;
4603 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4604 struct intel_encoder *encoder;
d4906093 4605 const intel_limit_t *limit;
5c3b82e2 4606 int ret;
79e53945 4607
6c2b7c12 4608 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4609 switch (encoder->type) {
79e53945
JB		 4610 case INTEL_OUTPUT_LVDS:
4611 is_lvds = true;
4612 break;
4613 case INTEL_OUTPUT_SDVO:
7d57382e 4614 case INTEL_OUTPUT_HDMI:
79e53945 4615 is_sdvo = true;
5eddb70b 4616 if (encoder->needs_tv_clock)
e2f0ba97 4617 is_tv = true;
79e53945 4618 break;
79e53945
JB		 4619 case INTEL_OUTPUT_TVOUT:
4620 is_tv = true;
4621 break;
a4fc5ed6
KP		 4622 case INTEL_OUTPUT_DISPLAYPORT:
4623 is_dp = true;
4624 break;
79e53945 4625 }
43565a06 4626
c751ce4f 4627 num_connectors++;
79e53945
JB		 4628 }
4629
c65d77d8 4630 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4631
d4906093
ML		 4632 /*
4633 * Returns a set of divisors for the desired target clock with the given
4634 * refclk, or FALSE. The returned values represent the clock equation:
4635 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4636 */
1b894b59 4637 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4638 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4639 &clock);
79e53945
JB		 4640 if (!ok) {
4641 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4642 return -EINVAL;
79e53945
JB		 4643 }
4644
cda4b7d3 4645 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4646 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4647
ddc9003c 4648 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4649 /*
4650 * Ensure we match the reduced clock's P to the target clock.
4651 * If the clocks don't match, we can't switch the display clock
4652 * by using the FP0/FP1. In such case we will disable the LVDS
4653 * downclock feature.
4654 */
ddc9003c 4655 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4656 dev_priv->lvds_downclock,
4657 refclk,
cec2f356 4658 &clock,
5eddb70b 4659 &reduced_clock);
7026d4ac
ZW		 4660 }
4661
c65d77d8
JB		 4662 if (is_sdvo && is_tv)
4663 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4664
eb1cbe48 4665 if (IS_GEN2(dev))
2a8f64ca
VP		 4666 i8xx_update_pll(crtc, adjusted_mode, &clock,
4667 has_reduced_clock ? &reduced_clock : NULL,
4668 num_connectors);
a0c4da24 4669 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4670 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4671 has_reduced_clock ? &reduced_clock : NULL,
4672 num_connectors);
79e53945 4673 else
eb1cbe48
DV		 4674 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4675 has_reduced_clock ? &reduced_clock : NULL,
4676 num_connectors);
79e53945
JB		 4677
4678 /* setup pipeconf */
5eddb70b 4679 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4680
4681 /* Set up the display plane register */
4682 dspcntr = DISPPLANE_GAMMA_ENABLE;
4683
929c77fb
EA		 4684 if (pipe == 0)
4685 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4686 else
4687 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4688
a6c45cf0 4689 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4690 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4691 * core speed.
4692 *
4693 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4694 * pipe == 0 check?
4695 */
e70236a8
JB		 4696 if (mode->clock >
4697 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4698 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4699 else
5eddb70b 4700 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4701 }
4702
3b5c78a3 4703 /* default to 8bpc */
dfd07d72 4704 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4705 if (is_dp) {
0c96c65b 4706 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4707 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4708 PIPECONF_DITHER_EN |
4709 PIPECONF_DITHER_TYPE_SP;
4710 }
4711 }
4712
19c03924
GB		 4713 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4714 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4715 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4716 PIPECONF_ENABLE |
4717 I965_PIPECONF_ACTIVE;
4718 }
4719 }
4720
28c97730 4721 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4722 drm_mode_debug_printmodeline(mode);
4723
a7516a05
JB		 4724 if (HAS_PIPE_CXSR(dev)) {
4725 if (intel_crtc->lowfreq_avail) {
28c97730 4726 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4727 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4728 } else {
28c97730 4729 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4730 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4731 }
4732 }
4733
617cf884 4734 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4735 if (!IS_GEN2(dev) &&
b0e77b9c 4736 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4737 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4738 else
617cf884 4739 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4740
b0e77b9c 4741 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4742
4743 /* pipesrc and dspsize control the size that is scaled from,
4744 * which should always be the user's requested size.
79e53945 4745 */
929c77fb
EA		 4746 I915_WRITE(DSPSIZE(plane),
4747 ((mode->vdisplay - 1) << 16) |
4748 (mode->hdisplay - 1));
4749 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4750
f564048e
EA		 4751 I915_WRITE(PIPECONF(pipe), pipeconf);
4752 POSTING_READ(PIPECONF(pipe));
929c77fb 4753 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4754
4755 intel_wait_for_vblank(dev, pipe);
4756
f564048e
EA		 4757 I915_WRITE(DSPCNTR(plane), dspcntr);
4758 POSTING_READ(DSPCNTR(plane));
4759
94352cf9 4760 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4761
4762 intel_update_watermarks(dev);
4763
f564048e
EA		 4764 return ret;
4765}
4766
dde86e2d 4767static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4768{
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4771 struct intel_encoder *encoder;
13d83a67
JB		 4772 u32 temp;
4773 bool has_lvds = false;
199e5d79
KP		 4774 bool has_cpu_edp = false;
4775 bool has_pch_edp = false;
4776 bool has_panel = false;
99eb6a01
KP		 4777 bool has_ck505 = false;
4778 bool can_ssc = false;
13d83a67
JB		 4779
4780 /* We need to take the global config into account */
199e5d79
KP		 4781 list_for_each_entry(encoder, &mode_config->encoder_list,
4782 base.head) {
4783 switch (encoder->type) {
4784 case INTEL_OUTPUT_LVDS:
4785 has_panel = true;
4786 has_lvds = true;
4787 break;
4788 case INTEL_OUTPUT_EDP:
4789 has_panel = true;
4790 if (intel_encoder_is_pch_edp(&encoder->base))
4791 has_pch_edp = true;
4792 else
4793 has_cpu_edp = true;
4794 break;
13d83a67
JB		 4795 }
4796 }
4797
99eb6a01
KP		 4798 if (HAS_PCH_IBX(dev)) {
4799 has_ck505 = dev_priv->display_clock_mode;
4800 can_ssc = has_ck505;
4801 } else {
4802 has_ck505 = false;
4803 can_ssc = true;
4804 }
4805
4806 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4807 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4808 has_ck505);
13d83a67
JB		 4809
4810 /* Ironlake: try to setup display ref clock before DPLL
4811 * enabling. This is only under driver's control after
4812 * PCH B stepping, previous chipset stepping should be
4813 * ignoring this setting.
4814 */
4815 temp = I915_READ(PCH_DREF_CONTROL);
4816 /* Always enable nonspread source */
4817 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4818
99eb6a01
KP		 4819 if (has_ck505)
4820 temp |= DREF_NONSPREAD_CK505_ENABLE;
4821 else
4822 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4823
199e5d79
KP		 4824 if (has_panel) {
4825 temp &= ~DREF_SSC_SOURCE_MASK;
4826 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4827
199e5d79 4828 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4829 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4830 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4831 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4832 } else
4833 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4834
4835 /* Get SSC going before enabling the outputs */
4836 I915_WRITE(PCH_DREF_CONTROL, temp);
4837 POSTING_READ(PCH_DREF_CONTROL);
4838 udelay(200);
4839
13d83a67
JB		 4840 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4841
4842 /* Enable CPU source on CPU attached eDP */
199e5d79 4843 if (has_cpu_edp) {
99eb6a01 4844 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4845 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4846 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4847 }
13d83a67
JB		 4848 else
4849 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4850 } else
4851 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4852
4853 I915_WRITE(PCH_DREF_CONTROL, temp);
4854 POSTING_READ(PCH_DREF_CONTROL);
4855 udelay(200);
4856 } else {
4857 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4858
4859 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4860
4861 /* Turn off CPU output */
4862 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4863
4864 I915_WRITE(PCH_DREF_CONTROL, temp);
4865 POSTING_READ(PCH_DREF_CONTROL);
4866 udelay(200);
4867
4868 /* Turn off the SSC source */
4869 temp &= ~DREF_SSC_SOURCE_MASK;
4870 temp |= DREF_SSC_SOURCE_DISABLE;
4871
4872 /* Turn off SSC1 */
4873 temp &= ~ DREF_SSC1_ENABLE;
4874
13d83a67
JB		 4875 I915_WRITE(PCH_DREF_CONTROL, temp);
4876 POSTING_READ(PCH_DREF_CONTROL);
4877 udelay(200);
4878 }
4879}
4880
dde86e2d
PZ		 4881/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4882static void lpt_init_pch_refclk(struct drm_device *dev)
4883{
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct drm_mode_config *mode_config = &dev->mode_config;
4886 struct intel_encoder *encoder;
4887 bool has_vga = false;
4888 bool is_sdv = false;
4889 u32 tmp;
4890
4891 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4892 switch (encoder->type) {
4893 case INTEL_OUTPUT_ANALOG:
4894 has_vga = true;
4895 break;
4896 }
4897 }
4898
4899 if (!has_vga)
4900 return;
4901
c00db246
DV		 4902 mutex_lock(&dev_priv->dpio_lock);
4903
dde86e2d
PZ		 4904 /* XXX: Rip out SDV support once Haswell ships for real. */
4905 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4906 is_sdv = true;
4907
4908 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4909 tmp &= ~SBI_SSCCTL_DISABLE;
4910 tmp |= SBI_SSCCTL_PATHALT;
4911 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4912
4913 udelay(24);
4914
4915 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4916 tmp &= ~SBI_SSCCTL_PATHALT;
4917 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4918
4919 if (!is_sdv) {
4920 tmp = I915_READ(SOUTH_CHICKEN2);
4921 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4922 I915_WRITE(SOUTH_CHICKEN2, tmp);
4923
4924 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4925 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4926 DRM_ERROR("FDI mPHY reset assert timeout\n");
4927
4928 tmp = I915_READ(SOUTH_CHICKEN2);
4929 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4930 I915_WRITE(SOUTH_CHICKEN2, tmp);
4931
4932 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4933 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4934 100))
4935 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4936 }
4937
4938 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4939 tmp &= ~(0xFF << 24);
4940 tmp |= (0x12 << 24);
4941 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4942
4943 if (!is_sdv) {
4944 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4945 tmp &= ~(0x3 << 6);
4946 tmp |= (1 << 6) | (1 << 0);
4947 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4948 }
4949
4950 if (is_sdv) {
4951 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4952 tmp |= 0x7FFF;
4953 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4954 }
4955
4956 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4957 tmp |= (1 << 11);
4958 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4959
4960 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4961 tmp |= (1 << 11);
4962 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4963
4964 if (is_sdv) {
4965 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4966 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4967 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4968
4969 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4970 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4971 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4972
4973 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4974 tmp |= (0x3F << 8);
4975 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4976
4977 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4978 tmp |= (0x3F << 8);
4979 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4980 }
4981
4982 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4983 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4984 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4985
4986 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4987 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4988 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4989
4990 if (!is_sdv) {
4991 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4992 tmp &= ~(7 << 13);
4993 tmp |= (5 << 13);
4994 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4995
4996 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4997 tmp &= ~(7 << 13);
4998 tmp |= (5 << 13);
4999 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5000 }
5001
5002 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5003 tmp &= ~0xFF;
5004 tmp |= 0x1C;
5005 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5006
5007 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5008 tmp &= ~0xFF;
5009 tmp |= 0x1C;
5010 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5011
5012 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5013 tmp &= ~(0xFF << 16);
5014 tmp |= (0x1C << 16);
5015 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5016
5017 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5018 tmp &= ~(0xFF << 16);
5019 tmp |= (0x1C << 16);
5020 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5021
5022 if (!is_sdv) {
5023 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5024 tmp |= (1 << 27);
5025 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5026
5027 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5028 tmp |= (1 << 27);
5029 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5030
5031 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5032 tmp &= ~(0xF << 28);
5033 tmp |= (4 << 28);
5034 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5035
5036 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5037 tmp &= ~(0xF << 28);
5038 tmp |= (4 << 28);
5039 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5040 }
5041
5042 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5043 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5044 tmp |= SBI_DBUFF0_ENABLE;
5045 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5046
5047 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5048}
5049
5050/*
5051 * Initialize reference clocks when the driver loads
5052 */
5053void intel_init_pch_refclk(struct drm_device *dev)
5054{
5055 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5056 ironlake_init_pch_refclk(dev);
5057 else if (HAS_PCH_LPT(dev))
5058 lpt_init_pch_refclk(dev);
5059}
5060
d9d444cb
JB		 5061static int ironlake_get_refclk(struct drm_crtc *crtc)
5062{
5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_encoder *encoder;
d9d444cb
JB		 5066 struct intel_encoder *edp_encoder = NULL;
5067 int num_connectors = 0;
5068 bool is_lvds = false;
5069
6c2b7c12 5070 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5071 switch (encoder->type) {
5072 case INTEL_OUTPUT_LVDS:
5073 is_lvds = true;
5074 break;
5075 case INTEL_OUTPUT_EDP:
5076 edp_encoder = encoder;
5077 break;
5078 }
5079 num_connectors++;
5080 }
5081
5082 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5083 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5084 dev_priv->lvds_ssc_freq);
5085 return dev_priv->lvds_ssc_freq * 1000;
5086 }
5087
5088 return 120000;
5089}
5090
c8203565 5091static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5092 struct drm_display_mode *adjusted_mode,
c8203565 5093 bool dither)
79e53945 5094{
c8203565 5095 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5097 int pipe = intel_crtc->pipe;
c8203565
PZ		 5098 uint32_t val;
5099
5100 val = I915_READ(PIPECONF(pipe));
5101
dfd07d72 5102 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5103 switch (intel_crtc->bpp) {
5104 case 18:
dfd07d72 5105 val |= PIPECONF_6BPC;
c8203565
PZ		 5106 break;
5107 case 24:
dfd07d72 5108 val |= PIPECONF_8BPC;
c8203565
PZ		 5109 break;
5110 case 30:
dfd07d72 5111 val |= PIPECONF_10BPC;
c8203565
PZ		 5112 break;
5113 case 36:
dfd07d72 5114 val |= PIPECONF_12BPC;
c8203565
PZ		 5115 break;
5116 default:
cc769b62
PZ		 5117 /* Case prevented by intel_choose_pipe_bpp_dither. */
5118 BUG();
c8203565
PZ		 5119 }
5120
5121 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5122 if (dither)
5123 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5124
5125 val &= ~PIPECONF_INTERLACE_MASK;
5126 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5127 val |= PIPECONF_INTERLACED_ILK;
5128 else
5129 val |= PIPECONF_PROGRESSIVE;
5130
3685a8f3
VS		 5131 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5132 val |= PIPECONF_COLOR_RANGE_SELECT;
5133 else
5134 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5135
c8203565
PZ		 5136 I915_WRITE(PIPECONF(pipe), val);
5137 POSTING_READ(PIPECONF(pipe));
5138}
5139
86d3efce
VS		 5140/*
5141 * Set up the pipe CSC unit.
5142 *
5143 * Currently only full range RGB to limited range RGB conversion
5144 * is supported, but eventually this should handle various
5145 * RGB<->YCbCr scenarios as well.
5146 */
5147static void intel_set_pipe_csc(struct drm_crtc *crtc,
5148 const struct drm_display_mode *adjusted_mode)
5149{
5150 struct drm_device *dev = crtc->dev;
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153 int pipe = intel_crtc->pipe;
5154 uint16_t coeff = 0x7800; /* 1.0 */
5155
5156 /*
5157 * TODO: Check what kind of values actually come out of the pipe
5158 * with these coeff/postoff values and adjust to get the best
5159 * accuracy. Perhaps we even need to take the bpc value into
5160 * consideration.
5161 */
5162
5163 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5164 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5165
5166 /*
5167 * GY/GU and RY/RU should be the other way around according
5168 * to BSpec, but reality doesn't agree. Just set them up in
5169 * a way that results in the correct picture.
5170 */
5171 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5172 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5173
5174 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5175 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5176
5177 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5178 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5179
5180 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5181 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5182 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5183
5184 if (INTEL_INFO(dev)->gen > 6) {
5185 uint16_t postoff = 0;
5186
5187 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5188 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5189
5190 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5191 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5192 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5193
5194 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5195 } else {
5196 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5197
5198 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5199 mode |= CSC_BLACK_SCREEN_OFFSET;
5200
5201 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5202 }
5203}
5204
ee2b0b38
PZ		 5205static void haswell_set_pipeconf(struct drm_crtc *crtc,
5206 struct drm_display_mode *adjusted_mode,
5207 bool dither)
5208{
5209 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5211 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5212 uint32_t val;
5213
702e7a56 5214 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5215
5216 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5217 if (dither)
5218 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5219
5220 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5221 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5222 val |= PIPECONF_INTERLACED_ILK;
5223 else
5224 val |= PIPECONF_PROGRESSIVE;
5225
702e7a56
PZ		 5226 I915_WRITE(PIPECONF(cpu_transcoder), val);
5227 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5228}
5229
6591c6e4
PZ		 5230static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5231 struct drm_display_mode *adjusted_mode,
5232 intel_clock_t *clock,
5233 bool *has_reduced_clock,
5234 intel_clock_t *reduced_clock)
5235{
5236 struct drm_device *dev = crtc->dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct intel_encoder *intel_encoder;
5239 int refclk;
d4906093 5240 const intel_limit_t *limit;
6591c6e4 5241 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5242
6591c6e4
PZ		 5243 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5244 switch (intel_encoder->type) {
79e53945
JB		 5245 case INTEL_OUTPUT_LVDS:
5246 is_lvds = true;
5247 break;
5248 case INTEL_OUTPUT_SDVO:
7d57382e 5249 case INTEL_OUTPUT_HDMI:
79e53945 5250 is_sdvo = true;
6591c6e4 5251 if (intel_encoder->needs_tv_clock)
e2f0ba97 5252 is_tv = true;
79e53945 5253 break;
79e53945
JB		 5254 case INTEL_OUTPUT_TVOUT:
5255 is_tv = true;
5256 break;
79e53945
JB		 5257 }
5258 }
5259
d9d444cb 5260 refclk = ironlake_get_refclk(crtc);
79e53945 5261
d4906093
ML		 5262 /*
5263 * Returns a set of divisors for the desired target clock with the given
5264 * refclk, or FALSE. The returned values represent the clock equation:
5265 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5266 */
1b894b59 5267 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5268 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5269 clock);
5270 if (!ret)
5271 return false;
cda4b7d3 5272
ddc9003c 5273 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5274 /*
5275 * Ensure we match the reduced clock's P to the target clock.
5276 * If the clocks don't match, we can't switch the display clock
5277 * by using the FP0/FP1. In such case we will disable the LVDS
5278 * downclock feature.
5279 */
6591c6e4
PZ		 5280 *has_reduced_clock = limit->find_pll(limit, crtc,
5281 dev_priv->lvds_downclock,
5282 refclk,
5283 clock,
5284 reduced_clock);
652c393a 5285 }
61e9653f
DV		 5286
5287 if (is_sdvo && is_tv)
6591c6e4
PZ		 5288 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5289
5290 return true;
5291}
5292
01a415fd
DV		 5293static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5294{
5295 struct drm_i915_private *dev_priv = dev->dev_private;
5296 uint32_t temp;
5297
5298 temp = I915_READ(SOUTH_CHICKEN1);
5299 if (temp & FDI_BC_BIFURCATION_SELECT)
5300 return;
5301
5302 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5303 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5304
5305 temp |= FDI_BC_BIFURCATION_SELECT;
5306 DRM_DEBUG_KMS("enabling fdi C rx\n");
5307 I915_WRITE(SOUTH_CHICKEN1, temp);
5308 POSTING_READ(SOUTH_CHICKEN1);
5309}
5310
5311static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5312{
5313 struct drm_device *dev = intel_crtc->base.dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct intel_crtc *pipe_B_crtc =
5316 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5317
5318 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5319 intel_crtc->pipe, intel_crtc->fdi_lanes);
5320 if (intel_crtc->fdi_lanes > 4) {
5321 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5322 intel_crtc->pipe, intel_crtc->fdi_lanes);
5323 /* Clamp lanes to avoid programming the hw with bogus values. */
5324 intel_crtc->fdi_lanes = 4;
5325
5326 return false;
5327 }
5328
5329 if (dev_priv->num_pipe == 2)
5330 return true;
5331
5332 switch (intel_crtc->pipe) {
5333 case PIPE_A:
5334 return true;
5335 case PIPE_B:
5336 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5337 intel_crtc->fdi_lanes > 2) {
5338 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5339 intel_crtc->pipe, intel_crtc->fdi_lanes);
5340 /* Clamp lanes to avoid programming the hw with bogus values. */
5341 intel_crtc->fdi_lanes = 2;
5342
5343 return false;
5344 }
5345
5346 if (intel_crtc->fdi_lanes > 2)
5347 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5348 else
5349 cpt_enable_fdi_bc_bifurcation(dev);
5350
5351 return true;
5352 case PIPE_C:
5353 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5354 if (intel_crtc->fdi_lanes > 2) {
5355 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5356 intel_crtc->pipe, intel_crtc->fdi_lanes);
5357 /* Clamp lanes to avoid programming the hw with bogus values. */
5358 intel_crtc->fdi_lanes = 2;
5359
5360 return false;
5361 }
5362 } else {
5363 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5364 return false;
5365 }
5366
5367 cpt_enable_fdi_bc_bifurcation(dev);
5368
5369 return true;
5370 default:
5371 BUG();
5372 }
5373}
5374
d4b1931c
PZ		 5375int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5376{
5377 /*
5378 * Account for spread spectrum to avoid
5379 * oversubscribing the link. Max center spread
5380 * is 2.5%; use 5% for safety's sake.
5381 */
5382 u32 bps = target_clock * bpp * 21 / 20;
5383 return bps / (link_bw * 8) + 1;
5384}
5385
f48d8f23
PZ		 5386static void ironlake_set_m_n(struct drm_crtc *crtc,
5387 struct drm_display_mode *mode,
5388 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5389{
5390 struct drm_device *dev = crtc->dev;
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5393 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5394 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5395 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5396 int target_clock, pixel_multiplier, lane, link_bw;
5397 bool is_dp = false, is_cpu_edp = false;
79e53945 5398
f48d8f23
PZ		 5399 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5400 switch (intel_encoder->type) {
a4fc5ed6
KP		 5401 case INTEL_OUTPUT_DISPLAYPORT:
5402 is_dp = true;
5403 break;
32f9d658 5404 case INTEL_OUTPUT_EDP:
e3aef172 5405 is_dp = true;
f48d8f23 5406 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5407 is_cpu_edp = true;
f48d8f23 5408 edp_encoder = intel_encoder;
32f9d658 5409 break;
79e53945 5410 }
79e53945 5411 }
61e9653f 5412
2c07245f 5413 /* FDI link */
8febb297
EA		 5414 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5415 lane = 0;
5416 /* CPU eDP doesn't require FDI link, so just set DP M/N
5417 according to current link config */
e3aef172 5418 if (is_cpu_edp) {
e3aef172 5419 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5420 } else {
8febb297
EA		 5421 /* FDI is a binary signal running at ~2.7GHz, encoding
5422 * each output octet as 10 bits. The actual frequency
5423 * is stored as a divider into a 100MHz clock, and the
5424 * mode pixel clock is stored in units of 1KHz.
5425 * Hence the bw of each lane in terms of the mode signal
5426 * is:
5427 */
5428 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5429 }
58a27471 5430
94bf2ced
DV		 5431 /* [e]DP over FDI requires target mode clock instead of link clock. */
5432 if (edp_encoder)
5433 target_clock = intel_edp_target_clock(edp_encoder, mode);
5434 else if (is_dp)
5435 target_clock = mode->clock;
5436 else
5437 target_clock = adjusted_mode->clock;
5438
d4b1931c
PZ		 5439 if (!lane)
5440 lane = ironlake_get_lanes_required(target_clock, link_bw,
5441 intel_crtc->bpp);
2c07245f 5442
8febb297
EA		 5443 intel_crtc->fdi_lanes = lane;
5444
5445 if (pixel_multiplier > 1)
5446 link_bw *= pixel_multiplier;
e69d0bc1 5447 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5448
afe2fcf5
PZ		 5449 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5450 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5451 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5452 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5453}
5454
de13a2e3
PZ		 5455static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5456 struct drm_display_mode *adjusted_mode,
5457 intel_clock_t *clock, u32 fp)
79e53945 5458{
de13a2e3 5459 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5460 struct drm_device *dev = crtc->dev;
5461 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5462 struct intel_encoder *intel_encoder;
5463 uint32_t dpll;
5464 int factor, pixel_multiplier, num_connectors = 0;
5465 bool is_lvds = false, is_sdvo = false, is_tv = false;
5466 bool is_dp = false, is_cpu_edp = false;
79e53945 5467
de13a2e3
PZ		 5468 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5469 switch (intel_encoder->type) {
79e53945
JB		 5470 case INTEL_OUTPUT_LVDS:
5471 is_lvds = true;
5472 break;
5473 case INTEL_OUTPUT_SDVO:
7d57382e 5474 case INTEL_OUTPUT_HDMI:
79e53945 5475 is_sdvo = true;
de13a2e3 5476 if (intel_encoder->needs_tv_clock)
e2f0ba97 5477 is_tv = true;
79e53945 5478 break;
79e53945
JB		 5479 case INTEL_OUTPUT_TVOUT:
5480 is_tv = true;
5481 break;
a4fc5ed6
KP		 5482 case INTEL_OUTPUT_DISPLAYPORT:
5483 is_dp = true;
5484 break;
32f9d658 5485 case INTEL_OUTPUT_EDP:
e3aef172 5486 is_dp = true;
de13a2e3 5487 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5488 is_cpu_edp = true;
32f9d658 5489 break;
79e53945 5490 }
43565a06 5491
c751ce4f 5492 num_connectors++;
79e53945 5493 }
79e53945 5494
c1858123 5495 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5496 factor = 21;
5497 if (is_lvds) {
5498 if ((intel_panel_use_ssc(dev_priv) &&
5499 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5500 intel_is_dual_link_lvds(dev))
8febb297
EA		 5501 factor = 25;
5502 } else if (is_sdvo && is_tv)
5503 factor = 20;
c1858123 5504
de13a2e3 5505 if (clock->m < factor * clock->n)
8febb297 5506 fp |= FP_CB_TUNE;
2c07245f 5507
5eddb70b 5508 dpll = 0;
2c07245f 5509
a07d6787
EA		 5510 if (is_lvds)
5511 dpll |= DPLLB_MODE_LVDS;
5512 else
5513 dpll |= DPLLB_MODE_DAC_SERIAL;
5514 if (is_sdvo) {
de13a2e3 5515 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5516 if (pixel_multiplier > 1) {
5517 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5518 }
a07d6787
EA		 5519 dpll |= DPLL_DVO_HIGH_SPEED;
5520 }
e3aef172 5521 if (is_dp && !is_cpu_edp)
a07d6787 5522 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5523
a07d6787 5524 /* compute bitmask from p1 value */
de13a2e3 5525 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5526 /* also FPA1 */
de13a2e3 5527 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5528
de13a2e3 5529 switch (clock->p2) {
a07d6787
EA		 5530 case 5:
5531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5532 break;
5533 case 7:
5534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5535 break;
5536 case 10:
5537 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5538 break;
5539 case 14:
5540 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5541 break;
79e53945
JB		 5542 }
5543
43565a06
KH		 5544 if (is_sdvo && is_tv)
5545 dpll |= PLL_REF_INPUT_TVCLKINBC;
5546 else if (is_tv)
79e53945 5547 /* XXX: just matching BIOS for now */
43565a06 5548 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5549 dpll |= 3;
a7615030 5550 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5551 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5552 else
5553 dpll |= PLL_REF_INPUT_DREFCLK;
5554
de13a2e3
PZ		 5555 return dpll;
5556}
5557
5558static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5559 struct drm_display_mode *mode,
5560 struct drm_display_mode *adjusted_mode,
5561 int x, int y,
5562 struct drm_framebuffer *fb)
5563{
5564 struct drm_device *dev = crtc->dev;
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5567 int pipe = intel_crtc->pipe;
5568 int plane = intel_crtc->plane;
5569 int num_connectors = 0;
5570 intel_clock_t clock, reduced_clock;
5571 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5572 bool ok, has_reduced_clock = false;
5573 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5574 struct intel_encoder *encoder;
de13a2e3 5575 int ret;
01a415fd 5576 bool dither, fdi_config_ok;
de13a2e3
PZ		 5577
5578 for_each_encoder_on_crtc(dev, crtc, encoder) {
5579 switch (encoder->type) {
5580 case INTEL_OUTPUT_LVDS:
5581 is_lvds = true;
5582 break;
de13a2e3
PZ		 5583 case INTEL_OUTPUT_DISPLAYPORT:
5584 is_dp = true;
5585 break;
5586 case INTEL_OUTPUT_EDP:
5587 is_dp = true;
e2f12b07 5588 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5589 is_cpu_edp = true;
5590 break;
5591 }
5592
5593 num_connectors++;
a07d6787 5594 }
79e53945 5595
5dc5298b
PZ		 5596 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5597 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5598
de13a2e3
PZ		 5599 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5600 &has_reduced_clock, &reduced_clock);
5601 if (!ok) {
5602 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5603 return -EINVAL;
79e53945
JB		 5604 }
5605
de13a2e3
PZ		 5606 /* Ensure that the cursor is valid for the new mode before changing... */
5607 intel_crtc_update_cursor(crtc, true);
5608
5609 /* determine panel color depth */
c8241969
JN		 5610 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5611 adjusted_mode);
de13a2e3
PZ		 5612 if (is_lvds && dev_priv->lvds_dither)
5613 dither = true;
5614
5615 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5616 if (has_reduced_clock)
5617 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5618 reduced_clock.m2;
5619
5620 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5621
f7cb34d4 5622 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5623 drm_mode_debug_printmodeline(mode);
5624
5dc5298b
PZ		 5625 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5626 if (!is_cpu_edp) {
ee7b9f93 5627 struct intel_pch_pll *pll;
4b645f14 5628
ee7b9f93
JB		 5629 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5630 if (pll == NULL) {
5631 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5632 pipe);
4b645f14
JB		 5633 return -EINVAL;
5634 }
ee7b9f93
JB		 5635 } else
5636 intel_put_pch_pll(intel_crtc);
79e53945 5637
2f0c2ad1 5638 if (is_dp && !is_cpu_edp)
a4fc5ed6 5639 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5640
dafd226c
DV		 5641 for_each_encoder_on_crtc(dev, crtc, encoder)
5642 if (encoder->pre_pll_enable)
5643 encoder->pre_pll_enable(encoder);
79e53945 5644
ee7b9f93
JB		 5645 if (intel_crtc->pch_pll) {
5646 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5647
32f9d658 5648 /* Wait for the clocks to stabilize. */
ee7b9f93 5649 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5650 udelay(150);
5651
8febb297
EA		 5652 /* The pixel multiplier can only be updated once the
5653 * DPLL is enabled and the clocks are stable.
5654 *
5655 * So write it again.
5656 */
ee7b9f93 5657 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5658 }
79e53945 5659
5eddb70b 5660 intel_crtc->lowfreq_avail = false;
ee7b9f93 5661 if (intel_crtc->pch_pll) {
4b645f14 5662 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5663 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5664 intel_crtc->lowfreq_avail = true;
4b645f14 5665 } else {
ee7b9f93 5666 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5667 }
5668 }
5669
b0e77b9c 5670 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5671
01a415fd
DV		 5672 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5673 * ironlake_check_fdi_lanes. */
f48d8f23 5674 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5675
01a415fd 5676 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5677
c8203565 5678 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5679
9d0498a2 5680 intel_wait_for_vblank(dev, pipe);
79e53945 5681
a1f9e77e
PZ		 5682 /* Set up the display plane register */
5683 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5684 POSTING_READ(DSPCNTR(plane));
79e53945 5685
94352cf9 5686 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5687
5688 intel_update_watermarks(dev);
5689
1f8eeabf
ED		 5690 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5691
01a415fd 5692 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5693}
5694
d6dd9eb1
DV		 5695static void haswell_modeset_global_resources(struct drm_device *dev)
5696{
5697 struct drm_i915_private *dev_priv = dev->dev_private;
5698 bool enable = false;
5699 struct intel_crtc *crtc;
5700 struct intel_encoder *encoder;
5701
5702 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5703 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5704 enable = true;
5705 /* XXX: Should check for edp transcoder here, but thanks to init
5706 * sequence that's not yet available. Just in case desktop eDP
5707 * on PORT D is possible on haswell, too. */
5708 }
5709
5710 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5711 base.head) {
5712 if (encoder->type != INTEL_OUTPUT_EDP &&
5713 encoder->connectors_active)
5714 enable = true;
5715 }
5716
5717 /* Even the eDP panel fitter is outside the always-on well. */
5718 if (dev_priv->pch_pf_size)
5719 enable = true;
5720
5721 intel_set_power_well(dev, enable);
5722}
5723
09b4ddf9
PZ		 5724static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5725 struct drm_display_mode *mode,
5726 struct drm_display_mode *adjusted_mode,
5727 int x, int y,
5728 struct drm_framebuffer *fb)
5729{
5730 struct drm_device *dev = crtc->dev;
5731 struct drm_i915_private *dev_priv = dev->dev_private;
5732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5733 int pipe = intel_crtc->pipe;
5734 int plane = intel_crtc->plane;
5735 int num_connectors = 0;
ed7ef439 5736 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5737 struct intel_encoder *encoder;
09b4ddf9
PZ		 5738 int ret;
5739 bool dither;
5740
5741 for_each_encoder_on_crtc(dev, crtc, encoder) {
5742 switch (encoder->type) {
09b4ddf9
PZ		 5743 case INTEL_OUTPUT_DISPLAYPORT:
5744 is_dp = true;
5745 break;
5746 case INTEL_OUTPUT_EDP:
5747 is_dp = true;
5748 if (!intel_encoder_is_pch_edp(&encoder->base))
5749 is_cpu_edp = true;
5750 break;
5751 }
5752
5753 num_connectors++;
5754 }
5755
5dc5298b
PZ		 5756 /* We are not sure yet this won't happen. */
5757 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5758 INTEL_PCH_TYPE(dev));
5759
5760 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5761 num_connectors, pipe_name(pipe));
5762
702e7a56 5763 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5764 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5765
5766 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5767
6441ab5f
PZ		 5768 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5769 return -EINVAL;
5770
09b4ddf9
PZ		 5771 /* Ensure that the cursor is valid for the new mode before changing... */
5772 intel_crtc_update_cursor(crtc, true);
5773
5774 /* determine panel color depth */
c8241969
JN		 5775 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5776 adjusted_mode);
09b4ddf9 5777
09b4ddf9
PZ		 5778 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5779 drm_mode_debug_printmodeline(mode);
5780
ed7ef439 5781 if (is_dp && !is_cpu_edp)
09b4ddf9 5782 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5783
5784 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5785
5786 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5787
1eb8dfec
PZ		 5788 if (!is_dp || is_cpu_edp)
5789 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5790
ee2b0b38 5791 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5792
86d3efce
VS		 5793 intel_set_pipe_csc(crtc, adjusted_mode);
5794
09b4ddf9 5795 /* Set up the display plane register */
86d3efce 5796 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5797 POSTING_READ(DSPCNTR(plane));
5798
5799 ret = intel_pipe_set_base(crtc, x, y, fb);
5800
5801 intel_update_watermarks(dev);
5802
5803 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5804
1f803ee5 5805 return ret;
79e53945
JB		 5806}
5807
f564048e
EA		 5808static int intel_crtc_mode_set(struct drm_crtc *crtc,
5809 struct drm_display_mode *mode,
5810 struct drm_display_mode *adjusted_mode,
5811 int x, int y,
94352cf9 5812 struct drm_framebuffer *fb)
f564048e
EA		 5813{
5814 struct drm_device *dev = crtc->dev;
5815 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5816 struct drm_encoder_helper_funcs *encoder_funcs;
5817 struct intel_encoder *encoder;
0b701d27
EA		 5818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5819 int pipe = intel_crtc->pipe;
f564048e
EA		 5820 int ret;
5821
cc464b2a
PZ		 5822 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5823 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5824 else
5825 intel_crtc->cpu_transcoder = pipe;
5826
0b701d27 5827 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5828
f564048e 5829 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5830 x, y, fb);
79e53945 5831 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5832
9256aa19
DV		 5833 if (ret != 0)
5834 return ret;
5835
5836 for_each_encoder_on_crtc(dev, crtc, encoder) {
5837 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5838 encoder->base.base.id,
5839 drm_get_encoder_name(&encoder->base),
5840 mode->base.id, mode->name);
5841 encoder_funcs = encoder->base.helper_private;
5842 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5843 }
5844
5845 return 0;
79e53945
JB		 5846}
5847
3a9627f4
WF		 5848static bool intel_eld_uptodate(struct drm_connector *connector,
5849 int reg_eldv, uint32_t bits_eldv,
5850 int reg_elda, uint32_t bits_elda,
5851 int reg_edid)
5852{
5853 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5854 uint8_t *eld = connector->eld;
5855 uint32_t i;
5856
5857 i = I915_READ(reg_eldv);
5858 i &= bits_eldv;
5859
5860 if (!eld[0])
5861 return !i;
5862
5863 if (!i)
5864 return false;
5865
5866 i = I915_READ(reg_elda);
5867 i &= ~bits_elda;
5868 I915_WRITE(reg_elda, i);
5869
5870 for (i = 0; i < eld[2]; i++)
5871 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5872 return false;
5873
5874 return true;
5875}
5876
e0dac65e
WF		 5877static void g4x_write_eld(struct drm_connector *connector,
5878 struct drm_crtc *crtc)
5879{
5880 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5881 uint8_t *eld = connector->eld;
5882 uint32_t eldv;
5883 uint32_t len;
5884 uint32_t i;
5885
5886 i = I915_READ(G4X_AUD_VID_DID);
5887
5888 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5889 eldv = G4X_ELDV_DEVCL_DEVBLC;
5890 else
5891 eldv = G4X_ELDV_DEVCTG;
5892
3a9627f4
WF		 5893 if (intel_eld_uptodate(connector,
5894 G4X_AUD_CNTL_ST, eldv,
5895 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5896 G4X_HDMIW_HDMIEDID))
5897 return;
5898
e0dac65e
WF		 5899 i = I915_READ(G4X_AUD_CNTL_ST);
5900 i &= ~(eldv | G4X_ELD_ADDR);
5901 len = (i >> 9) & 0x1f; /* ELD buffer size */
5902 I915_WRITE(G4X_AUD_CNTL_ST, i);
5903
5904 if (!eld[0])
5905 return;
5906
5907 len = min_t(uint8_t, eld[2], len);
5908 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5909 for (i = 0; i < len; i++)
5910 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5911
5912 i = I915_READ(G4X_AUD_CNTL_ST);
5913 i |= eldv;
5914 I915_WRITE(G4X_AUD_CNTL_ST, i);
5915}
5916
83358c85
WX		 5917static void haswell_write_eld(struct drm_connector *connector,
5918 struct drm_crtc *crtc)
5919{
5920 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5921 uint8_t *eld = connector->eld;
5922 struct drm_device *dev = crtc->dev;
7b9f35a6 5923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5924 uint32_t eldv;
5925 uint32_t i;
5926 int len;
5927 int pipe = to_intel_crtc(crtc)->pipe;
5928 int tmp;
5929
5930 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5931 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5932 int aud_config = HSW_AUD_CFG(pipe);
5933 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5934
5935
5936 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5937
5938 /* Audio output enable */
5939 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5940 tmp = I915_READ(aud_cntrl_st2);
5941 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5942 I915_WRITE(aud_cntrl_st2, tmp);
5943
5944 /* Wait for 1 vertical blank */
5945 intel_wait_for_vblank(dev, pipe);
5946
5947 /* Set ELD valid state */
5948 tmp = I915_READ(aud_cntrl_st2);
5949 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5950 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5951 I915_WRITE(aud_cntrl_st2, tmp);
5952 tmp = I915_READ(aud_cntrl_st2);
5953 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5954
5955 /* Enable HDMI mode */
5956 tmp = I915_READ(aud_config);
5957 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5958 /* clear N_programing_enable and N_value_index */
5959 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5960 I915_WRITE(aud_config, tmp);
5961
5962 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5963
5964 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5965 intel_crtc->eld_vld = true;
83358c85
WX		 5966
5967 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5968 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5969 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5970 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5971 } else
5972 I915_WRITE(aud_config, 0);
5973
5974 if (intel_eld_uptodate(connector,
5975 aud_cntrl_st2, eldv,
5976 aud_cntl_st, IBX_ELD_ADDRESS,
5977 hdmiw_hdmiedid))
5978 return;
5979
5980 i = I915_READ(aud_cntrl_st2);
5981 i &= ~eldv;
5982 I915_WRITE(aud_cntrl_st2, i);
5983
5984 if (!eld[0])
5985 return;
5986
5987 i = I915_READ(aud_cntl_st);
5988 i &= ~IBX_ELD_ADDRESS;
5989 I915_WRITE(aud_cntl_st, i);
5990 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5991 DRM_DEBUG_DRIVER("port num:%d\n", i);
5992
5993 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5994 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5995 for (i = 0; i < len; i++)
5996 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5997
5998 i = I915_READ(aud_cntrl_st2);
5999 i |= eldv;
6000 I915_WRITE(aud_cntrl_st2, i);
6001
6002}
6003
e0dac65e
WF		 6004static void ironlake_write_eld(struct drm_connector *connector,
6005 struct drm_crtc *crtc)
6006{
6007 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6008 uint8_t *eld = connector->eld;
6009 uint32_t eldv;
6010 uint32_t i;
6011 int len;
6012 int hdmiw_hdmiedid;
b6daa025 6013 int aud_config;
e0dac65e
WF		 6014 int aud_cntl_st;
6015 int aud_cntrl_st2;
9b138a83 6016 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6017
b3f33cbf 6018 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6019 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6020 aud_config = IBX_AUD_CFG(pipe);
6021 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6022 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6023 } else {
9b138a83
WX		 6024 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6025 aud_config = CPT_AUD_CFG(pipe);
6026 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6027 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6028 }
6029
9b138a83 6030 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6031
6032 i = I915_READ(aud_cntl_st);
9b138a83 6033 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6034 if (!i) {
6035 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6036 /* operate blindly on all ports */
1202b4c6
WF		 6037 eldv = IBX_ELD_VALIDB;
6038 eldv |= IBX_ELD_VALIDB << 4;
6039 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6040 } else {
6041 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6042 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6043 }
6044
3a9627f4
WF		 6045 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6046 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6047 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6048 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6049 } else
6050 I915_WRITE(aud_config, 0);
e0dac65e 6051
3a9627f4
WF		 6052 if (intel_eld_uptodate(connector,
6053 aud_cntrl_st2, eldv,
6054 aud_cntl_st, IBX_ELD_ADDRESS,
6055 hdmiw_hdmiedid))
6056 return;
6057
e0dac65e
WF		 6058 i = I915_READ(aud_cntrl_st2);
6059 i &= ~eldv;
6060 I915_WRITE(aud_cntrl_st2, i);
6061
6062 if (!eld[0])
6063 return;
6064
e0dac65e 6065 i = I915_READ(aud_cntl_st);
1202b4c6 6066 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6067 I915_WRITE(aud_cntl_st, i);
6068
6069 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6070 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6071 for (i = 0; i < len; i++)
6072 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6073
6074 i = I915_READ(aud_cntrl_st2);
6075 i |= eldv;
6076 I915_WRITE(aud_cntrl_st2, i);
6077}
6078
6079void intel_write_eld(struct drm_encoder *encoder,
6080 struct drm_display_mode *mode)
6081{
6082 struct drm_crtc *crtc = encoder->crtc;
6083 struct drm_connector *connector;
6084 struct drm_device *dev = encoder->dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086
6087 connector = drm_select_eld(encoder, mode);
6088 if (!connector)
6089 return;
6090
6091 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6092 connector->base.id,
6093 drm_get_connector_name(connector),
6094 connector->encoder->base.id,
6095 drm_get_encoder_name(connector->encoder));
6096
6097 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6098
6099 if (dev_priv->display.write_eld)
6100 dev_priv->display.write_eld(connector, crtc);
6101}
6102
79e53945
JB		 6103/** Loads the palette/gamma unit for the CRTC with the prepared values */
6104void intel_crtc_load_lut(struct drm_crtc *crtc)
6105{
6106 struct drm_device *dev = crtc->dev;
6107 struct drm_i915_private *dev_priv = dev->dev_private;
6108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6109 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6110 int i;
6111
6112 /* The clocks have to be on to load the palette. */
aed3f09d 6113 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6114 return;
6115
f2b115e6 6116 /* use legacy palette for Ironlake */
bad720ff 6117 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6118 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6119
79e53945
JB		 6120 for (i = 0; i < 256; i++) {
6121 I915_WRITE(palreg + 4 * i,
6122 (intel_crtc->lut_r[i] << 16) |
6123 (intel_crtc->lut_g[i] << 8) |
6124 intel_crtc->lut_b[i]);
6125 }
6126}
6127
560b85bb
CW		 6128static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6129{
6130 struct drm_device *dev = crtc->dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133 bool visible = base != 0;
6134 u32 cntl;
6135
6136 if (intel_crtc->cursor_visible == visible)
6137 return;
6138
9db4a9c7 6139 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6140 if (visible) {
6141 /* On these chipsets we can only modify the base whilst
6142 * the cursor is disabled.
6143 */
9db4a9c7 6144 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6145
6146 cntl &= ~(CURSOR_FORMAT_MASK);
6147 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6148 cntl |= CURSOR_ENABLE |
6149 CURSOR_GAMMA_ENABLE |
6150 CURSOR_FORMAT_ARGB;
6151 } else
6152 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6153 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6154
6155 intel_crtc->cursor_visible = visible;
6156}
6157
6158static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6159{
6160 struct drm_device *dev = crtc->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163 int pipe = intel_crtc->pipe;
6164 bool visible = base != 0;
6165
6166 if (intel_crtc->cursor_visible != visible) {
548f245b 6167 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6168 if (base) {
6169 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6170 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6171 cntl |= pipe << 28; /* Connect to correct pipe */
6172 } else {
6173 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6174 cntl |= CURSOR_MODE_DISABLE;
6175 }
9db4a9c7 6176 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6177
6178 intel_crtc->cursor_visible = visible;
6179 }
6180 /* and commit changes on next vblank */
9db4a9c7 6181 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6182}
6183
65a21cd6
JB		 6184static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6185{
6186 struct drm_device *dev = crtc->dev;
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6189 int pipe = intel_crtc->pipe;
6190 bool visible = base != 0;
6191
6192 if (intel_crtc->cursor_visible != visible) {
6193 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6194 if (base) {
6195 cntl &= ~CURSOR_MODE;
6196 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6197 } else {
6198 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6199 cntl |= CURSOR_MODE_DISABLE;
6200 }
86d3efce
VS		 6201 if (IS_HASWELL(dev))
6202 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6203 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6204
6205 intel_crtc->cursor_visible = visible;
6206 }
6207 /* and commit changes on next vblank */
6208 I915_WRITE(CURBASE_IVB(pipe), base);
6209}
6210
cda4b7d3 6211/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6212static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6213 bool on)
cda4b7d3
CW		 6214{
6215 struct drm_device *dev = crtc->dev;
6216 struct drm_i915_private *dev_priv = dev->dev_private;
6217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6218 int pipe = intel_crtc->pipe;
6219 int x = intel_crtc->cursor_x;
6220 int y = intel_crtc->cursor_y;
560b85bb 6221 u32 base, pos;
cda4b7d3
CW		 6222 bool visible;
6223
6224 pos = 0;
6225
6b383a7f 6226 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6227 base = intel_crtc->cursor_addr;
6228 if (x > (int) crtc->fb->width)
6229 base = 0;
6230
6231 if (y > (int) crtc->fb->height)
6232 base = 0;
6233 } else
6234 base = 0;
6235
6236 if (x < 0) {
6237 if (x + intel_crtc->cursor_width < 0)
6238 base = 0;
6239
6240 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6241 x = -x;
6242 }
6243 pos |= x << CURSOR_X_SHIFT;
6244
6245 if (y < 0) {
6246 if (y + intel_crtc->cursor_height < 0)
6247 base = 0;
6248
6249 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6250 y = -y;
6251 }
6252 pos |= y << CURSOR_Y_SHIFT;
6253
6254 visible = base != 0;
560b85bb 6255 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6256 return;
6257
0cd83aa9 6258 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6259 I915_WRITE(CURPOS_IVB(pipe), pos);
6260 ivb_update_cursor(crtc, base);
6261 } else {
6262 I915_WRITE(CURPOS(pipe), pos);
6263 if (IS_845G(dev) || IS_I865G(dev))
6264 i845_update_cursor(crtc, base);
6265 else
6266 i9xx_update_cursor(crtc, base);
6267 }
cda4b7d3
CW		 6268}
6269
79e53945 6270static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6271 struct drm_file *file,
79e53945
JB		 6272 uint32_t handle,
6273 uint32_t width, uint32_t height)
6274{
6275 struct drm_device *dev = crtc->dev;
6276 struct drm_i915_private *dev_priv = dev->dev_private;
6277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6278 struct drm_i915_gem_object *obj;
cda4b7d3 6279 uint32_t addr;
3f8bc370 6280 int ret;
79e53945 6281
79e53945
JB		 6282 /* if we want to turn off the cursor ignore width and height */
6283 if (!handle) {
28c97730 6284 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6285 addr = 0;
05394f39 6286 obj = NULL;
5004417d 6287 mutex_lock(&dev->struct_mutex);
3f8bc370 6288 goto finish;
79e53945
JB		 6289 }
6290
6291 /* Currently we only support 64x64 cursors */
6292 if (width != 64 || height != 64) {
6293 DRM_ERROR("we currently only support 64x64 cursors\n");
6294 return -EINVAL;
6295 }
6296
05394f39 6297 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6298 if (&obj->base == NULL)
79e53945
JB		 6299 return -ENOENT;
6300
05394f39 6301 if (obj->base.size < width * height * 4) {
79e53945 6302 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6303 ret = -ENOMEM;
6304 goto fail;
79e53945
JB		 6305 }
6306
71acb5eb 6307 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6308 mutex_lock(&dev->struct_mutex);
b295d1b6 6309 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6310 if (obj->tiling_mode) {
6311 DRM_ERROR("cursor cannot be tiled\n");
6312 ret = -EINVAL;
6313 goto fail_locked;
6314 }
6315
2da3b9b9 6316 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6317 if (ret) {
6318 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6319 goto fail_locked;
e7b526bb
CW		 6320 }
6321
d9e86c0e
CW		 6322 ret = i915_gem_object_put_fence(obj);
6323 if (ret) {
2da3b9b9 6324 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6325 goto fail_unpin;
6326 }
6327
05394f39 6328 addr = obj->gtt_offset;
71acb5eb 6329 } else {
6eeefaf3 6330 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6331 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6332 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6333 align);
71acb5eb
DA		 6334 if (ret) {
6335 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6336 goto fail_locked;
71acb5eb 6337 }
05394f39 6338 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6339 }
6340
a6c45cf0 6341 if (IS_GEN2(dev))
14b60391
JB		 6342 I915_WRITE(CURSIZE, (height << 12) | width);
6343
3f8bc370 6344 finish:
3f8bc370 6345 if (intel_crtc->cursor_bo) {
b295d1b6 6346 if (dev_priv->info->cursor_needs_physical) {
05394f39 6347 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6348 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6349 } else
6350 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6351 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6352 }
80824003 6353
7f9872e0 6354 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6355
6356 intel_crtc->cursor_addr = addr;
05394f39 6357 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6358 intel_crtc->cursor_width = width;
6359 intel_crtc->cursor_height = height;
6360
6b383a7f 6361 intel_crtc_update_cursor(crtc, true);
3f8bc370 6362
79e53945 6363 return 0;
e7b526bb 6364fail_unpin:
05394f39 6365 i915_gem_object_unpin(obj);
7f9872e0 6366fail_locked:
34b8686e 6367 mutex_unlock(&dev->struct_mutex);
bc9025bd 6368fail:
05394f39 6369 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6370 return ret;
79e53945
JB		 6371}
6372
6373static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6374{
79e53945 6375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6376
cda4b7d3
CW		 6377 intel_crtc->cursor_x = x;
6378 intel_crtc->cursor_y = y;
652c393a 6379
6b383a7f 6380 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6381
6382 return 0;
6383}
6384
6385/** Sets the color ramps on behalf of RandR */
6386void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6387 u16 blue, int regno)
6388{
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390
6391 intel_crtc->lut_r[regno] = red >> 8;
6392 intel_crtc->lut_g[regno] = green >> 8;
6393 intel_crtc->lut_b[regno] = blue >> 8;
6394}
6395
b8c00ac5
DA		 6396void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6397 u16 *blue, int regno)
6398{
6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6400
6401 *red = intel_crtc->lut_r[regno] << 8;
6402 *green = intel_crtc->lut_g[regno] << 8;
6403 *blue = intel_crtc->lut_b[regno] << 8;
6404}
6405
79e53945 6406static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6407 u16 *blue, uint32_t start, uint32_t size)
79e53945 6408{
7203425a 6409 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6411
7203425a 6412 for (i = start; i < end; i++) {
79e53945
JB		 6413 intel_crtc->lut_r[i] = red[i] >> 8;
6414 intel_crtc->lut_g[i] = green[i] >> 8;
6415 intel_crtc->lut_b[i] = blue[i] >> 8;
6416 }
6417
6418 intel_crtc_load_lut(crtc);
6419}
6420
6421/**
6422 * Get a pipe with a simple mode set on it for doing load-based monitor
6423 * detection.
6424 *
6425 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6426 * its requirements. The pipe will be connected to no other encoders.
79e53945 6427 *
c751ce4f 6428 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6429 * configured for it. In the future, it could choose to temporarily disable
6430 * some outputs to free up a pipe for its use.
6431 *
6432 * \return crtc, or NULL if no pipes are available.
6433 */
6434
6435/* VESA 640x480x72Hz mode to set on the pipe */
6436static struct drm_display_mode load_detect_mode = {
6437 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6438 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6439};
6440
d2dff872
CW		 6441static struct drm_framebuffer *
6442intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6443 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6444 struct drm_i915_gem_object *obj)
6445{
6446 struct intel_framebuffer *intel_fb;
6447 int ret;
6448
6449 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6450 if (!intel_fb) {
6451 drm_gem_object_unreference_unlocked(&obj->base);
6452 return ERR_PTR(-ENOMEM);
6453 }
6454
6455 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6456 if (ret) {
6457 drm_gem_object_unreference_unlocked(&obj->base);
6458 kfree(intel_fb);
6459 return ERR_PTR(ret);
6460 }
6461
6462 return &intel_fb->base;
6463}
6464
6465static u32
6466intel_framebuffer_pitch_for_width(int width, int bpp)
6467{
6468 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6469 return ALIGN(pitch, 64);
6470}
6471
6472static u32
6473intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6474{
6475 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6476 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6477}
6478
6479static struct drm_framebuffer *
6480intel_framebuffer_create_for_mode(struct drm_device *dev,
6481 struct drm_display_mode *mode,
6482 int depth, int bpp)
6483{
6484 struct drm_i915_gem_object *obj;
0fed39bd 6485 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6486
6487 obj = i915_gem_alloc_object(dev,
6488 intel_framebuffer_size_for_mode(mode, bpp));
6489 if (obj == NULL)
6490 return ERR_PTR(-ENOMEM);
6491
6492 mode_cmd.width = mode->hdisplay;
6493 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6494 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6495 bpp);
5ca0c34a 6496 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6497
6498 return intel_framebuffer_create(dev, &mode_cmd, obj);
6499}
6500
6501static struct drm_framebuffer *
6502mode_fits_in_fbdev(struct drm_device *dev,
6503 struct drm_display_mode *mode)
6504{
6505 struct drm_i915_private *dev_priv = dev->dev_private;
6506 struct drm_i915_gem_object *obj;
6507 struct drm_framebuffer *fb;
6508
6509 if (dev_priv->fbdev == NULL)
6510 return NULL;
6511
6512 obj = dev_priv->fbdev->ifb.obj;
6513 if (obj == NULL)
6514 return NULL;
6515
6516 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6517 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6518 fb->bits_per_pixel))
d2dff872
CW		 6519 return NULL;
6520
01f2c773 6521 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6522 return NULL;
6523
6524 return fb;
6525}
6526
d2434ab7 6527bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6528 struct drm_display_mode *mode,
8261b191 6529 struct intel_load_detect_pipe *old)
79e53945
JB		 6530{
6531 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6532 struct intel_encoder *intel_encoder =
6533 intel_attached_encoder(connector);
79e53945 6534 struct drm_crtc *possible_crtc;
4ef69c7a 6535 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6536 struct drm_crtc *crtc = NULL;
6537 struct drm_device *dev = encoder->dev;
94352cf9 6538 struct drm_framebuffer *fb;
79e53945
JB		 6539 int i = -1;
6540
d2dff872
CW		 6541 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6542 connector->base.id, drm_get_connector_name(connector),
6543 encoder->base.id, drm_get_encoder_name(encoder));
6544
79e53945
JB		 6545 /*
6546 * Algorithm gets a little messy:
7a5e4805 6547 *
79e53945
JB		 6548 * - if the connector already has an assigned crtc, use it (but make
6549 * sure it's on first)
7a5e4805 6550 *
79e53945
JB		 6551 * - try to find the first unused crtc that can drive this connector,
6552 * and use that if we find one
79e53945
JB		 6553 */
6554
6555 /* See if we already have a CRTC for this connector */
6556 if (encoder->crtc) {
6557 crtc = encoder->crtc;
8261b191 6558
7b24056b
DV		 6559 mutex_lock(&crtc->mutex);
6560
24218aac 6561 old->dpms_mode = connector->dpms;
8261b191
CW		 6562 old->load_detect_temp = false;
6563
6564 /* Make sure the crtc and connector are running */
24218aac
DV		 6565 if (connector->dpms != DRM_MODE_DPMS_ON)
6566 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6567
7173188d 6568 return true;
79e53945
JB		 6569 }
6570
6571 /* Find an unused one (if possible) */
6572 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6573 i++;
6574 if (!(encoder->possible_crtcs & (1 << i)))
6575 continue;
6576 if (!possible_crtc->enabled) {
6577 crtc = possible_crtc;
6578 break;
6579 }
79e53945
JB		 6580 }
6581
6582 /*
6583 * If we didn't find an unused CRTC, don't use any.
6584 */
6585 if (!crtc) {
7173188d
CW		 6586 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6587 return false;
79e53945
JB		 6588 }
6589
7b24056b 6590 mutex_lock(&crtc->mutex);
fc303101
DV		 6591 intel_encoder->new_crtc = to_intel_crtc(crtc);
6592 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6593
6594 intel_crtc = to_intel_crtc(crtc);
24218aac 6595 old->dpms_mode = connector->dpms;
8261b191 6596 old->load_detect_temp = true;
d2dff872 6597 old->release_fb = NULL;
79e53945 6598
6492711d
CW		 6599 if (!mode)
6600 mode = &load_detect_mode;
79e53945 6601
d2dff872
CW		 6602 /* We need a framebuffer large enough to accommodate all accesses
6603 * that the plane may generate whilst we perform load detection.
6604 * We can not rely on the fbcon either being present (we get called
6605 * during its initialisation to detect all boot displays, or it may
6606 * not even exist) or that it is large enough to satisfy the
6607 * requested mode.
6608 */
94352cf9
DV		 6609 fb = mode_fits_in_fbdev(dev, mode);
6610 if (fb == NULL) {
d2dff872 6611 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6612 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6613 old->release_fb = fb;
d2dff872
CW		 6614 } else
6615 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6616 if (IS_ERR(fb)) {
d2dff872 6617 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6618 mutex_unlock(&crtc->mutex);
0e8b3d3e 6619 return false;
79e53945 6620 }
79e53945 6621
c0c36b94 6622 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6623 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6624 if (old->release_fb)
6625 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6626 mutex_unlock(&crtc->mutex);
0e8b3d3e 6627 return false;
79e53945 6628 }
7173188d 6629
79e53945 6630 /* let the connector get through one full cycle before testing */
9d0498a2 6631 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6632 return true;
79e53945
JB		 6633}
6634
d2434ab7 6635void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6636 struct intel_load_detect_pipe *old)
79e53945 6637{
d2434ab7
DV		 6638 struct intel_encoder *intel_encoder =
6639 intel_attached_encoder(connector);
4ef69c7a 6640 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6641 struct drm_crtc *crtc = encoder->crtc;
79e53945 6642
d2dff872
CW		 6643 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6644 connector->base.id, drm_get_connector_name(connector),
6645 encoder->base.id, drm_get_encoder_name(encoder));
6646
8261b191 6647 if (old->load_detect_temp) {
fc303101
DV		 6648 to_intel_connector(connector)->new_encoder = NULL;
6649 intel_encoder->new_crtc = NULL;
6650 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6651
36206361
DV		 6652 if (old->release_fb) {
6653 drm_framebuffer_unregister_private(old->release_fb);
6654 drm_framebuffer_unreference(old->release_fb);
6655 }
d2dff872 6656
67c96400 6657 mutex_unlock(&crtc->mutex);
0622a53c 6658 return;
79e53945
JB		 6659 }
6660
c751ce4f 6661 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6662 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6663 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6664
6665 mutex_unlock(&crtc->mutex);
79e53945
JB		 6666}
6667
6668/* Returns the clock of the currently programmed mode of the given pipe. */
6669static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6670{
6671 struct drm_i915_private *dev_priv = dev->dev_private;
6672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6673 int pipe = intel_crtc->pipe;
548f245b 6674 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6675 u32 fp;
6676 intel_clock_t clock;
6677
6678 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6679 fp = I915_READ(FP0(pipe));
79e53945 6680 else
39adb7a5 6681 fp = I915_READ(FP1(pipe));
79e53945
JB		 6682
6683 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6684 if (IS_PINEVIEW(dev)) {
6685 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6686 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6687 } else {
6688 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6689 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6690 }
6691
a6c45cf0 6692 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6693 if (IS_PINEVIEW(dev))
6694 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6695 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6696 else
6697 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6698 DPLL_FPA01_P1_POST_DIV_SHIFT);
6699
6700 switch (dpll & DPLL_MODE_MASK) {
6701 case DPLLB_MODE_DAC_SERIAL:
6702 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6703 5 : 10;
6704 break;
6705 case DPLLB_MODE_LVDS:
6706 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6707 7 : 14;
6708 break;
6709 default:
28c97730 6710 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6711 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6712 return 0;
6713 }
6714
6715 /* XXX: Handle the 100Mhz refclk */
2177832f 6716 intel_clock(dev, 96000, &clock);
79e53945
JB		 6717 } else {
6718 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6719
6720 if (is_lvds) {
6721 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6722 DPLL_FPA01_P1_POST_DIV_SHIFT);
6723 clock.p2 = 14;
6724
6725 if ((dpll & PLL_REF_INPUT_MASK) ==
6726 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6727 /* XXX: might not be 66MHz */
2177832f 6728 intel_clock(dev, 66000, &clock);
79e53945 6729 } else
2177832f 6730 intel_clock(dev, 48000, &clock);
79e53945
JB		 6731 } else {
6732 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6733 clock.p1 = 2;
6734 else {
6735 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6736 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6737 }
6738 if (dpll & PLL_P2_DIVIDE_BY_4)
6739 clock.p2 = 4;
6740 else
6741 clock.p2 = 2;
6742
2177832f 6743 intel_clock(dev, 48000, &clock);
79e53945
JB		 6744 }
6745 }
6746
6747 /* XXX: It would be nice to validate the clocks, but we can't reuse
6748 * i830PllIsValid() because it relies on the xf86_config connector
6749 * configuration being accurate, which it isn't necessarily.
6750 */
6751
6752 return clock.dot;
6753}
6754
6755/** Returns the currently programmed mode of the given pipe. */
6756struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6757 struct drm_crtc *crtc)
6758{
548f245b 6759 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6761 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6762 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6763 int htot = I915_READ(HTOTAL(cpu_transcoder));
6764 int hsync = I915_READ(HSYNC(cpu_transcoder));
6765 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6766 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6767
6768 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6769 if (!mode)
6770 return NULL;
6771
6772 mode->clock = intel_crtc_clock_get(dev, crtc);
6773 mode->hdisplay = (htot & 0xffff) + 1;
6774 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6775 mode->hsync_start = (hsync & 0xffff) + 1;
6776 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6777 mode->vdisplay = (vtot & 0xffff) + 1;
6778 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6779 mode->vsync_start = (vsync & 0xffff) + 1;
6780 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6781
6782 drm_mode_set_name(mode);
79e53945
JB		 6783
6784 return mode;
6785}
6786
3dec0095 6787static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6788{
6789 struct drm_device *dev = crtc->dev;
6790 drm_i915_private_t *dev_priv = dev->dev_private;
6791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6792 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6793 int dpll_reg = DPLL(pipe);
6794 int dpll;
652c393a 6795
bad720ff 6796 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6797 return;
6798
6799 if (!dev_priv->lvds_downclock_avail)
6800 return;
6801
dbdc6479 6802 dpll = I915_READ(dpll_reg);
652c393a 6803 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6804 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6805
8ac5a6d5 6806 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6807
6808 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6809 I915_WRITE(dpll_reg, dpll);
9d0498a2 6810 intel_wait_for_vblank(dev, pipe);
dbdc6479 6811
652c393a
JB		 6812 dpll = I915_READ(dpll_reg);
6813 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6814 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6815 }
652c393a
JB		 6816}
6817
6818static void intel_decrease_pllclock(struct drm_crtc *crtc)
6819{
6820 struct drm_device *dev = crtc->dev;
6821 drm_i915_private_t *dev_priv = dev->dev_private;
6822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6823
bad720ff 6824 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6825 return;
6826
6827 if (!dev_priv->lvds_downclock_avail)
6828 return;
6829
6830 /*
6831 * Since this is called by a timer, we should never get here in
6832 * the manual case.
6833 */
6834 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6835 int pipe = intel_crtc->pipe;
6836 int dpll_reg = DPLL(pipe);
6837 int dpll;
f6e5b160 6838
44d98a61 6839 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6840
8ac5a6d5 6841 assert_panel_unlocked(dev_priv, pipe);
652c393a 6842
dc257cf1 6843 dpll = I915_READ(dpll_reg);
652c393a
JB		 6844 dpll |= DISPLAY_RATE_SELECT_FPA1;
6845 I915_WRITE(dpll_reg, dpll);
9d0498a2 6846 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6847 dpll = I915_READ(dpll_reg);
6848 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6849 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6850 }
6851
6852}
6853
f047e395
CW		 6854void intel_mark_busy(struct drm_device *dev)
6855{
f047e395
CW		 6856 i915_update_gfx_val(dev->dev_private);
6857}
6858
6859void intel_mark_idle(struct drm_device *dev)
652c393a 6860{
652c393a 6861 struct drm_crtc *crtc;
652c393a
JB		 6862
6863 if (!i915_powersave)
6864 return;
6865
652c393a 6866 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6867 if (!crtc->fb)
6868 continue;
6869
725a5b54 6870 intel_decrease_pllclock(crtc);
652c393a 6871 }
652c393a
JB		 6872}
6873
725a5b54 6874void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6875{
f047e395
CW		 6876 struct drm_device *dev = obj->base.dev;
6877 struct drm_crtc *crtc;
652c393a 6878
f047e395 6879 if (!i915_powersave)
acb87dfb
CW		 6880 return;
6881
652c393a
JB		 6882 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6883 if (!crtc->fb)
6884 continue;
6885
f047e395 6886 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6887 intel_increase_pllclock(crtc);
652c393a
JB		 6888 }
6889}
6890
79e53945
JB		 6891static void intel_crtc_destroy(struct drm_crtc *crtc)
6892{
6893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6894 struct drm_device *dev = crtc->dev;
6895 struct intel_unpin_work *work;
6896 unsigned long flags;
6897
6898 spin_lock_irqsave(&dev->event_lock, flags);
6899 work = intel_crtc->unpin_work;
6900 intel_crtc->unpin_work = NULL;
6901 spin_unlock_irqrestore(&dev->event_lock, flags);
6902
6903 if (work) {
6904 cancel_work_sync(&work->work);
6905 kfree(work);
6906 }
79e53945
JB		 6907
6908 drm_crtc_cleanup(crtc);
67e77c5a 6909
79e53945
JB		 6910 kfree(intel_crtc);
6911}
6912
6b95a207
KH		 6913static void intel_unpin_work_fn(struct work_struct *__work)
6914{
6915 struct intel_unpin_work *work =
6916 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6917 struct drm_device *dev = work->crtc->dev;
6b95a207 6918
b4a98e57 6919 mutex_lock(&dev->struct_mutex);
1690e1eb 6920 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6921 drm_gem_object_unreference(&work->pending_flip_obj->base);
6922 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6923
b4a98e57
CW		 6924 intel_update_fbc(dev);
6925 mutex_unlock(&dev->struct_mutex);
6926
6927 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6928 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6929
6b95a207
KH		 6930 kfree(work);
6931}
6932
1afe3e9d 6933static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6934 struct drm_crtc *crtc)
6b95a207
KH		 6935{
6936 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6938 struct intel_unpin_work *work;
05394f39 6939 struct drm_i915_gem_object *obj;
6b95a207
KH		 6940 unsigned long flags;
6941
6942 /* Ignore early vblank irqs */
6943 if (intel_crtc == NULL)
6944 return;
6945
6946 spin_lock_irqsave(&dev->event_lock, flags);
6947 work = intel_crtc->unpin_work;
e7d841ca
CW		 6948
6949 /* Ensure we don't miss a work->pending update ... */
6950 smp_rmb();
6951
6952 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6953 spin_unlock_irqrestore(&dev->event_lock, flags);
6954 return;
6955 }
6956
e7d841ca
CW		 6957 /* and that the unpin work is consistent wrt ->pending. */
6958 smp_rmb();
6959
6b95a207 6960 intel_crtc->unpin_work = NULL;
6b95a207 6961
45a066eb
RC		 6962 if (work->event)
6963 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6964
0af7e4df
MK		 6965 drm_vblank_put(dev, intel_crtc->pipe);
6966
6b95a207
KH		 6967 spin_unlock_irqrestore(&dev->event_lock, flags);
6968
05394f39 6969 obj = work->old_fb_obj;
d9e86c0e 6970
2c10d571 6971 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6972
6973 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6974
6975 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6976}
6977
1afe3e9d
JB		 6978void intel_finish_page_flip(struct drm_device *dev, int pipe)
6979{
6980 drm_i915_private_t *dev_priv = dev->dev_private;
6981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6982
49b14a5c 6983 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6984}
6985
6986void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6987{
6988 drm_i915_private_t *dev_priv = dev->dev_private;
6989 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6990
49b14a5c 6991 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6992}
6993
6b95a207
KH		 6994void intel_prepare_page_flip(struct drm_device *dev, int plane)
6995{
6996 drm_i915_private_t *dev_priv = dev->dev_private;
6997 struct intel_crtc *intel_crtc =
6998 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6999 unsigned long flags;
7000
e7d841ca
CW		 7001 /* NB: An MMIO update of the plane base pointer will also
7002 * generate a page-flip completion irq, i.e. every modeset
7003 * is also accompanied by a spurious intel_prepare_page_flip().
7004 */
6b95a207 7005 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7006 if (intel_crtc->unpin_work)
7007 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7008 spin_unlock_irqrestore(&dev->event_lock, flags);
7009}
7010
e7d841ca
CW		 7011inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7012{
7013 /* Ensure that the work item is consistent when activating it ... */
7014 smp_wmb();
7015 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7016 /* and that it is marked active as soon as the irq could fire. */
7017 smp_wmb();
7018}
7019
8c9f3aaf
JB		 7020static int intel_gen2_queue_flip(struct drm_device *dev,
7021 struct drm_crtc *crtc,
7022 struct drm_framebuffer *fb,
7023 struct drm_i915_gem_object *obj)
7024{
7025 struct drm_i915_private *dev_priv = dev->dev_private;
7026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7027 u32 flip_mask;
6d90c952 7028 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7029 int ret;
7030
6d90c952 7031 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7032 if (ret)
83d4092b 7033 goto err;
8c9f3aaf 7034
6d90c952 7035 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7036 if (ret)
83d4092b 7037 goto err_unpin;
8c9f3aaf
JB		 7038
7039 /* Can't queue multiple flips, so wait for the previous
7040 * one to finish before executing the next.
7041 */
7042 if (intel_crtc->plane)
7043 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7044 else
7045 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7046 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7047 intel_ring_emit(ring, MI_NOOP);
7048 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7049 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7050 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7051 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7052 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7053
7054 intel_mark_page_flip_active(intel_crtc);
6d90c952 7055 intel_ring_advance(ring);
83d4092b
CW		 7056 return 0;
7057
7058err_unpin:
7059 intel_unpin_fb_obj(obj);
7060err:
8c9f3aaf
JB		 7061 return ret;
7062}
7063
7064static int intel_gen3_queue_flip(struct drm_device *dev,
7065 struct drm_crtc *crtc,
7066 struct drm_framebuffer *fb,
7067 struct drm_i915_gem_object *obj)
7068{
7069 struct drm_i915_private *dev_priv = dev->dev_private;
7070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7071 u32 flip_mask;
6d90c952 7072 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7073 int ret;
7074
6d90c952 7075 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7076 if (ret)
83d4092b 7077 goto err;
8c9f3aaf 7078
6d90c952 7079 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7080 if (ret)
83d4092b 7081 goto err_unpin;
8c9f3aaf
JB		 7082
7083 if (intel_crtc->plane)
7084 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7085 else
7086 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7087 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7088 intel_ring_emit(ring, MI_NOOP);
7089 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7090 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7091 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7092 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7093 intel_ring_emit(ring, MI_NOOP);
7094
e7d841ca 7095 intel_mark_page_flip_active(intel_crtc);
6d90c952 7096 intel_ring_advance(ring);
83d4092b
CW		 7097 return 0;
7098
7099err_unpin:
7100 intel_unpin_fb_obj(obj);
7101err:
8c9f3aaf
JB		 7102 return ret;
7103}
7104
7105static int intel_gen4_queue_flip(struct drm_device *dev,
7106 struct drm_crtc *crtc,
7107 struct drm_framebuffer *fb,
7108 struct drm_i915_gem_object *obj)
7109{
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7112 uint32_t pf, pipesrc;
6d90c952 7113 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7114 int ret;
7115
6d90c952 7116 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7117 if (ret)
83d4092b 7118 goto err;
8c9f3aaf 7119
6d90c952 7120 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7121 if (ret)
83d4092b 7122 goto err_unpin;
8c9f3aaf
JB		 7123
7124 /* i965+ uses the linear or tiled offsets from the
7125 * Display Registers (which do not change across a page-flip)
7126 * so we need only reprogram the base address.
7127 */
6d90c952
DV		 7128 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7129 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7130 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7131 intel_ring_emit(ring,
7132 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7133 obj->tiling_mode);
8c9f3aaf
JB		 7134
7135 /* XXX Enabling the panel-fitter across page-flip is so far
7136 * untested on non-native modes, so ignore it for now.
7137 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7138 */
7139 pf = 0;
7140 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7141 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7142
7143 intel_mark_page_flip_active(intel_crtc);
6d90c952 7144 intel_ring_advance(ring);
83d4092b
CW		 7145 return 0;
7146
7147err_unpin:
7148 intel_unpin_fb_obj(obj);
7149err:
8c9f3aaf
JB		 7150 return ret;
7151}
7152
7153static int intel_gen6_queue_flip(struct drm_device *dev,
7154 struct drm_crtc *crtc,
7155 struct drm_framebuffer *fb,
7156 struct drm_i915_gem_object *obj)
7157{
7158 struct drm_i915_private *dev_priv = dev->dev_private;
7159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7160 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7161 uint32_t pf, pipesrc;
7162 int ret;
7163
6d90c952 7164 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7165 if (ret)
83d4092b 7166 goto err;
8c9f3aaf 7167
6d90c952 7168 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7169 if (ret)
83d4092b 7170 goto err_unpin;
8c9f3aaf 7171
6d90c952
DV		 7172 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7173 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7174 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7175 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7176
dc257cf1
DV		 7177 /* Contrary to the suggestions in the documentation,
7178 * "Enable Panel Fitter" does not seem to be required when page
7179 * flipping with a non-native mode, and worse causes a normal
7180 * modeset to fail.
7181 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7182 */
7183 pf = 0;
8c9f3aaf 7184 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7185 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7186
7187 intel_mark_page_flip_active(intel_crtc);
6d90c952 7188 intel_ring_advance(ring);
83d4092b
CW		 7189 return 0;
7190
7191err_unpin:
7192 intel_unpin_fb_obj(obj);
7193err:
8c9f3aaf
JB		 7194 return ret;
7195}
7196
7c9017e5
JB		 7197/*
7198 * On gen7 we currently use the blit ring because (in early silicon at least)
7199 * the render ring doesn't give us interrpts for page flip completion, which
7200 * means clients will hang after the first flip is queued. Fortunately the
7201 * blit ring generates interrupts properly, so use it instead.
7202 */
7203static int intel_gen7_queue_flip(struct drm_device *dev,
7204 struct drm_crtc *crtc,
7205 struct drm_framebuffer *fb,
7206 struct drm_i915_gem_object *obj)
7207{
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7210 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7211 uint32_t plane_bit = 0;
7c9017e5
JB		 7212 int ret;
7213
7214 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7215 if (ret)
83d4092b 7216 goto err;
7c9017e5 7217
cb05d8de
DV		 7218 switch(intel_crtc->plane) {
7219 case PLANE_A:
7220 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7221 break;
7222 case PLANE_B:
7223 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7224 break;
7225 case PLANE_C:
7226 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7227 break;
7228 default:
7229 WARN_ONCE(1, "unknown plane in flip command\n");
7230 ret = -ENODEV;
ab3951eb 7231 goto err_unpin;
cb05d8de
DV		 7232 }
7233
7c9017e5
JB		 7234 ret = intel_ring_begin(ring, 4);
7235 if (ret)
83d4092b 7236 goto err_unpin;
7c9017e5 7237
cb05d8de 7238 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7239 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7240 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7241 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7242
7243 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7244 intel_ring_advance(ring);
83d4092b
CW		 7245 return 0;
7246
7247err_unpin:
7248 intel_unpin_fb_obj(obj);
7249err:
7c9017e5
JB		 7250 return ret;
7251}
7252
8c9f3aaf
JB		 7253static int intel_default_queue_flip(struct drm_device *dev,
7254 struct drm_crtc *crtc,
7255 struct drm_framebuffer *fb,
7256 struct drm_i915_gem_object *obj)
7257{
7258 return -ENODEV;
7259}
7260
6b95a207
KH		 7261static int intel_crtc_page_flip(struct drm_crtc *crtc,
7262 struct drm_framebuffer *fb,
7263 struct drm_pending_vblank_event *event)
7264{
7265 struct drm_device *dev = crtc->dev;
7266 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7267 struct drm_framebuffer *old_fb = crtc->fb;
7268 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270 struct intel_unpin_work *work;
8c9f3aaf 7271 unsigned long flags;
52e68630 7272 int ret;
6b95a207 7273
e6a595d2
VS		 7274 /* Can't change pixel format via MI display flips. */
7275 if (fb->pixel_format != crtc->fb->pixel_format)
7276 return -EINVAL;
7277
7278 /*
7279 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7280 * Note that pitch changes could also affect these register.
7281 */
7282 if (INTEL_INFO(dev)->gen > 3 &&
7283 (fb->offsets[0] != crtc->fb->offsets[0] ||
7284 fb->pitches[0] != crtc->fb->pitches[0]))
7285 return -EINVAL;
7286
6b95a207
KH		 7287 work = kzalloc(sizeof *work, GFP_KERNEL);
7288 if (work == NULL)
7289 return -ENOMEM;
7290
6b95a207 7291 work->event = event;
b4a98e57 7292 work->crtc = crtc;
4a35f83b 7293 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7294 INIT_WORK(&work->work, intel_unpin_work_fn);
7295
7317c75e
JB		 7296 ret = drm_vblank_get(dev, intel_crtc->pipe);
7297 if (ret)
7298 goto free_work;
7299
6b95a207
KH		 7300 /* We borrow the event spin lock for protecting unpin_work */
7301 spin_lock_irqsave(&dev->event_lock, flags);
7302 if (intel_crtc->unpin_work) {
7303 spin_unlock_irqrestore(&dev->event_lock, flags);
7304 kfree(work);
7317c75e 7305 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7306
7307 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7308 return -EBUSY;
7309 }
7310 intel_crtc->unpin_work = work;
7311 spin_unlock_irqrestore(&dev->event_lock, flags);
7312
b4a98e57
CW		 7313 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7314 flush_workqueue(dev_priv->wq);
7315
79158103
CW		 7316 ret = i915_mutex_lock_interruptible(dev);
7317 if (ret)
7318 goto cleanup;
6b95a207 7319
75dfca80 7320 /* Reference the objects for the scheduled work. */
05394f39
CW		 7321 drm_gem_object_reference(&work->old_fb_obj->base);
7322 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7323
7324 crtc->fb = fb;
96b099fd 7325
e1f99ce6 7326 work->pending_flip_obj = obj;
e1f99ce6 7327
4e5359cd
SF		 7328 work->enable_stall_check = true;
7329
b4a98e57 7330 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7331 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7332
8c9f3aaf
JB		 7333 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7334 if (ret)
7335 goto cleanup_pending;
6b95a207 7336
7782de3b 7337 intel_disable_fbc(dev);
f047e395 7338 intel_mark_fb_busy(obj);
6b95a207
KH		 7339 mutex_unlock(&dev->struct_mutex);
7340
e5510fac
JB		 7341 trace_i915_flip_request(intel_crtc->plane, obj);
7342
6b95a207 7343 return 0;
96b099fd 7344
8c9f3aaf 7345cleanup_pending:
b4a98e57 7346 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7347 crtc->fb = old_fb;
05394f39
CW		 7348 drm_gem_object_unreference(&work->old_fb_obj->base);
7349 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7350 mutex_unlock(&dev->struct_mutex);
7351
79158103 7352cleanup:
96b099fd
CW		 7353 spin_lock_irqsave(&dev->event_lock, flags);
7354 intel_crtc->unpin_work = NULL;
7355 spin_unlock_irqrestore(&dev->event_lock, flags);
7356
7317c75e
JB		 7357 drm_vblank_put(dev, intel_crtc->pipe);
7358free_work:
96b099fd
CW		 7359 kfree(work);
7360
7361 return ret;
6b95a207
KH		 7362}
7363
f6e5b160 7364static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7365 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7366 .load_lut = intel_crtc_load_lut,
976f8a20 7367 .disable = intel_crtc_noop,
f6e5b160
CW		 7368};
7369
6ed0f796 7370bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7371{
6ed0f796
DV		 7372 struct intel_encoder *other_encoder;
7373 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7374
6ed0f796
DV		 7375 if (WARN_ON(!crtc))
7376 return false;
7377
7378 list_for_each_entry(other_encoder,
7379 &crtc->dev->mode_config.encoder_list,
7380 base.head) {
7381
7382 if (&other_encoder->new_crtc->base != crtc ||
7383 encoder == other_encoder)
7384 continue;
7385 else
7386 return true;
f47166d2
CW		 7387 }
7388
6ed0f796
DV		 7389 return false;
7390}
47f1c6c9 7391
50f56119
DV		 7392static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7393 struct drm_crtc *crtc)
7394{
7395 struct drm_device *dev;
7396 struct drm_crtc *tmp;
7397 int crtc_mask = 1;
47f1c6c9 7398
50f56119 7399 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7400
50f56119 7401 dev = crtc->dev;
47f1c6c9 7402
50f56119
DV		 7403 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7404 if (tmp == crtc)
7405 break;
7406 crtc_mask <<= 1;
7407 }
47f1c6c9 7408
50f56119
DV		 7409 if (encoder->possible_crtcs & crtc_mask)
7410 return true;
7411 return false;
47f1c6c9 7412}
79e53945 7413
9a935856
DV		 7414/**
7415 * intel_modeset_update_staged_output_state
7416 *
7417 * Updates the staged output configuration state, e.g. after we've read out the
7418 * current hw state.
7419 */
7420static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7421{
9a935856
DV		 7422 struct intel_encoder *encoder;
7423 struct intel_connector *connector;
f6e5b160 7424
9a935856
DV		 7425 list_for_each_entry(connector, &dev->mode_config.connector_list,
7426 base.head) {
7427 connector->new_encoder =
7428 to_intel_encoder(connector->base.encoder);
7429 }
f6e5b160 7430
9a935856
DV		 7431 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7432 base.head) {
7433 encoder->new_crtc =
7434 to_intel_crtc(encoder->base.crtc);
7435 }
f6e5b160
CW		 7436}
7437
9a935856
DV		 7438/**
7439 * intel_modeset_commit_output_state
7440 *
7441 * This function copies the stage display pipe configuration to the real one.
7442 */
7443static void intel_modeset_commit_output_state(struct drm_device *dev)
7444{
7445 struct intel_encoder *encoder;
7446 struct intel_connector *connector;
f6e5b160 7447
9a935856
DV		 7448 list_for_each_entry(connector, &dev->mode_config.connector_list,
7449 base.head) {
7450 connector->base.encoder = &connector->new_encoder->base;
7451 }
f6e5b160 7452
9a935856
DV		 7453 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7454 base.head) {
7455 encoder->base.crtc = &encoder->new_crtc->base;
7456 }
7457}
7458
7758a113
DV		 7459static struct drm_display_mode *
7460intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7461 struct drm_display_mode *mode)
ee7b9f93 7462{
7758a113
DV		 7463 struct drm_device *dev = crtc->dev;
7464 struct drm_display_mode *adjusted_mode;
7465 struct drm_encoder_helper_funcs *encoder_funcs;
7466 struct intel_encoder *encoder;
ee7b9f93 7467
7758a113
DV		 7468 adjusted_mode = drm_mode_duplicate(dev, mode);
7469 if (!adjusted_mode)
7470 return ERR_PTR(-ENOMEM);
7471
7472 /* Pass our mode to the connectors and the CRTC to give them a chance to
7473 * adjust it according to limitations or connector properties, and also
7474 * a chance to reject the mode entirely.
47f1c6c9 7475 */
7758a113
DV		 7476 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7477 base.head) {
47f1c6c9 7478
7758a113
DV		 7479 if (&encoder->new_crtc->base != crtc)
7480 continue;
7481 encoder_funcs = encoder->base.helper_private;
7482 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7483 adjusted_mode))) {
7484 DRM_DEBUG_KMS("Encoder fixup failed\n");
7485 goto fail;
7486 }
ee7b9f93 7487 }
47f1c6c9 7488
7758a113
DV		 7489 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7490 DRM_DEBUG_KMS("CRTC fixup failed\n");
7491 goto fail;
ee7b9f93 7492 }
7758a113 7493 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7494
7758a113
DV		 7495 return adjusted_mode;
7496fail:
7497 drm_mode_destroy(dev, adjusted_mode);
7498 return ERR_PTR(-EINVAL);
ee7b9f93 7499}
47f1c6c9 7500
e2e1ed41
DV		 7501/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7502 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7503static void
7504intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7505 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7506{
7507 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7508 struct drm_device *dev = crtc->dev;
7509 struct intel_encoder *encoder;
7510 struct intel_connector *connector;
7511 struct drm_crtc *tmp_crtc;
79e53945 7512
e2e1ed41 7513 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7514
e2e1ed41
DV		 7515 /* Check which crtcs have changed outputs connected to them, these need
7516 * to be part of the prepare_pipes mask. We don't (yet) support global
7517 * modeset across multiple crtcs, so modeset_pipes will only have one
7518 * bit set at most. */
7519 list_for_each_entry(connector, &dev->mode_config.connector_list,
7520 base.head) {
7521 if (connector->base.encoder == &connector->new_encoder->base)
7522 continue;
79e53945 7523
e2e1ed41
DV		 7524 if (connector->base.encoder) {
7525 tmp_crtc = connector->base.encoder->crtc;
7526
7527 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7528 }
7529
7530 if (connector->new_encoder)
7531 *prepare_pipes |=
7532 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7533 }
7534
e2e1ed41
DV		 7535 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7536 base.head) {
7537 if (encoder->base.crtc == &encoder->new_crtc->base)
7538 continue;
7539
7540 if (encoder->base.crtc) {
7541 tmp_crtc = encoder->base.crtc;
7542
7543 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7544 }
7545
7546 if (encoder->new_crtc)
7547 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7548 }
7549
e2e1ed41
DV		 7550 /* Check for any pipes that will be fully disabled ... */
7551 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7552 base.head) {
7553 bool used = false;
22fd0fab 7554
e2e1ed41
DV		 7555 /* Don't try to disable disabled crtcs. */
7556 if (!intel_crtc->base.enabled)
7557 continue;
7e7d76c3 7558
e2e1ed41
DV		 7559 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7560 base.head) {
7561 if (encoder->new_crtc == intel_crtc)
7562 used = true;
7563 }
7564
7565 if (!used)
7566 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7567 }
7568
e2e1ed41
DV		 7569
7570 /* set_mode is also used to update properties on life display pipes. */
7571 intel_crtc = to_intel_crtc(crtc);
7572 if (crtc->enabled)
7573 *prepare_pipes |= 1 << intel_crtc->pipe;
7574
7575 /* We only support modeset on one single crtc, hence we need to do that
7576 * only for the passed in crtc iff we change anything else than just
7577 * disable crtcs.
7578 *
7579 * This is actually not true, to be fully compatible with the old crtc
7580 * helper we automatically disable _any_ output (i.e. doesn't need to be
7581 * connected to the crtc we're modesetting on) if it's disconnected.
7582 * Which is a rather nutty api (since changed the output configuration
7583 * without userspace's explicit request can lead to confusion), but
7584 * alas. Hence we currently need to modeset on all pipes we prepare. */
7585 if (*prepare_pipes)
7586 *modeset_pipes = *prepare_pipes;
7587
7588 /* ... and mask these out. */
7589 *modeset_pipes &= ~(*disable_pipes);
7590 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7591}
79e53945 7592
ea9d758d 7593static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7594{
ea9d758d 7595 struct drm_encoder *encoder;
f6e5b160 7596 struct drm_device *dev = crtc->dev;
f6e5b160 7597
ea9d758d
DV		 7598 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7599 if (encoder->crtc == crtc)
7600 return true;
7601
7602 return false;
7603}
7604
7605static void
7606intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7607{
7608 struct intel_encoder *intel_encoder;
7609 struct intel_crtc *intel_crtc;
7610 struct drm_connector *connector;
7611
7612 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7613 base.head) {
7614 if (!intel_encoder->base.crtc)
7615 continue;
7616
7617 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7618
7619 if (prepare_pipes & (1 << intel_crtc->pipe))
7620 intel_encoder->connectors_active = false;
7621 }
7622
7623 intel_modeset_commit_output_state(dev);
7624
7625 /* Update computed state. */
7626 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7627 base.head) {
7628 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7629 }
7630
7631 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7632 if (!connector->encoder || !connector->encoder->crtc)
7633 continue;
7634
7635 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7636
7637 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7638 struct drm_property *dpms_property =
7639 dev->mode_config.dpms_property;
7640
ea9d758d 7641 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7642 drm_object_property_set_value(&connector->base,
68d34720
DV		 7643 dpms_property,
7644 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7645
7646 intel_encoder = to_intel_encoder(connector->encoder);
7647 intel_encoder->connectors_active = true;
7648 }
7649 }
7650
7651}
7652
25c5b266
DV		 7653#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7654 list_for_each_entry((intel_crtc), \
7655 &(dev)->mode_config.crtc_list, \
7656 base.head) \
7657 if (mask & (1 <<(intel_crtc)->pipe)) \
7658
b980514c 7659void
8af6cf88
DV		 7660intel_modeset_check_state(struct drm_device *dev)
7661{
7662 struct intel_crtc *crtc;
7663 struct intel_encoder *encoder;
7664 struct intel_connector *connector;
7665
7666 list_for_each_entry(connector, &dev->mode_config.connector_list,
7667 base.head) {
7668 /* This also checks the encoder/connector hw state with the
7669 * ->get_hw_state callbacks. */
7670 intel_connector_check_state(connector);
7671
7672 WARN(&connector->new_encoder->base != connector->base.encoder,
7673 "connector's staged encoder doesn't match current encoder\n");
7674 }
7675
7676 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7677 base.head) {
7678 bool enabled = false;
7679 bool active = false;
7680 enum pipe pipe, tracked_pipe;
7681
7682 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7683 encoder->base.base.id,
7684 drm_get_encoder_name(&encoder->base));
7685
7686 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7687 "encoder's stage crtc doesn't match current crtc\n");
7688 WARN(encoder->connectors_active && !encoder->base.crtc,
7689 "encoder's active_connectors set, but no crtc\n");
7690
7691 list_for_each_entry(connector, &dev->mode_config.connector_list,
7692 base.head) {
7693 if (connector->base.encoder != &encoder->base)
7694 continue;
7695 enabled = true;
7696 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7697 active = true;
7698 }
7699 WARN(!!encoder->base.crtc != enabled,
7700 "encoder's enabled state mismatch "
7701 "(expected %i, found %i)\n",
7702 !!encoder->base.crtc, enabled);
7703 WARN(active && !encoder->base.crtc,
7704 "active encoder with no crtc\n");
7705
7706 WARN(encoder->connectors_active != active,
7707 "encoder's computed active state doesn't match tracked active state "
7708 "(expected %i, found %i)\n", active, encoder->connectors_active);
7709
7710 active = encoder->get_hw_state(encoder, &pipe);
7711 WARN(active != encoder->connectors_active,
7712 "encoder's hw state doesn't match sw tracking "
7713 "(expected %i, found %i)\n",
7714 encoder->connectors_active, active);
7715
7716 if (!encoder->base.crtc)
7717 continue;
7718
7719 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7720 WARN(active && pipe != tracked_pipe,
7721 "active encoder's pipe doesn't match"
7722 "(expected %i, found %i)\n",
7723 tracked_pipe, pipe);
7724
7725 }
7726
7727 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7728 base.head) {
7729 bool enabled = false;
7730 bool active = false;
7731
7732 DRM_DEBUG_KMS("[CRTC:%d]\n",
7733 crtc->base.base.id);
7734
7735 WARN(crtc->active && !crtc->base.enabled,
7736 "active crtc, but not enabled in sw tracking\n");
7737
7738 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7739 base.head) {
7740 if (encoder->base.crtc != &crtc->base)
7741 continue;
7742 enabled = true;
7743 if (encoder->connectors_active)
7744 active = true;
7745 }
7746 WARN(active != crtc->active,
7747 "crtc's computed active state doesn't match tracked active state "
7748 "(expected %i, found %i)\n", active, crtc->active);
7749 WARN(enabled != crtc->base.enabled,
7750 "crtc's computed enabled state doesn't match tracked enabled state "
7751 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7752
7753 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7754 }
7755}
7756
c0c36b94
CW		 7757int intel_set_mode(struct drm_crtc *crtc,
7758 struct drm_display_mode *mode,
7759 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7760{
7761 struct drm_device *dev = crtc->dev;
dbf2b54e 7762 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7763 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7764 struct intel_crtc *intel_crtc;
7765 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7766 int ret = 0;
a6778b3c 7767
3ac18232 7768 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7769 if (!saved_mode)
7770 return -ENOMEM;
3ac18232 7771 saved_hwmode = saved_mode + 1;
a6778b3c 7772
e2e1ed41 7773 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7774 &prepare_pipes, &disable_pipes);
7775
7776 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7777 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7778
976f8a20
DV		 7779 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7780 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7781
3ac18232
TG		 7782 *saved_hwmode = crtc->hwmode;
7783 *saved_mode = crtc->mode;
a6778b3c 7784
25c5b266
DV		 7785 /* Hack: Because we don't (yet) support global modeset on multiple
7786 * crtcs, we don't keep track of the new mode for more than one crtc.
7787 * Hence simply check whether any bit is set in modeset_pipes in all the
7788 * pieces of code that are not yet converted to deal with mutliple crtcs
7789 * changing their mode at the same time. */
7790 adjusted_mode = NULL;
7791 if (modeset_pipes) {
7792 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7793 if (IS_ERR(adjusted_mode)) {
c0c36b94 7794 ret = PTR_ERR(adjusted_mode);
3ac18232 7795 goto out;
25c5b266 7796 }
25c5b266 7797 }
a6778b3c 7798
ea9d758d
DV		 7799 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7800 if (intel_crtc->base.enabled)
7801 dev_priv->display.crtc_disable(&intel_crtc->base);
7802 }
a6778b3c 7803
6c4c86f5
DV		 7804 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7805 * to set it here already despite that we pass it down the callchain.
f6e5b160 7806 */
6c4c86f5 7807 if (modeset_pipes)
25c5b266 7808 crtc->mode = *mode;
7758a113 7809
ea9d758d
DV		 7810 /* Only after disabling all output pipelines that will be changed can we
7811 * update the the output configuration. */
7812 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7813
47fab737
DV		 7814 if (dev_priv->display.modeset_global_resources)
7815 dev_priv->display.modeset_global_resources(dev);
7816
a6778b3c
DV		 7817 /* Set up the DPLL and any encoders state that needs to adjust or depend
7818 * on the DPLL.
f6e5b160 7819 */
25c5b266 7820 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7821 ret = intel_crtc_mode_set(&intel_crtc->base,
7822 mode, adjusted_mode,
7823 x, y, fb);
7824 if (ret)
7825 goto done;
a6778b3c
DV		 7826 }
7827
7828 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7829 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7830 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7831
25c5b266
DV		 7832 if (modeset_pipes) {
7833 /* Store real post-adjustment hardware mode. */
7834 crtc->hwmode = *adjusted_mode;
a6778b3c 7835
25c5b266
DV		 7836 /* Calculate and store various constants which
7837 * are later needed by vblank and swap-completion
7838 * timestamping. They are derived from true hwmode.
7839 */
7840 drm_calc_timestamping_constants(crtc);
7841 }
a6778b3c
DV		 7842
7843 /* FIXME: add subpixel order */
7844done:
7845 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7846 if (ret && crtc->enabled) {
3ac18232
TG		 7847 crtc->hwmode = *saved_hwmode;
7848 crtc->mode = *saved_mode;
8af6cf88
DV		 7849 } else {
7850 intel_modeset_check_state(dev);
a6778b3c
DV		 7851 }
7852
3ac18232
TG		 7853out:
7854 kfree(saved_mode);
a6778b3c 7855 return ret;
f6e5b160
CW		 7856}
7857
c0c36b94
CW		 7858void intel_crtc_restore_mode(struct drm_crtc *crtc)
7859{
7860 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7861}
7862
25c5b266
DV		 7863#undef for_each_intel_crtc_masked
7864
d9e55608
DV		 7865static void intel_set_config_free(struct intel_set_config *config)
7866{
7867 if (!config)
7868 return;
7869
1aa4b628
DV		 7870 kfree(config->save_connector_encoders);
7871 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7872 kfree(config);
7873}
7874
85f9eb71
DV		 7875static int intel_set_config_save_state(struct drm_device *dev,
7876 struct intel_set_config *config)
7877{
85f9eb71
DV		 7878 struct drm_encoder *encoder;
7879 struct drm_connector *connector;
7880 int count;
7881
1aa4b628
DV		 7882 config->save_encoder_crtcs =
7883 kcalloc(dev->mode_config.num_encoder,
7884 sizeof(struct drm_crtc *), GFP_KERNEL);
7885 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7886 return -ENOMEM;
7887
1aa4b628
DV		 7888 config->save_connector_encoders =
7889 kcalloc(dev->mode_config.num_connector,
7890 sizeof(struct drm_encoder *), GFP_KERNEL);
7891 if (!config->save_connector_encoders)
85f9eb71
DV		 7892 return -ENOMEM;
7893
7894 /* Copy data. Note that driver private data is not affected.
7895 * Should anything bad happen only the expected state is
7896 * restored, not the drivers personal bookkeeping.
7897 */
85f9eb71
DV		 7898 count = 0;
7899 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7900 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7901 }
7902
7903 count = 0;
7904 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7905 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7906 }
7907
7908 return 0;
7909}
7910
7911static void intel_set_config_restore_state(struct drm_device *dev,
7912 struct intel_set_config *config)
7913{
9a935856
DV		 7914 struct intel_encoder *encoder;
7915 struct intel_connector *connector;
85f9eb71
DV		 7916 int count;
7917
85f9eb71 7918 count = 0;
9a935856
DV		 7919 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7920 encoder->new_crtc =
7921 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7922 }
7923
7924 count = 0;
9a935856
DV		 7925 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7926 connector->new_encoder =
7927 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7928 }
7929}
7930
5e2b584e
DV		 7931static void
7932intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7933 struct intel_set_config *config)
7934{
7935
7936 /* We should be able to check here if the fb has the same properties
7937 * and then just flip_or_move it */
7938 if (set->crtc->fb != set->fb) {
7939 /* If we have no fb then treat it as a full mode set */
7940 if (set->crtc->fb == NULL) {
7941 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7942 config->mode_changed = true;
7943 } else if (set->fb == NULL) {
7944 config->mode_changed = true;
7945 } else if (set->fb->depth != set->crtc->fb->depth) {
7946 config->mode_changed = true;
7947 } else if (set->fb->bits_per_pixel !=
7948 set->crtc->fb->bits_per_pixel) {
7949 config->mode_changed = true;
7950 } else
7951 config->fb_changed = true;
7952 }
7953
835c5873 7954 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7955 config->fb_changed = true;
7956
7957 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7958 DRM_DEBUG_KMS("modes are different, full mode set\n");
7959 drm_mode_debug_printmodeline(&set->crtc->mode);
7960 drm_mode_debug_printmodeline(set->mode);
7961 config->mode_changed = true;
7962 }
7963}
7964
2e431051 7965static int
9a935856
DV		 7966intel_modeset_stage_output_state(struct drm_device *dev,
7967 struct drm_mode_set *set,
7968 struct intel_set_config *config)
50f56119 7969{
85f9eb71 7970 struct drm_crtc *new_crtc;
9a935856
DV		 7971 struct intel_connector *connector;
7972 struct intel_encoder *encoder;
2e431051 7973 int count, ro;
50f56119 7974
9abdda74 7975 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7976 * of connectors. For paranoia, double-check this. */
7977 WARN_ON(!set->fb && (set->num_connectors != 0));
7978 WARN_ON(set->fb && (set->num_connectors == 0));
7979
50f56119 7980 count = 0;
9a935856
DV		 7981 list_for_each_entry(connector, &dev->mode_config.connector_list,
7982 base.head) {
7983 /* Otherwise traverse passed in connector list and get encoders
7984 * for them. */
50f56119 7985 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7986 if (set->connectors[ro] == &connector->base) {
7987 connector->new_encoder = connector->encoder;
50f56119
DV		 7988 break;
7989 }
7990 }
7991
9a935856
DV		 7992 /* If we disable the crtc, disable all its connectors. Also, if
7993 * the connector is on the changing crtc but not on the new
7994 * connector list, disable it. */
7995 if ((!set->fb || ro == set->num_connectors) &&
7996 connector->base.encoder &&
7997 connector->base.encoder->crtc == set->crtc) {
7998 connector->new_encoder = NULL;
7999
8000 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8001 connector->base.base.id,
8002 drm_get_connector_name(&connector->base));
8003 }
8004
8005
8006 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8007 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8008 config->mode_changed = true;
50f56119
DV		 8009 }
8010 }
9a935856 8011 /* connector->new_encoder is now updated for all connectors. */
50f56119 8012
9a935856 8013 /* Update crtc of enabled connectors. */
50f56119 8014 count = 0;
9a935856
DV		 8015 list_for_each_entry(connector, &dev->mode_config.connector_list,
8016 base.head) {
8017 if (!connector->new_encoder)
50f56119
DV		 8018 continue;
8019
9a935856 8020 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8021
8022 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8023 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8024 new_crtc = set->crtc;
8025 }
8026
8027 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8028 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8029 new_crtc)) {
5e2b584e 8030 return -EINVAL;
50f56119 8031 }
9a935856
DV		 8032 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8033
8034 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8035 connector->base.base.id,
8036 drm_get_connector_name(&connector->base),
8037 new_crtc->base.id);
8038 }
8039
8040 /* Check for any encoders that needs to be disabled. */
8041 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8042 base.head) {
8043 list_for_each_entry(connector,
8044 &dev->mode_config.connector_list,
8045 base.head) {
8046 if (connector->new_encoder == encoder) {
8047 WARN_ON(!connector->new_encoder->new_crtc);
8048
8049 goto next_encoder;
8050 }
8051 }
8052 encoder->new_crtc = NULL;
8053next_encoder:
8054 /* Only now check for crtc changes so we don't miss encoders
8055 * that will be disabled. */
8056 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8057 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8058 config->mode_changed = true;
50f56119
DV		 8059 }
8060 }
9a935856 8061 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8062
2e431051
DV		 8063 return 0;
8064}
8065
8066static int intel_crtc_set_config(struct drm_mode_set *set)
8067{
8068 struct drm_device *dev;
2e431051
DV		 8069 struct drm_mode_set save_set;
8070 struct intel_set_config *config;
8071 int ret;
2e431051 8072
8d3e375e
DV		 8073 BUG_ON(!set);
8074 BUG_ON(!set->crtc);
8075 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8076
8077 if (!set->mode)
8078 set->fb = NULL;
8079
431e50f7
DV		 8080 /* The fb helper likes to play gross jokes with ->mode_set_config.
8081 * Unfortunately the crtc helper doesn't do much at all for this case,
8082 * so we have to cope with this madness until the fb helper is fixed up. */
8083 if (set->fb && set->num_connectors == 0)
8084 return 0;
8085
2e431051
DV		 8086 if (set->fb) {
8087 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8088 set->crtc->base.id, set->fb->base.id,
8089 (int)set->num_connectors, set->x, set->y);
8090 } else {
8091 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8092 }
8093
8094 dev = set->crtc->dev;
8095
8096 ret = -ENOMEM;
8097 config = kzalloc(sizeof(*config), GFP_KERNEL);
8098 if (!config)
8099 goto out_config;
8100
8101 ret = intel_set_config_save_state(dev, config);
8102 if (ret)
8103 goto out_config;
8104
8105 save_set.crtc = set->crtc;
8106 save_set.mode = &set->crtc->mode;
8107 save_set.x = set->crtc->x;
8108 save_set.y = set->crtc->y;
8109 save_set.fb = set->crtc->fb;
8110
8111 /* Compute whether we need a full modeset, only an fb base update or no
8112 * change at all. In the future we might also check whether only the
8113 * mode changed, e.g. for LVDS where we only change the panel fitter in
8114 * such cases. */
8115 intel_set_config_compute_mode_changes(set, config);
8116
9a935856 8117 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8118 if (ret)
8119 goto fail;
8120
5e2b584e 8121 if (config->mode_changed) {
87f1faa6 8122 if (set->mode) {
50f56119
DV		 8123 DRM_DEBUG_KMS("attempting to set mode from"
8124 " userspace\n");
8125 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8126 }
8127
c0c36b94
CW		 8128 ret = intel_set_mode(set->crtc, set->mode,
8129 set->x, set->y, set->fb);
8130 if (ret) {
8131 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8132 set->crtc->base.id, ret);
87f1faa6
DV		 8133 goto fail;
8134 }
5e2b584e 8135 } else if (config->fb_changed) {
4f660f49 8136 ret = intel_pipe_set_base(set->crtc,
94352cf9 8137 set->x, set->y, set->fb);
50f56119
DV		 8138 }
8139
d9e55608
DV		 8140 intel_set_config_free(config);
8141
50f56119
DV		 8142 return 0;
8143
8144fail:
85f9eb71 8145 intel_set_config_restore_state(dev, config);
50f56119
DV		 8146
8147 /* Try to restore the config */
5e2b584e 8148 if (config->mode_changed &&
c0c36b94
CW		 8149 intel_set_mode(save_set.crtc, save_set.mode,
8150 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8151 DRM_ERROR("failed to restore config after modeset failure\n");
8152
d9e55608
DV		 8153out_config:
8154 intel_set_config_free(config);
50f56119
DV		 8155 return ret;
8156}
f6e5b160
CW		 8157
8158static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8159 .cursor_set = intel_crtc_cursor_set,
8160 .cursor_move = intel_crtc_cursor_move,
8161 .gamma_set = intel_crtc_gamma_set,
50f56119 8162 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8163 .destroy = intel_crtc_destroy,
8164 .page_flip = intel_crtc_page_flip,
8165};
8166
79f689aa
PZ		 8167static void intel_cpu_pll_init(struct drm_device *dev)
8168{
affa9354 8169 if (HAS_DDI(dev))
79f689aa
PZ		 8170 intel_ddi_pll_init(dev);
8171}
8172
ee7b9f93
JB		 8173static void intel_pch_pll_init(struct drm_device *dev)
8174{
8175 drm_i915_private_t *dev_priv = dev->dev_private;
8176 int i;
8177
8178 if (dev_priv->num_pch_pll == 0) {
8179 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8180 return;
8181 }
8182
8183 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8184 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8185 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8186 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8187 }
8188}
8189
b358d0a6 8190static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8191{
22fd0fab 8192 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8193 struct intel_crtc *intel_crtc;
8194 int i;
8195
8196 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8197 if (intel_crtc == NULL)
8198 return;
8199
8200 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8201
8202 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8203 for (i = 0; i < 256; i++) {
8204 intel_crtc->lut_r[i] = i;
8205 intel_crtc->lut_g[i] = i;
8206 intel_crtc->lut_b[i] = i;
8207 }
8208
80824003
JB		 8209 /* Swap pipes & planes for FBC on pre-965 */
8210 intel_crtc->pipe = pipe;
8211 intel_crtc->plane = pipe;
a5c961d1 8212 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8213 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8214 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8215 intel_crtc->plane = !pipe;
80824003
JB		 8216 }
8217
22fd0fab
JB		 8218 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8219 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8220 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8221 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8222
5a354204 8223 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8224
79e53945 8225 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8226}
8227
08d7b3d1 8228int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8229 struct drm_file *file)
08d7b3d1 8230{
08d7b3d1 8231 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8232 struct drm_mode_object *drmmode_obj;
8233 struct intel_crtc *crtc;
08d7b3d1 8234
1cff8f6b
DV		 8235 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8236 return -ENODEV;
08d7b3d1 8237
c05422d5
DV		 8238 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8239 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8240
c05422d5 8241 if (!drmmode_obj) {
08d7b3d1
CW		 8242 DRM_ERROR("no such CRTC id\n");
8243 return -EINVAL;
8244 }
8245
c05422d5
DV		 8246 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8247 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8248
c05422d5 8249 return 0;
08d7b3d1
CW		 8250}
8251
66a9278e 8252static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8253{
66a9278e
DV		 8254 struct drm_device *dev = encoder->base.dev;
8255 struct intel_encoder *source_encoder;
79e53945 8256 int index_mask = 0;
79e53945
JB		 8257 int entry = 0;
8258
66a9278e
DV		 8259 list_for_each_entry(source_encoder,
8260 &dev->mode_config.encoder_list, base.head) {
8261
8262 if (encoder == source_encoder)
79e53945 8263 index_mask |= (1 << entry);
66a9278e
DV		 8264
8265 /* Intel hw has only one MUX where enocoders could be cloned. */
8266 if (encoder->cloneable && source_encoder->cloneable)
8267 index_mask |= (1 << entry);
8268
79e53945
JB		 8269 entry++;
8270 }
4ef69c7a 8271
79e53945
JB		 8272 return index_mask;
8273}
8274
4d302442
CW		 8275static bool has_edp_a(struct drm_device *dev)
8276{
8277 struct drm_i915_private *dev_priv = dev->dev_private;
8278
8279 if (!IS_MOBILE(dev))
8280 return false;
8281
8282 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8283 return false;
8284
8285 if (IS_GEN5(dev) &&
8286 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8287 return false;
8288
8289 return true;
8290}
8291
79e53945
JB		 8292static void intel_setup_outputs(struct drm_device *dev)
8293{
725e30ad 8294 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8295 struct intel_encoder *encoder;
cb0953d7 8296 bool dpd_is_edp = false;
f3cfcba6 8297 bool has_lvds;
79e53945 8298
f3cfcba6 8299 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8300 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8301 /* disable the panel fitter on everything but LVDS */
8302 I915_WRITE(PFIT_CONTROL, 0);
8303 }
79e53945 8304
affa9354 8305 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8306 intel_crt_init(dev);
cb0953d7 8307
affa9354 8308 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8309 int found;
8310
8311 /* Haswell uses DDI functions to detect digital outputs */
8312 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8313 /* DDI A only supports eDP */
8314 if (found)
8315 intel_ddi_init(dev, PORT_A);
8316
8317 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8318 * register */
8319 found = I915_READ(SFUSE_STRAP);
8320
8321 if (found & SFUSE_STRAP_DDIB_DETECTED)
8322 intel_ddi_init(dev, PORT_B);
8323 if (found & SFUSE_STRAP_DDIC_DETECTED)
8324 intel_ddi_init(dev, PORT_C);
8325 if (found & SFUSE_STRAP_DDID_DETECTED)
8326 intel_ddi_init(dev, PORT_D);
8327 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8328 int found;
270b3042
DV		 8329 dpd_is_edp = intel_dpd_is_edp(dev);
8330
8331 if (has_edp_a(dev))
8332 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8333
30ad48b7 8334 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8335 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8336 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8337 if (!found)
08d644ad 8338 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8339 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8340 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8341 }
8342
8343 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8344 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8345
b708a1d5 8346 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8347 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8348
5eb08b69 8349 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8350 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8351
270b3042 8352 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8353 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8354 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8355 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8356 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8357 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8358
67cfc203
VS		 8359 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8360 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8361 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8362 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d
JB		 8363 }
8364
67cfc203
VS		 8365 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8366 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
5eb08b69 8367
103a196f 8368 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8369 bool found = false;
7d57382e 8370
725e30ad 8371 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8372 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8373 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8374 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8375 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8376 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8377 }
27185ae1 8378
b01f2c3a
JB		 8379 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8380 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8381 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8382 }
725e30ad 8383 }
13520b05
KH		 8384
8385 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8386
b01f2c3a
JB		 8387 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8388 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8389 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8390 }
27185ae1
ML		 8391
8392 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8393
b01f2c3a
JB		 8394 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8395 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8396 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8397 }
8398 if (SUPPORTS_INTEGRATED_DP(dev)) {
8399 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8400 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8401 }
725e30ad 8402 }
27185ae1 8403
b01f2c3a
JB		 8404 if (SUPPORTS_INTEGRATED_DP(dev) &&
8405 (I915_READ(DP_D) & DP_DETECTED)) {
8406 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8407 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8408 }
bad720ff 8409 } else if (IS_GEN2(dev))
79e53945
JB		 8410 intel_dvo_init(dev);
8411
103a196f 8412 if (SUPPORTS_TV(dev))
79e53945
JB		 8413 intel_tv_init(dev);
8414
4ef69c7a
CW		 8415 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8416 encoder->base.possible_crtcs = encoder->crtc_mask;
8417 encoder->base.possible_clones =
66a9278e 8418 intel_encoder_clones(encoder);
79e53945 8419 }
47356eb6 8420
dde86e2d 8421 intel_init_pch_refclk(dev);
270b3042
DV		 8422
8423 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8424}
8425
8426static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8427{
8428 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8429
8430 drm_framebuffer_cleanup(fb);
05394f39 8431 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8432
8433 kfree(intel_fb);
8434}
8435
8436static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8437 struct drm_file *file,
79e53945
JB		 8438 unsigned int *handle)
8439{
8440 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8441 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8442
05394f39 8443 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8444}
8445
8446static const struct drm_framebuffer_funcs intel_fb_funcs = {
8447 .destroy = intel_user_framebuffer_destroy,
8448 .create_handle = intel_user_framebuffer_create_handle,
8449};
8450
38651674
DA		 8451int intel_framebuffer_init(struct drm_device *dev,
8452 struct intel_framebuffer *intel_fb,
308e5bcb 8453 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8454 struct drm_i915_gem_object *obj)
79e53945 8455{
79e53945
JB		 8456 int ret;
8457
c16ed4be
CW		 8458 if (obj->tiling_mode == I915_TILING_Y) {
8459 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8460 return -EINVAL;
c16ed4be 8461 }
57cd6508 8462
c16ed4be
CW		 8463 if (mode_cmd->pitches[0] & 63) {
8464 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8465 mode_cmd->pitches[0]);
57cd6508 8466 return -EINVAL;
c16ed4be 8467 }
57cd6508 8468
5d7bd705 8469 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8470 if (mode_cmd->pitches[0] > 32768) {
8471 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8472 mode_cmd->pitches[0]);
5d7bd705 8473 return -EINVAL;
c16ed4be 8474 }
5d7bd705
VS		 8475
8476 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8477 mode_cmd->pitches[0] != obj->stride) {
8478 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8479 mode_cmd->pitches[0], obj->stride);
5d7bd705 8480 return -EINVAL;
c16ed4be 8481 }
5d7bd705 8482
57779d06 8483 /* Reject formats not supported by any plane early. */
308e5bcb 8484 switch (mode_cmd->pixel_format) {
57779d06 8485 case DRM_FORMAT_C8:
04b3924d
VS		 8486 case DRM_FORMAT_RGB565:
8487 case DRM_FORMAT_XRGB8888:
8488 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8489 break;
8490 case DRM_FORMAT_XRGB1555:
8491 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8492 if (INTEL_INFO(dev)->gen > 3) {
8493 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8494 return -EINVAL;
c16ed4be 8495 }
57779d06
VS		 8496 break;
8497 case DRM_FORMAT_XBGR8888:
8498 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8499 case DRM_FORMAT_XRGB2101010:
8500 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8501 case DRM_FORMAT_XBGR2101010:
8502 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8503 if (INTEL_INFO(dev)->gen < 4) {
8504 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8505 return -EINVAL;
c16ed4be 8506 }
b5626747 8507 break;
04b3924d
VS		 8508 case DRM_FORMAT_YUYV:
8509 case DRM_FORMAT_UYVY:
8510 case DRM_FORMAT_YVYU:
8511 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8512 if (INTEL_INFO(dev)->gen < 5) {
8513 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8514 return -EINVAL;
c16ed4be 8515 }
57cd6508
CW		 8516 break;
8517 default:
c16ed4be 8518 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8519 return -EINVAL;
8520 }
8521
90f9a336
VS		 8522 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8523 if (mode_cmd->offsets[0] != 0)
8524 return -EINVAL;
8525
c7d73f6a
DV		 8526 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8527 intel_fb->obj = obj;
8528
79e53945
JB		 8529 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8530 if (ret) {
8531 DRM_ERROR("framebuffer init failed %d\n", ret);
8532 return ret;
8533 }
8534
79e53945
JB		 8535 return 0;
8536}
8537
79e53945
JB		 8538static struct drm_framebuffer *
8539intel_user_framebuffer_create(struct drm_device *dev,
8540 struct drm_file *filp,
308e5bcb 8541 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8542{
05394f39 8543 struct drm_i915_gem_object *obj;
79e53945 8544
308e5bcb
JB		 8545 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8546 mode_cmd->handles[0]));
c8725226 8547 if (&obj->base == NULL)
cce13ff7 8548 return ERR_PTR(-ENOENT);
79e53945 8549
d2dff872 8550 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8551}
8552
79e53945 8553static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8554 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8555 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8556};
8557
e70236a8
JB		 8558/* Set up chip specific display functions */
8559static void intel_init_display(struct drm_device *dev)
8560{
8561 struct drm_i915_private *dev_priv = dev->dev_private;
8562
8563 /* We always want a DPMS function */
affa9354 8564 if (HAS_DDI(dev)) {
09b4ddf9 8565 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8566 dev_priv->display.crtc_enable = haswell_crtc_enable;
8567 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8568 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8569 dev_priv->display.update_plane = ironlake_update_plane;
8570 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8571 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8572 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8573 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8574 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8575 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8576 } else {
f564048e 8577 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8578 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8579 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8580 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8581 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8582 }
e70236a8 8583
e70236a8 8584 /* Returns the core display clock speed */
25eb05fc
JB		 8585 if (IS_VALLEYVIEW(dev))
8586 dev_priv->display.get_display_clock_speed =
8587 valleyview_get_display_clock_speed;
8588 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8589 dev_priv->display.get_display_clock_speed =
8590 i945_get_display_clock_speed;
8591 else if (IS_I915G(dev))
8592 dev_priv->display.get_display_clock_speed =
8593 i915_get_display_clock_speed;
f2b115e6 8594 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8595 dev_priv->display.get_display_clock_speed =
8596 i9xx_misc_get_display_clock_speed;
8597 else if (IS_I915GM(dev))
8598 dev_priv->display.get_display_clock_speed =
8599 i915gm_get_display_clock_speed;
8600 else if (IS_I865G(dev))
8601 dev_priv->display.get_display_clock_speed =
8602 i865_get_display_clock_speed;
f0f8a9ce 8603 else if (IS_I85X(dev))
e70236a8
JB		 8604 dev_priv->display.get_display_clock_speed =
8605 i855_get_display_clock_speed;
8606 else /* 852, 830 */
8607 dev_priv->display.get_display_clock_speed =
8608 i830_get_display_clock_speed;
8609
7f8a8569 8610 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8611 if (IS_GEN5(dev)) {
674cf967 8612 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8613 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8614 } else if (IS_GEN6(dev)) {
674cf967 8615 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8616 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8617 } else if (IS_IVYBRIDGE(dev)) {
8618 /* FIXME: detect B0+ stepping and use auto training */
8619 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8620 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8621 dev_priv->display.modeset_global_resources =
8622 ivb_modeset_global_resources;
c82e4d26
ED		 8623 } else if (IS_HASWELL(dev)) {
8624 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8625 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8626 dev_priv->display.modeset_global_resources =
8627 haswell_modeset_global_resources;
a0e63c22 8628 }
6067aaea 8629 } else if (IS_G4X(dev)) {
e0dac65e 8630 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8631 }
8c9f3aaf
JB		 8632
8633 /* Default just returns -ENODEV to indicate unsupported */
8634 dev_priv->display.queue_flip = intel_default_queue_flip;
8635
8636 switch (INTEL_INFO(dev)->gen) {
8637 case 2:
8638 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8639 break;
8640
8641 case 3:
8642 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8643 break;
8644
8645 case 4:
8646 case 5:
8647 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8648 break;
8649
8650 case 6:
8651 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8652 break;
7c9017e5
JB		 8653 case 7:
8654 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8655 break;
8c9f3aaf 8656 }
e70236a8
JB		 8657}
8658
b690e96c
JB		 8659/*
8660 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8661 * resume, or other times. This quirk makes sure that's the case for
8662 * affected systems.
8663 */
0206e353 8664static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8665{
8666 struct drm_i915_private *dev_priv = dev->dev_private;
8667
8668 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8669 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8670}
8671
435793df
KP		 8672/*
8673 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8674 */
8675static void quirk_ssc_force_disable(struct drm_device *dev)
8676{
8677 struct drm_i915_private *dev_priv = dev->dev_private;
8678 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8679 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8680}
8681
4dca20ef 8682/*
5a15ab5b
CE		 8683 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8684 * brightness value
4dca20ef
CE		 8685 */
8686static void quirk_invert_brightness(struct drm_device *dev)
8687{
8688 struct drm_i915_private *dev_priv = dev->dev_private;
8689 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8690 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8691}
8692
b690e96c
JB		 8693struct intel_quirk {
8694 int device;
8695 int subsystem_vendor;
8696 int subsystem_device;
8697 void (*hook)(struct drm_device *dev);
8698};
8699
5f85f176
EE		 8700/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8701struct intel_dmi_quirk {
8702 void (*hook)(struct drm_device *dev);
8703 const struct dmi_system_id (*dmi_id_list)[];
8704};
8705
8706static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8707{
8708 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8709 return 1;
8710}
8711
8712static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8713 {
8714 .dmi_id_list = &(const struct dmi_system_id[]) {
8715 {
8716 .callback = intel_dmi_reverse_brightness,
8717 .ident = "NCR Corporation",
8718 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8719 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8720 },
8721 },
8722 { } /* terminating entry */
8723 },
8724 .hook = quirk_invert_brightness,
8725 },
8726};
8727
c43b5634 8728static struct intel_quirk intel_quirks[] = {
b690e96c 8729 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8730 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8731
b690e96c
JB		 8732 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8733 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8734
b690e96c
JB		 8735 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8736 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8737
ccd0d36e 8738 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8739 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8740 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8741
8742 /* Lenovo U160 cannot use SSC on LVDS */
8743 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8744
8745 /* Sony Vaio Y cannot use SSC on LVDS */
8746 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8747
8748 /* Acer Aspire 5734Z must invert backlight brightness */
8749 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8750
8751 /* Acer/eMachines G725 */
8752 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8753
8754 /* Acer/eMachines e725 */
8755 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8756
8757 /* Acer/Packard Bell NCL20 */
8758 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8759
8760 /* Acer Aspire 4736Z */
8761 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8762};
8763
8764static void intel_init_quirks(struct drm_device *dev)
8765{
8766 struct pci_dev *d = dev->pdev;
8767 int i;
8768
8769 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8770 struct intel_quirk *q = &intel_quirks[i];
8771
8772 if (d->device == q->device &&
8773 (d->subsystem_vendor == q->subsystem_vendor ||
8774 q->subsystem_vendor == PCI_ANY_ID) &&
8775 (d->subsystem_device == q->subsystem_device ||
8776 q->subsystem_device == PCI_ANY_ID))
8777 q->hook(dev);
8778 }
5f85f176
EE		 8779 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8780 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8781 intel_dmi_quirks[i].hook(dev);
8782 }
b690e96c
JB		 8783}
8784
9cce37f4
JB		 8785/* Disable the VGA plane that we never use */
8786static void i915_disable_vga(struct drm_device *dev)
8787{
8788 struct drm_i915_private *dev_priv = dev->dev_private;
8789 u8 sr1;
766aa1c4 8790 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8791
8792 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8793 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8794 sr1 = inb(VGA_SR_DATA);
8795 outb(sr1 | 1<<5, VGA_SR_DATA);
8796 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8797 udelay(300);
8798
8799 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8800 POSTING_READ(vga_reg);
8801}
8802
f817586c
DV		 8803void intel_modeset_init_hw(struct drm_device *dev)
8804{
fa42e23c 8805 intel_init_power_well(dev);
0232e927 8806
a8f78b58
ED		 8807 intel_prepare_ddi(dev);
8808
f817586c
DV		 8809 intel_init_clock_gating(dev);
8810
79f5b2c7 8811 mutex_lock(&dev->struct_mutex);
8090c6b9 8812 intel_enable_gt_powersave(dev);
79f5b2c7 8813 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8814}
8815
79e53945
JB		 8816void intel_modeset_init(struct drm_device *dev)
8817{
652c393a 8818 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8819 int i, ret;
79e53945
JB		 8820
8821 drm_mode_config_init(dev);
8822
8823 dev->mode_config.min_width = 0;
8824 dev->mode_config.min_height = 0;
8825
019d96cb
DA		 8826 dev->mode_config.preferred_depth = 24;
8827 dev->mode_config.prefer_shadow = 1;
8828
e6ecefaa 8829 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8830
b690e96c
JB		 8831 intel_init_quirks(dev);
8832
1fa61106
ED		 8833 intel_init_pm(dev);
8834
e70236a8
JB		 8835 intel_init_display(dev);
8836
a6c45cf0
CW		 8837 if (IS_GEN2(dev)) {
8838 dev->mode_config.max_width = 2048;
8839 dev->mode_config.max_height = 2048;
8840 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8841 dev->mode_config.max_width = 4096;
8842 dev->mode_config.max_height = 4096;
79e53945 8843 } else {
a6c45cf0
CW		 8844 dev->mode_config.max_width = 8192;
8845 dev->mode_config.max_height = 8192;
79e53945 8846 }
5d4545ae 8847 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8848
28c97730 8849 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8850 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8851
a3524f1b 8852 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8853 intel_crtc_init(dev, i);
00c2064b
JB		 8854 ret = intel_plane_init(dev, i);
8855 if (ret)
8856 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8857 }
8858
79f689aa 8859 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8860 intel_pch_pll_init(dev);
8861
9cce37f4
JB		 8862 /* Just disable it once at startup */
8863 i915_disable_vga(dev);
79e53945 8864 intel_setup_outputs(dev);
11be49eb
CW		 8865
8866 /* Just in case the BIOS is doing something questionable. */
8867 intel_disable_fbc(dev);
2c7111db
CW		 8868}
8869
24929352
DV		 8870static void
8871intel_connector_break_all_links(struct intel_connector *connector)
8872{
8873 connector->base.dpms = DRM_MODE_DPMS_OFF;
8874 connector->base.encoder = NULL;
8875 connector->encoder->connectors_active = false;
8876 connector->encoder->base.crtc = NULL;
8877}
8878
7fad798e
DV		 8879static void intel_enable_pipe_a(struct drm_device *dev)
8880{
8881 struct intel_connector *connector;
8882 struct drm_connector *crt = NULL;
8883 struct intel_load_detect_pipe load_detect_temp;
8884
8885 /* We can't just switch on the pipe A, we need to set things up with a
8886 * proper mode and output configuration. As a gross hack, enable pipe A
8887 * by enabling the load detect pipe once. */
8888 list_for_each_entry(connector,
8889 &dev->mode_config.connector_list,
8890 base.head) {
8891 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8892 crt = &connector->base;
8893 break;
8894 }
8895 }
8896
8897 if (!crt)
8898 return;
8899
8900 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8901 intel_release_load_detect_pipe(crt, &load_detect_temp);
8902
652c393a 8903
7fad798e
DV		 8904}
8905
fa555837
DV		 8906static bool
8907intel_check_plane_mapping(struct intel_crtc *crtc)
8908{
8909 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8910 u32 reg, val;
8911
8912 if (dev_priv->num_pipe == 1)
8913 return true;
8914
8915 reg = DSPCNTR(!crtc->plane);
8916 val = I915_READ(reg);
8917
8918 if ((val & DISPLAY_PLANE_ENABLE) &&
8919 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8920 return false;
8921
8922 return true;
8923}
8924
24929352
DV		 8925static void intel_sanitize_crtc(struct intel_crtc *crtc)
8926{
8927 struct drm_device *dev = crtc->base.dev;
8928 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8929 u32 reg;
24929352 8930
24929352 8931 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8932 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8933 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8934
8935 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8936 * disable the crtc (and hence change the state) if it is wrong. Note
8937 * that gen4+ has a fixed plane -> pipe mapping. */
8938 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8939 struct intel_connector *connector;
8940 bool plane;
8941
24929352
DV		 8942 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8943 crtc->base.base.id);
8944
8945 /* Pipe has the wrong plane attached and the plane is active.
8946 * Temporarily change the plane mapping and disable everything
8947 * ... */
8948 plane = crtc->plane;
8949 crtc->plane = !plane;
8950 dev_priv->display.crtc_disable(&crtc->base);
8951 crtc->plane = plane;
8952
8953 /* ... and break all links. */
8954 list_for_each_entry(connector, &dev->mode_config.connector_list,
8955 base.head) {
8956 if (connector->encoder->base.crtc != &crtc->base)
8957 continue;
8958
8959 intel_connector_break_all_links(connector);
8960 }
8961
8962 WARN_ON(crtc->active);
8963 crtc->base.enabled = false;
8964 }
24929352 8965
7fad798e
DV		 8966 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8967 crtc->pipe == PIPE_A && !crtc->active) {
8968 /* BIOS forgot to enable pipe A, this mostly happens after
8969 * resume. Force-enable the pipe to fix this, the update_dpms
8970 * call below we restore the pipe to the right state, but leave
8971 * the required bits on. */
8972 intel_enable_pipe_a(dev);
8973 }
8974
24929352
DV		 8975 /* Adjust the state of the output pipe according to whether we
8976 * have active connectors/encoders. */
8977 intel_crtc_update_dpms(&crtc->base);
8978
8979 if (crtc->active != crtc->base.enabled) {
8980 struct intel_encoder *encoder;
8981
8982 /* This can happen either due to bugs in the get_hw_state
8983 * functions or because the pipe is force-enabled due to the
8984 * pipe A quirk. */
8985 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8986 crtc->base.base.id,
8987 crtc->base.enabled ? "enabled" : "disabled",
8988 crtc->active ? "enabled" : "disabled");
8989
8990 crtc->base.enabled = crtc->active;
8991
8992 /* Because we only establish the connector -> encoder ->
8993 * crtc links if something is active, this means the
8994 * crtc is now deactivated. Break the links. connector
8995 * -> encoder links are only establish when things are
8996 * actually up, hence no need to break them. */
8997 WARN_ON(crtc->active);
8998
8999 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9000 WARN_ON(encoder->connectors_active);
9001 encoder->base.crtc = NULL;
9002 }
9003 }
9004}
9005
9006static void intel_sanitize_encoder(struct intel_encoder *encoder)
9007{
9008 struct intel_connector *connector;
9009 struct drm_device *dev = encoder->base.dev;
9010
9011 /* We need to check both for a crtc link (meaning that the
9012 * encoder is active and trying to read from a pipe) and the
9013 * pipe itself being active. */
9014 bool has_active_crtc = encoder->base.crtc &&
9015 to_intel_crtc(encoder->base.crtc)->active;
9016
9017 if (encoder->connectors_active && !has_active_crtc) {
9018 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9019 encoder->base.base.id,
9020 drm_get_encoder_name(&encoder->base));
9021
9022 /* Connector is active, but has no active pipe. This is
9023 * fallout from our resume register restoring. Disable
9024 * the encoder manually again. */
9025 if (encoder->base.crtc) {
9026 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9027 encoder->base.base.id,
9028 drm_get_encoder_name(&encoder->base));
9029 encoder->disable(encoder);
9030 }
9031
9032 /* Inconsistent output/port/pipe state happens presumably due to
9033 * a bug in one of the get_hw_state functions. Or someplace else
9034 * in our code, like the register restore mess on resume. Clamp
9035 * things to off as a safer default. */
9036 list_for_each_entry(connector,
9037 &dev->mode_config.connector_list,
9038 base.head) {
9039 if (connector->encoder != encoder)
9040 continue;
9041
9042 intel_connector_break_all_links(connector);
9043 }
9044 }
9045 /* Enabled encoders without active connectors will be fixed in
9046 * the crtc fixup. */
9047}
9048
44cec740 9049void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9050{
9051 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9052 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9053
9054 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9055 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9056 i915_disable_vga(dev);
0fde901f
KM		 9057 }
9058}
9059
24929352
DV		 9060/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9061 * and i915 state tracking structures. */
45e2b5f6
DV		 9062void intel_modeset_setup_hw_state(struct drm_device *dev,
9063 bool force_restore)
24929352
DV		 9064{
9065 struct drm_i915_private *dev_priv = dev->dev_private;
9066 enum pipe pipe;
9067 u32 tmp;
9068 struct intel_crtc *crtc;
9069 struct intel_encoder *encoder;
9070 struct intel_connector *connector;
9071
affa9354 9072 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9073 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9074
9075 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9076 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9077 case TRANS_DDI_EDP_INPUT_A_ON:
9078 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9079 pipe = PIPE_A;
9080 break;
9081 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9082 pipe = PIPE_B;
9083 break;
9084 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9085 pipe = PIPE_C;
9086 break;
9087 }
9088
9089 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9090 crtc->cpu_transcoder = TRANSCODER_EDP;
9091
9092 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9093 pipe_name(pipe));
9094 }
9095 }
9096
24929352
DV		 9097 for_each_pipe(pipe) {
9098 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9099
702e7a56 9100 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9101 if (tmp & PIPECONF_ENABLE)
9102 crtc->active = true;
9103 else
9104 crtc->active = false;
9105
9106 crtc->base.enabled = crtc->active;
9107
9108 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9109 crtc->base.base.id,
9110 crtc->active ? "enabled" : "disabled");
9111 }
9112
affa9354 9113 if (HAS_DDI(dev))
6441ab5f
PZ		 9114 intel_ddi_setup_hw_pll_state(dev);
9115
24929352
DV		 9116 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9117 base.head) {
9118 pipe = 0;
9119
9120 if (encoder->get_hw_state(encoder, &pipe)) {
9121 encoder->base.crtc =
9122 dev_priv->pipe_to_crtc_mapping[pipe];
9123 } else {
9124 encoder->base.crtc = NULL;
9125 }
9126
9127 encoder->connectors_active = false;
9128 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9129 encoder->base.base.id,
9130 drm_get_encoder_name(&encoder->base),
9131 encoder->base.crtc ? "enabled" : "disabled",
9132 pipe);
9133 }
9134
9135 list_for_each_entry(connector, &dev->mode_config.connector_list,
9136 base.head) {
9137 if (connector->get_hw_state(connector)) {
9138 connector->base.dpms = DRM_MODE_DPMS_ON;
9139 connector->encoder->connectors_active = true;
9140 connector->base.encoder = &connector->encoder->base;
9141 } else {
9142 connector->base.dpms = DRM_MODE_DPMS_OFF;
9143 connector->base.encoder = NULL;
9144 }
9145 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9146 connector->base.base.id,
9147 drm_get_connector_name(&connector->base),
9148 connector->base.encoder ? "enabled" : "disabled");
9149 }
9150
9151 /* HW state is read out, now we need to sanitize this mess. */
9152 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9153 base.head) {
9154 intel_sanitize_encoder(encoder);
9155 }
9156
9157 for_each_pipe(pipe) {
9158 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9159 intel_sanitize_crtc(crtc);
9160 }
9a935856 9161
45e2b5f6
DV		 9162 if (force_restore) {
9163 for_each_pipe(pipe) {
c0c36b94 9164 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9165 }
0fde901f
KM		 9166
9167 i915_redisable_vga(dev);
45e2b5f6
DV		 9168 } else {
9169 intel_modeset_update_staged_output_state(dev);
9170 }
8af6cf88
DV		 9171
9172 intel_modeset_check_state(dev);
2e938892
DV		 9173
9174 drm_mode_config_reset(dev);
2c7111db
CW		 9175}
9176
9177void intel_modeset_gem_init(struct drm_device *dev)
9178{
1833b134 9179 intel_modeset_init_hw(dev);
02e792fb
DV		 9180
9181 intel_setup_overlay(dev);
24929352 9182
45e2b5f6 9183 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9184}
9185
9186void intel_modeset_cleanup(struct drm_device *dev)
9187{
652c393a
JB		 9188 struct drm_i915_private *dev_priv = dev->dev_private;
9189 struct drm_crtc *crtc;
9190 struct intel_crtc *intel_crtc;
9191
f87ea761 9192 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9193 mutex_lock(&dev->struct_mutex);
9194
723bfd70
JB		 9195 intel_unregister_dsm_handler();
9196
9197
652c393a
JB		 9198 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9199 /* Skip inactive CRTCs */
9200 if (!crtc->fb)
9201 continue;
9202
9203 intel_crtc = to_intel_crtc(crtc);
3dec0095 9204 intel_increase_pllclock(crtc);
652c393a
JB		 9205 }
9206
973d04f9 9207 intel_disable_fbc(dev);
e70236a8 9208
8090c6b9 9209 intel_disable_gt_powersave(dev);
0cdab21f 9210
930ebb46
DV		 9211 ironlake_teardown_rc6(dev);
9212
57f350b6
JB		 9213 if (IS_VALLEYVIEW(dev))
9214 vlv_init_dpio(dev);
9215
69341a5e
KH		 9216 mutex_unlock(&dev->struct_mutex);
9217
6c0d9350
DV		 9218 /* Disable the irq before mode object teardown, for the irq might
9219 * enqueue unpin/hotplug work. */
9220 drm_irq_uninstall(dev);
9221 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9222 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9223
1630fe75
CW		 9224 /* flush any delayed tasks or pending work */
9225 flush_scheduled_work();
9226
79e53945 9227 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9228
9229 intel_cleanup_overlay(dev);
79e53945
JB		 9230}
9231
f1c79df3
ZW		 9232/*
9233 * Return which encoder is currently attached for connector.
9234 */
df0e9248 9235struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9236{
df0e9248
CW		 9237 return &intel_attached_encoder(connector)->base;
9238}
f1c79df3 9239
df0e9248
CW		 9240void intel_connector_attach_encoder(struct intel_connector *connector,
9241 struct intel_encoder *encoder)
9242{
9243 connector->encoder = encoder;
9244 drm_mode_connector_attach_encoder(&connector->base,
9245 &encoder->base);
79e53945 9246}
28d52043
DA		 9247
9248/*
9249 * set vga decode state - true == enable VGA decode
9250 */
9251int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9252{
9253 struct drm_i915_private *dev_priv = dev->dev_private;
9254 u16 gmch_ctrl;
9255
9256 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9257 if (state)
9258 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9259 else
9260 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9261 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9262 return 0;
9263}
c4a1d9e4
CW		 9264
9265#ifdef CONFIG_DEBUG_FS
9266#include <linux/seq_file.h>
9267
9268struct intel_display_error_state {
9269 struct intel_cursor_error_state {
9270 u32 control;
9271 u32 position;
9272 u32 base;
9273 u32 size;
52331309 9274 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9275
9276 struct intel_pipe_error_state {
9277 u32 conf;
9278 u32 source;
9279
9280 u32 htotal;
9281 u32 hblank;
9282 u32 hsync;
9283 u32 vtotal;
9284 u32 vblank;
9285 u32 vsync;
52331309 9286 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9287
9288 struct intel_plane_error_state {
9289 u32 control;
9290 u32 stride;
9291 u32 size;
9292 u32 pos;
9293 u32 addr;
9294 u32 surface;
9295 u32 tile_offset;
52331309 9296 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9297};
9298
9299struct intel_display_error_state *
9300intel_display_capture_error_state(struct drm_device *dev)
9301{
0206e353 9302 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9303 struct intel_display_error_state *error;
702e7a56 9304 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9305 int i;
9306
9307 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9308 if (error == NULL)
9309 return NULL;
9310
52331309 9311 for_each_pipe(i) {
702e7a56
PZ		 9312 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9313
c4a1d9e4
CW		 9314 error->cursor[i].control = I915_READ(CURCNTR(i));
9315 error->cursor[i].position = I915_READ(CURPOS(i));
9316 error->cursor[i].base = I915_READ(CURBASE(i));
9317
9318 error->plane[i].control = I915_READ(DSPCNTR(i));
9319 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9320 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9321 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9322 error->plane[i].addr = I915_READ(DSPADDR(i));
9323 if (INTEL_INFO(dev)->gen >= 4) {
9324 error->plane[i].surface = I915_READ(DSPSURF(i));
9325 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9326 }
9327
702e7a56 9328 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9329 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9330 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9331 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9332 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9333 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9334 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9335 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9336 }
9337
9338 return error;
9339}
9340
9341void
9342intel_display_print_error_state(struct seq_file *m,
9343 struct drm_device *dev,
9344 struct intel_display_error_state *error)
9345{
52331309 9346 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9347 int i;
9348
52331309
DL		 9349 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9350 for_each_pipe(i) {
c4a1d9e4
CW		 9351 seq_printf(m, "Pipe [%d]:\n", i);
9352 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9353 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9354 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9355 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9356 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9357 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9358 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9359 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9360
9361 seq_printf(m, "Plane [%d]:\n", i);
9362 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9363 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9364 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9365 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9366 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9367 if (INTEL_INFO(dev)->gen >= 4) {
9368 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9369 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9370 }
9371
9372 seq_printf(m, "Cursor [%d]:\n", i);
9373 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9374 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9375 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9376 }
9377}
9378#endif
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