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drm/i915: Clear the stolen fb before enabling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
702e7a56 1217 reg = PIPECONF(cpu_transcoder);
b24e7179 1218 val = I915_READ(reg);
63d7bbe9
JB		 1219 cur_state = !!(val & PIPECONF_ENABLE);
1220 WARN(cur_state != state,
1221 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1222 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1223}
1224
931872fc
CW		 1225static void assert_plane(struct drm_i915_private *dev_priv,
1226 enum plane plane, bool state)
b24e7179
JB		 1227{
1228 int reg;
1229 u32 val;
931872fc 1230 bool cur_state;
b24e7179
JB		 1231
1232 reg = DSPCNTR(plane);
1233 val = I915_READ(reg);
931872fc
CW		 1234 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1235 WARN(cur_state != state,
1236 "plane %c assertion failure (expected %s, current %s)\n",
1237 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1238}
1239
931872fc
CW		 1240#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1241#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1242
b24e7179
JB		 1243static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1244 enum pipe pipe)
1245{
1246 int reg, i;
1247 u32 val;
1248 int cur_pipe;
1249
19ec1358 1250 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1251 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1252 reg = DSPCNTR(pipe);
1253 val = I915_READ(reg);
1254 WARN((val & DISPLAY_PLANE_ENABLE),
1255 "plane %c assertion failure, should be disabled but not\n",
1256 plane_name(pipe));
19ec1358 1257 return;
28c05794 1258 }
19ec1358 1259
b24e7179
JB		 1260 /* Need to check both planes against the pipe */
1261 for (i = 0; i < 2; i++) {
1262 reg = DSPCNTR(i);
1263 val = I915_READ(reg);
1264 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265 DISPPLANE_SEL_PIPE_SHIFT;
1266 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1267 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1269 }
1270}
1271
92f2584a
JB		 1272static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1273{
1274 u32 val;
1275 bool enabled;
1276
9d82aa17
ED		 1277 if (HAS_PCH_LPT(dev_priv->dev)) {
1278 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1279 return;
1280 }
1281
92f2584a
JB		 1282 val = I915_READ(PCH_DREF_CONTROL);
1283 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1284 DREF_SUPERSPREAD_SOURCE_MASK));
1285 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1286}
1287
1288static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290{
1291 int reg;
1292 u32 val;
1293 bool enabled;
1294
1295 reg = TRANSCONF(pipe);
1296 val = I915_READ(reg);
1297 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1298 WARN(enabled,
1299 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1300 pipe_name(pipe));
92f2584a
JB		 1301}
1302
4e634389
KP		 1303static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1305{
1306 if ((val & DP_PORT_EN) == 0)
1307 return false;
1308
1309 if (HAS_PCH_CPT(dev_priv->dev)) {
1310 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1311 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1312 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1313 return false;
1314 } else {
1315 if ((val & DP_PIPE_MASK) != (pipe << 30))
1316 return false;
1317 }
1318 return true;
1319}
1320
1519b995
KP		 1321static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, u32 val)
1323{
1324 if ((val & PORT_ENABLE) == 0)
1325 return false;
1326
1327 if (HAS_PCH_CPT(dev_priv->dev)) {
1328 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1329 return false;
1330 } else {
1331 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1332 return false;
1333 }
1334 return true;
1335}
1336
1337static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, u32 val)
1339{
1340 if ((val & LVDS_PORT_EN) == 0)
1341 return false;
1342
1343 if (HAS_PCH_CPT(dev_priv->dev)) {
1344 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1345 return false;
1346 } else {
1347 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1348 return false;
1349 }
1350 return true;
1351}
1352
1353static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1354 enum pipe pipe, u32 val)
1355{
1356 if ((val & ADPA_DAC_ENABLE) == 0)
1357 return false;
1358 if (HAS_PCH_CPT(dev_priv->dev)) {
1359 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1360 return false;
1361 } else {
1362 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1363 return false;
1364 }
1365 return true;
1366}
1367
291906f1 1368static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1369 enum pipe pipe, int reg, u32 port_sel)
291906f1 1370{
47a05eca 1371 u32 val = I915_READ(reg);
4e634389 1372 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1373 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1374 reg, pipe_name(pipe));
de9a35ab 1375
75c5da27
DV		 1376 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1377 && (val & DP_PIPEB_SELECT),
de9a35ab 1378 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1379}
1380
1381static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, int reg)
1383{
47a05eca 1384 u32 val = I915_READ(reg);
b70ad586 1385 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1386 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1387 reg, pipe_name(pipe));
de9a35ab 1388
75c5da27
DV		 1389 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1390 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1391 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1392}
1393
1394static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 int reg;
1398 u32 val;
291906f1 1399
f0575e92
KP		 1400 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1403
1404 reg = PCH_ADPA;
1405 val = I915_READ(reg);
b70ad586 1406 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1407 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1408 pipe_name(pipe));
291906f1
JB		 1409
1410 reg = PCH_LVDS;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1419}
1420
63d7bbe9
JB		 1421/**
1422 * intel_enable_pll - enable a PLL
1423 * @dev_priv: i915 private structure
1424 * @pipe: pipe PLL to enable
1425 *
1426 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1427 * make sure the PLL reg is writable first though, since the panel write
1428 * protect mechanism may be enabled.
1429 *
1430 * Note! This is for pre-ILK only.
7434a255
TR		 1431 *
1432 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1433 */
1434static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
1438
1439 /* No really, not for ILK+ */
a0c4da24 1440 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1441
1442 /* PLL is protected by panel, make sure we can write it */
1443 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1444 assert_panel_unlocked(dev_priv, pipe);
1445
1446 reg = DPLL(pipe);
1447 val = I915_READ(reg);
1448 val |= DPLL_VCO_ENABLE;
1449
1450 /* We do this three times for luck */
1451 I915_WRITE(reg, val);
1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460}
1461
1462/**
1463 * intel_disable_pll - disable a PLL
1464 * @dev_priv: i915 private structure
1465 * @pipe: pipe PLL to disable
1466 *
1467 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 *
1469 * Note! This is for pre-ILK only.
1470 */
1471static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1472{
1473 int reg;
1474 u32 val;
1475
1476 /* Don't disable pipe A or pipe A PLLs if needed */
1477 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1478 return;
1479
1480 /* Make sure the pipe isn't still relying on us */
1481 assert_pipe_disabled(dev_priv, pipe);
1482
1483 reg = DPLL(pipe);
1484 val = I915_READ(reg);
1485 val &= ~DPLL_VCO_ENABLE;
1486 I915_WRITE(reg, val);
1487 POSTING_READ(reg);
1488}
1489
a416edef
ED		 1490/* SBI access */
1491static void
1492intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1493{
09153000 1494 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1495
39fb50f6 1496 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1497 100)) {
1498 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1499 return;
a416edef
ED		 1500 }
1501
1502 I915_WRITE(SBI_ADDR,
1503 (reg << 16));
1504 I915_WRITE(SBI_DATA,
1505 value);
1506 I915_WRITE(SBI_CTL_STAT,
1507 SBI_BUSY |
1508 SBI_CTL_OP_CRWR);
1509
39fb50f6 1510 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1511 100)) {
1512 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1513 return;
a416edef 1514 }
a416edef
ED		 1515}
1516
1517static u32
1518intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1519{
09153000 1520 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1521
39fb50f6 1522 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1523 100)) {
1524 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1525 return 0;
a416edef
ED		 1526 }
1527
1528 I915_WRITE(SBI_ADDR,
1529 (reg << 16));
1530 I915_WRITE(SBI_CTL_STAT,
1531 SBI_BUSY |
1532 SBI_CTL_OP_CRRD);
1533
39fb50f6 1534 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1535 100)) {
1536 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1537 return 0;
a416edef
ED		 1538 }
1539
09153000 1540 return I915_READ(SBI_DATA);
a416edef
ED		 1541}
1542
92f2584a 1543/**
b6b4e185 1544 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1545 * @dev_priv: i915 private structure
1546 * @pipe: pipe PLL to enable
1547 *
1548 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1549 * drives the transcoder clock.
1550 */
b6b4e185 1551static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1552{
ee7b9f93 1553 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1554 struct intel_pch_pll *pll;
92f2584a
JB		 1555 int reg;
1556 u32 val;
1557
48da64a8 1558 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1559 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1560 pll = intel_crtc->pch_pll;
1561 if (pll == NULL)
1562 return;
1563
1564 if (WARN_ON(pll->refcount == 0))
1565 return;
ee7b9f93
JB		 1566
1567 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1568 pll->pll_reg, pll->active, pll->on,
1569 intel_crtc->base.base.id);
92f2584a
JB		 1570
1571 /* PCH refclock must be enabled first */
1572 assert_pch_refclk_enabled(dev_priv);
1573
ee7b9f93 1574 if (pll->active++ && pll->on) {
92b27b08 1575 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1576 return;
1577 }
1578
1579 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1580
1581 reg = pll->pll_reg;
92f2584a
JB		 1582 val = I915_READ(reg);
1583 val |= DPLL_VCO_ENABLE;
1584 I915_WRITE(reg, val);
1585 POSTING_READ(reg);
1586 udelay(200);
ee7b9f93
JB		 1587
1588 pll->on = true;
92f2584a
JB		 1589}
1590
ee7b9f93 1591static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1592{
ee7b9f93
JB		 1593 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1594 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1595 int reg;
ee7b9f93 1596 u32 val;
4c609cb8 1597
92f2584a
JB		 1598 /* PCH only available on ILK+ */
1599 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1600 if (pll == NULL)
1601 return;
92f2584a 1602
48da64a8
CW		 1603 if (WARN_ON(pll->refcount == 0))
1604 return;
7a419866 1605
ee7b9f93
JB		 1606 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1607 pll->pll_reg, pll->active, pll->on,
1608 intel_crtc->base.base.id);
7a419866 1609
48da64a8 1610 if (WARN_ON(pll->active == 0)) {
92b27b08 1611 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1612 return;
1613 }
1614
ee7b9f93 1615 if (--pll->active) {
92b27b08 1616 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1617 return;
ee7b9f93
JB		 1618 }
1619
1620 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1621
1622 /* Make sure transcoder isn't still depending on us */
1623 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1624
ee7b9f93 1625 reg = pll->pll_reg;
92f2584a
JB		 1626 val = I915_READ(reg);
1627 val &= ~DPLL_VCO_ENABLE;
1628 I915_WRITE(reg, val);
1629 POSTING_READ(reg);
1630 udelay(200);
ee7b9f93
JB		 1631
1632 pll->on = false;
92f2584a
JB		 1633}
1634
b8a4f404
PZ		 1635static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1636 enum pipe pipe)
040484af 1637{
23670b32 1638 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1639 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1640 uint32_t reg, val, pipeconf_val;
040484af
JB		 1641
1642 /* PCH only available on ILK+ */
1643 BUG_ON(dev_priv->info->gen < 5);
1644
1645 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1646 assert_pch_pll_enabled(dev_priv,
1647 to_intel_crtc(crtc)->pch_pll,
1648 to_intel_crtc(crtc));
040484af
JB		 1649
1650 /* FDI must be feeding us bits for PCH ports */
1651 assert_fdi_tx_enabled(dev_priv, pipe);
1652 assert_fdi_rx_enabled(dev_priv, pipe);
1653
23670b32
DV		 1654 if (HAS_PCH_CPT(dev)) {
1655 /* Workaround: Set the timing override bit before enabling the
1656 * pch transcoder. */
1657 reg = TRANS_CHICKEN2(pipe);
1658 val = I915_READ(reg);
1659 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1660 I915_WRITE(reg, val);
59c859d6 1661 }
23670b32 1662
040484af
JB		 1663 reg = TRANSCONF(pipe);
1664 val = I915_READ(reg);
5f7f726d 1665 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1666
1667 if (HAS_PCH_IBX(dev_priv->dev)) {
1668 /*
1669 * make the BPC in transcoder be consistent with
1670 * that in pipeconf reg.
1671 */
1672 val &= ~PIPE_BPC_MASK;
5f7f726d 1673 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1674 }
5f7f726d
PZ		 1675
1676 val &= ~TRANS_INTERLACE_MASK;
1677 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1678 if (HAS_PCH_IBX(dev_priv->dev) &&
1679 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1680 val |= TRANS_LEGACY_INTERLACED_ILK;
1681 else
1682 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1683 else
1684 val |= TRANS_PROGRESSIVE;
1685
040484af
JB		 1686 I915_WRITE(reg, val | TRANS_ENABLE);
1687 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1688 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1689}
1690
8fb033d7 1691static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1692 enum transcoder cpu_transcoder)
040484af 1693{
8fb033d7 1694 u32 val, pipeconf_val;
8fb033d7
PZ		 1695
1696 /* PCH only available on ILK+ */
1697 BUG_ON(dev_priv->info->gen < 5);
1698
8fb033d7 1699 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1700 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1701 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1702
223a6fdf
PZ		 1703 /* Workaround: set timing override bit. */
1704 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1706 I915_WRITE(_TRANSA_CHICKEN2, val);
1707
25f3ef11 1708 val = TRANS_ENABLE;
937bb610 1709 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1710
9a76b1c6
PZ		 1711 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1712 PIPECONF_INTERLACED_ILK)
a35f2679 1713 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1714 else
1715 val |= TRANS_PROGRESSIVE;
1716
25f3ef11 1717 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1718 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1719 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1720}
1721
b8a4f404
PZ		 1722static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1723 enum pipe pipe)
040484af 1724{
23670b32
DV		 1725 struct drm_device *dev = dev_priv->dev;
1726 uint32_t reg, val;
040484af
JB		 1727
1728 /* FDI relies on the transcoder */
1729 assert_fdi_tx_disabled(dev_priv, pipe);
1730 assert_fdi_rx_disabled(dev_priv, pipe);
1731
291906f1
JB		 1732 /* Ports must be off as well */
1733 assert_pch_ports_disabled(dev_priv, pipe);
1734
040484af
JB		 1735 reg = TRANSCONF(pipe);
1736 val = I915_READ(reg);
1737 val &= ~TRANS_ENABLE;
1738 I915_WRITE(reg, val);
1739 /* wait for PCH transcoder off, transcoder state */
1740 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1741 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1742
1743 if (!HAS_PCH_IBX(dev)) {
1744 /* Workaround: Clear the timing override chicken bit again. */
1745 reg = TRANS_CHICKEN2(pipe);
1746 val = I915_READ(reg);
1747 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1748 I915_WRITE(reg, val);
1749 }
040484af
JB		 1750}
1751
ab4d966c 1752static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1753{
8fb033d7
PZ		 1754 u32 val;
1755
8a52fd9f 1756 val = I915_READ(_TRANSACONF);
8fb033d7 1757 val &= ~TRANS_ENABLE;
8a52fd9f 1758 I915_WRITE(_TRANSACONF, val);
8fb033d7 1759 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1760 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1761 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1762
1763 /* Workaround: clear timing override bit. */
1764 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1765 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1766 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1767}
1768
b24e7179 1769/**
309cfea8 1770 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1771 * @dev_priv: i915 private structure
1772 * @pipe: pipe to enable
040484af 1773 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1774 *
1775 * Enable @pipe, making sure that various hardware specific requirements
1776 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1777 *
1778 * @pipe should be %PIPE_A or %PIPE_B.
1779 *
1780 * Will wait until the pipe is actually running (i.e. first vblank) before
1781 * returning.
1782 */
040484af
JB		 1783static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1784 bool pch_port)
b24e7179 1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
1a240d4d 1788 enum pipe pch_transcoder;
b24e7179
JB		 1789 int reg;
1790 u32 val;
1791
cc391bbb
PZ		 1792 if (IS_HASWELL(dev_priv->dev))
1793 pch_transcoder = TRANSCODER_A;
1794 else
1795 pch_transcoder = pipe;
1796
b24e7179
JB		 1797 /*
1798 * A pipe without a PLL won't actually be able to drive bits from
1799 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1800 * need the check.
1801 */
1802 if (!HAS_PCH_SPLIT(dev_priv->dev))
1803 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1804 else {
1805 if (pch_port) {
1806 /* if driving the PCH, we need FDI enabled */
cc391bbb 1807 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1808 assert_fdi_tx_pll_enabled(dev_priv,
1809 (enum pipe) cpu_transcoder);
040484af
JB		 1810 }
1811 /* FIXME: assert CPU port conditions for SNB+ */
1812 }
b24e7179 1813
702e7a56 1814 reg = PIPECONF(cpu_transcoder);
b24e7179 1815 val = I915_READ(reg);
00d70b15
CW		 1816 if (val & PIPECONF_ENABLE)
1817 return;
1818
1819 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1820 intel_wait_for_vblank(dev_priv->dev, pipe);
1821}
1822
1823/**
309cfea8 1824 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1825 * @dev_priv: i915 private structure
1826 * @pipe: pipe to disable
1827 *
1828 * Disable @pipe, making sure that various hardware specific requirements
1829 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1830 *
1831 * @pipe should be %PIPE_A or %PIPE_B.
1832 *
1833 * Will wait until the pipe has shut down before returning.
1834 */
1835static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1836 enum pipe pipe)
1837{
702e7a56
PZ		 1838 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1839 pipe);
b24e7179
JB		 1840 int reg;
1841 u32 val;
1842
1843 /*
1844 * Make sure planes won't keep trying to pump pixels to us,
1845 * or we might hang the display.
1846 */
1847 assert_planes_disabled(dev_priv, pipe);
1848
1849 /* Don't disable pipe A or pipe A PLLs if needed */
1850 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1851 return;
1852
702e7a56 1853 reg = PIPECONF(cpu_transcoder);
b24e7179 1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & PIPECONF_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1859 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1860}
1861
d74362c9
KP		 1862/*
1863 * Plane regs are double buffered, going from enabled->disabled needs a
1864 * trigger in order to latch. The display address reg provides this.
1865 */
6f1d69b0 1866void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1867 enum plane plane)
1868{
14f86147
DL		 1869 if (dev_priv->info->gen >= 4)
1870 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1871 else
1872 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1873}
1874
b24e7179
JB		 1875/**
1876 * intel_enable_plane - enable a display plane on a given pipe
1877 * @dev_priv: i915 private structure
1878 * @plane: plane to enable
1879 * @pipe: pipe being fed
1880 *
1881 * Enable @plane on @pipe, making sure that @pipe is running first.
1882 */
1883static void intel_enable_plane(struct drm_i915_private *dev_priv,
1884 enum plane plane, enum pipe pipe)
1885{
1886 int reg;
1887 u32 val;
1888
1889 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1890 assert_pipe_enabled(dev_priv, pipe);
1891
1892 reg = DSPCNTR(plane);
1893 val = I915_READ(reg);
00d70b15
CW		 1894 if (val & DISPLAY_PLANE_ENABLE)
1895 return;
1896
1897 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1898 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1899 intel_wait_for_vblank(dev_priv->dev, pipe);
1900}
1901
b24e7179
JB		 1902/**
1903 * intel_disable_plane - disable a display plane
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to disable
1906 * @pipe: pipe consuming the data
1907 *
1908 * Disable @plane; should be an independent operation.
1909 */
1910static void intel_disable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 reg = DSPCNTR(plane);
1917 val = I915_READ(reg);
00d70b15
CW		 1918 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1919 return;
1920
1921 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1922 intel_flush_display_plane(dev_priv, plane);
1923 intel_wait_for_vblank(dev_priv->dev, pipe);
1924}
1925
127bd2ac 1926int
48b956c5 1927intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1928 struct drm_i915_gem_object *obj,
919926ae 1929 struct intel_ring_buffer *pipelined)
6b95a207 1930{
ce453d81 1931 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1932 u32 alignment;
1933 int ret;
1934
05394f39 1935 switch (obj->tiling_mode) {
6b95a207 1936 case I915_TILING_NONE:
534843da
CW		 1937 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1938 alignment = 128 * 1024;
a6c45cf0 1939 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1940 alignment = 4 * 1024;
1941 else
1942 alignment = 64 * 1024;
6b95a207
KH		 1943 break;
1944 case I915_TILING_X:
1945 /* pin() will align the object as required by fence */
1946 alignment = 0;
1947 break;
1948 case I915_TILING_Y:
1949 /* FIXME: Is this true? */
1950 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1951 return -EINVAL;
1952 default:
1953 BUG();
1954 }
1955
ce453d81 1956 dev_priv->mm.interruptible = false;
2da3b9b9 1957 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1958 if (ret)
ce453d81 1959 goto err_interruptible;
6b95a207
KH		 1960
1961 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1962 * fence, whereas 965+ only requires a fence if using
1963 * framebuffer compression. For simplicity, we always install
1964 * a fence as the cost is not that onerous.
1965 */
06d98131 1966 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1967 if (ret)
1968 goto err_unpin;
1690e1eb 1969
9a5a53b3 1970 i915_gem_object_pin_fence(obj);
6b95a207 1971
ce453d81 1972 dev_priv->mm.interruptible = true;
6b95a207 1973 return 0;
48b956c5
CW		 1974
1975err_unpin:
1976 i915_gem_object_unpin(obj);
ce453d81
CW		 1977err_interruptible:
1978 dev_priv->mm.interruptible = true;
48b956c5 1979 return ret;
6b95a207
KH		 1980}
1981
1690e1eb
CW		 1982void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1983{
1984 i915_gem_object_unpin_fence(obj);
1985 i915_gem_object_unpin(obj);
1986}
1987
c2c75131
DV		 1988/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1989 * is assumed to be a power-of-two. */
5a35e99e
DL		 1990unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1991 unsigned int bpp,
1992 unsigned int pitch)
c2c75131
DV		 1993{
1994 int tile_rows, tiles;
1995
1996 tile_rows = *y / 8;
1997 *y %= 8;
1998 tiles = *x / (512/bpp);
1999 *x %= 512/bpp;
2000
2001 return tile_rows * pitch * 8 + tiles * 4096;
2002}
2003
17638cd6
JB		 2004static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2005 int x, int y)
81255565
JB		 2006{
2007 struct drm_device *dev = crtc->dev;
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2010 struct intel_framebuffer *intel_fb;
05394f39 2011 struct drm_i915_gem_object *obj;
81255565 2012 int plane = intel_crtc->plane;
e506a0c6 2013 unsigned long linear_offset;
81255565 2014 u32 dspcntr;
5eddb70b 2015 u32 reg;
81255565
JB		 2016
2017 switch (plane) {
2018 case 0:
2019 case 1:
2020 break;
2021 default:
2022 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2023 return -EINVAL;
2024 }
2025
2026 intel_fb = to_intel_framebuffer(fb);
2027 obj = intel_fb->obj;
81255565 2028
5eddb70b
CW		 2029 reg = DSPCNTR(plane);
2030 dspcntr = I915_READ(reg);
81255565
JB		 2031 /* Mask out pixel format bits in case we change it */
2032 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2033 switch (fb->pixel_format) {
2034 case DRM_FORMAT_C8:
81255565
JB		 2035 dspcntr |= DISPPLANE_8BPP;
2036 break;
57779d06
VS		 2037 case DRM_FORMAT_XRGB1555:
2038 case DRM_FORMAT_ARGB1555:
2039 dspcntr |= DISPPLANE_BGRX555;
81255565 2040 break;
57779d06
VS		 2041 case DRM_FORMAT_RGB565:
2042 dspcntr |= DISPPLANE_BGRX565;
2043 break;
2044 case DRM_FORMAT_XRGB8888:
2045 case DRM_FORMAT_ARGB8888:
2046 dspcntr |= DISPPLANE_BGRX888;
2047 break;
2048 case DRM_FORMAT_XBGR8888:
2049 case DRM_FORMAT_ABGR8888:
2050 dspcntr |= DISPPLANE_RGBX888;
2051 break;
2052 case DRM_FORMAT_XRGB2101010:
2053 case DRM_FORMAT_ARGB2101010:
2054 dspcntr |= DISPPLANE_BGRX101010;
2055 break;
2056 case DRM_FORMAT_XBGR2101010:
2057 case DRM_FORMAT_ABGR2101010:
2058 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2059 break;
2060 default:
57779d06 2061 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2062 return -EINVAL;
2063 }
57779d06 2064
a6c45cf0 2065 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2066 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2067 dspcntr |= DISPPLANE_TILED;
2068 else
2069 dspcntr &= ~DISPPLANE_TILED;
2070 }
2071
5eddb70b 2072 I915_WRITE(reg, dspcntr);
81255565 2073
e506a0c6 2074 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2075
c2c75131
DV		 2076 if (INTEL_INFO(dev)->gen >= 4) {
2077 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2078 intel_gen4_compute_offset_xtiled(&x, &y,
2079 fb->bits_per_pixel / 8,
2080 fb->pitches[0]);
c2c75131
DV		 2081 linear_offset -= intel_crtc->dspaddr_offset;
2082 } else {
e506a0c6 2083 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2084 }
e506a0c6
DV		 2085
2086 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2087 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2088 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2089 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2090 I915_MODIFY_DISPBASE(DSPSURF(plane),
2091 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2092 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2093 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2094 } else
e506a0c6 2095 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2096 POSTING_READ(reg);
81255565 2097
17638cd6
JB		 2098 return 0;
2099}
2100
2101static int ironlake_update_plane(struct drm_crtc *crtc,
2102 struct drm_framebuffer *fb, int x, int y)
2103{
2104 struct drm_device *dev = crtc->dev;
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2107 struct intel_framebuffer *intel_fb;
2108 struct drm_i915_gem_object *obj;
2109 int plane = intel_crtc->plane;
e506a0c6 2110 unsigned long linear_offset;
17638cd6
JB		 2111 u32 dspcntr;
2112 u32 reg;
2113
2114 switch (plane) {
2115 case 0:
2116 case 1:
27f8227b 2117 case 2:
17638cd6
JB		 2118 break;
2119 default:
2120 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2121 return -EINVAL;
2122 }
2123
2124 intel_fb = to_intel_framebuffer(fb);
2125 obj = intel_fb->obj;
2126
2127 reg = DSPCNTR(plane);
2128 dspcntr = I915_READ(reg);
2129 /* Mask out pixel format bits in case we change it */
2130 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2131 switch (fb->pixel_format) {
2132 case DRM_FORMAT_C8:
17638cd6
JB		 2133 dspcntr |= DISPPLANE_8BPP;
2134 break;
57779d06
VS		 2135 case DRM_FORMAT_RGB565:
2136 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2137 break;
57779d06
VS		 2138 case DRM_FORMAT_XRGB8888:
2139 case DRM_FORMAT_ARGB8888:
2140 dspcntr |= DISPPLANE_BGRX888;
2141 break;
2142 case DRM_FORMAT_XBGR8888:
2143 case DRM_FORMAT_ABGR8888:
2144 dspcntr |= DISPPLANE_RGBX888;
2145 break;
2146 case DRM_FORMAT_XRGB2101010:
2147 case DRM_FORMAT_ARGB2101010:
2148 dspcntr |= DISPPLANE_BGRX101010;
2149 break;
2150 case DRM_FORMAT_XBGR2101010:
2151 case DRM_FORMAT_ABGR2101010:
2152 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2153 break;
2154 default:
57779d06 2155 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2156 return -EINVAL;
2157 }
2158
2159 if (obj->tiling_mode != I915_TILING_NONE)
2160 dspcntr |= DISPPLANE_TILED;
2161 else
2162 dspcntr &= ~DISPPLANE_TILED;
2163
2164 /* must disable */
2165 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2166
2167 I915_WRITE(reg, dspcntr);
2168
e506a0c6 2169 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2170 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2171 intel_gen4_compute_offset_xtiled(&x, &y,
2172 fb->bits_per_pixel / 8,
2173 fb->pitches[0]);
c2c75131 2174 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2175
e506a0c6
DV		 2176 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2177 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2178 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2179 I915_MODIFY_DISPBASE(DSPSURF(plane),
2180 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2181 if (IS_HASWELL(dev)) {
2182 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2183 } else {
2184 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2185 I915_WRITE(DSPLINOFF(plane), linear_offset);
2186 }
17638cd6
JB		 2187 POSTING_READ(reg);
2188
2189 return 0;
2190}
2191
2192/* Assume fb object is pinned & idle & fenced and just update base pointers */
2193static int
2194intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2195 int x, int y, enum mode_set_atomic state)
2196{
2197 struct drm_device *dev = crtc->dev;
2198 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2199
6b8e6ed0
CW		 2200 if (dev_priv->display.disable_fbc)
2201 dev_priv->display.disable_fbc(dev);
3dec0095 2202 intel_increase_pllclock(crtc);
81255565 2203
6b8e6ed0 2204 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2205}
2206
14667a4b
CW		 2207static int
2208intel_finish_fb(struct drm_framebuffer *old_fb)
2209{
2210 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2211 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212 bool was_interruptible = dev_priv->mm.interruptible;
2213 int ret;
2214
2215 wait_event(dev_priv->pending_flip_queue,
2216 atomic_read(&dev_priv->mm.wedged) ||
2217 atomic_read(&obj->pending_flip) == 0);
2218
2219 /* Big Hammer, we also need to ensure that any pending
2220 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2221 * current scanout is retired before unpinning the old
2222 * framebuffer.
2223 *
2224 * This should only fail upon a hung GPU, in which case we
2225 * can safely continue.
2226 */
2227 dev_priv->mm.interruptible = false;
2228 ret = i915_gem_object_finish_gpu(obj);
2229 dev_priv->mm.interruptible = was_interruptible;
2230
2231 return ret;
2232}
2233
198598d0
VS		 2234static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2235{
2236 struct drm_device *dev = crtc->dev;
2237 struct drm_i915_master_private *master_priv;
2238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2239
2240 if (!dev->primary->master)
2241 return;
2242
2243 master_priv = dev->primary->master->driver_priv;
2244 if (!master_priv->sarea_priv)
2245 return;
2246
2247 switch (intel_crtc->pipe) {
2248 case 0:
2249 master_priv->sarea_priv->pipeA_x = x;
2250 master_priv->sarea_priv->pipeA_y = y;
2251 break;
2252 case 1:
2253 master_priv->sarea_priv->pipeB_x = x;
2254 master_priv->sarea_priv->pipeB_y = y;
2255 break;
2256 default:
2257 break;
2258 }
2259}
2260
5c3b82e2 2261static int
3c4fdcfb 2262intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2263 struct drm_framebuffer *fb)
79e53945
JB		 2264{
2265 struct drm_device *dev = crtc->dev;
6b8e6ed0 2266 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2268 struct drm_framebuffer *old_fb;
5c3b82e2 2269 int ret;
79e53945
JB		 2270
2271 /* no fb bound */
94352cf9 2272 if (!fb) {
a5071c2f 2273 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2274 return 0;
2275 }
2276
5826eca5
ED		 2277 if(intel_crtc->plane > dev_priv->num_pipe) {
2278 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2279 intel_crtc->plane,
2280 dev_priv->num_pipe);
5c3b82e2 2281 return -EINVAL;
79e53945
JB		 2282 }
2283
5c3b82e2 2284 mutex_lock(&dev->struct_mutex);
265db958 2285 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2286 to_intel_framebuffer(fb)->obj,
919926ae 2287 NULL);
5c3b82e2
CW		 2288 if (ret != 0) {
2289 mutex_unlock(&dev->struct_mutex);
a5071c2f 2290 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2291 return ret;
2292 }
79e53945 2293
94352cf9
DV		 2294 if (crtc->fb)
2295 intel_finish_fb(crtc->fb);
265db958 2296
94352cf9 2297 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2298 if (ret) {
94352cf9 2299 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("failed to update base address\n");
4e6cfefc 2302 return ret;
79e53945 2303 }
3c4fdcfb 2304
94352cf9
DV		 2305 old_fb = crtc->fb;
2306 crtc->fb = fb;
6c4c86f5
DV		 2307 crtc->x = x;
2308 crtc->y = y;
94352cf9 2309
b7f1de28
CW		 2310 if (old_fb) {
2311 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2312 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2313 }
652c393a 2314
6b8e6ed0 2315 intel_update_fbc(dev);
5c3b82e2 2316 mutex_unlock(&dev->struct_mutex);
79e53945 2317
198598d0 2318 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2319
2320 return 0;
79e53945
JB		 2321}
2322
5e84e1a4
ZW		 2323static void intel_fdi_normal_train(struct drm_crtc *crtc)
2324{
2325 struct drm_device *dev = crtc->dev;
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328 int pipe = intel_crtc->pipe;
2329 u32 reg, temp;
2330
2331 /* enable normal train */
2332 reg = FDI_TX_CTL(pipe);
2333 temp = I915_READ(reg);
61e499bf 2334 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2335 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2336 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2337 } else {
2338 temp &= ~FDI_LINK_TRAIN_NONE;
2339 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2340 }
5e84e1a4
ZW		 2341 I915_WRITE(reg, temp);
2342
2343 reg = FDI_RX_CTL(pipe);
2344 temp = I915_READ(reg);
2345 if (HAS_PCH_CPT(dev)) {
2346 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2347 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2348 } else {
2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_NONE;
2351 }
2352 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2353
2354 /* wait one idle pattern time */
2355 POSTING_READ(reg);
2356 udelay(1000);
357555c0
JB		 2357
2358 /* IVB wants error correction enabled */
2359 if (IS_IVYBRIDGE(dev))
2360 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2361 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2362}
2363
291427f5
JB		 2364static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2365{
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 u32 flags = I915_READ(SOUTH_CHICKEN1);
2368
2369 flags |= FDI_PHASE_SYNC_OVR(pipe);
2370 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2371 flags |= FDI_PHASE_SYNC_EN(pipe);
2372 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2373 POSTING_READ(SOUTH_CHICKEN1);
2374}
2375
01a415fd
DV		 2376static void ivb_modeset_global_resources(struct drm_device *dev)
2377{
2378 struct drm_i915_private *dev_priv = dev->dev_private;
2379 struct intel_crtc *pipe_B_crtc =
2380 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2381 struct intel_crtc *pipe_C_crtc =
2382 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2383 uint32_t temp;
2384
2385 /* When everything is off disable fdi C so that we could enable fdi B
2386 * with all lanes. XXX: This misses the case where a pipe is not using
2387 * any pch resources and so doesn't need any fdi lanes. */
2388 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2389 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2390 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2391
2392 temp = I915_READ(SOUTH_CHICKEN1);
2393 temp &= ~FDI_BC_BIFURCATION_SELECT;
2394 DRM_DEBUG_KMS("disabling fdi C rx\n");
2395 I915_WRITE(SOUTH_CHICKEN1, temp);
2396 }
2397}
2398
8db9d77b
ZW		 2399/* The FDI link training functions for ILK/Ibexpeak. */
2400static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2401{
2402 struct drm_device *dev = crtc->dev;
2403 struct drm_i915_private *dev_priv = dev->dev_private;
2404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2405 int pipe = intel_crtc->pipe;
0fc932b8 2406 int plane = intel_crtc->plane;
5eddb70b 2407 u32 reg, temp, tries;
8db9d77b 2408
0fc932b8
JB		 2409 /* FDI needs bits from pipe & plane first */
2410 assert_pipe_enabled(dev_priv, pipe);
2411 assert_plane_enabled(dev_priv, plane);
2412
e1a44743
AJ		 2413 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2414 for train result */
5eddb70b
CW		 2415 reg = FDI_RX_IMR(pipe);
2416 temp = I915_READ(reg);
e1a44743
AJ		 2417 temp &= ~FDI_RX_SYMBOL_LOCK;
2418 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2419 I915_WRITE(reg, temp);
2420 I915_READ(reg);
e1a44743
AJ		 2421 udelay(150);
2422
8db9d77b 2423 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
77ffb597
AJ		 2426 temp &= ~(7 << 19);
2427 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2430 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2431
5eddb70b
CW		 2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
8db9d77b
ZW		 2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2436 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2437
2438 POSTING_READ(reg);
8db9d77b
ZW		 2439 udelay(150);
2440
5b2adf89 2441 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2442 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2443 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2444 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2445
5eddb70b 2446 reg = FDI_RX_IIR(pipe);
e1a44743 2447 for (tries = 0; tries < 5; tries++) {
5eddb70b 2448 temp = I915_READ(reg);
8db9d77b
ZW		 2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450
2451 if ((temp & FDI_RX_BIT_LOCK)) {
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2453 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2454 break;
2455 }
8db9d77b 2456 }
e1a44743 2457 if (tries == 5)
5eddb70b 2458 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2459
2460 /* Train 2 */
5eddb70b
CW		 2461 reg = FDI_TX_CTL(pipe);
2462 temp = I915_READ(reg);
8db9d77b
ZW		 2463 temp &= ~FDI_LINK_TRAIN_NONE;
2464 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2465 I915_WRITE(reg, temp);
8db9d77b 2466
5eddb70b
CW		 2467 reg = FDI_RX_CTL(pipe);
2468 temp = I915_READ(reg);
8db9d77b
ZW		 2469 temp &= ~FDI_LINK_TRAIN_NONE;
2470 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2471 I915_WRITE(reg, temp);
8db9d77b 2472
5eddb70b
CW		 2473 POSTING_READ(reg);
2474 udelay(150);
8db9d77b 2475
5eddb70b 2476 reg = FDI_RX_IIR(pipe);
e1a44743 2477 for (tries = 0; tries < 5; tries++) {
5eddb70b 2478 temp = I915_READ(reg);
8db9d77b
ZW		 2479 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2480
2481 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2482 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI train 2 done.\n");
2484 break;
2485 }
8db9d77b 2486 }
e1a44743 2487 if (tries == 5)
5eddb70b 2488 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2489
2490 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2491
8db9d77b
ZW		 2492}
2493
0206e353 2494static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2495 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2496 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2497 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2498 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2499};
2500
2501/* The FDI link training functions for SNB/Cougarpoint. */
2502static void gen6_fdi_link_train(struct drm_crtc *crtc)
2503{
2504 struct drm_device *dev = crtc->dev;
2505 struct drm_i915_private *dev_priv = dev->dev_private;
2506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2507 int pipe = intel_crtc->pipe;
fa37d39e 2508 u32 reg, temp, i, retry;
8db9d77b 2509
e1a44743
AJ		 2510 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2511 for train result */
5eddb70b
CW		 2512 reg = FDI_RX_IMR(pipe);
2513 temp = I915_READ(reg);
e1a44743
AJ		 2514 temp &= ~FDI_RX_SYMBOL_LOCK;
2515 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2516 I915_WRITE(reg, temp);
2517
2518 POSTING_READ(reg);
e1a44743
AJ		 2519 udelay(150);
2520
8db9d77b 2521 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2522 reg = FDI_TX_CTL(pipe);
2523 temp = I915_READ(reg);
77ffb597
AJ		 2524 temp &= ~(7 << 19);
2525 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1;
2528 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2529 /* SNB-B */
2530 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2531 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2532
d74cf324
DV		 2533 I915_WRITE(FDI_RX_MISC(pipe),
2534 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2535
5eddb70b
CW		 2536 reg = FDI_RX_CTL(pipe);
2537 temp = I915_READ(reg);
8db9d77b
ZW		 2538 if (HAS_PCH_CPT(dev)) {
2539 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2540 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2541 } else {
2542 temp &= ~FDI_LINK_TRAIN_NONE;
2543 temp |= FDI_LINK_TRAIN_PATTERN_1;
2544 }
5eddb70b
CW		 2545 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2546
2547 POSTING_READ(reg);
8db9d77b
ZW		 2548 udelay(150);
2549
8f5718a6 2550 cpt_phase_pointer_enable(dev, pipe);
291427f5 2551
0206e353 2552 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
8db9d77b
ZW		 2555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2556 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2557 I915_WRITE(reg, temp);
2558
2559 POSTING_READ(reg);
8db9d77b
ZW		 2560 udelay(500);
2561
fa37d39e
SP		 2562 for (retry = 0; retry < 5; retry++) {
2563 reg = FDI_RX_IIR(pipe);
2564 temp = I915_READ(reg);
2565 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2566 if (temp & FDI_RX_BIT_LOCK) {
2567 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2568 DRM_DEBUG_KMS("FDI train 1 done.\n");
2569 break;
2570 }
2571 udelay(50);
8db9d77b 2572 }
fa37d39e
SP		 2573 if (retry < 5)
2574 break;
8db9d77b
ZW		 2575 }
2576 if (i == 4)
5eddb70b 2577 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2578
2579 /* Train 2 */
5eddb70b
CW		 2580 reg = FDI_TX_CTL(pipe);
2581 temp = I915_READ(reg);
8db9d77b
ZW		 2582 temp &= ~FDI_LINK_TRAIN_NONE;
2583 temp |= FDI_LINK_TRAIN_PATTERN_2;
2584 if (IS_GEN6(dev)) {
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 /* SNB-B */
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2588 }
5eddb70b 2589 I915_WRITE(reg, temp);
8db9d77b 2590
5eddb70b
CW		 2591 reg = FDI_RX_CTL(pipe);
2592 temp = I915_READ(reg);
8db9d77b
ZW		 2593 if (HAS_PCH_CPT(dev)) {
2594 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2595 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2596 } else {
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_2;
2599 }
5eddb70b
CW		 2600 I915_WRITE(reg, temp);
2601
2602 POSTING_READ(reg);
8db9d77b
ZW		 2603 udelay(150);
2604
0206e353 2605 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2606 reg = FDI_TX_CTL(pipe);
2607 temp = I915_READ(reg);
8db9d77b
ZW		 2608 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2609 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
8db9d77b
ZW		 2613 udelay(500);
2614
fa37d39e
SP		 2615 for (retry = 0; retry < 5; retry++) {
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619 if (temp & FDI_RX_SYMBOL_LOCK) {
2620 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2621 DRM_DEBUG_KMS("FDI train 2 done.\n");
2622 break;
2623 }
2624 udelay(50);
8db9d77b 2625 }
fa37d39e
SP		 2626 if (retry < 5)
2627 break;
8db9d77b
ZW		 2628 }
2629 if (i == 4)
5eddb70b 2630 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2631
2632 DRM_DEBUG_KMS("FDI train done.\n");
2633}
2634
357555c0
JB		 2635/* Manual link training for Ivy Bridge A0 parts */
2636static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2637{
2638 struct drm_device *dev = crtc->dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2641 int pipe = intel_crtc->pipe;
2642 u32 reg, temp, i;
2643
2644 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2645 for train result */
2646 reg = FDI_RX_IMR(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_RX_SYMBOL_LOCK;
2649 temp &= ~FDI_RX_BIT_LOCK;
2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
2653 udelay(150);
2654
01a415fd
DV		 2655 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2656 I915_READ(FDI_RX_IIR(pipe)));
2657
357555c0
JB		 2658 /* enable CPU FDI TX and PCH FDI RX */
2659 reg = FDI_TX_CTL(pipe);
2660 temp = I915_READ(reg);
2661 temp &= ~(7 << 19);
2662 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2663 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2664 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2667 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2668 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2669
d74cf324
DV		 2670 I915_WRITE(FDI_RX_MISC(pipe),
2671 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2672
357555c0
JB		 2673 reg = FDI_RX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_AUTO;
2676 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2677 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2678 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2679 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2680
2681 POSTING_READ(reg);
2682 udelay(150);
2683
8f5718a6 2684 cpt_phase_pointer_enable(dev, pipe);
291427f5 2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 1 fail!\n");
2709
2710 /* Train 2 */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2718
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
0206e353 2728 for (i = 0; i < 4; i++) {
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2745 break;
2746 }
2747 }
2748 if (i == 4)
2749 DRM_ERROR("FDI train 2 fail!\n");
2750
2751 DRM_DEBUG_KMS("FDI train done.\n");
2752}
2753
88cefb6c 2754static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2755{
88cefb6c 2756 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2757 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2758 int pipe = intel_crtc->pipe;
5eddb70b 2759 u32 reg, temp;
79e53945 2760
c64e311e 2761
c98e9dcf 2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2766 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
c98e9dcf
JB		 2771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
c98e9dcf
JB		 2778 udelay(200);
2779
20749730
PZ		 2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2785
20749730
PZ		 2786 POSTING_READ(reg);
2787 udelay(100);
6be4a607 2788 }
0e23b99d
JB		 2789}
2790
88cefb6c
DV		 2791static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792{
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808 POSTING_READ(reg);
2809 udelay(100);
2810
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815 /* Wait for the clocks to turn off. */
2816 POSTING_READ(reg);
2817 udelay(100);
2818}
2819
291427f5
JB		 2820static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2821{
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 u32 flags = I915_READ(SOUTH_CHICKEN1);
2824
2825 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2826 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2827 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2828 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2829 POSTING_READ(SOUTH_CHICKEN1);
2830}
0fc932b8
JB		 2831static void ironlake_fdi_disable(struct drm_crtc *crtc)
2832{
2833 struct drm_device *dev = crtc->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2836 int pipe = intel_crtc->pipe;
2837 u32 reg, temp;
2838
2839 /* disable CPU FDI tx and PCH FDI rx */
2840 reg = FDI_TX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2843 POSTING_READ(reg);
2844
2845 reg = FDI_RX_CTL(pipe);
2846 temp = I915_READ(reg);
2847 temp &= ~(0x7 << 16);
2848 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2849 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2850
2851 POSTING_READ(reg);
2852 udelay(100);
2853
2854 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2855 if (HAS_PCH_IBX(dev)) {
2856 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
291427f5
JB		 2857 } else if (HAS_PCH_CPT(dev)) {
2858 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2859 }
0fc932b8
JB		 2860
2861 /* still set train pattern 1 */
2862 reg = FDI_TX_CTL(pipe);
2863 temp = I915_READ(reg);
2864 temp &= ~FDI_LINK_TRAIN_NONE;
2865 temp |= FDI_LINK_TRAIN_PATTERN_1;
2866 I915_WRITE(reg, temp);
2867
2868 reg = FDI_RX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 if (HAS_PCH_CPT(dev)) {
2871 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2872 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2873 } else {
2874 temp &= ~FDI_LINK_TRAIN_NONE;
2875 temp |= FDI_LINK_TRAIN_PATTERN_1;
2876 }
2877 /* BPC in FDI rx is consistent with that in PIPECONF */
2878 temp &= ~(0x07 << 16);
2879 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2880 I915_WRITE(reg, temp);
2881
2882 POSTING_READ(reg);
2883 udelay(100);
2884}
2885
5bb61643
CW		 2886static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2887{
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 unsigned long flags;
2891 bool pending;
2892
2893 if (atomic_read(&dev_priv->mm.wedged))
2894 return false;
2895
2896 spin_lock_irqsave(&dev->event_lock, flags);
2897 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2898 spin_unlock_irqrestore(&dev->event_lock, flags);
2899
2900 return pending;
2901}
2902
e6c3a2a6
CW		 2903static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2904{
0f91128d 2905 struct drm_device *dev = crtc->dev;
5bb61643 2906 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2907
2908 if (crtc->fb == NULL)
2909 return;
2910
5bb61643
CW		 2911 wait_event(dev_priv->pending_flip_queue,
2912 !intel_crtc_has_pending_flip(crtc));
2913
0f91128d
CW		 2914 mutex_lock(&dev->struct_mutex);
2915 intel_finish_fb(crtc->fb);
2916 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2917}
2918
fc316cbe 2919static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2920{
2921 struct drm_device *dev = crtc->dev;
228d3e36 2922 struct intel_encoder *intel_encoder;
040484af
JB		 2923
2924 /*
2925 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2926 * must be driven by its own crtc; no sharing is possible.
2927 */
228d3e36 2928 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2929 switch (intel_encoder->type) {
040484af 2930 case INTEL_OUTPUT_EDP:
228d3e36 2931 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2932 return false;
2933 continue;
2934 }
2935 }
2936
2937 return true;
2938}
2939
fc316cbe
PZ		 2940static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2941{
2942 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2943}
2944
e615efe4
ED		 2945/* Program iCLKIP clock to the desired frequency */
2946static void lpt_program_iclkip(struct drm_crtc *crtc)
2947{
2948 struct drm_device *dev = crtc->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2951 u32 temp;
2952
09153000
DV		 2953 mutex_lock(&dev_priv->dpio_lock);
2954
e615efe4
ED		 2955 /* It is necessary to ungate the pixclk gate prior to programming
2956 * the divisors, and gate it back when it is done.
2957 */
2958 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2959
2960 /* Disable SSCCTL */
2961 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2962 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2963 SBI_SSCCTL_DISABLE);
2964
2965 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2966 if (crtc->mode.clock == 20000) {
2967 auxdiv = 1;
2968 divsel = 0x41;
2969 phaseinc = 0x20;
2970 } else {
2971 /* The iCLK virtual clock root frequency is in MHz,
2972 * but the crtc->mode.clock in in KHz. To get the divisors,
2973 * it is necessary to divide one by another, so we
2974 * convert the virtual clock precision to KHz here for higher
2975 * precision.
2976 */
2977 u32 iclk_virtual_root_freq = 172800 * 1000;
2978 u32 iclk_pi_range = 64;
2979 u32 desired_divisor, msb_divisor_value, pi_value;
2980
2981 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2982 msb_divisor_value = desired_divisor / iclk_pi_range;
2983 pi_value = desired_divisor % iclk_pi_range;
2984
2985 auxdiv = 0;
2986 divsel = msb_divisor_value - 2;
2987 phaseinc = pi_value;
2988 }
2989
2990 /* This should not happen with any sane values */
2991 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2992 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2993 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2994 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2995
2996 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2997 crtc->mode.clock,
2998 auxdiv,
2999 divsel,
3000 phasedir,
3001 phaseinc);
3002
3003 /* Program SSCDIVINTPHASE6 */
3004 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3005 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3006 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3007 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3008 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3009 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3010 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3011
3012 intel_sbi_write(dev_priv,
3013 SBI_SSCDIVINTPHASE6,
3014 temp);
3015
3016 /* Program SSCAUXDIV */
3017 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3018 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3019 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3020 intel_sbi_write(dev_priv,
3021 SBI_SSCAUXDIV6,
3022 temp);
3023
3024
3025 /* Enable modulator and associated divider */
3026 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3027 temp &= ~SBI_SSCCTL_DISABLE;
3028 intel_sbi_write(dev_priv,
3029 SBI_SSCCTL6,
3030 temp);
3031
3032 /* Wait for initialization time */
3033 udelay(24);
3034
3035 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3036
3037 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3038}
3039
f67a559d
JB		 3040/*
3041 * Enable PCH resources required for PCH ports:
3042 * - PCH PLLs
3043 * - FDI training & RX/TX
3044 * - update transcoder timings
3045 * - DP transcoding bits
3046 * - transcoder
3047 */
3048static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3049{
3050 struct drm_device *dev = crtc->dev;
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3053 int pipe = intel_crtc->pipe;
ee7b9f93 3054 u32 reg, temp;
2c07245f 3055
e7e164db
CW		 3056 assert_transcoder_disabled(dev_priv, pipe);
3057
cd986abb
DV		 3058 /* Write the TU size bits before fdi link training, so that error
3059 * detection works. */
3060 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3061 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3062
c98e9dcf 3063 /* For PCH output, training FDI link */
674cf967 3064 dev_priv->display.fdi_link_train(crtc);
2c07245f 3065
572deb37
DV		 3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3071 * unconditionally resets the pll - we need that to have the right LVDS
3072 * enable sequence. */
b6b4e185 3073 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3074
303b81e0 3075 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3076 u32 sel;
4b645f14 3077
c98e9dcf 3078 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3079 switch (pipe) {
3080 default:
3081 case 0:
3082 temp |= TRANSA_DPLL_ENABLE;
3083 sel = TRANSA_DPLLB_SEL;
3084 break;
3085 case 1:
3086 temp |= TRANSB_DPLL_ENABLE;
3087 sel = TRANSB_DPLLB_SEL;
3088 break;
3089 case 2:
3090 temp |= TRANSC_DPLL_ENABLE;
3091 sel = TRANSC_DPLLB_SEL;
3092 break;
d64311ab 3093 }
ee7b9f93
JB		 3094 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3095 temp |= sel;
3096 else
3097 temp &= ~sel;
c98e9dcf 3098 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3099 }
5eddb70b 3100
d9b6cb56
JB		 3101 /* set transcoder timing, panel must allow it */
3102 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3103 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3104 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3105 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3106
5eddb70b
CW		 3107 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3108 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3109 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3110 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3111
303b81e0 3112 intel_fdi_normal_train(crtc);
5e84e1a4 3113
c98e9dcf
JB		 3114 /* For PCH DP, enable TRANS_DP_CTL */
3115 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3116 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3117 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3118 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3119 reg = TRANS_DP_CTL(pipe);
3120 temp = I915_READ(reg);
3121 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3122 TRANS_DP_SYNC_MASK |
3123 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3124 temp |= (TRANS_DP_OUTPUT_ENABLE |
3125 TRANS_DP_ENH_FRAMING);
9325c9f0 3126 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3127
3128 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3129 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3130 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3131 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3132
3133 switch (intel_trans_dp_port_sel(crtc)) {
3134 case PCH_DP_B:
5eddb70b 3135 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3136 break;
3137 case PCH_DP_C:
5eddb70b 3138 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3139 break;
3140 case PCH_DP_D:
5eddb70b 3141 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3142 break;
3143 default:
e95d41e1 3144 BUG();
32f9d658 3145 }
2c07245f 3146
5eddb70b 3147 I915_WRITE(reg, temp);
6be4a607 3148 }
b52eb4dc 3149
b8a4f404 3150 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3151}
3152
1507e5bd
PZ		 3153static void lpt_pch_enable(struct drm_crtc *crtc)
3154{
3155 struct drm_device *dev = crtc->dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3158 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3159
daed2dbb 3160 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3161
8c52b5e8 3162 lpt_program_iclkip(crtc);
1507e5bd 3163
0540e488 3164 /* Set transcoder timing. */
daed2dbb
PZ		 3165 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3166 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3167 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3168
daed2dbb
PZ		 3169 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3170 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3171 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3172 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3173
937bb610 3174 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3175}
3176
ee7b9f93
JB		 3177static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3178{
3179 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3180
3181 if (pll == NULL)
3182 return;
3183
3184 if (pll->refcount == 0) {
3185 WARN(1, "bad PCH PLL refcount\n");
3186 return;
3187 }
3188
3189 --pll->refcount;
3190 intel_crtc->pch_pll = NULL;
3191}
3192
3193static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3194{
3195 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3196 struct intel_pch_pll *pll;
3197 int i;
3198
3199 pll = intel_crtc->pch_pll;
3200 if (pll) {
3201 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3202 intel_crtc->base.base.id, pll->pll_reg);
3203 goto prepare;
3204 }
3205
98b6bd99
DV		 3206 if (HAS_PCH_IBX(dev_priv->dev)) {
3207 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3208 i = intel_crtc->pipe;
3209 pll = &dev_priv->pch_plls[i];
3210
3211 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3212 intel_crtc->base.base.id, pll->pll_reg);
3213
3214 goto found;
3215 }
3216
ee7b9f93
JB		 3217 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3218 pll = &dev_priv->pch_plls[i];
3219
3220 /* Only want to check enabled timings first */
3221 if (pll->refcount == 0)
3222 continue;
3223
3224 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3225 fp == I915_READ(pll->fp0_reg)) {
3226 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3227 intel_crtc->base.base.id,
3228 pll->pll_reg, pll->refcount, pll->active);
3229
3230 goto found;
3231 }
3232 }
3233
3234 /* Ok no matching timings, maybe there's a free one? */
3235 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3236 pll = &dev_priv->pch_plls[i];
3237 if (pll->refcount == 0) {
3238 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3239 intel_crtc->base.base.id, pll->pll_reg);
3240 goto found;
3241 }
3242 }
3243
3244 return NULL;
3245
3246found:
3247 intel_crtc->pch_pll = pll;
3248 pll->refcount++;
3249 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3250prepare: /* separate function? */
3251 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3252
e04c7350
CW		 3253 /* Wait for the clocks to stabilize before rewriting the regs */
3254 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3255 POSTING_READ(pll->pll_reg);
3256 udelay(150);
e04c7350
CW		 3257
3258 I915_WRITE(pll->fp0_reg, fp);
3259 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3260 pll->on = false;
3261 return pll;
3262}
3263
d4270e57
JB		 3264void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3265{
3266 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3267 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3268 u32 temp;
3269
3270 temp = I915_READ(dslreg);
3271 udelay(500);
3272 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3273 if (wait_for(I915_READ(dslreg) != temp, 5))
3274 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3275 }
3276}
3277
f67a559d
JB		 3278static void ironlake_crtc_enable(struct drm_crtc *crtc)
3279{
3280 struct drm_device *dev = crtc->dev;
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3283 struct intel_encoder *encoder;
f67a559d
JB		 3284 int pipe = intel_crtc->pipe;
3285 int plane = intel_crtc->plane;
3286 u32 temp;
3287 bool is_pch_port;
3288
08a48469
DV		 3289 WARN_ON(!crtc->enabled);
3290
f67a559d
JB		 3291 if (intel_crtc->active)
3292 return;
3293
3294 intel_crtc->active = true;
3295 intel_update_watermarks(dev);
3296
3297 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3298 temp = I915_READ(PCH_LVDS);
3299 if ((temp & LVDS_PORT_EN) == 0)
3300 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3301 }
3302
fc316cbe 3303 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3304
46b6f814 3305 if (is_pch_port) {
fff367c7
DV		 3306 /* Note: FDI PLL enabling _must_ be done before we enable the
3307 * cpu pipes, hence this is separate from all the other fdi/pch
3308 * enabling. */
88cefb6c 3309 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3310 } else {
3311 assert_fdi_tx_disabled(dev_priv, pipe);
3312 assert_fdi_rx_disabled(dev_priv, pipe);
3313 }
f67a559d 3314
bf49ec8c
DV		 3315 for_each_encoder_on_crtc(dev, crtc, encoder)
3316 if (encoder->pre_enable)
3317 encoder->pre_enable(encoder);
f67a559d
JB		 3318
3319 /* Enable panel fitting for LVDS */
3320 if (dev_priv->pch_pf_size &&
547dc041
JN		 3321 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3322 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3323 /* Force use of hard-coded filter coefficients
3324 * as some pre-programmed values are broken,
3325 * e.g. x201.
3326 */
13888d78
PZ		 3327 if (IS_IVYBRIDGE(dev))
3328 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3329 PF_PIPE_SEL_IVB(pipe));
3330 else
3331 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3332 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3333 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3334 }
3335
9c54c0dd
JB		 3336 /*
3337 * On ILK+ LUT must be loaded before the pipe is running but with
3338 * clocks enabled
3339 */
3340 intel_crtc_load_lut(crtc);
3341
f67a559d
JB		 3342 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3343 intel_enable_plane(dev_priv, plane, pipe);
3344
3345 if (is_pch_port)
3346 ironlake_pch_enable(crtc);
c98e9dcf 3347
d1ebd816 3348 mutex_lock(&dev->struct_mutex);
bed4a673 3349 intel_update_fbc(dev);
d1ebd816
BW		 3350 mutex_unlock(&dev->struct_mutex);
3351
6b383a7f 3352 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3353
fa5c73b1
DV		 3354 for_each_encoder_on_crtc(dev, crtc, encoder)
3355 encoder->enable(encoder);
61b77ddd
DV		 3356
3357 if (HAS_PCH_CPT(dev))
3358 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3359
3360 /*
3361 * There seems to be a race in PCH platform hw (at least on some
3362 * outputs) where an enabled pipe still completes any pageflip right
3363 * away (as if the pipe is off) instead of waiting for vblank. As soon
3364 * as the first vblank happend, everything works as expected. Hence just
3365 * wait for one vblank before returning to avoid strange things
3366 * happening.
3367 */
3368 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3369}
3370
4f771f10
PZ		 3371static void haswell_crtc_enable(struct drm_crtc *crtc)
3372{
3373 struct drm_device *dev = crtc->dev;
3374 struct drm_i915_private *dev_priv = dev->dev_private;
3375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3376 struct intel_encoder *encoder;
3377 int pipe = intel_crtc->pipe;
3378 int plane = intel_crtc->plane;
4f771f10
PZ		 3379 bool is_pch_port;
3380
3381 WARN_ON(!crtc->enabled);
3382
3383 if (intel_crtc->active)
3384 return;
3385
3386 intel_crtc->active = true;
3387 intel_update_watermarks(dev);
3388
fc316cbe 3389 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3390
83616634 3391 if (is_pch_port)
04945641 3392 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3393
3394 for_each_encoder_on_crtc(dev, crtc, encoder)
3395 if (encoder->pre_enable)
3396 encoder->pre_enable(encoder);
3397
1f544388 3398 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3399
1f544388 3400 /* Enable panel fitting for eDP */
547dc041
JN		 3401 if (dev_priv->pch_pf_size &&
3402 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3403 /* Force use of hard-coded filter coefficients
3404 * as some pre-programmed values are broken,
3405 * e.g. x201.
3406 */
54075a7d
PZ		 3407 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3408 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3409 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3410 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3411 }
3412
3413 /*
3414 * On ILK+ LUT must be loaded before the pipe is running but with
3415 * clocks enabled
3416 */
3417 intel_crtc_load_lut(crtc);
3418
1f544388
PZ		 3419 intel_ddi_set_pipe_settings(crtc);
3420 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3421
3422 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3423 intel_enable_plane(dev_priv, plane, pipe);
3424
3425 if (is_pch_port)
1507e5bd 3426 lpt_pch_enable(crtc);
4f771f10
PZ		 3427
3428 mutex_lock(&dev->struct_mutex);
3429 intel_update_fbc(dev);
3430 mutex_unlock(&dev->struct_mutex);
3431
3432 intel_crtc_update_cursor(crtc, true);
3433
3434 for_each_encoder_on_crtc(dev, crtc, encoder)
3435 encoder->enable(encoder);
3436
4f771f10
PZ		 3437 /*
3438 * There seems to be a race in PCH platform hw (at least on some
3439 * outputs) where an enabled pipe still completes any pageflip right
3440 * away (as if the pipe is off) instead of waiting for vblank. As soon
3441 * as the first vblank happend, everything works as expected. Hence just
3442 * wait for one vblank before returning to avoid strange things
3443 * happening.
3444 */
3445 intel_wait_for_vblank(dev, intel_crtc->pipe);
3446}
3447
6be4a607
JB		 3448static void ironlake_crtc_disable(struct drm_crtc *crtc)
3449{
3450 struct drm_device *dev = crtc->dev;
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3453 struct intel_encoder *encoder;
6be4a607
JB		 3454 int pipe = intel_crtc->pipe;
3455 int plane = intel_crtc->plane;
5eddb70b 3456 u32 reg, temp;
b52eb4dc 3457
ef9c3aee 3458
f7abfe8b
CW		 3459 if (!intel_crtc->active)
3460 return;
3461
ea9d758d
DV		 3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 encoder->disable(encoder);
3464
e6c3a2a6 3465 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3466 drm_vblank_off(dev, pipe);
6b383a7f 3467 intel_crtc_update_cursor(crtc, false);
5eddb70b 3468
b24e7179 3469 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3470
973d04f9
CW		 3471 if (dev_priv->cfb_plane == plane)
3472 intel_disable_fbc(dev);
2c07245f 3473
b24e7179 3474 intel_disable_pipe(dev_priv, pipe);
32f9d658 3475
6be4a607 3476 /* Disable PF */
9db4a9c7
JB		 3477 I915_WRITE(PF_CTL(pipe), 0);
3478 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3479
bf49ec8c
DV		 3480 for_each_encoder_on_crtc(dev, crtc, encoder)
3481 if (encoder->post_disable)
3482 encoder->post_disable(encoder);
2c07245f 3483
0fc932b8 3484 ironlake_fdi_disable(crtc);
249c0e64 3485
b8a4f404 3486 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3487
6be4a607
JB		 3488 if (HAS_PCH_CPT(dev)) {
3489 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3490 reg = TRANS_DP_CTL(pipe);
3491 temp = I915_READ(reg);
3492 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3493 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3494 I915_WRITE(reg, temp);
6be4a607
JB		 3495
3496 /* disable DPLL_SEL */
3497 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3498 switch (pipe) {
3499 case 0:
d64311ab 3500 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3501 break;
3502 case 1:
6be4a607 3503 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3504 break;
3505 case 2:
4b645f14 3506 /* C shares PLL A or B */
d64311ab 3507 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3508 break;
3509 default:
3510 BUG(); /* wtf */
3511 }
6be4a607 3512 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3513 }
e3421a18 3514
6be4a607 3515 /* disable PCH DPLL */
ee7b9f93 3516 intel_disable_pch_pll(intel_crtc);
8db9d77b 3517
88cefb6c 3518 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3519
f7abfe8b 3520 intel_crtc->active = false;
6b383a7f 3521 intel_update_watermarks(dev);
d1ebd816
BW		 3522
3523 mutex_lock(&dev->struct_mutex);
6b383a7f 3524 intel_update_fbc(dev);
d1ebd816 3525 mutex_unlock(&dev->struct_mutex);
6be4a607 3526}
1b3c7a47 3527
4f771f10 3528static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3529{
4f771f10
PZ		 3530 struct drm_device *dev = crtc->dev;
3531 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3533 struct intel_encoder *encoder;
3534 int pipe = intel_crtc->pipe;
3535 int plane = intel_crtc->plane;
ad80a810 3536 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3537 bool is_pch_port;
ee7b9f93 3538
4f771f10
PZ		 3539 if (!intel_crtc->active)
3540 return;
3541
83616634
PZ		 3542 is_pch_port = haswell_crtc_driving_pch(crtc);
3543
4f771f10
PZ		 3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 encoder->disable(encoder);
3546
3547 intel_crtc_wait_for_pending_flips(crtc);
3548 drm_vblank_off(dev, pipe);
3549 intel_crtc_update_cursor(crtc, false);
3550
3551 intel_disable_plane(dev_priv, plane, pipe);
3552
3553 if (dev_priv->cfb_plane == plane)
3554 intel_disable_fbc(dev);
3555
3556 intel_disable_pipe(dev_priv, pipe);
3557
ad80a810 3558 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3559
3560 /* Disable PF */
3561 I915_WRITE(PF_CTL(pipe), 0);
3562 I915_WRITE(PF_WIN_SZ(pipe), 0);
3563
1f544388 3564 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3565
3566 for_each_encoder_on_crtc(dev, crtc, encoder)
3567 if (encoder->post_disable)
3568 encoder->post_disable(encoder);
3569
83616634 3570 if (is_pch_port) {
ab4d966c 3571 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3572 intel_ddi_fdi_disable(crtc);
83616634 3573 }
4f771f10
PZ		 3574
3575 intel_crtc->active = false;
3576 intel_update_watermarks(dev);
3577
3578 mutex_lock(&dev->struct_mutex);
3579 intel_update_fbc(dev);
3580 mutex_unlock(&dev->struct_mutex);
3581}
3582
ee7b9f93
JB		 3583static void ironlake_crtc_off(struct drm_crtc *crtc)
3584{
3585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586 intel_put_pch_pll(intel_crtc);
3587}
3588
6441ab5f
PZ		 3589static void haswell_crtc_off(struct drm_crtc *crtc)
3590{
a5c961d1
PZ		 3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592
3593 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3594 * start using it. */
1a240d4d 3595 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3596
6441ab5f
PZ		 3597 intel_ddi_put_crtc_pll(crtc);
3598}
3599
02e792fb
DV		 3600static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3601{
02e792fb 3602 if (!enable && intel_crtc->overlay) {
23f09ce3 3603 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3604 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3605
23f09ce3 3606 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3607 dev_priv->mm.interruptible = false;
3608 (void) intel_overlay_switch_off(intel_crtc->overlay);
3609 dev_priv->mm.interruptible = true;
23f09ce3 3610 mutex_unlock(&dev->struct_mutex);
02e792fb 3611 }
02e792fb 3612
5dcdbcb0
CW		 3613 /* Let userspace switch the overlay on again. In most cases userspace
3614 * has to recompute where to put it anyway.
3615 */
02e792fb
DV		 3616}
3617
0b8765c6 3618static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3619{
3620 struct drm_device *dev = crtc->dev;
79e53945
JB		 3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3623 struct intel_encoder *encoder;
79e53945 3624 int pipe = intel_crtc->pipe;
80824003 3625 int plane = intel_crtc->plane;
79e53945 3626
08a48469
DV		 3627 WARN_ON(!crtc->enabled);
3628
f7abfe8b
CW		 3629 if (intel_crtc->active)
3630 return;
3631
3632 intel_crtc->active = true;
6b383a7f
CW		 3633 intel_update_watermarks(dev);
3634
63d7bbe9 3635 intel_enable_pll(dev_priv, pipe);
040484af 3636 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3637 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3638
0b8765c6 3639 intel_crtc_load_lut(crtc);
bed4a673 3640 intel_update_fbc(dev);
79e53945 3641
0b8765c6
JB		 3642 /* Give the overlay scaler a chance to enable if it's on this pipe */
3643 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3644 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3645
fa5c73b1
DV		 3646 for_each_encoder_on_crtc(dev, crtc, encoder)
3647 encoder->enable(encoder);
0b8765c6 3648}
79e53945 3649
0b8765c6
JB		 3650static void i9xx_crtc_disable(struct drm_crtc *crtc)
3651{
3652 struct drm_device *dev = crtc->dev;
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3655 struct intel_encoder *encoder;
0b8765c6
JB		 3656 int pipe = intel_crtc->pipe;
3657 int plane = intel_crtc->plane;
b690e96c 3658
ef9c3aee 3659
f7abfe8b
CW		 3660 if (!intel_crtc->active)
3661 return;
3662
ea9d758d
DV		 3663 for_each_encoder_on_crtc(dev, crtc, encoder)
3664 encoder->disable(encoder);
3665
0b8765c6 3666 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3667 intel_crtc_wait_for_pending_flips(crtc);
3668 drm_vblank_off(dev, pipe);
0b8765c6 3669 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3670 intel_crtc_update_cursor(crtc, false);
0b8765c6 3671
973d04f9
CW		 3672 if (dev_priv->cfb_plane == plane)
3673 intel_disable_fbc(dev);
79e53945 3674
b24e7179 3675 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3676 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3677 intel_disable_pll(dev_priv, pipe);
0b8765c6 3678
f7abfe8b 3679 intel_crtc->active = false;
6b383a7f
CW		 3680 intel_update_fbc(dev);
3681 intel_update_watermarks(dev);
0b8765c6
JB		 3682}
3683
ee7b9f93
JB		 3684static void i9xx_crtc_off(struct drm_crtc *crtc)
3685{
3686}
3687
976f8a20
DV		 3688static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3689 bool enabled)
2c07245f
ZW		 3690{
3691 struct drm_device *dev = crtc->dev;
3692 struct drm_i915_master_private *master_priv;
3693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3694 int pipe = intel_crtc->pipe;
79e53945
JB		 3695
3696 if (!dev->primary->master)
3697 return;
3698
3699 master_priv = dev->primary->master->driver_priv;
3700 if (!master_priv->sarea_priv)
3701 return;
3702
79e53945
JB		 3703 switch (pipe) {
3704 case 0:
3705 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3706 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3707 break;
3708 case 1:
3709 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3710 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3711 break;
3712 default:
9db4a9c7 3713 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3714 break;
3715 }
79e53945
JB		 3716}
3717
976f8a20
DV		 3718/**
3719 * Sets the power management mode of the pipe and plane.
3720 */
3721void intel_crtc_update_dpms(struct drm_crtc *crtc)
3722{
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct intel_encoder *intel_encoder;
3726 bool enable = false;
3727
3728 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3729 enable |= intel_encoder->connectors_active;
3730
3731 if (enable)
3732 dev_priv->display.crtc_enable(crtc);
3733 else
3734 dev_priv->display.crtc_disable(crtc);
3735
3736 intel_crtc_update_sarea(crtc, enable);
3737}
3738
3739static void intel_crtc_noop(struct drm_crtc *crtc)
3740{
3741}
3742
cdd59983
CW		 3743static void intel_crtc_disable(struct drm_crtc *crtc)
3744{
cdd59983 3745 struct drm_device *dev = crtc->dev;
976f8a20 3746 struct drm_connector *connector;
ee7b9f93 3747 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3748
976f8a20
DV		 3749 /* crtc should still be enabled when we disable it. */
3750 WARN_ON(!crtc->enabled);
3751
3752 dev_priv->display.crtc_disable(crtc);
3753 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3754 dev_priv->display.off(crtc);
3755
931872fc
CW		 3756 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3757 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3758
3759 if (crtc->fb) {
3760 mutex_lock(&dev->struct_mutex);
1690e1eb 3761 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3762 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3763 crtc->fb = NULL;
3764 }
3765
3766 /* Update computed state. */
3767 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3768 if (!connector->encoder || !connector->encoder->crtc)
3769 continue;
3770
3771 if (connector->encoder->crtc != crtc)
3772 continue;
3773
3774 connector->dpms = DRM_MODE_DPMS_OFF;
3775 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3776 }
3777}
3778
a261b246 3779void intel_modeset_disable(struct drm_device *dev)
79e53945 3780{
a261b246
DV		 3781 struct drm_crtc *crtc;
3782
3783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3784 if (crtc->enabled)
3785 intel_crtc_disable(crtc);
3786 }
79e53945
JB		 3787}
3788
1f703855 3789void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3790{
7e7d76c3
JB		 3791}
3792
ea5b213a 3793void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3794{
4ef69c7a 3795 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3796
ea5b213a
CW		 3797 drm_encoder_cleanup(encoder);
3798 kfree(intel_encoder);
7e7d76c3
JB		 3799}
3800
5ab432ef
DV		 3801/* Simple dpms helper for encodres with just one connector, no cloning and only
3802 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3803 * state of the entire output pipe. */
3804void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3805{
5ab432ef
DV		 3806 if (mode == DRM_MODE_DPMS_ON) {
3807 encoder->connectors_active = true;
3808
b2cabb0e 3809 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3810 } else {
3811 encoder->connectors_active = false;
3812
b2cabb0e 3813 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3814 }
79e53945
JB		 3815}
3816
0a91ca29
DV		 3817/* Cross check the actual hw state with our own modeset state tracking (and it's
3818 * internal consistency). */
b980514c 3819static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3820{
0a91ca29
DV		 3821 if (connector->get_hw_state(connector)) {
3822 struct intel_encoder *encoder = connector->encoder;
3823 struct drm_crtc *crtc;
3824 bool encoder_enabled;
3825 enum pipe pipe;
3826
3827 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3828 connector->base.base.id,
3829 drm_get_connector_name(&connector->base));
3830
3831 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3832 "wrong connector dpms state\n");
3833 WARN(connector->base.encoder != &encoder->base,
3834 "active connector not linked to encoder\n");
3835 WARN(!encoder->connectors_active,
3836 "encoder->connectors_active not set\n");
3837
3838 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3839 WARN(!encoder_enabled, "encoder not enabled\n");
3840 if (WARN_ON(!encoder->base.crtc))
3841 return;
3842
3843 crtc = encoder->base.crtc;
3844
3845 WARN(!crtc->enabled, "crtc not enabled\n");
3846 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3847 WARN(pipe != to_intel_crtc(crtc)->pipe,
3848 "encoder active on the wrong pipe\n");
3849 }
79e53945
JB		 3850}
3851
5ab432ef
DV		 3852/* Even simpler default implementation, if there's really no special case to
3853 * consider. */
3854void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3855{
5ab432ef 3856 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3857
5ab432ef
DV		 3858 /* All the simple cases only support two dpms states. */
3859 if (mode != DRM_MODE_DPMS_ON)
3860 mode = DRM_MODE_DPMS_OFF;
d4270e57 3861
5ab432ef
DV		 3862 if (mode == connector->dpms)
3863 return;
3864
3865 connector->dpms = mode;
3866
3867 /* Only need to change hw state when actually enabled */
3868 if (encoder->base.crtc)
3869 intel_encoder_dpms(encoder, mode);
3870 else
8af6cf88 3871 WARN_ON(encoder->connectors_active != false);
0a91ca29 3872
b980514c 3873 intel_modeset_check_state(connector->dev);
79e53945
JB		 3874}
3875
f0947c37
DV		 3876/* Simple connector->get_hw_state implementation for encoders that support only
3877 * one connector and no cloning and hence the encoder state determines the state
3878 * of the connector. */
3879bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3880{
24929352 3881 enum pipe pipe = 0;
f0947c37 3882 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3883
f0947c37 3884 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3885}
3886
79e53945 3887static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3888 const struct drm_display_mode *mode,
79e53945
JB		 3889 struct drm_display_mode *adjusted_mode)
3890{
2c07245f 3891 struct drm_device *dev = crtc->dev;
89749350 3892
bad720ff 3893 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3894 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3895 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3896 return false;
2c07245f 3897 }
89749350 3898
f9bef081
DV		 3899 /* All interlaced capable intel hw wants timings in frames. Note though
3900 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3901 * timings, so we need to be careful not to clobber these.*/
3902 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3903 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3904
44f46b42
CW		 3905 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3906 * with a hsync front porch of 0.
3907 */
3908 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3909 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3910 return false;
3911
79e53945
JB		 3912 return true;
3913}
3914
25eb05fc
JB		 3915static int valleyview_get_display_clock_speed(struct drm_device *dev)
3916{
3917 return 400000; /* FIXME */
3918}
3919
e70236a8
JB		 3920static int i945_get_display_clock_speed(struct drm_device *dev)
3921{
3922 return 400000;
3923}
79e53945 3924
e70236a8 3925static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3926{
e70236a8
JB		 3927 return 333000;
3928}
79e53945 3929
e70236a8
JB		 3930static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3931{
3932 return 200000;
3933}
79e53945 3934
e70236a8
JB		 3935static int i915gm_get_display_clock_speed(struct drm_device *dev)
3936{
3937 u16 gcfgc = 0;
79e53945 3938
e70236a8
JB		 3939 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3940
3941 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3942 return 133000;
3943 else {
3944 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3945 case GC_DISPLAY_CLOCK_333_MHZ:
3946 return 333000;
3947 default:
3948 case GC_DISPLAY_CLOCK_190_200_MHZ:
3949 return 190000;
79e53945 3950 }
e70236a8
JB		 3951 }
3952}
3953
3954static int i865_get_display_clock_speed(struct drm_device *dev)
3955{
3956 return 266000;
3957}
3958
3959static int i855_get_display_clock_speed(struct drm_device *dev)
3960{
3961 u16 hpllcc = 0;
3962 /* Assume that the hardware is in the high speed state. This
3963 * should be the default.
3964 */
3965 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3966 case GC_CLOCK_133_200:
3967 case GC_CLOCK_100_200:
3968 return 200000;
3969 case GC_CLOCK_166_250:
3970 return 250000;
3971 case GC_CLOCK_100_133:
79e53945 3972 return 133000;
e70236a8 3973 }
79e53945 3974
e70236a8
JB		 3975 /* Shouldn't happen */
3976 return 0;
3977}
79e53945 3978
e70236a8
JB		 3979static int i830_get_display_clock_speed(struct drm_device *dev)
3980{
3981 return 133000;
79e53945
JB		 3982}
3983
2c07245f 3984static void
e69d0bc1 3985intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3986{
3987 while (*num > 0xffffff || *den > 0xffffff) {
3988 *num >>= 1;
3989 *den >>= 1;
3990 }
3991}
3992
e69d0bc1
DV		 3993void
3994intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3995 int pixel_clock, int link_clock,
3996 struct intel_link_m_n *m_n)
2c07245f 3997{
e69d0bc1 3998 m_n->tu = 64;
22ed1113
CW		 3999 m_n->gmch_m = bits_per_pixel * pixel_clock;
4000 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4001 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4002 m_n->link_m = pixel_clock;
4003 m_n->link_n = link_clock;
e69d0bc1 4004 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4005}
4006
a7615030
CW		 4007static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4008{
72bbe58c
KP		 4009 if (i915_panel_use_ssc >= 0)
4010 return i915_panel_use_ssc != 0;
4011 return dev_priv->lvds_use_ssc
435793df 4012 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4013}
4014
5a354204
JB		 4015/**
4016 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4017 * @crtc: CRTC structure
3b5c78a3 4018 * @mode: requested mode
5a354204
JB		 4019 *
4020 * A pipe may be connected to one or more outputs. Based on the depth of the
4021 * attached framebuffer, choose a good color depth to use on the pipe.
4022 *
4023 * If possible, match the pipe depth to the fb depth. In some cases, this
4024 * isn't ideal, because the connected output supports a lesser or restricted
4025 * set of depths. Resolve that here:
4026 * LVDS typically supports only 6bpc, so clamp down in that case
4027 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4028 * Displays may support a restricted set as well, check EDID and clamp as
4029 * appropriate.
3b5c78a3 4030 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4031 *
4032 * RETURNS:
4033 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4034 * true if they don't match).
4035 */
4036static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4037 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4038 unsigned int *pipe_bpp,
4039 struct drm_display_mode *mode)
5a354204
JB		 4040{
4041 struct drm_device *dev = crtc->dev;
4042 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4043 struct drm_connector *connector;
6c2b7c12 4044 struct intel_encoder *intel_encoder;
5a354204
JB		 4045 unsigned int display_bpc = UINT_MAX, bpc;
4046
4047 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4048 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4049
4050 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4051 unsigned int lvds_bpc;
4052
4053 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4054 LVDS_A3_POWER_UP)
4055 lvds_bpc = 8;
4056 else
4057 lvds_bpc = 6;
4058
4059 if (lvds_bpc < display_bpc) {
82820490 4060 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4061 display_bpc = lvds_bpc;
4062 }
4063 continue;
4064 }
4065
5a354204
JB		 4066 /* Not one of the known troublemakers, check the EDID */
4067 list_for_each_entry(connector, &dev->mode_config.connector_list,
4068 head) {
6c2b7c12 4069 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4070 continue;
4071
62ac41a6
JB		 4072 /* Don't use an invalid EDID bpc value */
4073 if (connector->display_info.bpc &&
4074 connector->display_info.bpc < display_bpc) {
82820490 4075 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4076 display_bpc = connector->display_info.bpc;
4077 }
4078 }
4079
4080 /*
4081 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4082 * through, clamp it down. (Note: >12bpc will be caught below.)
4083 */
4084 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4085 if (display_bpc > 8 && display_bpc < 12) {
82820490 4086 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4087 display_bpc = 12;
4088 } else {
82820490 4089 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4090 display_bpc = 8;
4091 }
4092 }
4093 }
4094
3b5c78a3
AJ		 4095 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4096 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4097 display_bpc = 6;
4098 }
4099
5a354204
JB		 4100 /*
4101 * We could just drive the pipe at the highest bpc all the time and
4102 * enable dithering as needed, but that costs bandwidth. So choose
4103 * the minimum value that expresses the full color range of the fb but
4104 * also stays within the max display bpc discovered above.
4105 */
4106
94352cf9 4107 switch (fb->depth) {
5a354204
JB		 4108 case 8:
4109 bpc = 8; /* since we go through a colormap */
4110 break;
4111 case 15:
4112 case 16:
4113 bpc = 6; /* min is 18bpp */
4114 break;
4115 case 24:
578393cd 4116 bpc = 8;
5a354204
JB		 4117 break;
4118 case 30:
578393cd 4119 bpc = 10;
5a354204
JB		 4120 break;
4121 case 48:
578393cd 4122 bpc = 12;
5a354204
JB		 4123 break;
4124 default:
4125 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4126 bpc = min((unsigned int)8, display_bpc);
4127 break;
4128 }
4129
578393cd
KP		 4130 display_bpc = min(display_bpc, bpc);
4131
82820490
AJ		 4132 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4133 bpc, display_bpc);
5a354204 4134
578393cd 4135 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4136
4137 return display_bpc != bpc;
4138}
4139
a0c4da24
JB		 4140static int vlv_get_refclk(struct drm_crtc *crtc)
4141{
4142 struct drm_device *dev = crtc->dev;
4143 struct drm_i915_private *dev_priv = dev->dev_private;
4144 int refclk = 27000; /* for DP & HDMI */
4145
4146 return 100000; /* only one validated so far */
4147
4148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4149 refclk = 96000;
4150 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4151 if (intel_panel_use_ssc(dev_priv))
4152 refclk = 100000;
4153 else
4154 refclk = 96000;
4155 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4156 refclk = 100000;
4157 }
4158
4159 return refclk;
4160}
4161
c65d77d8
JB		 4162static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4163{
4164 struct drm_device *dev = crtc->dev;
4165 struct drm_i915_private *dev_priv = dev->dev_private;
4166 int refclk;
4167
a0c4da24
JB		 4168 if (IS_VALLEYVIEW(dev)) {
4169 refclk = vlv_get_refclk(crtc);
4170 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4171 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4172 refclk = dev_priv->lvds_ssc_freq * 1000;
4173 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4174 refclk / 1000);
4175 } else if (!IS_GEN2(dev)) {
4176 refclk = 96000;
4177 } else {
4178 refclk = 48000;
4179 }
4180
4181 return refclk;
4182}
4183
4184static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4185 intel_clock_t *clock)
4186{
4187 /* SDVO TV has fixed PLL values depend on its clock range,
4188 this mirrors vbios setting. */
4189 if (adjusted_mode->clock >= 100000
4190 && adjusted_mode->clock < 140500) {
4191 clock->p1 = 2;
4192 clock->p2 = 10;
4193 clock->n = 3;
4194 clock->m1 = 16;
4195 clock->m2 = 8;
4196 } else if (adjusted_mode->clock >= 140500
4197 && adjusted_mode->clock <= 200000) {
4198 clock->p1 = 1;
4199 clock->p2 = 10;
4200 clock->n = 6;
4201 clock->m1 = 12;
4202 clock->m2 = 8;
4203 }
4204}
4205
a7516a05
JB		 4206static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4207 intel_clock_t *clock,
4208 intel_clock_t *reduced_clock)
4209{
4210 struct drm_device *dev = crtc->dev;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4213 int pipe = intel_crtc->pipe;
4214 u32 fp, fp2 = 0;
4215
4216 if (IS_PINEVIEW(dev)) {
4217 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4218 if (reduced_clock)
4219 fp2 = (1 << reduced_clock->n) << 16 |
4220 reduced_clock->m1 << 8 | reduced_clock->m2;
4221 } else {
4222 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4223 if (reduced_clock)
4224 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4225 reduced_clock->m2;
4226 }
4227
4228 I915_WRITE(FP0(pipe), fp);
4229
4230 intel_crtc->lowfreq_avail = false;
4231 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4232 reduced_clock && i915_powersave) {
4233 I915_WRITE(FP1(pipe), fp2);
4234 intel_crtc->lowfreq_avail = true;
4235 } else {
4236 I915_WRITE(FP1(pipe), fp);
4237 }
4238}
4239
a0c4da24
JB		 4240static void vlv_update_pll(struct drm_crtc *crtc,
4241 struct drm_display_mode *mode,
4242 struct drm_display_mode *adjusted_mode,
4243 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4244 int num_connectors)
a0c4da24
JB		 4245{
4246 struct drm_device *dev = crtc->dev;
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249 int pipe = intel_crtc->pipe;
4250 u32 dpll, mdiv, pdiv;
4251 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4252 bool is_sdvo;
4253 u32 temp;
a0c4da24 4254
09153000
DV		 4255 mutex_lock(&dev_priv->dpio_lock);
4256
2a8f64ca
VP		 4257 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4258 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4259
2a8f64ca
VP		 4260 dpll = DPLL_VGA_MODE_DIS;
4261 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4262 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4263 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4264
4265 I915_WRITE(DPLL(pipe), dpll);
4266 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4267
4268 bestn = clock->n;
4269 bestm1 = clock->m1;
4270 bestm2 = clock->m2;
4271 bestp1 = clock->p1;
4272 bestp2 = clock->p2;
4273
2a8f64ca
VP		 4274 /*
4275 * In Valleyview PLL and program lane counter registers are exposed
4276 * through DPIO interface
4277 */
a0c4da24
JB		 4278 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4279 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4280 mdiv |= ((bestn << DPIO_N_SHIFT));
4281 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4282 mdiv |= (1 << DPIO_K_SHIFT);
4283 mdiv |= DPIO_ENABLE_CALIBRATION;
4284 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4285
4286 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4287
2a8f64ca 4288 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4289 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4290 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4291 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4292 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4293
2a8f64ca 4294 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4295
4296 dpll |= DPLL_VCO_ENABLE;
4297 I915_WRITE(DPLL(pipe), dpll);
4298 POSTING_READ(DPLL(pipe));
4299 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4300 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4301
2a8f64ca
VP		 4302 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4303
4304 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4305 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4306
4307 I915_WRITE(DPLL(pipe), dpll);
4308
4309 /* Wait for the clocks to stabilize. */
4310 POSTING_READ(DPLL(pipe));
4311 udelay(150);
a0c4da24 4312
2a8f64ca
VP		 4313 temp = 0;
4314 if (is_sdvo) {
4315 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4316 if (temp > 1)
4317 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4318 else
4319 temp = 0;
a0c4da24 4320 }
2a8f64ca
VP		 4321 I915_WRITE(DPLL_MD(pipe), temp);
4322 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4323
2a8f64ca
VP		 4324 /* Now program lane control registers */
4325 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4326 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4327 {
4328 temp = 0x1000C4;
4329 if(pipe == 1)
4330 temp |= (1 << 21);
4331 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4332 }
4333 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4334 {
4335 temp = 0x1000C4;
4336 if(pipe == 1)
4337 temp |= (1 << 21);
4338 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4339 }
09153000
DV		 4340
4341 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4342}
4343
eb1cbe48
DV		 4344static void i9xx_update_pll(struct drm_crtc *crtc,
4345 struct drm_display_mode *mode,
4346 struct drm_display_mode *adjusted_mode,
4347 intel_clock_t *clock, intel_clock_t *reduced_clock,
4348 int num_connectors)
4349{
4350 struct drm_device *dev = crtc->dev;
4351 struct drm_i915_private *dev_priv = dev->dev_private;
4352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4353 struct intel_encoder *encoder;
eb1cbe48
DV		 4354 int pipe = intel_crtc->pipe;
4355 u32 dpll;
4356 bool is_sdvo;
4357
2a8f64ca
VP		 4358 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4359
eb1cbe48
DV		 4360 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4361 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4362
4363 dpll = DPLL_VGA_MODE_DIS;
4364
4365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4366 dpll |= DPLLB_MODE_LVDS;
4367 else
4368 dpll |= DPLLB_MODE_DAC_SERIAL;
4369 if (is_sdvo) {
4370 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4371 if (pixel_multiplier > 1) {
4372 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4373 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4374 }
4375 dpll |= DPLL_DVO_HIGH_SPEED;
4376 }
4377 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4378 dpll |= DPLL_DVO_HIGH_SPEED;
4379
4380 /* compute bitmask from p1 value */
4381 if (IS_PINEVIEW(dev))
4382 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4383 else {
4384 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4385 if (IS_G4X(dev) && reduced_clock)
4386 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4387 }
4388 switch (clock->p2) {
4389 case 5:
4390 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4391 break;
4392 case 7:
4393 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4394 break;
4395 case 10:
4396 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4397 break;
4398 case 14:
4399 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4400 break;
4401 }
4402 if (INTEL_INFO(dev)->gen >= 4)
4403 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4404
4405 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4406 dpll |= PLL_REF_INPUT_TVCLKINBC;
4407 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4408 /* XXX: just matching BIOS for now */
4409 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4410 dpll |= 3;
4411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4412 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4413 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4414 else
4415 dpll |= PLL_REF_INPUT_DREFCLK;
4416
4417 dpll |= DPLL_VCO_ENABLE;
4418 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4419 POSTING_READ(DPLL(pipe));
4420 udelay(150);
4421
dafd226c
DV		 4422 for_each_encoder_on_crtc(dev, crtc, encoder)
4423 if (encoder->pre_pll_enable)
4424 encoder->pre_pll_enable(encoder);
4425
eb1cbe48
DV		 4426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4427 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4428
4429 I915_WRITE(DPLL(pipe), dpll);
4430
4431 /* Wait for the clocks to stabilize. */
4432 POSTING_READ(DPLL(pipe));
4433 udelay(150);
4434
4435 if (INTEL_INFO(dev)->gen >= 4) {
4436 u32 temp = 0;
4437 if (is_sdvo) {
4438 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4439 if (temp > 1)
4440 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4441 else
4442 temp = 0;
4443 }
4444 I915_WRITE(DPLL_MD(pipe), temp);
4445 } else {
4446 /* The pixel multiplier can only be updated once the
4447 * DPLL is enabled and the clocks are stable.
4448 *
4449 * So write it again.
4450 */
4451 I915_WRITE(DPLL(pipe), dpll);
4452 }
4453}
4454
4455static void i8xx_update_pll(struct drm_crtc *crtc,
4456 struct drm_display_mode *adjusted_mode,
2a8f64ca 4457 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4458 int num_connectors)
4459{
4460 struct drm_device *dev = crtc->dev;
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4463 struct intel_encoder *encoder;
eb1cbe48
DV		 4464 int pipe = intel_crtc->pipe;
4465 u32 dpll;
4466
2a8f64ca
VP		 4467 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4468
eb1cbe48
DV		 4469 dpll = DPLL_VGA_MODE_DIS;
4470
4471 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4472 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4473 } else {
4474 if (clock->p1 == 2)
4475 dpll |= PLL_P1_DIVIDE_BY_TWO;
4476 else
4477 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4478 if (clock->p2 == 4)
4479 dpll |= PLL_P2_DIVIDE_BY_4;
4480 }
4481
4482 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4483 /* XXX: just matching BIOS for now */
4484 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4485 dpll |= 3;
4486 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4487 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4488 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4489 else
4490 dpll |= PLL_REF_INPUT_DREFCLK;
4491
4492 dpll |= DPLL_VCO_ENABLE;
4493 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4494 POSTING_READ(DPLL(pipe));
4495 udelay(150);
4496
dafd226c
DV		 4497 for_each_encoder_on_crtc(dev, crtc, encoder)
4498 if (encoder->pre_pll_enable)
4499 encoder->pre_pll_enable(encoder);
4500
5b5896e4
DV		 4501 I915_WRITE(DPLL(pipe), dpll);
4502
4503 /* Wait for the clocks to stabilize. */
4504 POSTING_READ(DPLL(pipe));
4505 udelay(150);
4506
eb1cbe48
DV		 4507 /* The pixel multiplier can only be updated once the
4508 * DPLL is enabled and the clocks are stable.
4509 *
4510 * So write it again.
4511 */
4512 I915_WRITE(DPLL(pipe), dpll);
4513}
4514
b0e77b9c
PZ		 4515static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4516 struct drm_display_mode *mode,
4517 struct drm_display_mode *adjusted_mode)
4518{
4519 struct drm_device *dev = intel_crtc->base.dev;
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4522 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4523 uint32_t vsyncshift;
4524
4525 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4526 /* the chip adds 2 halflines automatically */
4527 adjusted_mode->crtc_vtotal -= 1;
4528 adjusted_mode->crtc_vblank_end -= 1;
4529 vsyncshift = adjusted_mode->crtc_hsync_start
4530 - adjusted_mode->crtc_htotal / 2;
4531 } else {
4532 vsyncshift = 0;
4533 }
4534
4535 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4536 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4537
fe2b8f9d 4538 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4539 (adjusted_mode->crtc_hdisplay - 1) |
4540 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4541 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4542 (adjusted_mode->crtc_hblank_start - 1) |
4543 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4544 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4545 (adjusted_mode->crtc_hsync_start - 1) |
4546 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4547
fe2b8f9d 4548 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4549 (adjusted_mode->crtc_vdisplay - 1) |
4550 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4551 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4552 (adjusted_mode->crtc_vblank_start - 1) |
4553 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4554 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4555 (adjusted_mode->crtc_vsync_start - 1) |
4556 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4557
b5e508d4
PZ		 4558 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4559 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4560 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4561 * bits. */
4562 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4563 (pipe == PIPE_B || pipe == PIPE_C))
4564 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4565
b0e77b9c
PZ		 4566 /* pipesrc controls the size that is scaled from, which should
4567 * always be the user's requested size.
4568 */
4569 I915_WRITE(PIPESRC(pipe),
4570 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4571}
4572
f564048e
EA		 4573static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4574 struct drm_display_mode *mode,
4575 struct drm_display_mode *adjusted_mode,
4576 int x, int y,
94352cf9 4577 struct drm_framebuffer *fb)
79e53945
JB		 4578{
4579 struct drm_device *dev = crtc->dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582 int pipe = intel_crtc->pipe;
80824003 4583 int plane = intel_crtc->plane;
c751ce4f 4584 int refclk, num_connectors = 0;
652c393a 4585 intel_clock_t clock, reduced_clock;
b0e77b9c 4586 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4587 bool ok, has_reduced_clock = false, is_sdvo = false;
4588 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4589 struct intel_encoder *encoder;
d4906093 4590 const intel_limit_t *limit;
5c3b82e2 4591 int ret;
79e53945 4592
6c2b7c12 4593 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4594 switch (encoder->type) {
79e53945
JB		 4595 case INTEL_OUTPUT_LVDS:
4596 is_lvds = true;
4597 break;
4598 case INTEL_OUTPUT_SDVO:
7d57382e 4599 case INTEL_OUTPUT_HDMI:
79e53945 4600 is_sdvo = true;
5eddb70b 4601 if (encoder->needs_tv_clock)
e2f0ba97 4602 is_tv = true;
79e53945 4603 break;
79e53945
JB		 4604 case INTEL_OUTPUT_TVOUT:
4605 is_tv = true;
4606 break;
a4fc5ed6
KP		 4607 case INTEL_OUTPUT_DISPLAYPORT:
4608 is_dp = true;
4609 break;
79e53945 4610 }
43565a06 4611
c751ce4f 4612 num_connectors++;
79e53945
JB		 4613 }
4614
c65d77d8 4615 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4616
d4906093
ML		 4617 /*
4618 * Returns a set of divisors for the desired target clock with the given
4619 * refclk, or FALSE. The returned values represent the clock equation:
4620 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4621 */
1b894b59 4622 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4623 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4624 &clock);
79e53945
JB		 4625 if (!ok) {
4626 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4627 return -EINVAL;
79e53945
JB		 4628 }
4629
cda4b7d3 4630 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4631 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4632
ddc9003c 4633 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4634 /*
4635 * Ensure we match the reduced clock's P to the target clock.
4636 * If the clocks don't match, we can't switch the display clock
4637 * by using the FP0/FP1. In such case we will disable the LVDS
4638 * downclock feature.
4639 */
ddc9003c 4640 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4641 dev_priv->lvds_downclock,
4642 refclk,
cec2f356 4643 &clock,
5eddb70b 4644 &reduced_clock);
7026d4ac
ZW		 4645 }
4646
c65d77d8
JB		 4647 if (is_sdvo && is_tv)
4648 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4649
eb1cbe48 4650 if (IS_GEN2(dev))
2a8f64ca
VP		 4651 i8xx_update_pll(crtc, adjusted_mode, &clock,
4652 has_reduced_clock ? &reduced_clock : NULL,
4653 num_connectors);
a0c4da24 4654 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4655 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4656 has_reduced_clock ? &reduced_clock : NULL,
4657 num_connectors);
79e53945 4658 else
eb1cbe48
DV		 4659 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4660 has_reduced_clock ? &reduced_clock : NULL,
4661 num_connectors);
79e53945
JB		 4662
4663 /* setup pipeconf */
5eddb70b 4664 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4665
4666 /* Set up the display plane register */
4667 dspcntr = DISPPLANE_GAMMA_ENABLE;
4668
929c77fb
EA		 4669 if (pipe == 0)
4670 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4671 else
4672 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4673
a6c45cf0 4674 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4675 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4676 * core speed.
4677 *
4678 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4679 * pipe == 0 check?
4680 */
e70236a8
JB		 4681 if (mode->clock >
4682 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4683 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4684 else
5eddb70b 4685 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4686 }
4687
3b5c78a3
AJ		 4688 /* default to 8bpc */
4689 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4690 if (is_dp) {
0c96c65b 4691 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4692 pipeconf |= PIPECONF_BPP_6 |
4693 PIPECONF_DITHER_EN |
4694 PIPECONF_DITHER_TYPE_SP;
4695 }
4696 }
4697
19c03924
GB		 4698 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4699 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4700 pipeconf |= PIPECONF_BPP_6 |
4701 PIPECONF_ENABLE |
4702 I965_PIPECONF_ACTIVE;
4703 }
4704 }
4705
28c97730 4706 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4707 drm_mode_debug_printmodeline(mode);
4708
a7516a05
JB		 4709 if (HAS_PIPE_CXSR(dev)) {
4710 if (intel_crtc->lowfreq_avail) {
28c97730 4711 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4712 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4713 } else {
28c97730 4714 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4715 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4716 }
4717 }
4718
617cf884 4719 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4720 if (!IS_GEN2(dev) &&
b0e77b9c 4721 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4722 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4723 else
617cf884 4724 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4725
b0e77b9c 4726 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4727
4728 /* pipesrc and dspsize control the size that is scaled from,
4729 * which should always be the user's requested size.
79e53945 4730 */
929c77fb
EA		 4731 I915_WRITE(DSPSIZE(plane),
4732 ((mode->vdisplay - 1) << 16) |
4733 (mode->hdisplay - 1));
4734 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4735
f564048e
EA		 4736 I915_WRITE(PIPECONF(pipe), pipeconf);
4737 POSTING_READ(PIPECONF(pipe));
929c77fb 4738 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4739
4740 intel_wait_for_vblank(dev, pipe);
4741
f564048e
EA		 4742 I915_WRITE(DSPCNTR(plane), dspcntr);
4743 POSTING_READ(DSPCNTR(plane));
4744
94352cf9 4745 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4746
4747 intel_update_watermarks(dev);
4748
f564048e
EA		 4749 return ret;
4750}
4751
9fb526db
KP		 4752/*
4753 * Initialize reference clocks when the driver loads
4754 */
4755void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4756{
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4759 struct intel_encoder *encoder;
13d83a67
JB		 4760 u32 temp;
4761 bool has_lvds = false;
199e5d79
KP		 4762 bool has_cpu_edp = false;
4763 bool has_pch_edp = false;
4764 bool has_panel = false;
99eb6a01
KP		 4765 bool has_ck505 = false;
4766 bool can_ssc = false;
13d83a67
JB		 4767
4768 /* We need to take the global config into account */
199e5d79
KP		 4769 list_for_each_entry(encoder, &mode_config->encoder_list,
4770 base.head) {
4771 switch (encoder->type) {
4772 case INTEL_OUTPUT_LVDS:
4773 has_panel = true;
4774 has_lvds = true;
4775 break;
4776 case INTEL_OUTPUT_EDP:
4777 has_panel = true;
4778 if (intel_encoder_is_pch_edp(&encoder->base))
4779 has_pch_edp = true;
4780 else
4781 has_cpu_edp = true;
4782 break;
13d83a67
JB		 4783 }
4784 }
4785
99eb6a01
KP		 4786 if (HAS_PCH_IBX(dev)) {
4787 has_ck505 = dev_priv->display_clock_mode;
4788 can_ssc = has_ck505;
4789 } else {
4790 has_ck505 = false;
4791 can_ssc = true;
4792 }
4793
4794 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4795 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4796 has_ck505);
13d83a67
JB		 4797
4798 /* Ironlake: try to setup display ref clock before DPLL
4799 * enabling. This is only under driver's control after
4800 * PCH B stepping, previous chipset stepping should be
4801 * ignoring this setting.
4802 */
4803 temp = I915_READ(PCH_DREF_CONTROL);
4804 /* Always enable nonspread source */
4805 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4806
99eb6a01
KP		 4807 if (has_ck505)
4808 temp |= DREF_NONSPREAD_CK505_ENABLE;
4809 else
4810 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4811
199e5d79
KP		 4812 if (has_panel) {
4813 temp &= ~DREF_SSC_SOURCE_MASK;
4814 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4815
199e5d79 4816 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4817 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4818 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4819 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4820 } else
4821 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4822
4823 /* Get SSC going before enabling the outputs */
4824 I915_WRITE(PCH_DREF_CONTROL, temp);
4825 POSTING_READ(PCH_DREF_CONTROL);
4826 udelay(200);
4827
13d83a67
JB		 4828 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4829
4830 /* Enable CPU source on CPU attached eDP */
199e5d79 4831 if (has_cpu_edp) {
99eb6a01 4832 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4833 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4834 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4835 }
13d83a67
JB		 4836 else
4837 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4838 } else
4839 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4840
4841 I915_WRITE(PCH_DREF_CONTROL, temp);
4842 POSTING_READ(PCH_DREF_CONTROL);
4843 udelay(200);
4844 } else {
4845 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4846
4847 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4848
4849 /* Turn off CPU output */
4850 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4851
4852 I915_WRITE(PCH_DREF_CONTROL, temp);
4853 POSTING_READ(PCH_DREF_CONTROL);
4854 udelay(200);
4855
4856 /* Turn off the SSC source */
4857 temp &= ~DREF_SSC_SOURCE_MASK;
4858 temp |= DREF_SSC_SOURCE_DISABLE;
4859
4860 /* Turn off SSC1 */
4861 temp &= ~ DREF_SSC1_ENABLE;
4862
13d83a67
JB		 4863 I915_WRITE(PCH_DREF_CONTROL, temp);
4864 POSTING_READ(PCH_DREF_CONTROL);
4865 udelay(200);
4866 }
4867}
4868
d9d444cb
JB		 4869static int ironlake_get_refclk(struct drm_crtc *crtc)
4870{
4871 struct drm_device *dev = crtc->dev;
4872 struct drm_i915_private *dev_priv = dev->dev_private;
4873 struct intel_encoder *encoder;
d9d444cb
JB		 4874 struct intel_encoder *edp_encoder = NULL;
4875 int num_connectors = 0;
4876 bool is_lvds = false;
4877
6c2b7c12 4878 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4879 switch (encoder->type) {
4880 case INTEL_OUTPUT_LVDS:
4881 is_lvds = true;
4882 break;
4883 case INTEL_OUTPUT_EDP:
4884 edp_encoder = encoder;
4885 break;
4886 }
4887 num_connectors++;
4888 }
4889
4890 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4891 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4892 dev_priv->lvds_ssc_freq);
4893 return dev_priv->lvds_ssc_freq * 1000;
4894 }
4895
4896 return 120000;
4897}
4898
c8203565 4899static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 4900 struct drm_display_mode *adjusted_mode,
c8203565 4901 bool dither)
79e53945 4902{
c8203565 4903 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 4904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905 int pipe = intel_crtc->pipe;
c8203565
PZ		 4906 uint32_t val;
4907
4908 val = I915_READ(PIPECONF(pipe));
4909
4910 val &= ~PIPE_BPC_MASK;
4911 switch (intel_crtc->bpp) {
4912 case 18:
4913 val |= PIPE_6BPC;
4914 break;
4915 case 24:
4916 val |= PIPE_8BPC;
4917 break;
4918 case 30:
4919 val |= PIPE_10BPC;
4920 break;
4921 case 36:
4922 val |= PIPE_12BPC;
4923 break;
4924 default:
cc769b62
PZ		 4925 /* Case prevented by intel_choose_pipe_bpp_dither. */
4926 BUG();
c8203565
PZ		 4927 }
4928
4929 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4930 if (dither)
4931 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4932
4933 val &= ~PIPECONF_INTERLACE_MASK;
4934 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4935 val |= PIPECONF_INTERLACED_ILK;
4936 else
4937 val |= PIPECONF_PROGRESSIVE;
4938
4939 I915_WRITE(PIPECONF(pipe), val);
4940 POSTING_READ(PIPECONF(pipe));
4941}
4942
ee2b0b38
PZ		 4943static void haswell_set_pipeconf(struct drm_crtc *crtc,
4944 struct drm_display_mode *adjusted_mode,
4945 bool dither)
4946{
4947 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4949 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4950 uint32_t val;
4951
702e7a56 4952 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4953
4954 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4955 if (dither)
4956 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4957
4958 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4959 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4960 val |= PIPECONF_INTERLACED_ILK;
4961 else
4962 val |= PIPECONF_PROGRESSIVE;
4963
702e7a56
PZ		 4964 I915_WRITE(PIPECONF(cpu_transcoder), val);
4965 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4966}
4967
6591c6e4
PZ		 4968static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4969 struct drm_display_mode *adjusted_mode,
4970 intel_clock_t *clock,
4971 bool *has_reduced_clock,
4972 intel_clock_t *reduced_clock)
4973{
4974 struct drm_device *dev = crtc->dev;
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976 struct intel_encoder *intel_encoder;
4977 int refclk;
d4906093 4978 const intel_limit_t *limit;
6591c6e4 4979 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 4980
6591c6e4
PZ		 4981 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4982 switch (intel_encoder->type) {
79e53945
JB		 4983 case INTEL_OUTPUT_LVDS:
4984 is_lvds = true;
4985 break;
4986 case INTEL_OUTPUT_SDVO:
7d57382e 4987 case INTEL_OUTPUT_HDMI:
79e53945 4988 is_sdvo = true;
6591c6e4 4989 if (intel_encoder->needs_tv_clock)
e2f0ba97 4990 is_tv = true;
79e53945 4991 break;
79e53945
JB		 4992 case INTEL_OUTPUT_TVOUT:
4993 is_tv = true;
4994 break;
79e53945
JB		 4995 }
4996 }
4997
d9d444cb 4998 refclk = ironlake_get_refclk(crtc);
79e53945 4999
d4906093
ML		 5000 /*
5001 * Returns a set of divisors for the desired target clock with the given
5002 * refclk, or FALSE. The returned values represent the clock equation:
5003 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5004 */
1b894b59 5005 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5006 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5007 clock);
5008 if (!ret)
5009 return false;
cda4b7d3 5010
ddc9003c 5011 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5012 /*
5013 * Ensure we match the reduced clock's P to the target clock.
5014 * If the clocks don't match, we can't switch the display clock
5015 * by using the FP0/FP1. In such case we will disable the LVDS
5016 * downclock feature.
5017 */
6591c6e4
PZ		 5018 *has_reduced_clock = limit->find_pll(limit, crtc,
5019 dev_priv->lvds_downclock,
5020 refclk,
5021 clock,
5022 reduced_clock);
652c393a 5023 }
61e9653f
DV		 5024
5025 if (is_sdvo && is_tv)
6591c6e4
PZ		 5026 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5027
5028 return true;
5029}
5030
01a415fd
DV		 5031static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5032{
5033 struct drm_i915_private *dev_priv = dev->dev_private;
5034 uint32_t temp;
5035
5036 temp = I915_READ(SOUTH_CHICKEN1);
5037 if (temp & FDI_BC_BIFURCATION_SELECT)
5038 return;
5039
5040 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5041 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5042
5043 temp |= FDI_BC_BIFURCATION_SELECT;
5044 DRM_DEBUG_KMS("enabling fdi C rx\n");
5045 I915_WRITE(SOUTH_CHICKEN1, temp);
5046 POSTING_READ(SOUTH_CHICKEN1);
5047}
5048
5049static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5050{
5051 struct drm_device *dev = intel_crtc->base.dev;
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 struct intel_crtc *pipe_B_crtc =
5054 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5055
5056 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5057 intel_crtc->pipe, intel_crtc->fdi_lanes);
5058 if (intel_crtc->fdi_lanes > 4) {
5059 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5060 intel_crtc->pipe, intel_crtc->fdi_lanes);
5061 /* Clamp lanes to avoid programming the hw with bogus values. */
5062 intel_crtc->fdi_lanes = 4;
5063
5064 return false;
5065 }
5066
5067 if (dev_priv->num_pipe == 2)
5068 return true;
5069
5070 switch (intel_crtc->pipe) {
5071 case PIPE_A:
5072 return true;
5073 case PIPE_B:
5074 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5075 intel_crtc->fdi_lanes > 2) {
5076 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5077 intel_crtc->pipe, intel_crtc->fdi_lanes);
5078 /* Clamp lanes to avoid programming the hw with bogus values. */
5079 intel_crtc->fdi_lanes = 2;
5080
5081 return false;
5082 }
5083
5084 if (intel_crtc->fdi_lanes > 2)
5085 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5086 else
5087 cpt_enable_fdi_bc_bifurcation(dev);
5088
5089 return true;
5090 case PIPE_C:
5091 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5092 if (intel_crtc->fdi_lanes > 2) {
5093 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5094 intel_crtc->pipe, intel_crtc->fdi_lanes);
5095 /* Clamp lanes to avoid programming the hw with bogus values. */
5096 intel_crtc->fdi_lanes = 2;
5097
5098 return false;
5099 }
5100 } else {
5101 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5102 return false;
5103 }
5104
5105 cpt_enable_fdi_bc_bifurcation(dev);
5106
5107 return true;
5108 default:
5109 BUG();
5110 }
5111}
5112
f48d8f23
PZ		 5113static void ironlake_set_m_n(struct drm_crtc *crtc,
5114 struct drm_display_mode *mode,
5115 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5116{
5117 struct drm_device *dev = crtc->dev;
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5120 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5121 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5122 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5123 int target_clock, pixel_multiplier, lane, link_bw;
5124 bool is_dp = false, is_cpu_edp = false;
79e53945 5125
f48d8f23
PZ		 5126 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5127 switch (intel_encoder->type) {
a4fc5ed6
KP		 5128 case INTEL_OUTPUT_DISPLAYPORT:
5129 is_dp = true;
5130 break;
32f9d658 5131 case INTEL_OUTPUT_EDP:
e3aef172 5132 is_dp = true;
f48d8f23 5133 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5134 is_cpu_edp = true;
f48d8f23 5135 edp_encoder = intel_encoder;
32f9d658 5136 break;
79e53945 5137 }
79e53945 5138 }
61e9653f 5139
2c07245f 5140 /* FDI link */
8febb297
EA		 5141 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5142 lane = 0;
5143 /* CPU eDP doesn't require FDI link, so just set DP M/N
5144 according to current link config */
e3aef172 5145 if (is_cpu_edp) {
e3aef172 5146 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5147 } else {
8febb297
EA		 5148 /* FDI is a binary signal running at ~2.7GHz, encoding
5149 * each output octet as 10 bits. The actual frequency
5150 * is stored as a divider into a 100MHz clock, and the
5151 * mode pixel clock is stored in units of 1KHz.
5152 * Hence the bw of each lane in terms of the mode signal
5153 * is:
5154 */
5155 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5156 }
58a27471 5157
94bf2ced
DV		 5158 /* [e]DP over FDI requires target mode clock instead of link clock. */
5159 if (edp_encoder)
5160 target_clock = intel_edp_target_clock(edp_encoder, mode);
5161 else if (is_dp)
5162 target_clock = mode->clock;
5163 else
5164 target_clock = adjusted_mode->clock;
5165
8febb297
EA		 5166 if (!lane) {
5167 /*
5168 * Account for spread spectrum to avoid
5169 * oversubscribing the link. Max center spread
5170 * is 2.5%; use 5% for safety's sake.
5171 */
5a354204 5172 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5173 lane = bps / (link_bw * 8) + 1;
5eb08b69 5174 }
2c07245f 5175
8febb297
EA		 5176 intel_crtc->fdi_lanes = lane;
5177
5178 if (pixel_multiplier > 1)
5179 link_bw *= pixel_multiplier;
e69d0bc1 5180 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5181
afe2fcf5
PZ		 5182 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5183 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5184 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5185 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5186}
5187
de13a2e3
PZ		 5188static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5189 struct drm_display_mode *adjusted_mode,
5190 intel_clock_t *clock, u32 fp)
79e53945 5191{
de13a2e3 5192 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5193 struct drm_device *dev = crtc->dev;
5194 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5195 struct intel_encoder *intel_encoder;
5196 uint32_t dpll;
5197 int factor, pixel_multiplier, num_connectors = 0;
5198 bool is_lvds = false, is_sdvo = false, is_tv = false;
5199 bool is_dp = false, is_cpu_edp = false;
79e53945 5200
de13a2e3
PZ		 5201 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5202 switch (intel_encoder->type) {
79e53945
JB		 5203 case INTEL_OUTPUT_LVDS:
5204 is_lvds = true;
5205 break;
5206 case INTEL_OUTPUT_SDVO:
7d57382e 5207 case INTEL_OUTPUT_HDMI:
79e53945 5208 is_sdvo = true;
de13a2e3 5209 if (intel_encoder->needs_tv_clock)
e2f0ba97 5210 is_tv = true;
79e53945 5211 break;
79e53945
JB		 5212 case INTEL_OUTPUT_TVOUT:
5213 is_tv = true;
5214 break;
a4fc5ed6
KP		 5215 case INTEL_OUTPUT_DISPLAYPORT:
5216 is_dp = true;
5217 break;
32f9d658 5218 case INTEL_OUTPUT_EDP:
e3aef172 5219 is_dp = true;
de13a2e3 5220 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5221 is_cpu_edp = true;
32f9d658 5222 break;
79e53945 5223 }
43565a06 5224
c751ce4f 5225 num_connectors++;
79e53945 5226 }
79e53945 5227
c1858123 5228 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5229 factor = 21;
5230 if (is_lvds) {
5231 if ((intel_panel_use_ssc(dev_priv) &&
5232 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5233 intel_is_dual_link_lvds(dev))
8febb297
EA		 5234 factor = 25;
5235 } else if (is_sdvo && is_tv)
5236 factor = 20;
c1858123 5237
de13a2e3 5238 if (clock->m < factor * clock->n)
8febb297 5239 fp |= FP_CB_TUNE;
2c07245f 5240
5eddb70b 5241 dpll = 0;
2c07245f 5242
a07d6787
EA		 5243 if (is_lvds)
5244 dpll |= DPLLB_MODE_LVDS;
5245 else
5246 dpll |= DPLLB_MODE_DAC_SERIAL;
5247 if (is_sdvo) {
de13a2e3 5248 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5249 if (pixel_multiplier > 1) {
5250 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5251 }
a07d6787
EA		 5252 dpll |= DPLL_DVO_HIGH_SPEED;
5253 }
e3aef172 5254 if (is_dp && !is_cpu_edp)
a07d6787 5255 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5256
a07d6787 5257 /* compute bitmask from p1 value */
de13a2e3 5258 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5259 /* also FPA1 */
de13a2e3 5260 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5261
de13a2e3 5262 switch (clock->p2) {
a07d6787
EA		 5263 case 5:
5264 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5265 break;
5266 case 7:
5267 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5268 break;
5269 case 10:
5270 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5271 break;
5272 case 14:
5273 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5274 break;
79e53945
JB		 5275 }
5276
43565a06
KH		 5277 if (is_sdvo && is_tv)
5278 dpll |= PLL_REF_INPUT_TVCLKINBC;
5279 else if (is_tv)
79e53945 5280 /* XXX: just matching BIOS for now */
43565a06 5281 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5282 dpll |= 3;
a7615030 5283 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5284 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5285 else
5286 dpll |= PLL_REF_INPUT_DREFCLK;
5287
de13a2e3
PZ		 5288 return dpll;
5289}
5290
5291static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5292 struct drm_display_mode *mode,
5293 struct drm_display_mode *adjusted_mode,
5294 int x, int y,
5295 struct drm_framebuffer *fb)
5296{
5297 struct drm_device *dev = crtc->dev;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5300 int pipe = intel_crtc->pipe;
5301 int plane = intel_crtc->plane;
5302 int num_connectors = 0;
5303 intel_clock_t clock, reduced_clock;
5304 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5305 bool ok, has_reduced_clock = false;
5306 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5307 struct intel_encoder *encoder;
de13a2e3 5308 int ret;
01a415fd 5309 bool dither, fdi_config_ok;
de13a2e3
PZ		 5310
5311 for_each_encoder_on_crtc(dev, crtc, encoder) {
5312 switch (encoder->type) {
5313 case INTEL_OUTPUT_LVDS:
5314 is_lvds = true;
5315 break;
de13a2e3
PZ		 5316 case INTEL_OUTPUT_DISPLAYPORT:
5317 is_dp = true;
5318 break;
5319 case INTEL_OUTPUT_EDP:
5320 is_dp = true;
e2f12b07 5321 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5322 is_cpu_edp = true;
5323 break;
5324 }
5325
5326 num_connectors++;
a07d6787 5327 }
79e53945 5328
5dc5298b
PZ		 5329 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5330 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5331
de13a2e3
PZ		 5332 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5333 &has_reduced_clock, &reduced_clock);
5334 if (!ok) {
5335 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5336 return -EINVAL;
79e53945
JB		 5337 }
5338
de13a2e3
PZ		 5339 /* Ensure that the cursor is valid for the new mode before changing... */
5340 intel_crtc_update_cursor(crtc, true);
5341
5342 /* determine panel color depth */
c8241969
JN		 5343 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5344 adjusted_mode);
de13a2e3
PZ		 5345 if (is_lvds && dev_priv->lvds_dither)
5346 dither = true;
5347
5348 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5349 if (has_reduced_clock)
5350 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5351 reduced_clock.m2;
5352
5353 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5354
f7cb34d4 5355 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5356 drm_mode_debug_printmodeline(mode);
5357
5dc5298b
PZ		 5358 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5359 if (!is_cpu_edp) {
ee7b9f93 5360 struct intel_pch_pll *pll;
4b645f14 5361
ee7b9f93
JB		 5362 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5363 if (pll == NULL) {
5364 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5365 pipe);
4b645f14
JB		 5366 return -EINVAL;
5367 }
ee7b9f93
JB		 5368 } else
5369 intel_put_pch_pll(intel_crtc);
79e53945 5370
2f0c2ad1 5371 if (is_dp && !is_cpu_edp)
a4fc5ed6 5372 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5373
dafd226c
DV		 5374 for_each_encoder_on_crtc(dev, crtc, encoder)
5375 if (encoder->pre_pll_enable)
5376 encoder->pre_pll_enable(encoder);
5377
ee7b9f93
JB		 5378 if (intel_crtc->pch_pll) {
5379 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5380
32f9d658 5381 /* Wait for the clocks to stabilize. */
ee7b9f93 5382 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5383 udelay(150);
5384
8febb297
EA		 5385 /* The pixel multiplier can only be updated once the
5386 * DPLL is enabled and the clocks are stable.
5387 *
5388 * So write it again.
5389 */
ee7b9f93 5390 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5391 }
79e53945 5392
5eddb70b 5393 intel_crtc->lowfreq_avail = false;
ee7b9f93 5394 if (intel_crtc->pch_pll) {
4b645f14 5395 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5396 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5397 intel_crtc->lowfreq_avail = true;
4b645f14 5398 } else {
ee7b9f93 5399 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5400 }
5401 }
5402
b0e77b9c 5403 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5404
01a415fd
DV		 5405 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5406 * ironlake_check_fdi_lanes. */
f48d8f23 5407 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5408
01a415fd 5409 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5410
c8203565 5411 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5412
9d0498a2 5413 intel_wait_for_vblank(dev, pipe);
79e53945 5414
a1f9e77e
PZ		 5415 /* Set up the display plane register */
5416 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5417 POSTING_READ(DSPCNTR(plane));
79e53945 5418
94352cf9 5419 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5420
5421 intel_update_watermarks(dev);
5422
1f8eeabf
ED		 5423 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5424
01a415fd 5425 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5426}
5427
09b4ddf9
PZ		 5428static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5429 struct drm_display_mode *mode,
5430 struct drm_display_mode *adjusted_mode,
5431 int x, int y,
5432 struct drm_framebuffer *fb)
5433{
5434 struct drm_device *dev = crtc->dev;
5435 struct drm_i915_private *dev_priv = dev->dev_private;
5436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5437 int pipe = intel_crtc->pipe;
5438 int plane = intel_crtc->plane;
5439 int num_connectors = 0;
ed7ef439 5440 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5441 struct intel_encoder *encoder;
09b4ddf9
PZ		 5442 int ret;
5443 bool dither;
5444
5445 for_each_encoder_on_crtc(dev, crtc, encoder) {
5446 switch (encoder->type) {
09b4ddf9
PZ		 5447 case INTEL_OUTPUT_DISPLAYPORT:
5448 is_dp = true;
5449 break;
5450 case INTEL_OUTPUT_EDP:
5451 is_dp = true;
5452 if (!intel_encoder_is_pch_edp(&encoder->base))
5453 is_cpu_edp = true;
5454 break;
5455 }
5456
5457 num_connectors++;
5458 }
5459
a5c961d1
PZ		 5460 if (is_cpu_edp)
5461 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5462 else
5463 intel_crtc->cpu_transcoder = pipe;
5464
5dc5298b
PZ		 5465 /* We are not sure yet this won't happen. */
5466 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5467 INTEL_PCH_TYPE(dev));
5468
5469 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5470 num_connectors, pipe_name(pipe));
5471
702e7a56 5472 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5473 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5474
5475 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5476
6441ab5f
PZ		 5477 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5478 return -EINVAL;
5479
09b4ddf9
PZ		 5480 /* Ensure that the cursor is valid for the new mode before changing... */
5481 intel_crtc_update_cursor(crtc, true);
5482
5483 /* determine panel color depth */
c8241969
JN		 5484 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5485 adjusted_mode);
09b4ddf9 5486
09b4ddf9
PZ		 5487 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5488 drm_mode_debug_printmodeline(mode);
5489
ed7ef439 5490 if (is_dp && !is_cpu_edp)
09b4ddf9 5491 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5492
5493 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5494
5495 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5496
1eb8dfec
PZ		 5497 if (!is_dp || is_cpu_edp)
5498 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5499
ee2b0b38 5500 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5501
09b4ddf9
PZ		 5502 /* Set up the display plane register */
5503 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5504 POSTING_READ(DSPCNTR(plane));
5505
5506 ret = intel_pipe_set_base(crtc, x, y, fb);
5507
5508 intel_update_watermarks(dev);
5509
5510 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5511
1f803ee5 5512 return ret;
79e53945
JB		 5513}
5514
f564048e
EA		 5515static int intel_crtc_mode_set(struct drm_crtc *crtc,
5516 struct drm_display_mode *mode,
5517 struct drm_display_mode *adjusted_mode,
5518 int x, int y,
94352cf9 5519 struct drm_framebuffer *fb)
f564048e
EA		 5520{
5521 struct drm_device *dev = crtc->dev;
5522 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5523 struct drm_encoder_helper_funcs *encoder_funcs;
5524 struct intel_encoder *encoder;
0b701d27
EA		 5525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5526 int pipe = intel_crtc->pipe;
f564048e
EA		 5527 int ret;
5528
0b701d27 5529 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5530
f564048e 5531 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5532 x, y, fb);
79e53945 5533 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5534
9256aa19
DV		 5535 if (ret != 0)
5536 return ret;
5537
5538 for_each_encoder_on_crtc(dev, crtc, encoder) {
5539 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5540 encoder->base.base.id,
5541 drm_get_encoder_name(&encoder->base),
5542 mode->base.id, mode->name);
5543 encoder_funcs = encoder->base.helper_private;
5544 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5545 }
5546
5547 return 0;
79e53945
JB		 5548}
5549
3a9627f4
WF		 5550static bool intel_eld_uptodate(struct drm_connector *connector,
5551 int reg_eldv, uint32_t bits_eldv,
5552 int reg_elda, uint32_t bits_elda,
5553 int reg_edid)
5554{
5555 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5556 uint8_t *eld = connector->eld;
5557 uint32_t i;
5558
5559 i = I915_READ(reg_eldv);
5560 i &= bits_eldv;
5561
5562 if (!eld[0])
5563 return !i;
5564
5565 if (!i)
5566 return false;
5567
5568 i = I915_READ(reg_elda);
5569 i &= ~bits_elda;
5570 I915_WRITE(reg_elda, i);
5571
5572 for (i = 0; i < eld[2]; i++)
5573 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5574 return false;
5575
5576 return true;
5577}
5578
e0dac65e
WF		 5579static void g4x_write_eld(struct drm_connector *connector,
5580 struct drm_crtc *crtc)
5581{
5582 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5583 uint8_t *eld = connector->eld;
5584 uint32_t eldv;
5585 uint32_t len;
5586 uint32_t i;
5587
5588 i = I915_READ(G4X_AUD_VID_DID);
5589
5590 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5591 eldv = G4X_ELDV_DEVCL_DEVBLC;
5592 else
5593 eldv = G4X_ELDV_DEVCTG;
5594
3a9627f4
WF		 5595 if (intel_eld_uptodate(connector,
5596 G4X_AUD_CNTL_ST, eldv,
5597 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5598 G4X_HDMIW_HDMIEDID))
5599 return;
5600
e0dac65e
WF		 5601 i = I915_READ(G4X_AUD_CNTL_ST);
5602 i &= ~(eldv | G4X_ELD_ADDR);
5603 len = (i >> 9) & 0x1f; /* ELD buffer size */
5604 I915_WRITE(G4X_AUD_CNTL_ST, i);
5605
5606 if (!eld[0])
5607 return;
5608
5609 len = min_t(uint8_t, eld[2], len);
5610 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5611 for (i = 0; i < len; i++)
5612 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5613
5614 i = I915_READ(G4X_AUD_CNTL_ST);
5615 i |= eldv;
5616 I915_WRITE(G4X_AUD_CNTL_ST, i);
5617}
5618
83358c85
WX		 5619static void haswell_write_eld(struct drm_connector *connector,
5620 struct drm_crtc *crtc)
5621{
5622 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5623 uint8_t *eld = connector->eld;
5624 struct drm_device *dev = crtc->dev;
5625 uint32_t eldv;
5626 uint32_t i;
5627 int len;
5628 int pipe = to_intel_crtc(crtc)->pipe;
5629 int tmp;
5630
5631 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5632 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5633 int aud_config = HSW_AUD_CFG(pipe);
5634 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5635
5636
5637 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5638
5639 /* Audio output enable */
5640 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5641 tmp = I915_READ(aud_cntrl_st2);
5642 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5643 I915_WRITE(aud_cntrl_st2, tmp);
5644
5645 /* Wait for 1 vertical blank */
5646 intel_wait_for_vblank(dev, pipe);
5647
5648 /* Set ELD valid state */
5649 tmp = I915_READ(aud_cntrl_st2);
5650 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5651 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5652 I915_WRITE(aud_cntrl_st2, tmp);
5653 tmp = I915_READ(aud_cntrl_st2);
5654 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5655
5656 /* Enable HDMI mode */
5657 tmp = I915_READ(aud_config);
5658 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5659 /* clear N_programing_enable and N_value_index */
5660 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5661 I915_WRITE(aud_config, tmp);
5662
5663 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5664
5665 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5666
5667 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5668 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5669 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5670 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5671 } else
5672 I915_WRITE(aud_config, 0);
5673
5674 if (intel_eld_uptodate(connector,
5675 aud_cntrl_st2, eldv,
5676 aud_cntl_st, IBX_ELD_ADDRESS,
5677 hdmiw_hdmiedid))
5678 return;
5679
5680 i = I915_READ(aud_cntrl_st2);
5681 i &= ~eldv;
5682 I915_WRITE(aud_cntrl_st2, i);
5683
5684 if (!eld[0])
5685 return;
5686
5687 i = I915_READ(aud_cntl_st);
5688 i &= ~IBX_ELD_ADDRESS;
5689 I915_WRITE(aud_cntl_st, i);
5690 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5691 DRM_DEBUG_DRIVER("port num:%d\n", i);
5692
5693 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5694 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5695 for (i = 0; i < len; i++)
5696 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5697
5698 i = I915_READ(aud_cntrl_st2);
5699 i |= eldv;
5700 I915_WRITE(aud_cntrl_st2, i);
5701
5702}
5703
e0dac65e
WF		 5704static void ironlake_write_eld(struct drm_connector *connector,
5705 struct drm_crtc *crtc)
5706{
5707 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5708 uint8_t *eld = connector->eld;
5709 uint32_t eldv;
5710 uint32_t i;
5711 int len;
5712 int hdmiw_hdmiedid;
b6daa025 5713 int aud_config;
e0dac65e
WF		 5714 int aud_cntl_st;
5715 int aud_cntrl_st2;
9b138a83 5716 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5717
b3f33cbf 5718 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5719 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5720 aud_config = IBX_AUD_CFG(pipe);
5721 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5722 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5723 } else {
9b138a83
WX		 5724 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5725 aud_config = CPT_AUD_CFG(pipe);
5726 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5727 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5728 }
5729
9b138a83 5730 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5731
5732 i = I915_READ(aud_cntl_st);
9b138a83 5733 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5734 if (!i) {
5735 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5736 /* operate blindly on all ports */
1202b4c6
WF		 5737 eldv = IBX_ELD_VALIDB;
5738 eldv |= IBX_ELD_VALIDB << 4;
5739 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5740 } else {
5741 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5742 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5743 }
5744
3a9627f4
WF		 5745 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5746 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5747 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5748 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5749 } else
5750 I915_WRITE(aud_config, 0);
e0dac65e 5751
3a9627f4
WF		 5752 if (intel_eld_uptodate(connector,
5753 aud_cntrl_st2, eldv,
5754 aud_cntl_st, IBX_ELD_ADDRESS,
5755 hdmiw_hdmiedid))
5756 return;
5757
e0dac65e
WF		 5758 i = I915_READ(aud_cntrl_st2);
5759 i &= ~eldv;
5760 I915_WRITE(aud_cntrl_st2, i);
5761
5762 if (!eld[0])
5763 return;
5764
e0dac65e 5765 i = I915_READ(aud_cntl_st);
1202b4c6 5766 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5767 I915_WRITE(aud_cntl_st, i);
5768
5769 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5770 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5771 for (i = 0; i < len; i++)
5772 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5773
5774 i = I915_READ(aud_cntrl_st2);
5775 i |= eldv;
5776 I915_WRITE(aud_cntrl_st2, i);
5777}
5778
5779void intel_write_eld(struct drm_encoder *encoder,
5780 struct drm_display_mode *mode)
5781{
5782 struct drm_crtc *crtc = encoder->crtc;
5783 struct drm_connector *connector;
5784 struct drm_device *dev = encoder->dev;
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5786
5787 connector = drm_select_eld(encoder, mode);
5788 if (!connector)
5789 return;
5790
5791 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5792 connector->base.id,
5793 drm_get_connector_name(connector),
5794 connector->encoder->base.id,
5795 drm_get_encoder_name(connector->encoder));
5796
5797 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5798
5799 if (dev_priv->display.write_eld)
5800 dev_priv->display.write_eld(connector, crtc);
5801}
5802
79e53945
JB		 5803/** Loads the palette/gamma unit for the CRTC with the prepared values */
5804void intel_crtc_load_lut(struct drm_crtc *crtc)
5805{
5806 struct drm_device *dev = crtc->dev;
5807 struct drm_i915_private *dev_priv = dev->dev_private;
5808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5809 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5810 int i;
5811
5812 /* The clocks have to be on to load the palette. */
aed3f09d 5813 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5814 return;
5815
f2b115e6 5816 /* use legacy palette for Ironlake */
bad720ff 5817 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5818 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5819
79e53945
JB		 5820 for (i = 0; i < 256; i++) {
5821 I915_WRITE(palreg + 4 * i,
5822 (intel_crtc->lut_r[i] << 16) |
5823 (intel_crtc->lut_g[i] << 8) |
5824 intel_crtc->lut_b[i]);
5825 }
5826}
5827
560b85bb
CW		 5828static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5829{
5830 struct drm_device *dev = crtc->dev;
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5833 bool visible = base != 0;
5834 u32 cntl;
5835
5836 if (intel_crtc->cursor_visible == visible)
5837 return;
5838
9db4a9c7 5839 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5840 if (visible) {
5841 /* On these chipsets we can only modify the base whilst
5842 * the cursor is disabled.
5843 */
9db4a9c7 5844 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5845
5846 cntl &= ~(CURSOR_FORMAT_MASK);
5847 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5848 cntl |= CURSOR_ENABLE |
5849 CURSOR_GAMMA_ENABLE |
5850 CURSOR_FORMAT_ARGB;
5851 } else
5852 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5853 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5854
5855 intel_crtc->cursor_visible = visible;
5856}
5857
5858static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5859{
5860 struct drm_device *dev = crtc->dev;
5861 struct drm_i915_private *dev_priv = dev->dev_private;
5862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5863 int pipe = intel_crtc->pipe;
5864 bool visible = base != 0;
5865
5866 if (intel_crtc->cursor_visible != visible) {
548f245b 5867 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5868 if (base) {
5869 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5870 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5871 cntl |= pipe << 28; /* Connect to correct pipe */
5872 } else {
5873 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5874 cntl |= CURSOR_MODE_DISABLE;
5875 }
9db4a9c7 5876 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5877
5878 intel_crtc->cursor_visible = visible;
5879 }
5880 /* and commit changes on next vblank */
9db4a9c7 5881 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5882}
5883
65a21cd6
JB		 5884static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5885{
5886 struct drm_device *dev = crtc->dev;
5887 struct drm_i915_private *dev_priv = dev->dev_private;
5888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5889 int pipe = intel_crtc->pipe;
5890 bool visible = base != 0;
5891
5892 if (intel_crtc->cursor_visible != visible) {
5893 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5894 if (base) {
5895 cntl &= ~CURSOR_MODE;
5896 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5897 } else {
5898 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5899 cntl |= CURSOR_MODE_DISABLE;
5900 }
5901 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5902
5903 intel_crtc->cursor_visible = visible;
5904 }
5905 /* and commit changes on next vblank */
5906 I915_WRITE(CURBASE_IVB(pipe), base);
5907}
5908
cda4b7d3 5909/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5910static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5911 bool on)
cda4b7d3
CW		 5912{
5913 struct drm_device *dev = crtc->dev;
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916 int pipe = intel_crtc->pipe;
5917 int x = intel_crtc->cursor_x;
5918 int y = intel_crtc->cursor_y;
560b85bb 5919 u32 base, pos;
cda4b7d3
CW		 5920 bool visible;
5921
5922 pos = 0;
5923
6b383a7f 5924 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5925 base = intel_crtc->cursor_addr;
5926 if (x > (int) crtc->fb->width)
5927 base = 0;
5928
5929 if (y > (int) crtc->fb->height)
5930 base = 0;
5931 } else
5932 base = 0;
5933
5934 if (x < 0) {
5935 if (x + intel_crtc->cursor_width < 0)
5936 base = 0;
5937
5938 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5939 x = -x;
5940 }
5941 pos |= x << CURSOR_X_SHIFT;
5942
5943 if (y < 0) {
5944 if (y + intel_crtc->cursor_height < 0)
5945 base = 0;
5946
5947 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5948 y = -y;
5949 }
5950 pos |= y << CURSOR_Y_SHIFT;
5951
5952 visible = base != 0;
560b85bb 5953 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5954 return;
5955
0cd83aa9 5956 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5957 I915_WRITE(CURPOS_IVB(pipe), pos);
5958 ivb_update_cursor(crtc, base);
5959 } else {
5960 I915_WRITE(CURPOS(pipe), pos);
5961 if (IS_845G(dev) || IS_I865G(dev))
5962 i845_update_cursor(crtc, base);
5963 else
5964 i9xx_update_cursor(crtc, base);
5965 }
cda4b7d3
CW		 5966}
5967
79e53945 5968static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5969 struct drm_file *file,
79e53945
JB		 5970 uint32_t handle,
5971 uint32_t width, uint32_t height)
5972{
5973 struct drm_device *dev = crtc->dev;
5974 struct drm_i915_private *dev_priv = dev->dev_private;
5975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5976 struct drm_i915_gem_object *obj;
cda4b7d3 5977 uint32_t addr;
3f8bc370 5978 int ret;
79e53945 5979
79e53945
JB		 5980 /* if we want to turn off the cursor ignore width and height */
5981 if (!handle) {
28c97730 5982 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5983 addr = 0;
05394f39 5984 obj = NULL;
5004417d 5985 mutex_lock(&dev->struct_mutex);
3f8bc370 5986 goto finish;
79e53945
JB		 5987 }
5988
5989 /* Currently we only support 64x64 cursors */
5990 if (width != 64 || height != 64) {
5991 DRM_ERROR("we currently only support 64x64 cursors\n");
5992 return -EINVAL;
5993 }
5994
05394f39 5995 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5996 if (&obj->base == NULL)
79e53945
JB		 5997 return -ENOENT;
5998
05394f39 5999 if (obj->base.size < width * height * 4) {
79e53945 6000 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6001 ret = -ENOMEM;
6002 goto fail;
79e53945
JB		 6003 }
6004
71acb5eb 6005 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6006 mutex_lock(&dev->struct_mutex);
b295d1b6 6007 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6008 if (obj->tiling_mode) {
6009 DRM_ERROR("cursor cannot be tiled\n");
6010 ret = -EINVAL;
6011 goto fail_locked;
6012 }
6013
2da3b9b9 6014 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6015 if (ret) {
6016 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6017 goto fail_locked;
e7b526bb
CW		 6018 }
6019
d9e86c0e
CW		 6020 ret = i915_gem_object_put_fence(obj);
6021 if (ret) {
2da3b9b9 6022 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6023 goto fail_unpin;
6024 }
6025
05394f39 6026 addr = obj->gtt_offset;
71acb5eb 6027 } else {
6eeefaf3 6028 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6029 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6030 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6031 align);
71acb5eb
DA		 6032 if (ret) {
6033 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6034 goto fail_locked;
71acb5eb 6035 }
05394f39 6036 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6037 }
6038
a6c45cf0 6039 if (IS_GEN2(dev))
14b60391
JB		 6040 I915_WRITE(CURSIZE, (height << 12) | width);
6041
3f8bc370 6042 finish:
3f8bc370 6043 if (intel_crtc->cursor_bo) {
b295d1b6 6044 if (dev_priv->info->cursor_needs_physical) {
05394f39 6045 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6046 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6047 } else
6048 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6049 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6050 }
80824003 6051
7f9872e0 6052 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6053
6054 intel_crtc->cursor_addr = addr;
05394f39 6055 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6056 intel_crtc->cursor_width = width;
6057 intel_crtc->cursor_height = height;
6058
6b383a7f 6059 intel_crtc_update_cursor(crtc, true);
3f8bc370 6060
79e53945 6061 return 0;
e7b526bb 6062fail_unpin:
05394f39 6063 i915_gem_object_unpin(obj);
7f9872e0 6064fail_locked:
34b8686e 6065 mutex_unlock(&dev->struct_mutex);
bc9025bd 6066fail:
05394f39 6067 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6068 return ret;
79e53945
JB		 6069}
6070
6071static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6072{
79e53945 6073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6074
cda4b7d3
CW		 6075 intel_crtc->cursor_x = x;
6076 intel_crtc->cursor_y = y;
652c393a 6077
6b383a7f 6078 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6079
6080 return 0;
6081}
6082
6083/** Sets the color ramps on behalf of RandR */
6084void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6085 u16 blue, int regno)
6086{
6087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6088
6089 intel_crtc->lut_r[regno] = red >> 8;
6090 intel_crtc->lut_g[regno] = green >> 8;
6091 intel_crtc->lut_b[regno] = blue >> 8;
6092}
6093
b8c00ac5
DA		 6094void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6095 u16 *blue, int regno)
6096{
6097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6098
6099 *red = intel_crtc->lut_r[regno] << 8;
6100 *green = intel_crtc->lut_g[regno] << 8;
6101 *blue = intel_crtc->lut_b[regno] << 8;
6102}
6103
79e53945 6104static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6105 u16 *blue, uint32_t start, uint32_t size)
79e53945 6106{
7203425a 6107 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6109
7203425a 6110 for (i = start; i < end; i++) {
79e53945
JB		 6111 intel_crtc->lut_r[i] = red[i] >> 8;
6112 intel_crtc->lut_g[i] = green[i] >> 8;
6113 intel_crtc->lut_b[i] = blue[i] >> 8;
6114 }
6115
6116 intel_crtc_load_lut(crtc);
6117}
6118
6119/**
6120 * Get a pipe with a simple mode set on it for doing load-based monitor
6121 * detection.
6122 *
6123 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6124 * its requirements. The pipe will be connected to no other encoders.
79e53945 6125 *
c751ce4f 6126 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6127 * configured for it. In the future, it could choose to temporarily disable
6128 * some outputs to free up a pipe for its use.
6129 *
6130 * \return crtc, or NULL if no pipes are available.
6131 */
6132
6133/* VESA 640x480x72Hz mode to set on the pipe */
6134static struct drm_display_mode load_detect_mode = {
6135 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6136 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6137};
6138
d2dff872
CW		 6139static struct drm_framebuffer *
6140intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6141 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6142 struct drm_i915_gem_object *obj)
6143{
6144 struct intel_framebuffer *intel_fb;
6145 int ret;
6146
6147 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6148 if (!intel_fb) {
6149 drm_gem_object_unreference_unlocked(&obj->base);
6150 return ERR_PTR(-ENOMEM);
6151 }
6152
6153 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6154 if (ret) {
6155 drm_gem_object_unreference_unlocked(&obj->base);
6156 kfree(intel_fb);
6157 return ERR_PTR(ret);
6158 }
6159
6160 return &intel_fb->base;
6161}
6162
6163static u32
6164intel_framebuffer_pitch_for_width(int width, int bpp)
6165{
6166 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6167 return ALIGN(pitch, 64);
6168}
6169
6170static u32
6171intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6172{
6173 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6174 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6175}
6176
6177static struct drm_framebuffer *
6178intel_framebuffer_create_for_mode(struct drm_device *dev,
6179 struct drm_display_mode *mode,
6180 int depth, int bpp)
6181{
6182 struct drm_i915_gem_object *obj;
0fed39bd 6183 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6184
6185 obj = i915_gem_alloc_object(dev,
6186 intel_framebuffer_size_for_mode(mode, bpp));
6187 if (obj == NULL)
6188 return ERR_PTR(-ENOMEM);
6189
6190 mode_cmd.width = mode->hdisplay;
6191 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6192 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6193 bpp);
5ca0c34a 6194 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6195
6196 return intel_framebuffer_create(dev, &mode_cmd, obj);
6197}
6198
6199static struct drm_framebuffer *
6200mode_fits_in_fbdev(struct drm_device *dev,
6201 struct drm_display_mode *mode)
6202{
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 struct drm_i915_gem_object *obj;
6205 struct drm_framebuffer *fb;
6206
6207 if (dev_priv->fbdev == NULL)
6208 return NULL;
6209
6210 obj = dev_priv->fbdev->ifb.obj;
6211 if (obj == NULL)
6212 return NULL;
6213
6214 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6215 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6216 fb->bits_per_pixel))
d2dff872
CW		 6217 return NULL;
6218
01f2c773 6219 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6220 return NULL;
6221
6222 return fb;
6223}
6224
d2434ab7 6225bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6226 struct drm_display_mode *mode,
8261b191 6227 struct intel_load_detect_pipe *old)
79e53945
JB		 6228{
6229 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6230 struct intel_encoder *intel_encoder =
6231 intel_attached_encoder(connector);
79e53945 6232 struct drm_crtc *possible_crtc;
4ef69c7a 6233 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6234 struct drm_crtc *crtc = NULL;
6235 struct drm_device *dev = encoder->dev;
94352cf9 6236 struct drm_framebuffer *fb;
79e53945
JB		 6237 int i = -1;
6238
d2dff872
CW		 6239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6240 connector->base.id, drm_get_connector_name(connector),
6241 encoder->base.id, drm_get_encoder_name(encoder));
6242
79e53945
JB		 6243 /*
6244 * Algorithm gets a little messy:
7a5e4805 6245 *
79e53945
JB		 6246 * - if the connector already has an assigned crtc, use it (but make
6247 * sure it's on first)
7a5e4805 6248 *
79e53945
JB		 6249 * - try to find the first unused crtc that can drive this connector,
6250 * and use that if we find one
79e53945
JB		 6251 */
6252
6253 /* See if we already have a CRTC for this connector */
6254 if (encoder->crtc) {
6255 crtc = encoder->crtc;
8261b191 6256
24218aac 6257 old->dpms_mode = connector->dpms;
8261b191
CW		 6258 old->load_detect_temp = false;
6259
6260 /* Make sure the crtc and connector are running */
24218aac
DV		 6261 if (connector->dpms != DRM_MODE_DPMS_ON)
6262 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6263
7173188d 6264 return true;
79e53945
JB		 6265 }
6266
6267 /* Find an unused one (if possible) */
6268 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6269 i++;
6270 if (!(encoder->possible_crtcs & (1 << i)))
6271 continue;
6272 if (!possible_crtc->enabled) {
6273 crtc = possible_crtc;
6274 break;
6275 }
79e53945
JB		 6276 }
6277
6278 /*
6279 * If we didn't find an unused CRTC, don't use any.
6280 */
6281 if (!crtc) {
7173188d
CW		 6282 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6283 return false;
79e53945
JB		 6284 }
6285
fc303101
DV		 6286 intel_encoder->new_crtc = to_intel_crtc(crtc);
6287 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6288
6289 intel_crtc = to_intel_crtc(crtc);
24218aac 6290 old->dpms_mode = connector->dpms;
8261b191 6291 old->load_detect_temp = true;
d2dff872 6292 old->release_fb = NULL;
79e53945 6293
6492711d
CW		 6294 if (!mode)
6295 mode = &load_detect_mode;
79e53945 6296
d2dff872
CW		 6297 /* We need a framebuffer large enough to accommodate all accesses
6298 * that the plane may generate whilst we perform load detection.
6299 * We can not rely on the fbcon either being present (we get called
6300 * during its initialisation to detect all boot displays, or it may
6301 * not even exist) or that it is large enough to satisfy the
6302 * requested mode.
6303 */
94352cf9
DV		 6304 fb = mode_fits_in_fbdev(dev, mode);
6305 if (fb == NULL) {
d2dff872 6306 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6307 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6308 old->release_fb = fb;
d2dff872
CW		 6309 } else
6310 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6311 if (IS_ERR(fb)) {
d2dff872 6312 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6313 return false;
79e53945 6314 }
79e53945 6315
94352cf9 6316 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6317 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6318 if (old->release_fb)
6319 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6320 return false;
79e53945 6321 }
7173188d 6322
79e53945 6323 /* let the connector get through one full cycle before testing */
9d0498a2 6324 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6325 return true;
79e53945
JB		 6326}
6327
d2434ab7 6328void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6329 struct intel_load_detect_pipe *old)
79e53945 6330{
d2434ab7
DV		 6331 struct intel_encoder *intel_encoder =
6332 intel_attached_encoder(connector);
4ef69c7a 6333 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6334
d2dff872
CW		 6335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6336 connector->base.id, drm_get_connector_name(connector),
6337 encoder->base.id, drm_get_encoder_name(encoder));
6338
8261b191 6339 if (old->load_detect_temp) {
fc303101
DV		 6340 struct drm_crtc *crtc = encoder->crtc;
6341
6342 to_intel_connector(connector)->new_encoder = NULL;
6343 intel_encoder->new_crtc = NULL;
6344 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6345
6346 if (old->release_fb)
6347 old->release_fb->funcs->destroy(old->release_fb);
6348
0622a53c 6349 return;
79e53945
JB		 6350 }
6351
c751ce4f 6352 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6353 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6354 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6355}
6356
6357/* Returns the clock of the currently programmed mode of the given pipe. */
6358static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6359{
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362 int pipe = intel_crtc->pipe;
548f245b 6363 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6364 u32 fp;
6365 intel_clock_t clock;
6366
6367 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6368 fp = I915_READ(FP0(pipe));
79e53945 6369 else
39adb7a5 6370 fp = I915_READ(FP1(pipe));
79e53945
JB		 6371
6372 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6373 if (IS_PINEVIEW(dev)) {
6374 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6375 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6376 } else {
6377 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6378 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6379 }
6380
a6c45cf0 6381 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6382 if (IS_PINEVIEW(dev))
6383 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6384 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6385 else
6386 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6387 DPLL_FPA01_P1_POST_DIV_SHIFT);
6388
6389 switch (dpll & DPLL_MODE_MASK) {
6390 case DPLLB_MODE_DAC_SERIAL:
6391 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6392 5 : 10;
6393 break;
6394 case DPLLB_MODE_LVDS:
6395 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6396 7 : 14;
6397 break;
6398 default:
28c97730 6399 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6400 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6401 return 0;
6402 }
6403
6404 /* XXX: Handle the 100Mhz refclk */
2177832f 6405 intel_clock(dev, 96000, &clock);
79e53945
JB		 6406 } else {
6407 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6408
6409 if (is_lvds) {
6410 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6411 DPLL_FPA01_P1_POST_DIV_SHIFT);
6412 clock.p2 = 14;
6413
6414 if ((dpll & PLL_REF_INPUT_MASK) ==
6415 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6416 /* XXX: might not be 66MHz */
2177832f 6417 intel_clock(dev, 66000, &clock);
79e53945 6418 } else
2177832f 6419 intel_clock(dev, 48000, &clock);
79e53945
JB		 6420 } else {
6421 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6422 clock.p1 = 2;
6423 else {
6424 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6425 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6426 }
6427 if (dpll & PLL_P2_DIVIDE_BY_4)
6428 clock.p2 = 4;
6429 else
6430 clock.p2 = 2;
6431
2177832f 6432 intel_clock(dev, 48000, &clock);
79e53945
JB		 6433 }
6434 }
6435
6436 /* XXX: It would be nice to validate the clocks, but we can't reuse
6437 * i830PllIsValid() because it relies on the xf86_config connector
6438 * configuration being accurate, which it isn't necessarily.
6439 */
6440
6441 return clock.dot;
6442}
6443
6444/** Returns the currently programmed mode of the given pipe. */
6445struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6446 struct drm_crtc *crtc)
6447{
548f245b 6448 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6450 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6451 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6452 int htot = I915_READ(HTOTAL(cpu_transcoder));
6453 int hsync = I915_READ(HSYNC(cpu_transcoder));
6454 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6455 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6456
6457 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6458 if (!mode)
6459 return NULL;
6460
6461 mode->clock = intel_crtc_clock_get(dev, crtc);
6462 mode->hdisplay = (htot & 0xffff) + 1;
6463 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6464 mode->hsync_start = (hsync & 0xffff) + 1;
6465 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6466 mode->vdisplay = (vtot & 0xffff) + 1;
6467 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6468 mode->vsync_start = (vsync & 0xffff) + 1;
6469 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6470
6471 drm_mode_set_name(mode);
79e53945
JB		 6472
6473 return mode;
6474}
6475
3dec0095 6476static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6477{
6478 struct drm_device *dev = crtc->dev;
6479 drm_i915_private_t *dev_priv = dev->dev_private;
6480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6481 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6482 int dpll_reg = DPLL(pipe);
6483 int dpll;
652c393a 6484
bad720ff 6485 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6486 return;
6487
6488 if (!dev_priv->lvds_downclock_avail)
6489 return;
6490
dbdc6479 6491 dpll = I915_READ(dpll_reg);
652c393a 6492 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6493 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6494
8ac5a6d5 6495 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6496
6497 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6498 I915_WRITE(dpll_reg, dpll);
9d0498a2 6499 intel_wait_for_vblank(dev, pipe);
dbdc6479 6500
652c393a
JB		 6501 dpll = I915_READ(dpll_reg);
6502 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6503 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6504 }
652c393a
JB		 6505}
6506
6507static void intel_decrease_pllclock(struct drm_crtc *crtc)
6508{
6509 struct drm_device *dev = crtc->dev;
6510 drm_i915_private_t *dev_priv = dev->dev_private;
6511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6512
bad720ff 6513 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6514 return;
6515
6516 if (!dev_priv->lvds_downclock_avail)
6517 return;
6518
6519 /*
6520 * Since this is called by a timer, we should never get here in
6521 * the manual case.
6522 */
6523 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6524 int pipe = intel_crtc->pipe;
6525 int dpll_reg = DPLL(pipe);
6526 int dpll;
f6e5b160 6527
44d98a61 6528 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6529
8ac5a6d5 6530 assert_panel_unlocked(dev_priv, pipe);
652c393a 6531
dc257cf1 6532 dpll = I915_READ(dpll_reg);
652c393a
JB		 6533 dpll |= DISPLAY_RATE_SELECT_FPA1;
6534 I915_WRITE(dpll_reg, dpll);
9d0498a2 6535 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6536 dpll = I915_READ(dpll_reg);
6537 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6538 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6539 }
6540
6541}
6542
f047e395
CW		 6543void intel_mark_busy(struct drm_device *dev)
6544{
f047e395
CW		 6545 i915_update_gfx_val(dev->dev_private);
6546}
6547
6548void intel_mark_idle(struct drm_device *dev)
652c393a 6549{
f047e395
CW		 6550}
6551
6552void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6553{
6554 struct drm_device *dev = obj->base.dev;
652c393a 6555 struct drm_crtc *crtc;
652c393a
JB		 6556
6557 if (!i915_powersave)
6558 return;
6559
652c393a 6560 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6561 if (!crtc->fb)
6562 continue;
6563
f047e395
CW		 6564 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6565 intel_increase_pllclock(crtc);
652c393a 6566 }
652c393a
JB		 6567}
6568
f047e395 6569void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6570{
f047e395
CW		 6571 struct drm_device *dev = obj->base.dev;
6572 struct drm_crtc *crtc;
652c393a 6573
f047e395 6574 if (!i915_powersave)
acb87dfb
CW		 6575 return;
6576
652c393a
JB		 6577 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6578 if (!crtc->fb)
6579 continue;
6580
f047e395
CW		 6581 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6582 intel_decrease_pllclock(crtc);
652c393a
JB		 6583 }
6584}
6585
79e53945
JB		 6586static void intel_crtc_destroy(struct drm_crtc *crtc)
6587{
6588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6589 struct drm_device *dev = crtc->dev;
6590 struct intel_unpin_work *work;
6591 unsigned long flags;
6592
6593 spin_lock_irqsave(&dev->event_lock, flags);
6594 work = intel_crtc->unpin_work;
6595 intel_crtc->unpin_work = NULL;
6596 spin_unlock_irqrestore(&dev->event_lock, flags);
6597
6598 if (work) {
6599 cancel_work_sync(&work->work);
6600 kfree(work);
6601 }
79e53945
JB		 6602
6603 drm_crtc_cleanup(crtc);
67e77c5a 6604
79e53945
JB		 6605 kfree(intel_crtc);
6606}
6607
6b95a207
KH		 6608static void intel_unpin_work_fn(struct work_struct *__work)
6609{
6610 struct intel_unpin_work *work =
6611 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6612 struct drm_device *dev = work->crtc->dev;
6b95a207 6613
b4a98e57 6614 mutex_lock(&dev->struct_mutex);
1690e1eb 6615 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6616 drm_gem_object_unreference(&work->pending_flip_obj->base);
6617 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6618
b4a98e57
CW		 6619 intel_update_fbc(dev);
6620 mutex_unlock(&dev->struct_mutex);
6621
6622 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6623 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6624
6b95a207
KH		 6625 kfree(work);
6626}
6627
1afe3e9d 6628static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6629 struct drm_crtc *crtc)
6b95a207
KH		 6630{
6631 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6633 struct intel_unpin_work *work;
05394f39 6634 struct drm_i915_gem_object *obj;
6b95a207
KH		 6635 unsigned long flags;
6636
6637 /* Ignore early vblank irqs */
6638 if (intel_crtc == NULL)
6639 return;
6640
6641 spin_lock_irqsave(&dev->event_lock, flags);
6642 work = intel_crtc->unpin_work;
6643 if (work == NULL || !work->pending) {
6644 spin_unlock_irqrestore(&dev->event_lock, flags);
6645 return;
6646 }
6647
6648 intel_crtc->unpin_work = NULL;
6b95a207 6649
45a066eb
RC		 6650 if (work->event)
6651 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6652
0af7e4df
MK		 6653 drm_vblank_put(dev, intel_crtc->pipe);
6654
6b95a207
KH		 6655 spin_unlock_irqrestore(&dev->event_lock, flags);
6656
05394f39 6657 obj = work->old_fb_obj;
d9e86c0e 6658
5bb61643 6659 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6660
6661 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6662
6663 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6664}
6665
1afe3e9d
JB		 6666void intel_finish_page_flip(struct drm_device *dev, int pipe)
6667{
6668 drm_i915_private_t *dev_priv = dev->dev_private;
6669 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6670
49b14a5c 6671 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6672}
6673
6674void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6675{
6676 drm_i915_private_t *dev_priv = dev->dev_private;
6677 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6678
49b14a5c 6679 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6680}
6681
6b95a207
KH		 6682void intel_prepare_page_flip(struct drm_device *dev, int plane)
6683{
6684 drm_i915_private_t *dev_priv = dev->dev_private;
6685 struct intel_crtc *intel_crtc =
6686 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6687 unsigned long flags;
6688
6689 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6690 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6691 if ((++intel_crtc->unpin_work->pending) > 1)
6692 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6693 } else {
6694 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6695 }
6b95a207
KH		 6696 spin_unlock_irqrestore(&dev->event_lock, flags);
6697}
6698
8c9f3aaf
JB		 6699static int intel_gen2_queue_flip(struct drm_device *dev,
6700 struct drm_crtc *crtc,
6701 struct drm_framebuffer *fb,
6702 struct drm_i915_gem_object *obj)
6703{
6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6706 u32 flip_mask;
6d90c952 6707 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6708 int ret;
6709
6d90c952 6710 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6711 if (ret)
83d4092b 6712 goto err;
8c9f3aaf 6713
6d90c952 6714 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6715 if (ret)
83d4092b 6716 goto err_unpin;
8c9f3aaf
JB		 6717
6718 /* Can't queue multiple flips, so wait for the previous
6719 * one to finish before executing the next.
6720 */
6721 if (intel_crtc->plane)
6722 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6723 else
6724 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6725 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6726 intel_ring_emit(ring, MI_NOOP);
6727 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6728 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6729 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6730 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6731 intel_ring_emit(ring, 0); /* aux display base address, unused */
6732 intel_ring_advance(ring);
83d4092b
CW		 6733 return 0;
6734
6735err_unpin:
6736 intel_unpin_fb_obj(obj);
6737err:
8c9f3aaf
JB		 6738 return ret;
6739}
6740
6741static int intel_gen3_queue_flip(struct drm_device *dev,
6742 struct drm_crtc *crtc,
6743 struct drm_framebuffer *fb,
6744 struct drm_i915_gem_object *obj)
6745{
6746 struct drm_i915_private *dev_priv = dev->dev_private;
6747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6748 u32 flip_mask;
6d90c952 6749 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6750 int ret;
6751
6d90c952 6752 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6753 if (ret)
83d4092b 6754 goto err;
8c9f3aaf 6755
6d90c952 6756 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6757 if (ret)
83d4092b 6758 goto err_unpin;
8c9f3aaf
JB		 6759
6760 if (intel_crtc->plane)
6761 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6762 else
6763 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6764 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6765 intel_ring_emit(ring, MI_NOOP);
6766 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6767 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6768 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6769 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6770 intel_ring_emit(ring, MI_NOOP);
6771
6772 intel_ring_advance(ring);
83d4092b
CW		 6773 return 0;
6774
6775err_unpin:
6776 intel_unpin_fb_obj(obj);
6777err:
8c9f3aaf
JB		 6778 return ret;
6779}
6780
6781static int intel_gen4_queue_flip(struct drm_device *dev,
6782 struct drm_crtc *crtc,
6783 struct drm_framebuffer *fb,
6784 struct drm_i915_gem_object *obj)
6785{
6786 struct drm_i915_private *dev_priv = dev->dev_private;
6787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6788 uint32_t pf, pipesrc;
6d90c952 6789 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6790 int ret;
6791
6d90c952 6792 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6793 if (ret)
83d4092b 6794 goto err;
8c9f3aaf 6795
6d90c952 6796 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6797 if (ret)
83d4092b 6798 goto err_unpin;
8c9f3aaf
JB		 6799
6800 /* i965+ uses the linear or tiled offsets from the
6801 * Display Registers (which do not change across a page-flip)
6802 * so we need only reprogram the base address.
6803 */
6d90c952
DV		 6804 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6805 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6806 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6807 intel_ring_emit(ring,
6808 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6809 obj->tiling_mode);
8c9f3aaf
JB		 6810
6811 /* XXX Enabling the panel-fitter across page-flip is so far
6812 * untested on non-native modes, so ignore it for now.
6813 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6814 */
6815 pf = 0;
6816 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6817 intel_ring_emit(ring, pf | pipesrc);
6818 intel_ring_advance(ring);
83d4092b
CW		 6819 return 0;
6820
6821err_unpin:
6822 intel_unpin_fb_obj(obj);
6823err:
8c9f3aaf
JB		 6824 return ret;
6825}
6826
6827static int intel_gen6_queue_flip(struct drm_device *dev,
6828 struct drm_crtc *crtc,
6829 struct drm_framebuffer *fb,
6830 struct drm_i915_gem_object *obj)
6831{
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6834 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6835 uint32_t pf, pipesrc;
6836 int ret;
6837
6d90c952 6838 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6839 if (ret)
83d4092b 6840 goto err;
8c9f3aaf 6841
6d90c952 6842 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6843 if (ret)
83d4092b 6844 goto err_unpin;
8c9f3aaf 6845
6d90c952
DV		 6846 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6847 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6848 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6849 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6850
dc257cf1
DV		 6851 /* Contrary to the suggestions in the documentation,
6852 * "Enable Panel Fitter" does not seem to be required when page
6853 * flipping with a non-native mode, and worse causes a normal
6854 * modeset to fail.
6855 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6856 */
6857 pf = 0;
8c9f3aaf 6858 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6859 intel_ring_emit(ring, pf | pipesrc);
6860 intel_ring_advance(ring);
83d4092b
CW		 6861 return 0;
6862
6863err_unpin:
6864 intel_unpin_fb_obj(obj);
6865err:
8c9f3aaf
JB		 6866 return ret;
6867}
6868
7c9017e5
JB		 6869/*
6870 * On gen7 we currently use the blit ring because (in early silicon at least)
6871 * the render ring doesn't give us interrpts for page flip completion, which
6872 * means clients will hang after the first flip is queued. Fortunately the
6873 * blit ring generates interrupts properly, so use it instead.
6874 */
6875static int intel_gen7_queue_flip(struct drm_device *dev,
6876 struct drm_crtc *crtc,
6877 struct drm_framebuffer *fb,
6878 struct drm_i915_gem_object *obj)
6879{
6880 struct drm_i915_private *dev_priv = dev->dev_private;
6881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6882 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6883 uint32_t plane_bit = 0;
7c9017e5
JB		 6884 int ret;
6885
6886 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6887 if (ret)
83d4092b 6888 goto err;
7c9017e5 6889
cb05d8de
DV		 6890 switch(intel_crtc->plane) {
6891 case PLANE_A:
6892 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6893 break;
6894 case PLANE_B:
6895 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6896 break;
6897 case PLANE_C:
6898 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6899 break;
6900 default:
6901 WARN_ONCE(1, "unknown plane in flip command\n");
6902 ret = -ENODEV;
ab3951eb 6903 goto err_unpin;
cb05d8de
DV		 6904 }
6905
7c9017e5
JB		 6906 ret = intel_ring_begin(ring, 4);
6907 if (ret)
83d4092b 6908 goto err_unpin;
7c9017e5 6909
cb05d8de 6910 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6911 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6912 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6913 intel_ring_emit(ring, (MI_NOOP));
6914 intel_ring_advance(ring);
83d4092b
CW		 6915 return 0;
6916
6917err_unpin:
6918 intel_unpin_fb_obj(obj);
6919err:
7c9017e5
JB		 6920 return ret;
6921}
6922
8c9f3aaf
JB		 6923static int intel_default_queue_flip(struct drm_device *dev,
6924 struct drm_crtc *crtc,
6925 struct drm_framebuffer *fb,
6926 struct drm_i915_gem_object *obj)
6927{
6928 return -ENODEV;
6929}
6930
6b95a207
KH		 6931static int intel_crtc_page_flip(struct drm_crtc *crtc,
6932 struct drm_framebuffer *fb,
6933 struct drm_pending_vblank_event *event)
6934{
6935 struct drm_device *dev = crtc->dev;
6936 struct drm_i915_private *dev_priv = dev->dev_private;
6937 struct intel_framebuffer *intel_fb;
05394f39 6938 struct drm_i915_gem_object *obj;
6b95a207
KH		 6939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6940 struct intel_unpin_work *work;
8c9f3aaf 6941 unsigned long flags;
52e68630 6942 int ret;
6b95a207 6943
e6a595d2
VS		 6944 /* Can't change pixel format via MI display flips. */
6945 if (fb->pixel_format != crtc->fb->pixel_format)
6946 return -EINVAL;
6947
6948 /*
6949 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6950 * Note that pitch changes could also affect these register.
6951 */
6952 if (INTEL_INFO(dev)->gen > 3 &&
6953 (fb->offsets[0] != crtc->fb->offsets[0] ||
6954 fb->pitches[0] != crtc->fb->pitches[0]))
6955 return -EINVAL;
6956
6b95a207
KH		 6957 work = kzalloc(sizeof *work, GFP_KERNEL);
6958 if (work == NULL)
6959 return -ENOMEM;
6960
6b95a207 6961 work->event = event;
b4a98e57 6962 work->crtc = crtc;
6b95a207 6963 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6964 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6965 INIT_WORK(&work->work, intel_unpin_work_fn);
6966
7317c75e
JB		 6967 ret = drm_vblank_get(dev, intel_crtc->pipe);
6968 if (ret)
6969 goto free_work;
6970
6b95a207
KH		 6971 /* We borrow the event spin lock for protecting unpin_work */
6972 spin_lock_irqsave(&dev->event_lock, flags);
6973 if (intel_crtc->unpin_work) {
6974 spin_unlock_irqrestore(&dev->event_lock, flags);
6975 kfree(work);
7317c75e 6976 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6977
6978 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6979 return -EBUSY;
6980 }
6981 intel_crtc->unpin_work = work;
6982 spin_unlock_irqrestore(&dev->event_lock, flags);
6983
6984 intel_fb = to_intel_framebuffer(fb);
6985 obj = intel_fb->obj;
6986
b4a98e57
CW		 6987 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
6988 flush_workqueue(dev_priv->wq);
6989
79158103
CW		 6990 ret = i915_mutex_lock_interruptible(dev);
6991 if (ret)
6992 goto cleanup;
6b95a207 6993
75dfca80 6994 /* Reference the objects for the scheduled work. */
05394f39
CW		 6995 drm_gem_object_reference(&work->old_fb_obj->base);
6996 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6997
6998 crtc->fb = fb;
96b099fd 6999
e1f99ce6 7000 work->pending_flip_obj = obj;
e1f99ce6 7001
4e5359cd
SF		 7002 work->enable_stall_check = true;
7003
b4a98e57 7004 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7005
8c9f3aaf
JB		 7006 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7007 if (ret)
7008 goto cleanup_pending;
6b95a207 7009
7782de3b 7010 intel_disable_fbc(dev);
f047e395 7011 intel_mark_fb_busy(obj);
6b95a207
KH		 7012 mutex_unlock(&dev->struct_mutex);
7013
e5510fac
JB		 7014 trace_i915_flip_request(intel_crtc->plane, obj);
7015
6b95a207 7016 return 0;
96b099fd 7017
8c9f3aaf 7018cleanup_pending:
b4a98e57 7019 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7020 drm_gem_object_unreference(&work->old_fb_obj->base);
7021 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7022 mutex_unlock(&dev->struct_mutex);
7023
79158103 7024cleanup:
96b099fd
CW		 7025 spin_lock_irqsave(&dev->event_lock, flags);
7026 intel_crtc->unpin_work = NULL;
7027 spin_unlock_irqrestore(&dev->event_lock, flags);
7028
7317c75e
JB		 7029 drm_vblank_put(dev, intel_crtc->pipe);
7030free_work:
96b099fd
CW		 7031 kfree(work);
7032
7033 return ret;
6b95a207
KH		 7034}
7035
f6e5b160 7036static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7037 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7038 .load_lut = intel_crtc_load_lut,
976f8a20 7039 .disable = intel_crtc_noop,
f6e5b160
CW		 7040};
7041
6ed0f796 7042bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7043{
6ed0f796
DV		 7044 struct intel_encoder *other_encoder;
7045 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7046
6ed0f796
DV		 7047 if (WARN_ON(!crtc))
7048 return false;
7049
7050 list_for_each_entry(other_encoder,
7051 &crtc->dev->mode_config.encoder_list,
7052 base.head) {
7053
7054 if (&other_encoder->new_crtc->base != crtc ||
7055 encoder == other_encoder)
7056 continue;
7057 else
7058 return true;
f47166d2
CW		 7059 }
7060
6ed0f796
DV		 7061 return false;
7062}
47f1c6c9 7063
50f56119
DV		 7064static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7065 struct drm_crtc *crtc)
7066{
7067 struct drm_device *dev;
7068 struct drm_crtc *tmp;
7069 int crtc_mask = 1;
47f1c6c9 7070
50f56119 7071 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7072
50f56119 7073 dev = crtc->dev;
47f1c6c9 7074
50f56119
DV		 7075 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7076 if (tmp == crtc)
7077 break;
7078 crtc_mask <<= 1;
7079 }
47f1c6c9 7080
50f56119
DV		 7081 if (encoder->possible_crtcs & crtc_mask)
7082 return true;
7083 return false;
47f1c6c9 7084}
79e53945 7085
9a935856
DV		 7086/**
7087 * intel_modeset_update_staged_output_state
7088 *
7089 * Updates the staged output configuration state, e.g. after we've read out the
7090 * current hw state.
7091 */
7092static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7093{
9a935856
DV		 7094 struct intel_encoder *encoder;
7095 struct intel_connector *connector;
f6e5b160 7096
9a935856
DV		 7097 list_for_each_entry(connector, &dev->mode_config.connector_list,
7098 base.head) {
7099 connector->new_encoder =
7100 to_intel_encoder(connector->base.encoder);
7101 }
f6e5b160 7102
9a935856
DV		 7103 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7104 base.head) {
7105 encoder->new_crtc =
7106 to_intel_crtc(encoder->base.crtc);
7107 }
f6e5b160
CW		 7108}
7109
9a935856
DV		 7110/**
7111 * intel_modeset_commit_output_state
7112 *
7113 * This function copies the stage display pipe configuration to the real one.
7114 */
7115static void intel_modeset_commit_output_state(struct drm_device *dev)
7116{
7117 struct intel_encoder *encoder;
7118 struct intel_connector *connector;
f6e5b160 7119
9a935856
DV		 7120 list_for_each_entry(connector, &dev->mode_config.connector_list,
7121 base.head) {
7122 connector->base.encoder = &connector->new_encoder->base;
7123 }
f6e5b160 7124
9a935856
DV		 7125 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7126 base.head) {
7127 encoder->base.crtc = &encoder->new_crtc->base;
7128 }
7129}
7130
7758a113
DV		 7131static struct drm_display_mode *
7132intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7133 struct drm_display_mode *mode)
ee7b9f93 7134{
7758a113
DV		 7135 struct drm_device *dev = crtc->dev;
7136 struct drm_display_mode *adjusted_mode;
7137 struct drm_encoder_helper_funcs *encoder_funcs;
7138 struct intel_encoder *encoder;
ee7b9f93 7139
7758a113
DV		 7140 adjusted_mode = drm_mode_duplicate(dev, mode);
7141 if (!adjusted_mode)
7142 return ERR_PTR(-ENOMEM);
7143
7144 /* Pass our mode to the connectors and the CRTC to give them a chance to
7145 * adjust it according to limitations or connector properties, and also
7146 * a chance to reject the mode entirely.
47f1c6c9 7147 */
7758a113
DV		 7148 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7149 base.head) {
47f1c6c9 7150
7758a113
DV		 7151 if (&encoder->new_crtc->base != crtc)
7152 continue;
7153 encoder_funcs = encoder->base.helper_private;
7154 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7155 adjusted_mode))) {
7156 DRM_DEBUG_KMS("Encoder fixup failed\n");
7157 goto fail;
7158 }
ee7b9f93 7159 }
47f1c6c9 7160
7758a113
DV		 7161 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7162 DRM_DEBUG_KMS("CRTC fixup failed\n");
7163 goto fail;
ee7b9f93 7164 }
7758a113 7165 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7166
7758a113
DV		 7167 return adjusted_mode;
7168fail:
7169 drm_mode_destroy(dev, adjusted_mode);
7170 return ERR_PTR(-EINVAL);
ee7b9f93 7171}
47f1c6c9 7172
e2e1ed41
DV		 7173/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7174 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7175static void
7176intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7177 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7178{
7179 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7180 struct drm_device *dev = crtc->dev;
7181 struct intel_encoder *encoder;
7182 struct intel_connector *connector;
7183 struct drm_crtc *tmp_crtc;
79e53945 7184
e2e1ed41 7185 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7186
e2e1ed41
DV		 7187 /* Check which crtcs have changed outputs connected to them, these need
7188 * to be part of the prepare_pipes mask. We don't (yet) support global
7189 * modeset across multiple crtcs, so modeset_pipes will only have one
7190 * bit set at most. */
7191 list_for_each_entry(connector, &dev->mode_config.connector_list,
7192 base.head) {
7193 if (connector->base.encoder == &connector->new_encoder->base)
7194 continue;
79e53945 7195
e2e1ed41
DV		 7196 if (connector->base.encoder) {
7197 tmp_crtc = connector->base.encoder->crtc;
7198
7199 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7200 }
7201
7202 if (connector->new_encoder)
7203 *prepare_pipes |=
7204 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7205 }
7206
e2e1ed41
DV		 7207 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7208 base.head) {
7209 if (encoder->base.crtc == &encoder->new_crtc->base)
7210 continue;
7211
7212 if (encoder->base.crtc) {
7213 tmp_crtc = encoder->base.crtc;
7214
7215 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7216 }
7217
7218 if (encoder->new_crtc)
7219 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7220 }
7221
e2e1ed41
DV		 7222 /* Check for any pipes that will be fully disabled ... */
7223 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7224 base.head) {
7225 bool used = false;
22fd0fab 7226
e2e1ed41
DV		 7227 /* Don't try to disable disabled crtcs. */
7228 if (!intel_crtc->base.enabled)
7229 continue;
7e7d76c3 7230
e2e1ed41
DV		 7231 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7232 base.head) {
7233 if (encoder->new_crtc == intel_crtc)
7234 used = true;
7235 }
7236
7237 if (!used)
7238 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7239 }
7240
e2e1ed41
DV		 7241
7242 /* set_mode is also used to update properties on life display pipes. */
7243 intel_crtc = to_intel_crtc(crtc);
7244 if (crtc->enabled)
7245 *prepare_pipes |= 1 << intel_crtc->pipe;
7246
7247 /* We only support modeset on one single crtc, hence we need to do that
7248 * only for the passed in crtc iff we change anything else than just
7249 * disable crtcs.
7250 *
7251 * This is actually not true, to be fully compatible with the old crtc
7252 * helper we automatically disable _any_ output (i.e. doesn't need to be
7253 * connected to the crtc we're modesetting on) if it's disconnected.
7254 * Which is a rather nutty api (since changed the output configuration
7255 * without userspace's explicit request can lead to confusion), but
7256 * alas. Hence we currently need to modeset on all pipes we prepare. */
7257 if (*prepare_pipes)
7258 *modeset_pipes = *prepare_pipes;
7259
7260 /* ... and mask these out. */
7261 *modeset_pipes &= ~(*disable_pipes);
7262 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7263}
79e53945 7264
ea9d758d 7265static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7266{
ea9d758d 7267 struct drm_encoder *encoder;
f6e5b160 7268 struct drm_device *dev = crtc->dev;
f6e5b160 7269
ea9d758d
DV		 7270 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7271 if (encoder->crtc == crtc)
7272 return true;
7273
7274 return false;
7275}
7276
7277static void
7278intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7279{
7280 struct intel_encoder *intel_encoder;
7281 struct intel_crtc *intel_crtc;
7282 struct drm_connector *connector;
7283
7284 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7285 base.head) {
7286 if (!intel_encoder->base.crtc)
7287 continue;
7288
7289 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7290
7291 if (prepare_pipes & (1 << intel_crtc->pipe))
7292 intel_encoder->connectors_active = false;
7293 }
7294
7295 intel_modeset_commit_output_state(dev);
7296
7297 /* Update computed state. */
7298 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7299 base.head) {
7300 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7301 }
7302
7303 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7304 if (!connector->encoder || !connector->encoder->crtc)
7305 continue;
7306
7307 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7308
7309 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7310 struct drm_property *dpms_property =
7311 dev->mode_config.dpms_property;
7312
ea9d758d 7313 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7314 drm_object_property_set_value(&connector->base,
68d34720
DV		 7315 dpms_property,
7316 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7317
7318 intel_encoder = to_intel_encoder(connector->encoder);
7319 intel_encoder->connectors_active = true;
7320 }
7321 }
7322
7323}
7324
25c5b266
DV		 7325#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7326 list_for_each_entry((intel_crtc), \
7327 &(dev)->mode_config.crtc_list, \
7328 base.head) \
7329 if (mask & (1 <<(intel_crtc)->pipe)) \
7330
b980514c 7331void
8af6cf88
DV		 7332intel_modeset_check_state(struct drm_device *dev)
7333{
7334 struct intel_crtc *crtc;
7335 struct intel_encoder *encoder;
7336 struct intel_connector *connector;
7337
7338 list_for_each_entry(connector, &dev->mode_config.connector_list,
7339 base.head) {
7340 /* This also checks the encoder/connector hw state with the
7341 * ->get_hw_state callbacks. */
7342 intel_connector_check_state(connector);
7343
7344 WARN(&connector->new_encoder->base != connector->base.encoder,
7345 "connector's staged encoder doesn't match current encoder\n");
7346 }
7347
7348 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7349 base.head) {
7350 bool enabled = false;
7351 bool active = false;
7352 enum pipe pipe, tracked_pipe;
7353
7354 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7355 encoder->base.base.id,
7356 drm_get_encoder_name(&encoder->base));
7357
7358 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7359 "encoder's stage crtc doesn't match current crtc\n");
7360 WARN(encoder->connectors_active && !encoder->base.crtc,
7361 "encoder's active_connectors set, but no crtc\n");
7362
7363 list_for_each_entry(connector, &dev->mode_config.connector_list,
7364 base.head) {
7365 if (connector->base.encoder != &encoder->base)
7366 continue;
7367 enabled = true;
7368 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7369 active = true;
7370 }
7371 WARN(!!encoder->base.crtc != enabled,
7372 "encoder's enabled state mismatch "
7373 "(expected %i, found %i)\n",
7374 !!encoder->base.crtc, enabled);
7375 WARN(active && !encoder->base.crtc,
7376 "active encoder with no crtc\n");
7377
7378 WARN(encoder->connectors_active != active,
7379 "encoder's computed active state doesn't match tracked active state "
7380 "(expected %i, found %i)\n", active, encoder->connectors_active);
7381
7382 active = encoder->get_hw_state(encoder, &pipe);
7383 WARN(active != encoder->connectors_active,
7384 "encoder's hw state doesn't match sw tracking "
7385 "(expected %i, found %i)\n",
7386 encoder->connectors_active, active);
7387
7388 if (!encoder->base.crtc)
7389 continue;
7390
7391 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7392 WARN(active && pipe != tracked_pipe,
7393 "active encoder's pipe doesn't match"
7394 "(expected %i, found %i)\n",
7395 tracked_pipe, pipe);
7396
7397 }
7398
7399 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7400 base.head) {
7401 bool enabled = false;
7402 bool active = false;
7403
7404 DRM_DEBUG_KMS("[CRTC:%d]\n",
7405 crtc->base.base.id);
7406
7407 WARN(crtc->active && !crtc->base.enabled,
7408 "active crtc, but not enabled in sw tracking\n");
7409
7410 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7411 base.head) {
7412 if (encoder->base.crtc != &crtc->base)
7413 continue;
7414 enabled = true;
7415 if (encoder->connectors_active)
7416 active = true;
7417 }
7418 WARN(active != crtc->active,
7419 "crtc's computed active state doesn't match tracked active state "
7420 "(expected %i, found %i)\n", active, crtc->active);
7421 WARN(enabled != crtc->base.enabled,
7422 "crtc's computed enabled state doesn't match tracked enabled state "
7423 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7424
7425 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7426 }
7427}
7428
a6778b3c
DV		 7429bool intel_set_mode(struct drm_crtc *crtc,
7430 struct drm_display_mode *mode,
94352cf9 7431 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7432{
7433 struct drm_device *dev = crtc->dev;
dbf2b54e 7434 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7435 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7436 struct intel_crtc *intel_crtc;
7437 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7438 bool ret = true;
7439
3ac18232
TG		 7440 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7441 if (!saved_mode) {
7442 DRM_ERROR("i915: Could not allocate saved display mode.\n");
7443 return false;
7444 }
7445 saved_hwmode = saved_mode + 1;
7446
e2e1ed41 7447 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7448 &prepare_pipes, &disable_pipes);
7449
7450 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7451 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7452
976f8a20
DV		 7453 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7454 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7455
3ac18232
TG		 7456 *saved_hwmode = crtc->hwmode;
7457 *saved_mode = crtc->mode;
a6778b3c 7458
25c5b266
DV		 7459 /* Hack: Because we don't (yet) support global modeset on multiple
7460 * crtcs, we don't keep track of the new mode for more than one crtc.
7461 * Hence simply check whether any bit is set in modeset_pipes in all the
7462 * pieces of code that are not yet converted to deal with mutliple crtcs
7463 * changing their mode at the same time. */
7464 adjusted_mode = NULL;
7465 if (modeset_pipes) {
7466 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7467 if (IS_ERR(adjusted_mode)) {
3ac18232
TG		 7468 ret = false;
7469 goto out;
25c5b266 7470 }
25c5b266 7471 }
a6778b3c 7472
ea9d758d
DV		 7473 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7474 if (intel_crtc->base.enabled)
7475 dev_priv->display.crtc_disable(&intel_crtc->base);
7476 }
a6778b3c 7477
6c4c86f5
DV		 7478 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7479 * to set it here already despite that we pass it down the callchain.
f6e5b160 7480 */
6c4c86f5 7481 if (modeset_pipes)
25c5b266 7482 crtc->mode = *mode;
7758a113 7483
ea9d758d
DV		 7484 /* Only after disabling all output pipelines that will be changed can we
7485 * update the the output configuration. */
7486 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7487
47fab737
DV		 7488 if (dev_priv->display.modeset_global_resources)
7489 dev_priv->display.modeset_global_resources(dev);
7490
a6778b3c
DV		 7491 /* Set up the DPLL and any encoders state that needs to adjust or depend
7492 * on the DPLL.
f6e5b160 7493 */
25c5b266
DV		 7494 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7495 ret = !intel_crtc_mode_set(&intel_crtc->base,
7496 mode, adjusted_mode,
7497 x, y, fb);
7498 if (!ret)
7499 goto done;
a6778b3c
DV		 7500 }
7501
7502 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7503 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7504 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7505
25c5b266
DV		 7506 if (modeset_pipes) {
7507 /* Store real post-adjustment hardware mode. */
7508 crtc->hwmode = *adjusted_mode;
a6778b3c 7509
25c5b266
DV		 7510 /* Calculate and store various constants which
7511 * are later needed by vblank and swap-completion
7512 * timestamping. They are derived from true hwmode.
7513 */
7514 drm_calc_timestamping_constants(crtc);
7515 }
a6778b3c
DV		 7516
7517 /* FIXME: add subpixel order */
7518done:
7519 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7520 if (!ret && crtc->enabled) {
3ac18232
TG		 7521 crtc->hwmode = *saved_hwmode;
7522 crtc->mode = *saved_mode;
8af6cf88
DV		 7523 } else {
7524 intel_modeset_check_state(dev);
a6778b3c
DV		 7525 }
7526
3ac18232
TG		 7527out:
7528 kfree(saved_mode);
a6778b3c 7529 return ret;
f6e5b160
CW		 7530}
7531
25c5b266
DV		 7532#undef for_each_intel_crtc_masked
7533
d9e55608
DV		 7534static void intel_set_config_free(struct intel_set_config *config)
7535{
7536 if (!config)
7537 return;
7538
1aa4b628
DV		 7539 kfree(config->save_connector_encoders);
7540 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7541 kfree(config);
7542}
7543
85f9eb71
DV		 7544static int intel_set_config_save_state(struct drm_device *dev,
7545 struct intel_set_config *config)
7546{
85f9eb71
DV		 7547 struct drm_encoder *encoder;
7548 struct drm_connector *connector;
7549 int count;
7550
1aa4b628
DV		 7551 config->save_encoder_crtcs =
7552 kcalloc(dev->mode_config.num_encoder,
7553 sizeof(struct drm_crtc *), GFP_KERNEL);
7554 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7555 return -ENOMEM;
7556
1aa4b628
DV		 7557 config->save_connector_encoders =
7558 kcalloc(dev->mode_config.num_connector,
7559 sizeof(struct drm_encoder *), GFP_KERNEL);
7560 if (!config->save_connector_encoders)
85f9eb71
DV		 7561 return -ENOMEM;
7562
7563 /* Copy data. Note that driver private data is not affected.
7564 * Should anything bad happen only the expected state is
7565 * restored, not the drivers personal bookkeeping.
7566 */
85f9eb71
DV		 7567 count = 0;
7568 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7569 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7570 }
7571
7572 count = 0;
7573 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7574 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7575 }
7576
7577 return 0;
7578}
7579
7580static void intel_set_config_restore_state(struct drm_device *dev,
7581 struct intel_set_config *config)
7582{
9a935856
DV		 7583 struct intel_encoder *encoder;
7584 struct intel_connector *connector;
85f9eb71
DV		 7585 int count;
7586
85f9eb71 7587 count = 0;
9a935856
DV		 7588 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7589 encoder->new_crtc =
7590 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7591 }
7592
7593 count = 0;
9a935856
DV		 7594 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7595 connector->new_encoder =
7596 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7597 }
7598}
7599
5e2b584e
DV		 7600static void
7601intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7602 struct intel_set_config *config)
7603{
7604
7605 /* We should be able to check here if the fb has the same properties
7606 * and then just flip_or_move it */
7607 if (set->crtc->fb != set->fb) {
7608 /* If we have no fb then treat it as a full mode set */
7609 if (set->crtc->fb == NULL) {
7610 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7611 config->mode_changed = true;
7612 } else if (set->fb == NULL) {
7613 config->mode_changed = true;
7614 } else if (set->fb->depth != set->crtc->fb->depth) {
7615 config->mode_changed = true;
7616 } else if (set->fb->bits_per_pixel !=
7617 set->crtc->fb->bits_per_pixel) {
7618 config->mode_changed = true;
7619 } else
7620 config->fb_changed = true;
7621 }
7622
835c5873 7623 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7624 config->fb_changed = true;
7625
7626 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7627 DRM_DEBUG_KMS("modes are different, full mode set\n");
7628 drm_mode_debug_printmodeline(&set->crtc->mode);
7629 drm_mode_debug_printmodeline(set->mode);
7630 config->mode_changed = true;
7631 }
7632}
7633
2e431051 7634static int
9a935856
DV		 7635intel_modeset_stage_output_state(struct drm_device *dev,
7636 struct drm_mode_set *set,
7637 struct intel_set_config *config)
50f56119 7638{
85f9eb71 7639 struct drm_crtc *new_crtc;
9a935856
DV		 7640 struct intel_connector *connector;
7641 struct intel_encoder *encoder;
2e431051 7642 int count, ro;
50f56119 7643
9a935856
DV		 7644 /* The upper layers ensure that we either disabl a crtc or have a list
7645 * of connectors. For paranoia, double-check this. */
7646 WARN_ON(!set->fb && (set->num_connectors != 0));
7647 WARN_ON(set->fb && (set->num_connectors == 0));
7648
50f56119 7649 count = 0;
9a935856
DV		 7650 list_for_each_entry(connector, &dev->mode_config.connector_list,
7651 base.head) {
7652 /* Otherwise traverse passed in connector list and get encoders
7653 * for them. */
50f56119 7654 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7655 if (set->connectors[ro] == &connector->base) {
7656 connector->new_encoder = connector->encoder;
50f56119
DV		 7657 break;
7658 }
7659 }
7660
9a935856
DV		 7661 /* If we disable the crtc, disable all its connectors. Also, if
7662 * the connector is on the changing crtc but not on the new
7663 * connector list, disable it. */
7664 if ((!set->fb || ro == set->num_connectors) &&
7665 connector->base.encoder &&
7666 connector->base.encoder->crtc == set->crtc) {
7667 connector->new_encoder = NULL;
7668
7669 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7670 connector->base.base.id,
7671 drm_get_connector_name(&connector->base));
7672 }
7673
7674
7675 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7676 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7677 config->mode_changed = true;
50f56119 7678 }
9a935856
DV		 7679
7680 /* Disable all disconnected encoders. */
7681 if (connector->base.status == connector_status_disconnected)
7682 connector->new_encoder = NULL;
50f56119 7683 }
9a935856 7684 /* connector->new_encoder is now updated for all connectors. */
50f56119 7685
9a935856 7686 /* Update crtc of enabled connectors. */
50f56119 7687 count = 0;
9a935856
DV		 7688 list_for_each_entry(connector, &dev->mode_config.connector_list,
7689 base.head) {
7690 if (!connector->new_encoder)
50f56119
DV		 7691 continue;
7692
9a935856 7693 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7694
7695 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7696 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7697 new_crtc = set->crtc;
7698 }
7699
7700 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7701 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7702 new_crtc)) {
5e2b584e 7703 return -EINVAL;
50f56119 7704 }
9a935856
DV		 7705 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7706
7707 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7708 connector->base.base.id,
7709 drm_get_connector_name(&connector->base),
7710 new_crtc->base.id);
7711 }
7712
7713 /* Check for any encoders that needs to be disabled. */
7714 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7715 base.head) {
7716 list_for_each_entry(connector,
7717 &dev->mode_config.connector_list,
7718 base.head) {
7719 if (connector->new_encoder == encoder) {
7720 WARN_ON(!connector->new_encoder->new_crtc);
7721
7722 goto next_encoder;
7723 }
7724 }
7725 encoder->new_crtc = NULL;
7726next_encoder:
7727 /* Only now check for crtc changes so we don't miss encoders
7728 * that will be disabled. */
7729 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7730 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7731 config->mode_changed = true;
50f56119
DV		 7732 }
7733 }
9a935856 7734 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7735
2e431051
DV		 7736 return 0;
7737}
7738
7739static int intel_crtc_set_config(struct drm_mode_set *set)
7740{
7741 struct drm_device *dev;
2e431051
DV		 7742 struct drm_mode_set save_set;
7743 struct intel_set_config *config;
7744 int ret;
2e431051 7745
8d3e375e
DV		 7746 BUG_ON(!set);
7747 BUG_ON(!set->crtc);
7748 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7749
7750 if (!set->mode)
7751 set->fb = NULL;
7752
431e50f7
DV		 7753 /* The fb helper likes to play gross jokes with ->mode_set_config.
7754 * Unfortunately the crtc helper doesn't do much at all for this case,
7755 * so we have to cope with this madness until the fb helper is fixed up. */
7756 if (set->fb && set->num_connectors == 0)
7757 return 0;
7758
2e431051
DV		 7759 if (set->fb) {
7760 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7761 set->crtc->base.id, set->fb->base.id,
7762 (int)set->num_connectors, set->x, set->y);
7763 } else {
7764 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7765 }
7766
7767 dev = set->crtc->dev;
7768
7769 ret = -ENOMEM;
7770 config = kzalloc(sizeof(*config), GFP_KERNEL);
7771 if (!config)
7772 goto out_config;
7773
7774 ret = intel_set_config_save_state(dev, config);
7775 if (ret)
7776 goto out_config;
7777
7778 save_set.crtc = set->crtc;
7779 save_set.mode = &set->crtc->mode;
7780 save_set.x = set->crtc->x;
7781 save_set.y = set->crtc->y;
7782 save_set.fb = set->crtc->fb;
7783
7784 /* Compute whether we need a full modeset, only an fb base update or no
7785 * change at all. In the future we might also check whether only the
7786 * mode changed, e.g. for LVDS where we only change the panel fitter in
7787 * such cases. */
7788 intel_set_config_compute_mode_changes(set, config);
7789
9a935856 7790 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7791 if (ret)
7792 goto fail;
7793
5e2b584e 7794 if (config->mode_changed) {
87f1faa6 7795 if (set->mode) {
50f56119
DV		 7796 DRM_DEBUG_KMS("attempting to set mode from"
7797 " userspace\n");
7798 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7799 }
7800
7801 if (!intel_set_mode(set->crtc, set->mode,
7802 set->x, set->y, set->fb)) {
7803 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7804 set->crtc->base.id);
7805 ret = -EINVAL;
7806 goto fail;
7807 }
5e2b584e 7808 } else if (config->fb_changed) {
4f660f49 7809 ret = intel_pipe_set_base(set->crtc,
94352cf9 7810 set->x, set->y, set->fb);
50f56119
DV		 7811 }
7812
d9e55608
DV		 7813 intel_set_config_free(config);
7814
50f56119
DV		 7815 return 0;
7816
7817fail:
85f9eb71 7818 intel_set_config_restore_state(dev, config);
50f56119
DV		 7819
7820 /* Try to restore the config */
5e2b584e 7821 if (config->mode_changed &&
a6778b3c
DV		 7822 !intel_set_mode(save_set.crtc, save_set.mode,
7823 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7824 DRM_ERROR("failed to restore config after modeset failure\n");
7825
d9e55608
DV		 7826out_config:
7827 intel_set_config_free(config);
50f56119
DV		 7828 return ret;
7829}
f6e5b160
CW		 7830
7831static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7832 .cursor_set = intel_crtc_cursor_set,
7833 .cursor_move = intel_crtc_cursor_move,
7834 .gamma_set = intel_crtc_gamma_set,
50f56119 7835 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7836 .destroy = intel_crtc_destroy,
7837 .page_flip = intel_crtc_page_flip,
7838};
7839
79f689aa
PZ		 7840static void intel_cpu_pll_init(struct drm_device *dev)
7841{
affa9354 7842 if (HAS_DDI(dev))
79f689aa
PZ		 7843 intel_ddi_pll_init(dev);
7844}
7845
ee7b9f93
JB		 7846static void intel_pch_pll_init(struct drm_device *dev)
7847{
7848 drm_i915_private_t *dev_priv = dev->dev_private;
7849 int i;
7850
7851 if (dev_priv->num_pch_pll == 0) {
7852 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7853 return;
7854 }
7855
7856 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7857 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7858 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7859 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7860 }
7861}
7862
b358d0a6 7863static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7864{
22fd0fab 7865 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7866 struct intel_crtc *intel_crtc;
7867 int i;
7868
7869 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7870 if (intel_crtc == NULL)
7871 return;
7872
7873 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7874
7875 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7876 for (i = 0; i < 256; i++) {
7877 intel_crtc->lut_r[i] = i;
7878 intel_crtc->lut_g[i] = i;
7879 intel_crtc->lut_b[i] = i;
7880 }
7881
80824003
JB		 7882 /* Swap pipes & planes for FBC on pre-965 */
7883 intel_crtc->pipe = pipe;
7884 intel_crtc->plane = pipe;
a5c961d1 7885 intel_crtc->cpu_transcoder = pipe;
e2e767ab 7886 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7887 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7888 intel_crtc->plane = !pipe;
80824003
JB		 7889 }
7890
22fd0fab
JB		 7891 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7892 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7893 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7894 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7895
5a354204 7896 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7897
79e53945 7898 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7899}
7900
08d7b3d1 7901int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7902 struct drm_file *file)
08d7b3d1 7903{
08d7b3d1 7904 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7905 struct drm_mode_object *drmmode_obj;
7906 struct intel_crtc *crtc;
08d7b3d1 7907
1cff8f6b
DV		 7908 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7909 return -ENODEV;
08d7b3d1 7910
c05422d5
DV		 7911 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7912 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7913
c05422d5 7914 if (!drmmode_obj) {
08d7b3d1
CW		 7915 DRM_ERROR("no such CRTC id\n");
7916 return -EINVAL;
7917 }
7918
c05422d5
DV		 7919 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7920 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7921
c05422d5 7922 return 0;
08d7b3d1
CW		 7923}
7924
66a9278e 7925static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7926{
66a9278e
DV		 7927 struct drm_device *dev = encoder->base.dev;
7928 struct intel_encoder *source_encoder;
79e53945 7929 int index_mask = 0;
79e53945
JB		 7930 int entry = 0;
7931
66a9278e
DV		 7932 list_for_each_entry(source_encoder,
7933 &dev->mode_config.encoder_list, base.head) {
7934
7935 if (encoder == source_encoder)
79e53945 7936 index_mask |= (1 << entry);
66a9278e
DV		 7937
7938 /* Intel hw has only one MUX where enocoders could be cloned. */
7939 if (encoder->cloneable && source_encoder->cloneable)
7940 index_mask |= (1 << entry);
7941
79e53945
JB		 7942 entry++;
7943 }
4ef69c7a 7944
79e53945
JB		 7945 return index_mask;
7946}
7947
4d302442
CW		 7948static bool has_edp_a(struct drm_device *dev)
7949{
7950 struct drm_i915_private *dev_priv = dev->dev_private;
7951
7952 if (!IS_MOBILE(dev))
7953 return false;
7954
7955 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7956 return false;
7957
7958 if (IS_GEN5(dev) &&
7959 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7960 return false;
7961
7962 return true;
7963}
7964
79e53945
JB		 7965static void intel_setup_outputs(struct drm_device *dev)
7966{
725e30ad 7967 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7968 struct intel_encoder *encoder;
cb0953d7 7969 bool dpd_is_edp = false;
f3cfcba6 7970 bool has_lvds;
79e53945 7971
f3cfcba6 7972 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7973 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7974 /* disable the panel fitter on everything but LVDS */
7975 I915_WRITE(PFIT_CONTROL, 0);
7976 }
79e53945 7977
affa9354 7978 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 7979 intel_crt_init(dev);
cb0953d7 7980
affa9354 7981 if (HAS_DDI(dev)) {
0e72a5b5
ED		 7982 int found;
7983
7984 /* Haswell uses DDI functions to detect digital outputs */
7985 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7986 /* DDI A only supports eDP */
7987 if (found)
7988 intel_ddi_init(dev, PORT_A);
7989
7990 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7991 * register */
7992 found = I915_READ(SFUSE_STRAP);
7993
7994 if (found & SFUSE_STRAP_DDIB_DETECTED)
7995 intel_ddi_init(dev, PORT_B);
7996 if (found & SFUSE_STRAP_DDIC_DETECTED)
7997 intel_ddi_init(dev, PORT_C);
7998 if (found & SFUSE_STRAP_DDID_DETECTED)
7999 intel_ddi_init(dev, PORT_D);
8000 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8001 int found;
270b3042
DV		 8002 dpd_is_edp = intel_dpd_is_edp(dev);
8003
8004 if (has_edp_a(dev))
8005 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8006
30ad48b7 8007 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8008 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8009 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8010 if (!found)
08d644ad 8011 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8012 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8013 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8014 }
8015
8016 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8017 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8018
b708a1d5 8019 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8020 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8021
5eb08b69 8022 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8023 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8024
270b3042 8025 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8026 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8027 } else if (IS_VALLEYVIEW(dev)) {
8028 int found;
8029
19c03924
GB		 8030 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8031 if (I915_READ(DP_C) & DP_DETECTED)
8032 intel_dp_init(dev, DP_C, PORT_C);
8033
4a87d65d
JB		 8034 if (I915_READ(SDVOB) & PORT_DETECTED) {
8035 /* SDVOB multiplex with HDMIB */
8036 found = intel_sdvo_init(dev, SDVOB, true);
8037 if (!found)
08d644ad 8038 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8039 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8040 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8041 }
8042
8043 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8044 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8045
103a196f 8046 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8047 bool found = false;
7d57382e 8048
725e30ad 8049 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8050 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8051 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8052 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8053 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8054 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8055 }
27185ae1 8056
b01f2c3a
JB		 8057 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8058 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8059 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8060 }
725e30ad 8061 }
13520b05
KH		 8062
8063 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8064
b01f2c3a
JB		 8065 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8066 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8067 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8068 }
27185ae1
ML		 8069
8070 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8071
b01f2c3a
JB		 8072 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8073 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8074 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8075 }
8076 if (SUPPORTS_INTEGRATED_DP(dev)) {
8077 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8078 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8079 }
725e30ad 8080 }
27185ae1 8081
b01f2c3a
JB		 8082 if (SUPPORTS_INTEGRATED_DP(dev) &&
8083 (I915_READ(DP_D) & DP_DETECTED)) {
8084 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8085 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8086 }
bad720ff 8087 } else if (IS_GEN2(dev))
79e53945
JB		 8088 intel_dvo_init(dev);
8089
103a196f 8090 if (SUPPORTS_TV(dev))
79e53945
JB		 8091 intel_tv_init(dev);
8092
4ef69c7a
CW		 8093 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8094 encoder->base.possible_crtcs = encoder->crtc_mask;
8095 encoder->base.possible_clones =
66a9278e 8096 intel_encoder_clones(encoder);
79e53945 8097 }
47356eb6 8098
40579abe 8099 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8100 ironlake_init_pch_refclk(dev);
270b3042
DV		 8101
8102 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8103}
8104
8105static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8106{
8107 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8108
8109 drm_framebuffer_cleanup(fb);
05394f39 8110 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8111
8112 kfree(intel_fb);
8113}
8114
8115static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8116 struct drm_file *file,
79e53945
JB		 8117 unsigned int *handle)
8118{
8119 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8120 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8121
05394f39 8122 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8123}
8124
8125static const struct drm_framebuffer_funcs intel_fb_funcs = {
8126 .destroy = intel_user_framebuffer_destroy,
8127 .create_handle = intel_user_framebuffer_create_handle,
8128};
8129
38651674
DA		 8130int intel_framebuffer_init(struct drm_device *dev,
8131 struct intel_framebuffer *intel_fb,
308e5bcb 8132 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8133 struct drm_i915_gem_object *obj)
79e53945 8134{
79e53945
JB		 8135 int ret;
8136
05394f39 8137 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8138 return -EINVAL;
8139
308e5bcb 8140 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8141 return -EINVAL;
8142
5d7bd705
VS		 8143 /* FIXME <= Gen4 stride limits are bit unclear */
8144 if (mode_cmd->pitches[0] > 32768)
8145 return -EINVAL;
8146
8147 if (obj->tiling_mode != I915_TILING_NONE &&
8148 mode_cmd->pitches[0] != obj->stride)
8149 return -EINVAL;
8150
57779d06 8151 /* Reject formats not supported by any plane early. */
308e5bcb 8152 switch (mode_cmd->pixel_format) {
57779d06 8153 case DRM_FORMAT_C8:
04b3924d
VS		 8154 case DRM_FORMAT_RGB565:
8155 case DRM_FORMAT_XRGB8888:
8156 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8157 break;
8158 case DRM_FORMAT_XRGB1555:
8159 case DRM_FORMAT_ARGB1555:
8160 if (INTEL_INFO(dev)->gen > 3)
8161 return -EINVAL;
8162 break;
8163 case DRM_FORMAT_XBGR8888:
8164 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8165 case DRM_FORMAT_XRGB2101010:
8166 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8167 case DRM_FORMAT_XBGR2101010:
8168 case DRM_FORMAT_ABGR2101010:
8169 if (INTEL_INFO(dev)->gen < 4)
8170 return -EINVAL;
b5626747 8171 break;
04b3924d
VS		 8172 case DRM_FORMAT_YUYV:
8173 case DRM_FORMAT_UYVY:
8174 case DRM_FORMAT_YVYU:
8175 case DRM_FORMAT_VYUY:
57779d06
VS		 8176 if (INTEL_INFO(dev)->gen < 6)
8177 return -EINVAL;
57cd6508
CW		 8178 break;
8179 default:
57779d06 8180 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8181 return -EINVAL;
8182 }
8183
90f9a336
VS		 8184 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8185 if (mode_cmd->offsets[0] != 0)
8186 return -EINVAL;
8187
79e53945
JB		 8188 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8189 if (ret) {
8190 DRM_ERROR("framebuffer init failed %d\n", ret);
8191 return ret;
8192 }
8193
8194 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8195 intel_fb->obj = obj;
79e53945
JB		 8196 return 0;
8197}
8198
79e53945
JB		 8199static struct drm_framebuffer *
8200intel_user_framebuffer_create(struct drm_device *dev,
8201 struct drm_file *filp,
308e5bcb 8202 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8203{
05394f39 8204 struct drm_i915_gem_object *obj;
79e53945 8205
308e5bcb
JB		 8206 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8207 mode_cmd->handles[0]));
c8725226 8208 if (&obj->base == NULL)
cce13ff7 8209 return ERR_PTR(-ENOENT);
79e53945 8210
d2dff872 8211 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8212}
8213
79e53945 8214static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8215 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8216 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8217};
8218
e70236a8
JB		 8219/* Set up chip specific display functions */
8220static void intel_init_display(struct drm_device *dev)
8221{
8222 struct drm_i915_private *dev_priv = dev->dev_private;
8223
8224 /* We always want a DPMS function */
affa9354 8225 if (HAS_DDI(dev)) {
09b4ddf9 8226 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8227 dev_priv->display.crtc_enable = haswell_crtc_enable;
8228 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8229 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8230 dev_priv->display.update_plane = ironlake_update_plane;
8231 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8232 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8233 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8234 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8235 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8236 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8237 } else {
f564048e 8238 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8239 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8240 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8241 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8242 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8243 }
e70236a8 8244
e70236a8 8245 /* Returns the core display clock speed */
25eb05fc
JB		 8246 if (IS_VALLEYVIEW(dev))
8247 dev_priv->display.get_display_clock_speed =
8248 valleyview_get_display_clock_speed;
8249 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8250 dev_priv->display.get_display_clock_speed =
8251 i945_get_display_clock_speed;
8252 else if (IS_I915G(dev))
8253 dev_priv->display.get_display_clock_speed =
8254 i915_get_display_clock_speed;
f2b115e6 8255 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8256 dev_priv->display.get_display_clock_speed =
8257 i9xx_misc_get_display_clock_speed;
8258 else if (IS_I915GM(dev))
8259 dev_priv->display.get_display_clock_speed =
8260 i915gm_get_display_clock_speed;
8261 else if (IS_I865G(dev))
8262 dev_priv->display.get_display_clock_speed =
8263 i865_get_display_clock_speed;
f0f8a9ce 8264 else if (IS_I85X(dev))
e70236a8
JB		 8265 dev_priv->display.get_display_clock_speed =
8266 i855_get_display_clock_speed;
8267 else /* 852, 830 */
8268 dev_priv->display.get_display_clock_speed =
8269 i830_get_display_clock_speed;
8270
7f8a8569 8271 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8272 if (IS_GEN5(dev)) {
674cf967 8273 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8274 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8275 } else if (IS_GEN6(dev)) {
674cf967 8276 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8277 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8278 } else if (IS_IVYBRIDGE(dev)) {
8279 /* FIXME: detect B0+ stepping and use auto training */
8280 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8281 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8282 dev_priv->display.modeset_global_resources =
8283 ivb_modeset_global_resources;
c82e4d26
ED		 8284 } else if (IS_HASWELL(dev)) {
8285 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8286 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8287 } else
8288 dev_priv->display.update_wm = NULL;
6067aaea 8289 } else if (IS_G4X(dev)) {
e0dac65e 8290 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8291 }
8c9f3aaf
JB		 8292
8293 /* Default just returns -ENODEV to indicate unsupported */
8294 dev_priv->display.queue_flip = intel_default_queue_flip;
8295
8296 switch (INTEL_INFO(dev)->gen) {
8297 case 2:
8298 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8299 break;
8300
8301 case 3:
8302 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8303 break;
8304
8305 case 4:
8306 case 5:
8307 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8308 break;
8309
8310 case 6:
8311 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8312 break;
7c9017e5
JB		 8313 case 7:
8314 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8315 break;
8c9f3aaf 8316 }
e70236a8
JB		 8317}
8318
b690e96c
JB		 8319/*
8320 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8321 * resume, or other times. This quirk makes sure that's the case for
8322 * affected systems.
8323 */
0206e353 8324static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8325{
8326 struct drm_i915_private *dev_priv = dev->dev_private;
8327
8328 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8329 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8330}
8331
435793df
KP		 8332/*
8333 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8334 */
8335static void quirk_ssc_force_disable(struct drm_device *dev)
8336{
8337 struct drm_i915_private *dev_priv = dev->dev_private;
8338 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8339 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8340}
8341
4dca20ef 8342/*
5a15ab5b
CE		 8343 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8344 * brightness value
4dca20ef
CE		 8345 */
8346static void quirk_invert_brightness(struct drm_device *dev)
8347{
8348 struct drm_i915_private *dev_priv = dev->dev_private;
8349 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8350 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8351}
8352
b690e96c
JB		 8353struct intel_quirk {
8354 int device;
8355 int subsystem_vendor;
8356 int subsystem_device;
8357 void (*hook)(struct drm_device *dev);
8358};
8359
5f85f176
EE		 8360/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8361struct intel_dmi_quirk {
8362 void (*hook)(struct drm_device *dev);
8363 const struct dmi_system_id (*dmi_id_list)[];
8364};
8365
8366static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8367{
8368 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8369 return 1;
8370}
8371
8372static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8373 {
8374 .dmi_id_list = &(const struct dmi_system_id[]) {
8375 {
8376 .callback = intel_dmi_reverse_brightness,
8377 .ident = "NCR Corporation",
8378 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8379 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8380 },
8381 },
8382 { } /* terminating entry */
8383 },
8384 .hook = quirk_invert_brightness,
8385 },
8386};
8387
c43b5634 8388static struct intel_quirk intel_quirks[] = {
b690e96c 8389 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8390 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8391
b690e96c
JB		 8392 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8393 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8394
b690e96c
JB		 8395 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8396 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8397
ccd0d36e 8398 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8399 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8400 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8401
8402 /* Lenovo U160 cannot use SSC on LVDS */
8403 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8404
8405 /* Sony Vaio Y cannot use SSC on LVDS */
8406 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8407
8408 /* Acer Aspire 5734Z must invert backlight brightness */
8409 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8410};
8411
8412static void intel_init_quirks(struct drm_device *dev)
8413{
8414 struct pci_dev *d = dev->pdev;
8415 int i;
8416
8417 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8418 struct intel_quirk *q = &intel_quirks[i];
8419
8420 if (d->device == q->device &&
8421 (d->subsystem_vendor == q->subsystem_vendor ||
8422 q->subsystem_vendor == PCI_ANY_ID) &&
8423 (d->subsystem_device == q->subsystem_device ||
8424 q->subsystem_device == PCI_ANY_ID))
8425 q->hook(dev);
8426 }
5f85f176
EE		 8427 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8428 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8429 intel_dmi_quirks[i].hook(dev);
8430 }
b690e96c
JB		 8431}
8432
9cce37f4
JB		 8433/* Disable the VGA plane that we never use */
8434static void i915_disable_vga(struct drm_device *dev)
8435{
8436 struct drm_i915_private *dev_priv = dev->dev_private;
8437 u8 sr1;
8438 u32 vga_reg;
8439
8440 if (HAS_PCH_SPLIT(dev))
8441 vga_reg = CPU_VGACNTRL;
8442 else
8443 vga_reg = VGACNTRL;
8444
8445 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8446 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8447 sr1 = inb(VGA_SR_DATA);
8448 outb(sr1 | 1<<5, VGA_SR_DATA);
8449 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8450 udelay(300);
8451
8452 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8453 POSTING_READ(vga_reg);
8454}
8455
f817586c
DV		 8456void intel_modeset_init_hw(struct drm_device *dev)
8457{
0232e927
ED		 8458 /* We attempt to init the necessary power wells early in the initialization
8459 * time, so the subsystems that expect power to be enabled can work.
8460 */
8461 intel_init_power_wells(dev);
8462
a8f78b58
ED		 8463 intel_prepare_ddi(dev);
8464
f817586c
DV		 8465 intel_init_clock_gating(dev);
8466
79f5b2c7 8467 mutex_lock(&dev->struct_mutex);
8090c6b9 8468 intel_enable_gt_powersave(dev);
79f5b2c7 8469 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8470}
8471
79e53945
JB		 8472void intel_modeset_init(struct drm_device *dev)
8473{
652c393a 8474 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8475 int i, ret;
79e53945
JB		 8476
8477 drm_mode_config_init(dev);
8478
8479 dev->mode_config.min_width = 0;
8480 dev->mode_config.min_height = 0;
8481
019d96cb
DA		 8482 dev->mode_config.preferred_depth = 24;
8483 dev->mode_config.prefer_shadow = 1;
8484
e6ecefaa 8485 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8486
b690e96c
JB		 8487 intel_init_quirks(dev);
8488
1fa61106
ED		 8489 intel_init_pm(dev);
8490
e70236a8
JB		 8491 intel_init_display(dev);
8492
a6c45cf0
CW		 8493 if (IS_GEN2(dev)) {
8494 dev->mode_config.max_width = 2048;
8495 dev->mode_config.max_height = 2048;
8496 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8497 dev->mode_config.max_width = 4096;
8498 dev->mode_config.max_height = 4096;
79e53945 8499 } else {
a6c45cf0
CW		 8500 dev->mode_config.max_width = 8192;
8501 dev->mode_config.max_height = 8192;
79e53945 8502 }
dd2757f8 8503 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8504
28c97730 8505 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8506 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8507
a3524f1b 8508 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8509 intel_crtc_init(dev, i);
00c2064b
JB		 8510 ret = intel_plane_init(dev, i);
8511 if (ret)
8512 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8513 }
8514
79f689aa 8515 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8516 intel_pch_pll_init(dev);
8517
9cce37f4
JB		 8518 /* Just disable it once at startup */
8519 i915_disable_vga(dev);
79e53945 8520 intel_setup_outputs(dev);
11be49eb
CW		 8521
8522 /* Just in case the BIOS is doing something questionable. */
8523 intel_disable_fbc(dev);
2c7111db
CW		 8524}
8525
24929352
DV		 8526static void
8527intel_connector_break_all_links(struct intel_connector *connector)
8528{
8529 connector->base.dpms = DRM_MODE_DPMS_OFF;
8530 connector->base.encoder = NULL;
8531 connector->encoder->connectors_active = false;
8532 connector->encoder->base.crtc = NULL;
8533}
8534
7fad798e
DV		 8535static void intel_enable_pipe_a(struct drm_device *dev)
8536{
8537 struct intel_connector *connector;
8538 struct drm_connector *crt = NULL;
8539 struct intel_load_detect_pipe load_detect_temp;
8540
8541 /* We can't just switch on the pipe A, we need to set things up with a
8542 * proper mode and output configuration. As a gross hack, enable pipe A
8543 * by enabling the load detect pipe once. */
8544 list_for_each_entry(connector,
8545 &dev->mode_config.connector_list,
8546 base.head) {
8547 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8548 crt = &connector->base;
8549 break;
8550 }
8551 }
8552
8553 if (!crt)
8554 return;
8555
8556 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8557 intel_release_load_detect_pipe(crt, &load_detect_temp);
8558
652c393a 8559
7fad798e
DV		 8560}
8561
fa555837
DV		 8562static bool
8563intel_check_plane_mapping(struct intel_crtc *crtc)
8564{
8565 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8566 u32 reg, val;
8567
8568 if (dev_priv->num_pipe == 1)
8569 return true;
8570
8571 reg = DSPCNTR(!crtc->plane);
8572 val = I915_READ(reg);
8573
8574 if ((val & DISPLAY_PLANE_ENABLE) &&
8575 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8576 return false;
8577
8578 return true;
8579}
8580
24929352
DV		 8581static void intel_sanitize_crtc(struct intel_crtc *crtc)
8582{
8583 struct drm_device *dev = crtc->base.dev;
8584 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8585 u32 reg;
24929352 8586
24929352 8587 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8588 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8589 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8590
8591 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8592 * disable the crtc (and hence change the state) if it is wrong. Note
8593 * that gen4+ has a fixed plane -> pipe mapping. */
8594 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8595 struct intel_connector *connector;
8596 bool plane;
8597
24929352
DV		 8598 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8599 crtc->base.base.id);
8600
8601 /* Pipe has the wrong plane attached and the plane is active.
8602 * Temporarily change the plane mapping and disable everything
8603 * ... */
8604 plane = crtc->plane;
8605 crtc->plane = !plane;
8606 dev_priv->display.crtc_disable(&crtc->base);
8607 crtc->plane = plane;
8608
8609 /* ... and break all links. */
8610 list_for_each_entry(connector, &dev->mode_config.connector_list,
8611 base.head) {
8612 if (connector->encoder->base.crtc != &crtc->base)
8613 continue;
8614
8615 intel_connector_break_all_links(connector);
8616 }
8617
8618 WARN_ON(crtc->active);
8619 crtc->base.enabled = false;
8620 }
24929352 8621
7fad798e
DV		 8622 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8623 crtc->pipe == PIPE_A && !crtc->active) {
8624 /* BIOS forgot to enable pipe A, this mostly happens after
8625 * resume. Force-enable the pipe to fix this, the update_dpms
8626 * call below we restore the pipe to the right state, but leave
8627 * the required bits on. */
8628 intel_enable_pipe_a(dev);
8629 }
8630
24929352
DV		 8631 /* Adjust the state of the output pipe according to whether we
8632 * have active connectors/encoders. */
8633 intel_crtc_update_dpms(&crtc->base);
8634
8635 if (crtc->active != crtc->base.enabled) {
8636 struct intel_encoder *encoder;
8637
8638 /* This can happen either due to bugs in the get_hw_state
8639 * functions or because the pipe is force-enabled due to the
8640 * pipe A quirk. */
8641 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8642 crtc->base.base.id,
8643 crtc->base.enabled ? "enabled" : "disabled",
8644 crtc->active ? "enabled" : "disabled");
8645
8646 crtc->base.enabled = crtc->active;
8647
8648 /* Because we only establish the connector -> encoder ->
8649 * crtc links if something is active, this means the
8650 * crtc is now deactivated. Break the links. connector
8651 * -> encoder links are only establish when things are
8652 * actually up, hence no need to break them. */
8653 WARN_ON(crtc->active);
8654
8655 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8656 WARN_ON(encoder->connectors_active);
8657 encoder->base.crtc = NULL;
8658 }
8659 }
8660}
8661
8662static void intel_sanitize_encoder(struct intel_encoder *encoder)
8663{
8664 struct intel_connector *connector;
8665 struct drm_device *dev = encoder->base.dev;
8666
8667 /* We need to check both for a crtc link (meaning that the
8668 * encoder is active and trying to read from a pipe) and the
8669 * pipe itself being active. */
8670 bool has_active_crtc = encoder->base.crtc &&
8671 to_intel_crtc(encoder->base.crtc)->active;
8672
8673 if (encoder->connectors_active && !has_active_crtc) {
8674 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8675 encoder->base.base.id,
8676 drm_get_encoder_name(&encoder->base));
8677
8678 /* Connector is active, but has no active pipe. This is
8679 * fallout from our resume register restoring. Disable
8680 * the encoder manually again. */
8681 if (encoder->base.crtc) {
8682 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8683 encoder->base.base.id,
8684 drm_get_encoder_name(&encoder->base));
8685 encoder->disable(encoder);
8686 }
8687
8688 /* Inconsistent output/port/pipe state happens presumably due to
8689 * a bug in one of the get_hw_state functions. Or someplace else
8690 * in our code, like the register restore mess on resume. Clamp
8691 * things to off as a safer default. */
8692 list_for_each_entry(connector,
8693 &dev->mode_config.connector_list,
8694 base.head) {
8695 if (connector->encoder != encoder)
8696 continue;
8697
8698 intel_connector_break_all_links(connector);
8699 }
8700 }
8701 /* Enabled encoders without active connectors will be fixed in
8702 * the crtc fixup. */
8703}
8704
8705/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8706 * and i915 state tracking structures. */
45e2b5f6
DV		 8707void intel_modeset_setup_hw_state(struct drm_device *dev,
8708 bool force_restore)
24929352
DV		 8709{
8710 struct drm_i915_private *dev_priv = dev->dev_private;
8711 enum pipe pipe;
8712 u32 tmp;
8713 struct intel_crtc *crtc;
8714 struct intel_encoder *encoder;
8715 struct intel_connector *connector;
8716
affa9354 8717 if (HAS_DDI(dev)) {
e28d54cb
PZ		 8718 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8719
8720 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8721 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8722 case TRANS_DDI_EDP_INPUT_A_ON:
8723 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8724 pipe = PIPE_A;
8725 break;
8726 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8727 pipe = PIPE_B;
8728 break;
8729 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8730 pipe = PIPE_C;
8731 break;
8732 }
8733
8734 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8735 crtc->cpu_transcoder = TRANSCODER_EDP;
8736
8737 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8738 pipe_name(pipe));
8739 }
8740 }
8741
24929352
DV		 8742 for_each_pipe(pipe) {
8743 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8744
702e7a56 8745 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8746 if (tmp & PIPECONF_ENABLE)
8747 crtc->active = true;
8748 else
8749 crtc->active = false;
8750
8751 crtc->base.enabled = crtc->active;
8752
8753 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8754 crtc->base.base.id,
8755 crtc->active ? "enabled" : "disabled");
8756 }
8757
affa9354 8758 if (HAS_DDI(dev))
6441ab5f
PZ		 8759 intel_ddi_setup_hw_pll_state(dev);
8760
24929352
DV		 8761 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8762 base.head) {
8763 pipe = 0;
8764
8765 if (encoder->get_hw_state(encoder, &pipe)) {
8766 encoder->base.crtc =
8767 dev_priv->pipe_to_crtc_mapping[pipe];
8768 } else {
8769 encoder->base.crtc = NULL;
8770 }
8771
8772 encoder->connectors_active = false;
8773 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8774 encoder->base.base.id,
8775 drm_get_encoder_name(&encoder->base),
8776 encoder->base.crtc ? "enabled" : "disabled",
8777 pipe);
8778 }
8779
8780 list_for_each_entry(connector, &dev->mode_config.connector_list,
8781 base.head) {
8782 if (connector->get_hw_state(connector)) {
8783 connector->base.dpms = DRM_MODE_DPMS_ON;
8784 connector->encoder->connectors_active = true;
8785 connector->base.encoder = &connector->encoder->base;
8786 } else {
8787 connector->base.dpms = DRM_MODE_DPMS_OFF;
8788 connector->base.encoder = NULL;
8789 }
8790 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8791 connector->base.base.id,
8792 drm_get_connector_name(&connector->base),
8793 connector->base.encoder ? "enabled" : "disabled");
8794 }
8795
8796 /* HW state is read out, now we need to sanitize this mess. */
8797 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8798 base.head) {
8799 intel_sanitize_encoder(encoder);
8800 }
8801
8802 for_each_pipe(pipe) {
8803 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8804 intel_sanitize_crtc(crtc);
8805 }
9a935856 8806
45e2b5f6
DV		 8807 if (force_restore) {
8808 for_each_pipe(pipe) {
8809 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8810 intel_set_mode(&crtc->base, &crtc->base.mode,
8811 crtc->base.x, crtc->base.y, crtc->base.fb);
8812 }
8813 } else {
8814 intel_modeset_update_staged_output_state(dev);
8815 }
8af6cf88
DV		 8816
8817 intel_modeset_check_state(dev);
2e938892
DV		 8818
8819 drm_mode_config_reset(dev);
2c7111db
CW		 8820}
8821
8822void intel_modeset_gem_init(struct drm_device *dev)
8823{
1833b134 8824 intel_modeset_init_hw(dev);
02e792fb
DV		 8825
8826 intel_setup_overlay(dev);
24929352 8827
45e2b5f6 8828 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 8829}
8830
8831void intel_modeset_cleanup(struct drm_device *dev)
8832{
652c393a
JB		 8833 struct drm_i915_private *dev_priv = dev->dev_private;
8834 struct drm_crtc *crtc;
8835 struct intel_crtc *intel_crtc;
8836
f87ea761 8837 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8838 mutex_lock(&dev->struct_mutex);
8839
723bfd70
JB		 8840 intel_unregister_dsm_handler();
8841
8842
652c393a
JB		 8843 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8844 /* Skip inactive CRTCs */
8845 if (!crtc->fb)
8846 continue;
8847
8848 intel_crtc = to_intel_crtc(crtc);
3dec0095 8849 intel_increase_pllclock(crtc);
652c393a
JB		 8850 }
8851
973d04f9 8852 intel_disable_fbc(dev);
e70236a8 8853
8090c6b9 8854 intel_disable_gt_powersave(dev);
0cdab21f 8855
930ebb46
DV		 8856 ironlake_teardown_rc6(dev);
8857
57f350b6
JB		 8858 if (IS_VALLEYVIEW(dev))
8859 vlv_init_dpio(dev);
8860
69341a5e
KH		 8861 mutex_unlock(&dev->struct_mutex);
8862
6c0d9350
DV		 8863 /* Disable the irq before mode object teardown, for the irq might
8864 * enqueue unpin/hotplug work. */
8865 drm_irq_uninstall(dev);
8866 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8867 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8868
1630fe75
CW		 8869 /* flush any delayed tasks or pending work */
8870 flush_scheduled_work();
8871
79e53945
JB		 8872 drm_mode_config_cleanup(dev);
8873}
8874
f1c79df3
ZW		 8875/*
8876 * Return which encoder is currently attached for connector.
8877 */
df0e9248 8878struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8879{
df0e9248
CW		 8880 return &intel_attached_encoder(connector)->base;
8881}
f1c79df3 8882
df0e9248
CW		 8883void intel_connector_attach_encoder(struct intel_connector *connector,
8884 struct intel_encoder *encoder)
8885{
8886 connector->encoder = encoder;
8887 drm_mode_connector_attach_encoder(&connector->base,
8888 &encoder->base);
79e53945 8889}
28d52043
DA		 8890
8891/*
8892 * set vga decode state - true == enable VGA decode
8893 */
8894int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8895{
8896 struct drm_i915_private *dev_priv = dev->dev_private;
8897 u16 gmch_ctrl;
8898
8899 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8900 if (state)
8901 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8902 else
8903 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8904 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8905 return 0;
8906}
c4a1d9e4
CW		 8907
8908#ifdef CONFIG_DEBUG_FS
8909#include <linux/seq_file.h>
8910
8911struct intel_display_error_state {
8912 struct intel_cursor_error_state {
8913 u32 control;
8914 u32 position;
8915 u32 base;
8916 u32 size;
52331309 8917 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8918
8919 struct intel_pipe_error_state {
8920 u32 conf;
8921 u32 source;
8922
8923 u32 htotal;
8924 u32 hblank;
8925 u32 hsync;
8926 u32 vtotal;
8927 u32 vblank;
8928 u32 vsync;
52331309 8929 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8930
8931 struct intel_plane_error_state {
8932 u32 control;
8933 u32 stride;
8934 u32 size;
8935 u32 pos;
8936 u32 addr;
8937 u32 surface;
8938 u32 tile_offset;
52331309 8939 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8940};
8941
8942struct intel_display_error_state *
8943intel_display_capture_error_state(struct drm_device *dev)
8944{
0206e353 8945 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 8946 struct intel_display_error_state *error;
702e7a56 8947 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 8948 int i;
8949
8950 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8951 if (error == NULL)
8952 return NULL;
8953
52331309 8954 for_each_pipe(i) {
702e7a56
PZ		 8955 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8956
c4a1d9e4
CW		 8957 error->cursor[i].control = I915_READ(CURCNTR(i));
8958 error->cursor[i].position = I915_READ(CURPOS(i));
8959 error->cursor[i].base = I915_READ(CURBASE(i));
8960
8961 error->plane[i].control = I915_READ(DSPCNTR(i));
8962 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8963 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8964 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8965 error->plane[i].addr = I915_READ(DSPADDR(i));
8966 if (INTEL_INFO(dev)->gen >= 4) {
8967 error->plane[i].surface = I915_READ(DSPSURF(i));
8968 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8969 }
8970
702e7a56 8971 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 8972 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 8973 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8974 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8975 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8976 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8977 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8978 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 8979 }
8980
8981 return error;
8982}
8983
8984void
8985intel_display_print_error_state(struct seq_file *m,
8986 struct drm_device *dev,
8987 struct intel_display_error_state *error)
8988{
52331309 8989 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8990 int i;
8991
52331309
DL		 8992 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8993 for_each_pipe(i) {
c4a1d9e4
CW		 8994 seq_printf(m, "Pipe [%d]:\n", i);
8995 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8996 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8997 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8998 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8999 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9000 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9001 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9002 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9003
9004 seq_printf(m, "Plane [%d]:\n", i);
9005 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9006 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9007 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9008 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9009 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9010 if (INTEL_INFO(dev)->gen >= 4) {
9011 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9012 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9013 }
9014
9015 seq_printf(m, "Cursor [%d]:\n", i);
9016 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9017 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9018 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9019 }
9020}
9021#endif
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