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drm/i915: drop unnecessary check from fdi_link_train code
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a 1581/**
b6b4e185 1582 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
b6b4e185 1589static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
b8a4f404
PZ		 1673static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
040484af
JB		 1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692 reg = TRANSCONF(pipe);
1693 val = I915_READ(reg);
5f7f726d 1694 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1695
1696 if (HAS_PCH_IBX(dev_priv->dev)) {
1697 /*
1698 * make the BPC in transcoder be consistent with
1699 * that in pipeconf reg.
1700 */
1701 val &= ~PIPE_BPC_MASK;
5f7f726d 1702 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1703 }
5f7f726d
PZ		 1704
1705 val &= ~TRANS_INTERLACE_MASK;
1706 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1707 if (HAS_PCH_IBX(dev_priv->dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709 val |= TRANS_LEGACY_INTERLACED_ILK;
1710 else
1711 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1712 else
1713 val |= TRANS_PROGRESSIVE;
1714
040484af
JB		 1715 I915_WRITE(reg, val | TRANS_ENABLE);
1716 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718}
1719
8fb033d7 1720static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1721 enum transcoder cpu_transcoder)
8fb033d7 1722{
8fb033d7 1723 u32 val, pipeconf_val;
8fb033d7
PZ		 1724
1725 /* PCH only available on ILK+ */
1726 BUG_ON(dev_priv->info->gen < 5);
1727
8fb033d7 1728 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1729 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1731
223a6fdf
PZ		 1732 /* Workaround: set timing override bit. */
1733 val = I915_READ(_TRANSA_CHICKEN2);
1734 val |= TRANS_AUTOTRAIN_GEN_STALL_DIS;
1735 I915_WRITE(_TRANSA_CHICKEN2, val);
1736
25f3ef11 1737 val = TRANS_ENABLE;
937bb610 1738 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1739
9a76b1c6
PZ		 1740 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1741 PIPECONF_INTERLACED_ILK)
a35f2679 1742 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1743 else
1744 val |= TRANS_PROGRESSIVE;
1745
25f3ef11 1746 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1747 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1748 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1749}
1750
b8a4f404
PZ		 1751static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1752 enum pipe pipe)
040484af
JB		 1753{
1754 int reg;
1755 u32 val;
1756
1757 /* FDI relies on the transcoder */
1758 assert_fdi_tx_disabled(dev_priv, pipe);
1759 assert_fdi_rx_disabled(dev_priv, pipe);
1760
291906f1
JB		 1761 /* Ports must be off as well */
1762 assert_pch_ports_disabled(dev_priv, pipe);
1763
040484af
JB		 1764 reg = TRANSCONF(pipe);
1765 val = I915_READ(reg);
1766 val &= ~TRANS_ENABLE;
1767 I915_WRITE(reg, val);
1768 /* wait for PCH transcoder off, transcoder state */
1769 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1770 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1771}
1772
ab4d966c 1773static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1774{
8fb033d7
PZ		 1775 u32 val;
1776
8a52fd9f 1777 val = I915_READ(_TRANSACONF);
8fb033d7 1778 val &= ~TRANS_ENABLE;
8a52fd9f 1779 I915_WRITE(_TRANSACONF, val);
8fb033d7 1780 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1781 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1782 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1783
1784 /* Workaround: clear timing override bit. */
1785 val = I915_READ(_TRANSA_CHICKEN2);
1786 val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS;
1787 I915_WRITE(_TRANSA_CHICKEN2, val);
8fb033d7
PZ		 1788}
1789
b24e7179 1790/**
309cfea8 1791 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1792 * @dev_priv: i915 private structure
1793 * @pipe: pipe to enable
040484af 1794 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1795 *
1796 * Enable @pipe, making sure that various hardware specific requirements
1797 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1798 *
1799 * @pipe should be %PIPE_A or %PIPE_B.
1800 *
1801 * Will wait until the pipe is actually running (i.e. first vblank) before
1802 * returning.
1803 */
040484af
JB		 1804static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1805 bool pch_port)
b24e7179 1806{
702e7a56
PZ		 1807 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1808 pipe);
b24e7179
JB		 1809 int reg;
1810 u32 val;
1811
1812 /*
1813 * A pipe without a PLL won't actually be able to drive bits from
1814 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1815 * need the check.
1816 */
1817 if (!HAS_PCH_SPLIT(dev_priv->dev))
1818 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1819 else {
1820 if (pch_port) {
1821 /* if driving the PCH, we need FDI enabled */
1822 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1823 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
b24e7179 1827
702e7a56 1828 reg = PIPECONF(cpu_transcoder);
b24e7179 1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
1837/**
309cfea8 1838 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851{
702e7a56
PZ		 1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
b24e7179
JB		 1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874}
1875
d74362c9
KP		 1876/*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
6f1d69b0 1880void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1881 enum plane plane)
1882{
14f86147
DL		 1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1887}
1888
b24e7179
JB		 1889/**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899{
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
00d70b15
CW		 1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1912 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914}
1915
b24e7179
JB		 1916/**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926{
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
00d70b15
CW		 1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938}
1939
127bd2ac 1940int
48b956c5 1941intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1942 struct drm_i915_gem_object *obj,
919926ae 1943 struct intel_ring_buffer *pipelined)
6b95a207 1944{
ce453d81 1945 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1946 u32 alignment;
1947 int ret;
1948
05394f39 1949 switch (obj->tiling_mode) {
6b95a207 1950 case I915_TILING_NONE:
534843da
CW		 1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
a6c45cf0 1953 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
6b95a207
KH		 1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
ce453d81 1970 dev_priv->mm.interruptible = false;
2da3b9b9 1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1972 if (ret)
ce453d81 1973 goto err_interruptible;
6b95a207
KH		 1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
06d98131 1980 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1981 if (ret)
1982 goto err_unpin;
1690e1eb 1983
9a5a53b3 1984 i915_gem_object_pin_fence(obj);
6b95a207 1985
ce453d81 1986 dev_priv->mm.interruptible = true;
6b95a207 1987 return 0;
48b956c5
CW		 1988
1989err_unpin:
1990 i915_gem_object_unpin(obj);
ce453d81
CW		 1991err_interruptible:
1992 dev_priv->mm.interruptible = true;
48b956c5 1993 return ret;
6b95a207
KH		 1994}
1995
1690e1eb
CW		 1996void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997{
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000}
2001
c2c75131
DV		 2002/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
5a35e99e
DL		 2004unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005 unsigned int bpp,
2006 unsigned int pitch)
c2c75131
DV		 2007{
2008 int tile_rows, tiles;
2009
2010 tile_rows = *y / 8;
2011 *y %= 8;
2012 tiles = *x / (512/bpp);
2013 *x %= 512/bpp;
2014
2015 return tile_rows * pitch * 8 + tiles * 4096;
2016}
2017
17638cd6
JB		 2018static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019 int x, int y)
81255565
JB		 2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
05394f39 2025 struct drm_i915_gem_object *obj;
81255565 2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
81255565 2028 u32 dspcntr;
5eddb70b 2029 u32 reg;
81255565
JB		 2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
2034 break;
2035 default:
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037 return -EINVAL;
2038 }
2039
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
81255565 2042
5eddb70b
CW		 2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
81255565
JB		 2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2047 switch (fb->pixel_format) {
2048 case DRM_FORMAT_C8:
81255565
JB		 2049 dspcntr |= DISPPLANE_8BPP;
2050 break;
57779d06
VS		 2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
81255565 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2057 break;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2073 break;
2074 default:
57779d06 2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2076 return -EINVAL;
2077 }
57779d06 2078
a6c45cf0 2079 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2080 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084 }
2085
5eddb70b 2086 I915_WRITE(reg, dspcntr);
81255565 2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2089
c2c75131
DV		 2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131
DV		 2095 linear_offset -= intel_crtc->dspaddr_offset;
2096 } else {
e506a0c6 2097 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2098 }
e506a0c6
DV		 2099
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2108 } else
e506a0c6 2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2110 POSTING_READ(reg);
81255565 2111
17638cd6
JB		 2112 return 0;
2113}
2114
2115static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117{
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
e506a0c6 2124 unsigned long linear_offset;
17638cd6
JB		 2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
27f8227b 2131 case 2:
17638cd6
JB		 2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
17638cd6
JB		 2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
57779d06
VS		 2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2151 break;
57779d06
VS		 2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2167 break;
2168 default:
57779d06 2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
e506a0c6 2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2184 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2187 fb->pitches[0]);
c2c75131 2188 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2189
e506a0c6
DV		 2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197 } else {
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200 }
17638cd6
JB		 2201 POSTING_READ(reg);
2202
2203 return 0;
2204}
2205
2206/* Assume fb object is pinned & idle & fenced and just update base pointers */
2207static int
2208intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2210{
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2213
6b8e6ed0
CW		 2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
3dec0095 2216 intel_increase_pllclock(crtc);
81255565 2217
6b8e6ed0 2218 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2219}
2220
14667a4b
CW		 2221static int
2222intel_finish_fb(struct drm_framebuffer *old_fb)
2223{
2224 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226 bool was_interruptible = dev_priv->mm.interruptible;
2227 int ret;
2228
2229 wait_event(dev_priv->pending_flip_queue,
2230 atomic_read(&dev_priv->mm.wedged) ||
2231 atomic_read(&obj->pending_flip) == 0);
2232
2233 /* Big Hammer, we also need to ensure that any pending
2234 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2235 * current scanout is retired before unpinning the old
2236 * framebuffer.
2237 *
2238 * This should only fail upon a hung GPU, in which case we
2239 * can safely continue.
2240 */
2241 dev_priv->mm.interruptible = false;
2242 ret = i915_gem_object_finish_gpu(obj);
2243 dev_priv->mm.interruptible = was_interruptible;
2244
2245 return ret;
2246}
2247
198598d0
VS		 2248static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2249{
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_master_private *master_priv;
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253
2254 if (!dev->primary->master)
2255 return;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return;
2260
2261 switch (intel_crtc->pipe) {
2262 case 0:
2263 master_priv->sarea_priv->pipeA_x = x;
2264 master_priv->sarea_priv->pipeA_y = y;
2265 break;
2266 case 1:
2267 master_priv->sarea_priv->pipeB_x = x;
2268 master_priv->sarea_priv->pipeB_y = y;
2269 break;
2270 default:
2271 break;
2272 }
2273}
2274
5c3b82e2 2275static int
3c4fdcfb 2276intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2277 struct drm_framebuffer *fb)
79e53945
JB		 2278{
2279 struct drm_device *dev = crtc->dev;
6b8e6ed0 2280 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2282 struct drm_framebuffer *old_fb;
5c3b82e2 2283 int ret;
79e53945
JB		 2284
2285 /* no fb bound */
94352cf9 2286 if (!fb) {
a5071c2f 2287 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2288 return 0;
2289 }
2290
5826eca5
ED		 2291 if(intel_crtc->plane > dev_priv->num_pipe) {
2292 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2293 intel_crtc->plane,
2294 dev_priv->num_pipe);
5c3b82e2 2295 return -EINVAL;
79e53945
JB		 2296 }
2297
5c3b82e2 2298 mutex_lock(&dev->struct_mutex);
265db958 2299 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2300 to_intel_framebuffer(fb)->obj,
919926ae 2301 NULL);
5c3b82e2
CW		 2302 if (ret != 0) {
2303 mutex_unlock(&dev->struct_mutex);
a5071c2f 2304 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2305 return ret;
2306 }
79e53945 2307
94352cf9
DV		 2308 if (crtc->fb)
2309 intel_finish_fb(crtc->fb);
265db958 2310
94352cf9 2311 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2312 if (ret) {
94352cf9 2313 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2314 mutex_unlock(&dev->struct_mutex);
a5071c2f 2315 DRM_ERROR("failed to update base address\n");
4e6cfefc 2316 return ret;
79e53945 2317 }
3c4fdcfb 2318
94352cf9
DV		 2319 old_fb = crtc->fb;
2320 crtc->fb = fb;
6c4c86f5
DV		 2321 crtc->x = x;
2322 crtc->y = y;
94352cf9 2323
b7f1de28
CW		 2324 if (old_fb) {
2325 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2326 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2327 }
652c393a 2328
6b8e6ed0 2329 intel_update_fbc(dev);
5c3b82e2 2330 mutex_unlock(&dev->struct_mutex);
79e53945 2331
198598d0 2332 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2333
2334 return 0;
79e53945
JB		 2335}
2336
5eddb70b 2337static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2338{
2339 struct drm_device *dev = crtc->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 u32 dpa_ctl;
2342
28c97730 2343 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2344 dpa_ctl = I915_READ(DP_A);
2345 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2346
2347 if (clock < 200000) {
2348 u32 temp;
2349 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2350 /* workaround for 160Mhz:
2351 1) program 0x4600c bits 15:0 = 0x8124
2352 2) program 0x46010 bit 0 = 1
2353 3) program 0x46034 bit 24 = 1
2354 4) program 0x64000 bit 14 = 1
2355 */
2356 temp = I915_READ(0x4600c);
2357 temp &= 0xffff0000;
2358 I915_WRITE(0x4600c, temp | 0x8124);
2359
2360 temp = I915_READ(0x46010);
2361 I915_WRITE(0x46010, temp | 1);
2362
2363 temp = I915_READ(0x46034);
2364 I915_WRITE(0x46034, temp | (1 << 24));
2365 } else {
2366 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2367 }
2368 I915_WRITE(DP_A, dpa_ctl);
2369
5eddb70b 2370 POSTING_READ(DP_A);
32f9d658
ZW		 2371 udelay(500);
2372}
2373
5e84e1a4
ZW		 2374static void intel_fdi_normal_train(struct drm_crtc *crtc)
2375{
2376 struct drm_device *dev = crtc->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379 int pipe = intel_crtc->pipe;
2380 u32 reg, temp;
2381
2382 /* enable normal train */
2383 reg = FDI_TX_CTL(pipe);
2384 temp = I915_READ(reg);
61e499bf 2385 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2386 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2387 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2388 } else {
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2391 }
5e84e1a4
ZW		 2392 I915_WRITE(reg, temp);
2393
2394 reg = FDI_RX_CTL(pipe);
2395 temp = I915_READ(reg);
2396 if (HAS_PCH_CPT(dev)) {
2397 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2398 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2399 } else {
2400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_NONE;
2402 }
2403 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2404
2405 /* wait one idle pattern time */
2406 POSTING_READ(reg);
2407 udelay(1000);
357555c0
JB		 2408
2409 /* IVB wants error correction enabled */
2410 if (IS_IVYBRIDGE(dev))
2411 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2412 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2413}
2414
291427f5
JB		 2415static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2416{
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 u32 flags = I915_READ(SOUTH_CHICKEN1);
2419
2420 flags |= FDI_PHASE_SYNC_OVR(pipe);
2421 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2422 flags |= FDI_PHASE_SYNC_EN(pipe);
2423 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2424 POSTING_READ(SOUTH_CHICKEN1);
2425}
2426
01a415fd
DV		 2427static void ivb_modeset_global_resources(struct drm_device *dev)
2428{
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 struct intel_crtc *pipe_B_crtc =
2431 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432 struct intel_crtc *pipe_C_crtc =
2433 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2434 uint32_t temp;
2435
2436 /* When everything is off disable fdi C so that we could enable fdi B
2437 * with all lanes. XXX: This misses the case where a pipe is not using
2438 * any pch resources and so doesn't need any fdi lanes. */
2439 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2440 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2441 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2442
2443 temp = I915_READ(SOUTH_CHICKEN1);
2444 temp &= ~FDI_BC_BIFURCATION_SELECT;
2445 DRM_DEBUG_KMS("disabling fdi C rx\n");
2446 I915_WRITE(SOUTH_CHICKEN1, temp);
2447 }
2448}
2449
8db9d77b
ZW		 2450/* The FDI link training functions for ILK/Ibexpeak. */
2451static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2452{
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
0fc932b8 2457 int plane = intel_crtc->plane;
5eddb70b 2458 u32 reg, temp, tries;
8db9d77b 2459
0fc932b8
JB		 2460 /* FDI needs bits from pipe & plane first */
2461 assert_pipe_enabled(dev_priv, pipe);
2462 assert_plane_enabled(dev_priv, plane);
2463
e1a44743
AJ		 2464 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2465 for train result */
5eddb70b
CW		 2466 reg = FDI_RX_IMR(pipe);
2467 temp = I915_READ(reg);
e1a44743
AJ		 2468 temp &= ~FDI_RX_SYMBOL_LOCK;
2469 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2470 I915_WRITE(reg, temp);
2471 I915_READ(reg);
e1a44743
AJ		 2472 udelay(150);
2473
8db9d77b 2474 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2475 reg = FDI_TX_CTL(pipe);
2476 temp = I915_READ(reg);
77ffb597
AJ		 2477 temp &= ~(7 << 19);
2478 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2479 temp &= ~FDI_LINK_TRAIN_NONE;
2480 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2481 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2482
5eddb70b
CW		 2483 reg = FDI_RX_CTL(pipe);
2484 temp = I915_READ(reg);
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2487 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2488
2489 POSTING_READ(reg);
8db9d77b
ZW		 2490 udelay(150);
2491
5b2adf89 2492 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2493 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2494 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2495 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2496
5eddb70b 2497 reg = FDI_RX_IIR(pipe);
e1a44743 2498 for (tries = 0; tries < 5; tries++) {
5eddb70b 2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2501
2502 if ((temp & FDI_RX_BIT_LOCK)) {
2503 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2504 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2505 break;
2506 }
8db9d77b 2507 }
e1a44743 2508 if (tries == 5)
5eddb70b 2509 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2510
2511 /* Train 2 */
5eddb70b
CW		 2512 reg = FDI_TX_CTL(pipe);
2513 temp = I915_READ(reg);
8db9d77b
ZW		 2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2516 I915_WRITE(reg, temp);
8db9d77b 2517
5eddb70b
CW		 2518 reg = FDI_RX_CTL(pipe);
2519 temp = I915_READ(reg);
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2522 I915_WRITE(reg, temp);
8db9d77b 2523
5eddb70b
CW		 2524 POSTING_READ(reg);
2525 udelay(150);
8db9d77b 2526
5eddb70b 2527 reg = FDI_RX_IIR(pipe);
e1a44743 2528 for (tries = 0; tries < 5; tries++) {
5eddb70b 2529 temp = I915_READ(reg);
8db9d77b
ZW		 2530 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2531
2532 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2533 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2534 DRM_DEBUG_KMS("FDI train 2 done.\n");
2535 break;
2536 }
8db9d77b 2537 }
e1a44743 2538 if (tries == 5)
5eddb70b 2539 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2540
2541 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2542
8db9d77b
ZW		 2543}
2544
0206e353 2545static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2546 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2547 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2548 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2549 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2550};
2551
2552/* The FDI link training functions for SNB/Cougarpoint. */
2553static void gen6_fdi_link_train(struct drm_crtc *crtc)
2554{
2555 struct drm_device *dev = crtc->dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558 int pipe = intel_crtc->pipe;
fa37d39e 2559 u32 reg, temp, i, retry;
8db9d77b 2560
e1a44743
AJ		 2561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562 for train result */
5eddb70b
CW		 2563 reg = FDI_RX_IMR(pipe);
2564 temp = I915_READ(reg);
e1a44743
AJ		 2565 temp &= ~FDI_RX_SYMBOL_LOCK;
2566 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
e1a44743
AJ		 2570 udelay(150);
2571
8db9d77b 2572 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2573 reg = FDI_TX_CTL(pipe);
2574 temp = I915_READ(reg);
77ffb597
AJ		 2575 temp &= ~(7 << 19);
2576 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2577 temp &= ~FDI_LINK_TRAIN_NONE;
2578 temp |= FDI_LINK_TRAIN_PATTERN_1;
2579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580 /* SNB-B */
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2582 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2583
d74cf324
DV		 2584 I915_WRITE(FDI_RX_MISC(pipe),
2585 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2586
5eddb70b
CW		 2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1;
2595 }
5eddb70b
CW		 2596 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598 POSTING_READ(reg);
8db9d77b
ZW		 2599 udelay(150);
2600
8f5718a6 2601 cpt_phase_pointer_enable(dev, pipe);
291427f5 2602
0206e353 2603 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2604 reg = FDI_TX_CTL(pipe);
2605 temp = I915_READ(reg);
8db9d77b
ZW		 2606 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
8db9d77b
ZW		 2611 udelay(500);
2612
fa37d39e
SP		 2613 for (retry = 0; retry < 5; retry++) {
2614 reg = FDI_RX_IIR(pipe);
2615 temp = I915_READ(reg);
2616 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617 if (temp & FDI_RX_BIT_LOCK) {
2618 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2619 DRM_DEBUG_KMS("FDI train 1 done.\n");
2620 break;
2621 }
2622 udelay(50);
8db9d77b 2623 }
fa37d39e
SP		 2624 if (retry < 5)
2625 break;
8db9d77b
ZW		 2626 }
2627 if (i == 4)
5eddb70b 2628 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2629
2630 /* Train 2 */
5eddb70b
CW		 2631 reg = FDI_TX_CTL(pipe);
2632 temp = I915_READ(reg);
8db9d77b
ZW		 2633 temp &= ~FDI_LINK_TRAIN_NONE;
2634 temp |= FDI_LINK_TRAIN_PATTERN_2;
2635 if (IS_GEN6(dev)) {
2636 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637 /* SNB-B */
2638 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639 }
5eddb70b 2640 I915_WRITE(reg, temp);
8db9d77b 2641
5eddb70b
CW		 2642 reg = FDI_RX_CTL(pipe);
2643 temp = I915_READ(reg);
8db9d77b
ZW		 2644 if (HAS_PCH_CPT(dev)) {
2645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647 } else {
2648 temp &= ~FDI_LINK_TRAIN_NONE;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650 }
5eddb70b
CW		 2651 I915_WRITE(reg, temp);
2652
2653 POSTING_READ(reg);
8db9d77b
ZW		 2654 udelay(150);
2655
0206e353 2656 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
8db9d77b
ZW		 2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2661 I915_WRITE(reg, temp);
2662
2663 POSTING_READ(reg);
8db9d77b
ZW		 2664 udelay(500);
2665
fa37d39e
SP		 2666 for (retry = 0; retry < 5; retry++) {
2667 reg = FDI_RX_IIR(pipe);
2668 temp = I915_READ(reg);
2669 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2670 if (temp & FDI_RX_SYMBOL_LOCK) {
2671 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2672 DRM_DEBUG_KMS("FDI train 2 done.\n");
2673 break;
2674 }
2675 udelay(50);
8db9d77b 2676 }
fa37d39e
SP		 2677 if (retry < 5)
2678 break;
8db9d77b
ZW		 2679 }
2680 if (i == 4)
5eddb70b 2681 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2682
2683 DRM_DEBUG_KMS("FDI train done.\n");
2684}
2685
357555c0
JB		 2686/* Manual link training for Ivy Bridge A0 parts */
2687static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2688{
2689 struct drm_device *dev = crtc->dev;
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692 int pipe = intel_crtc->pipe;
2693 u32 reg, temp, i;
2694
2695 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2696 for train result */
2697 reg = FDI_RX_IMR(pipe);
2698 temp = I915_READ(reg);
2699 temp &= ~FDI_RX_SYMBOL_LOCK;
2700 temp &= ~FDI_RX_BIT_LOCK;
2701 I915_WRITE(reg, temp);
2702
2703 POSTING_READ(reg);
2704 udelay(150);
2705
01a415fd
DV		 2706 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2707 I915_READ(FDI_RX_IIR(pipe)));
2708
357555c0
JB		 2709 /* enable CPU FDI TX and PCH FDI RX */
2710 reg = FDI_TX_CTL(pipe);
2711 temp = I915_READ(reg);
2712 temp &= ~(7 << 19);
2713 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2714 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2715 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2716 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2717 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2718 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2719 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2720
d74cf324
DV		 2721 I915_WRITE(FDI_RX_MISC(pipe),
2722 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2723
357555c0
JB		 2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~FDI_LINK_TRAIN_AUTO;
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2729 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2730 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2731
2732 POSTING_READ(reg);
2733 udelay(150);
2734
8f5718a6 2735 cpt_phase_pointer_enable(dev, pipe);
291427f5 2736
0206e353 2737 for (i = 0; i < 4; i++) {
357555c0
JB		 2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741 temp |= snb_b_fdi_train_param[i];
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(500);
2746
2747 reg = FDI_RX_IIR(pipe);
2748 temp = I915_READ(reg);
2749 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2750
2751 if (temp & FDI_RX_BIT_LOCK ||
2752 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2754 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2755 break;
2756 }
2757 }
2758 if (i == 4)
2759 DRM_ERROR("FDI train 1 fail!\n");
2760
2761 /* Train 2 */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774 I915_WRITE(reg, temp);
2775
2776 POSTING_READ(reg);
2777 udelay(150);
2778
0206e353 2779 for (i = 0; i < 4; i++) {
357555c0
JB		 2780 reg = FDI_TX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783 temp |= snb_b_fdi_train_param[i];
2784 I915_WRITE(reg, temp);
2785
2786 POSTING_READ(reg);
2787 udelay(500);
2788
2789 reg = FDI_RX_IIR(pipe);
2790 temp = I915_READ(reg);
2791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792
2793 if (temp & FDI_RX_SYMBOL_LOCK) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2796 break;
2797 }
2798 }
2799 if (i == 4)
2800 DRM_ERROR("FDI train 2 fail!\n");
2801
2802 DRM_DEBUG_KMS("FDI train done.\n");
2803}
2804
88cefb6c 2805static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2806{
88cefb6c 2807 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2808 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2809 int pipe = intel_crtc->pipe;
5eddb70b 2810 u32 reg, temp;
79e53945 2811
c64e311e 2812
c98e9dcf 2813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2817 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821 POSTING_READ(reg);
c98e9dcf
JB		 2822 udelay(200);
2823
2824 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828 POSTING_READ(reg);
c98e9dcf
JB		 2829 udelay(200);
2830
bf507ef7
ED		 2831 /* On Haswell, the PLL configuration for ports and pipes is handled
2832 * separately, as part of DDI setup */
2833 if (!IS_HASWELL(dev)) {
2834 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835 reg = FDI_TX_CTL(pipe);
2836 temp = I915_READ(reg);
2837 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2839
bf507ef7
ED		 2840 POSTING_READ(reg);
2841 udelay(100);
2842 }
6be4a607 2843 }
0e23b99d
JB		 2844}
2845
88cefb6c
DV		 2846static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847{
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
291427f5
JB		 2875static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2876{
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878 u32 flags = I915_READ(SOUTH_CHICKEN1);
2879
2880 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2881 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2882 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2883 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2884 POSTING_READ(SOUTH_CHICKEN1);
2885}
0fc932b8
JB		 2886static void ironlake_fdi_disable(struct drm_crtc *crtc)
2887{
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2891 int pipe = intel_crtc->pipe;
2892 u32 reg, temp;
2893
2894 /* disable CPU FDI tx and PCH FDI rx */
2895 reg = FDI_TX_CTL(pipe);
2896 temp = I915_READ(reg);
2897 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2898 POSTING_READ(reg);
2899
2900 reg = FDI_RX_CTL(pipe);
2901 temp = I915_READ(reg);
2902 temp &= ~(0x7 << 16);
2903 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2904 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2905
2906 POSTING_READ(reg);
2907 udelay(100);
2908
2909 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2910 if (HAS_PCH_IBX(dev)) {
2911 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2912 I915_WRITE(FDI_RX_CHICKEN(pipe),
2913 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2914 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2915 } else if (HAS_PCH_CPT(dev)) {
2916 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2917 }
0fc932b8
JB		 2918
2919 /* still set train pattern 1 */
2920 reg = FDI_TX_CTL(pipe);
2921 temp = I915_READ(reg);
2922 temp &= ~FDI_LINK_TRAIN_NONE;
2923 temp |= FDI_LINK_TRAIN_PATTERN_1;
2924 I915_WRITE(reg, temp);
2925
2926 reg = FDI_RX_CTL(pipe);
2927 temp = I915_READ(reg);
2928 if (HAS_PCH_CPT(dev)) {
2929 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2930 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2931 } else {
2932 temp &= ~FDI_LINK_TRAIN_NONE;
2933 temp |= FDI_LINK_TRAIN_PATTERN_1;
2934 }
2935 /* BPC in FDI rx is consistent with that in PIPECONF */
2936 temp &= ~(0x07 << 16);
2937 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2938 I915_WRITE(reg, temp);
2939
2940 POSTING_READ(reg);
2941 udelay(100);
2942}
2943
5bb61643
CW		 2944static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2945{
2946 struct drm_device *dev = crtc->dev;
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948 unsigned long flags;
2949 bool pending;
2950
2951 if (atomic_read(&dev_priv->mm.wedged))
2952 return false;
2953
2954 spin_lock_irqsave(&dev->event_lock, flags);
2955 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2956 spin_unlock_irqrestore(&dev->event_lock, flags);
2957
2958 return pending;
2959}
2960
e6c3a2a6
CW		 2961static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2962{
0f91128d 2963 struct drm_device *dev = crtc->dev;
5bb61643 2964 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2965
2966 if (crtc->fb == NULL)
2967 return;
2968
5bb61643
CW		 2969 wait_event(dev_priv->pending_flip_queue,
2970 !intel_crtc_has_pending_flip(crtc));
2971
0f91128d
CW		 2972 mutex_lock(&dev->struct_mutex);
2973 intel_finish_fb(crtc->fb);
2974 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2975}
2976
fc316cbe 2977static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2978{
2979 struct drm_device *dev = crtc->dev;
228d3e36 2980 struct intel_encoder *intel_encoder;
040484af
JB		 2981
2982 /*
2983 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2984 * must be driven by its own crtc; no sharing is possible.
2985 */
228d3e36 2986 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2987 switch (intel_encoder->type) {
040484af 2988 case INTEL_OUTPUT_EDP:
228d3e36 2989 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2990 return false;
2991 continue;
2992 }
2993 }
2994
2995 return true;
2996}
2997
fc316cbe
PZ		 2998static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999{
3000 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001}
3002
e615efe4
ED		 3003/* Program iCLKIP clock to the desired frequency */
3004static void lpt_program_iclkip(struct drm_crtc *crtc)
3005{
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009 u32 temp;
3010
3011 /* It is necessary to ungate the pixclk gate prior to programming
3012 * the divisors, and gate it back when it is done.
3013 */
3014 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3015
3016 /* Disable SSCCTL */
3017 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3018 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3019 SBI_SSCCTL_DISABLE);
3020
3021 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022 if (crtc->mode.clock == 20000) {
3023 auxdiv = 1;
3024 divsel = 0x41;
3025 phaseinc = 0x20;
3026 } else {
3027 /* The iCLK virtual clock root frequency is in MHz,
3028 * but the crtc->mode.clock in in KHz. To get the divisors,
3029 * it is necessary to divide one by another, so we
3030 * convert the virtual clock precision to KHz here for higher
3031 * precision.
3032 */
3033 u32 iclk_virtual_root_freq = 172800 * 1000;
3034 u32 iclk_pi_range = 64;
3035 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038 msb_divisor_value = desired_divisor / iclk_pi_range;
3039 pi_value = desired_divisor % iclk_pi_range;
3040
3041 auxdiv = 0;
3042 divsel = msb_divisor_value - 2;
3043 phaseinc = pi_value;
3044 }
3045
3046 /* This should not happen with any sane values */
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053 crtc->mode.clock,
3054 auxdiv,
3055 divsel,
3056 phasedir,
3057 phaseinc);
3058
3059 /* Program SSCDIVINTPHASE6 */
3060 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3061 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3067
3068 intel_sbi_write(dev_priv,
3069 SBI_SSCDIVINTPHASE6,
3070 temp);
3071
3072 /* Program SSCAUXDIV */
3073 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3074 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3076 intel_sbi_write(dev_priv,
3077 SBI_SSCAUXDIV6,
3078 temp);
3079
3080
3081 /* Enable modulator and associated divider */
3082 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3083 temp &= ~SBI_SSCCTL_DISABLE;
3084 intel_sbi_write(dev_priv,
3085 SBI_SSCCTL6,
3086 temp);
3087
3088 /* Wait for initialization time */
3089 udelay(24);
3090
3091 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3092}
3093
f67a559d
JB		 3094/*
3095 * Enable PCH resources required for PCH ports:
3096 * - PCH PLLs
3097 * - FDI training & RX/TX
3098 * - update transcoder timings
3099 * - DP transcoding bits
3100 * - transcoder
3101 */
3102static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3103{
3104 struct drm_device *dev = crtc->dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3107 int pipe = intel_crtc->pipe;
ee7b9f93 3108 u32 reg, temp;
2c07245f 3109
e7e164db
CW		 3110 assert_transcoder_disabled(dev_priv, pipe);
3111
cd986abb
DV		 3112 /* Write the TU size bits before fdi link training, so that error
3113 * detection works. */
3114 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3115 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3116
c98e9dcf 3117 /* For PCH output, training FDI link */
674cf967 3118 dev_priv->display.fdi_link_train(crtc);
2c07245f 3119
572deb37
DV		 3120 /* XXX: pch pll's can be enabled any time before we enable the PCH
3121 * transcoder, and we actually should do this to not upset any PCH
3122 * transcoder that already use the clock when we share it.
3123 *
3124 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3125 * unconditionally resets the pll - we need that to have the right LVDS
3126 * enable sequence. */
b6b4e185 3127 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3128
303b81e0 3129 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3130 u32 sel;
4b645f14 3131
c98e9dcf 3132 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3133 switch (pipe) {
3134 default:
3135 case 0:
3136 temp |= TRANSA_DPLL_ENABLE;
3137 sel = TRANSA_DPLLB_SEL;
3138 break;
3139 case 1:
3140 temp |= TRANSB_DPLL_ENABLE;
3141 sel = TRANSB_DPLLB_SEL;
3142 break;
3143 case 2:
3144 temp |= TRANSC_DPLL_ENABLE;
3145 sel = TRANSC_DPLLB_SEL;
3146 break;
d64311ab 3147 }
ee7b9f93
JB		 3148 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3149 temp |= sel;
3150 else
3151 temp &= ~sel;
c98e9dcf 3152 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3153 }
5eddb70b 3154
d9b6cb56
JB		 3155 /* set transcoder timing, panel must allow it */
3156 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3157 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3158 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3159 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3160
5eddb70b
CW		 3161 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3162 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3163 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3164 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3165
303b81e0 3166 intel_fdi_normal_train(crtc);
5e84e1a4 3167
c98e9dcf
JB		 3168 /* For PCH DP, enable TRANS_DP_CTL */
3169 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3170 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3171 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3172 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3173 reg = TRANS_DP_CTL(pipe);
3174 temp = I915_READ(reg);
3175 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3176 TRANS_DP_SYNC_MASK |
3177 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3178 temp |= (TRANS_DP_OUTPUT_ENABLE |
3179 TRANS_DP_ENH_FRAMING);
9325c9f0 3180 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3181
3182 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3183 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3184 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3185 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3186
3187 switch (intel_trans_dp_port_sel(crtc)) {
3188 case PCH_DP_B:
5eddb70b 3189 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3190 break;
3191 case PCH_DP_C:
5eddb70b 3192 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3193 break;
3194 case PCH_DP_D:
5eddb70b 3195 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3196 break;
3197 default:
e95d41e1 3198 BUG();
32f9d658 3199 }
2c07245f 3200
5eddb70b 3201 I915_WRITE(reg, temp);
6be4a607 3202 }
b52eb4dc 3203
b8a4f404 3204 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3205}
3206
1507e5bd
PZ		 3207static void lpt_pch_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 int pipe = intel_crtc->pipe;
daed2dbb 3213 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3214
daed2dbb 3215 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd
PZ		 3216
3217 /* Write the TU size bits before fdi link training, so that error
3218 * detection works. */
3219 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3220 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3221
3222 /* For PCH output, training FDI link */
3223 dev_priv->display.fdi_link_train(crtc);
3224
8c52b5e8 3225 lpt_program_iclkip(crtc);
1507e5bd 3226
0540e488 3227 /* Set transcoder timing. */
daed2dbb
PZ		 3228 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3231
daed2dbb
PZ		 3232 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3235 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3236
937bb610 3237 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
1507e5bd
PZ		 3238}
3239
ee7b9f93
JB		 3240static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241{
3242 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244 if (pll == NULL)
3245 return;
3246
3247 if (pll->refcount == 0) {
3248 WARN(1, "bad PCH PLL refcount\n");
3249 return;
3250 }
3251
3252 --pll->refcount;
3253 intel_crtc->pch_pll = NULL;
3254}
3255
3256static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257{
3258 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259 struct intel_pch_pll *pll;
3260 int i;
3261
3262 pll = intel_crtc->pch_pll;
3263 if (pll) {
3264 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265 intel_crtc->base.base.id, pll->pll_reg);
3266 goto prepare;
3267 }
3268
98b6bd99
DV		 3269 if (HAS_PCH_IBX(dev_priv->dev)) {
3270 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271 i = intel_crtc->pipe;
3272 pll = &dev_priv->pch_plls[i];
3273
3274 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275 intel_crtc->base.base.id, pll->pll_reg);
3276
3277 goto found;
3278 }
3279
ee7b9f93
JB		 3280 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281 pll = &dev_priv->pch_plls[i];
3282
3283 /* Only want to check enabled timings first */
3284 if (pll->refcount == 0)
3285 continue;
3286
3287 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288 fp == I915_READ(pll->fp0_reg)) {
3289 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290 intel_crtc->base.base.id,
3291 pll->pll_reg, pll->refcount, pll->active);
3292
3293 goto found;
3294 }
3295 }
3296
3297 /* Ok no matching timings, maybe there's a free one? */
3298 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299 pll = &dev_priv->pch_plls[i];
3300 if (pll->refcount == 0) {
3301 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302 intel_crtc->base.base.id, pll->pll_reg);
3303 goto found;
3304 }
3305 }
3306
3307 return NULL;
3308
3309found:
3310 intel_crtc->pch_pll = pll;
3311 pll->refcount++;
3312 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313prepare: /* separate function? */
3314 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3315
e04c7350
CW		 3316 /* Wait for the clocks to stabilize before rewriting the regs */
3317 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3318 POSTING_READ(pll->pll_reg);
3319 udelay(150);
e04c7350
CW		 3320
3321 I915_WRITE(pll->fp0_reg, fp);
3322 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3323 pll->on = false;
3324 return pll;
3325}
3326
d4270e57
JB		 3327void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3331 u32 temp;
3332
3333 temp = I915_READ(dslreg);
3334 udelay(500);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336 /* Without this, mode sets may fail silently on FDI */
3337 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3338 udelay(250);
3339 I915_WRITE(tc2reg, 0);
3340 if (wait_for(I915_READ(dslreg) != temp, 5))
3341 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3342 }
3343}
3344
f67a559d
JB		 3345static void ironlake_crtc_enable(struct drm_crtc *crtc)
3346{
3347 struct drm_device *dev = crtc->dev;
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3350 struct intel_encoder *encoder;
f67a559d
JB		 3351 int pipe = intel_crtc->pipe;
3352 int plane = intel_crtc->plane;
3353 u32 temp;
3354 bool is_pch_port;
3355
08a48469
DV		 3356 WARN_ON(!crtc->enabled);
3357
f67a559d
JB		 3358 if (intel_crtc->active)
3359 return;
3360
3361 intel_crtc->active = true;
3362 intel_update_watermarks(dev);
3363
3364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3365 temp = I915_READ(PCH_LVDS);
3366 if ((temp & LVDS_PORT_EN) == 0)
3367 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3368 }
3369
fc316cbe 3370 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3371
46b6f814 3372 if (is_pch_port) {
fff367c7
DV		 3373 /* Note: FDI PLL enabling _must_ be done before we enable the
3374 * cpu pipes, hence this is separate from all the other fdi/pch
3375 * enabling. */
88cefb6c 3376 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3377 } else {
3378 assert_fdi_tx_disabled(dev_priv, pipe);
3379 assert_fdi_rx_disabled(dev_priv, pipe);
3380 }
f67a559d 3381
bf49ec8c
DV		 3382 for_each_encoder_on_crtc(dev, crtc, encoder)
3383 if (encoder->pre_enable)
3384 encoder->pre_enable(encoder);
3385
f67a559d
JB		 3386 /* Enable panel fitting for LVDS */
3387 if (dev_priv->pch_pf_size &&
3388 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3389 /* Force use of hard-coded filter coefficients
3390 * as some pre-programmed values are broken,
3391 * e.g. x201.
3392 */
9db4a9c7
JB		 3393 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3394 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3395 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3396 }
3397
9c54c0dd
JB		 3398 /*
3399 * On ILK+ LUT must be loaded before the pipe is running but with
3400 * clocks enabled
3401 */
3402 intel_crtc_load_lut(crtc);
3403
f67a559d
JB		 3404 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3405 intel_enable_plane(dev_priv, plane, pipe);
3406
3407 if (is_pch_port)
3408 ironlake_pch_enable(crtc);
c98e9dcf 3409
d1ebd816 3410 mutex_lock(&dev->struct_mutex);
bed4a673 3411 intel_update_fbc(dev);
d1ebd816
BW		 3412 mutex_unlock(&dev->struct_mutex);
3413
6b383a7f 3414 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3415
fa5c73b1
DV		 3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->enable(encoder);
61b77ddd
DV		 3418
3419 if (HAS_PCH_CPT(dev))
3420 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3421
3422 /*
3423 * There seems to be a race in PCH platform hw (at least on some
3424 * outputs) where an enabled pipe still completes any pageflip right
3425 * away (as if the pipe is off) instead of waiting for vblank. As soon
3426 * as the first vblank happend, everything works as expected. Hence just
3427 * wait for one vblank before returning to avoid strange things
3428 * happening.
3429 */
3430 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3431}
3432
4f771f10
PZ		 3433static void haswell_crtc_enable(struct drm_crtc *crtc)
3434{
3435 struct drm_device *dev = crtc->dev;
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438 struct intel_encoder *encoder;
3439 int pipe = intel_crtc->pipe;
3440 int plane = intel_crtc->plane;
4f771f10
PZ		 3441 bool is_pch_port;
3442
3443 WARN_ON(!crtc->enabled);
3444
3445 if (intel_crtc->active)
3446 return;
3447
3448 intel_crtc->active = true;
3449 intel_update_watermarks(dev);
3450
fc316cbe 3451 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3452
83616634 3453 if (is_pch_port)
4f771f10 3454 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3455
3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 if (encoder->pre_enable)
3458 encoder->pre_enable(encoder);
3459
1f544388 3460 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3461
1f544388
PZ		 3462 /* Enable panel fitting for eDP */
3463 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3464 /* Force use of hard-coded filter coefficients
3465 * as some pre-programmed values are broken,
3466 * e.g. x201.
3467 */
3468 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3469 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3470 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3471 }
3472
3473 /*
3474 * On ILK+ LUT must be loaded before the pipe is running but with
3475 * clocks enabled
3476 */
3477 intel_crtc_load_lut(crtc);
3478
1f544388
PZ		 3479 intel_ddi_set_pipe_settings(crtc);
3480 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3481
3482 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3483 intel_enable_plane(dev_priv, plane, pipe);
3484
3485 if (is_pch_port)
1507e5bd 3486 lpt_pch_enable(crtc);
4f771f10
PZ		 3487
3488 mutex_lock(&dev->struct_mutex);
3489 intel_update_fbc(dev);
3490 mutex_unlock(&dev->struct_mutex);
3491
3492 intel_crtc_update_cursor(crtc, true);
3493
3494 for_each_encoder_on_crtc(dev, crtc, encoder)
3495 encoder->enable(encoder);
3496
4f771f10
PZ		 3497 /*
3498 * There seems to be a race in PCH platform hw (at least on some
3499 * outputs) where an enabled pipe still completes any pageflip right
3500 * away (as if the pipe is off) instead of waiting for vblank. As soon
3501 * as the first vblank happend, everything works as expected. Hence just
3502 * wait for one vblank before returning to avoid strange things
3503 * happening.
3504 */
3505 intel_wait_for_vblank(dev, intel_crtc->pipe);
3506}
3507
6be4a607
JB		 3508static void ironlake_crtc_disable(struct drm_crtc *crtc)
3509{
3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3513 struct intel_encoder *encoder;
6be4a607
JB		 3514 int pipe = intel_crtc->pipe;
3515 int plane = intel_crtc->plane;
5eddb70b 3516 u32 reg, temp;
b52eb4dc 3517
ef9c3aee 3518
f7abfe8b
CW		 3519 if (!intel_crtc->active)
3520 return;
3521
ea9d758d
DV		 3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 encoder->disable(encoder);
3524
e6c3a2a6 3525 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3526 drm_vblank_off(dev, pipe);
6b383a7f 3527 intel_crtc_update_cursor(crtc, false);
5eddb70b 3528
b24e7179 3529 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3530
973d04f9
CW		 3531 if (dev_priv->cfb_plane == plane)
3532 intel_disable_fbc(dev);
2c07245f 3533
b24e7179 3534 intel_disable_pipe(dev_priv, pipe);
32f9d658 3535
6be4a607 3536 /* Disable PF */
9db4a9c7
JB		 3537 I915_WRITE(PF_CTL(pipe), 0);
3538 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3539
bf49ec8c
DV		 3540 for_each_encoder_on_crtc(dev, crtc, encoder)
3541 if (encoder->post_disable)
3542 encoder->post_disable(encoder);
3543
0fc932b8 3544 ironlake_fdi_disable(crtc);
2c07245f 3545
b8a4f404 3546 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3547
6be4a607
JB		 3548 if (HAS_PCH_CPT(dev)) {
3549 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3550 reg = TRANS_DP_CTL(pipe);
3551 temp = I915_READ(reg);
3552 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3553 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3554 I915_WRITE(reg, temp);
6be4a607
JB		 3555
3556 /* disable DPLL_SEL */
3557 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3558 switch (pipe) {
3559 case 0:
d64311ab 3560 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3561 break;
3562 case 1:
6be4a607 3563 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3564 break;
3565 case 2:
4b645f14 3566 /* C shares PLL A or B */
d64311ab 3567 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3568 break;
3569 default:
3570 BUG(); /* wtf */
3571 }
6be4a607 3572 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3573 }
e3421a18 3574
6be4a607 3575 /* disable PCH DPLL */
ee7b9f93 3576 intel_disable_pch_pll(intel_crtc);
8db9d77b 3577
88cefb6c 3578 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3579
f7abfe8b 3580 intel_crtc->active = false;
6b383a7f 3581 intel_update_watermarks(dev);
d1ebd816
BW		 3582
3583 mutex_lock(&dev->struct_mutex);
6b383a7f 3584 intel_update_fbc(dev);
d1ebd816 3585 mutex_unlock(&dev->struct_mutex);
6be4a607 3586}
1b3c7a47 3587
4f771f10
PZ		 3588static void haswell_crtc_disable(struct drm_crtc *crtc)
3589{
3590 struct drm_device *dev = crtc->dev;
3591 struct drm_i915_private *dev_priv = dev->dev_private;
3592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593 struct intel_encoder *encoder;
3594 int pipe = intel_crtc->pipe;
3595 int plane = intel_crtc->plane;
ad80a810 3596 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3597 bool is_pch_port;
4f771f10
PZ		 3598
3599 if (!intel_crtc->active)
3600 return;
3601
83616634
PZ		 3602 is_pch_port = haswell_crtc_driving_pch(crtc);
3603
4f771f10
PZ		 3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 encoder->disable(encoder);
3606
3607 intel_crtc_wait_for_pending_flips(crtc);
3608 drm_vblank_off(dev, pipe);
3609 intel_crtc_update_cursor(crtc, false);
3610
3611 intel_disable_plane(dev_priv, plane, pipe);
3612
3613 if (dev_priv->cfb_plane == plane)
3614 intel_disable_fbc(dev);
3615
3616 intel_disable_pipe(dev_priv, pipe);
3617
ad80a810 3618 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3619
3620 /* Disable PF */
3621 I915_WRITE(PF_CTL(pipe), 0);
3622 I915_WRITE(PF_WIN_SZ(pipe), 0);
3623
1f544388 3624 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3625
3626 for_each_encoder_on_crtc(dev, crtc, encoder)
3627 if (encoder->post_disable)
3628 encoder->post_disable(encoder);
3629
83616634
PZ		 3630 if (is_pch_port) {
3631 ironlake_fdi_disable(crtc);
ab4d966c 3632 lpt_disable_pch_transcoder(dev_priv);
83616634
PZ		 3633 ironlake_fdi_pll_disable(intel_crtc);
3634 }
4f771f10
PZ		 3635
3636 intel_crtc->active = false;
3637 intel_update_watermarks(dev);
3638
3639 mutex_lock(&dev->struct_mutex);
3640 intel_update_fbc(dev);
3641 mutex_unlock(&dev->struct_mutex);
3642}
3643
ee7b9f93
JB		 3644static void ironlake_crtc_off(struct drm_crtc *crtc)
3645{
3646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647 intel_put_pch_pll(intel_crtc);
3648}
3649
6441ab5f
PZ		 3650static void haswell_crtc_off(struct drm_crtc *crtc)
3651{
a5c961d1
PZ		 3652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653
3654 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3655 * start using it. */
3656 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3657
6441ab5f
PZ		 3658 intel_ddi_put_crtc_pll(crtc);
3659}
3660
02e792fb
DV		 3661static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3662{
02e792fb 3663 if (!enable && intel_crtc->overlay) {
23f09ce3 3664 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3665 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3666
23f09ce3 3667 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3668 dev_priv->mm.interruptible = false;
3669 (void) intel_overlay_switch_off(intel_crtc->overlay);
3670 dev_priv->mm.interruptible = true;
23f09ce3 3671 mutex_unlock(&dev->struct_mutex);
02e792fb 3672 }
02e792fb 3673
5dcdbcb0
CW		 3674 /* Let userspace switch the overlay on again. In most cases userspace
3675 * has to recompute where to put it anyway.
3676 */
02e792fb
DV		 3677}
3678
0b8765c6 3679static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3680{
3681 struct drm_device *dev = crtc->dev;
79e53945
JB		 3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3684 struct intel_encoder *encoder;
79e53945 3685 int pipe = intel_crtc->pipe;
80824003 3686 int plane = intel_crtc->plane;
79e53945 3687
08a48469
DV		 3688 WARN_ON(!crtc->enabled);
3689
f7abfe8b
CW		 3690 if (intel_crtc->active)
3691 return;
3692
3693 intel_crtc->active = true;
6b383a7f
CW		 3694 intel_update_watermarks(dev);
3695
63d7bbe9 3696 intel_enable_pll(dev_priv, pipe);
040484af 3697 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3698 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3699
0b8765c6 3700 intel_crtc_load_lut(crtc);
bed4a673 3701 intel_update_fbc(dev);
79e53945 3702
0b8765c6
JB		 3703 /* Give the overlay scaler a chance to enable if it's on this pipe */
3704 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3705 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3706
fa5c73b1
DV		 3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 encoder->enable(encoder);
0b8765c6 3709}
79e53945 3710
0b8765c6
JB		 3711static void i9xx_crtc_disable(struct drm_crtc *crtc)
3712{
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3716 struct intel_encoder *encoder;
0b8765c6
JB		 3717 int pipe = intel_crtc->pipe;
3718 int plane = intel_crtc->plane;
b690e96c 3719
ef9c3aee 3720
f7abfe8b
CW		 3721 if (!intel_crtc->active)
3722 return;
3723
ea9d758d
DV		 3724 for_each_encoder_on_crtc(dev, crtc, encoder)
3725 encoder->disable(encoder);
3726
0b8765c6 3727 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3728 intel_crtc_wait_for_pending_flips(crtc);
3729 drm_vblank_off(dev, pipe);
0b8765c6 3730 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3731 intel_crtc_update_cursor(crtc, false);
0b8765c6 3732
973d04f9
CW		 3733 if (dev_priv->cfb_plane == plane)
3734 intel_disable_fbc(dev);
79e53945 3735
b24e7179 3736 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3737 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3738 intel_disable_pll(dev_priv, pipe);
0b8765c6 3739
f7abfe8b 3740 intel_crtc->active = false;
6b383a7f
CW		 3741 intel_update_fbc(dev);
3742 intel_update_watermarks(dev);
0b8765c6
JB		 3743}
3744
ee7b9f93
JB		 3745static void i9xx_crtc_off(struct drm_crtc *crtc)
3746{
3747}
3748
976f8a20
DV		 3749static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3750 bool enabled)
2c07245f
ZW		 3751{
3752 struct drm_device *dev = crtc->dev;
3753 struct drm_i915_master_private *master_priv;
3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3755 int pipe = intel_crtc->pipe;
79e53945
JB		 3756
3757 if (!dev->primary->master)
3758 return;
3759
3760 master_priv = dev->primary->master->driver_priv;
3761 if (!master_priv->sarea_priv)
3762 return;
3763
79e53945
JB		 3764 switch (pipe) {
3765 case 0:
3766 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3767 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3768 break;
3769 case 1:
3770 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3771 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3772 break;
3773 default:
9db4a9c7 3774 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3775 break;
3776 }
79e53945
JB		 3777}
3778
976f8a20
DV		 3779/**
3780 * Sets the power management mode of the pipe and plane.
3781 */
3782void intel_crtc_update_dpms(struct drm_crtc *crtc)
3783{
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_encoder *intel_encoder;
3787 bool enable = false;
3788
3789 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3790 enable |= intel_encoder->connectors_active;
3791
3792 if (enable)
3793 dev_priv->display.crtc_enable(crtc);
3794 else
3795 dev_priv->display.crtc_disable(crtc);
3796
3797 intel_crtc_update_sarea(crtc, enable);
3798}
3799
3800static void intel_crtc_noop(struct drm_crtc *crtc)
3801{
3802}
3803
cdd59983
CW		 3804static void intel_crtc_disable(struct drm_crtc *crtc)
3805{
cdd59983 3806 struct drm_device *dev = crtc->dev;
976f8a20 3807 struct drm_connector *connector;
ee7b9f93 3808 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3809
976f8a20
DV		 3810 /* crtc should still be enabled when we disable it. */
3811 WARN_ON(!crtc->enabled);
3812
3813 dev_priv->display.crtc_disable(crtc);
3814 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3815 dev_priv->display.off(crtc);
3816
931872fc
CW		 3817 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3818 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3819
3820 if (crtc->fb) {
3821 mutex_lock(&dev->struct_mutex);
1690e1eb 3822 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3823 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3824 crtc->fb = NULL;
3825 }
3826
3827 /* Update computed state. */
3828 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3829 if (!connector->encoder || !connector->encoder->crtc)
3830 continue;
3831
3832 if (connector->encoder->crtc != crtc)
3833 continue;
3834
3835 connector->dpms = DRM_MODE_DPMS_OFF;
3836 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3837 }
3838}
3839
a261b246 3840void intel_modeset_disable(struct drm_device *dev)
79e53945 3841{
a261b246
DV		 3842 struct drm_crtc *crtc;
3843
3844 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3845 if (crtc->enabled)
3846 intel_crtc_disable(crtc);
3847 }
79e53945
JB		 3848}
3849
1f703855 3850void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3851{
7e7d76c3
JB		 3852}
3853
ea5b213a 3854void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3855{
4ef69c7a 3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3857
ea5b213a
CW		 3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
7e7d76c3
JB		 3860}
3861
5ab432ef
DV		 3862/* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3866{
5ab432ef
DV		 3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3869
b2cabb0e 3870 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3871 } else {
3872 encoder->connectors_active = false;
3873
b2cabb0e 3874 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3875 }
79e53945
JB		 3876}
3877
0a91ca29
DV		 3878/* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
b980514c 3880static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3881{
0a91ca29
DV		 3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3886 enum pipe pipe;
3887
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3891
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3898
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3902 return;
3903
3904 crtc = encoder->base.crtc;
3905
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3910 }
79e53945
JB		 3911}
3912
5ab432ef
DV		 3913/* Even simpler default implementation, if there's really no special case to
3914 * consider. */
3915void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3916{
5ab432ef 3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3918
5ab432ef
DV		 3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
d4270e57 3922
5ab432ef
DV		 3923 if (mode == connector->dpms)
3924 return;
3925
3926 connector->dpms = mode;
3927
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3931 else
8af6cf88 3932 WARN_ON(encoder->connectors_active != false);
0a91ca29 3933
b980514c 3934 intel_modeset_check_state(connector->dev);
79e53945
JB		 3935}
3936
f0947c37
DV		 3937/* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3941{
24929352 3942 enum pipe pipe = 0;
f0947c37 3943 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3944
f0947c37 3945 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3946}
3947
79e53945 3948static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3949 const struct drm_display_mode *mode,
79e53945
JB		 3950 struct drm_display_mode *adjusted_mode)
3951{
2c07245f 3952 struct drm_device *dev = crtc->dev;
89749350 3953
bad720ff 3954 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3955 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3956 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3957 return false;
2c07245f 3958 }
89749350 3959
f9bef081
DV		 3960 /* All interlaced capable intel hw wants timings in frames. Note though
3961 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3962 * timings, so we need to be careful not to clobber these.*/
3963 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3964 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3965
44f46b42
CW		 3966 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3967 * with a hsync front porch of 0.
3968 */
3969 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3970 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3971 return false;
3972
79e53945
JB		 3973 return true;
3974}
3975
25eb05fc
JB		 3976static int valleyview_get_display_clock_speed(struct drm_device *dev)
3977{
3978 return 400000; /* FIXME */
3979}
3980
e70236a8
JB		 3981static int i945_get_display_clock_speed(struct drm_device *dev)
3982{
3983 return 400000;
3984}
79e53945 3985
e70236a8 3986static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3987{
e70236a8
JB		 3988 return 333000;
3989}
79e53945 3990
e70236a8
JB		 3991static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3992{
3993 return 200000;
3994}
79e53945 3995
e70236a8
JB		 3996static int i915gm_get_display_clock_speed(struct drm_device *dev)
3997{
3998 u16 gcfgc = 0;
79e53945 3999
e70236a8
JB		 4000 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4001
4002 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4003 return 133000;
4004 else {
4005 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4006 case GC_DISPLAY_CLOCK_333_MHZ:
4007 return 333000;
4008 default:
4009 case GC_DISPLAY_CLOCK_190_200_MHZ:
4010 return 190000;
79e53945 4011 }
e70236a8
JB		 4012 }
4013}
4014
4015static int i865_get_display_clock_speed(struct drm_device *dev)
4016{
4017 return 266000;
4018}
4019
4020static int i855_get_display_clock_speed(struct drm_device *dev)
4021{
4022 u16 hpllcc = 0;
4023 /* Assume that the hardware is in the high speed state. This
4024 * should be the default.
4025 */
4026 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4027 case GC_CLOCK_133_200:
4028 case GC_CLOCK_100_200:
4029 return 200000;
4030 case GC_CLOCK_166_250:
4031 return 250000;
4032 case GC_CLOCK_100_133:
79e53945 4033 return 133000;
e70236a8 4034 }
79e53945 4035
e70236a8
JB		 4036 /* Shouldn't happen */
4037 return 0;
4038}
79e53945 4039
e70236a8
JB		 4040static int i830_get_display_clock_speed(struct drm_device *dev)
4041{
4042 return 133000;
79e53945
JB		 4043}
4044
2c07245f
ZW		 4045struct fdi_m_n {
4046 u32 tu;
4047 u32 gmch_m;
4048 u32 gmch_n;
4049 u32 link_m;
4050 u32 link_n;
4051};
4052
4053static void
4054fdi_reduce_ratio(u32 *num, u32 *den)
4055{
4056 while (*num > 0xffffff || *den > 0xffffff) {
4057 *num >>= 1;
4058 *den >>= 1;
4059 }
4060}
4061
2c07245f 4062static void
f2b115e6
AJ		 4063ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4064 int link_clock, struct fdi_m_n *m_n)
2c07245f 4065{
2c07245f
ZW		 4066 m_n->tu = 64; /* default size */
4067
22ed1113
CW		 4068 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4069 m_n->gmch_m = bits_per_pixel * pixel_clock;
4070 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4071 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4072
22ed1113
CW		 4073 m_n->link_m = pixel_clock;
4074 m_n->link_n = link_clock;
2c07245f
ZW		 4075 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4076}
4077
a7615030
CW		 4078static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4079{
72bbe58c
KP		 4080 if (i915_panel_use_ssc >= 0)
4081 return i915_panel_use_ssc != 0;
4082 return dev_priv->lvds_use_ssc
435793df 4083 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4084}
4085
5a354204
JB		 4086/**
4087 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4088 * @crtc: CRTC structure
3b5c78a3 4089 * @mode: requested mode
5a354204
JB		 4090 *
4091 * A pipe may be connected to one or more outputs. Based on the depth of the
4092 * attached framebuffer, choose a good color depth to use on the pipe.
4093 *
4094 * If possible, match the pipe depth to the fb depth. In some cases, this
4095 * isn't ideal, because the connected output supports a lesser or restricted
4096 * set of depths. Resolve that here:
4097 * LVDS typically supports only 6bpc, so clamp down in that case
4098 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4099 * Displays may support a restricted set as well, check EDID and clamp as
4100 * appropriate.
3b5c78a3 4101 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4102 *
4103 * RETURNS:
4104 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4105 * true if they don't match).
4106 */
4107static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4108 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4109 unsigned int *pipe_bpp,
4110 struct drm_display_mode *mode)
5a354204
JB		 4111{
4112 struct drm_device *dev = crtc->dev;
4113 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4114 struct drm_connector *connector;
6c2b7c12 4115 struct intel_encoder *intel_encoder;
5a354204
JB		 4116 unsigned int display_bpc = UINT_MAX, bpc;
4117
4118 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4119 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4120
4121 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4122 unsigned int lvds_bpc;
4123
4124 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4125 LVDS_A3_POWER_UP)
4126 lvds_bpc = 8;
4127 else
4128 lvds_bpc = 6;
4129
4130 if (lvds_bpc < display_bpc) {
82820490 4131 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4132 display_bpc = lvds_bpc;
4133 }
4134 continue;
4135 }
4136
5a354204
JB		 4137 /* Not one of the known troublemakers, check the EDID */
4138 list_for_each_entry(connector, &dev->mode_config.connector_list,
4139 head) {
6c2b7c12 4140 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4141 continue;
4142
62ac41a6
JB		 4143 /* Don't use an invalid EDID bpc value */
4144 if (connector->display_info.bpc &&
4145 connector->display_info.bpc < display_bpc) {
82820490 4146 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4147 display_bpc = connector->display_info.bpc;
4148 }
4149 }
4150
4151 /*
4152 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4153 * through, clamp it down. (Note: >12bpc will be caught below.)
4154 */
4155 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4156 if (display_bpc > 8 && display_bpc < 12) {
82820490 4157 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4158 display_bpc = 12;
4159 } else {
82820490 4160 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4161 display_bpc = 8;
4162 }
4163 }
4164 }
4165
3b5c78a3
AJ		 4166 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4167 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4168 display_bpc = 6;
4169 }
4170
5a354204
JB		 4171 /*
4172 * We could just drive the pipe at the highest bpc all the time and
4173 * enable dithering as needed, but that costs bandwidth. So choose
4174 * the minimum value that expresses the full color range of the fb but
4175 * also stays within the max display bpc discovered above.
4176 */
4177
94352cf9 4178 switch (fb->depth) {
5a354204
JB		 4179 case 8:
4180 bpc = 8; /* since we go through a colormap */
4181 break;
4182 case 15:
4183 case 16:
4184 bpc = 6; /* min is 18bpp */
4185 break;
4186 case 24:
578393cd 4187 bpc = 8;
5a354204
JB		 4188 break;
4189 case 30:
578393cd 4190 bpc = 10;
5a354204
JB		 4191 break;
4192 case 48:
578393cd 4193 bpc = 12;
5a354204
JB		 4194 break;
4195 default:
4196 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4197 bpc = min((unsigned int)8, display_bpc);
4198 break;
4199 }
4200
578393cd
KP		 4201 display_bpc = min(display_bpc, bpc);
4202
82820490
AJ		 4203 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4204 bpc, display_bpc);
5a354204 4205
578393cd 4206 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4207
4208 return display_bpc != bpc;
4209}
4210
a0c4da24
JB		 4211static int vlv_get_refclk(struct drm_crtc *crtc)
4212{
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 int refclk = 27000; /* for DP & HDMI */
4216
4217 return 100000; /* only one validated so far */
4218
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4220 refclk = 96000;
4221 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4222 if (intel_panel_use_ssc(dev_priv))
4223 refclk = 100000;
4224 else
4225 refclk = 96000;
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4227 refclk = 100000;
4228 }
4229
4230 return refclk;
4231}
4232
c65d77d8
JB		 4233static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4234{
4235 struct drm_device *dev = crtc->dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 int refclk;
4238
a0c4da24
JB		 4239 if (IS_VALLEYVIEW(dev)) {
4240 refclk = vlv_get_refclk(crtc);
4241 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4242 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4243 refclk = dev_priv->lvds_ssc_freq * 1000;
4244 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4245 refclk / 1000);
4246 } else if (!IS_GEN2(dev)) {
4247 refclk = 96000;
4248 } else {
4249 refclk = 48000;
4250 }
4251
4252 return refclk;
4253}
4254
4255static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4256 intel_clock_t *clock)
4257{
4258 /* SDVO TV has fixed PLL values depend on its clock range,
4259 this mirrors vbios setting. */
4260 if (adjusted_mode->clock >= 100000
4261 && adjusted_mode->clock < 140500) {
4262 clock->p1 = 2;
4263 clock->p2 = 10;
4264 clock->n = 3;
4265 clock->m1 = 16;
4266 clock->m2 = 8;
4267 } else if (adjusted_mode->clock >= 140500
4268 && adjusted_mode->clock <= 200000) {
4269 clock->p1 = 1;
4270 clock->p2 = 10;
4271 clock->n = 6;
4272 clock->m1 = 12;
4273 clock->m2 = 8;
4274 }
4275}
4276
a7516a05
JB		 4277static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4278 intel_clock_t *clock,
4279 intel_clock_t *reduced_clock)
4280{
4281 struct drm_device *dev = crtc->dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284 int pipe = intel_crtc->pipe;
4285 u32 fp, fp2 = 0;
4286
4287 if (IS_PINEVIEW(dev)) {
4288 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4289 if (reduced_clock)
4290 fp2 = (1 << reduced_clock->n) << 16 |
4291 reduced_clock->m1 << 8 | reduced_clock->m2;
4292 } else {
4293 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4294 if (reduced_clock)
4295 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4296 reduced_clock->m2;
4297 }
4298
4299 I915_WRITE(FP0(pipe), fp);
4300
4301 intel_crtc->lowfreq_avail = false;
4302 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4303 reduced_clock && i915_powersave) {
4304 I915_WRITE(FP1(pipe), fp2);
4305 intel_crtc->lowfreq_avail = true;
4306 } else {
4307 I915_WRITE(FP1(pipe), fp);
4308 }
4309}
4310
93e537a1
DV		 4311static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4312 struct drm_display_mode *adjusted_mode)
4313{
4314 struct drm_device *dev = crtc->dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 int pipe = intel_crtc->pipe;
284d5df5 4318 u32 temp;
93e537a1
DV		 4319
4320 temp = I915_READ(LVDS);
4321 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4322 if (pipe == 1) {
4323 temp |= LVDS_PIPEB_SELECT;
4324 } else {
4325 temp &= ~LVDS_PIPEB_SELECT;
4326 }
4327 /* set the corresponsding LVDS_BORDER bit */
4328 temp |= dev_priv->lvds_border_bits;
4329 /* Set the B0-B3 data pairs corresponding to whether we're going to
4330 * set the DPLLs for dual-channel mode or not.
4331 */
4332 if (clock->p2 == 7)
4333 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4334 else
4335 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4336
4337 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4338 * appropriately here, but we need to look more thoroughly into how
4339 * panels behave in the two modes.
4340 */
4341 /* set the dithering flag on LVDS as needed */
4342 if (INTEL_INFO(dev)->gen >= 4) {
4343 if (dev_priv->lvds_dither)
4344 temp |= LVDS_ENABLE_DITHER;
4345 else
4346 temp &= ~LVDS_ENABLE_DITHER;
4347 }
284d5df5 4348 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4349 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4350 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4351 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4352 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4353 I915_WRITE(LVDS, temp);
4354}
4355
a0c4da24
JB		 4356static void vlv_update_pll(struct drm_crtc *crtc,
4357 struct drm_display_mode *mode,
4358 struct drm_display_mode *adjusted_mode,
4359 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4360 int num_connectors)
a0c4da24
JB		 4361{
4362 struct drm_device *dev = crtc->dev;
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365 int pipe = intel_crtc->pipe;
4366 u32 dpll, mdiv, pdiv;
4367 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4368 bool is_sdvo;
4369 u32 temp;
4370
4371 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4372 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4373
2a8f64ca
VP		 4374 dpll = DPLL_VGA_MODE_DIS;
4375 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4376 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4377 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4378
4379 I915_WRITE(DPLL(pipe), dpll);
4380 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4381
4382 bestn = clock->n;
4383 bestm1 = clock->m1;
4384 bestm2 = clock->m2;
4385 bestp1 = clock->p1;
4386 bestp2 = clock->p2;
4387
2a8f64ca
VP		 4388 /*
4389 * In Valleyview PLL and program lane counter registers are exposed
4390 * through DPIO interface
4391 */
a0c4da24
JB		 4392 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4393 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4394 mdiv |= ((bestn << DPIO_N_SHIFT));
4395 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4396 mdiv |= (1 << DPIO_K_SHIFT);
4397 mdiv |= DPIO_ENABLE_CALIBRATION;
4398 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4399
4400 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4401
2a8f64ca 4402 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4403 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4404 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4405 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4406 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4407
2a8f64ca 4408 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4409
4410 dpll |= DPLL_VCO_ENABLE;
4411 I915_WRITE(DPLL(pipe), dpll);
4412 POSTING_READ(DPLL(pipe));
4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4414 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4415
2a8f64ca
VP		 4416 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4417
4418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4419 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4420
4421 I915_WRITE(DPLL(pipe), dpll);
4422
4423 /* Wait for the clocks to stabilize. */
4424 POSTING_READ(DPLL(pipe));
4425 udelay(150);
a0c4da24 4426
2a8f64ca
VP		 4427 temp = 0;
4428 if (is_sdvo) {
4429 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4430 if (temp > 1)
4431 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4432 else
4433 temp = 0;
a0c4da24 4434 }
2a8f64ca
VP		 4435 I915_WRITE(DPLL_MD(pipe), temp);
4436 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4437
2a8f64ca
VP		 4438 /* Now program lane control registers */
4439 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4440 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4441 {
4442 temp = 0x1000C4;
4443 if(pipe == 1)
4444 temp |= (1 << 21);
4445 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4446 }
4447 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4448 {
4449 temp = 0x1000C4;
4450 if(pipe == 1)
4451 temp |= (1 << 21);
4452 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4453 }
a0c4da24
JB		 4454}
4455
eb1cbe48
DV		 4456static void i9xx_update_pll(struct drm_crtc *crtc,
4457 struct drm_display_mode *mode,
4458 struct drm_display_mode *adjusted_mode,
4459 intel_clock_t *clock, intel_clock_t *reduced_clock,
4460 int num_connectors)
4461{
4462 struct drm_device *dev = crtc->dev;
4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465 int pipe = intel_crtc->pipe;
4466 u32 dpll;
4467 bool is_sdvo;
4468
2a8f64ca
VP		 4469 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4470
eb1cbe48
DV		 4471 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4472 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4473
4474 dpll = DPLL_VGA_MODE_DIS;
4475
4476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4477 dpll |= DPLLB_MODE_LVDS;
4478 else
4479 dpll |= DPLLB_MODE_DAC_SERIAL;
4480 if (is_sdvo) {
4481 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4482 if (pixel_multiplier > 1) {
4483 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4484 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4485 }
4486 dpll |= DPLL_DVO_HIGH_SPEED;
4487 }
4488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4490
4491 /* compute bitmask from p1 value */
4492 if (IS_PINEVIEW(dev))
4493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4494 else {
4495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4496 if (IS_G4X(dev) && reduced_clock)
4497 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4498 }
4499 switch (clock->p2) {
4500 case 5:
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4502 break;
4503 case 7:
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4505 break;
4506 case 10:
4507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4508 break;
4509 case 14:
4510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4511 break;
4512 }
4513 if (INTEL_INFO(dev)->gen >= 4)
4514 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4515
4516 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4517 dpll |= PLL_REF_INPUT_TVCLKINBC;
4518 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519 /* XXX: just matching BIOS for now */
4520 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4521 dpll |= 3;
4522 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4523 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4524 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4525 else
4526 dpll |= PLL_REF_INPUT_DREFCLK;
4527
4528 dpll |= DPLL_VCO_ENABLE;
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530 POSTING_READ(DPLL(pipe));
4531 udelay(150);
4532
4533 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4534 * This is an exception to the general rule that mode_set doesn't turn
4535 * things on.
4536 */
4537 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4538 intel_update_lvds(crtc, clock, adjusted_mode);
4539
4540 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4541 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4542
4543 I915_WRITE(DPLL(pipe), dpll);
4544
4545 /* Wait for the clocks to stabilize. */
4546 POSTING_READ(DPLL(pipe));
4547 udelay(150);
4548
4549 if (INTEL_INFO(dev)->gen >= 4) {
4550 u32 temp = 0;
4551 if (is_sdvo) {
4552 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4553 if (temp > 1)
4554 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4555 else
4556 temp = 0;
4557 }
4558 I915_WRITE(DPLL_MD(pipe), temp);
4559 } else {
4560 /* The pixel multiplier can only be updated once the
4561 * DPLL is enabled and the clocks are stable.
4562 *
4563 * So write it again.
4564 */
4565 I915_WRITE(DPLL(pipe), dpll);
4566 }
4567}
4568
4569static void i8xx_update_pll(struct drm_crtc *crtc,
4570 struct drm_display_mode *adjusted_mode,
2a8f64ca 4571 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4572 int num_connectors)
4573{
4574 struct drm_device *dev = crtc->dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
4578 u32 dpll;
4579
2a8f64ca
VP		 4580 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4581
eb1cbe48
DV		 4582 dpll = DPLL_VGA_MODE_DIS;
4583
4584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4586 } else {
4587 if (clock->p1 == 2)
4588 dpll |= PLL_P1_DIVIDE_BY_TWO;
4589 else
4590 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591 if (clock->p2 == 4)
4592 dpll |= PLL_P2_DIVIDE_BY_4;
4593 }
4594
4595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4596 /* XXX: just matching BIOS for now */
4597 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4598 dpll |= 3;
4599 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4600 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4602 else
4603 dpll |= PLL_REF_INPUT_DREFCLK;
4604
4605 dpll |= DPLL_VCO_ENABLE;
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4607 POSTING_READ(DPLL(pipe));
4608 udelay(150);
4609
eb1cbe48
DV		 4610 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4611 * This is an exception to the general rule that mode_set doesn't turn
4612 * things on.
4613 */
4614 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4615 intel_update_lvds(crtc, clock, adjusted_mode);
4616
5b5896e4
DV		 4617 I915_WRITE(DPLL(pipe), dpll);
4618
4619 /* Wait for the clocks to stabilize. */
4620 POSTING_READ(DPLL(pipe));
4621 udelay(150);
4622
eb1cbe48
DV		 4623 /* The pixel multiplier can only be updated once the
4624 * DPLL is enabled and the clocks are stable.
4625 *
4626 * So write it again.
4627 */
4628 I915_WRITE(DPLL(pipe), dpll);
4629}
4630
b0e77b9c
PZ		 4631static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4632 struct drm_display_mode *mode,
4633 struct drm_display_mode *adjusted_mode)
4634{
4635 struct drm_device *dev = intel_crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4638 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4639 uint32_t vsyncshift;
4640
4641 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4642 /* the chip adds 2 halflines automatically */
4643 adjusted_mode->crtc_vtotal -= 1;
4644 adjusted_mode->crtc_vblank_end -= 1;
4645 vsyncshift = adjusted_mode->crtc_hsync_start
4646 - adjusted_mode->crtc_htotal / 2;
4647 } else {
4648 vsyncshift = 0;
4649 }
4650
4651 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4652 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4653
fe2b8f9d 4654 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4655 (adjusted_mode->crtc_hdisplay - 1) |
4656 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4657 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4658 (adjusted_mode->crtc_hblank_start - 1) |
4659 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4660 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4661 (adjusted_mode->crtc_hsync_start - 1) |
4662 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4663
fe2b8f9d 4664 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4665 (adjusted_mode->crtc_vdisplay - 1) |
4666 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4667 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4668 (adjusted_mode->crtc_vblank_start - 1) |
4669 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4670 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4671 (adjusted_mode->crtc_vsync_start - 1) |
4672 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4673
b5e508d4
PZ		 4674 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4675 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4676 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4677 * bits. */
4678 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4679 (pipe == PIPE_B || pipe == PIPE_C))
4680 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4681
b0e77b9c
PZ		 4682 /* pipesrc controls the size that is scaled from, which should
4683 * always be the user's requested size.
4684 */
4685 I915_WRITE(PIPESRC(pipe),
4686 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4687}
4688
f564048e
EA		 4689static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4690 struct drm_display_mode *mode,
4691 struct drm_display_mode *adjusted_mode,
4692 int x, int y,
94352cf9 4693 struct drm_framebuffer *fb)
79e53945
JB		 4694{
4695 struct drm_device *dev = crtc->dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
80824003 4699 int plane = intel_crtc->plane;
c751ce4f 4700 int refclk, num_connectors = 0;
652c393a 4701 intel_clock_t clock, reduced_clock;
b0e77b9c 4702 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4703 bool ok, has_reduced_clock = false, is_sdvo = false;
4704 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4705 struct intel_encoder *encoder;
d4906093 4706 const intel_limit_t *limit;
5c3b82e2 4707 int ret;
79e53945 4708
6c2b7c12 4709 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4710 switch (encoder->type) {
79e53945
JB		 4711 case INTEL_OUTPUT_LVDS:
4712 is_lvds = true;
4713 break;
4714 case INTEL_OUTPUT_SDVO:
7d57382e 4715 case INTEL_OUTPUT_HDMI:
79e53945 4716 is_sdvo = true;
5eddb70b 4717 if (encoder->needs_tv_clock)
e2f0ba97 4718 is_tv = true;
79e53945 4719 break;
79e53945
JB		 4720 case INTEL_OUTPUT_TVOUT:
4721 is_tv = true;
4722 break;
a4fc5ed6
KP		 4723 case INTEL_OUTPUT_DISPLAYPORT:
4724 is_dp = true;
4725 break;
79e53945 4726 }
43565a06 4727
c751ce4f 4728 num_connectors++;
79e53945
JB		 4729 }
4730
c65d77d8 4731 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4732
d4906093
ML		 4733 /*
4734 * Returns a set of divisors for the desired target clock with the given
4735 * refclk, or FALSE. The returned values represent the clock equation:
4736 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4737 */
1b894b59 4738 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4739 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4740 &clock);
79e53945
JB		 4741 if (!ok) {
4742 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4743 return -EINVAL;
79e53945
JB		 4744 }
4745
cda4b7d3 4746 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4747 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4748
ddc9003c 4749 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4750 /*
4751 * Ensure we match the reduced clock's P to the target clock.
4752 * If the clocks don't match, we can't switch the display clock
4753 * by using the FP0/FP1. In such case we will disable the LVDS
4754 * downclock feature.
4755 */
ddc9003c 4756 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4757 dev_priv->lvds_downclock,
4758 refclk,
cec2f356 4759 &clock,
5eddb70b 4760 &reduced_clock);
7026d4ac
ZW		 4761 }
4762
c65d77d8
JB		 4763 if (is_sdvo && is_tv)
4764 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4765
eb1cbe48 4766 if (IS_GEN2(dev))
2a8f64ca
VP		 4767 i8xx_update_pll(crtc, adjusted_mode, &clock,
4768 has_reduced_clock ? &reduced_clock : NULL,
4769 num_connectors);
a0c4da24 4770 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4771 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4772 has_reduced_clock ? &reduced_clock : NULL,
4773 num_connectors);
79e53945 4774 else
eb1cbe48
DV		 4775 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4776 has_reduced_clock ? &reduced_clock : NULL,
4777 num_connectors);
79e53945
JB		 4778
4779 /* setup pipeconf */
5eddb70b 4780 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4781
4782 /* Set up the display plane register */
4783 dspcntr = DISPPLANE_GAMMA_ENABLE;
4784
929c77fb
EA		 4785 if (pipe == 0)
4786 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4787 else
4788 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4789
a6c45cf0 4790 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4791 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4792 * core speed.
4793 *
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795 * pipe == 0 check?
4796 */
e70236a8
JB		 4797 if (mode->clock >
4798 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4799 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4800 else
5eddb70b 4801 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4802 }
4803
3b5c78a3
AJ		 4804 /* default to 8bpc */
4805 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4806 if (is_dp) {
0c96c65b 4807 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4808 pipeconf |= PIPECONF_BPP_6 |
4809 PIPECONF_DITHER_EN |
4810 PIPECONF_DITHER_TYPE_SP;
4811 }
4812 }
4813
19c03924
GB		 4814 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4815 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4816 pipeconf |= PIPECONF_BPP_6 |
4817 PIPECONF_ENABLE |
4818 I965_PIPECONF_ACTIVE;
4819 }
4820 }
4821
28c97730 4822 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4823 drm_mode_debug_printmodeline(mode);
4824
a7516a05
JB		 4825 if (HAS_PIPE_CXSR(dev)) {
4826 if (intel_crtc->lowfreq_avail) {
28c97730 4827 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4828 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4829 } else {
28c97730 4830 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4831 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4832 }
4833 }
4834
617cf884 4835 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4836 if (!IS_GEN2(dev) &&
b0e77b9c 4837 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4838 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4839 else
617cf884 4840 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4841
b0e77b9c 4842 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4843
4844 /* pipesrc and dspsize control the size that is scaled from,
4845 * which should always be the user's requested size.
79e53945 4846 */
929c77fb
EA		 4847 I915_WRITE(DSPSIZE(plane),
4848 ((mode->vdisplay - 1) << 16) |
4849 (mode->hdisplay - 1));
4850 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4851
f564048e
EA		 4852 I915_WRITE(PIPECONF(pipe), pipeconf);
4853 POSTING_READ(PIPECONF(pipe));
929c77fb 4854 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4855
4856 intel_wait_for_vblank(dev, pipe);
4857
f564048e
EA		 4858 I915_WRITE(DSPCNTR(plane), dspcntr);
4859 POSTING_READ(DSPCNTR(plane));
4860
94352cf9 4861 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4862
4863 intel_update_watermarks(dev);
4864
f564048e
EA		 4865 return ret;
4866}
4867
9fb526db
KP		 4868/*
4869 * Initialize reference clocks when the driver loads
4870 */
4871void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4872{
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4875 struct intel_encoder *encoder;
13d83a67
JB		 4876 u32 temp;
4877 bool has_lvds = false;
199e5d79
KP		 4878 bool has_cpu_edp = false;
4879 bool has_pch_edp = false;
4880 bool has_panel = false;
99eb6a01
KP		 4881 bool has_ck505 = false;
4882 bool can_ssc = false;
13d83a67
JB		 4883
4884 /* We need to take the global config into account */
199e5d79
KP		 4885 list_for_each_entry(encoder, &mode_config->encoder_list,
4886 base.head) {
4887 switch (encoder->type) {
4888 case INTEL_OUTPUT_LVDS:
4889 has_panel = true;
4890 has_lvds = true;
4891 break;
4892 case INTEL_OUTPUT_EDP:
4893 has_panel = true;
4894 if (intel_encoder_is_pch_edp(&encoder->base))
4895 has_pch_edp = true;
4896 else
4897 has_cpu_edp = true;
4898 break;
13d83a67
JB		 4899 }
4900 }
4901
99eb6a01
KP		 4902 if (HAS_PCH_IBX(dev)) {
4903 has_ck505 = dev_priv->display_clock_mode;
4904 can_ssc = has_ck505;
4905 } else {
4906 has_ck505 = false;
4907 can_ssc = true;
4908 }
4909
4910 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4911 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4912 has_ck505);
13d83a67
JB		 4913
4914 /* Ironlake: try to setup display ref clock before DPLL
4915 * enabling. This is only under driver's control after
4916 * PCH B stepping, previous chipset stepping should be
4917 * ignoring this setting.
4918 */
4919 temp = I915_READ(PCH_DREF_CONTROL);
4920 /* Always enable nonspread source */
4921 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4922
99eb6a01
KP		 4923 if (has_ck505)
4924 temp |= DREF_NONSPREAD_CK505_ENABLE;
4925 else
4926 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4927
199e5d79
KP		 4928 if (has_panel) {
4929 temp &= ~DREF_SSC_SOURCE_MASK;
4930 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4931
199e5d79 4932 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4933 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4934 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4935 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4936 } else
4937 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4938
4939 /* Get SSC going before enabling the outputs */
4940 I915_WRITE(PCH_DREF_CONTROL, temp);
4941 POSTING_READ(PCH_DREF_CONTROL);
4942 udelay(200);
4943
13d83a67
JB		 4944 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4945
4946 /* Enable CPU source on CPU attached eDP */
199e5d79 4947 if (has_cpu_edp) {
99eb6a01 4948 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4949 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4950 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4951 }
13d83a67
JB		 4952 else
4953 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4954 } else
4955 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4956
4957 I915_WRITE(PCH_DREF_CONTROL, temp);
4958 POSTING_READ(PCH_DREF_CONTROL);
4959 udelay(200);
4960 } else {
4961 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4962
4963 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4964
4965 /* Turn off CPU output */
4966 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4967
4968 I915_WRITE(PCH_DREF_CONTROL, temp);
4969 POSTING_READ(PCH_DREF_CONTROL);
4970 udelay(200);
4971
4972 /* Turn off the SSC source */
4973 temp &= ~DREF_SSC_SOURCE_MASK;
4974 temp |= DREF_SSC_SOURCE_DISABLE;
4975
4976 /* Turn off SSC1 */
4977 temp &= ~ DREF_SSC1_ENABLE;
4978
13d83a67
JB		 4979 I915_WRITE(PCH_DREF_CONTROL, temp);
4980 POSTING_READ(PCH_DREF_CONTROL);
4981 udelay(200);
4982 }
4983}
4984
d9d444cb
JB		 4985static int ironlake_get_refclk(struct drm_crtc *crtc)
4986{
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_encoder *encoder;
d9d444cb
JB		 4990 struct intel_encoder *edp_encoder = NULL;
4991 int num_connectors = 0;
4992 bool is_lvds = false;
4993
6c2b7c12 4994 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4995 switch (encoder->type) {
4996 case INTEL_OUTPUT_LVDS:
4997 is_lvds = true;
4998 break;
4999 case INTEL_OUTPUT_EDP:
5000 edp_encoder = encoder;
5001 break;
5002 }
5003 num_connectors++;
5004 }
5005
5006 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5007 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5008 dev_priv->lvds_ssc_freq);
5009 return dev_priv->lvds_ssc_freq * 1000;
5010 }
5011
5012 return 120000;
5013}
5014
c8203565
PZ		 5015static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5016 struct drm_display_mode *adjusted_mode,
5017 bool dither)
5018{
5019 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021 int pipe = intel_crtc->pipe;
5022 uint32_t val;
5023
5024 val = I915_READ(PIPECONF(pipe));
5025
5026 val &= ~PIPE_BPC_MASK;
5027 switch (intel_crtc->bpp) {
5028 case 18:
5029 val |= PIPE_6BPC;
5030 break;
5031 case 24:
5032 val |= PIPE_8BPC;
5033 break;
5034 case 30:
5035 val |= PIPE_10BPC;
5036 break;
5037 case 36:
5038 val |= PIPE_12BPC;
5039 break;
5040 default:
cc769b62
PZ		 5041 /* Case prevented by intel_choose_pipe_bpp_dither. */
5042 BUG();
c8203565
PZ		 5043 }
5044
5045 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5046 if (dither)
5047 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5048
5049 val &= ~PIPECONF_INTERLACE_MASK;
5050 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5051 val |= PIPECONF_INTERLACED_ILK;
5052 else
5053 val |= PIPECONF_PROGRESSIVE;
5054
5055 I915_WRITE(PIPECONF(pipe), val);
5056 POSTING_READ(PIPECONF(pipe));
5057}
5058
ee2b0b38
PZ		 5059static void haswell_set_pipeconf(struct drm_crtc *crtc,
5060 struct drm_display_mode *adjusted_mode,
5061 bool dither)
5062{
5063 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5065 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5066 uint32_t val;
5067
702e7a56 5068 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5069
5070 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5071 if (dither)
5072 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5073
5074 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5075 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5076 val |= PIPECONF_INTERLACED_ILK;
5077 else
5078 val |= PIPECONF_PROGRESSIVE;
5079
702e7a56
PZ		 5080 I915_WRITE(PIPECONF(cpu_transcoder), val);
5081 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5082}
5083
6591c6e4
PZ		 5084static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5085 struct drm_display_mode *adjusted_mode,
5086 intel_clock_t *clock,
5087 bool *has_reduced_clock,
5088 intel_clock_t *reduced_clock)
5089{
5090 struct drm_device *dev = crtc->dev;
5091 struct drm_i915_private *dev_priv = dev->dev_private;
5092 struct intel_encoder *intel_encoder;
5093 int refclk;
5094 const intel_limit_t *limit;
5095 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5096
5097 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5098 switch (intel_encoder->type) {
5099 case INTEL_OUTPUT_LVDS:
5100 is_lvds = true;
5101 break;
5102 case INTEL_OUTPUT_SDVO:
5103 case INTEL_OUTPUT_HDMI:
5104 is_sdvo = true;
5105 if (intel_encoder->needs_tv_clock)
5106 is_tv = true;
5107 break;
5108 case INTEL_OUTPUT_TVOUT:
5109 is_tv = true;
5110 break;
5111 }
5112 }
5113
5114 refclk = ironlake_get_refclk(crtc);
5115
5116 /*
5117 * Returns a set of divisors for the desired target clock with the given
5118 * refclk, or FALSE. The returned values represent the clock equation:
5119 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5120 */
5121 limit = intel_limit(crtc, refclk);
5122 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5123 clock);
5124 if (!ret)
5125 return false;
5126
5127 if (is_lvds && dev_priv->lvds_downclock_avail) {
5128 /*
5129 * Ensure we match the reduced clock's P to the target clock.
5130 * If the clocks don't match, we can't switch the display clock
5131 * by using the FP0/FP1. In such case we will disable the LVDS
5132 * downclock feature.
5133 */
5134 *has_reduced_clock = limit->find_pll(limit, crtc,
5135 dev_priv->lvds_downclock,
5136 refclk,
5137 clock,
5138 reduced_clock);
5139 }
5140
5141 if (is_sdvo && is_tv)
5142 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5143
5144 return true;
5145}
5146
01a415fd
DV		 5147static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5148{
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5150 uint32_t temp;
5151
5152 temp = I915_READ(SOUTH_CHICKEN1);
5153 if (temp & FDI_BC_BIFURCATION_SELECT)
5154 return;
5155
5156 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5157 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5158
5159 temp |= FDI_BC_BIFURCATION_SELECT;
5160 DRM_DEBUG_KMS("enabling fdi C rx\n");
5161 I915_WRITE(SOUTH_CHICKEN1, temp);
5162 POSTING_READ(SOUTH_CHICKEN1);
5163}
5164
5165static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5166{
5167 struct drm_device *dev = intel_crtc->base.dev;
5168 struct drm_i915_private *dev_priv = dev->dev_private;
5169 struct intel_crtc *pipe_B_crtc =
5170 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5171
5172 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5173 intel_crtc->pipe, intel_crtc->fdi_lanes);
5174 if (intel_crtc->fdi_lanes > 4) {
5175 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5176 intel_crtc->pipe, intel_crtc->fdi_lanes);
5177 /* Clamp lanes to avoid programming the hw with bogus values. */
5178 intel_crtc->fdi_lanes = 4;
5179
5180 return false;
5181 }
5182
5183 if (dev_priv->num_pipe == 2)
5184 return true;
5185
5186 switch (intel_crtc->pipe) {
5187 case PIPE_A:
5188 return true;
5189 case PIPE_B:
5190 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5191 intel_crtc->fdi_lanes > 2) {
5192 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5193 intel_crtc->pipe, intel_crtc->fdi_lanes);
5194 /* Clamp lanes to avoid programming the hw with bogus values. */
5195 intel_crtc->fdi_lanes = 2;
5196
5197 return false;
5198 }
5199
5200 if (intel_crtc->fdi_lanes > 2)
5201 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5202 else
5203 cpt_enable_fdi_bc_bifurcation(dev);
5204
5205 return true;
5206 case PIPE_C:
5207 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5208 if (intel_crtc->fdi_lanes > 2) {
5209 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5210 intel_crtc->pipe, intel_crtc->fdi_lanes);
5211 /* Clamp lanes to avoid programming the hw with bogus values. */
5212 intel_crtc->fdi_lanes = 2;
5213
5214 return false;
5215 }
5216 } else {
5217 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5218 return false;
5219 }
5220
5221 cpt_enable_fdi_bc_bifurcation(dev);
5222
5223 return true;
5224 default:
5225 BUG();
5226 }
5227}
5228
f48d8f23
PZ		 5229static void ironlake_set_m_n(struct drm_crtc *crtc,
5230 struct drm_display_mode *mode,
5231 struct drm_display_mode *adjusted_mode)
5232{
5233 struct drm_device *dev = crtc->dev;
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5236 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5237 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5238 struct fdi_m_n m_n = {0};
5239 int target_clock, pixel_multiplier, lane, link_bw;
5240 bool is_dp = false, is_cpu_edp = false;
5241
5242 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5243 switch (intel_encoder->type) {
5244 case INTEL_OUTPUT_DISPLAYPORT:
5245 is_dp = true;
5246 break;
5247 case INTEL_OUTPUT_EDP:
5248 is_dp = true;
5249 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5250 is_cpu_edp = true;
5251 edp_encoder = intel_encoder;
5252 break;
5253 }
5254 }
5255
5256 /* FDI link */
5257 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5258 lane = 0;
5259 /* CPU eDP doesn't require FDI link, so just set DP M/N
5260 according to current link config */
5261 if (is_cpu_edp) {
5262 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5263 } else {
5264 /* FDI is a binary signal running at ~2.7GHz, encoding
5265 * each output octet as 10 bits. The actual frequency
5266 * is stored as a divider into a 100MHz clock, and the
5267 * mode pixel clock is stored in units of 1KHz.
5268 * Hence the bw of each lane in terms of the mode signal
5269 * is:
5270 */
5271 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5272 }
5273
5274 /* [e]DP over FDI requires target mode clock instead of link clock. */
5275 if (edp_encoder)
5276 target_clock = intel_edp_target_clock(edp_encoder, mode);
5277 else if (is_dp)
5278 target_clock = mode->clock;
5279 else
5280 target_clock = adjusted_mode->clock;
5281
5282 if (!lane) {
5283 /*
5284 * Account for spread spectrum to avoid
5285 * oversubscribing the link. Max center spread
5286 * is 2.5%; use 5% for safety's sake.
5287 */
5288 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5289 lane = bps / (link_bw * 8) + 1;
5290 }
5291
5292 intel_crtc->fdi_lanes = lane;
5293
5294 if (pixel_multiplier > 1)
5295 link_bw *= pixel_multiplier;
5296 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5297 &m_n);
5298
afe2fcf5
PZ		 5299 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5300 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5301 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5302 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5303}
5304
de13a2e3
PZ		 5305static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5306 struct drm_display_mode *adjusted_mode,
5307 intel_clock_t *clock, u32 fp)
79e53945 5308{
de13a2e3 5309 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5310 struct drm_device *dev = crtc->dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5312 struct intel_encoder *intel_encoder;
5313 uint32_t dpll;
5314 int factor, pixel_multiplier, num_connectors = 0;
5315 bool is_lvds = false, is_sdvo = false, is_tv = false;
5316 bool is_dp = false, is_cpu_edp = false;
79e53945 5317
de13a2e3
PZ		 5318 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5319 switch (intel_encoder->type) {
79e53945
JB		 5320 case INTEL_OUTPUT_LVDS:
5321 is_lvds = true;
5322 break;
5323 case INTEL_OUTPUT_SDVO:
7d57382e 5324 case INTEL_OUTPUT_HDMI:
79e53945 5325 is_sdvo = true;
de13a2e3 5326 if (intel_encoder->needs_tv_clock)
e2f0ba97 5327 is_tv = true;
79e53945 5328 break;
79e53945
JB		 5329 case INTEL_OUTPUT_TVOUT:
5330 is_tv = true;
5331 break;
a4fc5ed6
KP		 5332 case INTEL_OUTPUT_DISPLAYPORT:
5333 is_dp = true;
5334 break;
32f9d658 5335 case INTEL_OUTPUT_EDP:
e3aef172 5336 is_dp = true;
de13a2e3 5337 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5338 is_cpu_edp = true;
32f9d658 5339 break;
79e53945 5340 }
43565a06 5341
c751ce4f 5342 num_connectors++;
79e53945
JB		 5343 }
5344
c1858123 5345 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5346 factor = 21;
5347 if (is_lvds) {
5348 if ((intel_panel_use_ssc(dev_priv) &&
5349 dev_priv->lvds_ssc_freq == 100) ||
5350 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5351 factor = 25;
5352 } else if (is_sdvo && is_tv)
5353 factor = 20;
c1858123 5354
de13a2e3 5355 if (clock->m < factor * clock->n)
8febb297 5356 fp |= FP_CB_TUNE;
2c07245f 5357
5eddb70b 5358 dpll = 0;
2c07245f 5359
a07d6787
EA		 5360 if (is_lvds)
5361 dpll |= DPLLB_MODE_LVDS;
5362 else
5363 dpll |= DPLLB_MODE_DAC_SERIAL;
5364 if (is_sdvo) {
de13a2e3 5365 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5366 if (pixel_multiplier > 1) {
5367 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5368 }
a07d6787
EA		 5369 dpll |= DPLL_DVO_HIGH_SPEED;
5370 }
e3aef172 5371 if (is_dp && !is_cpu_edp)
a07d6787 5372 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5373
a07d6787 5374 /* compute bitmask from p1 value */
de13a2e3 5375 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5376 /* also FPA1 */
de13a2e3 5377 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5378
de13a2e3 5379 switch (clock->p2) {
a07d6787
EA		 5380 case 5:
5381 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5382 break;
5383 case 7:
5384 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5385 break;
5386 case 10:
5387 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5388 break;
5389 case 14:
5390 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5391 break;
79e53945
JB		 5392 }
5393
43565a06
KH		 5394 if (is_sdvo && is_tv)
5395 dpll |= PLL_REF_INPUT_TVCLKINBC;
5396 else if (is_tv)
79e53945 5397 /* XXX: just matching BIOS for now */
43565a06 5398 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5399 dpll |= 3;
a7615030 5400 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5401 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5402 else
5403 dpll |= PLL_REF_INPUT_DREFCLK;
5404
de13a2e3
PZ		 5405 return dpll;
5406}
5407
5408static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5409 struct drm_display_mode *mode,
5410 struct drm_display_mode *adjusted_mode,
5411 int x, int y,
5412 struct drm_framebuffer *fb)
5413{
5414 struct drm_device *dev = crtc->dev;
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5417 int pipe = intel_crtc->pipe;
5418 int plane = intel_crtc->plane;
5419 int num_connectors = 0;
5420 intel_clock_t clock, reduced_clock;
5421 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5422 bool ok, has_reduced_clock = false;
5423 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5424 struct intel_encoder *encoder;
5425 u32 temp;
5426 int ret;
01a415fd 5427 bool dither, fdi_config_ok;
de13a2e3
PZ		 5428
5429 for_each_encoder_on_crtc(dev, crtc, encoder) {
5430 switch (encoder->type) {
5431 case INTEL_OUTPUT_LVDS:
5432 is_lvds = true;
5433 break;
de13a2e3
PZ		 5434 case INTEL_OUTPUT_DISPLAYPORT:
5435 is_dp = true;
5436 break;
5437 case INTEL_OUTPUT_EDP:
5438 is_dp = true;
e2f12b07 5439 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5440 is_cpu_edp = true;
5441 break;
5442 }
5443
5444 num_connectors++;
5445 }
5446
5dc5298b
PZ		 5447 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5448 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5449
de13a2e3
PZ		 5450 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5451 &has_reduced_clock, &reduced_clock);
5452 if (!ok) {
5453 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5454 return -EINVAL;
5455 }
5456
5457 /* Ensure that the cursor is valid for the new mode before changing... */
5458 intel_crtc_update_cursor(crtc, true);
5459
5460 /* determine panel color depth */
c8241969
JN		 5461 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5462 adjusted_mode);
de13a2e3
PZ		 5463 if (is_lvds && dev_priv->lvds_dither)
5464 dither = true;
5465
5466 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5467 if (has_reduced_clock)
5468 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5469 reduced_clock.m2;
5470
5471 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5472
f7cb34d4 5473 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5474 drm_mode_debug_printmodeline(mode);
5475
5dc5298b
PZ		 5476 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5477 if (!is_cpu_edp) {
ee7b9f93 5478 struct intel_pch_pll *pll;
4b645f14 5479
ee7b9f93
JB		 5480 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5481 if (pll == NULL) {
5482 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5483 pipe);
4b645f14
JB		 5484 return -EINVAL;
5485 }
ee7b9f93
JB		 5486 } else
5487 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5488
5489 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5490 * This is an exception to the general rule that mode_set doesn't turn
5491 * things on.
5492 */
5493 if (is_lvds) {
fae14981 5494 temp = I915_READ(PCH_LVDS);
5eddb70b 5495 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5496 if (HAS_PCH_CPT(dev)) {
5497 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5498 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5499 } else {
5500 if (pipe == 1)
5501 temp |= LVDS_PIPEB_SELECT;
5502 else
5503 temp &= ~LVDS_PIPEB_SELECT;
5504 }
4b645f14 5505
a3e17eb8 5506 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5507 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5508 /* Set the B0-B3 data pairs corresponding to whether we're going to
5509 * set the DPLLs for dual-channel mode or not.
5510 */
5511 if (clock.p2 == 7)
5eddb70b 5512 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5513 else
5eddb70b 5514 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5515
5516 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5517 * appropriately here, but we need to look more thoroughly into how
5518 * panels behave in the two modes.
5519 */
284d5df5 5520 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5521 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5522 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5523 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5524 temp |= LVDS_VSYNC_POLARITY;
fae14981 5525 I915_WRITE(PCH_LVDS, temp);
79e53945 5526 }
434ed097 5527
e3aef172 5528 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5529 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5530 } else {
8db9d77b 5531 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5532 I915_WRITE(TRANSDATA_M1(pipe), 0);
5533 I915_WRITE(TRANSDATA_N1(pipe), 0);
5534 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5535 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5536 }
79e53945 5537
ee7b9f93
JB		 5538 if (intel_crtc->pch_pll) {
5539 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5540
32f9d658 5541 /* Wait for the clocks to stabilize. */
ee7b9f93 5542 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5543 udelay(150);
5544
8febb297
EA		 5545 /* The pixel multiplier can only be updated once the
5546 * DPLL is enabled and the clocks are stable.
5547 *
5548 * So write it again.
5549 */
ee7b9f93 5550 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5551 }
79e53945 5552
5eddb70b 5553 intel_crtc->lowfreq_avail = false;
ee7b9f93 5554 if (intel_crtc->pch_pll) {
4b645f14 5555 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5556 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5557 intel_crtc->lowfreq_avail = true;
4b645f14 5558 } else {
ee7b9f93 5559 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5560 }
5561 }
5562
b0e77b9c 5563 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5564
01a415fd
DV		 5565 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5566 * ironlake_check_fdi_lanes. */
f48d8f23 5567 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5568
01a415fd
DV		 5569 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5570
e3aef172 5571 if (is_cpu_edp)
8febb297 5572 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5573
c8203565 5574 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5575
9d0498a2 5576 intel_wait_for_vblank(dev, pipe);
79e53945 5577
a1f9e77e
PZ		 5578 /* Set up the display plane register */
5579 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5580 POSTING_READ(DSPCNTR(plane));
79e53945 5581
94352cf9 5582 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5583
5584 intel_update_watermarks(dev);
5585
1f8eeabf
ED		 5586 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5587
01a415fd 5588 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5589}
5590
09b4ddf9
PZ		 5591static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5592 struct drm_display_mode *mode,
5593 struct drm_display_mode *adjusted_mode,
5594 int x, int y,
5595 struct drm_framebuffer *fb)
5596{
5597 struct drm_device *dev = crtc->dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 int pipe = intel_crtc->pipe;
5601 int plane = intel_crtc->plane;
5602 int num_connectors = 0;
5603 intel_clock_t clock, reduced_clock;
5dc5298b 5604 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5605 bool ok, has_reduced_clock = false;
5606 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5607 struct intel_encoder *encoder;
5608 u32 temp;
5609 int ret;
5610 bool dither;
5611
5612 for_each_encoder_on_crtc(dev, crtc, encoder) {
5613 switch (encoder->type) {
5614 case INTEL_OUTPUT_LVDS:
5615 is_lvds = true;
5616 break;
5617 case INTEL_OUTPUT_DISPLAYPORT:
5618 is_dp = true;
5619 break;
5620 case INTEL_OUTPUT_EDP:
5621 is_dp = true;
5622 if (!intel_encoder_is_pch_edp(&encoder->base))
5623 is_cpu_edp = true;
5624 break;
5625 }
5626
5627 num_connectors++;
5628 }
5629
a5c961d1
PZ		 5630 if (is_cpu_edp)
5631 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5632 else
5633 intel_crtc->cpu_transcoder = pipe;
5634
5dc5298b
PZ		 5635 /* We are not sure yet this won't happen. */
5636 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5637 INTEL_PCH_TYPE(dev));
5638
5639 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5640 num_connectors, pipe_name(pipe));
5641
702e7a56 5642 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5643 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5644
5645 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5646
6441ab5f
PZ		 5647 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5648 return -EINVAL;
5649
5dc5298b
PZ		 5650 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5651 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5652 &has_reduced_clock,
5653 &reduced_clock);
5654 if (!ok) {
5655 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5656 return -EINVAL;
5657 }
09b4ddf9
PZ		 5658 }
5659
5660 /* Ensure that the cursor is valid for the new mode before changing... */
5661 intel_crtc_update_cursor(crtc, true);
5662
5663 /* determine panel color depth */
c8241969
JN		 5664 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5665 adjusted_mode);
09b4ddf9
PZ		 5666 if (is_lvds && dev_priv->lvds_dither)
5667 dither = true;
5668
09b4ddf9
PZ		 5669 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5670 drm_mode_debug_printmodeline(mode);
5671
5dc5298b
PZ		 5672 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5673 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5674 if (has_reduced_clock)
5675 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5676 reduced_clock.m2;
5677
5678 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5679 fp);
5680
5681 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5682 * own on pre-Haswell/LPT generation */
5683 if (!is_cpu_edp) {
5684 struct intel_pch_pll *pll;
5685
5686 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5687 if (pll == NULL) {
5688 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5689 pipe);
5690 return -EINVAL;
5691 }
5692 } else
5693 intel_put_pch_pll(intel_crtc);
09b4ddf9 5694
5dc5298b
PZ		 5695 /* The LVDS pin pair needs to be on before the DPLLs are
5696 * enabled. This is an exception to the general rule that
5697 * mode_set doesn't turn things on.
5698 */
5699 if (is_lvds) {
5700 temp = I915_READ(PCH_LVDS);
5701 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5702 if (HAS_PCH_CPT(dev)) {
5703 temp &= ~PORT_TRANS_SEL_MASK;
5704 temp |= PORT_TRANS_SEL_CPT(pipe);
5705 } else {
5706 if (pipe == 1)
5707 temp |= LVDS_PIPEB_SELECT;
5708 else
5709 temp &= ~LVDS_PIPEB_SELECT;
5710 }
09b4ddf9 5711
5dc5298b
PZ		 5712 /* set the corresponsding LVDS_BORDER bit */
5713 temp |= dev_priv->lvds_border_bits;
5714 /* Set the B0-B3 data pairs corresponding to whether
5715 * we're going to set the DPLLs for dual-channel mode or
5716 * not.
5717 */
5718 if (clock.p2 == 7)
5719 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5720 else
5dc5298b
PZ		 5721 temp &= ~(LVDS_B0B3_POWER_UP |
5722 LVDS_CLKB_POWER_UP);
5723
5724 /* It would be nice to set 24 vs 18-bit mode
5725 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5726 * look more thoroughly into how panels behave in the
5727 * two modes.
5728 */
5729 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5730 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5731 temp |= LVDS_HSYNC_POLARITY;
5732 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5733 temp |= LVDS_VSYNC_POLARITY;
5734 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5735 }
09b4ddf9
PZ		 5736 }
5737
5738 if (is_dp && !is_cpu_edp) {
5739 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5740 } else {
5dc5298b
PZ		 5741 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5742 /* For non-DP output, clear any trans DP clock recovery
5743 * setting.*/
5744 I915_WRITE(TRANSDATA_M1(pipe), 0);
5745 I915_WRITE(TRANSDATA_N1(pipe), 0);
5746 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5747 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5748 }
09b4ddf9
PZ		 5749 }
5750
5751 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5752 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5753 if (intel_crtc->pch_pll) {
5754 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5755
5756 /* Wait for the clocks to stabilize. */
5757 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5758 udelay(150);
5759
5760 /* The pixel multiplier can only be updated once the
5761 * DPLL is enabled and the clocks are stable.
5762 *
5763 * So write it again.
5764 */
5765 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5766 }
5767
5768 if (intel_crtc->pch_pll) {
5769 if (is_lvds && has_reduced_clock && i915_powersave) {
5770 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5771 intel_crtc->lowfreq_avail = true;
5772 } else {
5773 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5774 }
09b4ddf9
PZ		 5775 }
5776 }
5777
5778 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5779
1eb8dfec
PZ		 5780 if (!is_dp || is_cpu_edp)
5781 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5782
5dc5298b
PZ		 5783 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5784 if (is_cpu_edp)
5785 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5786
ee2b0b38 5787 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5788
09b4ddf9
PZ		 5789 /* Set up the display plane register */
5790 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5791 POSTING_READ(DSPCNTR(plane));
5792
5793 ret = intel_pipe_set_base(crtc, x, y, fb);
5794
5795 intel_update_watermarks(dev);
5796
5797 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5798
5799 return ret;
5800}
5801
f564048e
EA		 5802static int intel_crtc_mode_set(struct drm_crtc *crtc,
5803 struct drm_display_mode *mode,
5804 struct drm_display_mode *adjusted_mode,
5805 int x, int y,
94352cf9 5806 struct drm_framebuffer *fb)
f564048e
EA		 5807{
5808 struct drm_device *dev = crtc->dev;
5809 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5810 struct drm_encoder_helper_funcs *encoder_funcs;
5811 struct intel_encoder *encoder;
0b701d27
EA		 5812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5813 int pipe = intel_crtc->pipe;
f564048e
EA		 5814 int ret;
5815
0b701d27 5816 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5817
f564048e 5818 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5819 x, y, fb);
79e53945 5820 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5821
9256aa19
DV		 5822 if (ret != 0)
5823 return ret;
5824
5825 for_each_encoder_on_crtc(dev, crtc, encoder) {
5826 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5827 encoder->base.base.id,
5828 drm_get_encoder_name(&encoder->base),
5829 mode->base.id, mode->name);
5830 encoder_funcs = encoder->base.helper_private;
5831 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5832 }
5833
5834 return 0;
79e53945
JB		 5835}
5836
3a9627f4
WF		 5837static bool intel_eld_uptodate(struct drm_connector *connector,
5838 int reg_eldv, uint32_t bits_eldv,
5839 int reg_elda, uint32_t bits_elda,
5840 int reg_edid)
5841{
5842 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843 uint8_t *eld = connector->eld;
5844 uint32_t i;
5845
5846 i = I915_READ(reg_eldv);
5847 i &= bits_eldv;
5848
5849 if (!eld[0])
5850 return !i;
5851
5852 if (!i)
5853 return false;
5854
5855 i = I915_READ(reg_elda);
5856 i &= ~bits_elda;
5857 I915_WRITE(reg_elda, i);
5858
5859 for (i = 0; i < eld[2]; i++)
5860 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5861 return false;
5862
5863 return true;
5864}
5865
e0dac65e
WF		 5866static void g4x_write_eld(struct drm_connector *connector,
5867 struct drm_crtc *crtc)
5868{
5869 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5870 uint8_t *eld = connector->eld;
5871 uint32_t eldv;
5872 uint32_t len;
5873 uint32_t i;
5874
5875 i = I915_READ(G4X_AUD_VID_DID);
5876
5877 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5878 eldv = G4X_ELDV_DEVCL_DEVBLC;
5879 else
5880 eldv = G4X_ELDV_DEVCTG;
5881
3a9627f4
WF		 5882 if (intel_eld_uptodate(connector,
5883 G4X_AUD_CNTL_ST, eldv,
5884 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5885 G4X_HDMIW_HDMIEDID))
5886 return;
5887
e0dac65e
WF		 5888 i = I915_READ(G4X_AUD_CNTL_ST);
5889 i &= ~(eldv | G4X_ELD_ADDR);
5890 len = (i >> 9) & 0x1f; /* ELD buffer size */
5891 I915_WRITE(G4X_AUD_CNTL_ST, i);
5892
5893 if (!eld[0])
5894 return;
5895
5896 len = min_t(uint8_t, eld[2], len);
5897 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5898 for (i = 0; i < len; i++)
5899 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5900
5901 i = I915_READ(G4X_AUD_CNTL_ST);
5902 i |= eldv;
5903 I915_WRITE(G4X_AUD_CNTL_ST, i);
5904}
5905
83358c85
WX		 5906static void haswell_write_eld(struct drm_connector *connector,
5907 struct drm_crtc *crtc)
5908{
5909 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5910 uint8_t *eld = connector->eld;
5911 struct drm_device *dev = crtc->dev;
5912 uint32_t eldv;
5913 uint32_t i;
5914 int len;
5915 int pipe = to_intel_crtc(crtc)->pipe;
5916 int tmp;
5917
5918 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5919 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5920 int aud_config = HSW_AUD_CFG(pipe);
5921 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5922
5923
5924 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5925
5926 /* Audio output enable */
5927 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5928 tmp = I915_READ(aud_cntrl_st2);
5929 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5930 I915_WRITE(aud_cntrl_st2, tmp);
5931
5932 /* Wait for 1 vertical blank */
5933 intel_wait_for_vblank(dev, pipe);
5934
5935 /* Set ELD valid state */
5936 tmp = I915_READ(aud_cntrl_st2);
5937 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5938 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5939 I915_WRITE(aud_cntrl_st2, tmp);
5940 tmp = I915_READ(aud_cntrl_st2);
5941 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5942
5943 /* Enable HDMI mode */
5944 tmp = I915_READ(aud_config);
5945 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5946 /* clear N_programing_enable and N_value_index */
5947 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5948 I915_WRITE(aud_config, tmp);
5949
5950 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5951
5952 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5953
5954 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5955 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5956 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5957 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5958 } else
5959 I915_WRITE(aud_config, 0);
5960
5961 if (intel_eld_uptodate(connector,
5962 aud_cntrl_st2, eldv,
5963 aud_cntl_st, IBX_ELD_ADDRESS,
5964 hdmiw_hdmiedid))
5965 return;
5966
5967 i = I915_READ(aud_cntrl_st2);
5968 i &= ~eldv;
5969 I915_WRITE(aud_cntrl_st2, i);
5970
5971 if (!eld[0])
5972 return;
5973
5974 i = I915_READ(aud_cntl_st);
5975 i &= ~IBX_ELD_ADDRESS;
5976 I915_WRITE(aud_cntl_st, i);
5977 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5978 DRM_DEBUG_DRIVER("port num:%d\n", i);
5979
5980 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5981 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5982 for (i = 0; i < len; i++)
5983 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5984
5985 i = I915_READ(aud_cntrl_st2);
5986 i |= eldv;
5987 I915_WRITE(aud_cntrl_st2, i);
5988
5989}
5990
e0dac65e
WF		 5991static void ironlake_write_eld(struct drm_connector *connector,
5992 struct drm_crtc *crtc)
5993{
5994 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5995 uint8_t *eld = connector->eld;
5996 uint32_t eldv;
5997 uint32_t i;
5998 int len;
5999 int hdmiw_hdmiedid;
b6daa025 6000 int aud_config;
e0dac65e
WF		 6001 int aud_cntl_st;
6002 int aud_cntrl_st2;
9b138a83 6003 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6004
b3f33cbf 6005 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6006 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6007 aud_config = IBX_AUD_CFG(pipe);
6008 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6009 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6010 } else {
9b138a83
WX		 6011 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6012 aud_config = CPT_AUD_CFG(pipe);
6013 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6014 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6015 }
6016
9b138a83 6017 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6018
6019 i = I915_READ(aud_cntl_st);
9b138a83 6020 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6021 if (!i) {
6022 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6023 /* operate blindly on all ports */
1202b4c6
WF		 6024 eldv = IBX_ELD_VALIDB;
6025 eldv |= IBX_ELD_VALIDB << 4;
6026 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6027 } else {
6028 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6029 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6030 }
6031
3a9627f4
WF		 6032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6033 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6034 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6035 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6036 } else
6037 I915_WRITE(aud_config, 0);
e0dac65e 6038
3a9627f4
WF		 6039 if (intel_eld_uptodate(connector,
6040 aud_cntrl_st2, eldv,
6041 aud_cntl_st, IBX_ELD_ADDRESS,
6042 hdmiw_hdmiedid))
6043 return;
6044
e0dac65e
WF		 6045 i = I915_READ(aud_cntrl_st2);
6046 i &= ~eldv;
6047 I915_WRITE(aud_cntrl_st2, i);
6048
6049 if (!eld[0])
6050 return;
6051
e0dac65e 6052 i = I915_READ(aud_cntl_st);
1202b4c6 6053 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6054 I915_WRITE(aud_cntl_st, i);
6055
6056 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6057 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6058 for (i = 0; i < len; i++)
6059 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6060
6061 i = I915_READ(aud_cntrl_st2);
6062 i |= eldv;
6063 I915_WRITE(aud_cntrl_st2, i);
6064}
6065
6066void intel_write_eld(struct drm_encoder *encoder,
6067 struct drm_display_mode *mode)
6068{
6069 struct drm_crtc *crtc = encoder->crtc;
6070 struct drm_connector *connector;
6071 struct drm_device *dev = encoder->dev;
6072 struct drm_i915_private *dev_priv = dev->dev_private;
6073
6074 connector = drm_select_eld(encoder, mode);
6075 if (!connector)
6076 return;
6077
6078 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6079 connector->base.id,
6080 drm_get_connector_name(connector),
6081 connector->encoder->base.id,
6082 drm_get_encoder_name(connector->encoder));
6083
6084 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6085
6086 if (dev_priv->display.write_eld)
6087 dev_priv->display.write_eld(connector, crtc);
6088}
6089
79e53945
JB		 6090/** Loads the palette/gamma unit for the CRTC with the prepared values */
6091void intel_crtc_load_lut(struct drm_crtc *crtc)
6092{
6093 struct drm_device *dev = crtc->dev;
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6096 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6097 int i;
6098
6099 /* The clocks have to be on to load the palette. */
aed3f09d 6100 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6101 return;
6102
f2b115e6 6103 /* use legacy palette for Ironlake */
bad720ff 6104 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6105 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6106
79e53945
JB		 6107 for (i = 0; i < 256; i++) {
6108 I915_WRITE(palreg + 4 * i,
6109 (intel_crtc->lut_r[i] << 16) |
6110 (intel_crtc->lut_g[i] << 8) |
6111 intel_crtc->lut_b[i]);
6112 }
6113}
6114
560b85bb
CW		 6115static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6116{
6117 struct drm_device *dev = crtc->dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120 bool visible = base != 0;
6121 u32 cntl;
6122
6123 if (intel_crtc->cursor_visible == visible)
6124 return;
6125
9db4a9c7 6126 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6127 if (visible) {
6128 /* On these chipsets we can only modify the base whilst
6129 * the cursor is disabled.
6130 */
9db4a9c7 6131 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6132
6133 cntl &= ~(CURSOR_FORMAT_MASK);
6134 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6135 cntl |= CURSOR_ENABLE |
6136 CURSOR_GAMMA_ENABLE |
6137 CURSOR_FORMAT_ARGB;
6138 } else
6139 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6140 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6141
6142 intel_crtc->cursor_visible = visible;
6143}
6144
6145static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6146{
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150 int pipe = intel_crtc->pipe;
6151 bool visible = base != 0;
6152
6153 if (intel_crtc->cursor_visible != visible) {
548f245b 6154 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6155 if (base) {
6156 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6157 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6158 cntl |= pipe << 28; /* Connect to correct pipe */
6159 } else {
6160 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6161 cntl |= CURSOR_MODE_DISABLE;
6162 }
9db4a9c7 6163 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6164
6165 intel_crtc->cursor_visible = visible;
6166 }
6167 /* and commit changes on next vblank */
9db4a9c7 6168 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6169}
6170
65a21cd6
JB		 6171static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6172{
6173 struct drm_device *dev = crtc->dev;
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6176 int pipe = intel_crtc->pipe;
6177 bool visible = base != 0;
6178
6179 if (intel_crtc->cursor_visible != visible) {
6180 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6181 if (base) {
6182 cntl &= ~CURSOR_MODE;
6183 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6184 } else {
6185 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6186 cntl |= CURSOR_MODE_DISABLE;
6187 }
6188 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6189
6190 intel_crtc->cursor_visible = visible;
6191 }
6192 /* and commit changes on next vblank */
6193 I915_WRITE(CURBASE_IVB(pipe), base);
6194}
6195
cda4b7d3 6196/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6197static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6198 bool on)
cda4b7d3
CW		 6199{
6200 struct drm_device *dev = crtc->dev;
6201 struct drm_i915_private *dev_priv = dev->dev_private;
6202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203 int pipe = intel_crtc->pipe;
6204 int x = intel_crtc->cursor_x;
6205 int y = intel_crtc->cursor_y;
560b85bb 6206 u32 base, pos;
cda4b7d3
CW		 6207 bool visible;
6208
6209 pos = 0;
6210
6b383a7f 6211 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6212 base = intel_crtc->cursor_addr;
6213 if (x > (int) crtc->fb->width)
6214 base = 0;
6215
6216 if (y > (int) crtc->fb->height)
6217 base = 0;
6218 } else
6219 base = 0;
6220
6221 if (x < 0) {
6222 if (x + intel_crtc->cursor_width < 0)
6223 base = 0;
6224
6225 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6226 x = -x;
6227 }
6228 pos |= x << CURSOR_X_SHIFT;
6229
6230 if (y < 0) {
6231 if (y + intel_crtc->cursor_height < 0)
6232 base = 0;
6233
6234 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6235 y = -y;
6236 }
6237 pos |= y << CURSOR_Y_SHIFT;
6238
6239 visible = base != 0;
560b85bb 6240 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6241 return;
6242
0cd83aa9 6243 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6244 I915_WRITE(CURPOS_IVB(pipe), pos);
6245 ivb_update_cursor(crtc, base);
6246 } else {
6247 I915_WRITE(CURPOS(pipe), pos);
6248 if (IS_845G(dev) || IS_I865G(dev))
6249 i845_update_cursor(crtc, base);
6250 else
6251 i9xx_update_cursor(crtc, base);
6252 }
cda4b7d3
CW		 6253}
6254
79e53945 6255static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6256 struct drm_file *file,
79e53945
JB		 6257 uint32_t handle,
6258 uint32_t width, uint32_t height)
6259{
6260 struct drm_device *dev = crtc->dev;
6261 struct drm_i915_private *dev_priv = dev->dev_private;
6262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6263 struct drm_i915_gem_object *obj;
cda4b7d3 6264 uint32_t addr;
3f8bc370 6265 int ret;
79e53945 6266
79e53945
JB		 6267 /* if we want to turn off the cursor ignore width and height */
6268 if (!handle) {
28c97730 6269 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6270 addr = 0;
05394f39 6271 obj = NULL;
5004417d 6272 mutex_lock(&dev->struct_mutex);
3f8bc370 6273 goto finish;
79e53945
JB		 6274 }
6275
6276 /* Currently we only support 64x64 cursors */
6277 if (width != 64 || height != 64) {
6278 DRM_ERROR("we currently only support 64x64 cursors\n");
6279 return -EINVAL;
6280 }
6281
05394f39 6282 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6283 if (&obj->base == NULL)
79e53945
JB		 6284 return -ENOENT;
6285
05394f39 6286 if (obj->base.size < width * height * 4) {
79e53945 6287 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6288 ret = -ENOMEM;
6289 goto fail;
79e53945
JB		 6290 }
6291
71acb5eb 6292 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6293 mutex_lock(&dev->struct_mutex);
b295d1b6 6294 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6295 if (obj->tiling_mode) {
6296 DRM_ERROR("cursor cannot be tiled\n");
6297 ret = -EINVAL;
6298 goto fail_locked;
6299 }
6300
2da3b9b9 6301 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6302 if (ret) {
6303 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6304 goto fail_locked;
e7b526bb
CW		 6305 }
6306
d9e86c0e
CW		 6307 ret = i915_gem_object_put_fence(obj);
6308 if (ret) {
2da3b9b9 6309 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6310 goto fail_unpin;
6311 }
6312
05394f39 6313 addr = obj->gtt_offset;
71acb5eb 6314 } else {
6eeefaf3 6315 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6316 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6317 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6318 align);
71acb5eb
DA		 6319 if (ret) {
6320 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6321 goto fail_locked;
71acb5eb 6322 }
05394f39 6323 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6324 }
6325
a6c45cf0 6326 if (IS_GEN2(dev))
14b60391
JB		 6327 I915_WRITE(CURSIZE, (height << 12) | width);
6328
3f8bc370 6329 finish:
3f8bc370 6330 if (intel_crtc->cursor_bo) {
b295d1b6 6331 if (dev_priv->info->cursor_needs_physical) {
05394f39 6332 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6333 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6334 } else
6335 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6336 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6337 }
80824003 6338
7f9872e0 6339 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6340
6341 intel_crtc->cursor_addr = addr;
05394f39 6342 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6343 intel_crtc->cursor_width = width;
6344 intel_crtc->cursor_height = height;
6345
6b383a7f 6346 intel_crtc_update_cursor(crtc, true);
3f8bc370 6347
79e53945 6348 return 0;
e7b526bb 6349fail_unpin:
05394f39 6350 i915_gem_object_unpin(obj);
7f9872e0 6351fail_locked:
34b8686e 6352 mutex_unlock(&dev->struct_mutex);
bc9025bd 6353fail:
05394f39 6354 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6355 return ret;
79e53945
JB		 6356}
6357
6358static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6359{
79e53945 6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6361
cda4b7d3
CW		 6362 intel_crtc->cursor_x = x;
6363 intel_crtc->cursor_y = y;
652c393a 6364
6b383a7f 6365 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6366
6367 return 0;
6368}
6369
6370/** Sets the color ramps on behalf of RandR */
6371void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6372 u16 blue, int regno)
6373{
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375
6376 intel_crtc->lut_r[regno] = red >> 8;
6377 intel_crtc->lut_g[regno] = green >> 8;
6378 intel_crtc->lut_b[regno] = blue >> 8;
6379}
6380
b8c00ac5
DA		 6381void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6382 u16 *blue, int regno)
6383{
6384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385
6386 *red = intel_crtc->lut_r[regno] << 8;
6387 *green = intel_crtc->lut_g[regno] << 8;
6388 *blue = intel_crtc->lut_b[regno] << 8;
6389}
6390
79e53945 6391static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6392 u16 *blue, uint32_t start, uint32_t size)
79e53945 6393{
7203425a 6394 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6396
7203425a 6397 for (i = start; i < end; i++) {
79e53945
JB		 6398 intel_crtc->lut_r[i] = red[i] >> 8;
6399 intel_crtc->lut_g[i] = green[i] >> 8;
6400 intel_crtc->lut_b[i] = blue[i] >> 8;
6401 }
6402
6403 intel_crtc_load_lut(crtc);
6404}
6405
6406/**
6407 * Get a pipe with a simple mode set on it for doing load-based monitor
6408 * detection.
6409 *
6410 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6411 * its requirements. The pipe will be connected to no other encoders.
79e53945 6412 *
c751ce4f 6413 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6414 * configured for it. In the future, it could choose to temporarily disable
6415 * some outputs to free up a pipe for its use.
6416 *
6417 * \return crtc, or NULL if no pipes are available.
6418 */
6419
6420/* VESA 640x480x72Hz mode to set on the pipe */
6421static struct drm_display_mode load_detect_mode = {
6422 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6423 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6424};
6425
d2dff872
CW		 6426static struct drm_framebuffer *
6427intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6428 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6429 struct drm_i915_gem_object *obj)
6430{
6431 struct intel_framebuffer *intel_fb;
6432 int ret;
6433
6434 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6435 if (!intel_fb) {
6436 drm_gem_object_unreference_unlocked(&obj->base);
6437 return ERR_PTR(-ENOMEM);
6438 }
6439
6440 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6441 if (ret) {
6442 drm_gem_object_unreference_unlocked(&obj->base);
6443 kfree(intel_fb);
6444 return ERR_PTR(ret);
6445 }
6446
6447 return &intel_fb->base;
6448}
6449
6450static u32
6451intel_framebuffer_pitch_for_width(int width, int bpp)
6452{
6453 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6454 return ALIGN(pitch, 64);
6455}
6456
6457static u32
6458intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6459{
6460 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6461 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6462}
6463
6464static struct drm_framebuffer *
6465intel_framebuffer_create_for_mode(struct drm_device *dev,
6466 struct drm_display_mode *mode,
6467 int depth, int bpp)
6468{
6469 struct drm_i915_gem_object *obj;
308e5bcb 6470 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6471
6472 obj = i915_gem_alloc_object(dev,
6473 intel_framebuffer_size_for_mode(mode, bpp));
6474 if (obj == NULL)
6475 return ERR_PTR(-ENOMEM);
6476
6477 mode_cmd.width = mode->hdisplay;
6478 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6479 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6480 bpp);
5ca0c34a 6481 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6482
6483 return intel_framebuffer_create(dev, &mode_cmd, obj);
6484}
6485
6486static struct drm_framebuffer *
6487mode_fits_in_fbdev(struct drm_device *dev,
6488 struct drm_display_mode *mode)
6489{
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 struct drm_i915_gem_object *obj;
6492 struct drm_framebuffer *fb;
6493
6494 if (dev_priv->fbdev == NULL)
6495 return NULL;
6496
6497 obj = dev_priv->fbdev->ifb.obj;
6498 if (obj == NULL)
6499 return NULL;
6500
6501 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6502 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6503 fb->bits_per_pixel))
d2dff872
CW		 6504 return NULL;
6505
01f2c773 6506 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6507 return NULL;
6508
6509 return fb;
6510}
6511
d2434ab7 6512bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6513 struct drm_display_mode *mode,
8261b191 6514 struct intel_load_detect_pipe *old)
79e53945
JB		 6515{
6516 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6517 struct intel_encoder *intel_encoder =
6518 intel_attached_encoder(connector);
79e53945 6519 struct drm_crtc *possible_crtc;
4ef69c7a 6520 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6521 struct drm_crtc *crtc = NULL;
6522 struct drm_device *dev = encoder->dev;
94352cf9 6523 struct drm_framebuffer *fb;
79e53945
JB		 6524 int i = -1;
6525
d2dff872
CW		 6526 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6527 connector->base.id, drm_get_connector_name(connector),
6528 encoder->base.id, drm_get_encoder_name(encoder));
6529
79e53945
JB		 6530 /*
6531 * Algorithm gets a little messy:
7a5e4805 6532 *
79e53945
JB		 6533 * - if the connector already has an assigned crtc, use it (but make
6534 * sure it's on first)
7a5e4805 6535 *
79e53945
JB		 6536 * - try to find the first unused crtc that can drive this connector,
6537 * and use that if we find one
79e53945
JB		 6538 */
6539
6540 /* See if we already have a CRTC for this connector */
6541 if (encoder->crtc) {
6542 crtc = encoder->crtc;
8261b191 6543
24218aac 6544 old->dpms_mode = connector->dpms;
8261b191
CW		 6545 old->load_detect_temp = false;
6546
6547 /* Make sure the crtc and connector are running */
24218aac
DV		 6548 if (connector->dpms != DRM_MODE_DPMS_ON)
6549 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6550
7173188d 6551 return true;
79e53945
JB		 6552 }
6553
6554 /* Find an unused one (if possible) */
6555 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6556 i++;
6557 if (!(encoder->possible_crtcs & (1 << i)))
6558 continue;
6559 if (!possible_crtc->enabled) {
6560 crtc = possible_crtc;
6561 break;
6562 }
79e53945
JB		 6563 }
6564
6565 /*
6566 * If we didn't find an unused CRTC, don't use any.
6567 */
6568 if (!crtc) {
7173188d
CW		 6569 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6570 return false;
79e53945
JB		 6571 }
6572
fc303101
DV		 6573 intel_encoder->new_crtc = to_intel_crtc(crtc);
6574 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6575
6576 intel_crtc = to_intel_crtc(crtc);
24218aac 6577 old->dpms_mode = connector->dpms;
8261b191 6578 old->load_detect_temp = true;
d2dff872 6579 old->release_fb = NULL;
79e53945 6580
6492711d
CW		 6581 if (!mode)
6582 mode = &load_detect_mode;
79e53945 6583
d2dff872
CW		 6584 /* We need a framebuffer large enough to accommodate all accesses
6585 * that the plane may generate whilst we perform load detection.
6586 * We can not rely on the fbcon either being present (we get called
6587 * during its initialisation to detect all boot displays, or it may
6588 * not even exist) or that it is large enough to satisfy the
6589 * requested mode.
6590 */
94352cf9
DV		 6591 fb = mode_fits_in_fbdev(dev, mode);
6592 if (fb == NULL) {
d2dff872 6593 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6594 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6595 old->release_fb = fb;
d2dff872
CW		 6596 } else
6597 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6598 if (IS_ERR(fb)) {
d2dff872 6599 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6600 goto fail;
79e53945 6601 }
79e53945 6602
94352cf9 6603 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6604 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6605 if (old->release_fb)
6606 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6607 goto fail;
79e53945 6608 }
7173188d 6609
79e53945 6610 /* let the connector get through one full cycle before testing */
9d0498a2 6611 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6612
7173188d 6613 return true;
24218aac
DV		 6614fail:
6615 connector->encoder = NULL;
6616 encoder->crtc = NULL;
24218aac 6617 return false;
79e53945
JB		 6618}
6619
d2434ab7 6620void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6621 struct intel_load_detect_pipe *old)
79e53945 6622{
d2434ab7
DV		 6623 struct intel_encoder *intel_encoder =
6624 intel_attached_encoder(connector);
4ef69c7a 6625 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6626
d2dff872
CW		 6627 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6628 connector->base.id, drm_get_connector_name(connector),
6629 encoder->base.id, drm_get_encoder_name(encoder));
6630
8261b191 6631 if (old->load_detect_temp) {
fc303101
DV		 6632 struct drm_crtc *crtc = encoder->crtc;
6633
6634 to_intel_connector(connector)->new_encoder = NULL;
6635 intel_encoder->new_crtc = NULL;
6636 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6637
6638 if (old->release_fb)
6639 old->release_fb->funcs->destroy(old->release_fb);
6640
0622a53c 6641 return;
79e53945
JB		 6642 }
6643
c751ce4f 6644 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6645 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6646 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6647}
6648
6649/* Returns the clock of the currently programmed mode of the given pipe. */
6650static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6651{
6652 struct drm_i915_private *dev_priv = dev->dev_private;
6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654 int pipe = intel_crtc->pipe;
548f245b 6655 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6656 u32 fp;
6657 intel_clock_t clock;
6658
6659 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6660 fp = I915_READ(FP0(pipe));
79e53945 6661 else
39adb7a5 6662 fp = I915_READ(FP1(pipe));
79e53945
JB		 6663
6664 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6665 if (IS_PINEVIEW(dev)) {
6666 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6667 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6668 } else {
6669 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6670 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6671 }
6672
a6c45cf0 6673 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6674 if (IS_PINEVIEW(dev))
6675 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6676 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6677 else
6678 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6679 DPLL_FPA01_P1_POST_DIV_SHIFT);
6680
6681 switch (dpll & DPLL_MODE_MASK) {
6682 case DPLLB_MODE_DAC_SERIAL:
6683 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6684 5 : 10;
6685 break;
6686 case DPLLB_MODE_LVDS:
6687 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6688 7 : 14;
6689 break;
6690 default:
28c97730 6691 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6692 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6693 return 0;
6694 }
6695
6696 /* XXX: Handle the 100Mhz refclk */
2177832f 6697 intel_clock(dev, 96000, &clock);
79e53945
JB		 6698 } else {
6699 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6700
6701 if (is_lvds) {
6702 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6703 DPLL_FPA01_P1_POST_DIV_SHIFT);
6704 clock.p2 = 14;
6705
6706 if ((dpll & PLL_REF_INPUT_MASK) ==
6707 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6708 /* XXX: might not be 66MHz */
2177832f 6709 intel_clock(dev, 66000, &clock);
79e53945 6710 } else
2177832f 6711 intel_clock(dev, 48000, &clock);
79e53945
JB		 6712 } else {
6713 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6714 clock.p1 = 2;
6715 else {
6716 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6717 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6718 }
6719 if (dpll & PLL_P2_DIVIDE_BY_4)
6720 clock.p2 = 4;
6721 else
6722 clock.p2 = 2;
6723
2177832f 6724 intel_clock(dev, 48000, &clock);
79e53945
JB		 6725 }
6726 }
6727
6728 /* XXX: It would be nice to validate the clocks, but we can't reuse
6729 * i830PllIsValid() because it relies on the xf86_config connector
6730 * configuration being accurate, which it isn't necessarily.
6731 */
6732
6733 return clock.dot;
6734}
6735
6736/** Returns the currently programmed mode of the given pipe. */
6737struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6738 struct drm_crtc *crtc)
6739{
548f245b 6740 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6742 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6743 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6744 int htot = I915_READ(HTOTAL(cpu_transcoder));
6745 int hsync = I915_READ(HSYNC(cpu_transcoder));
6746 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6747 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6748
6749 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6750 if (!mode)
6751 return NULL;
6752
6753 mode->clock = intel_crtc_clock_get(dev, crtc);
6754 mode->hdisplay = (htot & 0xffff) + 1;
6755 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6756 mode->hsync_start = (hsync & 0xffff) + 1;
6757 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6758 mode->vdisplay = (vtot & 0xffff) + 1;
6759 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6760 mode->vsync_start = (vsync & 0xffff) + 1;
6761 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6762
6763 drm_mode_set_name(mode);
79e53945
JB		 6764
6765 return mode;
6766}
6767
3dec0095 6768static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6769{
6770 struct drm_device *dev = crtc->dev;
6771 drm_i915_private_t *dev_priv = dev->dev_private;
6772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6773 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6774 int dpll_reg = DPLL(pipe);
6775 int dpll;
652c393a 6776
bad720ff 6777 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6778 return;
6779
6780 if (!dev_priv->lvds_downclock_avail)
6781 return;
6782
dbdc6479 6783 dpll = I915_READ(dpll_reg);
652c393a 6784 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6785 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6786
8ac5a6d5 6787 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6788
6789 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6790 I915_WRITE(dpll_reg, dpll);
9d0498a2 6791 intel_wait_for_vblank(dev, pipe);
dbdc6479 6792
652c393a
JB		 6793 dpll = I915_READ(dpll_reg);
6794 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6795 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6796 }
652c393a
JB		 6797}
6798
6799static void intel_decrease_pllclock(struct drm_crtc *crtc)
6800{
6801 struct drm_device *dev = crtc->dev;
6802 drm_i915_private_t *dev_priv = dev->dev_private;
6803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6804
bad720ff 6805 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6806 return;
6807
6808 if (!dev_priv->lvds_downclock_avail)
6809 return;
6810
6811 /*
6812 * Since this is called by a timer, we should never get here in
6813 * the manual case.
6814 */
6815 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6816 int pipe = intel_crtc->pipe;
6817 int dpll_reg = DPLL(pipe);
6818 int dpll;
f6e5b160 6819
44d98a61 6820 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6821
8ac5a6d5 6822 assert_panel_unlocked(dev_priv, pipe);
652c393a 6823
dc257cf1 6824 dpll = I915_READ(dpll_reg);
652c393a
JB		 6825 dpll |= DISPLAY_RATE_SELECT_FPA1;
6826 I915_WRITE(dpll_reg, dpll);
9d0498a2 6827 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6828 dpll = I915_READ(dpll_reg);
6829 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6830 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6831 }
6832
6833}
6834
f047e395
CW		 6835void intel_mark_busy(struct drm_device *dev)
6836{
f047e395
CW		 6837 i915_update_gfx_val(dev->dev_private);
6838}
6839
6840void intel_mark_idle(struct drm_device *dev)
652c393a 6841{
f047e395
CW		 6842}
6843
6844void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6845{
6846 struct drm_device *dev = obj->base.dev;
652c393a 6847 struct drm_crtc *crtc;
652c393a
JB		 6848
6849 if (!i915_powersave)
6850 return;
6851
652c393a 6852 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6853 if (!crtc->fb)
6854 continue;
6855
f047e395
CW		 6856 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6857 intel_increase_pllclock(crtc);
652c393a 6858 }
652c393a
JB		 6859}
6860
f047e395 6861void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6862{
f047e395
CW		 6863 struct drm_device *dev = obj->base.dev;
6864 struct drm_crtc *crtc;
652c393a 6865
f047e395 6866 if (!i915_powersave)
acb87dfb
CW		 6867 return;
6868
652c393a
JB		 6869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6870 if (!crtc->fb)
6871 continue;
6872
f047e395
CW		 6873 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6874 intel_decrease_pllclock(crtc);
652c393a
JB		 6875 }
6876}
6877
79e53945
JB		 6878static void intel_crtc_destroy(struct drm_crtc *crtc)
6879{
6880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6881 struct drm_device *dev = crtc->dev;
6882 struct intel_unpin_work *work;
6883 unsigned long flags;
6884
6885 spin_lock_irqsave(&dev->event_lock, flags);
6886 work = intel_crtc->unpin_work;
6887 intel_crtc->unpin_work = NULL;
6888 spin_unlock_irqrestore(&dev->event_lock, flags);
6889
6890 if (work) {
6891 cancel_work_sync(&work->work);
6892 kfree(work);
6893 }
79e53945
JB		 6894
6895 drm_crtc_cleanup(crtc);
67e77c5a 6896
79e53945
JB		 6897 kfree(intel_crtc);
6898}
6899
6b95a207
KH		 6900static void intel_unpin_work_fn(struct work_struct *__work)
6901{
6902 struct intel_unpin_work *work =
6903 container_of(__work, struct intel_unpin_work, work);
6904
6905 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6906 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6907 drm_gem_object_unreference(&work->pending_flip_obj->base);
6908 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6909
7782de3b 6910 intel_update_fbc(work->dev);
6b95a207
KH		 6911 mutex_unlock(&work->dev->struct_mutex);
6912 kfree(work);
6913}
6914
1afe3e9d 6915static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6916 struct drm_crtc *crtc)
6b95a207
KH		 6917{
6918 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920 struct intel_unpin_work *work;
05394f39 6921 struct drm_i915_gem_object *obj;
6b95a207 6922 struct drm_pending_vblank_event *e;
95cb1b02 6923 struct timeval tvbl;
6b95a207
KH		 6924 unsigned long flags;
6925
6926 /* Ignore early vblank irqs */
6927 if (intel_crtc == NULL)
6928 return;
6929
6930 spin_lock_irqsave(&dev->event_lock, flags);
6931 work = intel_crtc->unpin_work;
6932 if (work == NULL || !work->pending) {
6933 spin_unlock_irqrestore(&dev->event_lock, flags);
6934 return;
6935 }
6936
6937 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6938
6939 if (work->event) {
6940 e = work->event;
49b14a5c 6941 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6942
49b14a5c
MK		 6943 e->event.tv_sec = tvbl.tv_sec;
6944 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6945
6b95a207
KH		 6946 list_add_tail(&e->base.link,
6947 &e->base.file_priv->event_list);
6948 wake_up_interruptible(&e->base.file_priv->event_wait);
6949 }
6950
0af7e4df
MK		 6951 drm_vblank_put(dev, intel_crtc->pipe);
6952
6b95a207
KH		 6953 spin_unlock_irqrestore(&dev->event_lock, flags);
6954
05394f39 6955 obj = work->old_fb_obj;
d9e86c0e 6956
e59f2bac 6957 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6958 &obj->pending_flip.counter);
d9e86c0e 6959
5bb61643 6960 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6961 schedule_work(&work->work);
e5510fac
JB		 6962
6963 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6964}
6965
1afe3e9d
JB		 6966void intel_finish_page_flip(struct drm_device *dev, int pipe)
6967{
6968 drm_i915_private_t *dev_priv = dev->dev_private;
6969 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6970
49b14a5c 6971 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6972}
6973
6974void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6975{
6976 drm_i915_private_t *dev_priv = dev->dev_private;
6977 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6978
49b14a5c 6979 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6980}
6981
6b95a207
KH		 6982void intel_prepare_page_flip(struct drm_device *dev, int plane)
6983{
6984 drm_i915_private_t *dev_priv = dev->dev_private;
6985 struct intel_crtc *intel_crtc =
6986 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6987 unsigned long flags;
6988
6989 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6990 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6991 if ((++intel_crtc->unpin_work->pending) > 1)
6992 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6993 } else {
6994 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6995 }
6b95a207
KH		 6996 spin_unlock_irqrestore(&dev->event_lock, flags);
6997}
6998
8c9f3aaf
JB		 6999static int intel_gen2_queue_flip(struct drm_device *dev,
7000 struct drm_crtc *crtc,
7001 struct drm_framebuffer *fb,
7002 struct drm_i915_gem_object *obj)
7003{
7004 struct drm_i915_private *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7006 u32 flip_mask;
6d90c952 7007 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7008 int ret;
7009
6d90c952 7010 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7011 if (ret)
83d4092b 7012 goto err;
8c9f3aaf 7013
6d90c952 7014 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7015 if (ret)
83d4092b 7016 goto err_unpin;
8c9f3aaf
JB		 7017
7018 /* Can't queue multiple flips, so wait for the previous
7019 * one to finish before executing the next.
7020 */
7021 if (intel_crtc->plane)
7022 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7023 else
7024 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7025 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7026 intel_ring_emit(ring, MI_NOOP);
7027 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7028 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7029 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7030 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7031 intel_ring_emit(ring, 0); /* aux display base address, unused */
7032 intel_ring_advance(ring);
83d4092b
CW		 7033 return 0;
7034
7035err_unpin:
7036 intel_unpin_fb_obj(obj);
7037err:
8c9f3aaf
JB		 7038 return ret;
7039}
7040
7041static int intel_gen3_queue_flip(struct drm_device *dev,
7042 struct drm_crtc *crtc,
7043 struct drm_framebuffer *fb,
7044 struct drm_i915_gem_object *obj)
7045{
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7048 u32 flip_mask;
6d90c952 7049 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7050 int ret;
7051
6d90c952 7052 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7053 if (ret)
83d4092b 7054 goto err;
8c9f3aaf 7055
6d90c952 7056 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7057 if (ret)
83d4092b 7058 goto err_unpin;
8c9f3aaf
JB		 7059
7060 if (intel_crtc->plane)
7061 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7062 else
7063 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7064 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7065 intel_ring_emit(ring, MI_NOOP);
7066 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7068 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7069 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7070 intel_ring_emit(ring, MI_NOOP);
7071
7072 intel_ring_advance(ring);
83d4092b
CW		 7073 return 0;
7074
7075err_unpin:
7076 intel_unpin_fb_obj(obj);
7077err:
8c9f3aaf
JB		 7078 return ret;
7079}
7080
7081static int intel_gen4_queue_flip(struct drm_device *dev,
7082 struct drm_crtc *crtc,
7083 struct drm_framebuffer *fb,
7084 struct drm_i915_gem_object *obj)
7085{
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7088 uint32_t pf, pipesrc;
6d90c952 7089 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7090 int ret;
7091
6d90c952 7092 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7093 if (ret)
83d4092b 7094 goto err;
8c9f3aaf 7095
6d90c952 7096 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7097 if (ret)
83d4092b 7098 goto err_unpin;
8c9f3aaf
JB		 7099
7100 /* i965+ uses the linear or tiled offsets from the
7101 * Display Registers (which do not change across a page-flip)
7102 * so we need only reprogram the base address.
7103 */
6d90c952
DV		 7104 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7105 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7106 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7107 intel_ring_emit(ring,
7108 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7109 obj->tiling_mode);
8c9f3aaf
JB		 7110
7111 /* XXX Enabling the panel-fitter across page-flip is so far
7112 * untested on non-native modes, so ignore it for now.
7113 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7114 */
7115 pf = 0;
7116 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7117 intel_ring_emit(ring, pf | pipesrc);
7118 intel_ring_advance(ring);
83d4092b
CW		 7119 return 0;
7120
7121err_unpin:
7122 intel_unpin_fb_obj(obj);
7123err:
8c9f3aaf
JB		 7124 return ret;
7125}
7126
7127static int intel_gen6_queue_flip(struct drm_device *dev,
7128 struct drm_crtc *crtc,
7129 struct drm_framebuffer *fb,
7130 struct drm_i915_gem_object *obj)
7131{
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7134 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7135 uint32_t pf, pipesrc;
7136 int ret;
7137
6d90c952 7138 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7139 if (ret)
83d4092b 7140 goto err;
8c9f3aaf 7141
6d90c952 7142 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7143 if (ret)
83d4092b 7144 goto err_unpin;
8c9f3aaf 7145
6d90c952
DV		 7146 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7147 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7148 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7149 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7150
dc257cf1
DV		 7151 /* Contrary to the suggestions in the documentation,
7152 * "Enable Panel Fitter" does not seem to be required when page
7153 * flipping with a non-native mode, and worse causes a normal
7154 * modeset to fail.
7155 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7156 */
7157 pf = 0;
8c9f3aaf 7158 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7159 intel_ring_emit(ring, pf | pipesrc);
7160 intel_ring_advance(ring);
83d4092b
CW		 7161 return 0;
7162
7163err_unpin:
7164 intel_unpin_fb_obj(obj);
7165err:
8c9f3aaf
JB		 7166 return ret;
7167}
7168
7c9017e5
JB		 7169/*
7170 * On gen7 we currently use the blit ring because (in early silicon at least)
7171 * the render ring doesn't give us interrpts for page flip completion, which
7172 * means clients will hang after the first flip is queued. Fortunately the
7173 * blit ring generates interrupts properly, so use it instead.
7174 */
7175static int intel_gen7_queue_flip(struct drm_device *dev,
7176 struct drm_crtc *crtc,
7177 struct drm_framebuffer *fb,
7178 struct drm_i915_gem_object *obj)
7179{
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7182 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7183 uint32_t plane_bit = 0;
7c9017e5
JB		 7184 int ret;
7185
7186 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7187 if (ret)
83d4092b 7188 goto err;
7c9017e5 7189
cb05d8de
DV		 7190 switch(intel_crtc->plane) {
7191 case PLANE_A:
7192 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7193 break;
7194 case PLANE_B:
7195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7196 break;
7197 case PLANE_C:
7198 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7199 break;
7200 default:
7201 WARN_ONCE(1, "unknown plane in flip command\n");
7202 ret = -ENODEV;
ab3951eb 7203 goto err_unpin;
cb05d8de
DV		 7204 }
7205
7c9017e5
JB		 7206 ret = intel_ring_begin(ring, 4);
7207 if (ret)
83d4092b 7208 goto err_unpin;
7c9017e5 7209
cb05d8de 7210 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7211 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7212 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7213 intel_ring_emit(ring, (MI_NOOP));
7214 intel_ring_advance(ring);
83d4092b
CW		 7215 return 0;
7216
7217err_unpin:
7218 intel_unpin_fb_obj(obj);
7219err:
7c9017e5
JB		 7220 return ret;
7221}
7222
8c9f3aaf
JB		 7223static int intel_default_queue_flip(struct drm_device *dev,
7224 struct drm_crtc *crtc,
7225 struct drm_framebuffer *fb,
7226 struct drm_i915_gem_object *obj)
7227{
7228 return -ENODEV;
7229}
7230
6b95a207
KH		 7231static int intel_crtc_page_flip(struct drm_crtc *crtc,
7232 struct drm_framebuffer *fb,
7233 struct drm_pending_vblank_event *event)
7234{
7235 struct drm_device *dev = crtc->dev;
7236 struct drm_i915_private *dev_priv = dev->dev_private;
7237 struct intel_framebuffer *intel_fb;
05394f39 7238 struct drm_i915_gem_object *obj;
6b95a207
KH		 7239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7240 struct intel_unpin_work *work;
8c9f3aaf 7241 unsigned long flags;
52e68630 7242 int ret;
6b95a207 7243
e6a595d2
VS		 7244 /* Can't change pixel format via MI display flips. */
7245 if (fb->pixel_format != crtc->fb->pixel_format)
7246 return -EINVAL;
7247
7248 /*
7249 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7250 * Note that pitch changes could also affect these register.
7251 */
7252 if (INTEL_INFO(dev)->gen > 3 &&
7253 (fb->offsets[0] != crtc->fb->offsets[0] ||
7254 fb->pitches[0] != crtc->fb->pitches[0]))
7255 return -EINVAL;
7256
6b95a207
KH		 7257 work = kzalloc(sizeof *work, GFP_KERNEL);
7258 if (work == NULL)
7259 return -ENOMEM;
7260
6b95a207
KH		 7261 work->event = event;
7262 work->dev = crtc->dev;
7263 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7264 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7265 INIT_WORK(&work->work, intel_unpin_work_fn);
7266
7317c75e
JB		 7267 ret = drm_vblank_get(dev, intel_crtc->pipe);
7268 if (ret)
7269 goto free_work;
7270
6b95a207
KH		 7271 /* We borrow the event spin lock for protecting unpin_work */
7272 spin_lock_irqsave(&dev->event_lock, flags);
7273 if (intel_crtc->unpin_work) {
7274 spin_unlock_irqrestore(&dev->event_lock, flags);
7275 kfree(work);
7317c75e 7276 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7277
7278 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7279 return -EBUSY;
7280 }
7281 intel_crtc->unpin_work = work;
7282 spin_unlock_irqrestore(&dev->event_lock, flags);
7283
7284 intel_fb = to_intel_framebuffer(fb);
7285 obj = intel_fb->obj;
7286
79158103
CW		 7287 ret = i915_mutex_lock_interruptible(dev);
7288 if (ret)
7289 goto cleanup;
6b95a207 7290
75dfca80 7291 /* Reference the objects for the scheduled work. */
05394f39
CW		 7292 drm_gem_object_reference(&work->old_fb_obj->base);
7293 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7294
7295 crtc->fb = fb;
96b099fd 7296
e1f99ce6 7297 work->pending_flip_obj = obj;
e1f99ce6 7298
4e5359cd
SF		 7299 work->enable_stall_check = true;
7300
e1f99ce6
CW		 7301 /* Block clients from rendering to the new back buffer until
7302 * the flip occurs and the object is no longer visible.
7303 */
05394f39 7304 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7305
8c9f3aaf
JB		 7306 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7307 if (ret)
7308 goto cleanup_pending;
6b95a207 7309
7782de3b 7310 intel_disable_fbc(dev);
f047e395 7311 intel_mark_fb_busy(obj);
6b95a207
KH		 7312 mutex_unlock(&dev->struct_mutex);
7313
e5510fac
JB		 7314 trace_i915_flip_request(intel_crtc->plane, obj);
7315
6b95a207 7316 return 0;
96b099fd 7317
8c9f3aaf
JB		 7318cleanup_pending:
7319 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7320 drm_gem_object_unreference(&work->old_fb_obj->base);
7321 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7322 mutex_unlock(&dev->struct_mutex);
7323
79158103 7324cleanup:
96b099fd
CW		 7325 spin_lock_irqsave(&dev->event_lock, flags);
7326 intel_crtc->unpin_work = NULL;
7327 spin_unlock_irqrestore(&dev->event_lock, flags);
7328
7317c75e
JB		 7329 drm_vblank_put(dev, intel_crtc->pipe);
7330free_work:
96b099fd
CW		 7331 kfree(work);
7332
7333 return ret;
6b95a207
KH		 7334}
7335
f6e5b160 7336static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7337 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7338 .load_lut = intel_crtc_load_lut,
976f8a20 7339 .disable = intel_crtc_noop,
f6e5b160
CW		 7340};
7341
6ed0f796 7342bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7343{
6ed0f796
DV		 7344 struct intel_encoder *other_encoder;
7345 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7346
6ed0f796
DV		 7347 if (WARN_ON(!crtc))
7348 return false;
7349
7350 list_for_each_entry(other_encoder,
7351 &crtc->dev->mode_config.encoder_list,
7352 base.head) {
7353
7354 if (&other_encoder->new_crtc->base != crtc ||
7355 encoder == other_encoder)
7356 continue;
7357 else
7358 return true;
f47166d2
CW		 7359 }
7360
6ed0f796
DV		 7361 return false;
7362}
47f1c6c9 7363
50f56119
DV		 7364static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7365 struct drm_crtc *crtc)
7366{
7367 struct drm_device *dev;
7368 struct drm_crtc *tmp;
7369 int crtc_mask = 1;
47f1c6c9 7370
50f56119 7371 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7372
50f56119 7373 dev = crtc->dev;
47f1c6c9 7374
50f56119
DV		 7375 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7376 if (tmp == crtc)
7377 break;
7378 crtc_mask <<= 1;
7379 }
47f1c6c9 7380
50f56119
DV		 7381 if (encoder->possible_crtcs & crtc_mask)
7382 return true;
7383 return false;
47f1c6c9 7384}
79e53945 7385
9a935856
DV		 7386/**
7387 * intel_modeset_update_staged_output_state
7388 *
7389 * Updates the staged output configuration state, e.g. after we've read out the
7390 * current hw state.
7391 */
7392static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7393{
9a935856
DV		 7394 struct intel_encoder *encoder;
7395 struct intel_connector *connector;
f6e5b160 7396
9a935856
DV		 7397 list_for_each_entry(connector, &dev->mode_config.connector_list,
7398 base.head) {
7399 connector->new_encoder =
7400 to_intel_encoder(connector->base.encoder);
7401 }
f6e5b160 7402
9a935856
DV		 7403 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7404 base.head) {
7405 encoder->new_crtc =
7406 to_intel_crtc(encoder->base.crtc);
7407 }
f6e5b160
CW		 7408}
7409
9a935856
DV		 7410/**
7411 * intel_modeset_commit_output_state
7412 *
7413 * This function copies the stage display pipe configuration to the real one.
7414 */
7415static void intel_modeset_commit_output_state(struct drm_device *dev)
7416{
7417 struct intel_encoder *encoder;
7418 struct intel_connector *connector;
f6e5b160 7419
9a935856
DV		 7420 list_for_each_entry(connector, &dev->mode_config.connector_list,
7421 base.head) {
7422 connector->base.encoder = &connector->new_encoder->base;
7423 }
f6e5b160 7424
9a935856
DV		 7425 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7426 base.head) {
7427 encoder->base.crtc = &encoder->new_crtc->base;
7428 }
7429}
7430
7758a113
DV		 7431static struct drm_display_mode *
7432intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7433 struct drm_display_mode *mode)
ee7b9f93 7434{
7758a113
DV		 7435 struct drm_device *dev = crtc->dev;
7436 struct drm_display_mode *adjusted_mode;
7437 struct drm_encoder_helper_funcs *encoder_funcs;
7438 struct intel_encoder *encoder;
ee7b9f93 7439
7758a113
DV		 7440 adjusted_mode = drm_mode_duplicate(dev, mode);
7441 if (!adjusted_mode)
7442 return ERR_PTR(-ENOMEM);
7443
7444 /* Pass our mode to the connectors and the CRTC to give them a chance to
7445 * adjust it according to limitations or connector properties, and also
7446 * a chance to reject the mode entirely.
7447 */
7448 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7449 base.head) {
7450
7451 if (&encoder->new_crtc->base != crtc)
7452 continue;
7453 encoder_funcs = encoder->base.helper_private;
7454 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7455 adjusted_mode))) {
7456 DRM_DEBUG_KMS("Encoder fixup failed\n");
7457 goto fail;
7458 }
ee7b9f93
JB		 7459 }
7460
7758a113
DV		 7461 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7462 DRM_DEBUG_KMS("CRTC fixup failed\n");
7463 goto fail;
ee7b9f93 7464 }
7758a113
DV		 7465 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7466
7467 return adjusted_mode;
7468fail:
7469 drm_mode_destroy(dev, adjusted_mode);
7470 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7471}
7472
e2e1ed41
DV		 7473/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7474 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7475static void
7476intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7477 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7478{
7479 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7480 struct drm_device *dev = crtc->dev;
7481 struct intel_encoder *encoder;
7482 struct intel_connector *connector;
7483 struct drm_crtc *tmp_crtc;
79e53945 7484
e2e1ed41 7485 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7486
e2e1ed41
DV		 7487 /* Check which crtcs have changed outputs connected to them, these need
7488 * to be part of the prepare_pipes mask. We don't (yet) support global
7489 * modeset across multiple crtcs, so modeset_pipes will only have one
7490 * bit set at most. */
7491 list_for_each_entry(connector, &dev->mode_config.connector_list,
7492 base.head) {
7493 if (connector->base.encoder == &connector->new_encoder->base)
7494 continue;
79e53945 7495
e2e1ed41
DV		 7496 if (connector->base.encoder) {
7497 tmp_crtc = connector->base.encoder->crtc;
7498
7499 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7500 }
7501
7502 if (connector->new_encoder)
7503 *prepare_pipes |=
7504 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7505 }
7506
e2e1ed41
DV		 7507 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7508 base.head) {
7509 if (encoder->base.crtc == &encoder->new_crtc->base)
7510 continue;
7511
7512 if (encoder->base.crtc) {
7513 tmp_crtc = encoder->base.crtc;
7514
7515 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7516 }
7517
7518 if (encoder->new_crtc)
7519 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7520 }
7521
e2e1ed41
DV		 7522 /* Check for any pipes that will be fully disabled ... */
7523 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7524 base.head) {
7525 bool used = false;
22fd0fab 7526
e2e1ed41
DV		 7527 /* Don't try to disable disabled crtcs. */
7528 if (!intel_crtc->base.enabled)
7529 continue;
7e7d76c3 7530
e2e1ed41
DV		 7531 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7532 base.head) {
7533 if (encoder->new_crtc == intel_crtc)
7534 used = true;
7535 }
7536
7537 if (!used)
7538 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7539 }
7540
e2e1ed41
DV		 7541
7542 /* set_mode is also used to update properties on life display pipes. */
7543 intel_crtc = to_intel_crtc(crtc);
7544 if (crtc->enabled)
7545 *prepare_pipes |= 1 << intel_crtc->pipe;
7546
7547 /* We only support modeset on one single crtc, hence we need to do that
7548 * only for the passed in crtc iff we change anything else than just
7549 * disable crtcs.
7550 *
7551 * This is actually not true, to be fully compatible with the old crtc
7552 * helper we automatically disable _any_ output (i.e. doesn't need to be
7553 * connected to the crtc we're modesetting on) if it's disconnected.
7554 * Which is a rather nutty api (since changed the output configuration
7555 * without userspace's explicit request can lead to confusion), but
7556 * alas. Hence we currently need to modeset on all pipes we prepare. */
7557 if (*prepare_pipes)
7558 *modeset_pipes = *prepare_pipes;
7559
7560 /* ... and mask these out. */
7561 *modeset_pipes &= ~(*disable_pipes);
7562 *prepare_pipes &= ~(*disable_pipes);
7563}
7564
ea9d758d
DV		 7565static bool intel_crtc_in_use(struct drm_crtc *crtc)
7566{
7567 struct drm_encoder *encoder;
7568 struct drm_device *dev = crtc->dev;
7569
7570 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7571 if (encoder->crtc == crtc)
7572 return true;
7573
7574 return false;
7575}
7576
7577static void
7578intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7579{
7580 struct intel_encoder *intel_encoder;
7581 struct intel_crtc *intel_crtc;
7582 struct drm_connector *connector;
7583
7584 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7585 base.head) {
7586 if (!intel_encoder->base.crtc)
7587 continue;
7588
7589 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7590
7591 if (prepare_pipes & (1 << intel_crtc->pipe))
7592 intel_encoder->connectors_active = false;
7593 }
7594
7595 intel_modeset_commit_output_state(dev);
7596
7597 /* Update computed state. */
7598 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7599 base.head) {
7600 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7601 }
7602
7603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7604 if (!connector->encoder || !connector->encoder->crtc)
7605 continue;
7606
7607 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7608
7609 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7610 struct drm_property *dpms_property =
7611 dev->mode_config.dpms_property;
7612
ea9d758d 7613 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7614 drm_connector_property_set_value(connector,
7615 dpms_property,
7616 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7617
7618 intel_encoder = to_intel_encoder(connector->encoder);
7619 intel_encoder->connectors_active = true;
7620 }
7621 }
7622
7623}
7624
25c5b266
DV		 7625#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7626 list_for_each_entry((intel_crtc), \
7627 &(dev)->mode_config.crtc_list, \
7628 base.head) \
7629 if (mask & (1 <<(intel_crtc)->pipe)) \
7630
b980514c 7631void
8af6cf88
DV		 7632intel_modeset_check_state(struct drm_device *dev)
7633{
7634 struct intel_crtc *crtc;
7635 struct intel_encoder *encoder;
7636 struct intel_connector *connector;
7637
7638 list_for_each_entry(connector, &dev->mode_config.connector_list,
7639 base.head) {
7640 /* This also checks the encoder/connector hw state with the
7641 * ->get_hw_state callbacks. */
7642 intel_connector_check_state(connector);
7643
7644 WARN(&connector->new_encoder->base != connector->base.encoder,
7645 "connector's staged encoder doesn't match current encoder\n");
7646 }
7647
7648 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649 base.head) {
7650 bool enabled = false;
7651 bool active = false;
7652 enum pipe pipe, tracked_pipe;
7653
7654 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7655 encoder->base.base.id,
7656 drm_get_encoder_name(&encoder->base));
7657
7658 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7659 "encoder's stage crtc doesn't match current crtc\n");
7660 WARN(encoder->connectors_active && !encoder->base.crtc,
7661 "encoder's active_connectors set, but no crtc\n");
7662
7663 list_for_each_entry(connector, &dev->mode_config.connector_list,
7664 base.head) {
7665 if (connector->base.encoder != &encoder->base)
7666 continue;
7667 enabled = true;
7668 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7669 active = true;
7670 }
7671 WARN(!!encoder->base.crtc != enabled,
7672 "encoder's enabled state mismatch "
7673 "(expected %i, found %i)\n",
7674 !!encoder->base.crtc, enabled);
7675 WARN(active && !encoder->base.crtc,
7676 "active encoder with no crtc\n");
7677
7678 WARN(encoder->connectors_active != active,
7679 "encoder's computed active state doesn't match tracked active state "
7680 "(expected %i, found %i)\n", active, encoder->connectors_active);
7681
7682 active = encoder->get_hw_state(encoder, &pipe);
7683 WARN(active != encoder->connectors_active,
7684 "encoder's hw state doesn't match sw tracking "
7685 "(expected %i, found %i)\n",
7686 encoder->connectors_active, active);
7687
7688 if (!encoder->base.crtc)
7689 continue;
7690
7691 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7692 WARN(active && pipe != tracked_pipe,
7693 "active encoder's pipe doesn't match"
7694 "(expected %i, found %i)\n",
7695 tracked_pipe, pipe);
7696
7697 }
7698
7699 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7700 base.head) {
7701 bool enabled = false;
7702 bool active = false;
7703
7704 DRM_DEBUG_KMS("[CRTC:%d]\n",
7705 crtc->base.base.id);
7706
7707 WARN(crtc->active && !crtc->base.enabled,
7708 "active crtc, but not enabled in sw tracking\n");
7709
7710 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7711 base.head) {
7712 if (encoder->base.crtc != &crtc->base)
7713 continue;
7714 enabled = true;
7715 if (encoder->connectors_active)
7716 active = true;
7717 }
7718 WARN(active != crtc->active,
7719 "crtc's computed active state doesn't match tracked active state "
7720 "(expected %i, found %i)\n", active, crtc->active);
7721 WARN(enabled != crtc->base.enabled,
7722 "crtc's computed enabled state doesn't match tracked enabled state "
7723 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7724
7725 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7726 }
7727}
7728
a6778b3c
DV		 7729bool intel_set_mode(struct drm_crtc *crtc,
7730 struct drm_display_mode *mode,
94352cf9 7731 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7732{
7733 struct drm_device *dev = crtc->dev;
dbf2b54e 7734 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7735 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7736 struct intel_crtc *intel_crtc;
7737 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7738 bool ret = true;
7739
e2e1ed41 7740 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7741 &prepare_pipes, &disable_pipes);
7742
7743 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7744 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7745
976f8a20
DV		 7746 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7747 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7748
a6778b3c
DV		 7749 saved_hwmode = crtc->hwmode;
7750 saved_mode = crtc->mode;
a6778b3c 7751
25c5b266
DV		 7752 /* Hack: Because we don't (yet) support global modeset on multiple
7753 * crtcs, we don't keep track of the new mode for more than one crtc.
7754 * Hence simply check whether any bit is set in modeset_pipes in all the
7755 * pieces of code that are not yet converted to deal with mutliple crtcs
7756 * changing their mode at the same time. */
7757 adjusted_mode = NULL;
7758 if (modeset_pipes) {
7759 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7760 if (IS_ERR(adjusted_mode)) {
7761 return false;
7762 }
25c5b266 7763 }
a6778b3c 7764
ea9d758d
DV		 7765 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7766 if (intel_crtc->base.enabled)
7767 dev_priv->display.crtc_disable(&intel_crtc->base);
7768 }
a6778b3c 7769
6c4c86f5
DV		 7770 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7771 * to set it here already despite that we pass it down the callchain.
7772 */
7773 if (modeset_pipes)
25c5b266 7774 crtc->mode = *mode;
7758a113 7775
ea9d758d
DV		 7776 /* Only after disabling all output pipelines that will be changed can we
7777 * update the the output configuration. */
7778 intel_modeset_update_state(dev, prepare_pipes);
7779
47fab737
DV		 7780 if (dev_priv->display.modeset_global_resources)
7781 dev_priv->display.modeset_global_resources(dev);
7782
a6778b3c
DV		 7783 /* Set up the DPLL and any encoders state that needs to adjust or depend
7784 * on the DPLL.
7785 */
25c5b266
DV		 7786 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7787 ret = !intel_crtc_mode_set(&intel_crtc->base,
7788 mode, adjusted_mode,
7789 x, y, fb);
7790 if (!ret)
7791 goto done;
a6778b3c
DV		 7792 }
7793
7794 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7795 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7796 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7797
25c5b266
DV		 7798 if (modeset_pipes) {
7799 /* Store real post-adjustment hardware mode. */
7800 crtc->hwmode = *adjusted_mode;
a6778b3c 7801
25c5b266
DV		 7802 /* Calculate and store various constants which
7803 * are later needed by vblank and swap-completion
7804 * timestamping. They are derived from true hwmode.
7805 */
7806 drm_calc_timestamping_constants(crtc);
7807 }
a6778b3c
DV		 7808
7809 /* FIXME: add subpixel order */
7810done:
7811 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7812 if (!ret && crtc->enabled) {
a6778b3c
DV		 7813 crtc->hwmode = saved_hwmode;
7814 crtc->mode = saved_mode;
8af6cf88
DV		 7815 } else {
7816 intel_modeset_check_state(dev);
a6778b3c
DV		 7817 }
7818
7819 return ret;
7820}
7821
25c5b266
DV		 7822#undef for_each_intel_crtc_masked
7823
d9e55608
DV		 7824static void intel_set_config_free(struct intel_set_config *config)
7825{
7826 if (!config)
7827 return;
7828
1aa4b628
DV		 7829 kfree(config->save_connector_encoders);
7830 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7831 kfree(config);
7832}
7833
85f9eb71
DV		 7834static int intel_set_config_save_state(struct drm_device *dev,
7835 struct intel_set_config *config)
7836{
85f9eb71
DV		 7837 struct drm_encoder *encoder;
7838 struct drm_connector *connector;
7839 int count;
7840
1aa4b628
DV		 7841 config->save_encoder_crtcs =
7842 kcalloc(dev->mode_config.num_encoder,
7843 sizeof(struct drm_crtc *), GFP_KERNEL);
7844 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7845 return -ENOMEM;
7846
1aa4b628
DV		 7847 config->save_connector_encoders =
7848 kcalloc(dev->mode_config.num_connector,
7849 sizeof(struct drm_encoder *), GFP_KERNEL);
7850 if (!config->save_connector_encoders)
85f9eb71
DV		 7851 return -ENOMEM;
7852
7853 /* Copy data. Note that driver private data is not affected.
7854 * Should anything bad happen only the expected state is
7855 * restored, not the drivers personal bookkeeping.
7856 */
85f9eb71
DV		 7857 count = 0;
7858 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7859 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7860 }
7861
7862 count = 0;
7863 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7864 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7865 }
7866
7867 return 0;
7868}
7869
7870static void intel_set_config_restore_state(struct drm_device *dev,
7871 struct intel_set_config *config)
7872{
9a935856
DV		 7873 struct intel_encoder *encoder;
7874 struct intel_connector *connector;
85f9eb71
DV		 7875 int count;
7876
85f9eb71 7877 count = 0;
9a935856
DV		 7878 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7879 encoder->new_crtc =
7880 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7881 }
7882
7883 count = 0;
9a935856
DV		 7884 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7885 connector->new_encoder =
7886 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7887 }
7888}
7889
5e2b584e
DV		 7890static void
7891intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7892 struct intel_set_config *config)
7893{
7894
7895 /* We should be able to check here if the fb has the same properties
7896 * and then just flip_or_move it */
7897 if (set->crtc->fb != set->fb) {
7898 /* If we have no fb then treat it as a full mode set */
7899 if (set->crtc->fb == NULL) {
7900 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7901 config->mode_changed = true;
7902 } else if (set->fb == NULL) {
7903 config->mode_changed = true;
7904 } else if (set->fb->depth != set->crtc->fb->depth) {
7905 config->mode_changed = true;
7906 } else if (set->fb->bits_per_pixel !=
7907 set->crtc->fb->bits_per_pixel) {
7908 config->mode_changed = true;
7909 } else
7910 config->fb_changed = true;
7911 }
7912
835c5873 7913 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7914 config->fb_changed = true;
7915
7916 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7917 DRM_DEBUG_KMS("modes are different, full mode set\n");
7918 drm_mode_debug_printmodeline(&set->crtc->mode);
7919 drm_mode_debug_printmodeline(set->mode);
7920 config->mode_changed = true;
7921 }
7922}
7923
2e431051 7924static int
9a935856
DV		 7925intel_modeset_stage_output_state(struct drm_device *dev,
7926 struct drm_mode_set *set,
7927 struct intel_set_config *config)
50f56119 7928{
85f9eb71 7929 struct drm_crtc *new_crtc;
9a935856
DV		 7930 struct intel_connector *connector;
7931 struct intel_encoder *encoder;
2e431051 7932 int count, ro;
50f56119 7933
9a935856
DV		 7934 /* The upper layers ensure that we either disabl a crtc or have a list
7935 * of connectors. For paranoia, double-check this. */
7936 WARN_ON(!set->fb && (set->num_connectors != 0));
7937 WARN_ON(set->fb && (set->num_connectors == 0));
7938
50f56119 7939 count = 0;
9a935856
DV		 7940 list_for_each_entry(connector, &dev->mode_config.connector_list,
7941 base.head) {
7942 /* Otherwise traverse passed in connector list and get encoders
7943 * for them. */
50f56119 7944 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7945 if (set->connectors[ro] == &connector->base) {
7946 connector->new_encoder = connector->encoder;
50f56119
DV		 7947 break;
7948 }
7949 }
7950
9a935856
DV		 7951 /* If we disable the crtc, disable all its connectors. Also, if
7952 * the connector is on the changing crtc but not on the new
7953 * connector list, disable it. */
7954 if ((!set->fb || ro == set->num_connectors) &&
7955 connector->base.encoder &&
7956 connector->base.encoder->crtc == set->crtc) {
7957 connector->new_encoder = NULL;
7958
7959 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7960 connector->base.base.id,
7961 drm_get_connector_name(&connector->base));
7962 }
7963
7964
7965 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7966 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7967 config->mode_changed = true;
50f56119 7968 }
9a935856
DV		 7969
7970 /* Disable all disconnected encoders. */
7971 if (connector->base.status == connector_status_disconnected)
7972 connector->new_encoder = NULL;
50f56119 7973 }
9a935856 7974 /* connector->new_encoder is now updated for all connectors. */
50f56119 7975
9a935856 7976 /* Update crtc of enabled connectors. */
50f56119 7977 count = 0;
9a935856
DV		 7978 list_for_each_entry(connector, &dev->mode_config.connector_list,
7979 base.head) {
7980 if (!connector->new_encoder)
50f56119
DV		 7981 continue;
7982
9a935856 7983 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7984
7985 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7986 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7987 new_crtc = set->crtc;
7988 }
7989
7990 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7991 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7992 new_crtc)) {
5e2b584e 7993 return -EINVAL;
50f56119 7994 }
9a935856
DV		 7995 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7996
7997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7998 connector->base.base.id,
7999 drm_get_connector_name(&connector->base),
8000 new_crtc->base.id);
8001 }
8002
8003 /* Check for any encoders that needs to be disabled. */
8004 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8005 base.head) {
8006 list_for_each_entry(connector,
8007 &dev->mode_config.connector_list,
8008 base.head) {
8009 if (connector->new_encoder == encoder) {
8010 WARN_ON(!connector->new_encoder->new_crtc);
8011
8012 goto next_encoder;
8013 }
8014 }
8015 encoder->new_crtc = NULL;
8016next_encoder:
8017 /* Only now check for crtc changes so we don't miss encoders
8018 * that will be disabled. */
8019 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8020 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8021 config->mode_changed = true;
50f56119
DV		 8022 }
8023 }
9a935856 8024 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8025
2e431051
DV		 8026 return 0;
8027}
8028
8029static int intel_crtc_set_config(struct drm_mode_set *set)
8030{
8031 struct drm_device *dev;
2e431051
DV		 8032 struct drm_mode_set save_set;
8033 struct intel_set_config *config;
8034 int ret;
2e431051 8035
8d3e375e
DV		 8036 BUG_ON(!set);
8037 BUG_ON(!set->crtc);
8038 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8039
8040 if (!set->mode)
8041 set->fb = NULL;
8042
431e50f7
DV		 8043 /* The fb helper likes to play gross jokes with ->mode_set_config.
8044 * Unfortunately the crtc helper doesn't do much at all for this case,
8045 * so we have to cope with this madness until the fb helper is fixed up. */
8046 if (set->fb && set->num_connectors == 0)
8047 return 0;
8048
2e431051
DV		 8049 if (set->fb) {
8050 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8051 set->crtc->base.id, set->fb->base.id,
8052 (int)set->num_connectors, set->x, set->y);
8053 } else {
8054 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8055 }
8056
8057 dev = set->crtc->dev;
8058
8059 ret = -ENOMEM;
8060 config = kzalloc(sizeof(*config), GFP_KERNEL);
8061 if (!config)
8062 goto out_config;
8063
8064 ret = intel_set_config_save_state(dev, config);
8065 if (ret)
8066 goto out_config;
8067
8068 save_set.crtc = set->crtc;
8069 save_set.mode = &set->crtc->mode;
8070 save_set.x = set->crtc->x;
8071 save_set.y = set->crtc->y;
8072 save_set.fb = set->crtc->fb;
8073
8074 /* Compute whether we need a full modeset, only an fb base update or no
8075 * change at all. In the future we might also check whether only the
8076 * mode changed, e.g. for LVDS where we only change the panel fitter in
8077 * such cases. */
8078 intel_set_config_compute_mode_changes(set, config);
8079
9a935856 8080 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8081 if (ret)
8082 goto fail;
8083
5e2b584e 8084 if (config->mode_changed) {
87f1faa6 8085 if (set->mode) {
50f56119
DV		 8086 DRM_DEBUG_KMS("attempting to set mode from"
8087 " userspace\n");
8088 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8089 }
8090
8091 if (!intel_set_mode(set->crtc, set->mode,
8092 set->x, set->y, set->fb)) {
8093 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8094 set->crtc->base.id);
8095 ret = -EINVAL;
8096 goto fail;
8097 }
5e2b584e 8098 } else if (config->fb_changed) {
4f660f49 8099 ret = intel_pipe_set_base(set->crtc,
94352cf9 8100 set->x, set->y, set->fb);
50f56119
DV		 8101 }
8102
d9e55608
DV		 8103 intel_set_config_free(config);
8104
50f56119
DV		 8105 return 0;
8106
8107fail:
85f9eb71 8108 intel_set_config_restore_state(dev, config);
50f56119
DV		 8109
8110 /* Try to restore the config */
5e2b584e 8111 if (config->mode_changed &&
a6778b3c
DV		 8112 !intel_set_mode(save_set.crtc, save_set.mode,
8113 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8114 DRM_ERROR("failed to restore config after modeset failure\n");
8115
d9e55608
DV		 8116out_config:
8117 intel_set_config_free(config);
50f56119
DV		 8118 return ret;
8119}
8120
f6e5b160 8121static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8122 .cursor_set = intel_crtc_cursor_set,
8123 .cursor_move = intel_crtc_cursor_move,
8124 .gamma_set = intel_crtc_gamma_set,
50f56119 8125 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8126 .destroy = intel_crtc_destroy,
8127 .page_flip = intel_crtc_page_flip,
8128};
8129
79f689aa
PZ		 8130static void intel_cpu_pll_init(struct drm_device *dev)
8131{
8132 if (IS_HASWELL(dev))
8133 intel_ddi_pll_init(dev);
8134}
8135
ee7b9f93
JB		 8136static void intel_pch_pll_init(struct drm_device *dev)
8137{
8138 drm_i915_private_t *dev_priv = dev->dev_private;
8139 int i;
8140
8141 if (dev_priv->num_pch_pll == 0) {
8142 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8143 return;
8144 }
8145
8146 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8147 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8148 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8149 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8150 }
8151}
8152
b358d0a6 8153static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8154{
22fd0fab 8155 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8156 struct intel_crtc *intel_crtc;
8157 int i;
8158
8159 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8160 if (intel_crtc == NULL)
8161 return;
8162
8163 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8164
8165 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8166 for (i = 0; i < 256; i++) {
8167 intel_crtc->lut_r[i] = i;
8168 intel_crtc->lut_g[i] = i;
8169 intel_crtc->lut_b[i] = i;
8170 }
8171
80824003
JB		 8172 /* Swap pipes & planes for FBC on pre-965 */
8173 intel_crtc->pipe = pipe;
8174 intel_crtc->plane = pipe;
a5c961d1 8175 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8176 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8177 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8178 intel_crtc->plane = !pipe;
80824003
JB		 8179 }
8180
22fd0fab
JB		 8181 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8182 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8183 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8184 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8185
5a354204 8186 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8187
79e53945 8188 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8189}
8190
08d7b3d1 8191int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8192 struct drm_file *file)
08d7b3d1 8193{
08d7b3d1 8194 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8195 struct drm_mode_object *drmmode_obj;
8196 struct intel_crtc *crtc;
08d7b3d1 8197
1cff8f6b
DV		 8198 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8199 return -ENODEV;
08d7b3d1 8200
c05422d5
DV		 8201 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8202 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8203
c05422d5 8204 if (!drmmode_obj) {
08d7b3d1
CW		 8205 DRM_ERROR("no such CRTC id\n");
8206 return -EINVAL;
8207 }
8208
c05422d5
DV		 8209 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8210 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8211
c05422d5 8212 return 0;
08d7b3d1
CW		 8213}
8214
66a9278e 8215static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8216{
66a9278e
DV		 8217 struct drm_device *dev = encoder->base.dev;
8218 struct intel_encoder *source_encoder;
79e53945 8219 int index_mask = 0;
79e53945
JB		 8220 int entry = 0;
8221
66a9278e
DV		 8222 list_for_each_entry(source_encoder,
8223 &dev->mode_config.encoder_list, base.head) {
8224
8225 if (encoder == source_encoder)
79e53945 8226 index_mask |= (1 << entry);
66a9278e
DV		 8227
8228 /* Intel hw has only one MUX where enocoders could be cloned. */
8229 if (encoder->cloneable && source_encoder->cloneable)
8230 index_mask |= (1 << entry);
8231
79e53945
JB		 8232 entry++;
8233 }
4ef69c7a 8234
79e53945
JB		 8235 return index_mask;
8236}
8237
4d302442
CW		 8238static bool has_edp_a(struct drm_device *dev)
8239{
8240 struct drm_i915_private *dev_priv = dev->dev_private;
8241
8242 if (!IS_MOBILE(dev))
8243 return false;
8244
8245 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8246 return false;
8247
8248 if (IS_GEN5(dev) &&
8249 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8250 return false;
8251
8252 return true;
8253}
8254
79e53945
JB		 8255static void intel_setup_outputs(struct drm_device *dev)
8256{
725e30ad 8257 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8258 struct intel_encoder *encoder;
cb0953d7 8259 bool dpd_is_edp = false;
f3cfcba6 8260 bool has_lvds;
79e53945 8261
f3cfcba6 8262 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8263 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8264 /* disable the panel fitter on everything but LVDS */
8265 I915_WRITE(PFIT_CONTROL, 0);
8266 }
79e53945 8267
cb0953d7
AJ		 8268 intel_crt_init(dev);
8269
0e72a5b5
ED		 8270 if (IS_HASWELL(dev)) {
8271 int found;
8272
8273 /* Haswell uses DDI functions to detect digital outputs */
8274 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8275 /* DDI A only supports eDP */
8276 if (found)
8277 intel_ddi_init(dev, PORT_A);
8278
8279 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8280 * register */
8281 found = I915_READ(SFUSE_STRAP);
8282
8283 if (found & SFUSE_STRAP_DDIB_DETECTED)
8284 intel_ddi_init(dev, PORT_B);
8285 if (found & SFUSE_STRAP_DDIC_DETECTED)
8286 intel_ddi_init(dev, PORT_C);
8287 if (found & SFUSE_STRAP_DDID_DETECTED)
8288 intel_ddi_init(dev, PORT_D);
8289 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8290 int found;
270b3042
DV		 8291 dpd_is_edp = intel_dpd_is_edp(dev);
8292
8293 if (has_edp_a(dev))
8294 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8295
30ad48b7 8296 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8297 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8298 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8299 if (!found)
08d644ad 8300 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8301 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8302 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8303 }
8304
8305 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8306 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8307
b708a1d5 8308 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8309 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8310
5eb08b69 8311 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8312 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8313
270b3042 8314 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8315 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8316 } else if (IS_VALLEYVIEW(dev)) {
8317 int found;
8318
19c03924
GB		 8319 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8320 if (I915_READ(DP_C) & DP_DETECTED)
8321 intel_dp_init(dev, DP_C, PORT_C);
8322
4a87d65d
JB		 8323 if (I915_READ(SDVOB) & PORT_DETECTED) {
8324 /* SDVOB multiplex with HDMIB */
8325 found = intel_sdvo_init(dev, SDVOB, true);
8326 if (!found)
08d644ad 8327 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8328 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8329 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8330 }
8331
8332 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8333 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8334
103a196f 8335 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8336 bool found = false;
7d57382e 8337
725e30ad 8338 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8339 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8340 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8341 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8342 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8343 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8344 }
27185ae1 8345
b01f2c3a
JB		 8346 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8347 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8348 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8349 }
725e30ad 8350 }
13520b05
KH		 8351
8352 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8353
b01f2c3a
JB		 8354 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8355 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8356 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8357 }
27185ae1
ML		 8358
8359 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8360
b01f2c3a
JB		 8361 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8362 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8363 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8364 }
8365 if (SUPPORTS_INTEGRATED_DP(dev)) {
8366 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8367 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8368 }
725e30ad 8369 }
27185ae1 8370
b01f2c3a
JB		 8371 if (SUPPORTS_INTEGRATED_DP(dev) &&
8372 (I915_READ(DP_D) & DP_DETECTED)) {
8373 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8374 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8375 }
bad720ff 8376 } else if (IS_GEN2(dev))
79e53945
JB		 8377 intel_dvo_init(dev);
8378
103a196f 8379 if (SUPPORTS_TV(dev))
79e53945
JB		 8380 intel_tv_init(dev);
8381
4ef69c7a
CW		 8382 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8383 encoder->base.possible_crtcs = encoder->crtc_mask;
8384 encoder->base.possible_clones =
66a9278e 8385 intel_encoder_clones(encoder);
79e53945 8386 }
47356eb6 8387
40579abe 8388 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8389 ironlake_init_pch_refclk(dev);
270b3042
DV		 8390
8391 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8392}
8393
8394static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8395{
8396 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8397
8398 drm_framebuffer_cleanup(fb);
05394f39 8399 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8400
8401 kfree(intel_fb);
8402}
8403
8404static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8405 struct drm_file *file,
79e53945
JB		 8406 unsigned int *handle)
8407{
8408 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8409 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8410
05394f39 8411 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8412}
8413
8414static const struct drm_framebuffer_funcs intel_fb_funcs = {
8415 .destroy = intel_user_framebuffer_destroy,
8416 .create_handle = intel_user_framebuffer_create_handle,
8417};
8418
38651674
DA		 8419int intel_framebuffer_init(struct drm_device *dev,
8420 struct intel_framebuffer *intel_fb,
308e5bcb 8421 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8422 struct drm_i915_gem_object *obj)
79e53945 8423{
79e53945
JB		 8424 int ret;
8425
05394f39 8426 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8427 return -EINVAL;
8428
308e5bcb 8429 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8430 return -EINVAL;
8431
5d7bd705
VS		 8432 /* FIXME <= Gen4 stride limits are bit unclear */
8433 if (mode_cmd->pitches[0] > 32768)
8434 return -EINVAL;
8435
8436 if (obj->tiling_mode != I915_TILING_NONE &&
8437 mode_cmd->pitches[0] != obj->stride)
8438 return -EINVAL;
8439
57779d06 8440 /* Reject formats not supported by any plane early. */
308e5bcb 8441 switch (mode_cmd->pixel_format) {
57779d06 8442 case DRM_FORMAT_C8:
04b3924d
VS		 8443 case DRM_FORMAT_RGB565:
8444 case DRM_FORMAT_XRGB8888:
8445 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8446 break;
8447 case DRM_FORMAT_XRGB1555:
8448 case DRM_FORMAT_ARGB1555:
8449 if (INTEL_INFO(dev)->gen > 3)
8450 return -EINVAL;
8451 break;
8452 case DRM_FORMAT_XBGR8888:
8453 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8454 case DRM_FORMAT_XRGB2101010:
8455 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8456 case DRM_FORMAT_XBGR2101010:
8457 case DRM_FORMAT_ABGR2101010:
8458 if (INTEL_INFO(dev)->gen < 4)
8459 return -EINVAL;
b5626747 8460 break;
04b3924d
VS		 8461 case DRM_FORMAT_YUYV:
8462 case DRM_FORMAT_UYVY:
8463 case DRM_FORMAT_YVYU:
8464 case DRM_FORMAT_VYUY:
57779d06
VS		 8465 if (INTEL_INFO(dev)->gen < 6)
8466 return -EINVAL;
57cd6508
CW		 8467 break;
8468 default:
57779d06 8469 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8470 return -EINVAL;
8471 }
8472
90f9a336
VS		 8473 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8474 if (mode_cmd->offsets[0] != 0)
8475 return -EINVAL;
8476
79e53945
JB		 8477 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8478 if (ret) {
8479 DRM_ERROR("framebuffer init failed %d\n", ret);
8480 return ret;
8481 }
8482
8483 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8484 intel_fb->obj = obj;
79e53945
JB		 8485 return 0;
8486}
8487
79e53945
JB		 8488static struct drm_framebuffer *
8489intel_user_framebuffer_create(struct drm_device *dev,
8490 struct drm_file *filp,
308e5bcb 8491 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8492{
05394f39 8493 struct drm_i915_gem_object *obj;
79e53945 8494
308e5bcb
JB		 8495 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8496 mode_cmd->handles[0]));
c8725226 8497 if (&obj->base == NULL)
cce13ff7 8498 return ERR_PTR(-ENOENT);
79e53945 8499
d2dff872 8500 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8501}
8502
79e53945 8503static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8504 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8505 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8506};
8507
e70236a8
JB		 8508/* Set up chip specific display functions */
8509static void intel_init_display(struct drm_device *dev)
8510{
8511 struct drm_i915_private *dev_priv = dev->dev_private;
8512
8513 /* We always want a DPMS function */
09b4ddf9
PZ		 8514 if (IS_HASWELL(dev)) {
8515 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8516 dev_priv->display.crtc_enable = haswell_crtc_enable;
8517 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8518 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8519 dev_priv->display.update_plane = ironlake_update_plane;
8520 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8521 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8522 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8523 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8524 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8525 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8526 } else {
f564048e 8527 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8528 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8529 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8530 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8531 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8532 }
e70236a8 8533
e70236a8 8534 /* Returns the core display clock speed */
25eb05fc
JB		 8535 if (IS_VALLEYVIEW(dev))
8536 dev_priv->display.get_display_clock_speed =
8537 valleyview_get_display_clock_speed;
8538 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8539 dev_priv->display.get_display_clock_speed =
8540 i945_get_display_clock_speed;
8541 else if (IS_I915G(dev))
8542 dev_priv->display.get_display_clock_speed =
8543 i915_get_display_clock_speed;
f2b115e6 8544 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8545 dev_priv->display.get_display_clock_speed =
8546 i9xx_misc_get_display_clock_speed;
8547 else if (IS_I915GM(dev))
8548 dev_priv->display.get_display_clock_speed =
8549 i915gm_get_display_clock_speed;
8550 else if (IS_I865G(dev))
8551 dev_priv->display.get_display_clock_speed =
8552 i865_get_display_clock_speed;
f0f8a9ce 8553 else if (IS_I85X(dev))
e70236a8
JB		 8554 dev_priv->display.get_display_clock_speed =
8555 i855_get_display_clock_speed;
8556 else /* 852, 830 */
8557 dev_priv->display.get_display_clock_speed =
8558 i830_get_display_clock_speed;
8559
7f8a8569 8560 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8561 if (IS_GEN5(dev)) {
674cf967 8562 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8563 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8564 } else if (IS_GEN6(dev)) {
674cf967 8565 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8566 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8567 } else if (IS_IVYBRIDGE(dev)) {
8568 /* FIXME: detect B0+ stepping and use auto training */
8569 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8570 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8571 dev_priv->display.modeset_global_resources =
8572 ivb_modeset_global_resources;
c82e4d26
ED		 8573 } else if (IS_HASWELL(dev)) {
8574 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8575 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8576 } else
8577 dev_priv->display.update_wm = NULL;
6067aaea 8578 } else if (IS_G4X(dev)) {
e0dac65e 8579 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8580 }
8c9f3aaf
JB		 8581
8582 /* Default just returns -ENODEV to indicate unsupported */
8583 dev_priv->display.queue_flip = intel_default_queue_flip;
8584
8585 switch (INTEL_INFO(dev)->gen) {
8586 case 2:
8587 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8588 break;
8589
8590 case 3:
8591 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8592 break;
8593
8594 case 4:
8595 case 5:
8596 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8597 break;
8598
8599 case 6:
8600 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8601 break;
7c9017e5
JB		 8602 case 7:
8603 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8604 break;
8c9f3aaf 8605 }
e70236a8
JB		 8606}
8607
b690e96c
JB		 8608/*
8609 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8610 * resume, or other times. This quirk makes sure that's the case for
8611 * affected systems.
8612 */
0206e353 8613static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8614{
8615 struct drm_i915_private *dev_priv = dev->dev_private;
8616
8617 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8618 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8619}
8620
435793df
KP		 8621/*
8622 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8623 */
8624static void quirk_ssc_force_disable(struct drm_device *dev)
8625{
8626 struct drm_i915_private *dev_priv = dev->dev_private;
8627 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8628 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8629}
8630
4dca20ef 8631/*
5a15ab5b
CE		 8632 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8633 * brightness value
4dca20ef
CE		 8634 */
8635static void quirk_invert_brightness(struct drm_device *dev)
8636{
8637 struct drm_i915_private *dev_priv = dev->dev_private;
8638 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8639 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8640}
8641
b690e96c
JB		 8642struct intel_quirk {
8643 int device;
8644 int subsystem_vendor;
8645 int subsystem_device;
8646 void (*hook)(struct drm_device *dev);
8647};
8648
c43b5634 8649static struct intel_quirk intel_quirks[] = {
b690e96c 8650 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8651 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8652
b690e96c
JB		 8653 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8654 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8655
b690e96c
JB		 8656 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8657 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8658
ccd0d36e 8659 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8660 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8661 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8662
8663 /* Lenovo U160 cannot use SSC on LVDS */
8664 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8665
8666 /* Sony Vaio Y cannot use SSC on LVDS */
8667 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8668
8669 /* Acer Aspire 5734Z must invert backlight brightness */
8670 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8671};
8672
8673static void intel_init_quirks(struct drm_device *dev)
8674{
8675 struct pci_dev *d = dev->pdev;
8676 int i;
8677
8678 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8679 struct intel_quirk *q = &intel_quirks[i];
8680
8681 if (d->device == q->device &&
8682 (d->subsystem_vendor == q->subsystem_vendor ||
8683 q->subsystem_vendor == PCI_ANY_ID) &&
8684 (d->subsystem_device == q->subsystem_device ||
8685 q->subsystem_device == PCI_ANY_ID))
8686 q->hook(dev);
8687 }
8688}
8689
9cce37f4
JB		 8690/* Disable the VGA plane that we never use */
8691static void i915_disable_vga(struct drm_device *dev)
8692{
8693 struct drm_i915_private *dev_priv = dev->dev_private;
8694 u8 sr1;
8695 u32 vga_reg;
8696
8697 if (HAS_PCH_SPLIT(dev))
8698 vga_reg = CPU_VGACNTRL;
8699 else
8700 vga_reg = VGACNTRL;
8701
8702 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8703 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8704 sr1 = inb(VGA_SR_DATA);
8705 outb(sr1 | 1<<5, VGA_SR_DATA);
8706 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8707 udelay(300);
8708
8709 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8710 POSTING_READ(vga_reg);
8711}
8712
f817586c
DV		 8713void intel_modeset_init_hw(struct drm_device *dev)
8714{
0232e927
ED		 8715 /* We attempt to init the necessary power wells early in the initialization
8716 * time, so the subsystems that expect power to be enabled can work.
8717 */
8718 intel_init_power_wells(dev);
8719
a8f78b58
ED		 8720 intel_prepare_ddi(dev);
8721
f817586c
DV		 8722 intel_init_clock_gating(dev);
8723
79f5b2c7 8724 mutex_lock(&dev->struct_mutex);
8090c6b9 8725 intel_enable_gt_powersave(dev);
79f5b2c7 8726 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8727}
8728
79e53945
JB		 8729void intel_modeset_init(struct drm_device *dev)
8730{
652c393a 8731 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8732 int i, ret;
79e53945
JB		 8733
8734 drm_mode_config_init(dev);
8735
8736 dev->mode_config.min_width = 0;
8737 dev->mode_config.min_height = 0;
8738
019d96cb
DA		 8739 dev->mode_config.preferred_depth = 24;
8740 dev->mode_config.prefer_shadow = 1;
8741
e6ecefaa 8742 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8743
b690e96c
JB		 8744 intel_init_quirks(dev);
8745
1fa61106
ED		 8746 intel_init_pm(dev);
8747
e70236a8
JB		 8748 intel_init_display(dev);
8749
a6c45cf0
CW		 8750 if (IS_GEN2(dev)) {
8751 dev->mode_config.max_width = 2048;
8752 dev->mode_config.max_height = 2048;
8753 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8754 dev->mode_config.max_width = 4096;
8755 dev->mode_config.max_height = 4096;
79e53945 8756 } else {
a6c45cf0
CW		 8757 dev->mode_config.max_width = 8192;
8758 dev->mode_config.max_height = 8192;
79e53945 8759 }
dd2757f8 8760 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8761
28c97730 8762 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8763 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8764
a3524f1b 8765 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8766 intel_crtc_init(dev, i);
00c2064b
JB		 8767 ret = intel_plane_init(dev, i);
8768 if (ret)
8769 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8770 }
8771
79f689aa 8772 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8773 intel_pch_pll_init(dev);
8774
9cce37f4
JB		 8775 /* Just disable it once at startup */
8776 i915_disable_vga(dev);
79e53945 8777 intel_setup_outputs(dev);
2c7111db
CW		 8778}
8779
24929352
DV		 8780static void
8781intel_connector_break_all_links(struct intel_connector *connector)
8782{
8783 connector->base.dpms = DRM_MODE_DPMS_OFF;
8784 connector->base.encoder = NULL;
8785 connector->encoder->connectors_active = false;
8786 connector->encoder->base.crtc = NULL;
8787}
8788
7fad798e
DV		 8789static void intel_enable_pipe_a(struct drm_device *dev)
8790{
8791 struct intel_connector *connector;
8792 struct drm_connector *crt = NULL;
8793 struct intel_load_detect_pipe load_detect_temp;
8794
8795 /* We can't just switch on the pipe A, we need to set things up with a
8796 * proper mode and output configuration. As a gross hack, enable pipe A
8797 * by enabling the load detect pipe once. */
8798 list_for_each_entry(connector,
8799 &dev->mode_config.connector_list,
8800 base.head) {
8801 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8802 crt = &connector->base;
8803 break;
8804 }
8805 }
8806
8807 if (!crt)
8808 return;
8809
8810 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8811 intel_release_load_detect_pipe(crt, &load_detect_temp);
8812
8813
8814}
8815
fa555837
DV		 8816static bool
8817intel_check_plane_mapping(struct intel_crtc *crtc)
8818{
8819 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8820 u32 reg, val;
8821
8822 if (dev_priv->num_pipe == 1)
8823 return true;
8824
8825 reg = DSPCNTR(!crtc->plane);
8826 val = I915_READ(reg);
8827
8828 if ((val & DISPLAY_PLANE_ENABLE) &&
8829 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8830 return false;
8831
8832 return true;
8833}
8834
24929352
DV		 8835static void intel_sanitize_crtc(struct intel_crtc *crtc)
8836{
8837 struct drm_device *dev = crtc->base.dev;
8838 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8839 u32 reg;
24929352 8840
24929352 8841 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8842 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8843 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8844
8845 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8846 * disable the crtc (and hence change the state) if it is wrong. Note
8847 * that gen4+ has a fixed plane -> pipe mapping. */
8848 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8849 struct intel_connector *connector;
8850 bool plane;
8851
24929352
DV		 8852 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8853 crtc->base.base.id);
8854
8855 /* Pipe has the wrong plane attached and the plane is active.
8856 * Temporarily change the plane mapping and disable everything
8857 * ... */
8858 plane = crtc->plane;
8859 crtc->plane = !plane;
8860 dev_priv->display.crtc_disable(&crtc->base);
8861 crtc->plane = plane;
8862
8863 /* ... and break all links. */
8864 list_for_each_entry(connector, &dev->mode_config.connector_list,
8865 base.head) {
8866 if (connector->encoder->base.crtc != &crtc->base)
8867 continue;
8868
8869 intel_connector_break_all_links(connector);
8870 }
8871
8872 WARN_ON(crtc->active);
8873 crtc->base.enabled = false;
8874 }
24929352 8875
7fad798e
DV		 8876 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8877 crtc->pipe == PIPE_A && !crtc->active) {
8878 /* BIOS forgot to enable pipe A, this mostly happens after
8879 * resume. Force-enable the pipe to fix this, the update_dpms
8880 * call below we restore the pipe to the right state, but leave
8881 * the required bits on. */
8882 intel_enable_pipe_a(dev);
8883 }
8884
24929352
DV		 8885 /* Adjust the state of the output pipe according to whether we
8886 * have active connectors/encoders. */
8887 intel_crtc_update_dpms(&crtc->base);
8888
8889 if (crtc->active != crtc->base.enabled) {
8890 struct intel_encoder *encoder;
8891
8892 /* This can happen either due to bugs in the get_hw_state
8893 * functions or because the pipe is force-enabled due to the
8894 * pipe A quirk. */
8895 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8896 crtc->base.base.id,
8897 crtc->base.enabled ? "enabled" : "disabled",
8898 crtc->active ? "enabled" : "disabled");
8899
8900 crtc->base.enabled = crtc->active;
8901
8902 /* Because we only establish the connector -> encoder ->
8903 * crtc links if something is active, this means the
8904 * crtc is now deactivated. Break the links. connector
8905 * -> encoder links are only establish when things are
8906 * actually up, hence no need to break them. */
8907 WARN_ON(crtc->active);
8908
8909 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8910 WARN_ON(encoder->connectors_active);
8911 encoder->base.crtc = NULL;
8912 }
8913 }
8914}
8915
8916static void intel_sanitize_encoder(struct intel_encoder *encoder)
8917{
8918 struct intel_connector *connector;
8919 struct drm_device *dev = encoder->base.dev;
8920
8921 /* We need to check both for a crtc link (meaning that the
8922 * encoder is active and trying to read from a pipe) and the
8923 * pipe itself being active. */
8924 bool has_active_crtc = encoder->base.crtc &&
8925 to_intel_crtc(encoder->base.crtc)->active;
8926
8927 if (encoder->connectors_active && !has_active_crtc) {
8928 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8929 encoder->base.base.id,
8930 drm_get_encoder_name(&encoder->base));
8931
8932 /* Connector is active, but has no active pipe. This is
8933 * fallout from our resume register restoring. Disable
8934 * the encoder manually again. */
8935 if (encoder->base.crtc) {
8936 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8937 encoder->base.base.id,
8938 drm_get_encoder_name(&encoder->base));
8939 encoder->disable(encoder);
8940 }
8941
8942 /* Inconsistent output/port/pipe state happens presumably due to
8943 * a bug in one of the get_hw_state functions. Or someplace else
8944 * in our code, like the register restore mess on resume. Clamp
8945 * things to off as a safer default. */
8946 list_for_each_entry(connector,
8947 &dev->mode_config.connector_list,
8948 base.head) {
8949 if (connector->encoder != encoder)
8950 continue;
8951
8952 intel_connector_break_all_links(connector);
8953 }
8954 }
8955 /* Enabled encoders without active connectors will be fixed in
8956 * the crtc fixup. */
8957}
8958
8959/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8960 * and i915 state tracking structures. */
8961void intel_modeset_setup_hw_state(struct drm_device *dev)
8962{
8963 struct drm_i915_private *dev_priv = dev->dev_private;
8964 enum pipe pipe;
8965 u32 tmp;
8966 struct intel_crtc *crtc;
8967 struct intel_encoder *encoder;
8968 struct intel_connector *connector;
8969
e28d54cb
PZ		 8970 if (IS_HASWELL(dev)) {
8971 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8972
8973 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8974 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8975 case TRANS_DDI_EDP_INPUT_A_ON:
8976 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8977 pipe = PIPE_A;
8978 break;
8979 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8980 pipe = PIPE_B;
8981 break;
8982 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8983 pipe = PIPE_C;
8984 break;
8985 }
8986
8987 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8988 crtc->cpu_transcoder = TRANSCODER_EDP;
8989
8990 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8991 pipe_name(pipe));
8992 }
8993 }
8994
24929352
DV		 8995 for_each_pipe(pipe) {
8996 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8997
702e7a56 8998 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8999 if (tmp & PIPECONF_ENABLE)
9000 crtc->active = true;
9001 else
9002 crtc->active = false;
9003
9004 crtc->base.enabled = crtc->active;
9005
9006 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9007 crtc->base.base.id,
9008 crtc->active ? "enabled" : "disabled");
9009 }
9010
6441ab5f
PZ		 9011 if (IS_HASWELL(dev))
9012 intel_ddi_setup_hw_pll_state(dev);
9013
24929352
DV		 9014 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9015 base.head) {
9016 pipe = 0;
9017
9018 if (encoder->get_hw_state(encoder, &pipe)) {
9019 encoder->base.crtc =
9020 dev_priv->pipe_to_crtc_mapping[pipe];
9021 } else {
9022 encoder->base.crtc = NULL;
9023 }
9024
9025 encoder->connectors_active = false;
9026 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9027 encoder->base.base.id,
9028 drm_get_encoder_name(&encoder->base),
9029 encoder->base.crtc ? "enabled" : "disabled",
9030 pipe);
9031 }
9032
9033 list_for_each_entry(connector, &dev->mode_config.connector_list,
9034 base.head) {
9035 if (connector->get_hw_state(connector)) {
9036 connector->base.dpms = DRM_MODE_DPMS_ON;
9037 connector->encoder->connectors_active = true;
9038 connector->base.encoder = &connector->encoder->base;
9039 } else {
9040 connector->base.dpms = DRM_MODE_DPMS_OFF;
9041 connector->base.encoder = NULL;
9042 }
9043 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9044 connector->base.base.id,
9045 drm_get_connector_name(&connector->base),
9046 connector->base.encoder ? "enabled" : "disabled");
9047 }
9048
9049 /* HW state is read out, now we need to sanitize this mess. */
9050 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9051 base.head) {
9052 intel_sanitize_encoder(encoder);
9053 }
9054
9055 for_each_pipe(pipe) {
9056 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9057 intel_sanitize_crtc(crtc);
9058 }
9a935856
DV		 9059
9060 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9061
9062 intel_modeset_check_state(dev);
2e938892
DV		 9063
9064 drm_mode_config_reset(dev);
24929352
DV		 9065}
9066
2c7111db
CW		 9067void intel_modeset_gem_init(struct drm_device *dev)
9068{
1833b134 9069 intel_modeset_init_hw(dev);
02e792fb
DV		 9070
9071 intel_setup_overlay(dev);
24929352
DV		 9072
9073 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9074}
9075
9076void intel_modeset_cleanup(struct drm_device *dev)
9077{
652c393a
JB		 9078 struct drm_i915_private *dev_priv = dev->dev_private;
9079 struct drm_crtc *crtc;
9080 struct intel_crtc *intel_crtc;
9081
f87ea761 9082 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9083 mutex_lock(&dev->struct_mutex);
9084
723bfd70
JB		 9085 intel_unregister_dsm_handler();
9086
9087
652c393a
JB		 9088 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9089 /* Skip inactive CRTCs */
9090 if (!crtc->fb)
9091 continue;
9092
9093 intel_crtc = to_intel_crtc(crtc);
3dec0095 9094 intel_increase_pllclock(crtc);
652c393a
JB		 9095 }
9096
973d04f9 9097 intel_disable_fbc(dev);
e70236a8 9098
8090c6b9 9099 intel_disable_gt_powersave(dev);
0cdab21f 9100
930ebb46
DV		 9101 ironlake_teardown_rc6(dev);
9102
57f350b6
JB		 9103 if (IS_VALLEYVIEW(dev))
9104 vlv_init_dpio(dev);
9105
69341a5e
KH		 9106 mutex_unlock(&dev->struct_mutex);
9107
6c0d9350
DV		 9108 /* Disable the irq before mode object teardown, for the irq might
9109 * enqueue unpin/hotplug work. */
9110 drm_irq_uninstall(dev);
9111 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9112 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9113
1630fe75
CW		 9114 /* flush any delayed tasks or pending work */
9115 flush_scheduled_work();
9116
79e53945
JB		 9117 drm_mode_config_cleanup(dev);
9118}
9119
f1c79df3
ZW		 9120/*
9121 * Return which encoder is currently attached for connector.
9122 */
df0e9248 9123struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9124{
df0e9248
CW		 9125 return &intel_attached_encoder(connector)->base;
9126}
f1c79df3 9127
df0e9248
CW		 9128void intel_connector_attach_encoder(struct intel_connector *connector,
9129 struct intel_encoder *encoder)
9130{
9131 connector->encoder = encoder;
9132 drm_mode_connector_attach_encoder(&connector->base,
9133 &encoder->base);
79e53945 9134}
28d52043
DA		 9135
9136/*
9137 * set vga decode state - true == enable VGA decode
9138 */
9139int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9140{
9141 struct drm_i915_private *dev_priv = dev->dev_private;
9142 u16 gmch_ctrl;
9143
9144 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9145 if (state)
9146 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9147 else
9148 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9149 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9150 return 0;
9151}
c4a1d9e4
CW		 9152
9153#ifdef CONFIG_DEBUG_FS
9154#include <linux/seq_file.h>
9155
9156struct intel_display_error_state {
9157 struct intel_cursor_error_state {
9158 u32 control;
9159 u32 position;
9160 u32 base;
9161 u32 size;
52331309 9162 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9163
9164 struct intel_pipe_error_state {
9165 u32 conf;
9166 u32 source;
9167
9168 u32 htotal;
9169 u32 hblank;
9170 u32 hsync;
9171 u32 vtotal;
9172 u32 vblank;
9173 u32 vsync;
52331309 9174 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9175
9176 struct intel_plane_error_state {
9177 u32 control;
9178 u32 stride;
9179 u32 size;
9180 u32 pos;
9181 u32 addr;
9182 u32 surface;
9183 u32 tile_offset;
52331309 9184 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9185};
9186
9187struct intel_display_error_state *
9188intel_display_capture_error_state(struct drm_device *dev)
9189{
0206e353 9190 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9191 struct intel_display_error_state *error;
702e7a56 9192 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9193 int i;
9194
9195 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9196 if (error == NULL)
9197 return NULL;
9198
52331309 9199 for_each_pipe(i) {
702e7a56
PZ		 9200 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9201
c4a1d9e4
CW		 9202 error->cursor[i].control = I915_READ(CURCNTR(i));
9203 error->cursor[i].position = I915_READ(CURPOS(i));
9204 error->cursor[i].base = I915_READ(CURBASE(i));
9205
9206 error->plane[i].control = I915_READ(DSPCNTR(i));
9207 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9208 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9209 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9210 error->plane[i].addr = I915_READ(DSPADDR(i));
9211 if (INTEL_INFO(dev)->gen >= 4) {
9212 error->plane[i].surface = I915_READ(DSPSURF(i));
9213 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9214 }
9215
702e7a56 9216 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9217 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9218 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9219 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9220 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9221 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9222 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9223 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9224 }
9225
9226 return error;
9227}
9228
9229void
9230intel_display_print_error_state(struct seq_file *m,
9231 struct drm_device *dev,
9232 struct intel_display_error_state *error)
9233{
52331309 9234 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9235 int i;
9236
52331309
DL		 9237 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9238 for_each_pipe(i) {
c4a1d9e4
CW		 9239 seq_printf(m, "Pipe [%d]:\n", i);
9240 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9241 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9242 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9243 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9244 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9245 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9246 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9247 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9248
9249 seq_printf(m, "Plane [%d]:\n", i);
9250 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9251 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9252 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9253 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9254 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9255 if (INTEL_INFO(dev)->gen >= 4) {
9256 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9257 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9258 }
9259
9260 seq_printf(m, "Cursor [%d]:\n", i);
9261 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9262 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9263 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9264 }
9265}
9266#endif
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