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drm/i915: split up intel_modeset_check_state
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
e2b78267
DV		 912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
a43f6e0f 917 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 918 return NULL;
919
a43f6e0f 920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 921}
922
040484af 923/* For ILK+ */
e72f9fbf
DV		 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
e72f9fbf 926 bool state)
040484af 927{
040484af 928 bool cur_state;
5358901f 929 struct intel_dpll_hw_state hw_state;
040484af 930
9d82aa17
ED		 931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
933 return;
934 }
935
92b27b08 936 if (WARN (!pll,
46edb027 937 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 938 return;
ee7b9f93 939
5358901f 940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 941 WARN(cur_state != state,
5358901f
DV		 942 "%s assertion failure (expected %s, current %s)\n",
943 pll->name, state_string(state), state_string(cur_state));
040484af 944}
e9d6944e
DV		 945#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
946#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
040484af
JB		 947
948static void assert_fdi_tx(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state)
950{
951 int reg;
952 u32 val;
953 bool cur_state;
ad80a810
PZ		 954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
955 pipe);
040484af 956
affa9354
PZ		 957 if (HAS_DDI(dev_priv->dev)) {
958 /* DDI does not have a specific FDI_TX register */
ad80a810 959 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 960 val = I915_READ(reg);
ad80a810 961 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 962 } else {
963 reg = FDI_TX_CTL(pipe);
964 val = I915_READ(reg);
965 cur_state = !!(val & FDI_TX_ENABLE);
966 }
040484af
JB		 967 WARN(cur_state != state,
968 "FDI TX state assertion failure (expected %s, current %s)\n",
969 state_string(state), state_string(cur_state));
970}
971#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
972#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
973
974static void assert_fdi_rx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
976{
977 int reg;
978 u32 val;
979 bool cur_state;
980
d63fa0dc
PZ		 981 reg = FDI_RX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 984 WARN(cur_state != state,
985 "FDI RX state assertion failure (expected %s, current %s)\n",
986 state_string(state), state_string(cur_state));
987}
988#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
989#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
990
991static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993{
994 int reg;
995 u32 val;
996
997 /* ILK FDI PLL is always enabled */
998 if (dev_priv->info->gen == 5)
999 return;
1000
bf507ef7 1001 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1002 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1003 return;
1004
040484af
JB		 1005 reg = FDI_TX_CTL(pipe);
1006 val = I915_READ(reg);
1007 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008}
1009
1010static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012{
1013 int reg;
1014 u32 val;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019}
1020
ea0760cf
JB		 1021static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023{
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
0de3b485 1027 bool locked = true;
ea0760cf
JB		 1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1047 pipe_name(pipe));
ea0760cf
JB		 1048}
1049
b840d907
JB		 1050void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
b24e7179
JB		 1052{
1053 int reg;
1054 u32 val;
63d7bbe9 1055 bool cur_state;
702e7a56
PZ		 1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
b24e7179 1058
8e636784
DV		 1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
b97186f0
PZ		 1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
63d7bbe9
JB		 1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
653e1026 1098 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
653e1026
VS		 1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
19ec1358 1110 return;
28c05794 1111 }
19ec1358 1112
b24e7179 1113 /* Need to check both planes against the pipe */
653e1026 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1122 }
1123}
1124
19332d7a
JB		 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
20674eef 1128 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1129 int reg, i;
1130 u32 val;
1131
20674eef
VS		 1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
1142 val = I915_READ(reg);
1143 WARN((val & SPRITE_ENABLE),
1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
19332d7a 1148 val = I915_READ(reg);
20674eef 1149 WARN((val & DVS_ENABLE),
06da8da2 1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1151 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1152 }
1153}
1154
92f2584a
JB		 1155static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156{
1157 u32 val;
1158 bool enabled;
1159
9d82aa17
ED		 1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
92f2584a
JB		 1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169}
1170
ab9412ba
DV		 1171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
92f2584a
JB		 1173{
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
ab9412ba 1178 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
92f2584a
JB		 1184}
1185
4e634389
KP		 1186static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1188{
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202}
1203
1519b995
KP		 1204static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206{
dc0fa718 1207 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1212 return false;
1213 } else {
dc0fa718 1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1215 return false;
1216 }
1217 return true;
1218}
1219
1220static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222{
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234}
1235
1236static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249}
1250
291906f1 1251static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1252 enum pipe pipe, int reg, u32 port_sel)
291906f1 1253{
47a05eca 1254 u32 val = I915_READ(reg);
4e634389 1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1257 reg, pipe_name(pipe));
de9a35ab 1258
75c5da27
DV		 1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
de9a35ab 1261 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1262}
1263
1264static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266{
47a05eca 1267 u32 val = I915_READ(reg);
b70ad586 1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1270 reg, pipe_name(pipe));
de9a35ab 1271
dc0fa718 1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1273 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1274 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1275}
1276
1277static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279{
1280 int reg;
1281 u32 val;
291906f1 1282
f0575e92
KP		 1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
b70ad586 1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 pipe_name(pipe));
291906f1
JB		 1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
b70ad586 1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 pipe_name(pipe));
291906f1 1298
e2debe91
PZ		 1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1302}
1303
63d7bbe9
JB		 1304/**
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1308 *
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1312 *
1313 * Note! This is for pre-ILK only.
7434a255
TR		 1314 *
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1316 */
1317static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321
58c6eaa2
DV		 1322 assert_pipe_disabled(dev_priv, pipe);
1323
63d7bbe9 1324 /* No really, not for ILK+ */
a0c4da24 1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1326
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1330
1331 reg = DPLL(pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1334
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1337 POSTING_READ(reg);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344 udelay(150); /* wait for warmup */
1345}
1346
1347/**
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1351 *
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1353 *
1354 * Note! This is for pre-ILK only.
1355 */
1356static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357{
1358 int reg;
1359 u32 val;
1360
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 return;
1364
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1367
1368 reg = DPLL(pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373}
1374
89b667f8
JB		 1375void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376{
1377 u32 port_mask;
1378
1379 if (!port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1381 else
1382 port_mask = DPLL_PORTC_READY_MASK;
1383
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1387}
1388
92f2584a 1389/**
e72f9fbf 1390 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1393 *
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1396 */
e2b78267 1397static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1398{
e2b78267
DV		 1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1404 if (pll == NULL)
1405 return;
1406
1407 if (WARN_ON(pll->refcount == 0))
1408 return;
ee7b9f93 1409
46edb027
DV		 1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411 pll->name, pll->active, pll->on,
e2b78267 1412 crtc->base.base.id);
92f2584a 1413
cdbd2316
DV		 1414 if (pll->active++) {
1415 WARN_ON(!pll->on);
e9d6944e 1416 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1417 return;
1418 }
f4a091c7 1419 WARN_ON(pll->on);
ee7b9f93 1420
46edb027 1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1422 pll->enable(dev_priv, pll);
ee7b9f93 1423 pll->on = true;
92f2584a
JB		 1424}
1425
e2b78267 1426static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1427{
e2b78267
DV		 1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1430
92f2584a
JB		 1431 /* PCH only available on ILK+ */
1432 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1433 if (pll == NULL)
1434 return;
92f2584a 1435
48da64a8
CW		 1436 if (WARN_ON(pll->refcount == 0))
1437 return;
7a419866 1438
46edb027
DV		 1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440 pll->name, pll->active, pll->on,
e2b78267 1441 crtc->base.base.id);
7a419866 1442
48da64a8 1443 if (WARN_ON(pll->active == 0)) {
e9d6944e 1444 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1445 return;
1446 }
1447
e9d6944e 1448 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1449 WARN_ON(!pll->on);
cdbd2316 1450 if (--pll->active)
7a419866 1451 return;
ee7b9f93 1452
46edb027 1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1454 pll->disable(dev_priv, pll);
ee7b9f93 1455 pll->on = false;
92f2584a
JB		 1456}
1457
b8a4f404
PZ		 1458static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
040484af 1460{
23670b32 1461 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1464 uint32_t reg, val, pipeconf_val;
040484af
JB		 1465
1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
1468
1469 /* Make sure PCH DPLL is enabled */
e72f9fbf 1470 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1471 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1472
1473 /* FDI must be feeding us bits for PCH ports */
1474 assert_fdi_tx_enabled(dev_priv, pipe);
1475 assert_fdi_rx_enabled(dev_priv, pipe);
1476
23670b32
DV		 1477 if (HAS_PCH_CPT(dev)) {
1478 /* Workaround: Set the timing override bit before enabling the
1479 * pch transcoder. */
1480 reg = TRANS_CHICKEN2(pipe);
1481 val = I915_READ(reg);
1482 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483 I915_WRITE(reg, val);
59c859d6 1484 }
23670b32 1485
ab9412ba 1486 reg = PCH_TRANSCONF(pipe);
040484af 1487 val = I915_READ(reg);
5f7f726d 1488 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1489
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1491 /*
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1494 */
dfd07d72
DV		 1495 val &= ~PIPECONF_BPC_MASK;
1496 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1497 }
5f7f726d
PZ		 1498
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1504 else
1505 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1506 else
1507 val |= TRANS_PROGRESSIVE;
1508
040484af
JB		 1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1512}
1513
8fb033d7 1514static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1515 enum transcoder cpu_transcoder)
040484af 1516{
8fb033d7 1517 u32 val, pipeconf_val;
8fb033d7
PZ		 1518
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1521
8fb033d7 1522 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1523 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1524 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1525
223a6fdf
PZ		 1526 /* Workaround: set timing override bit. */
1527 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1529 I915_WRITE(_TRANSA_CHICKEN2, val);
1530
25f3ef11 1531 val = TRANS_ENABLE;
937bb610 1532 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1533
9a76b1c6
PZ		 1534 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535 PIPECONF_INTERLACED_ILK)
a35f2679 1536 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1537 else
1538 val |= TRANS_PROGRESSIVE;
1539
ab9412ba
DV		 1540 I915_WRITE(LPT_TRANSCONF, val);
1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1542 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1543}
1544
b8a4f404
PZ		 1545static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546 enum pipe pipe)
040484af 1547{
23670b32
DV		 1548 struct drm_device *dev = dev_priv->dev;
1549 uint32_t reg, val;
040484af
JB		 1550
1551 /* FDI relies on the transcoder */
1552 assert_fdi_tx_disabled(dev_priv, pipe);
1553 assert_fdi_rx_disabled(dev_priv, pipe);
1554
291906f1
JB		 1555 /* Ports must be off as well */
1556 assert_pch_ports_disabled(dev_priv, pipe);
1557
ab9412ba 1558 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1559 val = I915_READ(reg);
1560 val &= ~TRANS_ENABLE;
1561 I915_WRITE(reg, val);
1562 /* wait for PCH transcoder off, transcoder state */
1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1565
1566 if (!HAS_PCH_IBX(dev)) {
1567 /* Workaround: Clear the timing override chicken bit again. */
1568 reg = TRANS_CHICKEN2(pipe);
1569 val = I915_READ(reg);
1570 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571 I915_WRITE(reg, val);
1572 }
040484af
JB		 1573}
1574
ab4d966c 1575static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1576{
8fb033d7
PZ		 1577 u32 val;
1578
ab9412ba 1579 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1580 val &= ~TRANS_ENABLE;
ab9412ba 1581 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1582 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1584 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1585
1586 /* Workaround: clear timing override bit. */
1587 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1589 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1590}
1591
b24e7179 1592/**
309cfea8 1593 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1594 * @dev_priv: i915 private structure
1595 * @pipe: pipe to enable
040484af 1596 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1597 *
1598 * Enable @pipe, making sure that various hardware specific requirements
1599 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600 *
1601 * @pipe should be %PIPE_A or %PIPE_B.
1602 *
1603 * Will wait until the pipe is actually running (i.e. first vblank) before
1604 * returning.
1605 */
040484af
JB		 1606static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607 bool pch_port)
b24e7179 1608{
702e7a56
PZ		 1609 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610 pipe);
1a240d4d 1611 enum pipe pch_transcoder;
b24e7179
JB		 1612 int reg;
1613 u32 val;
1614
58c6eaa2
DV		 1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1617
681e5811 1618 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1619 pch_transcoder = TRANSCODER_A;
1620 else
1621 pch_transcoder = pipe;
1622
b24e7179
JB		 1623 /*
1624 * A pipe without a PLL won't actually be able to drive bits from
1625 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1626 * need the check.
1627 */
1628 if (!HAS_PCH_SPLIT(dev_priv->dev))
1629 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1630 else {
1631 if (pch_port) {
1632 /* if driving the PCH, we need FDI enabled */
cc391bbb 1633 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1634 assert_fdi_tx_pll_enabled(dev_priv,
1635 (enum pipe) cpu_transcoder);
040484af
JB		 1636 }
1637 /* FIXME: assert CPU port conditions for SNB+ */
1638 }
b24e7179 1639
702e7a56 1640 reg = PIPECONF(cpu_transcoder);
b24e7179 1641 val = I915_READ(reg);
00d70b15
CW		 1642 if (val & PIPECONF_ENABLE)
1643 return;
1644
1645 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1646 intel_wait_for_vblank(dev_priv->dev, pipe);
1647}
1648
1649/**
309cfea8 1650 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to disable
1653 *
1654 * Disable @pipe, making sure that various hardware specific requirements
1655 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656 *
1657 * @pipe should be %PIPE_A or %PIPE_B.
1658 *
1659 * Will wait until the pipe has shut down before returning.
1660 */
1661static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663{
702e7a56
PZ		 1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
b24e7179
JB		 1666 int reg;
1667 u32 val;
1668
1669 /*
1670 * Make sure planes won't keep trying to pump pixels to us,
1671 * or we might hang the display.
1672 */
1673 assert_planes_disabled(dev_priv, pipe);
19332d7a 1674 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1675
1676 /* Don't disable pipe A or pipe A PLLs if needed */
1677 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678 return;
1679
702e7a56 1680 reg = PIPECONF(cpu_transcoder);
b24e7179 1681 val = I915_READ(reg);
00d70b15
CW		 1682 if ((val & PIPECONF_ENABLE) == 0)
1683 return;
1684
1685 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1686 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687}
1688
d74362c9
KP		 1689/*
1690 * Plane regs are double buffered, going from enabled->disabled needs a
1691 * trigger in order to latch. The display address reg provides this.
1692 */
6f1d69b0 1693void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1694 enum plane plane)
1695{
14f86147
DL		 1696 if (dev_priv->info->gen >= 4)
1697 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698 else
1699 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1700}
1701
b24e7179
JB		 1702/**
1703 * intel_enable_plane - enable a display plane on a given pipe
1704 * @dev_priv: i915 private structure
1705 * @plane: plane to enable
1706 * @pipe: pipe being fed
1707 *
1708 * Enable @plane on @pipe, making sure that @pipe is running first.
1709 */
1710static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711 enum plane plane, enum pipe pipe)
1712{
1713 int reg;
1714 u32 val;
1715
1716 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717 assert_pipe_enabled(dev_priv, pipe);
1718
1719 reg = DSPCNTR(plane);
1720 val = I915_READ(reg);
00d70b15
CW		 1721 if (val & DISPLAY_PLANE_ENABLE)
1722 return;
1723
1724 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1725 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1726 intel_wait_for_vblank(dev_priv->dev, pipe);
1727}
1728
b24e7179
JB		 1729/**
1730 * intel_disable_plane - disable a display plane
1731 * @dev_priv: i915 private structure
1732 * @plane: plane to disable
1733 * @pipe: pipe consuming the data
1734 *
1735 * Disable @plane; should be an independent operation.
1736 */
1737static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738 enum plane plane, enum pipe pipe)
1739{
1740 int reg;
1741 u32 val;
1742
1743 reg = DSPCNTR(plane);
1744 val = I915_READ(reg);
00d70b15
CW		 1745 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746 return;
1747
1748 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1749 intel_flush_display_plane(dev_priv, plane);
1750 intel_wait_for_vblank(dev_priv->dev, pipe);
1751}
1752
693db184
CW		 1753static bool need_vtd_wa(struct drm_device *dev)
1754{
1755#ifdef CONFIG_INTEL_IOMMU
1756 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757 return true;
1758#endif
1759 return false;
1760}
1761
127bd2ac 1762int
48b956c5 1763intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1764 struct drm_i915_gem_object *obj,
919926ae 1765 struct intel_ring_buffer *pipelined)
6b95a207 1766{
ce453d81 1767 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1768 u32 alignment;
1769 int ret;
1770
05394f39 1771 switch (obj->tiling_mode) {
6b95a207 1772 case I915_TILING_NONE:
534843da
CW		 1773 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774 alignment = 128 * 1024;
a6c45cf0 1775 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1776 alignment = 4 * 1024;
1777 else
1778 alignment = 64 * 1024;
6b95a207
KH		 1779 break;
1780 case I915_TILING_X:
1781 /* pin() will align the object as required by fence */
1782 alignment = 0;
1783 break;
1784 case I915_TILING_Y:
8bb6e959
DV		 1785 /* Despite that we check this in framebuffer_init userspace can
1786 * screw us over and change the tiling after the fact. Only
1787 * pinned buffers can't change their tiling. */
1788 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1789 return -EINVAL;
1790 default:
1791 BUG();
1792 }
1793
693db184
CW		 1794 /* Note that the w/a also requires 64 PTE of padding following the
1795 * bo. We currently fill all unused PTE with the shadow page and so
1796 * we should always have valid PTE following the scanout preventing
1797 * the VT-d warning.
1798 */
1799 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800 alignment = 256 * 1024;
1801
ce453d81 1802 dev_priv->mm.interruptible = false;
2da3b9b9 1803 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1804 if (ret)
ce453d81 1805 goto err_interruptible;
6b95a207
KH		 1806
1807 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808 * fence, whereas 965+ only requires a fence if using
1809 * framebuffer compression. For simplicity, we always install
1810 * a fence as the cost is not that onerous.
1811 */
06d98131 1812 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1813 if (ret)
1814 goto err_unpin;
1690e1eb 1815
9a5a53b3 1816 i915_gem_object_pin_fence(obj);
6b95a207 1817
ce453d81 1818 dev_priv->mm.interruptible = true;
6b95a207 1819 return 0;
48b956c5
CW		 1820
1821err_unpin:
1822 i915_gem_object_unpin(obj);
ce453d81
CW		 1823err_interruptible:
1824 dev_priv->mm.interruptible = true;
48b956c5 1825 return ret;
6b95a207
KH		 1826}
1827
1690e1eb
CW		 1828void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829{
1830 i915_gem_object_unpin_fence(obj);
1831 i915_gem_object_unpin(obj);
1832}
1833
c2c75131
DV		 1834/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835 * is assumed to be a power-of-two. */
bc752862
CW		 1836unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837 unsigned int tiling_mode,
1838 unsigned int cpp,
1839 unsigned int pitch)
c2c75131 1840{
bc752862
CW		 1841 if (tiling_mode != I915_TILING_NONE) {
1842 unsigned int tile_rows, tiles;
c2c75131 1843
bc752862
CW		 1844 tile_rows = *y / 8;
1845 *y %= 8;
c2c75131 1846
bc752862
CW		 1847 tiles = *x / (512/cpp);
1848 *x %= 512/cpp;
1849
1850 return tile_rows * pitch * 8 + tiles * 4096;
1851 } else {
1852 unsigned int offset;
1853
1854 offset = *y * pitch + *x * cpp;
1855 *y = 0;
1856 *x = (offset & 4095) / cpp;
1857 return offset & -4096;
1858 }
c2c75131
DV		 1859}
1860
17638cd6
JB		 1861static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862 int x, int y)
81255565
JB		 1863{
1864 struct drm_device *dev = crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867 struct intel_framebuffer *intel_fb;
05394f39 1868 struct drm_i915_gem_object *obj;
81255565 1869 int plane = intel_crtc->plane;
e506a0c6 1870 unsigned long linear_offset;
81255565 1871 u32 dspcntr;
5eddb70b 1872 u32 reg;
81255565
JB		 1873
1874 switch (plane) {
1875 case 0:
1876 case 1:
1877 break;
1878 default:
84f44ce7 1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1880 return -EINVAL;
1881 }
1882
1883 intel_fb = to_intel_framebuffer(fb);
1884 obj = intel_fb->obj;
81255565 1885
5eddb70b
CW		 1886 reg = DSPCNTR(plane);
1887 dspcntr = I915_READ(reg);
81255565
JB		 1888 /* Mask out pixel format bits in case we change it */
1889 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1890 switch (fb->pixel_format) {
1891 case DRM_FORMAT_C8:
81255565
JB		 1892 dspcntr |= DISPPLANE_8BPP;
1893 break;
57779d06
VS		 1894 case DRM_FORMAT_XRGB1555:
1895 case DRM_FORMAT_ARGB1555:
1896 dspcntr |= DISPPLANE_BGRX555;
81255565 1897 break;
57779d06
VS		 1898 case DRM_FORMAT_RGB565:
1899 dspcntr |= DISPPLANE_BGRX565;
1900 break;
1901 case DRM_FORMAT_XRGB8888:
1902 case DRM_FORMAT_ARGB8888:
1903 dspcntr |= DISPPLANE_BGRX888;
1904 break;
1905 case DRM_FORMAT_XBGR8888:
1906 case DRM_FORMAT_ABGR8888:
1907 dspcntr |= DISPPLANE_RGBX888;
1908 break;
1909 case DRM_FORMAT_XRGB2101010:
1910 case DRM_FORMAT_ARGB2101010:
1911 dspcntr |= DISPPLANE_BGRX101010;
1912 break;
1913 case DRM_FORMAT_XBGR2101010:
1914 case DRM_FORMAT_ABGR2101010:
1915 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1916 break;
1917 default:
baba133a 1918 BUG();
81255565 1919 }
57779d06 1920
a6c45cf0 1921 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1922 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1923 dspcntr |= DISPPLANE_TILED;
1924 else
1925 dspcntr &= ~DISPPLANE_TILED;
1926 }
1927
de1aa629
VS		 1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
5eddb70b 1931 I915_WRITE(reg, dspcntr);
81255565 1932
e506a0c6 1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1934
c2c75131
DV		 1935 if (INTEL_INFO(dev)->gen >= 4) {
1936 intel_crtc->dspaddr_offset =
bc752862
CW		 1937 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938 fb->bits_per_pixel / 8,
1939 fb->pitches[0]);
c2c75131
DV		 1940 linear_offset -= intel_crtc->dspaddr_offset;
1941 } else {
e506a0c6 1942 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1943 }
e506a0c6
DV		 1944
1945 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1947 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1948 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1949 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1951 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1952 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1953 } else
e506a0c6 1954 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1955 POSTING_READ(reg);
81255565 1956
17638cd6
JB		 1957 return 0;
1958}
1959
1960static int ironlake_update_plane(struct drm_crtc *crtc,
1961 struct drm_framebuffer *fb, int x, int y)
1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
17638cd6
JB		 1970 u32 dspcntr;
1971 u32 reg;
1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
27f8227b 1976 case 2:
17638cd6
JB		 1977 break;
1978 default:
84f44ce7 1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1980 return -EINVAL;
1981 }
1982
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
1985
1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1990 switch (fb->pixel_format) {
1991 case DRM_FORMAT_C8:
17638cd6
JB		 1992 dspcntr |= DISPPLANE_8BPP;
1993 break;
57779d06
VS		 1994 case DRM_FORMAT_RGB565:
1995 dspcntr |= DISPPLANE_BGRX565;
17638cd6 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_XRGB8888:
1998 case DRM_FORMAT_ARGB8888:
1999 dspcntr |= DISPPLANE_BGRX888;
2000 break;
2001 case DRM_FORMAT_XBGR8888:
2002 case DRM_FORMAT_ABGR8888:
2003 dspcntr |= DISPPLANE_RGBX888;
2004 break;
2005 case DRM_FORMAT_XRGB2101010:
2006 case DRM_FORMAT_ARGB2101010:
2007 dspcntr |= DISPPLANE_BGRX101010;
2008 break;
2009 case DRM_FORMAT_XBGR2101010:
2010 case DRM_FORMAT_ABGR2101010:
2011 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2012 break;
2013 default:
baba133a 2014 BUG();
17638cd6
JB		 2015 }
2016
2017 if (obj->tiling_mode != I915_TILING_NONE)
2018 dspcntr |= DISPPLANE_TILED;
2019 else
2020 dspcntr &= ~DISPPLANE_TILED;
2021
2022 /* must disable */
2023 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025 I915_WRITE(reg, dspcntr);
2026
e506a0c6 2027 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2028 intel_crtc->dspaddr_offset =
bc752862
CW		 2029 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030 fb->bits_per_pixel / 8,
2031 fb->pitches[0]);
c2c75131 2032 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2033
e506a0c6
DV		 2034 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2036 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2037 I915_MODIFY_DISPBASE(DSPSURF(plane),
2038 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2039 if (IS_HASWELL(dev)) {
2040 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041 } else {
2042 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044 }
17638cd6
JB		 2045 POSTING_READ(reg);
2046
2047 return 0;
2048}
2049
2050/* Assume fb object is pinned & idle & fenced and just update base pointers */
2051static int
2052intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y, enum mode_set_atomic state)
2054{
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2057
6b8e6ed0
CW		 2058 if (dev_priv->display.disable_fbc)
2059 dev_priv->display.disable_fbc(dev);
3dec0095 2060 intel_increase_pllclock(crtc);
81255565 2061
6b8e6ed0 2062 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2063}
2064
96a02917
VS		 2065void intel_display_handle_reset(struct drm_device *dev)
2066{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct drm_crtc *crtc;
2069
2070 /*
2071 * Flips in the rings have been nuked by the reset,
2072 * so complete all pending flips so that user space
2073 * will get its events and not get stuck.
2074 *
2075 * Also update the base address of all primary
2076 * planes to the the last fb to make sure we're
2077 * showing the correct fb after a reset.
2078 *
2079 * Need to make two loops over the crtcs so that we
2080 * don't try to grab a crtc mutex before the
2081 * pending_flip_queue really got woken up.
2082 */
2083
2084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086 enum plane plane = intel_crtc->plane;
2087
2088 intel_prepare_page_flip(dev, plane);
2089 intel_finish_page_flip_plane(dev, plane);
2090 }
2091
2092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095 mutex_lock(&crtc->mutex);
2096 if (intel_crtc->active)
2097 dev_priv->display.update_plane(crtc, crtc->fb,
2098 crtc->x, crtc->y);
2099 mutex_unlock(&crtc->mutex);
2100 }
2101}
2102
14667a4b
CW		 2103static int
2104intel_finish_fb(struct drm_framebuffer *old_fb)
2105{
2106 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108 bool was_interruptible = dev_priv->mm.interruptible;
2109 int ret;
2110
14667a4b
CW		 2111 /* Big Hammer, we also need to ensure that any pending
2112 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113 * current scanout is retired before unpinning the old
2114 * framebuffer.
2115 *
2116 * This should only fail upon a hung GPU, in which case we
2117 * can safely continue.
2118 */
2119 dev_priv->mm.interruptible = false;
2120 ret = i915_gem_object_finish_gpu(obj);
2121 dev_priv->mm.interruptible = was_interruptible;
2122
2123 return ret;
2124}
2125
198598d0
VS		 2126static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127{
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_master_private *master_priv;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132 if (!dev->primary->master)
2133 return;
2134
2135 master_priv = dev->primary->master->driver_priv;
2136 if (!master_priv->sarea_priv)
2137 return;
2138
2139 switch (intel_crtc->pipe) {
2140 case 0:
2141 master_priv->sarea_priv->pipeA_x = x;
2142 master_priv->sarea_priv->pipeA_y = y;
2143 break;
2144 case 1:
2145 master_priv->sarea_priv->pipeB_x = x;
2146 master_priv->sarea_priv->pipeB_y = y;
2147 break;
2148 default:
2149 break;
2150 }
2151}
2152
5c3b82e2 2153static int
3c4fdcfb 2154intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2155 struct drm_framebuffer *fb)
79e53945
JB		 2156{
2157 struct drm_device *dev = crtc->dev;
6b8e6ed0 2158 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2160 struct drm_framebuffer *old_fb;
5c3b82e2 2161 int ret;
79e53945
JB		 2162
2163 /* no fb bound */
94352cf9 2164 if (!fb) {
a5071c2f 2165 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2166 return 0;
2167 }
2168
7eb552ae 2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171 plane_name(intel_crtc->plane),
2172 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2173 return -EINVAL;
79e53945
JB		 2174 }
2175
5c3b82e2 2176 mutex_lock(&dev->struct_mutex);
265db958 2177 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2178 to_intel_framebuffer(fb)->obj,
919926ae 2179 NULL);
5c3b82e2
CW		 2180 if (ret != 0) {
2181 mutex_unlock(&dev->struct_mutex);
a5071c2f 2182 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2183 return ret;
2184 }
79e53945 2185
94352cf9 2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2187 if (ret) {
94352cf9 2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2189 mutex_unlock(&dev->struct_mutex);
a5071c2f 2190 DRM_ERROR("failed to update base address\n");
4e6cfefc 2191 return ret;
79e53945 2192 }
3c4fdcfb 2193
94352cf9
DV		 2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
6c4c86f5
DV		 2196 crtc->x = x;
2197 crtc->y = y;
94352cf9 2198
b7f1de28 2199 if (old_fb) {
d7697eea
DV		 2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2203 }
652c393a 2204
6b8e6ed0 2205 intel_update_fbc(dev);
5c3b82e2 2206 mutex_unlock(&dev->struct_mutex);
79e53945 2207
198598d0 2208 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2209
2210 return 0;
79e53945
JB		 2211}
2212
5e84e1a4
ZW		 2213static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214{
2215 struct drm_device *dev = crtc->dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218 int pipe = intel_crtc->pipe;
2219 u32 reg, temp;
2220
2221 /* enable normal train */
2222 reg = FDI_TX_CTL(pipe);
2223 temp = I915_READ(reg);
61e499bf 2224 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2227 } else {
2228 temp &= ~FDI_LINK_TRAIN_NONE;
2229 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2230 }
5e84e1a4
ZW		 2231 I915_WRITE(reg, temp);
2232
2233 reg = FDI_RX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 if (HAS_PCH_CPT(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238 } else {
2239 temp &= ~FDI_LINK_TRAIN_NONE;
2240 temp |= FDI_LINK_TRAIN_NONE;
2241 }
2242 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244 /* wait one idle pattern time */
2245 POSTING_READ(reg);
2246 udelay(1000);
357555c0
JB		 2247
2248 /* IVB wants error correction enabled */
2249 if (IS_IVYBRIDGE(dev))
2250 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2252}
2253
1e833f40
DV		 2254static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255{
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257}
2258
01a415fd
DV		 2259static void ivb_modeset_global_resources(struct drm_device *dev)
2260{
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *pipe_B_crtc =
2263 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264 struct intel_crtc *pipe_C_crtc =
2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266 uint32_t temp;
2267
1e833f40
DV		 2268 /*
2269 * When everything is off disable fdi C so that we could enable fdi B
2270 * with all lanes. Note that we don't care about enabled pipes without
2271 * an enabled pch encoder.
2272 */
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278 temp = I915_READ(SOUTH_CHICKEN1);
2279 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281 I915_WRITE(SOUTH_CHICKEN1, temp);
2282 }
2283}
2284
8db9d77b
ZW		 2285/* The FDI link training functions for ILK/Ibexpeak. */
2286static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287{
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
0fc932b8 2292 int plane = intel_crtc->plane;
5eddb70b 2293 u32 reg, temp, tries;
8db9d77b 2294
0fc932b8
JB		 2295 /* FDI needs bits from pipe & plane first */
2296 assert_pipe_enabled(dev_priv, pipe);
2297 assert_plane_enabled(dev_priv, plane);
2298
e1a44743
AJ		 2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
5eddb70b
CW		 2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
e1a44743
AJ		 2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2305 I915_WRITE(reg, temp);
2306 I915_READ(reg);
e1a44743
AJ		 2307 udelay(150);
2308
8db9d77b 2309 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2310 reg = FDI_TX_CTL(pipe);
2311 temp = I915_READ(reg);
627eb5a3
DV		 2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2317
5eddb70b
CW		 2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
8db9d77b
ZW		 2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324 POSTING_READ(reg);
8db9d77b
ZW		 2325 udelay(150);
2326
5b2adf89 2327 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2328 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2331
5eddb70b 2332 reg = FDI_RX_IIR(pipe);
e1a44743 2333 for (tries = 0; tries < 5; tries++) {
5eddb70b 2334 temp = I915_READ(reg);
8db9d77b
ZW		 2335 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337 if ((temp & FDI_RX_BIT_LOCK)) {
2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2339 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2340 break;
2341 }
8db9d77b 2342 }
e1a44743 2343 if (tries == 5)
5eddb70b 2344 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2345
2346 /* Train 2 */
5eddb70b
CW		 2347 reg = FDI_TX_CTL(pipe);
2348 temp = I915_READ(reg);
8db9d77b
ZW		 2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2351 I915_WRITE(reg, temp);
8db9d77b 2352
5eddb70b
CW		 2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
8db9d77b
ZW		 2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2357 I915_WRITE(reg, temp);
8db9d77b 2358
5eddb70b
CW		 2359 POSTING_READ(reg);
2360 udelay(150);
8db9d77b 2361
5eddb70b 2362 reg = FDI_RX_IIR(pipe);
e1a44743 2363 for (tries = 0; tries < 5; tries++) {
5eddb70b 2364 temp = I915_READ(reg);
8db9d77b
ZW		 2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2369 DRM_DEBUG_KMS("FDI train 2 done.\n");
2370 break;
2371 }
8db9d77b 2372 }
e1a44743 2373 if (tries == 5)
5eddb70b 2374 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2375
2376 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2377
8db9d77b
ZW		 2378}
2379
0206e353 2380static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2381 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385};
2386
2387/* The FDI link training functions for SNB/Cougarpoint. */
2388static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389{
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
fa37d39e 2394 u32 reg, temp, i, retry;
8db9d77b 2395
e1a44743
AJ		 2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
5eddb70b
CW		 2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
e1a44743
AJ		 2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
e1a44743
AJ		 2405 udelay(150);
2406
8db9d77b 2407 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
627eb5a3
DV		 2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415 /* SNB-B */
2416 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2418
d74cf324
DV		 2419 I915_WRITE(FDI_RX_MISC(pipe),
2420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
5eddb70b
CW		 2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
8db9d77b
ZW		 2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427 } else {
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430 }
5eddb70b
CW		 2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433 POSTING_READ(reg);
8db9d77b
ZW		 2434 udelay(150);
2435
0206e353 2436 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2441 I915_WRITE(reg, temp);
2442
2443 POSTING_READ(reg);
8db9d77b
ZW		 2444 udelay(500);
2445
fa37d39e
SP		 2446 for (retry = 0; retry < 5; retry++) {
2447 reg = FDI_RX_IIR(pipe);
2448 temp = I915_READ(reg);
2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_BIT_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453 break;
2454 }
2455 udelay(50);
8db9d77b 2456 }
fa37d39e
SP		 2457 if (retry < 5)
2458 break;
8db9d77b
ZW		 2459 }
2460 if (i == 4)
5eddb70b 2461 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2462
2463 /* Train 2 */
5eddb70b
CW		 2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
2468 if (IS_GEN6(dev)) {
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 /* SNB-B */
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472 }
5eddb70b 2473 I915_WRITE(reg, temp);
8db9d77b 2474
5eddb70b
CW		 2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480 } else {
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 }
5eddb70b
CW		 2484 I915_WRITE(reg, temp);
2485
2486 POSTING_READ(reg);
8db9d77b
ZW		 2487 udelay(150);
2488
0206e353 2489 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
8db9d77b
ZW		 2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
8db9d77b
ZW		 2497 udelay(500);
2498
fa37d39e
SP		 2499 for (retry = 0; retry < 5; retry++) {
2500 reg = FDI_RX_IIR(pipe);
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503 if (temp & FDI_RX_SYMBOL_LOCK) {
2504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506 break;
2507 }
2508 udelay(50);
8db9d77b 2509 }
fa37d39e
SP		 2510 if (retry < 5)
2511 break;
8db9d77b
ZW		 2512 }
2513 if (i == 4)
5eddb70b 2514 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2515
2516 DRM_DEBUG_KMS("FDI train done.\n");
2517}
2518
357555c0
JB		 2519/* Manual link training for Ivy Bridge A0 parts */
2520static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2526 u32 reg, temp, i;
2527
2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
2537 udelay(150);
2538
01a415fd
DV		 2539 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540 I915_READ(FDI_RX_IIR(pipe)));
2541
357555c0
JB		 2542 /* enable CPU FDI TX and PCH FDI RX */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
627eb5a3
DV		 2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2551 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
d74cf324
DV		 2554 I915_WRITE(FDI_RX_MISC(pipe),
2555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
357555c0
JB		 2557 reg = FDI_RX_CTL(pipe);
2558 temp = I915_READ(reg);
2559 temp &= ~FDI_LINK_TRAIN_AUTO;
2560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2562 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
357555c0
JB		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582 if (temp & FDI_RX_BIT_LOCK ||
2583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp);
2600
2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
2608 udelay(150);
2609
0206e353 2610 for (i = 0; i < 4; i++) {
357555c0
JB		 2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(500);
2619
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
2625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2626 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2627 break;
2628 }
2629 }
2630 if (i == 4)
2631 DRM_ERROR("FDI train 2 fail!\n");
2632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634}
2635
88cefb6c 2636static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2637{
88cefb6c 2638 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2639 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2640 int pipe = intel_crtc->pipe;
5eddb70b 2641 u32 reg, temp;
79e53945 2642
c64e311e 2643
c98e9dcf 2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
627eb5a3
DV		 2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652 POSTING_READ(reg);
c98e9dcf
JB		 2653 udelay(200);
2654
2655 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2656 temp = I915_READ(reg);
2657 I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659 POSTING_READ(reg);
c98e9dcf
JB		 2660 udelay(200);
2661
20749730
PZ		 2662 /* Enable CPU FDI TX PLL, always on for Ironlake */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2667
20749730
PZ		 2668 POSTING_READ(reg);
2669 udelay(100);
6be4a607 2670 }
0e23b99d
JB		 2671}
2672
88cefb6c
DV		 2673static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674{
2675 struct drm_device *dev = intel_crtc->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int pipe = intel_crtc->pipe;
2678 u32 reg, temp;
2679
2680 /* Switch from PCDclk to Rawclk */
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685 /* Disable CPU FDI TX PLL */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
2691 udelay(100);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697 /* Wait for the clocks to turn off. */
2698 POSTING_READ(reg);
2699 udelay(100);
2700}
2701
0fc932b8
JB		 2702static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703{
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp;
2709
2710 /* disable CPU FDI tx and PCH FDI rx */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714 POSTING_READ(reg);
2715
2716 reg = FDI_RX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(0x7 << 16);
dfd07d72 2719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722 POSTING_READ(reg);
2723 udelay(100);
2724
2725 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2726 if (HAS_PCH_IBX(dev)) {
2727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2728 }
0fc932b8
JB		 2729
2730 /* still set train pattern 1 */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1;
2735 I915_WRITE(reg, temp);
2736
2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (HAS_PCH_CPT(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 }
2746 /* BPC in FDI rx is consistent with that in PIPECONF */
2747 temp &= ~(0x07 << 16);
dfd07d72 2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2749 I915_WRITE(reg, temp);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753}
2754
5bb61643
CW		 2755static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756{
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2760 unsigned long flags;
2761 bool pending;
2762
10d83730
VS		 2763 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2765 return false;
2766
2767 spin_lock_irqsave(&dev->event_lock, flags);
2768 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769 spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771 return pending;
2772}
2773
e6c3a2a6
CW		 2774static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775{
0f91128d 2776 struct drm_device *dev = crtc->dev;
5bb61643 2777 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2778
2779 if (crtc->fb == NULL)
2780 return;
2781
2c10d571
DV		 2782 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
5bb61643
CW		 2784 wait_event(dev_priv->pending_flip_queue,
2785 !intel_crtc_has_pending_flip(crtc));
2786
0f91128d
CW		 2787 mutex_lock(&dev->struct_mutex);
2788 intel_finish_fb(crtc->fb);
2789 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2790}
2791
e615efe4
ED		 2792/* Program iCLKIP clock to the desired frequency */
2793static void lpt_program_iclkip(struct drm_crtc *crtc)
2794{
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798 u32 temp;
2799
09153000
DV		 2800 mutex_lock(&dev_priv->dpio_lock);
2801
e615efe4
ED		 2802 /* It is necessary to ungate the pixclk gate prior to programming
2803 * the divisors, and gate it back when it is done.
2804 */
2805 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807 /* Disable SSCCTL */
2808 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2809 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810 SBI_SSCCTL_DISABLE,
2811 SBI_ICLK);
e615efe4
ED		 2812
2813 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814 if (crtc->mode.clock == 20000) {
2815 auxdiv = 1;
2816 divsel = 0x41;
2817 phaseinc = 0x20;
2818 } else {
2819 /* The iCLK virtual clock root frequency is in MHz,
2820 * but the crtc->mode.clock in in KHz. To get the divisors,
2821 * it is necessary to divide one by another, so we
2822 * convert the virtual clock precision to KHz here for higher
2823 * precision.
2824 */
2825 u32 iclk_virtual_root_freq = 172800 * 1000;
2826 u32 iclk_pi_range = 64;
2827 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830 msb_divisor_value = desired_divisor / iclk_pi_range;
2831 pi_value = desired_divisor % iclk_pi_range;
2832
2833 auxdiv = 0;
2834 divsel = msb_divisor_value - 2;
2835 phaseinc = pi_value;
2836 }
2837
2838 /* This should not happen with any sane values */
2839 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845 crtc->mode.clock,
2846 auxdiv,
2847 divsel,
2848 phasedir,
2849 phaseinc);
2850
2851 /* Program SSCDIVINTPHASE6 */
988d6ee8 2852 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2853 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2859 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2860
2861 /* Program SSCAUXDIV */
988d6ee8 2862 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2863 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2865 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2866
2867 /* Enable modulator and associated divider */
988d6ee8 2868 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2869 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2870 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2871
2872 /* Wait for initialization time */
2873 udelay(24);
2874
2875 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2876
2877 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2878}
2879
275f01b2
DV		 2880static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2882{
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2893
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902}
2903
f67a559d
JB		 2904/*
2905 * Enable PCH resources required for PCH ports:
2906 * - PCH PLLs
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2910 * - transcoder
2911 */
2912static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
ee7b9f93 2918 u32 reg, temp;
2c07245f 2919
ab9412ba 2920 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2921
cd986abb
DV		 2922 /* Write the TU size bits before fdi link training, so that error
2923 * detection works. */
2924 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
c98e9dcf 2927 /* For PCH output, training FDI link */
674cf967 2928 dev_priv->display.fdi_link_train(crtc);
2c07245f 2929
572deb37
DV		 2930 /* XXX: pch pll's can be enabled any time before we enable the PCH
2931 * transcoder, and we actually should do this to not upset any PCH
2932 * transcoder that already use the clock when we share it.
2933 *
e72f9fbf
DV		 2934 * Note that enable_shared_dpll tries to do the right thing, but
2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2936 * the right LVDS enable sequence. */
2937 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2938
303b81e0 2939 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2940 u32 sel;
4b645f14 2941
c98e9dcf 2942 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2943 temp |= TRANS_DPLL_ENABLE(pipe);
2944 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2946 temp |= sel;
2947 else
2948 temp &= ~sel;
c98e9dcf 2949 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2950 }
5eddb70b 2951
d9b6cb56
JB		 2952 /* set transcoder timing, panel must allow it */
2953 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2955
303b81e0 2956 intel_fdi_normal_train(crtc);
5e84e1a4 2957
c98e9dcf
JB		 2958 /* For PCH DP, enable TRANS_DP_CTL */
2959 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2960 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2962 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2963 reg = TRANS_DP_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2966 TRANS_DP_SYNC_MASK |
2967 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2968 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969 TRANS_DP_ENH_FRAMING);
9325c9f0 2970 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2971
2972 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2973 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2974 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2975 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2976
2977 switch (intel_trans_dp_port_sel(crtc)) {
2978 case PCH_DP_B:
5eddb70b 2979 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2980 break;
2981 case PCH_DP_C:
5eddb70b 2982 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2983 break;
2984 case PCH_DP_D:
5eddb70b 2985 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2986 break;
2987 default:
e95d41e1 2988 BUG();
32f9d658 2989 }
2c07245f 2990
5eddb70b 2991 I915_WRITE(reg, temp);
6be4a607 2992 }
b52eb4dc 2993
b8a4f404 2994 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 2995}
2996
1507e5bd
PZ		 2997static void lpt_pch_enable(struct drm_crtc *crtc)
2998{
2999 struct drm_device *dev = crtc->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3003
ab9412ba 3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3005
8c52b5e8 3006 lpt_program_iclkip(crtc);
1507e5bd 3007
0540e488 3008 /* Set transcoder timing. */
275f01b2 3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3010
937bb610 3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3012}
3013
e2b78267 3014static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3015{
e2b78267 3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3017
3018 if (pll == NULL)
3019 return;
3020
3021 if (pll->refcount == 0) {
46edb027 3022 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3023 return;
3024 }
3025
f4a091c7
DV		 3026 if (--pll->refcount == 0) {
3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
a43f6e0f 3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3032}
3033
e2b78267 3034static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
ee7b9f93 3035{
e2b78267
DV		 3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038 enum intel_dpll_id i;
ee7b9f93 3039
ee7b9f93 3040 if (pll) {
46edb027
DV		 3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042 crtc->base.base.id, pll->name);
e2b78267 3043 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3044 }
3045
98b6bd99
DV		 3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3048 i = crtc->pipe;
e72f9fbf 3049 pll = &dev_priv->shared_dplls[i];
98b6bd99 3050
46edb027
DV		 3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052 crtc->base.base.id, pll->name);
98b6bd99
DV		 3053
3054 goto found;
3055 }
3056
e72f9fbf
DV		 3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3059
3060 /* Only want to check enabled timings first */
3061 if (pll->refcount == 0)
3062 continue;
3063
e9a632a5
DV		 3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065 fp == I915_READ(PCH_FP0(pll->id))) {
46edb027 3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3067 crtc->base.base.id,
46edb027 3068 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3069
3070 goto found;
3071 }
3072 }
3073
3074 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3077 if (pll->refcount == 0) {
46edb027
DV		 3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3080 goto found;
3081 }
3082 }
3083
3084 return NULL;
3085
3086found:
a43f6e0f 3087 crtc->config.shared_dpll = i;
46edb027
DV		 3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089 pipe_name(crtc->pipe));
cdbd2316 3090 if (pll->active == 0) {
46edb027 3091 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3092 WARN_ON(pll->on);
e9d6944e 3093 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3094
cdbd2316 3095 /* Wait for the clocks to stabilize before rewriting the regs */
e9a632a5
DV		 3096 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3097 POSTING_READ(PCH_DPLL(pll->id));
cdbd2316
DV		 3098 udelay(150);
3099
e9a632a5
DV		 3100 I915_WRITE(PCH_FP0(pll->id), fp);
3101 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
cdbd2316
DV		 3102 }
3103 pll->refcount++;
e04c7350 3104
ee7b9f93
JB		 3105 return pll;
3106}
3107
a1520318 3108static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3109{
3110 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3111 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3112 u32 temp;
3113
3114 temp = I915_READ(dslreg);
3115 udelay(500);
3116 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3117 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3118 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3119 }
3120}
3121
b074cec8
JB		 3122static void ironlake_pfit_enable(struct intel_crtc *crtc)
3123{
3124 struct drm_device *dev = crtc->base.dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 int pipe = crtc->pipe;
3127
0ef37f3f 3128 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3129 /* Force use of hard-coded filter coefficients
3130 * as some pre-programmed values are broken,
3131 * e.g. x201.
3132 */
3133 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3134 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3135 PF_PIPE_SEL_IVB(pipe));
3136 else
3137 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3138 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3139 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3140 }
3141}
3142
bb53d4ae
VS		 3143static void intel_enable_planes(struct drm_crtc *crtc)
3144{
3145 struct drm_device *dev = crtc->dev;
3146 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3147 struct intel_plane *intel_plane;
3148
3149 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3150 if (intel_plane->pipe == pipe)
3151 intel_plane_restore(&intel_plane->base);
3152}
3153
3154static void intel_disable_planes(struct drm_crtc *crtc)
3155{
3156 struct drm_device *dev = crtc->dev;
3157 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3158 struct intel_plane *intel_plane;
3159
3160 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3161 if (intel_plane->pipe == pipe)
3162 intel_plane_disable(&intel_plane->base);
3163}
3164
f67a559d
JB		 3165static void ironlake_crtc_enable(struct drm_crtc *crtc)
3166{
3167 struct drm_device *dev = crtc->dev;
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3170 struct intel_encoder *encoder;
f67a559d
JB		 3171 int pipe = intel_crtc->pipe;
3172 int plane = intel_crtc->plane;
3173 u32 temp;
f67a559d 3174
08a48469
DV		 3175 WARN_ON(!crtc->enabled);
3176
f67a559d
JB		 3177 if (intel_crtc->active)
3178 return;
3179
3180 intel_crtc->active = true;
8664281b
PZ		 3181
3182 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3183 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3184
f67a559d
JB		 3185 intel_update_watermarks(dev);
3186
3187 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3188 temp = I915_READ(PCH_LVDS);
3189 if ((temp & LVDS_PORT_EN) == 0)
3190 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3191 }
3192
f67a559d 3193
5bfe2ac0 3194 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3195 /* Note: FDI PLL enabling _must_ be done before we enable the
3196 * cpu pipes, hence this is separate from all the other fdi/pch
3197 * enabling. */
88cefb6c 3198 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3199 } else {
3200 assert_fdi_tx_disabled(dev_priv, pipe);
3201 assert_fdi_rx_disabled(dev_priv, pipe);
3202 }
f67a559d 3203
bf49ec8c
DV		 3204 for_each_encoder_on_crtc(dev, crtc, encoder)
3205 if (encoder->pre_enable)
3206 encoder->pre_enable(encoder);
f67a559d
JB		 3207
3208 /* Enable panel fitting for LVDS */
b074cec8 3209 ironlake_pfit_enable(intel_crtc);
f67a559d 3210
9c54c0dd
JB		 3211 /*
3212 * On ILK+ LUT must be loaded before the pipe is running but with
3213 * clocks enabled
3214 */
3215 intel_crtc_load_lut(crtc);
3216
5bfe2ac0
DV		 3217 intel_enable_pipe(dev_priv, pipe,
3218 intel_crtc->config.has_pch_encoder);
f67a559d 3219 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3220 intel_enable_planes(crtc);
5c38d48c 3221 intel_crtc_update_cursor(crtc, true);
f67a559d 3222
5bfe2ac0 3223 if (intel_crtc->config.has_pch_encoder)
f67a559d 3224 ironlake_pch_enable(crtc);
c98e9dcf 3225
d1ebd816 3226 mutex_lock(&dev->struct_mutex);
bed4a673 3227 intel_update_fbc(dev);
d1ebd816
BW		 3228 mutex_unlock(&dev->struct_mutex);
3229
fa5c73b1
DV		 3230 for_each_encoder_on_crtc(dev, crtc, encoder)
3231 encoder->enable(encoder);
61b77ddd
DV		 3232
3233 if (HAS_PCH_CPT(dev))
a1520318 3234 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3235
3236 /*
3237 * There seems to be a race in PCH platform hw (at least on some
3238 * outputs) where an enabled pipe still completes any pageflip right
3239 * away (as if the pipe is off) instead of waiting for vblank. As soon
3240 * as the first vblank happend, everything works as expected. Hence just
3241 * wait for one vblank before returning to avoid strange things
3242 * happening.
3243 */
3244 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3245}
3246
42db64ef
PZ		 3247/* IPS only exists on ULT machines and is tied to pipe A. */
3248static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3249{
3250 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3251}
3252
3253static void hsw_enable_ips(struct intel_crtc *crtc)
3254{
3255 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3256
3257 if (!crtc->config.ips_enabled)
3258 return;
3259
3260 /* We can only enable IPS after we enable a plane and wait for a vblank.
3261 * We guarantee that the plane is enabled by calling intel_enable_ips
3262 * only after intel_enable_plane. And intel_enable_plane already waits
3263 * for a vblank, so all we need to do here is to enable the IPS bit. */
3264 assert_plane_enabled(dev_priv, crtc->plane);
3265 I915_WRITE(IPS_CTL, IPS_ENABLE);
3266}
3267
3268static void hsw_disable_ips(struct intel_crtc *crtc)
3269{
3270 struct drm_device *dev = crtc->base.dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272
3273 if (!crtc->config.ips_enabled)
3274 return;
3275
3276 assert_plane_enabled(dev_priv, crtc->plane);
3277 I915_WRITE(IPS_CTL, 0);
3278
3279 /* We need to wait for a vblank before we can disable the plane. */
3280 intel_wait_for_vblank(dev, crtc->pipe);
3281}
3282
4f771f10
PZ		 3283static void haswell_crtc_enable(struct drm_crtc *crtc)
3284{
3285 struct drm_device *dev = crtc->dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288 struct intel_encoder *encoder;
3289 int pipe = intel_crtc->pipe;
3290 int plane = intel_crtc->plane;
4f771f10
PZ		 3291
3292 WARN_ON(!crtc->enabled);
3293
3294 if (intel_crtc->active)
3295 return;
3296
3297 intel_crtc->active = true;
8664281b
PZ		 3298
3299 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3300 if (intel_crtc->config.has_pch_encoder)
3301 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3302
4f771f10
PZ		 3303 intel_update_watermarks(dev);
3304
5bfe2ac0 3305 if (intel_crtc->config.has_pch_encoder)
04945641 3306 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3307
3308 for_each_encoder_on_crtc(dev, crtc, encoder)
3309 if (encoder->pre_enable)
3310 encoder->pre_enable(encoder);
3311
1f544388 3312 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3313
1f544388 3314 /* Enable panel fitting for eDP */
b074cec8 3315 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3316
3317 /*
3318 * On ILK+ LUT must be loaded before the pipe is running but with
3319 * clocks enabled
3320 */
3321 intel_crtc_load_lut(crtc);
3322
1f544388 3323 intel_ddi_set_pipe_settings(crtc);
8228c251 3324 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3325
5bfe2ac0
DV		 3326 intel_enable_pipe(dev_priv, pipe,
3327 intel_crtc->config.has_pch_encoder);
4f771f10 3328 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3329 intel_enable_planes(crtc);
5c38d48c 3330 intel_crtc_update_cursor(crtc, true);
4f771f10 3331
42db64ef
PZ		 3332 hsw_enable_ips(intel_crtc);
3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3335 lpt_pch_enable(crtc);
4f771f10
PZ		 3336
3337 mutex_lock(&dev->struct_mutex);
3338 intel_update_fbc(dev);
3339 mutex_unlock(&dev->struct_mutex);
3340
4f771f10
PZ		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
3343
4f771f10
PZ		 3344 /*
3345 * There seems to be a race in PCH platform hw (at least on some
3346 * outputs) where an enabled pipe still completes any pageflip right
3347 * away (as if the pipe is off) instead of waiting for vblank. As soon
3348 * as the first vblank happend, everything works as expected. Hence just
3349 * wait for one vblank before returning to avoid strange things
3350 * happening.
3351 */
3352 intel_wait_for_vblank(dev, intel_crtc->pipe);
3353}
3354
3f8dce3a
DV		 3355static void ironlake_pfit_disable(struct intel_crtc *crtc)
3356{
3357 struct drm_device *dev = crtc->base.dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 int pipe = crtc->pipe;
3360
3361 /* To avoid upsetting the power well on haswell only disable the pfit if
3362 * it's in use. The hw state code will make sure we get this right. */
3363 if (crtc->config.pch_pfit.size) {
3364 I915_WRITE(PF_CTL(pipe), 0);
3365 I915_WRITE(PF_WIN_POS(pipe), 0);
3366 I915_WRITE(PF_WIN_SZ(pipe), 0);
3367 }
3368}
3369
6be4a607
JB		 3370static void ironlake_crtc_disable(struct drm_crtc *crtc)
3371{
3372 struct drm_device *dev = crtc->dev;
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3375 struct intel_encoder *encoder;
6be4a607
JB		 3376 int pipe = intel_crtc->pipe;
3377 int plane = intel_crtc->plane;
5eddb70b 3378 u32 reg, temp;
b52eb4dc 3379
ef9c3aee 3380
f7abfe8b
CW		 3381 if (!intel_crtc->active)
3382 return;
3383
ea9d758d
DV		 3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 encoder->disable(encoder);
3386
e6c3a2a6 3387 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3388 drm_vblank_off(dev, pipe);
913d8d11 3389
973d04f9
CW		 3390 if (dev_priv->cfb_plane == plane)
3391 intel_disable_fbc(dev);
2c07245f 3392
0d5b8c61 3393 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3394 intel_disable_planes(crtc);
0d5b8c61
VS		 3395 intel_disable_plane(dev_priv, plane, pipe);
3396
d925c59a
DV		 3397 if (intel_crtc->config.has_pch_encoder)
3398 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3399
b24e7179 3400 intel_disable_pipe(dev_priv, pipe);
32f9d658 3401
3f8dce3a 3402 ironlake_pfit_disable(intel_crtc);
2c07245f 3403
bf49ec8c
DV		 3404 for_each_encoder_on_crtc(dev, crtc, encoder)
3405 if (encoder->post_disable)
3406 encoder->post_disable(encoder);
2c07245f 3407
d925c59a
DV		 3408 if (intel_crtc->config.has_pch_encoder) {
3409 ironlake_fdi_disable(crtc);
249c0e64 3410
d925c59a
DV		 3411 ironlake_disable_pch_transcoder(dev_priv, pipe);
3412 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3413
d925c59a
DV		 3414 if (HAS_PCH_CPT(dev)) {
3415 /* disable TRANS_DP_CTL */
3416 reg = TRANS_DP_CTL(pipe);
3417 temp = I915_READ(reg);
3418 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3419 TRANS_DP_PORT_SEL_MASK);
3420 temp |= TRANS_DP_PORT_SEL_NONE;
3421 I915_WRITE(reg, temp);
3422
3423 /* disable DPLL_SEL */
3424 temp = I915_READ(PCH_DPLL_SEL);
11887397 3425 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3426 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3427 }
e3421a18 3428
d925c59a 3429 /* disable PCH DPLL */
e72f9fbf 3430 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3431
d925c59a
DV		 3432 ironlake_fdi_pll_disable(intel_crtc);
3433 }
6b383a7f 3434
f7abfe8b 3435 intel_crtc->active = false;
6b383a7f 3436 intel_update_watermarks(dev);
d1ebd816
BW		 3437
3438 mutex_lock(&dev->struct_mutex);
6b383a7f 3439 intel_update_fbc(dev);
d1ebd816 3440 mutex_unlock(&dev->struct_mutex);
6be4a607 3441}
1b3c7a47 3442
4f771f10 3443static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3444{
4f771f10
PZ		 3445 struct drm_device *dev = crtc->dev;
3446 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3448 struct intel_encoder *encoder;
3449 int pipe = intel_crtc->pipe;
3450 int plane = intel_crtc->plane;
3b117c8f 3451 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3452
4f771f10
PZ		 3453 if (!intel_crtc->active)
3454 return;
3455
3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 encoder->disable(encoder);
3458
3459 intel_crtc_wait_for_pending_flips(crtc);
3460 drm_vblank_off(dev, pipe);
4f771f10 3461
891348b2 3462 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3463 if (dev_priv->cfb_plane == plane)
3464 intel_disable_fbc(dev);
3465
42db64ef
PZ		 3466 hsw_disable_ips(intel_crtc);
3467
0d5b8c61 3468 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3469 intel_disable_planes(crtc);
891348b2
RV		 3470 intel_disable_plane(dev_priv, plane, pipe);
3471
8664281b
PZ		 3472 if (intel_crtc->config.has_pch_encoder)
3473 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3474 intel_disable_pipe(dev_priv, pipe);
3475
ad80a810 3476 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3477
3f8dce3a 3478 ironlake_pfit_disable(intel_crtc);
4f771f10 3479
1f544388 3480 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3481
3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 if (encoder->post_disable)
3484 encoder->post_disable(encoder);
3485
88adfff1 3486 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3487 lpt_disable_pch_transcoder(dev_priv);
8664281b 3488 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3489 intel_ddi_fdi_disable(crtc);
83616634 3490 }
4f771f10
PZ		 3491
3492 intel_crtc->active = false;
3493 intel_update_watermarks(dev);
3494
3495 mutex_lock(&dev->struct_mutex);
3496 intel_update_fbc(dev);
3497 mutex_unlock(&dev->struct_mutex);
3498}
3499
ee7b9f93
JB		 3500static void ironlake_crtc_off(struct drm_crtc *crtc)
3501{
3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3503 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3504}
3505
6441ab5f
PZ		 3506static void haswell_crtc_off(struct drm_crtc *crtc)
3507{
3508 intel_ddi_put_crtc_pll(crtc);
3509}
3510
02e792fb
DV		 3511static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3512{
02e792fb 3513 if (!enable && intel_crtc->overlay) {
23f09ce3 3514 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3515 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3516
23f09ce3 3517 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3518 dev_priv->mm.interruptible = false;
3519 (void) intel_overlay_switch_off(intel_crtc->overlay);
3520 dev_priv->mm.interruptible = true;
23f09ce3 3521 mutex_unlock(&dev->struct_mutex);
02e792fb 3522 }
02e792fb 3523
5dcdbcb0
CW		 3524 /* Let userspace switch the overlay on again. In most cases userspace
3525 * has to recompute where to put it anyway.
3526 */
02e792fb
DV		 3527}
3528
61bc95c1
EE		 3529/**
3530 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3531 * cursor plane briefly if not already running after enabling the display
3532 * plane.
3533 * This workaround avoids occasional blank screens when self refresh is
3534 * enabled.
3535 */
3536static void
3537g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3538{
3539 u32 cntl = I915_READ(CURCNTR(pipe));
3540
3541 if ((cntl & CURSOR_MODE) == 0) {
3542 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3543
3544 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3545 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3546 intel_wait_for_vblank(dev_priv->dev, pipe);
3547 I915_WRITE(CURCNTR(pipe), cntl);
3548 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3549 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3550 }
3551}
3552
2dd24552
JB		 3553static void i9xx_pfit_enable(struct intel_crtc *crtc)
3554{
3555 struct drm_device *dev = crtc->base.dev;
3556 struct drm_i915_private *dev_priv = dev->dev_private;
3557 struct intel_crtc_config *pipe_config = &crtc->config;
3558
328d8e82 3559 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3560 return;
3561
2dd24552 3562 /*
c0b03411
DV		 3563 * The panel fitter should only be adjusted whilst the pipe is disabled,
3564 * according to register description and PRM.
2dd24552 3565 */
c0b03411
DV		 3566 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3567 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3568
b074cec8
JB		 3569 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3570 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3571
3572 /* Border color in case we don't scale up to the full screen. Black by
3573 * default, change to something else for debugging. */
3574 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3575}
3576
89b667f8
JB		 3577static void valleyview_crtc_enable(struct drm_crtc *crtc)
3578{
3579 struct drm_device *dev = crtc->dev;
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3582 struct intel_encoder *encoder;
3583 int pipe = intel_crtc->pipe;
3584 int plane = intel_crtc->plane;
3585
3586 WARN_ON(!crtc->enabled);
3587
3588 if (intel_crtc->active)
3589 return;
3590
3591 intel_crtc->active = true;
3592 intel_update_watermarks(dev);
3593
3594 mutex_lock(&dev_priv->dpio_lock);
3595
3596 for_each_encoder_on_crtc(dev, crtc, encoder)
3597 if (encoder->pre_pll_enable)
3598 encoder->pre_pll_enable(encoder);
3599
3600 intel_enable_pll(dev_priv, pipe);
3601
3602 for_each_encoder_on_crtc(dev, crtc, encoder)
3603 if (encoder->pre_enable)
3604 encoder->pre_enable(encoder);
3605
3606 /* VLV wants encoder enabling _before_ the pipe is up. */
3607 for_each_encoder_on_crtc(dev, crtc, encoder)
3608 encoder->enable(encoder);
3609
2dd24552
JB		 3610 /* Enable panel fitting for eDP */
3611 i9xx_pfit_enable(intel_crtc);
3612
63cbb074
VS		 3613 intel_crtc_load_lut(crtc);
3614
89b667f8
JB		 3615 intel_enable_pipe(dev_priv, pipe, false);
3616 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3617 intel_enable_planes(crtc);
5c38d48c 3618 intel_crtc_update_cursor(crtc, true);
89b667f8 3619
f440eb13
VS		 3620 intel_update_fbc(dev);
3621
89b667f8
JB		 3622 mutex_unlock(&dev_priv->dpio_lock);
3623}
3624
0b8765c6 3625static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3626{
3627 struct drm_device *dev = crtc->dev;
79e53945
JB		 3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3630 struct intel_encoder *encoder;
79e53945 3631 int pipe = intel_crtc->pipe;
80824003 3632 int plane = intel_crtc->plane;
79e53945 3633
08a48469
DV		 3634 WARN_ON(!crtc->enabled);
3635
f7abfe8b
CW		 3636 if (intel_crtc->active)
3637 return;
3638
3639 intel_crtc->active = true;
6b383a7f
CW		 3640 intel_update_watermarks(dev);
3641
63d7bbe9 3642 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3643
3644 for_each_encoder_on_crtc(dev, crtc, encoder)
3645 if (encoder->pre_enable)
3646 encoder->pre_enable(encoder);
3647
2dd24552
JB		 3648 /* Enable panel fitting for LVDS */
3649 i9xx_pfit_enable(intel_crtc);
3650
63cbb074
VS		 3651 intel_crtc_load_lut(crtc);
3652
040484af 3653 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3654 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3655 intel_enable_planes(crtc);
22e407d7 3656 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3657 if (IS_G4X(dev))
3658 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3659 intel_crtc_update_cursor(crtc, true);
79e53945 3660
0b8765c6
JB		 3661 /* Give the overlay scaler a chance to enable if it's on this pipe */
3662 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3663
f440eb13
VS		 3664 intel_update_fbc(dev);
3665
fa5c73b1
DV		 3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 encoder->enable(encoder);
0b8765c6 3668}
79e53945 3669
87476d63
DV		 3670static void i9xx_pfit_disable(struct intel_crtc *crtc)
3671{
3672 struct drm_device *dev = crtc->base.dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3674
328d8e82
DV		 3675 if (!crtc->config.gmch_pfit.control)
3676 return;
87476d63 3677
328d8e82 3678 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3679
328d8e82
DV		 3680 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3681 I915_READ(PFIT_CONTROL));
3682 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3683}
3684
0b8765c6
JB		 3685static void i9xx_crtc_disable(struct drm_crtc *crtc)
3686{
3687 struct drm_device *dev = crtc->dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3690 struct intel_encoder *encoder;
0b8765c6
JB		 3691 int pipe = intel_crtc->pipe;
3692 int plane = intel_crtc->plane;
ef9c3aee 3693
f7abfe8b
CW		 3694 if (!intel_crtc->active)
3695 return;
3696
ea9d758d
DV		 3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 encoder->disable(encoder);
3699
0b8765c6 3700 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3701 intel_crtc_wait_for_pending_flips(crtc);
3702 drm_vblank_off(dev, pipe);
0b8765c6 3703
973d04f9
CW		 3704 if (dev_priv->cfb_plane == plane)
3705 intel_disable_fbc(dev);
79e53945 3706
0d5b8c61
VS		 3707 intel_crtc_dpms_overlay(intel_crtc, false);
3708 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3709 intel_disable_planes(crtc);
b24e7179 3710 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3711
b24e7179 3712 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3713
87476d63 3714 i9xx_pfit_disable(intel_crtc);
24a1f16d 3715
89b667f8
JB		 3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->post_disable)
3718 encoder->post_disable(encoder);
3719
63d7bbe9 3720 intel_disable_pll(dev_priv, pipe);
0b8765c6 3721
f7abfe8b 3722 intel_crtc->active = false;
6b383a7f
CW		 3723 intel_update_fbc(dev);
3724 intel_update_watermarks(dev);
0b8765c6
JB		 3725}
3726
ee7b9f93
JB		 3727static void i9xx_crtc_off(struct drm_crtc *crtc)
3728{
3729}
3730
976f8a20
DV		 3731static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3732 bool enabled)
2c07245f
ZW		 3733{
3734 struct drm_device *dev = crtc->dev;
3735 struct drm_i915_master_private *master_priv;
3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737 int pipe = intel_crtc->pipe;
79e53945
JB		 3738
3739 if (!dev->primary->master)
3740 return;
3741
3742 master_priv = dev->primary->master->driver_priv;
3743 if (!master_priv->sarea_priv)
3744 return;
3745
79e53945
JB		 3746 switch (pipe) {
3747 case 0:
3748 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3749 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3750 break;
3751 case 1:
3752 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 default:
9db4a9c7 3756 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3757 break;
3758 }
79e53945
JB		 3759}
3760
976f8a20
DV		 3761/**
3762 * Sets the power management mode of the pipe and plane.
3763 */
3764void intel_crtc_update_dpms(struct drm_crtc *crtc)
3765{
3766 struct drm_device *dev = crtc->dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 struct intel_encoder *intel_encoder;
3769 bool enable = false;
3770
3771 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3772 enable |= intel_encoder->connectors_active;
3773
3774 if (enable)
3775 dev_priv->display.crtc_enable(crtc);
3776 else
3777 dev_priv->display.crtc_disable(crtc);
3778
3779 intel_crtc_update_sarea(crtc, enable);
3780}
3781
cdd59983
CW		 3782static void intel_crtc_disable(struct drm_crtc *crtc)
3783{
cdd59983 3784 struct drm_device *dev = crtc->dev;
976f8a20 3785 struct drm_connector *connector;
ee7b9f93 3786 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3788
976f8a20
DV		 3789 /* crtc should still be enabled when we disable it. */
3790 WARN_ON(!crtc->enabled);
3791
3792 dev_priv->display.crtc_disable(crtc);
c77bf565 3793 intel_crtc->eld_vld = false;
976f8a20 3794 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3795 dev_priv->display.off(crtc);
3796
931872fc
CW		 3797 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3798 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3799
3800 if (crtc->fb) {
3801 mutex_lock(&dev->struct_mutex);
1690e1eb 3802 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3803 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3804 crtc->fb = NULL;
3805 }
3806
3807 /* Update computed state. */
3808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3809 if (!connector->encoder || !connector->encoder->crtc)
3810 continue;
3811
3812 if (connector->encoder->crtc != crtc)
3813 continue;
3814
3815 connector->dpms = DRM_MODE_DPMS_OFF;
3816 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3817 }
3818}
3819
a261b246 3820void intel_modeset_disable(struct drm_device *dev)
79e53945 3821{
a261b246
DV		 3822 struct drm_crtc *crtc;
3823
3824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3825 if (crtc->enabled)
3826 intel_crtc_disable(crtc);
3827 }
79e53945
JB		 3828}
3829
ea5b213a 3830void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3831{
4ef69c7a 3832 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3833
ea5b213a
CW		 3834 drm_encoder_cleanup(encoder);
3835 kfree(intel_encoder);
7e7d76c3
JB		 3836}
3837
5ab432ef
DV		 3838/* Simple dpms helper for encodres with just one connector, no cloning and only
3839 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3840 * state of the entire output pipe. */
3841void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3842{
5ab432ef
DV		 3843 if (mode == DRM_MODE_DPMS_ON) {
3844 encoder->connectors_active = true;
3845
b2cabb0e 3846 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3847 } else {
3848 encoder->connectors_active = false;
3849
b2cabb0e 3850 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3851 }
79e53945
JB		 3852}
3853
0a91ca29
DV		 3854/* Cross check the actual hw state with our own modeset state tracking (and it's
3855 * internal consistency). */
b980514c 3856static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3857{
0a91ca29
DV		 3858 if (connector->get_hw_state(connector)) {
3859 struct intel_encoder *encoder = connector->encoder;
3860 struct drm_crtc *crtc;
3861 bool encoder_enabled;
3862 enum pipe pipe;
3863
3864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3865 connector->base.base.id,
3866 drm_get_connector_name(&connector->base));
3867
3868 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3869 "wrong connector dpms state\n");
3870 WARN(connector->base.encoder != &encoder->base,
3871 "active connector not linked to encoder\n");
3872 WARN(!encoder->connectors_active,
3873 "encoder->connectors_active not set\n");
3874
3875 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3876 WARN(!encoder_enabled, "encoder not enabled\n");
3877 if (WARN_ON(!encoder->base.crtc))
3878 return;
3879
3880 crtc = encoder->base.crtc;
3881
3882 WARN(!crtc->enabled, "crtc not enabled\n");
3883 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3884 WARN(pipe != to_intel_crtc(crtc)->pipe,
3885 "encoder active on the wrong pipe\n");
3886 }
79e53945
JB		 3887}
3888
5ab432ef
DV		 3889/* Even simpler default implementation, if there's really no special case to
3890 * consider. */
3891void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3892{
5ab432ef 3893 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3894
5ab432ef
DV		 3895 /* All the simple cases only support two dpms states. */
3896 if (mode != DRM_MODE_DPMS_ON)
3897 mode = DRM_MODE_DPMS_OFF;
d4270e57 3898
5ab432ef
DV		 3899 if (mode == connector->dpms)
3900 return;
3901
3902 connector->dpms = mode;
3903
3904 /* Only need to change hw state when actually enabled */
3905 if (encoder->base.crtc)
3906 intel_encoder_dpms(encoder, mode);
3907 else
8af6cf88 3908 WARN_ON(encoder->connectors_active != false);
0a91ca29 3909
b980514c 3910 intel_modeset_check_state(connector->dev);
79e53945
JB		 3911}
3912
f0947c37
DV		 3913/* Simple connector->get_hw_state implementation for encoders that support only
3914 * one connector and no cloning and hence the encoder state determines the state
3915 * of the connector. */
3916bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3917{
24929352 3918 enum pipe pipe = 0;
f0947c37 3919 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3920
f0947c37 3921 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3922}
3923
1857e1da
DV		 3924static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3925 struct intel_crtc_config *pipe_config)
3926{
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *pipe_B_crtc =
3929 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3930
3931 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3932 pipe_name(pipe), pipe_config->fdi_lanes);
3933 if (pipe_config->fdi_lanes > 4) {
3934 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3935 pipe_name(pipe), pipe_config->fdi_lanes);
3936 return false;
3937 }
3938
3939 if (IS_HASWELL(dev)) {
3940 if (pipe_config->fdi_lanes > 2) {
3941 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3942 pipe_config->fdi_lanes);
3943 return false;
3944 } else {
3945 return true;
3946 }
3947 }
3948
3949 if (INTEL_INFO(dev)->num_pipes == 2)
3950 return true;
3951
3952 /* Ivybridge 3 pipe is really complicated */
3953 switch (pipe) {
3954 case PIPE_A:
3955 return true;
3956 case PIPE_B:
3957 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3958 pipe_config->fdi_lanes > 2) {
3959 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3960 pipe_name(pipe), pipe_config->fdi_lanes);
3961 return false;
3962 }
3963 return true;
3964 case PIPE_C:
1e833f40 3965 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3966 pipe_B_crtc->config.fdi_lanes <= 2) {
3967 if (pipe_config->fdi_lanes > 2) {
3968 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3969 pipe_name(pipe), pipe_config->fdi_lanes);
3970 return false;
3971 }
3972 } else {
3973 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3974 return false;
3975 }
3976 return true;
3977 default:
3978 BUG();
3979 }
3980}
3981
e29c22c0
DV		 3982#define RETRY 1
3983static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3984 struct intel_crtc_config *pipe_config)
877d48d5 3985{
1857e1da 3986 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 3988 int lane, link_bw, fdi_dotclock;
e29c22c0 3989 bool setup_ok, needs_recompute = false;
877d48d5 3990
e29c22c0 3991retry:
877d48d5
DV		 3992 /* FDI is a binary signal running at ~2.7GHz, encoding
3993 * each output octet as 10 bits. The actual frequency
3994 * is stored as a divider into a 100MHz clock, and the
3995 * mode pixel clock is stored in units of 1KHz.
3996 * Hence the bw of each lane in terms of the mode signal
3997 * is:
3998 */
3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4000
ff9a6750 4001 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4002 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4003
4004 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4005 pipe_config->pipe_bpp);
4006
4007 pipe_config->fdi_lanes = lane;
4008
2bd89a07 4009 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4010 link_bw, &pipe_config->fdi_m_n);
1857e1da 4011
e29c22c0
DV		 4012 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4013 intel_crtc->pipe, pipe_config);
4014 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4015 pipe_config->pipe_bpp -= 2*3;
4016 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4017 pipe_config->pipe_bpp);
4018 needs_recompute = true;
4019 pipe_config->bw_constrained = true;
4020
4021 goto retry;
4022 }
4023
4024 if (needs_recompute)
4025 return RETRY;
4026
4027 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4028}
4029
42db64ef
PZ		 4030static void hsw_compute_ips_config(struct intel_crtc *crtc,
4031 struct intel_crtc_config *pipe_config)
4032{
3c4ca58c
PZ		 4033 pipe_config->ips_enabled = i915_enable_ips &&
4034 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4035 pipe_config->pipe_bpp == 24;
4036}
4037
a43f6e0f 4038static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4039 struct intel_crtc_config *pipe_config)
79e53945 4040{
a43f6e0f 4041 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4043
bad720ff 4044 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4045 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4046 if (pipe_config->requested_mode.clock * 3
4047 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4048 return -EINVAL;
2c07245f 4049 }
89749350 4050
f9bef081
DV		 4051 /* All interlaced capable intel hw wants timings in frames. Note though
4052 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4053 * timings, so we need to be careful not to clobber these.*/
7ae89233 4054 if (!pipe_config->timings_set)
f9bef081 4055 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4056
8693a824
DL		 4057 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4058 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4059 */
4060 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4061 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4062 return -EINVAL;
44f46b42 4063
bd080ee5 4064 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4065 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4066 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4067 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4068 * for lvds. */
4069 pipe_config->pipe_bpp = 8*3;
4070 }
4071
42db64ef 4072 if (IS_HASWELL(dev))
a43f6e0f
DV		 4073 hsw_compute_ips_config(crtc, pipe_config);
4074
4075 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4076 * clock survives for now. */
4077 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4078 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4079
877d48d5 4080 if (pipe_config->has_pch_encoder)
a43f6e0f 4081 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4082
e29c22c0 4083 return 0;
79e53945
JB		 4084}
4085
25eb05fc
JB		 4086static int valleyview_get_display_clock_speed(struct drm_device *dev)
4087{
4088 return 400000; /* FIXME */
4089}
4090
e70236a8
JB		 4091static int i945_get_display_clock_speed(struct drm_device *dev)
4092{
4093 return 400000;
4094}
79e53945 4095
e70236a8 4096static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4097{
e70236a8
JB		 4098 return 333000;
4099}
79e53945 4100
e70236a8
JB		 4101static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4102{
4103 return 200000;
4104}
79e53945 4105
e70236a8
JB		 4106static int i915gm_get_display_clock_speed(struct drm_device *dev)
4107{
4108 u16 gcfgc = 0;
79e53945 4109
e70236a8
JB		 4110 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4111
4112 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4113 return 133000;
4114 else {
4115 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4116 case GC_DISPLAY_CLOCK_333_MHZ:
4117 return 333000;
4118 default:
4119 case GC_DISPLAY_CLOCK_190_200_MHZ:
4120 return 190000;
79e53945 4121 }
e70236a8
JB		 4122 }
4123}
4124
4125static int i865_get_display_clock_speed(struct drm_device *dev)
4126{
4127 return 266000;
4128}
4129
4130static int i855_get_display_clock_speed(struct drm_device *dev)
4131{
4132 u16 hpllcc = 0;
4133 /* Assume that the hardware is in the high speed state. This
4134 * should be the default.
4135 */
4136 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4137 case GC_CLOCK_133_200:
4138 case GC_CLOCK_100_200:
4139 return 200000;
4140 case GC_CLOCK_166_250:
4141 return 250000;
4142 case GC_CLOCK_100_133:
79e53945 4143 return 133000;
e70236a8 4144 }
79e53945 4145
e70236a8
JB		 4146 /* Shouldn't happen */
4147 return 0;
4148}
79e53945 4149
e70236a8
JB		 4150static int i830_get_display_clock_speed(struct drm_device *dev)
4151{
4152 return 133000;
79e53945
JB		 4153}
4154
2c07245f 4155static void
a65851af 4156intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4157{
a65851af
VS		 4158 while (*num > DATA_LINK_M_N_MASK ||
4159 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4160 *num >>= 1;
4161 *den >>= 1;
4162 }
4163}
4164
a65851af
VS		 4165static void compute_m_n(unsigned int m, unsigned int n,
4166 uint32_t *ret_m, uint32_t *ret_n)
4167{
4168 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4169 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4170 intel_reduce_m_n_ratio(ret_m, ret_n);
4171}
4172
e69d0bc1
DV		 4173void
4174intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4175 int pixel_clock, int link_clock,
4176 struct intel_link_m_n *m_n)
2c07245f 4177{
e69d0bc1 4178 m_n->tu = 64;
a65851af
VS		 4179
4180 compute_m_n(bits_per_pixel * pixel_clock,
4181 link_clock * nlanes * 8,
4182 &m_n->gmch_m, &m_n->gmch_n);
4183
4184 compute_m_n(pixel_clock, link_clock,
4185 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4186}
4187
a7615030
CW		 4188static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4189{
72bbe58c
KP		 4190 if (i915_panel_use_ssc >= 0)
4191 return i915_panel_use_ssc != 0;
41aa3448 4192 return dev_priv->vbt.lvds_use_ssc
435793df 4193 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4194}
4195
a0c4da24
JB		 4196static int vlv_get_refclk(struct drm_crtc *crtc)
4197{
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int refclk = 27000; /* for DP & HDMI */
4201
4202 return 100000; /* only one validated so far */
4203
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4205 refclk = 96000;
4206 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207 if (intel_panel_use_ssc(dev_priv))
4208 refclk = 100000;
4209 else
4210 refclk = 96000;
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4212 refclk = 100000;
4213 }
4214
4215 return refclk;
4216}
4217
c65d77d8
JB		 4218static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4219{
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 int refclk;
4223
a0c4da24
JB		 4224 if (IS_VALLEYVIEW(dev)) {
4225 refclk = vlv_get_refclk(crtc);
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4227 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4228 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4229 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4230 refclk / 1000);
4231 } else if (!IS_GEN2(dev)) {
4232 refclk = 96000;
4233 } else {
4234 refclk = 48000;
4235 }
4236
4237 return refclk;
4238}
4239
7429e9d4
DV		 4240static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4241{
7df00d7a 4242 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4
DV		 4243}
4244
4245static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4246{
4247 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4248}
4249
f47709a9 4250static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4251 intel_clock_t *reduced_clock)
4252{
f47709a9 4253 struct drm_device *dev = crtc->base.dev;
a7516a05 4254 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4255 int pipe = crtc->pipe;
a7516a05
JB		 4256 u32 fp, fp2 = 0;
4257
4258 if (IS_PINEVIEW(dev)) {
7429e9d4 4259 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4260 if (reduced_clock)
7429e9d4 4261 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4262 } else {
7429e9d4 4263 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4264 if (reduced_clock)
7429e9d4 4265 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4266 }
4267
4268 I915_WRITE(FP0(pipe), fp);
4269
f47709a9
DV		 4270 crtc->lowfreq_avail = false;
4271 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4272 reduced_clock && i915_powersave) {
4273 I915_WRITE(FP1(pipe), fp2);
f47709a9 4274 crtc->lowfreq_avail = true;
a7516a05
JB		 4275 } else {
4276 I915_WRITE(FP1(pipe), fp);
4277 }
4278}
4279
89b667f8
JB		 4280static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4281{
4282 u32 reg_val;
4283
4284 /*
4285 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286 * and set it to a reasonable value instead.
4287 */
ae99258f 4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4289 reg_val &= 0xffffff00;
4290 reg_val |= 0x00000030;
ae99258f 4291 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4292
ae99258f 4293 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4294 reg_val &= 0x8cffffff;
4295 reg_val = 0x8c000000;
ae99258f 4296 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4297
ae99258f 4298 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4299 reg_val &= 0xffffff00;
ae99258f 4300 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4301
ae99258f 4302 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4303 reg_val &= 0x00ffffff;
4304 reg_val |= 0xb0000000;
ae99258f 4305 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4306}
4307
b551842d
DV		 4308static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309 struct intel_link_m_n *m_n)
4310{
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4314
e3b95f1e
DV		 4315 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4319}
4320
4321static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322 struct intel_link_m_n *m_n)
4323{
4324 struct drm_device *dev = crtc->base.dev;
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 int pipe = crtc->pipe;
4327 enum transcoder transcoder = crtc->config.cpu_transcoder;
4328
4329 if (INTEL_INFO(dev)->gen >= 5) {
4330 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4334 } else {
e3b95f1e
DV		 4335 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4339 }
4340}
4341
03afc4a2
DV		 4342static void intel_dp_set_m_n(struct intel_crtc *crtc)
4343{
4344 if (crtc->config.has_pch_encoder)
4345 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4346 else
4347 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4348}
4349
f47709a9 4350static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4351{
f47709a9 4352 struct drm_device *dev = crtc->base.dev;
a0c4da24 4353 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4354 struct intel_encoder *encoder;
f47709a9 4355 int pipe = crtc->pipe;
89b667f8 4356 u32 dpll, mdiv;
a0c4da24 4357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4358 bool is_hdmi;
198a037f 4359 u32 coreclk, reg_val, dpll_md;
a0c4da24 4360
09153000
DV		 4361 mutex_lock(&dev_priv->dpio_lock);
4362
89b667f8 4363 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4364
f47709a9
DV		 4365 bestn = crtc->config.dpll.n;
4366 bestm1 = crtc->config.dpll.m1;
4367 bestm2 = crtc->config.dpll.m2;
4368 bestp1 = crtc->config.dpll.p1;
4369 bestp2 = crtc->config.dpll.p2;
a0c4da24 4370
89b667f8
JB		 4371 /* See eDP HDMI DPIO driver vbios notes doc */
4372
4373 /* PLL B needs special handling */
4374 if (pipe)
4375 vlv_pllb_recal_opamp(dev_priv);
4376
4377 /* Set up Tx target for periodic Rcomp update */
ae99258f 4378 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4379
4380 /* Disable target IRef on PLL */
ae99258f 4381 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4382 reg_val &= 0x00ffffff;
ae99258f 4383 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4384
4385 /* Disable fast lock */
ae99258f 4386 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4387
4388 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4389 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4390 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4391 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4392 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4393
4394 /*
4395 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4396 * but we don't support that).
4397 * Note: don't use the DAC post divider as it seems unstable.
4398 */
4399 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4400 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4401
89b667f8 4402 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4404
89b667f8 4405 /* Set HBR and RBR LPF coefficients */
ff9a6750 4406 if (crtc->config.port_clock == 162000 ||
89b667f8 4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4408 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4409 0x005f0021);
4410 else
ae99258f 4411 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4412 0x00d0000f);
4413
4414 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4415 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4416 /* Use SSC source */
4417 if (!pipe)
ae99258f 4418 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4419 0x0df40000);
4420 else
ae99258f 4421 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4422 0x0df70000);
4423 } else { /* HDMI or VGA */
4424 /* Use bend source */
4425 if (!pipe)
ae99258f 4426 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4427 0x0df70000);
4428 else
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4430 0x0df40000);
4431 }
a0c4da24 4432
ae99258f 4433 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4434 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4435 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4436 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4437 coreclk |= 0x01000000;
ae99258f 4438 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4439
ae99258f 4440 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4441
89b667f8
JB		 4442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4443 if (encoder->pre_pll_enable)
4444 encoder->pre_pll_enable(encoder);
2a8f64ca 4445
89b667f8
JB		 4446 /* Enable DPIO clock input */
4447 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4448 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4449 if (pipe)
4450 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4451
89b667f8 4452 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4453 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4454 POSTING_READ(DPLL(pipe));
4455 udelay(150);
a0c4da24 4456
89b667f8
JB		 4457 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4458 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4459
ef1b460d
DV		 4460 dpll_md = (crtc->config.pixel_multiplier - 1)
4461 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4462 I915_WRITE(DPLL_MD(pipe), dpll_md);
4463 POSTING_READ(DPLL_MD(pipe));
f47709a9 4464
89b667f8
JB		 4465 if (crtc->config.has_dp_encoder)
4466 intel_dp_set_m_n(crtc);
09153000
DV		 4467
4468 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4469}
4470
f47709a9
DV		 4471static void i9xx_update_pll(struct intel_crtc *crtc,
4472 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4473 int num_connectors)
4474{
f47709a9 4475 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4476 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4477 struct intel_encoder *encoder;
f47709a9 4478 int pipe = crtc->pipe;
eb1cbe48
DV		 4479 u32 dpll;
4480 bool is_sdvo;
f47709a9 4481 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4482
f47709a9 4483 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4484
f47709a9
DV		 4485 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4486 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4487
4488 dpll = DPLL_VGA_MODE_DIS;
4489
f47709a9 4490 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4491 dpll |= DPLLB_MODE_LVDS;
4492 else
4493 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4494
ef1b460d 4495 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4496 dpll |= (crtc->config.pixel_multiplier - 1)
4497 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4498 }
198a037f
DV		 4499
4500 if (is_sdvo)
4501 dpll |= DPLL_DVO_HIGH_SPEED;
4502
f47709a9 4503 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4504 dpll |= DPLL_DVO_HIGH_SPEED;
4505
4506 /* compute bitmask from p1 value */
4507 if (IS_PINEVIEW(dev))
4508 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4509 else {
4510 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4511 if (IS_G4X(dev) && reduced_clock)
4512 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4513 }
4514 switch (clock->p2) {
4515 case 5:
4516 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4517 break;
4518 case 7:
4519 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4520 break;
4521 case 10:
4522 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4523 break;
4524 case 14:
4525 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4526 break;
4527 }
4528 if (INTEL_INFO(dev)->gen >= 4)
4529 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4530
09ede541 4531 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4532 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4533 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4534 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4535 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4536 else
4537 dpll |= PLL_REF_INPUT_DREFCLK;
4538
4539 dpll |= DPLL_VCO_ENABLE;
4540 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4541 POSTING_READ(DPLL(pipe));
4542 udelay(150);
4543
f47709a9 4544 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4545 if (encoder->pre_pll_enable)
4546 encoder->pre_pll_enable(encoder);
eb1cbe48 4547
f47709a9
DV		 4548 if (crtc->config.has_dp_encoder)
4549 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4550
4551 I915_WRITE(DPLL(pipe), dpll);
4552
4553 /* Wait for the clocks to stabilize. */
4554 POSTING_READ(DPLL(pipe));
4555 udelay(150);
4556
4557 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4558 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4559 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4560 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4561 } else {
4562 /* The pixel multiplier can only be updated once the
4563 * DPLL is enabled and the clocks are stable.
4564 *
4565 * So write it again.
4566 */
4567 I915_WRITE(DPLL(pipe), dpll);
4568 }
4569}
4570
f47709a9 4571static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4572 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4573 int num_connectors)
4574{
f47709a9 4575 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4576 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4577 struct intel_encoder *encoder;
f47709a9 4578 int pipe = crtc->pipe;
eb1cbe48 4579 u32 dpll;
f47709a9 4580 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4581
f47709a9 4582 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4583
eb1cbe48
DV		 4584 dpll = DPLL_VGA_MODE_DIS;
4585
f47709a9 4586 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4587 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588 } else {
4589 if (clock->p1 == 2)
4590 dpll |= PLL_P1_DIVIDE_BY_TWO;
4591 else
4592 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593 if (clock->p2 == 4)
4594 dpll |= PLL_P2_DIVIDE_BY_4;
4595 }
4596
f47709a9 4597 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4598 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4599 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4600 else
4601 dpll |= PLL_REF_INPUT_DREFCLK;
4602
4603 dpll |= DPLL_VCO_ENABLE;
4604 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4605 POSTING_READ(DPLL(pipe));
4606 udelay(150);
4607
f47709a9 4608 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4609 if (encoder->pre_pll_enable)
4610 encoder->pre_pll_enable(encoder);
eb1cbe48 4611
5b5896e4
DV		 4612 I915_WRITE(DPLL(pipe), dpll);
4613
4614 /* Wait for the clocks to stabilize. */
4615 POSTING_READ(DPLL(pipe));
4616 udelay(150);
4617
eb1cbe48
DV		 4618 /* The pixel multiplier can only be updated once the
4619 * DPLL is enabled and the clocks are stable.
4620 *
4621 * So write it again.
4622 */
4623 I915_WRITE(DPLL(pipe), dpll);
4624}
4625
8a654f3b 4626static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4627{
4628 struct drm_device *dev = intel_crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4631 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4632 struct drm_display_mode *adjusted_mode =
4633 &intel_crtc->config.adjusted_mode;
4634 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4635 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4636
4637 /* We need to be careful not to changed the adjusted mode, for otherwise
4638 * the hw state checker will get angry at the mismatch. */
4639 crtc_vtotal = adjusted_mode->crtc_vtotal;
4640 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4641
4642 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4643 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4644 crtc_vtotal -= 1;
4645 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4646 vsyncshift = adjusted_mode->crtc_hsync_start
4647 - adjusted_mode->crtc_htotal / 2;
4648 } else {
4649 vsyncshift = 0;
4650 }
4651
4652 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4653 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4654
fe2b8f9d 4655 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4656 (adjusted_mode->crtc_hdisplay - 1) |
4657 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4658 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4659 (adjusted_mode->crtc_hblank_start - 1) |
4660 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4661 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4662 (adjusted_mode->crtc_hsync_start - 1) |
4663 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4664
fe2b8f9d 4665 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4666 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4667 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4668 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4669 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4670 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4671 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4672 (adjusted_mode->crtc_vsync_start - 1) |
4673 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4674
b5e508d4
PZ		 4675 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4676 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4677 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4678 * bits. */
4679 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4680 (pipe == PIPE_B || pipe == PIPE_C))
4681 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4682
b0e77b9c
PZ		 4683 /* pipesrc controls the size that is scaled from, which should
4684 * always be the user's requested size.
4685 */
4686 I915_WRITE(PIPESRC(pipe),
4687 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4688}
4689
1bd1bd80
DV		 4690static void intel_get_pipe_timings(struct intel_crtc *crtc,
4691 struct intel_crtc_config *pipe_config)
4692{
4693 struct drm_device *dev = crtc->base.dev;
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4696 uint32_t tmp;
4697
4698 tmp = I915_READ(HTOTAL(cpu_transcoder));
4699 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4700 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4701 tmp = I915_READ(HBLANK(cpu_transcoder));
4702 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4703 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4704 tmp = I915_READ(HSYNC(cpu_transcoder));
4705 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4706 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4707
4708 tmp = I915_READ(VTOTAL(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4711 tmp = I915_READ(VBLANK(cpu_transcoder));
4712 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4713 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4714 tmp = I915_READ(VSYNC(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4717
4718 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4719 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4720 pipe_config->adjusted_mode.crtc_vtotal += 1;
4721 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4722 }
4723
4724 tmp = I915_READ(PIPESRC(crtc->pipe));
4725 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4726 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4727}
4728
84b046f3
DV		 4729static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4730{
4731 struct drm_device *dev = intel_crtc->base.dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 uint32_t pipeconf;
4734
4735 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4736
4737 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4738 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4739 * core speed.
4740 *
4741 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4742 * pipe == 0 check?
4743 */
4744 if (intel_crtc->config.requested_mode.clock >
4745 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4746 pipeconf |= PIPECONF_DOUBLE_WIDE;
4747 else
4748 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4749 }
4750
ff9ce46e
DV		 4751 /* only g4x and later have fancy bpc/dither controls */
4752 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4753 pipeconf &= ~(PIPECONF_BPC_MASK |
4754 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4755
4756 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4757 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4758 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4759 PIPECONF_DITHER_TYPE_SP;
84b046f3 4760
ff9ce46e
DV		 4761 switch (intel_crtc->config.pipe_bpp) {
4762 case 18:
4763 pipeconf |= PIPECONF_6BPC;
4764 break;
4765 case 24:
4766 pipeconf |= PIPECONF_8BPC;
4767 break;
4768 case 30:
4769 pipeconf |= PIPECONF_10BPC;
4770 break;
4771 default:
4772 /* Case prevented by intel_choose_pipe_bpp_dither. */
4773 BUG();
84b046f3
DV		 4774 }
4775 }
4776
4777 if (HAS_PIPE_CXSR(dev)) {
4778 if (intel_crtc->lowfreq_avail) {
4779 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4780 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4781 } else {
4782 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4783 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4784 }
4785 }
4786
4787 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4788 if (!IS_GEN2(dev) &&
4789 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4790 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4791 else
4792 pipeconf |= PIPECONF_PROGRESSIVE;
4793
9c8e09b7
VS		 4794 if (IS_VALLEYVIEW(dev)) {
4795 if (intel_crtc->config.limited_color_range)
4796 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4797 else
4798 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4799 }
4800
84b046f3
DV		 4801 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4802 POSTING_READ(PIPECONF(intel_crtc->pipe));
4803}
4804
f564048e 4805static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4806 int x, int y,
94352cf9 4807 struct drm_framebuffer *fb)
79e53945
JB		 4808{
4809 struct drm_device *dev = crtc->dev;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4812 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4813 int pipe = intel_crtc->pipe;
80824003 4814 int plane = intel_crtc->plane;
c751ce4f 4815 int refclk, num_connectors = 0;
652c393a 4816 intel_clock_t clock, reduced_clock;
84b046f3 4817 u32 dspcntr;
a16af721
DV		 4818 bool ok, has_reduced_clock = false;
4819 bool is_lvds = false;
5eddb70b 4820 struct intel_encoder *encoder;
d4906093 4821 const intel_limit_t *limit;
5c3b82e2 4822 int ret;
79e53945 4823
6c2b7c12 4824 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4825 switch (encoder->type) {
79e53945
JB		 4826 case INTEL_OUTPUT_LVDS:
4827 is_lvds = true;
4828 break;
79e53945 4829 }
43565a06 4830
c751ce4f 4831 num_connectors++;
79e53945
JB		 4832 }
4833
c65d77d8 4834 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4835
d4906093
ML		 4836 /*
4837 * Returns a set of divisors for the desired target clock with the given
4838 * refclk, or FALSE. The returned values represent the clock equation:
4839 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4840 */
1b894b59 4841 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4842 ok = dev_priv->display.find_dpll(limit, crtc,
4843 intel_crtc->config.port_clock,
ee9300bb
DV		 4844 refclk, NULL, &clock);
4845 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4846 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4847 return -EINVAL;
79e53945
JB		 4848 }
4849
cda4b7d3 4850 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4851 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4852
ddc9003c 4853 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4854 /*
4855 * Ensure we match the reduced clock's P to the target clock.
4856 * If the clocks don't match, we can't switch the display clock
4857 * by using the FP0/FP1. In such case we will disable the LVDS
4858 * downclock feature.
4859 */
ee9300bb
DV		 4860 has_reduced_clock =
4861 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4862 dev_priv->lvds_downclock,
ee9300bb 4863 refclk, &clock,
5eddb70b 4864 &reduced_clock);
7026d4ac 4865 }
f47709a9
DV		 4866 /* Compat-code for transition, will disappear. */
4867 if (!intel_crtc->config.clock_set) {
4868 intel_crtc->config.dpll.n = clock.n;
4869 intel_crtc->config.dpll.m1 = clock.m1;
4870 intel_crtc->config.dpll.m2 = clock.m2;
4871 intel_crtc->config.dpll.p1 = clock.p1;
4872 intel_crtc->config.dpll.p2 = clock.p2;
4873 }
7026d4ac 4874
eb1cbe48 4875 if (IS_GEN2(dev))
8a654f3b 4876 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4877 has_reduced_clock ? &reduced_clock : NULL,
4878 num_connectors);
a0c4da24 4879 else if (IS_VALLEYVIEW(dev))
f47709a9 4880 vlv_update_pll(intel_crtc);
79e53945 4881 else
f47709a9 4882 i9xx_update_pll(intel_crtc,
eb1cbe48 4883 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4884 num_connectors);
79e53945 4885
79e53945
JB		 4886 /* Set up the display plane register */
4887 dspcntr = DISPPLANE_GAMMA_ENABLE;
4888
da6ecc5d
JB		 4889 if (!IS_VALLEYVIEW(dev)) {
4890 if (pipe == 0)
4891 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4892 else
4893 dspcntr |= DISPPLANE_SEL_PIPE_B;
4894 }
79e53945 4895
8a654f3b 4896 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4897
4898 /* pipesrc and dspsize control the size that is scaled from,
4899 * which should always be the user's requested size.
79e53945 4900 */
929c77fb
EA		 4901 I915_WRITE(DSPSIZE(plane),
4902 ((mode->vdisplay - 1) << 16) |
4903 (mode->hdisplay - 1));
4904 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4905
84b046f3
DV		 4906 i9xx_set_pipeconf(intel_crtc);
4907
f564048e
EA		 4908 I915_WRITE(DSPCNTR(plane), dspcntr);
4909 POSTING_READ(DSPCNTR(plane));
4910
94352cf9 4911 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4912
4913 intel_update_watermarks(dev);
4914
f564048e
EA		 4915 return ret;
4916}
4917
2fa2fe9a
DV		 4918static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4919 struct intel_crtc_config *pipe_config)
4920{
4921 struct drm_device *dev = crtc->base.dev;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 uint32_t tmp;
4924
4925 tmp = I915_READ(PFIT_CONTROL);
4926
4927 if (INTEL_INFO(dev)->gen < 4) {
4928 if (crtc->pipe != PIPE_B)
4929 return;
4930
4931 /* gen2/3 store dither state in pfit control, needs to match */
4932 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4933 } else {
4934 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4935 return;
4936 }
4937
4938 if (!(tmp & PFIT_ENABLE))
4939 return;
4940
4941 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4942 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4943 if (INTEL_INFO(dev)->gen < 5)
4944 pipe_config->gmch_pfit.lvds_border_bits =
4945 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4946}
4947
0e8ffe1b
DV		 4948static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4949 struct intel_crtc_config *pipe_config)
4950{
4951 struct drm_device *dev = crtc->base.dev;
4952 struct drm_i915_private *dev_priv = dev->dev_private;
4953 uint32_t tmp;
4954
eccb140b 4955 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4956 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4957
0e8ffe1b
DV		 4958 tmp = I915_READ(PIPECONF(crtc->pipe));
4959 if (!(tmp & PIPECONF_ENABLE))
4960 return false;
4961
1bd1bd80
DV		 4962 intel_get_pipe_timings(crtc, pipe_config);
4963
2fa2fe9a
DV		 4964 i9xx_get_pfit_config(crtc, pipe_config);
4965
6c49f241
DV		 4966 if (INTEL_INFO(dev)->gen >= 4) {
4967 tmp = I915_READ(DPLL_MD(crtc->pipe));
4968 pipe_config->pixel_multiplier =
4969 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4970 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4971 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4972 tmp = I915_READ(DPLL(crtc->pipe));
4973 pipe_config->pixel_multiplier =
4974 ((tmp & SDVO_MULTIPLIER_MASK)
4975 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4976 } else {
4977 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4978 * port and will be fixed up in the encoder->get_config
4979 * function. */
4980 pipe_config->pixel_multiplier = 1;
4981 }
4982
0e8ffe1b
DV		 4983 return true;
4984}
4985
dde86e2d 4986static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4987{
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4990 struct intel_encoder *encoder;
74cfd7ac 4991 u32 val, final;
13d83a67 4992 bool has_lvds = false;
199e5d79 4993 bool has_cpu_edp = false;
199e5d79 4994 bool has_panel = false;
99eb6a01
KP		 4995 bool has_ck505 = false;
4996 bool can_ssc = false;
13d83a67
JB		 4997
4998 /* We need to take the global config into account */
199e5d79
KP		 4999 list_for_each_entry(encoder, &mode_config->encoder_list,
5000 base.head) {
5001 switch (encoder->type) {
5002 case INTEL_OUTPUT_LVDS:
5003 has_panel = true;
5004 has_lvds = true;
5005 break;
5006 case INTEL_OUTPUT_EDP:
5007 has_panel = true;
2de6905f 5008 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5009 has_cpu_edp = true;
5010 break;
13d83a67
JB		 5011 }
5012 }
5013
99eb6a01 5014 if (HAS_PCH_IBX(dev)) {
41aa3448 5015 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5016 can_ssc = has_ck505;
5017 } else {
5018 has_ck505 = false;
5019 can_ssc = true;
5020 }
5021
2de6905f
ID		 5022 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5023 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5024
5025 /* Ironlake: try to setup display ref clock before DPLL
5026 * enabling. This is only under driver's control after
5027 * PCH B stepping, previous chipset stepping should be
5028 * ignoring this setting.
5029 */
74cfd7ac
CW		 5030 val = I915_READ(PCH_DREF_CONTROL);
5031
5032 /* As we must carefully and slowly disable/enable each source in turn,
5033 * compute the final state we want first and check if we need to
5034 * make any changes at all.
5035 */
5036 final = val;
5037 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5038 if (has_ck505)
5039 final |= DREF_NONSPREAD_CK505_ENABLE;
5040 else
5041 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5042
5043 final &= ~DREF_SSC_SOURCE_MASK;
5044 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5045 final &= ~DREF_SSC1_ENABLE;
5046
5047 if (has_panel) {
5048 final |= DREF_SSC_SOURCE_ENABLE;
5049
5050 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5051 final |= DREF_SSC1_ENABLE;
5052
5053 if (has_cpu_edp) {
5054 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5055 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5056 else
5057 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5058 } else
5059 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5060 } else {
5061 final |= DREF_SSC_SOURCE_DISABLE;
5062 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5063 }
5064
5065 if (final == val)
5066 return;
5067
13d83a67 5068 /* Always enable nonspread source */
74cfd7ac 5069 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5070
99eb6a01 5071 if (has_ck505)
74cfd7ac 5072 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5073 else
74cfd7ac 5074 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5075
199e5d79 5076 if (has_panel) {
74cfd7ac
CW		 5077 val &= ~DREF_SSC_SOURCE_MASK;
5078 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5079
199e5d79 5080 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5081 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5082 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5083 val |= DREF_SSC1_ENABLE;
e77166b5 5084 } else
74cfd7ac 5085 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5086
5087 /* Get SSC going before enabling the outputs */
74cfd7ac 5088 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5089 POSTING_READ(PCH_DREF_CONTROL);
5090 udelay(200);
5091
74cfd7ac 5092 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5093
5094 /* Enable CPU source on CPU attached eDP */
199e5d79 5095 if (has_cpu_edp) {
99eb6a01 5096 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5097 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5098 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5099 }
13d83a67 5100 else
74cfd7ac 5101 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5102 } else
74cfd7ac 5103 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5104
74cfd7ac 5105 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5106 POSTING_READ(PCH_DREF_CONTROL);
5107 udelay(200);
5108 } else {
5109 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5110
74cfd7ac 5111 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5112
5113 /* Turn off CPU output */
74cfd7ac 5114 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5115
74cfd7ac 5116 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5117 POSTING_READ(PCH_DREF_CONTROL);
5118 udelay(200);
5119
5120 /* Turn off the SSC source */
74cfd7ac
CW		 5121 val &= ~DREF_SSC_SOURCE_MASK;
5122 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5123
5124 /* Turn off SSC1 */
74cfd7ac 5125 val &= ~DREF_SSC1_ENABLE;
199e5d79 5126
74cfd7ac 5127 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5128 POSTING_READ(PCH_DREF_CONTROL);
5129 udelay(200);
5130 }
74cfd7ac
CW		 5131
5132 BUG_ON(val != final);
13d83a67
JB		 5133}
5134
dde86e2d
PZ		 5135/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5136static void lpt_init_pch_refclk(struct drm_device *dev)
5137{
5138 struct drm_i915_private *dev_priv = dev->dev_private;
5139 struct drm_mode_config *mode_config = &dev->mode_config;
5140 struct intel_encoder *encoder;
5141 bool has_vga = false;
5142 bool is_sdv = false;
5143 u32 tmp;
5144
5145 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5146 switch (encoder->type) {
5147 case INTEL_OUTPUT_ANALOG:
5148 has_vga = true;
5149 break;
5150 }
5151 }
5152
5153 if (!has_vga)
5154 return;
5155
c00db246
DV		 5156 mutex_lock(&dev_priv->dpio_lock);
5157
dde86e2d
PZ		 5158 /* XXX: Rip out SDV support once Haswell ships for real. */
5159 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5160 is_sdv = true;
5161
5162 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5163 tmp &= ~SBI_SSCCTL_DISABLE;
5164 tmp |= SBI_SSCCTL_PATHALT;
5165 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5166
5167 udelay(24);
5168
5169 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5170 tmp &= ~SBI_SSCCTL_PATHALT;
5171 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5172
5173 if (!is_sdv) {
5174 tmp = I915_READ(SOUTH_CHICKEN2);
5175 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5176 I915_WRITE(SOUTH_CHICKEN2, tmp);
5177
5178 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5179 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5180 DRM_ERROR("FDI mPHY reset assert timeout\n");
5181
5182 tmp = I915_READ(SOUTH_CHICKEN2);
5183 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5184 I915_WRITE(SOUTH_CHICKEN2, tmp);
5185
5186 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5187 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5188 100))
5189 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5190 }
5191
5192 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5193 tmp &= ~(0xFF << 24);
5194 tmp |= (0x12 << 24);
5195 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5196
dde86e2d
PZ		 5197 if (is_sdv) {
5198 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5199 tmp |= 0x7FFF;
5200 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5201 }
5202
5203 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5204 tmp |= (1 << 11);
5205 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5206
5207 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5208 tmp |= (1 << 11);
5209 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5210
5211 if (is_sdv) {
5212 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5213 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5214 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5215
5216 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5217 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5218 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5219
5220 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5221 tmp |= (0x3F << 8);
5222 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5223
5224 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5225 tmp |= (0x3F << 8);
5226 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5227 }
5228
5229 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5230 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5231 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5232
5233 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5234 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5235 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5236
5237 if (!is_sdv) {
5238 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5239 tmp &= ~(7 << 13);
5240 tmp |= (5 << 13);
5241 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5242
5243 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5244 tmp &= ~(7 << 13);
5245 tmp |= (5 << 13);
5246 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5247 }
5248
5249 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5250 tmp &= ~0xFF;
5251 tmp |= 0x1C;
5252 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5255 tmp &= ~0xFF;
5256 tmp |= 0x1C;
5257 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5258
5259 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5260 tmp &= ~(0xFF << 16);
5261 tmp |= (0x1C << 16);
5262 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5263
5264 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5265 tmp &= ~(0xFF << 16);
5266 tmp |= (0x1C << 16);
5267 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5268
5269 if (!is_sdv) {
5270 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5271 tmp |= (1 << 27);
5272 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5275 tmp |= (1 << 27);
5276 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5279 tmp &= ~(0xF << 28);
5280 tmp |= (4 << 28);
5281 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5282
5283 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5284 tmp &= ~(0xF << 28);
5285 tmp |= (4 << 28);
5286 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5287 }
5288
5289 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5290 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5291 tmp |= SBI_DBUFF0_ENABLE;
5292 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5293
5294 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5295}
5296
5297/*
5298 * Initialize reference clocks when the driver loads
5299 */
5300void intel_init_pch_refclk(struct drm_device *dev)
5301{
5302 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5303 ironlake_init_pch_refclk(dev);
5304 else if (HAS_PCH_LPT(dev))
5305 lpt_init_pch_refclk(dev);
5306}
5307
d9d444cb
JB		 5308static int ironlake_get_refclk(struct drm_crtc *crtc)
5309{
5310 struct drm_device *dev = crtc->dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 struct intel_encoder *encoder;
d9d444cb
JB		 5313 int num_connectors = 0;
5314 bool is_lvds = false;
5315
6c2b7c12 5316 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5317 switch (encoder->type) {
5318 case INTEL_OUTPUT_LVDS:
5319 is_lvds = true;
5320 break;
d9d444cb
JB		 5321 }
5322 num_connectors++;
5323 }
5324
5325 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5326 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5327 dev_priv->vbt.lvds_ssc_freq);
5328 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5329 }
5330
5331 return 120000;
5332}
5333
6ff93609 5334static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5335{
c8203565 5336 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5338 int pipe = intel_crtc->pipe;
c8203565
PZ		 5339 uint32_t val;
5340
5341 val = I915_READ(PIPECONF(pipe));
5342
dfd07d72 5343 val &= ~PIPECONF_BPC_MASK;
965e0c48 5344 switch (intel_crtc->config.pipe_bpp) {
c8203565 5345 case 18:
dfd07d72 5346 val |= PIPECONF_6BPC;
c8203565
PZ		 5347 break;
5348 case 24:
dfd07d72 5349 val |= PIPECONF_8BPC;
c8203565
PZ		 5350 break;
5351 case 30:
dfd07d72 5352 val |= PIPECONF_10BPC;
c8203565
PZ		 5353 break;
5354 case 36:
dfd07d72 5355 val |= PIPECONF_12BPC;
c8203565
PZ		 5356 break;
5357 default:
cc769b62
PZ		 5358 /* Case prevented by intel_choose_pipe_bpp_dither. */
5359 BUG();
c8203565
PZ		 5360 }
5361
5362 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5363 if (intel_crtc->config.dither)
c8203565
PZ		 5364 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5365
5366 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5367 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5368 val |= PIPECONF_INTERLACED_ILK;
5369 else
5370 val |= PIPECONF_PROGRESSIVE;
5371
50f3b016 5372 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5373 val |= PIPECONF_COLOR_RANGE_SELECT;
5374 else
5375 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5376
c8203565
PZ		 5377 I915_WRITE(PIPECONF(pipe), val);
5378 POSTING_READ(PIPECONF(pipe));
5379}
5380
86d3efce
VS		 5381/*
5382 * Set up the pipe CSC unit.
5383 *
5384 * Currently only full range RGB to limited range RGB conversion
5385 * is supported, but eventually this should handle various
5386 * RGB<->YCbCr scenarios as well.
5387 */
50f3b016 5388static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5389{
5390 struct drm_device *dev = crtc->dev;
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5393 int pipe = intel_crtc->pipe;
5394 uint16_t coeff = 0x7800; /* 1.0 */
5395
5396 /*
5397 * TODO: Check what kind of values actually come out of the pipe
5398 * with these coeff/postoff values and adjust to get the best
5399 * accuracy. Perhaps we even need to take the bpc value into
5400 * consideration.
5401 */
5402
50f3b016 5403 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5404 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5405
5406 /*
5407 * GY/GU and RY/RU should be the other way around according
5408 * to BSpec, but reality doesn't agree. Just set them up in
5409 * a way that results in the correct picture.
5410 */
5411 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5412 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5413
5414 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5415 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5416
5417 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5418 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5419
5420 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5421 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5422 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5423
5424 if (INTEL_INFO(dev)->gen > 6) {
5425 uint16_t postoff = 0;
5426
50f3b016 5427 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5428 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5429
5430 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5431 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5432 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5433
5434 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5435 } else {
5436 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5437
50f3b016 5438 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5439 mode |= CSC_BLACK_SCREEN_OFFSET;
5440
5441 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5442 }
5443}
5444
6ff93609 5445static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5446{
5447 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5449 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5450 uint32_t val;
5451
702e7a56 5452 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5453
5454 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5455 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5456 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5457
5458 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5459 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5460 val |= PIPECONF_INTERLACED_ILK;
5461 else
5462 val |= PIPECONF_PROGRESSIVE;
5463
702e7a56
PZ		 5464 I915_WRITE(PIPECONF(cpu_transcoder), val);
5465 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5466}
5467
6591c6e4 5468static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5469 intel_clock_t *clock,
5470 bool *has_reduced_clock,
5471 intel_clock_t *reduced_clock)
5472{
5473 struct drm_device *dev = crtc->dev;
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475 struct intel_encoder *intel_encoder;
5476 int refclk;
d4906093 5477 const intel_limit_t *limit;
a16af721 5478 bool ret, is_lvds = false;
79e53945 5479
6591c6e4
PZ		 5480 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5481 switch (intel_encoder->type) {
79e53945
JB		 5482 case INTEL_OUTPUT_LVDS:
5483 is_lvds = true;
5484 break;
79e53945
JB		 5485 }
5486 }
5487
d9d444cb 5488 refclk = ironlake_get_refclk(crtc);
79e53945 5489
d4906093
ML		 5490 /*
5491 * Returns a set of divisors for the desired target clock with the given
5492 * refclk, or FALSE. The returned values represent the clock equation:
5493 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5494 */
1b894b59 5495 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5496 ret = dev_priv->display.find_dpll(limit, crtc,
5497 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5498 refclk, NULL, clock);
6591c6e4
PZ		 5499 if (!ret)
5500 return false;
cda4b7d3 5501
ddc9003c 5502 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5503 /*
5504 * Ensure we match the reduced clock's P to the target clock.
5505 * If the clocks don't match, we can't switch the display clock
5506 * by using the FP0/FP1. In such case we will disable the LVDS
5507 * downclock feature.
5508 */
ee9300bb
DV		 5509 *has_reduced_clock =
5510 dev_priv->display.find_dpll(limit, crtc,
5511 dev_priv->lvds_downclock,
5512 refclk, clock,
5513 reduced_clock);
652c393a 5514 }
61e9653f 5515
6591c6e4
PZ		 5516 return true;
5517}
5518
01a415fd
DV		 5519static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5520{
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522 uint32_t temp;
5523
5524 temp = I915_READ(SOUTH_CHICKEN1);
5525 if (temp & FDI_BC_BIFURCATION_SELECT)
5526 return;
5527
5528 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5529 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5530
5531 temp |= FDI_BC_BIFURCATION_SELECT;
5532 DRM_DEBUG_KMS("enabling fdi C rx\n");
5533 I915_WRITE(SOUTH_CHICKEN1, temp);
5534 POSTING_READ(SOUTH_CHICKEN1);
5535}
5536
ebfd86fd
DV		 5537static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5538{
5539 struct drm_device *dev = intel_crtc->base.dev;
5540 struct drm_i915_private *dev_priv = dev->dev_private;
5541
5542 switch (intel_crtc->pipe) {
5543 case PIPE_A:
5544 break;
5545 case PIPE_B:
5546 if (intel_crtc->config.fdi_lanes > 2)
5547 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5548 else
5549 cpt_enable_fdi_bc_bifurcation(dev);
5550
5551 break;
5552 case PIPE_C:
01a415fd
DV		 5553 cpt_enable_fdi_bc_bifurcation(dev);
5554
ebfd86fd 5555 break;
01a415fd
DV		 5556 default:
5557 BUG();
5558 }
5559}
5560
d4b1931c
PZ		 5561int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5562{
5563 /*
5564 * Account for spread spectrum to avoid
5565 * oversubscribing the link. Max center spread
5566 * is 2.5%; use 5% for safety's sake.
5567 */
5568 u32 bps = target_clock * bpp * 21 / 20;
5569 return bps / (link_bw * 8) + 1;
5570}
5571
7429e9d4
DV		 5572static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5573{
5574 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5575}
5576
de13a2e3 5577static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5578 u32 *fp,
9a7c7890 5579 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5580{
de13a2e3 5581 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5582 struct drm_device *dev = crtc->dev;
5583 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5584 struct intel_encoder *intel_encoder;
5585 uint32_t dpll;
6cc5f341 5586 int factor, num_connectors = 0;
09ede541 5587 bool is_lvds = false, is_sdvo = false;
79e53945 5588
de13a2e3
PZ		 5589 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5590 switch (intel_encoder->type) {
79e53945
JB		 5591 case INTEL_OUTPUT_LVDS:
5592 is_lvds = true;
5593 break;
5594 case INTEL_OUTPUT_SDVO:
7d57382e 5595 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5596 is_sdvo = true;
5597 break;
79e53945 5598 }
43565a06 5599
c751ce4f 5600 num_connectors++;
79e53945 5601 }
79e53945 5602
c1858123 5603 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5604 factor = 21;
5605 if (is_lvds) {
5606 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5607 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5608 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5609 factor = 25;
09ede541 5610 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5611 factor = 20;
c1858123 5612
7429e9d4 5613 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5614 *fp |= FP_CB_TUNE;
2c07245f 5615
9a7c7890
DV		 5616 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5617 *fp2 |= FP_CB_TUNE;
5618
5eddb70b 5619 dpll = 0;
2c07245f 5620
a07d6787
EA		 5621 if (is_lvds)
5622 dpll |= DPLLB_MODE_LVDS;
5623 else
5624 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5625
ef1b460d
DV		 5626 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5627 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5628
5629 if (is_sdvo)
5630 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5631 if (intel_crtc->config.has_dp_encoder)
a07d6787 5632 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5633
a07d6787 5634 /* compute bitmask from p1 value */
7429e9d4 5635 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5636 /* also FPA1 */
7429e9d4 5637 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5638
7429e9d4 5639 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5640 case 5:
5641 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5642 break;
5643 case 7:
5644 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5645 break;
5646 case 10:
5647 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5648 break;
5649 case 14:
5650 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5651 break;
79e53945
JB		 5652 }
5653
b4c09f3b 5654 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5655 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5656 else
5657 dpll |= PLL_REF_INPUT_DREFCLK;
5658
de13a2e3
PZ		 5659 return dpll;
5660}
5661
5662static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5663 int x, int y,
5664 struct drm_framebuffer *fb)
5665{
5666 struct drm_device *dev = crtc->dev;
5667 struct drm_i915_private *dev_priv = dev->dev_private;
5668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5669 int pipe = intel_crtc->pipe;
5670 int plane = intel_crtc->plane;
5671 int num_connectors = 0;
5672 intel_clock_t clock, reduced_clock;
cbbab5bd 5673 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5674 bool ok, has_reduced_clock = false;
8b47047b 5675 bool is_lvds = false;
de13a2e3 5676 struct intel_encoder *encoder;
e2b78267 5677 struct intel_shared_dpll *pll;
de13a2e3 5678 int ret;
de13a2e3
PZ		 5679
5680 for_each_encoder_on_crtc(dev, crtc, encoder) {
5681 switch (encoder->type) {
5682 case INTEL_OUTPUT_LVDS:
5683 is_lvds = true;
5684 break;
de13a2e3
PZ		 5685 }
5686
5687 num_connectors++;
a07d6787 5688 }
79e53945 5689
5dc5298b
PZ		 5690 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5691 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5692
ff9a6750 5693 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5694 &has_reduced_clock, &reduced_clock);
ee9300bb 5695 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5696 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5697 return -EINVAL;
79e53945 5698 }
f47709a9
DV		 5699 /* Compat-code for transition, will disappear. */
5700 if (!intel_crtc->config.clock_set) {
5701 intel_crtc->config.dpll.n = clock.n;
5702 intel_crtc->config.dpll.m1 = clock.m1;
5703 intel_crtc->config.dpll.m2 = clock.m2;
5704 intel_crtc->config.dpll.p1 = clock.p1;
5705 intel_crtc->config.dpll.p2 = clock.p2;
5706 }
79e53945 5707
de13a2e3
PZ		 5708 /* Ensure that the cursor is valid for the new mode before changing... */
5709 intel_crtc_update_cursor(crtc, true);
5710
5dc5298b 5711 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5712 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5713 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5714 if (has_reduced_clock)
7429e9d4 5715 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5716
7429e9d4 5717 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5718 &fp, &reduced_clock,
5719 has_reduced_clock ? &fp2 : NULL);
5720
e72f9fbf 5721 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
ee7b9f93 5722 if (pll == NULL) {
84f44ce7
VS		 5723 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5724 pipe_name(pipe));
4b645f14
JB		 5725 return -EINVAL;
5726 }
ee7b9f93 5727 } else
e72f9fbf 5728 intel_put_shared_dpll(intel_crtc);
79e53945 5729
03afc4a2
DV		 5730 if (intel_crtc->config.has_dp_encoder)
5731 intel_dp_set_m_n(intel_crtc);
79e53945 5732
dafd226c
DV		 5733 for_each_encoder_on_crtc(dev, crtc, encoder)
5734 if (encoder->pre_pll_enable)
5735 encoder->pre_pll_enable(encoder);
79e53945 5736
e2b78267
DV		 5737 intel_crtc->lowfreq_avail = false;
5738
5739 if (intel_crtc->config.has_pch_encoder) {
5740 pll = intel_crtc_to_shared_dpll(intel_crtc);
5741
e9a632a5 5742 I915_WRITE(PCH_DPLL(pll->id), dpll);
5eddb70b 5743
32f9d658 5744 /* Wait for the clocks to stabilize. */
e9a632a5 5745 POSTING_READ(PCH_DPLL(pll->id));
32f9d658
ZW		 5746 udelay(150);
5747
8febb297
EA		 5748 /* The pixel multiplier can only be updated once the
5749 * DPLL is enabled and the clocks are stable.
5750 *
5751 * So write it again.
5752 */
e9a632a5 5753 I915_WRITE(PCH_DPLL(pll->id), dpll);
79e53945 5754
4b645f14 5755 if (is_lvds && has_reduced_clock && i915_powersave) {
e9a632a5 5756 I915_WRITE(PCH_FP1(pll->id), fp2);
4b645f14 5757 intel_crtc->lowfreq_avail = true;
4b645f14 5758 } else {
e9a632a5 5759 I915_WRITE(PCH_FP1(pll->id), fp);
652c393a
JB		 5760 }
5761 }
5762
8a654f3b 5763 intel_set_pipe_timings(intel_crtc);
5eddb70b 5764
ca3a0ff8 5765 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5766 intel_cpu_transcoder_set_m_n(intel_crtc,
5767 &intel_crtc->config.fdi_m_n);
5768 }
2c07245f 5769
ebfd86fd
DV		 5770 if (IS_IVYBRIDGE(dev))
5771 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5772
6ff93609 5773 ironlake_set_pipeconf(crtc);
79e53945 5774
a1f9e77e
PZ		 5775 /* Set up the display plane register */
5776 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5777 POSTING_READ(DSPCNTR(plane));
79e53945 5778
94352cf9 5779 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5780
5781 intel_update_watermarks(dev);
5782
1857e1da 5783 return ret;
79e53945
JB		 5784}
5785
72419203
DV		 5786static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5787 struct intel_crtc_config *pipe_config)
5788{
5789 struct drm_device *dev = crtc->base.dev;
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791 enum transcoder transcoder = pipe_config->cpu_transcoder;
5792
5793 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5794 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5795 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5796 & ~TU_SIZE_MASK;
5797 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5798 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5799 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5800}
5801
2fa2fe9a
DV		 5802static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5803 struct intel_crtc_config *pipe_config)
5804{
5805 struct drm_device *dev = crtc->base.dev;
5806 struct drm_i915_private *dev_priv = dev->dev_private;
5807 uint32_t tmp;
5808
5809 tmp = I915_READ(PF_CTL(crtc->pipe));
5810
5811 if (tmp & PF_ENABLE) {
5812 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5813 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5814
5815 /* We currently do not free assignements of panel fitters on
5816 * ivb/hsw (since we don't use the higher upscaling modes which
5817 * differentiates them) so just WARN about this case for now. */
5818 if (IS_GEN7(dev)) {
5819 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5820 PF_PIPE_SEL_IVB(crtc->pipe));
5821 }
2fa2fe9a
DV		 5822 }
5823}
5824
0e8ffe1b
DV		 5825static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5826 struct intel_crtc_config *pipe_config)
5827{
5828 struct drm_device *dev = crtc->base.dev;
5829 struct drm_i915_private *dev_priv = dev->dev_private;
5830 uint32_t tmp;
5831
eccb140b 5832 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5833 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5834
0e8ffe1b
DV		 5835 tmp = I915_READ(PIPECONF(crtc->pipe));
5836 if (!(tmp & PIPECONF_ENABLE))
5837 return false;
5838
ab9412ba 5839 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5840 pipe_config->has_pch_encoder = true;
5841
627eb5a3
DV		 5842 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5843 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5844 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5845
5846 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5847
5848 /* XXX: Can't properly read out the pch dpll pixel multiplier
5849 * since we don't have state tracking for pch clocks yet. */
5850 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5851
5852 if (HAS_PCH_IBX(dev_priv->dev)) {
5853 pipe_config->shared_dpll = crtc->pipe;
5854 } else {
5855 tmp = I915_READ(PCH_DPLL_SEL);
5856 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5857 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5858 else
5859 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5860 }
6c49f241
DV		 5861 } else {
5862 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5863 }
5864
1bd1bd80
DV		 5865 intel_get_pipe_timings(crtc, pipe_config);
5866
2fa2fe9a
DV		 5867 ironlake_get_pfit_config(crtc, pipe_config);
5868
0e8ffe1b
DV		 5869 return true;
5870}
5871
d6dd9eb1
DV		 5872static void haswell_modeset_global_resources(struct drm_device *dev)
5873{
d6dd9eb1
DV		 5874 bool enable = false;
5875 struct intel_crtc *crtc;
d6dd9eb1
DV		 5876
5877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5878 if (!crtc->base.enabled)
5879 continue;
d6dd9eb1 5880
e7a639c4
DV		 5881 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5882 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5883 enable = true;
5884 }
5885
d6dd9eb1
DV		 5886 intel_set_power_well(dev, enable);
5887}
5888
09b4ddf9 5889static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5890 int x, int y,
5891 struct drm_framebuffer *fb)
5892{
5893 struct drm_device *dev = crtc->dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5896 int plane = intel_crtc->plane;
09b4ddf9 5897 int ret;
09b4ddf9 5898
ff9a6750 5899 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5900 return -EINVAL;
5901
09b4ddf9
PZ		 5902 /* Ensure that the cursor is valid for the new mode before changing... */
5903 intel_crtc_update_cursor(crtc, true);
5904
03afc4a2
DV		 5905 if (intel_crtc->config.has_dp_encoder)
5906 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5907
5908 intel_crtc->lowfreq_avail = false;
09b4ddf9 5909
8a654f3b 5910 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5911
ca3a0ff8 5912 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5913 intel_cpu_transcoder_set_m_n(intel_crtc,
5914 &intel_crtc->config.fdi_m_n);
5915 }
09b4ddf9 5916
6ff93609 5917 haswell_set_pipeconf(crtc);
09b4ddf9 5918
50f3b016 5919 intel_set_pipe_csc(crtc);
86d3efce 5920
09b4ddf9 5921 /* Set up the display plane register */
86d3efce 5922 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5923 POSTING_READ(DSPCNTR(plane));
5924
5925 ret = intel_pipe_set_base(crtc, x, y, fb);
5926
5927 intel_update_watermarks(dev);
5928
1f803ee5 5929 return ret;
79e53945
JB		 5930}
5931
0e8ffe1b
DV		 5932static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5933 struct intel_crtc_config *pipe_config)
5934{
5935 struct drm_device *dev = crtc->base.dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5937 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5938 uint32_t tmp;
5939
eccb140b 5940 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5941 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5942
eccb140b
DV		 5943 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5944 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5945 enum pipe trans_edp_pipe;
5946 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5947 default:
5948 WARN(1, "unknown pipe linked to edp transcoder\n");
5949 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5950 case TRANS_DDI_EDP_INPUT_A_ON:
5951 trans_edp_pipe = PIPE_A;
5952 break;
5953 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5954 trans_edp_pipe = PIPE_B;
5955 break;
5956 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5957 trans_edp_pipe = PIPE_C;
5958 break;
5959 }
5960
5961 if (trans_edp_pipe == crtc->pipe)
5962 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5963 }
5964
b97186f0 5965 if (!intel_display_power_enabled(dev,
eccb140b 5966 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5967 return false;
5968
eccb140b 5969 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5970 if (!(tmp & PIPECONF_ENABLE))
5971 return false;
5972
88adfff1 5973 /*
f196e6be 5974 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5975 * DDI E. So just check whether this pipe is wired to DDI E and whether
5976 * the PCH transcoder is on.
5977 */
eccb140b 5978 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5979 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5980 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5981 pipe_config->has_pch_encoder = true;
5982
627eb5a3
DV		 5983 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5984 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5985 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5986
5987 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5988 }
5989
1bd1bd80
DV		 5990 intel_get_pipe_timings(crtc, pipe_config);
5991
2fa2fe9a
DV		 5992 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5993 if (intel_display_power_enabled(dev, pfit_domain))
5994 ironlake_get_pfit_config(crtc, pipe_config);
5995
42db64ef
PZ		 5996 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5997 (I915_READ(IPS_CTL) & IPS_ENABLE);
5998
6c49f241
DV		 5999 pipe_config->pixel_multiplier = 1;
6000
0e8ffe1b
DV		 6001 return true;
6002}
6003
f564048e 6004static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6005 int x, int y,
94352cf9 6006 struct drm_framebuffer *fb)
f564048e
EA		 6007{
6008 struct drm_device *dev = crtc->dev;
6009 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6010 struct drm_encoder_helper_funcs *encoder_funcs;
6011 struct intel_encoder *encoder;
0b701d27 6012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6013 struct drm_display_mode *adjusted_mode =
6014 &intel_crtc->config.adjusted_mode;
6015 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6016 int pipe = intel_crtc->pipe;
f564048e
EA		 6017 int ret;
6018
0b701d27 6019 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6020
b8cecdf5
DV		 6021 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6022
79e53945 6023 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6024
9256aa19
DV		 6025 if (ret != 0)
6026 return ret;
6027
6028 for_each_encoder_on_crtc(dev, crtc, encoder) {
6029 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6030 encoder->base.base.id,
6031 drm_get_encoder_name(&encoder->base),
6032 mode->base.id, mode->name);
6cc5f341
DV		 6033 if (encoder->mode_set) {
6034 encoder->mode_set(encoder);
6035 } else {
6036 encoder_funcs = encoder->base.helper_private;
6037 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6038 }
9256aa19
DV		 6039 }
6040
6041 return 0;
79e53945
JB		 6042}
6043
3a9627f4
WF		 6044static bool intel_eld_uptodate(struct drm_connector *connector,
6045 int reg_eldv, uint32_t bits_eldv,
6046 int reg_elda, uint32_t bits_elda,
6047 int reg_edid)
6048{
6049 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6050 uint8_t *eld = connector->eld;
6051 uint32_t i;
6052
6053 i = I915_READ(reg_eldv);
6054 i &= bits_eldv;
6055
6056 if (!eld[0])
6057 return !i;
6058
6059 if (!i)
6060 return false;
6061
6062 i = I915_READ(reg_elda);
6063 i &= ~bits_elda;
6064 I915_WRITE(reg_elda, i);
6065
6066 for (i = 0; i < eld[2]; i++)
6067 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6068 return false;
6069
6070 return true;
6071}
6072
e0dac65e
WF		 6073static void g4x_write_eld(struct drm_connector *connector,
6074 struct drm_crtc *crtc)
6075{
6076 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6077 uint8_t *eld = connector->eld;
6078 uint32_t eldv;
6079 uint32_t len;
6080 uint32_t i;
6081
6082 i = I915_READ(G4X_AUD_VID_DID);
6083
6084 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6085 eldv = G4X_ELDV_DEVCL_DEVBLC;
6086 else
6087 eldv = G4X_ELDV_DEVCTG;
6088
3a9627f4
WF		 6089 if (intel_eld_uptodate(connector,
6090 G4X_AUD_CNTL_ST, eldv,
6091 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6092 G4X_HDMIW_HDMIEDID))
6093 return;
6094
e0dac65e
WF		 6095 i = I915_READ(G4X_AUD_CNTL_ST);
6096 i &= ~(eldv | G4X_ELD_ADDR);
6097 len = (i >> 9) & 0x1f; /* ELD buffer size */
6098 I915_WRITE(G4X_AUD_CNTL_ST, i);
6099
6100 if (!eld[0])
6101 return;
6102
6103 len = min_t(uint8_t, eld[2], len);
6104 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6105 for (i = 0; i < len; i++)
6106 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6107
6108 i = I915_READ(G4X_AUD_CNTL_ST);
6109 i |= eldv;
6110 I915_WRITE(G4X_AUD_CNTL_ST, i);
6111}
6112
83358c85
WX		 6113static void haswell_write_eld(struct drm_connector *connector,
6114 struct drm_crtc *crtc)
6115{
6116 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6117 uint8_t *eld = connector->eld;
6118 struct drm_device *dev = crtc->dev;
7b9f35a6 6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6120 uint32_t eldv;
6121 uint32_t i;
6122 int len;
6123 int pipe = to_intel_crtc(crtc)->pipe;
6124 int tmp;
6125
6126 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6127 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6128 int aud_config = HSW_AUD_CFG(pipe);
6129 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6130
6131
6132 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6133
6134 /* Audio output enable */
6135 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6136 tmp = I915_READ(aud_cntrl_st2);
6137 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6138 I915_WRITE(aud_cntrl_st2, tmp);
6139
6140 /* Wait for 1 vertical blank */
6141 intel_wait_for_vblank(dev, pipe);
6142
6143 /* Set ELD valid state */
6144 tmp = I915_READ(aud_cntrl_st2);
6145 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6146 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6147 I915_WRITE(aud_cntrl_st2, tmp);
6148 tmp = I915_READ(aud_cntrl_st2);
6149 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6150
6151 /* Enable HDMI mode */
6152 tmp = I915_READ(aud_config);
6153 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6154 /* clear N_programing_enable and N_value_index */
6155 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6156 I915_WRITE(aud_config, tmp);
6157
6158 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6159
6160 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6161 intel_crtc->eld_vld = true;
83358c85
WX		 6162
6163 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6164 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6165 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6166 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6167 } else
6168 I915_WRITE(aud_config, 0);
6169
6170 if (intel_eld_uptodate(connector,
6171 aud_cntrl_st2, eldv,
6172 aud_cntl_st, IBX_ELD_ADDRESS,
6173 hdmiw_hdmiedid))
6174 return;
6175
6176 i = I915_READ(aud_cntrl_st2);
6177 i &= ~eldv;
6178 I915_WRITE(aud_cntrl_st2, i);
6179
6180 if (!eld[0])
6181 return;
6182
6183 i = I915_READ(aud_cntl_st);
6184 i &= ~IBX_ELD_ADDRESS;
6185 I915_WRITE(aud_cntl_st, i);
6186 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6187 DRM_DEBUG_DRIVER("port num:%d\n", i);
6188
6189 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6190 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6191 for (i = 0; i < len; i++)
6192 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6193
6194 i = I915_READ(aud_cntrl_st2);
6195 i |= eldv;
6196 I915_WRITE(aud_cntrl_st2, i);
6197
6198}
6199
e0dac65e
WF		 6200static void ironlake_write_eld(struct drm_connector *connector,
6201 struct drm_crtc *crtc)
6202{
6203 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6204 uint8_t *eld = connector->eld;
6205 uint32_t eldv;
6206 uint32_t i;
6207 int len;
6208 int hdmiw_hdmiedid;
b6daa025 6209 int aud_config;
e0dac65e
WF		 6210 int aud_cntl_st;
6211 int aud_cntrl_st2;
9b138a83 6212 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6213
b3f33cbf 6214 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6215 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6216 aud_config = IBX_AUD_CFG(pipe);
6217 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6218 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6219 } else {
9b138a83
WX		 6220 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6221 aud_config = CPT_AUD_CFG(pipe);
6222 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6223 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6224 }
6225
9b138a83 6226 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6227
6228 i = I915_READ(aud_cntl_st);
9b138a83 6229 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6230 if (!i) {
6231 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6232 /* operate blindly on all ports */
1202b4c6
WF		 6233 eldv = IBX_ELD_VALIDB;
6234 eldv |= IBX_ELD_VALIDB << 4;
6235 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6236 } else {
2582a850 6237 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6238 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6239 }
6240
3a9627f4
WF		 6241 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6242 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6243 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6244 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6245 } else
6246 I915_WRITE(aud_config, 0);
e0dac65e 6247
3a9627f4
WF		 6248 if (intel_eld_uptodate(connector,
6249 aud_cntrl_st2, eldv,
6250 aud_cntl_st, IBX_ELD_ADDRESS,
6251 hdmiw_hdmiedid))
6252 return;
6253
e0dac65e
WF		 6254 i = I915_READ(aud_cntrl_st2);
6255 i &= ~eldv;
6256 I915_WRITE(aud_cntrl_st2, i);
6257
6258 if (!eld[0])
6259 return;
6260
e0dac65e 6261 i = I915_READ(aud_cntl_st);
1202b4c6 6262 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6263 I915_WRITE(aud_cntl_st, i);
6264
6265 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6266 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6267 for (i = 0; i < len; i++)
6268 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6269
6270 i = I915_READ(aud_cntrl_st2);
6271 i |= eldv;
6272 I915_WRITE(aud_cntrl_st2, i);
6273}
6274
6275void intel_write_eld(struct drm_encoder *encoder,
6276 struct drm_display_mode *mode)
6277{
6278 struct drm_crtc *crtc = encoder->crtc;
6279 struct drm_connector *connector;
6280 struct drm_device *dev = encoder->dev;
6281 struct drm_i915_private *dev_priv = dev->dev_private;
6282
6283 connector = drm_select_eld(encoder, mode);
6284 if (!connector)
6285 return;
6286
6287 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6288 connector->base.id,
6289 drm_get_connector_name(connector),
6290 connector->encoder->base.id,
6291 drm_get_encoder_name(connector->encoder));
6292
6293 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6294
6295 if (dev_priv->display.write_eld)
6296 dev_priv->display.write_eld(connector, crtc);
6297}
6298
79e53945
JB		 6299/** Loads the palette/gamma unit for the CRTC with the prepared values */
6300void intel_crtc_load_lut(struct drm_crtc *crtc)
6301{
6302 struct drm_device *dev = crtc->dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6305 enum pipe pipe = intel_crtc->pipe;
6306 int palreg = PALETTE(pipe);
79e53945 6307 int i;
42db64ef 6308 bool reenable_ips = false;
79e53945
JB		 6309
6310 /* The clocks have to be on to load the palette. */
aed3f09d 6311 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6312 return;
6313
14420bd0
VS		 6314 if (!HAS_PCH_SPLIT(dev_priv->dev))
6315 assert_pll_enabled(dev_priv, pipe);
6316
f2b115e6 6317 /* use legacy palette for Ironlake */
bad720ff 6318 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6319 palreg = LGC_PALETTE(pipe);
6320
6321 /* Workaround : Do not read or write the pipe palette/gamma data while
6322 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6323 */
6324 if (intel_crtc->config.ips_enabled &&
6325 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6326 GAMMA_MODE_MODE_SPLIT)) {
6327 hsw_disable_ips(intel_crtc);
6328 reenable_ips = true;
6329 }
2c07245f 6330
79e53945
JB		 6331 for (i = 0; i < 256; i++) {
6332 I915_WRITE(palreg + 4 * i,
6333 (intel_crtc->lut_r[i] << 16) |
6334 (intel_crtc->lut_g[i] << 8) |
6335 intel_crtc->lut_b[i]);
6336 }
42db64ef
PZ		 6337
6338 if (reenable_ips)
6339 hsw_enable_ips(intel_crtc);
79e53945
JB		 6340}
6341
560b85bb
CW		 6342static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6343{
6344 struct drm_device *dev = crtc->dev;
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 bool visible = base != 0;
6348 u32 cntl;
6349
6350 if (intel_crtc->cursor_visible == visible)
6351 return;
6352
9db4a9c7 6353 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6354 if (visible) {
6355 /* On these chipsets we can only modify the base whilst
6356 * the cursor is disabled.
6357 */
9db4a9c7 6358 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6359
6360 cntl &= ~(CURSOR_FORMAT_MASK);
6361 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6362 cntl |= CURSOR_ENABLE |
6363 CURSOR_GAMMA_ENABLE |
6364 CURSOR_FORMAT_ARGB;
6365 } else
6366 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6367 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6368
6369 intel_crtc->cursor_visible = visible;
6370}
6371
6372static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6373{
6374 struct drm_device *dev = crtc->dev;
6375 struct drm_i915_private *dev_priv = dev->dev_private;
6376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377 int pipe = intel_crtc->pipe;
6378 bool visible = base != 0;
6379
6380 if (intel_crtc->cursor_visible != visible) {
548f245b 6381 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6382 if (base) {
6383 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6384 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6385 cntl |= pipe << 28; /* Connect to correct pipe */
6386 } else {
6387 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6388 cntl |= CURSOR_MODE_DISABLE;
6389 }
9db4a9c7 6390 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6391
6392 intel_crtc->cursor_visible = visible;
6393 }
6394 /* and commit changes on next vblank */
9db4a9c7 6395 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6396}
6397
65a21cd6
JB		 6398static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6399{
6400 struct drm_device *dev = crtc->dev;
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6403 int pipe = intel_crtc->pipe;
6404 bool visible = base != 0;
6405
6406 if (intel_crtc->cursor_visible != visible) {
6407 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6408 if (base) {
6409 cntl &= ~CURSOR_MODE;
6410 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6411 } else {
6412 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6413 cntl |= CURSOR_MODE_DISABLE;
6414 }
86d3efce
VS		 6415 if (IS_HASWELL(dev))
6416 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6417 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6418
6419 intel_crtc->cursor_visible = visible;
6420 }
6421 /* and commit changes on next vblank */
6422 I915_WRITE(CURBASE_IVB(pipe), base);
6423}
6424
cda4b7d3 6425/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6426static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6427 bool on)
cda4b7d3
CW		 6428{
6429 struct drm_device *dev = crtc->dev;
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432 int pipe = intel_crtc->pipe;
6433 int x = intel_crtc->cursor_x;
6434 int y = intel_crtc->cursor_y;
560b85bb 6435 u32 base, pos;
cda4b7d3
CW		 6436 bool visible;
6437
6438 pos = 0;
6439
6b383a7f 6440 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6441 base = intel_crtc->cursor_addr;
6442 if (x > (int) crtc->fb->width)
6443 base = 0;
6444
6445 if (y > (int) crtc->fb->height)
6446 base = 0;
6447 } else
6448 base = 0;
6449
6450 if (x < 0) {
6451 if (x + intel_crtc->cursor_width < 0)
6452 base = 0;
6453
6454 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6455 x = -x;
6456 }
6457 pos |= x << CURSOR_X_SHIFT;
6458
6459 if (y < 0) {
6460 if (y + intel_crtc->cursor_height < 0)
6461 base = 0;
6462
6463 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6464 y = -y;
6465 }
6466 pos |= y << CURSOR_Y_SHIFT;
6467
6468 visible = base != 0;
560b85bb 6469 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6470 return;
6471
0cd83aa9 6472 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6473 I915_WRITE(CURPOS_IVB(pipe), pos);
6474 ivb_update_cursor(crtc, base);
6475 } else {
6476 I915_WRITE(CURPOS(pipe), pos);
6477 if (IS_845G(dev) || IS_I865G(dev))
6478 i845_update_cursor(crtc, base);
6479 else
6480 i9xx_update_cursor(crtc, base);
6481 }
cda4b7d3
CW		 6482}
6483
79e53945 6484static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6485 struct drm_file *file,
79e53945
JB		 6486 uint32_t handle,
6487 uint32_t width, uint32_t height)
6488{
6489 struct drm_device *dev = crtc->dev;
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6492 struct drm_i915_gem_object *obj;
cda4b7d3 6493 uint32_t addr;
3f8bc370 6494 int ret;
79e53945 6495
79e53945
JB		 6496 /* if we want to turn off the cursor ignore width and height */
6497 if (!handle) {
28c97730 6498 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6499 addr = 0;
05394f39 6500 obj = NULL;
5004417d 6501 mutex_lock(&dev->struct_mutex);
3f8bc370 6502 goto finish;
79e53945
JB		 6503 }
6504
6505 /* Currently we only support 64x64 cursors */
6506 if (width != 64 || height != 64) {
6507 DRM_ERROR("we currently only support 64x64 cursors\n");
6508 return -EINVAL;
6509 }
6510
05394f39 6511 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6512 if (&obj->base == NULL)
79e53945
JB		 6513 return -ENOENT;
6514
05394f39 6515 if (obj->base.size < width * height * 4) {
79e53945 6516 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6517 ret = -ENOMEM;
6518 goto fail;
79e53945
JB		 6519 }
6520
71acb5eb 6521 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6522 mutex_lock(&dev->struct_mutex);
b295d1b6 6523 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6524 unsigned alignment;
6525
d9e86c0e
CW		 6526 if (obj->tiling_mode) {
6527 DRM_ERROR("cursor cannot be tiled\n");
6528 ret = -EINVAL;
6529 goto fail_locked;
6530 }
6531
693db184
CW		 6532 /* Note that the w/a also requires 2 PTE of padding following
6533 * the bo. We currently fill all unused PTE with the shadow
6534 * page and so we should always have valid PTE following the
6535 * cursor preventing the VT-d warning.
6536 */
6537 alignment = 0;
6538 if (need_vtd_wa(dev))
6539 alignment = 64*1024;
6540
6541 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6542 if (ret) {
6543 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6544 goto fail_locked;
e7b526bb
CW		 6545 }
6546
d9e86c0e
CW		 6547 ret = i915_gem_object_put_fence(obj);
6548 if (ret) {
2da3b9b9 6549 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6550 goto fail_unpin;
6551 }
6552
05394f39 6553 addr = obj->gtt_offset;
71acb5eb 6554 } else {
6eeefaf3 6555 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6556 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6557 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6558 align);
71acb5eb
DA		 6559 if (ret) {
6560 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6561 goto fail_locked;
71acb5eb 6562 }
05394f39 6563 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6564 }
6565
a6c45cf0 6566 if (IS_GEN2(dev))
14b60391
JB		 6567 I915_WRITE(CURSIZE, (height << 12) | width);
6568
3f8bc370 6569 finish:
3f8bc370 6570 if (intel_crtc->cursor_bo) {
b295d1b6 6571 if (dev_priv->info->cursor_needs_physical) {
05394f39 6572 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6573 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6574 } else
6575 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6576 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6577 }
80824003 6578
7f9872e0 6579 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6580
6581 intel_crtc->cursor_addr = addr;
05394f39 6582 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6583 intel_crtc->cursor_width = width;
6584 intel_crtc->cursor_height = height;
6585
40ccc72b 6586 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6587
79e53945 6588 return 0;
e7b526bb 6589fail_unpin:
05394f39 6590 i915_gem_object_unpin(obj);
7f9872e0 6591fail_locked:
34b8686e 6592 mutex_unlock(&dev->struct_mutex);
bc9025bd 6593fail:
05394f39 6594 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6595 return ret;
79e53945
JB		 6596}
6597
6598static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6599{
79e53945 6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6601
cda4b7d3
CW		 6602 intel_crtc->cursor_x = x;
6603 intel_crtc->cursor_y = y;
652c393a 6604
40ccc72b 6605 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6606
6607 return 0;
6608}
6609
6610/** Sets the color ramps on behalf of RandR */
6611void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6612 u16 blue, int regno)
6613{
6614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615
6616 intel_crtc->lut_r[regno] = red >> 8;
6617 intel_crtc->lut_g[regno] = green >> 8;
6618 intel_crtc->lut_b[regno] = blue >> 8;
6619}
6620
b8c00ac5
DA		 6621void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6622 u16 *blue, int regno)
6623{
6624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6625
6626 *red = intel_crtc->lut_r[regno] << 8;
6627 *green = intel_crtc->lut_g[regno] << 8;
6628 *blue = intel_crtc->lut_b[regno] << 8;
6629}
6630
79e53945 6631static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6632 u16 *blue, uint32_t start, uint32_t size)
79e53945 6633{
7203425a 6634 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6636
7203425a 6637 for (i = start; i < end; i++) {
79e53945
JB		 6638 intel_crtc->lut_r[i] = red[i] >> 8;
6639 intel_crtc->lut_g[i] = green[i] >> 8;
6640 intel_crtc->lut_b[i] = blue[i] >> 8;
6641 }
6642
6643 intel_crtc_load_lut(crtc);
6644}
6645
79e53945
JB		 6646/* VESA 640x480x72Hz mode to set on the pipe */
6647static struct drm_display_mode load_detect_mode = {
6648 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6649 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6650};
6651
d2dff872
CW		 6652static struct drm_framebuffer *
6653intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6654 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6655 struct drm_i915_gem_object *obj)
6656{
6657 struct intel_framebuffer *intel_fb;
6658 int ret;
6659
6660 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6661 if (!intel_fb) {
6662 drm_gem_object_unreference_unlocked(&obj->base);
6663 return ERR_PTR(-ENOMEM);
6664 }
6665
6666 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6667 if (ret) {
6668 drm_gem_object_unreference_unlocked(&obj->base);
6669 kfree(intel_fb);
6670 return ERR_PTR(ret);
6671 }
6672
6673 return &intel_fb->base;
6674}
6675
6676static u32
6677intel_framebuffer_pitch_for_width(int width, int bpp)
6678{
6679 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6680 return ALIGN(pitch, 64);
6681}
6682
6683static u32
6684intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6685{
6686 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6687 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6688}
6689
6690static struct drm_framebuffer *
6691intel_framebuffer_create_for_mode(struct drm_device *dev,
6692 struct drm_display_mode *mode,
6693 int depth, int bpp)
6694{
6695 struct drm_i915_gem_object *obj;
0fed39bd 6696 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6697
6698 obj = i915_gem_alloc_object(dev,
6699 intel_framebuffer_size_for_mode(mode, bpp));
6700 if (obj == NULL)
6701 return ERR_PTR(-ENOMEM);
6702
6703 mode_cmd.width = mode->hdisplay;
6704 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6705 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6706 bpp);
5ca0c34a 6707 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6708
6709 return intel_framebuffer_create(dev, &mode_cmd, obj);
6710}
6711
6712static struct drm_framebuffer *
6713mode_fits_in_fbdev(struct drm_device *dev,
6714 struct drm_display_mode *mode)
6715{
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6717 struct drm_i915_gem_object *obj;
6718 struct drm_framebuffer *fb;
6719
6720 if (dev_priv->fbdev == NULL)
6721 return NULL;
6722
6723 obj = dev_priv->fbdev->ifb.obj;
6724 if (obj == NULL)
6725 return NULL;
6726
6727 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6728 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6729 fb->bits_per_pixel))
d2dff872
CW		 6730 return NULL;
6731
01f2c773 6732 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6733 return NULL;
6734
6735 return fb;
6736}
6737
d2434ab7 6738bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6739 struct drm_display_mode *mode,
8261b191 6740 struct intel_load_detect_pipe *old)
79e53945
JB		 6741{
6742 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6743 struct intel_encoder *intel_encoder =
6744 intel_attached_encoder(connector);
79e53945 6745 struct drm_crtc *possible_crtc;
4ef69c7a 6746 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6747 struct drm_crtc *crtc = NULL;
6748 struct drm_device *dev = encoder->dev;
94352cf9 6749 struct drm_framebuffer *fb;
79e53945
JB		 6750 int i = -1;
6751
d2dff872
CW		 6752 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6753 connector->base.id, drm_get_connector_name(connector),
6754 encoder->base.id, drm_get_encoder_name(encoder));
6755
79e53945
JB		 6756 /*
6757 * Algorithm gets a little messy:
7a5e4805 6758 *
79e53945
JB		 6759 * - if the connector already has an assigned crtc, use it (but make
6760 * sure it's on first)
7a5e4805 6761 *
79e53945
JB		 6762 * - try to find the first unused crtc that can drive this connector,
6763 * and use that if we find one
79e53945
JB		 6764 */
6765
6766 /* See if we already have a CRTC for this connector */
6767 if (encoder->crtc) {
6768 crtc = encoder->crtc;
8261b191 6769
7b24056b
DV		 6770 mutex_lock(&crtc->mutex);
6771
24218aac 6772 old->dpms_mode = connector->dpms;
8261b191
CW		 6773 old->load_detect_temp = false;
6774
6775 /* Make sure the crtc and connector are running */
24218aac
DV		 6776 if (connector->dpms != DRM_MODE_DPMS_ON)
6777 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6778
7173188d 6779 return true;
79e53945
JB		 6780 }
6781
6782 /* Find an unused one (if possible) */
6783 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6784 i++;
6785 if (!(encoder->possible_crtcs & (1 << i)))
6786 continue;
6787 if (!possible_crtc->enabled) {
6788 crtc = possible_crtc;
6789 break;
6790 }
79e53945
JB		 6791 }
6792
6793 /*
6794 * If we didn't find an unused CRTC, don't use any.
6795 */
6796 if (!crtc) {
7173188d
CW		 6797 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6798 return false;
79e53945
JB		 6799 }
6800
7b24056b 6801 mutex_lock(&crtc->mutex);
fc303101
DV		 6802 intel_encoder->new_crtc = to_intel_crtc(crtc);
6803 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6804
6805 intel_crtc = to_intel_crtc(crtc);
24218aac 6806 old->dpms_mode = connector->dpms;
8261b191 6807 old->load_detect_temp = true;
d2dff872 6808 old->release_fb = NULL;
79e53945 6809
6492711d
CW		 6810 if (!mode)
6811 mode = &load_detect_mode;
79e53945 6812
d2dff872
CW		 6813 /* We need a framebuffer large enough to accommodate all accesses
6814 * that the plane may generate whilst we perform load detection.
6815 * We can not rely on the fbcon either being present (we get called
6816 * during its initialisation to detect all boot displays, or it may
6817 * not even exist) or that it is large enough to satisfy the
6818 * requested mode.
6819 */
94352cf9
DV		 6820 fb = mode_fits_in_fbdev(dev, mode);
6821 if (fb == NULL) {
d2dff872 6822 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6823 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6824 old->release_fb = fb;
d2dff872
CW		 6825 } else
6826 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6827 if (IS_ERR(fb)) {
d2dff872 6828 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6829 mutex_unlock(&crtc->mutex);
0e8b3d3e 6830 return false;
79e53945 6831 }
79e53945 6832
c0c36b94 6833 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6834 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6835 if (old->release_fb)
6836 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6837 mutex_unlock(&crtc->mutex);
0e8b3d3e 6838 return false;
79e53945 6839 }
7173188d 6840
79e53945 6841 /* let the connector get through one full cycle before testing */
9d0498a2 6842 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6843 return true;
79e53945
JB		 6844}
6845
d2434ab7 6846void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6847 struct intel_load_detect_pipe *old)
79e53945 6848{
d2434ab7
DV		 6849 struct intel_encoder *intel_encoder =
6850 intel_attached_encoder(connector);
4ef69c7a 6851 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6852 struct drm_crtc *crtc = encoder->crtc;
79e53945 6853
d2dff872
CW		 6854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6855 connector->base.id, drm_get_connector_name(connector),
6856 encoder->base.id, drm_get_encoder_name(encoder));
6857
8261b191 6858 if (old->load_detect_temp) {
fc303101
DV		 6859 to_intel_connector(connector)->new_encoder = NULL;
6860 intel_encoder->new_crtc = NULL;
6861 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6862
36206361
DV		 6863 if (old->release_fb) {
6864 drm_framebuffer_unregister_private(old->release_fb);
6865 drm_framebuffer_unreference(old->release_fb);
6866 }
d2dff872 6867
67c96400 6868 mutex_unlock(&crtc->mutex);
0622a53c 6869 return;
79e53945
JB		 6870 }
6871
c751ce4f 6872 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6873 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6874 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6875
6876 mutex_unlock(&crtc->mutex);
79e53945
JB		 6877}
6878
6879/* Returns the clock of the currently programmed mode of the given pipe. */
6880static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6881{
6882 struct drm_i915_private *dev_priv = dev->dev_private;
6883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6884 int pipe = intel_crtc->pipe;
548f245b 6885 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6886 u32 fp;
6887 intel_clock_t clock;
6888
6889 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6890 fp = I915_READ(FP0(pipe));
79e53945 6891 else
39adb7a5 6892 fp = I915_READ(FP1(pipe));
79e53945
JB		 6893
6894 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6895 if (IS_PINEVIEW(dev)) {
6896 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6897 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6898 } else {
6899 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6900 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6901 }
6902
a6c45cf0 6903 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6904 if (IS_PINEVIEW(dev))
6905 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6906 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6907 else
6908 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6909 DPLL_FPA01_P1_POST_DIV_SHIFT);
6910
6911 switch (dpll & DPLL_MODE_MASK) {
6912 case DPLLB_MODE_DAC_SERIAL:
6913 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6914 5 : 10;
6915 break;
6916 case DPLLB_MODE_LVDS:
6917 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6918 7 : 14;
6919 break;
6920 default:
28c97730 6921 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6922 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6923 return 0;
6924 }
6925
ac58c3f0
DV		 6926 if (IS_PINEVIEW(dev))
6927 pineview_clock(96000, &clock);
6928 else
6929 i9xx_clock(96000, &clock);
79e53945
JB		 6930 } else {
6931 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6932
6933 if (is_lvds) {
6934 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6935 DPLL_FPA01_P1_POST_DIV_SHIFT);
6936 clock.p2 = 14;
6937
6938 if ((dpll & PLL_REF_INPUT_MASK) ==
6939 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6940 /* XXX: might not be 66MHz */
ac58c3f0 6941 i9xx_clock(66000, &clock);
79e53945 6942 } else
ac58c3f0 6943 i9xx_clock(48000, &clock);
79e53945
JB		 6944 } else {
6945 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6946 clock.p1 = 2;
6947 else {
6948 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6949 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6950 }
6951 if (dpll & PLL_P2_DIVIDE_BY_4)
6952 clock.p2 = 4;
6953 else
6954 clock.p2 = 2;
6955
ac58c3f0 6956 i9xx_clock(48000, &clock);
79e53945
JB		 6957 }
6958 }
6959
6960 /* XXX: It would be nice to validate the clocks, but we can't reuse
6961 * i830PllIsValid() because it relies on the xf86_config connector
6962 * configuration being accurate, which it isn't necessarily.
6963 */
6964
6965 return clock.dot;
6966}
6967
6968/** Returns the currently programmed mode of the given pipe. */
6969struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6970 struct drm_crtc *crtc)
6971{
548f245b 6972 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6974 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6975 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6976 int htot = I915_READ(HTOTAL(cpu_transcoder));
6977 int hsync = I915_READ(HSYNC(cpu_transcoder));
6978 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6979 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6980
6981 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6982 if (!mode)
6983 return NULL;
6984
6985 mode->clock = intel_crtc_clock_get(dev, crtc);
6986 mode->hdisplay = (htot & 0xffff) + 1;
6987 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6988 mode->hsync_start = (hsync & 0xffff) + 1;
6989 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6990 mode->vdisplay = (vtot & 0xffff) + 1;
6991 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6992 mode->vsync_start = (vsync & 0xffff) + 1;
6993 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6994
6995 drm_mode_set_name(mode);
79e53945
JB		 6996
6997 return mode;
6998}
6999
3dec0095 7000static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7001{
7002 struct drm_device *dev = crtc->dev;
7003 drm_i915_private_t *dev_priv = dev->dev_private;
7004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7005 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7006 int dpll_reg = DPLL(pipe);
7007 int dpll;
652c393a 7008
bad720ff 7009 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7010 return;
7011
7012 if (!dev_priv->lvds_downclock_avail)
7013 return;
7014
dbdc6479 7015 dpll = I915_READ(dpll_reg);
652c393a 7016 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7017 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7018
8ac5a6d5 7019 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7020
7021 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7022 I915_WRITE(dpll_reg, dpll);
9d0498a2 7023 intel_wait_for_vblank(dev, pipe);
dbdc6479 7024
652c393a
JB		 7025 dpll = I915_READ(dpll_reg);
7026 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7027 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7028 }
652c393a
JB		 7029}
7030
7031static void intel_decrease_pllclock(struct drm_crtc *crtc)
7032{
7033 struct drm_device *dev = crtc->dev;
7034 drm_i915_private_t *dev_priv = dev->dev_private;
7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7036
bad720ff 7037 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7038 return;
7039
7040 if (!dev_priv->lvds_downclock_avail)
7041 return;
7042
7043 /*
7044 * Since this is called by a timer, we should never get here in
7045 * the manual case.
7046 */
7047 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7048 int pipe = intel_crtc->pipe;
7049 int dpll_reg = DPLL(pipe);
7050 int dpll;
f6e5b160 7051
44d98a61 7052 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7053
8ac5a6d5 7054 assert_panel_unlocked(dev_priv, pipe);
652c393a 7055
dc257cf1 7056 dpll = I915_READ(dpll_reg);
652c393a
JB		 7057 dpll |= DISPLAY_RATE_SELECT_FPA1;
7058 I915_WRITE(dpll_reg, dpll);
9d0498a2 7059 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7060 dpll = I915_READ(dpll_reg);
7061 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7062 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7063 }
7064
7065}
7066
f047e395
CW		 7067void intel_mark_busy(struct drm_device *dev)
7068{
f047e395
CW		 7069 i915_update_gfx_val(dev->dev_private);
7070}
7071
7072void intel_mark_idle(struct drm_device *dev)
652c393a 7073{
652c393a 7074 struct drm_crtc *crtc;
652c393a
JB		 7075
7076 if (!i915_powersave)
7077 return;
7078
652c393a 7079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7080 if (!crtc->fb)
7081 continue;
7082
725a5b54 7083 intel_decrease_pllclock(crtc);
652c393a 7084 }
652c393a
JB		 7085}
7086
c65355bb
CW		 7087void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7088 struct intel_ring_buffer *ring)
652c393a 7089{
f047e395
CW		 7090 struct drm_device *dev = obj->base.dev;
7091 struct drm_crtc *crtc;
652c393a 7092
f047e395 7093 if (!i915_powersave)
acb87dfb
CW		 7094 return;
7095
652c393a
JB		 7096 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7097 if (!crtc->fb)
7098 continue;
7099
c65355bb
CW		 7100 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7101 continue;
7102
7103 intel_increase_pllclock(crtc);
7104 if (ring && intel_fbc_enabled(dev))
7105 ring->fbc_dirty = true;
652c393a
JB		 7106 }
7107}
7108
79e53945
JB		 7109static void intel_crtc_destroy(struct drm_crtc *crtc)
7110{
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7112 struct drm_device *dev = crtc->dev;
7113 struct intel_unpin_work *work;
7114 unsigned long flags;
7115
7116 spin_lock_irqsave(&dev->event_lock, flags);
7117 work = intel_crtc->unpin_work;
7118 intel_crtc->unpin_work = NULL;
7119 spin_unlock_irqrestore(&dev->event_lock, flags);
7120
7121 if (work) {
7122 cancel_work_sync(&work->work);
7123 kfree(work);
7124 }
79e53945 7125
40ccc72b
MK		 7126 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7127
79e53945 7128 drm_crtc_cleanup(crtc);
67e77c5a 7129
79e53945
JB		 7130 kfree(intel_crtc);
7131}
7132
6b95a207
KH		 7133static void intel_unpin_work_fn(struct work_struct *__work)
7134{
7135 struct intel_unpin_work *work =
7136 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7137 struct drm_device *dev = work->crtc->dev;
6b95a207 7138
b4a98e57 7139 mutex_lock(&dev->struct_mutex);
1690e1eb 7140 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7141 drm_gem_object_unreference(&work->pending_flip_obj->base);
7142 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7143
b4a98e57
CW		 7144 intel_update_fbc(dev);
7145 mutex_unlock(&dev->struct_mutex);
7146
7147 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7148 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7149
6b95a207
KH		 7150 kfree(work);
7151}
7152
1afe3e9d 7153static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7154 struct drm_crtc *crtc)
6b95a207
KH		 7155{
7156 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158 struct intel_unpin_work *work;
6b95a207
KH		 7159 unsigned long flags;
7160
7161 /* Ignore early vblank irqs */
7162 if (intel_crtc == NULL)
7163 return;
7164
7165 spin_lock_irqsave(&dev->event_lock, flags);
7166 work = intel_crtc->unpin_work;
e7d841ca
CW		 7167
7168 /* Ensure we don't miss a work->pending update ... */
7169 smp_rmb();
7170
7171 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7172 spin_unlock_irqrestore(&dev->event_lock, flags);
7173 return;
7174 }
7175
e7d841ca
CW		 7176 /* and that the unpin work is consistent wrt ->pending. */
7177 smp_rmb();
7178
6b95a207 7179 intel_crtc->unpin_work = NULL;
6b95a207 7180
45a066eb
RC		 7181 if (work->event)
7182 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7183
0af7e4df
MK		 7184 drm_vblank_put(dev, intel_crtc->pipe);
7185
6b95a207
KH		 7186 spin_unlock_irqrestore(&dev->event_lock, flags);
7187
2c10d571 7188 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7189
7190 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7191
7192 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7193}
7194
1afe3e9d
JB		 7195void intel_finish_page_flip(struct drm_device *dev, int pipe)
7196{
7197 drm_i915_private_t *dev_priv = dev->dev_private;
7198 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7199
49b14a5c 7200 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7201}
7202
7203void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7204{
7205 drm_i915_private_t *dev_priv = dev->dev_private;
7206 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7207
49b14a5c 7208 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7209}
7210
6b95a207
KH		 7211void intel_prepare_page_flip(struct drm_device *dev, int plane)
7212{
7213 drm_i915_private_t *dev_priv = dev->dev_private;
7214 struct intel_crtc *intel_crtc =
7215 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7216 unsigned long flags;
7217
e7d841ca
CW		 7218 /* NB: An MMIO update of the plane base pointer will also
7219 * generate a page-flip completion irq, i.e. every modeset
7220 * is also accompanied by a spurious intel_prepare_page_flip().
7221 */
6b95a207 7222 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7223 if (intel_crtc->unpin_work)
7224 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7225 spin_unlock_irqrestore(&dev->event_lock, flags);
7226}
7227
e7d841ca
CW		 7228inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7229{
7230 /* Ensure that the work item is consistent when activating it ... */
7231 smp_wmb();
7232 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7233 /* and that it is marked active as soon as the irq could fire. */
7234 smp_wmb();
7235}
7236
8c9f3aaf
JB		 7237static int intel_gen2_queue_flip(struct drm_device *dev,
7238 struct drm_crtc *crtc,
7239 struct drm_framebuffer *fb,
7240 struct drm_i915_gem_object *obj)
7241{
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7244 u32 flip_mask;
6d90c952 7245 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7246 int ret;
7247
6d90c952 7248 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7249 if (ret)
83d4092b 7250 goto err;
8c9f3aaf 7251
6d90c952 7252 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7253 if (ret)
83d4092b 7254 goto err_unpin;
8c9f3aaf
JB		 7255
7256 /* Can't queue multiple flips, so wait for the previous
7257 * one to finish before executing the next.
7258 */
7259 if (intel_crtc->plane)
7260 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7261 else
7262 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7263 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7264 intel_ring_emit(ring, MI_NOOP);
7265 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7266 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7267 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7268 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7269 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7270
7271 intel_mark_page_flip_active(intel_crtc);
6d90c952 7272 intel_ring_advance(ring);
83d4092b
CW		 7273 return 0;
7274
7275err_unpin:
7276 intel_unpin_fb_obj(obj);
7277err:
8c9f3aaf
JB		 7278 return ret;
7279}
7280
7281static int intel_gen3_queue_flip(struct drm_device *dev,
7282 struct drm_crtc *crtc,
7283 struct drm_framebuffer *fb,
7284 struct drm_i915_gem_object *obj)
7285{
7286 struct drm_i915_private *dev_priv = dev->dev_private;
7287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7288 u32 flip_mask;
6d90c952 7289 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7290 int ret;
7291
6d90c952 7292 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7293 if (ret)
83d4092b 7294 goto err;
8c9f3aaf 7295
6d90c952 7296 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7297 if (ret)
83d4092b 7298 goto err_unpin;
8c9f3aaf
JB		 7299
7300 if (intel_crtc->plane)
7301 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7302 else
7303 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7304 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7305 intel_ring_emit(ring, MI_NOOP);
7306 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7307 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7308 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7309 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7310 intel_ring_emit(ring, MI_NOOP);
7311
e7d841ca 7312 intel_mark_page_flip_active(intel_crtc);
6d90c952 7313 intel_ring_advance(ring);
83d4092b
CW		 7314 return 0;
7315
7316err_unpin:
7317 intel_unpin_fb_obj(obj);
7318err:
8c9f3aaf
JB		 7319 return ret;
7320}
7321
7322static int intel_gen4_queue_flip(struct drm_device *dev,
7323 struct drm_crtc *crtc,
7324 struct drm_framebuffer *fb,
7325 struct drm_i915_gem_object *obj)
7326{
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7329 uint32_t pf, pipesrc;
6d90c952 7330 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7331 int ret;
7332
6d90c952 7333 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7334 if (ret)
83d4092b 7335 goto err;
8c9f3aaf 7336
6d90c952 7337 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7338 if (ret)
83d4092b 7339 goto err_unpin;
8c9f3aaf
JB		 7340
7341 /* i965+ uses the linear or tiled offsets from the
7342 * Display Registers (which do not change across a page-flip)
7343 * so we need only reprogram the base address.
7344 */
6d90c952
DV		 7345 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7347 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7348 intel_ring_emit(ring,
7349 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7350 obj->tiling_mode);
8c9f3aaf
JB		 7351
7352 /* XXX Enabling the panel-fitter across page-flip is so far
7353 * untested on non-native modes, so ignore it for now.
7354 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7355 */
7356 pf = 0;
7357 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7358 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7359
7360 intel_mark_page_flip_active(intel_crtc);
6d90c952 7361 intel_ring_advance(ring);
83d4092b
CW		 7362 return 0;
7363
7364err_unpin:
7365 intel_unpin_fb_obj(obj);
7366err:
8c9f3aaf
JB		 7367 return ret;
7368}
7369
7370static int intel_gen6_queue_flip(struct drm_device *dev,
7371 struct drm_crtc *crtc,
7372 struct drm_framebuffer *fb,
7373 struct drm_i915_gem_object *obj)
7374{
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7377 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7378 uint32_t pf, pipesrc;
7379 int ret;
7380
6d90c952 7381 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7382 if (ret)
83d4092b 7383 goto err;
8c9f3aaf 7384
6d90c952 7385 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7386 if (ret)
83d4092b 7387 goto err_unpin;
8c9f3aaf 7388
6d90c952
DV		 7389 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7390 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7391 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7392 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7393
dc257cf1
DV		 7394 /* Contrary to the suggestions in the documentation,
7395 * "Enable Panel Fitter" does not seem to be required when page
7396 * flipping with a non-native mode, and worse causes a normal
7397 * modeset to fail.
7398 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7399 */
7400 pf = 0;
8c9f3aaf 7401 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7402 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7403
7404 intel_mark_page_flip_active(intel_crtc);
6d90c952 7405 intel_ring_advance(ring);
83d4092b
CW		 7406 return 0;
7407
7408err_unpin:
7409 intel_unpin_fb_obj(obj);
7410err:
8c9f3aaf
JB		 7411 return ret;
7412}
7413
7c9017e5
JB		 7414/*
7415 * On gen7 we currently use the blit ring because (in early silicon at least)
7416 * the render ring doesn't give us interrpts for page flip completion, which
7417 * means clients will hang after the first flip is queued. Fortunately the
7418 * blit ring generates interrupts properly, so use it instead.
7419 */
7420static int intel_gen7_queue_flip(struct drm_device *dev,
7421 struct drm_crtc *crtc,
7422 struct drm_framebuffer *fb,
7423 struct drm_i915_gem_object *obj)
7424{
7425 struct drm_i915_private *dev_priv = dev->dev_private;
7426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7427 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7428 uint32_t plane_bit = 0;
7c9017e5
JB		 7429 int ret;
7430
7431 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7432 if (ret)
83d4092b 7433 goto err;
7c9017e5 7434
cb05d8de
DV		 7435 switch(intel_crtc->plane) {
7436 case PLANE_A:
7437 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7438 break;
7439 case PLANE_B:
7440 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7441 break;
7442 case PLANE_C:
7443 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7444 break;
7445 default:
7446 WARN_ONCE(1, "unknown plane in flip command\n");
7447 ret = -ENODEV;
ab3951eb 7448 goto err_unpin;
cb05d8de
DV		 7449 }
7450
7c9017e5
JB		 7451 ret = intel_ring_begin(ring, 4);
7452 if (ret)
83d4092b 7453 goto err_unpin;
7c9017e5 7454
cb05d8de 7455 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7456 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7457 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7458 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7459
7460 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7461 intel_ring_advance(ring);
83d4092b
CW		 7462 return 0;
7463
7464err_unpin:
7465 intel_unpin_fb_obj(obj);
7466err:
7c9017e5
JB		 7467 return ret;
7468}
7469
8c9f3aaf
JB		 7470static int intel_default_queue_flip(struct drm_device *dev,
7471 struct drm_crtc *crtc,
7472 struct drm_framebuffer *fb,
7473 struct drm_i915_gem_object *obj)
7474{
7475 return -ENODEV;
7476}
7477
6b95a207
KH		 7478static int intel_crtc_page_flip(struct drm_crtc *crtc,
7479 struct drm_framebuffer *fb,
7480 struct drm_pending_vblank_event *event)
7481{
7482 struct drm_device *dev = crtc->dev;
7483 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7484 struct drm_framebuffer *old_fb = crtc->fb;
7485 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7487 struct intel_unpin_work *work;
8c9f3aaf 7488 unsigned long flags;
52e68630 7489 int ret;
6b95a207 7490
e6a595d2
VS		 7491 /* Can't change pixel format via MI display flips. */
7492 if (fb->pixel_format != crtc->fb->pixel_format)
7493 return -EINVAL;
7494
7495 /*
7496 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7497 * Note that pitch changes could also affect these register.
7498 */
7499 if (INTEL_INFO(dev)->gen > 3 &&
7500 (fb->offsets[0] != crtc->fb->offsets[0] ||
7501 fb->pitches[0] != crtc->fb->pitches[0]))
7502 return -EINVAL;
7503
6b95a207
KH		 7504 work = kzalloc(sizeof *work, GFP_KERNEL);
7505 if (work == NULL)
7506 return -ENOMEM;
7507
6b95a207 7508 work->event = event;
b4a98e57 7509 work->crtc = crtc;
4a35f83b 7510 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7511 INIT_WORK(&work->work, intel_unpin_work_fn);
7512
7317c75e
JB		 7513 ret = drm_vblank_get(dev, intel_crtc->pipe);
7514 if (ret)
7515 goto free_work;
7516
6b95a207
KH		 7517 /* We borrow the event spin lock for protecting unpin_work */
7518 spin_lock_irqsave(&dev->event_lock, flags);
7519 if (intel_crtc->unpin_work) {
7520 spin_unlock_irqrestore(&dev->event_lock, flags);
7521 kfree(work);
7317c75e 7522 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7523
7524 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7525 return -EBUSY;
7526 }
7527 intel_crtc->unpin_work = work;
7528 spin_unlock_irqrestore(&dev->event_lock, flags);
7529
b4a98e57
CW		 7530 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7531 flush_workqueue(dev_priv->wq);
7532
79158103
CW		 7533 ret = i915_mutex_lock_interruptible(dev);
7534 if (ret)
7535 goto cleanup;
6b95a207 7536
75dfca80 7537 /* Reference the objects for the scheduled work. */
05394f39
CW		 7538 drm_gem_object_reference(&work->old_fb_obj->base);
7539 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7540
7541 crtc->fb = fb;
96b099fd 7542
e1f99ce6 7543 work->pending_flip_obj = obj;
e1f99ce6 7544
4e5359cd
SF		 7545 work->enable_stall_check = true;
7546
b4a98e57 7547 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7548 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7549
8c9f3aaf
JB		 7550 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7551 if (ret)
7552 goto cleanup_pending;
6b95a207 7553
7782de3b 7554 intel_disable_fbc(dev);
c65355bb 7555 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7556 mutex_unlock(&dev->struct_mutex);
7557
e5510fac
JB		 7558 trace_i915_flip_request(intel_crtc->plane, obj);
7559
6b95a207 7560 return 0;
96b099fd 7561
8c9f3aaf 7562cleanup_pending:
b4a98e57 7563 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7564 crtc->fb = old_fb;
05394f39
CW		 7565 drm_gem_object_unreference(&work->old_fb_obj->base);
7566 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7567 mutex_unlock(&dev->struct_mutex);
7568
79158103 7569cleanup:
96b099fd
CW		 7570 spin_lock_irqsave(&dev->event_lock, flags);
7571 intel_crtc->unpin_work = NULL;
7572 spin_unlock_irqrestore(&dev->event_lock, flags);
7573
7317c75e
JB		 7574 drm_vblank_put(dev, intel_crtc->pipe);
7575free_work:
96b099fd
CW		 7576 kfree(work);
7577
7578 return ret;
6b95a207
KH		 7579}
7580
f6e5b160 7581static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7582 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7583 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7584};
7585
50f56119
DV		 7586static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7587 struct drm_crtc *crtc)
7588{
7589 struct drm_device *dev;
7590 struct drm_crtc *tmp;
7591 int crtc_mask = 1;
47f1c6c9 7592
50f56119 7593 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7594
50f56119 7595 dev = crtc->dev;
47f1c6c9 7596
50f56119
DV		 7597 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7598 if (tmp == crtc)
7599 break;
7600 crtc_mask <<= 1;
7601 }
47f1c6c9 7602
50f56119
DV		 7603 if (encoder->possible_crtcs & crtc_mask)
7604 return true;
7605 return false;
47f1c6c9 7606}
79e53945 7607
9a935856
DV		 7608/**
7609 * intel_modeset_update_staged_output_state
7610 *
7611 * Updates the staged output configuration state, e.g. after we've read out the
7612 * current hw state.
7613 */
7614static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7615{
9a935856
DV		 7616 struct intel_encoder *encoder;
7617 struct intel_connector *connector;
f6e5b160 7618
9a935856
DV		 7619 list_for_each_entry(connector, &dev->mode_config.connector_list,
7620 base.head) {
7621 connector->new_encoder =
7622 to_intel_encoder(connector->base.encoder);
7623 }
f6e5b160 7624
9a935856
DV		 7625 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7626 base.head) {
7627 encoder->new_crtc =
7628 to_intel_crtc(encoder->base.crtc);
7629 }
f6e5b160
CW		 7630}
7631
9a935856
DV		 7632/**
7633 * intel_modeset_commit_output_state
7634 *
7635 * This function copies the stage display pipe configuration to the real one.
7636 */
7637static void intel_modeset_commit_output_state(struct drm_device *dev)
7638{
7639 struct intel_encoder *encoder;
7640 struct intel_connector *connector;
f6e5b160 7641
9a935856
DV		 7642 list_for_each_entry(connector, &dev->mode_config.connector_list,
7643 base.head) {
7644 connector->base.encoder = &connector->new_encoder->base;
7645 }
f6e5b160 7646
9a935856
DV		 7647 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7648 base.head) {
7649 encoder->base.crtc = &encoder->new_crtc->base;
7650 }
7651}
7652
050f7aeb
DV		 7653static void
7654connected_sink_compute_bpp(struct intel_connector * connector,
7655 struct intel_crtc_config *pipe_config)
7656{
7657 int bpp = pipe_config->pipe_bpp;
7658
7659 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7660 connector->base.base.id,
7661 drm_get_connector_name(&connector->base));
7662
7663 /* Don't use an invalid EDID bpc value */
7664 if (connector->base.display_info.bpc &&
7665 connector->base.display_info.bpc * 3 < bpp) {
7666 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7667 bpp, connector->base.display_info.bpc*3);
7668 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7669 }
7670
7671 /* Clamp bpp to 8 on screens without EDID 1.4 */
7672 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7673 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7674 bpp);
7675 pipe_config->pipe_bpp = 24;
7676 }
7677}
7678
4e53c2e0 7679static int
050f7aeb
DV		 7680compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7681 struct drm_framebuffer *fb,
7682 struct intel_crtc_config *pipe_config)
4e53c2e0 7683{
050f7aeb
DV		 7684 struct drm_device *dev = crtc->base.dev;
7685 struct intel_connector *connector;
4e53c2e0
DV		 7686 int bpp;
7687
d42264b1
DV		 7688 switch (fb->pixel_format) {
7689 case DRM_FORMAT_C8:
4e53c2e0
DV		 7690 bpp = 8*3; /* since we go through a colormap */
7691 break;
d42264b1
DV		 7692 case DRM_FORMAT_XRGB1555:
7693 case DRM_FORMAT_ARGB1555:
7694 /* checked in intel_framebuffer_init already */
7695 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7696 return -EINVAL;
7697 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7698 bpp = 6*3; /* min is 18bpp */
7699 break;
d42264b1
DV		 7700 case DRM_FORMAT_XBGR8888:
7701 case DRM_FORMAT_ABGR8888:
7702 /* checked in intel_framebuffer_init already */
7703 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7704 return -EINVAL;
7705 case DRM_FORMAT_XRGB8888:
7706 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7707 bpp = 8*3;
7708 break;
d42264b1
DV		 7709 case DRM_FORMAT_XRGB2101010:
7710 case DRM_FORMAT_ARGB2101010:
7711 case DRM_FORMAT_XBGR2101010:
7712 case DRM_FORMAT_ABGR2101010:
7713 /* checked in intel_framebuffer_init already */
7714 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7715 return -EINVAL;
4e53c2e0
DV		 7716 bpp = 10*3;
7717 break;
baba133a 7718 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7719 default:
7720 DRM_DEBUG_KMS("unsupported depth\n");
7721 return -EINVAL;
7722 }
7723
4e53c2e0
DV		 7724 pipe_config->pipe_bpp = bpp;
7725
7726 /* Clamp display bpp to EDID value */
7727 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7728 base.head) {
1b829e05
DV		 7729 if (!connector->new_encoder ||
7730 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7731 continue;
7732
050f7aeb 7733 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7734 }
7735
7736 return bpp;
7737}
7738
c0b03411
DV		 7739static void intel_dump_pipe_config(struct intel_crtc *crtc,
7740 struct intel_crtc_config *pipe_config,
7741 const char *context)
7742{
7743 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7744 context, pipe_name(crtc->pipe));
7745
7746 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7747 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7748 pipe_config->pipe_bpp, pipe_config->dither);
7749 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7750 pipe_config->has_pch_encoder,
7751 pipe_config->fdi_lanes,
7752 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7753 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7754 pipe_config->fdi_m_n.tu);
7755 DRM_DEBUG_KMS("requested mode:\n");
7756 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7757 DRM_DEBUG_KMS("adjusted mode:\n");
7758 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7759 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7760 pipe_config->gmch_pfit.control,
7761 pipe_config->gmch_pfit.pgm_ratios,
7762 pipe_config->gmch_pfit.lvds_border_bits);
7763 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7764 pipe_config->pch_pfit.pos,
7765 pipe_config->pch_pfit.size);
42db64ef 7766 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7767}
7768
accfc0c5
DV		 7769static bool check_encoder_cloning(struct drm_crtc *crtc)
7770{
7771 int num_encoders = 0;
7772 bool uncloneable_encoders = false;
7773 struct intel_encoder *encoder;
7774
7775 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7776 base.head) {
7777 if (&encoder->new_crtc->base != crtc)
7778 continue;
7779
7780 num_encoders++;
7781 if (!encoder->cloneable)
7782 uncloneable_encoders = true;
7783 }
7784
7785 return !(num_encoders > 1 && uncloneable_encoders);
7786}
7787
b8cecdf5
DV		 7788static struct intel_crtc_config *
7789intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7790 struct drm_framebuffer *fb,
b8cecdf5 7791 struct drm_display_mode *mode)
ee7b9f93 7792{
7758a113 7793 struct drm_device *dev = crtc->dev;
7758a113
DV		 7794 struct drm_encoder_helper_funcs *encoder_funcs;
7795 struct intel_encoder *encoder;
b8cecdf5 7796 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7797 int plane_bpp, ret = -EINVAL;
7798 bool retry = true;
ee7b9f93 7799
accfc0c5
DV		 7800 if (!check_encoder_cloning(crtc)) {
7801 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7802 return ERR_PTR(-EINVAL);
7803 }
7804
b8cecdf5
DV		 7805 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7806 if (!pipe_config)
7758a113
DV		 7807 return ERR_PTR(-ENOMEM);
7808
b8cecdf5
DV		 7809 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7810 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7811 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7812 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7813
050f7aeb
DV		 7814 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7815 * plane pixel format and any sink constraints into account. Returns the
7816 * source plane bpp so that dithering can be selected on mismatches
7817 * after encoders and crtc also have had their say. */
7818 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7819 fb, pipe_config);
4e53c2e0
DV		 7820 if (plane_bpp < 0)
7821 goto fail;
7822
e29c22c0 7823encoder_retry:
ef1b460d 7824 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7825 pipe_config->port_clock = 0;
ef1b460d 7826 pipe_config->pixel_multiplier = 1;
ff9a6750 7827
7758a113
DV		 7828 /* Pass our mode to the connectors and the CRTC to give them a chance to
7829 * adjust it according to limitations or connector properties, and also
7830 * a chance to reject the mode entirely.
47f1c6c9 7831 */
7758a113
DV		 7832 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7833 base.head) {
47f1c6c9 7834
7758a113
DV		 7835 if (&encoder->new_crtc->base != crtc)
7836 continue;
7ae89233
DV		 7837
7838 if (encoder->compute_config) {
7839 if (!(encoder->compute_config(encoder, pipe_config))) {
7840 DRM_DEBUG_KMS("Encoder config failure\n");
7841 goto fail;
7842 }
7843
7844 continue;
7845 }
7846
7758a113 7847 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7848 if (!(encoder_funcs->mode_fixup(&encoder->base,
7849 &pipe_config->requested_mode,
7850 &pipe_config->adjusted_mode))) {
7758a113
DV		 7851 DRM_DEBUG_KMS("Encoder fixup failed\n");
7852 goto fail;
7853 }
ee7b9f93 7854 }
47f1c6c9 7855
ff9a6750
DV		 7856 /* Set default port clock if not overwritten by the encoder. Needs to be
7857 * done afterwards in case the encoder adjusts the mode. */
7858 if (!pipe_config->port_clock)
7859 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7860
a43f6e0f 7861 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7862 if (ret < 0) {
7758a113
DV		 7863 DRM_DEBUG_KMS("CRTC fixup failed\n");
7864 goto fail;
ee7b9f93 7865 }
e29c22c0
DV		 7866
7867 if (ret == RETRY) {
7868 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7869 ret = -EINVAL;
7870 goto fail;
7871 }
7872
7873 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7874 retry = false;
7875 goto encoder_retry;
7876 }
7877
4e53c2e0
DV		 7878 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7879 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7880 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7881
b8cecdf5 7882 return pipe_config;
7758a113 7883fail:
b8cecdf5 7884 kfree(pipe_config);
e29c22c0 7885 return ERR_PTR(ret);
ee7b9f93 7886}
47f1c6c9 7887
e2e1ed41
DV		 7888/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7889 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7890static void
7891intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7892 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7893{
7894 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7895 struct drm_device *dev = crtc->dev;
7896 struct intel_encoder *encoder;
7897 struct intel_connector *connector;
7898 struct drm_crtc *tmp_crtc;
79e53945 7899
e2e1ed41 7900 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7901
e2e1ed41
DV		 7902 /* Check which crtcs have changed outputs connected to them, these need
7903 * to be part of the prepare_pipes mask. We don't (yet) support global
7904 * modeset across multiple crtcs, so modeset_pipes will only have one
7905 * bit set at most. */
7906 list_for_each_entry(connector, &dev->mode_config.connector_list,
7907 base.head) {
7908 if (connector->base.encoder == &connector->new_encoder->base)
7909 continue;
79e53945 7910
e2e1ed41
DV		 7911 if (connector->base.encoder) {
7912 tmp_crtc = connector->base.encoder->crtc;
7913
7914 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7915 }
7916
7917 if (connector->new_encoder)
7918 *prepare_pipes |=
7919 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7920 }
7921
e2e1ed41
DV		 7922 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7923 base.head) {
7924 if (encoder->base.crtc == &encoder->new_crtc->base)
7925 continue;
7926
7927 if (encoder->base.crtc) {
7928 tmp_crtc = encoder->base.crtc;
7929
7930 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7931 }
7932
7933 if (encoder->new_crtc)
7934 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7935 }
7936
e2e1ed41
DV		 7937 /* Check for any pipes that will be fully disabled ... */
7938 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7939 base.head) {
7940 bool used = false;
22fd0fab 7941
e2e1ed41
DV		 7942 /* Don't try to disable disabled crtcs. */
7943 if (!intel_crtc->base.enabled)
7944 continue;
7e7d76c3 7945
e2e1ed41
DV		 7946 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7947 base.head) {
7948 if (encoder->new_crtc == intel_crtc)
7949 used = true;
7950 }
7951
7952 if (!used)
7953 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7954 }
7955
e2e1ed41
DV		 7956
7957 /* set_mode is also used to update properties on life display pipes. */
7958 intel_crtc = to_intel_crtc(crtc);
7959 if (crtc->enabled)
7960 *prepare_pipes |= 1 << intel_crtc->pipe;
7961
b6c5164d
DV		 7962 /*
7963 * For simplicity do a full modeset on any pipe where the output routing
7964 * changed. We could be more clever, but that would require us to be
7965 * more careful with calling the relevant encoder->mode_set functions.
7966 */
e2e1ed41
DV		 7967 if (*prepare_pipes)
7968 *modeset_pipes = *prepare_pipes;
7969
7970 /* ... and mask these out. */
7971 *modeset_pipes &= ~(*disable_pipes);
7972 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7973
7974 /*
7975 * HACK: We don't (yet) fully support global modesets. intel_set_config
7976 * obies this rule, but the modeset restore mode of
7977 * intel_modeset_setup_hw_state does not.
7978 */
7979 *modeset_pipes &= 1 << intel_crtc->pipe;
7980 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7981
7982 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7983 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7984}
79e53945 7985
ea9d758d 7986static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7987{
ea9d758d 7988 struct drm_encoder *encoder;
f6e5b160 7989 struct drm_device *dev = crtc->dev;
f6e5b160 7990
ea9d758d
DV		 7991 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7992 if (encoder->crtc == crtc)
7993 return true;
7994
7995 return false;
7996}
7997
7998static void
7999intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8000{
8001 struct intel_encoder *intel_encoder;
8002 struct intel_crtc *intel_crtc;
8003 struct drm_connector *connector;
8004
8005 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8006 base.head) {
8007 if (!intel_encoder->base.crtc)
8008 continue;
8009
8010 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8011
8012 if (prepare_pipes & (1 << intel_crtc->pipe))
8013 intel_encoder->connectors_active = false;
8014 }
8015
8016 intel_modeset_commit_output_state(dev);
8017
8018 /* Update computed state. */
8019 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8020 base.head) {
8021 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8022 }
8023
8024 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8025 if (!connector->encoder || !connector->encoder->crtc)
8026 continue;
8027
8028 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8029
8030 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8031 struct drm_property *dpms_property =
8032 dev->mode_config.dpms_property;
8033
ea9d758d 8034 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8035 drm_object_property_set_value(&connector->base,
68d34720
DV		 8036 dpms_property,
8037 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8038
8039 intel_encoder = to_intel_encoder(connector->encoder);
8040 intel_encoder->connectors_active = true;
8041 }
8042 }
8043
8044}
8045
25c5b266
DV		 8046#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8047 list_for_each_entry((intel_crtc), \
8048 &(dev)->mode_config.crtc_list, \
8049 base.head) \
0973f18f 8050 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8051
0e8ffe1b 8052static bool
2fa2fe9a
DV		 8053intel_pipe_config_compare(struct drm_device *dev,
8054 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8055 struct intel_crtc_config *pipe_config)
8056{
08a24034
DV		 8057#define PIPE_CONF_CHECK_I(name) \
8058 if (current_config->name != pipe_config->name) { \
8059 DRM_ERROR("mismatch in " #name " " \
8060 "(expected %i, found %i)\n", \
8061 current_config->name, \
8062 pipe_config->name); \
8063 return false; \
88adfff1
DV		 8064 }
8065
1bd1bd80
DV		 8066#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8067 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8068 DRM_ERROR("mismatch in " #name " " \
8069 "(expected %i, found %i)\n", \
8070 current_config->name & (mask), \
8071 pipe_config->name & (mask)); \
8072 return false; \
8073 }
8074
bb760063
DV		 8075#define PIPE_CONF_QUIRK(quirk) \
8076 ((current_config->quirks | pipe_config->quirks) & (quirk))
8077
eccb140b
DV		 8078 PIPE_CONF_CHECK_I(cpu_transcoder);
8079
08a24034
DV		 8080 PIPE_CONF_CHECK_I(has_pch_encoder);
8081 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8082 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8083 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8084 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8085 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8086 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8087
1bd1bd80
DV		 8088 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8089 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8090 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8091 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8092 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8093 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8094
8095 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8096 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8097 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8098 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8099 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8100 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8101
6c49f241
DV		 8102 if (!HAS_PCH_SPLIT(dev))
8103 PIPE_CONF_CHECK_I(pixel_multiplier);
8104
1bd1bd80
DV		 8105 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8106 DRM_MODE_FLAG_INTERLACE);
8107
bb760063
DV		 8108 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8109 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8110 DRM_MODE_FLAG_PHSYNC);
8111 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8112 DRM_MODE_FLAG_NHSYNC);
8113 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8114 DRM_MODE_FLAG_PVSYNC);
8115 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8116 DRM_MODE_FLAG_NVSYNC);
8117 }
045ac3b5 8118
1bd1bd80
DV		 8119 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8120 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8121
2fa2fe9a
DV		 8122 PIPE_CONF_CHECK_I(gmch_pfit.control);
8123 /* pfit ratios are autocomputed by the hw on gen4+ */
8124 if (INTEL_INFO(dev)->gen < 4)
8125 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8126 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8127 PIPE_CONF_CHECK_I(pch_pfit.pos);
8128 PIPE_CONF_CHECK_I(pch_pfit.size);
8129
42db64ef
PZ		 8130 PIPE_CONF_CHECK_I(ips_enabled);
8131
c0d43d62
DV		 8132 PIPE_CONF_CHECK_I(shared_dpll);
8133
08a24034 8134#undef PIPE_CONF_CHECK_I
1bd1bd80 8135#undef PIPE_CONF_CHECK_FLAGS
bb760063 8136#undef PIPE_CONF_QUIRK
627eb5a3 8137
0e8ffe1b
DV		 8138 return true;
8139}
8140
91d1b4bd
DV		 8141static void
8142check_connector_state(struct drm_device *dev)
8af6cf88 8143{
8af6cf88
DV		 8144 struct intel_connector *connector;
8145
8146 list_for_each_entry(connector, &dev->mode_config.connector_list,
8147 base.head) {
8148 /* This also checks the encoder/connector hw state with the
8149 * ->get_hw_state callbacks. */
8150 intel_connector_check_state(connector);
8151
8152 WARN(&connector->new_encoder->base != connector->base.encoder,
8153 "connector's staged encoder doesn't match current encoder\n");
8154 }
91d1b4bd
DV		 8155}
8156
8157static void
8158check_encoder_state(struct drm_device *dev)
8159{
8160 struct intel_encoder *encoder;
8161 struct intel_connector *connector;
8af6cf88
DV		 8162
8163 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8164 base.head) {
8165 bool enabled = false;
8166 bool active = false;
8167 enum pipe pipe, tracked_pipe;
8168
8169 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8170 encoder->base.base.id,
8171 drm_get_encoder_name(&encoder->base));
8172
8173 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8174 "encoder's stage crtc doesn't match current crtc\n");
8175 WARN(encoder->connectors_active && !encoder->base.crtc,
8176 "encoder's active_connectors set, but no crtc\n");
8177
8178 list_for_each_entry(connector, &dev->mode_config.connector_list,
8179 base.head) {
8180 if (connector->base.encoder != &encoder->base)
8181 continue;
8182 enabled = true;
8183 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8184 active = true;
8185 }
8186 WARN(!!encoder->base.crtc != enabled,
8187 "encoder's enabled state mismatch "
8188 "(expected %i, found %i)\n",
8189 !!encoder->base.crtc, enabled);
8190 WARN(active && !encoder->base.crtc,
8191 "active encoder with no crtc\n");
8192
8193 WARN(encoder->connectors_active != active,
8194 "encoder's computed active state doesn't match tracked active state "
8195 "(expected %i, found %i)\n", active, encoder->connectors_active);
8196
8197 active = encoder->get_hw_state(encoder, &pipe);
8198 WARN(active != encoder->connectors_active,
8199 "encoder's hw state doesn't match sw tracking "
8200 "(expected %i, found %i)\n",
8201 encoder->connectors_active, active);
8202
8203 if (!encoder->base.crtc)
8204 continue;
8205
8206 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8207 WARN(active && pipe != tracked_pipe,
8208 "active encoder's pipe doesn't match"
8209 "(expected %i, found %i)\n",
8210 tracked_pipe, pipe);
8211
8212 }
91d1b4bd
DV		 8213}
8214
8215static void
8216check_crtc_state(struct drm_device *dev)
8217{
8218 drm_i915_private_t *dev_priv = dev->dev_private;
8219 struct intel_crtc *crtc;
8220 struct intel_encoder *encoder;
8221 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8222
8223 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8224 base.head) {
8225 bool enabled = false;
8226 bool active = false;
8227
045ac3b5
JB		 8228 memset(&pipe_config, 0, sizeof(pipe_config));
8229
8af6cf88
DV		 8230 DRM_DEBUG_KMS("[CRTC:%d]\n",
8231 crtc->base.base.id);
8232
8233 WARN(crtc->active && !crtc->base.enabled,
8234 "active crtc, but not enabled in sw tracking\n");
8235
8236 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8237 base.head) {
8238 if (encoder->base.crtc != &crtc->base)
8239 continue;
8240 enabled = true;
8241 if (encoder->connectors_active)
8242 active = true;
8243 }
6c49f241 8244
8af6cf88
DV		 8245 WARN(active != crtc->active,
8246 "crtc's computed active state doesn't match tracked active state "
8247 "(expected %i, found %i)\n", active, crtc->active);
8248 WARN(enabled != crtc->base.enabled,
8249 "crtc's computed enabled state doesn't match tracked enabled state "
8250 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8251
0e8ffe1b
DV		 8252 active = dev_priv->display.get_pipe_config(crtc,
8253 &pipe_config);
6c49f241
DV		 8254 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8255 base.head) {
8256 if (encoder->base.crtc != &crtc->base)
8257 continue;
8258 if (encoder->get_config)
8259 encoder->get_config(encoder, &pipe_config);
8260 }
8261
0e8ffe1b
DV		 8262 WARN(crtc->active != active,
8263 "crtc active state doesn't match with hw state "
8264 "(expected %i, found %i)\n", crtc->active, active);
8265
c0b03411
DV		 8266 if (active &&
8267 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8268 WARN(1, "pipe state doesn't match!\n");
8269 intel_dump_pipe_config(crtc, &pipe_config,
8270 "[hw state]");
8271 intel_dump_pipe_config(crtc, &crtc->config,
8272 "[sw state]");
8273 }
8af6cf88 8274 }
91d1b4bd
DV		 8275}
8276
8277static void
8278check_shared_dpll_state(struct drm_device *dev)
8279{
8280 drm_i915_private_t *dev_priv = dev->dev_private;
8281 struct intel_crtc *crtc;
8282 struct intel_dpll_hw_state dpll_hw_state;
8283 int i;
5358901f
DV		 8284
8285 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8286 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8287 int enabled_crtcs = 0, active_crtcs = 0;
8288 bool active;
8289
8290 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8291
8292 DRM_DEBUG_KMS("%s\n", pll->name);
8293
8294 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8295
8296 WARN(pll->active > pll->refcount,
8297 "more active pll users than references: %i vs %i\n",
8298 pll->active, pll->refcount);
8299 WARN(pll->active && !pll->on,
8300 "pll in active use but not on in sw tracking\n");
8301 WARN(pll->on != active,
8302 "pll on state mismatch (expected %i, found %i)\n",
8303 pll->on, active);
8304
8305 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8306 base.head) {
8307 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8308 enabled_crtcs++;
8309 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8310 active_crtcs++;
8311 }
8312 WARN(pll->active != active_crtcs,
8313 "pll active crtcs mismatch (expected %i, found %i)\n",
8314 pll->active, active_crtcs);
8315 WARN(pll->refcount != enabled_crtcs,
8316 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8317 pll->refcount, enabled_crtcs);
8318 }
8af6cf88
DV		 8319}
8320
91d1b4bd
DV		 8321void
8322intel_modeset_check_state(struct drm_device *dev)
8323{
8324 check_connector_state(dev);
8325 check_encoder_state(dev);
8326 check_crtc_state(dev);
8327 check_shared_dpll_state(dev);
8328}
8329
f30da187
DV		 8330static int __intel_set_mode(struct drm_crtc *crtc,
8331 struct drm_display_mode *mode,
8332 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8333{
8334 struct drm_device *dev = crtc->dev;
dbf2b54e 8335 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8336 struct drm_display_mode *saved_mode, *saved_hwmode;
8337 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8338 struct intel_crtc *intel_crtc;
8339 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8340 int ret = 0;
a6778b3c 8341
3ac18232 8342 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8343 if (!saved_mode)
8344 return -ENOMEM;
3ac18232 8345 saved_hwmode = saved_mode + 1;
a6778b3c 8346
e2e1ed41 8347 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8348 &prepare_pipes, &disable_pipes);
8349
3ac18232
TG		 8350 *saved_hwmode = crtc->hwmode;
8351 *saved_mode = crtc->mode;
a6778b3c 8352
25c5b266
DV		 8353 /* Hack: Because we don't (yet) support global modeset on multiple
8354 * crtcs, we don't keep track of the new mode for more than one crtc.
8355 * Hence simply check whether any bit is set in modeset_pipes in all the
8356 * pieces of code that are not yet converted to deal with mutliple crtcs
8357 * changing their mode at the same time. */
25c5b266 8358 if (modeset_pipes) {
4e53c2e0 8359 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8360 if (IS_ERR(pipe_config)) {
8361 ret = PTR_ERR(pipe_config);
8362 pipe_config = NULL;
8363
3ac18232 8364 goto out;
25c5b266 8365 }
c0b03411
DV		 8366 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8367 "[modeset]");
25c5b266 8368 }
a6778b3c 8369
460da916
DV		 8370 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8371 intel_crtc_disable(&intel_crtc->base);
8372
ea9d758d
DV		 8373 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8374 if (intel_crtc->base.enabled)
8375 dev_priv->display.crtc_disable(&intel_crtc->base);
8376 }
a6778b3c 8377
6c4c86f5
DV		 8378 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8379 * to set it here already despite that we pass it down the callchain.
f6e5b160 8380 */
b8cecdf5 8381 if (modeset_pipes) {
25c5b266 8382 crtc->mode = *mode;
b8cecdf5
DV		 8383 /* mode_set/enable/disable functions rely on a correct pipe
8384 * config. */
8385 to_intel_crtc(crtc)->config = *pipe_config;
8386 }
7758a113 8387
ea9d758d
DV		 8388 /* Only after disabling all output pipelines that will be changed can we
8389 * update the the output configuration. */
8390 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8391
47fab737
DV		 8392 if (dev_priv->display.modeset_global_resources)
8393 dev_priv->display.modeset_global_resources(dev);
8394
a6778b3c
DV		 8395 /* Set up the DPLL and any encoders state that needs to adjust or depend
8396 * on the DPLL.
f6e5b160 8397 */
25c5b266 8398 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8399 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8400 x, y, fb);
8401 if (ret)
8402 goto done;
a6778b3c
DV		 8403 }
8404
8405 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8406 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8407 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8408
25c5b266
DV		 8409 if (modeset_pipes) {
8410 /* Store real post-adjustment hardware mode. */
b8cecdf5 8411 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8412
25c5b266
DV		 8413 /* Calculate and store various constants which
8414 * are later needed by vblank and swap-completion
8415 * timestamping. They are derived from true hwmode.
8416 */
8417 drm_calc_timestamping_constants(crtc);
8418 }
a6778b3c
DV		 8419
8420 /* FIXME: add subpixel order */
8421done:
c0c36b94 8422 if (ret && crtc->enabled) {
3ac18232
TG		 8423 crtc->hwmode = *saved_hwmode;
8424 crtc->mode = *saved_mode;
a6778b3c
DV		 8425 }
8426
3ac18232 8427out:
b8cecdf5 8428 kfree(pipe_config);
3ac18232 8429 kfree(saved_mode);
a6778b3c 8430 return ret;
f6e5b160
CW		 8431}
8432
f30da187
DV		 8433int intel_set_mode(struct drm_crtc *crtc,
8434 struct drm_display_mode *mode,
8435 int x, int y, struct drm_framebuffer *fb)
8436{
8437 int ret;
8438
8439 ret = __intel_set_mode(crtc, mode, x, y, fb);
8440
8441 if (ret == 0)
8442 intel_modeset_check_state(crtc->dev);
8443
8444 return ret;
8445}
8446
c0c36b94
CW		 8447void intel_crtc_restore_mode(struct drm_crtc *crtc)
8448{
8449 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8450}
8451
25c5b266
DV		 8452#undef for_each_intel_crtc_masked
8453
d9e55608
DV		 8454static void intel_set_config_free(struct intel_set_config *config)
8455{
8456 if (!config)
8457 return;
8458
1aa4b628
DV		 8459 kfree(config->save_connector_encoders);
8460 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8461 kfree(config);
8462}
8463
85f9eb71
DV		 8464static int intel_set_config_save_state(struct drm_device *dev,
8465 struct intel_set_config *config)
8466{
85f9eb71
DV		 8467 struct drm_encoder *encoder;
8468 struct drm_connector *connector;
8469 int count;
8470
1aa4b628
DV		 8471 config->save_encoder_crtcs =
8472 kcalloc(dev->mode_config.num_encoder,
8473 sizeof(struct drm_crtc *), GFP_KERNEL);
8474 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8475 return -ENOMEM;
8476
1aa4b628
DV		 8477 config->save_connector_encoders =
8478 kcalloc(dev->mode_config.num_connector,
8479 sizeof(struct drm_encoder *), GFP_KERNEL);
8480 if (!config->save_connector_encoders)
85f9eb71
DV		 8481 return -ENOMEM;
8482
8483 /* Copy data. Note that driver private data is not affected.
8484 * Should anything bad happen only the expected state is
8485 * restored, not the drivers personal bookkeeping.
8486 */
85f9eb71
DV		 8487 count = 0;
8488 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8489 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8490 }
8491
8492 count = 0;
8493 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8494 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8495 }
8496
8497 return 0;
8498}
8499
8500static void intel_set_config_restore_state(struct drm_device *dev,
8501 struct intel_set_config *config)
8502{
9a935856
DV		 8503 struct intel_encoder *encoder;
8504 struct intel_connector *connector;
85f9eb71
DV		 8505 int count;
8506
85f9eb71 8507 count = 0;
9a935856
DV		 8508 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8509 encoder->new_crtc =
8510 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8511 }
8512
8513 count = 0;
9a935856
DV		 8514 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8515 connector->new_encoder =
8516 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8517 }
8518}
8519
5e2b584e
DV		 8520static void
8521intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8522 struct intel_set_config *config)
8523{
8524
8525 /* We should be able to check here if the fb has the same properties
8526 * and then just flip_or_move it */
8527 if (set->crtc->fb != set->fb) {
8528 /* If we have no fb then treat it as a full mode set */
8529 if (set->crtc->fb == NULL) {
8530 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8531 config->mode_changed = true;
8532 } else if (set->fb == NULL) {
8533 config->mode_changed = true;
72f4901e
DV		 8534 } else if (set->fb->pixel_format !=
8535 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8536 config->mode_changed = true;
8537 } else
8538 config->fb_changed = true;
8539 }
8540
835c5873 8541 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8542 config->fb_changed = true;
8543
8544 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8545 DRM_DEBUG_KMS("modes are different, full mode set\n");
8546 drm_mode_debug_printmodeline(&set->crtc->mode);
8547 drm_mode_debug_printmodeline(set->mode);
8548 config->mode_changed = true;
8549 }
8550}
8551
2e431051 8552static int
9a935856
DV		 8553intel_modeset_stage_output_state(struct drm_device *dev,
8554 struct drm_mode_set *set,
8555 struct intel_set_config *config)
50f56119 8556{
85f9eb71 8557 struct drm_crtc *new_crtc;
9a935856
DV		 8558 struct intel_connector *connector;
8559 struct intel_encoder *encoder;
2e431051 8560 int count, ro;
50f56119 8561
9abdda74 8562 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8563 * of connectors. For paranoia, double-check this. */
8564 WARN_ON(!set->fb && (set->num_connectors != 0));
8565 WARN_ON(set->fb && (set->num_connectors == 0));
8566
50f56119 8567 count = 0;
9a935856
DV		 8568 list_for_each_entry(connector, &dev->mode_config.connector_list,
8569 base.head) {
8570 /* Otherwise traverse passed in connector list and get encoders
8571 * for them. */
50f56119 8572 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8573 if (set->connectors[ro] == &connector->base) {
8574 connector->new_encoder = connector->encoder;
50f56119
DV		 8575 break;
8576 }
8577 }
8578
9a935856
DV		 8579 /* If we disable the crtc, disable all its connectors. Also, if
8580 * the connector is on the changing crtc but not on the new
8581 * connector list, disable it. */
8582 if ((!set->fb || ro == set->num_connectors) &&
8583 connector->base.encoder &&
8584 connector->base.encoder->crtc == set->crtc) {
8585 connector->new_encoder = NULL;
8586
8587 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8588 connector->base.base.id,
8589 drm_get_connector_name(&connector->base));
8590 }
8591
8592
8593 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8594 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8595 config->mode_changed = true;
50f56119
DV		 8596 }
8597 }
9a935856 8598 /* connector->new_encoder is now updated for all connectors. */
50f56119 8599
9a935856 8600 /* Update crtc of enabled connectors. */
50f56119 8601 count = 0;
9a935856
DV		 8602 list_for_each_entry(connector, &dev->mode_config.connector_list,
8603 base.head) {
8604 if (!connector->new_encoder)
50f56119
DV		 8605 continue;
8606
9a935856 8607 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8608
8609 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8610 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8611 new_crtc = set->crtc;
8612 }
8613
8614 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8615 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8616 new_crtc)) {
5e2b584e 8617 return -EINVAL;
50f56119 8618 }
9a935856
DV		 8619 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8620
8621 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8622 connector->base.base.id,
8623 drm_get_connector_name(&connector->base),
8624 new_crtc->base.id);
8625 }
8626
8627 /* Check for any encoders that needs to be disabled. */
8628 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8629 base.head) {
8630 list_for_each_entry(connector,
8631 &dev->mode_config.connector_list,
8632 base.head) {
8633 if (connector->new_encoder == encoder) {
8634 WARN_ON(!connector->new_encoder->new_crtc);
8635
8636 goto next_encoder;
8637 }
8638 }
8639 encoder->new_crtc = NULL;
8640next_encoder:
8641 /* Only now check for crtc changes so we don't miss encoders
8642 * that will be disabled. */
8643 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8644 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8645 config->mode_changed = true;
50f56119
DV		 8646 }
8647 }
9a935856 8648 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8649
2e431051
DV		 8650 return 0;
8651}
8652
8653static int intel_crtc_set_config(struct drm_mode_set *set)
8654{
8655 struct drm_device *dev;
2e431051
DV		 8656 struct drm_mode_set save_set;
8657 struct intel_set_config *config;
8658 int ret;
2e431051 8659
8d3e375e
DV		 8660 BUG_ON(!set);
8661 BUG_ON(!set->crtc);
8662 BUG_ON(!set->crtc->helper_private);
2e431051 8663
7e53f3a4
DV		 8664 /* Enforce sane interface api - has been abused by the fb helper. */
8665 BUG_ON(!set->mode && set->fb);
8666 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8667
2e431051
DV		 8668 if (set->fb) {
8669 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8670 set->crtc->base.id, set->fb->base.id,
8671 (int)set->num_connectors, set->x, set->y);
8672 } else {
8673 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8674 }
8675
8676 dev = set->crtc->dev;
8677
8678 ret = -ENOMEM;
8679 config = kzalloc(sizeof(*config), GFP_KERNEL);
8680 if (!config)
8681 goto out_config;
8682
8683 ret = intel_set_config_save_state(dev, config);
8684 if (ret)
8685 goto out_config;
8686
8687 save_set.crtc = set->crtc;
8688 save_set.mode = &set->crtc->mode;
8689 save_set.x = set->crtc->x;
8690 save_set.y = set->crtc->y;
8691 save_set.fb = set->crtc->fb;
8692
8693 /* Compute whether we need a full modeset, only an fb base update or no
8694 * change at all. In the future we might also check whether only the
8695 * mode changed, e.g. for LVDS where we only change the panel fitter in
8696 * such cases. */
8697 intel_set_config_compute_mode_changes(set, config);
8698
9a935856 8699 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8700 if (ret)
8701 goto fail;
8702
5e2b584e 8703 if (config->mode_changed) {
c0c36b94
CW		 8704 ret = intel_set_mode(set->crtc, set->mode,
8705 set->x, set->y, set->fb);
8706 if (ret) {
8707 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8708 set->crtc->base.id, ret);
87f1faa6
DV		 8709 goto fail;
8710 }
5e2b584e 8711 } else if (config->fb_changed) {
4878cae2
VS		 8712 intel_crtc_wait_for_pending_flips(set->crtc);
8713
4f660f49 8714 ret = intel_pipe_set_base(set->crtc,
94352cf9 8715 set->x, set->y, set->fb);
50f56119
DV		 8716 }
8717
d9e55608
DV		 8718 intel_set_config_free(config);
8719
50f56119
DV		 8720 return 0;
8721
8722fail:
85f9eb71 8723 intel_set_config_restore_state(dev, config);
50f56119
DV		 8724
8725 /* Try to restore the config */
5e2b584e 8726 if (config->mode_changed &&
c0c36b94
CW		 8727 intel_set_mode(save_set.crtc, save_set.mode,
8728 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8729 DRM_ERROR("failed to restore config after modeset failure\n");
8730
d9e55608
DV		 8731out_config:
8732 intel_set_config_free(config);
50f56119
DV		 8733 return ret;
8734}
f6e5b160
CW		 8735
8736static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8737 .cursor_set = intel_crtc_cursor_set,
8738 .cursor_move = intel_crtc_cursor_move,
8739 .gamma_set = intel_crtc_gamma_set,
50f56119 8740 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8741 .destroy = intel_crtc_destroy,
8742 .page_flip = intel_crtc_page_flip,
8743};
8744
79f689aa
PZ		 8745static void intel_cpu_pll_init(struct drm_device *dev)
8746{
affa9354 8747 if (HAS_DDI(dev))
79f689aa
PZ		 8748 intel_ddi_pll_init(dev);
8749}
8750
5358901f
DV		 8751static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8752 struct intel_shared_dpll *pll,
8753 struct intel_dpll_hw_state *hw_state)
8754{
8755 uint32_t val;
8756
8757 val = I915_READ(PCH_DPLL(pll->id));
8758
8759 return val & DPLL_VCO_ENABLE;
8760}
8761
e7b903d2
DV		 8762static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8763 struct intel_shared_dpll *pll)
8764{
8765 uint32_t reg, val;
8766
8767 /* PCH refclock must be enabled first */
8768 assert_pch_refclk_enabled(dev_priv);
8769
8770 reg = PCH_DPLL(pll->id);
8771 val = I915_READ(reg);
8772 val |= DPLL_VCO_ENABLE;
8773 I915_WRITE(reg, val);
8774 POSTING_READ(reg);
8775 udelay(200);
8776}
8777
8778static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8779 struct intel_shared_dpll *pll)
8780{
8781 struct drm_device *dev = dev_priv->dev;
8782 struct intel_crtc *crtc;
8783 uint32_t reg, val;
8784
8785 /* Make sure no transcoder isn't still depending on us. */
8786 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8787 if (intel_crtc_to_shared_dpll(crtc) == pll)
8788 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8789 }
8790
8791 reg = PCH_DPLL(pll->id);
8792 val = I915_READ(reg);
8793 val &= ~DPLL_VCO_ENABLE;
8794 I915_WRITE(reg, val);
8795 POSTING_READ(reg);
8796 udelay(200);
8797}
8798
46edb027
DV		 8799static char *ibx_pch_dpll_names[] = {
8800 "PCH DPLL A",
8801 "PCH DPLL B",
8802};
8803
7c74ade1 8804static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8805{
e7b903d2 8806 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8807 int i;
8808
7c74ade1 8809 dev_priv->num_shared_dpll = 2;
ee7b9f93 8810
e72f9fbf 8811 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8812 dev_priv->shared_dplls[i].id = i;
8813 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
e7b903d2
DV		 8814 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8815 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8816 dev_priv->shared_dplls[i].get_hw_state =
8817 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8818 }
8819}
8820
7c74ade1
DV		 8821static void intel_shared_dpll_init(struct drm_device *dev)
8822{
e7b903d2 8823 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8824
8825 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8826 ibx_pch_dpll_init(dev);
8827 else
8828 dev_priv->num_shared_dpll = 0;
8829
8830 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8831 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8832 dev_priv->num_shared_dpll);
8833}
8834
b358d0a6 8835static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8836{
22fd0fab 8837 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8838 struct intel_crtc *intel_crtc;
8839 int i;
8840
8841 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8842 if (intel_crtc == NULL)
8843 return;
8844
8845 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8846
8847 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8848 for (i = 0; i < 256; i++) {
8849 intel_crtc->lut_r[i] = i;
8850 intel_crtc->lut_g[i] = i;
8851 intel_crtc->lut_b[i] = i;
8852 }
8853
80824003
JB		 8854 /* Swap pipes & planes for FBC on pre-965 */
8855 intel_crtc->pipe = pipe;
8856 intel_crtc->plane = pipe;
e2e767ab 8857 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8858 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8859 intel_crtc->plane = !pipe;
80824003
JB		 8860 }
8861
22fd0fab
JB		 8862 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8863 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8864 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8865 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8866
79e53945 8867 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8868}
8869
08d7b3d1 8870int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8871 struct drm_file *file)
08d7b3d1 8872{
08d7b3d1 8873 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8874 struct drm_mode_object *drmmode_obj;
8875 struct intel_crtc *crtc;
08d7b3d1 8876
1cff8f6b
DV		 8877 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8878 return -ENODEV;
08d7b3d1 8879
c05422d5
DV		 8880 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8881 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8882
c05422d5 8883 if (!drmmode_obj) {
08d7b3d1
CW		 8884 DRM_ERROR("no such CRTC id\n");
8885 return -EINVAL;
8886 }
8887
c05422d5
DV		 8888 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8889 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8890
c05422d5 8891 return 0;
08d7b3d1
CW		 8892}
8893
66a9278e 8894static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8895{
66a9278e
DV		 8896 struct drm_device *dev = encoder->base.dev;
8897 struct intel_encoder *source_encoder;
79e53945 8898 int index_mask = 0;
79e53945
JB		 8899 int entry = 0;
8900
66a9278e
DV		 8901 list_for_each_entry(source_encoder,
8902 &dev->mode_config.encoder_list, base.head) {
8903
8904 if (encoder == source_encoder)
79e53945 8905 index_mask |= (1 << entry);
66a9278e
DV		 8906
8907 /* Intel hw has only one MUX where enocoders could be cloned. */
8908 if (encoder->cloneable && source_encoder->cloneable)
8909 index_mask |= (1 << entry);
8910
79e53945
JB		 8911 entry++;
8912 }
4ef69c7a 8913
79e53945
JB		 8914 return index_mask;
8915}
8916
4d302442
CW		 8917static bool has_edp_a(struct drm_device *dev)
8918{
8919 struct drm_i915_private *dev_priv = dev->dev_private;
8920
8921 if (!IS_MOBILE(dev))
8922 return false;
8923
8924 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8925 return false;
8926
8927 if (IS_GEN5(dev) &&
8928 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8929 return false;
8930
8931 return true;
8932}
8933
79e53945
JB		 8934static void intel_setup_outputs(struct drm_device *dev)
8935{
725e30ad 8936 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8937 struct intel_encoder *encoder;
cb0953d7 8938 bool dpd_is_edp = false;
f3cfcba6 8939 bool has_lvds;
79e53945 8940
f3cfcba6 8941 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8942 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8943 /* disable the panel fitter on everything but LVDS */
8944 I915_WRITE(PFIT_CONTROL, 0);
8945 }
79e53945 8946
c40c0f5b 8947 if (!IS_ULT(dev))
79935fca 8948 intel_crt_init(dev);
cb0953d7 8949
affa9354 8950 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8951 int found;
8952
8953 /* Haswell uses DDI functions to detect digital outputs */
8954 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8955 /* DDI A only supports eDP */
8956 if (found)
8957 intel_ddi_init(dev, PORT_A);
8958
8959 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8960 * register */
8961 found = I915_READ(SFUSE_STRAP);
8962
8963 if (found & SFUSE_STRAP_DDIB_DETECTED)
8964 intel_ddi_init(dev, PORT_B);
8965 if (found & SFUSE_STRAP_DDIC_DETECTED)
8966 intel_ddi_init(dev, PORT_C);
8967 if (found & SFUSE_STRAP_DDID_DETECTED)
8968 intel_ddi_init(dev, PORT_D);
8969 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8970 int found;
270b3042
DV		 8971 dpd_is_edp = intel_dpd_is_edp(dev);
8972
8973 if (has_edp_a(dev))
8974 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8975
dc0fa718 8976 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8977 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8978 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8979 if (!found)
e2debe91 8980 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8981 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8982 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8983 }
8984
dc0fa718 8985 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8986 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8987
dc0fa718 8988 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8989 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8990
5eb08b69 8991 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8992 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8993
270b3042 8994 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8995 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8996 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8997 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8998 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8999 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9000
dc0fa718 9001 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9002 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9003 PORT_B);
67cfc203
VS		 9004 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9005 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9006 }
103a196f 9007 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9008 bool found = false;
7d57382e 9009
e2debe91 9010 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9011 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9012 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9013 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9014 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9015 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9016 }
27185ae1 9017
e7281eab 9018 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9019 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9020 }
13520b05
KH		 9021
9022 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9023
e2debe91 9024 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9025 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9026 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9027 }
27185ae1 9028
e2debe91 9029 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9030
b01f2c3a
JB		 9031 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9032 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9033 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9034 }
e7281eab 9035 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9036 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9037 }
27185ae1 9038
b01f2c3a 9039 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9040 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9041 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9042 } else if (IS_GEN2(dev))
79e53945
JB		 9043 intel_dvo_init(dev);
9044
103a196f 9045 if (SUPPORTS_TV(dev))
79e53945
JB		 9046 intel_tv_init(dev);
9047
4ef69c7a
CW		 9048 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9049 encoder->base.possible_crtcs = encoder->crtc_mask;
9050 encoder->base.possible_clones =
66a9278e 9051 intel_encoder_clones(encoder);
79e53945 9052 }
47356eb6 9053
dde86e2d 9054 intel_init_pch_refclk(dev);
270b3042
DV		 9055
9056 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9057}
9058
9059static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9060{
9061 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9062
9063 drm_framebuffer_cleanup(fb);
05394f39 9064 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9065
9066 kfree(intel_fb);
9067}
9068
9069static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9070 struct drm_file *file,
79e53945
JB		 9071 unsigned int *handle)
9072{
9073 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9074 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9075
05394f39 9076 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9077}
9078
9079static const struct drm_framebuffer_funcs intel_fb_funcs = {
9080 .destroy = intel_user_framebuffer_destroy,
9081 .create_handle = intel_user_framebuffer_create_handle,
9082};
9083
38651674
DA		 9084int intel_framebuffer_init(struct drm_device *dev,
9085 struct intel_framebuffer *intel_fb,
308e5bcb 9086 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9087 struct drm_i915_gem_object *obj)
79e53945 9088{
79e53945
JB		 9089 int ret;
9090
c16ed4be
CW		 9091 if (obj->tiling_mode == I915_TILING_Y) {
9092 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9093 return -EINVAL;
c16ed4be 9094 }
57cd6508 9095
c16ed4be
CW		 9096 if (mode_cmd->pitches[0] & 63) {
9097 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9098 mode_cmd->pitches[0]);
57cd6508 9099 return -EINVAL;
c16ed4be 9100 }
57cd6508 9101
5d7bd705 9102 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 9103 if (mode_cmd->pitches[0] > 32768) {
9104 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9105 mode_cmd->pitches[0]);
5d7bd705 9106 return -EINVAL;
c16ed4be 9107 }
5d7bd705
VS		 9108
9109 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9110 mode_cmd->pitches[0] != obj->stride) {
9111 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9112 mode_cmd->pitches[0], obj->stride);
5d7bd705 9113 return -EINVAL;
c16ed4be 9114 }
5d7bd705 9115
57779d06 9116 /* Reject formats not supported by any plane early. */
308e5bcb 9117 switch (mode_cmd->pixel_format) {
57779d06 9118 case DRM_FORMAT_C8:
04b3924d
VS		 9119 case DRM_FORMAT_RGB565:
9120 case DRM_FORMAT_XRGB8888:
9121 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9122 break;
9123 case DRM_FORMAT_XRGB1555:
9124 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9125 if (INTEL_INFO(dev)->gen > 3) {
9126 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9127 return -EINVAL;
c16ed4be 9128 }
57779d06
VS		 9129 break;
9130 case DRM_FORMAT_XBGR8888:
9131 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9132 case DRM_FORMAT_XRGB2101010:
9133 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9134 case DRM_FORMAT_XBGR2101010:
9135 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9136 if (INTEL_INFO(dev)->gen < 4) {
9137 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9138 return -EINVAL;
c16ed4be 9139 }
b5626747 9140 break;
04b3924d
VS		 9141 case DRM_FORMAT_YUYV:
9142 case DRM_FORMAT_UYVY:
9143 case DRM_FORMAT_YVYU:
9144 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9145 if (INTEL_INFO(dev)->gen < 5) {
9146 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9147 return -EINVAL;
c16ed4be 9148 }
57cd6508
CW		 9149 break;
9150 default:
c16ed4be 9151 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9152 return -EINVAL;
9153 }
9154
90f9a336
VS		 9155 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9156 if (mode_cmd->offsets[0] != 0)
9157 return -EINVAL;
9158
c7d73f6a
DV		 9159 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9160 intel_fb->obj = obj;
9161
79e53945
JB		 9162 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9163 if (ret) {
9164 DRM_ERROR("framebuffer init failed %d\n", ret);
9165 return ret;
9166 }
9167
79e53945
JB		 9168 return 0;
9169}
9170
79e53945
JB		 9171static struct drm_framebuffer *
9172intel_user_framebuffer_create(struct drm_device *dev,
9173 struct drm_file *filp,
308e5bcb 9174 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9175{
05394f39 9176 struct drm_i915_gem_object *obj;
79e53945 9177
308e5bcb
JB		 9178 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9179 mode_cmd->handles[0]));
c8725226 9180 if (&obj->base == NULL)
cce13ff7 9181 return ERR_PTR(-ENOENT);
79e53945 9182
d2dff872 9183 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9184}
9185
79e53945 9186static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9187 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9188 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9189};
9190
e70236a8
JB		 9191/* Set up chip specific display functions */
9192static void intel_init_display(struct drm_device *dev)
9193{
9194 struct drm_i915_private *dev_priv = dev->dev_private;
9195
ee9300bb
DV		 9196 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9197 dev_priv->display.find_dpll = g4x_find_best_dpll;
9198 else if (IS_VALLEYVIEW(dev))
9199 dev_priv->display.find_dpll = vlv_find_best_dpll;
9200 else if (IS_PINEVIEW(dev))
9201 dev_priv->display.find_dpll = pnv_find_best_dpll;
9202 else
9203 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9204
affa9354 9205 if (HAS_DDI(dev)) {
0e8ffe1b 9206 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9207 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9208 dev_priv->display.crtc_enable = haswell_crtc_enable;
9209 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9210 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9211 dev_priv->display.update_plane = ironlake_update_plane;
9212 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9213 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9214 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9215 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9216 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9217 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9218 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9219 } else if (IS_VALLEYVIEW(dev)) {
9220 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9221 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9222 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9223 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9224 dev_priv->display.off = i9xx_crtc_off;
9225 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9226 } else {
0e8ffe1b 9227 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9228 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9229 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9230 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9231 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9232 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9233 }
e70236a8 9234
e70236a8 9235 /* Returns the core display clock speed */
25eb05fc
JB		 9236 if (IS_VALLEYVIEW(dev))
9237 dev_priv->display.get_display_clock_speed =
9238 valleyview_get_display_clock_speed;
9239 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9240 dev_priv->display.get_display_clock_speed =
9241 i945_get_display_clock_speed;
9242 else if (IS_I915G(dev))
9243 dev_priv->display.get_display_clock_speed =
9244 i915_get_display_clock_speed;
f2b115e6 9245 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9246 dev_priv->display.get_display_clock_speed =
9247 i9xx_misc_get_display_clock_speed;
9248 else if (IS_I915GM(dev))
9249 dev_priv->display.get_display_clock_speed =
9250 i915gm_get_display_clock_speed;
9251 else if (IS_I865G(dev))
9252 dev_priv->display.get_display_clock_speed =
9253 i865_get_display_clock_speed;
f0f8a9ce 9254 else if (IS_I85X(dev))
e70236a8
JB		 9255 dev_priv->display.get_display_clock_speed =
9256 i855_get_display_clock_speed;
9257 else /* 852, 830 */
9258 dev_priv->display.get_display_clock_speed =
9259 i830_get_display_clock_speed;
9260
7f8a8569 9261 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9262 if (IS_GEN5(dev)) {
674cf967 9263 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9264 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9265 } else if (IS_GEN6(dev)) {
674cf967 9266 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9267 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9268 } else if (IS_IVYBRIDGE(dev)) {
9269 /* FIXME: detect B0+ stepping and use auto training */
9270 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9271 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9272 dev_priv->display.modeset_global_resources =
9273 ivb_modeset_global_resources;
c82e4d26
ED		 9274 } else if (IS_HASWELL(dev)) {
9275 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9276 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9277 dev_priv->display.modeset_global_resources =
9278 haswell_modeset_global_resources;
a0e63c22 9279 }
6067aaea 9280 } else if (IS_G4X(dev)) {
e0dac65e 9281 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9282 }
8c9f3aaf
JB		 9283
9284 /* Default just returns -ENODEV to indicate unsupported */
9285 dev_priv->display.queue_flip = intel_default_queue_flip;
9286
9287 switch (INTEL_INFO(dev)->gen) {
9288 case 2:
9289 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9290 break;
9291
9292 case 3:
9293 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9294 break;
9295
9296 case 4:
9297 case 5:
9298 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9299 break;
9300
9301 case 6:
9302 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9303 break;
7c9017e5
JB		 9304 case 7:
9305 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9306 break;
8c9f3aaf 9307 }
e70236a8
JB		 9308}
9309
b690e96c
JB		 9310/*
9311 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9312 * resume, or other times. This quirk makes sure that's the case for
9313 * affected systems.
9314 */
0206e353 9315static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9316{
9317 struct drm_i915_private *dev_priv = dev->dev_private;
9318
9319 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9320 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9321}
9322
435793df
KP		 9323/*
9324 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9325 */
9326static void quirk_ssc_force_disable(struct drm_device *dev)
9327{
9328 struct drm_i915_private *dev_priv = dev->dev_private;
9329 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9330 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9331}
9332
4dca20ef 9333/*
5a15ab5b
CE		 9334 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9335 * brightness value
4dca20ef
CE		 9336 */
9337static void quirk_invert_brightness(struct drm_device *dev)
9338{
9339 struct drm_i915_private *dev_priv = dev->dev_private;
9340 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9341 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9342}
9343
b690e96c
JB		 9344struct intel_quirk {
9345 int device;
9346 int subsystem_vendor;
9347 int subsystem_device;
9348 void (*hook)(struct drm_device *dev);
9349};
9350
5f85f176
EE		 9351/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9352struct intel_dmi_quirk {
9353 void (*hook)(struct drm_device *dev);
9354 const struct dmi_system_id (*dmi_id_list)[];
9355};
9356
9357static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9358{
9359 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9360 return 1;
9361}
9362
9363static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9364 {
9365 .dmi_id_list = &(const struct dmi_system_id[]) {
9366 {
9367 .callback = intel_dmi_reverse_brightness,
9368 .ident = "NCR Corporation",
9369 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9370 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9371 },
9372 },
9373 { } /* terminating entry */
9374 },
9375 .hook = quirk_invert_brightness,
9376 },
9377};
9378
c43b5634 9379static struct intel_quirk intel_quirks[] = {
b690e96c 9380 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9381 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9382
b690e96c
JB		 9383 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9384 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9385
b690e96c
JB		 9386 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9387 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9388
ccd0d36e 9389 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9390 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9391 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9392
9393 /* Lenovo U160 cannot use SSC on LVDS */
9394 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9395
9396 /* Sony Vaio Y cannot use SSC on LVDS */
9397 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9398
9399 /* Acer Aspire 5734Z must invert backlight brightness */
9400 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9401
9402 /* Acer/eMachines G725 */
9403 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9404
9405 /* Acer/eMachines e725 */
9406 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9407
9408 /* Acer/Packard Bell NCL20 */
9409 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9410
9411 /* Acer Aspire 4736Z */
9412 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9413};
9414
9415static void intel_init_quirks(struct drm_device *dev)
9416{
9417 struct pci_dev *d = dev->pdev;
9418 int i;
9419
9420 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9421 struct intel_quirk *q = &intel_quirks[i];
9422
9423 if (d->device == q->device &&
9424 (d->subsystem_vendor == q->subsystem_vendor ||
9425 q->subsystem_vendor == PCI_ANY_ID) &&
9426 (d->subsystem_device == q->subsystem_device ||
9427 q->subsystem_device == PCI_ANY_ID))
9428 q->hook(dev);
9429 }
5f85f176
EE		 9430 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9431 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9432 intel_dmi_quirks[i].hook(dev);
9433 }
b690e96c
JB		 9434}
9435
9cce37f4
JB		 9436/* Disable the VGA plane that we never use */
9437static void i915_disable_vga(struct drm_device *dev)
9438{
9439 struct drm_i915_private *dev_priv = dev->dev_private;
9440 u8 sr1;
766aa1c4 9441 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9442
9443 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9444 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9445 sr1 = inb(VGA_SR_DATA);
9446 outb(sr1 | 1<<5, VGA_SR_DATA);
9447 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9448 udelay(300);
9449
9450 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9451 POSTING_READ(vga_reg);
9452}
9453
f817586c
DV		 9454void intel_modeset_init_hw(struct drm_device *dev)
9455{
fa42e23c 9456 intel_init_power_well(dev);
0232e927 9457
a8f78b58
ED		 9458 intel_prepare_ddi(dev);
9459
f817586c
DV		 9460 intel_init_clock_gating(dev);
9461
79f5b2c7 9462 mutex_lock(&dev->struct_mutex);
8090c6b9 9463 intel_enable_gt_powersave(dev);
79f5b2c7 9464 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9465}
9466
7d708ee4
ID		 9467void intel_modeset_suspend_hw(struct drm_device *dev)
9468{
9469 intel_suspend_hw(dev);
9470}
9471
79e53945
JB		 9472void intel_modeset_init(struct drm_device *dev)
9473{
652c393a 9474 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9475 int i, j, ret;
79e53945
JB		 9476
9477 drm_mode_config_init(dev);
9478
9479 dev->mode_config.min_width = 0;
9480 dev->mode_config.min_height = 0;
9481
019d96cb
DA		 9482 dev->mode_config.preferred_depth = 24;
9483 dev->mode_config.prefer_shadow = 1;
9484
e6ecefaa 9485 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9486
b690e96c
JB		 9487 intel_init_quirks(dev);
9488
1fa61106
ED		 9489 intel_init_pm(dev);
9490
e3c74757
BW		 9491 if (INTEL_INFO(dev)->num_pipes == 0)
9492 return;
9493
e70236a8
JB		 9494 intel_init_display(dev);
9495
a6c45cf0
CW		 9496 if (IS_GEN2(dev)) {
9497 dev->mode_config.max_width = 2048;
9498 dev->mode_config.max_height = 2048;
9499 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9500 dev->mode_config.max_width = 4096;
9501 dev->mode_config.max_height = 4096;
79e53945 9502 } else {
a6c45cf0
CW		 9503 dev->mode_config.max_width = 8192;
9504 dev->mode_config.max_height = 8192;
79e53945 9505 }
5d4545ae 9506 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9507
28c97730 9508 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9509 INTEL_INFO(dev)->num_pipes,
9510 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9511
7eb552ae 9512 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9513 intel_crtc_init(dev, i);
7f1f3851
JB		 9514 for (j = 0; j < dev_priv->num_plane; j++) {
9515 ret = intel_plane_init(dev, i, j);
9516 if (ret)
06da8da2
VS		 9517 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9518 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9519 }
79e53945
JB		 9520 }
9521
79f689aa 9522 intel_cpu_pll_init(dev);
e72f9fbf 9523 intel_shared_dpll_init(dev);
ee7b9f93 9524
9cce37f4
JB		 9525 /* Just disable it once at startup */
9526 i915_disable_vga(dev);
79e53945 9527 intel_setup_outputs(dev);
11be49eb
CW		 9528
9529 /* Just in case the BIOS is doing something questionable. */
9530 intel_disable_fbc(dev);
2c7111db
CW		 9531}
9532
24929352
DV		 9533static void
9534intel_connector_break_all_links(struct intel_connector *connector)
9535{
9536 connector->base.dpms = DRM_MODE_DPMS_OFF;
9537 connector->base.encoder = NULL;
9538 connector->encoder->connectors_active = false;
9539 connector->encoder->base.crtc = NULL;
9540}
9541
7fad798e
DV		 9542static void intel_enable_pipe_a(struct drm_device *dev)
9543{
9544 struct intel_connector *connector;
9545 struct drm_connector *crt = NULL;
9546 struct intel_load_detect_pipe load_detect_temp;
9547
9548 /* We can't just switch on the pipe A, we need to set things up with a
9549 * proper mode and output configuration. As a gross hack, enable pipe A
9550 * by enabling the load detect pipe once. */
9551 list_for_each_entry(connector,
9552 &dev->mode_config.connector_list,
9553 base.head) {
9554 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9555 crt = &connector->base;
9556 break;
9557 }
9558 }
9559
9560 if (!crt)
9561 return;
9562
9563 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9564 intel_release_load_detect_pipe(crt, &load_detect_temp);
9565
652c393a 9566
7fad798e
DV		 9567}
9568
fa555837
DV		 9569static bool
9570intel_check_plane_mapping(struct intel_crtc *crtc)
9571{
7eb552ae
BW		 9572 struct drm_device *dev = crtc->base.dev;
9573 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9574 u32 reg, val;
9575
7eb552ae 9576 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9577 return true;
9578
9579 reg = DSPCNTR(!crtc->plane);
9580 val = I915_READ(reg);
9581
9582 if ((val & DISPLAY_PLANE_ENABLE) &&
9583 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9584 return false;
9585
9586 return true;
9587}
9588
24929352
DV		 9589static void intel_sanitize_crtc(struct intel_crtc *crtc)
9590{
9591 struct drm_device *dev = crtc->base.dev;
9592 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9593 u32 reg;
24929352 9594
24929352 9595 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9596 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9597 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9598
9599 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9600 * disable the crtc (and hence change the state) if it is wrong. Note
9601 * that gen4+ has a fixed plane -> pipe mapping. */
9602 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9603 struct intel_connector *connector;
9604 bool plane;
9605
24929352
DV		 9606 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9607 crtc->base.base.id);
9608
9609 /* Pipe has the wrong plane attached and the plane is active.
9610 * Temporarily change the plane mapping and disable everything
9611 * ... */
9612 plane = crtc->plane;
9613 crtc->plane = !plane;
9614 dev_priv->display.crtc_disable(&crtc->base);
9615 crtc->plane = plane;
9616
9617 /* ... and break all links. */
9618 list_for_each_entry(connector, &dev->mode_config.connector_list,
9619 base.head) {
9620 if (connector->encoder->base.crtc != &crtc->base)
9621 continue;
9622
9623 intel_connector_break_all_links(connector);
9624 }
9625
9626 WARN_ON(crtc->active);
9627 crtc->base.enabled = false;
9628 }
24929352 9629
7fad798e
DV		 9630 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9631 crtc->pipe == PIPE_A && !crtc->active) {
9632 /* BIOS forgot to enable pipe A, this mostly happens after
9633 * resume. Force-enable the pipe to fix this, the update_dpms
9634 * call below we restore the pipe to the right state, but leave
9635 * the required bits on. */
9636 intel_enable_pipe_a(dev);
9637 }
9638
24929352
DV		 9639 /* Adjust the state of the output pipe according to whether we
9640 * have active connectors/encoders. */
9641 intel_crtc_update_dpms(&crtc->base);
9642
9643 if (crtc->active != crtc->base.enabled) {
9644 struct intel_encoder *encoder;
9645
9646 /* This can happen either due to bugs in the get_hw_state
9647 * functions or because the pipe is force-enabled due to the
9648 * pipe A quirk. */
9649 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9650 crtc->base.base.id,
9651 crtc->base.enabled ? "enabled" : "disabled",
9652 crtc->active ? "enabled" : "disabled");
9653
9654 crtc->base.enabled = crtc->active;
9655
9656 /* Because we only establish the connector -> encoder ->
9657 * crtc links if something is active, this means the
9658 * crtc is now deactivated. Break the links. connector
9659 * -> encoder links are only establish when things are
9660 * actually up, hence no need to break them. */
9661 WARN_ON(crtc->active);
9662
9663 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9664 WARN_ON(encoder->connectors_active);
9665 encoder->base.crtc = NULL;
9666 }
9667 }
9668}
9669
9670static void intel_sanitize_encoder(struct intel_encoder *encoder)
9671{
9672 struct intel_connector *connector;
9673 struct drm_device *dev = encoder->base.dev;
9674
9675 /* We need to check both for a crtc link (meaning that the
9676 * encoder is active and trying to read from a pipe) and the
9677 * pipe itself being active. */
9678 bool has_active_crtc = encoder->base.crtc &&
9679 to_intel_crtc(encoder->base.crtc)->active;
9680
9681 if (encoder->connectors_active && !has_active_crtc) {
9682 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9683 encoder->base.base.id,
9684 drm_get_encoder_name(&encoder->base));
9685
9686 /* Connector is active, but has no active pipe. This is
9687 * fallout from our resume register restoring. Disable
9688 * the encoder manually again. */
9689 if (encoder->base.crtc) {
9690 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9691 encoder->base.base.id,
9692 drm_get_encoder_name(&encoder->base));
9693 encoder->disable(encoder);
9694 }
9695
9696 /* Inconsistent output/port/pipe state happens presumably due to
9697 * a bug in one of the get_hw_state functions. Or someplace else
9698 * in our code, like the register restore mess on resume. Clamp
9699 * things to off as a safer default. */
9700 list_for_each_entry(connector,
9701 &dev->mode_config.connector_list,
9702 base.head) {
9703 if (connector->encoder != encoder)
9704 continue;
9705
9706 intel_connector_break_all_links(connector);
9707 }
9708 }
9709 /* Enabled encoders without active connectors will be fixed in
9710 * the crtc fixup. */
9711}
9712
44cec740 9713void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9714{
9715 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9716 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9717
9718 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9719 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9720 i915_disable_vga(dev);
0fde901f
KM		 9721 }
9722}
9723
30e984df 9724static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9725{
9726 struct drm_i915_private *dev_priv = dev->dev_private;
9727 enum pipe pipe;
24929352
DV		 9728 struct intel_crtc *crtc;
9729 struct intel_encoder *encoder;
9730 struct intel_connector *connector;
5358901f 9731 int i;
24929352 9732
0e8ffe1b
DV		 9733 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9734 base.head) {
88adfff1 9735 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9736
0e8ffe1b
DV		 9737 crtc->active = dev_priv->display.get_pipe_config(crtc,
9738 &crtc->config);
24929352
DV		 9739
9740 crtc->base.enabled = crtc->active;
9741
9742 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9743 crtc->base.base.id,
9744 crtc->active ? "enabled" : "disabled");
9745 }
9746
5358901f 9747 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9748 if (HAS_DDI(dev))
6441ab5f
PZ		 9749 intel_ddi_setup_hw_pll_state(dev);
9750
5358901f
DV		 9751 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9752 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9753
9754 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9755 pll->active = 0;
9756 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9757 base.head) {
9758 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9759 pll->active++;
9760 }
9761 pll->refcount = pll->active;
9762
9763 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9764 pll->name, pll->refcount);
9765 }
9766
24929352
DV		 9767 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9768 base.head) {
9769 pipe = 0;
9770
9771 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9772 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9773 encoder->base.crtc = &crtc->base;
9774 if (encoder->get_config)
9775 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9776 } else {
9777 encoder->base.crtc = NULL;
9778 }
9779
9780 encoder->connectors_active = false;
9781 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9782 encoder->base.base.id,
9783 drm_get_encoder_name(&encoder->base),
9784 encoder->base.crtc ? "enabled" : "disabled",
9785 pipe);
9786 }
9787
9788 list_for_each_entry(connector, &dev->mode_config.connector_list,
9789 base.head) {
9790 if (connector->get_hw_state(connector)) {
9791 connector->base.dpms = DRM_MODE_DPMS_ON;
9792 connector->encoder->connectors_active = true;
9793 connector->base.encoder = &connector->encoder->base;
9794 } else {
9795 connector->base.dpms = DRM_MODE_DPMS_OFF;
9796 connector->base.encoder = NULL;
9797 }
9798 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9799 connector->base.base.id,
9800 drm_get_connector_name(&connector->base),
9801 connector->base.encoder ? "enabled" : "disabled");
9802 }
30e984df
DV		 9803}
9804
9805/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9806 * and i915 state tracking structures. */
9807void intel_modeset_setup_hw_state(struct drm_device *dev,
9808 bool force_restore)
9809{
9810 struct drm_i915_private *dev_priv = dev->dev_private;
9811 enum pipe pipe;
9812 struct drm_plane *plane;
9813 struct intel_crtc *crtc;
9814 struct intel_encoder *encoder;
9815
9816 intel_modeset_readout_hw_state(dev);
24929352
DV		 9817
9818 /* HW state is read out, now we need to sanitize this mess. */
9819 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9820 base.head) {
9821 intel_sanitize_encoder(encoder);
9822 }
9823
9824 for_each_pipe(pipe) {
9825 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9826 intel_sanitize_crtc(crtc);
c0b03411 9827 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9828 }
9a935856 9829
45e2b5f6 9830 if (force_restore) {
f30da187
DV		 9831 /*
9832 * We need to use raw interfaces for restoring state to avoid
9833 * checking (bogus) intermediate states.
9834 */
45e2b5f6 9835 for_each_pipe(pipe) {
b5644d05
JB		 9836 struct drm_crtc *crtc =
9837 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9838
9839 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9840 crtc->fb);
45e2b5f6 9841 }
b5644d05
JB		 9842 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9843 intel_plane_restore(plane);
0fde901f
KM		 9844
9845 i915_redisable_vga(dev);
45e2b5f6
DV		 9846 } else {
9847 intel_modeset_update_staged_output_state(dev);
9848 }
8af6cf88
DV		 9849
9850 intel_modeset_check_state(dev);
2e938892
DV		 9851
9852 drm_mode_config_reset(dev);
2c7111db
CW		 9853}
9854
9855void intel_modeset_gem_init(struct drm_device *dev)
9856{
1833b134 9857 intel_modeset_init_hw(dev);
02e792fb
DV		 9858
9859 intel_setup_overlay(dev);
24929352 9860
45e2b5f6 9861 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9862}
9863
9864void intel_modeset_cleanup(struct drm_device *dev)
9865{
652c393a
JB		 9866 struct drm_i915_private *dev_priv = dev->dev_private;
9867 struct drm_crtc *crtc;
9868 struct intel_crtc *intel_crtc;
9869
fd0c0642
DV		 9870 /*
9871 * Interrupts and polling as the first thing to avoid creating havoc.
9872 * Too much stuff here (turning of rps, connectors, ...) would
9873 * experience fancy races otherwise.
9874 */
9875 drm_irq_uninstall(dev);
9876 cancel_work_sync(&dev_priv->hotplug_work);
9877 /*
9878 * Due to the hpd irq storm handling the hotplug work can re-arm the
9879 * poll handlers. Hence disable polling after hpd handling is shut down.
9880 */
f87ea761 9881 drm_kms_helper_poll_fini(dev);
fd0c0642 9882
652c393a
JB		 9883 mutex_lock(&dev->struct_mutex);
9884
723bfd70
JB		 9885 intel_unregister_dsm_handler();
9886
652c393a
JB		 9887 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9888 /* Skip inactive CRTCs */
9889 if (!crtc->fb)
9890 continue;
9891
9892 intel_crtc = to_intel_crtc(crtc);
3dec0095 9893 intel_increase_pllclock(crtc);
652c393a
JB		 9894 }
9895
973d04f9 9896 intel_disable_fbc(dev);
e70236a8 9897
8090c6b9 9898 intel_disable_gt_powersave(dev);
0cdab21f 9899
930ebb46
DV		 9900 ironlake_teardown_rc6(dev);
9901
69341a5e
KH		 9902 mutex_unlock(&dev->struct_mutex);
9903
1630fe75
CW		 9904 /* flush any delayed tasks or pending work */
9905 flush_scheduled_work();
9906
dc652f90
JN		 9907 /* destroy backlight, if any, before the connectors */
9908 intel_panel_destroy_backlight(dev);
9909
79e53945 9910 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9911
9912 intel_cleanup_overlay(dev);
79e53945
JB		 9913}
9914
f1c79df3
ZW		 9915/*
9916 * Return which encoder is currently attached for connector.
9917 */
df0e9248 9918struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9919{
df0e9248
CW		 9920 return &intel_attached_encoder(connector)->base;
9921}
f1c79df3 9922
df0e9248
CW		 9923void intel_connector_attach_encoder(struct intel_connector *connector,
9924 struct intel_encoder *encoder)
9925{
9926 connector->encoder = encoder;
9927 drm_mode_connector_attach_encoder(&connector->base,
9928 &encoder->base);
79e53945 9929}
28d52043
DA		 9930
9931/*
9932 * set vga decode state - true == enable VGA decode
9933 */
9934int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9935{
9936 struct drm_i915_private *dev_priv = dev->dev_private;
9937 u16 gmch_ctrl;
9938
9939 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9940 if (state)
9941 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9942 else
9943 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9944 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9945 return 0;
9946}
c4a1d9e4
CW		 9947
9948#ifdef CONFIG_DEBUG_FS
9949#include <linux/seq_file.h>
9950
9951struct intel_display_error_state {
ff57f1b0
PZ		 9952
9953 u32 power_well_driver;
9954
c4a1d9e4
CW		 9955 struct intel_cursor_error_state {
9956 u32 control;
9957 u32 position;
9958 u32 base;
9959 u32 size;
52331309 9960 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9961
9962 struct intel_pipe_error_state {
ff57f1b0 9963 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9964 u32 conf;
9965 u32 source;
9966
9967 u32 htotal;
9968 u32 hblank;
9969 u32 hsync;
9970 u32 vtotal;
9971 u32 vblank;
9972 u32 vsync;
52331309 9973 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9974
9975 struct intel_plane_error_state {
9976 u32 control;
9977 u32 stride;
9978 u32 size;
9979 u32 pos;
9980 u32 addr;
9981 u32 surface;
9982 u32 tile_offset;
52331309 9983 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9984};
9985
9986struct intel_display_error_state *
9987intel_display_capture_error_state(struct drm_device *dev)
9988{
0206e353 9989 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9990 struct intel_display_error_state *error;
702e7a56 9991 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9992 int i;
9993
9994 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9995 if (error == NULL)
9996 return NULL;
9997
ff57f1b0
PZ		 9998 if (HAS_POWER_WELL(dev))
9999 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10000
52331309 10001 for_each_pipe(i) {
702e7a56 10002 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10003 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10004
a18c4c3d
PZ		 10005 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10006 error->cursor[i].control = I915_READ(CURCNTR(i));
10007 error->cursor[i].position = I915_READ(CURPOS(i));
10008 error->cursor[i].base = I915_READ(CURBASE(i));
10009 } else {
10010 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10011 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10012 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10013 }
c4a1d9e4
CW		 10014
10015 error->plane[i].control = I915_READ(DSPCNTR(i));
10016 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10017 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10018 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10019 error->plane[i].pos = I915_READ(DSPPOS(i));
10020 }
ca291363
PZ		 10021 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10022 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10023 if (INTEL_INFO(dev)->gen >= 4) {
10024 error->plane[i].surface = I915_READ(DSPSURF(i));
10025 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10026 }
10027
702e7a56 10028 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10029 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10030 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10031 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10032 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10033 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10034 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10035 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10036 }
10037
12d217c7
PZ		 10038 /* In the code above we read the registers without checking if the power
10039 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10040 * prevent the next I915_WRITE from detecting it and printing an error
10041 * message. */
10042 if (HAS_POWER_WELL(dev))
10043 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10044
c4a1d9e4
CW		 10045 return error;
10046}
10047
edc3d884
MK		 10048#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10049
c4a1d9e4 10050void
edc3d884 10051intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10052 struct drm_device *dev,
10053 struct intel_display_error_state *error)
10054{
10055 int i;
10056
edc3d884 10057 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10058 if (HAS_POWER_WELL(dev))
edc3d884 10059 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10060 error->power_well_driver);
52331309 10061 for_each_pipe(i) {
edc3d884
MK		 10062 err_printf(m, "Pipe [%d]:\n", i);
10063 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10064 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10065 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10066 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10067 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10068 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10069 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10070 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10071 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10072 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10073
10074 err_printf(m, "Plane [%d]:\n", i);
10075 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10076 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10077 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10078 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10079 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10080 }
4b71a570 10081 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10082 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10083 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10084 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10085 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10086 }
10087
edc3d884
MK		 10088 err_printf(m, "Cursor [%d]:\n", i);
10089 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10090 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10091 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10092 }
10093}
10094#endif
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