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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
e7457a9a | 106 | |
0e32b39c DA |
107 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
108 | { | |
109 | if (!connector->mst_port) | |
110 | return connector->encoder; | |
111 | else | |
112 | return &connector->mst_port->mst_encoders[pipe]->base; | |
113 | } | |
114 | ||
79e53945 | 115 | typedef struct { |
0206e353 | 116 | int min, max; |
79e53945 JB |
117 | } intel_range_t; |
118 | ||
119 | typedef struct { | |
0206e353 AJ |
120 | int dot_limit; |
121 | int p2_slow, p2_fast; | |
79e53945 JB |
122 | } intel_p2_t; |
123 | ||
d4906093 ML |
124 | typedef struct intel_limit intel_limit_t; |
125 | struct intel_limit { | |
0206e353 AJ |
126 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
127 | intel_p2_t p2; | |
d4906093 | 128 | }; |
79e53945 | 129 | |
d2acd215 DV |
130 | int |
131 | intel_pch_rawclk(struct drm_device *dev) | |
132 | { | |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
134 | ||
135 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
136 | ||
137 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
138 | } | |
139 | ||
021357ac CW |
140 | static inline u32 /* units of 100MHz */ |
141 | intel_fdi_link_freq(struct drm_device *dev) | |
142 | { | |
8b99e68c CW |
143 | if (IS_GEN5(dev)) { |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
145 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
146 | } else | |
147 | return 27; | |
021357ac CW |
148 | } |
149 | ||
5d536e28 | 150 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 151 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 152 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 153 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
154 | .m = { .min = 96, .max = 140 }, |
155 | .m1 = { .min = 18, .max = 26 }, | |
156 | .m2 = { .min = 6, .max = 16 }, | |
157 | .p = { .min = 4, .max = 128 }, | |
158 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
159 | .p2 = { .dot_limit = 165000, |
160 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
161 | }; |
162 | ||
5d536e28 DV |
163 | static const intel_limit_t intel_limits_i8xx_dvo = { |
164 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 165 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 166 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
167 | .m = { .min = 96, .max = 140 }, |
168 | .m1 = { .min = 18, .max = 26 }, | |
169 | .m2 = { .min = 6, .max = 16 }, | |
170 | .p = { .min = 4, .max = 128 }, | |
171 | .p1 = { .min = 2, .max = 33 }, | |
172 | .p2 = { .dot_limit = 165000, | |
173 | .p2_slow = 4, .p2_fast = 4 }, | |
174 | }; | |
175 | ||
e4b36699 | 176 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 177 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 178 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 179 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
180 | .m = { .min = 96, .max = 140 }, |
181 | .m1 = { .min = 18, .max = 26 }, | |
182 | .m2 = { .min = 6, .max = 16 }, | |
183 | .p = { .min = 4, .max = 128 }, | |
184 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
185 | .p2 = { .dot_limit = 165000, |
186 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 187 | }; |
273e27ca | 188 | |
e4b36699 | 189 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
190 | .dot = { .min = 20000, .max = 400000 }, |
191 | .vco = { .min = 1400000, .max = 2800000 }, | |
192 | .n = { .min = 1, .max = 6 }, | |
193 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
194 | .m1 = { .min = 8, .max = 18 }, |
195 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
196 | .p = { .min = 5, .max = 80 }, |
197 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
198 | .p2 = { .dot_limit = 200000, |
199 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
200 | }; |
201 | ||
202 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
203 | .dot = { .min = 20000, .max = 400000 }, |
204 | .vco = { .min = 1400000, .max = 2800000 }, | |
205 | .n = { .min = 1, .max = 6 }, | |
206 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
207 | .m1 = { .min = 8, .max = 18 }, |
208 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
209 | .p = { .min = 7, .max = 98 }, |
210 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
211 | .p2 = { .dot_limit = 112000, |
212 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
213 | }; |
214 | ||
273e27ca | 215 | |
e4b36699 | 216 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
217 | .dot = { .min = 25000, .max = 270000 }, |
218 | .vco = { .min = 1750000, .max = 3500000}, | |
219 | .n = { .min = 1, .max = 4 }, | |
220 | .m = { .min = 104, .max = 138 }, | |
221 | .m1 = { .min = 17, .max = 23 }, | |
222 | .m2 = { .min = 5, .max = 11 }, | |
223 | .p = { .min = 10, .max = 30 }, | |
224 | .p1 = { .min = 1, .max = 3}, | |
225 | .p2 = { .dot_limit = 270000, | |
226 | .p2_slow = 10, | |
227 | .p2_fast = 10 | |
044c7c41 | 228 | }, |
e4b36699 KP |
229 | }; |
230 | ||
231 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
232 | .dot = { .min = 22000, .max = 400000 }, |
233 | .vco = { .min = 1750000, .max = 3500000}, | |
234 | .n = { .min = 1, .max = 4 }, | |
235 | .m = { .min = 104, .max = 138 }, | |
236 | .m1 = { .min = 16, .max = 23 }, | |
237 | .m2 = { .min = 5, .max = 11 }, | |
238 | .p = { .min = 5, .max = 80 }, | |
239 | .p1 = { .min = 1, .max = 8}, | |
240 | .p2 = { .dot_limit = 165000, | |
241 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
242 | }; |
243 | ||
244 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
245 | .dot = { .min = 20000, .max = 115000 }, |
246 | .vco = { .min = 1750000, .max = 3500000 }, | |
247 | .n = { .min = 1, .max = 3 }, | |
248 | .m = { .min = 104, .max = 138 }, | |
249 | .m1 = { .min = 17, .max = 23 }, | |
250 | .m2 = { .min = 5, .max = 11 }, | |
251 | .p = { .min = 28, .max = 112 }, | |
252 | .p1 = { .min = 2, .max = 8 }, | |
253 | .p2 = { .dot_limit = 0, | |
254 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 255 | }, |
e4b36699 KP |
256 | }; |
257 | ||
258 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
259 | .dot = { .min = 80000, .max = 224000 }, |
260 | .vco = { .min = 1750000, .max = 3500000 }, | |
261 | .n = { .min = 1, .max = 3 }, | |
262 | .m = { .min = 104, .max = 138 }, | |
263 | .m1 = { .min = 17, .max = 23 }, | |
264 | .m2 = { .min = 5, .max = 11 }, | |
265 | .p = { .min = 14, .max = 42 }, | |
266 | .p1 = { .min = 2, .max = 6 }, | |
267 | .p2 = { .dot_limit = 0, | |
268 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 269 | }, |
e4b36699 KP |
270 | }; |
271 | ||
f2b115e6 | 272 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
273 | .dot = { .min = 20000, .max = 400000}, |
274 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 275 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
276 | .n = { .min = 3, .max = 6 }, |
277 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 278 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
279 | .m1 = { .min = 0, .max = 0 }, |
280 | .m2 = { .min = 0, .max = 254 }, | |
281 | .p = { .min = 5, .max = 80 }, | |
282 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
283 | .p2 = { .dot_limit = 200000, |
284 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
285 | }; |
286 | ||
f2b115e6 | 287 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
288 | .dot = { .min = 20000, .max = 400000 }, |
289 | .vco = { .min = 1700000, .max = 3500000 }, | |
290 | .n = { .min = 3, .max = 6 }, | |
291 | .m = { .min = 2, .max = 256 }, | |
292 | .m1 = { .min = 0, .max = 0 }, | |
293 | .m2 = { .min = 0, .max = 254 }, | |
294 | .p = { .min = 7, .max = 112 }, | |
295 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
296 | .p2 = { .dot_limit = 112000, |
297 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
298 | }; |
299 | ||
273e27ca EA |
300 | /* Ironlake / Sandybridge |
301 | * | |
302 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
303 | * the range value for them is (actual_value - 2). | |
304 | */ | |
b91ad0ec | 305 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
306 | .dot = { .min = 25000, .max = 350000 }, |
307 | .vco = { .min = 1760000, .max = 3510000 }, | |
308 | .n = { .min = 1, .max = 5 }, | |
309 | .m = { .min = 79, .max = 127 }, | |
310 | .m1 = { .min = 12, .max = 22 }, | |
311 | .m2 = { .min = 5, .max = 9 }, | |
312 | .p = { .min = 5, .max = 80 }, | |
313 | .p1 = { .min = 1, .max = 8 }, | |
314 | .p2 = { .dot_limit = 225000, | |
315 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
316 | }; |
317 | ||
b91ad0ec | 318 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
319 | .dot = { .min = 25000, .max = 350000 }, |
320 | .vco = { .min = 1760000, .max = 3510000 }, | |
321 | .n = { .min = 1, .max = 3 }, | |
322 | .m = { .min = 79, .max = 118 }, | |
323 | .m1 = { .min = 12, .max = 22 }, | |
324 | .m2 = { .min = 5, .max = 9 }, | |
325 | .p = { .min = 28, .max = 112 }, | |
326 | .p1 = { .min = 2, .max = 8 }, | |
327 | .p2 = { .dot_limit = 225000, | |
328 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
329 | }; |
330 | ||
331 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
332 | .dot = { .min = 25000, .max = 350000 }, |
333 | .vco = { .min = 1760000, .max = 3510000 }, | |
334 | .n = { .min = 1, .max = 3 }, | |
335 | .m = { .min = 79, .max = 127 }, | |
336 | .m1 = { .min = 12, .max = 22 }, | |
337 | .m2 = { .min = 5, .max = 9 }, | |
338 | .p = { .min = 14, .max = 56 }, | |
339 | .p1 = { .min = 2, .max = 8 }, | |
340 | .p2 = { .dot_limit = 225000, | |
341 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
342 | }; |
343 | ||
273e27ca | 344 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 345 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
346 | .dot = { .min = 25000, .max = 350000 }, |
347 | .vco = { .min = 1760000, .max = 3510000 }, | |
348 | .n = { .min = 1, .max = 2 }, | |
349 | .m = { .min = 79, .max = 126 }, | |
350 | .m1 = { .min = 12, .max = 22 }, | |
351 | .m2 = { .min = 5, .max = 9 }, | |
352 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 353 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
354 | .p2 = { .dot_limit = 225000, |
355 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
356 | }; |
357 | ||
358 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 3 }, | |
362 | .m = { .min = 79, .max = 126 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 366 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
367 | .p2 = { .dot_limit = 225000, |
368 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
369 | }; |
370 | ||
dc730512 | 371 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
372 | /* |
373 | * These are the data rate limits (measured in fast clocks) | |
374 | * since those are the strictest limits we have. The fast | |
375 | * clock and actual rate limits are more relaxed, so checking | |
376 | * them would make no difference. | |
377 | */ | |
378 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 379 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 380 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
381 | .m1 = { .min = 2, .max = 3 }, |
382 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 383 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 384 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
385 | }; |
386 | ||
ef9348c8 CML |
387 | static const intel_limit_t intel_limits_chv = { |
388 | /* | |
389 | * These are the data rate limits (measured in fast clocks) | |
390 | * since those are the strictest limits we have. The fast | |
391 | * clock and actual rate limits are more relaxed, so checking | |
392 | * them would make no difference. | |
393 | */ | |
394 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 395 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
396 | .n = { .min = 1, .max = 1 }, |
397 | .m1 = { .min = 2, .max = 2 }, | |
398 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
399 | .p1 = { .min = 2, .max = 4 }, | |
400 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
401 | }; | |
402 | ||
6b4bf1c4 VS |
403 | static void vlv_clock(int refclk, intel_clock_t *clock) |
404 | { | |
405 | clock->m = clock->m1 * clock->m2; | |
406 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
407 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
408 | return; | |
fb03ac01 VS |
409 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
410 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
411 | } |
412 | ||
e0638cdf PZ |
413 | /** |
414 | * Returns whether any output on the specified pipe is of the specified type | |
415 | */ | |
4093561b | 416 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 417 | { |
409ee761 | 418 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
419 | struct intel_encoder *encoder; |
420 | ||
409ee761 | 421 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
422 | if (encoder->type == type) |
423 | return true; | |
424 | ||
425 | return false; | |
426 | } | |
427 | ||
d0737e1d ACO |
428 | /** |
429 | * Returns whether any output on the specified pipe will have the specified | |
430 | * type after a staged modeset is complete, i.e., the same as | |
431 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
432 | * encoder->crtc. | |
433 | */ | |
434 | static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) | |
435 | { | |
436 | struct drm_device *dev = crtc->base.dev; | |
437 | struct intel_encoder *encoder; | |
438 | ||
439 | for_each_intel_encoder(dev, encoder) | |
440 | if (encoder->new_crtc == crtc && encoder->type == type) | |
441 | return true; | |
442 | ||
443 | return false; | |
444 | } | |
445 | ||
409ee761 | 446 | static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
1b894b59 | 447 | int refclk) |
2c07245f | 448 | { |
409ee761 | 449 | struct drm_device *dev = crtc->base.dev; |
2c07245f | 450 | const intel_limit_t *limit; |
b91ad0ec | 451 | |
d0737e1d | 452 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 453 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 454 | if (refclk == 100000) |
b91ad0ec ZW |
455 | limit = &intel_limits_ironlake_dual_lvds_100m; |
456 | else | |
457 | limit = &intel_limits_ironlake_dual_lvds; | |
458 | } else { | |
1b894b59 | 459 | if (refclk == 100000) |
b91ad0ec ZW |
460 | limit = &intel_limits_ironlake_single_lvds_100m; |
461 | else | |
462 | limit = &intel_limits_ironlake_single_lvds; | |
463 | } | |
c6bb3538 | 464 | } else |
b91ad0ec | 465 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
466 | |
467 | return limit; | |
468 | } | |
469 | ||
409ee761 | 470 | static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
044c7c41 | 471 | { |
409ee761 | 472 | struct drm_device *dev = crtc->base.dev; |
044c7c41 ML |
473 | const intel_limit_t *limit; |
474 | ||
d0737e1d | 475 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 476 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 477 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 478 | else |
e4b36699 | 479 | limit = &intel_limits_g4x_single_channel_lvds; |
d0737e1d ACO |
480 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
481 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 482 | limit = &intel_limits_g4x_hdmi; |
d0737e1d | 483 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 484 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 485 | } else /* The option is for other outputs */ |
e4b36699 | 486 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
487 | |
488 | return limit; | |
489 | } | |
490 | ||
409ee761 | 491 | static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
79e53945 | 492 | { |
409ee761 | 493 | struct drm_device *dev = crtc->base.dev; |
79e53945 JB |
494 | const intel_limit_t *limit; |
495 | ||
bad720ff | 496 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 497 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 498 | else if (IS_G4X(dev)) { |
044c7c41 | 499 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 500 | } else if (IS_PINEVIEW(dev)) { |
d0737e1d | 501 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 502 | limit = &intel_limits_pineview_lvds; |
2177832f | 503 | else |
f2b115e6 | 504 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
505 | } else if (IS_CHERRYVIEW(dev)) { |
506 | limit = &intel_limits_chv; | |
a0c4da24 | 507 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 508 | limit = &intel_limits_vlv; |
a6c45cf0 | 509 | } else if (!IS_GEN2(dev)) { |
d0737e1d | 510 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
511 | limit = &intel_limits_i9xx_lvds; |
512 | else | |
513 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 514 | } else { |
d0737e1d | 515 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 516 | limit = &intel_limits_i8xx_lvds; |
d0737e1d | 517 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 518 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
519 | else |
520 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
521 | } |
522 | return limit; | |
523 | } | |
524 | ||
f2b115e6 AJ |
525 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
526 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 527 | { |
2177832f SL |
528 | clock->m = clock->m2 + 2; |
529 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
530 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
531 | return; | |
fb03ac01 VS |
532 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
533 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
534 | } |
535 | ||
7429e9d4 DV |
536 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
537 | { | |
538 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
539 | } | |
540 | ||
ac58c3f0 | 541 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 542 | { |
7429e9d4 | 543 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 544 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
545 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
546 | return; | |
fb03ac01 VS |
547 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
548 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
549 | } |
550 | ||
ef9348c8 CML |
551 | static void chv_clock(int refclk, intel_clock_t *clock) |
552 | { | |
553 | clock->m = clock->m1 * clock->m2; | |
554 | clock->p = clock->p1 * clock->p2; | |
555 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
556 | return; | |
557 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
558 | clock->n << 22); | |
559 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
560 | } | |
561 | ||
7c04d1d9 | 562 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
563 | /** |
564 | * Returns whether the given set of divisors are valid for a given refclk with | |
565 | * the given connectors. | |
566 | */ | |
567 | ||
1b894b59 CW |
568 | static bool intel_PLL_is_valid(struct drm_device *dev, |
569 | const intel_limit_t *limit, | |
570 | const intel_clock_t *clock) | |
79e53945 | 571 | { |
f01b7962 VS |
572 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
573 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 574 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 575 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 576 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 577 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 578 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 579 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
580 | |
581 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
582 | if (clock->m1 <= clock->m2) | |
583 | INTELPllInvalid("m1 <= m2\n"); | |
584 | ||
585 | if (!IS_VALLEYVIEW(dev)) { | |
586 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
587 | INTELPllInvalid("p out of range\n"); | |
588 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
589 | INTELPllInvalid("m out of range\n"); | |
590 | } | |
591 | ||
79e53945 | 592 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 593 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
594 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
595 | * connector, etc., rather than just a single range. | |
596 | */ | |
597 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 598 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
599 | |
600 | return true; | |
601 | } | |
602 | ||
d4906093 | 603 | static bool |
a919ff14 | 604 | i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
cec2f356 SP |
605 | int target, int refclk, intel_clock_t *match_clock, |
606 | intel_clock_t *best_clock) | |
79e53945 | 607 | { |
a919ff14 | 608 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 609 | intel_clock_t clock; |
79e53945 JB |
610 | int err = target; |
611 | ||
d0737e1d | 612 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 613 | /* |
a210b028 DV |
614 | * For LVDS just rely on its current settings for dual-channel. |
615 | * We haven't figured out how to reliably set up different | |
616 | * single/dual channel state, if we even can. | |
79e53945 | 617 | */ |
1974cad0 | 618 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
619 | clock.p2 = limit->p2.p2_fast; |
620 | else | |
621 | clock.p2 = limit->p2.p2_slow; | |
622 | } else { | |
623 | if (target < limit->p2.dot_limit) | |
624 | clock.p2 = limit->p2.p2_slow; | |
625 | else | |
626 | clock.p2 = limit->p2.p2_fast; | |
627 | } | |
628 | ||
0206e353 | 629 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 630 | |
42158660 ZY |
631 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
632 | clock.m1++) { | |
633 | for (clock.m2 = limit->m2.min; | |
634 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 635 | if (clock.m2 >= clock.m1) |
42158660 ZY |
636 | break; |
637 | for (clock.n = limit->n.min; | |
638 | clock.n <= limit->n.max; clock.n++) { | |
639 | for (clock.p1 = limit->p1.min; | |
640 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
641 | int this_err; |
642 | ||
ac58c3f0 DV |
643 | i9xx_clock(refclk, &clock); |
644 | if (!intel_PLL_is_valid(dev, limit, | |
645 | &clock)) | |
646 | continue; | |
647 | if (match_clock && | |
648 | clock.p != match_clock->p) | |
649 | continue; | |
650 | ||
651 | this_err = abs(clock.dot - target); | |
652 | if (this_err < err) { | |
653 | *best_clock = clock; | |
654 | err = this_err; | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | } | |
660 | ||
661 | return (err != target); | |
662 | } | |
663 | ||
664 | static bool | |
a919ff14 | 665 | pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
666 | int target, int refclk, intel_clock_t *match_clock, |
667 | intel_clock_t *best_clock) | |
79e53945 | 668 | { |
a919ff14 | 669 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 670 | intel_clock_t clock; |
79e53945 JB |
671 | int err = target; |
672 | ||
d0737e1d | 673 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 674 | /* |
a210b028 DV |
675 | * For LVDS just rely on its current settings for dual-channel. |
676 | * We haven't figured out how to reliably set up different | |
677 | * single/dual channel state, if we even can. | |
79e53945 | 678 | */ |
1974cad0 | 679 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
680 | clock.p2 = limit->p2.p2_fast; |
681 | else | |
682 | clock.p2 = limit->p2.p2_slow; | |
683 | } else { | |
684 | if (target < limit->p2.dot_limit) | |
685 | clock.p2 = limit->p2.p2_slow; | |
686 | else | |
687 | clock.p2 = limit->p2.p2_fast; | |
688 | } | |
689 | ||
0206e353 | 690 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 691 | |
42158660 ZY |
692 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
693 | clock.m1++) { | |
694 | for (clock.m2 = limit->m2.min; | |
695 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
696 | for (clock.n = limit->n.min; |
697 | clock.n <= limit->n.max; clock.n++) { | |
698 | for (clock.p1 = limit->p1.min; | |
699 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
700 | int this_err; |
701 | ||
ac58c3f0 | 702 | pineview_clock(refclk, &clock); |
1b894b59 CW |
703 | if (!intel_PLL_is_valid(dev, limit, |
704 | &clock)) | |
79e53945 | 705 | continue; |
cec2f356 SP |
706 | if (match_clock && |
707 | clock.p != match_clock->p) | |
708 | continue; | |
79e53945 JB |
709 | |
710 | this_err = abs(clock.dot - target); | |
711 | if (this_err < err) { | |
712 | *best_clock = clock; | |
713 | err = this_err; | |
714 | } | |
715 | } | |
716 | } | |
717 | } | |
718 | } | |
719 | ||
720 | return (err != target); | |
721 | } | |
722 | ||
d4906093 | 723 | static bool |
a919ff14 | 724 | g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
725 | int target, int refclk, intel_clock_t *match_clock, |
726 | intel_clock_t *best_clock) | |
d4906093 | 727 | { |
a919ff14 | 728 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
729 | intel_clock_t clock; |
730 | int max_n; | |
731 | bool found; | |
6ba770dc AJ |
732 | /* approximately equals target * 0.00585 */ |
733 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
734 | found = false; |
735 | ||
d0737e1d | 736 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 737 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
738 | clock.p2 = limit->p2.p2_fast; |
739 | else | |
740 | clock.p2 = limit->p2.p2_slow; | |
741 | } else { | |
742 | if (target < limit->p2.dot_limit) | |
743 | clock.p2 = limit->p2.p2_slow; | |
744 | else | |
745 | clock.p2 = limit->p2.p2_fast; | |
746 | } | |
747 | ||
748 | memset(best_clock, 0, sizeof(*best_clock)); | |
749 | max_n = limit->n.max; | |
f77f13e2 | 750 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 751 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 752 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
753 | for (clock.m1 = limit->m1.max; |
754 | clock.m1 >= limit->m1.min; clock.m1--) { | |
755 | for (clock.m2 = limit->m2.max; | |
756 | clock.m2 >= limit->m2.min; clock.m2--) { | |
757 | for (clock.p1 = limit->p1.max; | |
758 | clock.p1 >= limit->p1.min; clock.p1--) { | |
759 | int this_err; | |
760 | ||
ac58c3f0 | 761 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
762 | if (!intel_PLL_is_valid(dev, limit, |
763 | &clock)) | |
d4906093 | 764 | continue; |
1b894b59 CW |
765 | |
766 | this_err = abs(clock.dot - target); | |
d4906093 ML |
767 | if (this_err < err_most) { |
768 | *best_clock = clock; | |
769 | err_most = this_err; | |
770 | max_n = clock.n; | |
771 | found = true; | |
772 | } | |
773 | } | |
774 | } | |
775 | } | |
776 | } | |
2c07245f ZW |
777 | return found; |
778 | } | |
779 | ||
d5dd62bd ID |
780 | /* |
781 | * Check if the calculated PLL configuration is more optimal compared to the | |
782 | * best configuration and error found so far. Return the calculated error. | |
783 | */ | |
784 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
785 | const intel_clock_t *calculated_clock, | |
786 | const intel_clock_t *best_clock, | |
787 | unsigned int best_error_ppm, | |
788 | unsigned int *error_ppm) | |
789 | { | |
9ca3ba01 ID |
790 | /* |
791 | * For CHV ignore the error and consider only the P value. | |
792 | * Prefer a bigger P value based on HW requirements. | |
793 | */ | |
794 | if (IS_CHERRYVIEW(dev)) { | |
795 | *error_ppm = 0; | |
796 | ||
797 | return calculated_clock->p > best_clock->p; | |
798 | } | |
799 | ||
24be4e46 ID |
800 | if (WARN_ON_ONCE(!target_freq)) |
801 | return false; | |
802 | ||
d5dd62bd ID |
803 | *error_ppm = div_u64(1000000ULL * |
804 | abs(target_freq - calculated_clock->dot), | |
805 | target_freq); | |
806 | /* | |
807 | * Prefer a better P value over a better (smaller) error if the error | |
808 | * is small. Ensure this preference for future configurations too by | |
809 | * setting the error to 0. | |
810 | */ | |
811 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
812 | *error_ppm = 0; | |
813 | ||
814 | return true; | |
815 | } | |
816 | ||
817 | return *error_ppm + 10 < best_error_ppm; | |
818 | } | |
819 | ||
a0c4da24 | 820 | static bool |
a919ff14 | 821 | vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
822 | int target, int refclk, intel_clock_t *match_clock, |
823 | intel_clock_t *best_clock) | |
a0c4da24 | 824 | { |
a919ff14 | 825 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 826 | intel_clock_t clock; |
69e4f900 | 827 | unsigned int bestppm = 1000000; |
27e639bf VS |
828 | /* min update 19.2 MHz */ |
829 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 830 | bool found = false; |
a0c4da24 | 831 | |
6b4bf1c4 VS |
832 | target *= 5; /* fast clock */ |
833 | ||
834 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
835 | |
836 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 837 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 838 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 839 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 840 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 841 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 842 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 843 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 844 | unsigned int ppm; |
69e4f900 | 845 | |
6b4bf1c4 VS |
846 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
847 | refclk * clock.m1); | |
848 | ||
849 | vlv_clock(refclk, &clock); | |
43b0ac53 | 850 | |
f01b7962 VS |
851 | if (!intel_PLL_is_valid(dev, limit, |
852 | &clock)) | |
43b0ac53 VS |
853 | continue; |
854 | ||
d5dd62bd ID |
855 | if (!vlv_PLL_is_optimal(dev, target, |
856 | &clock, | |
857 | best_clock, | |
858 | bestppm, &ppm)) | |
859 | continue; | |
6b4bf1c4 | 860 | |
d5dd62bd ID |
861 | *best_clock = clock; |
862 | bestppm = ppm; | |
863 | found = true; | |
a0c4da24 JB |
864 | } |
865 | } | |
866 | } | |
867 | } | |
a0c4da24 | 868 | |
49e497ef | 869 | return found; |
a0c4da24 | 870 | } |
a4fc5ed6 | 871 | |
ef9348c8 | 872 | static bool |
a919ff14 | 873 | chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ef9348c8 CML |
874 | int target, int refclk, intel_clock_t *match_clock, |
875 | intel_clock_t *best_clock) | |
876 | { | |
a919ff14 | 877 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 878 | unsigned int best_error_ppm; |
ef9348c8 CML |
879 | intel_clock_t clock; |
880 | uint64_t m2; | |
881 | int found = false; | |
882 | ||
883 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 884 | best_error_ppm = 1000000; |
ef9348c8 CML |
885 | |
886 | /* | |
887 | * Based on hardware doc, the n always set to 1, and m1 always | |
888 | * set to 2. If requires to support 200Mhz refclk, we need to | |
889 | * revisit this because n may not 1 anymore. | |
890 | */ | |
891 | clock.n = 1, clock.m1 = 2; | |
892 | target *= 5; /* fast clock */ | |
893 | ||
894 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
895 | for (clock.p2 = limit->p2.p2_fast; | |
896 | clock.p2 >= limit->p2.p2_slow; | |
897 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 898 | unsigned int error_ppm; |
ef9348c8 CML |
899 | |
900 | clock.p = clock.p1 * clock.p2; | |
901 | ||
902 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
903 | clock.n) << 22, refclk * clock.m1); | |
904 | ||
905 | if (m2 > INT_MAX/clock.m1) | |
906 | continue; | |
907 | ||
908 | clock.m2 = m2; | |
909 | ||
910 | chv_clock(refclk, &clock); | |
911 | ||
912 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
913 | continue; | |
914 | ||
9ca3ba01 ID |
915 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
916 | best_error_ppm, &error_ppm)) | |
917 | continue; | |
918 | ||
919 | *best_clock = clock; | |
920 | best_error_ppm = error_ppm; | |
921 | found = true; | |
ef9348c8 CML |
922 | } |
923 | } | |
924 | ||
925 | return found; | |
926 | } | |
927 | ||
20ddf665 VS |
928 | bool intel_crtc_active(struct drm_crtc *crtc) |
929 | { | |
930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
931 | ||
932 | /* Be paranoid as we can arrive here with only partial | |
933 | * state retrieved from the hardware during setup. | |
934 | * | |
241bfc38 | 935 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
936 | * as Haswell has gained clock readout/fastboot support. |
937 | * | |
66e514c1 | 938 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 939 | * properly reconstruct framebuffers. |
c3d1f436 MR |
940 | * |
941 | * FIXME: The intel_crtc->active here should be switched to | |
942 | * crtc->state->active once we have proper CRTC states wired up | |
943 | * for atomic. | |
20ddf665 | 944 | */ |
c3d1f436 | 945 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 946 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
947 | } |
948 | ||
a5c961d1 PZ |
949 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
950 | enum pipe pipe) | |
951 | { | |
952 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
953 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
954 | ||
6e3c9717 | 955 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
956 | } |
957 | ||
fbf49ea2 VS |
958 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
959 | { | |
960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
961 | u32 reg = PIPEDSL(pipe); | |
962 | u32 line1, line2; | |
963 | u32 line_mask; | |
964 | ||
965 | if (IS_GEN2(dev)) | |
966 | line_mask = DSL_LINEMASK_GEN2; | |
967 | else | |
968 | line_mask = DSL_LINEMASK_GEN3; | |
969 | ||
970 | line1 = I915_READ(reg) & line_mask; | |
971 | mdelay(5); | |
972 | line2 = I915_READ(reg) & line_mask; | |
973 | ||
974 | return line1 == line2; | |
975 | } | |
976 | ||
ab7ad7f6 KP |
977 | /* |
978 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 979 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
980 | * |
981 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
982 | * spinning on the vblank interrupt status bit, since we won't actually | |
983 | * see an interrupt when the pipe is disabled. | |
984 | * | |
ab7ad7f6 KP |
985 | * On Gen4 and above: |
986 | * wait for the pipe register state bit to turn off | |
987 | * | |
988 | * Otherwise: | |
989 | * wait for the display line value to settle (it usually | |
990 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 991 | * |
9d0498a2 | 992 | */ |
575f7ab7 | 993 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 994 | { |
575f7ab7 | 995 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 996 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 997 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 998 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
999 | |
1000 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1001 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1002 | |
1003 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1004 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1005 | 100)) | |
284637d9 | 1006 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1007 | } else { |
ab7ad7f6 | 1008 | /* Wait for the display line to settle */ |
fbf49ea2 | 1009 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1010 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1011 | } |
79e53945 JB |
1012 | } |
1013 | ||
b0ea7d37 DL |
1014 | /* |
1015 | * ibx_digital_port_connected - is the specified port connected? | |
1016 | * @dev_priv: i915 private structure | |
1017 | * @port: the port to test | |
1018 | * | |
1019 | * Returns true if @port is connected, false otherwise. | |
1020 | */ | |
1021 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1022 | struct intel_digital_port *port) | |
1023 | { | |
1024 | u32 bit; | |
1025 | ||
c36346e3 | 1026 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1027 | switch (port->port) { |
c36346e3 DL |
1028 | case PORT_B: |
1029 | bit = SDE_PORTB_HOTPLUG; | |
1030 | break; | |
1031 | case PORT_C: | |
1032 | bit = SDE_PORTC_HOTPLUG; | |
1033 | break; | |
1034 | case PORT_D: | |
1035 | bit = SDE_PORTD_HOTPLUG; | |
1036 | break; | |
1037 | default: | |
1038 | return true; | |
1039 | } | |
1040 | } else { | |
eba905b2 | 1041 | switch (port->port) { |
c36346e3 DL |
1042 | case PORT_B: |
1043 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1044 | break; | |
1045 | case PORT_C: | |
1046 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1047 | break; | |
1048 | case PORT_D: | |
1049 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1050 | break; | |
1051 | default: | |
1052 | return true; | |
1053 | } | |
b0ea7d37 DL |
1054 | } |
1055 | ||
1056 | return I915_READ(SDEISR) & bit; | |
1057 | } | |
1058 | ||
b24e7179 JB |
1059 | static const char *state_string(bool enabled) |
1060 | { | |
1061 | return enabled ? "on" : "off"; | |
1062 | } | |
1063 | ||
1064 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1065 | void assert_pll(struct drm_i915_private *dev_priv, |
1066 | enum pipe pipe, bool state) | |
b24e7179 JB |
1067 | { |
1068 | int reg; | |
1069 | u32 val; | |
1070 | bool cur_state; | |
1071 | ||
1072 | reg = DPLL(pipe); | |
1073 | val = I915_READ(reg); | |
1074 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1075 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1076 | "PLL state assertion failure (expected %s, current %s)\n", |
1077 | state_string(state), state_string(cur_state)); | |
1078 | } | |
b24e7179 | 1079 | |
23538ef1 JN |
1080 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1081 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1082 | { | |
1083 | u32 val; | |
1084 | bool cur_state; | |
1085 | ||
1086 | mutex_lock(&dev_priv->dpio_lock); | |
1087 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1088 | mutex_unlock(&dev_priv->dpio_lock); | |
1089 | ||
1090 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1091 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1092 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1093 | state_string(state), state_string(cur_state)); | |
1094 | } | |
1095 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1096 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1097 | ||
55607e8a | 1098 | struct intel_shared_dpll * |
e2b78267 DV |
1099 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1100 | { | |
1101 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1102 | ||
6e3c9717 | 1103 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1104 | return NULL; |
1105 | ||
6e3c9717 | 1106 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1107 | } |
1108 | ||
040484af | 1109 | /* For ILK+ */ |
55607e8a DV |
1110 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1111 | struct intel_shared_dpll *pll, | |
1112 | bool state) | |
040484af | 1113 | { |
040484af | 1114 | bool cur_state; |
5358901f | 1115 | struct intel_dpll_hw_state hw_state; |
040484af | 1116 | |
92b27b08 | 1117 | if (WARN (!pll, |
46edb027 | 1118 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1119 | return; |
ee7b9f93 | 1120 | |
5358901f | 1121 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1122 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1123 | "%s assertion failure (expected %s, current %s)\n", |
1124 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1125 | } |
040484af JB |
1126 | |
1127 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1128 | enum pipe pipe, bool state) | |
1129 | { | |
1130 | int reg; | |
1131 | u32 val; | |
1132 | bool cur_state; | |
ad80a810 PZ |
1133 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1134 | pipe); | |
040484af | 1135 | |
affa9354 PZ |
1136 | if (HAS_DDI(dev_priv->dev)) { |
1137 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1138 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1139 | val = I915_READ(reg); |
ad80a810 | 1140 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1141 | } else { |
1142 | reg = FDI_TX_CTL(pipe); | |
1143 | val = I915_READ(reg); | |
1144 | cur_state = !!(val & FDI_TX_ENABLE); | |
1145 | } | |
e2c719b7 | 1146 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1147 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1148 | state_string(state), state_string(cur_state)); | |
1149 | } | |
1150 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1151 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1152 | ||
1153 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1154 | enum pipe pipe, bool state) | |
1155 | { | |
1156 | int reg; | |
1157 | u32 val; | |
1158 | bool cur_state; | |
1159 | ||
d63fa0dc PZ |
1160 | reg = FDI_RX_CTL(pipe); |
1161 | val = I915_READ(reg); | |
1162 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1163 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1164 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1165 | state_string(state), state_string(cur_state)); | |
1166 | } | |
1167 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1168 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1169 | ||
1170 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1171 | enum pipe pipe) | |
1172 | { | |
1173 | int reg; | |
1174 | u32 val; | |
1175 | ||
1176 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1177 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1178 | return; |
1179 | ||
bf507ef7 | 1180 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1181 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1182 | return; |
1183 | ||
040484af JB |
1184 | reg = FDI_TX_CTL(pipe); |
1185 | val = I915_READ(reg); | |
e2c719b7 | 1186 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1187 | } |
1188 | ||
55607e8a DV |
1189 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1190 | enum pipe pipe, bool state) | |
040484af JB |
1191 | { |
1192 | int reg; | |
1193 | u32 val; | |
55607e8a | 1194 | bool cur_state; |
040484af JB |
1195 | |
1196 | reg = FDI_RX_CTL(pipe); | |
1197 | val = I915_READ(reg); | |
55607e8a | 1198 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1199 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1200 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1201 | state_string(state), state_string(cur_state)); | |
040484af JB |
1202 | } |
1203 | ||
b680c37a DV |
1204 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1205 | enum pipe pipe) | |
ea0760cf | 1206 | { |
bedd4dba JN |
1207 | struct drm_device *dev = dev_priv->dev; |
1208 | int pp_reg; | |
ea0760cf JB |
1209 | u32 val; |
1210 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1211 | bool locked = true; |
ea0760cf | 1212 | |
bedd4dba JN |
1213 | if (WARN_ON(HAS_DDI(dev))) |
1214 | return; | |
1215 | ||
1216 | if (HAS_PCH_SPLIT(dev)) { | |
1217 | u32 port_sel; | |
1218 | ||
ea0760cf | 1219 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1220 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1221 | ||
1222 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1223 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1224 | panel_pipe = PIPE_B; | |
1225 | /* XXX: else fix for eDP */ | |
1226 | } else if (IS_VALLEYVIEW(dev)) { | |
1227 | /* presumably write lock depends on pipe, not port select */ | |
1228 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1229 | panel_pipe = pipe; | |
ea0760cf JB |
1230 | } else { |
1231 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1232 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1233 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1234 | } |
1235 | ||
1236 | val = I915_READ(pp_reg); | |
1237 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1238 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1239 | locked = false; |
1240 | ||
e2c719b7 | 1241 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1242 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1243 | pipe_name(pipe)); |
ea0760cf JB |
1244 | } |
1245 | ||
93ce0ba6 JN |
1246 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1247 | enum pipe pipe, bool state) | |
1248 | { | |
1249 | struct drm_device *dev = dev_priv->dev; | |
1250 | bool cur_state; | |
1251 | ||
d9d82081 | 1252 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1253 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1254 | else |
5efb3e28 | 1255 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1256 | |
e2c719b7 | 1257 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1258 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1259 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1260 | } | |
1261 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1262 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1263 | ||
b840d907 JB |
1264 | void assert_pipe(struct drm_i915_private *dev_priv, |
1265 | enum pipe pipe, bool state) | |
b24e7179 JB |
1266 | { |
1267 | int reg; | |
1268 | u32 val; | |
63d7bbe9 | 1269 | bool cur_state; |
702e7a56 PZ |
1270 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1271 | pipe); | |
b24e7179 | 1272 | |
b6b5d049 VS |
1273 | /* if we need the pipe quirk it must be always on */ |
1274 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1275 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1276 | state = true; |
1277 | ||
f458ebbc | 1278 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1279 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1280 | cur_state = false; |
1281 | } else { | |
1282 | reg = PIPECONF(cpu_transcoder); | |
1283 | val = I915_READ(reg); | |
1284 | cur_state = !!(val & PIPECONF_ENABLE); | |
1285 | } | |
1286 | ||
e2c719b7 | 1287 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1288 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1289 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1290 | } |
1291 | ||
931872fc CW |
1292 | static void assert_plane(struct drm_i915_private *dev_priv, |
1293 | enum plane plane, bool state) | |
b24e7179 JB |
1294 | { |
1295 | int reg; | |
1296 | u32 val; | |
931872fc | 1297 | bool cur_state; |
b24e7179 JB |
1298 | |
1299 | reg = DSPCNTR(plane); | |
1300 | val = I915_READ(reg); | |
931872fc | 1301 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1302 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1303 | "plane %c assertion failure (expected %s, current %s)\n", |
1304 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1305 | } |
1306 | ||
931872fc CW |
1307 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1308 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1309 | ||
b24e7179 JB |
1310 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1311 | enum pipe pipe) | |
1312 | { | |
653e1026 | 1313 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1314 | int reg, i; |
1315 | u32 val; | |
1316 | int cur_pipe; | |
1317 | ||
653e1026 VS |
1318 | /* Primary planes are fixed to pipes on gen4+ */ |
1319 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1320 | reg = DSPCNTR(pipe); |
1321 | val = I915_READ(reg); | |
e2c719b7 | 1322 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1323 | "plane %c assertion failure, should be disabled but not\n", |
1324 | plane_name(pipe)); | |
19ec1358 | 1325 | return; |
28c05794 | 1326 | } |
19ec1358 | 1327 | |
b24e7179 | 1328 | /* Need to check both planes against the pipe */ |
055e393f | 1329 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1330 | reg = DSPCNTR(i); |
1331 | val = I915_READ(reg); | |
1332 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1333 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1334 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1335 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1336 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1337 | } |
1338 | } | |
1339 | ||
19332d7a JB |
1340 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe) | |
1342 | { | |
20674eef | 1343 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1344 | int reg, sprite; |
19332d7a JB |
1345 | u32 val; |
1346 | ||
7feb8b88 | 1347 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1348 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1349 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1350 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1351 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1352 | sprite, pipe_name(pipe)); | |
1353 | } | |
1354 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1355 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1356 | reg = SPCNTR(pipe, sprite); |
20674eef | 1357 | val = I915_READ(reg); |
e2c719b7 | 1358 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1359 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1360 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1361 | } |
1362 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1363 | reg = SPRCTL(pipe); | |
19332d7a | 1364 | val = I915_READ(reg); |
e2c719b7 | 1365 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1366 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1367 | plane_name(pipe), pipe_name(pipe)); |
1368 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1369 | reg = DVSCNTR(pipe); | |
19332d7a | 1370 | val = I915_READ(reg); |
e2c719b7 | 1371 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1372 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1373 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1374 | } |
1375 | } | |
1376 | ||
08c71e5e VS |
1377 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1378 | { | |
e2c719b7 | 1379 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1380 | drm_crtc_vblank_put(crtc); |
1381 | } | |
1382 | ||
89eff4be | 1383 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1384 | { |
1385 | u32 val; | |
1386 | bool enabled; | |
1387 | ||
e2c719b7 | 1388 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1389 | |
92f2584a JB |
1390 | val = I915_READ(PCH_DREF_CONTROL); |
1391 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1392 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1393 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1394 | } |
1395 | ||
ab9412ba DV |
1396 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1397 | enum pipe pipe) | |
92f2584a JB |
1398 | { |
1399 | int reg; | |
1400 | u32 val; | |
1401 | bool enabled; | |
1402 | ||
ab9412ba | 1403 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1404 | val = I915_READ(reg); |
1405 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1406 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1407 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1408 | pipe_name(pipe)); | |
92f2584a JB |
1409 | } |
1410 | ||
4e634389 KP |
1411 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1412 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1413 | { |
1414 | if ((val & DP_PORT_EN) == 0) | |
1415 | return false; | |
1416 | ||
1417 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1418 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1419 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1420 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1421 | return false; | |
44f37d1f CML |
1422 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1423 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1424 | return false; | |
f0575e92 KP |
1425 | } else { |
1426 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1427 | return false; | |
1428 | } | |
1429 | return true; | |
1430 | } | |
1431 | ||
1519b995 KP |
1432 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1433 | enum pipe pipe, u32 val) | |
1434 | { | |
dc0fa718 | 1435 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1436 | return false; |
1437 | ||
1438 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1439 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1440 | return false; |
44f37d1f CML |
1441 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1442 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1443 | return false; | |
1519b995 | 1444 | } else { |
dc0fa718 | 1445 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1446 | return false; |
1447 | } | |
1448 | return true; | |
1449 | } | |
1450 | ||
1451 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1452 | enum pipe pipe, u32 val) | |
1453 | { | |
1454 | if ((val & LVDS_PORT_EN) == 0) | |
1455 | return false; | |
1456 | ||
1457 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1458 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1459 | return false; | |
1460 | } else { | |
1461 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1462 | return false; | |
1463 | } | |
1464 | return true; | |
1465 | } | |
1466 | ||
1467 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1468 | enum pipe pipe, u32 val) | |
1469 | { | |
1470 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1471 | return false; | |
1472 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1473 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1474 | return false; | |
1475 | } else { | |
1476 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1477 | return false; | |
1478 | } | |
1479 | return true; | |
1480 | } | |
1481 | ||
291906f1 | 1482 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1483 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1484 | { |
47a05eca | 1485 | u32 val = I915_READ(reg); |
e2c719b7 | 1486 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1487 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1488 | reg, pipe_name(pipe)); |
de9a35ab | 1489 | |
e2c719b7 | 1490 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1491 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1492 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1493 | } |
1494 | ||
1495 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1496 | enum pipe pipe, int reg) | |
1497 | { | |
47a05eca | 1498 | u32 val = I915_READ(reg); |
e2c719b7 | 1499 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1500 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1501 | reg, pipe_name(pipe)); |
de9a35ab | 1502 | |
e2c719b7 | 1503 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1504 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1505 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1506 | } |
1507 | ||
1508 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1509 | enum pipe pipe) | |
1510 | { | |
1511 | int reg; | |
1512 | u32 val; | |
291906f1 | 1513 | |
f0575e92 KP |
1514 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1515 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1516 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1517 | |
1518 | reg = PCH_ADPA; | |
1519 | val = I915_READ(reg); | |
e2c719b7 | 1520 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1521 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1522 | pipe_name(pipe)); |
291906f1 JB |
1523 | |
1524 | reg = PCH_LVDS; | |
1525 | val = I915_READ(reg); | |
e2c719b7 | 1526 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1527 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1528 | pipe_name(pipe)); |
291906f1 | 1529 | |
e2debe91 PZ |
1530 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1531 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1532 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1533 | } |
1534 | ||
40e9cf64 JB |
1535 | static void intel_init_dpio(struct drm_device *dev) |
1536 | { | |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1538 | ||
1539 | if (!IS_VALLEYVIEW(dev)) | |
1540 | return; | |
1541 | ||
a09caddd CML |
1542 | /* |
1543 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1544 | * CHV x1 PHY (DP/HDMI D) | |
1545 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1546 | */ | |
1547 | if (IS_CHERRYVIEW(dev)) { | |
1548 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1549 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1550 | } else { | |
1551 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1552 | } | |
5382f5f3 JB |
1553 | } |
1554 | ||
d288f65f | 1555 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1556 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1557 | { |
426115cf DV |
1558 | struct drm_device *dev = crtc->base.dev; |
1559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1560 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1561 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1562 | |
426115cf | 1563 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1564 | |
1565 | /* No really, not for ILK+ */ | |
1566 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1567 | ||
1568 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1569 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1570 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1571 | |
426115cf DV |
1572 | I915_WRITE(reg, dpll); |
1573 | POSTING_READ(reg); | |
1574 | udelay(150); | |
1575 | ||
1576 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1577 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1578 | ||
d288f65f | 1579 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1580 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1581 | |
1582 | /* We do this three times for luck */ | |
426115cf | 1583 | I915_WRITE(reg, dpll); |
87442f73 DV |
1584 | POSTING_READ(reg); |
1585 | udelay(150); /* wait for warmup */ | |
426115cf | 1586 | I915_WRITE(reg, dpll); |
87442f73 DV |
1587 | POSTING_READ(reg); |
1588 | udelay(150); /* wait for warmup */ | |
426115cf | 1589 | I915_WRITE(reg, dpll); |
87442f73 DV |
1590 | POSTING_READ(reg); |
1591 | udelay(150); /* wait for warmup */ | |
1592 | } | |
1593 | ||
d288f65f | 1594 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1595 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1596 | { |
1597 | struct drm_device *dev = crtc->base.dev; | |
1598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1599 | int pipe = crtc->pipe; | |
1600 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1601 | u32 tmp; |
1602 | ||
1603 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1604 | ||
1605 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1606 | ||
1607 | mutex_lock(&dev_priv->dpio_lock); | |
1608 | ||
1609 | /* Enable back the 10bit clock to display controller */ | |
1610 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1611 | tmp |= DPIO_DCLKP_EN; | |
1612 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1613 | ||
1614 | /* | |
1615 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1616 | */ | |
1617 | udelay(1); | |
1618 | ||
1619 | /* Enable PLL */ | |
d288f65f | 1620 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1621 | |
1622 | /* Check PLL is locked */ | |
a11b0703 | 1623 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1624 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1625 | ||
a11b0703 | 1626 | /* not sure when this should be written */ |
d288f65f | 1627 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1628 | POSTING_READ(DPLL_MD(pipe)); |
1629 | ||
9d556c99 CML |
1630 | mutex_unlock(&dev_priv->dpio_lock); |
1631 | } | |
1632 | ||
1c4e0274 VS |
1633 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1634 | { | |
1635 | struct intel_crtc *crtc; | |
1636 | int count = 0; | |
1637 | ||
1638 | for_each_intel_crtc(dev, crtc) | |
1639 | count += crtc->active && | |
409ee761 | 1640 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1641 | |
1642 | return count; | |
1643 | } | |
1644 | ||
66e3d5c0 | 1645 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1646 | { |
66e3d5c0 DV |
1647 | struct drm_device *dev = crtc->base.dev; |
1648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1649 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1650 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1651 | |
66e3d5c0 | 1652 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1653 | |
63d7bbe9 | 1654 | /* No really, not for ILK+ */ |
3d13ef2e | 1655 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1656 | |
1657 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1658 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1659 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1660 | |
1c4e0274 VS |
1661 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1662 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1663 | /* | |
1664 | * It appears to be important that we don't enable this | |
1665 | * for the current pipe before otherwise configuring the | |
1666 | * PLL. No idea how this should be handled if multiple | |
1667 | * DVO outputs are enabled simultaneosly. | |
1668 | */ | |
1669 | dpll |= DPLL_DVO_2X_MODE; | |
1670 | I915_WRITE(DPLL(!crtc->pipe), | |
1671 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1672 | } | |
66e3d5c0 DV |
1673 | |
1674 | /* Wait for the clocks to stabilize. */ | |
1675 | POSTING_READ(reg); | |
1676 | udelay(150); | |
1677 | ||
1678 | if (INTEL_INFO(dev)->gen >= 4) { | |
1679 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1680 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1681 | } else { |
1682 | /* The pixel multiplier can only be updated once the | |
1683 | * DPLL is enabled and the clocks are stable. | |
1684 | * | |
1685 | * So write it again. | |
1686 | */ | |
1687 | I915_WRITE(reg, dpll); | |
1688 | } | |
63d7bbe9 JB |
1689 | |
1690 | /* We do this three times for luck */ | |
66e3d5c0 | 1691 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1692 | POSTING_READ(reg); |
1693 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1694 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1695 | POSTING_READ(reg); |
1696 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1697 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1698 | POSTING_READ(reg); |
1699 | udelay(150); /* wait for warmup */ | |
1700 | } | |
1701 | ||
1702 | /** | |
50b44a44 | 1703 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1704 | * @dev_priv: i915 private structure |
1705 | * @pipe: pipe PLL to disable | |
1706 | * | |
1707 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1708 | * | |
1709 | * Note! This is for pre-ILK only. | |
1710 | */ | |
1c4e0274 | 1711 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1712 | { |
1c4e0274 VS |
1713 | struct drm_device *dev = crtc->base.dev; |
1714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1715 | enum pipe pipe = crtc->pipe; | |
1716 | ||
1717 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1718 | if (IS_I830(dev) && | |
409ee761 | 1719 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1720 | intel_num_dvo_pipes(dev) == 1) { |
1721 | I915_WRITE(DPLL(PIPE_B), | |
1722 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1723 | I915_WRITE(DPLL(PIPE_A), | |
1724 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1725 | } | |
1726 | ||
b6b5d049 VS |
1727 | /* Don't disable pipe or pipe PLLs if needed */ |
1728 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1729 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1730 | return; |
1731 | ||
1732 | /* Make sure the pipe isn't still relying on us */ | |
1733 | assert_pipe_disabled(dev_priv, pipe); | |
1734 | ||
50b44a44 DV |
1735 | I915_WRITE(DPLL(pipe), 0); |
1736 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1737 | } |
1738 | ||
f6071166 JB |
1739 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1740 | { | |
1741 | u32 val = 0; | |
1742 | ||
1743 | /* Make sure the pipe isn't still relying on us */ | |
1744 | assert_pipe_disabled(dev_priv, pipe); | |
1745 | ||
e5cbfbfb ID |
1746 | /* |
1747 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1748 | * The latter is needed for VGA hotplug / manual detection. | |
1749 | */ | |
f6071166 | 1750 | if (pipe == PIPE_B) |
e5cbfbfb | 1751 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1752 | I915_WRITE(DPLL(pipe), val); |
1753 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1754 | |
1755 | } | |
1756 | ||
1757 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1758 | { | |
d752048d | 1759 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1760 | u32 val; |
1761 | ||
a11b0703 VS |
1762 | /* Make sure the pipe isn't still relying on us */ |
1763 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1764 | |
a11b0703 | 1765 | /* Set PLL en = 0 */ |
d17ec4ce | 1766 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1767 | if (pipe != PIPE_A) |
1768 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1769 | I915_WRITE(DPLL(pipe), val); | |
1770 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1771 | |
1772 | mutex_lock(&dev_priv->dpio_lock); | |
1773 | ||
1774 | /* Disable 10bit clock to display controller */ | |
1775 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1776 | val &= ~DPIO_DCLKP_EN; | |
1777 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1778 | ||
61407f6d VS |
1779 | /* disable left/right clock distribution */ |
1780 | if (pipe != PIPE_B) { | |
1781 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1782 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1783 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1784 | } else { | |
1785 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1786 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1787 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1788 | } | |
1789 | ||
d752048d | 1790 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1791 | } |
1792 | ||
e4607fcf CML |
1793 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1794 | struct intel_digital_port *dport) | |
89b667f8 JB |
1795 | { |
1796 | u32 port_mask; | |
00fc31b7 | 1797 | int dpll_reg; |
89b667f8 | 1798 | |
e4607fcf CML |
1799 | switch (dport->port) { |
1800 | case PORT_B: | |
89b667f8 | 1801 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1802 | dpll_reg = DPLL(0); |
e4607fcf CML |
1803 | break; |
1804 | case PORT_C: | |
89b667f8 | 1805 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1806 | dpll_reg = DPLL(0); |
1807 | break; | |
1808 | case PORT_D: | |
1809 | port_mask = DPLL_PORTD_READY_MASK; | |
1810 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1811 | break; |
1812 | default: | |
1813 | BUG(); | |
1814 | } | |
89b667f8 | 1815 | |
00fc31b7 | 1816 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1817 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1818 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1819 | } |
1820 | ||
b14b1055 DV |
1821 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1822 | { | |
1823 | struct drm_device *dev = crtc->base.dev; | |
1824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1825 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1826 | ||
be19f0ff CW |
1827 | if (WARN_ON(pll == NULL)) |
1828 | return; | |
1829 | ||
3e369b76 | 1830 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1831 | if (pll->active == 0) { |
1832 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1833 | WARN_ON(pll->on); | |
1834 | assert_shared_dpll_disabled(dev_priv, pll); | |
1835 | ||
1836 | pll->mode_set(dev_priv, pll); | |
1837 | } | |
1838 | } | |
1839 | ||
92f2584a | 1840 | /** |
85b3894f | 1841 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1842 | * @dev_priv: i915 private structure |
1843 | * @pipe: pipe PLL to enable | |
1844 | * | |
1845 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1846 | * drives the transcoder clock. | |
1847 | */ | |
85b3894f | 1848 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1849 | { |
3d13ef2e DL |
1850 | struct drm_device *dev = crtc->base.dev; |
1851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1852 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1853 | |
87a875bb | 1854 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1855 | return; |
1856 | ||
3e369b76 | 1857 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1858 | return; |
ee7b9f93 | 1859 | |
74dd6928 | 1860 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1861 | pll->name, pll->active, pll->on, |
e2b78267 | 1862 | crtc->base.base.id); |
92f2584a | 1863 | |
cdbd2316 DV |
1864 | if (pll->active++) { |
1865 | WARN_ON(!pll->on); | |
e9d6944e | 1866 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1867 | return; |
1868 | } | |
f4a091c7 | 1869 | WARN_ON(pll->on); |
ee7b9f93 | 1870 | |
bd2bb1b9 PZ |
1871 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1872 | ||
46edb027 | 1873 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1874 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1875 | pll->on = true; |
92f2584a JB |
1876 | } |
1877 | ||
f6daaec2 | 1878 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1879 | { |
3d13ef2e DL |
1880 | struct drm_device *dev = crtc->base.dev; |
1881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1882 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1883 | |
92f2584a | 1884 | /* PCH only available on ILK+ */ |
3d13ef2e | 1885 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1886 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1887 | return; |
92f2584a | 1888 | |
3e369b76 | 1889 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1890 | return; |
7a419866 | 1891 | |
46edb027 DV |
1892 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1893 | pll->name, pll->active, pll->on, | |
e2b78267 | 1894 | crtc->base.base.id); |
7a419866 | 1895 | |
48da64a8 | 1896 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1897 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1898 | return; |
1899 | } | |
1900 | ||
e9d6944e | 1901 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1902 | WARN_ON(!pll->on); |
cdbd2316 | 1903 | if (--pll->active) |
7a419866 | 1904 | return; |
ee7b9f93 | 1905 | |
46edb027 | 1906 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1907 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1908 | pll->on = false; |
bd2bb1b9 PZ |
1909 | |
1910 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1911 | } |
1912 | ||
b8a4f404 PZ |
1913 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1914 | enum pipe pipe) | |
040484af | 1915 | { |
23670b32 | 1916 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1917 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1918 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1919 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1920 | |
1921 | /* PCH only available on ILK+ */ | |
55522f37 | 1922 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1923 | |
1924 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1925 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1926 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1927 | |
1928 | /* FDI must be feeding us bits for PCH ports */ | |
1929 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1930 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1931 | ||
23670b32 DV |
1932 | if (HAS_PCH_CPT(dev)) { |
1933 | /* Workaround: Set the timing override bit before enabling the | |
1934 | * pch transcoder. */ | |
1935 | reg = TRANS_CHICKEN2(pipe); | |
1936 | val = I915_READ(reg); | |
1937 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1938 | I915_WRITE(reg, val); | |
59c859d6 | 1939 | } |
23670b32 | 1940 | |
ab9412ba | 1941 | reg = PCH_TRANSCONF(pipe); |
040484af | 1942 | val = I915_READ(reg); |
5f7f726d | 1943 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1944 | |
1945 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1946 | /* | |
1947 | * make the BPC in transcoder be consistent with | |
1948 | * that in pipeconf reg. | |
1949 | */ | |
dfd07d72 DV |
1950 | val &= ~PIPECONF_BPC_MASK; |
1951 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1952 | } |
5f7f726d PZ |
1953 | |
1954 | val &= ~TRANS_INTERLACE_MASK; | |
1955 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1956 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1957 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1958 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1959 | else | |
1960 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1961 | else |
1962 | val |= TRANS_PROGRESSIVE; | |
1963 | ||
040484af JB |
1964 | I915_WRITE(reg, val | TRANS_ENABLE); |
1965 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1966 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1967 | } |
1968 | ||
8fb033d7 | 1969 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1970 | enum transcoder cpu_transcoder) |
040484af | 1971 | { |
8fb033d7 | 1972 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1973 | |
1974 | /* PCH only available on ILK+ */ | |
55522f37 | 1975 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1976 | |
8fb033d7 | 1977 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1978 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1979 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1980 | |
223a6fdf PZ |
1981 | /* Workaround: set timing override bit. */ |
1982 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1983 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1984 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1985 | ||
25f3ef11 | 1986 | val = TRANS_ENABLE; |
937bb610 | 1987 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1988 | |
9a76b1c6 PZ |
1989 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1990 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1991 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1992 | else |
1993 | val |= TRANS_PROGRESSIVE; | |
1994 | ||
ab9412ba DV |
1995 | I915_WRITE(LPT_TRANSCONF, val); |
1996 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1997 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1998 | } |
1999 | ||
b8a4f404 PZ |
2000 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2001 | enum pipe pipe) | |
040484af | 2002 | { |
23670b32 DV |
2003 | struct drm_device *dev = dev_priv->dev; |
2004 | uint32_t reg, val; | |
040484af JB |
2005 | |
2006 | /* FDI relies on the transcoder */ | |
2007 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2008 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2009 | ||
291906f1 JB |
2010 | /* Ports must be off as well */ |
2011 | assert_pch_ports_disabled(dev_priv, pipe); | |
2012 | ||
ab9412ba | 2013 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2014 | val = I915_READ(reg); |
2015 | val &= ~TRANS_ENABLE; | |
2016 | I915_WRITE(reg, val); | |
2017 | /* wait for PCH transcoder off, transcoder state */ | |
2018 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2019 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2020 | |
2021 | if (!HAS_PCH_IBX(dev)) { | |
2022 | /* Workaround: Clear the timing override chicken bit again. */ | |
2023 | reg = TRANS_CHICKEN2(pipe); | |
2024 | val = I915_READ(reg); | |
2025 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2026 | I915_WRITE(reg, val); | |
2027 | } | |
040484af JB |
2028 | } |
2029 | ||
ab4d966c | 2030 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2031 | { |
8fb033d7 PZ |
2032 | u32 val; |
2033 | ||
ab9412ba | 2034 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2035 | val &= ~TRANS_ENABLE; |
ab9412ba | 2036 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2037 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2038 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2039 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2040 | |
2041 | /* Workaround: clear timing override bit. */ | |
2042 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2043 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2044 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2045 | } |
2046 | ||
b24e7179 | 2047 | /** |
309cfea8 | 2048 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2049 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2050 | * |
0372264a | 2051 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2052 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2053 | */ |
e1fdc473 | 2054 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2055 | { |
0372264a PZ |
2056 | struct drm_device *dev = crtc->base.dev; |
2057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2058 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2059 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2060 | pipe); | |
1a240d4d | 2061 | enum pipe pch_transcoder; |
b24e7179 JB |
2062 | int reg; |
2063 | u32 val; | |
2064 | ||
58c6eaa2 | 2065 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2066 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2067 | assert_sprites_disabled(dev_priv, pipe); |
2068 | ||
681e5811 | 2069 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2070 | pch_transcoder = TRANSCODER_A; |
2071 | else | |
2072 | pch_transcoder = pipe; | |
2073 | ||
b24e7179 JB |
2074 | /* |
2075 | * A pipe without a PLL won't actually be able to drive bits from | |
2076 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2077 | * need the check. | |
2078 | */ | |
2079 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2080 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2081 | assert_dsi_pll_enabled(dev_priv); |
2082 | else | |
2083 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2084 | else { |
6e3c9717 | 2085 | if (crtc->config->has_pch_encoder) { |
040484af | 2086 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2087 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2088 | assert_fdi_tx_pll_enabled(dev_priv, |
2089 | (enum pipe) cpu_transcoder); | |
040484af JB |
2090 | } |
2091 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2092 | } | |
b24e7179 | 2093 | |
702e7a56 | 2094 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2095 | val = I915_READ(reg); |
7ad25d48 | 2096 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2097 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2098 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2099 | return; |
7ad25d48 | 2100 | } |
00d70b15 CW |
2101 | |
2102 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2103 | POSTING_READ(reg); |
b24e7179 JB |
2104 | } |
2105 | ||
2106 | /** | |
309cfea8 | 2107 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2108 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2109 | * |
575f7ab7 VS |
2110 | * Disable the pipe of @crtc, making sure that various hardware |
2111 | * specific requirements are met, if applicable, e.g. plane | |
2112 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2113 | * |
2114 | * Will wait until the pipe has shut down before returning. | |
2115 | */ | |
575f7ab7 | 2116 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2117 | { |
575f7ab7 | 2118 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2119 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2120 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2121 | int reg; |
2122 | u32 val; | |
2123 | ||
2124 | /* | |
2125 | * Make sure planes won't keep trying to pump pixels to us, | |
2126 | * or we might hang the display. | |
2127 | */ | |
2128 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2129 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2130 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2131 | |
702e7a56 | 2132 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2133 | val = I915_READ(reg); |
00d70b15 CW |
2134 | if ((val & PIPECONF_ENABLE) == 0) |
2135 | return; | |
2136 | ||
67adc644 VS |
2137 | /* |
2138 | * Double wide has implications for planes | |
2139 | * so best keep it disabled when not needed. | |
2140 | */ | |
6e3c9717 | 2141 | if (crtc->config->double_wide) |
67adc644 VS |
2142 | val &= ~PIPECONF_DOUBLE_WIDE; |
2143 | ||
2144 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2145 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2146 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2147 | val &= ~PIPECONF_ENABLE; |
2148 | ||
2149 | I915_WRITE(reg, val); | |
2150 | if ((val & PIPECONF_ENABLE) == 0) | |
2151 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2152 | } |
2153 | ||
d74362c9 KP |
2154 | /* |
2155 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2156 | * trigger in order to latch. The display address reg provides this. | |
2157 | */ | |
1dba99f4 VS |
2158 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2159 | enum plane plane) | |
d74362c9 | 2160 | { |
3d13ef2e DL |
2161 | struct drm_device *dev = dev_priv->dev; |
2162 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2163 | |
2164 | I915_WRITE(reg, I915_READ(reg)); | |
2165 | POSTING_READ(reg); | |
d74362c9 KP |
2166 | } |
2167 | ||
b24e7179 | 2168 | /** |
262ca2b0 | 2169 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2170 | * @plane: plane to be enabled |
2171 | * @crtc: crtc for the plane | |
b24e7179 | 2172 | * |
fdd508a6 | 2173 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2174 | */ |
fdd508a6 VS |
2175 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2176 | struct drm_crtc *crtc) | |
b24e7179 | 2177 | { |
fdd508a6 VS |
2178 | struct drm_device *dev = plane->dev; |
2179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2181 | |
2182 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2183 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2184 | |
98ec7739 VS |
2185 | if (intel_crtc->primary_enabled) |
2186 | return; | |
0037f71c | 2187 | |
4c445e0e | 2188 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2189 | |
fdd508a6 VS |
2190 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2191 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2192 | |
2193 | /* | |
2194 | * BDW signals flip done immediately if the plane | |
2195 | * is disabled, even if the plane enable is already | |
2196 | * armed to occur at the next vblank :( | |
2197 | */ | |
2198 | if (IS_BROADWELL(dev)) | |
2199 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2200 | } |
2201 | ||
b24e7179 | 2202 | /** |
262ca2b0 | 2203 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2204 | * @plane: plane to be disabled |
2205 | * @crtc: crtc for the plane | |
b24e7179 | 2206 | * |
fdd508a6 | 2207 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2208 | */ |
fdd508a6 VS |
2209 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2210 | struct drm_crtc *crtc) | |
b24e7179 | 2211 | { |
fdd508a6 VS |
2212 | struct drm_device *dev = plane->dev; |
2213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2215 | ||
32b7eeec MR |
2216 | if (WARN_ON(!intel_crtc->active)) |
2217 | return; | |
b24e7179 | 2218 | |
98ec7739 VS |
2219 | if (!intel_crtc->primary_enabled) |
2220 | return; | |
0037f71c | 2221 | |
4c445e0e | 2222 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2223 | |
fdd508a6 VS |
2224 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2225 | crtc->x, crtc->y); | |
b24e7179 JB |
2226 | } |
2227 | ||
693db184 CW |
2228 | static bool need_vtd_wa(struct drm_device *dev) |
2229 | { | |
2230 | #ifdef CONFIG_INTEL_IOMMU | |
2231 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2232 | return true; | |
2233 | #endif | |
2234 | return false; | |
2235 | } | |
2236 | ||
50470bb0 | 2237 | unsigned int |
6761dd31 TU |
2238 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2239 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2240 | { |
6761dd31 TU |
2241 | unsigned int tile_height; |
2242 | uint32_t pixel_bytes; | |
a57ce0b2 | 2243 | |
b5d0e9bf DL |
2244 | switch (fb_format_modifier) { |
2245 | case DRM_FORMAT_MOD_NONE: | |
2246 | tile_height = 1; | |
2247 | break; | |
2248 | case I915_FORMAT_MOD_X_TILED: | |
2249 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2250 | break; | |
2251 | case I915_FORMAT_MOD_Y_TILED: | |
2252 | tile_height = 32; | |
2253 | break; | |
2254 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2255 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2256 | switch (pixel_bytes) { | |
b5d0e9bf | 2257 | default: |
6761dd31 | 2258 | case 1: |
b5d0e9bf DL |
2259 | tile_height = 64; |
2260 | break; | |
6761dd31 TU |
2261 | case 2: |
2262 | case 4: | |
b5d0e9bf DL |
2263 | tile_height = 32; |
2264 | break; | |
6761dd31 | 2265 | case 8: |
b5d0e9bf DL |
2266 | tile_height = 16; |
2267 | break; | |
6761dd31 | 2268 | case 16: |
b5d0e9bf DL |
2269 | WARN_ONCE(1, |
2270 | "128-bit pixels are not supported for display!"); | |
2271 | tile_height = 16; | |
2272 | break; | |
2273 | } | |
2274 | break; | |
2275 | default: | |
2276 | MISSING_CASE(fb_format_modifier); | |
2277 | tile_height = 1; | |
2278 | break; | |
2279 | } | |
091df6cb | 2280 | |
6761dd31 TU |
2281 | return tile_height; |
2282 | } | |
2283 | ||
2284 | unsigned int | |
2285 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2286 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2287 | { | |
2288 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2289 | fb_format_modifier)); | |
a57ce0b2 JB |
2290 | } |
2291 | ||
f64b98cd TU |
2292 | static int |
2293 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2294 | const struct drm_plane_state *plane_state) | |
2295 | { | |
50470bb0 TU |
2296 | struct intel_rotation_info *info = &view->rotation_info; |
2297 | static const struct i915_ggtt_view rotated_view = | |
2298 | { .type = I915_GGTT_VIEW_ROTATED }; | |
2299 | ||
f64b98cd TU |
2300 | *view = i915_ggtt_view_normal; |
2301 | ||
50470bb0 TU |
2302 | if (!plane_state) |
2303 | return 0; | |
2304 | ||
121920fa | 2305 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2306 | return 0; |
2307 | ||
2308 | *view = rotated_view; | |
2309 | ||
2310 | info->height = fb->height; | |
2311 | info->pixel_format = fb->pixel_format; | |
2312 | info->pitch = fb->pitches[0]; | |
2313 | info->fb_modifier = fb->modifier[0]; | |
2314 | ||
2315 | if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED || | |
2316 | info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) { | |
2317 | DRM_DEBUG_KMS( | |
2318 | "Y or Yf tiling is needed for 90/270 rotation!\n"); | |
2319 | return -EINVAL; | |
2320 | } | |
2321 | ||
f64b98cd TU |
2322 | return 0; |
2323 | } | |
2324 | ||
127bd2ac | 2325 | int |
850c4cdc TU |
2326 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2327 | struct drm_framebuffer *fb, | |
82bc3b2d | 2328 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2329 | struct intel_engine_cs *pipelined) |
6b95a207 | 2330 | { |
850c4cdc | 2331 | struct drm_device *dev = fb->dev; |
ce453d81 | 2332 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2333 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2334 | struct i915_ggtt_view view; |
6b95a207 KH |
2335 | u32 alignment; |
2336 | int ret; | |
2337 | ||
ebcdd39e MR |
2338 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2339 | ||
7b911adc TU |
2340 | switch (fb->modifier[0]) { |
2341 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2342 | if (INTEL_INFO(dev)->gen >= 9) |
2343 | alignment = 256 * 1024; | |
2344 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2345 | alignment = 128 * 1024; |
a6c45cf0 | 2346 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2347 | alignment = 4 * 1024; |
2348 | else | |
2349 | alignment = 64 * 1024; | |
6b95a207 | 2350 | break; |
7b911adc | 2351 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2352 | if (INTEL_INFO(dev)->gen >= 9) |
2353 | alignment = 256 * 1024; | |
2354 | else { | |
2355 | /* pin() will align the object as required by fence */ | |
2356 | alignment = 0; | |
2357 | } | |
6b95a207 | 2358 | break; |
7b911adc | 2359 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2360 | case I915_FORMAT_MOD_Yf_TILED: |
2361 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2362 | "Y tiling bo slipped through, driver bug!\n")) | |
2363 | return -EINVAL; | |
2364 | alignment = 1 * 1024 * 1024; | |
2365 | break; | |
6b95a207 | 2366 | default: |
7b911adc TU |
2367 | MISSING_CASE(fb->modifier[0]); |
2368 | return -EINVAL; | |
6b95a207 KH |
2369 | } |
2370 | ||
f64b98cd TU |
2371 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2372 | if (ret) | |
2373 | return ret; | |
2374 | ||
693db184 CW |
2375 | /* Note that the w/a also requires 64 PTE of padding following the |
2376 | * bo. We currently fill all unused PTE with the shadow page and so | |
2377 | * we should always have valid PTE following the scanout preventing | |
2378 | * the VT-d warning. | |
2379 | */ | |
2380 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2381 | alignment = 256 * 1024; | |
2382 | ||
d6dd6843 PZ |
2383 | /* |
2384 | * Global gtt pte registers are special registers which actually forward | |
2385 | * writes to a chunk of system memory. Which means that there is no risk | |
2386 | * that the register values disappear as soon as we call | |
2387 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2388 | * pin/unpin/fence and not more. | |
2389 | */ | |
2390 | intel_runtime_pm_get(dev_priv); | |
2391 | ||
ce453d81 | 2392 | dev_priv->mm.interruptible = false; |
e6617330 | 2393 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2394 | &view); |
48b956c5 | 2395 | if (ret) |
ce453d81 | 2396 | goto err_interruptible; |
6b95a207 KH |
2397 | |
2398 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2399 | * fence, whereas 965+ only requires a fence if using | |
2400 | * framebuffer compression. For simplicity, we always install | |
2401 | * a fence as the cost is not that onerous. | |
2402 | */ | |
06d98131 | 2403 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2404 | if (ret) |
2405 | goto err_unpin; | |
1690e1eb | 2406 | |
9a5a53b3 | 2407 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2408 | |
ce453d81 | 2409 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2410 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2411 | return 0; |
48b956c5 CW |
2412 | |
2413 | err_unpin: | |
f64b98cd | 2414 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2415 | err_interruptible: |
2416 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2417 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2418 | return ret; |
6b95a207 KH |
2419 | } |
2420 | ||
82bc3b2d TU |
2421 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2422 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2423 | { |
82bc3b2d | 2424 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2425 | struct i915_ggtt_view view; |
2426 | int ret; | |
82bc3b2d | 2427 | |
ebcdd39e MR |
2428 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2429 | ||
f64b98cd TU |
2430 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2431 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2432 | ||
1690e1eb | 2433 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2434 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2435 | } |
2436 | ||
c2c75131 DV |
2437 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2438 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2439 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2440 | unsigned int tiling_mode, | |
2441 | unsigned int cpp, | |
2442 | unsigned int pitch) | |
c2c75131 | 2443 | { |
bc752862 CW |
2444 | if (tiling_mode != I915_TILING_NONE) { |
2445 | unsigned int tile_rows, tiles; | |
c2c75131 | 2446 | |
bc752862 CW |
2447 | tile_rows = *y / 8; |
2448 | *y %= 8; | |
c2c75131 | 2449 | |
bc752862 CW |
2450 | tiles = *x / (512/cpp); |
2451 | *x %= 512/cpp; | |
2452 | ||
2453 | return tile_rows * pitch * 8 + tiles * 4096; | |
2454 | } else { | |
2455 | unsigned int offset; | |
2456 | ||
2457 | offset = *y * pitch + *x * cpp; | |
2458 | *y = 0; | |
2459 | *x = (offset & 4095) / cpp; | |
2460 | return offset & -4096; | |
2461 | } | |
c2c75131 DV |
2462 | } |
2463 | ||
b35d63fa | 2464 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2465 | { |
2466 | switch (format) { | |
2467 | case DISPPLANE_8BPP: | |
2468 | return DRM_FORMAT_C8; | |
2469 | case DISPPLANE_BGRX555: | |
2470 | return DRM_FORMAT_XRGB1555; | |
2471 | case DISPPLANE_BGRX565: | |
2472 | return DRM_FORMAT_RGB565; | |
2473 | default: | |
2474 | case DISPPLANE_BGRX888: | |
2475 | return DRM_FORMAT_XRGB8888; | |
2476 | case DISPPLANE_RGBX888: | |
2477 | return DRM_FORMAT_XBGR8888; | |
2478 | case DISPPLANE_BGRX101010: | |
2479 | return DRM_FORMAT_XRGB2101010; | |
2480 | case DISPPLANE_RGBX101010: | |
2481 | return DRM_FORMAT_XBGR2101010; | |
2482 | } | |
2483 | } | |
2484 | ||
bc8d7dff DL |
2485 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2486 | { | |
2487 | switch (format) { | |
2488 | case PLANE_CTL_FORMAT_RGB_565: | |
2489 | return DRM_FORMAT_RGB565; | |
2490 | default: | |
2491 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2492 | if (rgb_order) { | |
2493 | if (alpha) | |
2494 | return DRM_FORMAT_ABGR8888; | |
2495 | else | |
2496 | return DRM_FORMAT_XBGR8888; | |
2497 | } else { | |
2498 | if (alpha) | |
2499 | return DRM_FORMAT_ARGB8888; | |
2500 | else | |
2501 | return DRM_FORMAT_XRGB8888; | |
2502 | } | |
2503 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2504 | if (rgb_order) | |
2505 | return DRM_FORMAT_XBGR2101010; | |
2506 | else | |
2507 | return DRM_FORMAT_XRGB2101010; | |
2508 | } | |
2509 | } | |
2510 | ||
5724dbd1 | 2511 | static bool |
f6936e29 DV |
2512 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2513 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2514 | { |
2515 | struct drm_device *dev = crtc->base.dev; | |
2516 | struct drm_i915_gem_object *obj = NULL; | |
2517 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2518 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2519 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2520 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2521 | PAGE_SIZE); | |
2522 | ||
2523 | size_aligned -= base_aligned; | |
46f297fb | 2524 | |
ff2652ea CW |
2525 | if (plane_config->size == 0) |
2526 | return false; | |
2527 | ||
f37b5c2b DV |
2528 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2529 | base_aligned, | |
2530 | base_aligned, | |
2531 | size_aligned); | |
46f297fb | 2532 | if (!obj) |
484b41dd | 2533 | return false; |
46f297fb | 2534 | |
49af449b DL |
2535 | obj->tiling_mode = plane_config->tiling; |
2536 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2537 | obj->stride = fb->pitches[0]; |
46f297fb | 2538 | |
6bf129df DL |
2539 | mode_cmd.pixel_format = fb->pixel_format; |
2540 | mode_cmd.width = fb->width; | |
2541 | mode_cmd.height = fb->height; | |
2542 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2543 | mode_cmd.modifier[0] = fb->modifier[0]; |
2544 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2545 | |
2546 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2547 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2548 | &mode_cmd, obj)) { |
46f297fb JB |
2549 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2550 | goto out_unref_obj; | |
2551 | } | |
46f297fb | 2552 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2553 | |
f6936e29 | 2554 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2555 | return true; |
46f297fb JB |
2556 | |
2557 | out_unref_obj: | |
2558 | drm_gem_object_unreference(&obj->base); | |
2559 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2560 | return false; |
2561 | } | |
2562 | ||
afd65eb4 MR |
2563 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2564 | static void | |
2565 | update_state_fb(struct drm_plane *plane) | |
2566 | { | |
2567 | if (plane->fb == plane->state->fb) | |
2568 | return; | |
2569 | ||
2570 | if (plane->state->fb) | |
2571 | drm_framebuffer_unreference(plane->state->fb); | |
2572 | plane->state->fb = plane->fb; | |
2573 | if (plane->state->fb) | |
2574 | drm_framebuffer_reference(plane->state->fb); | |
2575 | } | |
2576 | ||
5724dbd1 | 2577 | static void |
f6936e29 DV |
2578 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2579 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2580 | { |
2581 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2582 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2583 | struct drm_crtc *c; |
2584 | struct intel_crtc *i; | |
2ff8fde1 | 2585 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2586 | struct drm_plane *primary = intel_crtc->base.primary; |
2587 | struct drm_framebuffer *fb; | |
484b41dd | 2588 | |
2d14030b | 2589 | if (!plane_config->fb) |
484b41dd JB |
2590 | return; |
2591 | ||
f6936e29 | 2592 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2593 | fb = &plane_config->fb->base; |
2594 | goto valid_fb; | |
f55548b5 | 2595 | } |
484b41dd | 2596 | |
2d14030b | 2597 | kfree(plane_config->fb); |
484b41dd JB |
2598 | |
2599 | /* | |
2600 | * Failed to alloc the obj, check to see if we should share | |
2601 | * an fb with another CRTC instead | |
2602 | */ | |
70e1e0ec | 2603 | for_each_crtc(dev, c) { |
484b41dd JB |
2604 | i = to_intel_crtc(c); |
2605 | ||
2606 | if (c == &intel_crtc->base) | |
2607 | continue; | |
2608 | ||
2ff8fde1 MR |
2609 | if (!i->active) |
2610 | continue; | |
2611 | ||
88595ac9 DV |
2612 | fb = c->primary->fb; |
2613 | if (!fb) | |
484b41dd JB |
2614 | continue; |
2615 | ||
88595ac9 | 2616 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2617 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2618 | drm_framebuffer_reference(fb); |
2619 | goto valid_fb; | |
484b41dd JB |
2620 | } |
2621 | } | |
88595ac9 DV |
2622 | |
2623 | return; | |
2624 | ||
2625 | valid_fb: | |
2626 | obj = intel_fb_obj(fb); | |
2627 | if (obj->tiling_mode != I915_TILING_NONE) | |
2628 | dev_priv->preserve_bios_swizzle = true; | |
2629 | ||
2630 | primary->fb = fb; | |
2631 | primary->state->crtc = &intel_crtc->base; | |
2632 | primary->crtc = &intel_crtc->base; | |
2633 | update_state_fb(primary); | |
2634 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2635 | } |
2636 | ||
29b9bde6 DV |
2637 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2638 | struct drm_framebuffer *fb, | |
2639 | int x, int y) | |
81255565 JB |
2640 | { |
2641 | struct drm_device *dev = crtc->dev; | |
2642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2644 | struct drm_i915_gem_object *obj; |
81255565 | 2645 | int plane = intel_crtc->plane; |
e506a0c6 | 2646 | unsigned long linear_offset; |
81255565 | 2647 | u32 dspcntr; |
f45651ba | 2648 | u32 reg = DSPCNTR(plane); |
48404c1e | 2649 | int pixel_size; |
f45651ba | 2650 | |
fdd508a6 VS |
2651 | if (!intel_crtc->primary_enabled) { |
2652 | I915_WRITE(reg, 0); | |
2653 | if (INTEL_INFO(dev)->gen >= 4) | |
2654 | I915_WRITE(DSPSURF(plane), 0); | |
2655 | else | |
2656 | I915_WRITE(DSPADDR(plane), 0); | |
2657 | POSTING_READ(reg); | |
2658 | return; | |
2659 | } | |
2660 | ||
c9ba6fad VS |
2661 | obj = intel_fb_obj(fb); |
2662 | if (WARN_ON(obj == NULL)) | |
2663 | return; | |
2664 | ||
2665 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2666 | ||
f45651ba VS |
2667 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2668 | ||
fdd508a6 | 2669 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2670 | |
2671 | if (INTEL_INFO(dev)->gen < 4) { | |
2672 | if (intel_crtc->pipe == PIPE_B) | |
2673 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2674 | ||
2675 | /* pipesrc and dspsize control the size that is scaled from, | |
2676 | * which should always be the user's requested size. | |
2677 | */ | |
2678 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2679 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2680 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2681 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2682 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2683 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2684 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2685 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2686 | I915_WRITE(PRIMPOS(plane), 0); |
2687 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2688 | } |
81255565 | 2689 | |
57779d06 VS |
2690 | switch (fb->pixel_format) { |
2691 | case DRM_FORMAT_C8: | |
81255565 JB |
2692 | dspcntr |= DISPPLANE_8BPP; |
2693 | break; | |
57779d06 VS |
2694 | case DRM_FORMAT_XRGB1555: |
2695 | case DRM_FORMAT_ARGB1555: | |
2696 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2697 | break; |
57779d06 VS |
2698 | case DRM_FORMAT_RGB565: |
2699 | dspcntr |= DISPPLANE_BGRX565; | |
2700 | break; | |
2701 | case DRM_FORMAT_XRGB8888: | |
2702 | case DRM_FORMAT_ARGB8888: | |
2703 | dspcntr |= DISPPLANE_BGRX888; | |
2704 | break; | |
2705 | case DRM_FORMAT_XBGR8888: | |
2706 | case DRM_FORMAT_ABGR8888: | |
2707 | dspcntr |= DISPPLANE_RGBX888; | |
2708 | break; | |
2709 | case DRM_FORMAT_XRGB2101010: | |
2710 | case DRM_FORMAT_ARGB2101010: | |
2711 | dspcntr |= DISPPLANE_BGRX101010; | |
2712 | break; | |
2713 | case DRM_FORMAT_XBGR2101010: | |
2714 | case DRM_FORMAT_ABGR2101010: | |
2715 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2716 | break; |
2717 | default: | |
baba133a | 2718 | BUG(); |
81255565 | 2719 | } |
57779d06 | 2720 | |
f45651ba VS |
2721 | if (INTEL_INFO(dev)->gen >= 4 && |
2722 | obj->tiling_mode != I915_TILING_NONE) | |
2723 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2724 | |
de1aa629 VS |
2725 | if (IS_G4X(dev)) |
2726 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2727 | ||
b9897127 | 2728 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2729 | |
c2c75131 DV |
2730 | if (INTEL_INFO(dev)->gen >= 4) { |
2731 | intel_crtc->dspaddr_offset = | |
bc752862 | 2732 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2733 | pixel_size, |
bc752862 | 2734 | fb->pitches[0]); |
c2c75131 DV |
2735 | linear_offset -= intel_crtc->dspaddr_offset; |
2736 | } else { | |
e506a0c6 | 2737 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2738 | } |
e506a0c6 | 2739 | |
8e7d688b | 2740 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2741 | dspcntr |= DISPPLANE_ROTATE_180; |
2742 | ||
6e3c9717 ACO |
2743 | x += (intel_crtc->config->pipe_src_w - 1); |
2744 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2745 | |
2746 | /* Finding the last pixel of the last line of the display | |
2747 | data and adding to linear_offset*/ | |
2748 | linear_offset += | |
6e3c9717 ACO |
2749 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2750 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2751 | } |
2752 | ||
2753 | I915_WRITE(reg, dspcntr); | |
2754 | ||
01f2c773 | 2755 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2756 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2757 | I915_WRITE(DSPSURF(plane), |
2758 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2759 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2760 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2761 | } else |
f343c5f6 | 2762 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2763 | POSTING_READ(reg); |
17638cd6 JB |
2764 | } |
2765 | ||
29b9bde6 DV |
2766 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2767 | struct drm_framebuffer *fb, | |
2768 | int x, int y) | |
17638cd6 JB |
2769 | { |
2770 | struct drm_device *dev = crtc->dev; | |
2771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2773 | struct drm_i915_gem_object *obj; |
17638cd6 | 2774 | int plane = intel_crtc->plane; |
e506a0c6 | 2775 | unsigned long linear_offset; |
17638cd6 | 2776 | u32 dspcntr; |
f45651ba | 2777 | u32 reg = DSPCNTR(plane); |
48404c1e | 2778 | int pixel_size; |
f45651ba | 2779 | |
fdd508a6 VS |
2780 | if (!intel_crtc->primary_enabled) { |
2781 | I915_WRITE(reg, 0); | |
2782 | I915_WRITE(DSPSURF(plane), 0); | |
2783 | POSTING_READ(reg); | |
2784 | return; | |
2785 | } | |
2786 | ||
c9ba6fad VS |
2787 | obj = intel_fb_obj(fb); |
2788 | if (WARN_ON(obj == NULL)) | |
2789 | return; | |
2790 | ||
2791 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2792 | ||
f45651ba VS |
2793 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2794 | ||
fdd508a6 | 2795 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2796 | |
2797 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2798 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2799 | |
57779d06 VS |
2800 | switch (fb->pixel_format) { |
2801 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2802 | dspcntr |= DISPPLANE_8BPP; |
2803 | break; | |
57779d06 VS |
2804 | case DRM_FORMAT_RGB565: |
2805 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2806 | break; |
57779d06 VS |
2807 | case DRM_FORMAT_XRGB8888: |
2808 | case DRM_FORMAT_ARGB8888: | |
2809 | dspcntr |= DISPPLANE_BGRX888; | |
2810 | break; | |
2811 | case DRM_FORMAT_XBGR8888: | |
2812 | case DRM_FORMAT_ABGR8888: | |
2813 | dspcntr |= DISPPLANE_RGBX888; | |
2814 | break; | |
2815 | case DRM_FORMAT_XRGB2101010: | |
2816 | case DRM_FORMAT_ARGB2101010: | |
2817 | dspcntr |= DISPPLANE_BGRX101010; | |
2818 | break; | |
2819 | case DRM_FORMAT_XBGR2101010: | |
2820 | case DRM_FORMAT_ABGR2101010: | |
2821 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2822 | break; |
2823 | default: | |
baba133a | 2824 | BUG(); |
17638cd6 JB |
2825 | } |
2826 | ||
2827 | if (obj->tiling_mode != I915_TILING_NONE) | |
2828 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2829 | |
f45651ba | 2830 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2831 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2832 | |
b9897127 | 2833 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2834 | intel_crtc->dspaddr_offset = |
bc752862 | 2835 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2836 | pixel_size, |
bc752862 | 2837 | fb->pitches[0]); |
c2c75131 | 2838 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2839 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2840 | dspcntr |= DISPPLANE_ROTATE_180; |
2841 | ||
2842 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2843 | x += (intel_crtc->config->pipe_src_w - 1); |
2844 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2845 | |
2846 | /* Finding the last pixel of the last line of the display | |
2847 | data and adding to linear_offset*/ | |
2848 | linear_offset += | |
6e3c9717 ACO |
2849 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2850 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2851 | } |
2852 | } | |
2853 | ||
2854 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2855 | |
01f2c773 | 2856 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2857 | I915_WRITE(DSPSURF(plane), |
2858 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2859 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2860 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2861 | } else { | |
2862 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2863 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2864 | } | |
17638cd6 | 2865 | POSTING_READ(reg); |
17638cd6 JB |
2866 | } |
2867 | ||
b321803d DL |
2868 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2869 | uint32_t pixel_format) | |
2870 | { | |
2871 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2872 | ||
2873 | /* | |
2874 | * The stride is either expressed as a multiple of 64 bytes | |
2875 | * chunks for linear buffers or in number of tiles for tiled | |
2876 | * buffers. | |
2877 | */ | |
2878 | switch (fb_modifier) { | |
2879 | case DRM_FORMAT_MOD_NONE: | |
2880 | return 64; | |
2881 | case I915_FORMAT_MOD_X_TILED: | |
2882 | if (INTEL_INFO(dev)->gen == 2) | |
2883 | return 128; | |
2884 | return 512; | |
2885 | case I915_FORMAT_MOD_Y_TILED: | |
2886 | /* No need to check for old gens and Y tiling since this is | |
2887 | * about the display engine and those will be blocked before | |
2888 | * we get here. | |
2889 | */ | |
2890 | return 128; | |
2891 | case I915_FORMAT_MOD_Yf_TILED: | |
2892 | if (bits_per_pixel == 8) | |
2893 | return 64; | |
2894 | else | |
2895 | return 128; | |
2896 | default: | |
2897 | MISSING_CASE(fb_modifier); | |
2898 | return 64; | |
2899 | } | |
2900 | } | |
2901 | ||
121920fa TU |
2902 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2903 | struct drm_i915_gem_object *obj) | |
2904 | { | |
2905 | enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL; | |
2906 | ||
2907 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
2908 | view = I915_GGTT_VIEW_ROTATED; | |
2909 | ||
2910 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2911 | } | |
2912 | ||
70d21f0e DL |
2913 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2914 | struct drm_framebuffer *fb, | |
2915 | int x, int y) | |
2916 | { | |
2917 | struct drm_device *dev = crtc->dev; | |
2918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2920 | struct drm_i915_gem_object *obj; |
2921 | int pipe = intel_crtc->pipe; | |
b321803d | 2922 | u32 plane_ctl, stride_div; |
121920fa | 2923 | unsigned long surf_addr; |
70d21f0e DL |
2924 | |
2925 | if (!intel_crtc->primary_enabled) { | |
2926 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2927 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2928 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2929 | return; | |
2930 | } | |
2931 | ||
2932 | plane_ctl = PLANE_CTL_ENABLE | | |
2933 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2934 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2935 | ||
2936 | switch (fb->pixel_format) { | |
2937 | case DRM_FORMAT_RGB565: | |
2938 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2939 | break; | |
2940 | case DRM_FORMAT_XRGB8888: | |
2941 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2942 | break; | |
f75fb42a JN |
2943 | case DRM_FORMAT_ARGB8888: |
2944 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2945 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2946 | break; | |
70d21f0e DL |
2947 | case DRM_FORMAT_XBGR8888: |
2948 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2949 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2950 | break; | |
f75fb42a JN |
2951 | case DRM_FORMAT_ABGR8888: |
2952 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2953 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2954 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2955 | break; | |
70d21f0e DL |
2956 | case DRM_FORMAT_XRGB2101010: |
2957 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2958 | break; | |
2959 | case DRM_FORMAT_XBGR2101010: | |
2960 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2961 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2962 | break; | |
2963 | default: | |
2964 | BUG(); | |
2965 | } | |
2966 | ||
30af77c4 DV |
2967 | switch (fb->modifier[0]) { |
2968 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 2969 | break; |
30af77c4 | 2970 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 2971 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
2972 | break; |
2973 | case I915_FORMAT_MOD_Y_TILED: | |
2974 | plane_ctl |= PLANE_CTL_TILED_Y; | |
2975 | break; | |
2976 | case I915_FORMAT_MOD_Yf_TILED: | |
2977 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
2978 | break; |
2979 | default: | |
b321803d | 2980 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
2981 | } |
2982 | ||
2983 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
8e7d688b | 2984 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) |
1447dde0 | 2985 | plane_ctl |= PLANE_CTL_ROTATE_180; |
70d21f0e | 2986 | |
b321803d DL |
2987 | obj = intel_fb_obj(fb); |
2988 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
2989 | fb->pixel_format); | |
121920fa | 2990 | surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj); |
b321803d | 2991 | |
70d21f0e | 2992 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
70d21f0e DL |
2993 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
2994 | I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); | |
2995 | I915_WRITE(PLANE_SIZE(pipe, 0), | |
6e3c9717 ACO |
2996 | (intel_crtc->config->pipe_src_h - 1) << 16 | |
2997 | (intel_crtc->config->pipe_src_w - 1)); | |
b321803d | 2998 | I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div); |
121920fa | 2999 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3000 | |
3001 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3002 | } | |
3003 | ||
17638cd6 JB |
3004 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3005 | static int | |
3006 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3007 | int x, int y, enum mode_set_atomic state) | |
3008 | { | |
3009 | struct drm_device *dev = crtc->dev; | |
3010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3011 | |
6b8e6ed0 CW |
3012 | if (dev_priv->display.disable_fbc) |
3013 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3014 | |
29b9bde6 DV |
3015 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3016 | ||
3017 | return 0; | |
81255565 JB |
3018 | } |
3019 | ||
7514747d | 3020 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3021 | { |
96a02917 VS |
3022 | struct drm_crtc *crtc; |
3023 | ||
70e1e0ec | 3024 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3026 | enum plane plane = intel_crtc->plane; | |
3027 | ||
3028 | intel_prepare_page_flip(dev, plane); | |
3029 | intel_finish_page_flip_plane(dev, plane); | |
3030 | } | |
7514747d VS |
3031 | } |
3032 | ||
3033 | static void intel_update_primary_planes(struct drm_device *dev) | |
3034 | { | |
3035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3036 | struct drm_crtc *crtc; | |
96a02917 | 3037 | |
70e1e0ec | 3038 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3040 | ||
51fd371b | 3041 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3042 | /* |
3043 | * FIXME: Once we have proper support for primary planes (and | |
3044 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3045 | * a NULL crtc->primary->fb. |
947fdaad | 3046 | */ |
f4510a27 | 3047 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3048 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3049 | crtc->primary->fb, |
262ca2b0 MR |
3050 | crtc->x, |
3051 | crtc->y); | |
51fd371b | 3052 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3053 | } |
3054 | } | |
3055 | ||
7514747d VS |
3056 | void intel_prepare_reset(struct drm_device *dev) |
3057 | { | |
f98ce92f VS |
3058 | struct drm_i915_private *dev_priv = to_i915(dev); |
3059 | struct intel_crtc *crtc; | |
3060 | ||
7514747d VS |
3061 | /* no reset support for gen2 */ |
3062 | if (IS_GEN2(dev)) | |
3063 | return; | |
3064 | ||
3065 | /* reset doesn't touch the display */ | |
3066 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3067 | return; | |
3068 | ||
3069 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3070 | |
3071 | /* | |
3072 | * Disabling the crtcs gracefully seems nicer. Also the | |
3073 | * g33 docs say we should at least disable all the planes. | |
3074 | */ | |
3075 | for_each_intel_crtc(dev, crtc) { | |
3076 | if (crtc->active) | |
3077 | dev_priv->display.crtc_disable(&crtc->base); | |
3078 | } | |
7514747d VS |
3079 | } |
3080 | ||
3081 | void intel_finish_reset(struct drm_device *dev) | |
3082 | { | |
3083 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3084 | ||
3085 | /* | |
3086 | * Flips in the rings will be nuked by the reset, | |
3087 | * so complete all pending flips so that user space | |
3088 | * will get its events and not get stuck. | |
3089 | */ | |
3090 | intel_complete_page_flips(dev); | |
3091 | ||
3092 | /* no reset support for gen2 */ | |
3093 | if (IS_GEN2(dev)) | |
3094 | return; | |
3095 | ||
3096 | /* reset doesn't touch the display */ | |
3097 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3098 | /* | |
3099 | * Flips in the rings have been nuked by the reset, | |
3100 | * so update the base address of all primary | |
3101 | * planes to the the last fb to make sure we're | |
3102 | * showing the correct fb after a reset. | |
3103 | */ | |
3104 | intel_update_primary_planes(dev); | |
3105 | return; | |
3106 | } | |
3107 | ||
3108 | /* | |
3109 | * The display has been reset as well, | |
3110 | * so need a full re-initialization. | |
3111 | */ | |
3112 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3113 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3114 | ||
3115 | intel_modeset_init_hw(dev); | |
3116 | ||
3117 | spin_lock_irq(&dev_priv->irq_lock); | |
3118 | if (dev_priv->display.hpd_irq_setup) | |
3119 | dev_priv->display.hpd_irq_setup(dev); | |
3120 | spin_unlock_irq(&dev_priv->irq_lock); | |
3121 | ||
3122 | intel_modeset_setup_hw_state(dev, true); | |
3123 | ||
3124 | intel_hpd_init(dev_priv); | |
3125 | ||
3126 | drm_modeset_unlock_all(dev); | |
3127 | } | |
3128 | ||
14667a4b CW |
3129 | static int |
3130 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3131 | { | |
2ff8fde1 | 3132 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3133 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3134 | bool was_interruptible = dev_priv->mm.interruptible; | |
3135 | int ret; | |
3136 | ||
14667a4b CW |
3137 | /* Big Hammer, we also need to ensure that any pending |
3138 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3139 | * current scanout is retired before unpinning the old | |
3140 | * framebuffer. | |
3141 | * | |
3142 | * This should only fail upon a hung GPU, in which case we | |
3143 | * can safely continue. | |
3144 | */ | |
3145 | dev_priv->mm.interruptible = false; | |
3146 | ret = i915_gem_object_finish_gpu(obj); | |
3147 | dev_priv->mm.interruptible = was_interruptible; | |
3148 | ||
3149 | return ret; | |
3150 | } | |
3151 | ||
7d5e3799 CW |
3152 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3153 | { | |
3154 | struct drm_device *dev = crtc->dev; | |
3155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3157 | bool pending; |
3158 | ||
3159 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3160 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3161 | return false; | |
3162 | ||
5e2d7afc | 3163 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3164 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3165 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3166 | |
3167 | return pending; | |
3168 | } | |
3169 | ||
e30e8f75 GP |
3170 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3171 | { | |
3172 | struct drm_device *dev = crtc->base.dev; | |
3173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3174 | const struct drm_display_mode *adjusted_mode; | |
3175 | ||
3176 | if (!i915.fastboot) | |
3177 | return; | |
3178 | ||
3179 | /* | |
3180 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3181 | * that in compute_mode_changes we check the native mode (not the pfit | |
3182 | * mode) to see if we can flip rather than do a full mode set. In the | |
3183 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3184 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3185 | * sized surface. | |
3186 | * | |
3187 | * To fix this properly, we need to hoist the checks up into | |
3188 | * compute_mode_changes (or above), check the actual pfit state and | |
3189 | * whether the platform allows pfit disable with pipe active, and only | |
3190 | * then update the pipesrc and pfit state, even on the flip path. | |
3191 | */ | |
3192 | ||
6e3c9717 | 3193 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3194 | |
3195 | I915_WRITE(PIPESRC(crtc->pipe), | |
3196 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3197 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3198 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3199 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3200 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3201 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3202 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3203 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3204 | } | |
6e3c9717 ACO |
3205 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3206 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3207 | } |
3208 | ||
5e84e1a4 ZW |
3209 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3210 | { | |
3211 | struct drm_device *dev = crtc->dev; | |
3212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3214 | int pipe = intel_crtc->pipe; | |
3215 | u32 reg, temp; | |
3216 | ||
3217 | /* enable normal train */ | |
3218 | reg = FDI_TX_CTL(pipe); | |
3219 | temp = I915_READ(reg); | |
61e499bf | 3220 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3221 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3222 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3223 | } else { |
3224 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3225 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3226 | } |
5e84e1a4 ZW |
3227 | I915_WRITE(reg, temp); |
3228 | ||
3229 | reg = FDI_RX_CTL(pipe); | |
3230 | temp = I915_READ(reg); | |
3231 | if (HAS_PCH_CPT(dev)) { | |
3232 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3233 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3234 | } else { | |
3235 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3236 | temp |= FDI_LINK_TRAIN_NONE; | |
3237 | } | |
3238 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3239 | ||
3240 | /* wait one idle pattern time */ | |
3241 | POSTING_READ(reg); | |
3242 | udelay(1000); | |
357555c0 JB |
3243 | |
3244 | /* IVB wants error correction enabled */ | |
3245 | if (IS_IVYBRIDGE(dev)) | |
3246 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3247 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3248 | } |
3249 | ||
8db9d77b ZW |
3250 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3251 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3252 | { | |
3253 | struct drm_device *dev = crtc->dev; | |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3255 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3256 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3257 | u32 reg, temp, tries; |
8db9d77b | 3258 | |
1c8562f6 | 3259 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3260 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3261 | |
e1a44743 AJ |
3262 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3263 | for train result */ | |
5eddb70b CW |
3264 | reg = FDI_RX_IMR(pipe); |
3265 | temp = I915_READ(reg); | |
e1a44743 AJ |
3266 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3267 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3268 | I915_WRITE(reg, temp); |
3269 | I915_READ(reg); | |
e1a44743 AJ |
3270 | udelay(150); |
3271 | ||
8db9d77b | 3272 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3273 | reg = FDI_TX_CTL(pipe); |
3274 | temp = I915_READ(reg); | |
627eb5a3 | 3275 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3276 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3277 | temp &= ~FDI_LINK_TRAIN_NONE; |
3278 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3279 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3280 | |
5eddb70b CW |
3281 | reg = FDI_RX_CTL(pipe); |
3282 | temp = I915_READ(reg); | |
8db9d77b ZW |
3283 | temp &= ~FDI_LINK_TRAIN_NONE; |
3284 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3285 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3286 | ||
3287 | POSTING_READ(reg); | |
8db9d77b ZW |
3288 | udelay(150); |
3289 | ||
5b2adf89 | 3290 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3291 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3292 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3293 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3294 | |
5eddb70b | 3295 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3296 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3297 | temp = I915_READ(reg); |
8db9d77b ZW |
3298 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3299 | ||
3300 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3301 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3302 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3303 | break; |
3304 | } | |
8db9d77b | 3305 | } |
e1a44743 | 3306 | if (tries == 5) |
5eddb70b | 3307 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3308 | |
3309 | /* Train 2 */ | |
5eddb70b CW |
3310 | reg = FDI_TX_CTL(pipe); |
3311 | temp = I915_READ(reg); | |
8db9d77b ZW |
3312 | temp &= ~FDI_LINK_TRAIN_NONE; |
3313 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3314 | I915_WRITE(reg, temp); |
8db9d77b | 3315 | |
5eddb70b CW |
3316 | reg = FDI_RX_CTL(pipe); |
3317 | temp = I915_READ(reg); | |
8db9d77b ZW |
3318 | temp &= ~FDI_LINK_TRAIN_NONE; |
3319 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3320 | I915_WRITE(reg, temp); |
8db9d77b | 3321 | |
5eddb70b CW |
3322 | POSTING_READ(reg); |
3323 | udelay(150); | |
8db9d77b | 3324 | |
5eddb70b | 3325 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3326 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3327 | temp = I915_READ(reg); |
8db9d77b ZW |
3328 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3329 | ||
3330 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3331 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3332 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3333 | break; | |
3334 | } | |
8db9d77b | 3335 | } |
e1a44743 | 3336 | if (tries == 5) |
5eddb70b | 3337 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3338 | |
3339 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3340 | |
8db9d77b ZW |
3341 | } |
3342 | ||
0206e353 | 3343 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3344 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3345 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3346 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3347 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3348 | }; | |
3349 | ||
3350 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3351 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3352 | { | |
3353 | struct drm_device *dev = crtc->dev; | |
3354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3355 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3356 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3357 | u32 reg, temp, i, retry; |
8db9d77b | 3358 | |
e1a44743 AJ |
3359 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3360 | for train result */ | |
5eddb70b CW |
3361 | reg = FDI_RX_IMR(pipe); |
3362 | temp = I915_READ(reg); | |
e1a44743 AJ |
3363 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3364 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3365 | I915_WRITE(reg, temp); |
3366 | ||
3367 | POSTING_READ(reg); | |
e1a44743 AJ |
3368 | udelay(150); |
3369 | ||
8db9d77b | 3370 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3371 | reg = FDI_TX_CTL(pipe); |
3372 | temp = I915_READ(reg); | |
627eb5a3 | 3373 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3374 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3375 | temp &= ~FDI_LINK_TRAIN_NONE; |
3376 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3377 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3378 | /* SNB-B */ | |
3379 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3380 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3381 | |
d74cf324 DV |
3382 | I915_WRITE(FDI_RX_MISC(pipe), |
3383 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3384 | ||
5eddb70b CW |
3385 | reg = FDI_RX_CTL(pipe); |
3386 | temp = I915_READ(reg); | |
8db9d77b ZW |
3387 | if (HAS_PCH_CPT(dev)) { |
3388 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3389 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3390 | } else { | |
3391 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3392 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3393 | } | |
5eddb70b CW |
3394 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3395 | ||
3396 | POSTING_READ(reg); | |
8db9d77b ZW |
3397 | udelay(150); |
3398 | ||
0206e353 | 3399 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3400 | reg = FDI_TX_CTL(pipe); |
3401 | temp = I915_READ(reg); | |
8db9d77b ZW |
3402 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3403 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3404 | I915_WRITE(reg, temp); |
3405 | ||
3406 | POSTING_READ(reg); | |
8db9d77b ZW |
3407 | udelay(500); |
3408 | ||
fa37d39e SP |
3409 | for (retry = 0; retry < 5; retry++) { |
3410 | reg = FDI_RX_IIR(pipe); | |
3411 | temp = I915_READ(reg); | |
3412 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3413 | if (temp & FDI_RX_BIT_LOCK) { | |
3414 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3415 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3416 | break; | |
3417 | } | |
3418 | udelay(50); | |
8db9d77b | 3419 | } |
fa37d39e SP |
3420 | if (retry < 5) |
3421 | break; | |
8db9d77b ZW |
3422 | } |
3423 | if (i == 4) | |
5eddb70b | 3424 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3425 | |
3426 | /* Train 2 */ | |
5eddb70b CW |
3427 | reg = FDI_TX_CTL(pipe); |
3428 | temp = I915_READ(reg); | |
8db9d77b ZW |
3429 | temp &= ~FDI_LINK_TRAIN_NONE; |
3430 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3431 | if (IS_GEN6(dev)) { | |
3432 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3433 | /* SNB-B */ | |
3434 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3435 | } | |
5eddb70b | 3436 | I915_WRITE(reg, temp); |
8db9d77b | 3437 | |
5eddb70b CW |
3438 | reg = FDI_RX_CTL(pipe); |
3439 | temp = I915_READ(reg); | |
8db9d77b ZW |
3440 | if (HAS_PCH_CPT(dev)) { |
3441 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3442 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3443 | } else { | |
3444 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3445 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3446 | } | |
5eddb70b CW |
3447 | I915_WRITE(reg, temp); |
3448 | ||
3449 | POSTING_READ(reg); | |
8db9d77b ZW |
3450 | udelay(150); |
3451 | ||
0206e353 | 3452 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3453 | reg = FDI_TX_CTL(pipe); |
3454 | temp = I915_READ(reg); | |
8db9d77b ZW |
3455 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3456 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3457 | I915_WRITE(reg, temp); |
3458 | ||
3459 | POSTING_READ(reg); | |
8db9d77b ZW |
3460 | udelay(500); |
3461 | ||
fa37d39e SP |
3462 | for (retry = 0; retry < 5; retry++) { |
3463 | reg = FDI_RX_IIR(pipe); | |
3464 | temp = I915_READ(reg); | |
3465 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3466 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3467 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3468 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3469 | break; | |
3470 | } | |
3471 | udelay(50); | |
8db9d77b | 3472 | } |
fa37d39e SP |
3473 | if (retry < 5) |
3474 | break; | |
8db9d77b ZW |
3475 | } |
3476 | if (i == 4) | |
5eddb70b | 3477 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3478 | |
3479 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3480 | } | |
3481 | ||
357555c0 JB |
3482 | /* Manual link training for Ivy Bridge A0 parts */ |
3483 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3484 | { | |
3485 | struct drm_device *dev = crtc->dev; | |
3486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3488 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3489 | u32 reg, temp, i, j; |
357555c0 JB |
3490 | |
3491 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3492 | for train result */ | |
3493 | reg = FDI_RX_IMR(pipe); | |
3494 | temp = I915_READ(reg); | |
3495 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3496 | temp &= ~FDI_RX_BIT_LOCK; | |
3497 | I915_WRITE(reg, temp); | |
3498 | ||
3499 | POSTING_READ(reg); | |
3500 | udelay(150); | |
3501 | ||
01a415fd DV |
3502 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3503 | I915_READ(FDI_RX_IIR(pipe))); | |
3504 | ||
139ccd3f JB |
3505 | /* Try each vswing and preemphasis setting twice before moving on */ |
3506 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3507 | /* disable first in case we need to retry */ | |
3508 | reg = FDI_TX_CTL(pipe); | |
3509 | temp = I915_READ(reg); | |
3510 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3511 | temp &= ~FDI_TX_ENABLE; | |
3512 | I915_WRITE(reg, temp); | |
357555c0 | 3513 | |
139ccd3f JB |
3514 | reg = FDI_RX_CTL(pipe); |
3515 | temp = I915_READ(reg); | |
3516 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3517 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3518 | temp &= ~FDI_RX_ENABLE; | |
3519 | I915_WRITE(reg, temp); | |
357555c0 | 3520 | |
139ccd3f | 3521 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3522 | reg = FDI_TX_CTL(pipe); |
3523 | temp = I915_READ(reg); | |
139ccd3f | 3524 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3525 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3526 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3527 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3528 | temp |= snb_b_fdi_train_param[j/2]; |
3529 | temp |= FDI_COMPOSITE_SYNC; | |
3530 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3531 | |
139ccd3f JB |
3532 | I915_WRITE(FDI_RX_MISC(pipe), |
3533 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3534 | |
139ccd3f | 3535 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3536 | temp = I915_READ(reg); |
139ccd3f JB |
3537 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3538 | temp |= FDI_COMPOSITE_SYNC; | |
3539 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3540 | |
139ccd3f JB |
3541 | POSTING_READ(reg); |
3542 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3543 | |
139ccd3f JB |
3544 | for (i = 0; i < 4; i++) { |
3545 | reg = FDI_RX_IIR(pipe); | |
3546 | temp = I915_READ(reg); | |
3547 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3548 | |
139ccd3f JB |
3549 | if (temp & FDI_RX_BIT_LOCK || |
3550 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3551 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3552 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3553 | i); | |
3554 | break; | |
3555 | } | |
3556 | udelay(1); /* should be 0.5us */ | |
3557 | } | |
3558 | if (i == 4) { | |
3559 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3560 | continue; | |
3561 | } | |
357555c0 | 3562 | |
139ccd3f | 3563 | /* Train 2 */ |
357555c0 JB |
3564 | reg = FDI_TX_CTL(pipe); |
3565 | temp = I915_READ(reg); | |
139ccd3f JB |
3566 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3567 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3568 | I915_WRITE(reg, temp); | |
3569 | ||
3570 | reg = FDI_RX_CTL(pipe); | |
3571 | temp = I915_READ(reg); | |
3572 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3573 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3574 | I915_WRITE(reg, temp); |
3575 | ||
3576 | POSTING_READ(reg); | |
139ccd3f | 3577 | udelay(2); /* should be 1.5us */ |
357555c0 | 3578 | |
139ccd3f JB |
3579 | for (i = 0; i < 4; i++) { |
3580 | reg = FDI_RX_IIR(pipe); | |
3581 | temp = I915_READ(reg); | |
3582 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3583 | |
139ccd3f JB |
3584 | if (temp & FDI_RX_SYMBOL_LOCK || |
3585 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3586 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3587 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3588 | i); | |
3589 | goto train_done; | |
3590 | } | |
3591 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3592 | } |
139ccd3f JB |
3593 | if (i == 4) |
3594 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3595 | } |
357555c0 | 3596 | |
139ccd3f | 3597 | train_done: |
357555c0 JB |
3598 | DRM_DEBUG_KMS("FDI train done.\n"); |
3599 | } | |
3600 | ||
88cefb6c | 3601 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3602 | { |
88cefb6c | 3603 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3604 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3605 | int pipe = intel_crtc->pipe; |
5eddb70b | 3606 | u32 reg, temp; |
79e53945 | 3607 | |
c64e311e | 3608 | |
c98e9dcf | 3609 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3610 | reg = FDI_RX_CTL(pipe); |
3611 | temp = I915_READ(reg); | |
627eb5a3 | 3612 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3613 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3614 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3615 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3616 | ||
3617 | POSTING_READ(reg); | |
c98e9dcf JB |
3618 | udelay(200); |
3619 | ||
3620 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3621 | temp = I915_READ(reg); |
3622 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3623 | ||
3624 | POSTING_READ(reg); | |
c98e9dcf JB |
3625 | udelay(200); |
3626 | ||
20749730 PZ |
3627 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3628 | reg = FDI_TX_CTL(pipe); | |
3629 | temp = I915_READ(reg); | |
3630 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3631 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3632 | |
20749730 PZ |
3633 | POSTING_READ(reg); |
3634 | udelay(100); | |
6be4a607 | 3635 | } |
0e23b99d JB |
3636 | } |
3637 | ||
88cefb6c DV |
3638 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3639 | { | |
3640 | struct drm_device *dev = intel_crtc->base.dev; | |
3641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3642 | int pipe = intel_crtc->pipe; | |
3643 | u32 reg, temp; | |
3644 | ||
3645 | /* Switch from PCDclk to Rawclk */ | |
3646 | reg = FDI_RX_CTL(pipe); | |
3647 | temp = I915_READ(reg); | |
3648 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3649 | ||
3650 | /* Disable CPU FDI TX PLL */ | |
3651 | reg = FDI_TX_CTL(pipe); | |
3652 | temp = I915_READ(reg); | |
3653 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3654 | ||
3655 | POSTING_READ(reg); | |
3656 | udelay(100); | |
3657 | ||
3658 | reg = FDI_RX_CTL(pipe); | |
3659 | temp = I915_READ(reg); | |
3660 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3661 | ||
3662 | /* Wait for the clocks to turn off. */ | |
3663 | POSTING_READ(reg); | |
3664 | udelay(100); | |
3665 | } | |
3666 | ||
0fc932b8 JB |
3667 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3668 | { | |
3669 | struct drm_device *dev = crtc->dev; | |
3670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3672 | int pipe = intel_crtc->pipe; | |
3673 | u32 reg, temp; | |
3674 | ||
3675 | /* disable CPU FDI tx and PCH FDI rx */ | |
3676 | reg = FDI_TX_CTL(pipe); | |
3677 | temp = I915_READ(reg); | |
3678 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3679 | POSTING_READ(reg); | |
3680 | ||
3681 | reg = FDI_RX_CTL(pipe); | |
3682 | temp = I915_READ(reg); | |
3683 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3684 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3685 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3686 | ||
3687 | POSTING_READ(reg); | |
3688 | udelay(100); | |
3689 | ||
3690 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3691 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3692 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3693 | |
3694 | /* still set train pattern 1 */ | |
3695 | reg = FDI_TX_CTL(pipe); | |
3696 | temp = I915_READ(reg); | |
3697 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3698 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3699 | I915_WRITE(reg, temp); | |
3700 | ||
3701 | reg = FDI_RX_CTL(pipe); | |
3702 | temp = I915_READ(reg); | |
3703 | if (HAS_PCH_CPT(dev)) { | |
3704 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3705 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3706 | } else { | |
3707 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3708 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3709 | } | |
3710 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3711 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3712 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3713 | I915_WRITE(reg, temp); |
3714 | ||
3715 | POSTING_READ(reg); | |
3716 | udelay(100); | |
3717 | } | |
3718 | ||
5dce5b93 CW |
3719 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3720 | { | |
3721 | struct intel_crtc *crtc; | |
3722 | ||
3723 | /* Note that we don't need to be called with mode_config.lock here | |
3724 | * as our list of CRTC objects is static for the lifetime of the | |
3725 | * device and so cannot disappear as we iterate. Similarly, we can | |
3726 | * happily treat the predicates as racy, atomic checks as userspace | |
3727 | * cannot claim and pin a new fb without at least acquring the | |
3728 | * struct_mutex and so serialising with us. | |
3729 | */ | |
d3fcc808 | 3730 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3731 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3732 | continue; | |
3733 | ||
3734 | if (crtc->unpin_work) | |
3735 | intel_wait_for_vblank(dev, crtc->pipe); | |
3736 | ||
3737 | return true; | |
3738 | } | |
3739 | ||
3740 | return false; | |
3741 | } | |
3742 | ||
d6bbafa1 CW |
3743 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3744 | { | |
3745 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3746 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3747 | ||
3748 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3749 | smp_rmb(); | |
3750 | intel_crtc->unpin_work = NULL; | |
3751 | ||
3752 | if (work->event) | |
3753 | drm_send_vblank_event(intel_crtc->base.dev, | |
3754 | intel_crtc->pipe, | |
3755 | work->event); | |
3756 | ||
3757 | drm_crtc_vblank_put(&intel_crtc->base); | |
3758 | ||
3759 | wake_up_all(&dev_priv->pending_flip_queue); | |
3760 | queue_work(dev_priv->wq, &work->work); | |
3761 | ||
3762 | trace_i915_flip_complete(intel_crtc->plane, | |
3763 | work->pending_flip_obj); | |
3764 | } | |
3765 | ||
46a55d30 | 3766 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3767 | { |
0f91128d | 3768 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3769 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3770 | |
2c10d571 | 3771 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3772 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3773 | !intel_crtc_has_pending_flip(crtc), | |
3774 | 60*HZ) == 0)) { | |
3775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3776 | |
5e2d7afc | 3777 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3778 | if (intel_crtc->unpin_work) { |
3779 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3780 | page_flip_completed(intel_crtc); | |
3781 | } | |
5e2d7afc | 3782 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3783 | } |
5bb61643 | 3784 | |
975d568a CW |
3785 | if (crtc->primary->fb) { |
3786 | mutex_lock(&dev->struct_mutex); | |
3787 | intel_finish_fb(crtc->primary->fb); | |
3788 | mutex_unlock(&dev->struct_mutex); | |
3789 | } | |
e6c3a2a6 CW |
3790 | } |
3791 | ||
e615efe4 ED |
3792 | /* Program iCLKIP clock to the desired frequency */ |
3793 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3794 | { | |
3795 | struct drm_device *dev = crtc->dev; | |
3796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3797 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3798 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3799 | u32 temp; | |
3800 | ||
09153000 DV |
3801 | mutex_lock(&dev_priv->dpio_lock); |
3802 | ||
e615efe4 ED |
3803 | /* It is necessary to ungate the pixclk gate prior to programming |
3804 | * the divisors, and gate it back when it is done. | |
3805 | */ | |
3806 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3807 | ||
3808 | /* Disable SSCCTL */ | |
3809 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3810 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3811 | SBI_SSCCTL_DISABLE, | |
3812 | SBI_ICLK); | |
e615efe4 ED |
3813 | |
3814 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3815 | if (clock == 20000) { |
e615efe4 ED |
3816 | auxdiv = 1; |
3817 | divsel = 0x41; | |
3818 | phaseinc = 0x20; | |
3819 | } else { | |
3820 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3821 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3822 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3823 | * convert the virtual clock precision to KHz here for higher |
3824 | * precision. | |
3825 | */ | |
3826 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3827 | u32 iclk_pi_range = 64; | |
3828 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3829 | ||
12d7ceed | 3830 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3831 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3832 | pi_value = desired_divisor % iclk_pi_range; | |
3833 | ||
3834 | auxdiv = 0; | |
3835 | divsel = msb_divisor_value - 2; | |
3836 | phaseinc = pi_value; | |
3837 | } | |
3838 | ||
3839 | /* This should not happen with any sane values */ | |
3840 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3841 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3842 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3843 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3844 | ||
3845 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3846 | clock, |
e615efe4 ED |
3847 | auxdiv, |
3848 | divsel, | |
3849 | phasedir, | |
3850 | phaseinc); | |
3851 | ||
3852 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3853 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3854 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3855 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3856 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3857 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3858 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3859 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3860 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3861 | |
3862 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3863 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3864 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3865 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3866 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3867 | |
3868 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3869 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3870 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3871 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3872 | |
3873 | /* Wait for initialization time */ | |
3874 | udelay(24); | |
3875 | ||
3876 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3877 | |
3878 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3879 | } |
3880 | ||
275f01b2 DV |
3881 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3882 | enum pipe pch_transcoder) | |
3883 | { | |
3884 | struct drm_device *dev = crtc->base.dev; | |
3885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3886 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3887 | |
3888 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3889 | I915_READ(HTOTAL(cpu_transcoder))); | |
3890 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3891 | I915_READ(HBLANK(cpu_transcoder))); | |
3892 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3893 | I915_READ(HSYNC(cpu_transcoder))); | |
3894 | ||
3895 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3896 | I915_READ(VTOTAL(cpu_transcoder))); | |
3897 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3898 | I915_READ(VBLANK(cpu_transcoder))); | |
3899 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3900 | I915_READ(VSYNC(cpu_transcoder))); | |
3901 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3902 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3903 | } | |
3904 | ||
003632d9 | 3905 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
3906 | { |
3907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3908 | uint32_t temp; | |
3909 | ||
3910 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3911 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3912 | return; |
3913 | ||
3914 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3915 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3916 | ||
003632d9 ACO |
3917 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
3918 | if (enable) | |
3919 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3920 | ||
3921 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
3922 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3923 | POSTING_READ(SOUTH_CHICKEN1); | |
3924 | } | |
3925 | ||
3926 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3927 | { | |
3928 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
3929 | |
3930 | switch (intel_crtc->pipe) { | |
3931 | case PIPE_A: | |
3932 | break; | |
3933 | case PIPE_B: | |
6e3c9717 | 3934 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 3935 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 3936 | else |
003632d9 | 3937 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3938 | |
3939 | break; | |
3940 | case PIPE_C: | |
003632d9 | 3941 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3942 | |
3943 | break; | |
3944 | default: | |
3945 | BUG(); | |
3946 | } | |
3947 | } | |
3948 | ||
f67a559d JB |
3949 | /* |
3950 | * Enable PCH resources required for PCH ports: | |
3951 | * - PCH PLLs | |
3952 | * - FDI training & RX/TX | |
3953 | * - update transcoder timings | |
3954 | * - DP transcoding bits | |
3955 | * - transcoder | |
3956 | */ | |
3957 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3958 | { |
3959 | struct drm_device *dev = crtc->dev; | |
3960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3962 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3963 | u32 reg, temp; |
2c07245f | 3964 | |
ab9412ba | 3965 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3966 | |
1fbc0d78 DV |
3967 | if (IS_IVYBRIDGE(dev)) |
3968 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3969 | ||
cd986abb DV |
3970 | /* Write the TU size bits before fdi link training, so that error |
3971 | * detection works. */ | |
3972 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3973 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3974 | ||
c98e9dcf | 3975 | /* For PCH output, training FDI link */ |
674cf967 | 3976 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3977 | |
3ad8a208 DV |
3978 | /* We need to program the right clock selection before writing the pixel |
3979 | * mutliplier into the DPLL. */ | |
303b81e0 | 3980 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3981 | u32 sel; |
4b645f14 | 3982 | |
c98e9dcf | 3983 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3984 | temp |= TRANS_DPLL_ENABLE(pipe); |
3985 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 3986 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3987 | temp |= sel; |
3988 | else | |
3989 | temp &= ~sel; | |
c98e9dcf | 3990 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3991 | } |
5eddb70b | 3992 | |
3ad8a208 DV |
3993 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3994 | * transcoder, and we actually should do this to not upset any PCH | |
3995 | * transcoder that already use the clock when we share it. | |
3996 | * | |
3997 | * Note that enable_shared_dpll tries to do the right thing, but | |
3998 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3999 | * the right LVDS enable sequence. */ | |
85b3894f | 4000 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4001 | |
d9b6cb56 JB |
4002 | /* set transcoder timing, panel must allow it */ |
4003 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4004 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4005 | |
303b81e0 | 4006 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4007 | |
c98e9dcf | 4008 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4009 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4010 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4011 | reg = TRANS_DP_CTL(pipe); |
4012 | temp = I915_READ(reg); | |
4013 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4014 | TRANS_DP_SYNC_MASK | |
4015 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4016 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4017 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4018 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4019 | |
4020 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4021 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4022 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4023 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4024 | |
4025 | switch (intel_trans_dp_port_sel(crtc)) { | |
4026 | case PCH_DP_B: | |
5eddb70b | 4027 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4028 | break; |
4029 | case PCH_DP_C: | |
5eddb70b | 4030 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4031 | break; |
4032 | case PCH_DP_D: | |
5eddb70b | 4033 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4034 | break; |
4035 | default: | |
e95d41e1 | 4036 | BUG(); |
32f9d658 | 4037 | } |
2c07245f | 4038 | |
5eddb70b | 4039 | I915_WRITE(reg, temp); |
6be4a607 | 4040 | } |
b52eb4dc | 4041 | |
b8a4f404 | 4042 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4043 | } |
4044 | ||
1507e5bd PZ |
4045 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4046 | { | |
4047 | struct drm_device *dev = crtc->dev; | |
4048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4050 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4051 | |
ab9412ba | 4052 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4053 | |
8c52b5e8 | 4054 | lpt_program_iclkip(crtc); |
1507e5bd | 4055 | |
0540e488 | 4056 | /* Set transcoder timing. */ |
275f01b2 | 4057 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4058 | |
937bb610 | 4059 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4060 | } |
4061 | ||
716c2e55 | 4062 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4063 | { |
e2b78267 | 4064 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4065 | |
4066 | if (pll == NULL) | |
4067 | return; | |
4068 | ||
3e369b76 | 4069 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4070 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4071 | return; |
4072 | } | |
4073 | ||
3e369b76 ACO |
4074 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4075 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4076 | WARN_ON(pll->on); |
4077 | WARN_ON(pll->active); | |
4078 | } | |
4079 | ||
6e3c9717 | 4080 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4081 | } |
4082 | ||
190f68c5 ACO |
4083 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4084 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4085 | { |
e2b78267 | 4086 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4087 | struct intel_shared_dpll *pll; |
e2b78267 | 4088 | enum intel_dpll_id i; |
ee7b9f93 | 4089 | |
98b6bd99 DV |
4090 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4091 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4092 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4093 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4094 | |
46edb027 DV |
4095 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4096 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4097 | |
8bd31e67 | 4098 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4099 | |
98b6bd99 DV |
4100 | goto found; |
4101 | } | |
4102 | ||
e72f9fbf DV |
4103 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4104 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4105 | |
4106 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4107 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4108 | continue; |
4109 | ||
190f68c5 | 4110 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4111 | &pll->new_config->hw_state, |
4112 | sizeof(pll->new_config->hw_state)) == 0) { | |
4113 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4114 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4115 | pll->new_config->crtc_mask, |
4116 | pll->active); | |
ee7b9f93 JB |
4117 | goto found; |
4118 | } | |
4119 | } | |
4120 | ||
4121 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4122 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4123 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4124 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4125 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4126 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4127 | goto found; |
4128 | } | |
4129 | } | |
4130 | ||
4131 | return NULL; | |
4132 | ||
4133 | found: | |
8bd31e67 | 4134 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4135 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4136 | |
190f68c5 | 4137 | crtc_state->shared_dpll = i; |
46edb027 DV |
4138 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4139 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4140 | |
8bd31e67 | 4141 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4142 | |
ee7b9f93 JB |
4143 | return pll; |
4144 | } | |
4145 | ||
8bd31e67 ACO |
4146 | /** |
4147 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4148 | * @dev_priv: DRM device | |
4149 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4150 | * | |
4151 | * Starts a new PLL staged config, copying the current config but | |
4152 | * releasing the references of pipes specified in clear_pipes. | |
4153 | */ | |
4154 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4155 | unsigned clear_pipes) | |
4156 | { | |
4157 | struct intel_shared_dpll *pll; | |
4158 | enum intel_dpll_id i; | |
4159 | ||
4160 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4161 | pll = &dev_priv->shared_dplls[i]; | |
4162 | ||
4163 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4164 | GFP_KERNEL); | |
4165 | if (!pll->new_config) | |
4166 | goto cleanup; | |
4167 | ||
4168 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4169 | } | |
4170 | ||
4171 | return 0; | |
4172 | ||
4173 | cleanup: | |
4174 | while (--i >= 0) { | |
4175 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4176 | kfree(pll->new_config); |
8bd31e67 ACO |
4177 | pll->new_config = NULL; |
4178 | } | |
4179 | ||
4180 | return -ENOMEM; | |
4181 | } | |
4182 | ||
4183 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4184 | { | |
4185 | struct intel_shared_dpll *pll; | |
4186 | enum intel_dpll_id i; | |
4187 | ||
4188 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4189 | pll = &dev_priv->shared_dplls[i]; | |
4190 | ||
4191 | WARN_ON(pll->new_config == &pll->config); | |
4192 | ||
4193 | pll->config = *pll->new_config; | |
4194 | kfree(pll->new_config); | |
4195 | pll->new_config = NULL; | |
4196 | } | |
4197 | } | |
4198 | ||
4199 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4200 | { | |
4201 | struct intel_shared_dpll *pll; | |
4202 | enum intel_dpll_id i; | |
4203 | ||
4204 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4205 | pll = &dev_priv->shared_dplls[i]; | |
4206 | ||
4207 | WARN_ON(pll->new_config == &pll->config); | |
4208 | ||
4209 | kfree(pll->new_config); | |
4210 | pll->new_config = NULL; | |
4211 | } | |
4212 | } | |
4213 | ||
a1520318 | 4214 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4215 | { |
4216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4217 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4218 | u32 temp; |
4219 | ||
4220 | temp = I915_READ(dslreg); | |
4221 | udelay(500); | |
4222 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4223 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4224 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4225 | } |
4226 | } | |
4227 | ||
bd2e244f JB |
4228 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4229 | { | |
4230 | struct drm_device *dev = crtc->base.dev; | |
4231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4232 | int pipe = crtc->pipe; | |
4233 | ||
6e3c9717 | 4234 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f | 4235 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); |
6e3c9717 ACO |
4236 | I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4237 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4238 | } |
4239 | } | |
4240 | ||
b074cec8 JB |
4241 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4242 | { | |
4243 | struct drm_device *dev = crtc->base.dev; | |
4244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4245 | int pipe = crtc->pipe; | |
4246 | ||
6e3c9717 | 4247 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4248 | /* Force use of hard-coded filter coefficients |
4249 | * as some pre-programmed values are broken, | |
4250 | * e.g. x201. | |
4251 | */ | |
4252 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4253 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4254 | PF_PIPE_SEL_IVB(pipe)); | |
4255 | else | |
4256 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4257 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4258 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4259 | } |
4260 | } | |
4261 | ||
4a3b8769 | 4262 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4263 | { |
4264 | struct drm_device *dev = crtc->dev; | |
4265 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4266 | struct drm_plane *plane; |
bb53d4ae VS |
4267 | struct intel_plane *intel_plane; |
4268 | ||
af2b653b MR |
4269 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4270 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4271 | if (intel_plane->pipe == pipe) |
4272 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4273 | } |
bb53d4ae VS |
4274 | } |
4275 | ||
0d703d4e MR |
4276 | /* |
4277 | * Disable a plane internally without actually modifying the plane's state. | |
4278 | * This will allow us to easily restore the plane later by just reprogramming | |
4279 | * its state. | |
4280 | */ | |
4281 | static void disable_plane_internal(struct drm_plane *plane) | |
4282 | { | |
4283 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4284 | struct drm_plane_state *state = | |
4285 | plane->funcs->atomic_duplicate_state(plane); | |
4286 | struct intel_plane_state *intel_state = to_intel_plane_state(state); | |
4287 | ||
4288 | intel_state->visible = false; | |
4289 | intel_plane->commit_plane(plane, intel_state); | |
4290 | ||
4291 | intel_plane_destroy_state(plane, state); | |
4292 | } | |
4293 | ||
4a3b8769 | 4294 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4295 | { |
4296 | struct drm_device *dev = crtc->dev; | |
4297 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4298 | struct drm_plane *plane; |
bb53d4ae VS |
4299 | struct intel_plane *intel_plane; |
4300 | ||
af2b653b MR |
4301 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4302 | intel_plane = to_intel_plane(plane); | |
0d703d4e MR |
4303 | if (plane->fb && intel_plane->pipe == pipe) |
4304 | disable_plane_internal(plane); | |
af2b653b | 4305 | } |
bb53d4ae VS |
4306 | } |
4307 | ||
20bc8673 | 4308 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4309 | { |
cea165c3 VS |
4310 | struct drm_device *dev = crtc->base.dev; |
4311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4312 | |
6e3c9717 | 4313 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4314 | return; |
4315 | ||
cea165c3 VS |
4316 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4317 | intel_wait_for_vblank(dev, crtc->pipe); | |
4318 | ||
d77e4531 | 4319 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4320 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4321 | mutex_lock(&dev_priv->rps.hw_lock); |
4322 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4323 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4324 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4325 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4326 | * mailbox." Moreover, the mailbox may return a bogus state, |
4327 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4328 | */ |
4329 | } else { | |
4330 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4331 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4332 | * is essentially intel_wait_for_vblank. If we don't have this | |
4333 | * and don't wait for vblanks until the end of crtc_enable, then | |
4334 | * the HW state readout code will complain that the expected | |
4335 | * IPS_CTL value is not the one we read. */ | |
4336 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4337 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4338 | } | |
d77e4531 PZ |
4339 | } |
4340 | ||
20bc8673 | 4341 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4342 | { |
4343 | struct drm_device *dev = crtc->base.dev; | |
4344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4345 | ||
6e3c9717 | 4346 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4347 | return; |
4348 | ||
4349 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4350 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4351 | mutex_lock(&dev_priv->rps.hw_lock); |
4352 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4353 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4354 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4355 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4356 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4357 | } else { |
2a114cc1 | 4358 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4359 | POSTING_READ(IPS_CTL); |
4360 | } | |
d77e4531 PZ |
4361 | |
4362 | /* We need to wait for a vblank before we can disable the plane. */ | |
4363 | intel_wait_for_vblank(dev, crtc->pipe); | |
4364 | } | |
4365 | ||
4366 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4367 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4368 | { | |
4369 | struct drm_device *dev = crtc->dev; | |
4370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4372 | enum pipe pipe = intel_crtc->pipe; | |
4373 | int palreg = PALETTE(pipe); | |
4374 | int i; | |
4375 | bool reenable_ips = false; | |
4376 | ||
4377 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4378 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4379 | return; |
4380 | ||
4381 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4382 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4383 | assert_dsi_pll_enabled(dev_priv); |
4384 | else | |
4385 | assert_pll_enabled(dev_priv, pipe); | |
4386 | } | |
4387 | ||
4388 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4389 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4390 | palreg = LGC_PALETTE(pipe); |
4391 | ||
4392 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4393 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4394 | */ | |
6e3c9717 | 4395 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4396 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4397 | GAMMA_MODE_MODE_SPLIT)) { | |
4398 | hsw_disable_ips(intel_crtc); | |
4399 | reenable_ips = true; | |
4400 | } | |
4401 | ||
4402 | for (i = 0; i < 256; i++) { | |
4403 | I915_WRITE(palreg + 4 * i, | |
4404 | (intel_crtc->lut_r[i] << 16) | | |
4405 | (intel_crtc->lut_g[i] << 8) | | |
4406 | intel_crtc->lut_b[i]); | |
4407 | } | |
4408 | ||
4409 | if (reenable_ips) | |
4410 | hsw_enable_ips(intel_crtc); | |
4411 | } | |
4412 | ||
d3eedb1a VS |
4413 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4414 | { | |
4415 | if (!enable && intel_crtc->overlay) { | |
4416 | struct drm_device *dev = intel_crtc->base.dev; | |
4417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4418 | ||
4419 | mutex_lock(&dev->struct_mutex); | |
4420 | dev_priv->mm.interruptible = false; | |
4421 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4422 | dev_priv->mm.interruptible = true; | |
4423 | mutex_unlock(&dev->struct_mutex); | |
4424 | } | |
4425 | ||
4426 | /* Let userspace switch the overlay on again. In most cases userspace | |
4427 | * has to recompute where to put it anyway. | |
4428 | */ | |
4429 | } | |
4430 | ||
d3eedb1a | 4431 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4432 | { |
4433 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4435 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4436 | |
fdd508a6 | 4437 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4438 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4439 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4440 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4441 | |
4442 | hsw_enable_ips(intel_crtc); | |
4443 | ||
4444 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4445 | intel_fbc_update(dev); |
a5c4d7bc | 4446 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4447 | |
4448 | /* | |
4449 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4450 | * to compute the mask of flip planes precisely. For the time being | |
4451 | * consider this a flip from a NULL plane. | |
4452 | */ | |
4453 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4454 | } |
4455 | ||
d3eedb1a | 4456 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4457 | { |
4458 | struct drm_device *dev = crtc->dev; | |
4459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4461 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4462 | |
4463 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4464 | |
e35fef21 | 4465 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4466 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4467 | |
4468 | hsw_disable_ips(intel_crtc); | |
4469 | ||
d3eedb1a | 4470 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4471 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4472 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4473 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4474 | |
f99d7069 DV |
4475 | /* |
4476 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4477 | * to compute the mask of flip planes precisely. For the time being | |
4478 | * consider this a flip to a NULL plane. | |
4479 | */ | |
4480 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4481 | } |
4482 | ||
f67a559d JB |
4483 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4484 | { | |
4485 | struct drm_device *dev = crtc->dev; | |
4486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4488 | struct intel_encoder *encoder; |
f67a559d | 4489 | int pipe = intel_crtc->pipe; |
f67a559d | 4490 | |
83d65738 | 4491 | WARN_ON(!crtc->state->enable); |
08a48469 | 4492 | |
f67a559d JB |
4493 | if (intel_crtc->active) |
4494 | return; | |
4495 | ||
6e3c9717 | 4496 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4497 | intel_prepare_shared_dpll(intel_crtc); |
4498 | ||
6e3c9717 | 4499 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4500 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4501 | |
4502 | intel_set_pipe_timings(intel_crtc); | |
4503 | ||
6e3c9717 | 4504 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4505 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4506 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4507 | } |
4508 | ||
4509 | ironlake_set_pipeconf(crtc); | |
4510 | ||
f67a559d | 4511 | intel_crtc->active = true; |
8664281b | 4512 | |
a72e4c9f DV |
4513 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4514 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4515 | |
f6736a1a | 4516 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4517 | if (encoder->pre_enable) |
4518 | encoder->pre_enable(encoder); | |
f67a559d | 4519 | |
6e3c9717 | 4520 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4521 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4522 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4523 | * enabling. */ | |
88cefb6c | 4524 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4525 | } else { |
4526 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4527 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4528 | } | |
f67a559d | 4529 | |
b074cec8 | 4530 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4531 | |
9c54c0dd JB |
4532 | /* |
4533 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4534 | * clocks enabled | |
4535 | */ | |
4536 | intel_crtc_load_lut(crtc); | |
4537 | ||
f37fcc2a | 4538 | intel_update_watermarks(crtc); |
e1fdc473 | 4539 | intel_enable_pipe(intel_crtc); |
f67a559d | 4540 | |
6e3c9717 | 4541 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4542 | ironlake_pch_enable(crtc); |
c98e9dcf | 4543 | |
f9b61ff6 DV |
4544 | assert_vblank_disabled(crtc); |
4545 | drm_crtc_vblank_on(crtc); | |
4546 | ||
fa5c73b1 DV |
4547 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4548 | encoder->enable(encoder); | |
61b77ddd DV |
4549 | |
4550 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4551 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4552 | |
d3eedb1a | 4553 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4554 | } |
4555 | ||
42db64ef PZ |
4556 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4557 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4558 | { | |
f5adf94e | 4559 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4560 | } |
4561 | ||
e4916946 PZ |
4562 | /* |
4563 | * This implements the workaround described in the "notes" section of the mode | |
4564 | * set sequence documentation. When going from no pipes or single pipe to | |
4565 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4566 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4567 | */ | |
4568 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4569 | { | |
4570 | struct drm_device *dev = crtc->base.dev; | |
4571 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4572 | ||
4573 | /* We want to get the other_active_crtc only if there's only 1 other | |
4574 | * active crtc. */ | |
d3fcc808 | 4575 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4576 | if (!crtc_it->active || crtc_it == crtc) |
4577 | continue; | |
4578 | ||
4579 | if (other_active_crtc) | |
4580 | return; | |
4581 | ||
4582 | other_active_crtc = crtc_it; | |
4583 | } | |
4584 | if (!other_active_crtc) | |
4585 | return; | |
4586 | ||
4587 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4588 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4589 | } | |
4590 | ||
4f771f10 PZ |
4591 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4592 | { | |
4593 | struct drm_device *dev = crtc->dev; | |
4594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4596 | struct intel_encoder *encoder; | |
4597 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4598 | |
83d65738 | 4599 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4600 | |
4601 | if (intel_crtc->active) | |
4602 | return; | |
4603 | ||
df8ad70c DV |
4604 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4605 | intel_enable_shared_dpll(intel_crtc); | |
4606 | ||
6e3c9717 | 4607 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4608 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4609 | |
4610 | intel_set_pipe_timings(intel_crtc); | |
4611 | ||
6e3c9717 ACO |
4612 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4613 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4614 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4615 | } |
4616 | ||
6e3c9717 | 4617 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4618 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4619 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4620 | } |
4621 | ||
4622 | haswell_set_pipeconf(crtc); | |
4623 | ||
4624 | intel_set_pipe_csc(crtc); | |
4625 | ||
4f771f10 | 4626 | intel_crtc->active = true; |
8664281b | 4627 | |
a72e4c9f | 4628 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4629 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4630 | if (encoder->pre_enable) | |
4631 | encoder->pre_enable(encoder); | |
4632 | ||
6e3c9717 | 4633 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4634 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4635 | true); | |
4fe9467d ID |
4636 | dev_priv->display.fdi_link_train(crtc); |
4637 | } | |
4638 | ||
1f544388 | 4639 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4640 | |
bd2e244f JB |
4641 | if (IS_SKYLAKE(dev)) |
4642 | skylake_pfit_enable(intel_crtc); | |
4643 | else | |
4644 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4645 | |
4646 | /* | |
4647 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4648 | * clocks enabled | |
4649 | */ | |
4650 | intel_crtc_load_lut(crtc); | |
4651 | ||
1f544388 | 4652 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4653 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4654 | |
f37fcc2a | 4655 | intel_update_watermarks(crtc); |
e1fdc473 | 4656 | intel_enable_pipe(intel_crtc); |
42db64ef | 4657 | |
6e3c9717 | 4658 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4659 | lpt_pch_enable(crtc); |
4f771f10 | 4660 | |
6e3c9717 | 4661 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4662 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4663 | ||
f9b61ff6 DV |
4664 | assert_vblank_disabled(crtc); |
4665 | drm_crtc_vblank_on(crtc); | |
4666 | ||
8807e55b | 4667 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4668 | encoder->enable(encoder); |
8807e55b JN |
4669 | intel_opregion_notify_encoder(encoder, true); |
4670 | } | |
4f771f10 | 4671 | |
e4916946 PZ |
4672 | /* If we change the relative order between pipe/planes enabling, we need |
4673 | * to change the workaround. */ | |
4674 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4675 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4676 | } |
4677 | ||
bd2e244f JB |
4678 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4679 | { | |
4680 | struct drm_device *dev = crtc->base.dev; | |
4681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4682 | int pipe = crtc->pipe; | |
4683 | ||
4684 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4685 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4686 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f JB |
4687 | I915_WRITE(PS_CTL(pipe), 0); |
4688 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4689 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4690 | } | |
4691 | } | |
4692 | ||
3f8dce3a DV |
4693 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4694 | { | |
4695 | struct drm_device *dev = crtc->base.dev; | |
4696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4697 | int pipe = crtc->pipe; | |
4698 | ||
4699 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4700 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4701 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4702 | I915_WRITE(PF_CTL(pipe), 0); |
4703 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4704 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4705 | } | |
4706 | } | |
4707 | ||
6be4a607 JB |
4708 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4709 | { | |
4710 | struct drm_device *dev = crtc->dev; | |
4711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4713 | struct intel_encoder *encoder; |
6be4a607 | 4714 | int pipe = intel_crtc->pipe; |
5eddb70b | 4715 | u32 reg, temp; |
b52eb4dc | 4716 | |
f7abfe8b CW |
4717 | if (!intel_crtc->active) |
4718 | return; | |
4719 | ||
d3eedb1a | 4720 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4721 | |
ea9d758d DV |
4722 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4723 | encoder->disable(encoder); | |
4724 | ||
f9b61ff6 DV |
4725 | drm_crtc_vblank_off(crtc); |
4726 | assert_vblank_disabled(crtc); | |
4727 | ||
6e3c9717 | 4728 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4729 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4730 | |
575f7ab7 | 4731 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4732 | |
3f8dce3a | 4733 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4734 | |
bf49ec8c DV |
4735 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4736 | if (encoder->post_disable) | |
4737 | encoder->post_disable(encoder); | |
2c07245f | 4738 | |
6e3c9717 | 4739 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4740 | ironlake_fdi_disable(crtc); |
913d8d11 | 4741 | |
d925c59a | 4742 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4743 | |
d925c59a DV |
4744 | if (HAS_PCH_CPT(dev)) { |
4745 | /* disable TRANS_DP_CTL */ | |
4746 | reg = TRANS_DP_CTL(pipe); | |
4747 | temp = I915_READ(reg); | |
4748 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4749 | TRANS_DP_PORT_SEL_MASK); | |
4750 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4751 | I915_WRITE(reg, temp); | |
4752 | ||
4753 | /* disable DPLL_SEL */ | |
4754 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4755 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4756 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4757 | } |
e3421a18 | 4758 | |
d925c59a | 4759 | /* disable PCH DPLL */ |
e72f9fbf | 4760 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4761 | |
d925c59a DV |
4762 | ironlake_fdi_pll_disable(intel_crtc); |
4763 | } | |
6b383a7f | 4764 | |
f7abfe8b | 4765 | intel_crtc->active = false; |
46ba614c | 4766 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4767 | |
4768 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4769 | intel_fbc_update(dev); |
d1ebd816 | 4770 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4771 | } |
1b3c7a47 | 4772 | |
4f771f10 | 4773 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4774 | { |
4f771f10 PZ |
4775 | struct drm_device *dev = crtc->dev; |
4776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4778 | struct intel_encoder *encoder; |
6e3c9717 | 4779 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 4780 | |
4f771f10 PZ |
4781 | if (!intel_crtc->active) |
4782 | return; | |
4783 | ||
d3eedb1a | 4784 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4785 | |
8807e55b JN |
4786 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4787 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4788 | encoder->disable(encoder); |
8807e55b | 4789 | } |
4f771f10 | 4790 | |
f9b61ff6 DV |
4791 | drm_crtc_vblank_off(crtc); |
4792 | assert_vblank_disabled(crtc); | |
4793 | ||
6e3c9717 | 4794 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
4795 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4796 | false); | |
575f7ab7 | 4797 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4798 | |
6e3c9717 | 4799 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
4800 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4801 | ||
ad80a810 | 4802 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4803 | |
bd2e244f JB |
4804 | if (IS_SKYLAKE(dev)) |
4805 | skylake_pfit_disable(intel_crtc); | |
4806 | else | |
4807 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4808 | |
1f544388 | 4809 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4810 | |
6e3c9717 | 4811 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 4812 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 4813 | intel_ddi_fdi_disable(crtc); |
83616634 | 4814 | } |
4f771f10 | 4815 | |
97b040aa ID |
4816 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4817 | if (encoder->post_disable) | |
4818 | encoder->post_disable(encoder); | |
4819 | ||
4f771f10 | 4820 | intel_crtc->active = false; |
46ba614c | 4821 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4822 | |
4823 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4824 | intel_fbc_update(dev); |
4f771f10 | 4825 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
4826 | |
4827 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4828 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4829 | } |
4830 | ||
ee7b9f93 JB |
4831 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4832 | { | |
4833 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4834 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4835 | } |
4836 | ||
6441ab5f | 4837 | |
2dd24552 JB |
4838 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4839 | { | |
4840 | struct drm_device *dev = crtc->base.dev; | |
4841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4842 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 4843 | |
681a8504 | 4844 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
4845 | return; |
4846 | ||
2dd24552 | 4847 | /* |
c0b03411 DV |
4848 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4849 | * according to register description and PRM. | |
2dd24552 | 4850 | */ |
c0b03411 DV |
4851 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4852 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4853 | |
b074cec8 JB |
4854 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4855 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4856 | |
4857 | /* Border color in case we don't scale up to the full screen. Black by | |
4858 | * default, change to something else for debugging. */ | |
4859 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4860 | } |
4861 | ||
d05410f9 DA |
4862 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4863 | { | |
4864 | switch (port) { | |
4865 | case PORT_A: | |
4866 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4867 | case PORT_B: | |
4868 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4869 | case PORT_C: | |
4870 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4871 | case PORT_D: | |
4872 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4873 | default: | |
4874 | WARN_ON_ONCE(1); | |
4875 | return POWER_DOMAIN_PORT_OTHER; | |
4876 | } | |
4877 | } | |
4878 | ||
77d22dca ID |
4879 | #define for_each_power_domain(domain, mask) \ |
4880 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4881 | if ((1 << (domain)) & (mask)) | |
4882 | ||
319be8ae ID |
4883 | enum intel_display_power_domain |
4884 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4885 | { | |
4886 | struct drm_device *dev = intel_encoder->base.dev; | |
4887 | struct intel_digital_port *intel_dig_port; | |
4888 | ||
4889 | switch (intel_encoder->type) { | |
4890 | case INTEL_OUTPUT_UNKNOWN: | |
4891 | /* Only DDI platforms should ever use this output type */ | |
4892 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4893 | case INTEL_OUTPUT_DISPLAYPORT: | |
4894 | case INTEL_OUTPUT_HDMI: | |
4895 | case INTEL_OUTPUT_EDP: | |
4896 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4897 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4898 | case INTEL_OUTPUT_DP_MST: |
4899 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4900 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4901 | case INTEL_OUTPUT_ANALOG: |
4902 | return POWER_DOMAIN_PORT_CRT; | |
4903 | case INTEL_OUTPUT_DSI: | |
4904 | return POWER_DOMAIN_PORT_DSI; | |
4905 | default: | |
4906 | return POWER_DOMAIN_PORT_OTHER; | |
4907 | } | |
4908 | } | |
4909 | ||
4910 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4911 | { |
319be8ae ID |
4912 | struct drm_device *dev = crtc->dev; |
4913 | struct intel_encoder *intel_encoder; | |
4914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4915 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4916 | unsigned long mask; |
4917 | enum transcoder transcoder; | |
4918 | ||
4919 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4920 | ||
4921 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4922 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
4923 | if (intel_crtc->config->pch_pfit.enabled || |
4924 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
4925 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4926 | ||
319be8ae ID |
4927 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4928 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4929 | ||
77d22dca ID |
4930 | return mask; |
4931 | } | |
4932 | ||
77d22dca ID |
4933 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
4934 | { | |
4935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4936 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4937 | struct intel_crtc *crtc; | |
4938 | ||
4939 | /* | |
4940 | * First get all needed power domains, then put all unneeded, to avoid | |
4941 | * any unnecessary toggling of the power wells. | |
4942 | */ | |
d3fcc808 | 4943 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4944 | enum intel_display_power_domain domain; |
4945 | ||
83d65738 | 4946 | if (!crtc->base.state->enable) |
77d22dca ID |
4947 | continue; |
4948 | ||
319be8ae | 4949 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4950 | |
4951 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4952 | intel_display_power_get(dev_priv, domain); | |
4953 | } | |
4954 | ||
50f6e502 VS |
4955 | if (dev_priv->display.modeset_global_resources) |
4956 | dev_priv->display.modeset_global_resources(dev); | |
4957 | ||
d3fcc808 | 4958 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4959 | enum intel_display_power_domain domain; |
4960 | ||
4961 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4962 | intel_display_power_put(dev_priv, domain); | |
4963 | ||
4964 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4965 | } | |
4966 | ||
4967 | intel_display_set_init_power(dev_priv, false); | |
4968 | } | |
4969 | ||
dfcab17e | 4970 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4971 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4972 | { |
586f49dc | 4973 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4974 | |
586f49dc JB |
4975 | /* Obtain SKU information */ |
4976 | mutex_lock(&dev_priv->dpio_lock); | |
4977 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4978 | CCK_FUSE_HPLL_FREQ_MASK; | |
4979 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4980 | |
dfcab17e | 4981 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4982 | } |
4983 | ||
f8bf63fd VS |
4984 | static void vlv_update_cdclk(struct drm_device *dev) |
4985 | { | |
4986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4987 | ||
4988 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 4989 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
4990 | dev_priv->vlv_cdclk_freq); |
4991 | ||
4992 | /* | |
4993 | * Program the gmbus_freq based on the cdclk frequency. | |
4994 | * BSpec erroneously claims we should aim for 4MHz, but | |
4995 | * in fact 1MHz is the correct frequency. | |
4996 | */ | |
6be1e3d3 | 4997 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
4998 | } |
4999 | ||
30a970c6 JB |
5000 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5001 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5002 | { | |
5003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5004 | u32 val, cmd; | |
5005 | ||
d197b7d3 | 5006 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 5007 | |
dfcab17e | 5008 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5009 | cmd = 2; |
dfcab17e | 5010 | else if (cdclk == 266667) |
30a970c6 JB |
5011 | cmd = 1; |
5012 | else | |
5013 | cmd = 0; | |
5014 | ||
5015 | mutex_lock(&dev_priv->rps.hw_lock); | |
5016 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5017 | val &= ~DSPFREQGUAR_MASK; | |
5018 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5019 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5020 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5021 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5022 | 50)) { | |
5023 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5024 | } | |
5025 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5026 | ||
dfcab17e | 5027 | if (cdclk == 400000) { |
6bcda4f0 | 5028 | u32 divider; |
30a970c6 | 5029 | |
6bcda4f0 | 5030 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5031 | |
5032 | mutex_lock(&dev_priv->dpio_lock); | |
5033 | /* adjust cdclk divider */ | |
5034 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5035 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5036 | val |= divider; |
5037 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5038 | |
5039 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5040 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5041 | 50)) | |
5042 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5043 | mutex_unlock(&dev_priv->dpio_lock); |
5044 | } | |
5045 | ||
5046 | mutex_lock(&dev_priv->dpio_lock); | |
5047 | /* adjust self-refresh exit latency value */ | |
5048 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5049 | val &= ~0x7f; | |
5050 | ||
5051 | /* | |
5052 | * For high bandwidth configs, we set a higher latency in the bunit | |
5053 | * so that the core display fetch happens in time to avoid underruns. | |
5054 | */ | |
dfcab17e | 5055 | if (cdclk == 400000) |
30a970c6 JB |
5056 | val |= 4500 / 250; /* 4.5 usec */ |
5057 | else | |
5058 | val |= 3000 / 250; /* 3.0 usec */ | |
5059 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5060 | mutex_unlock(&dev_priv->dpio_lock); | |
5061 | ||
f8bf63fd | 5062 | vlv_update_cdclk(dev); |
30a970c6 JB |
5063 | } |
5064 | ||
383c5a6a VS |
5065 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5066 | { | |
5067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5068 | u32 val, cmd; | |
5069 | ||
5070 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
5071 | ||
5072 | switch (cdclk) { | |
383c5a6a VS |
5073 | case 333333: |
5074 | case 320000: | |
383c5a6a | 5075 | case 266667: |
383c5a6a | 5076 | case 200000: |
383c5a6a VS |
5077 | break; |
5078 | default: | |
5f77eeb0 | 5079 | MISSING_CASE(cdclk); |
383c5a6a VS |
5080 | return; |
5081 | } | |
5082 | ||
9d0d3fda VS |
5083 | /* |
5084 | * Specs are full of misinformation, but testing on actual | |
5085 | * hardware has shown that we just need to write the desired | |
5086 | * CCK divider into the Punit register. | |
5087 | */ | |
5088 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5089 | ||
383c5a6a VS |
5090 | mutex_lock(&dev_priv->rps.hw_lock); |
5091 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5092 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5093 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5094 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5095 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5096 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5097 | 50)) { | |
5098 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5099 | } | |
5100 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5101 | ||
5102 | vlv_update_cdclk(dev); | |
5103 | } | |
5104 | ||
30a970c6 JB |
5105 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5106 | int max_pixclk) | |
5107 | { | |
6bcda4f0 | 5108 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5109 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5110 | |
30a970c6 JB |
5111 | /* |
5112 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5113 | * 200MHz | |
5114 | * 267MHz | |
29dc7ef3 | 5115 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5116 | * 400MHz (VLV only) |
5117 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5118 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5119 | * |
5120 | * We seem to get an unstable or solid color picture at 200MHz. | |
5121 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5122 | * are off. | |
30a970c6 | 5123 | */ |
6cca3195 VS |
5124 | if (!IS_CHERRYVIEW(dev_priv) && |
5125 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5126 | return 400000; |
6cca3195 | 5127 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5128 | return freq_320; |
e37c67a1 | 5129 | else if (max_pixclk > 0) |
dfcab17e | 5130 | return 266667; |
e37c67a1 VS |
5131 | else |
5132 | return 200000; | |
30a970c6 JB |
5133 | } |
5134 | ||
2f2d7aa1 VS |
5135 | /* compute the max pixel clock for new configuration */ |
5136 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
5137 | { |
5138 | struct drm_device *dev = dev_priv->dev; | |
5139 | struct intel_crtc *intel_crtc; | |
5140 | int max_pixclk = 0; | |
5141 | ||
d3fcc808 | 5142 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 5143 | if (intel_crtc->new_enabled) |
30a970c6 | 5144 | max_pixclk = max(max_pixclk, |
2d112de7 | 5145 | intel_crtc->new_config->base.adjusted_mode.crtc_clock); |
30a970c6 JB |
5146 | } |
5147 | ||
5148 | return max_pixclk; | |
5149 | } | |
5150 | ||
5151 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 5152 | unsigned *prepare_pipes) |
30a970c6 JB |
5153 | { |
5154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5155 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 5156 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 5157 | |
d60c4473 ID |
5158 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
5159 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
5160 | return; |
5161 | ||
2f2d7aa1 | 5162 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 5163 | for_each_intel_crtc(dev, intel_crtc) |
83d65738 | 5164 | if (intel_crtc->base.state->enable) |
30a970c6 JB |
5165 | *prepare_pipes |= (1 << intel_crtc->pipe); |
5166 | } | |
5167 | ||
1e69cd74 VS |
5168 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5169 | { | |
5170 | unsigned int credits, default_credits; | |
5171 | ||
5172 | if (IS_CHERRYVIEW(dev_priv)) | |
5173 | default_credits = PFI_CREDIT(12); | |
5174 | else | |
5175 | default_credits = PFI_CREDIT(8); | |
5176 | ||
5177 | if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { | |
5178 | /* CHV suggested value is 31 or 63 */ | |
5179 | if (IS_CHERRYVIEW(dev_priv)) | |
5180 | credits = PFI_CREDIT_31; | |
5181 | else | |
5182 | credits = PFI_CREDIT(15); | |
5183 | } else { | |
5184 | credits = default_credits; | |
5185 | } | |
5186 | ||
5187 | /* | |
5188 | * WA - write default credits before re-programming | |
5189 | * FIXME: should we also set the resend bit here? | |
5190 | */ | |
5191 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5192 | default_credits); | |
5193 | ||
5194 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5195 | credits | PFI_CREDIT_RESEND); | |
5196 | ||
5197 | /* | |
5198 | * FIXME is this guaranteed to clear | |
5199 | * immediately or should we poll for it? | |
5200 | */ | |
5201 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5202 | } | |
5203 | ||
30a970c6 JB |
5204 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
5205 | { | |
5206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 5207 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
5208 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
5209 | ||
383c5a6a | 5210 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
5211 | /* |
5212 | * FIXME: We can end up here with all power domains off, yet | |
5213 | * with a CDCLK frequency other than the minimum. To account | |
5214 | * for this take the PIPE-A power domain, which covers the HW | |
5215 | * blocks needed for the following programming. This can be | |
5216 | * removed once it's guaranteed that we get here either with | |
5217 | * the minimum CDCLK set, or the required power domains | |
5218 | * enabled. | |
5219 | */ | |
5220 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5221 | ||
383c5a6a VS |
5222 | if (IS_CHERRYVIEW(dev)) |
5223 | cherryview_set_cdclk(dev, req_cdclk); | |
5224 | else | |
5225 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5226 | |
1e69cd74 VS |
5227 | vlv_program_pfi_credits(dev_priv); |
5228 | ||
738c05c0 | 5229 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5230 | } |
30a970c6 JB |
5231 | } |
5232 | ||
89b667f8 JB |
5233 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5234 | { | |
5235 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5236 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5237 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5238 | struct intel_encoder *encoder; | |
5239 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5240 | bool is_dsi; |
89b667f8 | 5241 | |
83d65738 | 5242 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5243 | |
5244 | if (intel_crtc->active) | |
5245 | return; | |
5246 | ||
409ee761 | 5247 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5248 | |
1ae0d137 VS |
5249 | if (!is_dsi) { |
5250 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5251 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5252 | else |
6e3c9717 | 5253 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5254 | } |
5b18e57c | 5255 | |
6e3c9717 | 5256 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5257 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5258 | |
5259 | intel_set_pipe_timings(intel_crtc); | |
5260 | ||
c14b0485 VS |
5261 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5263 | ||
5264 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5265 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5266 | } | |
5267 | ||
5b18e57c DV |
5268 | i9xx_set_pipeconf(intel_crtc); |
5269 | ||
89b667f8 | 5270 | intel_crtc->active = true; |
89b667f8 | 5271 | |
a72e4c9f | 5272 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5273 | |
89b667f8 JB |
5274 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5275 | if (encoder->pre_pll_enable) | |
5276 | encoder->pre_pll_enable(encoder); | |
5277 | ||
9d556c99 CML |
5278 | if (!is_dsi) { |
5279 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5280 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5281 | else |
6e3c9717 | 5282 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5283 | } |
89b667f8 JB |
5284 | |
5285 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5286 | if (encoder->pre_enable) | |
5287 | encoder->pre_enable(encoder); | |
5288 | ||
2dd24552 JB |
5289 | i9xx_pfit_enable(intel_crtc); |
5290 | ||
63cbb074 VS |
5291 | intel_crtc_load_lut(crtc); |
5292 | ||
f37fcc2a | 5293 | intel_update_watermarks(crtc); |
e1fdc473 | 5294 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5295 | |
4b3a9526 VS |
5296 | assert_vblank_disabled(crtc); |
5297 | drm_crtc_vblank_on(crtc); | |
5298 | ||
f9b61ff6 DV |
5299 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5300 | encoder->enable(encoder); | |
5301 | ||
9ab0460b | 5302 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5303 | |
56b80e1f | 5304 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5305 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5306 | } |
5307 | ||
f13c2ef3 DV |
5308 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5309 | { | |
5310 | struct drm_device *dev = crtc->base.dev; | |
5311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5312 | ||
6e3c9717 ACO |
5313 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5314 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5315 | } |
5316 | ||
0b8765c6 | 5317 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5318 | { |
5319 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5320 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5321 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5322 | struct intel_encoder *encoder; |
79e53945 | 5323 | int pipe = intel_crtc->pipe; |
79e53945 | 5324 | |
83d65738 | 5325 | WARN_ON(!crtc->state->enable); |
08a48469 | 5326 | |
f7abfe8b CW |
5327 | if (intel_crtc->active) |
5328 | return; | |
5329 | ||
f13c2ef3 DV |
5330 | i9xx_set_pll_dividers(intel_crtc); |
5331 | ||
6e3c9717 | 5332 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5333 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5334 | |
5335 | intel_set_pipe_timings(intel_crtc); | |
5336 | ||
5b18e57c DV |
5337 | i9xx_set_pipeconf(intel_crtc); |
5338 | ||
f7abfe8b | 5339 | intel_crtc->active = true; |
6b383a7f | 5340 | |
4a3436e8 | 5341 | if (!IS_GEN2(dev)) |
a72e4c9f | 5342 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5343 | |
9d6d9f19 MK |
5344 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5345 | if (encoder->pre_enable) | |
5346 | encoder->pre_enable(encoder); | |
5347 | ||
f6736a1a DV |
5348 | i9xx_enable_pll(intel_crtc); |
5349 | ||
2dd24552 JB |
5350 | i9xx_pfit_enable(intel_crtc); |
5351 | ||
63cbb074 VS |
5352 | intel_crtc_load_lut(crtc); |
5353 | ||
f37fcc2a | 5354 | intel_update_watermarks(crtc); |
e1fdc473 | 5355 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5356 | |
4b3a9526 VS |
5357 | assert_vblank_disabled(crtc); |
5358 | drm_crtc_vblank_on(crtc); | |
5359 | ||
f9b61ff6 DV |
5360 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5361 | encoder->enable(encoder); | |
5362 | ||
9ab0460b | 5363 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5364 | |
4a3436e8 VS |
5365 | /* |
5366 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5367 | * So don't enable underrun reporting before at least some planes | |
5368 | * are enabled. | |
5369 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5370 | * but leave the pipe running. | |
5371 | */ | |
5372 | if (IS_GEN2(dev)) | |
a72e4c9f | 5373 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5374 | |
56b80e1f | 5375 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5376 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5377 | } |
79e53945 | 5378 | |
87476d63 DV |
5379 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5380 | { | |
5381 | struct drm_device *dev = crtc->base.dev; | |
5382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5383 | |
6e3c9717 | 5384 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5385 | return; |
87476d63 | 5386 | |
328d8e82 | 5387 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5388 | |
328d8e82 DV |
5389 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5390 | I915_READ(PFIT_CONTROL)); | |
5391 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5392 | } |
5393 | ||
0b8765c6 JB |
5394 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5395 | { | |
5396 | struct drm_device *dev = crtc->dev; | |
5397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5398 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5399 | struct intel_encoder *encoder; |
0b8765c6 | 5400 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5401 | |
f7abfe8b CW |
5402 | if (!intel_crtc->active) |
5403 | return; | |
5404 | ||
4a3436e8 VS |
5405 | /* |
5406 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5407 | * So diasble underrun reporting before all the planes get disabled. | |
5408 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5409 | * but leave the pipe running. | |
5410 | */ | |
5411 | if (IS_GEN2(dev)) | |
a72e4c9f | 5412 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5413 | |
564ed191 ID |
5414 | /* |
5415 | * Vblank time updates from the shadow to live plane control register | |
5416 | * are blocked if the memory self-refresh mode is active at that | |
5417 | * moment. So to make sure the plane gets truly disabled, disable | |
5418 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5419 | * will be checked/applied by the HW only at the next frame start | |
5420 | * event which is after the vblank start event, so we need to have a | |
5421 | * wait-for-vblank between disabling the plane and the pipe. | |
5422 | */ | |
5423 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5424 | intel_crtc_disable_planes(crtc); |
5425 | ||
6304cd91 VS |
5426 | /* |
5427 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5428 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5429 | * We also need to wait on all gmch platforms because of the |
5430 | * self-refresh mode constraint explained above. | |
6304cd91 | 5431 | */ |
564ed191 | 5432 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5433 | |
4b3a9526 VS |
5434 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5435 | encoder->disable(encoder); | |
5436 | ||
f9b61ff6 DV |
5437 | drm_crtc_vblank_off(crtc); |
5438 | assert_vblank_disabled(crtc); | |
5439 | ||
575f7ab7 | 5440 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5441 | |
87476d63 | 5442 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5443 | |
89b667f8 JB |
5444 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5445 | if (encoder->post_disable) | |
5446 | encoder->post_disable(encoder); | |
5447 | ||
409ee761 | 5448 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5449 | if (IS_CHERRYVIEW(dev)) |
5450 | chv_disable_pll(dev_priv, pipe); | |
5451 | else if (IS_VALLEYVIEW(dev)) | |
5452 | vlv_disable_pll(dev_priv, pipe); | |
5453 | else | |
1c4e0274 | 5454 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5455 | } |
0b8765c6 | 5456 | |
4a3436e8 | 5457 | if (!IS_GEN2(dev)) |
a72e4c9f | 5458 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5459 | |
f7abfe8b | 5460 | intel_crtc->active = false; |
46ba614c | 5461 | intel_update_watermarks(crtc); |
f37fcc2a | 5462 | |
efa9624e | 5463 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5464 | intel_fbc_update(dev); |
efa9624e | 5465 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5466 | } |
5467 | ||
ee7b9f93 JB |
5468 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5469 | { | |
5470 | } | |
5471 | ||
b04c5bd6 BF |
5472 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5473 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5474 | { |
5475 | struct drm_device *dev = crtc->dev; | |
5476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5477 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5478 | enum intel_display_power_domain domain; |
5479 | unsigned long domains; | |
976f8a20 | 5480 | |
0e572fe7 DV |
5481 | if (enable) { |
5482 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5483 | domains = get_crtc_power_domains(crtc); |
5484 | for_each_power_domain(domain, domains) | |
5485 | intel_display_power_get(dev_priv, domain); | |
5486 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5487 | |
5488 | dev_priv->display.crtc_enable(crtc); | |
5489 | } | |
5490 | } else { | |
5491 | if (intel_crtc->active) { | |
5492 | dev_priv->display.crtc_disable(crtc); | |
5493 | ||
e1e9fb84 DV |
5494 | domains = intel_crtc->enabled_power_domains; |
5495 | for_each_power_domain(domain, domains) | |
5496 | intel_display_power_put(dev_priv, domain); | |
5497 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5498 | } |
5499 | } | |
b04c5bd6 BF |
5500 | } |
5501 | ||
5502 | /** | |
5503 | * Sets the power management mode of the pipe and plane. | |
5504 | */ | |
5505 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5506 | { | |
5507 | struct drm_device *dev = crtc->dev; | |
5508 | struct intel_encoder *intel_encoder; | |
5509 | bool enable = false; | |
5510 | ||
5511 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5512 | enable |= intel_encoder->connectors_active; | |
5513 | ||
5514 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5515 | } |
5516 | ||
cdd59983 CW |
5517 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5518 | { | |
cdd59983 | 5519 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5520 | struct drm_connector *connector; |
ee7b9f93 | 5521 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5522 | |
976f8a20 | 5523 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 5524 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
5525 | |
5526 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5527 | dev_priv->display.off(crtc); |
5528 | ||
455a6808 | 5529 | crtc->primary->funcs->disable_plane(crtc->primary); |
976f8a20 DV |
5530 | |
5531 | /* Update computed state. */ | |
5532 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5533 | if (!connector->encoder || !connector->encoder->crtc) | |
5534 | continue; | |
5535 | ||
5536 | if (connector->encoder->crtc != crtc) | |
5537 | continue; | |
5538 | ||
5539 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5540 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5541 | } |
5542 | } | |
5543 | ||
ea5b213a | 5544 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5545 | { |
4ef69c7a | 5546 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5547 | |
ea5b213a CW |
5548 | drm_encoder_cleanup(encoder); |
5549 | kfree(intel_encoder); | |
7e7d76c3 JB |
5550 | } |
5551 | ||
9237329d | 5552 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5553 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5554 | * state of the entire output pipe. */ | |
9237329d | 5555 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5556 | { |
5ab432ef DV |
5557 | if (mode == DRM_MODE_DPMS_ON) { |
5558 | encoder->connectors_active = true; | |
5559 | ||
b2cabb0e | 5560 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5561 | } else { |
5562 | encoder->connectors_active = false; | |
5563 | ||
b2cabb0e | 5564 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5565 | } |
79e53945 JB |
5566 | } |
5567 | ||
0a91ca29 DV |
5568 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5569 | * internal consistency). */ | |
b980514c | 5570 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5571 | { |
0a91ca29 DV |
5572 | if (connector->get_hw_state(connector)) { |
5573 | struct intel_encoder *encoder = connector->encoder; | |
5574 | struct drm_crtc *crtc; | |
5575 | bool encoder_enabled; | |
5576 | enum pipe pipe; | |
5577 | ||
5578 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5579 | connector->base.base.id, | |
c23cc417 | 5580 | connector->base.name); |
0a91ca29 | 5581 | |
0e32b39c DA |
5582 | /* there is no real hw state for MST connectors */ |
5583 | if (connector->mst_port) | |
5584 | return; | |
5585 | ||
e2c719b7 | 5586 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 5587 | "wrong connector dpms state\n"); |
e2c719b7 | 5588 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 5589 | "active connector not linked to encoder\n"); |
0a91ca29 | 5590 | |
36cd7444 | 5591 | if (encoder) { |
e2c719b7 | 5592 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
5593 | "encoder->connectors_active not set\n"); |
5594 | ||
5595 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
5596 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
5597 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 5598 | return; |
0a91ca29 | 5599 | |
36cd7444 | 5600 | crtc = encoder->base.crtc; |
0a91ca29 | 5601 | |
83d65738 MR |
5602 | I915_STATE_WARN(!crtc->state->enable, |
5603 | "crtc not enabled\n"); | |
e2c719b7 RC |
5604 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5605 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
5606 | "encoder active on the wrong pipe\n"); |
5607 | } | |
0a91ca29 | 5608 | } |
79e53945 JB |
5609 | } |
5610 | ||
5ab432ef DV |
5611 | /* Even simpler default implementation, if there's really no special case to |
5612 | * consider. */ | |
5613 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5614 | { |
5ab432ef DV |
5615 | /* All the simple cases only support two dpms states. */ |
5616 | if (mode != DRM_MODE_DPMS_ON) | |
5617 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5618 | |
5ab432ef DV |
5619 | if (mode == connector->dpms) |
5620 | return; | |
5621 | ||
5622 | connector->dpms = mode; | |
5623 | ||
5624 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5625 | if (connector->encoder) |
5626 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5627 | |
b980514c | 5628 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5629 | } |
5630 | ||
f0947c37 DV |
5631 | /* Simple connector->get_hw_state implementation for encoders that support only |
5632 | * one connector and no cloning and hence the encoder state determines the state | |
5633 | * of the connector. */ | |
5634 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5635 | { |
24929352 | 5636 | enum pipe pipe = 0; |
f0947c37 | 5637 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5638 | |
f0947c37 | 5639 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5640 | } |
5641 | ||
d272ddfa VS |
5642 | static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe) |
5643 | { | |
5644 | struct intel_crtc *crtc = | |
5645 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5646 | ||
5647 | if (crtc->base.state->enable && | |
5648 | crtc->config->has_pch_encoder) | |
5649 | return crtc->config->fdi_lanes; | |
5650 | ||
5651 | return 0; | |
5652 | } | |
5653 | ||
1857e1da | 5654 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5655 | struct intel_crtc_state *pipe_config) |
1857e1da | 5656 | { |
1857e1da DV |
5657 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
5658 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5659 | if (pipe_config->fdi_lanes > 4) { | |
5660 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5661 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5662 | return false; | |
5663 | } | |
5664 | ||
bafb6553 | 5665 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5666 | if (pipe_config->fdi_lanes > 2) { |
5667 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5668 | pipe_config->fdi_lanes); | |
5669 | return false; | |
5670 | } else { | |
5671 | return true; | |
5672 | } | |
5673 | } | |
5674 | ||
5675 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5676 | return true; | |
5677 | ||
5678 | /* Ivybridge 3 pipe is really complicated */ | |
5679 | switch (pipe) { | |
5680 | case PIPE_A: | |
5681 | return true; | |
5682 | case PIPE_B: | |
d272ddfa VS |
5683 | if (pipe_config->fdi_lanes > 2 && |
5684 | pipe_required_fdi_lanes(dev, PIPE_C) > 0) { | |
1857e1da DV |
5685 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5686 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5687 | return false; | |
5688 | } | |
5689 | return true; | |
5690 | case PIPE_C: | |
251cc67c VS |
5691 | if (pipe_config->fdi_lanes > 2) { |
5692 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
5693 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5694 | return false; | |
5695 | } | |
d272ddfa | 5696 | if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) { |
1857e1da DV |
5697 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
5698 | return false; | |
5699 | } | |
5700 | return true; | |
5701 | default: | |
5702 | BUG(); | |
5703 | } | |
5704 | } | |
5705 | ||
e29c22c0 DV |
5706 | #define RETRY 1 |
5707 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 5708 | struct intel_crtc_state *pipe_config) |
877d48d5 | 5709 | { |
1857e1da | 5710 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 5711 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
ff9a6750 | 5712 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5713 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5714 | |
e29c22c0 | 5715 | retry: |
877d48d5 DV |
5716 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5717 | * each output octet as 10 bits. The actual frequency | |
5718 | * is stored as a divider into a 100MHz clock, and the | |
5719 | * mode pixel clock is stored in units of 1KHz. | |
5720 | * Hence the bw of each lane in terms of the mode signal | |
5721 | * is: | |
5722 | */ | |
5723 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5724 | ||
241bfc38 | 5725 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5726 | |
2bd89a07 | 5727 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5728 | pipe_config->pipe_bpp); |
5729 | ||
5730 | pipe_config->fdi_lanes = lane; | |
5731 | ||
2bd89a07 | 5732 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5733 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5734 | |
e29c22c0 DV |
5735 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5736 | intel_crtc->pipe, pipe_config); | |
5737 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5738 | pipe_config->pipe_bpp -= 2*3; | |
5739 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5740 | pipe_config->pipe_bpp); | |
5741 | needs_recompute = true; | |
5742 | pipe_config->bw_constrained = true; | |
5743 | ||
5744 | goto retry; | |
5745 | } | |
5746 | ||
5747 | if (needs_recompute) | |
5748 | return RETRY; | |
5749 | ||
5750 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5751 | } |
5752 | ||
42db64ef | 5753 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 5754 | struct intel_crtc_state *pipe_config) |
42db64ef | 5755 | { |
d330a953 | 5756 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5757 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5758 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5759 | } |
5760 | ||
a43f6e0f | 5761 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 5762 | struct intel_crtc_state *pipe_config) |
79e53945 | 5763 | { |
a43f6e0f | 5764 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5765 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 5766 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 5767 | |
ad3a4479 | 5768 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5769 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5770 | int clock_limit = |
5771 | dev_priv->display.get_display_clock_speed(dev); | |
5772 | ||
5773 | /* | |
5774 | * Enable pixel doubling when the dot clock | |
5775 | * is > 90% of the (display) core speed. | |
5776 | * | |
b397c96b VS |
5777 | * GDG double wide on either pipe, |
5778 | * otherwise pipe A only. | |
cf532bb2 | 5779 | */ |
b397c96b | 5780 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5781 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5782 | clock_limit *= 2; |
cf532bb2 | 5783 | pipe_config->double_wide = true; |
ad3a4479 VS |
5784 | } |
5785 | ||
241bfc38 | 5786 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5787 | return -EINVAL; |
2c07245f | 5788 | } |
89749350 | 5789 | |
1d1d0e27 VS |
5790 | /* |
5791 | * Pipe horizontal size must be even in: | |
5792 | * - DVO ganged mode | |
5793 | * - LVDS dual channel mode | |
5794 | * - Double wide pipe | |
5795 | */ | |
b4f2bf4c | 5796 | if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5797 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5798 | pipe_config->pipe_src_w &= ~1; | |
5799 | ||
8693a824 DL |
5800 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5801 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5802 | */ |
5803 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5804 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5805 | return -EINVAL; |
44f46b42 | 5806 | |
bd080ee5 | 5807 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5808 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5809 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5810 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5811 | * for lvds. */ | |
5812 | pipe_config->pipe_bpp = 8*3; | |
5813 | } | |
5814 | ||
f5adf94e | 5815 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5816 | hsw_compute_ips_config(crtc, pipe_config); |
5817 | ||
877d48d5 | 5818 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5819 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5820 | |
e29c22c0 | 5821 | return 0; |
79e53945 JB |
5822 | } |
5823 | ||
25eb05fc JB |
5824 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5825 | { | |
d197b7d3 | 5826 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
5827 | u32 val; |
5828 | int divider; | |
5829 | ||
6bcda4f0 VS |
5830 | if (dev_priv->hpll_freq == 0) |
5831 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
5832 | ||
d197b7d3 VS |
5833 | mutex_lock(&dev_priv->dpio_lock); |
5834 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5835 | mutex_unlock(&dev_priv->dpio_lock); | |
5836 | ||
5837 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5838 | ||
7d007f40 VS |
5839 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5840 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5841 | "cdclk change in progress\n"); | |
5842 | ||
6bcda4f0 | 5843 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
5844 | } |
5845 | ||
e70236a8 JB |
5846 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5847 | { | |
5848 | return 400000; | |
5849 | } | |
79e53945 | 5850 | |
e70236a8 | 5851 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5852 | { |
e70236a8 JB |
5853 | return 333000; |
5854 | } | |
79e53945 | 5855 | |
e70236a8 JB |
5856 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5857 | { | |
5858 | return 200000; | |
5859 | } | |
79e53945 | 5860 | |
257a7ffc DV |
5861 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5862 | { | |
5863 | u16 gcfgc = 0; | |
5864 | ||
5865 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5866 | ||
5867 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5868 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5869 | return 267000; | |
5870 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5871 | return 333000; | |
5872 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5873 | return 444000; | |
5874 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5875 | return 200000; | |
5876 | default: | |
5877 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5878 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5879 | return 133000; | |
5880 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5881 | return 167000; | |
5882 | } | |
5883 | } | |
5884 | ||
e70236a8 JB |
5885 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5886 | { | |
5887 | u16 gcfgc = 0; | |
79e53945 | 5888 | |
e70236a8 JB |
5889 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5890 | ||
5891 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5892 | return 133000; | |
5893 | else { | |
5894 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5895 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5896 | return 333000; | |
5897 | default: | |
5898 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5899 | return 190000; | |
79e53945 | 5900 | } |
e70236a8 JB |
5901 | } |
5902 | } | |
5903 | ||
5904 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5905 | { | |
5906 | return 266000; | |
5907 | } | |
5908 | ||
5909 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5910 | { | |
5911 | u16 hpllcc = 0; | |
5912 | /* Assume that the hardware is in the high speed state. This | |
5913 | * should be the default. | |
5914 | */ | |
5915 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5916 | case GC_CLOCK_133_200: | |
5917 | case GC_CLOCK_100_200: | |
5918 | return 200000; | |
5919 | case GC_CLOCK_166_250: | |
5920 | return 250000; | |
5921 | case GC_CLOCK_100_133: | |
79e53945 | 5922 | return 133000; |
e70236a8 | 5923 | } |
79e53945 | 5924 | |
e70236a8 JB |
5925 | /* Shouldn't happen */ |
5926 | return 0; | |
5927 | } | |
79e53945 | 5928 | |
e70236a8 JB |
5929 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5930 | { | |
5931 | return 133000; | |
79e53945 JB |
5932 | } |
5933 | ||
2c07245f | 5934 | static void |
a65851af | 5935 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5936 | { |
a65851af VS |
5937 | while (*num > DATA_LINK_M_N_MASK || |
5938 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5939 | *num >>= 1; |
5940 | *den >>= 1; | |
5941 | } | |
5942 | } | |
5943 | ||
a65851af VS |
5944 | static void compute_m_n(unsigned int m, unsigned int n, |
5945 | uint32_t *ret_m, uint32_t *ret_n) | |
5946 | { | |
5947 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5948 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5949 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5950 | } | |
5951 | ||
e69d0bc1 DV |
5952 | void |
5953 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5954 | int pixel_clock, int link_clock, | |
5955 | struct intel_link_m_n *m_n) | |
2c07245f | 5956 | { |
e69d0bc1 | 5957 | m_n->tu = 64; |
a65851af VS |
5958 | |
5959 | compute_m_n(bits_per_pixel * pixel_clock, | |
5960 | link_clock * nlanes * 8, | |
5961 | &m_n->gmch_m, &m_n->gmch_n); | |
5962 | ||
5963 | compute_m_n(pixel_clock, link_clock, | |
5964 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5965 | } |
5966 | ||
a7615030 CW |
5967 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5968 | { | |
d330a953 JN |
5969 | if (i915.panel_use_ssc >= 0) |
5970 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5971 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5972 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5973 | } |
5974 | ||
409ee761 | 5975 | static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
c65d77d8 | 5976 | { |
409ee761 | 5977 | struct drm_device *dev = crtc->base.dev; |
c65d77d8 JB |
5978 | struct drm_i915_private *dev_priv = dev->dev_private; |
5979 | int refclk; | |
5980 | ||
a0c4da24 | 5981 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5982 | refclk = 100000; |
d0737e1d | 5983 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5984 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5985 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5986 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5987 | } else if (!IS_GEN2(dev)) { |
5988 | refclk = 96000; | |
5989 | } else { | |
5990 | refclk = 48000; | |
5991 | } | |
5992 | ||
5993 | return refclk; | |
5994 | } | |
5995 | ||
7429e9d4 | 5996 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5997 | { |
7df00d7a | 5998 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5999 | } |
f47709a9 | 6000 | |
7429e9d4 DV |
6001 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6002 | { | |
6003 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6004 | } |
6005 | ||
f47709a9 | 6006 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6007 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6008 | intel_clock_t *reduced_clock) |
6009 | { | |
f47709a9 | 6010 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6011 | u32 fp, fp2 = 0; |
6012 | ||
6013 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6014 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6015 | if (reduced_clock) |
7429e9d4 | 6016 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6017 | } else { |
190f68c5 | 6018 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6019 | if (reduced_clock) |
7429e9d4 | 6020 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6021 | } |
6022 | ||
190f68c5 | 6023 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6024 | |
f47709a9 | 6025 | crtc->lowfreq_avail = false; |
e1f234bd | 6026 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
ab585dea | 6027 | reduced_clock) { |
190f68c5 | 6028 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6029 | crtc->lowfreq_avail = true; |
a7516a05 | 6030 | } else { |
190f68c5 | 6031 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6032 | } |
6033 | } | |
6034 | ||
5e69f97f CML |
6035 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6036 | pipe) | |
89b667f8 JB |
6037 | { |
6038 | u32 reg_val; | |
6039 | ||
6040 | /* | |
6041 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6042 | * and set it to a reasonable value instead. | |
6043 | */ | |
ab3c759a | 6044 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6045 | reg_val &= 0xffffff00; |
6046 | reg_val |= 0x00000030; | |
ab3c759a | 6047 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6048 | |
ab3c759a | 6049 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6050 | reg_val &= 0x8cffffff; |
6051 | reg_val = 0x8c000000; | |
ab3c759a | 6052 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6053 | |
ab3c759a | 6054 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6055 | reg_val &= 0xffffff00; |
ab3c759a | 6056 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6057 | |
ab3c759a | 6058 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6059 | reg_val &= 0x00ffffff; |
6060 | reg_val |= 0xb0000000; | |
ab3c759a | 6061 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6062 | } |
6063 | ||
b551842d DV |
6064 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6065 | struct intel_link_m_n *m_n) | |
6066 | { | |
6067 | struct drm_device *dev = crtc->base.dev; | |
6068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6069 | int pipe = crtc->pipe; | |
6070 | ||
e3b95f1e DV |
6071 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6072 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6073 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6074 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6075 | } |
6076 | ||
6077 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6078 | struct intel_link_m_n *m_n, |
6079 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6080 | { |
6081 | struct drm_device *dev = crtc->base.dev; | |
6082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6083 | int pipe = crtc->pipe; | |
6e3c9717 | 6084 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6085 | |
6086 | if (INTEL_INFO(dev)->gen >= 5) { | |
6087 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6088 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6089 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6090 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6091 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6092 | * for gen < 8) and if DRRS is supported (to make sure the | |
6093 | * registers are not unnecessarily accessed). | |
6094 | */ | |
44395bfe | 6095 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6096 | crtc->config->has_drrs) { |
f769cd24 VK |
6097 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6098 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6099 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6100 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6101 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6102 | } | |
b551842d | 6103 | } else { |
e3b95f1e DV |
6104 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6105 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6106 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6107 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6108 | } |
6109 | } | |
6110 | ||
fe3cd48d | 6111 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6112 | { |
fe3cd48d R |
6113 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6114 | ||
6115 | if (m_n == M1_N1) { | |
6116 | dp_m_n = &crtc->config->dp_m_n; | |
6117 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6118 | } else if (m_n == M2_N2) { | |
6119 | ||
6120 | /* | |
6121 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6122 | * needs to be programmed into M1_N1. | |
6123 | */ | |
6124 | dp_m_n = &crtc->config->dp_m2_n2; | |
6125 | } else { | |
6126 | DRM_ERROR("Unsupported divider value\n"); | |
6127 | return; | |
6128 | } | |
6129 | ||
6e3c9717 ACO |
6130 | if (crtc->config->has_pch_encoder) |
6131 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6132 | else |
fe3cd48d | 6133 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6134 | } |
6135 | ||
d288f65f | 6136 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6137 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6138 | { |
6139 | u32 dpll, dpll_md; | |
6140 | ||
6141 | /* | |
6142 | * Enable DPIO clock input. We should never disable the reference | |
6143 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6144 | * on it. | |
6145 | */ | |
6146 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6147 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6148 | /* We should never disable this, set it here for state tracking */ | |
6149 | if (crtc->pipe == PIPE_B) | |
6150 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6151 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6152 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6153 | |
d288f65f | 6154 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6155 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6156 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6157 | } |
6158 | ||
d288f65f | 6159 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6160 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6161 | { |
f47709a9 | 6162 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6163 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6164 | int pipe = crtc->pipe; |
bdd4b6a6 | 6165 | u32 mdiv; |
a0c4da24 | 6166 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6167 | u32 coreclk, reg_val; |
a0c4da24 | 6168 | |
09153000 DV |
6169 | mutex_lock(&dev_priv->dpio_lock); |
6170 | ||
d288f65f VS |
6171 | bestn = pipe_config->dpll.n; |
6172 | bestm1 = pipe_config->dpll.m1; | |
6173 | bestm2 = pipe_config->dpll.m2; | |
6174 | bestp1 = pipe_config->dpll.p1; | |
6175 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6176 | |
89b667f8 JB |
6177 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6178 | ||
6179 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6180 | if (pipe == PIPE_B) |
5e69f97f | 6181 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6182 | |
6183 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6184 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6185 | |
6186 | /* Disable target IRef on PLL */ | |
ab3c759a | 6187 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6188 | reg_val &= 0x00ffffff; |
ab3c759a | 6189 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6190 | |
6191 | /* Disable fast lock */ | |
ab3c759a | 6192 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6193 | |
6194 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6195 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6196 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6197 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6198 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6199 | |
6200 | /* | |
6201 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6202 | * but we don't support that). | |
6203 | * Note: don't use the DAC post divider as it seems unstable. | |
6204 | */ | |
6205 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6206 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6207 | |
a0c4da24 | 6208 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6209 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6210 | |
89b667f8 | 6211 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6212 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6213 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6214 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6215 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6216 | 0x009f0003); |
89b667f8 | 6217 | else |
ab3c759a | 6218 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6219 | 0x00d0000f); |
6220 | ||
681a8504 | 6221 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6222 | /* Use SSC source */ |
bdd4b6a6 | 6223 | if (pipe == PIPE_A) |
ab3c759a | 6224 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6225 | 0x0df40000); |
6226 | else | |
ab3c759a | 6227 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6228 | 0x0df70000); |
6229 | } else { /* HDMI or VGA */ | |
6230 | /* Use bend source */ | |
bdd4b6a6 | 6231 | if (pipe == PIPE_A) |
ab3c759a | 6232 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6233 | 0x0df70000); |
6234 | else | |
ab3c759a | 6235 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6236 | 0x0df40000); |
6237 | } | |
a0c4da24 | 6238 | |
ab3c759a | 6239 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6240 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6241 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6242 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6243 | coreclk |= 0x01000000; |
ab3c759a | 6244 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6245 | |
ab3c759a | 6246 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6247 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6248 | } |
6249 | ||
d288f65f | 6250 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6251 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6252 | { |
d288f65f | 6253 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6254 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6255 | DPLL_VCO_ENABLE; | |
6256 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6257 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6258 | |
d288f65f VS |
6259 | pipe_config->dpll_hw_state.dpll_md = |
6260 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6261 | } |
6262 | ||
d288f65f | 6263 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6264 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6265 | { |
6266 | struct drm_device *dev = crtc->base.dev; | |
6267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6268 | int pipe = crtc->pipe; | |
6269 | int dpll_reg = DPLL(crtc->pipe); | |
6270 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6271 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6272 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6273 | u32 dpio_val; |
9cbe40c1 | 6274 | int vco; |
9d556c99 | 6275 | |
d288f65f VS |
6276 | bestn = pipe_config->dpll.n; |
6277 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6278 | bestm1 = pipe_config->dpll.m1; | |
6279 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6280 | bestp1 = pipe_config->dpll.p1; | |
6281 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6282 | vco = pipe_config->dpll.vco; |
a945ce7e | 6283 | dpio_val = 0; |
9cbe40c1 | 6284 | loopfilter = 0; |
9d556c99 CML |
6285 | |
6286 | /* | |
6287 | * Enable Refclk and SSC | |
6288 | */ | |
a11b0703 | 6289 | I915_WRITE(dpll_reg, |
d288f65f | 6290 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6291 | |
6292 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6293 | |
9d556c99 CML |
6294 | /* p1 and p2 divider */ |
6295 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6296 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6297 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6298 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6299 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6300 | ||
6301 | /* Feedback post-divider - m2 */ | |
6302 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6303 | ||
6304 | /* Feedback refclk divider - n and m1 */ | |
6305 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6306 | DPIO_CHV_M1_DIV_BY_2 | | |
6307 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6308 | ||
6309 | /* M2 fraction division */ | |
a945ce7e VP |
6310 | if (bestm2_frac) |
6311 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6312 | |
6313 | /* M2 fraction division enable */ | |
a945ce7e VP |
6314 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6315 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6316 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6317 | if (bestm2_frac) | |
6318 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6319 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6320 | |
de3a0fde VP |
6321 | /* Program digital lock detect threshold */ |
6322 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6323 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6324 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6325 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6326 | if (!bestm2_frac) | |
6327 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6328 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6329 | ||
9d556c99 | 6330 | /* Loop filter */ |
9cbe40c1 VP |
6331 | if (vco == 5400000) { |
6332 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6333 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6334 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6335 | tribuf_calcntr = 0x9; | |
6336 | } else if (vco <= 6200000) { | |
6337 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6338 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6339 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6340 | tribuf_calcntr = 0x9; | |
6341 | } else if (vco <= 6480000) { | |
6342 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6343 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6344 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6345 | tribuf_calcntr = 0x8; | |
6346 | } else { | |
6347 | /* Not supported. Apply the same limits as in the max case */ | |
6348 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6349 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6350 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6351 | tribuf_calcntr = 0; | |
6352 | } | |
9d556c99 CML |
6353 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6354 | ||
968040b2 | 6355 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6356 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6357 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6358 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6359 | ||
9d556c99 CML |
6360 | /* AFC Recal */ |
6361 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6362 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6363 | DPIO_AFC_RECAL); | |
6364 | ||
6365 | mutex_unlock(&dev_priv->dpio_lock); | |
6366 | } | |
6367 | ||
d288f65f VS |
6368 | /** |
6369 | * vlv_force_pll_on - forcibly enable just the PLL | |
6370 | * @dev_priv: i915 private structure | |
6371 | * @pipe: pipe PLL to enable | |
6372 | * @dpll: PLL configuration | |
6373 | * | |
6374 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6375 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6376 | * be enabled. | |
6377 | */ | |
6378 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6379 | const struct dpll *dpll) | |
6380 | { | |
6381 | struct intel_crtc *crtc = | |
6382 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 6383 | struct intel_crtc_state pipe_config = { |
d288f65f VS |
6384 | .pixel_multiplier = 1, |
6385 | .dpll = *dpll, | |
6386 | }; | |
6387 | ||
6388 | if (IS_CHERRYVIEW(dev)) { | |
6389 | chv_update_pll(crtc, &pipe_config); | |
6390 | chv_prepare_pll(crtc, &pipe_config); | |
6391 | chv_enable_pll(crtc, &pipe_config); | |
6392 | } else { | |
6393 | vlv_update_pll(crtc, &pipe_config); | |
6394 | vlv_prepare_pll(crtc, &pipe_config); | |
6395 | vlv_enable_pll(crtc, &pipe_config); | |
6396 | } | |
6397 | } | |
6398 | ||
6399 | /** | |
6400 | * vlv_force_pll_off - forcibly disable just the PLL | |
6401 | * @dev_priv: i915 private structure | |
6402 | * @pipe: pipe PLL to disable | |
6403 | * | |
6404 | * Disable the PLL for @pipe. To be used in cases where we need | |
6405 | * the PLL enabled even when @pipe is not going to be enabled. | |
6406 | */ | |
6407 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6408 | { | |
6409 | if (IS_CHERRYVIEW(dev)) | |
6410 | chv_disable_pll(to_i915(dev), pipe); | |
6411 | else | |
6412 | vlv_disable_pll(to_i915(dev), pipe); | |
6413 | } | |
6414 | ||
f47709a9 | 6415 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6416 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6417 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6418 | int num_connectors) |
6419 | { | |
f47709a9 | 6420 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6421 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6422 | u32 dpll; |
6423 | bool is_sdvo; | |
190f68c5 | 6424 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6425 | |
190f68c5 | 6426 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6427 | |
d0737e1d ACO |
6428 | is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
6429 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6430 | |
6431 | dpll = DPLL_VGA_MODE_DIS; | |
6432 | ||
d0737e1d | 6433 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6434 | dpll |= DPLLB_MODE_LVDS; |
6435 | else | |
6436 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6437 | |
ef1b460d | 6438 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 6439 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6440 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6441 | } |
198a037f DV |
6442 | |
6443 | if (is_sdvo) | |
4a33e48d | 6444 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6445 | |
190f68c5 | 6446 | if (crtc_state->has_dp_encoder) |
4a33e48d | 6447 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6448 | |
6449 | /* compute bitmask from p1 value */ | |
6450 | if (IS_PINEVIEW(dev)) | |
6451 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6452 | else { | |
6453 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6454 | if (IS_G4X(dev) && reduced_clock) | |
6455 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6456 | } | |
6457 | switch (clock->p2) { | |
6458 | case 5: | |
6459 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6460 | break; | |
6461 | case 7: | |
6462 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6463 | break; | |
6464 | case 10: | |
6465 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6466 | break; | |
6467 | case 14: | |
6468 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6469 | break; | |
6470 | } | |
6471 | if (INTEL_INFO(dev)->gen >= 4) | |
6472 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6473 | ||
190f68c5 | 6474 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6475 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
d0737e1d | 6476 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6477 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6478 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6479 | else | |
6480 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6481 | ||
6482 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6483 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6484 | |
eb1cbe48 | 6485 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 6486 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6487 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6488 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6489 | } |
6490 | } | |
6491 | ||
f47709a9 | 6492 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6493 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6494 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6495 | int num_connectors) |
6496 | { | |
f47709a9 | 6497 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6498 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6499 | u32 dpll; |
190f68c5 | 6500 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6501 | |
190f68c5 | 6502 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6503 | |
eb1cbe48 DV |
6504 | dpll = DPLL_VGA_MODE_DIS; |
6505 | ||
d0737e1d | 6506 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6507 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6508 | } else { | |
6509 | if (clock->p1 == 2) | |
6510 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6511 | else | |
6512 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6513 | if (clock->p2 == 4) | |
6514 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6515 | } | |
6516 | ||
d0737e1d | 6517 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6518 | dpll |= DPLL_DVO_2X_MODE; |
6519 | ||
d0737e1d | 6520 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6521 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6522 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6523 | else | |
6524 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6525 | ||
6526 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6527 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6528 | } |
6529 | ||
8a654f3b | 6530 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6531 | { |
6532 | struct drm_device *dev = intel_crtc->base.dev; | |
6533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6534 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 6535 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 6536 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 6537 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6538 | uint32_t crtc_vtotal, crtc_vblank_end; |
6539 | int vsyncshift = 0; | |
4d8a62ea DV |
6540 | |
6541 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6542 | * the hw state checker will get angry at the mismatch. */ | |
6543 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6544 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6545 | |
609aeaca | 6546 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6547 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6548 | crtc_vtotal -= 1; |
6549 | crtc_vblank_end -= 1; | |
609aeaca | 6550 | |
409ee761 | 6551 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6552 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6553 | else | |
6554 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6555 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6556 | if (vsyncshift < 0) |
6557 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6558 | } |
6559 | ||
6560 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6561 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6562 | |
fe2b8f9d | 6563 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6564 | (adjusted_mode->crtc_hdisplay - 1) | |
6565 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6566 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6567 | (adjusted_mode->crtc_hblank_start - 1) | |
6568 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6569 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6570 | (adjusted_mode->crtc_hsync_start - 1) | |
6571 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6572 | ||
fe2b8f9d | 6573 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6574 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6575 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6576 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6577 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6578 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6579 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6580 | (adjusted_mode->crtc_vsync_start - 1) | |
6581 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6582 | ||
b5e508d4 PZ |
6583 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6584 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6585 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6586 | * bits. */ | |
6587 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6588 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6589 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6590 | ||
b0e77b9c PZ |
6591 | /* pipesrc controls the size that is scaled from, which should |
6592 | * always be the user's requested size. | |
6593 | */ | |
6594 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6595 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6596 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6597 | } |
6598 | ||
1bd1bd80 | 6599 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6600 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6601 | { |
6602 | struct drm_device *dev = crtc->base.dev; | |
6603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6604 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6605 | uint32_t tmp; | |
6606 | ||
6607 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6608 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6609 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6610 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6611 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6612 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6613 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6614 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6615 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6616 | |
6617 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6618 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6619 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6620 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6621 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6622 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6623 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6624 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6625 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6626 | |
6627 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6628 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6629 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6630 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
6631 | } |
6632 | ||
6633 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6634 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6635 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6636 | ||
2d112de7 ACO |
6637 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6638 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6639 | } |
6640 | ||
f6a83288 | 6641 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6642 | struct intel_crtc_state *pipe_config) |
babea61d | 6643 | { |
2d112de7 ACO |
6644 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6645 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6646 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6647 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6648 | |
2d112de7 ACO |
6649 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6650 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6651 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6652 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6653 | |
2d112de7 | 6654 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 6655 | |
2d112de7 ACO |
6656 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
6657 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
6658 | } |
6659 | ||
84b046f3 DV |
6660 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6661 | { | |
6662 | struct drm_device *dev = intel_crtc->base.dev; | |
6663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6664 | uint32_t pipeconf; | |
6665 | ||
9f11a9e4 | 6666 | pipeconf = 0; |
84b046f3 | 6667 | |
b6b5d049 VS |
6668 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6669 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6670 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6671 | |
6e3c9717 | 6672 | if (intel_crtc->config->double_wide) |
cf532bb2 | 6673 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 6674 | |
ff9ce46e DV |
6675 | /* only g4x and later have fancy bpc/dither controls */ |
6676 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 6677 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 6678 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 6679 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 6680 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6681 | |
6e3c9717 | 6682 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
6683 | case 18: |
6684 | pipeconf |= PIPECONF_6BPC; | |
6685 | break; | |
6686 | case 24: | |
6687 | pipeconf |= PIPECONF_8BPC; | |
6688 | break; | |
6689 | case 30: | |
6690 | pipeconf |= PIPECONF_10BPC; | |
6691 | break; | |
6692 | default: | |
6693 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6694 | BUG(); | |
84b046f3 DV |
6695 | } |
6696 | } | |
6697 | ||
6698 | if (HAS_PIPE_CXSR(dev)) { | |
6699 | if (intel_crtc->lowfreq_avail) { | |
6700 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6701 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6702 | } else { | |
6703 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6704 | } |
6705 | } | |
6706 | ||
6e3c9717 | 6707 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 6708 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 6709 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6710 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6711 | else | |
6712 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6713 | } else | |
84b046f3 DV |
6714 | pipeconf |= PIPECONF_PROGRESSIVE; |
6715 | ||
6e3c9717 | 6716 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 6717 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 6718 | |
84b046f3 DV |
6719 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6720 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6721 | } | |
6722 | ||
190f68c5 ACO |
6723 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
6724 | struct intel_crtc_state *crtc_state) | |
79e53945 | 6725 | { |
c7653199 | 6726 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6727 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6728 | int refclk, num_connectors = 0; |
652c393a | 6729 | intel_clock_t clock, reduced_clock; |
a16af721 | 6730 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6731 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6732 | struct intel_encoder *encoder; |
d4906093 | 6733 | const intel_limit_t *limit; |
79e53945 | 6734 | |
d0737e1d ACO |
6735 | for_each_intel_encoder(dev, encoder) { |
6736 | if (encoder->new_crtc != crtc) | |
6737 | continue; | |
6738 | ||
5eddb70b | 6739 | switch (encoder->type) { |
79e53945 JB |
6740 | case INTEL_OUTPUT_LVDS: |
6741 | is_lvds = true; | |
6742 | break; | |
e9fd1c02 JN |
6743 | case INTEL_OUTPUT_DSI: |
6744 | is_dsi = true; | |
6745 | break; | |
6847d71b PZ |
6746 | default: |
6747 | break; | |
79e53945 | 6748 | } |
43565a06 | 6749 | |
c751ce4f | 6750 | num_connectors++; |
79e53945 JB |
6751 | } |
6752 | ||
f2335330 | 6753 | if (is_dsi) |
5b18e57c | 6754 | return 0; |
f2335330 | 6755 | |
190f68c5 | 6756 | if (!crtc_state->clock_set) { |
409ee761 | 6757 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 6758 | |
e9fd1c02 JN |
6759 | /* |
6760 | * Returns a set of divisors for the desired target clock with | |
6761 | * the given refclk, or FALSE. The returned values represent | |
6762 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6763 | * 2) / p1 / p2. | |
6764 | */ | |
409ee761 | 6765 | limit = intel_limit(crtc, refclk); |
c7653199 | 6766 | ok = dev_priv->display.find_dpll(limit, crtc, |
190f68c5 | 6767 | crtc_state->port_clock, |
e9fd1c02 | 6768 | refclk, NULL, &clock); |
f2335330 | 6769 | if (!ok) { |
e9fd1c02 JN |
6770 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6771 | return -EINVAL; | |
6772 | } | |
79e53945 | 6773 | |
f2335330 JN |
6774 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6775 | /* | |
6776 | * Ensure we match the reduced clock's P to the target | |
6777 | * clock. If the clocks don't match, we can't switch | |
6778 | * the display clock by using the FP0/FP1. In such case | |
6779 | * we will disable the LVDS downclock feature. | |
6780 | */ | |
6781 | has_reduced_clock = | |
c7653199 | 6782 | dev_priv->display.find_dpll(limit, crtc, |
f2335330 JN |
6783 | dev_priv->lvds_downclock, |
6784 | refclk, &clock, | |
6785 | &reduced_clock); | |
6786 | } | |
6787 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
6788 | crtc_state->dpll.n = clock.n; |
6789 | crtc_state->dpll.m1 = clock.m1; | |
6790 | crtc_state->dpll.m2 = clock.m2; | |
6791 | crtc_state->dpll.p1 = clock.p1; | |
6792 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 6793 | } |
7026d4ac | 6794 | |
e9fd1c02 | 6795 | if (IS_GEN2(dev)) { |
190f68c5 | 6796 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
6797 | has_reduced_clock ? &reduced_clock : NULL, |
6798 | num_connectors); | |
9d556c99 | 6799 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 6800 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6801 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 6802 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6803 | } else { |
190f68c5 | 6804 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 6805 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6806 | num_connectors); |
e9fd1c02 | 6807 | } |
79e53945 | 6808 | |
c8f7a0db | 6809 | return 0; |
f564048e EA |
6810 | } |
6811 | ||
2fa2fe9a | 6812 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 6813 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
6814 | { |
6815 | struct drm_device *dev = crtc->base.dev; | |
6816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6817 | uint32_t tmp; | |
6818 | ||
dc9e7dec VS |
6819 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6820 | return; | |
6821 | ||
2fa2fe9a | 6822 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6823 | if (!(tmp & PFIT_ENABLE)) |
6824 | return; | |
2fa2fe9a | 6825 | |
06922821 | 6826 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6827 | if (INTEL_INFO(dev)->gen < 4) { |
6828 | if (crtc->pipe != PIPE_B) | |
6829 | return; | |
2fa2fe9a DV |
6830 | } else { |
6831 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6832 | return; | |
6833 | } | |
6834 | ||
06922821 | 6835 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6836 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6837 | if (INTEL_INFO(dev)->gen < 5) | |
6838 | pipe_config->gmch_pfit.lvds_border_bits = | |
6839 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6840 | } | |
6841 | ||
acbec814 | 6842 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6843 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
6844 | { |
6845 | struct drm_device *dev = crtc->base.dev; | |
6846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6847 | int pipe = pipe_config->cpu_transcoder; | |
6848 | intel_clock_t clock; | |
6849 | u32 mdiv; | |
662c6ecb | 6850 | int refclk = 100000; |
acbec814 | 6851 | |
f573de5a SK |
6852 | /* In case of MIPI DPLL will not even be used */ |
6853 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6854 | return; | |
6855 | ||
acbec814 | 6856 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6857 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6858 | mutex_unlock(&dev_priv->dpio_lock); |
6859 | ||
6860 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6861 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6862 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6863 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6864 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6865 | ||
f646628b | 6866 | vlv_clock(refclk, &clock); |
acbec814 | 6867 | |
f646628b VS |
6868 | /* clock.dot is the fast clock */ |
6869 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6870 | } |
6871 | ||
5724dbd1 DL |
6872 | static void |
6873 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
6874 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
6875 | { |
6876 | struct drm_device *dev = crtc->base.dev; | |
6877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6878 | u32 val, base, offset; | |
6879 | int pipe = crtc->pipe, plane = crtc->plane; | |
6880 | int fourcc, pixel_format; | |
6761dd31 | 6881 | unsigned int aligned_height; |
b113d5ee | 6882 | struct drm_framebuffer *fb; |
1b842c89 | 6883 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 6884 | |
42a7b088 DL |
6885 | val = I915_READ(DSPCNTR(plane)); |
6886 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
6887 | return; | |
6888 | ||
d9806c9f | 6889 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 6890 | if (!intel_fb) { |
1ad292b5 JB |
6891 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6892 | return; | |
6893 | } | |
6894 | ||
1b842c89 DL |
6895 | fb = &intel_fb->base; |
6896 | ||
18c5247e DV |
6897 | if (INTEL_INFO(dev)->gen >= 4) { |
6898 | if (val & DISPPLANE_TILED) { | |
49af449b | 6899 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
6900 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
6901 | } | |
6902 | } | |
1ad292b5 JB |
6903 | |
6904 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 6905 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
6906 | fb->pixel_format = fourcc; |
6907 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
6908 | |
6909 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 6910 | if (plane_config->tiling) |
1ad292b5 JB |
6911 | offset = I915_READ(DSPTILEOFF(plane)); |
6912 | else | |
6913 | offset = I915_READ(DSPLINOFF(plane)); | |
6914 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6915 | } else { | |
6916 | base = I915_READ(DSPADDR(plane)); | |
6917 | } | |
6918 | plane_config->base = base; | |
6919 | ||
6920 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
6921 | fb->width = ((val >> 16) & 0xfff) + 1; |
6922 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6923 | |
6924 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 6925 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6926 | |
b113d5ee | 6927 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
6928 | fb->pixel_format, |
6929 | fb->modifier[0]); | |
1ad292b5 | 6930 | |
f37b5c2b | 6931 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 6932 | |
2844a921 DL |
6933 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
6934 | pipe_name(pipe), plane, fb->width, fb->height, | |
6935 | fb->bits_per_pixel, base, fb->pitches[0], | |
6936 | plane_config->size); | |
1ad292b5 | 6937 | |
2d14030b | 6938 | plane_config->fb = intel_fb; |
1ad292b5 JB |
6939 | } |
6940 | ||
70b23a98 | 6941 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6942 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
6943 | { |
6944 | struct drm_device *dev = crtc->base.dev; | |
6945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6946 | int pipe = pipe_config->cpu_transcoder; | |
6947 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6948 | intel_clock_t clock; | |
6949 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6950 | int refclk = 100000; | |
6951 | ||
6952 | mutex_lock(&dev_priv->dpio_lock); | |
6953 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6954 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6955 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6956 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6957 | mutex_unlock(&dev_priv->dpio_lock); | |
6958 | ||
6959 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6960 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6961 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6962 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6963 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6964 | ||
6965 | chv_clock(refclk, &clock); | |
6966 | ||
6967 | /* clock.dot is the fast clock */ | |
6968 | pipe_config->port_clock = clock.dot / 5; | |
6969 | } | |
6970 | ||
0e8ffe1b | 6971 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 6972 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
6973 | { |
6974 | struct drm_device *dev = crtc->base.dev; | |
6975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6976 | uint32_t tmp; | |
6977 | ||
f458ebbc DV |
6978 | if (!intel_display_power_is_enabled(dev_priv, |
6979 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
6980 | return false; |
6981 | ||
e143a21c | 6982 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6983 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6984 | |
0e8ffe1b DV |
6985 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6986 | if (!(tmp & PIPECONF_ENABLE)) | |
6987 | return false; | |
6988 | ||
42571aef VS |
6989 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6990 | switch (tmp & PIPECONF_BPC_MASK) { | |
6991 | case PIPECONF_6BPC: | |
6992 | pipe_config->pipe_bpp = 18; | |
6993 | break; | |
6994 | case PIPECONF_8BPC: | |
6995 | pipe_config->pipe_bpp = 24; | |
6996 | break; | |
6997 | case PIPECONF_10BPC: | |
6998 | pipe_config->pipe_bpp = 30; | |
6999 | break; | |
7000 | default: | |
7001 | break; | |
7002 | } | |
7003 | } | |
7004 | ||
b5a9fa09 DV |
7005 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7006 | pipe_config->limited_color_range = true; | |
7007 | ||
282740f7 VS |
7008 | if (INTEL_INFO(dev)->gen < 4) |
7009 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7010 | ||
1bd1bd80 DV |
7011 | intel_get_pipe_timings(crtc, pipe_config); |
7012 | ||
2fa2fe9a DV |
7013 | i9xx_get_pfit_config(crtc, pipe_config); |
7014 | ||
6c49f241 DV |
7015 | if (INTEL_INFO(dev)->gen >= 4) { |
7016 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7017 | pipe_config->pixel_multiplier = | |
7018 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7019 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7020 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7021 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7022 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7023 | pipe_config->pixel_multiplier = | |
7024 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7025 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7026 | } else { | |
7027 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7028 | * port and will be fixed up in the encoder->get_config | |
7029 | * function. */ | |
7030 | pipe_config->pixel_multiplier = 1; | |
7031 | } | |
8bcc2795 DV |
7032 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7033 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7034 | /* |
7035 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7036 | * on 830. Filter it out here so that we don't | |
7037 | * report errors due to that. | |
7038 | */ | |
7039 | if (IS_I830(dev)) | |
7040 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7041 | ||
8bcc2795 DV |
7042 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7043 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7044 | } else { |
7045 | /* Mask out read-only status bits. */ | |
7046 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7047 | DPLL_PORTC_READY_MASK | | |
7048 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7049 | } |
6c49f241 | 7050 | |
70b23a98 VS |
7051 | if (IS_CHERRYVIEW(dev)) |
7052 | chv_crtc_clock_get(crtc, pipe_config); | |
7053 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7054 | vlv_crtc_clock_get(crtc, pipe_config); |
7055 | else | |
7056 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7057 | |
0e8ffe1b DV |
7058 | return true; |
7059 | } | |
7060 | ||
dde86e2d | 7061 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7062 | { |
7063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7064 | struct intel_encoder *encoder; |
74cfd7ac | 7065 | u32 val, final; |
13d83a67 | 7066 | bool has_lvds = false; |
199e5d79 | 7067 | bool has_cpu_edp = false; |
199e5d79 | 7068 | bool has_panel = false; |
99eb6a01 KP |
7069 | bool has_ck505 = false; |
7070 | bool can_ssc = false; | |
13d83a67 JB |
7071 | |
7072 | /* We need to take the global config into account */ | |
b2784e15 | 7073 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7074 | switch (encoder->type) { |
7075 | case INTEL_OUTPUT_LVDS: | |
7076 | has_panel = true; | |
7077 | has_lvds = true; | |
7078 | break; | |
7079 | case INTEL_OUTPUT_EDP: | |
7080 | has_panel = true; | |
2de6905f | 7081 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7082 | has_cpu_edp = true; |
7083 | break; | |
6847d71b PZ |
7084 | default: |
7085 | break; | |
13d83a67 JB |
7086 | } |
7087 | } | |
7088 | ||
99eb6a01 | 7089 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7090 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7091 | can_ssc = has_ck505; |
7092 | } else { | |
7093 | has_ck505 = false; | |
7094 | can_ssc = true; | |
7095 | } | |
7096 | ||
2de6905f ID |
7097 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7098 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7099 | |
7100 | /* Ironlake: try to setup display ref clock before DPLL | |
7101 | * enabling. This is only under driver's control after | |
7102 | * PCH B stepping, previous chipset stepping should be | |
7103 | * ignoring this setting. | |
7104 | */ | |
74cfd7ac CW |
7105 | val = I915_READ(PCH_DREF_CONTROL); |
7106 | ||
7107 | /* As we must carefully and slowly disable/enable each source in turn, | |
7108 | * compute the final state we want first and check if we need to | |
7109 | * make any changes at all. | |
7110 | */ | |
7111 | final = val; | |
7112 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7113 | if (has_ck505) | |
7114 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7115 | else | |
7116 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7117 | ||
7118 | final &= ~DREF_SSC_SOURCE_MASK; | |
7119 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7120 | final &= ~DREF_SSC1_ENABLE; | |
7121 | ||
7122 | if (has_panel) { | |
7123 | final |= DREF_SSC_SOURCE_ENABLE; | |
7124 | ||
7125 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7126 | final |= DREF_SSC1_ENABLE; | |
7127 | ||
7128 | if (has_cpu_edp) { | |
7129 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7130 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7131 | else | |
7132 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7133 | } else | |
7134 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7135 | } else { | |
7136 | final |= DREF_SSC_SOURCE_DISABLE; | |
7137 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7138 | } | |
7139 | ||
7140 | if (final == val) | |
7141 | return; | |
7142 | ||
13d83a67 | 7143 | /* Always enable nonspread source */ |
74cfd7ac | 7144 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7145 | |
99eb6a01 | 7146 | if (has_ck505) |
74cfd7ac | 7147 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7148 | else |
74cfd7ac | 7149 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7150 | |
199e5d79 | 7151 | if (has_panel) { |
74cfd7ac CW |
7152 | val &= ~DREF_SSC_SOURCE_MASK; |
7153 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7154 | |
199e5d79 | 7155 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7156 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7157 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7158 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7159 | } else |
74cfd7ac | 7160 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7161 | |
7162 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7163 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7164 | POSTING_READ(PCH_DREF_CONTROL); |
7165 | udelay(200); | |
7166 | ||
74cfd7ac | 7167 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7168 | |
7169 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7170 | if (has_cpu_edp) { |
99eb6a01 | 7171 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7172 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7173 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7174 | } else |
74cfd7ac | 7175 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7176 | } else |
74cfd7ac | 7177 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7178 | |
74cfd7ac | 7179 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7180 | POSTING_READ(PCH_DREF_CONTROL); |
7181 | udelay(200); | |
7182 | } else { | |
7183 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7184 | ||
74cfd7ac | 7185 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7186 | |
7187 | /* Turn off CPU output */ | |
74cfd7ac | 7188 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7189 | |
74cfd7ac | 7190 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7191 | POSTING_READ(PCH_DREF_CONTROL); |
7192 | udelay(200); | |
7193 | ||
7194 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7195 | val &= ~DREF_SSC_SOURCE_MASK; |
7196 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7197 | |
7198 | /* Turn off SSC1 */ | |
74cfd7ac | 7199 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7200 | |
74cfd7ac | 7201 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7202 | POSTING_READ(PCH_DREF_CONTROL); |
7203 | udelay(200); | |
7204 | } | |
74cfd7ac CW |
7205 | |
7206 | BUG_ON(val != final); | |
13d83a67 JB |
7207 | } |
7208 | ||
f31f2d55 | 7209 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7210 | { |
f31f2d55 | 7211 | uint32_t tmp; |
dde86e2d | 7212 | |
0ff066a9 PZ |
7213 | tmp = I915_READ(SOUTH_CHICKEN2); |
7214 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7215 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7216 | |
0ff066a9 PZ |
7217 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7218 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7219 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7220 | |
0ff066a9 PZ |
7221 | tmp = I915_READ(SOUTH_CHICKEN2); |
7222 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7223 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7224 | |
0ff066a9 PZ |
7225 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7226 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7227 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7228 | } |
7229 | ||
7230 | /* WaMPhyProgramming:hsw */ | |
7231 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7232 | { | |
7233 | uint32_t tmp; | |
dde86e2d PZ |
7234 | |
7235 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7236 | tmp &= ~(0xFF << 24); | |
7237 | tmp |= (0x12 << 24); | |
7238 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7239 | ||
dde86e2d PZ |
7240 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7241 | tmp |= (1 << 11); | |
7242 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7243 | ||
7244 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7245 | tmp |= (1 << 11); | |
7246 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7247 | ||
dde86e2d PZ |
7248 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7249 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7250 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7251 | ||
7252 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7253 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7254 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7255 | ||
0ff066a9 PZ |
7256 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7257 | tmp &= ~(7 << 13); | |
7258 | tmp |= (5 << 13); | |
7259 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7260 | |
0ff066a9 PZ |
7261 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7262 | tmp &= ~(7 << 13); | |
7263 | tmp |= (5 << 13); | |
7264 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7265 | |
7266 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7267 | tmp &= ~0xFF; | |
7268 | tmp |= 0x1C; | |
7269 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7270 | ||
7271 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7272 | tmp &= ~0xFF; | |
7273 | tmp |= 0x1C; | |
7274 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7275 | ||
7276 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7277 | tmp &= ~(0xFF << 16); | |
7278 | tmp |= (0x1C << 16); | |
7279 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7280 | ||
7281 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7282 | tmp &= ~(0xFF << 16); | |
7283 | tmp |= (0x1C << 16); | |
7284 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7285 | ||
0ff066a9 PZ |
7286 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7287 | tmp |= (1 << 27); | |
7288 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7289 | |
0ff066a9 PZ |
7290 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7291 | tmp |= (1 << 27); | |
7292 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7293 | |
0ff066a9 PZ |
7294 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7295 | tmp &= ~(0xF << 28); | |
7296 | tmp |= (4 << 28); | |
7297 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7298 | |
0ff066a9 PZ |
7299 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7300 | tmp &= ~(0xF << 28); | |
7301 | tmp |= (4 << 28); | |
7302 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7303 | } |
7304 | ||
2fa86a1f PZ |
7305 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7306 | * Programming" based on the parameters passed: | |
7307 | * - Sequence to enable CLKOUT_DP | |
7308 | * - Sequence to enable CLKOUT_DP without spread | |
7309 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7310 | */ | |
7311 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7312 | bool with_fdi) | |
f31f2d55 PZ |
7313 | { |
7314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7315 | uint32_t reg, tmp; |
7316 | ||
7317 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7318 | with_spread = true; | |
7319 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7320 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7321 | with_fdi = false; | |
f31f2d55 PZ |
7322 | |
7323 | mutex_lock(&dev_priv->dpio_lock); | |
7324 | ||
7325 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7326 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7327 | tmp |= SBI_SSCCTL_PATHALT; | |
7328 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7329 | ||
7330 | udelay(24); | |
7331 | ||
2fa86a1f PZ |
7332 | if (with_spread) { |
7333 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7334 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7335 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7336 | |
2fa86a1f PZ |
7337 | if (with_fdi) { |
7338 | lpt_reset_fdi_mphy(dev_priv); | |
7339 | lpt_program_fdi_mphy(dev_priv); | |
7340 | } | |
7341 | } | |
dde86e2d | 7342 | |
2fa86a1f PZ |
7343 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7344 | SBI_GEN0 : SBI_DBUFF0; | |
7345 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7346 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7347 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7348 | |
7349 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7350 | } |
7351 | ||
47701c3b PZ |
7352 | /* Sequence to disable CLKOUT_DP */ |
7353 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7354 | { | |
7355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7356 | uint32_t reg, tmp; | |
7357 | ||
7358 | mutex_lock(&dev_priv->dpio_lock); | |
7359 | ||
7360 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7361 | SBI_GEN0 : SBI_DBUFF0; | |
7362 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7363 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7364 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7365 | ||
7366 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7367 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7368 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7369 | tmp |= SBI_SSCCTL_PATHALT; | |
7370 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7371 | udelay(32); | |
7372 | } | |
7373 | tmp |= SBI_SSCCTL_DISABLE; | |
7374 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7375 | } | |
7376 | ||
7377 | mutex_unlock(&dev_priv->dpio_lock); | |
7378 | } | |
7379 | ||
bf8fa3d3 PZ |
7380 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7381 | { | |
bf8fa3d3 PZ |
7382 | struct intel_encoder *encoder; |
7383 | bool has_vga = false; | |
7384 | ||
b2784e15 | 7385 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7386 | switch (encoder->type) { |
7387 | case INTEL_OUTPUT_ANALOG: | |
7388 | has_vga = true; | |
7389 | break; | |
6847d71b PZ |
7390 | default: |
7391 | break; | |
bf8fa3d3 PZ |
7392 | } |
7393 | } | |
7394 | ||
47701c3b PZ |
7395 | if (has_vga) |
7396 | lpt_enable_clkout_dp(dev, true, true); | |
7397 | else | |
7398 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7399 | } |
7400 | ||
dde86e2d PZ |
7401 | /* |
7402 | * Initialize reference clocks when the driver loads | |
7403 | */ | |
7404 | void intel_init_pch_refclk(struct drm_device *dev) | |
7405 | { | |
7406 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7407 | ironlake_init_pch_refclk(dev); | |
7408 | else if (HAS_PCH_LPT(dev)) | |
7409 | lpt_init_pch_refclk(dev); | |
7410 | } | |
7411 | ||
d9d444cb JB |
7412 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
7413 | { | |
7414 | struct drm_device *dev = crtc->dev; | |
7415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7416 | struct intel_encoder *encoder; | |
d9d444cb JB |
7417 | int num_connectors = 0; |
7418 | bool is_lvds = false; | |
7419 | ||
d0737e1d ACO |
7420 | for_each_intel_encoder(dev, encoder) { |
7421 | if (encoder->new_crtc != to_intel_crtc(crtc)) | |
7422 | continue; | |
7423 | ||
d9d444cb JB |
7424 | switch (encoder->type) { |
7425 | case INTEL_OUTPUT_LVDS: | |
7426 | is_lvds = true; | |
7427 | break; | |
6847d71b PZ |
7428 | default: |
7429 | break; | |
d9d444cb JB |
7430 | } |
7431 | num_connectors++; | |
7432 | } | |
7433 | ||
7434 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7435 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7436 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7437 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7438 | } |
7439 | ||
7440 | return 120000; | |
7441 | } | |
7442 | ||
6ff93609 | 7443 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7444 | { |
c8203565 | 7445 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7447 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7448 | uint32_t val; |
7449 | ||
78114071 | 7450 | val = 0; |
c8203565 | 7451 | |
6e3c9717 | 7452 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7453 | case 18: |
dfd07d72 | 7454 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7455 | break; |
7456 | case 24: | |
dfd07d72 | 7457 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7458 | break; |
7459 | case 30: | |
dfd07d72 | 7460 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7461 | break; |
7462 | case 36: | |
dfd07d72 | 7463 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7464 | break; |
7465 | default: | |
cc769b62 PZ |
7466 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7467 | BUG(); | |
c8203565 PZ |
7468 | } |
7469 | ||
6e3c9717 | 7470 | if (intel_crtc->config->dither) |
c8203565 PZ |
7471 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7472 | ||
6e3c9717 | 7473 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7474 | val |= PIPECONF_INTERLACED_ILK; |
7475 | else | |
7476 | val |= PIPECONF_PROGRESSIVE; | |
7477 | ||
6e3c9717 | 7478 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7479 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7480 | |
c8203565 PZ |
7481 | I915_WRITE(PIPECONF(pipe), val); |
7482 | POSTING_READ(PIPECONF(pipe)); | |
7483 | } | |
7484 | ||
86d3efce VS |
7485 | /* |
7486 | * Set up the pipe CSC unit. | |
7487 | * | |
7488 | * Currently only full range RGB to limited range RGB conversion | |
7489 | * is supported, but eventually this should handle various | |
7490 | * RGB<->YCbCr scenarios as well. | |
7491 | */ | |
50f3b016 | 7492 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7493 | { |
7494 | struct drm_device *dev = crtc->dev; | |
7495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7497 | int pipe = intel_crtc->pipe; | |
7498 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7499 | ||
7500 | /* | |
7501 | * TODO: Check what kind of values actually come out of the pipe | |
7502 | * with these coeff/postoff values and adjust to get the best | |
7503 | * accuracy. Perhaps we even need to take the bpc value into | |
7504 | * consideration. | |
7505 | */ | |
7506 | ||
6e3c9717 | 7507 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7508 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7509 | ||
7510 | /* | |
7511 | * GY/GU and RY/RU should be the other way around according | |
7512 | * to BSpec, but reality doesn't agree. Just set them up in | |
7513 | * a way that results in the correct picture. | |
7514 | */ | |
7515 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7516 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7517 | ||
7518 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7519 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7520 | ||
7521 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7522 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7523 | ||
7524 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7525 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7526 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7527 | ||
7528 | if (INTEL_INFO(dev)->gen > 6) { | |
7529 | uint16_t postoff = 0; | |
7530 | ||
6e3c9717 | 7531 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 7532 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7533 | |
7534 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7535 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7536 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7537 | ||
7538 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7539 | } else { | |
7540 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7541 | ||
6e3c9717 | 7542 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7543 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7544 | ||
7545 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7546 | } | |
7547 | } | |
7548 | ||
6ff93609 | 7549 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7550 | { |
756f85cf PZ |
7551 | struct drm_device *dev = crtc->dev; |
7552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7553 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7554 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7555 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
7556 | uint32_t val; |
7557 | ||
3eff4faa | 7558 | val = 0; |
ee2b0b38 | 7559 | |
6e3c9717 | 7560 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7561 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7562 | ||
6e3c9717 | 7563 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7564 | val |= PIPECONF_INTERLACED_ILK; |
7565 | else | |
7566 | val |= PIPECONF_PROGRESSIVE; | |
7567 | ||
702e7a56 PZ |
7568 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7569 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7570 | |
7571 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7572 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7573 | |
3cdf122c | 7574 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7575 | val = 0; |
7576 | ||
6e3c9717 | 7577 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
7578 | case 18: |
7579 | val |= PIPEMISC_DITHER_6_BPC; | |
7580 | break; | |
7581 | case 24: | |
7582 | val |= PIPEMISC_DITHER_8_BPC; | |
7583 | break; | |
7584 | case 30: | |
7585 | val |= PIPEMISC_DITHER_10_BPC; | |
7586 | break; | |
7587 | case 36: | |
7588 | val |= PIPEMISC_DITHER_12_BPC; | |
7589 | break; | |
7590 | default: | |
7591 | /* Case prevented by pipe_config_set_bpp. */ | |
7592 | BUG(); | |
7593 | } | |
7594 | ||
6e3c9717 | 7595 | if (intel_crtc->config->dither) |
756f85cf PZ |
7596 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
7597 | ||
7598 | I915_WRITE(PIPEMISC(pipe), val); | |
7599 | } | |
ee2b0b38 PZ |
7600 | } |
7601 | ||
6591c6e4 | 7602 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 7603 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
7604 | intel_clock_t *clock, |
7605 | bool *has_reduced_clock, | |
7606 | intel_clock_t *reduced_clock) | |
7607 | { | |
7608 | struct drm_device *dev = crtc->dev; | |
7609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a919ff14 | 7610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591c6e4 | 7611 | int refclk; |
d4906093 | 7612 | const intel_limit_t *limit; |
a16af721 | 7613 | bool ret, is_lvds = false; |
79e53945 | 7614 | |
d0737e1d | 7615 | is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7616 | |
d9d444cb | 7617 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7618 | |
d4906093 ML |
7619 | /* |
7620 | * Returns a set of divisors for the desired target clock with the given | |
7621 | * refclk, or FALSE. The returned values represent the clock equation: | |
7622 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7623 | */ | |
409ee761 | 7624 | limit = intel_limit(intel_crtc, refclk); |
a919ff14 | 7625 | ret = dev_priv->display.find_dpll(limit, intel_crtc, |
190f68c5 | 7626 | crtc_state->port_clock, |
ee9300bb | 7627 | refclk, NULL, clock); |
6591c6e4 PZ |
7628 | if (!ret) |
7629 | return false; | |
cda4b7d3 | 7630 | |
ddc9003c | 7631 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7632 | /* |
7633 | * Ensure we match the reduced clock's P to the target clock. | |
7634 | * If the clocks don't match, we can't switch the display clock | |
7635 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7636 | * downclock feature. | |
7637 | */ | |
ee9300bb | 7638 | *has_reduced_clock = |
a919ff14 | 7639 | dev_priv->display.find_dpll(limit, intel_crtc, |
ee9300bb DV |
7640 | dev_priv->lvds_downclock, |
7641 | refclk, clock, | |
7642 | reduced_clock); | |
652c393a | 7643 | } |
61e9653f | 7644 | |
6591c6e4 PZ |
7645 | return true; |
7646 | } | |
7647 | ||
d4b1931c PZ |
7648 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7649 | { | |
7650 | /* | |
7651 | * Account for spread spectrum to avoid | |
7652 | * oversubscribing the link. Max center spread | |
7653 | * is 2.5%; use 5% for safety's sake. | |
7654 | */ | |
7655 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7656 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7657 | } |
7658 | ||
7429e9d4 | 7659 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7660 | { |
7429e9d4 | 7661 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7662 | } |
7663 | ||
de13a2e3 | 7664 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 7665 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 7666 | u32 *fp, |
9a7c7890 | 7667 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7668 | { |
de13a2e3 | 7669 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7670 | struct drm_device *dev = crtc->dev; |
7671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7672 | struct intel_encoder *intel_encoder; |
7673 | uint32_t dpll; | |
6cc5f341 | 7674 | int factor, num_connectors = 0; |
09ede541 | 7675 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7676 | |
d0737e1d ACO |
7677 | for_each_intel_encoder(dev, intel_encoder) { |
7678 | if (intel_encoder->new_crtc != to_intel_crtc(crtc)) | |
7679 | continue; | |
7680 | ||
de13a2e3 | 7681 | switch (intel_encoder->type) { |
79e53945 JB |
7682 | case INTEL_OUTPUT_LVDS: |
7683 | is_lvds = true; | |
7684 | break; | |
7685 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7686 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7687 | is_sdvo = true; |
79e53945 | 7688 | break; |
6847d71b PZ |
7689 | default: |
7690 | break; | |
79e53945 | 7691 | } |
43565a06 | 7692 | |
c751ce4f | 7693 | num_connectors++; |
79e53945 | 7694 | } |
79e53945 | 7695 | |
c1858123 | 7696 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7697 | factor = 21; |
7698 | if (is_lvds) { | |
7699 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7700 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7701 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7702 | factor = 25; |
190f68c5 | 7703 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 7704 | factor = 20; |
c1858123 | 7705 | |
190f68c5 | 7706 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 7707 | *fp |= FP_CB_TUNE; |
2c07245f | 7708 | |
9a7c7890 DV |
7709 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7710 | *fp2 |= FP_CB_TUNE; | |
7711 | ||
5eddb70b | 7712 | dpll = 0; |
2c07245f | 7713 | |
a07d6787 EA |
7714 | if (is_lvds) |
7715 | dpll |= DPLLB_MODE_LVDS; | |
7716 | else | |
7717 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7718 | |
190f68c5 | 7719 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7720 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7721 | |
7722 | if (is_sdvo) | |
4a33e48d | 7723 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 7724 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7725 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7726 | |
a07d6787 | 7727 | /* compute bitmask from p1 value */ |
190f68c5 | 7728 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7729 | /* also FPA1 */ |
190f68c5 | 7730 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7731 | |
190f68c5 | 7732 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
7733 | case 5: |
7734 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7735 | break; | |
7736 | case 7: | |
7737 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7738 | break; | |
7739 | case 10: | |
7740 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7741 | break; | |
7742 | case 14: | |
7743 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7744 | break; | |
79e53945 JB |
7745 | } |
7746 | ||
b4c09f3b | 7747 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7748 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7749 | else |
7750 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7751 | ||
959e16d6 | 7752 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7753 | } |
7754 | ||
190f68c5 ACO |
7755 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
7756 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 7757 | { |
c7653199 | 7758 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7759 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 7760 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7761 | bool ok, has_reduced_clock = false; |
8b47047b | 7762 | bool is_lvds = false; |
e2b78267 | 7763 | struct intel_shared_dpll *pll; |
de13a2e3 | 7764 | |
409ee761 | 7765 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7766 | |
5dc5298b PZ |
7767 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7768 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7769 | |
190f68c5 | 7770 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 7771 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 7772 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
7773 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7774 | return -EINVAL; | |
79e53945 | 7775 | } |
f47709a9 | 7776 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7777 | if (!crtc_state->clock_set) { |
7778 | crtc_state->dpll.n = clock.n; | |
7779 | crtc_state->dpll.m1 = clock.m1; | |
7780 | crtc_state->dpll.m2 = clock.m2; | |
7781 | crtc_state->dpll.p1 = clock.p1; | |
7782 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7783 | } |
79e53945 | 7784 | |
5dc5298b | 7785 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
7786 | if (crtc_state->has_pch_encoder) { |
7787 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 7788 | if (has_reduced_clock) |
7429e9d4 | 7789 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7790 | |
190f68c5 | 7791 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
7792 | &fp, &reduced_clock, |
7793 | has_reduced_clock ? &fp2 : NULL); | |
7794 | ||
190f68c5 ACO |
7795 | crtc_state->dpll_hw_state.dpll = dpll; |
7796 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 7797 | if (has_reduced_clock) |
190f68c5 | 7798 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 7799 | else |
190f68c5 | 7800 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 7801 | |
190f68c5 | 7802 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 7803 | if (pll == NULL) { |
84f44ce7 | 7804 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 7805 | pipe_name(crtc->pipe)); |
4b645f14 JB |
7806 | return -EINVAL; |
7807 | } | |
3fb37703 | 7808 | } |
79e53945 | 7809 | |
ab585dea | 7810 | if (is_lvds && has_reduced_clock) |
c7653199 | 7811 | crtc->lowfreq_avail = true; |
bcd644e0 | 7812 | else |
c7653199 | 7813 | crtc->lowfreq_avail = false; |
e2b78267 | 7814 | |
c8f7a0db | 7815 | return 0; |
79e53945 JB |
7816 | } |
7817 | ||
eb14cb74 VS |
7818 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7819 | struct intel_link_m_n *m_n) | |
7820 | { | |
7821 | struct drm_device *dev = crtc->base.dev; | |
7822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7823 | enum pipe pipe = crtc->pipe; | |
7824 | ||
7825 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7826 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7827 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7828 | & ~TU_SIZE_MASK; | |
7829 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7830 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7831 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7832 | } | |
7833 | ||
7834 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7835 | enum transcoder transcoder, | |
b95af8be VK |
7836 | struct intel_link_m_n *m_n, |
7837 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7838 | { |
7839 | struct drm_device *dev = crtc->base.dev; | |
7840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7841 | enum pipe pipe = crtc->pipe; |
72419203 | 7842 | |
eb14cb74 VS |
7843 | if (INTEL_INFO(dev)->gen >= 5) { |
7844 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7845 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7846 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7847 | & ~TU_SIZE_MASK; | |
7848 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7849 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7850 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7851 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7852 | * gen < 8) and if DRRS is supported (to make sure the | |
7853 | * registers are not unnecessarily read). | |
7854 | */ | |
7855 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 7856 | crtc->config->has_drrs) { |
b95af8be VK |
7857 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
7858 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7859 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7860 | & ~TU_SIZE_MASK; | |
7861 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7862 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7863 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7864 | } | |
eb14cb74 VS |
7865 | } else { |
7866 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7867 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7868 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7869 | & ~TU_SIZE_MASK; | |
7870 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7871 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7872 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7873 | } | |
7874 | } | |
7875 | ||
7876 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 7877 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 7878 | { |
681a8504 | 7879 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
7880 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
7881 | else | |
7882 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7883 | &pipe_config->dp_m_n, |
7884 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7885 | } |
72419203 | 7886 | |
eb14cb74 | 7887 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 7888 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
7889 | { |
7890 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7891 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7892 | } |
7893 | ||
bd2e244f | 7894 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7895 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
7896 | { |
7897 | struct drm_device *dev = crtc->base.dev; | |
7898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7899 | uint32_t tmp; | |
7900 | ||
7901 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
7902 | ||
7903 | if (tmp & PS_ENABLE) { | |
7904 | pipe_config->pch_pfit.enabled = true; | |
7905 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
7906 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
7907 | } | |
7908 | } | |
7909 | ||
5724dbd1 DL |
7910 | static void |
7911 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
7912 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
7913 | { |
7914 | struct drm_device *dev = crtc->base.dev; | |
7915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 7916 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
7917 | int pipe = crtc->pipe; |
7918 | int fourcc, pixel_format; | |
6761dd31 | 7919 | unsigned int aligned_height; |
bc8d7dff | 7920 | struct drm_framebuffer *fb; |
1b842c89 | 7921 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 7922 | |
d9806c9f | 7923 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7924 | if (!intel_fb) { |
bc8d7dff DL |
7925 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7926 | return; | |
7927 | } | |
7928 | ||
1b842c89 DL |
7929 | fb = &intel_fb->base; |
7930 | ||
bc8d7dff | 7931 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
7932 | if (!(val & PLANE_CTL_ENABLE)) |
7933 | goto error; | |
7934 | ||
bc8d7dff DL |
7935 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
7936 | fourcc = skl_format_to_fourcc(pixel_format, | |
7937 | val & PLANE_CTL_ORDER_RGBX, | |
7938 | val & PLANE_CTL_ALPHA_MASK); | |
7939 | fb->pixel_format = fourcc; | |
7940 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
7941 | ||
40f46283 DL |
7942 | tiling = val & PLANE_CTL_TILED_MASK; |
7943 | switch (tiling) { | |
7944 | case PLANE_CTL_TILED_LINEAR: | |
7945 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
7946 | break; | |
7947 | case PLANE_CTL_TILED_X: | |
7948 | plane_config->tiling = I915_TILING_X; | |
7949 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
7950 | break; | |
7951 | case PLANE_CTL_TILED_Y: | |
7952 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
7953 | break; | |
7954 | case PLANE_CTL_TILED_YF: | |
7955 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
7956 | break; | |
7957 | default: | |
7958 | MISSING_CASE(tiling); | |
7959 | goto error; | |
7960 | } | |
7961 | ||
bc8d7dff DL |
7962 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
7963 | plane_config->base = base; | |
7964 | ||
7965 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
7966 | ||
7967 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
7968 | fb->height = ((val >> 16) & 0xfff) + 1; | |
7969 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
7970 | ||
7971 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
7972 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
7973 | fb->pixel_format); | |
bc8d7dff DL |
7974 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
7975 | ||
7976 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
7977 | fb->pixel_format, |
7978 | fb->modifier[0]); | |
bc8d7dff | 7979 | |
f37b5c2b | 7980 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
7981 | |
7982 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
7983 | pipe_name(pipe), fb->width, fb->height, | |
7984 | fb->bits_per_pixel, base, fb->pitches[0], | |
7985 | plane_config->size); | |
7986 | ||
2d14030b | 7987 | plane_config->fb = intel_fb; |
bc8d7dff DL |
7988 | return; |
7989 | ||
7990 | error: | |
7991 | kfree(fb); | |
7992 | } | |
7993 | ||
2fa2fe9a | 7994 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7995 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7996 | { |
7997 | struct drm_device *dev = crtc->base.dev; | |
7998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7999 | uint32_t tmp; | |
8000 | ||
8001 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8002 | ||
8003 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8004 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8005 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8006 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8007 | |
8008 | /* We currently do not free assignements of panel fitters on | |
8009 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8010 | * differentiates them) so just WARN about this case for now. */ | |
8011 | if (IS_GEN7(dev)) { | |
8012 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8013 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8014 | } | |
2fa2fe9a | 8015 | } |
79e53945 JB |
8016 | } |
8017 | ||
5724dbd1 DL |
8018 | static void |
8019 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8020 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8021 | { |
8022 | struct drm_device *dev = crtc->base.dev; | |
8023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8024 | u32 val, base, offset; | |
aeee5a49 | 8025 | int pipe = crtc->pipe; |
4c6baa59 | 8026 | int fourcc, pixel_format; |
6761dd31 | 8027 | unsigned int aligned_height; |
b113d5ee | 8028 | struct drm_framebuffer *fb; |
1b842c89 | 8029 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8030 | |
42a7b088 DL |
8031 | val = I915_READ(DSPCNTR(pipe)); |
8032 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8033 | return; | |
8034 | ||
d9806c9f | 8035 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8036 | if (!intel_fb) { |
4c6baa59 JB |
8037 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8038 | return; | |
8039 | } | |
8040 | ||
1b842c89 DL |
8041 | fb = &intel_fb->base; |
8042 | ||
18c5247e DV |
8043 | if (INTEL_INFO(dev)->gen >= 4) { |
8044 | if (val & DISPPLANE_TILED) { | |
49af449b | 8045 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8046 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8047 | } | |
8048 | } | |
4c6baa59 JB |
8049 | |
8050 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8051 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8052 | fb->pixel_format = fourcc; |
8053 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8054 | |
aeee5a49 | 8055 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8056 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8057 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8058 | } else { |
49af449b | 8059 | if (plane_config->tiling) |
aeee5a49 | 8060 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8061 | else |
aeee5a49 | 8062 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8063 | } |
8064 | plane_config->base = base; | |
8065 | ||
8066 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8067 | fb->width = ((val >> 16) & 0xfff) + 1; |
8068 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8069 | |
8070 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8071 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8072 | |
b113d5ee | 8073 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8074 | fb->pixel_format, |
8075 | fb->modifier[0]); | |
4c6baa59 | 8076 | |
f37b5c2b | 8077 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8078 | |
2844a921 DL |
8079 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8080 | pipe_name(pipe), fb->width, fb->height, | |
8081 | fb->bits_per_pixel, base, fb->pitches[0], | |
8082 | plane_config->size); | |
b113d5ee | 8083 | |
2d14030b | 8084 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8085 | } |
8086 | ||
0e8ffe1b | 8087 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8088 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8089 | { |
8090 | struct drm_device *dev = crtc->base.dev; | |
8091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8092 | uint32_t tmp; | |
8093 | ||
f458ebbc DV |
8094 | if (!intel_display_power_is_enabled(dev_priv, |
8095 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8096 | return false; |
8097 | ||
e143a21c | 8098 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8099 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8100 | |
0e8ffe1b DV |
8101 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8102 | if (!(tmp & PIPECONF_ENABLE)) | |
8103 | return false; | |
8104 | ||
42571aef VS |
8105 | switch (tmp & PIPECONF_BPC_MASK) { |
8106 | case PIPECONF_6BPC: | |
8107 | pipe_config->pipe_bpp = 18; | |
8108 | break; | |
8109 | case PIPECONF_8BPC: | |
8110 | pipe_config->pipe_bpp = 24; | |
8111 | break; | |
8112 | case PIPECONF_10BPC: | |
8113 | pipe_config->pipe_bpp = 30; | |
8114 | break; | |
8115 | case PIPECONF_12BPC: | |
8116 | pipe_config->pipe_bpp = 36; | |
8117 | break; | |
8118 | default: | |
8119 | break; | |
8120 | } | |
8121 | ||
b5a9fa09 DV |
8122 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8123 | pipe_config->limited_color_range = true; | |
8124 | ||
ab9412ba | 8125 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8126 | struct intel_shared_dpll *pll; |
8127 | ||
88adfff1 DV |
8128 | pipe_config->has_pch_encoder = true; |
8129 | ||
627eb5a3 DV |
8130 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8131 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8132 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8133 | |
8134 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8135 | |
c0d43d62 | 8136 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8137 | pipe_config->shared_dpll = |
8138 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8139 | } else { |
8140 | tmp = I915_READ(PCH_DPLL_SEL); | |
8141 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8142 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8143 | else | |
8144 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8145 | } | |
66e985c0 DV |
8146 | |
8147 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8148 | ||
8149 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8150 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8151 | |
8152 | tmp = pipe_config->dpll_hw_state.dpll; | |
8153 | pipe_config->pixel_multiplier = | |
8154 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8155 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8156 | |
8157 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8158 | } else { |
8159 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8160 | } |
8161 | ||
1bd1bd80 DV |
8162 | intel_get_pipe_timings(crtc, pipe_config); |
8163 | ||
2fa2fe9a DV |
8164 | ironlake_get_pfit_config(crtc, pipe_config); |
8165 | ||
0e8ffe1b DV |
8166 | return true; |
8167 | } | |
8168 | ||
be256dc7 PZ |
8169 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8170 | { | |
8171 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8172 | struct intel_crtc *crtc; |
be256dc7 | 8173 | |
d3fcc808 | 8174 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8175 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8176 | pipe_name(crtc->pipe)); |
8177 | ||
e2c719b7 RC |
8178 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8179 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8180 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8181 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8182 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8183 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8184 | "CPU PWM1 enabled\n"); |
c5107b87 | 8185 | if (IS_HASWELL(dev)) |
e2c719b7 | 8186 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8187 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8188 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8189 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8190 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8191 | "Utility pin enabled\n"); |
e2c719b7 | 8192 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8193 | |
9926ada1 PZ |
8194 | /* |
8195 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8196 | * interrupts remain enabled. We used to check for that, but since it's | |
8197 | * gen-specific and since we only disable LCPLL after we fully disable | |
8198 | * the interrupts, the check below should be enough. | |
8199 | */ | |
e2c719b7 | 8200 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8201 | } |
8202 | ||
9ccd5aeb PZ |
8203 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8204 | { | |
8205 | struct drm_device *dev = dev_priv->dev; | |
8206 | ||
8207 | if (IS_HASWELL(dev)) | |
8208 | return I915_READ(D_COMP_HSW); | |
8209 | else | |
8210 | return I915_READ(D_COMP_BDW); | |
8211 | } | |
8212 | ||
3c4c9b81 PZ |
8213 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8214 | { | |
8215 | struct drm_device *dev = dev_priv->dev; | |
8216 | ||
8217 | if (IS_HASWELL(dev)) { | |
8218 | mutex_lock(&dev_priv->rps.hw_lock); | |
8219 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8220 | val)) | |
f475dadf | 8221 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8222 | mutex_unlock(&dev_priv->rps.hw_lock); |
8223 | } else { | |
9ccd5aeb PZ |
8224 | I915_WRITE(D_COMP_BDW, val); |
8225 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8226 | } |
be256dc7 PZ |
8227 | } |
8228 | ||
8229 | /* | |
8230 | * This function implements pieces of two sequences from BSpec: | |
8231 | * - Sequence for display software to disable LCPLL | |
8232 | * - Sequence for display software to allow package C8+ | |
8233 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8234 | * register. Callers should take care of disabling all the display engine | |
8235 | * functions, doing the mode unset, fixing interrupts, etc. | |
8236 | */ | |
6ff58d53 PZ |
8237 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8238 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8239 | { |
8240 | uint32_t val; | |
8241 | ||
8242 | assert_can_disable_lcpll(dev_priv); | |
8243 | ||
8244 | val = I915_READ(LCPLL_CTL); | |
8245 | ||
8246 | if (switch_to_fclk) { | |
8247 | val |= LCPLL_CD_SOURCE_FCLK; | |
8248 | I915_WRITE(LCPLL_CTL, val); | |
8249 | ||
8250 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8251 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8252 | DRM_ERROR("Switching to FCLK failed\n"); | |
8253 | ||
8254 | val = I915_READ(LCPLL_CTL); | |
8255 | } | |
8256 | ||
8257 | val |= LCPLL_PLL_DISABLE; | |
8258 | I915_WRITE(LCPLL_CTL, val); | |
8259 | POSTING_READ(LCPLL_CTL); | |
8260 | ||
8261 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8262 | DRM_ERROR("LCPLL still locked\n"); | |
8263 | ||
9ccd5aeb | 8264 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8265 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8266 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8267 | ndelay(100); |
8268 | ||
9ccd5aeb PZ |
8269 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8270 | 1)) | |
be256dc7 PZ |
8271 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8272 | ||
8273 | if (allow_power_down) { | |
8274 | val = I915_READ(LCPLL_CTL); | |
8275 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8276 | I915_WRITE(LCPLL_CTL, val); | |
8277 | POSTING_READ(LCPLL_CTL); | |
8278 | } | |
8279 | } | |
8280 | ||
8281 | /* | |
8282 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8283 | * source. | |
8284 | */ | |
6ff58d53 | 8285 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8286 | { |
8287 | uint32_t val; | |
8288 | ||
8289 | val = I915_READ(LCPLL_CTL); | |
8290 | ||
8291 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8292 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8293 | return; | |
8294 | ||
a8a8bd54 PZ |
8295 | /* |
8296 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8297 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8298 | */ |
59bad947 | 8299 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8300 | |
be256dc7 PZ |
8301 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8302 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8303 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8304 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8305 | } |
8306 | ||
9ccd5aeb | 8307 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8308 | val |= D_COMP_COMP_FORCE; |
8309 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8310 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8311 | |
8312 | val = I915_READ(LCPLL_CTL); | |
8313 | val &= ~LCPLL_PLL_DISABLE; | |
8314 | I915_WRITE(LCPLL_CTL, val); | |
8315 | ||
8316 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8317 | DRM_ERROR("LCPLL not locked yet\n"); | |
8318 | ||
8319 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8320 | val = I915_READ(LCPLL_CTL); | |
8321 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8322 | I915_WRITE(LCPLL_CTL, val); | |
8323 | ||
8324 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
8325 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
8326 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
8327 | } | |
215733fa | 8328 | |
59bad947 | 8329 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
8330 | } |
8331 | ||
765dab67 PZ |
8332 | /* |
8333 | * Package states C8 and deeper are really deep PC states that can only be | |
8334 | * reached when all the devices on the system allow it, so even if the graphics | |
8335 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8336 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8337 | * | |
8338 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8339 | * well is disabled and most interrupts are disabled, and these are also | |
8340 | * requirements for runtime PM. When these conditions are met, we manually do | |
8341 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8342 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8343 | * hang the machine. | |
8344 | * | |
8345 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8346 | * the state of some registers, so when we come back from PC8+ we need to | |
8347 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8348 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8349 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8350 | * because of the runtime PM support). | |
8351 | * | |
8352 | * For more, read "Display Sequences for Package C8" on the hardware | |
8353 | * documentation. | |
8354 | */ | |
a14cb6fc | 8355 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8356 | { |
c67a470b PZ |
8357 | struct drm_device *dev = dev_priv->dev; |
8358 | uint32_t val; | |
8359 | ||
c67a470b PZ |
8360 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8361 | ||
c67a470b PZ |
8362 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
8363 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8364 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8365 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8366 | } | |
8367 | ||
8368 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
8369 | hsw_disable_lcpll(dev_priv, true, true); |
8370 | } | |
8371 | ||
a14cb6fc | 8372 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
8373 | { |
8374 | struct drm_device *dev = dev_priv->dev; | |
8375 | uint32_t val; | |
8376 | ||
c67a470b PZ |
8377 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8378 | ||
8379 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
8380 | lpt_init_pch_refclk(dev); |
8381 | ||
8382 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
8383 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8384 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8385 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8386 | } | |
8387 | ||
8388 | intel_prepare_ddi(dev); | |
c67a470b PZ |
8389 | } |
8390 | ||
190f68c5 ACO |
8391 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8392 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8393 | { |
190f68c5 | 8394 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 8395 | return -EINVAL; |
716c2e55 | 8396 | |
c7653199 | 8397 | crtc->lowfreq_avail = false; |
644cef34 | 8398 | |
c8f7a0db | 8399 | return 0; |
79e53945 JB |
8400 | } |
8401 | ||
96b7dfb7 S |
8402 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8403 | enum port port, | |
5cec258b | 8404 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8405 | { |
3148ade7 | 8406 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
8407 | |
8408 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
8409 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
8410 | ||
8411 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
8412 | case SKL_DPLL0: |
8413 | /* | |
8414 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
8415 | * of the shared DPLL framework and thus needs to be read out | |
8416 | * separately | |
8417 | */ | |
8418 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8419 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8420 | break; | |
96b7dfb7 S |
8421 | case SKL_DPLL1: |
8422 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8423 | break; | |
8424 | case SKL_DPLL2: | |
8425 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8426 | break; | |
8427 | case SKL_DPLL3: | |
8428 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8429 | break; | |
96b7dfb7 S |
8430 | } |
8431 | } | |
8432 | ||
7d2c8175 DL |
8433 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8434 | enum port port, | |
5cec258b | 8435 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
8436 | { |
8437 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8438 | ||
8439 | switch (pipe_config->ddi_pll_sel) { | |
8440 | case PORT_CLK_SEL_WRPLL1: | |
8441 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8442 | break; | |
8443 | case PORT_CLK_SEL_WRPLL2: | |
8444 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8445 | break; | |
8446 | } | |
8447 | } | |
8448 | ||
26804afd | 8449 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 8450 | struct intel_crtc_state *pipe_config) |
26804afd DV |
8451 | { |
8452 | struct drm_device *dev = crtc->base.dev; | |
8453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8454 | struct intel_shared_dpll *pll; |
26804afd DV |
8455 | enum port port; |
8456 | uint32_t tmp; | |
8457 | ||
8458 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8459 | ||
8460 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8461 | ||
96b7dfb7 S |
8462 | if (IS_SKYLAKE(dev)) |
8463 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8464 | else | |
8465 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8466 | |
d452c5b6 DV |
8467 | if (pipe_config->shared_dpll >= 0) { |
8468 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8469 | ||
8470 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8471 | &pipe_config->dpll_hw_state)); | |
8472 | } | |
8473 | ||
26804afd DV |
8474 | /* |
8475 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8476 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8477 | * the PCH transcoder is on. | |
8478 | */ | |
ca370455 DL |
8479 | if (INTEL_INFO(dev)->gen < 9 && |
8480 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8481 | pipe_config->has_pch_encoder = true; |
8482 | ||
8483 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8484 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8485 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8486 | ||
8487 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8488 | } | |
8489 | } | |
8490 | ||
0e8ffe1b | 8491 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8492 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8493 | { |
8494 | struct drm_device *dev = crtc->base.dev; | |
8495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8496 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8497 | uint32_t tmp; |
8498 | ||
f458ebbc | 8499 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8500 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8501 | return false; | |
8502 | ||
e143a21c | 8503 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8504 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8505 | ||
eccb140b DV |
8506 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8507 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8508 | enum pipe trans_edp_pipe; | |
8509 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8510 | default: | |
8511 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8512 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8513 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8514 | trans_edp_pipe = PIPE_A; | |
8515 | break; | |
8516 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8517 | trans_edp_pipe = PIPE_B; | |
8518 | break; | |
8519 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8520 | trans_edp_pipe = PIPE_C; | |
8521 | break; | |
8522 | } | |
8523 | ||
8524 | if (trans_edp_pipe == crtc->pipe) | |
8525 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8526 | } | |
8527 | ||
f458ebbc | 8528 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8529 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8530 | return false; |
8531 | ||
eccb140b | 8532 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8533 | if (!(tmp & PIPECONF_ENABLE)) |
8534 | return false; | |
8535 | ||
26804afd | 8536 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8537 | |
1bd1bd80 DV |
8538 | intel_get_pipe_timings(crtc, pipe_config); |
8539 | ||
2fa2fe9a | 8540 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8541 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8542 | if (IS_SKYLAKE(dev)) | |
8543 | skylake_get_pfit_config(crtc, pipe_config); | |
8544 | else | |
8545 | ironlake_get_pfit_config(crtc, pipe_config); | |
8546 | } | |
88adfff1 | 8547 | |
e59150dc JB |
8548 | if (IS_HASWELL(dev)) |
8549 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8550 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8551 | |
ebb69c95 CT |
8552 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8553 | pipe_config->pixel_multiplier = | |
8554 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8555 | } else { | |
8556 | pipe_config->pixel_multiplier = 1; | |
8557 | } | |
6c49f241 | 8558 | |
0e8ffe1b DV |
8559 | return true; |
8560 | } | |
8561 | ||
560b85bb CW |
8562 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8563 | { | |
8564 | struct drm_device *dev = crtc->dev; | |
8565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8567 | uint32_t cntl = 0, size = 0; |
560b85bb | 8568 | |
dc41c154 | 8569 | if (base) { |
3dd512fb MR |
8570 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
8571 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
8572 | unsigned int stride = roundup_pow_of_two(width) * 4; |
8573 | ||
8574 | switch (stride) { | |
8575 | default: | |
8576 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8577 | width, stride); | |
8578 | stride = 256; | |
8579 | /* fallthrough */ | |
8580 | case 256: | |
8581 | case 512: | |
8582 | case 1024: | |
8583 | case 2048: | |
8584 | break; | |
4b0e333e CW |
8585 | } |
8586 | ||
dc41c154 VS |
8587 | cntl |= CURSOR_ENABLE | |
8588 | CURSOR_GAMMA_ENABLE | | |
8589 | CURSOR_FORMAT_ARGB | | |
8590 | CURSOR_STRIDE(stride); | |
8591 | ||
8592 | size = (height << 12) | width; | |
4b0e333e | 8593 | } |
560b85bb | 8594 | |
dc41c154 VS |
8595 | if (intel_crtc->cursor_cntl != 0 && |
8596 | (intel_crtc->cursor_base != base || | |
8597 | intel_crtc->cursor_size != size || | |
8598 | intel_crtc->cursor_cntl != cntl)) { | |
8599 | /* On these chipsets we can only modify the base/size/stride | |
8600 | * whilst the cursor is disabled. | |
8601 | */ | |
8602 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8603 | POSTING_READ(_CURACNTR); |
dc41c154 | 8604 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8605 | } |
560b85bb | 8606 | |
99d1f387 | 8607 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8608 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8609 | intel_crtc->cursor_base = base; |
8610 | } | |
4726e0b0 | 8611 | |
dc41c154 VS |
8612 | if (intel_crtc->cursor_size != size) { |
8613 | I915_WRITE(CURSIZE, size); | |
8614 | intel_crtc->cursor_size = size; | |
4b0e333e | 8615 | } |
560b85bb | 8616 | |
4b0e333e | 8617 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8618 | I915_WRITE(_CURACNTR, cntl); |
8619 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8620 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8621 | } |
560b85bb CW |
8622 | } |
8623 | ||
560b85bb | 8624 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8625 | { |
8626 | struct drm_device *dev = crtc->dev; | |
8627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8629 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8630 | uint32_t cntl; |
8631 | ||
8632 | cntl = 0; | |
8633 | if (base) { | |
8634 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 8635 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
8636 | case 64: |
8637 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8638 | break; | |
8639 | case 128: | |
8640 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8641 | break; | |
8642 | case 256: | |
8643 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8644 | break; | |
8645 | default: | |
3dd512fb | 8646 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 8647 | return; |
65a21cd6 | 8648 | } |
4b0e333e | 8649 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8650 | |
8651 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8652 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8653 | } |
65a21cd6 | 8654 | |
8e7d688b | 8655 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
8656 | cntl |= CURSOR_ROTATE_180; |
8657 | ||
4b0e333e CW |
8658 | if (intel_crtc->cursor_cntl != cntl) { |
8659 | I915_WRITE(CURCNTR(pipe), cntl); | |
8660 | POSTING_READ(CURCNTR(pipe)); | |
8661 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8662 | } |
4b0e333e | 8663 | |
65a21cd6 | 8664 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8665 | I915_WRITE(CURBASE(pipe), base); |
8666 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8667 | |
8668 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8669 | } |
8670 | ||
cda4b7d3 | 8671 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8672 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8673 | bool on) | |
cda4b7d3 CW |
8674 | { |
8675 | struct drm_device *dev = crtc->dev; | |
8676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8678 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8679 | int x = crtc->cursor_x; |
8680 | int y = crtc->cursor_y; | |
d6e4db15 | 8681 | u32 base = 0, pos = 0; |
cda4b7d3 | 8682 | |
d6e4db15 | 8683 | if (on) |
cda4b7d3 | 8684 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8685 | |
6e3c9717 | 8686 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
8687 | base = 0; |
8688 | ||
6e3c9717 | 8689 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
8690 | base = 0; |
8691 | ||
8692 | if (x < 0) { | |
3dd512fb | 8693 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
8694 | base = 0; |
8695 | ||
8696 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8697 | x = -x; | |
8698 | } | |
8699 | pos |= x << CURSOR_X_SHIFT; | |
8700 | ||
8701 | if (y < 0) { | |
3dd512fb | 8702 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
8703 | base = 0; |
8704 | ||
8705 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8706 | y = -y; | |
8707 | } | |
8708 | pos |= y << CURSOR_Y_SHIFT; | |
8709 | ||
4b0e333e | 8710 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8711 | return; |
8712 | ||
5efb3e28 VS |
8713 | I915_WRITE(CURPOS(pipe), pos); |
8714 | ||
4398ad45 VS |
8715 | /* ILK+ do this automagically */ |
8716 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 8717 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
8718 | base += (intel_crtc->base.cursor->state->crtc_h * |
8719 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
8720 | } |
8721 | ||
8ac54669 | 8722 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8723 | i845_update_cursor(crtc, base); |
8724 | else | |
8725 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8726 | } |
8727 | ||
dc41c154 VS |
8728 | static bool cursor_size_ok(struct drm_device *dev, |
8729 | uint32_t width, uint32_t height) | |
8730 | { | |
8731 | if (width == 0 || height == 0) | |
8732 | return false; | |
8733 | ||
8734 | /* | |
8735 | * 845g/865g are special in that they are only limited by | |
8736 | * the width of their cursors, the height is arbitrary up to | |
8737 | * the precision of the register. Everything else requires | |
8738 | * square cursors, limited to a few power-of-two sizes. | |
8739 | */ | |
8740 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8741 | if ((width & 63) != 0) | |
8742 | return false; | |
8743 | ||
8744 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8745 | return false; | |
8746 | ||
8747 | if (height > 1023) | |
8748 | return false; | |
8749 | } else { | |
8750 | switch (width | height) { | |
8751 | case 256: | |
8752 | case 128: | |
8753 | if (IS_GEN2(dev)) | |
8754 | return false; | |
8755 | case 64: | |
8756 | break; | |
8757 | default: | |
8758 | return false; | |
8759 | } | |
8760 | } | |
8761 | ||
8762 | return true; | |
8763 | } | |
8764 | ||
79e53945 | 8765 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8766 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8767 | { |
7203425a | 8768 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8769 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8770 | |
7203425a | 8771 | for (i = start; i < end; i++) { |
79e53945 JB |
8772 | intel_crtc->lut_r[i] = red[i] >> 8; |
8773 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8774 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8775 | } | |
8776 | ||
8777 | intel_crtc_load_lut(crtc); | |
8778 | } | |
8779 | ||
79e53945 JB |
8780 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8781 | static struct drm_display_mode load_detect_mode = { | |
8782 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8783 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8784 | }; | |
8785 | ||
a8bb6818 DV |
8786 | struct drm_framebuffer * |
8787 | __intel_framebuffer_create(struct drm_device *dev, | |
8788 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8789 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8790 | { |
8791 | struct intel_framebuffer *intel_fb; | |
8792 | int ret; | |
8793 | ||
8794 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8795 | if (!intel_fb) { | |
6ccb81f2 | 8796 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
8797 | return ERR_PTR(-ENOMEM); |
8798 | } | |
8799 | ||
8800 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8801 | if (ret) |
8802 | goto err; | |
d2dff872 CW |
8803 | |
8804 | return &intel_fb->base; | |
dd4916c5 | 8805 | err: |
6ccb81f2 | 8806 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
8807 | kfree(intel_fb); |
8808 | ||
8809 | return ERR_PTR(ret); | |
d2dff872 CW |
8810 | } |
8811 | ||
b5ea642a | 8812 | static struct drm_framebuffer * |
a8bb6818 DV |
8813 | intel_framebuffer_create(struct drm_device *dev, |
8814 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8815 | struct drm_i915_gem_object *obj) | |
8816 | { | |
8817 | struct drm_framebuffer *fb; | |
8818 | int ret; | |
8819 | ||
8820 | ret = i915_mutex_lock_interruptible(dev); | |
8821 | if (ret) | |
8822 | return ERR_PTR(ret); | |
8823 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8824 | mutex_unlock(&dev->struct_mutex); | |
8825 | ||
8826 | return fb; | |
8827 | } | |
8828 | ||
d2dff872 CW |
8829 | static u32 |
8830 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8831 | { | |
8832 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8833 | return ALIGN(pitch, 64); | |
8834 | } | |
8835 | ||
8836 | static u32 | |
8837 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8838 | { | |
8839 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8840 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8841 | } |
8842 | ||
8843 | static struct drm_framebuffer * | |
8844 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8845 | struct drm_display_mode *mode, | |
8846 | int depth, int bpp) | |
8847 | { | |
8848 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8849 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8850 | |
8851 | obj = i915_gem_alloc_object(dev, | |
8852 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8853 | if (obj == NULL) | |
8854 | return ERR_PTR(-ENOMEM); | |
8855 | ||
8856 | mode_cmd.width = mode->hdisplay; | |
8857 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8858 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8859 | bpp); | |
5ca0c34a | 8860 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8861 | |
8862 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8863 | } | |
8864 | ||
8865 | static struct drm_framebuffer * | |
8866 | mode_fits_in_fbdev(struct drm_device *dev, | |
8867 | struct drm_display_mode *mode) | |
8868 | { | |
4520f53a | 8869 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8870 | struct drm_i915_private *dev_priv = dev->dev_private; |
8871 | struct drm_i915_gem_object *obj; | |
8872 | struct drm_framebuffer *fb; | |
8873 | ||
4c0e5528 | 8874 | if (!dev_priv->fbdev) |
d2dff872 CW |
8875 | return NULL; |
8876 | ||
4c0e5528 | 8877 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8878 | return NULL; |
8879 | ||
4c0e5528 DV |
8880 | obj = dev_priv->fbdev->fb->obj; |
8881 | BUG_ON(!obj); | |
8882 | ||
8bcd4553 | 8883 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8884 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8885 | fb->bits_per_pixel)) | |
d2dff872 CW |
8886 | return NULL; |
8887 | ||
01f2c773 | 8888 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8889 | return NULL; |
8890 | ||
8891 | return fb; | |
4520f53a DV |
8892 | #else |
8893 | return NULL; | |
8894 | #endif | |
d2dff872 CW |
8895 | } |
8896 | ||
d2434ab7 | 8897 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8898 | struct drm_display_mode *mode, |
51fd371b RC |
8899 | struct intel_load_detect_pipe *old, |
8900 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8901 | { |
8902 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8903 | struct intel_encoder *intel_encoder = |
8904 | intel_attached_encoder(connector); | |
79e53945 | 8905 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8906 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8907 | struct drm_crtc *crtc = NULL; |
8908 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8909 | struct drm_framebuffer *fb; |
51fd371b | 8910 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 8911 | struct drm_atomic_state *state = NULL; |
944b0c76 | 8912 | struct drm_connector_state *connector_state; |
51fd371b | 8913 | int ret, i = -1; |
79e53945 | 8914 | |
d2dff872 | 8915 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8916 | connector->base.id, connector->name, |
8e329a03 | 8917 | encoder->base.id, encoder->name); |
d2dff872 | 8918 | |
51fd371b RC |
8919 | retry: |
8920 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8921 | if (ret) | |
8922 | goto fail_unlock; | |
6e9f798d | 8923 | |
79e53945 JB |
8924 | /* |
8925 | * Algorithm gets a little messy: | |
7a5e4805 | 8926 | * |
79e53945 JB |
8927 | * - if the connector already has an assigned crtc, use it (but make |
8928 | * sure it's on first) | |
7a5e4805 | 8929 | * |
79e53945 JB |
8930 | * - try to find the first unused crtc that can drive this connector, |
8931 | * and use that if we find one | |
79e53945 JB |
8932 | */ |
8933 | ||
8934 | /* See if we already have a CRTC for this connector */ | |
8935 | if (encoder->crtc) { | |
8936 | crtc = encoder->crtc; | |
8261b191 | 8937 | |
51fd371b | 8938 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
8939 | if (ret) |
8940 | goto fail_unlock; | |
8941 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
8942 | if (ret) |
8943 | goto fail_unlock; | |
7b24056b | 8944 | |
24218aac | 8945 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8946 | old->load_detect_temp = false; |
8947 | ||
8948 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8949 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8950 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8951 | |
7173188d | 8952 | return true; |
79e53945 JB |
8953 | } |
8954 | ||
8955 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8956 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8957 | i++; |
8958 | if (!(encoder->possible_crtcs & (1 << i))) | |
8959 | continue; | |
83d65738 | 8960 | if (possible_crtc->state->enable) |
a459249c VS |
8961 | continue; |
8962 | /* This can occur when applying the pipe A quirk on resume. */ | |
8963 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8964 | continue; | |
8965 | ||
8966 | crtc = possible_crtc; | |
8967 | break; | |
79e53945 JB |
8968 | } |
8969 | ||
8970 | /* | |
8971 | * If we didn't find an unused CRTC, don't use any. | |
8972 | */ | |
8973 | if (!crtc) { | |
7173188d | 8974 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8975 | goto fail_unlock; |
79e53945 JB |
8976 | } |
8977 | ||
51fd371b RC |
8978 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8979 | if (ret) | |
4d02e2de DV |
8980 | goto fail_unlock; |
8981 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
8982 | if (ret) | |
51fd371b | 8983 | goto fail_unlock; |
fc303101 DV |
8984 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8985 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8986 | |
8987 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 8988 | intel_crtc->new_enabled = true; |
6e3c9717 | 8989 | intel_crtc->new_config = intel_crtc->config; |
24218aac | 8990 | old->dpms_mode = connector->dpms; |
8261b191 | 8991 | old->load_detect_temp = true; |
d2dff872 | 8992 | old->release_fb = NULL; |
79e53945 | 8993 | |
83a57153 ACO |
8994 | state = drm_atomic_state_alloc(dev); |
8995 | if (!state) | |
8996 | return false; | |
8997 | ||
8998 | state->acquire_ctx = ctx; | |
8999 | ||
944b0c76 ACO |
9000 | connector_state = drm_atomic_get_connector_state(state, connector); |
9001 | if (IS_ERR(connector_state)) { | |
9002 | ret = PTR_ERR(connector_state); | |
9003 | goto fail; | |
9004 | } | |
9005 | ||
9006 | connector_state->crtc = crtc; | |
9007 | connector_state->best_encoder = &intel_encoder->base; | |
9008 | ||
6492711d CW |
9009 | if (!mode) |
9010 | mode = &load_detect_mode; | |
79e53945 | 9011 | |
d2dff872 CW |
9012 | /* We need a framebuffer large enough to accommodate all accesses |
9013 | * that the plane may generate whilst we perform load detection. | |
9014 | * We can not rely on the fbcon either being present (we get called | |
9015 | * during its initialisation to detect all boot displays, or it may | |
9016 | * not even exist) or that it is large enough to satisfy the | |
9017 | * requested mode. | |
9018 | */ | |
94352cf9 DV |
9019 | fb = mode_fits_in_fbdev(dev, mode); |
9020 | if (fb == NULL) { | |
d2dff872 | 9021 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9022 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9023 | old->release_fb = fb; | |
d2dff872 CW |
9024 | } else |
9025 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9026 | if (IS_ERR(fb)) { |
d2dff872 | 9027 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9028 | goto fail; |
79e53945 | 9029 | } |
79e53945 | 9030 | |
83a57153 | 9031 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9032 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9033 | if (old->release_fb) |
9034 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9035 | goto fail; |
79e53945 | 9036 | } |
9128b040 | 9037 | crtc->primary->crtc = crtc; |
7173188d | 9038 | |
79e53945 | 9039 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9040 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9041 | return true; |
412b61d8 VS |
9042 | |
9043 | fail: | |
83d65738 | 9044 | intel_crtc->new_enabled = crtc->state->enable; |
412b61d8 | 9045 | if (intel_crtc->new_enabled) |
6e3c9717 | 9046 | intel_crtc->new_config = intel_crtc->config; |
412b61d8 VS |
9047 | else |
9048 | intel_crtc->new_config = NULL; | |
51fd371b | 9049 | fail_unlock: |
83a57153 ACO |
9050 | if (state) { |
9051 | drm_atomic_state_free(state); | |
9052 | state = NULL; | |
9053 | } | |
9054 | ||
51fd371b RC |
9055 | if (ret == -EDEADLK) { |
9056 | drm_modeset_backoff(ctx); | |
9057 | goto retry; | |
9058 | } | |
9059 | ||
412b61d8 | 9060 | return false; |
79e53945 JB |
9061 | } |
9062 | ||
d2434ab7 | 9063 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9064 | struct intel_load_detect_pipe *old, |
9065 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9066 | { |
83a57153 | 9067 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9068 | struct intel_encoder *intel_encoder = |
9069 | intel_attached_encoder(connector); | |
4ef69c7a | 9070 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9071 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9073 | struct drm_atomic_state *state; |
944b0c76 | 9074 | struct drm_connector_state *connector_state; |
79e53945 | 9075 | |
d2dff872 | 9076 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9077 | connector->base.id, connector->name, |
8e329a03 | 9078 | encoder->base.id, encoder->name); |
d2dff872 | 9079 | |
8261b191 | 9080 | if (old->load_detect_temp) { |
83a57153 | 9081 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9082 | if (!state) |
9083 | goto fail; | |
83a57153 ACO |
9084 | |
9085 | state->acquire_ctx = ctx; | |
9086 | ||
944b0c76 ACO |
9087 | connector_state = drm_atomic_get_connector_state(state, connector); |
9088 | if (IS_ERR(connector_state)) | |
9089 | goto fail; | |
9090 | ||
fc303101 DV |
9091 | to_intel_connector(connector)->new_encoder = NULL; |
9092 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
9093 | intel_crtc->new_enabled = false; |
9094 | intel_crtc->new_config = NULL; | |
944b0c76 ACO |
9095 | |
9096 | connector_state->best_encoder = NULL; | |
9097 | connector_state->crtc = NULL; | |
9098 | ||
83a57153 ACO |
9099 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9100 | ||
9101 | drm_atomic_state_free(state); | |
d2dff872 | 9102 | |
36206361 DV |
9103 | if (old->release_fb) { |
9104 | drm_framebuffer_unregister_private(old->release_fb); | |
9105 | drm_framebuffer_unreference(old->release_fb); | |
9106 | } | |
d2dff872 | 9107 | |
0622a53c | 9108 | return; |
79e53945 JB |
9109 | } |
9110 | ||
c751ce4f | 9111 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9112 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9113 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9114 | |
9115 | return; | |
9116 | fail: | |
9117 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9118 | drm_atomic_state_free(state); | |
79e53945 JB |
9119 | } |
9120 | ||
da4a1efa | 9121 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9122 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9123 | { |
9124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9125 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9126 | ||
9127 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9128 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9129 | else if (HAS_PCH_SPLIT(dev)) |
9130 | return 120000; | |
9131 | else if (!IS_GEN2(dev)) | |
9132 | return 96000; | |
9133 | else | |
9134 | return 48000; | |
9135 | } | |
9136 | ||
79e53945 | 9137 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9138 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9139 | struct intel_crtc_state *pipe_config) |
79e53945 | 9140 | { |
f1f644dc | 9141 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9142 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9143 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9144 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9145 | u32 fp; |
9146 | intel_clock_t clock; | |
da4a1efa | 9147 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9148 | |
9149 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9150 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9151 | else |
293623f7 | 9152 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9153 | |
9154 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9155 | if (IS_PINEVIEW(dev)) { |
9156 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9157 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9158 | } else { |
9159 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9160 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9161 | } | |
9162 | ||
a6c45cf0 | 9163 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9164 | if (IS_PINEVIEW(dev)) |
9165 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9166 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9167 | else |
9168 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9169 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9170 | ||
9171 | switch (dpll & DPLL_MODE_MASK) { | |
9172 | case DPLLB_MODE_DAC_SERIAL: | |
9173 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9174 | 5 : 10; | |
9175 | break; | |
9176 | case DPLLB_MODE_LVDS: | |
9177 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9178 | 7 : 14; | |
9179 | break; | |
9180 | default: | |
28c97730 | 9181 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9182 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9183 | return; |
79e53945 JB |
9184 | } |
9185 | ||
ac58c3f0 | 9186 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9187 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9188 | else |
da4a1efa | 9189 | i9xx_clock(refclk, &clock); |
79e53945 | 9190 | } else { |
0fb58223 | 9191 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9192 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9193 | |
9194 | if (is_lvds) { | |
9195 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9196 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9197 | |
9198 | if (lvds & LVDS_CLKB_POWER_UP) | |
9199 | clock.p2 = 7; | |
9200 | else | |
9201 | clock.p2 = 14; | |
79e53945 JB |
9202 | } else { |
9203 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9204 | clock.p1 = 2; | |
9205 | else { | |
9206 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9207 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9208 | } | |
9209 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9210 | clock.p2 = 4; | |
9211 | else | |
9212 | clock.p2 = 2; | |
79e53945 | 9213 | } |
da4a1efa VS |
9214 | |
9215 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9216 | } |
9217 | ||
18442d08 VS |
9218 | /* |
9219 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9220 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9221 | * encoder's get_config() function. |
9222 | */ | |
9223 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9224 | } |
9225 | ||
6878da05 VS |
9226 | int intel_dotclock_calculate(int link_freq, |
9227 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9228 | { |
f1f644dc JB |
9229 | /* |
9230 | * The calculation for the data clock is: | |
1041a02f | 9231 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9232 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9233 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9234 | * |
9235 | * and the link clock is simpler: | |
1041a02f | 9236 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9237 | */ |
9238 | ||
6878da05 VS |
9239 | if (!m_n->link_n) |
9240 | return 0; | |
f1f644dc | 9241 | |
6878da05 VS |
9242 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9243 | } | |
f1f644dc | 9244 | |
18442d08 | 9245 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9246 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9247 | { |
9248 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9249 | |
18442d08 VS |
9250 | /* read out port_clock from the DPLL */ |
9251 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9252 | |
f1f644dc | 9253 | /* |
18442d08 | 9254 | * This value does not include pixel_multiplier. |
241bfc38 | 9255 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9256 | * agree once we know their relationship in the encoder's |
9257 | * get_config() function. | |
79e53945 | 9258 | */ |
2d112de7 | 9259 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9260 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9261 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9262 | } |
9263 | ||
9264 | /** Returns the currently programmed mode of the given pipe. */ | |
9265 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9266 | struct drm_crtc *crtc) | |
9267 | { | |
548f245b | 9268 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9270 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9271 | struct drm_display_mode *mode; |
5cec258b | 9272 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9273 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9274 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9275 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9276 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9277 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9278 | |
9279 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9280 | if (!mode) | |
9281 | return NULL; | |
9282 | ||
f1f644dc JB |
9283 | /* |
9284 | * Construct a pipe_config sufficient for getting the clock info | |
9285 | * back out of crtc_clock_get. | |
9286 | * | |
9287 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9288 | * to use a real value here instead. | |
9289 | */ | |
293623f7 | 9290 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9291 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9292 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9293 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9294 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9295 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9296 | ||
773ae034 | 9297 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9298 | mode->hdisplay = (htot & 0xffff) + 1; |
9299 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9300 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9301 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9302 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9303 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9304 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9305 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9306 | ||
9307 | drm_mode_set_name(mode); | |
79e53945 JB |
9308 | |
9309 | return mode; | |
9310 | } | |
9311 | ||
652c393a JB |
9312 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
9313 | { | |
9314 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9315 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9317 | |
baff296c | 9318 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9319 | return; |
9320 | ||
9321 | if (!dev_priv->lvds_downclock_avail) | |
9322 | return; | |
9323 | ||
9324 | /* | |
9325 | * Since this is called by a timer, we should never get here in | |
9326 | * the manual case. | |
9327 | */ | |
9328 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9329 | int pipe = intel_crtc->pipe; |
9330 | int dpll_reg = DPLL(pipe); | |
9331 | int dpll; | |
f6e5b160 | 9332 | |
44d98a61 | 9333 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9334 | |
8ac5a6d5 | 9335 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9336 | |
dc257cf1 | 9337 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9338 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9339 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9340 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9341 | dpll = I915_READ(dpll_reg); |
9342 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9343 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9344 | } |
9345 | ||
9346 | } | |
9347 | ||
f047e395 CW |
9348 | void intel_mark_busy(struct drm_device *dev) |
9349 | { | |
c67a470b PZ |
9350 | struct drm_i915_private *dev_priv = dev->dev_private; |
9351 | ||
f62a0076 CW |
9352 | if (dev_priv->mm.busy) |
9353 | return; | |
9354 | ||
43694d69 | 9355 | intel_runtime_pm_get(dev_priv); |
c67a470b | 9356 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
9357 | if (INTEL_INFO(dev)->gen >= 6) |
9358 | gen6_rps_busy(dev_priv); | |
f62a0076 | 9359 | dev_priv->mm.busy = true; |
f047e395 CW |
9360 | } |
9361 | ||
9362 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 9363 | { |
c67a470b | 9364 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9365 | struct drm_crtc *crtc; |
652c393a | 9366 | |
f62a0076 CW |
9367 | if (!dev_priv->mm.busy) |
9368 | return; | |
9369 | ||
9370 | dev_priv->mm.busy = false; | |
9371 | ||
70e1e0ec | 9372 | for_each_crtc(dev, crtc) { |
f4510a27 | 9373 | if (!crtc->primary->fb) |
652c393a JB |
9374 | continue; |
9375 | ||
725a5b54 | 9376 | intel_decrease_pllclock(crtc); |
652c393a | 9377 | } |
b29c19b6 | 9378 | |
3d13ef2e | 9379 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9380 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 9381 | |
43694d69 | 9382 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9383 | } |
9384 | ||
f5de6e07 ACO |
9385 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
9386 | struct intel_crtc_state *crtc_state) | |
9387 | { | |
9388 | kfree(crtc->config); | |
9389 | crtc->config = crtc_state; | |
16f3f658 | 9390 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
9391 | } |
9392 | ||
79e53945 JB |
9393 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9394 | { | |
9395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9396 | struct drm_device *dev = crtc->dev; |
9397 | struct intel_unpin_work *work; | |
67e77c5a | 9398 | |
5e2d7afc | 9399 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
9400 | work = intel_crtc->unpin_work; |
9401 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 9402 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
9403 | |
9404 | if (work) { | |
9405 | cancel_work_sync(&work->work); | |
9406 | kfree(work); | |
9407 | } | |
79e53945 | 9408 | |
f5de6e07 | 9409 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 9410 | drm_crtc_cleanup(crtc); |
67e77c5a | 9411 | |
79e53945 JB |
9412 | kfree(intel_crtc); |
9413 | } | |
9414 | ||
6b95a207 KH |
9415 | static void intel_unpin_work_fn(struct work_struct *__work) |
9416 | { | |
9417 | struct intel_unpin_work *work = | |
9418 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9419 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9420 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9421 | |
b4a98e57 | 9422 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 9423 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 9424 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 9425 | |
7ff0ebcc | 9426 | intel_fbc_update(dev); |
f06cc1b9 JH |
9427 | |
9428 | if (work->flip_queued_req) | |
146d84f0 | 9429 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
9430 | mutex_unlock(&dev->struct_mutex); |
9431 | ||
f99d7069 | 9432 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 9433 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 9434 | |
b4a98e57 CW |
9435 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9436 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9437 | ||
6b95a207 KH |
9438 | kfree(work); |
9439 | } | |
9440 | ||
1afe3e9d | 9441 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9442 | struct drm_crtc *crtc) |
6b95a207 | 9443 | { |
6b95a207 KH |
9444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9445 | struct intel_unpin_work *work; | |
6b95a207 KH |
9446 | unsigned long flags; |
9447 | ||
9448 | /* Ignore early vblank irqs */ | |
9449 | if (intel_crtc == NULL) | |
9450 | return; | |
9451 | ||
f326038a DV |
9452 | /* |
9453 | * This is called both by irq handlers and the reset code (to complete | |
9454 | * lost pageflips) so needs the full irqsave spinlocks. | |
9455 | */ | |
6b95a207 KH |
9456 | spin_lock_irqsave(&dev->event_lock, flags); |
9457 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9458 | |
9459 | /* Ensure we don't miss a work->pending update ... */ | |
9460 | smp_rmb(); | |
9461 | ||
9462 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9463 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9464 | return; | |
9465 | } | |
9466 | ||
d6bbafa1 | 9467 | page_flip_completed(intel_crtc); |
0af7e4df | 9468 | |
6b95a207 | 9469 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9470 | } |
9471 | ||
1afe3e9d JB |
9472 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9473 | { | |
fbee40df | 9474 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9475 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9476 | ||
49b14a5c | 9477 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9478 | } |
9479 | ||
9480 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9481 | { | |
fbee40df | 9482 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9483 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9484 | ||
49b14a5c | 9485 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9486 | } |
9487 | ||
75f7f3ec VS |
9488 | /* Is 'a' after or equal to 'b'? */ |
9489 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9490 | { | |
9491 | return !((a - b) & 0x80000000); | |
9492 | } | |
9493 | ||
9494 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9495 | { | |
9496 | struct drm_device *dev = crtc->base.dev; | |
9497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9498 | ||
bdfa7542 VS |
9499 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9500 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9501 | return true; | |
9502 | ||
75f7f3ec VS |
9503 | /* |
9504 | * The relevant registers doen't exist on pre-ctg. | |
9505 | * As the flip done interrupt doesn't trigger for mmio | |
9506 | * flips on gmch platforms, a flip count check isn't | |
9507 | * really needed there. But since ctg has the registers, | |
9508 | * include it in the check anyway. | |
9509 | */ | |
9510 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9511 | return true; | |
9512 | ||
9513 | /* | |
9514 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9515 | * used the same base address. In that case the mmio flip might | |
9516 | * have completed, but the CS hasn't even executed the flip yet. | |
9517 | * | |
9518 | * A flip count check isn't enough as the CS might have updated | |
9519 | * the base address just after start of vblank, but before we | |
9520 | * managed to process the interrupt. This means we'd complete the | |
9521 | * CS flip too soon. | |
9522 | * | |
9523 | * Combining both checks should get us a good enough result. It may | |
9524 | * still happen that the CS flip has been executed, but has not | |
9525 | * yet actually completed. But in case the base address is the same | |
9526 | * anyway, we don't really care. | |
9527 | */ | |
9528 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9529 | crtc->unpin_work->gtt_offset && | |
9530 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9531 | crtc->unpin_work->flip_count); | |
9532 | } | |
9533 | ||
6b95a207 KH |
9534 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9535 | { | |
fbee40df | 9536 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9537 | struct intel_crtc *intel_crtc = |
9538 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9539 | unsigned long flags; | |
9540 | ||
f326038a DV |
9541 | |
9542 | /* | |
9543 | * This is called both by irq handlers and the reset code (to complete | |
9544 | * lost pageflips) so needs the full irqsave spinlocks. | |
9545 | * | |
9546 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9547 | * generate a page-flip completion irq, i.e. every modeset |
9548 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9549 | */ | |
6b95a207 | 9550 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9551 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9552 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9553 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9554 | } | |
9555 | ||
eba905b2 | 9556 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9557 | { |
9558 | /* Ensure that the work item is consistent when activating it ... */ | |
9559 | smp_wmb(); | |
9560 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9561 | /* and that it is marked active as soon as the irq could fire. */ | |
9562 | smp_wmb(); | |
9563 | } | |
9564 | ||
8c9f3aaf JB |
9565 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9566 | struct drm_crtc *crtc, | |
9567 | struct drm_framebuffer *fb, | |
ed8d1975 | 9568 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9569 | struct intel_engine_cs *ring, |
ed8d1975 | 9570 | uint32_t flags) |
8c9f3aaf | 9571 | { |
8c9f3aaf | 9572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9573 | u32 flip_mask; |
9574 | int ret; | |
9575 | ||
6d90c952 | 9576 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9577 | if (ret) |
4fa62c89 | 9578 | return ret; |
8c9f3aaf JB |
9579 | |
9580 | /* Can't queue multiple flips, so wait for the previous | |
9581 | * one to finish before executing the next. | |
9582 | */ | |
9583 | if (intel_crtc->plane) | |
9584 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9585 | else | |
9586 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9587 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9588 | intel_ring_emit(ring, MI_NOOP); | |
9589 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9590 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9591 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9592 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9593 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9594 | |
9595 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9596 | __intel_ring_advance(ring); |
83d4092b | 9597 | return 0; |
8c9f3aaf JB |
9598 | } |
9599 | ||
9600 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9601 | struct drm_crtc *crtc, | |
9602 | struct drm_framebuffer *fb, | |
ed8d1975 | 9603 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9604 | struct intel_engine_cs *ring, |
ed8d1975 | 9605 | uint32_t flags) |
8c9f3aaf | 9606 | { |
8c9f3aaf | 9607 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9608 | u32 flip_mask; |
9609 | int ret; | |
9610 | ||
6d90c952 | 9611 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9612 | if (ret) |
4fa62c89 | 9613 | return ret; |
8c9f3aaf JB |
9614 | |
9615 | if (intel_crtc->plane) | |
9616 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9617 | else | |
9618 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9619 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9620 | intel_ring_emit(ring, MI_NOOP); | |
9621 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9622 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9623 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9624 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9625 | intel_ring_emit(ring, MI_NOOP); |
9626 | ||
e7d841ca | 9627 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9628 | __intel_ring_advance(ring); |
83d4092b | 9629 | return 0; |
8c9f3aaf JB |
9630 | } |
9631 | ||
9632 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9633 | struct drm_crtc *crtc, | |
9634 | struct drm_framebuffer *fb, | |
ed8d1975 | 9635 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9636 | struct intel_engine_cs *ring, |
ed8d1975 | 9637 | uint32_t flags) |
8c9f3aaf JB |
9638 | { |
9639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9640 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9641 | uint32_t pf, pipesrc; | |
9642 | int ret; | |
9643 | ||
6d90c952 | 9644 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9645 | if (ret) |
4fa62c89 | 9646 | return ret; |
8c9f3aaf JB |
9647 | |
9648 | /* i965+ uses the linear or tiled offsets from the | |
9649 | * Display Registers (which do not change across a page-flip) | |
9650 | * so we need only reprogram the base address. | |
9651 | */ | |
6d90c952 DV |
9652 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9653 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9654 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9655 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9656 | obj->tiling_mode); |
8c9f3aaf JB |
9657 | |
9658 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9659 | * untested on non-native modes, so ignore it for now. | |
9660 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9661 | */ | |
9662 | pf = 0; | |
9663 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9664 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9665 | |
9666 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9667 | __intel_ring_advance(ring); |
83d4092b | 9668 | return 0; |
8c9f3aaf JB |
9669 | } |
9670 | ||
9671 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9672 | struct drm_crtc *crtc, | |
9673 | struct drm_framebuffer *fb, | |
ed8d1975 | 9674 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9675 | struct intel_engine_cs *ring, |
ed8d1975 | 9676 | uint32_t flags) |
8c9f3aaf JB |
9677 | { |
9678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9679 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9680 | uint32_t pf, pipesrc; | |
9681 | int ret; | |
9682 | ||
6d90c952 | 9683 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9684 | if (ret) |
4fa62c89 | 9685 | return ret; |
8c9f3aaf | 9686 | |
6d90c952 DV |
9687 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9688 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9689 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9690 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9691 | |
dc257cf1 DV |
9692 | /* Contrary to the suggestions in the documentation, |
9693 | * "Enable Panel Fitter" does not seem to be required when page | |
9694 | * flipping with a non-native mode, and worse causes a normal | |
9695 | * modeset to fail. | |
9696 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9697 | */ | |
9698 | pf = 0; | |
8c9f3aaf | 9699 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9700 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9701 | |
9702 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9703 | __intel_ring_advance(ring); |
83d4092b | 9704 | return 0; |
8c9f3aaf JB |
9705 | } |
9706 | ||
7c9017e5 JB |
9707 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9708 | struct drm_crtc *crtc, | |
9709 | struct drm_framebuffer *fb, | |
ed8d1975 | 9710 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9711 | struct intel_engine_cs *ring, |
ed8d1975 | 9712 | uint32_t flags) |
7c9017e5 | 9713 | { |
7c9017e5 | 9714 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9715 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9716 | int len, ret; |
9717 | ||
eba905b2 | 9718 | switch (intel_crtc->plane) { |
cb05d8de DV |
9719 | case PLANE_A: |
9720 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9721 | break; | |
9722 | case PLANE_B: | |
9723 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9724 | break; | |
9725 | case PLANE_C: | |
9726 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9727 | break; | |
9728 | default: | |
9729 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9730 | return -ENODEV; |
cb05d8de DV |
9731 | } |
9732 | ||
ffe74d75 | 9733 | len = 4; |
f476828a | 9734 | if (ring->id == RCS) { |
ffe74d75 | 9735 | len += 6; |
f476828a DL |
9736 | /* |
9737 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9738 | * 48bits addresses, and we need a NOOP for the batch size to | |
9739 | * stay even. | |
9740 | */ | |
9741 | if (IS_GEN8(dev)) | |
9742 | len += 2; | |
9743 | } | |
ffe74d75 | 9744 | |
f66fab8e VS |
9745 | /* |
9746 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9747 | * "The full packet must be contained within the same cache line." | |
9748 | * | |
9749 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9750 | * cacheline, if we ever start emitting more commands before | |
9751 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9752 | * then do the cacheline alignment, and finally emit the | |
9753 | * MI_DISPLAY_FLIP. | |
9754 | */ | |
9755 | ret = intel_ring_cacheline_align(ring); | |
9756 | if (ret) | |
4fa62c89 | 9757 | return ret; |
f66fab8e | 9758 | |
ffe74d75 | 9759 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9760 | if (ret) |
4fa62c89 | 9761 | return ret; |
7c9017e5 | 9762 | |
ffe74d75 CW |
9763 | /* Unmask the flip-done completion message. Note that the bspec says that |
9764 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9765 | * more than one flip event at any time (or ensure that one flip message | |
9766 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9767 | * Experimentation says that BCS works despite DERRMR masking all | |
9768 | * flip-done completion events and that unmasking all planes at once | |
9769 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9770 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9771 | */ | |
9772 | if (ring->id == RCS) { | |
9773 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9774 | intel_ring_emit(ring, DERRMR); | |
9775 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9776 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9777 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9778 | if (IS_GEN8(dev)) |
9779 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9780 | MI_SRM_LRM_GLOBAL_GTT); | |
9781 | else | |
9782 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9783 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9784 | intel_ring_emit(ring, DERRMR); |
9785 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9786 | if (IS_GEN8(dev)) { |
9787 | intel_ring_emit(ring, 0); | |
9788 | intel_ring_emit(ring, MI_NOOP); | |
9789 | } | |
ffe74d75 CW |
9790 | } |
9791 | ||
cb05d8de | 9792 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9793 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9794 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9795 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9796 | |
9797 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9798 | __intel_ring_advance(ring); |
83d4092b | 9799 | return 0; |
7c9017e5 JB |
9800 | } |
9801 | ||
84c33a64 SG |
9802 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9803 | struct drm_i915_gem_object *obj) | |
9804 | { | |
9805 | /* | |
9806 | * This is not being used for older platforms, because | |
9807 | * non-availability of flip done interrupt forces us to use | |
9808 | * CS flips. Older platforms derive flip done using some clever | |
9809 | * tricks involving the flip_pending status bits and vblank irqs. | |
9810 | * So using MMIO flips there would disrupt this mechanism. | |
9811 | */ | |
9812 | ||
8e09bf83 CW |
9813 | if (ring == NULL) |
9814 | return true; | |
9815 | ||
84c33a64 SG |
9816 | if (INTEL_INFO(ring->dev)->gen < 5) |
9817 | return false; | |
9818 | ||
9819 | if (i915.use_mmio_flip < 0) | |
9820 | return false; | |
9821 | else if (i915.use_mmio_flip > 0) | |
9822 | return true; | |
14bf993e OM |
9823 | else if (i915.enable_execlists) |
9824 | return true; | |
84c33a64 | 9825 | else |
41c52415 | 9826 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
9827 | } |
9828 | ||
ff944564 DL |
9829 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
9830 | { | |
9831 | struct drm_device *dev = intel_crtc->base.dev; | |
9832 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9833 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
9834 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
9835 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9836 | const enum pipe pipe = intel_crtc->pipe; | |
9837 | u32 ctl, stride; | |
9838 | ||
9839 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
9840 | ctl &= ~PLANE_CTL_TILED_MASK; | |
9841 | if (obj->tiling_mode == I915_TILING_X) | |
9842 | ctl |= PLANE_CTL_TILED_X; | |
9843 | ||
9844 | /* | |
9845 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
9846 | * linear buffers or in number of tiles for tiled buffers. | |
9847 | */ | |
9848 | stride = fb->pitches[0] >> 6; | |
9849 | if (obj->tiling_mode == I915_TILING_X) | |
9850 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
9851 | ||
9852 | /* | |
9853 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
9854 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
9855 | */ | |
9856 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
9857 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
9858 | ||
9859 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
9860 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
9861 | } | |
9862 | ||
9863 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
9864 | { |
9865 | struct drm_device *dev = intel_crtc->base.dev; | |
9866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9867 | struct intel_framebuffer *intel_fb = | |
9868 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9869 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9870 | u32 dspcntr; | |
9871 | u32 reg; | |
9872 | ||
84c33a64 SG |
9873 | reg = DSPCNTR(intel_crtc->plane); |
9874 | dspcntr = I915_READ(reg); | |
9875 | ||
c5d97472 DL |
9876 | if (obj->tiling_mode != I915_TILING_NONE) |
9877 | dspcntr |= DISPPLANE_TILED; | |
9878 | else | |
9879 | dspcntr &= ~DISPPLANE_TILED; | |
9880 | ||
84c33a64 SG |
9881 | I915_WRITE(reg, dspcntr); |
9882 | ||
9883 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9884 | intel_crtc->unpin_work->gtt_offset); | |
9885 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 9886 | |
ff944564 DL |
9887 | } |
9888 | ||
9889 | /* | |
9890 | * XXX: This is the temporary way to update the plane registers until we get | |
9891 | * around to using the usual plane update functions for MMIO flips | |
9892 | */ | |
9893 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9894 | { | |
9895 | struct drm_device *dev = intel_crtc->base.dev; | |
9896 | bool atomic_update; | |
9897 | u32 start_vbl_count; | |
9898 | ||
9899 | intel_mark_page_flip_active(intel_crtc); | |
9900 | ||
9901 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
9902 | ||
9903 | if (INTEL_INFO(dev)->gen >= 9) | |
9904 | skl_do_mmio_flip(intel_crtc); | |
9905 | else | |
9906 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
9907 | ilk_do_mmio_flip(intel_crtc); | |
9908 | ||
9362c7c5 ACO |
9909 | if (atomic_update) |
9910 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
9911 | } |
9912 | ||
9362c7c5 | 9913 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 9914 | { |
cc8c4cc2 | 9915 | struct intel_crtc *crtc = |
9362c7c5 | 9916 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 9917 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 9918 | |
cc8c4cc2 JH |
9919 | mmio_flip = &crtc->mmio_flip; |
9920 | if (mmio_flip->req) | |
9c654818 JH |
9921 | WARN_ON(__i915_wait_request(mmio_flip->req, |
9922 | crtc->reset_counter, | |
9923 | false, NULL, NULL) != 0); | |
84c33a64 | 9924 | |
cc8c4cc2 JH |
9925 | intel_do_mmio_flip(crtc); |
9926 | if (mmio_flip->req) { | |
9927 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 9928 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
9929 | mutex_unlock(&crtc->base.dev->struct_mutex); |
9930 | } | |
84c33a64 SG |
9931 | } |
9932 | ||
9933 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9934 | struct drm_crtc *crtc, | |
9935 | struct drm_framebuffer *fb, | |
9936 | struct drm_i915_gem_object *obj, | |
9937 | struct intel_engine_cs *ring, | |
9938 | uint32_t flags) | |
9939 | { | |
84c33a64 | 9940 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 9941 | |
cc8c4cc2 JH |
9942 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
9943 | obj->last_write_req); | |
536f5b5e ACO |
9944 | |
9945 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 9946 | |
84c33a64 SG |
9947 | return 0; |
9948 | } | |
9949 | ||
8c9f3aaf JB |
9950 | static int intel_default_queue_flip(struct drm_device *dev, |
9951 | struct drm_crtc *crtc, | |
9952 | struct drm_framebuffer *fb, | |
ed8d1975 | 9953 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9954 | struct intel_engine_cs *ring, |
ed8d1975 | 9955 | uint32_t flags) |
8c9f3aaf JB |
9956 | { |
9957 | return -ENODEV; | |
9958 | } | |
9959 | ||
d6bbafa1 CW |
9960 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9961 | struct drm_crtc *crtc) | |
9962 | { | |
9963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9964 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9965 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9966 | u32 addr; | |
9967 | ||
9968 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9969 | return true; | |
9970 | ||
9971 | if (!work->enable_stall_check) | |
9972 | return false; | |
9973 | ||
9974 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
9975 | if (work->flip_queued_req && |
9976 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
9977 | return false; |
9978 | ||
1e3feefd | 9979 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
9980 | } |
9981 | ||
1e3feefd | 9982 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
9983 | return false; |
9984 | ||
9985 | /* Potential stall - if we see that the flip has happened, | |
9986 | * assume a missed interrupt. */ | |
9987 | if (INTEL_INFO(dev)->gen >= 4) | |
9988 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9989 | else | |
9990 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9991 | ||
9992 | /* There is a potential issue here with a false positive after a flip | |
9993 | * to the same address. We could address this by checking for a | |
9994 | * non-incrementing frame counter. | |
9995 | */ | |
9996 | return addr == work->gtt_offset; | |
9997 | } | |
9998 | ||
9999 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10000 | { | |
10001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10002 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f326038a | 10004 | |
6c51d46f | 10005 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10006 | |
10007 | if (crtc == NULL) | |
10008 | return; | |
10009 | ||
f326038a | 10010 | spin_lock(&dev->event_lock); |
d6bbafa1 CW |
10011 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { |
10012 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
1e3feefd DV |
10013 | intel_crtc->unpin_work->flip_queued_vblank, |
10014 | drm_vblank_count(dev, pipe)); | |
d6bbafa1 CW |
10015 | page_flip_completed(intel_crtc); |
10016 | } | |
f326038a | 10017 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10018 | } |
10019 | ||
6b95a207 KH |
10020 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10021 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10022 | struct drm_pending_vblank_event *event, |
10023 | uint32_t page_flip_flags) | |
6b95a207 KH |
10024 | { |
10025 | struct drm_device *dev = crtc->dev; | |
10026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10027 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10028 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10029 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10030 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10031 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10032 | struct intel_unpin_work *work; |
a4872ba6 | 10033 | struct intel_engine_cs *ring; |
52e68630 | 10034 | int ret; |
6b95a207 | 10035 | |
2ff8fde1 MR |
10036 | /* |
10037 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10038 | * check to be safe. In the future we may enable pageflipping from | |
10039 | * a disabled primary plane. | |
10040 | */ | |
10041 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10042 | return -EBUSY; | |
10043 | ||
e6a595d2 | 10044 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10045 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10046 | return -EINVAL; |
10047 | ||
10048 | /* | |
10049 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10050 | * Note that pitch changes could also affect these register. | |
10051 | */ | |
10052 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10053 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10054 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10055 | return -EINVAL; |
10056 | ||
f900db47 CW |
10057 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10058 | goto out_hang; | |
10059 | ||
b14c5679 | 10060 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10061 | if (work == NULL) |
10062 | return -ENOMEM; | |
10063 | ||
6b95a207 | 10064 | work->event = event; |
b4a98e57 | 10065 | work->crtc = crtc; |
ab8d6675 | 10066 | work->old_fb = old_fb; |
6b95a207 KH |
10067 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10068 | ||
87b6b101 | 10069 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10070 | if (ret) |
10071 | goto free_work; | |
10072 | ||
6b95a207 | 10073 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10074 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10075 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10076 | /* Before declaring the flip queue wedged, check if |
10077 | * the hardware completed the operation behind our backs. | |
10078 | */ | |
10079 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10080 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10081 | page_flip_completed(intel_crtc); | |
10082 | } else { | |
10083 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10084 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10085 | |
d6bbafa1 CW |
10086 | drm_crtc_vblank_put(crtc); |
10087 | kfree(work); | |
10088 | return -EBUSY; | |
10089 | } | |
6b95a207 KH |
10090 | } |
10091 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10092 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10093 | |
b4a98e57 CW |
10094 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10095 | flush_workqueue(dev_priv->wq); | |
10096 | ||
75dfca80 | 10097 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10098 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10099 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10100 | |
f4510a27 | 10101 | crtc->primary->fb = fb; |
afd65eb4 | 10102 | update_state_fb(crtc->primary); |
1ed1f968 | 10103 | |
e1f99ce6 | 10104 | work->pending_flip_obj = obj; |
e1f99ce6 | 10105 | |
89ed88ba CW |
10106 | ret = i915_mutex_lock_interruptible(dev); |
10107 | if (ret) | |
10108 | goto cleanup; | |
10109 | ||
b4a98e57 | 10110 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10111 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10112 | |
75f7f3ec | 10113 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10114 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10115 | |
4fa62c89 VS |
10116 | if (IS_VALLEYVIEW(dev)) { |
10117 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10118 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10119 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10120 | ring = NULL; | |
48bf5b2d | 10121 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10122 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10123 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10124 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10125 | if (ring == NULL || ring->id != RCS) |
10126 | ring = &dev_priv->ring[BCS]; | |
10127 | } else { | |
10128 | ring = &dev_priv->ring[RCS]; | |
10129 | } | |
10130 | ||
82bc3b2d TU |
10131 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
10132 | crtc->primary->state, ring); | |
8c9f3aaf JB |
10133 | if (ret) |
10134 | goto cleanup_pending; | |
6b95a207 | 10135 | |
121920fa TU |
10136 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10137 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10138 | |
d6bbafa1 | 10139 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
10140 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10141 | page_flip_flags); | |
d6bbafa1 CW |
10142 | if (ret) |
10143 | goto cleanup_unpin; | |
10144 | ||
f06cc1b9 JH |
10145 | i915_gem_request_assign(&work->flip_queued_req, |
10146 | obj->last_write_req); | |
d6bbafa1 | 10147 | } else { |
84c33a64 | 10148 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10149 | page_flip_flags); |
10150 | if (ret) | |
10151 | goto cleanup_unpin; | |
10152 | ||
f06cc1b9 JH |
10153 | i915_gem_request_assign(&work->flip_queued_req, |
10154 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10155 | } |
10156 | ||
1e3feefd | 10157 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10158 | work->enable_stall_check = true; |
4fa62c89 | 10159 | |
ab8d6675 | 10160 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10161 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10162 | ||
7ff0ebcc | 10163 | intel_fbc_disable(dev); |
f99d7069 | 10164 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10165 | mutex_unlock(&dev->struct_mutex); |
10166 | ||
e5510fac JB |
10167 | trace_i915_flip_request(intel_crtc->plane, obj); |
10168 | ||
6b95a207 | 10169 | return 0; |
96b099fd | 10170 | |
4fa62c89 | 10171 | cleanup_unpin: |
82bc3b2d | 10172 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10173 | cleanup_pending: |
b4a98e57 | 10174 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10175 | mutex_unlock(&dev->struct_mutex); |
10176 | cleanup: | |
f4510a27 | 10177 | crtc->primary->fb = old_fb; |
afd65eb4 | 10178 | update_state_fb(crtc->primary); |
89ed88ba CW |
10179 | |
10180 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10181 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10182 | |
5e2d7afc | 10183 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10184 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10185 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10186 | |
87b6b101 | 10187 | drm_crtc_vblank_put(crtc); |
7317c75e | 10188 | free_work: |
96b099fd CW |
10189 | kfree(work); |
10190 | ||
f900db47 CW |
10191 | if (ret == -EIO) { |
10192 | out_hang: | |
53a366b9 | 10193 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10194 | if (ret == 0 && event) { |
5e2d7afc | 10195 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10196 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10197 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10198 | } |
f900db47 | 10199 | } |
96b099fd | 10200 | return ret; |
6b95a207 KH |
10201 | } |
10202 | ||
f6e5b160 | 10203 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10204 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10205 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10206 | .atomic_begin = intel_begin_crtc_commit, |
10207 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10208 | }; |
10209 | ||
9a935856 DV |
10210 | /** |
10211 | * intel_modeset_update_staged_output_state | |
10212 | * | |
10213 | * Updates the staged output configuration state, e.g. after we've read out the | |
10214 | * current hw state. | |
10215 | */ | |
10216 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10217 | { |
7668851f | 10218 | struct intel_crtc *crtc; |
9a935856 DV |
10219 | struct intel_encoder *encoder; |
10220 | struct intel_connector *connector; | |
f6e5b160 | 10221 | |
3a3371ff | 10222 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10223 | connector->new_encoder = |
10224 | to_intel_encoder(connector->base.encoder); | |
10225 | } | |
f6e5b160 | 10226 | |
b2784e15 | 10227 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10228 | encoder->new_crtc = |
10229 | to_intel_crtc(encoder->base.crtc); | |
10230 | } | |
7668851f | 10231 | |
d3fcc808 | 10232 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10233 | crtc->new_enabled = crtc->base.state->enable; |
7bd0a8e7 VS |
10234 | |
10235 | if (crtc->new_enabled) | |
6e3c9717 | 10236 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
10237 | else |
10238 | crtc->new_config = NULL; | |
7668851f | 10239 | } |
f6e5b160 CW |
10240 | } |
10241 | ||
d29b2f9d ACO |
10242 | /* Transitional helper to copy current connector/encoder state to |
10243 | * connector->state. This is needed so that code that is partially | |
10244 | * converted to atomic does the right thing. | |
10245 | */ | |
10246 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
10247 | { | |
10248 | struct intel_connector *connector; | |
10249 | ||
10250 | for_each_intel_connector(dev, connector) { | |
10251 | if (connector->base.encoder) { | |
10252 | connector->base.state->best_encoder = | |
10253 | connector->base.encoder; | |
10254 | connector->base.state->crtc = | |
10255 | connector->base.encoder->crtc; | |
10256 | } else { | |
10257 | connector->base.state->best_encoder = NULL; | |
10258 | connector->base.state->crtc = NULL; | |
10259 | } | |
10260 | } | |
10261 | } | |
10262 | ||
9a935856 DV |
10263 | /** |
10264 | * intel_modeset_commit_output_state | |
10265 | * | |
10266 | * This function copies the stage display pipe configuration to the real one. | |
10267 | */ | |
10268 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10269 | { | |
7668851f | 10270 | struct intel_crtc *crtc; |
9a935856 DV |
10271 | struct intel_encoder *encoder; |
10272 | struct intel_connector *connector; | |
f6e5b160 | 10273 | |
3a3371ff | 10274 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10275 | connector->base.encoder = &connector->new_encoder->base; |
10276 | } | |
f6e5b160 | 10277 | |
b2784e15 | 10278 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10279 | encoder->base.crtc = &encoder->new_crtc->base; |
10280 | } | |
7668851f | 10281 | |
d3fcc808 | 10282 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10283 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10284 | crtc->base.enabled = crtc->new_enabled; |
10285 | } | |
d29b2f9d ACO |
10286 | |
10287 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
10288 | } |
10289 | ||
050f7aeb | 10290 | static void |
eba905b2 | 10291 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10292 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
10293 | { |
10294 | int bpp = pipe_config->pipe_bpp; | |
10295 | ||
10296 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10297 | connector->base.base.id, | |
c23cc417 | 10298 | connector->base.name); |
050f7aeb DV |
10299 | |
10300 | /* Don't use an invalid EDID bpc value */ | |
10301 | if (connector->base.display_info.bpc && | |
10302 | connector->base.display_info.bpc * 3 < bpp) { | |
10303 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10304 | bpp, connector->base.display_info.bpc*3); | |
10305 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10306 | } | |
10307 | ||
10308 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10309 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10310 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10311 | bpp); | |
10312 | pipe_config->pipe_bpp = 24; | |
10313 | } | |
10314 | } | |
10315 | ||
4e53c2e0 | 10316 | static int |
050f7aeb DV |
10317 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10318 | struct drm_framebuffer *fb, | |
5cec258b | 10319 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10320 | { |
050f7aeb DV |
10321 | struct drm_device *dev = crtc->base.dev; |
10322 | struct intel_connector *connector; | |
4e53c2e0 DV |
10323 | int bpp; |
10324 | ||
d42264b1 DV |
10325 | switch (fb->pixel_format) { |
10326 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10327 | bpp = 8*3; /* since we go through a colormap */ |
10328 | break; | |
d42264b1 DV |
10329 | case DRM_FORMAT_XRGB1555: |
10330 | case DRM_FORMAT_ARGB1555: | |
10331 | /* checked in intel_framebuffer_init already */ | |
10332 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10333 | return -EINVAL; | |
10334 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10335 | bpp = 6*3; /* min is 18bpp */ |
10336 | break; | |
d42264b1 DV |
10337 | case DRM_FORMAT_XBGR8888: |
10338 | case DRM_FORMAT_ABGR8888: | |
10339 | /* checked in intel_framebuffer_init already */ | |
10340 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10341 | return -EINVAL; | |
10342 | case DRM_FORMAT_XRGB8888: | |
10343 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10344 | bpp = 8*3; |
10345 | break; | |
d42264b1 DV |
10346 | case DRM_FORMAT_XRGB2101010: |
10347 | case DRM_FORMAT_ARGB2101010: | |
10348 | case DRM_FORMAT_XBGR2101010: | |
10349 | case DRM_FORMAT_ABGR2101010: | |
10350 | /* checked in intel_framebuffer_init already */ | |
10351 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10352 | return -EINVAL; |
4e53c2e0 DV |
10353 | bpp = 10*3; |
10354 | break; | |
baba133a | 10355 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10356 | default: |
10357 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10358 | return -EINVAL; | |
10359 | } | |
10360 | ||
4e53c2e0 DV |
10361 | pipe_config->pipe_bpp = bpp; |
10362 | ||
10363 | /* Clamp display bpp to EDID value */ | |
3a3371ff | 10364 | for_each_intel_connector(dev, connector) { |
1b829e05 DV |
10365 | if (!connector->new_encoder || |
10366 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
10367 | continue; |
10368 | ||
050f7aeb | 10369 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10370 | } |
10371 | ||
10372 | return bpp; | |
10373 | } | |
10374 | ||
644db711 DV |
10375 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10376 | { | |
10377 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10378 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10379 | mode->crtc_clock, |
644db711 DV |
10380 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10381 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10382 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10383 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10384 | } | |
10385 | ||
c0b03411 | 10386 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10387 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10388 | const char *context) |
10389 | { | |
10390 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10391 | context, pipe_name(crtc->pipe)); | |
10392 | ||
10393 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10394 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10395 | pipe_config->pipe_bpp, pipe_config->dither); | |
10396 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10397 | pipe_config->has_pch_encoder, | |
10398 | pipe_config->fdi_lanes, | |
10399 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10400 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10401 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10402 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10403 | pipe_config->has_dp_encoder, | |
10404 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10405 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10406 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10407 | |
10408 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10409 | pipe_config->has_dp_encoder, | |
10410 | pipe_config->dp_m2_n2.gmch_m, | |
10411 | pipe_config->dp_m2_n2.gmch_n, | |
10412 | pipe_config->dp_m2_n2.link_m, | |
10413 | pipe_config->dp_m2_n2.link_n, | |
10414 | pipe_config->dp_m2_n2.tu); | |
10415 | ||
55072d19 DV |
10416 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
10417 | pipe_config->has_audio, | |
10418 | pipe_config->has_infoframe); | |
10419 | ||
c0b03411 | 10420 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10421 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10422 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10423 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10424 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 10425 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10426 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10427 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10428 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10429 | pipe_config->gmch_pfit.control, | |
10430 | pipe_config->gmch_pfit.pgm_ratios, | |
10431 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10432 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10433 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10434 | pipe_config->pch_pfit.size, |
10435 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10436 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10437 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10438 | } |
10439 | ||
bc079e8b VS |
10440 | static bool encoders_cloneable(const struct intel_encoder *a, |
10441 | const struct intel_encoder *b) | |
accfc0c5 | 10442 | { |
bc079e8b VS |
10443 | /* masks could be asymmetric, so check both ways */ |
10444 | return a == b || (a->cloneable & (1 << b->type) && | |
10445 | b->cloneable & (1 << a->type)); | |
10446 | } | |
10447 | ||
10448 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10449 | struct intel_encoder *encoder) | |
10450 | { | |
10451 | struct drm_device *dev = crtc->base.dev; | |
10452 | struct intel_encoder *source_encoder; | |
10453 | ||
b2784e15 | 10454 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10455 | if (source_encoder->new_crtc != crtc) |
10456 | continue; | |
10457 | ||
10458 | if (!encoders_cloneable(encoder, source_encoder)) | |
10459 | return false; | |
10460 | } | |
10461 | ||
10462 | return true; | |
10463 | } | |
10464 | ||
10465 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10466 | { | |
10467 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10468 | struct intel_encoder *encoder; |
10469 | ||
b2784e15 | 10470 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10471 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10472 | continue; |
10473 | ||
bc079e8b VS |
10474 | if (!check_single_encoder_cloning(crtc, encoder)) |
10475 | return false; | |
accfc0c5 DV |
10476 | } |
10477 | ||
bc079e8b | 10478 | return true; |
accfc0c5 DV |
10479 | } |
10480 | ||
00f0b378 VS |
10481 | static bool check_digital_port_conflicts(struct drm_device *dev) |
10482 | { | |
10483 | struct intel_connector *connector; | |
10484 | unsigned int used_ports = 0; | |
10485 | ||
10486 | /* | |
10487 | * Walk the connector list instead of the encoder | |
10488 | * list to detect the problem on ddi platforms | |
10489 | * where there's just one encoder per digital port. | |
10490 | */ | |
3a3371ff | 10491 | for_each_intel_connector(dev, connector) { |
00f0b378 VS |
10492 | struct intel_encoder *encoder = connector->new_encoder; |
10493 | ||
10494 | if (!encoder) | |
10495 | continue; | |
10496 | ||
10497 | WARN_ON(!encoder->new_crtc); | |
10498 | ||
10499 | switch (encoder->type) { | |
10500 | unsigned int port_mask; | |
10501 | case INTEL_OUTPUT_UNKNOWN: | |
10502 | if (WARN_ON(!HAS_DDI(dev))) | |
10503 | break; | |
10504 | case INTEL_OUTPUT_DISPLAYPORT: | |
10505 | case INTEL_OUTPUT_HDMI: | |
10506 | case INTEL_OUTPUT_EDP: | |
10507 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10508 | ||
10509 | /* the same port mustn't appear more than once */ | |
10510 | if (used_ports & port_mask) | |
10511 | return false; | |
10512 | ||
10513 | used_ports |= port_mask; | |
10514 | default: | |
10515 | break; | |
10516 | } | |
10517 | } | |
10518 | ||
10519 | return true; | |
10520 | } | |
10521 | ||
83a57153 ACO |
10522 | static void |
10523 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10524 | { | |
10525 | struct drm_crtc_state tmp_state; | |
10526 | ||
10527 | /* Clear only the intel specific part of the crtc state */ | |
10528 | tmp_state = crtc_state->base; | |
10529 | memset(crtc_state, 0, sizeof *crtc_state); | |
10530 | crtc_state->base = tmp_state; | |
10531 | } | |
10532 | ||
5cec258b | 10533 | static struct intel_crtc_state * |
b8cecdf5 | 10534 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
4e53c2e0 | 10535 | struct drm_framebuffer *fb, |
83a57153 ACO |
10536 | struct drm_display_mode *mode, |
10537 | struct drm_atomic_state *state) | |
ee7b9f93 | 10538 | { |
7758a113 | 10539 | struct drm_device *dev = crtc->dev; |
7758a113 | 10540 | struct intel_encoder *encoder; |
5cec258b | 10541 | struct intel_crtc_state *pipe_config; |
e29c22c0 DV |
10542 | int plane_bpp, ret = -EINVAL; |
10543 | bool retry = true; | |
ee7b9f93 | 10544 | |
bc079e8b | 10545 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10546 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10547 | return ERR_PTR(-EINVAL); | |
10548 | } | |
10549 | ||
00f0b378 VS |
10550 | if (!check_digital_port_conflicts(dev)) { |
10551 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
10552 | return ERR_PTR(-EINVAL); | |
10553 | } | |
10554 | ||
83a57153 ACO |
10555 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
10556 | if (IS_ERR(pipe_config)) | |
10557 | return pipe_config; | |
10558 | ||
10559 | clear_intel_crtc_state(pipe_config); | |
7758a113 | 10560 | |
07878248 | 10561 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
10562 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
10563 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 10564 | |
e143a21c DV |
10565 | pipe_config->cpu_transcoder = |
10566 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10567 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10568 | |
2960bc9c ID |
10569 | /* |
10570 | * Sanitize sync polarity flags based on requested ones. If neither | |
10571 | * positive or negative polarity is requested, treat this as meaning | |
10572 | * negative polarity. | |
10573 | */ | |
2d112de7 | 10574 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10575 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10576 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10577 | |
2d112de7 | 10578 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10579 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10580 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10581 | |
050f7aeb DV |
10582 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10583 | * plane pixel format and any sink constraints into account. Returns the | |
10584 | * source plane bpp so that dithering can be selected on mismatches | |
10585 | * after encoders and crtc also have had their say. */ | |
10586 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10587 | fb, pipe_config); | |
4e53c2e0 DV |
10588 | if (plane_bpp < 0) |
10589 | goto fail; | |
10590 | ||
e41a56be VS |
10591 | /* |
10592 | * Determine the real pipe dimensions. Note that stereo modes can | |
10593 | * increase the actual pipe size due to the frame doubling and | |
10594 | * insertion of additional space for blanks between the frame. This | |
10595 | * is stored in the crtc timings. We use the requested mode to do this | |
10596 | * computation to clearly distinguish it from the adjusted mode, which | |
10597 | * can be changed by the connectors in the below retry loop. | |
10598 | */ | |
2d112de7 | 10599 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10600 | &pipe_config->pipe_src_w, |
10601 | &pipe_config->pipe_src_h); | |
e41a56be | 10602 | |
e29c22c0 | 10603 | encoder_retry: |
ef1b460d | 10604 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10605 | pipe_config->port_clock = 0; |
ef1b460d | 10606 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10607 | |
135c81b8 | 10608 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10609 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10610 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10611 | |
7758a113 DV |
10612 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10613 | * adjust it according to limitations or connector properties, and also | |
10614 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10615 | */ |
b2784e15 | 10616 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10617 | |
7758a113 DV |
10618 | if (&encoder->new_crtc->base != crtc) |
10619 | continue; | |
7ae89233 | 10620 | |
efea6e8e DV |
10621 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10622 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10623 | goto fail; |
10624 | } | |
ee7b9f93 | 10625 | } |
47f1c6c9 | 10626 | |
ff9a6750 DV |
10627 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10628 | * done afterwards in case the encoder adjusts the mode. */ | |
10629 | if (!pipe_config->port_clock) | |
2d112de7 | 10630 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10631 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10632 | |
a43f6e0f | 10633 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10634 | if (ret < 0) { |
7758a113 DV |
10635 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10636 | goto fail; | |
ee7b9f93 | 10637 | } |
e29c22c0 DV |
10638 | |
10639 | if (ret == RETRY) { | |
10640 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10641 | ret = -EINVAL; | |
10642 | goto fail; | |
10643 | } | |
10644 | ||
10645 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10646 | retry = false; | |
10647 | goto encoder_retry; | |
10648 | } | |
10649 | ||
4e53c2e0 DV |
10650 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10651 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10652 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10653 | ||
b8cecdf5 | 10654 | return pipe_config; |
7758a113 | 10655 | fail: |
e29c22c0 | 10656 | return ERR_PTR(ret); |
ee7b9f93 | 10657 | } |
47f1c6c9 | 10658 | |
e2e1ed41 DV |
10659 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10660 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10661 | static void | |
10662 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10663 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10664 | { |
10665 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10666 | struct drm_device *dev = crtc->dev; |
10667 | struct intel_encoder *encoder; | |
10668 | struct intel_connector *connector; | |
10669 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10670 | |
e2e1ed41 | 10671 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10672 | |
e2e1ed41 DV |
10673 | /* Check which crtcs have changed outputs connected to them, these need |
10674 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10675 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10676 | * bit set at most. */ | |
3a3371ff | 10677 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
10678 | if (connector->base.encoder == &connector->new_encoder->base) |
10679 | continue; | |
79e53945 | 10680 | |
e2e1ed41 DV |
10681 | if (connector->base.encoder) { |
10682 | tmp_crtc = connector->base.encoder->crtc; | |
10683 | ||
10684 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10685 | } | |
10686 | ||
10687 | if (connector->new_encoder) | |
10688 | *prepare_pipes |= | |
10689 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10690 | } |
10691 | ||
b2784e15 | 10692 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10693 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10694 | continue; | |
10695 | ||
10696 | if (encoder->base.crtc) { | |
10697 | tmp_crtc = encoder->base.crtc; | |
10698 | ||
10699 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10700 | } | |
10701 | ||
10702 | if (encoder->new_crtc) | |
10703 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10704 | } |
10705 | ||
7668851f | 10706 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10707 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10708 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 10709 | continue; |
7e7d76c3 | 10710 | |
7668851f | 10711 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10712 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10713 | else |
10714 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10715 | } |
10716 | ||
e2e1ed41 DV |
10717 | |
10718 | /* set_mode is also used to update properties on life display pipes. */ | |
10719 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10720 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10721 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10722 | ||
b6c5164d DV |
10723 | /* |
10724 | * For simplicity do a full modeset on any pipe where the output routing | |
10725 | * changed. We could be more clever, but that would require us to be | |
10726 | * more careful with calling the relevant encoder->mode_set functions. | |
10727 | */ | |
e2e1ed41 DV |
10728 | if (*prepare_pipes) |
10729 | *modeset_pipes = *prepare_pipes; | |
10730 | ||
10731 | /* ... and mask these out. */ | |
10732 | *modeset_pipes &= ~(*disable_pipes); | |
10733 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10734 | |
10735 | /* | |
10736 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10737 | * obies this rule, but the modeset restore mode of | |
10738 | * intel_modeset_setup_hw_state does not. | |
10739 | */ | |
10740 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10741 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10742 | |
10743 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10744 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10745 | } |
79e53945 | 10746 | |
ea9d758d | 10747 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10748 | { |
ea9d758d | 10749 | struct drm_encoder *encoder; |
f6e5b160 | 10750 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10751 | |
ea9d758d DV |
10752 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10753 | if (encoder->crtc == crtc) | |
10754 | return true; | |
10755 | ||
10756 | return false; | |
10757 | } | |
10758 | ||
10759 | static void | |
10760 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10761 | { | |
ba41c0de | 10762 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
10763 | struct intel_encoder *intel_encoder; |
10764 | struct intel_crtc *intel_crtc; | |
10765 | struct drm_connector *connector; | |
10766 | ||
ba41c0de DV |
10767 | intel_shared_dpll_commit(dev_priv); |
10768 | ||
b2784e15 | 10769 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10770 | if (!intel_encoder->base.crtc) |
10771 | continue; | |
10772 | ||
10773 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10774 | ||
10775 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10776 | intel_encoder->connectors_active = false; | |
10777 | } | |
10778 | ||
10779 | intel_modeset_commit_output_state(dev); | |
10780 | ||
7668851f | 10781 | /* Double check state. */ |
d3fcc808 | 10782 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10783 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 | 10784 | WARN_ON(intel_crtc->new_config && |
6e3c9717 | 10785 | intel_crtc->new_config != intel_crtc->config); |
83d65738 | 10786 | WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config); |
ea9d758d DV |
10787 | } |
10788 | ||
10789 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10790 | if (!connector->encoder || !connector->encoder->crtc) | |
10791 | continue; | |
10792 | ||
10793 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10794 | ||
10795 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10796 | struct drm_property *dpms_property = |
10797 | dev->mode_config.dpms_property; | |
10798 | ||
ea9d758d | 10799 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10800 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10801 | dpms_property, |
10802 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10803 | |
10804 | intel_encoder = to_intel_encoder(connector->encoder); | |
10805 | intel_encoder->connectors_active = true; | |
10806 | } | |
10807 | } | |
10808 | ||
10809 | } | |
10810 | ||
3bd26263 | 10811 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10812 | { |
3bd26263 | 10813 | int diff; |
f1f644dc JB |
10814 | |
10815 | if (clock1 == clock2) | |
10816 | return true; | |
10817 | ||
10818 | if (!clock1 || !clock2) | |
10819 | return false; | |
10820 | ||
10821 | diff = abs(clock1 - clock2); | |
10822 | ||
10823 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10824 | return true; | |
10825 | ||
10826 | return false; | |
10827 | } | |
10828 | ||
25c5b266 DV |
10829 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10830 | list_for_each_entry((intel_crtc), \ | |
10831 | &(dev)->mode_config.crtc_list, \ | |
10832 | base.head) \ | |
0973f18f | 10833 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10834 | |
0e8ffe1b | 10835 | static bool |
2fa2fe9a | 10836 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
10837 | struct intel_crtc_state *current_config, |
10838 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 10839 | { |
66e985c0 DV |
10840 | #define PIPE_CONF_CHECK_X(name) \ |
10841 | if (current_config->name != pipe_config->name) { \ | |
10842 | DRM_ERROR("mismatch in " #name " " \ | |
10843 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10844 | current_config->name, \ | |
10845 | pipe_config->name); \ | |
10846 | return false; \ | |
10847 | } | |
10848 | ||
08a24034 DV |
10849 | #define PIPE_CONF_CHECK_I(name) \ |
10850 | if (current_config->name != pipe_config->name) { \ | |
10851 | DRM_ERROR("mismatch in " #name " " \ | |
10852 | "(expected %i, found %i)\n", \ | |
10853 | current_config->name, \ | |
10854 | pipe_config->name); \ | |
10855 | return false; \ | |
88adfff1 DV |
10856 | } |
10857 | ||
b95af8be VK |
10858 | /* This is required for BDW+ where there is only one set of registers for |
10859 | * switching between high and low RR. | |
10860 | * This macro can be used whenever a comparison has to be made between one | |
10861 | * hw state and multiple sw state variables. | |
10862 | */ | |
10863 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10864 | if ((current_config->name != pipe_config->name) && \ | |
10865 | (current_config->alt_name != pipe_config->name)) { \ | |
10866 | DRM_ERROR("mismatch in " #name " " \ | |
10867 | "(expected %i or %i, found %i)\n", \ | |
10868 | current_config->name, \ | |
10869 | current_config->alt_name, \ | |
10870 | pipe_config->name); \ | |
10871 | return false; \ | |
10872 | } | |
10873 | ||
1bd1bd80 DV |
10874 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10875 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10876 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10877 | "(expected %i, found %i)\n", \ |
10878 | current_config->name & (mask), \ | |
10879 | pipe_config->name & (mask)); \ | |
10880 | return false; \ | |
10881 | } | |
10882 | ||
5e550656 VS |
10883 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10884 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10885 | DRM_ERROR("mismatch in " #name " " \ | |
10886 | "(expected %i, found %i)\n", \ | |
10887 | current_config->name, \ | |
10888 | pipe_config->name); \ | |
10889 | return false; \ | |
10890 | } | |
10891 | ||
bb760063 DV |
10892 | #define PIPE_CONF_QUIRK(quirk) \ |
10893 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10894 | ||
eccb140b DV |
10895 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10896 | ||
08a24034 DV |
10897 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10898 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10899 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10900 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10901 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10902 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10903 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10904 | |
eb14cb74 | 10905 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10906 | |
10907 | if (INTEL_INFO(dev)->gen < 8) { | |
10908 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10909 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10910 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10911 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10912 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10913 | ||
10914 | if (current_config->has_drrs) { | |
10915 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10916 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10917 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10918 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10919 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10920 | } | |
10921 | } else { | |
10922 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10923 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10924 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10925 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10926 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10927 | } | |
eb14cb74 | 10928 | |
2d112de7 ACO |
10929 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
10930 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
10931 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
10932 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
10933 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
10934 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 10935 | |
2d112de7 ACO |
10936 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
10937 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
10938 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
10939 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
10940 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
10941 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 10942 | |
c93f54cf | 10943 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10944 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10945 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10946 | IS_VALLEYVIEW(dev)) | |
10947 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 10948 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 10949 | |
9ed109a7 DV |
10950 | PIPE_CONF_CHECK_I(has_audio); |
10951 | ||
2d112de7 | 10952 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
10953 | DRM_MODE_FLAG_INTERLACE); |
10954 | ||
bb760063 | 10955 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 10956 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10957 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 10958 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10959 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 10960 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10961 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 10962 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
10963 | DRM_MODE_FLAG_NVSYNC); |
10964 | } | |
045ac3b5 | 10965 | |
37327abd VS |
10966 | PIPE_CONF_CHECK_I(pipe_src_w); |
10967 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10968 | |
9953599b DV |
10969 | /* |
10970 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10971 | * screen. Since we don't yet re-compute the pipe config when moving | |
10972 | * just the lvds port away to another pipe the sw tracking won't match. | |
10973 | * | |
10974 | * Proper atomic modesets with recomputed global state will fix this. | |
10975 | * Until then just don't check gmch state for inherited modes. | |
10976 | */ | |
10977 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10978 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10979 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10980 | if (INTEL_INFO(dev)->gen < 4) | |
10981 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10982 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10983 | } | |
10984 | ||
fd4daa9c CW |
10985 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10986 | if (current_config->pch_pfit.enabled) { | |
10987 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10988 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10989 | } | |
2fa2fe9a | 10990 | |
e59150dc JB |
10991 | /* BDW+ don't expose a synchronous way to read the state */ |
10992 | if (IS_HASWELL(dev)) | |
10993 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10994 | |
282740f7 VS |
10995 | PIPE_CONF_CHECK_I(double_wide); |
10996 | ||
26804afd DV |
10997 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10998 | ||
c0d43d62 | 10999 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11000 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11001 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11002 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11003 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11004 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11005 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11006 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11007 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11008 | |
42571aef VS |
11009 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11010 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11011 | ||
2d112de7 | 11012 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11013 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11014 | |
66e985c0 | 11015 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11016 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11017 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11018 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11019 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11020 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11021 | |
0e8ffe1b DV |
11022 | return true; |
11023 | } | |
11024 | ||
08db6652 DL |
11025 | static void check_wm_state(struct drm_device *dev) |
11026 | { | |
11027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11028 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11029 | struct intel_crtc *intel_crtc; | |
11030 | int plane; | |
11031 | ||
11032 | if (INTEL_INFO(dev)->gen < 9) | |
11033 | return; | |
11034 | ||
11035 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11036 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11037 | ||
11038 | for_each_intel_crtc(dev, intel_crtc) { | |
11039 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11040 | const enum pipe pipe = intel_crtc->pipe; | |
11041 | ||
11042 | if (!intel_crtc->active) | |
11043 | continue; | |
11044 | ||
11045 | /* planes */ | |
dd740780 | 11046 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11047 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11048 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11049 | ||
11050 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11051 | continue; | |
11052 | ||
11053 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11054 | "(expected (%u,%u), found (%u,%u))\n", | |
11055 | pipe_name(pipe), plane + 1, | |
11056 | sw_entry->start, sw_entry->end, | |
11057 | hw_entry->start, hw_entry->end); | |
11058 | } | |
11059 | ||
11060 | /* cursor */ | |
11061 | hw_entry = &hw_ddb.cursor[pipe]; | |
11062 | sw_entry = &sw_ddb->cursor[pipe]; | |
11063 | ||
11064 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11065 | continue; | |
11066 | ||
11067 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11068 | "(expected (%u,%u), found (%u,%u))\n", | |
11069 | pipe_name(pipe), | |
11070 | sw_entry->start, sw_entry->end, | |
11071 | hw_entry->start, hw_entry->end); | |
11072 | } | |
11073 | } | |
11074 | ||
91d1b4bd DV |
11075 | static void |
11076 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11077 | { |
8af6cf88 DV |
11078 | struct intel_connector *connector; |
11079 | ||
3a3371ff | 11080 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11081 | /* This also checks the encoder/connector hw state with the |
11082 | * ->get_hw_state callbacks. */ | |
11083 | intel_connector_check_state(connector); | |
11084 | ||
e2c719b7 | 11085 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11086 | "connector's staged encoder doesn't match current encoder\n"); |
11087 | } | |
91d1b4bd DV |
11088 | } |
11089 | ||
11090 | static void | |
11091 | check_encoder_state(struct drm_device *dev) | |
11092 | { | |
11093 | struct intel_encoder *encoder; | |
11094 | struct intel_connector *connector; | |
8af6cf88 | 11095 | |
b2784e15 | 11096 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11097 | bool enabled = false; |
11098 | bool active = false; | |
11099 | enum pipe pipe, tracked_pipe; | |
11100 | ||
11101 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11102 | encoder->base.base.id, | |
8e329a03 | 11103 | encoder->base.name); |
8af6cf88 | 11104 | |
e2c719b7 | 11105 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11106 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11107 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11108 | "encoder's active_connectors set, but no crtc\n"); |
11109 | ||
3a3371ff | 11110 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11111 | if (connector->base.encoder != &encoder->base) |
11112 | continue; | |
11113 | enabled = true; | |
11114 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11115 | active = true; | |
11116 | } | |
0e32b39c DA |
11117 | /* |
11118 | * for MST connectors if we unplug the connector is gone | |
11119 | * away but the encoder is still connected to a crtc | |
11120 | * until a modeset happens in response to the hotplug. | |
11121 | */ | |
11122 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11123 | continue; | |
11124 | ||
e2c719b7 | 11125 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11126 | "encoder's enabled state mismatch " |
11127 | "(expected %i, found %i)\n", | |
11128 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11129 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11130 | "active encoder with no crtc\n"); |
11131 | ||
e2c719b7 | 11132 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11133 | "encoder's computed active state doesn't match tracked active state " |
11134 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11135 | ||
11136 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11137 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11138 | "encoder's hw state doesn't match sw tracking " |
11139 | "(expected %i, found %i)\n", | |
11140 | encoder->connectors_active, active); | |
11141 | ||
11142 | if (!encoder->base.crtc) | |
11143 | continue; | |
11144 | ||
11145 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11146 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11147 | "active encoder's pipe doesn't match" |
11148 | "(expected %i, found %i)\n", | |
11149 | tracked_pipe, pipe); | |
11150 | ||
11151 | } | |
91d1b4bd DV |
11152 | } |
11153 | ||
11154 | static void | |
11155 | check_crtc_state(struct drm_device *dev) | |
11156 | { | |
fbee40df | 11157 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11158 | struct intel_crtc *crtc; |
11159 | struct intel_encoder *encoder; | |
5cec258b | 11160 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11161 | |
d3fcc808 | 11162 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11163 | bool enabled = false; |
11164 | bool active = false; | |
11165 | ||
045ac3b5 JB |
11166 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11167 | ||
8af6cf88 DV |
11168 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
11169 | crtc->base.base.id); | |
11170 | ||
83d65738 | 11171 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
11172 | "active crtc, but not enabled in sw tracking\n"); |
11173 | ||
b2784e15 | 11174 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11175 | if (encoder->base.crtc != &crtc->base) |
11176 | continue; | |
11177 | enabled = true; | |
11178 | if (encoder->connectors_active) | |
11179 | active = true; | |
11180 | } | |
6c49f241 | 11181 | |
e2c719b7 | 11182 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
11183 | "crtc's computed active state doesn't match tracked active state " |
11184 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 11185 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 11186 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
11187 | "(expected %i, found %i)\n", enabled, |
11188 | crtc->base.state->enable); | |
8af6cf88 | 11189 | |
0e8ffe1b DV |
11190 | active = dev_priv->display.get_pipe_config(crtc, |
11191 | &pipe_config); | |
d62cf62a | 11192 | |
b6b5d049 VS |
11193 | /* hw state is inconsistent with the pipe quirk */ |
11194 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11195 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
11196 | active = crtc->active; |
11197 | ||
b2784e15 | 11198 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 11199 | enum pipe pipe; |
6c49f241 DV |
11200 | if (encoder->base.crtc != &crtc->base) |
11201 | continue; | |
1d37b689 | 11202 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
11203 | encoder->get_config(encoder, &pipe_config); |
11204 | } | |
11205 | ||
e2c719b7 | 11206 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
11207 | "crtc active state doesn't match with hw state " |
11208 | "(expected %i, found %i)\n", crtc->active, active); | |
11209 | ||
c0b03411 | 11210 | if (active && |
6e3c9717 | 11211 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 11212 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
11213 | intel_dump_pipe_config(crtc, &pipe_config, |
11214 | "[hw state]"); | |
6e3c9717 | 11215 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
11216 | "[sw state]"); |
11217 | } | |
8af6cf88 DV |
11218 | } |
11219 | } | |
11220 | ||
91d1b4bd DV |
11221 | static void |
11222 | check_shared_dpll_state(struct drm_device *dev) | |
11223 | { | |
fbee40df | 11224 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11225 | struct intel_crtc *crtc; |
11226 | struct intel_dpll_hw_state dpll_hw_state; | |
11227 | int i; | |
5358901f DV |
11228 | |
11229 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
11230 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11231 | int enabled_crtcs = 0, active_crtcs = 0; | |
11232 | bool active; | |
11233 | ||
11234 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
11235 | ||
11236 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11237 | ||
11238 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
11239 | ||
e2c719b7 | 11240 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 11241 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 11242 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 11243 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 11244 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 11245 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 11246 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 11247 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
11248 | "pll on state mismatch (expected %i, found %i)\n", |
11249 | pll->on, active); | |
11250 | ||
d3fcc808 | 11251 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11252 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
11253 | enabled_crtcs++; |
11254 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11255 | active_crtcs++; | |
11256 | } | |
e2c719b7 | 11257 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
11258 | "pll active crtcs mismatch (expected %i, found %i)\n", |
11259 | pll->active, active_crtcs); | |
e2c719b7 | 11260 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 11261 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 11262 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 11263 | |
e2c719b7 | 11264 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
11265 | sizeof(dpll_hw_state)), |
11266 | "pll hw state mismatch\n"); | |
5358901f | 11267 | } |
8af6cf88 DV |
11268 | } |
11269 | ||
91d1b4bd DV |
11270 | void |
11271 | intel_modeset_check_state(struct drm_device *dev) | |
11272 | { | |
08db6652 | 11273 | check_wm_state(dev); |
91d1b4bd DV |
11274 | check_connector_state(dev); |
11275 | check_encoder_state(dev); | |
11276 | check_crtc_state(dev); | |
11277 | check_shared_dpll_state(dev); | |
11278 | } | |
11279 | ||
5cec258b | 11280 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
11281 | int dotclock) |
11282 | { | |
11283 | /* | |
11284 | * FDI already provided one idea for the dotclock. | |
11285 | * Yell if the encoder disagrees. | |
11286 | */ | |
2d112de7 | 11287 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11288 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 11289 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
11290 | } |
11291 | ||
80715b2f VS |
11292 | static void update_scanline_offset(struct intel_crtc *crtc) |
11293 | { | |
11294 | struct drm_device *dev = crtc->base.dev; | |
11295 | ||
11296 | /* | |
11297 | * The scanline counter increments at the leading edge of hsync. | |
11298 | * | |
11299 | * On most platforms it starts counting from vtotal-1 on the | |
11300 | * first active line. That means the scanline counter value is | |
11301 | * always one less than what we would expect. Ie. just after | |
11302 | * start of vblank, which also occurs at start of hsync (on the | |
11303 | * last active line), the scanline counter will read vblank_start-1. | |
11304 | * | |
11305 | * On gen2 the scanline counter starts counting from 1 instead | |
11306 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11307 | * to keep the value positive), instead of adding one. | |
11308 | * | |
11309 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11310 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11311 | * there's an extra 1 line difference. So we need to add two instead of | |
11312 | * one to the value. | |
11313 | */ | |
11314 | if (IS_GEN2(dev)) { | |
6e3c9717 | 11315 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11316 | int vtotal; |
11317 | ||
11318 | vtotal = mode->crtc_vtotal; | |
11319 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
11320 | vtotal /= 2; | |
11321 | ||
11322 | crtc->scanline_offset = vtotal - 1; | |
11323 | } else if (HAS_DDI(dev) && | |
409ee761 | 11324 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11325 | crtc->scanline_offset = 2; |
11326 | } else | |
11327 | crtc->scanline_offset = 1; | |
11328 | } | |
11329 | ||
5cec258b | 11330 | static struct intel_crtc_state * |
7f27126e JB |
11331 | intel_modeset_compute_config(struct drm_crtc *crtc, |
11332 | struct drm_display_mode *mode, | |
11333 | struct drm_framebuffer *fb, | |
83a57153 | 11334 | struct drm_atomic_state *state, |
7f27126e JB |
11335 | unsigned *modeset_pipes, |
11336 | unsigned *prepare_pipes, | |
11337 | unsigned *disable_pipes) | |
11338 | { | |
db7542dd | 11339 | struct drm_device *dev = crtc->dev; |
5cec258b | 11340 | struct intel_crtc_state *pipe_config = NULL; |
db7542dd | 11341 | struct intel_crtc *intel_crtc; |
7f27126e JB |
11342 | |
11343 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
11344 | prepare_pipes, disable_pipes); | |
11345 | ||
db7542dd ACO |
11346 | for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { |
11347 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11348 | if (IS_ERR(pipe_config)) | |
11349 | return pipe_config; | |
11350 | ||
11351 | pipe_config->base.enable = false; | |
11352 | } | |
7f27126e JB |
11353 | |
11354 | /* | |
11355 | * Note this needs changes when we start tracking multiple modes | |
11356 | * and crtcs. At that point we'll need to compute the whole config | |
11357 | * (i.e. one pipe_config for each crtc) rather than just the one | |
11358 | * for this crtc. | |
11359 | */ | |
db7542dd ACO |
11360 | for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { |
11361 | /* FIXME: For now we still expect modeset_pipes has at most | |
11362 | * one bit set. */ | |
11363 | if (WARN_ON(&intel_crtc->base != crtc)) | |
11364 | continue; | |
83a57153 | 11365 | |
db7542dd ACO |
11366 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); |
11367 | if (IS_ERR(pipe_config)) | |
11368 | return pipe_config; | |
7f27126e | 11369 | |
db7542dd ACO |
11370 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
11371 | "[modeset]"); | |
11372 | } | |
11373 | ||
11374 | return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; | |
7f27126e JB |
11375 | } |
11376 | ||
ed6739ef ACO |
11377 | static int __intel_set_mode_setup_plls(struct drm_device *dev, |
11378 | unsigned modeset_pipes, | |
11379 | unsigned disable_pipes) | |
11380 | { | |
11381 | struct drm_i915_private *dev_priv = to_i915(dev); | |
11382 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
11383 | struct intel_crtc *intel_crtc; | |
11384 | int ret = 0; | |
11385 | ||
11386 | if (!dev_priv->display.crtc_compute_clock) | |
11387 | return 0; | |
11388 | ||
11389 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
11390 | if (ret) | |
11391 | goto done; | |
11392 | ||
11393 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
11394 | struct intel_crtc_state *state = intel_crtc->new_config; | |
11395 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11396 | state); | |
11397 | if (ret) { | |
11398 | intel_shared_dpll_abort_config(dev_priv); | |
11399 | goto done; | |
11400 | } | |
11401 | } | |
11402 | ||
11403 | done: | |
11404 | return ret; | |
11405 | } | |
11406 | ||
f30da187 DV |
11407 | static int __intel_set_mode(struct drm_crtc *crtc, |
11408 | struct drm_display_mode *mode, | |
7f27126e | 11409 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 11410 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11411 | unsigned modeset_pipes, |
11412 | unsigned prepare_pipes, | |
11413 | unsigned disable_pipes) | |
a6778b3c DV |
11414 | { |
11415 | struct drm_device *dev = crtc->dev; | |
fbee40df | 11416 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 11417 | struct drm_display_mode *saved_mode; |
83a57153 | 11418 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 11419 | struct intel_crtc *intel_crtc; |
c0c36b94 | 11420 | int ret = 0; |
a6778b3c | 11421 | |
4b4b9238 | 11422 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
11423 | if (!saved_mode) |
11424 | return -ENOMEM; | |
a6778b3c | 11425 | |
83a57153 ACO |
11426 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
11427 | if (!crtc_state_copy) { | |
11428 | ret = -ENOMEM; | |
11429 | goto done; | |
11430 | } | |
11431 | ||
3ac18232 | 11432 | *saved_mode = crtc->mode; |
a6778b3c | 11433 | |
b9950a13 VS |
11434 | if (modeset_pipes) |
11435 | to_intel_crtc(crtc)->new_config = pipe_config; | |
11436 | ||
30a970c6 JB |
11437 | /* |
11438 | * See if the config requires any additional preparation, e.g. | |
11439 | * to adjust global state with pipes off. We need to do this | |
11440 | * here so we can get the modeset_pipe updated config for the new | |
11441 | * mode set on this crtc. For other crtcs we need to use the | |
11442 | * adjusted_mode bits in the crtc directly. | |
11443 | */ | |
c164f833 | 11444 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 11445 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 11446 | |
c164f833 VS |
11447 | /* may have added more to prepare_pipes than we should */ |
11448 | prepare_pipes &= ~disable_pipes; | |
11449 | } | |
11450 | ||
ed6739ef ACO |
11451 | ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes); |
11452 | if (ret) | |
11453 | goto done; | |
8bd31e67 | 11454 | |
460da916 DV |
11455 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
11456 | intel_crtc_disable(&intel_crtc->base); | |
11457 | ||
ea9d758d | 11458 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 11459 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
11460 | dev_priv->display.crtc_disable(&intel_crtc->base); |
11461 | } | |
a6778b3c | 11462 | |
6c4c86f5 DV |
11463 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
11464 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
11465 | * |
11466 | * Note we'll need to fix this up when we start tracking multiple | |
11467 | * pipes; here we assume a single modeset_pipe and only track the | |
11468 | * single crtc and mode. | |
f6e5b160 | 11469 | */ |
b8cecdf5 | 11470 | if (modeset_pipes) { |
25c5b266 | 11471 | crtc->mode = *mode; |
b8cecdf5 DV |
11472 | /* mode_set/enable/disable functions rely on a correct pipe |
11473 | * config. */ | |
f5de6e07 | 11474 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
11475 | |
11476 | /* | |
11477 | * Calculate and store various constants which | |
11478 | * are later needed by vblank and swap-completion | |
11479 | * timestamping. They are derived from true hwmode. | |
11480 | */ | |
11481 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 11482 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 11483 | } |
7758a113 | 11484 | |
ea9d758d DV |
11485 | /* Only after disabling all output pipelines that will be changed can we |
11486 | * update the the output configuration. */ | |
11487 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11488 | |
50f6e502 | 11489 | modeset_update_crtc_power_domains(dev); |
47fab737 | 11490 | |
a6778b3c DV |
11491 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11492 | * on the DPLL. | |
f6e5b160 | 11493 | */ |
25c5b266 | 11494 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11495 | struct drm_plane *primary = intel_crtc->base.primary; |
11496 | int vdisplay, hdisplay; | |
4c10794f | 11497 | |
455a6808 GP |
11498 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
11499 | ret = primary->funcs->update_plane(primary, &intel_crtc->base, | |
11500 | fb, 0, 0, | |
11501 | hdisplay, vdisplay, | |
11502 | x << 16, y << 16, | |
11503 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11504 | } |
11505 | ||
11506 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11507 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11508 | update_scanline_offset(intel_crtc); | |
11509 | ||
25c5b266 | 11510 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11511 | } |
a6778b3c | 11512 | |
a6778b3c DV |
11513 | /* FIXME: add subpixel order */ |
11514 | done: | |
83d65738 | 11515 | if (ret && crtc->state->enable) |
3ac18232 | 11516 | crtc->mode = *saved_mode; |
a6778b3c | 11517 | |
83a57153 ACO |
11518 | if (ret == 0 && pipe_config) { |
11519 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11520 | ||
11521 | /* The pipe_config will be freed with the atomic state, so | |
11522 | * make a copy. */ | |
11523 | memcpy(crtc_state_copy, intel_crtc->config, | |
11524 | sizeof *crtc_state_copy); | |
11525 | intel_crtc->config = crtc_state_copy; | |
11526 | intel_crtc->base.state = &crtc_state_copy->base; | |
11527 | ||
11528 | if (modeset_pipes) | |
11529 | intel_crtc->new_config = intel_crtc->config; | |
11530 | } else { | |
11531 | kfree(crtc_state_copy); | |
11532 | } | |
11533 | ||
3ac18232 | 11534 | kfree(saved_mode); |
a6778b3c | 11535 | return ret; |
f6e5b160 CW |
11536 | } |
11537 | ||
7f27126e JB |
11538 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11539 | struct drm_display_mode *mode, | |
11540 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 11541 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11542 | unsigned modeset_pipes, |
11543 | unsigned prepare_pipes, | |
11544 | unsigned disable_pipes) | |
f30da187 DV |
11545 | { |
11546 | int ret; | |
11547 | ||
7f27126e JB |
11548 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11549 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11550 | |
11551 | if (ret == 0) | |
11552 | intel_modeset_check_state(crtc->dev); | |
11553 | ||
11554 | return ret; | |
11555 | } | |
11556 | ||
7f27126e JB |
11557 | static int intel_set_mode(struct drm_crtc *crtc, |
11558 | struct drm_display_mode *mode, | |
83a57153 ACO |
11559 | int x, int y, struct drm_framebuffer *fb, |
11560 | struct drm_atomic_state *state) | |
7f27126e | 11561 | { |
5cec258b | 11562 | struct intel_crtc_state *pipe_config; |
7f27126e | 11563 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 11564 | int ret = 0; |
7f27126e | 11565 | |
83a57153 | 11566 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, |
7f27126e JB |
11567 | &modeset_pipes, |
11568 | &prepare_pipes, | |
11569 | &disable_pipes); | |
11570 | ||
83a57153 ACO |
11571 | if (IS_ERR(pipe_config)) { |
11572 | ret = PTR_ERR(pipe_config); | |
11573 | goto out; | |
11574 | } | |
11575 | ||
11576 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11577 | modeset_pipes, prepare_pipes, | |
11578 | disable_pipes); | |
11579 | if (ret) | |
11580 | goto out; | |
7f27126e | 11581 | |
83a57153 ACO |
11582 | out: |
11583 | return ret; | |
7f27126e JB |
11584 | } |
11585 | ||
c0c36b94 CW |
11586 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11587 | { | |
83a57153 ACO |
11588 | struct drm_device *dev = crtc->dev; |
11589 | struct drm_atomic_state *state; | |
11590 | struct intel_encoder *encoder; | |
11591 | struct intel_connector *connector; | |
11592 | struct drm_connector_state *connector_state; | |
11593 | ||
11594 | state = drm_atomic_state_alloc(dev); | |
11595 | if (!state) { | |
11596 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
11597 | crtc->base.id); | |
11598 | return; | |
11599 | } | |
11600 | ||
11601 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
11602 | ||
11603 | /* The force restore path in the HW readout code relies on the staged | |
11604 | * config still keeping the user requested config while the actual | |
11605 | * state has been overwritten by the configuration read from HW. We | |
11606 | * need to copy the staged config to the atomic state, otherwise the | |
11607 | * mode set will just reapply the state the HW is already in. */ | |
11608 | for_each_intel_encoder(dev, encoder) { | |
11609 | if (&encoder->new_crtc->base != crtc) | |
11610 | continue; | |
11611 | ||
11612 | for_each_intel_connector(dev, connector) { | |
11613 | if (connector->new_encoder != encoder) | |
11614 | continue; | |
11615 | ||
11616 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
11617 | if (IS_ERR(connector_state)) { | |
11618 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
11619 | connector->base.base.id, | |
11620 | connector->base.name, | |
11621 | PTR_ERR(connector_state)); | |
11622 | continue; | |
11623 | } | |
11624 | ||
11625 | connector_state->crtc = crtc; | |
11626 | connector_state->best_encoder = &encoder->base; | |
11627 | } | |
11628 | } | |
11629 | ||
11630 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, | |
11631 | state); | |
11632 | ||
11633 | drm_atomic_state_free(state); | |
c0c36b94 CW |
11634 | } |
11635 | ||
25c5b266 DV |
11636 | #undef for_each_intel_crtc_masked |
11637 | ||
d9e55608 DV |
11638 | static void intel_set_config_free(struct intel_set_config *config) |
11639 | { | |
11640 | if (!config) | |
11641 | return; | |
11642 | ||
1aa4b628 DV |
11643 | kfree(config->save_connector_encoders); |
11644 | kfree(config->save_encoder_crtcs); | |
7668851f | 11645 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11646 | kfree(config); |
11647 | } | |
11648 | ||
85f9eb71 DV |
11649 | static int intel_set_config_save_state(struct drm_device *dev, |
11650 | struct intel_set_config *config) | |
11651 | { | |
7668851f | 11652 | struct drm_crtc *crtc; |
85f9eb71 DV |
11653 | struct drm_encoder *encoder; |
11654 | struct drm_connector *connector; | |
11655 | int count; | |
11656 | ||
7668851f VS |
11657 | config->save_crtc_enabled = |
11658 | kcalloc(dev->mode_config.num_crtc, | |
11659 | sizeof(bool), GFP_KERNEL); | |
11660 | if (!config->save_crtc_enabled) | |
11661 | return -ENOMEM; | |
11662 | ||
1aa4b628 DV |
11663 | config->save_encoder_crtcs = |
11664 | kcalloc(dev->mode_config.num_encoder, | |
11665 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11666 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11667 | return -ENOMEM; |
11668 | ||
1aa4b628 DV |
11669 | config->save_connector_encoders = |
11670 | kcalloc(dev->mode_config.num_connector, | |
11671 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11672 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11673 | return -ENOMEM; |
11674 | ||
11675 | /* Copy data. Note that driver private data is not affected. | |
11676 | * Should anything bad happen only the expected state is | |
11677 | * restored, not the drivers personal bookkeeping. | |
11678 | */ | |
7668851f | 11679 | count = 0; |
70e1e0ec | 11680 | for_each_crtc(dev, crtc) { |
83d65738 | 11681 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
11682 | } |
11683 | ||
85f9eb71 DV |
11684 | count = 0; |
11685 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11686 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11687 | } |
11688 | ||
11689 | count = 0; | |
11690 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11691 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11692 | } |
11693 | ||
11694 | return 0; | |
11695 | } | |
11696 | ||
11697 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11698 | struct intel_set_config *config) | |
11699 | { | |
7668851f | 11700 | struct intel_crtc *crtc; |
9a935856 DV |
11701 | struct intel_encoder *encoder; |
11702 | struct intel_connector *connector; | |
85f9eb71 DV |
11703 | int count; |
11704 | ||
7668851f | 11705 | count = 0; |
d3fcc808 | 11706 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11707 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11708 | |
11709 | if (crtc->new_enabled) | |
6e3c9717 | 11710 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11711 | else |
11712 | crtc->new_config = NULL; | |
7668851f VS |
11713 | } |
11714 | ||
85f9eb71 | 11715 | count = 0; |
b2784e15 | 11716 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11717 | encoder->new_crtc = |
11718 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11719 | } |
11720 | ||
11721 | count = 0; | |
3a3371ff | 11722 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11723 | connector->new_encoder = |
11724 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11725 | } |
11726 | } | |
11727 | ||
e3de42b6 | 11728 | static bool |
2e57f47d | 11729 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11730 | { |
11731 | int i; | |
11732 | ||
2e57f47d CW |
11733 | if (set->num_connectors == 0) |
11734 | return false; | |
11735 | ||
11736 | if (WARN_ON(set->connectors == NULL)) | |
11737 | return false; | |
11738 | ||
11739 | for (i = 0; i < set->num_connectors; i++) | |
11740 | if (set->connectors[i]->encoder && | |
11741 | set->connectors[i]->encoder->crtc == set->crtc && | |
11742 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11743 | return true; |
11744 | ||
11745 | return false; | |
11746 | } | |
11747 | ||
5e2b584e DV |
11748 | static void |
11749 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11750 | struct intel_set_config *config) | |
11751 | { | |
11752 | ||
11753 | /* We should be able to check here if the fb has the same properties | |
11754 | * and then just flip_or_move it */ | |
2e57f47d CW |
11755 | if (is_crtc_connector_off(set)) { |
11756 | config->mode_changed = true; | |
f4510a27 | 11757 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11758 | /* |
11759 | * If we have no fb, we can only flip as long as the crtc is | |
11760 | * active, otherwise we need a full mode set. The crtc may | |
11761 | * be active if we've only disabled the primary plane, or | |
11762 | * in fastboot situations. | |
11763 | */ | |
f4510a27 | 11764 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11765 | struct intel_crtc *intel_crtc = |
11766 | to_intel_crtc(set->crtc); | |
11767 | ||
3b150f08 | 11768 | if (intel_crtc->active) { |
319d9827 JB |
11769 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11770 | config->fb_changed = true; | |
11771 | } else { | |
11772 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11773 | config->mode_changed = true; | |
11774 | } | |
5e2b584e DV |
11775 | } else if (set->fb == NULL) { |
11776 | config->mode_changed = true; | |
72f4901e | 11777 | } else if (set->fb->pixel_format != |
f4510a27 | 11778 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11779 | config->mode_changed = true; |
e3de42b6 | 11780 | } else { |
5e2b584e | 11781 | config->fb_changed = true; |
e3de42b6 | 11782 | } |
5e2b584e DV |
11783 | } |
11784 | ||
835c5873 | 11785 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11786 | config->fb_changed = true; |
11787 | ||
11788 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11789 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11790 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11791 | drm_mode_debug_printmodeline(set->mode); | |
11792 | config->mode_changed = true; | |
11793 | } | |
a1d95703 CW |
11794 | |
11795 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11796 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11797 | } |
11798 | ||
2e431051 | 11799 | static int |
9a935856 DV |
11800 | intel_modeset_stage_output_state(struct drm_device *dev, |
11801 | struct drm_mode_set *set, | |
944b0c76 ACO |
11802 | struct intel_set_config *config, |
11803 | struct drm_atomic_state *state) | |
50f56119 | 11804 | { |
9a935856 | 11805 | struct intel_connector *connector; |
944b0c76 | 11806 | struct drm_connector_state *connector_state; |
9a935856 | 11807 | struct intel_encoder *encoder; |
7668851f | 11808 | struct intel_crtc *crtc; |
f3f08572 | 11809 | int ro; |
50f56119 | 11810 | |
9abdda74 | 11811 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11812 | * of connectors. For paranoia, double-check this. */ |
11813 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11814 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11815 | ||
3a3371ff | 11816 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11817 | /* Otherwise traverse passed in connector list and get encoders |
11818 | * for them. */ | |
50f56119 | 11819 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11820 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11821 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11822 | break; |
11823 | } | |
11824 | } | |
11825 | ||
9a935856 DV |
11826 | /* If we disable the crtc, disable all its connectors. Also, if |
11827 | * the connector is on the changing crtc but not on the new | |
11828 | * connector list, disable it. */ | |
11829 | if ((!set->fb || ro == set->num_connectors) && | |
11830 | connector->base.encoder && | |
11831 | connector->base.encoder->crtc == set->crtc) { | |
11832 | connector->new_encoder = NULL; | |
11833 | ||
11834 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11835 | connector->base.base.id, | |
c23cc417 | 11836 | connector->base.name); |
9a935856 DV |
11837 | } |
11838 | ||
11839 | ||
11840 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
11841 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
11842 | connector->base.base.id, | |
11843 | connector->base.name); | |
5e2b584e | 11844 | config->mode_changed = true; |
50f56119 DV |
11845 | } |
11846 | } | |
9a935856 | 11847 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11848 | |
9a935856 | 11849 | /* Update crtc of enabled connectors. */ |
3a3371ff | 11850 | for_each_intel_connector(dev, connector) { |
7668851f VS |
11851 | struct drm_crtc *new_crtc; |
11852 | ||
9a935856 | 11853 | if (!connector->new_encoder) |
50f56119 DV |
11854 | continue; |
11855 | ||
9a935856 | 11856 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11857 | |
11858 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11859 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11860 | new_crtc = set->crtc; |
11861 | } | |
11862 | ||
11863 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11864 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11865 | new_crtc)) { | |
5e2b584e | 11866 | return -EINVAL; |
50f56119 | 11867 | } |
0e32b39c | 11868 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 11869 | |
944b0c76 ACO |
11870 | connector_state = |
11871 | drm_atomic_get_connector_state(state, &connector->base); | |
11872 | if (IS_ERR(connector_state)) | |
11873 | return PTR_ERR(connector_state); | |
11874 | ||
11875 | connector_state->crtc = new_crtc; | |
11876 | connector_state->best_encoder = &connector->new_encoder->base; | |
11877 | ||
9a935856 DV |
11878 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
11879 | connector->base.base.id, | |
c23cc417 | 11880 | connector->base.name, |
9a935856 DV |
11881 | new_crtc->base.id); |
11882 | } | |
11883 | ||
11884 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11885 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11886 | int num_connectors = 0; |
3a3371ff | 11887 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11888 | if (connector->new_encoder == encoder) { |
11889 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11890 | num_connectors++; |
9a935856 DV |
11891 | } |
11892 | } | |
5a65f358 PZ |
11893 | |
11894 | if (num_connectors == 0) | |
11895 | encoder->new_crtc = NULL; | |
11896 | else if (num_connectors > 1) | |
11897 | return -EINVAL; | |
11898 | ||
9a935856 DV |
11899 | /* Only now check for crtc changes so we don't miss encoders |
11900 | * that will be disabled. */ | |
11901 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
11902 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
11903 | encoder->base.base.id, | |
11904 | encoder->base.name); | |
5e2b584e | 11905 | config->mode_changed = true; |
50f56119 DV |
11906 | } |
11907 | } | |
9a935856 | 11908 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 11909 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
11910 | connector_state = |
11911 | drm_atomic_get_connector_state(state, &connector->base); | |
11912 | ||
11913 | if (connector->new_encoder) { | |
0e32b39c DA |
11914 | if (connector->new_encoder != connector->encoder) |
11915 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
11916 | } else { |
11917 | connector_state->crtc = NULL; | |
11918 | } | |
0e32b39c | 11919 | } |
d3fcc808 | 11920 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11921 | crtc->new_enabled = false; |
11922 | ||
b2784e15 | 11923 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11924 | if (encoder->new_crtc == crtc) { |
11925 | crtc->new_enabled = true; | |
11926 | break; | |
11927 | } | |
11928 | } | |
11929 | ||
83d65738 | 11930 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
11931 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
11932 | crtc->base.base.id, | |
7668851f VS |
11933 | crtc->new_enabled ? "en" : "dis"); |
11934 | config->mode_changed = true; | |
11935 | } | |
7bd0a8e7 VS |
11936 | |
11937 | if (crtc->new_enabled) | |
6e3c9717 | 11938 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11939 | else |
11940 | crtc->new_config = NULL; | |
7668851f VS |
11941 | } |
11942 | ||
2e431051 DV |
11943 | return 0; |
11944 | } | |
11945 | ||
7d00a1f5 VS |
11946 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11947 | { | |
11948 | struct drm_device *dev = crtc->base.dev; | |
11949 | struct intel_encoder *encoder; | |
11950 | struct intel_connector *connector; | |
11951 | ||
11952 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11953 | pipe_name(crtc->pipe)); | |
11954 | ||
3a3371ff | 11955 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
11956 | if (connector->new_encoder && |
11957 | connector->new_encoder->new_crtc == crtc) | |
11958 | connector->new_encoder = NULL; | |
11959 | } | |
11960 | ||
b2784e15 | 11961 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11962 | if (encoder->new_crtc == crtc) |
11963 | encoder->new_crtc = NULL; | |
11964 | } | |
11965 | ||
11966 | crtc->new_enabled = false; | |
7bd0a8e7 | 11967 | crtc->new_config = NULL; |
7d00a1f5 VS |
11968 | } |
11969 | ||
2e431051 DV |
11970 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11971 | { | |
11972 | struct drm_device *dev; | |
2e431051 | 11973 | struct drm_mode_set save_set; |
83a57153 | 11974 | struct drm_atomic_state *state = NULL; |
2e431051 | 11975 | struct intel_set_config *config; |
5cec258b | 11976 | struct intel_crtc_state *pipe_config; |
50f52756 | 11977 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 11978 | int ret; |
2e431051 | 11979 | |
8d3e375e DV |
11980 | BUG_ON(!set); |
11981 | BUG_ON(!set->crtc); | |
11982 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11983 | |
7e53f3a4 DV |
11984 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11985 | BUG_ON(!set->mode && set->fb); | |
11986 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11987 | |
2e431051 DV |
11988 | if (set->fb) { |
11989 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11990 | set->crtc->base.id, set->fb->base.id, | |
11991 | (int)set->num_connectors, set->x, set->y); | |
11992 | } else { | |
11993 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11994 | } |
11995 | ||
11996 | dev = set->crtc->dev; | |
11997 | ||
11998 | ret = -ENOMEM; | |
11999 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12000 | if (!config) | |
12001 | goto out_config; | |
12002 | ||
12003 | ret = intel_set_config_save_state(dev, config); | |
12004 | if (ret) | |
12005 | goto out_config; | |
12006 | ||
12007 | save_set.crtc = set->crtc; | |
12008 | save_set.mode = &set->crtc->mode; | |
12009 | save_set.x = set->crtc->x; | |
12010 | save_set.y = set->crtc->y; | |
f4510a27 | 12011 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
12012 | |
12013 | /* Compute whether we need a full modeset, only an fb base update or no | |
12014 | * change at all. In the future we might also check whether only the | |
12015 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12016 | * such cases. */ | |
12017 | intel_set_config_compute_mode_changes(set, config); | |
12018 | ||
83a57153 ACO |
12019 | state = drm_atomic_state_alloc(dev); |
12020 | if (!state) { | |
12021 | ret = -ENOMEM; | |
12022 | goto out_config; | |
12023 | } | |
12024 | ||
12025 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12026 | ||
944b0c76 | 12027 | ret = intel_modeset_stage_output_state(dev, set, config, state); |
2e431051 DV |
12028 | if (ret) |
12029 | goto fail; | |
12030 | ||
50f52756 | 12031 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
83a57153 | 12032 | set->fb, state, |
50f52756 JB |
12033 | &modeset_pipes, |
12034 | &prepare_pipes, | |
12035 | &disable_pipes); | |
20664591 | 12036 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12037 | ret = PTR_ERR(pipe_config); |
50f52756 | 12038 | goto fail; |
20664591 | 12039 | } else if (pipe_config) { |
b9950a13 | 12040 | if (pipe_config->has_audio != |
6e3c9717 | 12041 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12042 | config->mode_changed = true; |
12043 | ||
af15d2ce JB |
12044 | /* |
12045 | * Note we have an issue here with infoframes: current code | |
12046 | * only updates them on the full mode set path per hw | |
12047 | * requirements. So here we should be checking for any | |
12048 | * required changes and forcing a mode set. | |
12049 | */ | |
20664591 | 12050 | } |
50f52756 | 12051 | |
1f9954d0 JB |
12052 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12053 | ||
5e2b584e | 12054 | if (config->mode_changed) { |
50f52756 JB |
12055 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12056 | set->x, set->y, set->fb, pipe_config, | |
12057 | modeset_pipes, prepare_pipes, | |
12058 | disable_pipes); | |
5e2b584e | 12059 | } else if (config->fb_changed) { |
3b150f08 | 12060 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
12061 | struct drm_plane *primary = set->crtc->primary; |
12062 | int vdisplay, hdisplay; | |
3b150f08 | 12063 | |
455a6808 GP |
12064 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
12065 | ret = primary->funcs->update_plane(primary, set->crtc, set->fb, | |
12066 | 0, 0, hdisplay, vdisplay, | |
12067 | set->x << 16, set->y << 16, | |
12068 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12069 | |
12070 | /* | |
12071 | * We need to make sure the primary plane is re-enabled if it | |
12072 | * has previously been turned off. | |
12073 | */ | |
12074 | if (!intel_crtc->primary_enabled && ret == 0) { | |
12075 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 12076 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
12077 | } |
12078 | ||
7ca51a3a JB |
12079 | /* |
12080 | * In the fastboot case this may be our only check of the | |
12081 | * state after boot. It would be better to only do it on | |
12082 | * the first update, but we don't have a nice way of doing that | |
12083 | * (and really, set_config isn't used much for high freq page | |
12084 | * flipping, so increasing its cost here shouldn't be a big | |
12085 | * deal). | |
12086 | */ | |
d330a953 | 12087 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12088 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12089 | } |
12090 | ||
2d05eae1 | 12091 | if (ret) { |
bf67dfeb DV |
12092 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12093 | set->crtc->base.id, ret); | |
50f56119 | 12094 | fail: |
2d05eae1 | 12095 | intel_set_config_restore_state(dev, config); |
50f56119 | 12096 | |
83a57153 ACO |
12097 | drm_atomic_state_clear(state); |
12098 | ||
7d00a1f5 VS |
12099 | /* |
12100 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12101 | * force the pipe off to avoid oopsing in the modeset code | |
12102 | * due to fb==NULL. This should only happen during boot since | |
12103 | * we don't yet reconstruct the FB from the hardware state. | |
12104 | */ | |
12105 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12106 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
12107 | ||
2d05eae1 CW |
12108 | /* Try to restore the config */ |
12109 | if (config->mode_changed && | |
12110 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
12111 | save_set.x, save_set.y, save_set.fb, |
12112 | state)) | |
2d05eae1 CW |
12113 | DRM_ERROR("failed to restore config after modeset failure\n"); |
12114 | } | |
50f56119 | 12115 | |
d9e55608 | 12116 | out_config: |
83a57153 ACO |
12117 | if (state) |
12118 | drm_atomic_state_free(state); | |
12119 | ||
d9e55608 | 12120 | intel_set_config_free(config); |
50f56119 DV |
12121 | return ret; |
12122 | } | |
f6e5b160 CW |
12123 | |
12124 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12125 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12126 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12127 | .destroy = intel_crtc_destroy, |
12128 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12129 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12130 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12131 | }; |
12132 | ||
5358901f DV |
12133 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12134 | struct intel_shared_dpll *pll, | |
12135 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12136 | { |
5358901f | 12137 | uint32_t val; |
ee7b9f93 | 12138 | |
f458ebbc | 12139 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12140 | return false; |
12141 | ||
5358901f | 12142 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12143 | hw_state->dpll = val; |
12144 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12145 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12146 | |
12147 | return val & DPLL_VCO_ENABLE; | |
12148 | } | |
12149 | ||
15bdd4cf DV |
12150 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12151 | struct intel_shared_dpll *pll) | |
12152 | { | |
3e369b76 ACO |
12153 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12154 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12155 | } |
12156 | ||
e7b903d2 DV |
12157 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12158 | struct intel_shared_dpll *pll) | |
12159 | { | |
e7b903d2 | 12160 | /* PCH refclock must be enabled first */ |
89eff4be | 12161 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12162 | |
3e369b76 | 12163 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12164 | |
12165 | /* Wait for the clocks to stabilize. */ | |
12166 | POSTING_READ(PCH_DPLL(pll->id)); | |
12167 | udelay(150); | |
12168 | ||
12169 | /* The pixel multiplier can only be updated once the | |
12170 | * DPLL is enabled and the clocks are stable. | |
12171 | * | |
12172 | * So write it again. | |
12173 | */ | |
3e369b76 | 12174 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12175 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12176 | udelay(200); |
12177 | } | |
12178 | ||
12179 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12180 | struct intel_shared_dpll *pll) | |
12181 | { | |
12182 | struct drm_device *dev = dev_priv->dev; | |
12183 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12184 | |
12185 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12186 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12187 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12188 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12189 | } |
12190 | ||
15bdd4cf DV |
12191 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12192 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12193 | udelay(200); |
12194 | } | |
12195 | ||
46edb027 DV |
12196 | static char *ibx_pch_dpll_names[] = { |
12197 | "PCH DPLL A", | |
12198 | "PCH DPLL B", | |
12199 | }; | |
12200 | ||
7c74ade1 | 12201 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12202 | { |
e7b903d2 | 12203 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12204 | int i; |
12205 | ||
7c74ade1 | 12206 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12207 | |
e72f9fbf | 12208 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12209 | dev_priv->shared_dplls[i].id = i; |
12210 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12211 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12212 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12213 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12214 | dev_priv->shared_dplls[i].get_hw_state = |
12215 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12216 | } |
12217 | } | |
12218 | ||
7c74ade1 DV |
12219 | static void intel_shared_dpll_init(struct drm_device *dev) |
12220 | { | |
e7b903d2 | 12221 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12222 | |
9cd86933 DV |
12223 | if (HAS_DDI(dev)) |
12224 | intel_ddi_pll_init(dev); | |
12225 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12226 | ibx_pch_dpll_init(dev); |
12227 | else | |
12228 | dev_priv->num_shared_dpll = 0; | |
12229 | ||
12230 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12231 | } |
12232 | ||
1fc0a8f7 TU |
12233 | /** |
12234 | * intel_wm_need_update - Check whether watermarks need updating | |
12235 | * @plane: drm plane | |
12236 | * @state: new plane state | |
12237 | * | |
12238 | * Check current plane state versus the new one to determine whether | |
12239 | * watermarks need to be recalculated. | |
12240 | * | |
12241 | * Returns true or false. | |
12242 | */ | |
12243 | bool intel_wm_need_update(struct drm_plane *plane, | |
12244 | struct drm_plane_state *state) | |
12245 | { | |
12246 | /* Update watermarks on tiling changes. */ | |
12247 | if (!plane->state->fb || !state->fb || | |
12248 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
12249 | plane->state->rotation != state->rotation) | |
12250 | return true; | |
12251 | ||
12252 | return false; | |
12253 | } | |
12254 | ||
6beb8c23 MR |
12255 | /** |
12256 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12257 | * @plane: drm plane to prepare for | |
12258 | * @fb: framebuffer to prepare for presentation | |
12259 | * | |
12260 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12261 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12262 | * bits. Some older platforms need special physical address handling for | |
12263 | * cursor planes. | |
12264 | * | |
12265 | * Returns 0 on success, negative error code on failure. | |
12266 | */ | |
12267 | int | |
12268 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12269 | struct drm_framebuffer *fb, |
12270 | const struct drm_plane_state *new_state) | |
465c120c MR |
12271 | { |
12272 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
12273 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12274 | enum pipe pipe = intel_plane->pipe; | |
12275 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12276 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12277 | unsigned frontbuffer_bits = 0; | |
12278 | int ret = 0; | |
465c120c | 12279 | |
ea2c67bb | 12280 | if (!obj) |
465c120c MR |
12281 | return 0; |
12282 | ||
6beb8c23 MR |
12283 | switch (plane->type) { |
12284 | case DRM_PLANE_TYPE_PRIMARY: | |
12285 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12286 | break; | |
12287 | case DRM_PLANE_TYPE_CURSOR: | |
12288 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12289 | break; | |
12290 | case DRM_PLANE_TYPE_OVERLAY: | |
12291 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
12292 | break; | |
12293 | } | |
465c120c | 12294 | |
6beb8c23 | 12295 | mutex_lock(&dev->struct_mutex); |
465c120c | 12296 | |
6beb8c23 MR |
12297 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12298 | INTEL_INFO(dev)->cursor_needs_physical) { | |
12299 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
12300 | ret = i915_gem_object_attach_phys(obj, align); | |
12301 | if (ret) | |
12302 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12303 | } else { | |
82bc3b2d | 12304 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 12305 | } |
465c120c | 12306 | |
6beb8c23 MR |
12307 | if (ret == 0) |
12308 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 12309 | |
4c34574f | 12310 | mutex_unlock(&dev->struct_mutex); |
465c120c | 12311 | |
6beb8c23 MR |
12312 | return ret; |
12313 | } | |
12314 | ||
38f3ce3a MR |
12315 | /** |
12316 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12317 | * @plane: drm plane to clean up for | |
12318 | * @fb: old framebuffer that was on plane | |
12319 | * | |
12320 | * Cleans up a framebuffer that has just been removed from a plane. | |
12321 | */ | |
12322 | void | |
12323 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12324 | struct drm_framebuffer *fb, |
12325 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
12326 | { |
12327 | struct drm_device *dev = plane->dev; | |
12328 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12329 | ||
12330 | if (WARN_ON(!obj)) | |
12331 | return; | |
12332 | ||
12333 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
12334 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
12335 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 12336 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
12337 | mutex_unlock(&dev->struct_mutex); |
12338 | } | |
465c120c MR |
12339 | } |
12340 | ||
12341 | static int | |
3c692a41 GP |
12342 | intel_check_primary_plane(struct drm_plane *plane, |
12343 | struct intel_plane_state *state) | |
12344 | { | |
32b7eeec MR |
12345 | struct drm_device *dev = plane->dev; |
12346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 12347 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12348 | struct intel_crtc *intel_crtc; |
2b875c22 | 12349 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
12350 | struct drm_rect *dest = &state->dst; |
12351 | struct drm_rect *src = &state->src; | |
12352 | const struct drm_rect *clip = &state->clip; | |
465c120c MR |
12353 | int ret; |
12354 | ||
ea2c67bb MR |
12355 | crtc = crtc ? crtc : plane->crtc; |
12356 | intel_crtc = to_intel_crtc(crtc); | |
12357 | ||
c59cb179 MR |
12358 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
12359 | src, dest, clip, | |
12360 | DRM_PLANE_HELPER_NO_SCALING, | |
12361 | DRM_PLANE_HELPER_NO_SCALING, | |
12362 | false, true, &state->visible); | |
12363 | if (ret) | |
12364 | return ret; | |
465c120c | 12365 | |
32b7eeec MR |
12366 | if (intel_crtc->active) { |
12367 | intel_crtc->atomic.wait_for_flips = true; | |
12368 | ||
12369 | /* | |
12370 | * FBC does not work on some platforms for rotated | |
12371 | * planes, so disable it when rotation is not 0 and | |
12372 | * update it when rotation is set back to 0. | |
12373 | * | |
12374 | * FIXME: This is redundant with the fbc update done in | |
12375 | * the primary plane enable function except that that | |
12376 | * one is done too late. We eventually need to unify | |
12377 | * this. | |
12378 | */ | |
12379 | if (intel_crtc->primary_enabled && | |
12380 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 12381 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 12382 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
12383 | intel_crtc->atomic.disable_fbc = true; |
12384 | } | |
12385 | ||
12386 | if (state->visible) { | |
12387 | /* | |
12388 | * BDW signals flip done immediately if the plane | |
12389 | * is disabled, even if the plane enable is already | |
12390 | * armed to occur at the next vblank :( | |
12391 | */ | |
12392 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
12393 | intel_crtc->atomic.wait_vblank = true; | |
12394 | } | |
12395 | ||
12396 | intel_crtc->atomic.fb_bits |= | |
12397 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
12398 | ||
12399 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 12400 | |
1fc0a8f7 | 12401 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 12402 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
12403 | } |
12404 | ||
14af293f GP |
12405 | return 0; |
12406 | } | |
12407 | ||
12408 | static void | |
12409 | intel_commit_primary_plane(struct drm_plane *plane, | |
12410 | struct intel_plane_state *state) | |
12411 | { | |
2b875c22 MR |
12412 | struct drm_crtc *crtc = state->base.crtc; |
12413 | struct drm_framebuffer *fb = state->base.fb; | |
12414 | struct drm_device *dev = plane->dev; | |
14af293f | 12415 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 12416 | struct intel_crtc *intel_crtc; |
14af293f GP |
12417 | struct drm_rect *src = &state->src; |
12418 | ||
ea2c67bb MR |
12419 | crtc = crtc ? crtc : plane->crtc; |
12420 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
12421 | |
12422 | plane->fb = fb; | |
9dc806fc MR |
12423 | crtc->x = src->x1 >> 16; |
12424 | crtc->y = src->y1 >> 16; | |
ccc759dc | 12425 | |
ccc759dc | 12426 | if (intel_crtc->active) { |
ccc759dc | 12427 | if (state->visible) { |
ccc759dc GP |
12428 | /* FIXME: kill this fastboot hack */ |
12429 | intel_update_pipe_size(intel_crtc); | |
465c120c | 12430 | |
ccc759dc | 12431 | intel_crtc->primary_enabled = true; |
465c120c | 12432 | |
ccc759dc GP |
12433 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
12434 | crtc->x, crtc->y); | |
ccc759dc GP |
12435 | } else { |
12436 | /* | |
12437 | * If clipping results in a non-visible primary plane, | |
12438 | * we'll disable the primary plane. Note that this is | |
12439 | * a bit different than what happens if userspace | |
12440 | * explicitly disables the plane by passing fb=0 | |
12441 | * because plane->fb still gets set and pinned. | |
12442 | */ | |
12443 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 12444 | } |
ccc759dc | 12445 | } |
465c120c MR |
12446 | } |
12447 | ||
32b7eeec | 12448 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 12449 | { |
32b7eeec | 12450 | struct drm_device *dev = crtc->dev; |
140fd38d | 12451 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 12452 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
12453 | struct intel_plane *intel_plane; |
12454 | struct drm_plane *p; | |
12455 | unsigned fb_bits = 0; | |
12456 | ||
12457 | /* Track fb's for any planes being disabled */ | |
12458 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
12459 | intel_plane = to_intel_plane(p); | |
12460 | ||
12461 | if (intel_crtc->atomic.disabled_planes & | |
12462 | (1 << drm_plane_index(p))) { | |
12463 | switch (p->type) { | |
12464 | case DRM_PLANE_TYPE_PRIMARY: | |
12465 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
12466 | break; | |
12467 | case DRM_PLANE_TYPE_CURSOR: | |
12468 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
12469 | break; | |
12470 | case DRM_PLANE_TYPE_OVERLAY: | |
12471 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
12472 | break; | |
12473 | } | |
3c692a41 | 12474 | |
ea2c67bb MR |
12475 | mutex_lock(&dev->struct_mutex); |
12476 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
12477 | mutex_unlock(&dev->struct_mutex); | |
12478 | } | |
12479 | } | |
3c692a41 | 12480 | |
32b7eeec MR |
12481 | if (intel_crtc->atomic.wait_for_flips) |
12482 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 12483 | |
32b7eeec MR |
12484 | if (intel_crtc->atomic.disable_fbc) |
12485 | intel_fbc_disable(dev); | |
3c692a41 | 12486 | |
32b7eeec MR |
12487 | if (intel_crtc->atomic.pre_disable_primary) |
12488 | intel_pre_disable_primary(crtc); | |
3c692a41 | 12489 | |
32b7eeec MR |
12490 | if (intel_crtc->atomic.update_wm) |
12491 | intel_update_watermarks(crtc); | |
3c692a41 | 12492 | |
32b7eeec | 12493 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 12494 | |
c34c9ee4 MR |
12495 | /* Perform vblank evasion around commit operation */ |
12496 | if (intel_crtc->active) | |
12497 | intel_crtc->atomic.evade = | |
12498 | intel_pipe_update_start(intel_crtc, | |
12499 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
12500 | } |
12501 | ||
12502 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
12503 | { | |
12504 | struct drm_device *dev = crtc->dev; | |
12505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12506 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12507 | struct drm_plane *p; | |
12508 | ||
c34c9ee4 MR |
12509 | if (intel_crtc->atomic.evade) |
12510 | intel_pipe_update_end(intel_crtc, | |
12511 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 12512 | |
140fd38d | 12513 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 12514 | |
32b7eeec MR |
12515 | if (intel_crtc->atomic.wait_vblank) |
12516 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
12517 | ||
12518 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
12519 | ||
12520 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 12521 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 12522 | intel_fbc_update(dev); |
ccc759dc | 12523 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 12524 | } |
3c692a41 | 12525 | |
32b7eeec MR |
12526 | if (intel_crtc->atomic.post_enable_primary) |
12527 | intel_post_enable_primary(crtc); | |
3c692a41 | 12528 | |
32b7eeec MR |
12529 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
12530 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
12531 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
12532 | false, false); | |
12533 | ||
12534 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
12535 | } |
12536 | ||
cf4c7c12 | 12537 | /** |
4a3b8769 MR |
12538 | * intel_plane_destroy - destroy a plane |
12539 | * @plane: plane to destroy | |
cf4c7c12 | 12540 | * |
4a3b8769 MR |
12541 | * Common destruction function for all types of planes (primary, cursor, |
12542 | * sprite). | |
cf4c7c12 | 12543 | */ |
4a3b8769 | 12544 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
12545 | { |
12546 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12547 | drm_plane_cleanup(plane); | |
12548 | kfree(intel_plane); | |
12549 | } | |
12550 | ||
65a3fea0 | 12551 | const struct drm_plane_funcs intel_plane_funcs = { |
ff42e093 DV |
12552 | .update_plane = drm_plane_helper_update, |
12553 | .disable_plane = drm_plane_helper_disable, | |
3d7d6510 | 12554 | .destroy = intel_plane_destroy, |
c196e1d6 | 12555 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
12556 | .atomic_get_property = intel_plane_atomic_get_property, |
12557 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12558 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12559 | .atomic_destroy_state = intel_plane_destroy_state, | |
12560 | ||
465c120c MR |
12561 | }; |
12562 | ||
12563 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
12564 | int pipe) | |
12565 | { | |
12566 | struct intel_plane *primary; | |
8e7d688b | 12567 | struct intel_plane_state *state; |
465c120c MR |
12568 | const uint32_t *intel_primary_formats; |
12569 | int num_formats; | |
12570 | ||
12571 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
12572 | if (primary == NULL) | |
12573 | return NULL; | |
12574 | ||
8e7d688b MR |
12575 | state = intel_create_plane_state(&primary->base); |
12576 | if (!state) { | |
ea2c67bb MR |
12577 | kfree(primary); |
12578 | return NULL; | |
12579 | } | |
8e7d688b | 12580 | primary->base.state = &state->base; |
ea2c67bb | 12581 | |
465c120c MR |
12582 | primary->can_scale = false; |
12583 | primary->max_downscale = 1; | |
12584 | primary->pipe = pipe; | |
12585 | primary->plane = pipe; | |
c59cb179 MR |
12586 | primary->check_plane = intel_check_primary_plane; |
12587 | primary->commit_plane = intel_commit_primary_plane; | |
465c120c MR |
12588 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
12589 | primary->plane = !pipe; | |
12590 | ||
12591 | if (INTEL_INFO(dev)->gen <= 3) { | |
12592 | intel_primary_formats = intel_primary_formats_gen2; | |
12593 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
12594 | } else { | |
12595 | intel_primary_formats = intel_primary_formats_gen4; | |
12596 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
12597 | } | |
12598 | ||
12599 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 12600 | &intel_plane_funcs, |
465c120c MR |
12601 | intel_primary_formats, num_formats, |
12602 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
12603 | |
12604 | if (INTEL_INFO(dev)->gen >= 4) { | |
12605 | if (!dev->mode_config.rotation_property) | |
12606 | dev->mode_config.rotation_property = | |
12607 | drm_mode_create_rotation_property(dev, | |
12608 | BIT(DRM_ROTATE_0) | | |
12609 | BIT(DRM_ROTATE_180)); | |
12610 | if (dev->mode_config.rotation_property) | |
12611 | drm_object_attach_property(&primary->base.base, | |
12612 | dev->mode_config.rotation_property, | |
8e7d688b | 12613 | state->base.rotation); |
48404c1e SJ |
12614 | } |
12615 | ||
ea2c67bb MR |
12616 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12617 | ||
465c120c MR |
12618 | return &primary->base; |
12619 | } | |
12620 | ||
3d7d6510 | 12621 | static int |
852e787c GP |
12622 | intel_check_cursor_plane(struct drm_plane *plane, |
12623 | struct intel_plane_state *state) | |
3d7d6510 | 12624 | { |
2b875c22 | 12625 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12626 | struct drm_device *dev = plane->dev; |
2b875c22 | 12627 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12628 | struct drm_rect *dest = &state->dst; |
12629 | struct drm_rect *src = &state->src; | |
12630 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 12631 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 12632 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
12633 | unsigned stride; |
12634 | int ret; | |
3d7d6510 | 12635 | |
ea2c67bb MR |
12636 | crtc = crtc ? crtc : plane->crtc; |
12637 | intel_crtc = to_intel_crtc(crtc); | |
12638 | ||
757f9a3e | 12639 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12640 | src, dest, clip, |
3d7d6510 MR |
12641 | DRM_PLANE_HELPER_NO_SCALING, |
12642 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12643 | true, true, &state->visible); |
757f9a3e GP |
12644 | if (ret) |
12645 | return ret; | |
12646 | ||
12647 | ||
12648 | /* if we want to turn off the cursor ignore width and height */ | |
12649 | if (!obj) | |
32b7eeec | 12650 | goto finish; |
757f9a3e | 12651 | |
757f9a3e | 12652 | /* Check for which cursor types we support */ |
ea2c67bb MR |
12653 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
12654 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
12655 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
12656 | return -EINVAL; |
12657 | } | |
12658 | ||
ea2c67bb MR |
12659 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
12660 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
12661 | DRM_DEBUG_KMS("buffer is too small\n"); |
12662 | return -ENOMEM; | |
12663 | } | |
12664 | ||
3a656b54 | 12665 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
12666 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
12667 | ret = -EINVAL; | |
12668 | } | |
757f9a3e | 12669 | |
32b7eeec MR |
12670 | finish: |
12671 | if (intel_crtc->active) { | |
3749f463 | 12672 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
12673 | intel_crtc->atomic.update_wm = true; |
12674 | ||
12675 | intel_crtc->atomic.fb_bits |= | |
12676 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
12677 | } | |
12678 | ||
757f9a3e | 12679 | return ret; |
852e787c | 12680 | } |
3d7d6510 | 12681 | |
f4a2cf29 | 12682 | static void |
852e787c GP |
12683 | intel_commit_cursor_plane(struct drm_plane *plane, |
12684 | struct intel_plane_state *state) | |
12685 | { | |
2b875c22 | 12686 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
12687 | struct drm_device *dev = plane->dev; |
12688 | struct intel_crtc *intel_crtc; | |
2b875c22 | 12689 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 12690 | uint32_t addr; |
852e787c | 12691 | |
ea2c67bb MR |
12692 | crtc = crtc ? crtc : plane->crtc; |
12693 | intel_crtc = to_intel_crtc(crtc); | |
12694 | ||
2b875c22 | 12695 | plane->fb = state->base.fb; |
ea2c67bb MR |
12696 | crtc->cursor_x = state->base.crtc_x; |
12697 | crtc->cursor_y = state->base.crtc_y; | |
12698 | ||
a912f12f GP |
12699 | if (intel_crtc->cursor_bo == obj) |
12700 | goto update; | |
4ed91096 | 12701 | |
f4a2cf29 | 12702 | if (!obj) |
a912f12f | 12703 | addr = 0; |
f4a2cf29 | 12704 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 12705 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 12706 | else |
a912f12f | 12707 | addr = obj->phys_handle->busaddr; |
852e787c | 12708 | |
a912f12f GP |
12709 | intel_crtc->cursor_addr = addr; |
12710 | intel_crtc->cursor_bo = obj; | |
12711 | update: | |
852e787c | 12712 | |
32b7eeec | 12713 | if (intel_crtc->active) |
a912f12f | 12714 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
12715 | } |
12716 | ||
3d7d6510 MR |
12717 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
12718 | int pipe) | |
12719 | { | |
12720 | struct intel_plane *cursor; | |
8e7d688b | 12721 | struct intel_plane_state *state; |
3d7d6510 MR |
12722 | |
12723 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12724 | if (cursor == NULL) | |
12725 | return NULL; | |
12726 | ||
8e7d688b MR |
12727 | state = intel_create_plane_state(&cursor->base); |
12728 | if (!state) { | |
ea2c67bb MR |
12729 | kfree(cursor); |
12730 | return NULL; | |
12731 | } | |
8e7d688b | 12732 | cursor->base.state = &state->base; |
ea2c67bb | 12733 | |
3d7d6510 MR |
12734 | cursor->can_scale = false; |
12735 | cursor->max_downscale = 1; | |
12736 | cursor->pipe = pipe; | |
12737 | cursor->plane = pipe; | |
c59cb179 MR |
12738 | cursor->check_plane = intel_check_cursor_plane; |
12739 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
12740 | |
12741 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 12742 | &intel_plane_funcs, |
3d7d6510 MR |
12743 | intel_cursor_formats, |
12744 | ARRAY_SIZE(intel_cursor_formats), | |
12745 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
12746 | |
12747 | if (INTEL_INFO(dev)->gen >= 4) { | |
12748 | if (!dev->mode_config.rotation_property) | |
12749 | dev->mode_config.rotation_property = | |
12750 | drm_mode_create_rotation_property(dev, | |
12751 | BIT(DRM_ROTATE_0) | | |
12752 | BIT(DRM_ROTATE_180)); | |
12753 | if (dev->mode_config.rotation_property) | |
12754 | drm_object_attach_property(&cursor->base.base, | |
12755 | dev->mode_config.rotation_property, | |
8e7d688b | 12756 | state->base.rotation); |
4398ad45 VS |
12757 | } |
12758 | ||
ea2c67bb MR |
12759 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
12760 | ||
3d7d6510 MR |
12761 | return &cursor->base; |
12762 | } | |
12763 | ||
b358d0a6 | 12764 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12765 | { |
fbee40df | 12766 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12767 | struct intel_crtc *intel_crtc; |
f5de6e07 | 12768 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
12769 | struct drm_plane *primary = NULL; |
12770 | struct drm_plane *cursor = NULL; | |
465c120c | 12771 | int i, ret; |
79e53945 | 12772 | |
955382f3 | 12773 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12774 | if (intel_crtc == NULL) |
12775 | return; | |
12776 | ||
f5de6e07 ACO |
12777 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
12778 | if (!crtc_state) | |
12779 | goto fail; | |
12780 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 12781 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 12782 | |
465c120c | 12783 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12784 | if (!primary) |
12785 | goto fail; | |
12786 | ||
12787 | cursor = intel_cursor_plane_create(dev, pipe); | |
12788 | if (!cursor) | |
12789 | goto fail; | |
12790 | ||
465c120c | 12791 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12792 | cursor, &intel_crtc_funcs); |
12793 | if (ret) | |
12794 | goto fail; | |
79e53945 JB |
12795 | |
12796 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12797 | for (i = 0; i < 256; i++) { |
12798 | intel_crtc->lut_r[i] = i; | |
12799 | intel_crtc->lut_g[i] = i; | |
12800 | intel_crtc->lut_b[i] = i; | |
12801 | } | |
12802 | ||
1f1c2e24 VS |
12803 | /* |
12804 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12805 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12806 | */ |
80824003 JB |
12807 | intel_crtc->pipe = pipe; |
12808 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12809 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12810 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12811 | intel_crtc->plane = !pipe; |
80824003 JB |
12812 | } |
12813 | ||
4b0e333e CW |
12814 | intel_crtc->cursor_base = ~0; |
12815 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12816 | intel_crtc->cursor_size = ~0; |
8d7849db | 12817 | |
22fd0fab JB |
12818 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12819 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12820 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12821 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12822 | ||
9362c7c5 ACO |
12823 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
12824 | ||
79e53945 | 12825 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12826 | |
12827 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12828 | return; |
12829 | ||
12830 | fail: | |
12831 | if (primary) | |
12832 | drm_plane_cleanup(primary); | |
12833 | if (cursor) | |
12834 | drm_plane_cleanup(cursor); | |
f5de6e07 | 12835 | kfree(crtc_state); |
3d7d6510 | 12836 | kfree(intel_crtc); |
79e53945 JB |
12837 | } |
12838 | ||
752aa88a JB |
12839 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12840 | { | |
12841 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12842 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12843 | |
51fd371b | 12844 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 12845 | |
d3babd3f | 12846 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
12847 | return INVALID_PIPE; |
12848 | ||
12849 | return to_intel_crtc(encoder->crtc)->pipe; | |
12850 | } | |
12851 | ||
08d7b3d1 | 12852 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12853 | struct drm_file *file) |
08d7b3d1 | 12854 | { |
08d7b3d1 | 12855 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12856 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12857 | struct intel_crtc *crtc; |
08d7b3d1 | 12858 | |
7707e653 | 12859 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12860 | |
7707e653 | 12861 | if (!drmmode_crtc) { |
08d7b3d1 | 12862 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12863 | return -ENOENT; |
08d7b3d1 CW |
12864 | } |
12865 | ||
7707e653 | 12866 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12867 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12868 | |
c05422d5 | 12869 | return 0; |
08d7b3d1 CW |
12870 | } |
12871 | ||
66a9278e | 12872 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12873 | { |
66a9278e DV |
12874 | struct drm_device *dev = encoder->base.dev; |
12875 | struct intel_encoder *source_encoder; | |
79e53945 | 12876 | int index_mask = 0; |
79e53945 JB |
12877 | int entry = 0; |
12878 | ||
b2784e15 | 12879 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12880 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12881 | index_mask |= (1 << entry); |
12882 | ||
79e53945 JB |
12883 | entry++; |
12884 | } | |
4ef69c7a | 12885 | |
79e53945 JB |
12886 | return index_mask; |
12887 | } | |
12888 | ||
4d302442 CW |
12889 | static bool has_edp_a(struct drm_device *dev) |
12890 | { | |
12891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12892 | ||
12893 | if (!IS_MOBILE(dev)) | |
12894 | return false; | |
12895 | ||
12896 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12897 | return false; | |
12898 | ||
e3589908 | 12899 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12900 | return false; |
12901 | ||
12902 | return true; | |
12903 | } | |
12904 | ||
84b4e042 JB |
12905 | static bool intel_crt_present(struct drm_device *dev) |
12906 | { | |
12907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12908 | ||
884497ed DL |
12909 | if (INTEL_INFO(dev)->gen >= 9) |
12910 | return false; | |
12911 | ||
cf404ce4 | 12912 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
12913 | return false; |
12914 | ||
12915 | if (IS_CHERRYVIEW(dev)) | |
12916 | return false; | |
12917 | ||
12918 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12919 | return false; | |
12920 | ||
12921 | return true; | |
12922 | } | |
12923 | ||
79e53945 JB |
12924 | static void intel_setup_outputs(struct drm_device *dev) |
12925 | { | |
725e30ad | 12926 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12927 | struct intel_encoder *encoder; |
c6f95f27 | 12928 | struct drm_connector *connector; |
cb0953d7 | 12929 | bool dpd_is_edp = false; |
79e53945 | 12930 | |
c9093354 | 12931 | intel_lvds_init(dev); |
79e53945 | 12932 | |
84b4e042 | 12933 | if (intel_crt_present(dev)) |
79935fca | 12934 | intel_crt_init(dev); |
cb0953d7 | 12935 | |
affa9354 | 12936 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12937 | int found; |
12938 | ||
de31facd JB |
12939 | /* |
12940 | * Haswell uses DDI functions to detect digital outputs. | |
12941 | * On SKL pre-D0 the strap isn't connected, so we assume | |
12942 | * it's there. | |
12943 | */ | |
0e72a5b5 | 12944 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
12945 | /* WaIgnoreDDIAStrap: skl */ |
12946 | if (found || | |
12947 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
12948 | intel_ddi_init(dev, PORT_A); |
12949 | ||
12950 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12951 | * register */ | |
12952 | found = I915_READ(SFUSE_STRAP); | |
12953 | ||
12954 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12955 | intel_ddi_init(dev, PORT_B); | |
12956 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12957 | intel_ddi_init(dev, PORT_C); | |
12958 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12959 | intel_ddi_init(dev, PORT_D); | |
12960 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12961 | int found; |
5d8a7752 | 12962 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12963 | |
12964 | if (has_edp_a(dev)) | |
12965 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12966 | |
dc0fa718 | 12967 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12968 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12969 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12970 | if (!found) |
e2debe91 | 12971 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12972 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12973 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12974 | } |
12975 | ||
dc0fa718 | 12976 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12977 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12978 | |
dc0fa718 | 12979 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12980 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12981 | |
5eb08b69 | 12982 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12983 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12984 | |
270b3042 | 12985 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12986 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12987 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
12988 | /* |
12989 | * The DP_DETECTED bit is the latched state of the DDC | |
12990 | * SDA pin at boot. However since eDP doesn't require DDC | |
12991 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
12992 | * eDP ports may have been muxed to an alternate function. | |
12993 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
12994 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
12995 | * detect eDP ports. | |
12996 | */ | |
d2182a66 VS |
12997 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
12998 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
12999 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13000 | PORT_B); | |
e17ac6db VS |
13001 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13002 | intel_dp_is_edp(dev, PORT_B)) | |
13003 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13004 | |
d2182a66 VS |
13005 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13006 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13007 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13008 | PORT_C); | |
e17ac6db VS |
13009 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13010 | intel_dp_is_edp(dev, PORT_C)) | |
13011 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13012 | |
9418c1f1 | 13013 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13014 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13015 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13016 | PORT_D); | |
e17ac6db VS |
13017 | /* eDP not supported on port D, so don't check VBT */ |
13018 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13019 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13020 | } |
13021 | ||
3cfca973 | 13022 | intel_dsi_init(dev); |
103a196f | 13023 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13024 | bool found = false; |
7d57382e | 13025 | |
e2debe91 | 13026 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13027 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13028 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13029 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13030 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13031 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13032 | } |
27185ae1 | 13033 | |
e7281eab | 13034 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13035 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13036 | } |
13520b05 KH |
13037 | |
13038 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13039 | |
e2debe91 | 13040 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13041 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13042 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13043 | } |
27185ae1 | 13044 | |
e2debe91 | 13045 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13046 | |
b01f2c3a JB |
13047 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13048 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13049 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13050 | } |
e7281eab | 13051 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13052 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13053 | } |
27185ae1 | 13054 | |
b01f2c3a | 13055 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13056 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13057 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13058 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13059 | intel_dvo_init(dev); |
13060 | ||
103a196f | 13061 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13062 | intel_tv_init(dev); |
13063 | ||
c6f95f27 MR |
13064 | /* |
13065 | * FIXME: We don't have full atomic support yet, but we want to be | |
13066 | * able to enable/test plane updates via the atomic interface in the | |
13067 | * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core | |
13068 | * will take some atomic codepaths to lookup properties during | |
13069 | * drmModeGetConnector() that unconditionally dereference | |
13070 | * connector->state. | |
13071 | * | |
13072 | * We create a dummy connector state here for each connector to ensure | |
13073 | * the DRM core doesn't try to dereference a NULL connector->state. | |
13074 | * The actual connector properties will never be updated or contain | |
13075 | * useful information, but since we're doing this specifically for | |
13076 | * testing/debug of the plane operations (and only when a specific | |
13077 | * kernel module option is given), that shouldn't really matter. | |
13078 | * | |
d29b2f9d ACO |
13079 | * We are also relying on these states to convert the legacy mode set |
13080 | * to use a drm_atomic_state struct. The states are kept consistent | |
13081 | * with actual state, so that it is safe to rely on that instead of | |
13082 | * the staged config. | |
13083 | * | |
c6f95f27 MR |
13084 | * Once atomic support for crtc's + connectors lands, this loop should |
13085 | * be removed since we'll be setting up real connector state, which | |
13086 | * will contain Intel-specific properties. | |
13087 | */ | |
d29b2f9d ACO |
13088 | list_for_each_entry(connector, |
13089 | &dev->mode_config.connector_list, | |
13090 | head) { | |
13091 | if (!WARN_ON(connector->state)) { | |
13092 | connector->state = kzalloc(sizeof(*connector->state), | |
13093 | GFP_KERNEL); | |
c6f95f27 MR |
13094 | } |
13095 | } | |
13096 | ||
0bc12bcb | 13097 | intel_psr_init(dev); |
7c8f8a70 | 13098 | |
b2784e15 | 13099 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13100 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13101 | encoder->base.possible_clones = | |
66a9278e | 13102 | intel_encoder_clones(encoder); |
79e53945 | 13103 | } |
47356eb6 | 13104 | |
dde86e2d | 13105 | intel_init_pch_refclk(dev); |
270b3042 DV |
13106 | |
13107 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13108 | } |
13109 | ||
13110 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13111 | { | |
60a5ca01 | 13112 | struct drm_device *dev = fb->dev; |
79e53945 | 13113 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13114 | |
ef2d633e | 13115 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13116 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13117 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13118 | drm_gem_object_unreference(&intel_fb->obj->base); |
13119 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13120 | kfree(intel_fb); |
13121 | } | |
13122 | ||
13123 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13124 | struct drm_file *file, |
79e53945 JB |
13125 | unsigned int *handle) |
13126 | { | |
13127 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13128 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13129 | |
05394f39 | 13130 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13131 | } |
13132 | ||
13133 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13134 | .destroy = intel_user_framebuffer_destroy, | |
13135 | .create_handle = intel_user_framebuffer_create_handle, | |
13136 | }; | |
13137 | ||
b321803d DL |
13138 | static |
13139 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13140 | uint32_t pixel_format) | |
13141 | { | |
13142 | u32 gen = INTEL_INFO(dev)->gen; | |
13143 | ||
13144 | if (gen >= 9) { | |
13145 | /* "The stride in bytes must not exceed the of the size of 8K | |
13146 | * pixels and 32K bytes." | |
13147 | */ | |
13148 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13149 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13150 | return 32*1024; | |
13151 | } else if (gen >= 4) { | |
13152 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13153 | return 16*1024; | |
13154 | else | |
13155 | return 32*1024; | |
13156 | } else if (gen >= 3) { | |
13157 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13158 | return 8*1024; | |
13159 | else | |
13160 | return 16*1024; | |
13161 | } else { | |
13162 | /* XXX DSPC is limited to 4k tiled */ | |
13163 | return 8*1024; | |
13164 | } | |
13165 | } | |
13166 | ||
b5ea642a DV |
13167 | static int intel_framebuffer_init(struct drm_device *dev, |
13168 | struct intel_framebuffer *intel_fb, | |
13169 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13170 | struct drm_i915_gem_object *obj) | |
79e53945 | 13171 | { |
6761dd31 | 13172 | unsigned int aligned_height; |
79e53945 | 13173 | int ret; |
b321803d | 13174 | u32 pitch_limit, stride_alignment; |
79e53945 | 13175 | |
dd4916c5 DV |
13176 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13177 | ||
2a80eada DV |
13178 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13179 | /* Enforce that fb modifier and tiling mode match, but only for | |
13180 | * X-tiled. This is needed for FBC. */ | |
13181 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13182 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13183 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13184 | return -EINVAL; | |
13185 | } | |
13186 | } else { | |
13187 | if (obj->tiling_mode == I915_TILING_X) | |
13188 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13189 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13190 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13191 | return -EINVAL; | |
13192 | } | |
13193 | } | |
13194 | ||
9a8f0a12 TU |
13195 | /* Passed in modifier sanity checking. */ |
13196 | switch (mode_cmd->modifier[0]) { | |
13197 | case I915_FORMAT_MOD_Y_TILED: | |
13198 | case I915_FORMAT_MOD_Yf_TILED: | |
13199 | if (INTEL_INFO(dev)->gen < 9) { | |
13200 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13201 | mode_cmd->modifier[0]); | |
13202 | return -EINVAL; | |
13203 | } | |
13204 | case DRM_FORMAT_MOD_NONE: | |
13205 | case I915_FORMAT_MOD_X_TILED: | |
13206 | break; | |
13207 | default: | |
c0f40428 JB |
13208 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13209 | mode_cmd->modifier[0]); | |
57cd6508 | 13210 | return -EINVAL; |
c16ed4be | 13211 | } |
57cd6508 | 13212 | |
b321803d DL |
13213 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13214 | mode_cmd->pixel_format); | |
13215 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13216 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13217 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13218 | return -EINVAL; |
c16ed4be | 13219 | } |
57cd6508 | 13220 | |
b321803d DL |
13221 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
13222 | mode_cmd->pixel_format); | |
a35cdaa0 | 13223 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
13224 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
13225 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 13226 | "tiled" : "linear", |
a35cdaa0 | 13227 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 13228 | return -EINVAL; |
c16ed4be | 13229 | } |
5d7bd705 | 13230 | |
2a80eada | 13231 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
13232 | mode_cmd->pitches[0] != obj->stride) { |
13233 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
13234 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 13235 | return -EINVAL; |
c16ed4be | 13236 | } |
5d7bd705 | 13237 | |
57779d06 | 13238 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13239 | switch (mode_cmd->pixel_format) { |
57779d06 | 13240 | case DRM_FORMAT_C8: |
04b3924d VS |
13241 | case DRM_FORMAT_RGB565: |
13242 | case DRM_FORMAT_XRGB8888: | |
13243 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13244 | break; |
13245 | case DRM_FORMAT_XRGB1555: | |
13246 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 13247 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
13248 | DRM_DEBUG("unsupported pixel format: %s\n", |
13249 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13250 | return -EINVAL; |
c16ed4be | 13251 | } |
57779d06 VS |
13252 | break; |
13253 | case DRM_FORMAT_XBGR8888: | |
13254 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
13255 | case DRM_FORMAT_XRGB2101010: |
13256 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
13257 | case DRM_FORMAT_XBGR2101010: |
13258 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 13259 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
13260 | DRM_DEBUG("unsupported pixel format: %s\n", |
13261 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13262 | return -EINVAL; |
c16ed4be | 13263 | } |
b5626747 | 13264 | break; |
04b3924d VS |
13265 | case DRM_FORMAT_YUYV: |
13266 | case DRM_FORMAT_UYVY: | |
13267 | case DRM_FORMAT_YVYU: | |
13268 | case DRM_FORMAT_VYUY: | |
c16ed4be | 13269 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
13270 | DRM_DEBUG("unsupported pixel format: %s\n", |
13271 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13272 | return -EINVAL; |
c16ed4be | 13273 | } |
57cd6508 CW |
13274 | break; |
13275 | default: | |
4ee62c76 VS |
13276 | DRM_DEBUG("unsupported pixel format: %s\n", |
13277 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
13278 | return -EINVAL; |
13279 | } | |
13280 | ||
90f9a336 VS |
13281 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13282 | if (mode_cmd->offsets[0] != 0) | |
13283 | return -EINVAL; | |
13284 | ||
ec2c981e | 13285 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
13286 | mode_cmd->pixel_format, |
13287 | mode_cmd->modifier[0]); | |
53155c0a DV |
13288 | /* FIXME drm helper for size checks (especially planar formats)? */ |
13289 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
13290 | return -EINVAL; | |
13291 | ||
c7d73f6a DV |
13292 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
13293 | intel_fb->obj = obj; | |
80075d49 | 13294 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 13295 | |
79e53945 JB |
13296 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
13297 | if (ret) { | |
13298 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
13299 | return ret; | |
13300 | } | |
13301 | ||
79e53945 JB |
13302 | return 0; |
13303 | } | |
13304 | ||
79e53945 JB |
13305 | static struct drm_framebuffer * |
13306 | intel_user_framebuffer_create(struct drm_device *dev, | |
13307 | struct drm_file *filp, | |
308e5bcb | 13308 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 13309 | { |
05394f39 | 13310 | struct drm_i915_gem_object *obj; |
79e53945 | 13311 | |
308e5bcb JB |
13312 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
13313 | mode_cmd->handles[0])); | |
c8725226 | 13314 | if (&obj->base == NULL) |
cce13ff7 | 13315 | return ERR_PTR(-ENOENT); |
79e53945 | 13316 | |
d2dff872 | 13317 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
13318 | } |
13319 | ||
4520f53a | 13320 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 13321 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
13322 | { |
13323 | } | |
13324 | #endif | |
13325 | ||
79e53945 | 13326 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 13327 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 13328 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
13329 | .atomic_check = intel_atomic_check, |
13330 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
13331 | }; |
13332 | ||
e70236a8 JB |
13333 | /* Set up chip specific display functions */ |
13334 | static void intel_init_display(struct drm_device *dev) | |
13335 | { | |
13336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13337 | ||
ee9300bb DV |
13338 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
13339 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
13340 | else if (IS_CHERRYVIEW(dev)) |
13341 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
13342 | else if (IS_VALLEYVIEW(dev)) |
13343 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
13344 | else if (IS_PINEVIEW(dev)) | |
13345 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
13346 | else | |
13347 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
13348 | ||
bc8d7dff DL |
13349 | if (INTEL_INFO(dev)->gen >= 9) { |
13350 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
13351 | dev_priv->display.get_initial_plane_config = |
13352 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
13353 | dev_priv->display.crtc_compute_clock = |
13354 | haswell_crtc_compute_clock; | |
13355 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
13356 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
13357 | dev_priv->display.off = ironlake_crtc_off; | |
13358 | dev_priv->display.update_primary_plane = | |
13359 | skylake_update_primary_plane; | |
13360 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 13361 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13362 | dev_priv->display.get_initial_plane_config = |
13363 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
13364 | dev_priv->display.crtc_compute_clock = |
13365 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
13366 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
13367 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 13368 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
13369 | dev_priv->display.update_primary_plane = |
13370 | ironlake_update_primary_plane; | |
09b4ddf9 | 13371 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 13372 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
13373 | dev_priv->display.get_initial_plane_config = |
13374 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
13375 | dev_priv->display.crtc_compute_clock = |
13376 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
13377 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
13378 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 13379 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
13380 | dev_priv->display.update_primary_plane = |
13381 | ironlake_update_primary_plane; | |
89b667f8 JB |
13382 | } else if (IS_VALLEYVIEW(dev)) { |
13383 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
13384 | dev_priv->display.get_initial_plane_config = |
13385 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13386 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
13387 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
13388 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
13389 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
13390 | dev_priv->display.update_primary_plane = |
13391 | i9xx_update_primary_plane; | |
f564048e | 13392 | } else { |
0e8ffe1b | 13393 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13394 | dev_priv->display.get_initial_plane_config = |
13395 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13396 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
13397 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
13398 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 13399 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
13400 | dev_priv->display.update_primary_plane = |
13401 | i9xx_update_primary_plane; | |
f564048e | 13402 | } |
e70236a8 | 13403 | |
e70236a8 | 13404 | /* Returns the core display clock speed */ |
25eb05fc JB |
13405 | if (IS_VALLEYVIEW(dev)) |
13406 | dev_priv->display.get_display_clock_speed = | |
13407 | valleyview_get_display_clock_speed; | |
13408 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
13409 | dev_priv->display.get_display_clock_speed = |
13410 | i945_get_display_clock_speed; | |
13411 | else if (IS_I915G(dev)) | |
13412 | dev_priv->display.get_display_clock_speed = | |
13413 | i915_get_display_clock_speed; | |
257a7ffc | 13414 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
13415 | dev_priv->display.get_display_clock_speed = |
13416 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
13417 | else if (IS_PINEVIEW(dev)) |
13418 | dev_priv->display.get_display_clock_speed = | |
13419 | pnv_get_display_clock_speed; | |
e70236a8 JB |
13420 | else if (IS_I915GM(dev)) |
13421 | dev_priv->display.get_display_clock_speed = | |
13422 | i915gm_get_display_clock_speed; | |
13423 | else if (IS_I865G(dev)) | |
13424 | dev_priv->display.get_display_clock_speed = | |
13425 | i865_get_display_clock_speed; | |
f0f8a9ce | 13426 | else if (IS_I85X(dev)) |
e70236a8 JB |
13427 | dev_priv->display.get_display_clock_speed = |
13428 | i855_get_display_clock_speed; | |
13429 | else /* 852, 830 */ | |
13430 | dev_priv->display.get_display_clock_speed = | |
13431 | i830_get_display_clock_speed; | |
13432 | ||
7c10a2b5 | 13433 | if (IS_GEN5(dev)) { |
3bb11b53 | 13434 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
13435 | } else if (IS_GEN6(dev)) { |
13436 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
13437 | } else if (IS_IVYBRIDGE(dev)) { |
13438 | /* FIXME: detect B0+ stepping and use auto training */ | |
13439 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 13440 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 13441 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
13442 | } else if (IS_VALLEYVIEW(dev)) { |
13443 | dev_priv->display.modeset_global_resources = | |
13444 | valleyview_modeset_global_resources; | |
e70236a8 | 13445 | } |
8c9f3aaf | 13446 | |
8c9f3aaf JB |
13447 | switch (INTEL_INFO(dev)->gen) { |
13448 | case 2: | |
13449 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
13450 | break; | |
13451 | ||
13452 | case 3: | |
13453 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
13454 | break; | |
13455 | ||
13456 | case 4: | |
13457 | case 5: | |
13458 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
13459 | break; | |
13460 | ||
13461 | case 6: | |
13462 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
13463 | break; | |
7c9017e5 | 13464 | case 7: |
4e0bbc31 | 13465 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
13466 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
13467 | break; | |
830c81db | 13468 | case 9: |
ba343e02 TU |
13469 | /* Drop through - unsupported since execlist only. */ |
13470 | default: | |
13471 | /* Default just returns -ENODEV to indicate unsupported */ | |
13472 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 13473 | } |
7bd688cd JN |
13474 | |
13475 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
13476 | |
13477 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
13478 | } |
13479 | ||
b690e96c JB |
13480 | /* |
13481 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
13482 | * resume, or other times. This quirk makes sure that's the case for | |
13483 | * affected systems. | |
13484 | */ | |
0206e353 | 13485 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
13486 | { |
13487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13488 | ||
13489 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 13490 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
13491 | } |
13492 | ||
b6b5d049 VS |
13493 | static void quirk_pipeb_force(struct drm_device *dev) |
13494 | { | |
13495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13496 | ||
13497 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
13498 | DRM_INFO("applying pipe b force quirk\n"); | |
13499 | } | |
13500 | ||
435793df KP |
13501 | /* |
13502 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
13503 | */ | |
13504 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
13505 | { | |
13506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13507 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 13508 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
13509 | } |
13510 | ||
4dca20ef | 13511 | /* |
5a15ab5b CE |
13512 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
13513 | * brightness value | |
4dca20ef CE |
13514 | */ |
13515 | static void quirk_invert_brightness(struct drm_device *dev) | |
13516 | { | |
13517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13518 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 13519 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
13520 | } |
13521 | ||
9c72cc6f SD |
13522 | /* Some VBT's incorrectly indicate no backlight is present */ |
13523 | static void quirk_backlight_present(struct drm_device *dev) | |
13524 | { | |
13525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13526 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
13527 | DRM_INFO("applying backlight present quirk\n"); | |
13528 | } | |
13529 | ||
b690e96c JB |
13530 | struct intel_quirk { |
13531 | int device; | |
13532 | int subsystem_vendor; | |
13533 | int subsystem_device; | |
13534 | void (*hook)(struct drm_device *dev); | |
13535 | }; | |
13536 | ||
5f85f176 EE |
13537 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
13538 | struct intel_dmi_quirk { | |
13539 | void (*hook)(struct drm_device *dev); | |
13540 | const struct dmi_system_id (*dmi_id_list)[]; | |
13541 | }; | |
13542 | ||
13543 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
13544 | { | |
13545 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
13546 | return 1; | |
13547 | } | |
13548 | ||
13549 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
13550 | { | |
13551 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
13552 | { | |
13553 | .callback = intel_dmi_reverse_brightness, | |
13554 | .ident = "NCR Corporation", | |
13555 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
13556 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
13557 | }, | |
13558 | }, | |
13559 | { } /* terminating entry */ | |
13560 | }, | |
13561 | .hook = quirk_invert_brightness, | |
13562 | }, | |
13563 | }; | |
13564 | ||
c43b5634 | 13565 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 13566 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 13567 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 13568 | |
b690e96c JB |
13569 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
13570 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
13571 | ||
b690e96c JB |
13572 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
13573 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
13574 | ||
5f080c0f VS |
13575 | /* 830 needs to leave pipe A & dpll A up */ |
13576 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
13577 | ||
b6b5d049 VS |
13578 | /* 830 needs to leave pipe B & dpll B up */ |
13579 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
13580 | ||
435793df KP |
13581 | /* Lenovo U160 cannot use SSC on LVDS */ |
13582 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
13583 | |
13584 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
13585 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 13586 | |
be505f64 AH |
13587 | /* Acer Aspire 5734Z must invert backlight brightness */ |
13588 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
13589 | ||
13590 | /* Acer/eMachines G725 */ | |
13591 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
13592 | ||
13593 | /* Acer/eMachines e725 */ | |
13594 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
13595 | ||
13596 | /* Acer/Packard Bell NCL20 */ | |
13597 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
13598 | ||
13599 | /* Acer Aspire 4736Z */ | |
13600 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
13601 | |
13602 | /* Acer Aspire 5336 */ | |
13603 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
13604 | |
13605 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
13606 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 13607 | |
dfb3d47b SD |
13608 | /* Acer C720 Chromebook (Core i3 4005U) */ |
13609 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
13610 | ||
b2a9601c | 13611 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
13612 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
13613 | ||
d4967d8c SD |
13614 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
13615 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
13616 | |
13617 | /* HP Chromebook 14 (Celeron 2955U) */ | |
13618 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
13619 | |
13620 | /* Dell Chromebook 11 */ | |
13621 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
13622 | }; |
13623 | ||
13624 | static void intel_init_quirks(struct drm_device *dev) | |
13625 | { | |
13626 | struct pci_dev *d = dev->pdev; | |
13627 | int i; | |
13628 | ||
13629 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
13630 | struct intel_quirk *q = &intel_quirks[i]; | |
13631 | ||
13632 | if (d->device == q->device && | |
13633 | (d->subsystem_vendor == q->subsystem_vendor || | |
13634 | q->subsystem_vendor == PCI_ANY_ID) && | |
13635 | (d->subsystem_device == q->subsystem_device || | |
13636 | q->subsystem_device == PCI_ANY_ID)) | |
13637 | q->hook(dev); | |
13638 | } | |
5f85f176 EE |
13639 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
13640 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
13641 | intel_dmi_quirks[i].hook(dev); | |
13642 | } | |
b690e96c JB |
13643 | } |
13644 | ||
9cce37f4 JB |
13645 | /* Disable the VGA plane that we never use */ |
13646 | static void i915_disable_vga(struct drm_device *dev) | |
13647 | { | |
13648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13649 | u8 sr1; | |
766aa1c4 | 13650 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 13651 | |
2b37c616 | 13652 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 13653 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 13654 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
13655 | sr1 = inb(VGA_SR_DATA); |
13656 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
13657 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
13658 | udelay(300); | |
13659 | ||
01f5a626 | 13660 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
13661 | POSTING_READ(vga_reg); |
13662 | } | |
13663 | ||
f817586c DV |
13664 | void intel_modeset_init_hw(struct drm_device *dev) |
13665 | { | |
a8f78b58 ED |
13666 | intel_prepare_ddi(dev); |
13667 | ||
f8bf63fd VS |
13668 | if (IS_VALLEYVIEW(dev)) |
13669 | vlv_update_cdclk(dev); | |
13670 | ||
f817586c DV |
13671 | intel_init_clock_gating(dev); |
13672 | ||
8090c6b9 | 13673 | intel_enable_gt_powersave(dev); |
f817586c DV |
13674 | } |
13675 | ||
79e53945 JB |
13676 | void intel_modeset_init(struct drm_device *dev) |
13677 | { | |
652c393a | 13678 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 13679 | int sprite, ret; |
8cc87b75 | 13680 | enum pipe pipe; |
46f297fb | 13681 | struct intel_crtc *crtc; |
79e53945 JB |
13682 | |
13683 | drm_mode_config_init(dev); | |
13684 | ||
13685 | dev->mode_config.min_width = 0; | |
13686 | dev->mode_config.min_height = 0; | |
13687 | ||
019d96cb DA |
13688 | dev->mode_config.preferred_depth = 24; |
13689 | dev->mode_config.prefer_shadow = 1; | |
13690 | ||
25bab385 TU |
13691 | dev->mode_config.allow_fb_modifiers = true; |
13692 | ||
e6ecefaa | 13693 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 13694 | |
b690e96c JB |
13695 | intel_init_quirks(dev); |
13696 | ||
1fa61106 ED |
13697 | intel_init_pm(dev); |
13698 | ||
e3c74757 BW |
13699 | if (INTEL_INFO(dev)->num_pipes == 0) |
13700 | return; | |
13701 | ||
e70236a8 | 13702 | intel_init_display(dev); |
7c10a2b5 | 13703 | intel_init_audio(dev); |
e70236a8 | 13704 | |
a6c45cf0 CW |
13705 | if (IS_GEN2(dev)) { |
13706 | dev->mode_config.max_width = 2048; | |
13707 | dev->mode_config.max_height = 2048; | |
13708 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13709 | dev->mode_config.max_width = 4096; |
13710 | dev->mode_config.max_height = 4096; | |
79e53945 | 13711 | } else { |
a6c45cf0 CW |
13712 | dev->mode_config.max_width = 8192; |
13713 | dev->mode_config.max_height = 8192; | |
79e53945 | 13714 | } |
068be561 | 13715 | |
dc41c154 VS |
13716 | if (IS_845G(dev) || IS_I865G(dev)) { |
13717 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13718 | dev->mode_config.cursor_height = 1023; | |
13719 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13720 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13721 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13722 | } else { | |
13723 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13724 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13725 | } | |
13726 | ||
5d4545ae | 13727 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13728 | |
28c97730 | 13729 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13730 | INTEL_INFO(dev)->num_pipes, |
13731 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13732 | |
055e393f | 13733 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13734 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 13735 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 13736 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 13737 | if (ret) |
06da8da2 | 13738 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13739 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13740 | } |
79e53945 JB |
13741 | } |
13742 | ||
f42bb70d JB |
13743 | intel_init_dpio(dev); |
13744 | ||
e72f9fbf | 13745 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13746 | |
9cce37f4 JB |
13747 | /* Just disable it once at startup */ |
13748 | i915_disable_vga(dev); | |
79e53945 | 13749 | intel_setup_outputs(dev); |
11be49eb CW |
13750 | |
13751 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 13752 | intel_fbc_disable(dev); |
fa9fa083 | 13753 | |
6e9f798d | 13754 | drm_modeset_lock_all(dev); |
fa9fa083 | 13755 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13756 | drm_modeset_unlock_all(dev); |
46f297fb | 13757 | |
d3fcc808 | 13758 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13759 | if (!crtc->active) |
13760 | continue; | |
13761 | ||
46f297fb | 13762 | /* |
46f297fb JB |
13763 | * Note that reserving the BIOS fb up front prevents us |
13764 | * from stuffing other stolen allocations like the ring | |
13765 | * on top. This prevents some ugliness at boot time, and | |
13766 | * can even allow for smooth boot transitions if the BIOS | |
13767 | * fb is large enough for the active pipe configuration. | |
13768 | */ | |
5724dbd1 DL |
13769 | if (dev_priv->display.get_initial_plane_config) { |
13770 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
13771 | &crtc->plane_config); |
13772 | /* | |
13773 | * If the fb is shared between multiple heads, we'll | |
13774 | * just get the first one. | |
13775 | */ | |
f6936e29 | 13776 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13777 | } |
46f297fb | 13778 | } |
2c7111db CW |
13779 | } |
13780 | ||
7fad798e DV |
13781 | static void intel_enable_pipe_a(struct drm_device *dev) |
13782 | { | |
13783 | struct intel_connector *connector; | |
13784 | struct drm_connector *crt = NULL; | |
13785 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13786 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13787 | |
13788 | /* We can't just switch on the pipe A, we need to set things up with a | |
13789 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13790 | * by enabling the load detect pipe once. */ | |
3a3371ff | 13791 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
13792 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
13793 | crt = &connector->base; | |
13794 | break; | |
13795 | } | |
13796 | } | |
13797 | ||
13798 | if (!crt) | |
13799 | return; | |
13800 | ||
208bf9fd | 13801 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 13802 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
13803 | } |
13804 | ||
fa555837 DV |
13805 | static bool |
13806 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13807 | { | |
7eb552ae BW |
13808 | struct drm_device *dev = crtc->base.dev; |
13809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13810 | u32 reg, val; |
13811 | ||
7eb552ae | 13812 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13813 | return true; |
13814 | ||
13815 | reg = DSPCNTR(!crtc->plane); | |
13816 | val = I915_READ(reg); | |
13817 | ||
13818 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13819 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13820 | return false; | |
13821 | ||
13822 | return true; | |
13823 | } | |
13824 | ||
24929352 DV |
13825 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13826 | { | |
13827 | struct drm_device *dev = crtc->base.dev; | |
13828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13829 | u32 reg; |
24929352 | 13830 | |
24929352 | 13831 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 13832 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
13833 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13834 | ||
d3eaf884 | 13835 | /* restore vblank interrupts to correct state */ |
9625604c | 13836 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
13837 | if (crtc->active) { |
13838 | update_scanline_offset(crtc); | |
9625604c DV |
13839 | drm_crtc_vblank_on(&crtc->base); |
13840 | } | |
d3eaf884 | 13841 | |
24929352 | 13842 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13843 | * disable the crtc (and hence change the state) if it is wrong. Note |
13844 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13845 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13846 | struct intel_connector *connector; |
13847 | bool plane; | |
13848 | ||
24929352 DV |
13849 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13850 | crtc->base.base.id); | |
13851 | ||
13852 | /* Pipe has the wrong plane attached and the plane is active. | |
13853 | * Temporarily change the plane mapping and disable everything | |
13854 | * ... */ | |
13855 | plane = crtc->plane; | |
13856 | crtc->plane = !plane; | |
9c8958bc | 13857 | crtc->primary_enabled = true; |
24929352 DV |
13858 | dev_priv->display.crtc_disable(&crtc->base); |
13859 | crtc->plane = plane; | |
13860 | ||
13861 | /* ... and break all links. */ | |
3a3371ff | 13862 | for_each_intel_connector(dev, connector) { |
24929352 DV |
13863 | if (connector->encoder->base.crtc != &crtc->base) |
13864 | continue; | |
13865 | ||
7f1950fb EE |
13866 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13867 | connector->base.encoder = NULL; | |
24929352 | 13868 | } |
7f1950fb EE |
13869 | /* multiple connectors may have the same encoder: |
13870 | * handle them and break crtc link separately */ | |
3a3371ff | 13871 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
13872 | if (connector->encoder->base.crtc == &crtc->base) { |
13873 | connector->encoder->base.crtc = NULL; | |
13874 | connector->encoder->connectors_active = false; | |
13875 | } | |
24929352 DV |
13876 | |
13877 | WARN_ON(crtc->active); | |
83d65738 | 13878 | crtc->base.state->enable = false; |
24929352 DV |
13879 | crtc->base.enabled = false; |
13880 | } | |
24929352 | 13881 | |
7fad798e DV |
13882 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13883 | crtc->pipe == PIPE_A && !crtc->active) { | |
13884 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13885 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13886 | * call below we restore the pipe to the right state, but leave | |
13887 | * the required bits on. */ | |
13888 | intel_enable_pipe_a(dev); | |
13889 | } | |
13890 | ||
24929352 DV |
13891 | /* Adjust the state of the output pipe according to whether we |
13892 | * have active connectors/encoders. */ | |
13893 | intel_crtc_update_dpms(&crtc->base); | |
13894 | ||
83d65738 | 13895 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
13896 | struct intel_encoder *encoder; |
13897 | ||
13898 | /* This can happen either due to bugs in the get_hw_state | |
13899 | * functions or because the pipe is force-enabled due to the | |
13900 | * pipe A quirk. */ | |
13901 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13902 | crtc->base.base.id, | |
83d65738 | 13903 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
13904 | crtc->active ? "enabled" : "disabled"); |
13905 | ||
83d65738 | 13906 | crtc->base.state->enable = crtc->active; |
24929352 DV |
13907 | crtc->base.enabled = crtc->active; |
13908 | ||
13909 | /* Because we only establish the connector -> encoder -> | |
13910 | * crtc links if something is active, this means the | |
13911 | * crtc is now deactivated. Break the links. connector | |
13912 | * -> encoder links are only establish when things are | |
13913 | * actually up, hence no need to break them. */ | |
13914 | WARN_ON(crtc->active); | |
13915 | ||
13916 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13917 | WARN_ON(encoder->connectors_active); | |
13918 | encoder->base.crtc = NULL; | |
13919 | } | |
13920 | } | |
c5ab3bc0 | 13921 | |
a3ed6aad | 13922 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13923 | /* |
13924 | * We start out with underrun reporting disabled to avoid races. | |
13925 | * For correct bookkeeping mark this on active crtcs. | |
13926 | * | |
c5ab3bc0 DV |
13927 | * Also on gmch platforms we dont have any hardware bits to |
13928 | * disable the underrun reporting. Which means we need to start | |
13929 | * out with underrun reporting disabled also on inactive pipes, | |
13930 | * since otherwise we'll complain about the garbage we read when | |
13931 | * e.g. coming up after runtime pm. | |
13932 | * | |
4cc31489 DV |
13933 | * No protection against concurrent access is required - at |
13934 | * worst a fifo underrun happens which also sets this to false. | |
13935 | */ | |
13936 | crtc->cpu_fifo_underrun_disabled = true; | |
13937 | crtc->pch_fifo_underrun_disabled = true; | |
13938 | } | |
24929352 DV |
13939 | } |
13940 | ||
13941 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13942 | { | |
13943 | struct intel_connector *connector; | |
13944 | struct drm_device *dev = encoder->base.dev; | |
13945 | ||
13946 | /* We need to check both for a crtc link (meaning that the | |
13947 | * encoder is active and trying to read from a pipe) and the | |
13948 | * pipe itself being active. */ | |
13949 | bool has_active_crtc = encoder->base.crtc && | |
13950 | to_intel_crtc(encoder->base.crtc)->active; | |
13951 | ||
13952 | if (encoder->connectors_active && !has_active_crtc) { | |
13953 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13954 | encoder->base.base.id, | |
8e329a03 | 13955 | encoder->base.name); |
24929352 DV |
13956 | |
13957 | /* Connector is active, but has no active pipe. This is | |
13958 | * fallout from our resume register restoring. Disable | |
13959 | * the encoder manually again. */ | |
13960 | if (encoder->base.crtc) { | |
13961 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13962 | encoder->base.base.id, | |
8e329a03 | 13963 | encoder->base.name); |
24929352 | 13964 | encoder->disable(encoder); |
a62d1497 VS |
13965 | if (encoder->post_disable) |
13966 | encoder->post_disable(encoder); | |
24929352 | 13967 | } |
7f1950fb EE |
13968 | encoder->base.crtc = NULL; |
13969 | encoder->connectors_active = false; | |
24929352 DV |
13970 | |
13971 | /* Inconsistent output/port/pipe state happens presumably due to | |
13972 | * a bug in one of the get_hw_state functions. Or someplace else | |
13973 | * in our code, like the register restore mess on resume. Clamp | |
13974 | * things to off as a safer default. */ | |
3a3371ff | 13975 | for_each_intel_connector(dev, connector) { |
24929352 DV |
13976 | if (connector->encoder != encoder) |
13977 | continue; | |
7f1950fb EE |
13978 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13979 | connector->base.encoder = NULL; | |
24929352 DV |
13980 | } |
13981 | } | |
13982 | /* Enabled encoders without active connectors will be fixed in | |
13983 | * the crtc fixup. */ | |
13984 | } | |
13985 | ||
04098753 | 13986 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13987 | { |
13988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13989 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13990 | |
04098753 ID |
13991 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13992 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13993 | i915_disable_vga(dev); | |
13994 | } | |
13995 | } | |
13996 | ||
13997 | void i915_redisable_vga(struct drm_device *dev) | |
13998 | { | |
13999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14000 | ||
8dc8a27c PZ |
14001 | /* This function can be called both from intel_modeset_setup_hw_state or |
14002 | * at a very early point in our resume sequence, where the power well | |
14003 | * structures are not yet restored. Since this function is at a very | |
14004 | * paranoid "someone might have enabled VGA while we were not looking" | |
14005 | * level, just check if the power well is enabled instead of trying to | |
14006 | * follow the "don't touch the power well if we don't need it" policy | |
14007 | * the rest of the driver uses. */ | |
f458ebbc | 14008 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14009 | return; |
14010 | ||
04098753 | 14011 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14012 | } |
14013 | ||
98ec7739 VS |
14014 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14015 | { | |
14016 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14017 | ||
14018 | if (!crtc->active) | |
14019 | return false; | |
14020 | ||
14021 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14022 | } | |
14023 | ||
30e984df | 14024 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14025 | { |
14026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14027 | enum pipe pipe; | |
24929352 DV |
14028 | struct intel_crtc *crtc; |
14029 | struct intel_encoder *encoder; | |
14030 | struct intel_connector *connector; | |
5358901f | 14031 | int i; |
24929352 | 14032 | |
d3fcc808 | 14033 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 14034 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14035 | |
6e3c9717 | 14036 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14037 | |
0e8ffe1b | 14038 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14039 | crtc->config); |
24929352 | 14040 | |
83d65738 | 14041 | crtc->base.state->enable = crtc->active; |
24929352 | 14042 | crtc->base.enabled = crtc->active; |
98ec7739 | 14043 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
14044 | |
14045 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14046 | crtc->base.base.id, | |
14047 | crtc->active ? "enabled" : "disabled"); | |
14048 | } | |
14049 | ||
5358901f DV |
14050 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14051 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14052 | ||
3e369b76 ACO |
14053 | pll->on = pll->get_hw_state(dev_priv, pll, |
14054 | &pll->config.hw_state); | |
5358901f | 14055 | pll->active = 0; |
3e369b76 | 14056 | pll->config.crtc_mask = 0; |
d3fcc808 | 14057 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14058 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14059 | pll->active++; |
3e369b76 | 14060 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14061 | } |
5358901f | 14062 | } |
5358901f | 14063 | |
1e6f2ddc | 14064 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14065 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14066 | |
3e369b76 | 14067 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14068 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14069 | } |
14070 | ||
b2784e15 | 14071 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14072 | pipe = 0; |
14073 | ||
14074 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14075 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14076 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14077 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14078 | } else { |
14079 | encoder->base.crtc = NULL; | |
14080 | } | |
14081 | ||
14082 | encoder->connectors_active = false; | |
6f2bcceb | 14083 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14084 | encoder->base.base.id, |
8e329a03 | 14085 | encoder->base.name, |
24929352 | 14086 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14087 | pipe_name(pipe)); |
24929352 DV |
14088 | } |
14089 | ||
3a3371ff | 14090 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14091 | if (connector->get_hw_state(connector)) { |
14092 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14093 | connector->encoder->connectors_active = true; | |
14094 | connector->base.encoder = &connector->encoder->base; | |
14095 | } else { | |
14096 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14097 | connector->base.encoder = NULL; | |
14098 | } | |
14099 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14100 | connector->base.base.id, | |
c23cc417 | 14101 | connector->base.name, |
24929352 DV |
14102 | connector->base.encoder ? "enabled" : "disabled"); |
14103 | } | |
30e984df DV |
14104 | } |
14105 | ||
14106 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14107 | * and i915 state tracking structures. */ | |
14108 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14109 | bool force_restore) | |
14110 | { | |
14111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14112 | enum pipe pipe; | |
30e984df DV |
14113 | struct intel_crtc *crtc; |
14114 | struct intel_encoder *encoder; | |
35c95375 | 14115 | int i; |
30e984df DV |
14116 | |
14117 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14118 | |
babea61d JB |
14119 | /* |
14120 | * Now that we have the config, copy it to each CRTC struct | |
14121 | * Note that this could go away if we move to using crtc_config | |
14122 | * checking everywhere. | |
14123 | */ | |
d3fcc808 | 14124 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14125 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14126 | intel_mode_from_pipe_config(&crtc->base.mode, |
14127 | crtc->config); | |
babea61d JB |
14128 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14129 | crtc->base.base.id); | |
14130 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14131 | } | |
14132 | } | |
14133 | ||
24929352 | 14134 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14135 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14136 | intel_sanitize_encoder(encoder); |
14137 | } | |
14138 | ||
055e393f | 14139 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14140 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14141 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14142 | intel_dump_pipe_config(crtc, crtc->config, |
14143 | "[setup_hw_state]"); | |
24929352 | 14144 | } |
9a935856 | 14145 | |
d29b2f9d ACO |
14146 | intel_modeset_update_connector_atomic_state(dev); |
14147 | ||
35c95375 DV |
14148 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14149 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14150 | ||
14151 | if (!pll->on || pll->active) | |
14152 | continue; | |
14153 | ||
14154 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14155 | ||
14156 | pll->disable(dev_priv, pll); | |
14157 | pll->on = false; | |
14158 | } | |
14159 | ||
3078999f PB |
14160 | if (IS_GEN9(dev)) |
14161 | skl_wm_get_hw_state(dev); | |
14162 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14163 | ilk_wm_get_hw_state(dev); |
14164 | ||
45e2b5f6 | 14165 | if (force_restore) { |
7d0bc1ea VS |
14166 | i915_redisable_vga(dev); |
14167 | ||
f30da187 DV |
14168 | /* |
14169 | * We need to use raw interfaces for restoring state to avoid | |
14170 | * checking (bogus) intermediate states. | |
14171 | */ | |
055e393f | 14172 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14173 | struct drm_crtc *crtc = |
14174 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14175 | |
83a57153 | 14176 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14177 | } |
14178 | } else { | |
14179 | intel_modeset_update_staged_output_state(dev); | |
14180 | } | |
8af6cf88 DV |
14181 | |
14182 | intel_modeset_check_state(dev); | |
2c7111db CW |
14183 | } |
14184 | ||
14185 | void intel_modeset_gem_init(struct drm_device *dev) | |
14186 | { | |
92122789 | 14187 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14188 | struct drm_crtc *c; |
2ff8fde1 | 14189 | struct drm_i915_gem_object *obj; |
484b41dd | 14190 | |
ae48434c ID |
14191 | mutex_lock(&dev->struct_mutex); |
14192 | intel_init_gt_powersave(dev); | |
14193 | mutex_unlock(&dev->struct_mutex); | |
14194 | ||
92122789 JB |
14195 | /* |
14196 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14197 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14198 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14199 | * indicates as much. | |
14200 | */ | |
14201 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14202 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14203 | DREF_SSC1_ENABLE); | |
14204 | ||
1833b134 | 14205 | intel_modeset_init_hw(dev); |
02e792fb DV |
14206 | |
14207 | intel_setup_overlay(dev); | |
484b41dd JB |
14208 | |
14209 | /* | |
14210 | * Make sure any fbs we allocated at startup are properly | |
14211 | * pinned & fenced. When we do the allocation it's too early | |
14212 | * for this. | |
14213 | */ | |
14214 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 14215 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
14216 | obj = intel_fb_obj(c->primary->fb); |
14217 | if (obj == NULL) | |
484b41dd JB |
14218 | continue; |
14219 | ||
850c4cdc TU |
14220 | if (intel_pin_and_fence_fb_obj(c->primary, |
14221 | c->primary->fb, | |
82bc3b2d | 14222 | c->primary->state, |
850c4cdc | 14223 | NULL)) { |
484b41dd JB |
14224 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
14225 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
14226 | drm_framebuffer_unreference(c->primary->fb); |
14227 | c->primary->fb = NULL; | |
afd65eb4 | 14228 | update_state_fb(c->primary); |
484b41dd JB |
14229 | } |
14230 | } | |
14231 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
14232 | |
14233 | intel_backlight_register(dev); | |
79e53945 JB |
14234 | } |
14235 | ||
4932e2c3 ID |
14236 | void intel_connector_unregister(struct intel_connector *intel_connector) |
14237 | { | |
14238 | struct drm_connector *connector = &intel_connector->base; | |
14239 | ||
14240 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 14241 | drm_connector_unregister(connector); |
4932e2c3 ID |
14242 | } |
14243 | ||
79e53945 JB |
14244 | void intel_modeset_cleanup(struct drm_device *dev) |
14245 | { | |
652c393a | 14246 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 14247 | struct drm_connector *connector; |
652c393a | 14248 | |
2eb5252e ID |
14249 | intel_disable_gt_powersave(dev); |
14250 | ||
0962c3c9 VS |
14251 | intel_backlight_unregister(dev); |
14252 | ||
fd0c0642 DV |
14253 | /* |
14254 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 14255 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
14256 | * experience fancy races otherwise. |
14257 | */ | |
2aeb7d3a | 14258 | intel_irq_uninstall(dev_priv); |
eb21b92b | 14259 | |
fd0c0642 DV |
14260 | /* |
14261 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
14262 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
14263 | */ | |
f87ea761 | 14264 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 14265 | |
652c393a JB |
14266 | mutex_lock(&dev->struct_mutex); |
14267 | ||
723bfd70 JB |
14268 | intel_unregister_dsm_handler(); |
14269 | ||
7ff0ebcc | 14270 | intel_fbc_disable(dev); |
e70236a8 | 14271 | |
69341a5e KH |
14272 | mutex_unlock(&dev->struct_mutex); |
14273 | ||
1630fe75 CW |
14274 | /* flush any delayed tasks or pending work */ |
14275 | flush_scheduled_work(); | |
14276 | ||
db31af1d JN |
14277 | /* destroy the backlight and sysfs files before encoders/connectors */ |
14278 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
14279 | struct intel_connector *intel_connector; |
14280 | ||
14281 | intel_connector = to_intel_connector(connector); | |
14282 | intel_connector->unregister(intel_connector); | |
db31af1d | 14283 | } |
d9255d57 | 14284 | |
79e53945 | 14285 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
14286 | |
14287 | intel_cleanup_overlay(dev); | |
ae48434c ID |
14288 | |
14289 | mutex_lock(&dev->struct_mutex); | |
14290 | intel_cleanup_gt_powersave(dev); | |
14291 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14292 | } |
14293 | ||
f1c79df3 ZW |
14294 | /* |
14295 | * Return which encoder is currently attached for connector. | |
14296 | */ | |
df0e9248 | 14297 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 14298 | { |
df0e9248 CW |
14299 | return &intel_attached_encoder(connector)->base; |
14300 | } | |
f1c79df3 | 14301 | |
df0e9248 CW |
14302 | void intel_connector_attach_encoder(struct intel_connector *connector, |
14303 | struct intel_encoder *encoder) | |
14304 | { | |
14305 | connector->encoder = encoder; | |
14306 | drm_mode_connector_attach_encoder(&connector->base, | |
14307 | &encoder->base); | |
79e53945 | 14308 | } |
28d52043 DA |
14309 | |
14310 | /* | |
14311 | * set vga decode state - true == enable VGA decode | |
14312 | */ | |
14313 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
14314 | { | |
14315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 14316 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
14317 | u16 gmch_ctrl; |
14318 | ||
75fa041d CW |
14319 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
14320 | DRM_ERROR("failed to read control word\n"); | |
14321 | return -EIO; | |
14322 | } | |
14323 | ||
c0cc8a55 CW |
14324 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
14325 | return 0; | |
14326 | ||
28d52043 DA |
14327 | if (state) |
14328 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
14329 | else | |
14330 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
14331 | |
14332 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
14333 | DRM_ERROR("failed to write control word\n"); | |
14334 | return -EIO; | |
14335 | } | |
14336 | ||
28d52043 DA |
14337 | return 0; |
14338 | } | |
c4a1d9e4 | 14339 | |
c4a1d9e4 | 14340 | struct intel_display_error_state { |
ff57f1b0 PZ |
14341 | |
14342 | u32 power_well_driver; | |
14343 | ||
63b66e5b CW |
14344 | int num_transcoders; |
14345 | ||
c4a1d9e4 CW |
14346 | struct intel_cursor_error_state { |
14347 | u32 control; | |
14348 | u32 position; | |
14349 | u32 base; | |
14350 | u32 size; | |
52331309 | 14351 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14352 | |
14353 | struct intel_pipe_error_state { | |
ddf9c536 | 14354 | bool power_domain_on; |
c4a1d9e4 | 14355 | u32 source; |
f301b1e1 | 14356 | u32 stat; |
52331309 | 14357 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14358 | |
14359 | struct intel_plane_error_state { | |
14360 | u32 control; | |
14361 | u32 stride; | |
14362 | u32 size; | |
14363 | u32 pos; | |
14364 | u32 addr; | |
14365 | u32 surface; | |
14366 | u32 tile_offset; | |
52331309 | 14367 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
14368 | |
14369 | struct intel_transcoder_error_state { | |
ddf9c536 | 14370 | bool power_domain_on; |
63b66e5b CW |
14371 | enum transcoder cpu_transcoder; |
14372 | ||
14373 | u32 conf; | |
14374 | ||
14375 | u32 htotal; | |
14376 | u32 hblank; | |
14377 | u32 hsync; | |
14378 | u32 vtotal; | |
14379 | u32 vblank; | |
14380 | u32 vsync; | |
14381 | } transcoder[4]; | |
c4a1d9e4 CW |
14382 | }; |
14383 | ||
14384 | struct intel_display_error_state * | |
14385 | intel_display_capture_error_state(struct drm_device *dev) | |
14386 | { | |
fbee40df | 14387 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 14388 | struct intel_display_error_state *error; |
63b66e5b CW |
14389 | int transcoders[] = { |
14390 | TRANSCODER_A, | |
14391 | TRANSCODER_B, | |
14392 | TRANSCODER_C, | |
14393 | TRANSCODER_EDP, | |
14394 | }; | |
c4a1d9e4 CW |
14395 | int i; |
14396 | ||
63b66e5b CW |
14397 | if (INTEL_INFO(dev)->num_pipes == 0) |
14398 | return NULL; | |
14399 | ||
9d1cb914 | 14400 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
14401 | if (error == NULL) |
14402 | return NULL; | |
14403 | ||
190be112 | 14404 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
14405 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
14406 | ||
055e393f | 14407 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 14408 | error->pipe[i].power_domain_on = |
f458ebbc DV |
14409 | __intel_display_power_is_enabled(dev_priv, |
14410 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 14411 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
14412 | continue; |
14413 | ||
5efb3e28 VS |
14414 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
14415 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
14416 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
14417 | |
14418 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
14419 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 14420 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 14421 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
14422 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
14423 | } | |
ca291363 PZ |
14424 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
14425 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
14426 | if (INTEL_INFO(dev)->gen >= 4) { |
14427 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
14428 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
14429 | } | |
14430 | ||
c4a1d9e4 | 14431 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 14432 | |
3abfce77 | 14433 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 14434 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
14435 | } |
14436 | ||
14437 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
14438 | if (HAS_DDI(dev_priv->dev)) | |
14439 | error->num_transcoders++; /* Account for eDP. */ | |
14440 | ||
14441 | for (i = 0; i < error->num_transcoders; i++) { | |
14442 | enum transcoder cpu_transcoder = transcoders[i]; | |
14443 | ||
ddf9c536 | 14444 | error->transcoder[i].power_domain_on = |
f458ebbc | 14445 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 14446 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 14447 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
14448 | continue; |
14449 | ||
63b66e5b CW |
14450 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
14451 | ||
14452 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
14453 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
14454 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
14455 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
14456 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
14457 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
14458 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
14459 | } |
14460 | ||
14461 | return error; | |
14462 | } | |
14463 | ||
edc3d884 MK |
14464 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
14465 | ||
c4a1d9e4 | 14466 | void |
edc3d884 | 14467 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
14468 | struct drm_device *dev, |
14469 | struct intel_display_error_state *error) | |
14470 | { | |
055e393f | 14471 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
14472 | int i; |
14473 | ||
63b66e5b CW |
14474 | if (!error) |
14475 | return; | |
14476 | ||
edc3d884 | 14477 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 14478 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 14479 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 14480 | error->power_well_driver); |
055e393f | 14481 | for_each_pipe(dev_priv, i) { |
edc3d884 | 14482 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
14483 | err_printf(m, " Power: %s\n", |
14484 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 14485 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 14486 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
14487 | |
14488 | err_printf(m, "Plane [%d]:\n", i); | |
14489 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
14490 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 14491 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
14492 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
14493 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 14494 | } |
4b71a570 | 14495 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 14496 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 14497 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
14498 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
14499 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
14500 | } |
14501 | ||
edc3d884 MK |
14502 | err_printf(m, "Cursor [%d]:\n", i); |
14503 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
14504 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
14505 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 14506 | } |
63b66e5b CW |
14507 | |
14508 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 14509 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 14510 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
14511 | err_printf(m, " Power: %s\n", |
14512 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
14513 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
14514 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
14515 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
14516 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
14517 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
14518 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
14519 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
14520 | } | |
c4a1d9e4 | 14521 | } |
e2fcdaa9 VS |
14522 | |
14523 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
14524 | { | |
14525 | struct intel_crtc *crtc; | |
14526 | ||
14527 | for_each_intel_crtc(dev, crtc) { | |
14528 | struct intel_unpin_work *work; | |
e2fcdaa9 | 14529 | |
5e2d7afc | 14530 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14531 | |
14532 | work = crtc->unpin_work; | |
14533 | ||
14534 | if (work && work->event && | |
14535 | work->event->base.file_priv == file) { | |
14536 | kfree(work->event); | |
14537 | work->event = NULL; | |
14538 | } | |
14539 | ||
5e2d7afc | 14540 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14541 | } |
14542 | } |