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drm/i915: remove leaky eDP functions
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
19332d7a
JB		 1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
92f2584a
JB		 1310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311{
1312 u32 val;
1313 bool enabled;
1314
9d82aa17
ED		 1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
92f2584a
JB		 1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324}
1325
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
92f2584a
JB		 1339}
1340
4e634389
KP		 1341static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1343{
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357}
1358
1519b995
KP		 1359static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
dc0fa718 1362 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1367 return false;
1368 } else {
dc0fa718 1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1370 return false;
1371 }
1372 return true;
1373}
1374
1375static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377{
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389}
1390
1391static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393{
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
291906f1 1406static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
291906f1 1408{
47a05eca 1409 u32 val = I915_READ(reg);
4e634389 1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1412 reg, pipe_name(pipe));
de9a35ab 1413
75c5da27
DV		 1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
de9a35ab 1416 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1417}
1418
1419static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421{
47a05eca 1422 u32 val = I915_READ(reg);
b70ad586 1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 reg, pipe_name(pipe));
de9a35ab 1426
dc0fa718 1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1428 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1429 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1430}
1431
1432static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
291906f1 1437
f0575e92
KP		 1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
b70ad586 1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1446 pipe_name(pipe));
291906f1
JB		 1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
b70ad586 1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1452 pipe_name(pipe));
291906f1 1453
e2debe91
PZ		 1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1457}
1458
63d7bbe9
JB		 1459/**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
7434a255
TR		 1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1471 */
1472static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
a0c4da24 1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498}
1499
1500/**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510{
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526}
1527
a416edef
ED		 1528/* SBI access */
1529static void
988d6ee8
PZ		 1530intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
a416edef 1532{
988d6ee8 1533 u32 tmp;
a416edef 1534
09153000 1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1536
39fb50f6 1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1540 return;
a416edef
ED		 1541 }
1542
988d6ee8
PZ		 1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1551
39fb50f6 1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1555 return;
a416edef 1556 }
a416edef
ED		 1557}
1558
1559static u32
988d6ee8
PZ		 1560intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
a416edef 1562{
39fb50f6 1563 u32 value = 0;
09153000 1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1565
39fb50f6 1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1569 return 0;
a416edef
ED		 1570 }
1571
988d6ee8
PZ		 1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1579
39fb50f6 1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1583 return 0;
a416edef
ED		 1584 }
1585
09153000 1586 return I915_READ(SBI_DATA);
a416edef
ED		 1587}
1588
92f2584a 1589/**
b6b4e185 1590 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
b6b4e185 1597static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1598{
ee7b9f93 1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1600 struct intel_pch_pll *pll;
92f2584a
JB		 1601 int reg;
1602 u32 val;
1603
48da64a8 1604 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1605 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
ee7b9f93
JB		 1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
92f2584a
JB		 1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
ee7b9f93 1620 if (pll->active++ && pll->on) {
92b27b08 1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
92f2584a
JB		 1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
ee7b9f93
JB		 1633
1634 pll->on = true;
92f2584a
JB		 1635}
1636
ee7b9f93 1637static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1638{
ee7b9f93
JB		 1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1641 int reg;
ee7b9f93 1642 u32 val;
4c609cb8 1643
92f2584a
JB		 1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1646 if (pll == NULL)
1647 return;
92f2584a 1648
48da64a8
CW		 1649 if (WARN_ON(pll->refcount == 0))
1650 return;
7a419866 1651
ee7b9f93
JB		 1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
7a419866 1655
48da64a8 1656 if (WARN_ON(pll->active == 0)) {
92b27b08 1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1658 return;
1659 }
1660
ee7b9f93 1661 if (--pll->active) {
92b27b08 1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1663 return;
ee7b9f93
JB		 1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1670
ee7b9f93 1671 reg = pll->pll_reg;
92f2584a
JB		 1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
ee7b9f93
JB		 1677
1678 pll->on = false;
92f2584a
JB		 1679}
1680
b8a4f404
PZ		 1681static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
040484af 1683{
23670b32 1684 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1686 uint32_t reg, val, pipeconf_val;
040484af
JB		 1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
040484af
JB		 1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
23670b32
DV		 1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
59c859d6 1707 }
23670b32 1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
5f7f726d 1711 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
dfd07d72
DV		 1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1720 }
5f7f726d
PZ		 1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
040484af
JB		 1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735}
1736
8fb033d7 1737static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1738 enum transcoder cpu_transcoder)
040484af 1739{
8fb033d7 1740 u32 val, pipeconf_val;
8fb033d7
PZ		 1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
8fb033d7 1745 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1748
223a6fdf
PZ		 1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
25f3ef11 1754 val = TRANS_ENABLE;
937bb610 1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1756
9a76b1c6
PZ		 1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
a35f2679 1759 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
25f3ef11 1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1766}
1767
b8a4f404
PZ		 1768static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
040484af 1770{
23670b32
DV		 1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
040484af
JB		 1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
291906f1
JB		 1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
040484af
JB		 1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
040484af
JB		 1796}
1797
ab4d966c 1798static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1799{
8fb033d7
PZ		 1800 u32 val;
1801
8a52fd9f 1802 val = I915_READ(_TRANSACONF);
8fb033d7 1803 val &= ~TRANS_ENABLE;
8a52fd9f 1804 I915_WRITE(_TRANSACONF, val);
8fb033d7 1805 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1812 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1813}
1814
b24e7179 1815/**
309cfea8 1816 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
040484af 1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
040484af
JB		 1829static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
b24e7179 1831{
702e7a56
PZ		 1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1a240d4d 1834 enum pipe pch_transcoder;
b24e7179
JB		 1835 int reg;
1836 u32 val;
1837
681e5811 1838 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
b24e7179
JB		 1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
cc391bbb 1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
040484af
JB		 1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
b24e7179 1859
702e7a56 1860 reg = PIPECONF(cpu_transcoder);
b24e7179 1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
1869/**
309cfea8 1870 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883{
702e7a56
PZ		 1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
b24e7179
JB		 1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
19332d7a 1894 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
702e7a56 1900 reg = PIPECONF(cpu_transcoder);
b24e7179 1901 val = I915_READ(reg);
00d70b15
CW		 1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907}
1908
d74362c9
KP		 1909/*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
6f1d69b0 1913void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1914 enum plane plane)
1915{
14f86147
DL		 1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1920}
1921
b24e7179
JB		 1922/**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
00d70b15
CW		 1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1945 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
b24e7179
JB		 1949/**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959{
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
00d70b15
CW		 1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971}
1972
693db184
CW		 1973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
127bd2ac 1982int
48b956c5 1983intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1984 struct drm_i915_gem_object *obj,
919926ae 1985 struct intel_ring_buffer *pipelined)
6b95a207 1986{
ce453d81 1987 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1988 u32 alignment;
1989 int ret;
1990
05394f39 1991 switch (obj->tiling_mode) {
6b95a207 1992 case I915_TILING_NONE:
534843da
CW		 1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
a6c45cf0 1995 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
6b95a207
KH		 1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
2005 /* FIXME: Is this true? */
2006 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007 return -EINVAL;
2008 default:
2009 BUG();
2010 }
2011
693db184
CW		 2012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2015 * the VT-d warning.
2016 */
2017 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018 alignment = 256 * 1024;
2019
ce453d81 2020 dev_priv->mm.interruptible = false;
2da3b9b9 2021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2022 if (ret)
ce453d81 2023 goto err_interruptible;
6b95a207
KH		 2024
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2029 */
06d98131 2030 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2031 if (ret)
2032 goto err_unpin;
1690e1eb 2033
9a5a53b3 2034 i915_gem_object_pin_fence(obj);
6b95a207 2035
ce453d81 2036 dev_priv->mm.interruptible = true;
6b95a207 2037 return 0;
48b956c5
CW		 2038
2039err_unpin:
2040 i915_gem_object_unpin(obj);
ce453d81
CW		 2041err_interruptible:
2042 dev_priv->mm.interruptible = true;
48b956c5 2043 return ret;
6b95a207
KH		 2044}
2045
1690e1eb
CW		 2046void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2047{
2048 i915_gem_object_unpin_fence(obj);
2049 i915_gem_object_unpin(obj);
2050}
2051
c2c75131
DV		 2052/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053 * is assumed to be a power-of-two. */
bc752862
CW		 2054unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2055 unsigned int tiling_mode,
2056 unsigned int cpp,
2057 unsigned int pitch)
c2c75131 2058{
bc752862
CW		 2059 if (tiling_mode != I915_TILING_NONE) {
2060 unsigned int tile_rows, tiles;
c2c75131 2061
bc752862
CW		 2062 tile_rows = *y / 8;
2063 *y %= 8;
c2c75131 2064
bc752862
CW		 2065 tiles = *x / (512/cpp);
2066 *x %= 512/cpp;
2067
2068 return tile_rows * pitch * 8 + tiles * 4096;
2069 } else {
2070 unsigned int offset;
2071
2072 offset = *y * pitch + *x * cpp;
2073 *y = 0;
2074 *x = (offset & 4095) / cpp;
2075 return offset & -4096;
2076 }
c2c75131
DV		 2077}
2078
17638cd6
JB		 2079static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
81255565
JB		 2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
05394f39 2086 struct drm_i915_gem_object *obj;
81255565 2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
81255565 2089 u32 dspcntr;
5eddb70b 2090 u32 reg;
81255565
JB		 2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
81255565 2103
5eddb70b
CW		 2104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
81255565
JB		 2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2108 switch (fb->pixel_format) {
2109 case DRM_FORMAT_C8:
81255565
JB		 2110 dspcntr |= DISPPLANE_8BPP;
2111 break;
57779d06
VS		 2112 case DRM_FORMAT_XRGB1555:
2113 case DRM_FORMAT_ARGB1555:
2114 dspcntr |= DISPPLANE_BGRX555;
81255565 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
2118 break;
2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2134 break;
2135 default:
baba133a 2136 BUG();
81255565 2137 }
57779d06 2138
a6c45cf0 2139 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2140 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2141 dspcntr |= DISPPLANE_TILED;
2142 else
2143 dspcntr &= ~DISPPLANE_TILED;
2144 }
2145
5eddb70b 2146 I915_WRITE(reg, dspcntr);
81255565 2147
e506a0c6 2148 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2149
c2c75131
DV		 2150 if (INTEL_INFO(dev)->gen >= 4) {
2151 intel_crtc->dspaddr_offset =
bc752862
CW		 2152 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2153 fb->bits_per_pixel / 8,
2154 fb->pitches[0]);
c2c75131
DV		 2155 linear_offset -= intel_crtc->dspaddr_offset;
2156 } else {
e506a0c6 2157 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2158 }
e506a0c6
DV		 2159
2160 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2162 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2163 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2164 I915_MODIFY_DISPBASE(DSPSURF(plane),
2165 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2166 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2167 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2168 } else
e506a0c6 2169 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2170 POSTING_READ(reg);
81255565 2171
17638cd6
JB		 2172 return 0;
2173}
2174
2175static int ironlake_update_plane(struct drm_crtc *crtc,
2176 struct drm_framebuffer *fb, int x, int y)
2177{
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 struct intel_framebuffer *intel_fb;
2182 struct drm_i915_gem_object *obj;
2183 int plane = intel_crtc->plane;
e506a0c6 2184 unsigned long linear_offset;
17638cd6
JB		 2185 u32 dspcntr;
2186 u32 reg;
2187
2188 switch (plane) {
2189 case 0:
2190 case 1:
27f8227b 2191 case 2:
17638cd6
JB		 2192 break;
2193 default:
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 return -EINVAL;
2196 }
2197
2198 intel_fb = to_intel_framebuffer(fb);
2199 obj = intel_fb->obj;
2200
2201 reg = DSPCNTR(plane);
2202 dspcntr = I915_READ(reg);
2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2205 switch (fb->pixel_format) {
2206 case DRM_FORMAT_C8:
17638cd6
JB		 2207 dspcntr |= DISPPLANE_8BPP;
2208 break;
57779d06
VS		 2209 case DRM_FORMAT_RGB565:
2210 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2211 break;
57779d06
VS		 2212 case DRM_FORMAT_XRGB8888:
2213 case DRM_FORMAT_ARGB8888:
2214 dspcntr |= DISPPLANE_BGRX888;
2215 break;
2216 case DRM_FORMAT_XBGR8888:
2217 case DRM_FORMAT_ABGR8888:
2218 dspcntr |= DISPPLANE_RGBX888;
2219 break;
2220 case DRM_FORMAT_XRGB2101010:
2221 case DRM_FORMAT_ARGB2101010:
2222 dspcntr |= DISPPLANE_BGRX101010;
2223 break;
2224 case DRM_FORMAT_XBGR2101010:
2225 case DRM_FORMAT_ABGR2101010:
2226 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2227 break;
2228 default:
baba133a 2229 BUG();
17638cd6
JB		 2230 }
2231
2232 if (obj->tiling_mode != I915_TILING_NONE)
2233 dspcntr |= DISPPLANE_TILED;
2234 else
2235 dspcntr &= ~DISPPLANE_TILED;
2236
2237 /* must disable */
2238 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2239
2240 I915_WRITE(reg, dspcntr);
2241
e506a0c6 2242 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2243 intel_crtc->dspaddr_offset =
bc752862
CW		 2244 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2245 fb->bits_per_pixel / 8,
2246 fb->pitches[0]);
c2c75131 2247 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2248
e506a0c6
DV		 2249 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2251 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2252 I915_MODIFY_DISPBASE(DSPSURF(plane),
2253 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2254 if (IS_HASWELL(dev)) {
2255 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2256 } else {
2257 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2258 I915_WRITE(DSPLINOFF(plane), linear_offset);
2259 }
17638cd6
JB		 2260 POSTING_READ(reg);
2261
2262 return 0;
2263}
2264
2265/* Assume fb object is pinned & idle & fenced and just update base pointers */
2266static int
2267intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2268 int x, int y, enum mode_set_atomic state)
2269{
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2272
6b8e6ed0
CW		 2273 if (dev_priv->display.disable_fbc)
2274 dev_priv->display.disable_fbc(dev);
3dec0095 2275 intel_increase_pllclock(crtc);
81255565 2276
6b8e6ed0 2277 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2278}
2279
96a02917
VS		 2280void intel_display_handle_reset(struct drm_device *dev)
2281{
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_crtc *crtc;
2284
2285 /*
2286 * Flips in the rings have been nuked by the reset,
2287 * so complete all pending flips so that user space
2288 * will get its events and not get stuck.
2289 *
2290 * Also update the base address of all primary
2291 * planes to the the last fb to make sure we're
2292 * showing the correct fb after a reset.
2293 *
2294 * Need to make two loops over the crtcs so that we
2295 * don't try to grab a crtc mutex before the
2296 * pending_flip_queue really got woken up.
2297 */
2298
2299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 enum plane plane = intel_crtc->plane;
2302
2303 intel_prepare_page_flip(dev, plane);
2304 intel_finish_page_flip_plane(dev, plane);
2305 }
2306
2307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
2310 mutex_lock(&crtc->mutex);
2311 if (intel_crtc->active)
2312 dev_priv->display.update_plane(crtc, crtc->fb,
2313 crtc->x, crtc->y);
2314 mutex_unlock(&crtc->mutex);
2315 }
2316}
2317
14667a4b
CW		 2318static int
2319intel_finish_fb(struct drm_framebuffer *old_fb)
2320{
2321 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323 bool was_interruptible = dev_priv->mm.interruptible;
2324 int ret;
2325
14667a4b
CW		 2326 /* Big Hammer, we also need to ensure that any pending
2327 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328 * current scanout is retired before unpinning the old
2329 * framebuffer.
2330 *
2331 * This should only fail upon a hung GPU, in which case we
2332 * can safely continue.
2333 */
2334 dev_priv->mm.interruptible = false;
2335 ret = i915_gem_object_finish_gpu(obj);
2336 dev_priv->mm.interruptible = was_interruptible;
2337
2338 return ret;
2339}
2340
198598d0
VS		 2341static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2342{
2343 struct drm_device *dev = crtc->dev;
2344 struct drm_i915_master_private *master_priv;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346
2347 if (!dev->primary->master)
2348 return;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return;
2353
2354 switch (intel_crtc->pipe) {
2355 case 0:
2356 master_priv->sarea_priv->pipeA_x = x;
2357 master_priv->sarea_priv->pipeA_y = y;
2358 break;
2359 case 1:
2360 master_priv->sarea_priv->pipeB_x = x;
2361 master_priv->sarea_priv->pipeB_y = y;
2362 break;
2363 default:
2364 break;
2365 }
2366}
2367
5c3b82e2 2368static int
3c4fdcfb 2369intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2370 struct drm_framebuffer *fb)
79e53945
JB		 2371{
2372 struct drm_device *dev = crtc->dev;
6b8e6ed0 2373 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2375 struct drm_framebuffer *old_fb;
5c3b82e2 2376 int ret;
79e53945
JB		 2377
2378 /* no fb bound */
94352cf9 2379 if (!fb) {
a5071c2f 2380 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2381 return 0;
2382 }
2383
7eb552ae 2384 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2385 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2386 intel_crtc->plane,
7eb552ae 2387 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2388 return -EINVAL;
79e53945
JB		 2389 }
2390
5c3b82e2 2391 mutex_lock(&dev->struct_mutex);
265db958 2392 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2393 to_intel_framebuffer(fb)->obj,
919926ae 2394 NULL);
5c3b82e2
CW		 2395 if (ret != 0) {
2396 mutex_unlock(&dev->struct_mutex);
a5071c2f 2397 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2398 return ret;
2399 }
79e53945 2400
94352cf9 2401 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2402 if (ret) {
94352cf9 2403 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2404 mutex_unlock(&dev->struct_mutex);
a5071c2f 2405 DRM_ERROR("failed to update base address\n");
4e6cfefc 2406 return ret;
79e53945 2407 }
3c4fdcfb 2408
94352cf9
DV		 2409 old_fb = crtc->fb;
2410 crtc->fb = fb;
6c4c86f5
DV		 2411 crtc->x = x;
2412 crtc->y = y;
94352cf9 2413
b7f1de28
CW		 2414 if (old_fb) {
2415 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2417 }
652c393a 2418
6b8e6ed0 2419 intel_update_fbc(dev);
5c3b82e2 2420 mutex_unlock(&dev->struct_mutex);
79e53945 2421
198598d0 2422 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2423
2424 return 0;
79e53945
JB		 2425}
2426
5e84e1a4
ZW		 2427static void intel_fdi_normal_train(struct drm_crtc *crtc)
2428{
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 int pipe = intel_crtc->pipe;
2433 u32 reg, temp;
2434
2435 /* enable normal train */
2436 reg = FDI_TX_CTL(pipe);
2437 temp = I915_READ(reg);
61e499bf 2438 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2439 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2440 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2441 } else {
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2444 }
5e84e1a4
ZW		 2445 I915_WRITE(reg, temp);
2446
2447 reg = FDI_RX_CTL(pipe);
2448 temp = I915_READ(reg);
2449 if (HAS_PCH_CPT(dev)) {
2450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2452 } else {
2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_NONE;
2455 }
2456 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2457
2458 /* wait one idle pattern time */
2459 POSTING_READ(reg);
2460 udelay(1000);
357555c0
JB		 2461
2462 /* IVB wants error correction enabled */
2463 if (IS_IVYBRIDGE(dev))
2464 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2465 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2466}
2467
01a415fd
DV		 2468static void ivb_modeset_global_resources(struct drm_device *dev)
2469{
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
2477 /* When everything is off disable fdi C so that we could enable fdi B
2478 * with all lanes. XXX: This misses the case where a pipe is not using
2479 * any pch resources and so doesn't need any fdi lanes. */
2480 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2482 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2483
2484 temp = I915_READ(SOUTH_CHICKEN1);
2485 temp &= ~FDI_BC_BIFURCATION_SELECT;
2486 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487 I915_WRITE(SOUTH_CHICKEN1, temp);
2488 }
2489}
2490
8db9d77b
ZW		 2491/* The FDI link training functions for ILK/Ibexpeak. */
2492static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2493{
2494 struct drm_device *dev = crtc->dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497 int pipe = intel_crtc->pipe;
0fc932b8 2498 int plane = intel_crtc->plane;
5eddb70b 2499 u32 reg, temp, tries;
8db9d77b 2500
0fc932b8
JB		 2501 /* FDI needs bits from pipe & plane first */
2502 assert_pipe_enabled(dev_priv, pipe);
2503 assert_plane_enabled(dev_priv, plane);
2504
e1a44743
AJ		 2505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506 for train result */
5eddb70b
CW		 2507 reg = FDI_RX_IMR(pipe);
2508 temp = I915_READ(reg);
e1a44743
AJ		 2509 temp &= ~FDI_RX_SYMBOL_LOCK;
2510 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2511 I915_WRITE(reg, temp);
2512 I915_READ(reg);
e1a44743
AJ		 2513 udelay(150);
2514
8db9d77b 2515 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
77ffb597
AJ		 2518 temp &= ~(7 << 19);
2519 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2523
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(150);
2532
5b2adf89 2533 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2534 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2535 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2536 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2537
5eddb70b 2538 reg = FDI_RX_IIR(pipe);
e1a44743 2539 for (tries = 0; tries < 5; tries++) {
5eddb70b 2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2542
2543 if ((temp & FDI_RX_BIT_LOCK)) {
2544 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2545 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2546 break;
2547 }
8db9d77b 2548 }
e1a44743 2549 if (tries == 5)
5eddb70b 2550 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2551
2552 /* Train 2 */
5eddb70b
CW		 2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
8db9d77b
ZW		 2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2557 I915_WRITE(reg, temp);
8db9d77b 2558
5eddb70b
CW		 2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2563 I915_WRITE(reg, temp);
8db9d77b 2564
5eddb70b
CW		 2565 POSTING_READ(reg);
2566 udelay(150);
8db9d77b 2567
5eddb70b 2568 reg = FDI_RX_IIR(pipe);
e1a44743 2569 for (tries = 0; tries < 5; tries++) {
5eddb70b 2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2576 break;
2577 }
8db9d77b 2578 }
e1a44743 2579 if (tries == 5)
5eddb70b 2580 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2581
2582 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2583
8db9d77b
ZW		 2584}
2585
0206e353 2586static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2587 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2588 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2589 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2590 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2591};
2592
2593/* The FDI link training functions for SNB/Cougarpoint. */
2594static void gen6_fdi_link_train(struct drm_crtc *crtc)
2595{
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
fa37d39e 2600 u32 reg, temp, i, retry;
8db9d77b 2601
e1a44743
AJ		 2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603 for train result */
5eddb70b
CW		 2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
e1a44743
AJ		 2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
e1a44743
AJ		 2611 udelay(150);
2612
8db9d77b 2613 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2614 reg = FDI_TX_CTL(pipe);
2615 temp = I915_READ(reg);
77ffb597
AJ		 2616 temp &= ~(7 << 19);
2617 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_1;
2620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621 /* SNB-B */
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2624
d74cf324
DV		 2625 I915_WRITE(FDI_RX_MISC(pipe),
2626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
5eddb70b
CW		 2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
8db9d77b
ZW		 2630 if (HAS_PCH_CPT(dev)) {
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633 } else {
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1;
2636 }
5eddb70b
CW		 2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
8db9d77b
ZW		 2640 udelay(150);
2641
0206e353 2642 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
8db9d77b
ZW		 2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
8db9d77b
ZW		 2650 udelay(500);
2651
fa37d39e
SP		 2652 for (retry = 0; retry < 5; retry++) {
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656 if (temp & FDI_RX_BIT_LOCK) {
2657 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2659 break;
2660 }
2661 udelay(50);
8db9d77b 2662 }
fa37d39e
SP		 2663 if (retry < 5)
2664 break;
8db9d77b
ZW		 2665 }
2666 if (i == 4)
5eddb70b 2667 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2668
2669 /* Train 2 */
5eddb70b
CW		 2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
8db9d77b
ZW		 2672 temp &= ~FDI_LINK_TRAIN_NONE;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2;
2674 if (IS_GEN6(dev)) {
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 /* SNB-B */
2677 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678 }
5eddb70b 2679 I915_WRITE(reg, temp);
8db9d77b 2680
5eddb70b
CW		 2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
8db9d77b
ZW		 2683 if (HAS_PCH_CPT(dev)) {
2684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2686 } else {
2687 temp &= ~FDI_LINK_TRAIN_NONE;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2;
2689 }
5eddb70b
CW		 2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
8db9d77b
ZW		 2693 udelay(150);
2694
0206e353 2695 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
8db9d77b
ZW		 2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2700 I915_WRITE(reg, temp);
2701
2702 POSTING_READ(reg);
8db9d77b
ZW		 2703 udelay(500);
2704
fa37d39e
SP		 2705 for (retry = 0; retry < 5; retry++) {
2706 reg = FDI_RX_IIR(pipe);
2707 temp = I915_READ(reg);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712 break;
2713 }
2714 udelay(50);
8db9d77b 2715 }
fa37d39e
SP		 2716 if (retry < 5)
2717 break;
8db9d77b
ZW		 2718 }
2719 if (i == 4)
5eddb70b 2720 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2721
2722 DRM_DEBUG_KMS("FDI train done.\n");
2723}
2724
357555c0
JB		 2725/* Manual link training for Ivy Bridge A0 parts */
2726static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2727{
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp, i;
2733
2734 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2735 for train result */
2736 reg = FDI_RX_IMR(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_RX_SYMBOL_LOCK;
2739 temp &= ~FDI_RX_BIT_LOCK;
2740 I915_WRITE(reg, temp);
2741
2742 POSTING_READ(reg);
2743 udelay(150);
2744
01a415fd
DV		 2745 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746 I915_READ(FDI_RX_IIR(pipe)));
2747
357555c0
JB		 2748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(7 << 19);
2752 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2753 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2754 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2757 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2758 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759
d74cf324
DV		 2760 I915_WRITE(FDI_RX_MISC(pipe),
2761 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762
357555c0
JB		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~FDI_LINK_TRAIN_AUTO;
2766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2768 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2769 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(150);
2773
0206e353 2774 for (i = 0; i < 4; i++) {
357555c0
JB		 2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778 temp |= snb_b_fdi_train_param[i];
2779 I915_WRITE(reg, temp);
2780
2781 POSTING_READ(reg);
2782 udelay(500);
2783
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788 if (temp & FDI_RX_BIT_LOCK ||
2789 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2792 break;
2793 }
2794 }
2795 if (i == 4)
2796 DRM_ERROR("FDI train 1 fail!\n");
2797
2798 /* Train 2 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2802 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2803 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2804 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2805 I915_WRITE(reg, temp);
2806
2807 reg = FDI_RX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2811 I915_WRITE(reg, temp);
2812
2813 POSTING_READ(reg);
2814 udelay(150);
2815
0206e353 2816 for (i = 0; i < 4; i++) {
357555c0
JB		 2817 reg = FDI_TX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2820 temp |= snb_b_fdi_train_param[i];
2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(500);
2825
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830 if (temp & FDI_RX_SYMBOL_LOCK) {
2831 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2832 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2833 break;
2834 }
2835 }
2836 if (i == 4)
2837 DRM_ERROR("FDI train 2 fail!\n");
2838
2839 DRM_DEBUG_KMS("FDI train done.\n");
2840}
2841
88cefb6c 2842static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2843{
88cefb6c 2844 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2845 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2846 int pipe = intel_crtc->pipe;
5eddb70b 2847 u32 reg, temp;
79e53945 2848
c64e311e 2849
c98e9dcf 2850 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2854 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2856 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2857
2858 POSTING_READ(reg);
c98e9dcf
JB		 2859 udelay(200);
2860
2861 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2862 temp = I915_READ(reg);
2863 I915_WRITE(reg, temp | FDI_PCDCLK);
2864
2865 POSTING_READ(reg);
c98e9dcf
JB		 2866 udelay(200);
2867
20749730
PZ		 2868 /* Enable CPU FDI TX PLL, always on for Ironlake */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2872 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2873
20749730
PZ		 2874 POSTING_READ(reg);
2875 udelay(100);
6be4a607 2876 }
0e23b99d
JB		 2877}
2878
88cefb6c
DV		 2879static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880{
2881 struct drm_device *dev = intel_crtc->base.dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 int pipe = intel_crtc->pipe;
2884 u32 reg, temp;
2885
2886 /* Switch from PCDclk to Rawclk */
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890
2891 /* Disable CPU FDI TX PLL */
2892 reg = FDI_TX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2895
2896 POSTING_READ(reg);
2897 udelay(100);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902
2903 /* Wait for the clocks to turn off. */
2904 POSTING_READ(reg);
2905 udelay(100);
2906}
2907
0fc932b8
JB		 2908static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909{
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913 int pipe = intel_crtc->pipe;
2914 u32 reg, temp;
2915
2916 /* disable CPU FDI tx and PCH FDI rx */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2920 POSTING_READ(reg);
2921
2922 reg = FDI_RX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~(0x7 << 16);
dfd07d72 2925 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2926 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2927
2928 POSTING_READ(reg);
2929 udelay(100);
2930
2931 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2932 if (HAS_PCH_IBX(dev)) {
2933 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2934 }
0fc932b8
JB		 2935
2936 /* still set train pattern 1 */
2937 reg = FDI_TX_CTL(pipe);
2938 temp = I915_READ(reg);
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 I915_WRITE(reg, temp);
2942
2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 if (HAS_PCH_CPT(dev)) {
2946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 } else {
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 }
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp &= ~(0x07 << 16);
dfd07d72 2954 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959}
2960
5bb61643
CW		 2961static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962{
2963 struct drm_device *dev = crtc->dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2966 unsigned long flags;
2967 bool pending;
2968
10d83730
VS		 2969 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2970 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2971 return false;
2972
2973 spin_lock_irqsave(&dev->event_lock, flags);
2974 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2975 spin_unlock_irqrestore(&dev->event_lock, flags);
2976
2977 return pending;
2978}
2979
e6c3a2a6
CW		 2980static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981{
0f91128d 2982 struct drm_device *dev = crtc->dev;
5bb61643 2983 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2984
2985 if (crtc->fb == NULL)
2986 return;
2987
2c10d571
DV		 2988 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989
5bb61643
CW		 2990 wait_event(dev_priv->pending_flip_queue,
2991 !intel_crtc_has_pending_flip(crtc));
2992
0f91128d
CW		 2993 mutex_lock(&dev->struct_mutex);
2994 intel_finish_fb(crtc->fb);
2995 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2996}
2997
fc316cbe
PZ		 2998static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999{
3000 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001}
3002
e615efe4
ED		 3003/* Program iCLKIP clock to the desired frequency */
3004static void lpt_program_iclkip(struct drm_crtc *crtc)
3005{
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009 u32 temp;
3010
09153000
DV		 3011 mutex_lock(&dev_priv->dpio_lock);
3012
e615efe4
ED		 3013 /* It is necessary to ungate the pixclk gate prior to programming
3014 * the divisors, and gate it back when it is done.
3015 */
3016 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3017
3018 /* Disable SSCCTL */
3019 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3020 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3021 SBI_SSCCTL_DISABLE,
3022 SBI_ICLK);
e615efe4
ED		 3023
3024 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3025 if (crtc->mode.clock == 20000) {
3026 auxdiv = 1;
3027 divsel = 0x41;
3028 phaseinc = 0x20;
3029 } else {
3030 /* The iCLK virtual clock root frequency is in MHz,
3031 * but the crtc->mode.clock in in KHz. To get the divisors,
3032 * it is necessary to divide one by another, so we
3033 * convert the virtual clock precision to KHz here for higher
3034 * precision.
3035 */
3036 u32 iclk_virtual_root_freq = 172800 * 1000;
3037 u32 iclk_pi_range = 64;
3038 u32 desired_divisor, msb_divisor_value, pi_value;
3039
3040 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3041 msb_divisor_value = desired_divisor / iclk_pi_range;
3042 pi_value = desired_divisor % iclk_pi_range;
3043
3044 auxdiv = 0;
3045 divsel = msb_divisor_value - 2;
3046 phaseinc = pi_value;
3047 }
3048
3049 /* This should not happen with any sane values */
3050 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3051 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3052 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3053 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3054
3055 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3056 crtc->mode.clock,
3057 auxdiv,
3058 divsel,
3059 phasedir,
3060 phaseinc);
3061
3062 /* Program SSCDIVINTPHASE6 */
988d6ee8 3063 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3064 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3065 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3066 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3067 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3068 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3069 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3070 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3071
3072 /* Program SSCAUXDIV */
988d6ee8 3073 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3074 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3076 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3077
3078 /* Enable modulator and associated divider */
988d6ee8 3079 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3080 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3081 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3082
3083 /* Wait for initialization time */
3084 udelay(24);
3085
3086 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3087
3088 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3089}
3090
f67a559d
JB		 3091/*
3092 * Enable PCH resources required for PCH ports:
3093 * - PCH PLLs
3094 * - FDI training & RX/TX
3095 * - update transcoder timings
3096 * - DP transcoding bits
3097 * - transcoder
3098 */
3099static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3100{
3101 struct drm_device *dev = crtc->dev;
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104 int pipe = intel_crtc->pipe;
ee7b9f93 3105 u32 reg, temp;
2c07245f 3106
e7e164db
CW		 3107 assert_transcoder_disabled(dev_priv, pipe);
3108
cd986abb
DV		 3109 /* Write the TU size bits before fdi link training, so that error
3110 * detection works. */
3111 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3112 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3113
c98e9dcf 3114 /* For PCH output, training FDI link */
674cf967 3115 dev_priv->display.fdi_link_train(crtc);
2c07245f 3116
572deb37
DV		 3117 /* XXX: pch pll's can be enabled any time before we enable the PCH
3118 * transcoder, and we actually should do this to not upset any PCH
3119 * transcoder that already use the clock when we share it.
3120 *
3121 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3122 * unconditionally resets the pll - we need that to have the right LVDS
3123 * enable sequence. */
b6b4e185 3124 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3125
303b81e0 3126 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3127 u32 sel;
4b645f14 3128
c98e9dcf 3129 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3130 switch (pipe) {
3131 default:
3132 case 0:
3133 temp |= TRANSA_DPLL_ENABLE;
3134 sel = TRANSA_DPLLB_SEL;
3135 break;
3136 case 1:
3137 temp |= TRANSB_DPLL_ENABLE;
3138 sel = TRANSB_DPLLB_SEL;
3139 break;
3140 case 2:
3141 temp |= TRANSC_DPLL_ENABLE;
3142 sel = TRANSC_DPLLB_SEL;
3143 break;
d64311ab 3144 }
ee7b9f93
JB		 3145 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3146 temp |= sel;
3147 else
3148 temp &= ~sel;
c98e9dcf 3149 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3150 }
5eddb70b 3151
d9b6cb56
JB		 3152 /* set transcoder timing, panel must allow it */
3153 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3154 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3155 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3156 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3157
5eddb70b
CW		 3158 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3159 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3160 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3161 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3162
303b81e0 3163 intel_fdi_normal_train(crtc);
5e84e1a4 3164
c98e9dcf
JB		 3165 /* For PCH DP, enable TRANS_DP_CTL */
3166 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3167 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3168 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3169 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3170 reg = TRANS_DP_CTL(pipe);
3171 temp = I915_READ(reg);
3172 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3173 TRANS_DP_SYNC_MASK |
3174 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3175 temp |= (TRANS_DP_OUTPUT_ENABLE |
3176 TRANS_DP_ENH_FRAMING);
9325c9f0 3177 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3178
3179 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3180 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3181 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3182 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3183
3184 switch (intel_trans_dp_port_sel(crtc)) {
3185 case PCH_DP_B:
5eddb70b 3186 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3187 break;
3188 case PCH_DP_C:
5eddb70b 3189 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3190 break;
3191 case PCH_DP_D:
5eddb70b 3192 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3193 break;
3194 default:
e95d41e1 3195 BUG();
32f9d658 3196 }
2c07245f 3197
5eddb70b 3198 I915_WRITE(reg, temp);
6be4a607 3199 }
b52eb4dc 3200
b8a4f404 3201 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3202}
3203
1507e5bd
PZ		 3204static void lpt_pch_enable(struct drm_crtc *crtc)
3205{
3206 struct drm_device *dev = crtc->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3209 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3210
daed2dbb 3211 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3212
8c52b5e8 3213 lpt_program_iclkip(crtc);
1507e5bd 3214
0540e488 3215 /* Set transcoder timing. */
daed2dbb
PZ		 3216 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3217 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3218 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3219
daed2dbb
PZ		 3220 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3221 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3222 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3223 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3224
937bb610 3225 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3226}
3227
ee7b9f93
JB		 3228static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3229{
3230 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3231
3232 if (pll == NULL)
3233 return;
3234
3235 if (pll->refcount == 0) {
3236 WARN(1, "bad PCH PLL refcount\n");
3237 return;
3238 }
3239
3240 --pll->refcount;
3241 intel_crtc->pch_pll = NULL;
3242}
3243
3244static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3245{
3246 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3247 struct intel_pch_pll *pll;
3248 int i;
3249
3250 pll = intel_crtc->pch_pll;
3251 if (pll) {
3252 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3253 intel_crtc->base.base.id, pll->pll_reg);
3254 goto prepare;
3255 }
3256
98b6bd99
DV		 3257 if (HAS_PCH_IBX(dev_priv->dev)) {
3258 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3259 i = intel_crtc->pipe;
3260 pll = &dev_priv->pch_plls[i];
3261
3262 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3263 intel_crtc->base.base.id, pll->pll_reg);
3264
3265 goto found;
3266 }
3267
ee7b9f93
JB		 3268 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3269 pll = &dev_priv->pch_plls[i];
3270
3271 /* Only want to check enabled timings first */
3272 if (pll->refcount == 0)
3273 continue;
3274
3275 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3276 fp == I915_READ(pll->fp0_reg)) {
3277 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3278 intel_crtc->base.base.id,
3279 pll->pll_reg, pll->refcount, pll->active);
3280
3281 goto found;
3282 }
3283 }
3284
3285 /* Ok no matching timings, maybe there's a free one? */
3286 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3287 pll = &dev_priv->pch_plls[i];
3288 if (pll->refcount == 0) {
3289 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3290 intel_crtc->base.base.id, pll->pll_reg);
3291 goto found;
3292 }
3293 }
3294
3295 return NULL;
3296
3297found:
3298 intel_crtc->pch_pll = pll;
3299 pll->refcount++;
3300 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3301prepare: /* separate function? */
3302 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3303
e04c7350
CW		 3304 /* Wait for the clocks to stabilize before rewriting the regs */
3305 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3306 POSTING_READ(pll->pll_reg);
3307 udelay(150);
e04c7350
CW		 3308
3309 I915_WRITE(pll->fp0_reg, fp);
3310 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3311 pll->on = false;
3312 return pll;
3313}
3314
d4270e57
JB		 3315void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3316{
3317 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3318 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3319 u32 temp;
3320
3321 temp = I915_READ(dslreg);
3322 udelay(500);
3323 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3324 if (wait_for(I915_READ(dslreg) != temp, 5))
3325 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3326 }
3327}
3328
f67a559d
JB		 3329static void ironlake_crtc_enable(struct drm_crtc *crtc)
3330{
3331 struct drm_device *dev = crtc->dev;
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3334 struct intel_encoder *encoder;
f67a559d
JB		 3335 int pipe = intel_crtc->pipe;
3336 int plane = intel_crtc->plane;
3337 u32 temp;
f67a559d 3338
08a48469
DV		 3339 WARN_ON(!crtc->enabled);
3340
f67a559d
JB		 3341 if (intel_crtc->active)
3342 return;
3343
3344 intel_crtc->active = true;
3345 intel_update_watermarks(dev);
3346
3347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3348 temp = I915_READ(PCH_LVDS);
3349 if ((temp & LVDS_PORT_EN) == 0)
3350 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3351 }
3352
f67a559d 3353
5bfe2ac0 3354 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3355 /* Note: FDI PLL enabling _must_ be done before we enable the
3356 * cpu pipes, hence this is separate from all the other fdi/pch
3357 * enabling. */
88cefb6c 3358 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3359 } else {
3360 assert_fdi_tx_disabled(dev_priv, pipe);
3361 assert_fdi_rx_disabled(dev_priv, pipe);
3362 }
f67a559d 3363
bf49ec8c
DV		 3364 for_each_encoder_on_crtc(dev, crtc, encoder)
3365 if (encoder->pre_enable)
3366 encoder->pre_enable(encoder);
f67a559d
JB		 3367
3368 /* Enable panel fitting for LVDS */
3369 if (dev_priv->pch_pf_size &&
547dc041
JN		 3370 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3371 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3372 /* Force use of hard-coded filter coefficients
3373 * as some pre-programmed values are broken,
3374 * e.g. x201.
3375 */
13888d78
PZ		 3376 if (IS_IVYBRIDGE(dev))
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3378 PF_PIPE_SEL_IVB(pipe));
3379 else
3380 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3381 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3382 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3383 }
3384
9c54c0dd
JB		 3385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
5bfe2ac0
DV		 3391 intel_enable_pipe(dev_priv, pipe,
3392 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3393 intel_enable_plane(dev_priv, plane, pipe);
3394
5bfe2ac0 3395 if (intel_crtc->config.has_pch_encoder)
f67a559d 3396 ironlake_pch_enable(crtc);
c98e9dcf 3397
d1ebd816 3398 mutex_lock(&dev->struct_mutex);
bed4a673 3399 intel_update_fbc(dev);
d1ebd816
BW		 3400 mutex_unlock(&dev->struct_mutex);
3401
6b383a7f 3402 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3403
fa5c73b1
DV		 3404 for_each_encoder_on_crtc(dev, crtc, encoder)
3405 encoder->enable(encoder);
61b77ddd
DV		 3406
3407 if (HAS_PCH_CPT(dev))
3408 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3409
3410 /*
3411 * There seems to be a race in PCH platform hw (at least on some
3412 * outputs) where an enabled pipe still completes any pageflip right
3413 * away (as if the pipe is off) instead of waiting for vblank. As soon
3414 * as the first vblank happend, everything works as expected. Hence just
3415 * wait for one vblank before returning to avoid strange things
3416 * happening.
3417 */
3418 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3419}
3420
4f771f10
PZ		 3421static void haswell_crtc_enable(struct drm_crtc *crtc)
3422{
3423 struct drm_device *dev = crtc->dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426 struct intel_encoder *encoder;
3427 int pipe = intel_crtc->pipe;
3428 int plane = intel_crtc->plane;
4f771f10
PZ		 3429
3430 WARN_ON(!crtc->enabled);
3431
3432 if (intel_crtc->active)
3433 return;
3434
3435 intel_crtc->active = true;
3436 intel_update_watermarks(dev);
3437
5bfe2ac0 3438 if (intel_crtc->config.has_pch_encoder)
04945641 3439 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3440
3441 for_each_encoder_on_crtc(dev, crtc, encoder)
3442 if (encoder->pre_enable)
3443 encoder->pre_enable(encoder);
3444
1f544388 3445 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3446
1f544388 3447 /* Enable panel fitting for eDP */
547dc041
JN		 3448 if (dev_priv->pch_pf_size &&
3449 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3450 /* Force use of hard-coded filter coefficients
3451 * as some pre-programmed values are broken,
3452 * e.g. x201.
3453 */
54075a7d
PZ		 3454 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3455 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3456 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3457 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3458 }
3459
3460 /*
3461 * On ILK+ LUT must be loaded before the pipe is running but with
3462 * clocks enabled
3463 */
3464 intel_crtc_load_lut(crtc);
3465
1f544388 3466 intel_ddi_set_pipe_settings(crtc);
8228c251 3467 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3468
5bfe2ac0
DV		 3469 intel_enable_pipe(dev_priv, pipe,
3470 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3471 intel_enable_plane(dev_priv, plane, pipe);
3472
5bfe2ac0 3473 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3474 lpt_pch_enable(crtc);
4f771f10
PZ		 3475
3476 mutex_lock(&dev->struct_mutex);
3477 intel_update_fbc(dev);
3478 mutex_unlock(&dev->struct_mutex);
3479
3480 intel_crtc_update_cursor(crtc, true);
3481
3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 encoder->enable(encoder);
3484
4f771f10
PZ		 3485 /*
3486 * There seems to be a race in PCH platform hw (at least on some
3487 * outputs) where an enabled pipe still completes any pageflip right
3488 * away (as if the pipe is off) instead of waiting for vblank. As soon
3489 * as the first vblank happend, everything works as expected. Hence just
3490 * wait for one vblank before returning to avoid strange things
3491 * happening.
3492 */
3493 intel_wait_for_vblank(dev, intel_crtc->pipe);
3494}
3495
6be4a607
JB		 3496static void ironlake_crtc_disable(struct drm_crtc *crtc)
3497{
3498 struct drm_device *dev = crtc->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3501 struct intel_encoder *encoder;
6be4a607
JB		 3502 int pipe = intel_crtc->pipe;
3503 int plane = intel_crtc->plane;
5eddb70b 3504 u32 reg, temp;
b52eb4dc 3505
ef9c3aee 3506
f7abfe8b
CW		 3507 if (!intel_crtc->active)
3508 return;
3509
ea9d758d
DV		 3510 for_each_encoder_on_crtc(dev, crtc, encoder)
3511 encoder->disable(encoder);
3512
e6c3a2a6 3513 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3514 drm_vblank_off(dev, pipe);
6b383a7f 3515 intel_crtc_update_cursor(crtc, false);
5eddb70b 3516
b24e7179 3517 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3518
973d04f9
CW		 3519 if (dev_priv->cfb_plane == plane)
3520 intel_disable_fbc(dev);
2c07245f 3521
b24e7179 3522 intel_disable_pipe(dev_priv, pipe);
32f9d658 3523
6be4a607 3524 /* Disable PF */
9db4a9c7
JB		 3525 I915_WRITE(PF_CTL(pipe), 0);
3526 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3527
bf49ec8c
DV		 3528 for_each_encoder_on_crtc(dev, crtc, encoder)
3529 if (encoder->post_disable)
3530 encoder->post_disable(encoder);
2c07245f 3531
0fc932b8 3532 ironlake_fdi_disable(crtc);
249c0e64 3533
b8a4f404 3534 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3535
6be4a607
JB		 3536 if (HAS_PCH_CPT(dev)) {
3537 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3538 reg = TRANS_DP_CTL(pipe);
3539 temp = I915_READ(reg);
3540 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3541 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3542 I915_WRITE(reg, temp);
6be4a607
JB		 3543
3544 /* disable DPLL_SEL */
3545 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3546 switch (pipe) {
3547 case 0:
d64311ab 3548 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3549 break;
3550 case 1:
6be4a607 3551 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3552 break;
3553 case 2:
4b645f14 3554 /* C shares PLL A or B */
d64311ab 3555 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3556 break;
3557 default:
3558 BUG(); /* wtf */
3559 }
6be4a607 3560 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3561 }
e3421a18 3562
6be4a607 3563 /* disable PCH DPLL */
ee7b9f93 3564 intel_disable_pch_pll(intel_crtc);
8db9d77b 3565
88cefb6c 3566 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3567
f7abfe8b 3568 intel_crtc->active = false;
6b383a7f 3569 intel_update_watermarks(dev);
d1ebd816
BW		 3570
3571 mutex_lock(&dev->struct_mutex);
6b383a7f 3572 intel_update_fbc(dev);
d1ebd816 3573 mutex_unlock(&dev->struct_mutex);
6be4a607 3574}
1b3c7a47 3575
4f771f10 3576static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3577{
4f771f10
PZ		 3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3581 struct intel_encoder *encoder;
3582 int pipe = intel_crtc->pipe;
3583 int plane = intel_crtc->plane;
ad80a810 3584 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3585 bool is_pch_port;
ee7b9f93 3586
4f771f10
PZ		 3587 if (!intel_crtc->active)
3588 return;
3589
83616634
PZ		 3590 is_pch_port = haswell_crtc_driving_pch(crtc);
3591
4f771f10
PZ		 3592 for_each_encoder_on_crtc(dev, crtc, encoder)
3593 encoder->disable(encoder);
3594
3595 intel_crtc_wait_for_pending_flips(crtc);
3596 drm_vblank_off(dev, pipe);
3597 intel_crtc_update_cursor(crtc, false);
3598
3599 intel_disable_plane(dev_priv, plane, pipe);
3600
3601 if (dev_priv->cfb_plane == plane)
3602 intel_disable_fbc(dev);
3603
3604 intel_disable_pipe(dev_priv, pipe);
3605
ad80a810 3606 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3607
3608 /* Disable PF */
3609 I915_WRITE(PF_CTL(pipe), 0);
3610 I915_WRITE(PF_WIN_SZ(pipe), 0);
3611
1f544388 3612 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3613
3614 for_each_encoder_on_crtc(dev, crtc, encoder)
3615 if (encoder->post_disable)
3616 encoder->post_disable(encoder);
3617
83616634 3618 if (is_pch_port) {
ab4d966c 3619 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3620 intel_ddi_fdi_disable(crtc);
83616634 3621 }
4f771f10
PZ		 3622
3623 intel_crtc->active = false;
3624 intel_update_watermarks(dev);
3625
3626 mutex_lock(&dev->struct_mutex);
3627 intel_update_fbc(dev);
3628 mutex_unlock(&dev->struct_mutex);
3629}
3630
ee7b9f93
JB		 3631static void ironlake_crtc_off(struct drm_crtc *crtc)
3632{
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634 intel_put_pch_pll(intel_crtc);
3635}
3636
6441ab5f
PZ		 3637static void haswell_crtc_off(struct drm_crtc *crtc)
3638{
a5c961d1
PZ		 3639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640
3641 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3642 * start using it. */
1a240d4d 3643 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3644
6441ab5f
PZ		 3645 intel_ddi_put_crtc_pll(crtc);
3646}
3647
02e792fb
DV		 3648static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3649{
02e792fb 3650 if (!enable && intel_crtc->overlay) {
23f09ce3 3651 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3652 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3653
23f09ce3 3654 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3655 dev_priv->mm.interruptible = false;
3656 (void) intel_overlay_switch_off(intel_crtc->overlay);
3657 dev_priv->mm.interruptible = true;
23f09ce3 3658 mutex_unlock(&dev->struct_mutex);
02e792fb 3659 }
02e792fb 3660
5dcdbcb0
CW		 3661 /* Let userspace switch the overlay on again. In most cases userspace
3662 * has to recompute where to put it anyway.
3663 */
02e792fb
DV		 3664}
3665
61bc95c1
EE		 3666/**
3667 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3668 * cursor plane briefly if not already running after enabling the display
3669 * plane.
3670 * This workaround avoids occasional blank screens when self refresh is
3671 * enabled.
3672 */
3673static void
3674g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3675{
3676 u32 cntl = I915_READ(CURCNTR(pipe));
3677
3678 if ((cntl & CURSOR_MODE) == 0) {
3679 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3680
3681 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3682 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3683 intel_wait_for_vblank(dev_priv->dev, pipe);
3684 I915_WRITE(CURCNTR(pipe), cntl);
3685 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3686 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3687 }
3688}
3689
0b8765c6 3690static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3691{
3692 struct drm_device *dev = crtc->dev;
79e53945
JB		 3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3695 struct intel_encoder *encoder;
79e53945 3696 int pipe = intel_crtc->pipe;
80824003 3697 int plane = intel_crtc->plane;
79e53945 3698
08a48469
DV		 3699 WARN_ON(!crtc->enabled);
3700
f7abfe8b
CW		 3701 if (intel_crtc->active)
3702 return;
3703
3704 intel_crtc->active = true;
6b383a7f
CW		 3705 intel_update_watermarks(dev);
3706
63d7bbe9 3707 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3708
3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 if (encoder->pre_enable)
3711 encoder->pre_enable(encoder);
3712
040484af 3713 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3714 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3715 if (IS_G4X(dev))
3716 g4x_fixup_plane(dev_priv, pipe);
79e53945 3717
0b8765c6 3718 intel_crtc_load_lut(crtc);
bed4a673 3719 intel_update_fbc(dev);
79e53945 3720
0b8765c6
JB		 3721 /* Give the overlay scaler a chance to enable if it's on this pipe */
3722 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3723 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3724
fa5c73b1
DV		 3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
0b8765c6 3727}
79e53945 3728
0b8765c6
JB		 3729static void i9xx_crtc_disable(struct drm_crtc *crtc)
3730{
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3734 struct intel_encoder *encoder;
0b8765c6
JB		 3735 int pipe = intel_crtc->pipe;
3736 int plane = intel_crtc->plane;
24a1f16d 3737 u32 pctl;
b690e96c 3738
ef9c3aee 3739
f7abfe8b
CW		 3740 if (!intel_crtc->active)
3741 return;
3742
ea9d758d
DV		 3743 for_each_encoder_on_crtc(dev, crtc, encoder)
3744 encoder->disable(encoder);
3745
0b8765c6 3746 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3747 intel_crtc_wait_for_pending_flips(crtc);
3748 drm_vblank_off(dev, pipe);
0b8765c6 3749 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3750 intel_crtc_update_cursor(crtc, false);
0b8765c6 3751
973d04f9
CW		 3752 if (dev_priv->cfb_plane == plane)
3753 intel_disable_fbc(dev);
79e53945 3754
b24e7179 3755 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3756 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3757
3758 /* Disable pannel fitter if it is on this pipe. */
3759 pctl = I915_READ(PFIT_CONTROL);
3760 if ((pctl & PFIT_ENABLE) &&
3761 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3762 I915_WRITE(PFIT_CONTROL, 0);
3763
63d7bbe9 3764 intel_disable_pll(dev_priv, pipe);
0b8765c6 3765
f7abfe8b 3766 intel_crtc->active = false;
6b383a7f
CW		 3767 intel_update_fbc(dev);
3768 intel_update_watermarks(dev);
0b8765c6
JB		 3769}
3770
ee7b9f93
JB		 3771static void i9xx_crtc_off(struct drm_crtc *crtc)
3772{
3773}
3774
976f8a20
DV		 3775static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3776 bool enabled)
2c07245f
ZW		 3777{
3778 struct drm_device *dev = crtc->dev;
3779 struct drm_i915_master_private *master_priv;
3780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781 int pipe = intel_crtc->pipe;
79e53945
JB		 3782
3783 if (!dev->primary->master)
3784 return;
3785
3786 master_priv = dev->primary->master->driver_priv;
3787 if (!master_priv->sarea_priv)
3788 return;
3789
79e53945
JB		 3790 switch (pipe) {
3791 case 0:
3792 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3793 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3794 break;
3795 case 1:
3796 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3797 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3798 break;
3799 default:
9db4a9c7 3800 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3801 break;
3802 }
79e53945
JB		 3803}
3804
976f8a20
DV		 3805/**
3806 * Sets the power management mode of the pipe and plane.
3807 */
3808void intel_crtc_update_dpms(struct drm_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_encoder *intel_encoder;
3813 bool enable = false;
3814
3815 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3816 enable |= intel_encoder->connectors_active;
3817
3818 if (enable)
3819 dev_priv->display.crtc_enable(crtc);
3820 else
3821 dev_priv->display.crtc_disable(crtc);
3822
3823 intel_crtc_update_sarea(crtc, enable);
3824}
3825
cdd59983
CW		 3826static void intel_crtc_disable(struct drm_crtc *crtc)
3827{
cdd59983 3828 struct drm_device *dev = crtc->dev;
976f8a20 3829 struct drm_connector *connector;
ee7b9f93 3830 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3832
976f8a20
DV		 3833 /* crtc should still be enabled when we disable it. */
3834 WARN_ON(!crtc->enabled);
3835
7b9f35a6 3836 intel_crtc->eld_vld = false;
976f8a20
DV		 3837 dev_priv->display.crtc_disable(crtc);
3838 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3839 dev_priv->display.off(crtc);
3840
931872fc
CW		 3841 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3842 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3843
3844 if (crtc->fb) {
3845 mutex_lock(&dev->struct_mutex);
1690e1eb 3846 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3847 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3848 crtc->fb = NULL;
3849 }
3850
3851 /* Update computed state. */
3852 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3853 if (!connector->encoder || !connector->encoder->crtc)
3854 continue;
3855
3856 if (connector->encoder->crtc != crtc)
3857 continue;
3858
3859 connector->dpms = DRM_MODE_DPMS_OFF;
3860 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3861 }
3862}
3863
a261b246 3864void intel_modeset_disable(struct drm_device *dev)
79e53945 3865{
a261b246
DV		 3866 struct drm_crtc *crtc;
3867
3868 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3869 if (crtc->enabled)
3870 intel_crtc_disable(crtc);
3871 }
79e53945
JB		 3872}
3873
ea5b213a 3874void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3875{
4ef69c7a 3876 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3877
ea5b213a
CW		 3878 drm_encoder_cleanup(encoder);
3879 kfree(intel_encoder);
7e7d76c3
JB		 3880}
3881
5ab432ef
DV		 3882/* Simple dpms helper for encodres with just one connector, no cloning and only
3883 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3884 * state of the entire output pipe. */
3885void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3886{
5ab432ef
DV		 3887 if (mode == DRM_MODE_DPMS_ON) {
3888 encoder->connectors_active = true;
3889
b2cabb0e 3890 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3891 } else {
3892 encoder->connectors_active = false;
3893
b2cabb0e 3894 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3895 }
79e53945
JB		 3896}
3897
0a91ca29
DV		 3898/* Cross check the actual hw state with our own modeset state tracking (and it's
3899 * internal consistency). */
b980514c 3900static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3901{
0a91ca29
DV		 3902 if (connector->get_hw_state(connector)) {
3903 struct intel_encoder *encoder = connector->encoder;
3904 struct drm_crtc *crtc;
3905 bool encoder_enabled;
3906 enum pipe pipe;
3907
3908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3909 connector->base.base.id,
3910 drm_get_connector_name(&connector->base));
3911
3912 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3913 "wrong connector dpms state\n");
3914 WARN(connector->base.encoder != &encoder->base,
3915 "active connector not linked to encoder\n");
3916 WARN(!encoder->connectors_active,
3917 "encoder->connectors_active not set\n");
3918
3919 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3920 WARN(!encoder_enabled, "encoder not enabled\n");
3921 if (WARN_ON(!encoder->base.crtc))
3922 return;
3923
3924 crtc = encoder->base.crtc;
3925
3926 WARN(!crtc->enabled, "crtc not enabled\n");
3927 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3928 WARN(pipe != to_intel_crtc(crtc)->pipe,
3929 "encoder active on the wrong pipe\n");
3930 }
79e53945
JB		 3931}
3932
5ab432ef
DV		 3933/* Even simpler default implementation, if there's really no special case to
3934 * consider. */
3935void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3936{
5ab432ef 3937 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3938
5ab432ef
DV		 3939 /* All the simple cases only support two dpms states. */
3940 if (mode != DRM_MODE_DPMS_ON)
3941 mode = DRM_MODE_DPMS_OFF;
d4270e57 3942
5ab432ef
DV		 3943 if (mode == connector->dpms)
3944 return;
3945
3946 connector->dpms = mode;
3947
3948 /* Only need to change hw state when actually enabled */
3949 if (encoder->base.crtc)
3950 intel_encoder_dpms(encoder, mode);
3951 else
8af6cf88 3952 WARN_ON(encoder->connectors_active != false);
0a91ca29 3953
b980514c 3954 intel_modeset_check_state(connector->dev);
79e53945
JB		 3955}
3956
f0947c37
DV		 3957/* Simple connector->get_hw_state implementation for encoders that support only
3958 * one connector and no cloning and hence the encoder state determines the state
3959 * of the connector. */
3960bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3961{
24929352 3962 enum pipe pipe = 0;
f0947c37 3963 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3964
f0947c37 3965 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3966}
3967
b8cecdf5
DV		 3968static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3969 struct intel_crtc_config *pipe_config)
79e53945 3970{
2c07245f 3971 struct drm_device *dev = crtc->dev;
b8cecdf5 3972 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3973
bad720ff 3974 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3975 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3976 if (pipe_config->requested_mode.clock * 3
3977 > IRONLAKE_FDI_FREQ * 4)
2377b741 3978 return false;
2c07245f 3979 }
89749350 3980
f9bef081
DV		 3981 /* All interlaced capable intel hw wants timings in frames. Note though
3982 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3983 * timings, so we need to be careful not to clobber these.*/
7ae89233 3984 if (!pipe_config->timings_set)
f9bef081 3985 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3986
44f46b42
CW		 3987 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3988 * with a hsync front porch of 0.
3989 */
3990 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3991 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3992 return false;
3993
5d2d38dd
DV		 3994 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3995 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3996 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3997 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3998 * for lvds. */
3999 pipe_config->pipe_bpp = 8*3;
4000 }
4001
79e53945
JB		 4002 return true;
4003}
4004
25eb05fc
JB		 4005static int valleyview_get_display_clock_speed(struct drm_device *dev)
4006{
4007 return 400000; /* FIXME */
4008}
4009
e70236a8
JB		 4010static int i945_get_display_clock_speed(struct drm_device *dev)
4011{
4012 return 400000;
4013}
79e53945 4014
e70236a8 4015static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4016{
e70236a8
JB		 4017 return 333000;
4018}
79e53945 4019
e70236a8
JB		 4020static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4021{
4022 return 200000;
4023}
79e53945 4024
e70236a8
JB		 4025static int i915gm_get_display_clock_speed(struct drm_device *dev)
4026{
4027 u16 gcfgc = 0;
79e53945 4028
e70236a8
JB		 4029 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4030
4031 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4032 return 133000;
4033 else {
4034 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4035 case GC_DISPLAY_CLOCK_333_MHZ:
4036 return 333000;
4037 default:
4038 case GC_DISPLAY_CLOCK_190_200_MHZ:
4039 return 190000;
79e53945 4040 }
e70236a8
JB		 4041 }
4042}
4043
4044static int i865_get_display_clock_speed(struct drm_device *dev)
4045{
4046 return 266000;
4047}
4048
4049static int i855_get_display_clock_speed(struct drm_device *dev)
4050{
4051 u16 hpllcc = 0;
4052 /* Assume that the hardware is in the high speed state. This
4053 * should be the default.
4054 */
4055 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4056 case GC_CLOCK_133_200:
4057 case GC_CLOCK_100_200:
4058 return 200000;
4059 case GC_CLOCK_166_250:
4060 return 250000;
4061 case GC_CLOCK_100_133:
79e53945 4062 return 133000;
e70236a8 4063 }
79e53945 4064
e70236a8
JB		 4065 /* Shouldn't happen */
4066 return 0;
4067}
79e53945 4068
e70236a8
JB		 4069static int i830_get_display_clock_speed(struct drm_device *dev)
4070{
4071 return 133000;
79e53945
JB		 4072}
4073
2c07245f 4074static void
e69d0bc1 4075intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4076{
4077 while (*num > 0xffffff || *den > 0xffffff) {
4078 *num >>= 1;
4079 *den >>= 1;
4080 }
4081}
4082
e69d0bc1
DV		 4083void
4084intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4085 int pixel_clock, int link_clock,
4086 struct intel_link_m_n *m_n)
2c07245f 4087{
e69d0bc1 4088 m_n->tu = 64;
22ed1113
CW		 4089 m_n->gmch_m = bits_per_pixel * pixel_clock;
4090 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4091 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4092 m_n->link_m = pixel_clock;
4093 m_n->link_n = link_clock;
e69d0bc1 4094 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4095}
4096
a7615030
CW		 4097static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4098{
72bbe58c
KP		 4099 if (i915_panel_use_ssc >= 0)
4100 return i915_panel_use_ssc != 0;
4101 return dev_priv->lvds_use_ssc
435793df 4102 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4103}
4104
a0c4da24
JB		 4105static int vlv_get_refclk(struct drm_crtc *crtc)
4106{
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 int refclk = 27000; /* for DP & HDMI */
4110
4111 return 100000; /* only one validated so far */
4112
4113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4114 refclk = 96000;
4115 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4116 if (intel_panel_use_ssc(dev_priv))
4117 refclk = 100000;
4118 else
4119 refclk = 96000;
4120 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4121 refclk = 100000;
4122 }
4123
4124 return refclk;
4125}
4126
c65d77d8
JB		 4127static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4128{
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 int refclk;
4132
a0c4da24
JB		 4133 if (IS_VALLEYVIEW(dev)) {
4134 refclk = vlv_get_refclk(crtc);
4135 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4136 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4137 refclk = dev_priv->lvds_ssc_freq * 1000;
4138 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4139 refclk / 1000);
4140 } else if (!IS_GEN2(dev)) {
4141 refclk = 96000;
4142 } else {
4143 refclk = 48000;
4144 }
4145
4146 return refclk;
4147}
4148
4149static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4150 intel_clock_t *clock)
4151{
4152 /* SDVO TV has fixed PLL values depend on its clock range,
4153 this mirrors vbios setting. */
4154 if (adjusted_mode->clock >= 100000
4155 && adjusted_mode->clock < 140500) {
4156 clock->p1 = 2;
4157 clock->p2 = 10;
4158 clock->n = 3;
4159 clock->m1 = 16;
4160 clock->m2 = 8;
4161 } else if (adjusted_mode->clock >= 140500
4162 && adjusted_mode->clock <= 200000) {
4163 clock->p1 = 1;
4164 clock->p2 = 10;
4165 clock->n = 6;
4166 clock->m1 = 12;
4167 clock->m2 = 8;
4168 }
4169}
4170
a7516a05
JB		 4171static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4172 intel_clock_t *clock,
4173 intel_clock_t *reduced_clock)
4174{
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 int pipe = intel_crtc->pipe;
4179 u32 fp, fp2 = 0;
4180
4181 if (IS_PINEVIEW(dev)) {
4182 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4183 if (reduced_clock)
4184 fp2 = (1 << reduced_clock->n) << 16 |
4185 reduced_clock->m1 << 8 | reduced_clock->m2;
4186 } else {
4187 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4188 if (reduced_clock)
4189 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4190 reduced_clock->m2;
4191 }
4192
4193 I915_WRITE(FP0(pipe), fp);
4194
4195 intel_crtc->lowfreq_avail = false;
4196 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197 reduced_clock && i915_powersave) {
4198 I915_WRITE(FP1(pipe), fp2);
4199 intel_crtc->lowfreq_avail = true;
4200 } else {
4201 I915_WRITE(FP1(pipe), fp);
4202 }
4203}
4204
03afc4a2
DV		 4205static void intel_dp_set_m_n(struct intel_crtc *crtc)
4206{
4207 if (crtc->config.has_pch_encoder)
4208 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4209 else
4210 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4211}
4212
a0c4da24 4213static void vlv_update_pll(struct drm_crtc *crtc,
a0c4da24 4214 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4215 int num_connectors)
a0c4da24
JB		 4216{
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220 int pipe = intel_crtc->pipe;
4221 u32 dpll, mdiv, pdiv;
4222 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4223 bool is_sdvo;
4224 u32 temp;
a0c4da24 4225
09153000
DV		 4226 mutex_lock(&dev_priv->dpio_lock);
4227
2a8f64ca
VP		 4228 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4229 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4230
2a8f64ca
VP		 4231 dpll = DPLL_VGA_MODE_DIS;
4232 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4233 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4234 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4235
4236 I915_WRITE(DPLL(pipe), dpll);
4237 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4238
4239 bestn = clock->n;
4240 bestm1 = clock->m1;
4241 bestm2 = clock->m2;
4242 bestp1 = clock->p1;
4243 bestp2 = clock->p2;
4244
2a8f64ca
VP		 4245 /*
4246 * In Valleyview PLL and program lane counter registers are exposed
4247 * through DPIO interface
4248 */
a0c4da24
JB		 4249 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4250 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4251 mdiv |= ((bestn << DPIO_N_SHIFT));
4252 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4253 mdiv |= (1 << DPIO_K_SHIFT);
4254 mdiv |= DPIO_ENABLE_CALIBRATION;
4255 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4256
4257 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4258
2a8f64ca 4259 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4260 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4261 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4262 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4263 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4264
2a8f64ca 4265 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4266
4267 dpll |= DPLL_VCO_ENABLE;
4268 I915_WRITE(DPLL(pipe), dpll);
4269 POSTING_READ(DPLL(pipe));
4270 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4271 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4272
2a8f64ca
VP		 4273 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4274
03afc4a2
DV		 4275 if (intel_crtc->config.has_dp_encoder)
4276 intel_dp_set_m_n(intel_crtc);
2a8f64ca
VP		 4277
4278 I915_WRITE(DPLL(pipe), dpll);
4279
4280 /* Wait for the clocks to stabilize. */
4281 POSTING_READ(DPLL(pipe));
4282 udelay(150);
a0c4da24 4283
2a8f64ca
VP		 4284 temp = 0;
4285 if (is_sdvo) {
6cc5f341
DV		 4286 temp = 0;
4287 if (intel_crtc->config.pixel_multiplier > 1) {
4288 temp = (intel_crtc->config.pixel_multiplier - 1)
4289 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4290 }
a0c4da24 4291 }
2a8f64ca
VP		 4292 I915_WRITE(DPLL_MD(pipe), temp);
4293 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4294
2a8f64ca
VP		 4295 /* Now program lane control registers */
4296 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4297 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4298 {
4299 temp = 0x1000C4;
4300 if(pipe == 1)
4301 temp |= (1 << 21);
4302 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4303 }
4304 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4305 {
4306 temp = 0x1000C4;
4307 if(pipe == 1)
4308 temp |= (1 << 21);
4309 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4310 }
09153000
DV		 4311
4312 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4313}
4314
eb1cbe48 4315static void i9xx_update_pll(struct drm_crtc *crtc,
eb1cbe48
DV		 4316 intel_clock_t *clock, intel_clock_t *reduced_clock,
4317 int num_connectors)
4318{
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4322 struct intel_encoder *encoder;
eb1cbe48
DV		 4323 int pipe = intel_crtc->pipe;
4324 u32 dpll;
4325 bool is_sdvo;
4326
2a8f64ca
VP		 4327 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4328
eb1cbe48
DV		 4329 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4330 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4331
4332 dpll = DPLL_VGA_MODE_DIS;
4333
4334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4335 dpll |= DPLLB_MODE_LVDS;
4336 else
4337 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4338
eb1cbe48 4339 if (is_sdvo) {
6cc5f341
DV		 4340 if ((intel_crtc->config.pixel_multiplier > 1) &&
4341 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4342 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4343 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4344 }
4345 dpll |= DPLL_DVO_HIGH_SPEED;
4346 }
4347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4348 dpll |= DPLL_DVO_HIGH_SPEED;
4349
4350 /* compute bitmask from p1 value */
4351 if (IS_PINEVIEW(dev))
4352 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4353 else {
4354 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4355 if (IS_G4X(dev) && reduced_clock)
4356 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4357 }
4358 switch (clock->p2) {
4359 case 5:
4360 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4361 break;
4362 case 7:
4363 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4364 break;
4365 case 10:
4366 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4367 break;
4368 case 14:
4369 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4370 break;
4371 }
4372 if (INTEL_INFO(dev)->gen >= 4)
4373 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4374
4375 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4376 dpll |= PLL_REF_INPUT_TVCLKINBC;
4377 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4378 /* XXX: just matching BIOS for now */
4379 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4380 dpll |= 3;
4381 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4382 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4383 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4384 else
4385 dpll |= PLL_REF_INPUT_DREFCLK;
4386
4387 dpll |= DPLL_VCO_ENABLE;
4388 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4389 POSTING_READ(DPLL(pipe));
4390 udelay(150);
4391
dafd226c
DV		 4392 for_each_encoder_on_crtc(dev, crtc, encoder)
4393 if (encoder->pre_pll_enable)
4394 encoder->pre_pll_enable(encoder);
eb1cbe48 4395
03afc4a2
DV		 4396 if (intel_crtc->config.has_dp_encoder)
4397 intel_dp_set_m_n(intel_crtc);
eb1cbe48
DV		 4398
4399 I915_WRITE(DPLL(pipe), dpll);
4400
4401 /* Wait for the clocks to stabilize. */
4402 POSTING_READ(DPLL(pipe));
4403 udelay(150);
4404
4405 if (INTEL_INFO(dev)->gen >= 4) {
4406 u32 temp = 0;
4407 if (is_sdvo) {
6cc5f341
DV		 4408 temp = 0;
4409 if (intel_crtc->config.pixel_multiplier > 1) {
4410 temp = (intel_crtc->config.pixel_multiplier - 1)
4411 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4412 }
eb1cbe48
DV		 4413 }
4414 I915_WRITE(DPLL_MD(pipe), temp);
4415 } else {
4416 /* The pixel multiplier can only be updated once the
4417 * DPLL is enabled and the clocks are stable.
4418 *
4419 * So write it again.
4420 */
4421 I915_WRITE(DPLL(pipe), dpll);
4422 }
4423}
4424
4425static void i8xx_update_pll(struct drm_crtc *crtc,
4426 struct drm_display_mode *adjusted_mode,
2a8f64ca 4427 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4428 int num_connectors)
4429{
4430 struct drm_device *dev = crtc->dev;
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4433 struct intel_encoder *encoder;
eb1cbe48
DV		 4434 int pipe = intel_crtc->pipe;
4435 u32 dpll;
4436
2a8f64ca
VP		 4437 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4438
eb1cbe48
DV		 4439 dpll = DPLL_VGA_MODE_DIS;
4440
4441 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4442 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4443 } else {
4444 if (clock->p1 == 2)
4445 dpll |= PLL_P1_DIVIDE_BY_TWO;
4446 else
4447 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4448 if (clock->p2 == 4)
4449 dpll |= PLL_P2_DIVIDE_BY_4;
4450 }
4451
83f377ab 4452 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4453 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4454 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4455 else
4456 dpll |= PLL_REF_INPUT_DREFCLK;
4457
4458 dpll |= DPLL_VCO_ENABLE;
4459 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4460 POSTING_READ(DPLL(pipe));
4461 udelay(150);
4462
dafd226c
DV		 4463 for_each_encoder_on_crtc(dev, crtc, encoder)
4464 if (encoder->pre_pll_enable)
4465 encoder->pre_pll_enable(encoder);
eb1cbe48 4466
5b5896e4
DV		 4467 I915_WRITE(DPLL(pipe), dpll);
4468
4469 /* Wait for the clocks to stabilize. */
4470 POSTING_READ(DPLL(pipe));
4471 udelay(150);
4472
eb1cbe48
DV		 4473 /* The pixel multiplier can only be updated once the
4474 * DPLL is enabled and the clocks are stable.
4475 *
4476 * So write it again.
4477 */
4478 I915_WRITE(DPLL(pipe), dpll);
4479}
4480
b0e77b9c
PZ		 4481static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4482 struct drm_display_mode *mode,
4483 struct drm_display_mode *adjusted_mode)
4484{
4485 struct drm_device *dev = intel_crtc->base.dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4488 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4489 uint32_t vsyncshift;
4490
4491 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4492 /* the chip adds 2 halflines automatically */
4493 adjusted_mode->crtc_vtotal -= 1;
4494 adjusted_mode->crtc_vblank_end -= 1;
4495 vsyncshift = adjusted_mode->crtc_hsync_start
4496 - adjusted_mode->crtc_htotal / 2;
4497 } else {
4498 vsyncshift = 0;
4499 }
4500
4501 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4502 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4503
fe2b8f9d 4504 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4505 (adjusted_mode->crtc_hdisplay - 1) |
4506 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4507 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4508 (adjusted_mode->crtc_hblank_start - 1) |
4509 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4510 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4511 (adjusted_mode->crtc_hsync_start - 1) |
4512 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4513
fe2b8f9d 4514 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4515 (adjusted_mode->crtc_vdisplay - 1) |
4516 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4517 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4518 (adjusted_mode->crtc_vblank_start - 1) |
4519 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4520 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4521 (adjusted_mode->crtc_vsync_start - 1) |
4522 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4523
b5e508d4
PZ		 4524 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4525 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4526 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4527 * bits. */
4528 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4529 (pipe == PIPE_B || pipe == PIPE_C))
4530 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4531
b0e77b9c
PZ		 4532 /* pipesrc controls the size that is scaled from, which should
4533 * always be the user's requested size.
4534 */
4535 I915_WRITE(PIPESRC(pipe),
4536 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4537}
4538
f564048e 4539static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4540 int x, int y,
94352cf9 4541 struct drm_framebuffer *fb)
79e53945
JB		 4542{
4543 struct drm_device *dev = crtc->dev;
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4546 struct drm_display_mode *adjusted_mode =
4547 &intel_crtc->config.adjusted_mode;
4548 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4549 int pipe = intel_crtc->pipe;
80824003 4550 int plane = intel_crtc->plane;
c751ce4f 4551 int refclk, num_connectors = 0;
652c393a 4552 intel_clock_t clock, reduced_clock;
b0e77b9c 4553 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4554 bool ok, has_reduced_clock = false, is_sdvo = false;
4555 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4556 struct intel_encoder *encoder;
d4906093 4557 const intel_limit_t *limit;
5c3b82e2 4558 int ret;
79e53945 4559
6c2b7c12 4560 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4561 switch (encoder->type) {
79e53945
JB		 4562 case INTEL_OUTPUT_LVDS:
4563 is_lvds = true;
4564 break;
4565 case INTEL_OUTPUT_SDVO:
7d57382e 4566 case INTEL_OUTPUT_HDMI:
79e53945 4567 is_sdvo = true;
5eddb70b 4568 if (encoder->needs_tv_clock)
e2f0ba97 4569 is_tv = true;
79e53945 4570 break;
79e53945
JB		 4571 case INTEL_OUTPUT_TVOUT:
4572 is_tv = true;
4573 break;
a4fc5ed6
KP		 4574 case INTEL_OUTPUT_DISPLAYPORT:
4575 is_dp = true;
4576 break;
79e53945 4577 }
43565a06 4578
c751ce4f 4579 num_connectors++;
79e53945
JB		 4580 }
4581
c65d77d8 4582 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4583
d4906093
ML		 4584 /*
4585 * Returns a set of divisors for the desired target clock with the given
4586 * refclk, or FALSE. The returned values represent the clock equation:
4587 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4588 */
1b894b59 4589 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4590 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4591 &clock);
79e53945
JB		 4592 if (!ok) {
4593 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4594 return -EINVAL;
79e53945
JB		 4595 }
4596
cda4b7d3 4597 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4598 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4599
ddc9003c 4600 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4601 /*
4602 * Ensure we match the reduced clock's P to the target clock.
4603 * If the clocks don't match, we can't switch the display clock
4604 * by using the FP0/FP1. In such case we will disable the LVDS
4605 * downclock feature.
4606 */
ddc9003c 4607 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4608 dev_priv->lvds_downclock,
4609 refclk,
cec2f356 4610 &clock,
5eddb70b 4611 &reduced_clock);
7026d4ac
ZW		 4612 }
4613
c65d77d8
JB		 4614 if (is_sdvo && is_tv)
4615 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4616
eb1cbe48 4617 if (IS_GEN2(dev))
2a8f64ca
VP		 4618 i8xx_update_pll(crtc, adjusted_mode, &clock,
4619 has_reduced_clock ? &reduced_clock : NULL,
4620 num_connectors);
a0c4da24 4621 else if (IS_VALLEYVIEW(dev))
6cc5f341 4622 vlv_update_pll(crtc, &clock,
2a8f64ca
VP		 4623 has_reduced_clock ? &reduced_clock : NULL,
4624 num_connectors);
79e53945 4625 else
6cc5f341 4626 i9xx_update_pll(crtc, &clock,
eb1cbe48
DV		 4627 has_reduced_clock ? &reduced_clock : NULL,
4628 num_connectors);
79e53945
JB		 4629
4630 /* setup pipeconf */
5eddb70b 4631 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4632
4633 /* Set up the display plane register */
4634 dspcntr = DISPPLANE_GAMMA_ENABLE;
4635
da6ecc5d
JB		 4636 if (!IS_VALLEYVIEW(dev)) {
4637 if (pipe == 0)
4638 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4639 else
4640 dspcntr |= DISPPLANE_SEL_PIPE_B;
4641 }
79e53945 4642
a6c45cf0 4643 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4644 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4645 * core speed.
4646 *
4647 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4648 * pipe == 0 check?
4649 */
e70236a8
JB		 4650 if (mode->clock >
4651 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4652 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4653 else
5eddb70b 4654 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4655 }
4656
3b5c78a3 4657 /* default to 8bpc */
dfd07d72 4658 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4659 if (is_dp) {
965e0c48 4660 if (intel_crtc->config.dither) {
dfd07d72 4661 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4662 PIPECONF_DITHER_EN |
4663 PIPECONF_DITHER_TYPE_SP;
4664 }
4665 }
4666
19c03924 4667 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
965e0c48 4668 if (intel_crtc->config.dither) {
dfd07d72 4669 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4670 PIPECONF_ENABLE |
4671 I965_PIPECONF_ACTIVE;
4672 }
4673 }
4674
28c97730 4675 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4676 drm_mode_debug_printmodeline(mode);
4677
a7516a05
JB		 4678 if (HAS_PIPE_CXSR(dev)) {
4679 if (intel_crtc->lowfreq_avail) {
28c97730 4680 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4681 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4682 } else {
28c97730 4683 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4684 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4685 }
4686 }
4687
617cf884 4688 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4689 if (!IS_GEN2(dev) &&
b0e77b9c 4690 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4691 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4692 else
617cf884 4693 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4694
b0e77b9c 4695 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4696
4697 /* pipesrc and dspsize control the size that is scaled from,
4698 * which should always be the user's requested size.
79e53945 4699 */
929c77fb
EA		 4700 I915_WRITE(DSPSIZE(plane),
4701 ((mode->vdisplay - 1) << 16) |
4702 (mode->hdisplay - 1));
4703 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4704
f564048e
EA		 4705 I915_WRITE(PIPECONF(pipe), pipeconf);
4706 POSTING_READ(PIPECONF(pipe));
929c77fb 4707 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4708
4709 intel_wait_for_vblank(dev, pipe);
4710
f564048e
EA		 4711 I915_WRITE(DSPCNTR(plane), dspcntr);
4712 POSTING_READ(DSPCNTR(plane));
4713
94352cf9 4714 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4715
4716 intel_update_watermarks(dev);
4717
f564048e
EA		 4718 return ret;
4719}
4720
dde86e2d 4721static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4722{
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4725 struct intel_encoder *encoder;
74cfd7ac 4726 u32 val, final;
13d83a67 4727 bool has_lvds = false;
199e5d79
KP		 4728 bool has_cpu_edp = false;
4729 bool has_pch_edp = false;
4730 bool has_panel = false;
99eb6a01
KP		 4731 bool has_ck505 = false;
4732 bool can_ssc = false;
13d83a67
JB		 4733
4734 /* We need to take the global config into account */
199e5d79
KP		 4735 list_for_each_entry(encoder, &mode_config->encoder_list,
4736 base.head) {
4737 switch (encoder->type) {
4738 case INTEL_OUTPUT_LVDS:
4739 has_panel = true;
4740 has_lvds = true;
4741 break;
4742 case INTEL_OUTPUT_EDP:
4743 has_panel = true;
4744 if (intel_encoder_is_pch_edp(&encoder->base))
4745 has_pch_edp = true;
4746 else
4747 has_cpu_edp = true;
4748 break;
13d83a67
JB		 4749 }
4750 }
4751
99eb6a01
KP		 4752 if (HAS_PCH_IBX(dev)) {
4753 has_ck505 = dev_priv->display_clock_mode;
4754 can_ssc = has_ck505;
4755 } else {
4756 has_ck505 = false;
4757 can_ssc = true;
4758 }
4759
4760 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4761 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4762 has_ck505);
13d83a67
JB		 4763
4764 /* Ironlake: try to setup display ref clock before DPLL
4765 * enabling. This is only under driver's control after
4766 * PCH B stepping, previous chipset stepping should be
4767 * ignoring this setting.
4768 */
74cfd7ac
CW		 4769 val = I915_READ(PCH_DREF_CONTROL);
4770
4771 /* As we must carefully and slowly disable/enable each source in turn,
4772 * compute the final state we want first and check if we need to
4773 * make any changes at all.
4774 */
4775 final = val;
4776 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4777 if (has_ck505)
4778 final |= DREF_NONSPREAD_CK505_ENABLE;
4779 else
4780 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4781
4782 final &= ~DREF_SSC_SOURCE_MASK;
4783 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4784 final &= ~DREF_SSC1_ENABLE;
4785
4786 if (has_panel) {
4787 final |= DREF_SSC_SOURCE_ENABLE;
4788
4789 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4790 final |= DREF_SSC1_ENABLE;
4791
4792 if (has_cpu_edp) {
4793 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4794 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4795 else
4796 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4797 } else
4798 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4799 } else {
4800 final |= DREF_SSC_SOURCE_DISABLE;
4801 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4802 }
4803
4804 if (final == val)
4805 return;
4806
13d83a67 4807 /* Always enable nonspread source */
74cfd7ac 4808 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4809
99eb6a01 4810 if (has_ck505)
74cfd7ac 4811 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4812 else
74cfd7ac 4813 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4814
199e5d79 4815 if (has_panel) {
74cfd7ac
CW		 4816 val &= ~DREF_SSC_SOURCE_MASK;
4817 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4818
199e5d79 4819 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4820 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4821 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4822 val |= DREF_SSC1_ENABLE;
e77166b5 4823 } else
74cfd7ac 4824 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4825
4826 /* Get SSC going before enabling the outputs */
74cfd7ac 4827 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4828 POSTING_READ(PCH_DREF_CONTROL);
4829 udelay(200);
4830
74cfd7ac 4831 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4832
4833 /* Enable CPU source on CPU attached eDP */
199e5d79 4834 if (has_cpu_edp) {
99eb6a01 4835 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4836 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4837 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4838 }
13d83a67 4839 else
74cfd7ac 4840 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4841 } else
74cfd7ac 4842 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4843
74cfd7ac 4844 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4845 POSTING_READ(PCH_DREF_CONTROL);
4846 udelay(200);
4847 } else {
4848 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4849
74cfd7ac 4850 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4851
4852 /* Turn off CPU output */
74cfd7ac 4853 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4854
74cfd7ac 4855 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4856 POSTING_READ(PCH_DREF_CONTROL);
4857 udelay(200);
4858
4859 /* Turn off the SSC source */
74cfd7ac
CW		 4860 val &= ~DREF_SSC_SOURCE_MASK;
4861 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4862
4863 /* Turn off SSC1 */
74cfd7ac 4864 val &= ~DREF_SSC1_ENABLE;
199e5d79 4865
74cfd7ac 4866 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4867 POSTING_READ(PCH_DREF_CONTROL);
4868 udelay(200);
4869 }
74cfd7ac
CW		 4870
4871 BUG_ON(val != final);
13d83a67
JB		 4872}
4873
dde86e2d
PZ		 4874/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4875static void lpt_init_pch_refclk(struct drm_device *dev)
4876{
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct drm_mode_config *mode_config = &dev->mode_config;
4879 struct intel_encoder *encoder;
4880 bool has_vga = false;
4881 bool is_sdv = false;
4882 u32 tmp;
4883
4884 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4885 switch (encoder->type) {
4886 case INTEL_OUTPUT_ANALOG:
4887 has_vga = true;
4888 break;
4889 }
4890 }
4891
4892 if (!has_vga)
4893 return;
4894
c00db246
DV		 4895 mutex_lock(&dev_priv->dpio_lock);
4896
dde86e2d
PZ		 4897 /* XXX: Rip out SDV support once Haswell ships for real. */
4898 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4899 is_sdv = true;
4900
4901 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4902 tmp &= ~SBI_SSCCTL_DISABLE;
4903 tmp |= SBI_SSCCTL_PATHALT;
4904 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4905
4906 udelay(24);
4907
4908 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4909 tmp &= ~SBI_SSCCTL_PATHALT;
4910 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4911
4912 if (!is_sdv) {
4913 tmp = I915_READ(SOUTH_CHICKEN2);
4914 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4915 I915_WRITE(SOUTH_CHICKEN2, tmp);
4916
4917 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4918 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4919 DRM_ERROR("FDI mPHY reset assert timeout\n");
4920
4921 tmp = I915_READ(SOUTH_CHICKEN2);
4922 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4923 I915_WRITE(SOUTH_CHICKEN2, tmp);
4924
4925 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4926 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4927 100))
4928 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4929 }
4930
4931 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4932 tmp &= ~(0xFF << 24);
4933 tmp |= (0x12 << 24);
4934 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4935
4936 if (!is_sdv) {
4937 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4938 tmp &= ~(0x3 << 6);
4939 tmp |= (1 << 6) | (1 << 0);
4940 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4941 }
4942
4943 if (is_sdv) {
4944 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4945 tmp |= 0x7FFF;
4946 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4947 }
4948
4949 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4950 tmp |= (1 << 11);
4951 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4952
4953 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4954 tmp |= (1 << 11);
4955 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4956
4957 if (is_sdv) {
4958 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4959 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4960 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4961
4962 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4963 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4964 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4965
4966 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4967 tmp |= (0x3F << 8);
4968 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4969
4970 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4971 tmp |= (0x3F << 8);
4972 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4973 }
4974
4975 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4976 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4977 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4978
4979 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4980 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4981 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4982
4983 if (!is_sdv) {
4984 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4985 tmp &= ~(7 << 13);
4986 tmp |= (5 << 13);
4987 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4988
4989 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4990 tmp &= ~(7 << 13);
4991 tmp |= (5 << 13);
4992 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4993 }
4994
4995 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4996 tmp &= ~0xFF;
4997 tmp |= 0x1C;
4998 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4999
5000 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5001 tmp &= ~0xFF;
5002 tmp |= 0x1C;
5003 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5004
5005 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5006 tmp &= ~(0xFF << 16);
5007 tmp |= (0x1C << 16);
5008 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5009
5010 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5011 tmp &= ~(0xFF << 16);
5012 tmp |= (0x1C << 16);
5013 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5014
5015 if (!is_sdv) {
5016 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5017 tmp |= (1 << 27);
5018 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5019
5020 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5021 tmp |= (1 << 27);
5022 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5023
5024 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5025 tmp &= ~(0xF << 28);
5026 tmp |= (4 << 28);
5027 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5028
5029 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5030 tmp &= ~(0xF << 28);
5031 tmp |= (4 << 28);
5032 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5033 }
5034
5035 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5036 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5037 tmp |= SBI_DBUFF0_ENABLE;
5038 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5039
5040 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5041}
5042
5043/*
5044 * Initialize reference clocks when the driver loads
5045 */
5046void intel_init_pch_refclk(struct drm_device *dev)
5047{
5048 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5049 ironlake_init_pch_refclk(dev);
5050 else if (HAS_PCH_LPT(dev))
5051 lpt_init_pch_refclk(dev);
5052}
5053
d9d444cb
JB		 5054static int ironlake_get_refclk(struct drm_crtc *crtc)
5055{
5056 struct drm_device *dev = crtc->dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 struct intel_encoder *encoder;
d9d444cb
JB		 5059 struct intel_encoder *edp_encoder = NULL;
5060 int num_connectors = 0;
5061 bool is_lvds = false;
5062
6c2b7c12 5063 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5064 switch (encoder->type) {
5065 case INTEL_OUTPUT_LVDS:
5066 is_lvds = true;
5067 break;
5068 case INTEL_OUTPUT_EDP:
5069 edp_encoder = encoder;
5070 break;
5071 }
5072 num_connectors++;
5073 }
5074
5075 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5076 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5077 dev_priv->lvds_ssc_freq);
5078 return dev_priv->lvds_ssc_freq * 1000;
5079 }
5080
5081 return 120000;
5082}
5083
c8203565 5084static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5085 struct drm_display_mode *adjusted_mode,
c8203565 5086 bool dither)
79e53945 5087{
c8203565 5088 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5090 int pipe = intel_crtc->pipe;
c8203565
PZ		 5091 uint32_t val;
5092
5093 val = I915_READ(PIPECONF(pipe));
5094
dfd07d72 5095 val &= ~PIPECONF_BPC_MASK;
965e0c48 5096 switch (intel_crtc->config.pipe_bpp) {
c8203565 5097 case 18:
dfd07d72 5098 val |= PIPECONF_6BPC;
c8203565
PZ		 5099 break;
5100 case 24:
dfd07d72 5101 val |= PIPECONF_8BPC;
c8203565
PZ		 5102 break;
5103 case 30:
dfd07d72 5104 val |= PIPECONF_10BPC;
c8203565
PZ		 5105 break;
5106 case 36:
dfd07d72 5107 val |= PIPECONF_12BPC;
c8203565
PZ		 5108 break;
5109 default:
cc769b62
PZ		 5110 /* Case prevented by intel_choose_pipe_bpp_dither. */
5111 BUG();
c8203565
PZ		 5112 }
5113
5114 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5115 if (dither)
5116 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5117
5118 val &= ~PIPECONF_INTERLACE_MASK;
5119 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5120 val |= PIPECONF_INTERLACED_ILK;
5121 else
5122 val |= PIPECONF_PROGRESSIVE;
5123
50f3b016 5124 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5125 val |= PIPECONF_COLOR_RANGE_SELECT;
5126 else
5127 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5128
c8203565
PZ		 5129 I915_WRITE(PIPECONF(pipe), val);
5130 POSTING_READ(PIPECONF(pipe));
5131}
5132
86d3efce
VS		 5133/*
5134 * Set up the pipe CSC unit.
5135 *
5136 * Currently only full range RGB to limited range RGB conversion
5137 * is supported, but eventually this should handle various
5138 * RGB<->YCbCr scenarios as well.
5139 */
50f3b016 5140static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5141{
5142 struct drm_device *dev = crtc->dev;
5143 struct drm_i915_private *dev_priv = dev->dev_private;
5144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5145 int pipe = intel_crtc->pipe;
5146 uint16_t coeff = 0x7800; /* 1.0 */
5147
5148 /*
5149 * TODO: Check what kind of values actually come out of the pipe
5150 * with these coeff/postoff values and adjust to get the best
5151 * accuracy. Perhaps we even need to take the bpc value into
5152 * consideration.
5153 */
5154
50f3b016 5155 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5156 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5157
5158 /*
5159 * GY/GU and RY/RU should be the other way around according
5160 * to BSpec, but reality doesn't agree. Just set them up in
5161 * a way that results in the correct picture.
5162 */
5163 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5164 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5165
5166 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5167 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5168
5169 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5170 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5171
5172 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5173 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5174 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5175
5176 if (INTEL_INFO(dev)->gen > 6) {
5177 uint16_t postoff = 0;
5178
50f3b016 5179 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5180 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5181
5182 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5183 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5184 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5185
5186 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5187 } else {
5188 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5189
50f3b016 5190 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5191 mode |= CSC_BLACK_SCREEN_OFFSET;
5192
5193 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5194 }
5195}
5196
ee2b0b38
PZ		 5197static void haswell_set_pipeconf(struct drm_crtc *crtc,
5198 struct drm_display_mode *adjusted_mode,
5199 bool dither)
5200{
5201 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5203 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5204 uint32_t val;
5205
702e7a56 5206 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5207
5208 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5209 if (dither)
5210 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5211
5212 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5213 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5214 val |= PIPECONF_INTERLACED_ILK;
5215 else
5216 val |= PIPECONF_PROGRESSIVE;
5217
702e7a56
PZ		 5218 I915_WRITE(PIPECONF(cpu_transcoder), val);
5219 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5220}
5221
6591c6e4
PZ		 5222static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5223 struct drm_display_mode *adjusted_mode,
5224 intel_clock_t *clock,
5225 bool *has_reduced_clock,
5226 intel_clock_t *reduced_clock)
5227{
5228 struct drm_device *dev = crtc->dev;
5229 struct drm_i915_private *dev_priv = dev->dev_private;
5230 struct intel_encoder *intel_encoder;
5231 int refclk;
d4906093 5232 const intel_limit_t *limit;
6591c6e4 5233 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5234
6591c6e4
PZ		 5235 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5236 switch (intel_encoder->type) {
79e53945
JB		 5237 case INTEL_OUTPUT_LVDS:
5238 is_lvds = true;
5239 break;
5240 case INTEL_OUTPUT_SDVO:
7d57382e 5241 case INTEL_OUTPUT_HDMI:
79e53945 5242 is_sdvo = true;
6591c6e4 5243 if (intel_encoder->needs_tv_clock)
e2f0ba97 5244 is_tv = true;
79e53945 5245 break;
79e53945
JB		 5246 case INTEL_OUTPUT_TVOUT:
5247 is_tv = true;
5248 break;
79e53945
JB		 5249 }
5250 }
5251
d9d444cb 5252 refclk = ironlake_get_refclk(crtc);
79e53945 5253
d4906093
ML		 5254 /*
5255 * Returns a set of divisors for the desired target clock with the given
5256 * refclk, or FALSE. The returned values represent the clock equation:
5257 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5258 */
1b894b59 5259 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5260 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5261 clock);
5262 if (!ret)
5263 return false;
cda4b7d3 5264
ddc9003c 5265 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5266 /*
5267 * Ensure we match the reduced clock's P to the target clock.
5268 * If the clocks don't match, we can't switch the display clock
5269 * by using the FP0/FP1. In such case we will disable the LVDS
5270 * downclock feature.
5271 */
6591c6e4
PZ		 5272 *has_reduced_clock = limit->find_pll(limit, crtc,
5273 dev_priv->lvds_downclock,
5274 refclk,
5275 clock,
5276 reduced_clock);
652c393a 5277 }
61e9653f
DV		 5278
5279 if (is_sdvo && is_tv)
6591c6e4
PZ		 5280 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5281
5282 return true;
5283}
5284
01a415fd
DV		 5285static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5286{
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288 uint32_t temp;
5289
5290 temp = I915_READ(SOUTH_CHICKEN1);
5291 if (temp & FDI_BC_BIFURCATION_SELECT)
5292 return;
5293
5294 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5295 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5296
5297 temp |= FDI_BC_BIFURCATION_SELECT;
5298 DRM_DEBUG_KMS("enabling fdi C rx\n");
5299 I915_WRITE(SOUTH_CHICKEN1, temp);
5300 POSTING_READ(SOUTH_CHICKEN1);
5301}
5302
5303static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5304{
5305 struct drm_device *dev = intel_crtc->base.dev;
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307 struct intel_crtc *pipe_B_crtc =
5308 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5309
5310 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5311 intel_crtc->pipe, intel_crtc->fdi_lanes);
5312 if (intel_crtc->fdi_lanes > 4) {
5313 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5314 intel_crtc->pipe, intel_crtc->fdi_lanes);
5315 /* Clamp lanes to avoid programming the hw with bogus values. */
5316 intel_crtc->fdi_lanes = 4;
5317
5318 return false;
5319 }
5320
7eb552ae 5321 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5322 return true;
5323
5324 switch (intel_crtc->pipe) {
5325 case PIPE_A:
5326 return true;
5327 case PIPE_B:
5328 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5329 intel_crtc->fdi_lanes > 2) {
5330 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5331 intel_crtc->pipe, intel_crtc->fdi_lanes);
5332 /* Clamp lanes to avoid programming the hw with bogus values. */
5333 intel_crtc->fdi_lanes = 2;
5334
5335 return false;
5336 }
5337
5338 if (intel_crtc->fdi_lanes > 2)
5339 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5340 else
5341 cpt_enable_fdi_bc_bifurcation(dev);
5342
5343 return true;
5344 case PIPE_C:
5345 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5346 if (intel_crtc->fdi_lanes > 2) {
5347 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5348 intel_crtc->pipe, intel_crtc->fdi_lanes);
5349 /* Clamp lanes to avoid programming the hw with bogus values. */
5350 intel_crtc->fdi_lanes = 2;
5351
5352 return false;
5353 }
5354 } else {
5355 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5356 return false;
5357 }
5358
5359 cpt_enable_fdi_bc_bifurcation(dev);
5360
5361 return true;
5362 default:
5363 BUG();
5364 }
5365}
5366
d4b1931c
PZ		 5367int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5368{
5369 /*
5370 * Account for spread spectrum to avoid
5371 * oversubscribing the link. Max center spread
5372 * is 2.5%; use 5% for safety's sake.
5373 */
5374 u32 bps = target_clock * bpp * 21 / 20;
5375 return bps / (link_bw * 8) + 1;
5376}
5377
6cf86a5e
DV		 5378void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5379 struct intel_link_m_n *m_n)
79e53945 5380{
6cf86a5e
DV		 5381 struct drm_device *dev = crtc->base.dev;
5382 struct drm_i915_private *dev_priv = dev->dev_private;
5383 int pipe = crtc->pipe;
5384
5385 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5386 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5387 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5388 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5389}
5390
5391void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5392 struct intel_link_m_n *m_n)
5393{
5394 struct drm_device *dev = crtc->base.dev;
79e53945 5395 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e
DV		 5396 int pipe = crtc->pipe;
5397 enum transcoder transcoder = crtc->cpu_transcoder;
5398
5399 if (INTEL_INFO(dev)->gen >= 5) {
5400 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5401 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5402 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5403 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5404 } else {
5405 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5406 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5407 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5408 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5409 }
5410}
5411
5412static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5413{
5414 struct drm_device *dev = crtc->dev;
79e53945 5415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5416 struct drm_display_mode *adjusted_mode =
5417 &intel_crtc->config.adjusted_mode;
e69d0bc1 5418 struct intel_link_m_n m_n = {0};
6cc5f341 5419 int target_clock, lane, link_bw;
df92b1e6 5420 uint32_t bps;
61e9653f 5421
6cf86a5e
DV		 5422 /* FDI is a binary signal running at ~2.7GHz, encoding
5423 * each output octet as 10 bits. The actual frequency
5424 * is stored as a divider into a 100MHz clock, and the
5425 * mode pixel clock is stored in units of 1KHz.
5426 * Hence the bw of each lane in terms of the mode signal
5427 * is:
5428 */
5429 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5430
df92b1e6
DV		 5431 if (intel_crtc->config.pixel_target_clock)
5432 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5433 else
5434 target_clock = adjusted_mode->clock;
5435
6cf86a5e
DV		 5436 lane = ironlake_get_lanes_required(target_clock, link_bw,
5437 intel_crtc->config.pipe_bpp);
2c07245f 5438
8febb297
EA		 5439 intel_crtc->fdi_lanes = lane;
5440
6cc5f341
DV		 5441 if (intel_crtc->config.pixel_multiplier > 1)
5442 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5443 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5444 link_bw, &m_n);
8febb297 5445
6cf86a5e 5446 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5447}
5448
de13a2e3 5449static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
de13a2e3 5450 intel_clock_t *clock, u32 fp)
79e53945 5451{
de13a2e3 5452 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5453 struct drm_device *dev = crtc->dev;
5454 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5455 struct intel_encoder *intel_encoder;
5456 uint32_t dpll;
6cc5f341 5457 int factor, num_connectors = 0;
de13a2e3
PZ		 5458 bool is_lvds = false, is_sdvo = false, is_tv = false;
5459 bool is_dp = false, is_cpu_edp = false;
79e53945 5460
de13a2e3
PZ		 5461 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5462 switch (intel_encoder->type) {
79e53945
JB		 5463 case INTEL_OUTPUT_LVDS:
5464 is_lvds = true;
5465 break;
5466 case INTEL_OUTPUT_SDVO:
7d57382e 5467 case INTEL_OUTPUT_HDMI:
79e53945 5468 is_sdvo = true;
de13a2e3 5469 if (intel_encoder->needs_tv_clock)
e2f0ba97 5470 is_tv = true;
79e53945 5471 break;
79e53945
JB		 5472 case INTEL_OUTPUT_TVOUT:
5473 is_tv = true;
5474 break;
a4fc5ed6
KP		 5475 case INTEL_OUTPUT_DISPLAYPORT:
5476 is_dp = true;
5477 break;
32f9d658 5478 case INTEL_OUTPUT_EDP:
e3aef172 5479 is_dp = true;
de13a2e3 5480 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5481 is_cpu_edp = true;
32f9d658 5482 break;
79e53945 5483 }
43565a06 5484
c751ce4f 5485 num_connectors++;
79e53945 5486 }
79e53945 5487
c1858123 5488 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5489 factor = 21;
5490 if (is_lvds) {
5491 if ((intel_panel_use_ssc(dev_priv) &&
5492 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5493 intel_is_dual_link_lvds(dev))
8febb297
EA		 5494 factor = 25;
5495 } else if (is_sdvo && is_tv)
5496 factor = 20;
c1858123 5497
de13a2e3 5498 if (clock->m < factor * clock->n)
8febb297 5499 fp |= FP_CB_TUNE;
2c07245f 5500
5eddb70b 5501 dpll = 0;
2c07245f 5502
a07d6787
EA		 5503 if (is_lvds)
5504 dpll |= DPLLB_MODE_LVDS;
5505 else
5506 dpll |= DPLLB_MODE_DAC_SERIAL;
5507 if (is_sdvo) {
6cc5f341
DV		 5508 if (intel_crtc->config.pixel_multiplier > 1) {
5509 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5510 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5511 }
a07d6787
EA		 5512 dpll |= DPLL_DVO_HIGH_SPEED;
5513 }
e3aef172 5514 if (is_dp && !is_cpu_edp)
a07d6787 5515 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5516
a07d6787 5517 /* compute bitmask from p1 value */
de13a2e3 5518 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5519 /* also FPA1 */
de13a2e3 5520 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5521
de13a2e3 5522 switch (clock->p2) {
a07d6787
EA		 5523 case 5:
5524 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5525 break;
5526 case 7:
5527 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5528 break;
5529 case 10:
5530 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5531 break;
5532 case 14:
5533 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5534 break;
79e53945
JB		 5535 }
5536
43565a06
KH		 5537 if (is_sdvo && is_tv)
5538 dpll |= PLL_REF_INPUT_TVCLKINBC;
5539 else if (is_tv)
79e53945 5540 /* XXX: just matching BIOS for now */
43565a06 5541 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5542 dpll |= 3;
a7615030 5543 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5544 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5545 else
5546 dpll |= PLL_REF_INPUT_DREFCLK;
5547
de13a2e3
PZ		 5548 return dpll;
5549}
5550
5551static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5552 int x, int y,
5553 struct drm_framebuffer *fb)
5554{
5555 struct drm_device *dev = crtc->dev;
5556 struct drm_i915_private *dev_priv = dev->dev_private;
5557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5558 struct drm_display_mode *adjusted_mode =
5559 &intel_crtc->config.adjusted_mode;
5560 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5561 int pipe = intel_crtc->pipe;
5562 int plane = intel_crtc->plane;
5563 int num_connectors = 0;
5564 intel_clock_t clock, reduced_clock;
5565 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5566 bool ok, has_reduced_clock = false;
5567 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5568 struct intel_encoder *encoder;
de13a2e3 5569 int ret;
01a415fd 5570 bool dither, fdi_config_ok;
de13a2e3
PZ		 5571
5572 for_each_encoder_on_crtc(dev, crtc, encoder) {
5573 switch (encoder->type) {
5574 case INTEL_OUTPUT_LVDS:
5575 is_lvds = true;
5576 break;
de13a2e3
PZ		 5577 case INTEL_OUTPUT_DISPLAYPORT:
5578 is_dp = true;
5579 break;
5580 case INTEL_OUTPUT_EDP:
5581 is_dp = true;
e2f12b07 5582 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5583 is_cpu_edp = true;
5584 break;
5585 }
5586
5587 num_connectors++;
a07d6787 5588 }
79e53945 5589
5dc5298b
PZ		 5590 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5591 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5592
6cf86a5e
DV		 5593 intel_crtc->cpu_transcoder = pipe;
5594
de13a2e3
PZ		 5595 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5596 &has_reduced_clock, &reduced_clock);
5597 if (!ok) {
5598 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5599 return -EINVAL;
79e53945
JB		 5600 }
5601
de13a2e3
PZ		 5602 /* Ensure that the cursor is valid for the new mode before changing... */
5603 intel_crtc_update_cursor(crtc, true);
5604
5605 /* determine panel color depth */
4e53c2e0 5606 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5607 if (is_lvds && dev_priv->lvds_dither)
5608 dither = true;
5609
5610 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5611 if (has_reduced_clock)
5612 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5613 reduced_clock.m2;
5614
6cc5f341 5615 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
79e53945 5616
f7cb34d4 5617 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5618 drm_mode_debug_printmodeline(mode);
5619
5dc5298b
PZ		 5620 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5621 if (!is_cpu_edp) {
ee7b9f93 5622 struct intel_pch_pll *pll;
4b645f14 5623
ee7b9f93
JB		 5624 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5625 if (pll == NULL) {
5626 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5627 pipe);
4b645f14
JB		 5628 return -EINVAL;
5629 }
ee7b9f93
JB		 5630 } else
5631 intel_put_pch_pll(intel_crtc);
79e53945 5632
03afc4a2
DV		 5633 if (intel_crtc->config.has_dp_encoder)
5634 intel_dp_set_m_n(intel_crtc);
79e53945 5635
dafd226c
DV		 5636 for_each_encoder_on_crtc(dev, crtc, encoder)
5637 if (encoder->pre_pll_enable)
5638 encoder->pre_pll_enable(encoder);
79e53945 5639
ee7b9f93
JB		 5640 if (intel_crtc->pch_pll) {
5641 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5642
32f9d658 5643 /* Wait for the clocks to stabilize. */
ee7b9f93 5644 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5645 udelay(150);
5646
8febb297
EA		 5647 /* The pixel multiplier can only be updated once the
5648 * DPLL is enabled and the clocks are stable.
5649 *
5650 * So write it again.
5651 */
ee7b9f93 5652 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5653 }
79e53945 5654
5eddb70b 5655 intel_crtc->lowfreq_avail = false;
ee7b9f93 5656 if (intel_crtc->pch_pll) {
4b645f14 5657 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5658 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5659 intel_crtc->lowfreq_avail = true;
4b645f14 5660 } else {
ee7b9f93 5661 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5662 }
5663 }
5664
b0e77b9c 5665 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5666
01a415fd
DV		 5667 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5668 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5669 intel_crtc->fdi_lanes = 0;
5670 if (intel_crtc->config.has_pch_encoder)
5671 ironlake_fdi_set_m_n(crtc);
2c07245f 5672
01a415fd 5673 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5674
c8203565 5675 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5676
9d0498a2 5677 intel_wait_for_vblank(dev, pipe);
79e53945 5678
a1f9e77e
PZ		 5679 /* Set up the display plane register */
5680 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5681 POSTING_READ(DSPCNTR(plane));
79e53945 5682
94352cf9 5683 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5684
5685 intel_update_watermarks(dev);
5686
1f8eeabf
ED		 5687 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5688
01a415fd 5689 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5690}
5691
d6dd9eb1
DV		 5692static void haswell_modeset_global_resources(struct drm_device *dev)
5693{
5694 struct drm_i915_private *dev_priv = dev->dev_private;
5695 bool enable = false;
5696 struct intel_crtc *crtc;
5697 struct intel_encoder *encoder;
5698
5699 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5700 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5701 enable = true;
5702 /* XXX: Should check for edp transcoder here, but thanks to init
5703 * sequence that's not yet available. Just in case desktop eDP
5704 * on PORT D is possible on haswell, too. */
5705 }
5706
5707 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5708 base.head) {
5709 if (encoder->type != INTEL_OUTPUT_EDP &&
5710 encoder->connectors_active)
5711 enable = true;
5712 }
5713
5714 /* Even the eDP panel fitter is outside the always-on well. */
5715 if (dev_priv->pch_pf_size)
5716 enable = true;
5717
5718 intel_set_power_well(dev, enable);
5719}
5720
09b4ddf9 5721static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5722 int x, int y,
5723 struct drm_framebuffer *fb)
5724{
5725 struct drm_device *dev = crtc->dev;
5726 struct drm_i915_private *dev_priv = dev->dev_private;
5727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5728 struct drm_display_mode *adjusted_mode =
5729 &intel_crtc->config.adjusted_mode;
5730 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5731 int pipe = intel_crtc->pipe;
5732 int plane = intel_crtc->plane;
5733 int num_connectors = 0;
ed7ef439 5734 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5735 struct intel_encoder *encoder;
09b4ddf9
PZ		 5736 int ret;
5737 bool dither;
5738
5739 for_each_encoder_on_crtc(dev, crtc, encoder) {
5740 switch (encoder->type) {
09b4ddf9
PZ		 5741 case INTEL_OUTPUT_DISPLAYPORT:
5742 is_dp = true;
5743 break;
5744 case INTEL_OUTPUT_EDP:
5745 is_dp = true;
5746 if (!intel_encoder_is_pch_edp(&encoder->base))
5747 is_cpu_edp = true;
5748 break;
5749 }
5750
5751 num_connectors++;
5752 }
5753
bba2181c
DV		 5754 if (is_cpu_edp)
5755 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5756 else
5757 intel_crtc->cpu_transcoder = pipe;
5758
5dc5298b
PZ		 5759 /* We are not sure yet this won't happen. */
5760 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5761 INTEL_PCH_TYPE(dev));
5762
5763 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5764 num_connectors, pipe_name(pipe));
5765
702e7a56 5766 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5767 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5768
5769 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5770
6441ab5f
PZ		 5771 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5772 return -EINVAL;
5773
09b4ddf9
PZ		 5774 /* Ensure that the cursor is valid for the new mode before changing... */
5775 intel_crtc_update_cursor(crtc, true);
5776
5777 /* determine panel color depth */
4e53c2e0 5778 dither = intel_crtc->config.dither;
09b4ddf9 5779
09b4ddf9
PZ		 5780 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5781 drm_mode_debug_printmodeline(mode);
5782
03afc4a2
DV		 5783 if (intel_crtc->config.has_dp_encoder)
5784 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5785
5786 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5787
5788 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5789
6cf86a5e
DV		 5790 if (intel_crtc->config.has_pch_encoder)
5791 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5792
ee2b0b38 5793 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5794
50f3b016 5795 intel_set_pipe_csc(crtc);
86d3efce 5796
09b4ddf9 5797 /* Set up the display plane register */
86d3efce 5798 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5799 POSTING_READ(DSPCNTR(plane));
5800
5801 ret = intel_pipe_set_base(crtc, x, y, fb);
5802
5803 intel_update_watermarks(dev);
5804
5805 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5806
1f803ee5 5807 return ret;
79e53945
JB		 5808}
5809
f564048e 5810static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5811 int x, int y,
94352cf9 5812 struct drm_framebuffer *fb)
f564048e
EA		 5813{
5814 struct drm_device *dev = crtc->dev;
5815 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5816 struct drm_encoder_helper_funcs *encoder_funcs;
5817 struct intel_encoder *encoder;
0b701d27 5818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5819 struct drm_display_mode *adjusted_mode =
5820 &intel_crtc->config.adjusted_mode;
5821 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5822 int pipe = intel_crtc->pipe;
f564048e
EA		 5823 int ret;
5824
0b701d27 5825 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5826
b8cecdf5
DV		 5827 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5828
79e53945 5829 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5830
9256aa19
DV		 5831 if (ret != 0)
5832 return ret;
5833
5834 for_each_encoder_on_crtc(dev, crtc, encoder) {
5835 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5836 encoder->base.base.id,
5837 drm_get_encoder_name(&encoder->base),
5838 mode->base.id, mode->name);
6cc5f341
DV		 5839 if (encoder->mode_set) {
5840 encoder->mode_set(encoder);
5841 } else {
5842 encoder_funcs = encoder->base.helper_private;
5843 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5844 }
9256aa19
DV		 5845 }
5846
5847 return 0;
79e53945
JB		 5848}
5849
3a9627f4
WF		 5850static bool intel_eld_uptodate(struct drm_connector *connector,
5851 int reg_eldv, uint32_t bits_eldv,
5852 int reg_elda, uint32_t bits_elda,
5853 int reg_edid)
5854{
5855 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5856 uint8_t *eld = connector->eld;
5857 uint32_t i;
5858
5859 i = I915_READ(reg_eldv);
5860 i &= bits_eldv;
5861
5862 if (!eld[0])
5863 return !i;
5864
5865 if (!i)
5866 return false;
5867
5868 i = I915_READ(reg_elda);
5869 i &= ~bits_elda;
5870 I915_WRITE(reg_elda, i);
5871
5872 for (i = 0; i < eld[2]; i++)
5873 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5874 return false;
5875
5876 return true;
5877}
5878
e0dac65e
WF		 5879static void g4x_write_eld(struct drm_connector *connector,
5880 struct drm_crtc *crtc)
5881{
5882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5883 uint8_t *eld = connector->eld;
5884 uint32_t eldv;
5885 uint32_t len;
5886 uint32_t i;
5887
5888 i = I915_READ(G4X_AUD_VID_DID);
5889
5890 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5891 eldv = G4X_ELDV_DEVCL_DEVBLC;
5892 else
5893 eldv = G4X_ELDV_DEVCTG;
5894
3a9627f4
WF		 5895 if (intel_eld_uptodate(connector,
5896 G4X_AUD_CNTL_ST, eldv,
5897 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5898 G4X_HDMIW_HDMIEDID))
5899 return;
5900
e0dac65e
WF		 5901 i = I915_READ(G4X_AUD_CNTL_ST);
5902 i &= ~(eldv | G4X_ELD_ADDR);
5903 len = (i >> 9) & 0x1f; /* ELD buffer size */
5904 I915_WRITE(G4X_AUD_CNTL_ST, i);
5905
5906 if (!eld[0])
5907 return;
5908
5909 len = min_t(uint8_t, eld[2], len);
5910 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5911 for (i = 0; i < len; i++)
5912 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5913
5914 i = I915_READ(G4X_AUD_CNTL_ST);
5915 i |= eldv;
5916 I915_WRITE(G4X_AUD_CNTL_ST, i);
5917}
5918
83358c85
WX		 5919static void haswell_write_eld(struct drm_connector *connector,
5920 struct drm_crtc *crtc)
5921{
5922 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5923 uint8_t *eld = connector->eld;
5924 struct drm_device *dev = crtc->dev;
7b9f35a6 5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5926 uint32_t eldv;
5927 uint32_t i;
5928 int len;
5929 int pipe = to_intel_crtc(crtc)->pipe;
5930 int tmp;
5931
5932 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5933 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5934 int aud_config = HSW_AUD_CFG(pipe);
5935 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5936
5937
5938 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5939
5940 /* Audio output enable */
5941 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5942 tmp = I915_READ(aud_cntrl_st2);
5943 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5944 I915_WRITE(aud_cntrl_st2, tmp);
5945
5946 /* Wait for 1 vertical blank */
5947 intel_wait_for_vblank(dev, pipe);
5948
5949 /* Set ELD valid state */
5950 tmp = I915_READ(aud_cntrl_st2);
5951 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5952 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5953 I915_WRITE(aud_cntrl_st2, tmp);
5954 tmp = I915_READ(aud_cntrl_st2);
5955 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5956
5957 /* Enable HDMI mode */
5958 tmp = I915_READ(aud_config);
5959 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5960 /* clear N_programing_enable and N_value_index */
5961 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5962 I915_WRITE(aud_config, tmp);
5963
5964 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5965
5966 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5967 intel_crtc->eld_vld = true;
83358c85
WX		 5968
5969 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5970 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5971 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5972 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5973 } else
5974 I915_WRITE(aud_config, 0);
5975
5976 if (intel_eld_uptodate(connector,
5977 aud_cntrl_st2, eldv,
5978 aud_cntl_st, IBX_ELD_ADDRESS,
5979 hdmiw_hdmiedid))
5980 return;
5981
5982 i = I915_READ(aud_cntrl_st2);
5983 i &= ~eldv;
5984 I915_WRITE(aud_cntrl_st2, i);
5985
5986 if (!eld[0])
5987 return;
5988
5989 i = I915_READ(aud_cntl_st);
5990 i &= ~IBX_ELD_ADDRESS;
5991 I915_WRITE(aud_cntl_st, i);
5992 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5993 DRM_DEBUG_DRIVER("port num:%d\n", i);
5994
5995 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5996 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5997 for (i = 0; i < len; i++)
5998 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5999
6000 i = I915_READ(aud_cntrl_st2);
6001 i |= eldv;
6002 I915_WRITE(aud_cntrl_st2, i);
6003
6004}
6005
e0dac65e
WF		 6006static void ironlake_write_eld(struct drm_connector *connector,
6007 struct drm_crtc *crtc)
6008{
6009 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6010 uint8_t *eld = connector->eld;
6011 uint32_t eldv;
6012 uint32_t i;
6013 int len;
6014 int hdmiw_hdmiedid;
b6daa025 6015 int aud_config;
e0dac65e
WF		 6016 int aud_cntl_st;
6017 int aud_cntrl_st2;
9b138a83 6018 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6019
b3f33cbf 6020 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6021 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6022 aud_config = IBX_AUD_CFG(pipe);
6023 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6024 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6025 } else {
9b138a83
WX		 6026 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6027 aud_config = CPT_AUD_CFG(pipe);
6028 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6029 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6030 }
6031
9b138a83 6032 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6033
6034 i = I915_READ(aud_cntl_st);
9b138a83 6035 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6036 if (!i) {
6037 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6038 /* operate blindly on all ports */
1202b4c6
WF		 6039 eldv = IBX_ELD_VALIDB;
6040 eldv |= IBX_ELD_VALIDB << 4;
6041 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6042 } else {
6043 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6044 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6045 }
6046
3a9627f4
WF		 6047 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6048 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6049 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6050 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6051 } else
6052 I915_WRITE(aud_config, 0);
e0dac65e 6053
3a9627f4
WF		 6054 if (intel_eld_uptodate(connector,
6055 aud_cntrl_st2, eldv,
6056 aud_cntl_st, IBX_ELD_ADDRESS,
6057 hdmiw_hdmiedid))
6058 return;
6059
e0dac65e
WF		 6060 i = I915_READ(aud_cntrl_st2);
6061 i &= ~eldv;
6062 I915_WRITE(aud_cntrl_st2, i);
6063
6064 if (!eld[0])
6065 return;
6066
e0dac65e 6067 i = I915_READ(aud_cntl_st);
1202b4c6 6068 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6069 I915_WRITE(aud_cntl_st, i);
6070
6071 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6072 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6073 for (i = 0; i < len; i++)
6074 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6075
6076 i = I915_READ(aud_cntrl_st2);
6077 i |= eldv;
6078 I915_WRITE(aud_cntrl_st2, i);
6079}
6080
6081void intel_write_eld(struct drm_encoder *encoder,
6082 struct drm_display_mode *mode)
6083{
6084 struct drm_crtc *crtc = encoder->crtc;
6085 struct drm_connector *connector;
6086 struct drm_device *dev = encoder->dev;
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088
6089 connector = drm_select_eld(encoder, mode);
6090 if (!connector)
6091 return;
6092
6093 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6094 connector->base.id,
6095 drm_get_connector_name(connector),
6096 connector->encoder->base.id,
6097 drm_get_encoder_name(connector->encoder));
6098
6099 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6100
6101 if (dev_priv->display.write_eld)
6102 dev_priv->display.write_eld(connector, crtc);
6103}
6104
79e53945
JB		 6105/** Loads the palette/gamma unit for the CRTC with the prepared values */
6106void intel_crtc_load_lut(struct drm_crtc *crtc)
6107{
6108 struct drm_device *dev = crtc->dev;
6109 struct drm_i915_private *dev_priv = dev->dev_private;
6110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6111 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6112 int i;
6113
6114 /* The clocks have to be on to load the palette. */
aed3f09d 6115 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6116 return;
6117
f2b115e6 6118 /* use legacy palette for Ironlake */
bad720ff 6119 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6120 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6121
79e53945
JB		 6122 for (i = 0; i < 256; i++) {
6123 I915_WRITE(palreg + 4 * i,
6124 (intel_crtc->lut_r[i] << 16) |
6125 (intel_crtc->lut_g[i] << 8) |
6126 intel_crtc->lut_b[i]);
6127 }
6128}
6129
560b85bb
CW		 6130static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6131{
6132 struct drm_device *dev = crtc->dev;
6133 struct drm_i915_private *dev_priv = dev->dev_private;
6134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135 bool visible = base != 0;
6136 u32 cntl;
6137
6138 if (intel_crtc->cursor_visible == visible)
6139 return;
6140
9db4a9c7 6141 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6142 if (visible) {
6143 /* On these chipsets we can only modify the base whilst
6144 * the cursor is disabled.
6145 */
9db4a9c7 6146 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6147
6148 cntl &= ~(CURSOR_FORMAT_MASK);
6149 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6150 cntl |= CURSOR_ENABLE |
6151 CURSOR_GAMMA_ENABLE |
6152 CURSOR_FORMAT_ARGB;
6153 } else
6154 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6155 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6156
6157 intel_crtc->cursor_visible = visible;
6158}
6159
6160static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6161{
6162 struct drm_device *dev = crtc->dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165 int pipe = intel_crtc->pipe;
6166 bool visible = base != 0;
6167
6168 if (intel_crtc->cursor_visible != visible) {
548f245b 6169 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6170 if (base) {
6171 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6172 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6173 cntl |= pipe << 28; /* Connect to correct pipe */
6174 } else {
6175 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6176 cntl |= CURSOR_MODE_DISABLE;
6177 }
9db4a9c7 6178 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6179
6180 intel_crtc->cursor_visible = visible;
6181 }
6182 /* and commit changes on next vblank */
9db4a9c7 6183 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6184}
6185
65a21cd6
JB		 6186static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6187{
6188 struct drm_device *dev = crtc->dev;
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191 int pipe = intel_crtc->pipe;
6192 bool visible = base != 0;
6193
6194 if (intel_crtc->cursor_visible != visible) {
6195 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6196 if (base) {
6197 cntl &= ~CURSOR_MODE;
6198 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6199 } else {
6200 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6201 cntl |= CURSOR_MODE_DISABLE;
6202 }
86d3efce
VS		 6203 if (IS_HASWELL(dev))
6204 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6205 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6206
6207 intel_crtc->cursor_visible = visible;
6208 }
6209 /* and commit changes on next vblank */
6210 I915_WRITE(CURBASE_IVB(pipe), base);
6211}
6212
cda4b7d3 6213/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6214static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6215 bool on)
cda4b7d3
CW		 6216{
6217 struct drm_device *dev = crtc->dev;
6218 struct drm_i915_private *dev_priv = dev->dev_private;
6219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6220 int pipe = intel_crtc->pipe;
6221 int x = intel_crtc->cursor_x;
6222 int y = intel_crtc->cursor_y;
560b85bb 6223 u32 base, pos;
cda4b7d3
CW		 6224 bool visible;
6225
6226 pos = 0;
6227
6b383a7f 6228 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6229 base = intel_crtc->cursor_addr;
6230 if (x > (int) crtc->fb->width)
6231 base = 0;
6232
6233 if (y > (int) crtc->fb->height)
6234 base = 0;
6235 } else
6236 base = 0;
6237
6238 if (x < 0) {
6239 if (x + intel_crtc->cursor_width < 0)
6240 base = 0;
6241
6242 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6243 x = -x;
6244 }
6245 pos |= x << CURSOR_X_SHIFT;
6246
6247 if (y < 0) {
6248 if (y + intel_crtc->cursor_height < 0)
6249 base = 0;
6250
6251 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6252 y = -y;
6253 }
6254 pos |= y << CURSOR_Y_SHIFT;
6255
6256 visible = base != 0;
560b85bb 6257 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6258 return;
6259
0cd83aa9 6260 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6261 I915_WRITE(CURPOS_IVB(pipe), pos);
6262 ivb_update_cursor(crtc, base);
6263 } else {
6264 I915_WRITE(CURPOS(pipe), pos);
6265 if (IS_845G(dev) || IS_I865G(dev))
6266 i845_update_cursor(crtc, base);
6267 else
6268 i9xx_update_cursor(crtc, base);
6269 }
cda4b7d3
CW		 6270}
6271
79e53945 6272static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6273 struct drm_file *file,
79e53945
JB		 6274 uint32_t handle,
6275 uint32_t width, uint32_t height)
6276{
6277 struct drm_device *dev = crtc->dev;
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6280 struct drm_i915_gem_object *obj;
cda4b7d3 6281 uint32_t addr;
3f8bc370 6282 int ret;
79e53945 6283
79e53945
JB		 6284 /* if we want to turn off the cursor ignore width and height */
6285 if (!handle) {
28c97730 6286 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6287 addr = 0;
05394f39 6288 obj = NULL;
5004417d 6289 mutex_lock(&dev->struct_mutex);
3f8bc370 6290 goto finish;
79e53945
JB		 6291 }
6292
6293 /* Currently we only support 64x64 cursors */
6294 if (width != 64 || height != 64) {
6295 DRM_ERROR("we currently only support 64x64 cursors\n");
6296 return -EINVAL;
6297 }
6298
05394f39 6299 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6300 if (&obj->base == NULL)
79e53945
JB		 6301 return -ENOENT;
6302
05394f39 6303 if (obj->base.size < width * height * 4) {
79e53945 6304 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6305 ret = -ENOMEM;
6306 goto fail;
79e53945
JB		 6307 }
6308
71acb5eb 6309 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6310 mutex_lock(&dev->struct_mutex);
b295d1b6 6311 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6312 unsigned alignment;
6313
d9e86c0e
CW		 6314 if (obj->tiling_mode) {
6315 DRM_ERROR("cursor cannot be tiled\n");
6316 ret = -EINVAL;
6317 goto fail_locked;
6318 }
6319
693db184
CW		 6320 /* Note that the w/a also requires 2 PTE of padding following
6321 * the bo. We currently fill all unused PTE with the shadow
6322 * page and so we should always have valid PTE following the
6323 * cursor preventing the VT-d warning.
6324 */
6325 alignment = 0;
6326 if (need_vtd_wa(dev))
6327 alignment = 64*1024;
6328
6329 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6330 if (ret) {
6331 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6332 goto fail_locked;
e7b526bb
CW		 6333 }
6334
d9e86c0e
CW		 6335 ret = i915_gem_object_put_fence(obj);
6336 if (ret) {
2da3b9b9 6337 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6338 goto fail_unpin;
6339 }
6340
05394f39 6341 addr = obj->gtt_offset;
71acb5eb 6342 } else {
6eeefaf3 6343 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6344 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6345 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6346 align);
71acb5eb
DA		 6347 if (ret) {
6348 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6349 goto fail_locked;
71acb5eb 6350 }
05394f39 6351 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6352 }
6353
a6c45cf0 6354 if (IS_GEN2(dev))
14b60391
JB		 6355 I915_WRITE(CURSIZE, (height << 12) | width);
6356
3f8bc370 6357 finish:
3f8bc370 6358 if (intel_crtc->cursor_bo) {
b295d1b6 6359 if (dev_priv->info->cursor_needs_physical) {
05394f39 6360 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6361 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6362 } else
6363 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6364 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6365 }
80824003 6366
7f9872e0 6367 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6368
6369 intel_crtc->cursor_addr = addr;
05394f39 6370 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6371 intel_crtc->cursor_width = width;
6372 intel_crtc->cursor_height = height;
6373
6b383a7f 6374 intel_crtc_update_cursor(crtc, true);
3f8bc370 6375
79e53945 6376 return 0;
e7b526bb 6377fail_unpin:
05394f39 6378 i915_gem_object_unpin(obj);
7f9872e0 6379fail_locked:
34b8686e 6380 mutex_unlock(&dev->struct_mutex);
bc9025bd 6381fail:
05394f39 6382 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6383 return ret;
79e53945
JB		 6384}
6385
6386static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6387{
79e53945 6388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6389
cda4b7d3
CW		 6390 intel_crtc->cursor_x = x;
6391 intel_crtc->cursor_y = y;
652c393a 6392
6b383a7f 6393 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6394
6395 return 0;
6396}
6397
6398/** Sets the color ramps on behalf of RandR */
6399void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6400 u16 blue, int regno)
6401{
6402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6403
6404 intel_crtc->lut_r[regno] = red >> 8;
6405 intel_crtc->lut_g[regno] = green >> 8;
6406 intel_crtc->lut_b[regno] = blue >> 8;
6407}
6408
b8c00ac5
DA		 6409void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6410 u16 *blue, int regno)
6411{
6412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6413
6414 *red = intel_crtc->lut_r[regno] << 8;
6415 *green = intel_crtc->lut_g[regno] << 8;
6416 *blue = intel_crtc->lut_b[regno] << 8;
6417}
6418
79e53945 6419static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6420 u16 *blue, uint32_t start, uint32_t size)
79e53945 6421{
7203425a 6422 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6424
7203425a 6425 for (i = start; i < end; i++) {
79e53945
JB		 6426 intel_crtc->lut_r[i] = red[i] >> 8;
6427 intel_crtc->lut_g[i] = green[i] >> 8;
6428 intel_crtc->lut_b[i] = blue[i] >> 8;
6429 }
6430
6431 intel_crtc_load_lut(crtc);
6432}
6433
79e53945
JB		 6434/* VESA 640x480x72Hz mode to set on the pipe */
6435static struct drm_display_mode load_detect_mode = {
6436 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6437 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6438};
6439
d2dff872
CW		 6440static struct drm_framebuffer *
6441intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6442 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6443 struct drm_i915_gem_object *obj)
6444{
6445 struct intel_framebuffer *intel_fb;
6446 int ret;
6447
6448 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6449 if (!intel_fb) {
6450 drm_gem_object_unreference_unlocked(&obj->base);
6451 return ERR_PTR(-ENOMEM);
6452 }
6453
6454 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6455 if (ret) {
6456 drm_gem_object_unreference_unlocked(&obj->base);
6457 kfree(intel_fb);
6458 return ERR_PTR(ret);
6459 }
6460
6461 return &intel_fb->base;
6462}
6463
6464static u32
6465intel_framebuffer_pitch_for_width(int width, int bpp)
6466{
6467 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6468 return ALIGN(pitch, 64);
6469}
6470
6471static u32
6472intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6473{
6474 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6475 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6476}
6477
6478static struct drm_framebuffer *
6479intel_framebuffer_create_for_mode(struct drm_device *dev,
6480 struct drm_display_mode *mode,
6481 int depth, int bpp)
6482{
6483 struct drm_i915_gem_object *obj;
0fed39bd 6484 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6485
6486 obj = i915_gem_alloc_object(dev,
6487 intel_framebuffer_size_for_mode(mode, bpp));
6488 if (obj == NULL)
6489 return ERR_PTR(-ENOMEM);
6490
6491 mode_cmd.width = mode->hdisplay;
6492 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6493 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6494 bpp);
5ca0c34a 6495 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6496
6497 return intel_framebuffer_create(dev, &mode_cmd, obj);
6498}
6499
6500static struct drm_framebuffer *
6501mode_fits_in_fbdev(struct drm_device *dev,
6502 struct drm_display_mode *mode)
6503{
6504 struct drm_i915_private *dev_priv = dev->dev_private;
6505 struct drm_i915_gem_object *obj;
6506 struct drm_framebuffer *fb;
6507
6508 if (dev_priv->fbdev == NULL)
6509 return NULL;
6510
6511 obj = dev_priv->fbdev->ifb.obj;
6512 if (obj == NULL)
6513 return NULL;
6514
6515 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6516 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6517 fb->bits_per_pixel))
d2dff872
CW		 6518 return NULL;
6519
01f2c773 6520 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6521 return NULL;
6522
6523 return fb;
6524}
6525
d2434ab7 6526bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6527 struct drm_display_mode *mode,
8261b191 6528 struct intel_load_detect_pipe *old)
79e53945
JB		 6529{
6530 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6531 struct intel_encoder *intel_encoder =
6532 intel_attached_encoder(connector);
79e53945 6533 struct drm_crtc *possible_crtc;
4ef69c7a 6534 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6535 struct drm_crtc *crtc = NULL;
6536 struct drm_device *dev = encoder->dev;
94352cf9 6537 struct drm_framebuffer *fb;
79e53945
JB		 6538 int i = -1;
6539
d2dff872
CW		 6540 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6541 connector->base.id, drm_get_connector_name(connector),
6542 encoder->base.id, drm_get_encoder_name(encoder));
6543
79e53945
JB		 6544 /*
6545 * Algorithm gets a little messy:
7a5e4805 6546 *
79e53945
JB		 6547 * - if the connector already has an assigned crtc, use it (but make
6548 * sure it's on first)
7a5e4805 6549 *
79e53945
JB		 6550 * - try to find the first unused crtc that can drive this connector,
6551 * and use that if we find one
79e53945
JB		 6552 */
6553
6554 /* See if we already have a CRTC for this connector */
6555 if (encoder->crtc) {
6556 crtc = encoder->crtc;
8261b191 6557
7b24056b
DV		 6558 mutex_lock(&crtc->mutex);
6559
24218aac 6560 old->dpms_mode = connector->dpms;
8261b191
CW		 6561 old->load_detect_temp = false;
6562
6563 /* Make sure the crtc and connector are running */
24218aac
DV		 6564 if (connector->dpms != DRM_MODE_DPMS_ON)
6565 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6566
7173188d 6567 return true;
79e53945
JB		 6568 }
6569
6570 /* Find an unused one (if possible) */
6571 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6572 i++;
6573 if (!(encoder->possible_crtcs & (1 << i)))
6574 continue;
6575 if (!possible_crtc->enabled) {
6576 crtc = possible_crtc;
6577 break;
6578 }
79e53945
JB		 6579 }
6580
6581 /*
6582 * If we didn't find an unused CRTC, don't use any.
6583 */
6584 if (!crtc) {
7173188d
CW		 6585 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6586 return false;
79e53945
JB		 6587 }
6588
7b24056b 6589 mutex_lock(&crtc->mutex);
fc303101
DV		 6590 intel_encoder->new_crtc = to_intel_crtc(crtc);
6591 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6592
6593 intel_crtc = to_intel_crtc(crtc);
24218aac 6594 old->dpms_mode = connector->dpms;
8261b191 6595 old->load_detect_temp = true;
d2dff872 6596 old->release_fb = NULL;
79e53945 6597
6492711d
CW		 6598 if (!mode)
6599 mode = &load_detect_mode;
79e53945 6600
d2dff872
CW		 6601 /* We need a framebuffer large enough to accommodate all accesses
6602 * that the plane may generate whilst we perform load detection.
6603 * We can not rely on the fbcon either being present (we get called
6604 * during its initialisation to detect all boot displays, or it may
6605 * not even exist) or that it is large enough to satisfy the
6606 * requested mode.
6607 */
94352cf9
DV		 6608 fb = mode_fits_in_fbdev(dev, mode);
6609 if (fb == NULL) {
d2dff872 6610 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6611 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6612 old->release_fb = fb;
d2dff872
CW		 6613 } else
6614 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6615 if (IS_ERR(fb)) {
d2dff872 6616 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6617 mutex_unlock(&crtc->mutex);
0e8b3d3e 6618 return false;
79e53945 6619 }
79e53945 6620
c0c36b94 6621 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6622 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6623 if (old->release_fb)
6624 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6625 mutex_unlock(&crtc->mutex);
0e8b3d3e 6626 return false;
79e53945 6627 }
7173188d 6628
79e53945 6629 /* let the connector get through one full cycle before testing */
9d0498a2 6630 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6631 return true;
79e53945
JB		 6632}
6633
d2434ab7 6634void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6635 struct intel_load_detect_pipe *old)
79e53945 6636{
d2434ab7
DV		 6637 struct intel_encoder *intel_encoder =
6638 intel_attached_encoder(connector);
4ef69c7a 6639 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6640 struct drm_crtc *crtc = encoder->crtc;
79e53945 6641
d2dff872
CW		 6642 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6643 connector->base.id, drm_get_connector_name(connector),
6644 encoder->base.id, drm_get_encoder_name(encoder));
6645
8261b191 6646 if (old->load_detect_temp) {
fc303101
DV		 6647 to_intel_connector(connector)->new_encoder = NULL;
6648 intel_encoder->new_crtc = NULL;
6649 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6650
36206361
DV		 6651 if (old->release_fb) {
6652 drm_framebuffer_unregister_private(old->release_fb);
6653 drm_framebuffer_unreference(old->release_fb);
6654 }
d2dff872 6655
67c96400 6656 mutex_unlock(&crtc->mutex);
0622a53c 6657 return;
79e53945
JB		 6658 }
6659
c751ce4f 6660 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6661 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6662 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6663
6664 mutex_unlock(&crtc->mutex);
79e53945
JB		 6665}
6666
6667/* Returns the clock of the currently programmed mode of the given pipe. */
6668static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6669{
6670 struct drm_i915_private *dev_priv = dev->dev_private;
6671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6672 int pipe = intel_crtc->pipe;
548f245b 6673 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6674 u32 fp;
6675 intel_clock_t clock;
6676
6677 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6678 fp = I915_READ(FP0(pipe));
79e53945 6679 else
39adb7a5 6680 fp = I915_READ(FP1(pipe));
79e53945
JB		 6681
6682 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6683 if (IS_PINEVIEW(dev)) {
6684 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6685 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6686 } else {
6687 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6688 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6689 }
6690
a6c45cf0 6691 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6692 if (IS_PINEVIEW(dev))
6693 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6694 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6695 else
6696 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6697 DPLL_FPA01_P1_POST_DIV_SHIFT);
6698
6699 switch (dpll & DPLL_MODE_MASK) {
6700 case DPLLB_MODE_DAC_SERIAL:
6701 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6702 5 : 10;
6703 break;
6704 case DPLLB_MODE_LVDS:
6705 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6706 7 : 14;
6707 break;
6708 default:
28c97730 6709 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6710 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6711 return 0;
6712 }
6713
6714 /* XXX: Handle the 100Mhz refclk */
2177832f 6715 intel_clock(dev, 96000, &clock);
79e53945
JB		 6716 } else {
6717 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6718
6719 if (is_lvds) {
6720 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6721 DPLL_FPA01_P1_POST_DIV_SHIFT);
6722 clock.p2 = 14;
6723
6724 if ((dpll & PLL_REF_INPUT_MASK) ==
6725 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6726 /* XXX: might not be 66MHz */
2177832f 6727 intel_clock(dev, 66000, &clock);
79e53945 6728 } else
2177832f 6729 intel_clock(dev, 48000, &clock);
79e53945
JB		 6730 } else {
6731 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6732 clock.p1 = 2;
6733 else {
6734 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6735 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6736 }
6737 if (dpll & PLL_P2_DIVIDE_BY_4)
6738 clock.p2 = 4;
6739 else
6740 clock.p2 = 2;
6741
2177832f 6742 intel_clock(dev, 48000, &clock);
79e53945
JB		 6743 }
6744 }
6745
6746 /* XXX: It would be nice to validate the clocks, but we can't reuse
6747 * i830PllIsValid() because it relies on the xf86_config connector
6748 * configuration being accurate, which it isn't necessarily.
6749 */
6750
6751 return clock.dot;
6752}
6753
6754/** Returns the currently programmed mode of the given pipe. */
6755struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6756 struct drm_crtc *crtc)
6757{
548f245b 6758 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6760 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6761 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6762 int htot = I915_READ(HTOTAL(cpu_transcoder));
6763 int hsync = I915_READ(HSYNC(cpu_transcoder));
6764 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6765 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6766
6767 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6768 if (!mode)
6769 return NULL;
6770
6771 mode->clock = intel_crtc_clock_get(dev, crtc);
6772 mode->hdisplay = (htot & 0xffff) + 1;
6773 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6774 mode->hsync_start = (hsync & 0xffff) + 1;
6775 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6776 mode->vdisplay = (vtot & 0xffff) + 1;
6777 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6778 mode->vsync_start = (vsync & 0xffff) + 1;
6779 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6780
6781 drm_mode_set_name(mode);
79e53945
JB		 6782
6783 return mode;
6784}
6785
3dec0095 6786static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6787{
6788 struct drm_device *dev = crtc->dev;
6789 drm_i915_private_t *dev_priv = dev->dev_private;
6790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6791 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6792 int dpll_reg = DPLL(pipe);
6793 int dpll;
652c393a 6794
bad720ff 6795 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6796 return;
6797
6798 if (!dev_priv->lvds_downclock_avail)
6799 return;
6800
dbdc6479 6801 dpll = I915_READ(dpll_reg);
652c393a 6802 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6803 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6804
8ac5a6d5 6805 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6806
6807 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6808 I915_WRITE(dpll_reg, dpll);
9d0498a2 6809 intel_wait_for_vblank(dev, pipe);
dbdc6479 6810
652c393a
JB		 6811 dpll = I915_READ(dpll_reg);
6812 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6813 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6814 }
652c393a
JB		 6815}
6816
6817static void intel_decrease_pllclock(struct drm_crtc *crtc)
6818{
6819 struct drm_device *dev = crtc->dev;
6820 drm_i915_private_t *dev_priv = dev->dev_private;
6821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6822
bad720ff 6823 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6824 return;
6825
6826 if (!dev_priv->lvds_downclock_avail)
6827 return;
6828
6829 /*
6830 * Since this is called by a timer, we should never get here in
6831 * the manual case.
6832 */
6833 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6834 int pipe = intel_crtc->pipe;
6835 int dpll_reg = DPLL(pipe);
6836 int dpll;
f6e5b160 6837
44d98a61 6838 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6839
8ac5a6d5 6840 assert_panel_unlocked(dev_priv, pipe);
652c393a 6841
dc257cf1 6842 dpll = I915_READ(dpll_reg);
652c393a
JB		 6843 dpll |= DISPLAY_RATE_SELECT_FPA1;
6844 I915_WRITE(dpll_reg, dpll);
9d0498a2 6845 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6846 dpll = I915_READ(dpll_reg);
6847 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6848 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6849 }
6850
6851}
6852
f047e395
CW		 6853void intel_mark_busy(struct drm_device *dev)
6854{
f047e395
CW		 6855 i915_update_gfx_val(dev->dev_private);
6856}
6857
6858void intel_mark_idle(struct drm_device *dev)
652c393a 6859{
652c393a 6860 struct drm_crtc *crtc;
652c393a
JB		 6861
6862 if (!i915_powersave)
6863 return;
6864
652c393a 6865 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6866 if (!crtc->fb)
6867 continue;
6868
725a5b54 6869 intel_decrease_pllclock(crtc);
652c393a 6870 }
652c393a
JB		 6871}
6872
725a5b54 6873void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6874{
f047e395
CW		 6875 struct drm_device *dev = obj->base.dev;
6876 struct drm_crtc *crtc;
652c393a 6877
f047e395 6878 if (!i915_powersave)
acb87dfb
CW		 6879 return;
6880
652c393a
JB		 6881 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6882 if (!crtc->fb)
6883 continue;
6884
f047e395 6885 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6886 intel_increase_pllclock(crtc);
652c393a
JB		 6887 }
6888}
6889
79e53945
JB		 6890static void intel_crtc_destroy(struct drm_crtc *crtc)
6891{
6892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6893 struct drm_device *dev = crtc->dev;
6894 struct intel_unpin_work *work;
6895 unsigned long flags;
6896
6897 spin_lock_irqsave(&dev->event_lock, flags);
6898 work = intel_crtc->unpin_work;
6899 intel_crtc->unpin_work = NULL;
6900 spin_unlock_irqrestore(&dev->event_lock, flags);
6901
6902 if (work) {
6903 cancel_work_sync(&work->work);
6904 kfree(work);
6905 }
79e53945
JB		 6906
6907 drm_crtc_cleanup(crtc);
67e77c5a 6908
79e53945
JB		 6909 kfree(intel_crtc);
6910}
6911
6b95a207
KH		 6912static void intel_unpin_work_fn(struct work_struct *__work)
6913{
6914 struct intel_unpin_work *work =
6915 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6916 struct drm_device *dev = work->crtc->dev;
6b95a207 6917
b4a98e57 6918 mutex_lock(&dev->struct_mutex);
1690e1eb 6919 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6920 drm_gem_object_unreference(&work->pending_flip_obj->base);
6921 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6922
b4a98e57
CW		 6923 intel_update_fbc(dev);
6924 mutex_unlock(&dev->struct_mutex);
6925
6926 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6927 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6928
6b95a207
KH		 6929 kfree(work);
6930}
6931
1afe3e9d 6932static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6933 struct drm_crtc *crtc)
6b95a207
KH		 6934{
6935 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6937 struct intel_unpin_work *work;
6b95a207
KH		 6938 unsigned long flags;
6939
6940 /* Ignore early vblank irqs */
6941 if (intel_crtc == NULL)
6942 return;
6943
6944 spin_lock_irqsave(&dev->event_lock, flags);
6945 work = intel_crtc->unpin_work;
e7d841ca
CW		 6946
6947 /* Ensure we don't miss a work->pending update ... */
6948 smp_rmb();
6949
6950 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6951 spin_unlock_irqrestore(&dev->event_lock, flags);
6952 return;
6953 }
6954
e7d841ca
CW		 6955 /* and that the unpin work is consistent wrt ->pending. */
6956 smp_rmb();
6957
6b95a207 6958 intel_crtc->unpin_work = NULL;
6b95a207 6959
45a066eb
RC		 6960 if (work->event)
6961 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6962
0af7e4df
MK		 6963 drm_vblank_put(dev, intel_crtc->pipe);
6964
6b95a207
KH		 6965 spin_unlock_irqrestore(&dev->event_lock, flags);
6966
2c10d571 6967 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6968
6969 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6970
6971 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6972}
6973
1afe3e9d
JB		 6974void intel_finish_page_flip(struct drm_device *dev, int pipe)
6975{
6976 drm_i915_private_t *dev_priv = dev->dev_private;
6977 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6978
49b14a5c 6979 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6980}
6981
6982void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6983{
6984 drm_i915_private_t *dev_priv = dev->dev_private;
6985 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6986
49b14a5c 6987 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6988}
6989
6b95a207
KH		 6990void intel_prepare_page_flip(struct drm_device *dev, int plane)
6991{
6992 drm_i915_private_t *dev_priv = dev->dev_private;
6993 struct intel_crtc *intel_crtc =
6994 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6995 unsigned long flags;
6996
e7d841ca
CW		 6997 /* NB: An MMIO update of the plane base pointer will also
6998 * generate a page-flip completion irq, i.e. every modeset
6999 * is also accompanied by a spurious intel_prepare_page_flip().
7000 */
6b95a207 7001 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7002 if (intel_crtc->unpin_work)
7003 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7004 spin_unlock_irqrestore(&dev->event_lock, flags);
7005}
7006
e7d841ca
CW		 7007inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7008{
7009 /* Ensure that the work item is consistent when activating it ... */
7010 smp_wmb();
7011 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7012 /* and that it is marked active as soon as the irq could fire. */
7013 smp_wmb();
7014}
7015
8c9f3aaf
JB		 7016static int intel_gen2_queue_flip(struct drm_device *dev,
7017 struct drm_crtc *crtc,
7018 struct drm_framebuffer *fb,
7019 struct drm_i915_gem_object *obj)
7020{
7021 struct drm_i915_private *dev_priv = dev->dev_private;
7022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7023 u32 flip_mask;
6d90c952 7024 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7025 int ret;
7026
6d90c952 7027 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7028 if (ret)
83d4092b 7029 goto err;
8c9f3aaf 7030
6d90c952 7031 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7032 if (ret)
83d4092b 7033 goto err_unpin;
8c9f3aaf
JB		 7034
7035 /* Can't queue multiple flips, so wait for the previous
7036 * one to finish before executing the next.
7037 */
7038 if (intel_crtc->plane)
7039 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7040 else
7041 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7042 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7043 intel_ring_emit(ring, MI_NOOP);
7044 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7045 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7046 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7047 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7048 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7049
7050 intel_mark_page_flip_active(intel_crtc);
6d90c952 7051 intel_ring_advance(ring);
83d4092b
CW		 7052 return 0;
7053
7054err_unpin:
7055 intel_unpin_fb_obj(obj);
7056err:
8c9f3aaf
JB		 7057 return ret;
7058}
7059
7060static int intel_gen3_queue_flip(struct drm_device *dev,
7061 struct drm_crtc *crtc,
7062 struct drm_framebuffer *fb,
7063 struct drm_i915_gem_object *obj)
7064{
7065 struct drm_i915_private *dev_priv = dev->dev_private;
7066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7067 u32 flip_mask;
6d90c952 7068 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7069 int ret;
7070
6d90c952 7071 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7072 if (ret)
83d4092b 7073 goto err;
8c9f3aaf 7074
6d90c952 7075 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7076 if (ret)
83d4092b 7077 goto err_unpin;
8c9f3aaf
JB		 7078
7079 if (intel_crtc->plane)
7080 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7081 else
7082 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7083 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7084 intel_ring_emit(ring, MI_NOOP);
7085 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7086 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7087 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7088 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7089 intel_ring_emit(ring, MI_NOOP);
7090
e7d841ca 7091 intel_mark_page_flip_active(intel_crtc);
6d90c952 7092 intel_ring_advance(ring);
83d4092b
CW		 7093 return 0;
7094
7095err_unpin:
7096 intel_unpin_fb_obj(obj);
7097err:
8c9f3aaf
JB		 7098 return ret;
7099}
7100
7101static int intel_gen4_queue_flip(struct drm_device *dev,
7102 struct drm_crtc *crtc,
7103 struct drm_framebuffer *fb,
7104 struct drm_i915_gem_object *obj)
7105{
7106 struct drm_i915_private *dev_priv = dev->dev_private;
7107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7108 uint32_t pf, pipesrc;
6d90c952 7109 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7110 int ret;
7111
6d90c952 7112 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7113 if (ret)
83d4092b 7114 goto err;
8c9f3aaf 7115
6d90c952 7116 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7117 if (ret)
83d4092b 7118 goto err_unpin;
8c9f3aaf
JB		 7119
7120 /* i965+ uses the linear or tiled offsets from the
7121 * Display Registers (which do not change across a page-flip)
7122 * so we need only reprogram the base address.
7123 */
6d90c952
DV		 7124 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7125 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7126 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7127 intel_ring_emit(ring,
7128 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7129 obj->tiling_mode);
8c9f3aaf
JB		 7130
7131 /* XXX Enabling the panel-fitter across page-flip is so far
7132 * untested on non-native modes, so ignore it for now.
7133 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7134 */
7135 pf = 0;
7136 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7137 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7138
7139 intel_mark_page_flip_active(intel_crtc);
6d90c952 7140 intel_ring_advance(ring);
83d4092b
CW		 7141 return 0;
7142
7143err_unpin:
7144 intel_unpin_fb_obj(obj);
7145err:
8c9f3aaf
JB		 7146 return ret;
7147}
7148
7149static int intel_gen6_queue_flip(struct drm_device *dev,
7150 struct drm_crtc *crtc,
7151 struct drm_framebuffer *fb,
7152 struct drm_i915_gem_object *obj)
7153{
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7156 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7157 uint32_t pf, pipesrc;
7158 int ret;
7159
6d90c952 7160 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7161 if (ret)
83d4092b 7162 goto err;
8c9f3aaf 7163
6d90c952 7164 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7165 if (ret)
83d4092b 7166 goto err_unpin;
8c9f3aaf 7167
6d90c952
DV		 7168 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7169 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7170 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7171 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7172
dc257cf1
DV		 7173 /* Contrary to the suggestions in the documentation,
7174 * "Enable Panel Fitter" does not seem to be required when page
7175 * flipping with a non-native mode, and worse causes a normal
7176 * modeset to fail.
7177 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7178 */
7179 pf = 0;
8c9f3aaf 7180 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7181 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7182
7183 intel_mark_page_flip_active(intel_crtc);
6d90c952 7184 intel_ring_advance(ring);
83d4092b
CW		 7185 return 0;
7186
7187err_unpin:
7188 intel_unpin_fb_obj(obj);
7189err:
8c9f3aaf
JB		 7190 return ret;
7191}
7192
7c9017e5
JB		 7193/*
7194 * On gen7 we currently use the blit ring because (in early silicon at least)
7195 * the render ring doesn't give us interrpts for page flip completion, which
7196 * means clients will hang after the first flip is queued. Fortunately the
7197 * blit ring generates interrupts properly, so use it instead.
7198 */
7199static int intel_gen7_queue_flip(struct drm_device *dev,
7200 struct drm_crtc *crtc,
7201 struct drm_framebuffer *fb,
7202 struct drm_i915_gem_object *obj)
7203{
7204 struct drm_i915_private *dev_priv = dev->dev_private;
7205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7206 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7207 uint32_t plane_bit = 0;
7c9017e5
JB		 7208 int ret;
7209
7210 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7211 if (ret)
83d4092b 7212 goto err;
7c9017e5 7213
cb05d8de
DV		 7214 switch(intel_crtc->plane) {
7215 case PLANE_A:
7216 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7217 break;
7218 case PLANE_B:
7219 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7220 break;
7221 case PLANE_C:
7222 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7223 break;
7224 default:
7225 WARN_ONCE(1, "unknown plane in flip command\n");
7226 ret = -ENODEV;
ab3951eb 7227 goto err_unpin;
cb05d8de
DV		 7228 }
7229
7c9017e5
JB		 7230 ret = intel_ring_begin(ring, 4);
7231 if (ret)
83d4092b 7232 goto err_unpin;
7c9017e5 7233
cb05d8de 7234 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7235 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7236 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7237 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7238
7239 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7240 intel_ring_advance(ring);
83d4092b
CW		 7241 return 0;
7242
7243err_unpin:
7244 intel_unpin_fb_obj(obj);
7245err:
7c9017e5
JB		 7246 return ret;
7247}
7248
8c9f3aaf
JB		 7249static int intel_default_queue_flip(struct drm_device *dev,
7250 struct drm_crtc *crtc,
7251 struct drm_framebuffer *fb,
7252 struct drm_i915_gem_object *obj)
7253{
7254 return -ENODEV;
7255}
7256
6b95a207
KH		 7257static int intel_crtc_page_flip(struct drm_crtc *crtc,
7258 struct drm_framebuffer *fb,
7259 struct drm_pending_vblank_event *event)
7260{
7261 struct drm_device *dev = crtc->dev;
7262 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7263 struct drm_framebuffer *old_fb = crtc->fb;
7264 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7266 struct intel_unpin_work *work;
8c9f3aaf 7267 unsigned long flags;
52e68630 7268 int ret;
6b95a207 7269
e6a595d2
VS		 7270 /* Can't change pixel format via MI display flips. */
7271 if (fb->pixel_format != crtc->fb->pixel_format)
7272 return -EINVAL;
7273
7274 /*
7275 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7276 * Note that pitch changes could also affect these register.
7277 */
7278 if (INTEL_INFO(dev)->gen > 3 &&
7279 (fb->offsets[0] != crtc->fb->offsets[0] ||
7280 fb->pitches[0] != crtc->fb->pitches[0]))
7281 return -EINVAL;
7282
6b95a207
KH		 7283 work = kzalloc(sizeof *work, GFP_KERNEL);
7284 if (work == NULL)
7285 return -ENOMEM;
7286
6b95a207 7287 work->event = event;
b4a98e57 7288 work->crtc = crtc;
4a35f83b 7289 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7290 INIT_WORK(&work->work, intel_unpin_work_fn);
7291
7317c75e
JB		 7292 ret = drm_vblank_get(dev, intel_crtc->pipe);
7293 if (ret)
7294 goto free_work;
7295
6b95a207
KH		 7296 /* We borrow the event spin lock for protecting unpin_work */
7297 spin_lock_irqsave(&dev->event_lock, flags);
7298 if (intel_crtc->unpin_work) {
7299 spin_unlock_irqrestore(&dev->event_lock, flags);
7300 kfree(work);
7317c75e 7301 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7302
7303 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7304 return -EBUSY;
7305 }
7306 intel_crtc->unpin_work = work;
7307 spin_unlock_irqrestore(&dev->event_lock, flags);
7308
b4a98e57
CW		 7309 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7310 flush_workqueue(dev_priv->wq);
7311
79158103
CW		 7312 ret = i915_mutex_lock_interruptible(dev);
7313 if (ret)
7314 goto cleanup;
6b95a207 7315
75dfca80 7316 /* Reference the objects for the scheduled work. */
05394f39
CW		 7317 drm_gem_object_reference(&work->old_fb_obj->base);
7318 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7319
7320 crtc->fb = fb;
96b099fd 7321
e1f99ce6 7322 work->pending_flip_obj = obj;
e1f99ce6 7323
4e5359cd
SF		 7324 work->enable_stall_check = true;
7325
b4a98e57 7326 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7327 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7328
8c9f3aaf
JB		 7329 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7330 if (ret)
7331 goto cleanup_pending;
6b95a207 7332
7782de3b 7333 intel_disable_fbc(dev);
f047e395 7334 intel_mark_fb_busy(obj);
6b95a207
KH		 7335 mutex_unlock(&dev->struct_mutex);
7336
e5510fac
JB		 7337 trace_i915_flip_request(intel_crtc->plane, obj);
7338
6b95a207 7339 return 0;
96b099fd 7340
8c9f3aaf 7341cleanup_pending:
b4a98e57 7342 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7343 crtc->fb = old_fb;
05394f39
CW		 7344 drm_gem_object_unreference(&work->old_fb_obj->base);
7345 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7346 mutex_unlock(&dev->struct_mutex);
7347
79158103 7348cleanup:
96b099fd
CW		 7349 spin_lock_irqsave(&dev->event_lock, flags);
7350 intel_crtc->unpin_work = NULL;
7351 spin_unlock_irqrestore(&dev->event_lock, flags);
7352
7317c75e
JB		 7353 drm_vblank_put(dev, intel_crtc->pipe);
7354free_work:
96b099fd
CW		 7355 kfree(work);
7356
7357 return ret;
6b95a207
KH		 7358}
7359
f6e5b160 7360static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7361 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7362 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7363};
7364
6ed0f796 7365bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7366{
6ed0f796
DV		 7367 struct intel_encoder *other_encoder;
7368 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7369
6ed0f796
DV		 7370 if (WARN_ON(!crtc))
7371 return false;
7372
7373 list_for_each_entry(other_encoder,
7374 &crtc->dev->mode_config.encoder_list,
7375 base.head) {
7376
7377 if (&other_encoder->new_crtc->base != crtc ||
7378 encoder == other_encoder)
7379 continue;
7380 else
7381 return true;
f47166d2
CW		 7382 }
7383
6ed0f796
DV		 7384 return false;
7385}
47f1c6c9 7386
50f56119
DV		 7387static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7388 struct drm_crtc *crtc)
7389{
7390 struct drm_device *dev;
7391 struct drm_crtc *tmp;
7392 int crtc_mask = 1;
47f1c6c9 7393
50f56119 7394 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7395
50f56119 7396 dev = crtc->dev;
47f1c6c9 7397
50f56119
DV		 7398 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7399 if (tmp == crtc)
7400 break;
7401 crtc_mask <<= 1;
7402 }
47f1c6c9 7403
50f56119
DV		 7404 if (encoder->possible_crtcs & crtc_mask)
7405 return true;
7406 return false;
47f1c6c9 7407}
79e53945 7408
9a935856
DV		 7409/**
7410 * intel_modeset_update_staged_output_state
7411 *
7412 * Updates the staged output configuration state, e.g. after we've read out the
7413 * current hw state.
7414 */
7415static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7416{
9a935856
DV		 7417 struct intel_encoder *encoder;
7418 struct intel_connector *connector;
f6e5b160 7419
9a935856
DV		 7420 list_for_each_entry(connector, &dev->mode_config.connector_list,
7421 base.head) {
7422 connector->new_encoder =
7423 to_intel_encoder(connector->base.encoder);
7424 }
f6e5b160 7425
9a935856
DV		 7426 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7427 base.head) {
7428 encoder->new_crtc =
7429 to_intel_crtc(encoder->base.crtc);
7430 }
f6e5b160
CW		 7431}
7432
9a935856
DV		 7433/**
7434 * intel_modeset_commit_output_state
7435 *
7436 * This function copies the stage display pipe configuration to the real one.
7437 */
7438static void intel_modeset_commit_output_state(struct drm_device *dev)
7439{
7440 struct intel_encoder *encoder;
7441 struct intel_connector *connector;
f6e5b160 7442
9a935856
DV		 7443 list_for_each_entry(connector, &dev->mode_config.connector_list,
7444 base.head) {
7445 connector->base.encoder = &connector->new_encoder->base;
7446 }
f6e5b160 7447
9a935856
DV		 7448 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7449 base.head) {
7450 encoder->base.crtc = &encoder->new_crtc->base;
7451 }
7452}
7453
4e53c2e0
DV		 7454static int
7455pipe_config_set_bpp(struct drm_crtc *crtc,
7456 struct drm_framebuffer *fb,
7457 struct intel_crtc_config *pipe_config)
7458{
7459 struct drm_device *dev = crtc->dev;
7460 struct drm_connector *connector;
7461 int bpp;
7462
d42264b1
DV		 7463 switch (fb->pixel_format) {
7464 case DRM_FORMAT_C8:
4e53c2e0
DV		 7465 bpp = 8*3; /* since we go through a colormap */
7466 break;
d42264b1
DV		 7467 case DRM_FORMAT_XRGB1555:
7468 case DRM_FORMAT_ARGB1555:
7469 /* checked in intel_framebuffer_init already */
7470 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7471 return -EINVAL;
7472 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7473 bpp = 6*3; /* min is 18bpp */
7474 break;
d42264b1
DV		 7475 case DRM_FORMAT_XBGR8888:
7476 case DRM_FORMAT_ABGR8888:
7477 /* checked in intel_framebuffer_init already */
7478 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7479 return -EINVAL;
7480 case DRM_FORMAT_XRGB8888:
7481 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7482 bpp = 8*3;
7483 break;
d42264b1
DV		 7484 case DRM_FORMAT_XRGB2101010:
7485 case DRM_FORMAT_ARGB2101010:
7486 case DRM_FORMAT_XBGR2101010:
7487 case DRM_FORMAT_ABGR2101010:
7488 /* checked in intel_framebuffer_init already */
7489 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7490 return -EINVAL;
4e53c2e0
DV		 7491 bpp = 10*3;
7492 break;
baba133a 7493 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7494 default:
7495 DRM_DEBUG_KMS("unsupported depth\n");
7496 return -EINVAL;
7497 }
7498
4e53c2e0
DV		 7499 pipe_config->pipe_bpp = bpp;
7500
7501 /* Clamp display bpp to EDID value */
7502 list_for_each_entry(connector, &dev->mode_config.connector_list,
7503 head) {
7504 if (connector->encoder && connector->encoder->crtc != crtc)
7505 continue;
7506
7507 /* Don't use an invalid EDID bpc value */
7508 if (connector->display_info.bpc &&
7509 connector->display_info.bpc * 3 < bpp) {
7510 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7511 bpp, connector->display_info.bpc*3);
7512 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7513 }
7514 }
7515
7516 return bpp;
7517}
7518
b8cecdf5
DV		 7519static struct intel_crtc_config *
7520intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7521 struct drm_framebuffer *fb,
b8cecdf5 7522 struct drm_display_mode *mode)
ee7b9f93 7523{
7758a113 7524 struct drm_device *dev = crtc->dev;
7758a113
DV		 7525 struct drm_encoder_helper_funcs *encoder_funcs;
7526 struct intel_encoder *encoder;
b8cecdf5 7527 struct intel_crtc_config *pipe_config;
4e53c2e0 7528 int plane_bpp;
ee7b9f93 7529
b8cecdf5
DV		 7530 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7531 if (!pipe_config)
7758a113
DV		 7532 return ERR_PTR(-ENOMEM);
7533
b8cecdf5
DV		 7534 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7535 drm_mode_copy(&pipe_config->requested_mode, mode);
7536
4e53c2e0
DV		 7537 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7538 if (plane_bpp < 0)
7539 goto fail;
7540
7758a113
DV		 7541 /* Pass our mode to the connectors and the CRTC to give them a chance to
7542 * adjust it according to limitations or connector properties, and also
7543 * a chance to reject the mode entirely.
47f1c6c9 7544 */
7758a113
DV		 7545 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7546 base.head) {
47f1c6c9 7547
7758a113
DV		 7548 if (&encoder->new_crtc->base != crtc)
7549 continue;
7ae89233
DV		 7550
7551 if (encoder->compute_config) {
7552 if (!(encoder->compute_config(encoder, pipe_config))) {
7553 DRM_DEBUG_KMS("Encoder config failure\n");
7554 goto fail;
7555 }
7556
7557 continue;
7558 }
7559
7758a113 7560 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7561 if (!(encoder_funcs->mode_fixup(&encoder->base,
7562 &pipe_config->requested_mode,
7563 &pipe_config->adjusted_mode))) {
7758a113
DV		 7564 DRM_DEBUG_KMS("Encoder fixup failed\n");
7565 goto fail;
7566 }
ee7b9f93 7567 }
47f1c6c9 7568
b8cecdf5 7569 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7570 DRM_DEBUG_KMS("CRTC fixup failed\n");
7571 goto fail;
ee7b9f93 7572 }
7758a113 7573 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7574
4e53c2e0
DV		 7575 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7576 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7577 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7578
b8cecdf5 7579 return pipe_config;
7758a113 7580fail:
b8cecdf5 7581 kfree(pipe_config);
7758a113 7582 return ERR_PTR(-EINVAL);
ee7b9f93 7583}
47f1c6c9 7584
e2e1ed41
DV		 7585/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7586 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7587static void
7588intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7589 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7590{
7591 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7592 struct drm_device *dev = crtc->dev;
7593 struct intel_encoder *encoder;
7594 struct intel_connector *connector;
7595 struct drm_crtc *tmp_crtc;
79e53945 7596
e2e1ed41 7597 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7598
e2e1ed41
DV		 7599 /* Check which crtcs have changed outputs connected to them, these need
7600 * to be part of the prepare_pipes mask. We don't (yet) support global
7601 * modeset across multiple crtcs, so modeset_pipes will only have one
7602 * bit set at most. */
7603 list_for_each_entry(connector, &dev->mode_config.connector_list,
7604 base.head) {
7605 if (connector->base.encoder == &connector->new_encoder->base)
7606 continue;
79e53945 7607
e2e1ed41
DV		 7608 if (connector->base.encoder) {
7609 tmp_crtc = connector->base.encoder->crtc;
7610
7611 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7612 }
7613
7614 if (connector->new_encoder)
7615 *prepare_pipes |=
7616 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7617 }
7618
e2e1ed41
DV		 7619 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7620 base.head) {
7621 if (encoder->base.crtc == &encoder->new_crtc->base)
7622 continue;
7623
7624 if (encoder->base.crtc) {
7625 tmp_crtc = encoder->base.crtc;
7626
7627 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7628 }
7629
7630 if (encoder->new_crtc)
7631 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7632 }
7633
e2e1ed41
DV		 7634 /* Check for any pipes that will be fully disabled ... */
7635 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7636 base.head) {
7637 bool used = false;
22fd0fab 7638
e2e1ed41
DV		 7639 /* Don't try to disable disabled crtcs. */
7640 if (!intel_crtc->base.enabled)
7641 continue;
7e7d76c3 7642
e2e1ed41
DV		 7643 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7644 base.head) {
7645 if (encoder->new_crtc == intel_crtc)
7646 used = true;
7647 }
7648
7649 if (!used)
7650 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7651 }
7652
e2e1ed41
DV		 7653
7654 /* set_mode is also used to update properties on life display pipes. */
7655 intel_crtc = to_intel_crtc(crtc);
7656 if (crtc->enabled)
7657 *prepare_pipes |= 1 << intel_crtc->pipe;
7658
7659 /* We only support modeset on one single crtc, hence we need to do that
7660 * only for the passed in crtc iff we change anything else than just
7661 * disable crtcs.
7662 *
7663 * This is actually not true, to be fully compatible with the old crtc
7664 * helper we automatically disable _any_ output (i.e. doesn't need to be
7665 * connected to the crtc we're modesetting on) if it's disconnected.
7666 * Which is a rather nutty api (since changed the output configuration
7667 * without userspace's explicit request can lead to confusion), but
7668 * alas. Hence we currently need to modeset on all pipes we prepare. */
7669 if (*prepare_pipes)
7670 *modeset_pipes = *prepare_pipes;
7671
7672 /* ... and mask these out. */
7673 *modeset_pipes &= ~(*disable_pipes);
7674 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7675}
79e53945 7676
ea9d758d 7677static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7678{
ea9d758d 7679 struct drm_encoder *encoder;
f6e5b160 7680 struct drm_device *dev = crtc->dev;
f6e5b160 7681
ea9d758d
DV		 7682 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7683 if (encoder->crtc == crtc)
7684 return true;
7685
7686 return false;
7687}
7688
7689static void
7690intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7691{
7692 struct intel_encoder *intel_encoder;
7693 struct intel_crtc *intel_crtc;
7694 struct drm_connector *connector;
7695
7696 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7697 base.head) {
7698 if (!intel_encoder->base.crtc)
7699 continue;
7700
7701 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7702
7703 if (prepare_pipes & (1 << intel_crtc->pipe))
7704 intel_encoder->connectors_active = false;
7705 }
7706
7707 intel_modeset_commit_output_state(dev);
7708
7709 /* Update computed state. */
7710 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7711 base.head) {
7712 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7713 }
7714
7715 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7716 if (!connector->encoder || !connector->encoder->crtc)
7717 continue;
7718
7719 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7720
7721 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7722 struct drm_property *dpms_property =
7723 dev->mode_config.dpms_property;
7724
ea9d758d 7725 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7726 drm_object_property_set_value(&connector->base,
68d34720
DV		 7727 dpms_property,
7728 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7729
7730 intel_encoder = to_intel_encoder(connector->encoder);
7731 intel_encoder->connectors_active = true;
7732 }
7733 }
7734
7735}
7736
25c5b266
DV		 7737#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7738 list_for_each_entry((intel_crtc), \
7739 &(dev)->mode_config.crtc_list, \
7740 base.head) \
7741 if (mask & (1 <<(intel_crtc)->pipe)) \
7742
b980514c 7743void
8af6cf88
DV		 7744intel_modeset_check_state(struct drm_device *dev)
7745{
7746 struct intel_crtc *crtc;
7747 struct intel_encoder *encoder;
7748 struct intel_connector *connector;
7749
7750 list_for_each_entry(connector, &dev->mode_config.connector_list,
7751 base.head) {
7752 /* This also checks the encoder/connector hw state with the
7753 * ->get_hw_state callbacks. */
7754 intel_connector_check_state(connector);
7755
7756 WARN(&connector->new_encoder->base != connector->base.encoder,
7757 "connector's staged encoder doesn't match current encoder\n");
7758 }
7759
7760 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7761 base.head) {
7762 bool enabled = false;
7763 bool active = false;
7764 enum pipe pipe, tracked_pipe;
7765
7766 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7767 encoder->base.base.id,
7768 drm_get_encoder_name(&encoder->base));
7769
7770 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7771 "encoder's stage crtc doesn't match current crtc\n");
7772 WARN(encoder->connectors_active && !encoder->base.crtc,
7773 "encoder's active_connectors set, but no crtc\n");
7774
7775 list_for_each_entry(connector, &dev->mode_config.connector_list,
7776 base.head) {
7777 if (connector->base.encoder != &encoder->base)
7778 continue;
7779 enabled = true;
7780 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7781 active = true;
7782 }
7783 WARN(!!encoder->base.crtc != enabled,
7784 "encoder's enabled state mismatch "
7785 "(expected %i, found %i)\n",
7786 !!encoder->base.crtc, enabled);
7787 WARN(active && !encoder->base.crtc,
7788 "active encoder with no crtc\n");
7789
7790 WARN(encoder->connectors_active != active,
7791 "encoder's computed active state doesn't match tracked active state "
7792 "(expected %i, found %i)\n", active, encoder->connectors_active);
7793
7794 active = encoder->get_hw_state(encoder, &pipe);
7795 WARN(active != encoder->connectors_active,
7796 "encoder's hw state doesn't match sw tracking "
7797 "(expected %i, found %i)\n",
7798 encoder->connectors_active, active);
7799
7800 if (!encoder->base.crtc)
7801 continue;
7802
7803 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7804 WARN(active && pipe != tracked_pipe,
7805 "active encoder's pipe doesn't match"
7806 "(expected %i, found %i)\n",
7807 tracked_pipe, pipe);
7808
7809 }
7810
7811 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7812 base.head) {
7813 bool enabled = false;
7814 bool active = false;
7815
7816 DRM_DEBUG_KMS("[CRTC:%d]\n",
7817 crtc->base.base.id);
7818
7819 WARN(crtc->active && !crtc->base.enabled,
7820 "active crtc, but not enabled in sw tracking\n");
7821
7822 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7823 base.head) {
7824 if (encoder->base.crtc != &crtc->base)
7825 continue;
7826 enabled = true;
7827 if (encoder->connectors_active)
7828 active = true;
7829 }
7830 WARN(active != crtc->active,
7831 "crtc's computed active state doesn't match tracked active state "
7832 "(expected %i, found %i)\n", active, crtc->active);
7833 WARN(enabled != crtc->base.enabled,
7834 "crtc's computed enabled state doesn't match tracked enabled state "
7835 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7836
7837 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7838 }
7839}
7840
c0c36b94
CW		 7841int intel_set_mode(struct drm_crtc *crtc,
7842 struct drm_display_mode *mode,
7843 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7844{
7845 struct drm_device *dev = crtc->dev;
dbf2b54e 7846 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7847 struct drm_display_mode *saved_mode, *saved_hwmode;
7848 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7849 struct intel_crtc *intel_crtc;
7850 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7851 int ret = 0;
a6778b3c 7852
3ac18232 7853 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7854 if (!saved_mode)
7855 return -ENOMEM;
3ac18232 7856 saved_hwmode = saved_mode + 1;
a6778b3c 7857
e2e1ed41 7858 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7859 &prepare_pipes, &disable_pipes);
7860
3ac18232
TG		 7861 *saved_hwmode = crtc->hwmode;
7862 *saved_mode = crtc->mode;
a6778b3c 7863
25c5b266
DV		 7864 /* Hack: Because we don't (yet) support global modeset on multiple
7865 * crtcs, we don't keep track of the new mode for more than one crtc.
7866 * Hence simply check whether any bit is set in modeset_pipes in all the
7867 * pieces of code that are not yet converted to deal with mutliple crtcs
7868 * changing their mode at the same time. */
25c5b266 7869 if (modeset_pipes) {
4e53c2e0 7870 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7871 if (IS_ERR(pipe_config)) {
7872 ret = PTR_ERR(pipe_config);
7873 pipe_config = NULL;
7874
3ac18232 7875 goto out;
25c5b266 7876 }
25c5b266 7877 }
a6778b3c 7878
460da916
DV		 7879 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7880 modeset_pipes, prepare_pipes, disable_pipes);
7881
7882 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7883 intel_crtc_disable(&intel_crtc->base);
7884
ea9d758d
DV		 7885 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7886 if (intel_crtc->base.enabled)
7887 dev_priv->display.crtc_disable(&intel_crtc->base);
7888 }
a6778b3c 7889
6c4c86f5
DV		 7890 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7891 * to set it here already despite that we pass it down the callchain.
f6e5b160 7892 */
b8cecdf5 7893 if (modeset_pipes) {
25c5b266 7894 crtc->mode = *mode;
b8cecdf5
DV		 7895 /* mode_set/enable/disable functions rely on a correct pipe
7896 * config. */
7897 to_intel_crtc(crtc)->config = *pipe_config;
7898 }
7758a113 7899
ea9d758d
DV		 7900 /* Only after disabling all output pipelines that will be changed can we
7901 * update the the output configuration. */
7902 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7903
47fab737
DV		 7904 if (dev_priv->display.modeset_global_resources)
7905 dev_priv->display.modeset_global_resources(dev);
7906
a6778b3c
DV		 7907 /* Set up the DPLL and any encoders state that needs to adjust or depend
7908 * on the DPLL.
f6e5b160 7909 */
25c5b266 7910 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 7911 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 7912 x, y, fb);
7913 if (ret)
7914 goto done;
a6778b3c
DV		 7915 }
7916
7917 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7918 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7919 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7920
25c5b266
DV		 7921 if (modeset_pipes) {
7922 /* Store real post-adjustment hardware mode. */
b8cecdf5 7923 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 7924
25c5b266
DV		 7925 /* Calculate and store various constants which
7926 * are later needed by vblank and swap-completion
7927 * timestamping. They are derived from true hwmode.
7928 */
7929 drm_calc_timestamping_constants(crtc);
7930 }
a6778b3c
DV		 7931
7932 /* FIXME: add subpixel order */
7933done:
c0c36b94 7934 if (ret && crtc->enabled) {
3ac18232
TG		 7935 crtc->hwmode = *saved_hwmode;
7936 crtc->mode = *saved_mode;
8af6cf88
DV		 7937 } else {
7938 intel_modeset_check_state(dev);
a6778b3c
DV		 7939 }
7940
3ac18232 7941out:
b8cecdf5 7942 kfree(pipe_config);
3ac18232 7943 kfree(saved_mode);
a6778b3c 7944 return ret;
f6e5b160
CW		 7945}
7946
c0c36b94
CW		 7947void intel_crtc_restore_mode(struct drm_crtc *crtc)
7948{
7949 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7950}
7951
25c5b266
DV		 7952#undef for_each_intel_crtc_masked
7953
d9e55608
DV		 7954static void intel_set_config_free(struct intel_set_config *config)
7955{
7956 if (!config)
7957 return;
7958
1aa4b628
DV		 7959 kfree(config->save_connector_encoders);
7960 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7961 kfree(config);
7962}
7963
85f9eb71
DV		 7964static int intel_set_config_save_state(struct drm_device *dev,
7965 struct intel_set_config *config)
7966{
85f9eb71
DV		 7967 struct drm_encoder *encoder;
7968 struct drm_connector *connector;
7969 int count;
7970
1aa4b628
DV		 7971 config->save_encoder_crtcs =
7972 kcalloc(dev->mode_config.num_encoder,
7973 sizeof(struct drm_crtc *), GFP_KERNEL);
7974 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7975 return -ENOMEM;
7976
1aa4b628
DV		 7977 config->save_connector_encoders =
7978 kcalloc(dev->mode_config.num_connector,
7979 sizeof(struct drm_encoder *), GFP_KERNEL);
7980 if (!config->save_connector_encoders)
85f9eb71
DV		 7981 return -ENOMEM;
7982
7983 /* Copy data. Note that driver private data is not affected.
7984 * Should anything bad happen only the expected state is
7985 * restored, not the drivers personal bookkeeping.
7986 */
85f9eb71
DV		 7987 count = 0;
7988 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7989 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7990 }
7991
7992 count = 0;
7993 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7994 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7995 }
7996
7997 return 0;
7998}
7999
8000static void intel_set_config_restore_state(struct drm_device *dev,
8001 struct intel_set_config *config)
8002{
9a935856
DV		 8003 struct intel_encoder *encoder;
8004 struct intel_connector *connector;
85f9eb71
DV		 8005 int count;
8006
85f9eb71 8007 count = 0;
9a935856
DV		 8008 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8009 encoder->new_crtc =
8010 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8011 }
8012
8013 count = 0;
9a935856
DV		 8014 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8015 connector->new_encoder =
8016 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8017 }
8018}
8019
5e2b584e
DV		 8020static void
8021intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8022 struct intel_set_config *config)
8023{
8024
8025 /* We should be able to check here if the fb has the same properties
8026 * and then just flip_or_move it */
8027 if (set->crtc->fb != set->fb) {
8028 /* If we have no fb then treat it as a full mode set */
8029 if (set->crtc->fb == NULL) {
8030 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8031 config->mode_changed = true;
8032 } else if (set->fb == NULL) {
8033 config->mode_changed = true;
72f4901e
DV		 8034 } else if (set->fb->pixel_format !=
8035 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8036 config->mode_changed = true;
8037 } else
8038 config->fb_changed = true;
8039 }
8040
835c5873 8041 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8042 config->fb_changed = true;
8043
8044 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8045 DRM_DEBUG_KMS("modes are different, full mode set\n");
8046 drm_mode_debug_printmodeline(&set->crtc->mode);
8047 drm_mode_debug_printmodeline(set->mode);
8048 config->mode_changed = true;
8049 }
8050}
8051
2e431051 8052static int
9a935856
DV		 8053intel_modeset_stage_output_state(struct drm_device *dev,
8054 struct drm_mode_set *set,
8055 struct intel_set_config *config)
50f56119 8056{
85f9eb71 8057 struct drm_crtc *new_crtc;
9a935856
DV		 8058 struct intel_connector *connector;
8059 struct intel_encoder *encoder;
2e431051 8060 int count, ro;
50f56119 8061
9abdda74 8062 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8063 * of connectors. For paranoia, double-check this. */
8064 WARN_ON(!set->fb && (set->num_connectors != 0));
8065 WARN_ON(set->fb && (set->num_connectors == 0));
8066
50f56119 8067 count = 0;
9a935856
DV		 8068 list_for_each_entry(connector, &dev->mode_config.connector_list,
8069 base.head) {
8070 /* Otherwise traverse passed in connector list and get encoders
8071 * for them. */
50f56119 8072 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8073 if (set->connectors[ro] == &connector->base) {
8074 connector->new_encoder = connector->encoder;
50f56119
DV		 8075 break;
8076 }
8077 }
8078
9a935856
DV		 8079 /* If we disable the crtc, disable all its connectors. Also, if
8080 * the connector is on the changing crtc but not on the new
8081 * connector list, disable it. */
8082 if ((!set->fb || ro == set->num_connectors) &&
8083 connector->base.encoder &&
8084 connector->base.encoder->crtc == set->crtc) {
8085 connector->new_encoder = NULL;
8086
8087 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8088 connector->base.base.id,
8089 drm_get_connector_name(&connector->base));
8090 }
8091
8092
8093 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8094 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8095 config->mode_changed = true;
50f56119
DV		 8096 }
8097 }
9a935856 8098 /* connector->new_encoder is now updated for all connectors. */
50f56119 8099
9a935856 8100 /* Update crtc of enabled connectors. */
50f56119 8101 count = 0;
9a935856
DV		 8102 list_for_each_entry(connector, &dev->mode_config.connector_list,
8103 base.head) {
8104 if (!connector->new_encoder)
50f56119
DV		 8105 continue;
8106
9a935856 8107 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8108
8109 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8110 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8111 new_crtc = set->crtc;
8112 }
8113
8114 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8115 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8116 new_crtc)) {
5e2b584e 8117 return -EINVAL;
50f56119 8118 }
9a935856
DV		 8119 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8120
8121 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8122 connector->base.base.id,
8123 drm_get_connector_name(&connector->base),
8124 new_crtc->base.id);
8125 }
8126
8127 /* Check for any encoders that needs to be disabled. */
8128 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8129 base.head) {
8130 list_for_each_entry(connector,
8131 &dev->mode_config.connector_list,
8132 base.head) {
8133 if (connector->new_encoder == encoder) {
8134 WARN_ON(!connector->new_encoder->new_crtc);
8135
8136 goto next_encoder;
8137 }
8138 }
8139 encoder->new_crtc = NULL;
8140next_encoder:
8141 /* Only now check for crtc changes so we don't miss encoders
8142 * that will be disabled. */
8143 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8144 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8145 config->mode_changed = true;
50f56119
DV		 8146 }
8147 }
9a935856 8148 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8149
2e431051
DV		 8150 return 0;
8151}
8152
8153static int intel_crtc_set_config(struct drm_mode_set *set)
8154{
8155 struct drm_device *dev;
2e431051
DV		 8156 struct drm_mode_set save_set;
8157 struct intel_set_config *config;
8158 int ret;
2e431051 8159
8d3e375e
DV		 8160 BUG_ON(!set);
8161 BUG_ON(!set->crtc);
8162 BUG_ON(!set->crtc->helper_private);
2e431051 8163
7e53f3a4
DV		 8164 /* Enforce sane interface api - has been abused by the fb helper. */
8165 BUG_ON(!set->mode && set->fb);
8166 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8167
2e431051
DV		 8168 if (set->fb) {
8169 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8170 set->crtc->base.id, set->fb->base.id,
8171 (int)set->num_connectors, set->x, set->y);
8172 } else {
8173 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8174 }
8175
8176 dev = set->crtc->dev;
8177
8178 ret = -ENOMEM;
8179 config = kzalloc(sizeof(*config), GFP_KERNEL);
8180 if (!config)
8181 goto out_config;
8182
8183 ret = intel_set_config_save_state(dev, config);
8184 if (ret)
8185 goto out_config;
8186
8187 save_set.crtc = set->crtc;
8188 save_set.mode = &set->crtc->mode;
8189 save_set.x = set->crtc->x;
8190 save_set.y = set->crtc->y;
8191 save_set.fb = set->crtc->fb;
8192
8193 /* Compute whether we need a full modeset, only an fb base update or no
8194 * change at all. In the future we might also check whether only the
8195 * mode changed, e.g. for LVDS where we only change the panel fitter in
8196 * such cases. */
8197 intel_set_config_compute_mode_changes(set, config);
8198
9a935856 8199 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8200 if (ret)
8201 goto fail;
8202
5e2b584e 8203 if (config->mode_changed) {
87f1faa6 8204 if (set->mode) {
50f56119
DV		 8205 DRM_DEBUG_KMS("attempting to set mode from"
8206 " userspace\n");
8207 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8208 }
8209
c0c36b94
CW		 8210 ret = intel_set_mode(set->crtc, set->mode,
8211 set->x, set->y, set->fb);
8212 if (ret) {
8213 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8214 set->crtc->base.id, ret);
87f1faa6
DV		 8215 goto fail;
8216 }
5e2b584e 8217 } else if (config->fb_changed) {
4878cae2
VS		 8218 intel_crtc_wait_for_pending_flips(set->crtc);
8219
4f660f49 8220 ret = intel_pipe_set_base(set->crtc,
94352cf9 8221 set->x, set->y, set->fb);
50f56119
DV		 8222 }
8223
d9e55608
DV		 8224 intel_set_config_free(config);
8225
50f56119
DV		 8226 return 0;
8227
8228fail:
85f9eb71 8229 intel_set_config_restore_state(dev, config);
50f56119
DV		 8230
8231 /* Try to restore the config */
5e2b584e 8232 if (config->mode_changed &&
c0c36b94
CW		 8233 intel_set_mode(save_set.crtc, save_set.mode,
8234 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8235 DRM_ERROR("failed to restore config after modeset failure\n");
8236
d9e55608
DV		 8237out_config:
8238 intel_set_config_free(config);
50f56119
DV		 8239 return ret;
8240}
f6e5b160
CW		 8241
8242static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8243 .cursor_set = intel_crtc_cursor_set,
8244 .cursor_move = intel_crtc_cursor_move,
8245 .gamma_set = intel_crtc_gamma_set,
50f56119 8246 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8247 .destroy = intel_crtc_destroy,
8248 .page_flip = intel_crtc_page_flip,
8249};
8250
79f689aa
PZ		 8251static void intel_cpu_pll_init(struct drm_device *dev)
8252{
affa9354 8253 if (HAS_DDI(dev))
79f689aa
PZ		 8254 intel_ddi_pll_init(dev);
8255}
8256
ee7b9f93
JB		 8257static void intel_pch_pll_init(struct drm_device *dev)
8258{
8259 drm_i915_private_t *dev_priv = dev->dev_private;
8260 int i;
8261
8262 if (dev_priv->num_pch_pll == 0) {
8263 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8264 return;
8265 }
8266
8267 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8268 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8269 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8270 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8271 }
8272}
8273
b358d0a6 8274static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8275{
22fd0fab 8276 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8277 struct intel_crtc *intel_crtc;
8278 int i;
8279
8280 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8281 if (intel_crtc == NULL)
8282 return;
8283
8284 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8285
8286 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8287 for (i = 0; i < 256; i++) {
8288 intel_crtc->lut_r[i] = i;
8289 intel_crtc->lut_g[i] = i;
8290 intel_crtc->lut_b[i] = i;
8291 }
8292
80824003
JB		 8293 /* Swap pipes & planes for FBC on pre-965 */
8294 intel_crtc->pipe = pipe;
8295 intel_crtc->plane = pipe;
a5c961d1 8296 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8297 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8298 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8299 intel_crtc->plane = !pipe;
80824003
JB		 8300 }
8301
22fd0fab
JB		 8302 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8303 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8304 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8305 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8306
79e53945 8307 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8308}
8309
08d7b3d1 8310int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8311 struct drm_file *file)
08d7b3d1 8312{
08d7b3d1 8313 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8314 struct drm_mode_object *drmmode_obj;
8315 struct intel_crtc *crtc;
08d7b3d1 8316
1cff8f6b
DV		 8317 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8318 return -ENODEV;
08d7b3d1 8319
c05422d5
DV		 8320 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8321 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8322
c05422d5 8323 if (!drmmode_obj) {
08d7b3d1
CW		 8324 DRM_ERROR("no such CRTC id\n");
8325 return -EINVAL;
8326 }
8327
c05422d5
DV		 8328 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8329 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8330
c05422d5 8331 return 0;
08d7b3d1
CW		 8332}
8333
66a9278e 8334static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8335{
66a9278e
DV		 8336 struct drm_device *dev = encoder->base.dev;
8337 struct intel_encoder *source_encoder;
79e53945 8338 int index_mask = 0;
79e53945
JB		 8339 int entry = 0;
8340
66a9278e
DV		 8341 list_for_each_entry(source_encoder,
8342 &dev->mode_config.encoder_list, base.head) {
8343
8344 if (encoder == source_encoder)
79e53945 8345 index_mask |= (1 << entry);
66a9278e
DV		 8346
8347 /* Intel hw has only one MUX where enocoders could be cloned. */
8348 if (encoder->cloneable && source_encoder->cloneable)
8349 index_mask |= (1 << entry);
8350
79e53945
JB		 8351 entry++;
8352 }
4ef69c7a 8353
79e53945
JB		 8354 return index_mask;
8355}
8356
4d302442
CW		 8357static bool has_edp_a(struct drm_device *dev)
8358{
8359 struct drm_i915_private *dev_priv = dev->dev_private;
8360
8361 if (!IS_MOBILE(dev))
8362 return false;
8363
8364 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8365 return false;
8366
8367 if (IS_GEN5(dev) &&
8368 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8369 return false;
8370
8371 return true;
8372}
8373
79e53945
JB		 8374static void intel_setup_outputs(struct drm_device *dev)
8375{
725e30ad 8376 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8377 struct intel_encoder *encoder;
cb0953d7 8378 bool dpd_is_edp = false;
f3cfcba6 8379 bool has_lvds;
79e53945 8380
f3cfcba6 8381 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8382 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8383 /* disable the panel fitter on everything but LVDS */
8384 I915_WRITE(PFIT_CONTROL, 0);
8385 }
79e53945 8386
affa9354 8387 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8388 intel_crt_init(dev);
cb0953d7 8389
affa9354 8390 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8391 int found;
8392
8393 /* Haswell uses DDI functions to detect digital outputs */
8394 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8395 /* DDI A only supports eDP */
8396 if (found)
8397 intel_ddi_init(dev, PORT_A);
8398
8399 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8400 * register */
8401 found = I915_READ(SFUSE_STRAP);
8402
8403 if (found & SFUSE_STRAP_DDIB_DETECTED)
8404 intel_ddi_init(dev, PORT_B);
8405 if (found & SFUSE_STRAP_DDIC_DETECTED)
8406 intel_ddi_init(dev, PORT_C);
8407 if (found & SFUSE_STRAP_DDID_DETECTED)
8408 intel_ddi_init(dev, PORT_D);
8409 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8410 int found;
270b3042
DV		 8411 dpd_is_edp = intel_dpd_is_edp(dev);
8412
8413 if (has_edp_a(dev))
8414 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8415
dc0fa718 8416 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8417 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8418 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8419 if (!found)
e2debe91 8420 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8421 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8422 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8423 }
8424
dc0fa718 8425 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8426 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8427
dc0fa718 8428 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8429 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8430
5eb08b69 8431 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8432 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8433
270b3042 8434 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8435 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8436 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8437 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8438 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8439 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8440
dc0fa718 8441 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8442 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8443 PORT_B);
67cfc203
VS		 8444 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8445 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8446 }
103a196f 8447 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8448 bool found = false;
7d57382e 8449
e2debe91 8450 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8451 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8452 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8453 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8454 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8455 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8456 }
27185ae1 8457
b01f2c3a
JB		 8458 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8459 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8460 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8461 }
725e30ad 8462 }
13520b05
KH		 8463
8464 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8465
e2debe91 8466 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8467 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8468 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8469 }
27185ae1 8470
e2debe91 8471 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8472
b01f2c3a
JB		 8473 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8474 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8475 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8476 }
8477 if (SUPPORTS_INTEGRATED_DP(dev)) {
8478 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8479 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8480 }
725e30ad 8481 }
27185ae1 8482
b01f2c3a
JB		 8483 if (SUPPORTS_INTEGRATED_DP(dev) &&
8484 (I915_READ(DP_D) & DP_DETECTED)) {
8485 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8486 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8487 }
bad720ff 8488 } else if (IS_GEN2(dev))
79e53945
JB		 8489 intel_dvo_init(dev);
8490
103a196f 8491 if (SUPPORTS_TV(dev))
79e53945
JB		 8492 intel_tv_init(dev);
8493
4ef69c7a
CW		 8494 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8495 encoder->base.possible_crtcs = encoder->crtc_mask;
8496 encoder->base.possible_clones =
66a9278e 8497 intel_encoder_clones(encoder);
79e53945 8498 }
47356eb6 8499
dde86e2d 8500 intel_init_pch_refclk(dev);
270b3042
DV		 8501
8502 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8503}
8504
8505static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8506{
8507 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8508
8509 drm_framebuffer_cleanup(fb);
05394f39 8510 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8511
8512 kfree(intel_fb);
8513}
8514
8515static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8516 struct drm_file *file,
79e53945
JB		 8517 unsigned int *handle)
8518{
8519 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8520 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8521
05394f39 8522 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8523}
8524
8525static const struct drm_framebuffer_funcs intel_fb_funcs = {
8526 .destroy = intel_user_framebuffer_destroy,
8527 .create_handle = intel_user_framebuffer_create_handle,
8528};
8529
38651674
DA		 8530int intel_framebuffer_init(struct drm_device *dev,
8531 struct intel_framebuffer *intel_fb,
308e5bcb 8532 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8533 struct drm_i915_gem_object *obj)
79e53945 8534{
79e53945
JB		 8535 int ret;
8536
c16ed4be
CW		 8537 if (obj->tiling_mode == I915_TILING_Y) {
8538 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8539 return -EINVAL;
c16ed4be 8540 }
57cd6508 8541
c16ed4be
CW		 8542 if (mode_cmd->pitches[0] & 63) {
8543 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8544 mode_cmd->pitches[0]);
57cd6508 8545 return -EINVAL;
c16ed4be 8546 }
57cd6508 8547
5d7bd705 8548 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8549 if (mode_cmd->pitches[0] > 32768) {
8550 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8551 mode_cmd->pitches[0]);
5d7bd705 8552 return -EINVAL;
c16ed4be 8553 }
5d7bd705
VS		 8554
8555 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8556 mode_cmd->pitches[0] != obj->stride) {
8557 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8558 mode_cmd->pitches[0], obj->stride);
5d7bd705 8559 return -EINVAL;
c16ed4be 8560 }
5d7bd705 8561
57779d06 8562 /* Reject formats not supported by any plane early. */
308e5bcb 8563 switch (mode_cmd->pixel_format) {
57779d06 8564 case DRM_FORMAT_C8:
04b3924d
VS		 8565 case DRM_FORMAT_RGB565:
8566 case DRM_FORMAT_XRGB8888:
8567 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8568 break;
8569 case DRM_FORMAT_XRGB1555:
8570 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8571 if (INTEL_INFO(dev)->gen > 3) {
8572 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8573 return -EINVAL;
c16ed4be 8574 }
57779d06
VS		 8575 break;
8576 case DRM_FORMAT_XBGR8888:
8577 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8578 case DRM_FORMAT_XRGB2101010:
8579 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8580 case DRM_FORMAT_XBGR2101010:
8581 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8582 if (INTEL_INFO(dev)->gen < 4) {
8583 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8584 return -EINVAL;
c16ed4be 8585 }
b5626747 8586 break;
04b3924d
VS		 8587 case DRM_FORMAT_YUYV:
8588 case DRM_FORMAT_UYVY:
8589 case DRM_FORMAT_YVYU:
8590 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8591 if (INTEL_INFO(dev)->gen < 5) {
8592 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8593 return -EINVAL;
c16ed4be 8594 }
57cd6508
CW		 8595 break;
8596 default:
c16ed4be 8597 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8598 return -EINVAL;
8599 }
8600
90f9a336
VS		 8601 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8602 if (mode_cmd->offsets[0] != 0)
8603 return -EINVAL;
8604
c7d73f6a
DV		 8605 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8606 intel_fb->obj = obj;
8607
79e53945
JB		 8608 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8609 if (ret) {
8610 DRM_ERROR("framebuffer init failed %d\n", ret);
8611 return ret;
8612 }
8613
79e53945
JB		 8614 return 0;
8615}
8616
79e53945
JB		 8617static struct drm_framebuffer *
8618intel_user_framebuffer_create(struct drm_device *dev,
8619 struct drm_file *filp,
308e5bcb 8620 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8621{
05394f39 8622 struct drm_i915_gem_object *obj;
79e53945 8623
308e5bcb
JB		 8624 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8625 mode_cmd->handles[0]));
c8725226 8626 if (&obj->base == NULL)
cce13ff7 8627 return ERR_PTR(-ENOENT);
79e53945 8628
d2dff872 8629 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8630}
8631
79e53945 8632static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8633 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8634 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8635};
8636
e70236a8
JB		 8637/* Set up chip specific display functions */
8638static void intel_init_display(struct drm_device *dev)
8639{
8640 struct drm_i915_private *dev_priv = dev->dev_private;
8641
affa9354 8642 if (HAS_DDI(dev)) {
09b4ddf9 8643 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8644 dev_priv->display.crtc_enable = haswell_crtc_enable;
8645 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8646 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8647 dev_priv->display.update_plane = ironlake_update_plane;
8648 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8649 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8650 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8651 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8652 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8653 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8654 } else {
f564048e 8655 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8656 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8657 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8658 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8659 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8660 }
e70236a8 8661
e70236a8 8662 /* Returns the core display clock speed */
25eb05fc
JB		 8663 if (IS_VALLEYVIEW(dev))
8664 dev_priv->display.get_display_clock_speed =
8665 valleyview_get_display_clock_speed;
8666 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8667 dev_priv->display.get_display_clock_speed =
8668 i945_get_display_clock_speed;
8669 else if (IS_I915G(dev))
8670 dev_priv->display.get_display_clock_speed =
8671 i915_get_display_clock_speed;
f2b115e6 8672 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8673 dev_priv->display.get_display_clock_speed =
8674 i9xx_misc_get_display_clock_speed;
8675 else if (IS_I915GM(dev))
8676 dev_priv->display.get_display_clock_speed =
8677 i915gm_get_display_clock_speed;
8678 else if (IS_I865G(dev))
8679 dev_priv->display.get_display_clock_speed =
8680 i865_get_display_clock_speed;
f0f8a9ce 8681 else if (IS_I85X(dev))
e70236a8
JB		 8682 dev_priv->display.get_display_clock_speed =
8683 i855_get_display_clock_speed;
8684 else /* 852, 830 */
8685 dev_priv->display.get_display_clock_speed =
8686 i830_get_display_clock_speed;
8687
7f8a8569 8688 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8689 if (IS_GEN5(dev)) {
674cf967 8690 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8691 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8692 } else if (IS_GEN6(dev)) {
674cf967 8693 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8694 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8695 } else if (IS_IVYBRIDGE(dev)) {
8696 /* FIXME: detect B0+ stepping and use auto training */
8697 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8698 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8699 dev_priv->display.modeset_global_resources =
8700 ivb_modeset_global_resources;
c82e4d26
ED		 8701 } else if (IS_HASWELL(dev)) {
8702 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8703 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8704 dev_priv->display.modeset_global_resources =
8705 haswell_modeset_global_resources;
a0e63c22 8706 }
6067aaea 8707 } else if (IS_G4X(dev)) {
e0dac65e 8708 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8709 }
8c9f3aaf
JB		 8710
8711 /* Default just returns -ENODEV to indicate unsupported */
8712 dev_priv->display.queue_flip = intel_default_queue_flip;
8713
8714 switch (INTEL_INFO(dev)->gen) {
8715 case 2:
8716 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8717 break;
8718
8719 case 3:
8720 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8721 break;
8722
8723 case 4:
8724 case 5:
8725 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8726 break;
8727
8728 case 6:
8729 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8730 break;
7c9017e5
JB		 8731 case 7:
8732 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8733 break;
8c9f3aaf 8734 }
e70236a8
JB		 8735}
8736
b690e96c
JB		 8737/*
8738 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8739 * resume, or other times. This quirk makes sure that's the case for
8740 * affected systems.
8741 */
0206e353 8742static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8743{
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745
8746 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8747 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8748}
8749
435793df
KP		 8750/*
8751 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8752 */
8753static void quirk_ssc_force_disable(struct drm_device *dev)
8754{
8755 struct drm_i915_private *dev_priv = dev->dev_private;
8756 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8757 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8758}
8759
4dca20ef 8760/*
5a15ab5b
CE		 8761 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8762 * brightness value
4dca20ef
CE		 8763 */
8764static void quirk_invert_brightness(struct drm_device *dev)
8765{
8766 struct drm_i915_private *dev_priv = dev->dev_private;
8767 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8768 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8769}
8770
b690e96c
JB		 8771struct intel_quirk {
8772 int device;
8773 int subsystem_vendor;
8774 int subsystem_device;
8775 void (*hook)(struct drm_device *dev);
8776};
8777
5f85f176
EE		 8778/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8779struct intel_dmi_quirk {
8780 void (*hook)(struct drm_device *dev);
8781 const struct dmi_system_id (*dmi_id_list)[];
8782};
8783
8784static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8785{
8786 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8787 return 1;
8788}
8789
8790static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8791 {
8792 .dmi_id_list = &(const struct dmi_system_id[]) {
8793 {
8794 .callback = intel_dmi_reverse_brightness,
8795 .ident = "NCR Corporation",
8796 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8797 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8798 },
8799 },
8800 { } /* terminating entry */
8801 },
8802 .hook = quirk_invert_brightness,
8803 },
8804};
8805
c43b5634 8806static struct intel_quirk intel_quirks[] = {
b690e96c 8807 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8808 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8809
b690e96c
JB		 8810 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8811 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8812
b690e96c
JB		 8813 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8814 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8815
ccd0d36e 8816 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8817 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8818 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8819
8820 /* Lenovo U160 cannot use SSC on LVDS */
8821 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8822
8823 /* Sony Vaio Y cannot use SSC on LVDS */
8824 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8825
8826 /* Acer Aspire 5734Z must invert backlight brightness */
8827 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8828
8829 /* Acer/eMachines G725 */
8830 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8831
8832 /* Acer/eMachines e725 */
8833 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8834
8835 /* Acer/Packard Bell NCL20 */
8836 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8837
8838 /* Acer Aspire 4736Z */
8839 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8840};
8841
8842static void intel_init_quirks(struct drm_device *dev)
8843{
8844 struct pci_dev *d = dev->pdev;
8845 int i;
8846
8847 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8848 struct intel_quirk *q = &intel_quirks[i];
8849
8850 if (d->device == q->device &&
8851 (d->subsystem_vendor == q->subsystem_vendor ||
8852 q->subsystem_vendor == PCI_ANY_ID) &&
8853 (d->subsystem_device == q->subsystem_device ||
8854 q->subsystem_device == PCI_ANY_ID))
8855 q->hook(dev);
8856 }
5f85f176
EE		 8857 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8858 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8859 intel_dmi_quirks[i].hook(dev);
8860 }
b690e96c
JB		 8861}
8862
9cce37f4
JB		 8863/* Disable the VGA plane that we never use */
8864static void i915_disable_vga(struct drm_device *dev)
8865{
8866 struct drm_i915_private *dev_priv = dev->dev_private;
8867 u8 sr1;
766aa1c4 8868 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8869
8870 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8871 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8872 sr1 = inb(VGA_SR_DATA);
8873 outb(sr1 | 1<<5, VGA_SR_DATA);
8874 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8875 udelay(300);
8876
8877 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8878 POSTING_READ(vga_reg);
8879}
8880
f817586c
DV		 8881void intel_modeset_init_hw(struct drm_device *dev)
8882{
fa42e23c 8883 intel_init_power_well(dev);
0232e927 8884
a8f78b58
ED		 8885 intel_prepare_ddi(dev);
8886
f817586c
DV		 8887 intel_init_clock_gating(dev);
8888
79f5b2c7 8889 mutex_lock(&dev->struct_mutex);
8090c6b9 8890 intel_enable_gt_powersave(dev);
79f5b2c7 8891 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8892}
8893
79e53945
JB		 8894void intel_modeset_init(struct drm_device *dev)
8895{
652c393a 8896 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 8897 int i, j, ret;
79e53945
JB		 8898
8899 drm_mode_config_init(dev);
8900
8901 dev->mode_config.min_width = 0;
8902 dev->mode_config.min_height = 0;
8903
019d96cb
DA		 8904 dev->mode_config.preferred_depth = 24;
8905 dev->mode_config.prefer_shadow = 1;
8906
e6ecefaa 8907 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8908
b690e96c
JB		 8909 intel_init_quirks(dev);
8910
1fa61106
ED		 8911 intel_init_pm(dev);
8912
e70236a8
JB		 8913 intel_init_display(dev);
8914
a6c45cf0
CW		 8915 if (IS_GEN2(dev)) {
8916 dev->mode_config.max_width = 2048;
8917 dev->mode_config.max_height = 2048;
8918 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8919 dev->mode_config.max_width = 4096;
8920 dev->mode_config.max_height = 4096;
79e53945 8921 } else {
a6c45cf0
CW		 8922 dev->mode_config.max_width = 8192;
8923 dev->mode_config.max_height = 8192;
79e53945 8924 }
5d4545ae 8925 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8926
28c97730 8927 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 8928 INTEL_INFO(dev)->num_pipes,
8929 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 8930
7eb552ae 8931 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 8932 intel_crtc_init(dev, i);
7f1f3851
JB		 8933 for (j = 0; j < dev_priv->num_plane; j++) {
8934 ret = intel_plane_init(dev, i, j);
8935 if (ret)
8936 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
8937 i, j, ret);
8938 }
79e53945
JB		 8939 }
8940
79f689aa 8941 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8942 intel_pch_pll_init(dev);
8943
9cce37f4
JB		 8944 /* Just disable it once at startup */
8945 i915_disable_vga(dev);
79e53945 8946 intel_setup_outputs(dev);
11be49eb
CW		 8947
8948 /* Just in case the BIOS is doing something questionable. */
8949 intel_disable_fbc(dev);
2c7111db
CW		 8950}
8951
24929352
DV		 8952static void
8953intel_connector_break_all_links(struct intel_connector *connector)
8954{
8955 connector->base.dpms = DRM_MODE_DPMS_OFF;
8956 connector->base.encoder = NULL;
8957 connector->encoder->connectors_active = false;
8958 connector->encoder->base.crtc = NULL;
8959}
8960
7fad798e
DV		 8961static void intel_enable_pipe_a(struct drm_device *dev)
8962{
8963 struct intel_connector *connector;
8964 struct drm_connector *crt = NULL;
8965 struct intel_load_detect_pipe load_detect_temp;
8966
8967 /* We can't just switch on the pipe A, we need to set things up with a
8968 * proper mode and output configuration. As a gross hack, enable pipe A
8969 * by enabling the load detect pipe once. */
8970 list_for_each_entry(connector,
8971 &dev->mode_config.connector_list,
8972 base.head) {
8973 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8974 crt = &connector->base;
8975 break;
8976 }
8977 }
8978
8979 if (!crt)
8980 return;
8981
8982 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8983 intel_release_load_detect_pipe(crt, &load_detect_temp);
8984
652c393a 8985
7fad798e
DV		 8986}
8987
fa555837
DV		 8988static bool
8989intel_check_plane_mapping(struct intel_crtc *crtc)
8990{
7eb552ae
BW		 8991 struct drm_device *dev = crtc->base.dev;
8992 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 8993 u32 reg, val;
8994
7eb552ae 8995 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 8996 return true;
8997
8998 reg = DSPCNTR(!crtc->plane);
8999 val = I915_READ(reg);
9000
9001 if ((val & DISPLAY_PLANE_ENABLE) &&
9002 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9003 return false;
9004
9005 return true;
9006}
9007
24929352
DV		 9008static void intel_sanitize_crtc(struct intel_crtc *crtc)
9009{
9010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9012 u32 reg;
24929352 9013
24929352 9014 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 9015 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 9016 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9017
9018 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9019 * disable the crtc (and hence change the state) if it is wrong. Note
9020 * that gen4+ has a fixed plane -> pipe mapping. */
9021 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9022 struct intel_connector *connector;
9023 bool plane;
9024
24929352
DV		 9025 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9026 crtc->base.base.id);
9027
9028 /* Pipe has the wrong plane attached and the plane is active.
9029 * Temporarily change the plane mapping and disable everything
9030 * ... */
9031 plane = crtc->plane;
9032 crtc->plane = !plane;
9033 dev_priv->display.crtc_disable(&crtc->base);
9034 crtc->plane = plane;
9035
9036 /* ... and break all links. */
9037 list_for_each_entry(connector, &dev->mode_config.connector_list,
9038 base.head) {
9039 if (connector->encoder->base.crtc != &crtc->base)
9040 continue;
9041
9042 intel_connector_break_all_links(connector);
9043 }
9044
9045 WARN_ON(crtc->active);
9046 crtc->base.enabled = false;
9047 }
24929352 9048
7fad798e
DV		 9049 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9050 crtc->pipe == PIPE_A && !crtc->active) {
9051 /* BIOS forgot to enable pipe A, this mostly happens after
9052 * resume. Force-enable the pipe to fix this, the update_dpms
9053 * call below we restore the pipe to the right state, but leave
9054 * the required bits on. */
9055 intel_enable_pipe_a(dev);
9056 }
9057
24929352
DV		 9058 /* Adjust the state of the output pipe according to whether we
9059 * have active connectors/encoders. */
9060 intel_crtc_update_dpms(&crtc->base);
9061
9062 if (crtc->active != crtc->base.enabled) {
9063 struct intel_encoder *encoder;
9064
9065 /* This can happen either due to bugs in the get_hw_state
9066 * functions or because the pipe is force-enabled due to the
9067 * pipe A quirk. */
9068 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9069 crtc->base.base.id,
9070 crtc->base.enabled ? "enabled" : "disabled",
9071 crtc->active ? "enabled" : "disabled");
9072
9073 crtc->base.enabled = crtc->active;
9074
9075 /* Because we only establish the connector -> encoder ->
9076 * crtc links if something is active, this means the
9077 * crtc is now deactivated. Break the links. connector
9078 * -> encoder links are only establish when things are
9079 * actually up, hence no need to break them. */
9080 WARN_ON(crtc->active);
9081
9082 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9083 WARN_ON(encoder->connectors_active);
9084 encoder->base.crtc = NULL;
9085 }
9086 }
9087}
9088
9089static void intel_sanitize_encoder(struct intel_encoder *encoder)
9090{
9091 struct intel_connector *connector;
9092 struct drm_device *dev = encoder->base.dev;
9093
9094 /* We need to check both for a crtc link (meaning that the
9095 * encoder is active and trying to read from a pipe) and the
9096 * pipe itself being active. */
9097 bool has_active_crtc = encoder->base.crtc &&
9098 to_intel_crtc(encoder->base.crtc)->active;
9099
9100 if (encoder->connectors_active && !has_active_crtc) {
9101 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9102 encoder->base.base.id,
9103 drm_get_encoder_name(&encoder->base));
9104
9105 /* Connector is active, but has no active pipe. This is
9106 * fallout from our resume register restoring. Disable
9107 * the encoder manually again. */
9108 if (encoder->base.crtc) {
9109 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9110 encoder->base.base.id,
9111 drm_get_encoder_name(&encoder->base));
9112 encoder->disable(encoder);
9113 }
9114
9115 /* Inconsistent output/port/pipe state happens presumably due to
9116 * a bug in one of the get_hw_state functions. Or someplace else
9117 * in our code, like the register restore mess on resume. Clamp
9118 * things to off as a safer default. */
9119 list_for_each_entry(connector,
9120 &dev->mode_config.connector_list,
9121 base.head) {
9122 if (connector->encoder != encoder)
9123 continue;
9124
9125 intel_connector_break_all_links(connector);
9126 }
9127 }
9128 /* Enabled encoders without active connectors will be fixed in
9129 * the crtc fixup. */
9130}
9131
44cec740 9132void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9133{
9134 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9135 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9136
9137 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9138 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9139 i915_disable_vga(dev);
0fde901f
KM		 9140 }
9141}
9142
24929352
DV		 9143/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9144 * and i915 state tracking structures. */
45e2b5f6
DV		 9145void intel_modeset_setup_hw_state(struct drm_device *dev,
9146 bool force_restore)
24929352
DV		 9147{
9148 struct drm_i915_private *dev_priv = dev->dev_private;
9149 enum pipe pipe;
9150 u32 tmp;
b5644d05 9151 struct drm_plane *plane;
24929352
DV		 9152 struct intel_crtc *crtc;
9153 struct intel_encoder *encoder;
9154 struct intel_connector *connector;
9155
affa9354 9156 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9157 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9158
9159 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9160 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9161 case TRANS_DDI_EDP_INPUT_A_ON:
9162 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9163 pipe = PIPE_A;
9164 break;
9165 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9166 pipe = PIPE_B;
9167 break;
9168 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9169 pipe = PIPE_C;
9170 break;
aaa148ec
DL		 9171 default:
9172 /* A bogus value has been programmed, disable
9173 * the transcoder */
9174 WARN(1, "Bogus eDP source %08x\n", tmp);
9175 intel_ddi_disable_transcoder_func(dev_priv,
9176 TRANSCODER_EDP);
9177 goto setup_pipes;
e28d54cb
PZ		 9178 }
9179
9180 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9181 crtc->cpu_transcoder = TRANSCODER_EDP;
9182
9183 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9184 pipe_name(pipe));
9185 }
9186 }
9187
aaa148ec 9188setup_pipes:
24929352
DV		 9189 for_each_pipe(pipe) {
9190 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9191
702e7a56 9192 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9193 if (tmp & PIPECONF_ENABLE)
9194 crtc->active = true;
9195 else
9196 crtc->active = false;
9197
9198 crtc->base.enabled = crtc->active;
9199
9200 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9201 crtc->base.base.id,
9202 crtc->active ? "enabled" : "disabled");
9203 }
9204
affa9354 9205 if (HAS_DDI(dev))
6441ab5f
PZ		 9206 intel_ddi_setup_hw_pll_state(dev);
9207
24929352
DV		 9208 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9209 base.head) {
9210 pipe = 0;
9211
9212 if (encoder->get_hw_state(encoder, &pipe)) {
9213 encoder->base.crtc =
9214 dev_priv->pipe_to_crtc_mapping[pipe];
9215 } else {
9216 encoder->base.crtc = NULL;
9217 }
9218
9219 encoder->connectors_active = false;
9220 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9221 encoder->base.base.id,
9222 drm_get_encoder_name(&encoder->base),
9223 encoder->base.crtc ? "enabled" : "disabled",
9224 pipe);
9225 }
9226
9227 list_for_each_entry(connector, &dev->mode_config.connector_list,
9228 base.head) {
9229 if (connector->get_hw_state(connector)) {
9230 connector->base.dpms = DRM_MODE_DPMS_ON;
9231 connector->encoder->connectors_active = true;
9232 connector->base.encoder = &connector->encoder->base;
9233 } else {
9234 connector->base.dpms = DRM_MODE_DPMS_OFF;
9235 connector->base.encoder = NULL;
9236 }
9237 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9238 connector->base.base.id,
9239 drm_get_connector_name(&connector->base),
9240 connector->base.encoder ? "enabled" : "disabled");
9241 }
9242
9243 /* HW state is read out, now we need to sanitize this mess. */
9244 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9245 base.head) {
9246 intel_sanitize_encoder(encoder);
9247 }
9248
9249 for_each_pipe(pipe) {
9250 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9251 intel_sanitize_crtc(crtc);
9252 }
9a935856 9253
45e2b5f6
DV		 9254 if (force_restore) {
9255 for_each_pipe(pipe) {
b5644d05
JB		 9256 struct drm_crtc *crtc =
9257 dev_priv->pipe_to_crtc_mapping[pipe];
9258 intel_crtc_restore_mode(crtc);
45e2b5f6 9259 }
b5644d05
JB		 9260 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9261 intel_plane_restore(plane);
0fde901f
KM		 9262
9263 i915_redisable_vga(dev);
45e2b5f6
DV		 9264 } else {
9265 intel_modeset_update_staged_output_state(dev);
9266 }
8af6cf88
DV		 9267
9268 intel_modeset_check_state(dev);
2e938892
DV		 9269
9270 drm_mode_config_reset(dev);
2c7111db
CW		 9271}
9272
9273void intel_modeset_gem_init(struct drm_device *dev)
9274{
1833b134 9275 intel_modeset_init_hw(dev);
02e792fb
DV		 9276
9277 intel_setup_overlay(dev);
24929352 9278
45e2b5f6 9279 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9280}
9281
9282void intel_modeset_cleanup(struct drm_device *dev)
9283{
652c393a
JB		 9284 struct drm_i915_private *dev_priv = dev->dev_private;
9285 struct drm_crtc *crtc;
9286 struct intel_crtc *intel_crtc;
9287
f87ea761 9288 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9289 mutex_lock(&dev->struct_mutex);
9290
723bfd70
JB		 9291 intel_unregister_dsm_handler();
9292
9293
652c393a
JB		 9294 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9295 /* Skip inactive CRTCs */
9296 if (!crtc->fb)
9297 continue;
9298
9299 intel_crtc = to_intel_crtc(crtc);
3dec0095 9300 intel_increase_pllclock(crtc);
652c393a
JB		 9301 }
9302
973d04f9 9303 intel_disable_fbc(dev);
e70236a8 9304
8090c6b9 9305 intel_disable_gt_powersave(dev);
0cdab21f 9306
930ebb46
DV		 9307 ironlake_teardown_rc6(dev);
9308
57f350b6
JB		 9309 if (IS_VALLEYVIEW(dev))
9310 vlv_init_dpio(dev);
9311
69341a5e
KH		 9312 mutex_unlock(&dev->struct_mutex);
9313
6c0d9350
DV		 9314 /* Disable the irq before mode object teardown, for the irq might
9315 * enqueue unpin/hotplug work. */
9316 drm_irq_uninstall(dev);
9317 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9318 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9319
1630fe75
CW		 9320 /* flush any delayed tasks or pending work */
9321 flush_scheduled_work();
9322
79e53945 9323 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9324
9325 intel_cleanup_overlay(dev);
79e53945
JB		 9326}
9327
f1c79df3
ZW		 9328/*
9329 * Return which encoder is currently attached for connector.
9330 */
df0e9248 9331struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9332{
df0e9248
CW		 9333 return &intel_attached_encoder(connector)->base;
9334}
f1c79df3 9335
df0e9248
CW		 9336void intel_connector_attach_encoder(struct intel_connector *connector,
9337 struct intel_encoder *encoder)
9338{
9339 connector->encoder = encoder;
9340 drm_mode_connector_attach_encoder(&connector->base,
9341 &encoder->base);
79e53945 9342}
28d52043
DA		 9343
9344/*
9345 * set vga decode state - true == enable VGA decode
9346 */
9347int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9348{
9349 struct drm_i915_private *dev_priv = dev->dev_private;
9350 u16 gmch_ctrl;
9351
9352 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9353 if (state)
9354 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9355 else
9356 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9357 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9358 return 0;
9359}
c4a1d9e4
CW		 9360
9361#ifdef CONFIG_DEBUG_FS
9362#include <linux/seq_file.h>
9363
9364struct intel_display_error_state {
9365 struct intel_cursor_error_state {
9366 u32 control;
9367 u32 position;
9368 u32 base;
9369 u32 size;
52331309 9370 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9371
9372 struct intel_pipe_error_state {
9373 u32 conf;
9374 u32 source;
9375
9376 u32 htotal;
9377 u32 hblank;
9378 u32 hsync;
9379 u32 vtotal;
9380 u32 vblank;
9381 u32 vsync;
52331309 9382 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9383
9384 struct intel_plane_error_state {
9385 u32 control;
9386 u32 stride;
9387 u32 size;
9388 u32 pos;
9389 u32 addr;
9390 u32 surface;
9391 u32 tile_offset;
52331309 9392 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9393};
9394
9395struct intel_display_error_state *
9396intel_display_capture_error_state(struct drm_device *dev)
9397{
0206e353 9398 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9399 struct intel_display_error_state *error;
702e7a56 9400 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9401 int i;
9402
9403 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9404 if (error == NULL)
9405 return NULL;
9406
52331309 9407 for_each_pipe(i) {
702e7a56
PZ		 9408 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9409
a18c4c3d
PZ		 9410 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9411 error->cursor[i].control = I915_READ(CURCNTR(i));
9412 error->cursor[i].position = I915_READ(CURPOS(i));
9413 error->cursor[i].base = I915_READ(CURBASE(i));
9414 } else {
9415 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9416 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9417 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9418 }
c4a1d9e4
CW		 9419
9420 error->plane[i].control = I915_READ(DSPCNTR(i));
9421 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9422 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9423 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9424 error->plane[i].pos = I915_READ(DSPPOS(i));
9425 }
ca291363
PZ		 9426 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9427 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9428 if (INTEL_INFO(dev)->gen >= 4) {
9429 error->plane[i].surface = I915_READ(DSPSURF(i));
9430 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9431 }
9432
702e7a56 9433 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9434 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9435 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9436 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9437 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9438 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9439 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9440 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9441 }
9442
9443 return error;
9444}
9445
9446void
9447intel_display_print_error_state(struct seq_file *m,
9448 struct drm_device *dev,
9449 struct intel_display_error_state *error)
9450{
9451 int i;
9452
7eb552ae 9453 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9454 for_each_pipe(i) {
c4a1d9e4
CW		 9455 seq_printf(m, "Pipe [%d]:\n", i);
9456 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9457 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9458 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9459 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9460 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9461 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9462 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9463 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9464
9465 seq_printf(m, "Plane [%d]:\n", i);
9466 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9467 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9468 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9469 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9470 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9471 }
4b71a570 9472 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9473 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9474 if (INTEL_INFO(dev)->gen >= 4) {
9475 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9476 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9477 }
9478
9479 seq_printf(m, "Cursor [%d]:\n", i);
9480 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9481 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9482 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9483 }
9484}
9485#endif
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