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drm/i915: Error out when trying to set a y-tiled as a sprite
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a
JB		 1581/**
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
ee7b9f93 1589static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
040484af
JB		 1673static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
1724static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
1839 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841}
1842
b24e7179
JB		 1843/**
1844 * intel_enable_plane - enable a display plane on a given pipe
1845 * @dev_priv: i915 private structure
1846 * @plane: plane to enable
1847 * @pipe: pipe being fed
1848 *
1849 * Enable @plane on @pipe, making sure that @pipe is running first.
1850 */
1851static void intel_enable_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane, enum pipe pipe)
1853{
1854 int reg;
1855 u32 val;
1856
1857 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858 assert_pipe_enabled(dev_priv, pipe);
1859
1860 reg = DSPCNTR(plane);
1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & DISPLAY_PLANE_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1866 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1867 intel_wait_for_vblank(dev_priv->dev, pipe);
1868}
1869
b24e7179
JB		 1870/**
1871 * intel_disable_plane - disable a display plane
1872 * @dev_priv: i915 private structure
1873 * @plane: plane to disable
1874 * @pipe: pipe consuming the data
1875 *
1876 * Disable @plane; should be an independent operation.
1877 */
1878static void intel_disable_plane(struct drm_i915_private *dev_priv,
1879 enum plane plane, enum pipe pipe)
1880{
1881 int reg;
1882 u32 val;
1883
1884 reg = DSPCNTR(plane);
1885 val = I915_READ(reg);
00d70b15
CW		 1886 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887 return;
1888
1889 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1890 intel_flush_display_plane(dev_priv, plane);
1891 intel_wait_for_vblank(dev_priv->dev, pipe);
1892}
1893
127bd2ac 1894int
48b956c5 1895intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1896 struct drm_i915_gem_object *obj,
919926ae 1897 struct intel_ring_buffer *pipelined)
6b95a207 1898{
ce453d81 1899 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1900 u32 alignment;
1901 int ret;
1902
05394f39 1903 switch (obj->tiling_mode) {
6b95a207 1904 case I915_TILING_NONE:
534843da
CW		 1905 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1906 alignment = 128 * 1024;
a6c45cf0 1907 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1908 alignment = 4 * 1024;
1909 else
1910 alignment = 64 * 1024;
6b95a207
KH		 1911 break;
1912 case I915_TILING_X:
1913 /* pin() will align the object as required by fence */
1914 alignment = 0;
1915 break;
1916 case I915_TILING_Y:
1917 /* FIXME: Is this true? */
1918 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1919 return -EINVAL;
1920 default:
1921 BUG();
1922 }
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1959 unsigned int bpp,
1960 unsigned int pitch)
1961{
1962 int tile_rows, tiles;
1963
1964 tile_rows = *y / 8;
1965 *y %= 8;
1966 tiles = *x / (512/bpp);
1967 *x %= 512/bpp;
1968
1969 return tile_rows * pitch * 8 + tiles * 4096;
1970}
1971
17638cd6
JB		 1972static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1973 int x, int y)
81255565
JB		 1974{
1975 struct drm_device *dev = crtc->dev;
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 struct intel_framebuffer *intel_fb;
05394f39 1979 struct drm_i915_gem_object *obj;
81255565 1980 int plane = intel_crtc->plane;
e506a0c6 1981 unsigned long linear_offset;
81255565 1982 u32 dspcntr;
5eddb70b 1983 u32 reg;
81255565
JB		 1984
1985 switch (plane) {
1986 case 0:
1987 case 1:
1988 break;
1989 default:
1990 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1991 return -EINVAL;
1992 }
1993
1994 intel_fb = to_intel_framebuffer(fb);
1995 obj = intel_fb->obj;
81255565 1996
5eddb70b
CW		 1997 reg = DSPCNTR(plane);
1998 dspcntr = I915_READ(reg);
81255565
JB		 1999 /* Mask out pixel format bits in case we change it */
2000 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2001 switch (fb->bits_per_pixel) {
2002 case 8:
2003 dspcntr |= DISPPLANE_8BPP;
2004 break;
2005 case 16:
2006 if (fb->depth == 15)
2007 dspcntr |= DISPPLANE_15_16BPP;
2008 else
2009 dspcntr |= DISPPLANE_16BPP;
2010 break;
2011 case 24:
2012 case 32:
2013 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2014 break;
2015 default:
17638cd6 2016 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2017 return -EINVAL;
2018 }
a6c45cf0 2019 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2020 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2021 dspcntr |= DISPPLANE_TILED;
2022 else
2023 dspcntr &= ~DISPPLANE_TILED;
2024 }
2025
5eddb70b 2026 I915_WRITE(reg, dspcntr);
81255565 2027
e506a0c6 2028 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2029
c2c75131
DV		 2030 if (INTEL_INFO(dev)->gen >= 4) {
2031 intel_crtc->dspaddr_offset =
2032 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2033 fb->bits_per_pixel / 8,
2034 fb->pitches[0]);
2035 linear_offset -= intel_crtc->dspaddr_offset;
2036 } else {
e506a0c6 2037 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2038 }
e506a0c6
DV		 2039
2040 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2042 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2044 I915_MODIFY_DISPBASE(DSPSURF(plane),
2045 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2046 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2047 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2048 } else
e506a0c6 2049 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2050 POSTING_READ(reg);
81255565 2051
17638cd6
JB		 2052 return 0;
2053}
2054
2055static int ironlake_update_plane(struct drm_crtc *crtc,
2056 struct drm_framebuffer *fb, int x, int y)
2057{
2058 struct drm_device *dev = crtc->dev;
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061 struct intel_framebuffer *intel_fb;
2062 struct drm_i915_gem_object *obj;
2063 int plane = intel_crtc->plane;
e506a0c6 2064 unsigned long linear_offset;
17638cd6
JB		 2065 u32 dspcntr;
2066 u32 reg;
2067
2068 switch (plane) {
2069 case 0:
2070 case 1:
27f8227b 2071 case 2:
17638cd6
JB		 2072 break;
2073 default:
2074 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075 return -EINVAL;
2076 }
2077
2078 intel_fb = to_intel_framebuffer(fb);
2079 obj = intel_fb->obj;
2080
2081 reg = DSPCNTR(plane);
2082 dspcntr = I915_READ(reg);
2083 /* Mask out pixel format bits in case we change it */
2084 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085 switch (fb->bits_per_pixel) {
2086 case 8:
2087 dspcntr |= DISPPLANE_8BPP;
2088 break;
2089 case 16:
2090 if (fb->depth != 16)
2091 return -EINVAL;
2092
2093 dspcntr |= DISPPLANE_16BPP;
2094 break;
2095 case 24:
2096 case 32:
2097 if (fb->depth == 24)
2098 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2099 else if (fb->depth == 30)
2100 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2101 else
2102 return -EINVAL;
2103 break;
2104 default:
2105 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2106 return -EINVAL;
2107 }
2108
2109 if (obj->tiling_mode != I915_TILING_NONE)
2110 dspcntr |= DISPPLANE_TILED;
2111 else
2112 dspcntr &= ~DISPPLANE_TILED;
2113
2114 /* must disable */
2115 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2116
2117 I915_WRITE(reg, dspcntr);
2118
e506a0c6 2119 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2120 intel_crtc->dspaddr_offset =
2121 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2122 fb->bits_per_pixel / 8,
2123 fb->pitches[0]);
2124 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2125
e506a0c6
DV		 2126 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2128 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2129 I915_MODIFY_DISPBASE(DSPSURF(plane),
2130 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2131 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2132 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2133 POSTING_READ(reg);
2134
2135 return 0;
2136}
2137
2138/* Assume fb object is pinned & idle & fenced and just update base pointers */
2139static int
2140intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2141 int x, int y, enum mode_set_atomic state)
2142{
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2145
6b8e6ed0
CW		 2146 if (dev_priv->display.disable_fbc)
2147 dev_priv->display.disable_fbc(dev);
3dec0095 2148 intel_increase_pllclock(crtc);
81255565 2149
6b8e6ed0 2150 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2151}
2152
14667a4b
CW		 2153static int
2154intel_finish_fb(struct drm_framebuffer *old_fb)
2155{
2156 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2157 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2158 bool was_interruptible = dev_priv->mm.interruptible;
2159 int ret;
2160
2161 wait_event(dev_priv->pending_flip_queue,
2162 atomic_read(&dev_priv->mm.wedged) ||
2163 atomic_read(&obj->pending_flip) == 0);
2164
2165 /* Big Hammer, we also need to ensure that any pending
2166 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2167 * current scanout is retired before unpinning the old
2168 * framebuffer.
2169 *
2170 * This should only fail upon a hung GPU, in which case we
2171 * can safely continue.
2172 */
2173 dev_priv->mm.interruptible = false;
2174 ret = i915_gem_object_finish_gpu(obj);
2175 dev_priv->mm.interruptible = was_interruptible;
2176
2177 return ret;
2178}
2179
5c3b82e2 2180static int
3c4fdcfb 2181intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2182 struct drm_framebuffer *fb)
79e53945
JB		 2183{
2184 struct drm_device *dev = crtc->dev;
6b8e6ed0 2185 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2186 struct drm_i915_master_private *master_priv;
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2188 struct drm_framebuffer *old_fb;
5c3b82e2 2189 int ret;
79e53945
JB		 2190
2191 /* no fb bound */
94352cf9 2192 if (!fb) {
a5071c2f 2193 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2194 return 0;
2195 }
2196
5826eca5
ED		 2197 if(intel_crtc->plane > dev_priv->num_pipe) {
2198 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2199 intel_crtc->plane,
2200 dev_priv->num_pipe);
5c3b82e2 2201 return -EINVAL;
79e53945
JB		 2202 }
2203
5c3b82e2 2204 mutex_lock(&dev->struct_mutex);
265db958 2205 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2206 to_intel_framebuffer(fb)->obj,
919926ae 2207 NULL);
5c3b82e2
CW		 2208 if (ret != 0) {
2209 mutex_unlock(&dev->struct_mutex);
a5071c2f 2210 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2211 return ret;
2212 }
79e53945 2213
94352cf9
DV		 2214 if (crtc->fb)
2215 intel_finish_fb(crtc->fb);
265db958 2216
94352cf9 2217 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2218 if (ret) {
94352cf9 2219 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2220 mutex_unlock(&dev->struct_mutex);
a5071c2f 2221 DRM_ERROR("failed to update base address\n");
4e6cfefc 2222 return ret;
79e53945 2223 }
3c4fdcfb 2224
94352cf9
DV		 2225 old_fb = crtc->fb;
2226 crtc->fb = fb;
6c4c86f5
DV		 2227 crtc->x = x;
2228 crtc->y = y;
94352cf9 2229
b7f1de28
CW		 2230 if (old_fb) {
2231 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2232 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2233 }
652c393a 2234
6b8e6ed0 2235 intel_update_fbc(dev);
5c3b82e2 2236 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2237
2238 if (!dev->primary->master)
5c3b82e2 2239 return 0;
79e53945
JB		 2240
2241 master_priv = dev->primary->master->driver_priv;
2242 if (!master_priv->sarea_priv)
5c3b82e2 2243 return 0;
79e53945 2244
265db958 2245 if (intel_crtc->pipe) {
79e53945
JB		 2246 master_priv->sarea_priv->pipeB_x = x;
2247 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2248 } else {
2249 master_priv->sarea_priv->pipeA_x = x;
2250 master_priv->sarea_priv->pipeA_y = y;
79e53945 2251 }
5c3b82e2
CW		 2252
2253 return 0;
79e53945
JB		 2254}
2255
5eddb70b 2256static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2257{
2258 struct drm_device *dev = crtc->dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 u32 dpa_ctl;
2261
28c97730 2262 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2263 dpa_ctl = I915_READ(DP_A);
2264 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266 if (clock < 200000) {
2267 u32 temp;
2268 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269 /* workaround for 160Mhz:
2270 1) program 0x4600c bits 15:0 = 0x8124
2271 2) program 0x46010 bit 0 = 1
2272 3) program 0x46034 bit 24 = 1
2273 4) program 0x64000 bit 14 = 1
2274 */
2275 temp = I915_READ(0x4600c);
2276 temp &= 0xffff0000;
2277 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279 temp = I915_READ(0x46010);
2280 I915_WRITE(0x46010, temp | 1);
2281
2282 temp = I915_READ(0x46034);
2283 I915_WRITE(0x46034, temp | (1 << 24));
2284 } else {
2285 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286 }
2287 I915_WRITE(DP_A, dpa_ctl);
2288
5eddb70b 2289 POSTING_READ(DP_A);
32f9d658
ZW		 2290 udelay(500);
2291}
2292
5e84e1a4
ZW		 2293static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294{
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 int pipe = intel_crtc->pipe;
2299 u32 reg, temp;
2300
2301 /* enable normal train */
2302 reg = FDI_TX_CTL(pipe);
2303 temp = I915_READ(reg);
61e499bf 2304 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2305 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2307 } else {
2308 temp &= ~FDI_LINK_TRAIN_NONE;
2309 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2310 }
5e84e1a4
ZW		 2311 I915_WRITE(reg, temp);
2312
2313 reg = FDI_RX_CTL(pipe);
2314 temp = I915_READ(reg);
2315 if (HAS_PCH_CPT(dev)) {
2316 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318 } else {
2319 temp &= ~FDI_LINK_TRAIN_NONE;
2320 temp |= FDI_LINK_TRAIN_NONE;
2321 }
2322 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324 /* wait one idle pattern time */
2325 POSTING_READ(reg);
2326 udelay(1000);
357555c0
JB		 2327
2328 /* IVB wants error correction enabled */
2329 if (IS_IVYBRIDGE(dev))
2330 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2332}
2333
291427f5
JB		 2334static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335{
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339 flags |= FDI_PHASE_SYNC_OVR(pipe);
2340 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341 flags |= FDI_PHASE_SYNC_EN(pipe);
2342 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343 POSTING_READ(SOUTH_CHICKEN1);
2344}
2345
01a415fd
DV		 2346static void ivb_modeset_global_resources(struct drm_device *dev)
2347{
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct intel_crtc *pipe_B_crtc =
2350 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2351 struct intel_crtc *pipe_C_crtc =
2352 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2353 uint32_t temp;
2354
2355 /* When everything is off disable fdi C so that we could enable fdi B
2356 * with all lanes. XXX: This misses the case where a pipe is not using
2357 * any pch resources and so doesn't need any fdi lanes. */
2358 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2359 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2360 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2361
2362 temp = I915_READ(SOUTH_CHICKEN1);
2363 temp &= ~FDI_BC_BIFURCATION_SELECT;
2364 DRM_DEBUG_KMS("disabling fdi C rx\n");
2365 I915_WRITE(SOUTH_CHICKEN1, temp);
2366 }
2367}
2368
8db9d77b
ZW		 2369/* The FDI link training functions for ILK/Ibexpeak. */
2370static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2371{
2372 struct drm_device *dev = crtc->dev;
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375 int pipe = intel_crtc->pipe;
0fc932b8 2376 int plane = intel_crtc->plane;
5eddb70b 2377 u32 reg, temp, tries;
8db9d77b 2378
0fc932b8
JB		 2379 /* FDI needs bits from pipe & plane first */
2380 assert_pipe_enabled(dev_priv, pipe);
2381 assert_plane_enabled(dev_priv, plane);
2382
e1a44743
AJ		 2383 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2384 for train result */
5eddb70b
CW		 2385 reg = FDI_RX_IMR(pipe);
2386 temp = I915_READ(reg);
e1a44743
AJ		 2387 temp &= ~FDI_RX_SYMBOL_LOCK;
2388 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2389 I915_WRITE(reg, temp);
2390 I915_READ(reg);
e1a44743
AJ		 2391 udelay(150);
2392
8db9d77b 2393 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2394 reg = FDI_TX_CTL(pipe);
2395 temp = I915_READ(reg);
77ffb597
AJ		 2396 temp &= ~(7 << 19);
2397 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2400 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2401
5eddb70b
CW		 2402 reg = FDI_RX_CTL(pipe);
2403 temp = I915_READ(reg);
8db9d77b
ZW		 2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2406 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2407
2408 POSTING_READ(reg);
8db9d77b
ZW		 2409 udelay(150);
2410
5b2adf89 2411 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2412 if (HAS_PCH_IBX(dev)) {
2413 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2414 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2415 FDI_RX_PHASE_SYNC_POINTER_EN);
2416 }
5b2adf89 2417
5eddb70b 2418 reg = FDI_RX_IIR(pipe);
e1a44743 2419 for (tries = 0; tries < 5; tries++) {
5eddb70b 2420 temp = I915_READ(reg);
8db9d77b
ZW		 2421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2422
2423 if ((temp & FDI_RX_BIT_LOCK)) {
2424 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2426 break;
2427 }
8db9d77b 2428 }
e1a44743 2429 if (tries == 5)
5eddb70b 2430 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2431
2432 /* Train 2 */
5eddb70b
CW		 2433 reg = FDI_TX_CTL(pipe);
2434 temp = I915_READ(reg);
8db9d77b
ZW		 2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2437 I915_WRITE(reg, temp);
8db9d77b 2438
5eddb70b
CW		 2439 reg = FDI_RX_CTL(pipe);
2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2443 I915_WRITE(reg, temp);
8db9d77b 2444
5eddb70b
CW		 2445 POSTING_READ(reg);
2446 udelay(150);
8db9d77b 2447
5eddb70b 2448 reg = FDI_RX_IIR(pipe);
e1a44743 2449 for (tries = 0; tries < 5; tries++) {
5eddb70b 2450 temp = I915_READ(reg);
8db9d77b
ZW		 2451 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2452
2453 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2454 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2455 DRM_DEBUG_KMS("FDI train 2 done.\n");
2456 break;
2457 }
8db9d77b 2458 }
e1a44743 2459 if (tries == 5)
5eddb70b 2460 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2461
2462 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2463
8db9d77b
ZW		 2464}
2465
0206e353 2466static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2467 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2468 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2469 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2470 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2471};
2472
2473/* The FDI link training functions for SNB/Cougarpoint. */
2474static void gen6_fdi_link_train(struct drm_crtc *crtc)
2475{
2476 struct drm_device *dev = crtc->dev;
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2479 int pipe = intel_crtc->pipe;
fa37d39e 2480 u32 reg, temp, i, retry;
8db9d77b 2481
e1a44743
AJ		 2482 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2483 for train result */
5eddb70b
CW		 2484 reg = FDI_RX_IMR(pipe);
2485 temp = I915_READ(reg);
e1a44743
AJ		 2486 temp &= ~FDI_RX_SYMBOL_LOCK;
2487 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2488 I915_WRITE(reg, temp);
2489
2490 POSTING_READ(reg);
e1a44743
AJ		 2491 udelay(150);
2492
8db9d77b 2493 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2494 reg = FDI_TX_CTL(pipe);
2495 temp = I915_READ(reg);
77ffb597
AJ		 2496 temp &= ~(7 << 19);
2497 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_1;
2500 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2501 /* SNB-B */
2502 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2503 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2504
d74cf324
DV		 2505 I915_WRITE(FDI_RX_MISC(pipe),
2506 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2507
5eddb70b
CW		 2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 if (HAS_PCH_CPT(dev)) {
2511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2513 } else {
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_1;
2516 }
5eddb70b
CW		 2517 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2518
2519 POSTING_READ(reg);
8db9d77b
ZW		 2520 udelay(150);
2521
291427f5
JB		 2522 if (HAS_PCH_CPT(dev))
2523 cpt_phase_pointer_enable(dev, pipe);
2524
0206e353 2525 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
8db9d77b
ZW		 2528 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2529 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2530 I915_WRITE(reg, temp);
2531
2532 POSTING_READ(reg);
8db9d77b
ZW		 2533 udelay(500);
2534
fa37d39e
SP		 2535 for (retry = 0; retry < 5; retry++) {
2536 reg = FDI_RX_IIR(pipe);
2537 temp = I915_READ(reg);
2538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2539 if (temp & FDI_RX_BIT_LOCK) {
2540 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2541 DRM_DEBUG_KMS("FDI train 1 done.\n");
2542 break;
2543 }
2544 udelay(50);
8db9d77b 2545 }
fa37d39e
SP		 2546 if (retry < 5)
2547 break;
8db9d77b
ZW		 2548 }
2549 if (i == 4)
5eddb70b 2550 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2551
2552 /* Train 2 */
5eddb70b
CW		 2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
8db9d77b
ZW		 2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
2557 if (IS_GEN6(dev)) {
2558 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2559 /* SNB-B */
2560 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2561 }
5eddb70b 2562 I915_WRITE(reg, temp);
8db9d77b 2563
5eddb70b
CW		 2564 reg = FDI_RX_CTL(pipe);
2565 temp = I915_READ(reg);
8db9d77b
ZW		 2566 if (HAS_PCH_CPT(dev)) {
2567 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2568 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2569 } else {
2570 temp &= ~FDI_LINK_TRAIN_NONE;
2571 temp |= FDI_LINK_TRAIN_PATTERN_2;
2572 }
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(150);
2577
0206e353 2578 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
8db9d77b
ZW		 2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2583 I915_WRITE(reg, temp);
2584
2585 POSTING_READ(reg);
8db9d77b
ZW		 2586 udelay(500);
2587
fa37d39e
SP		 2588 for (retry = 0; retry < 5; retry++) {
2589 reg = FDI_RX_IIR(pipe);
2590 temp = I915_READ(reg);
2591 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2592 if (temp & FDI_RX_SYMBOL_LOCK) {
2593 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2594 DRM_DEBUG_KMS("FDI train 2 done.\n");
2595 break;
2596 }
2597 udelay(50);
8db9d77b 2598 }
fa37d39e
SP		 2599 if (retry < 5)
2600 break;
8db9d77b
ZW		 2601 }
2602 if (i == 4)
5eddb70b 2603 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2604
2605 DRM_DEBUG_KMS("FDI train done.\n");
2606}
2607
357555c0
JB		 2608/* Manual link training for Ivy Bridge A0 parts */
2609static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2610{
2611 struct drm_device *dev = crtc->dev;
2612 struct drm_i915_private *dev_priv = dev->dev_private;
2613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2614 int pipe = intel_crtc->pipe;
2615 u32 reg, temp, i;
2616
2617 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2618 for train result */
2619 reg = FDI_RX_IMR(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_RX_SYMBOL_LOCK;
2622 temp &= ~FDI_RX_BIT_LOCK;
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(150);
2627
01a415fd
DV		 2628 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2629 I915_READ(FDI_RX_IIR(pipe)));
2630
357555c0
JB		 2631 /* enable CPU FDI TX and PCH FDI RX */
2632 reg = FDI_TX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~(7 << 19);
2635 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2636 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2637 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2640 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2641 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2642
d74cf324
DV		 2643 I915_WRITE(FDI_RX_MISC(pipe),
2644 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2645
357555c0
JB		 2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_AUTO;
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2651 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2652 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
291427f5
JB		 2657 if (HAS_PCH_CPT(dev))
2658 cpt_phase_pointer_enable(dev, pipe);
2659
0206e353 2660 for (i = 0; i < 4; i++) {
357555c0
JB		 2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
2668 udelay(500);
2669
2670 reg = FDI_RX_IIR(pipe);
2671 temp = I915_READ(reg);
2672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673
2674 if (temp & FDI_RX_BIT_LOCK ||
2675 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2676 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2677 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2678 break;
2679 }
2680 }
2681 if (i == 4)
2682 DRM_ERROR("FDI train 1 fail!\n");
2683
2684 /* Train 2 */
2685 reg = FDI_TX_CTL(pipe);
2686 temp = I915_READ(reg);
2687 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2691 I915_WRITE(reg, temp);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2696 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2697 I915_WRITE(reg, temp);
2698
2699 POSTING_READ(reg);
2700 udelay(150);
2701
0206e353 2702 for (i = 0; i < 4; i++) {
357555c0
JB		 2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2706 temp |= snb_b_fdi_train_param[i];
2707 I915_WRITE(reg, temp);
2708
2709 POSTING_READ(reg);
2710 udelay(500);
2711
2712 reg = FDI_RX_IIR(pipe);
2713 temp = I915_READ(reg);
2714 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2715
2716 if (temp & FDI_RX_SYMBOL_LOCK) {
2717 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2718 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2719 break;
2720 }
2721 }
2722 if (i == 4)
2723 DRM_ERROR("FDI train 2 fail!\n");
2724
2725 DRM_DEBUG_KMS("FDI train done.\n");
2726}
2727
88cefb6c 2728static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2729{
88cefb6c 2730 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2731 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2732 int pipe = intel_crtc->pipe;
5eddb70b 2733 u32 reg, temp;
79e53945 2734
c64e311e 2735
c98e9dcf 2736 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2740 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2741 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2742 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2743
2744 POSTING_READ(reg);
c98e9dcf
JB		 2745 udelay(200);
2746
2747 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2748 temp = I915_READ(reg);
2749 I915_WRITE(reg, temp | FDI_PCDCLK);
2750
2751 POSTING_READ(reg);
c98e9dcf
JB		 2752 udelay(200);
2753
bf507ef7
ED		 2754 /* On Haswell, the PLL configuration for ports and pipes is handled
2755 * separately, as part of DDI setup */
2756 if (!IS_HASWELL(dev)) {
2757 /* Enable CPU FDI TX PLL, always on for Ironlake */
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2761 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2762
bf507ef7
ED		 2763 POSTING_READ(reg);
2764 udelay(100);
2765 }
6be4a607 2766 }
0e23b99d
JB		 2767}
2768
88cefb6c
DV		 2769static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2770{
2771 struct drm_device *dev = intel_crtc->base.dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 int pipe = intel_crtc->pipe;
2774 u32 reg, temp;
2775
2776 /* Switch from PCDclk to Rawclk */
2777 reg = FDI_RX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2780
2781 /* Disable CPU FDI TX PLL */
2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2785
2786 POSTING_READ(reg);
2787 udelay(100);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2792
2793 /* Wait for the clocks to turn off. */
2794 POSTING_READ(reg);
2795 udelay(100);
2796}
2797
291427f5
JB		 2798static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2799{
2800 struct drm_i915_private *dev_priv = dev->dev_private;
2801 u32 flags = I915_READ(SOUTH_CHICKEN1);
2802
2803 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2804 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2805 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2806 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2807 POSTING_READ(SOUTH_CHICKEN1);
2808}
0fc932b8
JB		 2809static void ironlake_fdi_disable(struct drm_crtc *crtc)
2810{
2811 struct drm_device *dev = crtc->dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2814 int pipe = intel_crtc->pipe;
2815 u32 reg, temp;
2816
2817 /* disable CPU FDI tx and PCH FDI rx */
2818 reg = FDI_TX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2821 POSTING_READ(reg);
2822
2823 reg = FDI_RX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 temp &= ~(0x7 << 16);
2826 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2827 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2828
2829 POSTING_READ(reg);
2830 udelay(100);
2831
2832 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2833 if (HAS_PCH_IBX(dev)) {
2834 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2835 I915_WRITE(FDI_RX_CHICKEN(pipe),
2836 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2837 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2838 } else if (HAS_PCH_CPT(dev)) {
2839 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2840 }
0fc932b8
JB		 2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865}
2866
5bb61643
CW		 2867static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868{
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 unsigned long flags;
2872 bool pending;
2873
2874 if (atomic_read(&dev_priv->mm.wedged))
2875 return false;
2876
2877 spin_lock_irqsave(&dev->event_lock, flags);
2878 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879 spin_unlock_irqrestore(&dev->event_lock, flags);
2880
2881 return pending;
2882}
2883
e6c3a2a6
CW		 2884static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2885{
0f91128d 2886 struct drm_device *dev = crtc->dev;
5bb61643 2887 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2888
2889 if (crtc->fb == NULL)
2890 return;
2891
5bb61643
CW		 2892 wait_event(dev_priv->pending_flip_queue,
2893 !intel_crtc_has_pending_flip(crtc));
2894
0f91128d
CW		 2895 mutex_lock(&dev->struct_mutex);
2896 intel_finish_fb(crtc->fb);
2897 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2898}
2899
fc316cbe 2900static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2901{
2902 struct drm_device *dev = crtc->dev;
228d3e36 2903 struct intel_encoder *intel_encoder;
040484af
JB		 2904
2905 /*
2906 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2907 * must be driven by its own crtc; no sharing is possible.
2908 */
228d3e36 2909 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2910 switch (intel_encoder->type) {
040484af 2911 case INTEL_OUTPUT_EDP:
228d3e36 2912 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2913 return false;
2914 continue;
2915 }
2916 }
2917
2918 return true;
2919}
2920
fc316cbe
PZ		 2921static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2922{
2923 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2924}
2925
e615efe4
ED		 2926/* Program iCLKIP clock to the desired frequency */
2927static void lpt_program_iclkip(struct drm_crtc *crtc)
2928{
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2932 u32 temp;
2933
2934 /* It is necessary to ungate the pixclk gate prior to programming
2935 * the divisors, and gate it back when it is done.
2936 */
2937 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2938
2939 /* Disable SSCCTL */
2940 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2941 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2942 SBI_SSCCTL_DISABLE);
2943
2944 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2945 if (crtc->mode.clock == 20000) {
2946 auxdiv = 1;
2947 divsel = 0x41;
2948 phaseinc = 0x20;
2949 } else {
2950 /* The iCLK virtual clock root frequency is in MHz,
2951 * but the crtc->mode.clock in in KHz. To get the divisors,
2952 * it is necessary to divide one by another, so we
2953 * convert the virtual clock precision to KHz here for higher
2954 * precision.
2955 */
2956 u32 iclk_virtual_root_freq = 172800 * 1000;
2957 u32 iclk_pi_range = 64;
2958 u32 desired_divisor, msb_divisor_value, pi_value;
2959
2960 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2961 msb_divisor_value = desired_divisor / iclk_pi_range;
2962 pi_value = desired_divisor % iclk_pi_range;
2963
2964 auxdiv = 0;
2965 divsel = msb_divisor_value - 2;
2966 phaseinc = pi_value;
2967 }
2968
2969 /* This should not happen with any sane values */
2970 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2971 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2972 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2973 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2974
2975 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2976 crtc->mode.clock,
2977 auxdiv,
2978 divsel,
2979 phasedir,
2980 phaseinc);
2981
2982 /* Program SSCDIVINTPHASE6 */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2984 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2985 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2986 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2987 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2988 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2989 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2990
2991 intel_sbi_write(dev_priv,
2992 SBI_SSCDIVINTPHASE6,
2993 temp);
2994
2995 /* Program SSCAUXDIV */
2996 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2997 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2998 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2999 intel_sbi_write(dev_priv,
3000 SBI_SSCAUXDIV6,
3001 temp);
3002
3003
3004 /* Enable modulator and associated divider */
3005 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3006 temp &= ~SBI_SSCCTL_DISABLE;
3007 intel_sbi_write(dev_priv,
3008 SBI_SSCCTL6,
3009 temp);
3010
3011 /* Wait for initialization time */
3012 udelay(24);
3013
3014 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3015}
3016
f67a559d
JB		 3017/*
3018 * Enable PCH resources required for PCH ports:
3019 * - PCH PLLs
3020 * - FDI training & RX/TX
3021 * - update transcoder timings
3022 * - DP transcoding bits
3023 * - transcoder
3024 */
3025static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3026{
3027 struct drm_device *dev = crtc->dev;
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3030 int pipe = intel_crtc->pipe;
ee7b9f93 3031 u32 reg, temp;
2c07245f 3032
e7e164db
CW		 3033 assert_transcoder_disabled(dev_priv, pipe);
3034
cd986abb
DV		 3035 /* Write the TU size bits before fdi link training, so that error
3036 * detection works. */
3037 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3038 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3039
c98e9dcf 3040 /* For PCH output, training FDI link */
674cf967 3041 dev_priv->display.fdi_link_train(crtc);
2c07245f 3042
572deb37
DV		 3043 /* XXX: pch pll's can be enabled any time before we enable the PCH
3044 * transcoder, and we actually should do this to not upset any PCH
3045 * transcoder that already use the clock when we share it.
3046 *
3047 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3048 * unconditionally resets the pll - we need that to have the right LVDS
3049 * enable sequence. */
6f13b7b5
CW		 3050 intel_enable_pch_pll(intel_crtc);
3051
e615efe4
ED		 3052 if (HAS_PCH_LPT(dev)) {
3053 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3054 lpt_program_iclkip(crtc);
3055 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3056 u32 sel;
4b645f14 3057
c98e9dcf 3058 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3059 switch (pipe) {
3060 default:
3061 case 0:
3062 temp |= TRANSA_DPLL_ENABLE;
3063 sel = TRANSA_DPLLB_SEL;
3064 break;
3065 case 1:
3066 temp |= TRANSB_DPLL_ENABLE;
3067 sel = TRANSB_DPLLB_SEL;
3068 break;
3069 case 2:
3070 temp |= TRANSC_DPLL_ENABLE;
3071 sel = TRANSC_DPLLB_SEL;
3072 break;
d64311ab 3073 }
ee7b9f93
JB		 3074 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3075 temp |= sel;
3076 else
3077 temp &= ~sel;
c98e9dcf 3078 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3079 }
5eddb70b 3080
d9b6cb56
JB		 3081 /* set transcoder timing, panel must allow it */
3082 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3083 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3084 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3085 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3086
5eddb70b
CW		 3087 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3088 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3089 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3090 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3091
f57e1e3a
ED		 3092 if (!IS_HASWELL(dev))
3093 intel_fdi_normal_train(crtc);
5e84e1a4 3094
c98e9dcf
JB		 3095 /* For PCH DP, enable TRANS_DP_CTL */
3096 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3097 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3098 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3099 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3100 reg = TRANS_DP_CTL(pipe);
3101 temp = I915_READ(reg);
3102 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3103 TRANS_DP_SYNC_MASK |
3104 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3105 temp |= (TRANS_DP_OUTPUT_ENABLE |
3106 TRANS_DP_ENH_FRAMING);
9325c9f0 3107 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3108
3109 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3110 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3111 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3112 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3113
3114 switch (intel_trans_dp_port_sel(crtc)) {
3115 case PCH_DP_B:
5eddb70b 3116 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3117 break;
3118 case PCH_DP_C:
5eddb70b 3119 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3120 break;
3121 case PCH_DP_D:
5eddb70b 3122 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3123 break;
3124 default:
e95d41e1 3125 BUG();
32f9d658 3126 }
2c07245f 3127
5eddb70b 3128 I915_WRITE(reg, temp);
6be4a607 3129 }
b52eb4dc 3130
040484af 3131 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3132}
3133
ee7b9f93
JB		 3134static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3135{
3136 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3137
3138 if (pll == NULL)
3139 return;
3140
3141 if (pll->refcount == 0) {
3142 WARN(1, "bad PCH PLL refcount\n");
3143 return;
3144 }
3145
3146 --pll->refcount;
3147 intel_crtc->pch_pll = NULL;
3148}
3149
3150static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3151{
3152 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3153 struct intel_pch_pll *pll;
3154 int i;
3155
3156 pll = intel_crtc->pch_pll;
3157 if (pll) {
3158 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3159 intel_crtc->base.base.id, pll->pll_reg);
3160 goto prepare;
3161 }
3162
98b6bd99
DV		 3163 if (HAS_PCH_IBX(dev_priv->dev)) {
3164 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3165 i = intel_crtc->pipe;
3166 pll = &dev_priv->pch_plls[i];
3167
3168 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3169 intel_crtc->base.base.id, pll->pll_reg);
3170
3171 goto found;
3172 }
3173
ee7b9f93
JB		 3174 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3175 pll = &dev_priv->pch_plls[i];
3176
3177 /* Only want to check enabled timings first */
3178 if (pll->refcount == 0)
3179 continue;
3180
3181 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3182 fp == I915_READ(pll->fp0_reg)) {
3183 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3184 intel_crtc->base.base.id,
3185 pll->pll_reg, pll->refcount, pll->active);
3186
3187 goto found;
3188 }
3189 }
3190
3191 /* Ok no matching timings, maybe there's a free one? */
3192 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3193 pll = &dev_priv->pch_plls[i];
3194 if (pll->refcount == 0) {
3195 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3196 intel_crtc->base.base.id, pll->pll_reg);
3197 goto found;
3198 }
3199 }
3200
3201 return NULL;
3202
3203found:
3204 intel_crtc->pch_pll = pll;
3205 pll->refcount++;
3206 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3207prepare: /* separate function? */
3208 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3209
e04c7350
CW		 3210 /* Wait for the clocks to stabilize before rewriting the regs */
3211 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3212 POSTING_READ(pll->pll_reg);
3213 udelay(150);
e04c7350
CW		 3214
3215 I915_WRITE(pll->fp0_reg, fp);
3216 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3217 pll->on = false;
3218 return pll;
3219}
3220
d4270e57
JB		 3221void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3222{
3223 struct drm_i915_private *dev_priv = dev->dev_private;
3224 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3225 u32 temp;
3226
3227 temp = I915_READ(dslreg);
3228 udelay(500);
3229 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3230 /* Without this, mode sets may fail silently on FDI */
3231 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3232 udelay(250);
3233 I915_WRITE(tc2reg, 0);
3234 if (wait_for(I915_READ(dslreg) != temp, 5))
3235 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3236 }
3237}
3238
f67a559d
JB		 3239static void ironlake_crtc_enable(struct drm_crtc *crtc)
3240{
3241 struct drm_device *dev = crtc->dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3244 struct intel_encoder *encoder;
f67a559d
JB		 3245 int pipe = intel_crtc->pipe;
3246 int plane = intel_crtc->plane;
3247 u32 temp;
3248 bool is_pch_port;
3249
08a48469
DV		 3250 WARN_ON(!crtc->enabled);
3251
f67a559d
JB		 3252 if (intel_crtc->active)
3253 return;
3254
3255 intel_crtc->active = true;
3256 intel_update_watermarks(dev);
3257
3258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3259 temp = I915_READ(PCH_LVDS);
3260 if ((temp & LVDS_PORT_EN) == 0)
3261 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3262 }
3263
fc316cbe 3264 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3265
46b6f814 3266 if (is_pch_port) {
fff367c7
DV		 3267 /* Note: FDI PLL enabling _must_ be done before we enable the
3268 * cpu pipes, hence this is separate from all the other fdi/pch
3269 * enabling. */
88cefb6c 3270 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3271 } else {
3272 assert_fdi_tx_disabled(dev_priv, pipe);
3273 assert_fdi_rx_disabled(dev_priv, pipe);
3274 }
f67a559d 3275
bf49ec8c
DV		 3276 for_each_encoder_on_crtc(dev, crtc, encoder)
3277 if (encoder->pre_enable)
3278 encoder->pre_enable(encoder);
3279
f67a559d
JB		 3280 /* Enable panel fitting for LVDS */
3281 if (dev_priv->pch_pf_size &&
3282 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3283 /* Force use of hard-coded filter coefficients
3284 * as some pre-programmed values are broken,
3285 * e.g. x201.
3286 */
9db4a9c7
JB		 3287 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3288 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3289 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3290 }
3291
9c54c0dd
JB		 3292 /*
3293 * On ILK+ LUT must be loaded before the pipe is running but with
3294 * clocks enabled
3295 */
3296 intel_crtc_load_lut(crtc);
3297
f67a559d
JB		 3298 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3299 intel_enable_plane(dev_priv, plane, pipe);
3300
3301 if (is_pch_port)
3302 ironlake_pch_enable(crtc);
c98e9dcf 3303
d1ebd816 3304 mutex_lock(&dev->struct_mutex);
bed4a673 3305 intel_update_fbc(dev);
d1ebd816
BW		 3306 mutex_unlock(&dev->struct_mutex);
3307
6b383a7f 3308 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3309
fa5c73b1
DV		 3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 encoder->enable(encoder);
61b77ddd
DV		 3312
3313 if (HAS_PCH_CPT(dev))
3314 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3315
3316 /*
3317 * There seems to be a race in PCH platform hw (at least on some
3318 * outputs) where an enabled pipe still completes any pageflip right
3319 * away (as if the pipe is off) instead of waiting for vblank. As soon
3320 * as the first vblank happend, everything works as expected. Hence just
3321 * wait for one vblank before returning to avoid strange things
3322 * happening.
3323 */
3324 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3325}
3326
4f771f10
PZ		 3327static void haswell_crtc_enable(struct drm_crtc *crtc)
3328{
3329 struct drm_device *dev = crtc->dev;
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332 struct intel_encoder *encoder;
3333 int pipe = intel_crtc->pipe;
3334 int plane = intel_crtc->plane;
4f771f10
PZ		 3335 bool is_pch_port;
3336
3337 WARN_ON(!crtc->enabled);
3338
3339 if (intel_crtc->active)
3340 return;
3341
3342 intel_crtc->active = true;
3343 intel_update_watermarks(dev);
3344
fc316cbe 3345 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3346
83616634 3347 if (is_pch_port)
4f771f10 3348 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3349
3350 for_each_encoder_on_crtc(dev, crtc, encoder)
3351 if (encoder->pre_enable)
3352 encoder->pre_enable(encoder);
3353
1f544388 3354 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3355
1f544388
PZ		 3356 /* Enable panel fitting for eDP */
3357 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3358 /* Force use of hard-coded filter coefficients
3359 * as some pre-programmed values are broken,
3360 * e.g. x201.
3361 */
3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3365 }
3366
3367 /*
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3369 * clocks enabled
3370 */
3371 intel_crtc_load_lut(crtc);
3372
1f544388
PZ		 3373 intel_ddi_set_pipe_settings(crtc);
3374 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3375
3376 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3377 intel_enable_plane(dev_priv, plane, pipe);
3378
3379 if (is_pch_port)
3380 ironlake_pch_enable(crtc);
3381
3382 mutex_lock(&dev->struct_mutex);
3383 intel_update_fbc(dev);
3384 mutex_unlock(&dev->struct_mutex);
3385
3386 intel_crtc_update_cursor(crtc, true);
3387
3388 for_each_encoder_on_crtc(dev, crtc, encoder)
3389 encoder->enable(encoder);
3390
4f771f10
PZ		 3391 /*
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3397 * happening.
3398 */
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
3400}
3401
6be4a607
JB		 3402static void ironlake_crtc_disable(struct drm_crtc *crtc)
3403{
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3407 struct intel_encoder *encoder;
6be4a607
JB		 3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
5eddb70b 3410 u32 reg, temp;
b52eb4dc 3411
ef9c3aee 3412
f7abfe8b
CW		 3413 if (!intel_crtc->active)
3414 return;
3415
ea9d758d
DV		 3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->disable(encoder);
3418
e6c3a2a6 3419 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3420 drm_vblank_off(dev, pipe);
6b383a7f 3421 intel_crtc_update_cursor(crtc, false);
5eddb70b 3422
b24e7179 3423 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3424
973d04f9
CW		 3425 if (dev_priv->cfb_plane == plane)
3426 intel_disable_fbc(dev);
2c07245f 3427
b24e7179 3428 intel_disable_pipe(dev_priv, pipe);
32f9d658 3429
6be4a607 3430 /* Disable PF */
9db4a9c7
JB		 3431 I915_WRITE(PF_CTL(pipe), 0);
3432 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3433
bf49ec8c
DV		 3434 for_each_encoder_on_crtc(dev, crtc, encoder)
3435 if (encoder->post_disable)
3436 encoder->post_disable(encoder);
3437
0fc932b8 3438 ironlake_fdi_disable(crtc);
2c07245f 3439
040484af 3440 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3441
6be4a607
JB		 3442 if (HAS_PCH_CPT(dev)) {
3443 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3444 reg = TRANS_DP_CTL(pipe);
3445 temp = I915_READ(reg);
3446 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3447 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3448 I915_WRITE(reg, temp);
6be4a607
JB		 3449
3450 /* disable DPLL_SEL */
3451 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3452 switch (pipe) {
3453 case 0:
d64311ab 3454 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3455 break;
3456 case 1:
6be4a607 3457 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3458 break;
3459 case 2:
4b645f14 3460 /* C shares PLL A or B */
d64311ab 3461 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3462 break;
3463 default:
3464 BUG(); /* wtf */
3465 }
6be4a607 3466 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3467 }
e3421a18 3468
6be4a607 3469 /* disable PCH DPLL */
ee7b9f93 3470 intel_disable_pch_pll(intel_crtc);
8db9d77b 3471
88cefb6c 3472 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3473
f7abfe8b 3474 intel_crtc->active = false;
6b383a7f 3475 intel_update_watermarks(dev);
d1ebd816
BW		 3476
3477 mutex_lock(&dev->struct_mutex);
6b383a7f 3478 intel_update_fbc(dev);
d1ebd816 3479 mutex_unlock(&dev->struct_mutex);
6be4a607 3480}
1b3c7a47 3481
4f771f10
PZ		 3482static void haswell_crtc_disable(struct drm_crtc *crtc)
3483{
3484 struct drm_device *dev = crtc->dev;
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3487 struct intel_encoder *encoder;
3488 int pipe = intel_crtc->pipe;
3489 int plane = intel_crtc->plane;
ad80a810 3490 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3491 bool is_pch_port;
4f771f10
PZ		 3492
3493 if (!intel_crtc->active)
3494 return;
3495
83616634
PZ		 3496 is_pch_port = haswell_crtc_driving_pch(crtc);
3497
4f771f10
PZ		 3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->disable(encoder);
3500
3501 intel_crtc_wait_for_pending_flips(crtc);
3502 drm_vblank_off(dev, pipe);
3503 intel_crtc_update_cursor(crtc, false);
3504
3505 intel_disable_plane(dev_priv, plane, pipe);
3506
3507 if (dev_priv->cfb_plane == plane)
3508 intel_disable_fbc(dev);
3509
3510 intel_disable_pipe(dev_priv, pipe);
3511
ad80a810 3512 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3513
3514 /* Disable PF */
3515 I915_WRITE(PF_CTL(pipe), 0);
3516 I915_WRITE(PF_WIN_SZ(pipe), 0);
3517
1f544388 3518 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3519
3520 for_each_encoder_on_crtc(dev, crtc, encoder)
3521 if (encoder->post_disable)
3522 encoder->post_disable(encoder);
3523
83616634
PZ		 3524 if (is_pch_port) {
3525 ironlake_fdi_disable(crtc);
3526 intel_disable_transcoder(dev_priv, pipe);
3527 intel_disable_pch_pll(intel_crtc);
3528 ironlake_fdi_pll_disable(intel_crtc);
3529 }
4f771f10
PZ		 3530
3531 intel_crtc->active = false;
3532 intel_update_watermarks(dev);
3533
3534 mutex_lock(&dev->struct_mutex);
3535 intel_update_fbc(dev);
3536 mutex_unlock(&dev->struct_mutex);
3537}
3538
ee7b9f93
JB		 3539static void ironlake_crtc_off(struct drm_crtc *crtc)
3540{
3541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3542 intel_put_pch_pll(intel_crtc);
3543}
3544
6441ab5f
PZ		 3545static void haswell_crtc_off(struct drm_crtc *crtc)
3546{
a5c961d1
PZ		 3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548
3549 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3550 * start using it. */
3551 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3552
6441ab5f
PZ		 3553 intel_ddi_put_crtc_pll(crtc);
3554}
3555
02e792fb
DV		 3556static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3557{
02e792fb 3558 if (!enable && intel_crtc->overlay) {
23f09ce3 3559 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3560 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3561
23f09ce3 3562 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3563 dev_priv->mm.interruptible = false;
3564 (void) intel_overlay_switch_off(intel_crtc->overlay);
3565 dev_priv->mm.interruptible = true;
23f09ce3 3566 mutex_unlock(&dev->struct_mutex);
02e792fb 3567 }
02e792fb 3568
5dcdbcb0
CW		 3569 /* Let userspace switch the overlay on again. In most cases userspace
3570 * has to recompute where to put it anyway.
3571 */
02e792fb
DV		 3572}
3573
0b8765c6 3574static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3575{
3576 struct drm_device *dev = crtc->dev;
79e53945
JB		 3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3579 struct intel_encoder *encoder;
79e53945 3580 int pipe = intel_crtc->pipe;
80824003 3581 int plane = intel_crtc->plane;
79e53945 3582
08a48469
DV		 3583 WARN_ON(!crtc->enabled);
3584
f7abfe8b
CW		 3585 if (intel_crtc->active)
3586 return;
3587
3588 intel_crtc->active = true;
6b383a7f
CW		 3589 intel_update_watermarks(dev);
3590
63d7bbe9 3591 intel_enable_pll(dev_priv, pipe);
040484af 3592 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3593 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3594
0b8765c6 3595 intel_crtc_load_lut(crtc);
bed4a673 3596 intel_update_fbc(dev);
79e53945 3597
0b8765c6
JB		 3598 /* Give the overlay scaler a chance to enable if it's on this pipe */
3599 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3600 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3601
fa5c73b1
DV		 3602 for_each_encoder_on_crtc(dev, crtc, encoder)
3603 encoder->enable(encoder);
0b8765c6 3604}
79e53945 3605
0b8765c6
JB		 3606static void i9xx_crtc_disable(struct drm_crtc *crtc)
3607{
3608 struct drm_device *dev = crtc->dev;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3611 struct intel_encoder *encoder;
0b8765c6
JB		 3612 int pipe = intel_crtc->pipe;
3613 int plane = intel_crtc->plane;
b690e96c 3614
ef9c3aee 3615
f7abfe8b
CW		 3616 if (!intel_crtc->active)
3617 return;
3618
ea9d758d
DV		 3619 for_each_encoder_on_crtc(dev, crtc, encoder)
3620 encoder->disable(encoder);
3621
0b8765c6 3622 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3623 intel_crtc_wait_for_pending_flips(crtc);
3624 drm_vblank_off(dev, pipe);
0b8765c6 3625 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3626 intel_crtc_update_cursor(crtc, false);
0b8765c6 3627
973d04f9
CW		 3628 if (dev_priv->cfb_plane == plane)
3629 intel_disable_fbc(dev);
79e53945 3630
b24e7179 3631 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3632 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3633 intel_disable_pll(dev_priv, pipe);
0b8765c6 3634
f7abfe8b 3635 intel_crtc->active = false;
6b383a7f
CW		 3636 intel_update_fbc(dev);
3637 intel_update_watermarks(dev);
0b8765c6
JB		 3638}
3639
ee7b9f93
JB		 3640static void i9xx_crtc_off(struct drm_crtc *crtc)
3641{
3642}
3643
976f8a20
DV		 3644static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3645 bool enabled)
2c07245f
ZW		 3646{
3647 struct drm_device *dev = crtc->dev;
3648 struct drm_i915_master_private *master_priv;
3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650 int pipe = intel_crtc->pipe;
79e53945
JB		 3651
3652 if (!dev->primary->master)
3653 return;
3654
3655 master_priv = dev->primary->master->driver_priv;
3656 if (!master_priv->sarea_priv)
3657 return;
3658
79e53945
JB		 3659 switch (pipe) {
3660 case 0:
3661 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3662 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3663 break;
3664 case 1:
3665 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3666 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3667 break;
3668 default:
9db4a9c7 3669 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3670 break;
3671 }
79e53945
JB		 3672}
3673
976f8a20
DV		 3674/**
3675 * Sets the power management mode of the pipe and plane.
3676 */
3677void intel_crtc_update_dpms(struct drm_crtc *crtc)
3678{
3679 struct drm_device *dev = crtc->dev;
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 struct intel_encoder *intel_encoder;
3682 bool enable = false;
3683
3684 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3685 enable |= intel_encoder->connectors_active;
3686
3687 if (enable)
3688 dev_priv->display.crtc_enable(crtc);
3689 else
3690 dev_priv->display.crtc_disable(crtc);
3691
3692 intel_crtc_update_sarea(crtc, enable);
3693}
3694
3695static void intel_crtc_noop(struct drm_crtc *crtc)
3696{
3697}
3698
cdd59983
CW		 3699static void intel_crtc_disable(struct drm_crtc *crtc)
3700{
cdd59983 3701 struct drm_device *dev = crtc->dev;
976f8a20 3702 struct drm_connector *connector;
ee7b9f93 3703 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3704
976f8a20
DV		 3705 /* crtc should still be enabled when we disable it. */
3706 WARN_ON(!crtc->enabled);
3707
3708 dev_priv->display.crtc_disable(crtc);
3709 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3710 dev_priv->display.off(crtc);
3711
931872fc
CW		 3712 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3713 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3714
3715 if (crtc->fb) {
3716 mutex_lock(&dev->struct_mutex);
1690e1eb 3717 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3718 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3719 crtc->fb = NULL;
3720 }
3721
3722 /* Update computed state. */
3723 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3724 if (!connector->encoder || !connector->encoder->crtc)
3725 continue;
3726
3727 if (connector->encoder->crtc != crtc)
3728 continue;
3729
3730 connector->dpms = DRM_MODE_DPMS_OFF;
3731 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3732 }
3733}
3734
a261b246 3735void intel_modeset_disable(struct drm_device *dev)
79e53945 3736{
a261b246
DV		 3737 struct drm_crtc *crtc;
3738
3739 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3740 if (crtc->enabled)
3741 intel_crtc_disable(crtc);
3742 }
79e53945
JB		 3743}
3744
1f703855 3745void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3746{
7e7d76c3
JB		 3747}
3748
ea5b213a 3749void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3750{
4ef69c7a 3751 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3752
ea5b213a
CW		 3753 drm_encoder_cleanup(encoder);
3754 kfree(intel_encoder);
7e7d76c3
JB		 3755}
3756
5ab432ef
DV		 3757/* Simple dpms helper for encodres with just one connector, no cloning and only
3758 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3759 * state of the entire output pipe. */
3760void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3761{
5ab432ef
DV		 3762 if (mode == DRM_MODE_DPMS_ON) {
3763 encoder->connectors_active = true;
3764
b2cabb0e 3765 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3766 } else {
3767 encoder->connectors_active = false;
3768
b2cabb0e 3769 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3770 }
79e53945
JB		 3771}
3772
0a91ca29
DV		 3773/* Cross check the actual hw state with our own modeset state tracking (and it's
3774 * internal consistency). */
b980514c 3775static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3776{
0a91ca29
DV		 3777 if (connector->get_hw_state(connector)) {
3778 struct intel_encoder *encoder = connector->encoder;
3779 struct drm_crtc *crtc;
3780 bool encoder_enabled;
3781 enum pipe pipe;
3782
3783 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3784 connector->base.base.id,
3785 drm_get_connector_name(&connector->base));
3786
3787 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3788 "wrong connector dpms state\n");
3789 WARN(connector->base.encoder != &encoder->base,
3790 "active connector not linked to encoder\n");
3791 WARN(!encoder->connectors_active,
3792 "encoder->connectors_active not set\n");
3793
3794 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3795 WARN(!encoder_enabled, "encoder not enabled\n");
3796 if (WARN_ON(!encoder->base.crtc))
3797 return;
3798
3799 crtc = encoder->base.crtc;
3800
3801 WARN(!crtc->enabled, "crtc not enabled\n");
3802 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3803 WARN(pipe != to_intel_crtc(crtc)->pipe,
3804 "encoder active on the wrong pipe\n");
3805 }
79e53945
JB		 3806}
3807
5ab432ef
DV		 3808/* Even simpler default implementation, if there's really no special case to
3809 * consider. */
3810void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3811{
5ab432ef 3812 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3813
5ab432ef
DV		 3814 /* All the simple cases only support two dpms states. */
3815 if (mode != DRM_MODE_DPMS_ON)
3816 mode = DRM_MODE_DPMS_OFF;
d4270e57 3817
5ab432ef
DV		 3818 if (mode == connector->dpms)
3819 return;
3820
3821 connector->dpms = mode;
3822
3823 /* Only need to change hw state when actually enabled */
3824 if (encoder->base.crtc)
3825 intel_encoder_dpms(encoder, mode);
3826 else
8af6cf88 3827 WARN_ON(encoder->connectors_active != false);
0a91ca29 3828
b980514c 3829 intel_modeset_check_state(connector->dev);
79e53945
JB		 3830}
3831
f0947c37
DV		 3832/* Simple connector->get_hw_state implementation for encoders that support only
3833 * one connector and no cloning and hence the encoder state determines the state
3834 * of the connector. */
3835bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3836{
24929352 3837 enum pipe pipe = 0;
f0947c37 3838 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3839
f0947c37 3840 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3841}
3842
79e53945 3843static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3844 const struct drm_display_mode *mode,
79e53945
JB		 3845 struct drm_display_mode *adjusted_mode)
3846{
2c07245f 3847 struct drm_device *dev = crtc->dev;
89749350 3848
bad720ff 3849 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3850 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3851 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3852 return false;
2c07245f 3853 }
89749350 3854
f9bef081
DV		 3855 /* All interlaced capable intel hw wants timings in frames. Note though
3856 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3857 * timings, so we need to be careful not to clobber these.*/
3858 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3859 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3860
44f46b42
CW		 3861 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3862 * with a hsync front porch of 0.
3863 */
3864 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3865 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3866 return false;
3867
79e53945
JB		 3868 return true;
3869}
3870
25eb05fc
JB		 3871static int valleyview_get_display_clock_speed(struct drm_device *dev)
3872{
3873 return 400000; /* FIXME */
3874}
3875
e70236a8
JB		 3876static int i945_get_display_clock_speed(struct drm_device *dev)
3877{
3878 return 400000;
3879}
79e53945 3880
e70236a8 3881static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3882{
e70236a8
JB		 3883 return 333000;
3884}
79e53945 3885
e70236a8
JB		 3886static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3887{
3888 return 200000;
3889}
79e53945 3890
e70236a8
JB		 3891static int i915gm_get_display_clock_speed(struct drm_device *dev)
3892{
3893 u16 gcfgc = 0;
79e53945 3894
e70236a8
JB		 3895 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3896
3897 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3898 return 133000;
3899 else {
3900 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3901 case GC_DISPLAY_CLOCK_333_MHZ:
3902 return 333000;
3903 default:
3904 case GC_DISPLAY_CLOCK_190_200_MHZ:
3905 return 190000;
79e53945 3906 }
e70236a8
JB		 3907 }
3908}
3909
3910static int i865_get_display_clock_speed(struct drm_device *dev)
3911{
3912 return 266000;
3913}
3914
3915static int i855_get_display_clock_speed(struct drm_device *dev)
3916{
3917 u16 hpllcc = 0;
3918 /* Assume that the hardware is in the high speed state. This
3919 * should be the default.
3920 */
3921 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3922 case GC_CLOCK_133_200:
3923 case GC_CLOCK_100_200:
3924 return 200000;
3925 case GC_CLOCK_166_250:
3926 return 250000;
3927 case GC_CLOCK_100_133:
79e53945 3928 return 133000;
e70236a8 3929 }
79e53945 3930
e70236a8
JB		 3931 /* Shouldn't happen */
3932 return 0;
3933}
79e53945 3934
e70236a8
JB		 3935static int i830_get_display_clock_speed(struct drm_device *dev)
3936{
3937 return 133000;
79e53945
JB		 3938}
3939
2c07245f
ZW		 3940struct fdi_m_n {
3941 u32 tu;
3942 u32 gmch_m;
3943 u32 gmch_n;
3944 u32 link_m;
3945 u32 link_n;
3946};
3947
3948static void
3949fdi_reduce_ratio(u32 *num, u32 *den)
3950{
3951 while (*num > 0xffffff || *den > 0xffffff) {
3952 *num >>= 1;
3953 *den >>= 1;
3954 }
3955}
3956
2c07245f 3957static void
f2b115e6
AJ		 3958ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3959 int link_clock, struct fdi_m_n *m_n)
2c07245f 3960{
2c07245f
ZW		 3961 m_n->tu = 64; /* default size */
3962
22ed1113
CW		 3963 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3964 m_n->gmch_m = bits_per_pixel * pixel_clock;
3965 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3966 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3967
22ed1113
CW		 3968 m_n->link_m = pixel_clock;
3969 m_n->link_n = link_clock;
2c07245f
ZW		 3970 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3971}
3972
a7615030
CW		 3973static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3974{
72bbe58c
KP		 3975 if (i915_panel_use_ssc >= 0)
3976 return i915_panel_use_ssc != 0;
3977 return dev_priv->lvds_use_ssc
435793df 3978 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3979}
3980
5a354204
JB		 3981/**
3982 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3983 * @crtc: CRTC structure
3b5c78a3 3984 * @mode: requested mode
5a354204
JB		 3985 *
3986 * A pipe may be connected to one or more outputs. Based on the depth of the
3987 * attached framebuffer, choose a good color depth to use on the pipe.
3988 *
3989 * If possible, match the pipe depth to the fb depth. In some cases, this
3990 * isn't ideal, because the connected output supports a lesser or restricted
3991 * set of depths. Resolve that here:
3992 * LVDS typically supports only 6bpc, so clamp down in that case
3993 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3994 * Displays may support a restricted set as well, check EDID and clamp as
3995 * appropriate.
3b5c78a3 3996 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3997 *
3998 * RETURNS:
3999 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4000 * true if they don't match).
4001 */
4002static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4003 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4004 unsigned int *pipe_bpp,
4005 struct drm_display_mode *mode)
5a354204
JB		 4006{
4007 struct drm_device *dev = crtc->dev;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4009 struct drm_connector *connector;
6c2b7c12 4010 struct intel_encoder *intel_encoder;
5a354204
JB		 4011 unsigned int display_bpc = UINT_MAX, bpc;
4012
4013 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4014 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4015
4016 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4017 unsigned int lvds_bpc;
4018
4019 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4020 LVDS_A3_POWER_UP)
4021 lvds_bpc = 8;
4022 else
4023 lvds_bpc = 6;
4024
4025 if (lvds_bpc < display_bpc) {
82820490 4026 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4027 display_bpc = lvds_bpc;
4028 }
4029 continue;
4030 }
4031
5a354204
JB		 4032 /* Not one of the known troublemakers, check the EDID */
4033 list_for_each_entry(connector, &dev->mode_config.connector_list,
4034 head) {
6c2b7c12 4035 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4036 continue;
4037
62ac41a6
JB		 4038 /* Don't use an invalid EDID bpc value */
4039 if (connector->display_info.bpc &&
4040 connector->display_info.bpc < display_bpc) {
82820490 4041 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4042 display_bpc = connector->display_info.bpc;
4043 }
4044 }
4045
4046 /*
4047 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4048 * through, clamp it down. (Note: >12bpc will be caught below.)
4049 */
4050 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4051 if (display_bpc > 8 && display_bpc < 12) {
82820490 4052 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4053 display_bpc = 12;
4054 } else {
82820490 4055 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4056 display_bpc = 8;
4057 }
4058 }
4059 }
4060
3b5c78a3
AJ		 4061 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4062 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4063 display_bpc = 6;
4064 }
4065
5a354204
JB		 4066 /*
4067 * We could just drive the pipe at the highest bpc all the time and
4068 * enable dithering as needed, but that costs bandwidth. So choose
4069 * the minimum value that expresses the full color range of the fb but
4070 * also stays within the max display bpc discovered above.
4071 */
4072
94352cf9 4073 switch (fb->depth) {
5a354204
JB		 4074 case 8:
4075 bpc = 8; /* since we go through a colormap */
4076 break;
4077 case 15:
4078 case 16:
4079 bpc = 6; /* min is 18bpp */
4080 break;
4081 case 24:
578393cd 4082 bpc = 8;
5a354204
JB		 4083 break;
4084 case 30:
578393cd 4085 bpc = 10;
5a354204
JB		 4086 break;
4087 case 48:
578393cd 4088 bpc = 12;
5a354204
JB		 4089 break;
4090 default:
4091 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4092 bpc = min((unsigned int)8, display_bpc);
4093 break;
4094 }
4095
578393cd
KP		 4096 display_bpc = min(display_bpc, bpc);
4097
82820490
AJ		 4098 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4099 bpc, display_bpc);
5a354204 4100
578393cd 4101 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4102
4103 return display_bpc != bpc;
4104}
4105
a0c4da24
JB		 4106static int vlv_get_refclk(struct drm_crtc *crtc)
4107{
4108 struct drm_device *dev = crtc->dev;
4109 struct drm_i915_private *dev_priv = dev->dev_private;
4110 int refclk = 27000; /* for DP & HDMI */
4111
4112 return 100000; /* only one validated so far */
4113
4114 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4115 refclk = 96000;
4116 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4117 if (intel_panel_use_ssc(dev_priv))
4118 refclk = 100000;
4119 else
4120 refclk = 96000;
4121 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4122 refclk = 100000;
4123 }
4124
4125 return refclk;
4126}
4127
c65d77d8
JB		 4128static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4129{
4130 struct drm_device *dev = crtc->dev;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 int refclk;
4133
a0c4da24
JB		 4134 if (IS_VALLEYVIEW(dev)) {
4135 refclk = vlv_get_refclk(crtc);
4136 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4137 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4138 refclk = dev_priv->lvds_ssc_freq * 1000;
4139 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4140 refclk / 1000);
4141 } else if (!IS_GEN2(dev)) {
4142 refclk = 96000;
4143 } else {
4144 refclk = 48000;
4145 }
4146
4147 return refclk;
4148}
4149
4150static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4151 intel_clock_t *clock)
4152{
4153 /* SDVO TV has fixed PLL values depend on its clock range,
4154 this mirrors vbios setting. */
4155 if (adjusted_mode->clock >= 100000
4156 && adjusted_mode->clock < 140500) {
4157 clock->p1 = 2;
4158 clock->p2 = 10;
4159 clock->n = 3;
4160 clock->m1 = 16;
4161 clock->m2 = 8;
4162 } else if (adjusted_mode->clock >= 140500
4163 && adjusted_mode->clock <= 200000) {
4164 clock->p1 = 1;
4165 clock->p2 = 10;
4166 clock->n = 6;
4167 clock->m1 = 12;
4168 clock->m2 = 8;
4169 }
4170}
4171
a7516a05
JB		 4172static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4173 intel_clock_t *clock,
4174 intel_clock_t *reduced_clock)
4175{
4176 struct drm_device *dev = crtc->dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179 int pipe = intel_crtc->pipe;
4180 u32 fp, fp2 = 0;
4181
4182 if (IS_PINEVIEW(dev)) {
4183 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4184 if (reduced_clock)
4185 fp2 = (1 << reduced_clock->n) << 16 |
4186 reduced_clock->m1 << 8 | reduced_clock->m2;
4187 } else {
4188 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4189 if (reduced_clock)
4190 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4191 reduced_clock->m2;
4192 }
4193
4194 I915_WRITE(FP0(pipe), fp);
4195
4196 intel_crtc->lowfreq_avail = false;
4197 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4198 reduced_clock && i915_powersave) {
4199 I915_WRITE(FP1(pipe), fp2);
4200 intel_crtc->lowfreq_avail = true;
4201 } else {
4202 I915_WRITE(FP1(pipe), fp);
4203 }
4204}
4205
93e537a1
DV		 4206static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4207 struct drm_display_mode *adjusted_mode)
4208{
4209 struct drm_device *dev = crtc->dev;
4210 struct drm_i915_private *dev_priv = dev->dev_private;
4211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4212 int pipe = intel_crtc->pipe;
284d5df5 4213 u32 temp;
93e537a1
DV		 4214
4215 temp = I915_READ(LVDS);
4216 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4217 if (pipe == 1) {
4218 temp |= LVDS_PIPEB_SELECT;
4219 } else {
4220 temp &= ~LVDS_PIPEB_SELECT;
4221 }
4222 /* set the corresponsding LVDS_BORDER bit */
4223 temp |= dev_priv->lvds_border_bits;
4224 /* Set the B0-B3 data pairs corresponding to whether we're going to
4225 * set the DPLLs for dual-channel mode or not.
4226 */
4227 if (clock->p2 == 7)
4228 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4229 else
4230 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4231
4232 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4233 * appropriately here, but we need to look more thoroughly into how
4234 * panels behave in the two modes.
4235 */
4236 /* set the dithering flag on LVDS as needed */
4237 if (INTEL_INFO(dev)->gen >= 4) {
4238 if (dev_priv->lvds_dither)
4239 temp |= LVDS_ENABLE_DITHER;
4240 else
4241 temp &= ~LVDS_ENABLE_DITHER;
4242 }
284d5df5 4243 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4244 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4245 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4246 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4247 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4248 I915_WRITE(LVDS, temp);
4249}
4250
a0c4da24
JB		 4251static void vlv_update_pll(struct drm_crtc *crtc,
4252 struct drm_display_mode *mode,
4253 struct drm_display_mode *adjusted_mode,
4254 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4255 int num_connectors)
a0c4da24
JB		 4256{
4257 struct drm_device *dev = crtc->dev;
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260 int pipe = intel_crtc->pipe;
4261 u32 dpll, mdiv, pdiv;
4262 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4263 bool is_sdvo;
4264 u32 temp;
4265
4266 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4267 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4268
2a8f64ca
VP		 4269 dpll = DPLL_VGA_MODE_DIS;
4270 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4271 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4272 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4273
4274 I915_WRITE(DPLL(pipe), dpll);
4275 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4276
4277 bestn = clock->n;
4278 bestm1 = clock->m1;
4279 bestm2 = clock->m2;
4280 bestp1 = clock->p1;
4281 bestp2 = clock->p2;
4282
2a8f64ca
VP		 4283 /*
4284 * In Valleyview PLL and program lane counter registers are exposed
4285 * through DPIO interface
4286 */
a0c4da24
JB		 4287 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4288 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4289 mdiv |= ((bestn << DPIO_N_SHIFT));
4290 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4291 mdiv |= (1 << DPIO_K_SHIFT);
4292 mdiv |= DPIO_ENABLE_CALIBRATION;
4293 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4294
4295 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4296
2a8f64ca 4297 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4298 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4299 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4300 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4301 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4302
2a8f64ca 4303 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4304
4305 dpll |= DPLL_VCO_ENABLE;
4306 I915_WRITE(DPLL(pipe), dpll);
4307 POSTING_READ(DPLL(pipe));
4308 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4309 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4310
2a8f64ca
VP		 4311 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4312
4313 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4314 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4315
4316 I915_WRITE(DPLL(pipe), dpll);
4317
4318 /* Wait for the clocks to stabilize. */
4319 POSTING_READ(DPLL(pipe));
4320 udelay(150);
a0c4da24 4321
2a8f64ca
VP		 4322 temp = 0;
4323 if (is_sdvo) {
4324 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4325 if (temp > 1)
4326 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4327 else
4328 temp = 0;
a0c4da24 4329 }
2a8f64ca
VP		 4330 I915_WRITE(DPLL_MD(pipe), temp);
4331 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4332
2a8f64ca
VP		 4333 /* Now program lane control registers */
4334 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4335 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4336 {
4337 temp = 0x1000C4;
4338 if(pipe == 1)
4339 temp |= (1 << 21);
4340 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4341 }
4342 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4343 {
4344 temp = 0x1000C4;
4345 if(pipe == 1)
4346 temp |= (1 << 21);
4347 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4348 }
a0c4da24
JB		 4349}
4350
eb1cbe48
DV		 4351static void i9xx_update_pll(struct drm_crtc *crtc,
4352 struct drm_display_mode *mode,
4353 struct drm_display_mode *adjusted_mode,
4354 intel_clock_t *clock, intel_clock_t *reduced_clock,
4355 int num_connectors)
4356{
4357 struct drm_device *dev = crtc->dev;
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4360 int pipe = intel_crtc->pipe;
4361 u32 dpll;
4362 bool is_sdvo;
4363
2a8f64ca
VP		 4364 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4365
eb1cbe48
DV		 4366 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4367 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4368
4369 dpll = DPLL_VGA_MODE_DIS;
4370
4371 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4372 dpll |= DPLLB_MODE_LVDS;
4373 else
4374 dpll |= DPLLB_MODE_DAC_SERIAL;
4375 if (is_sdvo) {
4376 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4377 if (pixel_multiplier > 1) {
4378 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4379 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4380 }
4381 dpll |= DPLL_DVO_HIGH_SPEED;
4382 }
4383 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4384 dpll |= DPLL_DVO_HIGH_SPEED;
4385
4386 /* compute bitmask from p1 value */
4387 if (IS_PINEVIEW(dev))
4388 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4389 else {
4390 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4391 if (IS_G4X(dev) && reduced_clock)
4392 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4393 }
4394 switch (clock->p2) {
4395 case 5:
4396 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4397 break;
4398 case 7:
4399 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4400 break;
4401 case 10:
4402 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4403 break;
4404 case 14:
4405 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4406 break;
4407 }
4408 if (INTEL_INFO(dev)->gen >= 4)
4409 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4410
4411 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4412 dpll |= PLL_REF_INPUT_TVCLKINBC;
4413 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4414 /* XXX: just matching BIOS for now */
4415 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4416 dpll |= 3;
4417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4418 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4419 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4420 else
4421 dpll |= PLL_REF_INPUT_DREFCLK;
4422
4423 dpll |= DPLL_VCO_ENABLE;
4424 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4425 POSTING_READ(DPLL(pipe));
4426 udelay(150);
4427
4428 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4429 * This is an exception to the general rule that mode_set doesn't turn
4430 * things on.
4431 */
4432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4433 intel_update_lvds(crtc, clock, adjusted_mode);
4434
4435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4436 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4437
4438 I915_WRITE(DPLL(pipe), dpll);
4439
4440 /* Wait for the clocks to stabilize. */
4441 POSTING_READ(DPLL(pipe));
4442 udelay(150);
4443
4444 if (INTEL_INFO(dev)->gen >= 4) {
4445 u32 temp = 0;
4446 if (is_sdvo) {
4447 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4448 if (temp > 1)
4449 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4450 else
4451 temp = 0;
4452 }
4453 I915_WRITE(DPLL_MD(pipe), temp);
4454 } else {
4455 /* The pixel multiplier can only be updated once the
4456 * DPLL is enabled and the clocks are stable.
4457 *
4458 * So write it again.
4459 */
4460 I915_WRITE(DPLL(pipe), dpll);
4461 }
4462}
4463
4464static void i8xx_update_pll(struct drm_crtc *crtc,
4465 struct drm_display_mode *adjusted_mode,
2a8f64ca 4466 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4467 int num_connectors)
4468{
4469 struct drm_device *dev = crtc->dev;
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4472 int pipe = intel_crtc->pipe;
4473 u32 dpll;
4474
2a8f64ca
VP		 4475 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4476
eb1cbe48
DV		 4477 dpll = DPLL_VGA_MODE_DIS;
4478
4479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4480 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4481 } else {
4482 if (clock->p1 == 2)
4483 dpll |= PLL_P1_DIVIDE_BY_TWO;
4484 else
4485 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4486 if (clock->p2 == 4)
4487 dpll |= PLL_P2_DIVIDE_BY_4;
4488 }
4489
4490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4491 /* XXX: just matching BIOS for now */
4492 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4493 dpll |= 3;
4494 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4495 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4496 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4497 else
4498 dpll |= PLL_REF_INPUT_DREFCLK;
4499
4500 dpll |= DPLL_VCO_ENABLE;
4501 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4502 POSTING_READ(DPLL(pipe));
4503 udelay(150);
4504
eb1cbe48
DV		 4505 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4506 * This is an exception to the general rule that mode_set doesn't turn
4507 * things on.
4508 */
4509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4510 intel_update_lvds(crtc, clock, adjusted_mode);
4511
5b5896e4
DV		 4512 I915_WRITE(DPLL(pipe), dpll);
4513
4514 /* Wait for the clocks to stabilize. */
4515 POSTING_READ(DPLL(pipe));
4516 udelay(150);
4517
eb1cbe48
DV		 4518 /* The pixel multiplier can only be updated once the
4519 * DPLL is enabled and the clocks are stable.
4520 *
4521 * So write it again.
4522 */
4523 I915_WRITE(DPLL(pipe), dpll);
4524}
4525
b0e77b9c
PZ		 4526static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4527 struct drm_display_mode *mode,
4528 struct drm_display_mode *adjusted_mode)
4529{
4530 struct drm_device *dev = intel_crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4533 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4534 uint32_t vsyncshift;
4535
4536 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4537 /* the chip adds 2 halflines automatically */
4538 adjusted_mode->crtc_vtotal -= 1;
4539 adjusted_mode->crtc_vblank_end -= 1;
4540 vsyncshift = adjusted_mode->crtc_hsync_start
4541 - adjusted_mode->crtc_htotal / 2;
4542 } else {
4543 vsyncshift = 0;
4544 }
4545
4546 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4547 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4548
fe2b8f9d 4549 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4550 (adjusted_mode->crtc_hdisplay - 1) |
4551 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4552 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4553 (adjusted_mode->crtc_hblank_start - 1) |
4554 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4555 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4556 (adjusted_mode->crtc_hsync_start - 1) |
4557 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4558
fe2b8f9d 4559 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4560 (adjusted_mode->crtc_vdisplay - 1) |
4561 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4562 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4563 (adjusted_mode->crtc_vblank_start - 1) |
4564 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4565 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4566 (adjusted_mode->crtc_vsync_start - 1) |
4567 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4568
b5e508d4
PZ		 4569 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4570 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4571 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4572 * bits. */
4573 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4574 (pipe == PIPE_B || pipe == PIPE_C))
4575 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4576
b0e77b9c
PZ		 4577 /* pipesrc controls the size that is scaled from, which should
4578 * always be the user's requested size.
4579 */
4580 I915_WRITE(PIPESRC(pipe),
4581 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4582}
4583
f564048e
EA		 4584static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4585 struct drm_display_mode *mode,
4586 struct drm_display_mode *adjusted_mode,
4587 int x, int y,
94352cf9 4588 struct drm_framebuffer *fb)
79e53945
JB		 4589{
4590 struct drm_device *dev = crtc->dev;
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593 int pipe = intel_crtc->pipe;
80824003 4594 int plane = intel_crtc->plane;
c751ce4f 4595 int refclk, num_connectors = 0;
652c393a 4596 intel_clock_t clock, reduced_clock;
b0e77b9c 4597 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4598 bool ok, has_reduced_clock = false, is_sdvo = false;
4599 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4600 struct intel_encoder *encoder;
d4906093 4601 const intel_limit_t *limit;
5c3b82e2 4602 int ret;
79e53945 4603
6c2b7c12 4604 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4605 switch (encoder->type) {
79e53945
JB		 4606 case INTEL_OUTPUT_LVDS:
4607 is_lvds = true;
4608 break;
4609 case INTEL_OUTPUT_SDVO:
7d57382e 4610 case INTEL_OUTPUT_HDMI:
79e53945 4611 is_sdvo = true;
5eddb70b 4612 if (encoder->needs_tv_clock)
e2f0ba97 4613 is_tv = true;
79e53945 4614 break;
79e53945
JB		 4615 case INTEL_OUTPUT_TVOUT:
4616 is_tv = true;
4617 break;
a4fc5ed6
KP		 4618 case INTEL_OUTPUT_DISPLAYPORT:
4619 is_dp = true;
4620 break;
79e53945 4621 }
43565a06 4622
c751ce4f 4623 num_connectors++;
79e53945
JB		 4624 }
4625
c65d77d8 4626 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4627
d4906093
ML		 4628 /*
4629 * Returns a set of divisors for the desired target clock with the given
4630 * refclk, or FALSE. The returned values represent the clock equation:
4631 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4632 */
1b894b59 4633 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4634 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4635 &clock);
79e53945
JB		 4636 if (!ok) {
4637 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4638 return -EINVAL;
79e53945
JB		 4639 }
4640
cda4b7d3 4641 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4642 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4643
ddc9003c 4644 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4645 /*
4646 * Ensure we match the reduced clock's P to the target clock.
4647 * If the clocks don't match, we can't switch the display clock
4648 * by using the FP0/FP1. In such case we will disable the LVDS
4649 * downclock feature.
4650 */
ddc9003c 4651 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4652 dev_priv->lvds_downclock,
4653 refclk,
cec2f356 4654 &clock,
5eddb70b 4655 &reduced_clock);
7026d4ac
ZW		 4656 }
4657
c65d77d8
JB		 4658 if (is_sdvo && is_tv)
4659 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4660
eb1cbe48 4661 if (IS_GEN2(dev))
2a8f64ca
VP		 4662 i8xx_update_pll(crtc, adjusted_mode, &clock,
4663 has_reduced_clock ? &reduced_clock : NULL,
4664 num_connectors);
a0c4da24 4665 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4666 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4667 has_reduced_clock ? &reduced_clock : NULL,
4668 num_connectors);
79e53945 4669 else
eb1cbe48
DV		 4670 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4671 has_reduced_clock ? &reduced_clock : NULL,
4672 num_connectors);
79e53945
JB		 4673
4674 /* setup pipeconf */
5eddb70b 4675 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4676
4677 /* Set up the display plane register */
4678 dspcntr = DISPPLANE_GAMMA_ENABLE;
4679
929c77fb
EA		 4680 if (pipe == 0)
4681 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4682 else
4683 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4684
a6c45cf0 4685 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4686 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4687 * core speed.
4688 *
4689 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4690 * pipe == 0 check?
4691 */
e70236a8
JB		 4692 if (mode->clock >
4693 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4694 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4695 else
5eddb70b 4696 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4697 }
4698
3b5c78a3
AJ		 4699 /* default to 8bpc */
4700 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4701 if (is_dp) {
0c96c65b 4702 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4703 pipeconf |= PIPECONF_BPP_6 |
4704 PIPECONF_DITHER_EN |
4705 PIPECONF_DITHER_TYPE_SP;
4706 }
4707 }
4708
19c03924
GB		 4709 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4710 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4711 pipeconf |= PIPECONF_BPP_6 |
4712 PIPECONF_ENABLE |
4713 I965_PIPECONF_ACTIVE;
4714 }
4715 }
4716
28c97730 4717 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4718 drm_mode_debug_printmodeline(mode);
4719
a7516a05
JB		 4720 if (HAS_PIPE_CXSR(dev)) {
4721 if (intel_crtc->lowfreq_avail) {
28c97730 4722 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4723 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4724 } else {
28c97730 4725 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4726 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4727 }
4728 }
4729
617cf884 4730 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4731 if (!IS_GEN2(dev) &&
b0e77b9c 4732 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4733 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4734 else
617cf884 4735 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4736
b0e77b9c 4737 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4738
4739 /* pipesrc and dspsize control the size that is scaled from,
4740 * which should always be the user's requested size.
79e53945 4741 */
929c77fb
EA		 4742 I915_WRITE(DSPSIZE(plane),
4743 ((mode->vdisplay - 1) << 16) |
4744 (mode->hdisplay - 1));
4745 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4746
f564048e
EA		 4747 I915_WRITE(PIPECONF(pipe), pipeconf);
4748 POSTING_READ(PIPECONF(pipe));
929c77fb 4749 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4750
4751 intel_wait_for_vblank(dev, pipe);
4752
f564048e
EA		 4753 I915_WRITE(DSPCNTR(plane), dspcntr);
4754 POSTING_READ(DSPCNTR(plane));
4755
94352cf9 4756 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4757
4758 intel_update_watermarks(dev);
4759
f564048e
EA		 4760 return ret;
4761}
4762
9fb526db
KP		 4763/*
4764 * Initialize reference clocks when the driver loads
4765 */
4766void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4767{
4768 struct drm_i915_private *dev_priv = dev->dev_private;
4769 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4770 struct intel_encoder *encoder;
13d83a67
JB		 4771 u32 temp;
4772 bool has_lvds = false;
199e5d79
KP		 4773 bool has_cpu_edp = false;
4774 bool has_pch_edp = false;
4775 bool has_panel = false;
99eb6a01
KP		 4776 bool has_ck505 = false;
4777 bool can_ssc = false;
13d83a67
JB		 4778
4779 /* We need to take the global config into account */
199e5d79
KP		 4780 list_for_each_entry(encoder, &mode_config->encoder_list,
4781 base.head) {
4782 switch (encoder->type) {
4783 case INTEL_OUTPUT_LVDS:
4784 has_panel = true;
4785 has_lvds = true;
4786 break;
4787 case INTEL_OUTPUT_EDP:
4788 has_panel = true;
4789 if (intel_encoder_is_pch_edp(&encoder->base))
4790 has_pch_edp = true;
4791 else
4792 has_cpu_edp = true;
4793 break;
13d83a67
JB		 4794 }
4795 }
4796
99eb6a01
KP		 4797 if (HAS_PCH_IBX(dev)) {
4798 has_ck505 = dev_priv->display_clock_mode;
4799 can_ssc = has_ck505;
4800 } else {
4801 has_ck505 = false;
4802 can_ssc = true;
4803 }
4804
4805 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4806 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4807 has_ck505);
13d83a67
JB		 4808
4809 /* Ironlake: try to setup display ref clock before DPLL
4810 * enabling. This is only under driver's control after
4811 * PCH B stepping, previous chipset stepping should be
4812 * ignoring this setting.
4813 */
4814 temp = I915_READ(PCH_DREF_CONTROL);
4815 /* Always enable nonspread source */
4816 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4817
99eb6a01
KP		 4818 if (has_ck505)
4819 temp |= DREF_NONSPREAD_CK505_ENABLE;
4820 else
4821 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4822
199e5d79
KP		 4823 if (has_panel) {
4824 temp &= ~DREF_SSC_SOURCE_MASK;
4825 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4826
199e5d79 4827 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4828 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4829 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4830 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4831 } else
4832 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4833
4834 /* Get SSC going before enabling the outputs */
4835 I915_WRITE(PCH_DREF_CONTROL, temp);
4836 POSTING_READ(PCH_DREF_CONTROL);
4837 udelay(200);
4838
13d83a67
JB		 4839 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4840
4841 /* Enable CPU source on CPU attached eDP */
199e5d79 4842 if (has_cpu_edp) {
99eb6a01 4843 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4844 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4845 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4846 }
13d83a67
JB		 4847 else
4848 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4849 } else
4850 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4851
4852 I915_WRITE(PCH_DREF_CONTROL, temp);
4853 POSTING_READ(PCH_DREF_CONTROL);
4854 udelay(200);
4855 } else {
4856 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4857
4858 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4859
4860 /* Turn off CPU output */
4861 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4862
4863 I915_WRITE(PCH_DREF_CONTROL, temp);
4864 POSTING_READ(PCH_DREF_CONTROL);
4865 udelay(200);
4866
4867 /* Turn off the SSC source */
4868 temp &= ~DREF_SSC_SOURCE_MASK;
4869 temp |= DREF_SSC_SOURCE_DISABLE;
4870
4871 /* Turn off SSC1 */
4872 temp &= ~ DREF_SSC1_ENABLE;
4873
13d83a67
JB		 4874 I915_WRITE(PCH_DREF_CONTROL, temp);
4875 POSTING_READ(PCH_DREF_CONTROL);
4876 udelay(200);
4877 }
4878}
4879
d9d444cb
JB		 4880static int ironlake_get_refclk(struct drm_crtc *crtc)
4881{
4882 struct drm_device *dev = crtc->dev;
4883 struct drm_i915_private *dev_priv = dev->dev_private;
4884 struct intel_encoder *encoder;
d9d444cb
JB		 4885 struct intel_encoder *edp_encoder = NULL;
4886 int num_connectors = 0;
4887 bool is_lvds = false;
4888
6c2b7c12 4889 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4890 switch (encoder->type) {
4891 case INTEL_OUTPUT_LVDS:
4892 is_lvds = true;
4893 break;
4894 case INTEL_OUTPUT_EDP:
4895 edp_encoder = encoder;
4896 break;
4897 }
4898 num_connectors++;
4899 }
4900
4901 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4902 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4903 dev_priv->lvds_ssc_freq);
4904 return dev_priv->lvds_ssc_freq * 1000;
4905 }
4906
4907 return 120000;
4908}
4909
c8203565
PZ		 4910static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4911 struct drm_display_mode *adjusted_mode,
4912 bool dither)
4913{
4914 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4916 int pipe = intel_crtc->pipe;
4917 uint32_t val;
4918
4919 val = I915_READ(PIPECONF(pipe));
4920
4921 val &= ~PIPE_BPC_MASK;
4922 switch (intel_crtc->bpp) {
4923 case 18:
4924 val |= PIPE_6BPC;
4925 break;
4926 case 24:
4927 val |= PIPE_8BPC;
4928 break;
4929 case 30:
4930 val |= PIPE_10BPC;
4931 break;
4932 case 36:
4933 val |= PIPE_12BPC;
4934 break;
4935 default:
cc769b62
PZ		 4936 /* Case prevented by intel_choose_pipe_bpp_dither. */
4937 BUG();
c8203565
PZ		 4938 }
4939
4940 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4941 if (dither)
4942 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4943
4944 val &= ~PIPECONF_INTERLACE_MASK;
4945 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4946 val |= PIPECONF_INTERLACED_ILK;
4947 else
4948 val |= PIPECONF_PROGRESSIVE;
4949
4950 I915_WRITE(PIPECONF(pipe), val);
4951 POSTING_READ(PIPECONF(pipe));
4952}
4953
ee2b0b38
PZ		 4954static void haswell_set_pipeconf(struct drm_crtc *crtc,
4955 struct drm_display_mode *adjusted_mode,
4956 bool dither)
4957{
4958 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4960 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4961 uint32_t val;
4962
702e7a56 4963 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4964
4965 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4966 if (dither)
4967 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4968
4969 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4970 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4971 val |= PIPECONF_INTERLACED_ILK;
4972 else
4973 val |= PIPECONF_PROGRESSIVE;
4974
702e7a56
PZ		 4975 I915_WRITE(PIPECONF(cpu_transcoder), val);
4976 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4977}
4978
6591c6e4
PZ		 4979static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4980 struct drm_display_mode *adjusted_mode,
4981 intel_clock_t *clock,
4982 bool *has_reduced_clock,
4983 intel_clock_t *reduced_clock)
4984{
4985 struct drm_device *dev = crtc->dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 struct intel_encoder *intel_encoder;
4988 int refclk;
4989 const intel_limit_t *limit;
4990 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4991
4992 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4993 switch (intel_encoder->type) {
4994 case INTEL_OUTPUT_LVDS:
4995 is_lvds = true;
4996 break;
4997 case INTEL_OUTPUT_SDVO:
4998 case INTEL_OUTPUT_HDMI:
4999 is_sdvo = true;
5000 if (intel_encoder->needs_tv_clock)
5001 is_tv = true;
5002 break;
5003 case INTEL_OUTPUT_TVOUT:
5004 is_tv = true;
5005 break;
5006 }
5007 }
5008
5009 refclk = ironlake_get_refclk(crtc);
5010
5011 /*
5012 * Returns a set of divisors for the desired target clock with the given
5013 * refclk, or FALSE. The returned values represent the clock equation:
5014 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5015 */
5016 limit = intel_limit(crtc, refclk);
5017 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5018 clock);
5019 if (!ret)
5020 return false;
5021
5022 if (is_lvds && dev_priv->lvds_downclock_avail) {
5023 /*
5024 * Ensure we match the reduced clock's P to the target clock.
5025 * If the clocks don't match, we can't switch the display clock
5026 * by using the FP0/FP1. In such case we will disable the LVDS
5027 * downclock feature.
5028 */
5029 *has_reduced_clock = limit->find_pll(limit, crtc,
5030 dev_priv->lvds_downclock,
5031 refclk,
5032 clock,
5033 reduced_clock);
5034 }
5035
5036 if (is_sdvo && is_tv)
5037 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5038
5039 return true;
5040}
5041
01a415fd
DV		 5042static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5043{
5044 struct drm_i915_private *dev_priv = dev->dev_private;
5045 uint32_t temp;
5046
5047 temp = I915_READ(SOUTH_CHICKEN1);
5048 if (temp & FDI_BC_BIFURCATION_SELECT)
5049 return;
5050
5051 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5053
5054 temp |= FDI_BC_BIFURCATION_SELECT;
5055 DRM_DEBUG_KMS("enabling fdi C rx\n");
5056 I915_WRITE(SOUTH_CHICKEN1, temp);
5057 POSTING_READ(SOUTH_CHICKEN1);
5058}
5059
5060static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5061{
5062 struct drm_device *dev = intel_crtc->base.dev;
5063 struct drm_i915_private *dev_priv = dev->dev_private;
5064 struct intel_crtc *pipe_B_crtc =
5065 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5066
5067 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5068 intel_crtc->pipe, intel_crtc->fdi_lanes);
5069 if (intel_crtc->fdi_lanes > 4) {
5070 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5071 intel_crtc->pipe, intel_crtc->fdi_lanes);
5072 /* Clamp lanes to avoid programming the hw with bogus values. */
5073 intel_crtc->fdi_lanes = 4;
5074
5075 return false;
5076 }
5077
5078 if (dev_priv->num_pipe == 2)
5079 return true;
5080
5081 switch (intel_crtc->pipe) {
5082 case PIPE_A:
5083 return true;
5084 case PIPE_B:
5085 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5086 intel_crtc->fdi_lanes > 2) {
5087 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5088 intel_crtc->pipe, intel_crtc->fdi_lanes);
5089 /* Clamp lanes to avoid programming the hw with bogus values. */
5090 intel_crtc->fdi_lanes = 2;
5091
5092 return false;
5093 }
5094
5095 if (intel_crtc->fdi_lanes > 2)
5096 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5097 else
5098 cpt_enable_fdi_bc_bifurcation(dev);
5099
5100 return true;
5101 case PIPE_C:
5102 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5103 if (intel_crtc->fdi_lanes > 2) {
5104 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5105 intel_crtc->pipe, intel_crtc->fdi_lanes);
5106 /* Clamp lanes to avoid programming the hw with bogus values. */
5107 intel_crtc->fdi_lanes = 2;
5108
5109 return false;
5110 }
5111 } else {
5112 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5113 return false;
5114 }
5115
5116 cpt_enable_fdi_bc_bifurcation(dev);
5117
5118 return true;
5119 default:
5120 BUG();
5121 }
5122}
5123
f48d8f23
PZ		 5124static void ironlake_set_m_n(struct drm_crtc *crtc,
5125 struct drm_display_mode *mode,
5126 struct drm_display_mode *adjusted_mode)
5127{
5128 struct drm_device *dev = crtc->dev;
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5131 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5132 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5133 struct fdi_m_n m_n = {0};
5134 int target_clock, pixel_multiplier, lane, link_bw;
5135 bool is_dp = false, is_cpu_edp = false;
5136
5137 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5138 switch (intel_encoder->type) {
5139 case INTEL_OUTPUT_DISPLAYPORT:
5140 is_dp = true;
5141 break;
5142 case INTEL_OUTPUT_EDP:
5143 is_dp = true;
5144 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5145 is_cpu_edp = true;
5146 edp_encoder = intel_encoder;
5147 break;
5148 }
5149 }
5150
5151 /* FDI link */
5152 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5153 lane = 0;
5154 /* CPU eDP doesn't require FDI link, so just set DP M/N
5155 according to current link config */
5156 if (is_cpu_edp) {
5157 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5158 } else {
5159 /* FDI is a binary signal running at ~2.7GHz, encoding
5160 * each output octet as 10 bits. The actual frequency
5161 * is stored as a divider into a 100MHz clock, and the
5162 * mode pixel clock is stored in units of 1KHz.
5163 * Hence the bw of each lane in terms of the mode signal
5164 * is:
5165 */
5166 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5167 }
5168
5169 /* [e]DP over FDI requires target mode clock instead of link clock. */
5170 if (edp_encoder)
5171 target_clock = intel_edp_target_clock(edp_encoder, mode);
5172 else if (is_dp)
5173 target_clock = mode->clock;
5174 else
5175 target_clock = adjusted_mode->clock;
5176
5177 if (!lane) {
5178 /*
5179 * Account for spread spectrum to avoid
5180 * oversubscribing the link. Max center spread
5181 * is 2.5%; use 5% for safety's sake.
5182 */
5183 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5184 lane = bps / (link_bw * 8) + 1;
5185 }
5186
5187 intel_crtc->fdi_lanes = lane;
5188
5189 if (pixel_multiplier > 1)
5190 link_bw *= pixel_multiplier;
5191 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5192 &m_n);
5193
afe2fcf5
PZ		 5194 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5195 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5196 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5197 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5198}
5199
de13a2e3
PZ		 5200static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5201 struct drm_display_mode *adjusted_mode,
5202 intel_clock_t *clock, u32 fp)
79e53945 5203{
de13a2e3 5204 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5205 struct drm_device *dev = crtc->dev;
5206 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5207 struct intel_encoder *intel_encoder;
5208 uint32_t dpll;
5209 int factor, pixel_multiplier, num_connectors = 0;
5210 bool is_lvds = false, is_sdvo = false, is_tv = false;
5211 bool is_dp = false, is_cpu_edp = false;
79e53945 5212
de13a2e3
PZ		 5213 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5214 switch (intel_encoder->type) {
79e53945
JB		 5215 case INTEL_OUTPUT_LVDS:
5216 is_lvds = true;
5217 break;
5218 case INTEL_OUTPUT_SDVO:
7d57382e 5219 case INTEL_OUTPUT_HDMI:
79e53945 5220 is_sdvo = true;
de13a2e3 5221 if (intel_encoder->needs_tv_clock)
e2f0ba97 5222 is_tv = true;
79e53945 5223 break;
79e53945
JB		 5224 case INTEL_OUTPUT_TVOUT:
5225 is_tv = true;
5226 break;
a4fc5ed6
KP		 5227 case INTEL_OUTPUT_DISPLAYPORT:
5228 is_dp = true;
5229 break;
32f9d658 5230 case INTEL_OUTPUT_EDP:
e3aef172 5231 is_dp = true;
de13a2e3 5232 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5233 is_cpu_edp = true;
32f9d658 5234 break;
79e53945 5235 }
43565a06 5236
c751ce4f 5237 num_connectors++;
79e53945
JB		 5238 }
5239
c1858123 5240 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5241 factor = 21;
5242 if (is_lvds) {
5243 if ((intel_panel_use_ssc(dev_priv) &&
5244 dev_priv->lvds_ssc_freq == 100) ||
5245 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5246 factor = 25;
5247 } else if (is_sdvo && is_tv)
5248 factor = 20;
c1858123 5249
de13a2e3 5250 if (clock->m < factor * clock->n)
8febb297 5251 fp |= FP_CB_TUNE;
2c07245f 5252
5eddb70b 5253 dpll = 0;
2c07245f 5254
a07d6787
EA		 5255 if (is_lvds)
5256 dpll |= DPLLB_MODE_LVDS;
5257 else
5258 dpll |= DPLLB_MODE_DAC_SERIAL;
5259 if (is_sdvo) {
de13a2e3 5260 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5261 if (pixel_multiplier > 1) {
5262 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5263 }
a07d6787
EA		 5264 dpll |= DPLL_DVO_HIGH_SPEED;
5265 }
e3aef172 5266 if (is_dp && !is_cpu_edp)
a07d6787 5267 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5268
a07d6787 5269 /* compute bitmask from p1 value */
de13a2e3 5270 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5271 /* also FPA1 */
de13a2e3 5272 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5273
de13a2e3 5274 switch (clock->p2) {
a07d6787
EA		 5275 case 5:
5276 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5277 break;
5278 case 7:
5279 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5280 break;
5281 case 10:
5282 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5283 break;
5284 case 14:
5285 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5286 break;
79e53945
JB		 5287 }
5288
43565a06
KH		 5289 if (is_sdvo && is_tv)
5290 dpll |= PLL_REF_INPUT_TVCLKINBC;
5291 else if (is_tv)
79e53945 5292 /* XXX: just matching BIOS for now */
43565a06 5293 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5294 dpll |= 3;
a7615030 5295 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5296 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5297 else
5298 dpll |= PLL_REF_INPUT_DREFCLK;
5299
de13a2e3
PZ		 5300 return dpll;
5301}
5302
5303static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5304 struct drm_display_mode *mode,
5305 struct drm_display_mode *adjusted_mode,
5306 int x, int y,
5307 struct drm_framebuffer *fb)
5308{
5309 struct drm_device *dev = crtc->dev;
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5312 int pipe = intel_crtc->pipe;
5313 int plane = intel_crtc->plane;
5314 int num_connectors = 0;
5315 intel_clock_t clock, reduced_clock;
5316 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5317 bool ok, has_reduced_clock = false;
5318 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5319 struct intel_encoder *encoder;
5320 u32 temp;
5321 int ret;
01a415fd 5322 bool dither, fdi_config_ok;
de13a2e3
PZ		 5323
5324 for_each_encoder_on_crtc(dev, crtc, encoder) {
5325 switch (encoder->type) {
5326 case INTEL_OUTPUT_LVDS:
5327 is_lvds = true;
5328 break;
de13a2e3
PZ		 5329 case INTEL_OUTPUT_DISPLAYPORT:
5330 is_dp = true;
5331 break;
5332 case INTEL_OUTPUT_EDP:
5333 is_dp = true;
e2f12b07 5334 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5335 is_cpu_edp = true;
5336 break;
5337 }
5338
5339 num_connectors++;
5340 }
5341
5dc5298b
PZ		 5342 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5343 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5344
de13a2e3
PZ		 5345 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5346 &has_reduced_clock, &reduced_clock);
5347 if (!ok) {
5348 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5349 return -EINVAL;
5350 }
5351
5352 /* Ensure that the cursor is valid for the new mode before changing... */
5353 intel_crtc_update_cursor(crtc, true);
5354
5355 /* determine panel color depth */
c8241969
JN		 5356 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5357 adjusted_mode);
de13a2e3
PZ		 5358 if (is_lvds && dev_priv->lvds_dither)
5359 dither = true;
5360
5361 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5362 if (has_reduced_clock)
5363 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5364 reduced_clock.m2;
5365
5366 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5367
f7cb34d4 5368 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5369 drm_mode_debug_printmodeline(mode);
5370
5dc5298b
PZ		 5371 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5372 if (!is_cpu_edp) {
ee7b9f93 5373 struct intel_pch_pll *pll;
4b645f14 5374
ee7b9f93
JB		 5375 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5376 if (pll == NULL) {
5377 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5378 pipe);
4b645f14
JB		 5379 return -EINVAL;
5380 }
ee7b9f93
JB		 5381 } else
5382 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5383
5384 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5385 * This is an exception to the general rule that mode_set doesn't turn
5386 * things on.
5387 */
5388 if (is_lvds) {
fae14981 5389 temp = I915_READ(PCH_LVDS);
5eddb70b 5390 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5391 if (HAS_PCH_CPT(dev)) {
5392 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5393 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5394 } else {
5395 if (pipe == 1)
5396 temp |= LVDS_PIPEB_SELECT;
5397 else
5398 temp &= ~LVDS_PIPEB_SELECT;
5399 }
4b645f14 5400
a3e17eb8 5401 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5402 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5403 /* Set the B0-B3 data pairs corresponding to whether we're going to
5404 * set the DPLLs for dual-channel mode or not.
5405 */
5406 if (clock.p2 == 7)
5eddb70b 5407 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5408 else
5eddb70b 5409 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5410
5411 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5412 * appropriately here, but we need to look more thoroughly into how
5413 * panels behave in the two modes.
5414 */
284d5df5 5415 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5416 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5417 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5418 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5419 temp |= LVDS_VSYNC_POLARITY;
fae14981 5420 I915_WRITE(PCH_LVDS, temp);
79e53945 5421 }
434ed097 5422
e3aef172 5423 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5424 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5425 } else {
8db9d77b 5426 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5427 I915_WRITE(TRANSDATA_M1(pipe), 0);
5428 I915_WRITE(TRANSDATA_N1(pipe), 0);
5429 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5430 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5431 }
79e53945 5432
ee7b9f93
JB		 5433 if (intel_crtc->pch_pll) {
5434 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5435
32f9d658 5436 /* Wait for the clocks to stabilize. */
ee7b9f93 5437 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5438 udelay(150);
5439
8febb297
EA		 5440 /* The pixel multiplier can only be updated once the
5441 * DPLL is enabled and the clocks are stable.
5442 *
5443 * So write it again.
5444 */
ee7b9f93 5445 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5446 }
79e53945 5447
5eddb70b 5448 intel_crtc->lowfreq_avail = false;
ee7b9f93 5449 if (intel_crtc->pch_pll) {
4b645f14 5450 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5451 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5452 intel_crtc->lowfreq_avail = true;
4b645f14 5453 } else {
ee7b9f93 5454 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5455 }
5456 }
5457
b0e77b9c 5458 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5459
01a415fd
DV		 5460 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5461 * ironlake_check_fdi_lanes. */
f48d8f23 5462 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5463
01a415fd
DV		 5464 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5465
e3aef172 5466 if (is_cpu_edp)
8febb297 5467 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5468
c8203565 5469 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5470
9d0498a2 5471 intel_wait_for_vblank(dev, pipe);
79e53945 5472
a1f9e77e
PZ		 5473 /* Set up the display plane register */
5474 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5475 POSTING_READ(DSPCNTR(plane));
79e53945 5476
94352cf9 5477 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5478
5479 intel_update_watermarks(dev);
5480
1f8eeabf
ED		 5481 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5482
01a415fd 5483 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5484}
5485
09b4ddf9
PZ		 5486static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5487 struct drm_display_mode *mode,
5488 struct drm_display_mode *adjusted_mode,
5489 int x, int y,
5490 struct drm_framebuffer *fb)
5491{
5492 struct drm_device *dev = crtc->dev;
5493 struct drm_i915_private *dev_priv = dev->dev_private;
5494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5495 int pipe = intel_crtc->pipe;
5496 int plane = intel_crtc->plane;
5497 int num_connectors = 0;
5498 intel_clock_t clock, reduced_clock;
5dc5298b 5499 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5500 bool ok, has_reduced_clock = false;
5501 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5502 struct intel_encoder *encoder;
5503 u32 temp;
5504 int ret;
5505 bool dither;
5506
5507 for_each_encoder_on_crtc(dev, crtc, encoder) {
5508 switch (encoder->type) {
5509 case INTEL_OUTPUT_LVDS:
5510 is_lvds = true;
5511 break;
5512 case INTEL_OUTPUT_DISPLAYPORT:
5513 is_dp = true;
5514 break;
5515 case INTEL_OUTPUT_EDP:
5516 is_dp = true;
5517 if (!intel_encoder_is_pch_edp(&encoder->base))
5518 is_cpu_edp = true;
5519 break;
5520 }
5521
5522 num_connectors++;
5523 }
5524
a5c961d1
PZ		 5525 if (is_cpu_edp)
5526 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5527 else
5528 intel_crtc->cpu_transcoder = pipe;
5529
5dc5298b
PZ		 5530 /* We are not sure yet this won't happen. */
5531 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5532 INTEL_PCH_TYPE(dev));
5533
5534 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5535 num_connectors, pipe_name(pipe));
5536
702e7a56 5537 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5538 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5539
5540 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5541
6441ab5f
PZ		 5542 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5543 return -EINVAL;
5544
5dc5298b
PZ		 5545 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5546 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5547 &has_reduced_clock,
5548 &reduced_clock);
5549 if (!ok) {
5550 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5551 return -EINVAL;
5552 }
09b4ddf9
PZ		 5553 }
5554
5555 /* Ensure that the cursor is valid for the new mode before changing... */
5556 intel_crtc_update_cursor(crtc, true);
5557
5558 /* determine panel color depth */
c8241969
JN		 5559 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5560 adjusted_mode);
09b4ddf9
PZ		 5561 if (is_lvds && dev_priv->lvds_dither)
5562 dither = true;
5563
09b4ddf9
PZ		 5564 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5565 drm_mode_debug_printmodeline(mode);
5566
5dc5298b
PZ		 5567 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5568 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5569 if (has_reduced_clock)
5570 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5571 reduced_clock.m2;
5572
5573 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5574 fp);
5575
5576 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5577 * own on pre-Haswell/LPT generation */
5578 if (!is_cpu_edp) {
5579 struct intel_pch_pll *pll;
5580
5581 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5582 if (pll == NULL) {
5583 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5584 pipe);
5585 return -EINVAL;
5586 }
5587 } else
5588 intel_put_pch_pll(intel_crtc);
09b4ddf9 5589
5dc5298b
PZ		 5590 /* The LVDS pin pair needs to be on before the DPLLs are
5591 * enabled. This is an exception to the general rule that
5592 * mode_set doesn't turn things on.
5593 */
5594 if (is_lvds) {
5595 temp = I915_READ(PCH_LVDS);
5596 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5597 if (HAS_PCH_CPT(dev)) {
5598 temp &= ~PORT_TRANS_SEL_MASK;
5599 temp |= PORT_TRANS_SEL_CPT(pipe);
5600 } else {
5601 if (pipe == 1)
5602 temp |= LVDS_PIPEB_SELECT;
5603 else
5604 temp &= ~LVDS_PIPEB_SELECT;
5605 }
09b4ddf9 5606
5dc5298b
PZ		 5607 /* set the corresponsding LVDS_BORDER bit */
5608 temp |= dev_priv->lvds_border_bits;
5609 /* Set the B0-B3 data pairs corresponding to whether
5610 * we're going to set the DPLLs for dual-channel mode or
5611 * not.
5612 */
5613 if (clock.p2 == 7)
5614 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5615 else
5dc5298b
PZ		 5616 temp &= ~(LVDS_B0B3_POWER_UP |
5617 LVDS_CLKB_POWER_UP);
5618
5619 /* It would be nice to set 24 vs 18-bit mode
5620 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5621 * look more thoroughly into how panels behave in the
5622 * two modes.
5623 */
5624 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5625 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5626 temp |= LVDS_HSYNC_POLARITY;
5627 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5628 temp |= LVDS_VSYNC_POLARITY;
5629 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5630 }
09b4ddf9
PZ		 5631 }
5632
5633 if (is_dp && !is_cpu_edp) {
5634 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5635 } else {
5dc5298b
PZ		 5636 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5637 /* For non-DP output, clear any trans DP clock recovery
5638 * setting.*/
5639 I915_WRITE(TRANSDATA_M1(pipe), 0);
5640 I915_WRITE(TRANSDATA_N1(pipe), 0);
5641 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5642 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5643 }
09b4ddf9
PZ		 5644 }
5645
5646 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5647 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5648 if (intel_crtc->pch_pll) {
5649 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5650
5651 /* Wait for the clocks to stabilize. */
5652 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5653 udelay(150);
5654
5655 /* The pixel multiplier can only be updated once the
5656 * DPLL is enabled and the clocks are stable.
5657 *
5658 * So write it again.
5659 */
5660 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5661 }
5662
5663 if (intel_crtc->pch_pll) {
5664 if (is_lvds && has_reduced_clock && i915_powersave) {
5665 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5666 intel_crtc->lowfreq_avail = true;
5667 } else {
5668 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5669 }
09b4ddf9
PZ		 5670 }
5671 }
5672
5673 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5674
1eb8dfec
PZ		 5675 if (!is_dp || is_cpu_edp)
5676 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5677
5dc5298b
PZ		 5678 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5679 if (is_cpu_edp)
5680 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5681
ee2b0b38 5682 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5683
09b4ddf9
PZ		 5684 /* Set up the display plane register */
5685 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5686 POSTING_READ(DSPCNTR(plane));
5687
5688 ret = intel_pipe_set_base(crtc, x, y, fb);
5689
5690 intel_update_watermarks(dev);
5691
5692 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5693
5694 return ret;
5695}
5696
f564048e
EA		 5697static int intel_crtc_mode_set(struct drm_crtc *crtc,
5698 struct drm_display_mode *mode,
5699 struct drm_display_mode *adjusted_mode,
5700 int x, int y,
94352cf9 5701 struct drm_framebuffer *fb)
f564048e
EA		 5702{
5703 struct drm_device *dev = crtc->dev;
5704 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5706 int pipe = intel_crtc->pipe;
f564048e
EA		 5707 int ret;
5708
0b701d27 5709 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5710
f564048e 5711 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5712 x, y, fb);
79e53945 5713 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5714
1f803ee5 5715 return ret;
79e53945
JB		 5716}
5717
3a9627f4
WF		 5718static bool intel_eld_uptodate(struct drm_connector *connector,
5719 int reg_eldv, uint32_t bits_eldv,
5720 int reg_elda, uint32_t bits_elda,
5721 int reg_edid)
5722{
5723 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5724 uint8_t *eld = connector->eld;
5725 uint32_t i;
5726
5727 i = I915_READ(reg_eldv);
5728 i &= bits_eldv;
5729
5730 if (!eld[0])
5731 return !i;
5732
5733 if (!i)
5734 return false;
5735
5736 i = I915_READ(reg_elda);
5737 i &= ~bits_elda;
5738 I915_WRITE(reg_elda, i);
5739
5740 for (i = 0; i < eld[2]; i++)
5741 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5742 return false;
5743
5744 return true;
5745}
5746
e0dac65e
WF		 5747static void g4x_write_eld(struct drm_connector *connector,
5748 struct drm_crtc *crtc)
5749{
5750 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5751 uint8_t *eld = connector->eld;
5752 uint32_t eldv;
5753 uint32_t len;
5754 uint32_t i;
5755
5756 i = I915_READ(G4X_AUD_VID_DID);
5757
5758 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5759 eldv = G4X_ELDV_DEVCL_DEVBLC;
5760 else
5761 eldv = G4X_ELDV_DEVCTG;
5762
3a9627f4
WF		 5763 if (intel_eld_uptodate(connector,
5764 G4X_AUD_CNTL_ST, eldv,
5765 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5766 G4X_HDMIW_HDMIEDID))
5767 return;
5768
e0dac65e
WF		 5769 i = I915_READ(G4X_AUD_CNTL_ST);
5770 i &= ~(eldv | G4X_ELD_ADDR);
5771 len = (i >> 9) & 0x1f; /* ELD buffer size */
5772 I915_WRITE(G4X_AUD_CNTL_ST, i);
5773
5774 if (!eld[0])
5775 return;
5776
5777 len = min_t(uint8_t, eld[2], len);
5778 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5779 for (i = 0; i < len; i++)
5780 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5781
5782 i = I915_READ(G4X_AUD_CNTL_ST);
5783 i |= eldv;
5784 I915_WRITE(G4X_AUD_CNTL_ST, i);
5785}
5786
83358c85
WX		 5787static void haswell_write_eld(struct drm_connector *connector,
5788 struct drm_crtc *crtc)
5789{
5790 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5791 uint8_t *eld = connector->eld;
5792 struct drm_device *dev = crtc->dev;
5793 uint32_t eldv;
5794 uint32_t i;
5795 int len;
5796 int pipe = to_intel_crtc(crtc)->pipe;
5797 int tmp;
5798
5799 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5800 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5801 int aud_config = HSW_AUD_CFG(pipe);
5802 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5803
5804
5805 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5806
5807 /* Audio output enable */
5808 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5809 tmp = I915_READ(aud_cntrl_st2);
5810 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5811 I915_WRITE(aud_cntrl_st2, tmp);
5812
5813 /* Wait for 1 vertical blank */
5814 intel_wait_for_vblank(dev, pipe);
5815
5816 /* Set ELD valid state */
5817 tmp = I915_READ(aud_cntrl_st2);
5818 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5819 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5820 I915_WRITE(aud_cntrl_st2, tmp);
5821 tmp = I915_READ(aud_cntrl_st2);
5822 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5823
5824 /* Enable HDMI mode */
5825 tmp = I915_READ(aud_config);
5826 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5827 /* clear N_programing_enable and N_value_index */
5828 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5829 I915_WRITE(aud_config, tmp);
5830
5831 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5832
5833 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5834
5835 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5836 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5837 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5838 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5839 } else
5840 I915_WRITE(aud_config, 0);
5841
5842 if (intel_eld_uptodate(connector,
5843 aud_cntrl_st2, eldv,
5844 aud_cntl_st, IBX_ELD_ADDRESS,
5845 hdmiw_hdmiedid))
5846 return;
5847
5848 i = I915_READ(aud_cntrl_st2);
5849 i &= ~eldv;
5850 I915_WRITE(aud_cntrl_st2, i);
5851
5852 if (!eld[0])
5853 return;
5854
5855 i = I915_READ(aud_cntl_st);
5856 i &= ~IBX_ELD_ADDRESS;
5857 I915_WRITE(aud_cntl_st, i);
5858 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5859 DRM_DEBUG_DRIVER("port num:%d\n", i);
5860
5861 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5862 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5863 for (i = 0; i < len; i++)
5864 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5865
5866 i = I915_READ(aud_cntrl_st2);
5867 i |= eldv;
5868 I915_WRITE(aud_cntrl_st2, i);
5869
5870}
5871
e0dac65e
WF		 5872static void ironlake_write_eld(struct drm_connector *connector,
5873 struct drm_crtc *crtc)
5874{
5875 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5876 uint8_t *eld = connector->eld;
5877 uint32_t eldv;
5878 uint32_t i;
5879 int len;
5880 int hdmiw_hdmiedid;
b6daa025 5881 int aud_config;
e0dac65e
WF		 5882 int aud_cntl_st;
5883 int aud_cntrl_st2;
9b138a83 5884 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5885
b3f33cbf 5886 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5887 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5888 aud_config = IBX_AUD_CFG(pipe);
5889 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5890 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5891 } else {
9b138a83
WX		 5892 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5893 aud_config = CPT_AUD_CFG(pipe);
5894 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5895 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5896 }
5897
9b138a83 5898 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5899
5900 i = I915_READ(aud_cntl_st);
9b138a83 5901 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5902 if (!i) {
5903 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5904 /* operate blindly on all ports */
1202b4c6
WF		 5905 eldv = IBX_ELD_VALIDB;
5906 eldv |= IBX_ELD_VALIDB << 4;
5907 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5908 } else {
5909 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5910 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5911 }
5912
3a9627f4
WF		 5913 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5914 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5915 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5916 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5917 } else
5918 I915_WRITE(aud_config, 0);
e0dac65e 5919
3a9627f4
WF		 5920 if (intel_eld_uptodate(connector,
5921 aud_cntrl_st2, eldv,
5922 aud_cntl_st, IBX_ELD_ADDRESS,
5923 hdmiw_hdmiedid))
5924 return;
5925
e0dac65e
WF		 5926 i = I915_READ(aud_cntrl_st2);
5927 i &= ~eldv;
5928 I915_WRITE(aud_cntrl_st2, i);
5929
5930 if (!eld[0])
5931 return;
5932
e0dac65e 5933 i = I915_READ(aud_cntl_st);
1202b4c6 5934 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5935 I915_WRITE(aud_cntl_st, i);
5936
5937 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5938 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5939 for (i = 0; i < len; i++)
5940 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5941
5942 i = I915_READ(aud_cntrl_st2);
5943 i |= eldv;
5944 I915_WRITE(aud_cntrl_st2, i);
5945}
5946
5947void intel_write_eld(struct drm_encoder *encoder,
5948 struct drm_display_mode *mode)
5949{
5950 struct drm_crtc *crtc = encoder->crtc;
5951 struct drm_connector *connector;
5952 struct drm_device *dev = encoder->dev;
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954
5955 connector = drm_select_eld(encoder, mode);
5956 if (!connector)
5957 return;
5958
5959 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5960 connector->base.id,
5961 drm_get_connector_name(connector),
5962 connector->encoder->base.id,
5963 drm_get_encoder_name(connector->encoder));
5964
5965 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5966
5967 if (dev_priv->display.write_eld)
5968 dev_priv->display.write_eld(connector, crtc);
5969}
5970
79e53945
JB		 5971/** Loads the palette/gamma unit for the CRTC with the prepared values */
5972void intel_crtc_load_lut(struct drm_crtc *crtc)
5973{
5974 struct drm_device *dev = crtc->dev;
5975 struct drm_i915_private *dev_priv = dev->dev_private;
5976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5977 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5978 int i;
5979
5980 /* The clocks have to be on to load the palette. */
aed3f09d 5981 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5982 return;
5983
f2b115e6 5984 /* use legacy palette for Ironlake */
bad720ff 5985 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5986 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5987
79e53945
JB		 5988 for (i = 0; i < 256; i++) {
5989 I915_WRITE(palreg + 4 * i,
5990 (intel_crtc->lut_r[i] << 16) |
5991 (intel_crtc->lut_g[i] << 8) |
5992 intel_crtc->lut_b[i]);
5993 }
5994}
5995
560b85bb
CW		 5996static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5997{
5998 struct drm_device *dev = crtc->dev;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001 bool visible = base != 0;
6002 u32 cntl;
6003
6004 if (intel_crtc->cursor_visible == visible)
6005 return;
6006
9db4a9c7 6007 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6008 if (visible) {
6009 /* On these chipsets we can only modify the base whilst
6010 * the cursor is disabled.
6011 */
9db4a9c7 6012 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6013
6014 cntl &= ~(CURSOR_FORMAT_MASK);
6015 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6016 cntl |= CURSOR_ENABLE |
6017 CURSOR_GAMMA_ENABLE |
6018 CURSOR_FORMAT_ARGB;
6019 } else
6020 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6021 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6022
6023 intel_crtc->cursor_visible = visible;
6024}
6025
6026static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6027{
6028 struct drm_device *dev = crtc->dev;
6029 struct drm_i915_private *dev_priv = dev->dev_private;
6030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031 int pipe = intel_crtc->pipe;
6032 bool visible = base != 0;
6033
6034 if (intel_crtc->cursor_visible != visible) {
548f245b 6035 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6036 if (base) {
6037 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6038 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6039 cntl |= pipe << 28; /* Connect to correct pipe */
6040 } else {
6041 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6042 cntl |= CURSOR_MODE_DISABLE;
6043 }
9db4a9c7 6044 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6045
6046 intel_crtc->cursor_visible = visible;
6047 }
6048 /* and commit changes on next vblank */
9db4a9c7 6049 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6050}
6051
65a21cd6
JB		 6052static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6053{
6054 struct drm_device *dev = crtc->dev;
6055 struct drm_i915_private *dev_priv = dev->dev_private;
6056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6057 int pipe = intel_crtc->pipe;
6058 bool visible = base != 0;
6059
6060 if (intel_crtc->cursor_visible != visible) {
6061 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6062 if (base) {
6063 cntl &= ~CURSOR_MODE;
6064 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6065 } else {
6066 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6067 cntl |= CURSOR_MODE_DISABLE;
6068 }
6069 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6070
6071 intel_crtc->cursor_visible = visible;
6072 }
6073 /* and commit changes on next vblank */
6074 I915_WRITE(CURBASE_IVB(pipe), base);
6075}
6076
cda4b7d3 6077/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6078static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6079 bool on)
cda4b7d3
CW		 6080{
6081 struct drm_device *dev = crtc->dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6084 int pipe = intel_crtc->pipe;
6085 int x = intel_crtc->cursor_x;
6086 int y = intel_crtc->cursor_y;
560b85bb 6087 u32 base, pos;
cda4b7d3
CW		 6088 bool visible;
6089
6090 pos = 0;
6091
6b383a7f 6092 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6093 base = intel_crtc->cursor_addr;
6094 if (x > (int) crtc->fb->width)
6095 base = 0;
6096
6097 if (y > (int) crtc->fb->height)
6098 base = 0;
6099 } else
6100 base = 0;
6101
6102 if (x < 0) {
6103 if (x + intel_crtc->cursor_width < 0)
6104 base = 0;
6105
6106 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6107 x = -x;
6108 }
6109 pos |= x << CURSOR_X_SHIFT;
6110
6111 if (y < 0) {
6112 if (y + intel_crtc->cursor_height < 0)
6113 base = 0;
6114
6115 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6116 y = -y;
6117 }
6118 pos |= y << CURSOR_Y_SHIFT;
6119
6120 visible = base != 0;
560b85bb 6121 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6122 return;
6123
0cd83aa9 6124 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6125 I915_WRITE(CURPOS_IVB(pipe), pos);
6126 ivb_update_cursor(crtc, base);
6127 } else {
6128 I915_WRITE(CURPOS(pipe), pos);
6129 if (IS_845G(dev) || IS_I865G(dev))
6130 i845_update_cursor(crtc, base);
6131 else
6132 i9xx_update_cursor(crtc, base);
6133 }
cda4b7d3
CW		 6134}
6135
79e53945 6136static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6137 struct drm_file *file,
79e53945
JB		 6138 uint32_t handle,
6139 uint32_t width, uint32_t height)
6140{
6141 struct drm_device *dev = crtc->dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6144 struct drm_i915_gem_object *obj;
cda4b7d3 6145 uint32_t addr;
3f8bc370 6146 int ret;
79e53945 6147
79e53945
JB		 6148 /* if we want to turn off the cursor ignore width and height */
6149 if (!handle) {
28c97730 6150 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6151 addr = 0;
05394f39 6152 obj = NULL;
5004417d 6153 mutex_lock(&dev->struct_mutex);
3f8bc370 6154 goto finish;
79e53945
JB		 6155 }
6156
6157 /* Currently we only support 64x64 cursors */
6158 if (width != 64 || height != 64) {
6159 DRM_ERROR("we currently only support 64x64 cursors\n");
6160 return -EINVAL;
6161 }
6162
05394f39 6163 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6164 if (&obj->base == NULL)
79e53945
JB		 6165 return -ENOENT;
6166
05394f39 6167 if (obj->base.size < width * height * 4) {
79e53945 6168 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6169 ret = -ENOMEM;
6170 goto fail;
79e53945
JB		 6171 }
6172
71acb5eb 6173 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6174 mutex_lock(&dev->struct_mutex);
b295d1b6 6175 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6176 if (obj->tiling_mode) {
6177 DRM_ERROR("cursor cannot be tiled\n");
6178 ret = -EINVAL;
6179 goto fail_locked;
6180 }
6181
2da3b9b9 6182 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6183 if (ret) {
6184 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6185 goto fail_locked;
e7b526bb
CW		 6186 }
6187
d9e86c0e
CW		 6188 ret = i915_gem_object_put_fence(obj);
6189 if (ret) {
2da3b9b9 6190 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6191 goto fail_unpin;
6192 }
6193
05394f39 6194 addr = obj->gtt_offset;
71acb5eb 6195 } else {
6eeefaf3 6196 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6197 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6198 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6199 align);
71acb5eb
DA		 6200 if (ret) {
6201 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6202 goto fail_locked;
71acb5eb 6203 }
05394f39 6204 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6205 }
6206
a6c45cf0 6207 if (IS_GEN2(dev))
14b60391
JB		 6208 I915_WRITE(CURSIZE, (height << 12) | width);
6209
3f8bc370 6210 finish:
3f8bc370 6211 if (intel_crtc->cursor_bo) {
b295d1b6 6212 if (dev_priv->info->cursor_needs_physical) {
05394f39 6213 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6214 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6215 } else
6216 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6217 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6218 }
80824003 6219
7f9872e0 6220 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6221
6222 intel_crtc->cursor_addr = addr;
05394f39 6223 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6224 intel_crtc->cursor_width = width;
6225 intel_crtc->cursor_height = height;
6226
6b383a7f 6227 intel_crtc_update_cursor(crtc, true);
3f8bc370 6228
79e53945 6229 return 0;
e7b526bb 6230fail_unpin:
05394f39 6231 i915_gem_object_unpin(obj);
7f9872e0 6232fail_locked:
34b8686e 6233 mutex_unlock(&dev->struct_mutex);
bc9025bd 6234fail:
05394f39 6235 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6236 return ret;
79e53945
JB		 6237}
6238
6239static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6240{
79e53945 6241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6242
cda4b7d3
CW		 6243 intel_crtc->cursor_x = x;
6244 intel_crtc->cursor_y = y;
652c393a 6245
6b383a7f 6246 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6247
6248 return 0;
6249}
6250
6251/** Sets the color ramps on behalf of RandR */
6252void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6253 u16 blue, int regno)
6254{
6255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6256
6257 intel_crtc->lut_r[regno] = red >> 8;
6258 intel_crtc->lut_g[regno] = green >> 8;
6259 intel_crtc->lut_b[regno] = blue >> 8;
6260}
6261
b8c00ac5
DA		 6262void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6263 u16 *blue, int regno)
6264{
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6266
6267 *red = intel_crtc->lut_r[regno] << 8;
6268 *green = intel_crtc->lut_g[regno] << 8;
6269 *blue = intel_crtc->lut_b[regno] << 8;
6270}
6271
79e53945 6272static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6273 u16 *blue, uint32_t start, uint32_t size)
79e53945 6274{
7203425a 6275 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6277
7203425a 6278 for (i = start; i < end; i++) {
79e53945
JB		 6279 intel_crtc->lut_r[i] = red[i] >> 8;
6280 intel_crtc->lut_g[i] = green[i] >> 8;
6281 intel_crtc->lut_b[i] = blue[i] >> 8;
6282 }
6283
6284 intel_crtc_load_lut(crtc);
6285}
6286
6287/**
6288 * Get a pipe with a simple mode set on it for doing load-based monitor
6289 * detection.
6290 *
6291 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6292 * its requirements. The pipe will be connected to no other encoders.
79e53945 6293 *
c751ce4f 6294 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6295 * configured for it. In the future, it could choose to temporarily disable
6296 * some outputs to free up a pipe for its use.
6297 *
6298 * \return crtc, or NULL if no pipes are available.
6299 */
6300
6301/* VESA 640x480x72Hz mode to set on the pipe */
6302static struct drm_display_mode load_detect_mode = {
6303 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6304 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6305};
6306
d2dff872
CW		 6307static struct drm_framebuffer *
6308intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6309 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6310 struct drm_i915_gem_object *obj)
6311{
6312 struct intel_framebuffer *intel_fb;
6313 int ret;
6314
6315 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6316 if (!intel_fb) {
6317 drm_gem_object_unreference_unlocked(&obj->base);
6318 return ERR_PTR(-ENOMEM);
6319 }
6320
6321 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6322 if (ret) {
6323 drm_gem_object_unreference_unlocked(&obj->base);
6324 kfree(intel_fb);
6325 return ERR_PTR(ret);
6326 }
6327
6328 return &intel_fb->base;
6329}
6330
6331static u32
6332intel_framebuffer_pitch_for_width(int width, int bpp)
6333{
6334 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6335 return ALIGN(pitch, 64);
6336}
6337
6338static u32
6339intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6340{
6341 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6342 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6343}
6344
6345static struct drm_framebuffer *
6346intel_framebuffer_create_for_mode(struct drm_device *dev,
6347 struct drm_display_mode *mode,
6348 int depth, int bpp)
6349{
6350 struct drm_i915_gem_object *obj;
308e5bcb 6351 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6352
6353 obj = i915_gem_alloc_object(dev,
6354 intel_framebuffer_size_for_mode(mode, bpp));
6355 if (obj == NULL)
6356 return ERR_PTR(-ENOMEM);
6357
6358 mode_cmd.width = mode->hdisplay;
6359 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6360 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6361 bpp);
5ca0c34a 6362 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6363
6364 return intel_framebuffer_create(dev, &mode_cmd, obj);
6365}
6366
6367static struct drm_framebuffer *
6368mode_fits_in_fbdev(struct drm_device *dev,
6369 struct drm_display_mode *mode)
6370{
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 struct drm_i915_gem_object *obj;
6373 struct drm_framebuffer *fb;
6374
6375 if (dev_priv->fbdev == NULL)
6376 return NULL;
6377
6378 obj = dev_priv->fbdev->ifb.obj;
6379 if (obj == NULL)
6380 return NULL;
6381
6382 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6383 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6384 fb->bits_per_pixel))
d2dff872
CW		 6385 return NULL;
6386
01f2c773 6387 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6388 return NULL;
6389
6390 return fb;
6391}
6392
d2434ab7 6393bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6394 struct drm_display_mode *mode,
8261b191 6395 struct intel_load_detect_pipe *old)
79e53945
JB		 6396{
6397 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6398 struct intel_encoder *intel_encoder =
6399 intel_attached_encoder(connector);
79e53945 6400 struct drm_crtc *possible_crtc;
4ef69c7a 6401 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6402 struct drm_crtc *crtc = NULL;
6403 struct drm_device *dev = encoder->dev;
94352cf9 6404 struct drm_framebuffer *fb;
79e53945
JB		 6405 int i = -1;
6406
d2dff872
CW		 6407 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6408 connector->base.id, drm_get_connector_name(connector),
6409 encoder->base.id, drm_get_encoder_name(encoder));
6410
79e53945
JB		 6411 /*
6412 * Algorithm gets a little messy:
7a5e4805 6413 *
79e53945
JB		 6414 * - if the connector already has an assigned crtc, use it (but make
6415 * sure it's on first)
7a5e4805 6416 *
79e53945
JB		 6417 * - try to find the first unused crtc that can drive this connector,
6418 * and use that if we find one
79e53945
JB		 6419 */
6420
6421 /* See if we already have a CRTC for this connector */
6422 if (encoder->crtc) {
6423 crtc = encoder->crtc;
8261b191 6424
24218aac 6425 old->dpms_mode = connector->dpms;
8261b191
CW		 6426 old->load_detect_temp = false;
6427
6428 /* Make sure the crtc and connector are running */
24218aac
DV		 6429 if (connector->dpms != DRM_MODE_DPMS_ON)
6430 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6431
7173188d 6432 return true;
79e53945
JB		 6433 }
6434
6435 /* Find an unused one (if possible) */
6436 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6437 i++;
6438 if (!(encoder->possible_crtcs & (1 << i)))
6439 continue;
6440 if (!possible_crtc->enabled) {
6441 crtc = possible_crtc;
6442 break;
6443 }
79e53945
JB		 6444 }
6445
6446 /*
6447 * If we didn't find an unused CRTC, don't use any.
6448 */
6449 if (!crtc) {
7173188d
CW		 6450 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6451 return false;
79e53945
JB		 6452 }
6453
fc303101
DV		 6454 intel_encoder->new_crtc = to_intel_crtc(crtc);
6455 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6456
6457 intel_crtc = to_intel_crtc(crtc);
24218aac 6458 old->dpms_mode = connector->dpms;
8261b191 6459 old->load_detect_temp = true;
d2dff872 6460 old->release_fb = NULL;
79e53945 6461
6492711d
CW		 6462 if (!mode)
6463 mode = &load_detect_mode;
79e53945 6464
d2dff872
CW		 6465 /* We need a framebuffer large enough to accommodate all accesses
6466 * that the plane may generate whilst we perform load detection.
6467 * We can not rely on the fbcon either being present (we get called
6468 * during its initialisation to detect all boot displays, or it may
6469 * not even exist) or that it is large enough to satisfy the
6470 * requested mode.
6471 */
94352cf9
DV		 6472 fb = mode_fits_in_fbdev(dev, mode);
6473 if (fb == NULL) {
d2dff872 6474 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6475 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6476 old->release_fb = fb;
d2dff872
CW		 6477 } else
6478 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6479 if (IS_ERR(fb)) {
d2dff872 6480 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6481 goto fail;
79e53945 6482 }
79e53945 6483
94352cf9 6484 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6485 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6486 if (old->release_fb)
6487 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6488 goto fail;
79e53945 6489 }
7173188d 6490
79e53945 6491 /* let the connector get through one full cycle before testing */
9d0498a2 6492 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6493
7173188d 6494 return true;
24218aac
DV		 6495fail:
6496 connector->encoder = NULL;
6497 encoder->crtc = NULL;
24218aac 6498 return false;
79e53945
JB		 6499}
6500
d2434ab7 6501void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6502 struct intel_load_detect_pipe *old)
79e53945 6503{
d2434ab7
DV		 6504 struct intel_encoder *intel_encoder =
6505 intel_attached_encoder(connector);
4ef69c7a 6506 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6507
d2dff872
CW		 6508 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6509 connector->base.id, drm_get_connector_name(connector),
6510 encoder->base.id, drm_get_encoder_name(encoder));
6511
8261b191 6512 if (old->load_detect_temp) {
fc303101
DV		 6513 struct drm_crtc *crtc = encoder->crtc;
6514
6515 to_intel_connector(connector)->new_encoder = NULL;
6516 intel_encoder->new_crtc = NULL;
6517 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6518
6519 if (old->release_fb)
6520 old->release_fb->funcs->destroy(old->release_fb);
6521
0622a53c 6522 return;
79e53945
JB		 6523 }
6524
c751ce4f 6525 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6526 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6527 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6528}
6529
6530/* Returns the clock of the currently programmed mode of the given pipe. */
6531static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6532{
6533 struct drm_i915_private *dev_priv = dev->dev_private;
6534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6535 int pipe = intel_crtc->pipe;
548f245b 6536 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6537 u32 fp;
6538 intel_clock_t clock;
6539
6540 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6541 fp = I915_READ(FP0(pipe));
79e53945 6542 else
39adb7a5 6543 fp = I915_READ(FP1(pipe));
79e53945
JB		 6544
6545 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6546 if (IS_PINEVIEW(dev)) {
6547 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6548 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6549 } else {
6550 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6551 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6552 }
6553
a6c45cf0 6554 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6555 if (IS_PINEVIEW(dev))
6556 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6557 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6558 else
6559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6560 DPLL_FPA01_P1_POST_DIV_SHIFT);
6561
6562 switch (dpll & DPLL_MODE_MASK) {
6563 case DPLLB_MODE_DAC_SERIAL:
6564 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6565 5 : 10;
6566 break;
6567 case DPLLB_MODE_LVDS:
6568 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6569 7 : 14;
6570 break;
6571 default:
28c97730 6572 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6573 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6574 return 0;
6575 }
6576
6577 /* XXX: Handle the 100Mhz refclk */
2177832f 6578 intel_clock(dev, 96000, &clock);
79e53945
JB		 6579 } else {
6580 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6581
6582 if (is_lvds) {
6583 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6584 DPLL_FPA01_P1_POST_DIV_SHIFT);
6585 clock.p2 = 14;
6586
6587 if ((dpll & PLL_REF_INPUT_MASK) ==
6588 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6589 /* XXX: might not be 66MHz */
2177832f 6590 intel_clock(dev, 66000, &clock);
79e53945 6591 } else
2177832f 6592 intel_clock(dev, 48000, &clock);
79e53945
JB		 6593 } else {
6594 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6595 clock.p1 = 2;
6596 else {
6597 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6598 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6599 }
6600 if (dpll & PLL_P2_DIVIDE_BY_4)
6601 clock.p2 = 4;
6602 else
6603 clock.p2 = 2;
6604
2177832f 6605 intel_clock(dev, 48000, &clock);
79e53945
JB		 6606 }
6607 }
6608
6609 /* XXX: It would be nice to validate the clocks, but we can't reuse
6610 * i830PllIsValid() because it relies on the xf86_config connector
6611 * configuration being accurate, which it isn't necessarily.
6612 */
6613
6614 return clock.dot;
6615}
6616
6617/** Returns the currently programmed mode of the given pipe. */
6618struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6619 struct drm_crtc *crtc)
6620{
548f245b 6621 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6623 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6624 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6625 int htot = I915_READ(HTOTAL(cpu_transcoder));
6626 int hsync = I915_READ(HSYNC(cpu_transcoder));
6627 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6628 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6629
6630 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6631 if (!mode)
6632 return NULL;
6633
6634 mode->clock = intel_crtc_clock_get(dev, crtc);
6635 mode->hdisplay = (htot & 0xffff) + 1;
6636 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6637 mode->hsync_start = (hsync & 0xffff) + 1;
6638 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6639 mode->vdisplay = (vtot & 0xffff) + 1;
6640 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6641 mode->vsync_start = (vsync & 0xffff) + 1;
6642 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6643
6644 drm_mode_set_name(mode);
79e53945
JB		 6645
6646 return mode;
6647}
6648
3dec0095 6649static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6650{
6651 struct drm_device *dev = crtc->dev;
6652 drm_i915_private_t *dev_priv = dev->dev_private;
6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6655 int dpll_reg = DPLL(pipe);
6656 int dpll;
652c393a 6657
bad720ff 6658 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6659 return;
6660
6661 if (!dev_priv->lvds_downclock_avail)
6662 return;
6663
dbdc6479 6664 dpll = I915_READ(dpll_reg);
652c393a 6665 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6666 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6667
8ac5a6d5 6668 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6669
6670 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6671 I915_WRITE(dpll_reg, dpll);
9d0498a2 6672 intel_wait_for_vblank(dev, pipe);
dbdc6479 6673
652c393a
JB		 6674 dpll = I915_READ(dpll_reg);
6675 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6676 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6677 }
652c393a
JB		 6678}
6679
6680static void intel_decrease_pllclock(struct drm_crtc *crtc)
6681{
6682 struct drm_device *dev = crtc->dev;
6683 drm_i915_private_t *dev_priv = dev->dev_private;
6684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6685
bad720ff 6686 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6687 return;
6688
6689 if (!dev_priv->lvds_downclock_avail)
6690 return;
6691
6692 /*
6693 * Since this is called by a timer, we should never get here in
6694 * the manual case.
6695 */
6696 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6697 int pipe = intel_crtc->pipe;
6698 int dpll_reg = DPLL(pipe);
6699 int dpll;
f6e5b160 6700
44d98a61 6701 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6702
8ac5a6d5 6703 assert_panel_unlocked(dev_priv, pipe);
652c393a 6704
dc257cf1 6705 dpll = I915_READ(dpll_reg);
652c393a
JB		 6706 dpll |= DISPLAY_RATE_SELECT_FPA1;
6707 I915_WRITE(dpll_reg, dpll);
9d0498a2 6708 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6709 dpll = I915_READ(dpll_reg);
6710 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6711 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6712 }
6713
6714}
6715
f047e395
CW		 6716void intel_mark_busy(struct drm_device *dev)
6717{
f047e395
CW		 6718 i915_update_gfx_val(dev->dev_private);
6719}
6720
6721void intel_mark_idle(struct drm_device *dev)
652c393a 6722{
f047e395
CW		 6723}
6724
6725void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6726{
6727 struct drm_device *dev = obj->base.dev;
652c393a 6728 struct drm_crtc *crtc;
652c393a
JB		 6729
6730 if (!i915_powersave)
6731 return;
6732
652c393a 6733 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6734 if (!crtc->fb)
6735 continue;
6736
f047e395
CW		 6737 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6738 intel_increase_pllclock(crtc);
652c393a 6739 }
652c393a
JB		 6740}
6741
f047e395 6742void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6743{
f047e395
CW		 6744 struct drm_device *dev = obj->base.dev;
6745 struct drm_crtc *crtc;
652c393a 6746
f047e395 6747 if (!i915_powersave)
acb87dfb
CW		 6748 return;
6749
652c393a
JB		 6750 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6751 if (!crtc->fb)
6752 continue;
6753
f047e395
CW		 6754 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6755 intel_decrease_pllclock(crtc);
652c393a
JB		 6756 }
6757}
6758
79e53945
JB		 6759static void intel_crtc_destroy(struct drm_crtc *crtc)
6760{
6761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6762 struct drm_device *dev = crtc->dev;
6763 struct intel_unpin_work *work;
6764 unsigned long flags;
6765
6766 spin_lock_irqsave(&dev->event_lock, flags);
6767 work = intel_crtc->unpin_work;
6768 intel_crtc->unpin_work = NULL;
6769 spin_unlock_irqrestore(&dev->event_lock, flags);
6770
6771 if (work) {
6772 cancel_work_sync(&work->work);
6773 kfree(work);
6774 }
79e53945
JB		 6775
6776 drm_crtc_cleanup(crtc);
67e77c5a 6777
79e53945
JB		 6778 kfree(intel_crtc);
6779}
6780
6b95a207
KH		 6781static void intel_unpin_work_fn(struct work_struct *__work)
6782{
6783 struct intel_unpin_work *work =
6784 container_of(__work, struct intel_unpin_work, work);
6785
6786 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6787 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6788 drm_gem_object_unreference(&work->pending_flip_obj->base);
6789 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6790
7782de3b 6791 intel_update_fbc(work->dev);
6b95a207
KH		 6792 mutex_unlock(&work->dev->struct_mutex);
6793 kfree(work);
6794}
6795
1afe3e9d 6796static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6797 struct drm_crtc *crtc)
6b95a207
KH		 6798{
6799 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6801 struct intel_unpin_work *work;
05394f39 6802 struct drm_i915_gem_object *obj;
6b95a207 6803 struct drm_pending_vblank_event *e;
95cb1b02 6804 struct timeval tvbl;
6b95a207
KH		 6805 unsigned long flags;
6806
6807 /* Ignore early vblank irqs */
6808 if (intel_crtc == NULL)
6809 return;
6810
6811 spin_lock_irqsave(&dev->event_lock, flags);
6812 work = intel_crtc->unpin_work;
6813 if (work == NULL || !work->pending) {
6814 spin_unlock_irqrestore(&dev->event_lock, flags);
6815 return;
6816 }
6817
6818 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6819
6820 if (work->event) {
6821 e = work->event;
49b14a5c 6822 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6823
49b14a5c
MK		 6824 e->event.tv_sec = tvbl.tv_sec;
6825 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6826
6b95a207
KH		 6827 list_add_tail(&e->base.link,
6828 &e->base.file_priv->event_list);
6829 wake_up_interruptible(&e->base.file_priv->event_wait);
6830 }
6831
0af7e4df
MK		 6832 drm_vblank_put(dev, intel_crtc->pipe);
6833
6b95a207
KH		 6834 spin_unlock_irqrestore(&dev->event_lock, flags);
6835
05394f39 6836 obj = work->old_fb_obj;
d9e86c0e 6837
e59f2bac 6838 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6839 &obj->pending_flip.counter);
d9e86c0e 6840
5bb61643 6841 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6842 schedule_work(&work->work);
e5510fac
JB		 6843
6844 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6845}
6846
1afe3e9d
JB		 6847void intel_finish_page_flip(struct drm_device *dev, int pipe)
6848{
6849 drm_i915_private_t *dev_priv = dev->dev_private;
6850 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6851
49b14a5c 6852 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6853}
6854
6855void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6856{
6857 drm_i915_private_t *dev_priv = dev->dev_private;
6858 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6859
49b14a5c 6860 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6861}
6862
6b95a207
KH		 6863void intel_prepare_page_flip(struct drm_device *dev, int plane)
6864{
6865 drm_i915_private_t *dev_priv = dev->dev_private;
6866 struct intel_crtc *intel_crtc =
6867 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6868 unsigned long flags;
6869
6870 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6871 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6872 if ((++intel_crtc->unpin_work->pending) > 1)
6873 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6874 } else {
6875 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6876 }
6b95a207
KH		 6877 spin_unlock_irqrestore(&dev->event_lock, flags);
6878}
6879
8c9f3aaf
JB		 6880static int intel_gen2_queue_flip(struct drm_device *dev,
6881 struct drm_crtc *crtc,
6882 struct drm_framebuffer *fb,
6883 struct drm_i915_gem_object *obj)
6884{
6885 struct drm_i915_private *dev_priv = dev->dev_private;
6886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6887 u32 flip_mask;
6d90c952 6888 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6889 int ret;
6890
6d90c952 6891 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6892 if (ret)
83d4092b 6893 goto err;
8c9f3aaf 6894
6d90c952 6895 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6896 if (ret)
83d4092b 6897 goto err_unpin;
8c9f3aaf
JB		 6898
6899 /* Can't queue multiple flips, so wait for the previous
6900 * one to finish before executing the next.
6901 */
6902 if (intel_crtc->plane)
6903 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6904 else
6905 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6906 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6907 intel_ring_emit(ring, MI_NOOP);
6908 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6909 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6910 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6911 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6912 intel_ring_emit(ring, 0); /* aux display base address, unused */
6913 intel_ring_advance(ring);
83d4092b
CW		 6914 return 0;
6915
6916err_unpin:
6917 intel_unpin_fb_obj(obj);
6918err:
8c9f3aaf
JB		 6919 return ret;
6920}
6921
6922static int intel_gen3_queue_flip(struct drm_device *dev,
6923 struct drm_crtc *crtc,
6924 struct drm_framebuffer *fb,
6925 struct drm_i915_gem_object *obj)
6926{
6927 struct drm_i915_private *dev_priv = dev->dev_private;
6928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6929 u32 flip_mask;
6d90c952 6930 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6931 int ret;
6932
6d90c952 6933 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6934 if (ret)
83d4092b 6935 goto err;
8c9f3aaf 6936
6d90c952 6937 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6938 if (ret)
83d4092b 6939 goto err_unpin;
8c9f3aaf
JB		 6940
6941 if (intel_crtc->plane)
6942 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6943 else
6944 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6945 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6946 intel_ring_emit(ring, MI_NOOP);
6947 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6948 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6949 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6950 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6951 intel_ring_emit(ring, MI_NOOP);
6952
6953 intel_ring_advance(ring);
83d4092b
CW		 6954 return 0;
6955
6956err_unpin:
6957 intel_unpin_fb_obj(obj);
6958err:
8c9f3aaf
JB		 6959 return ret;
6960}
6961
6962static int intel_gen4_queue_flip(struct drm_device *dev,
6963 struct drm_crtc *crtc,
6964 struct drm_framebuffer *fb,
6965 struct drm_i915_gem_object *obj)
6966{
6967 struct drm_i915_private *dev_priv = dev->dev_private;
6968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6969 uint32_t pf, pipesrc;
6d90c952 6970 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6971 int ret;
6972
6d90c952 6973 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6974 if (ret)
83d4092b 6975 goto err;
8c9f3aaf 6976
6d90c952 6977 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6978 if (ret)
83d4092b 6979 goto err_unpin;
8c9f3aaf
JB		 6980
6981 /* i965+ uses the linear or tiled offsets from the
6982 * Display Registers (which do not change across a page-flip)
6983 * so we need only reprogram the base address.
6984 */
6d90c952
DV		 6985 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6986 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6987 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6988 intel_ring_emit(ring,
6989 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6990 obj->tiling_mode);
8c9f3aaf
JB		 6991
6992 /* XXX Enabling the panel-fitter across page-flip is so far
6993 * untested on non-native modes, so ignore it for now.
6994 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6995 */
6996 pf = 0;
6997 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6998 intel_ring_emit(ring, pf | pipesrc);
6999 intel_ring_advance(ring);
83d4092b
CW		 7000 return 0;
7001
7002err_unpin:
7003 intel_unpin_fb_obj(obj);
7004err:
8c9f3aaf
JB		 7005 return ret;
7006}
7007
7008static int intel_gen6_queue_flip(struct drm_device *dev,
7009 struct drm_crtc *crtc,
7010 struct drm_framebuffer *fb,
7011 struct drm_i915_gem_object *obj)
7012{
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7015 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7016 uint32_t pf, pipesrc;
7017 int ret;
7018
6d90c952 7019 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7020 if (ret)
83d4092b 7021 goto err;
8c9f3aaf 7022
6d90c952 7023 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7024 if (ret)
83d4092b 7025 goto err_unpin;
8c9f3aaf 7026
6d90c952
DV		 7027 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7028 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7029 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7030 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7031
dc257cf1
DV		 7032 /* Contrary to the suggestions in the documentation,
7033 * "Enable Panel Fitter" does not seem to be required when page
7034 * flipping with a non-native mode, and worse causes a normal
7035 * modeset to fail.
7036 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7037 */
7038 pf = 0;
8c9f3aaf 7039 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7040 intel_ring_emit(ring, pf | pipesrc);
7041 intel_ring_advance(ring);
83d4092b
CW		 7042 return 0;
7043
7044err_unpin:
7045 intel_unpin_fb_obj(obj);
7046err:
8c9f3aaf
JB		 7047 return ret;
7048}
7049
7c9017e5
JB		 7050/*
7051 * On gen7 we currently use the blit ring because (in early silicon at least)
7052 * the render ring doesn't give us interrpts for page flip completion, which
7053 * means clients will hang after the first flip is queued. Fortunately the
7054 * blit ring generates interrupts properly, so use it instead.
7055 */
7056static int intel_gen7_queue_flip(struct drm_device *dev,
7057 struct drm_crtc *crtc,
7058 struct drm_framebuffer *fb,
7059 struct drm_i915_gem_object *obj)
7060{
7061 struct drm_i915_private *dev_priv = dev->dev_private;
7062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7063 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7064 uint32_t plane_bit = 0;
7c9017e5
JB		 7065 int ret;
7066
7067 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7068 if (ret)
83d4092b 7069 goto err;
7c9017e5 7070
cb05d8de
DV		 7071 switch(intel_crtc->plane) {
7072 case PLANE_A:
7073 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7074 break;
7075 case PLANE_B:
7076 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7077 break;
7078 case PLANE_C:
7079 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7080 break;
7081 default:
7082 WARN_ONCE(1, "unknown plane in flip command\n");
7083 ret = -ENODEV;
ab3951eb 7084 goto err_unpin;
cb05d8de
DV		 7085 }
7086
7c9017e5
JB		 7087 ret = intel_ring_begin(ring, 4);
7088 if (ret)
83d4092b 7089 goto err_unpin;
7c9017e5 7090
cb05d8de 7091 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7092 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7093 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7094 intel_ring_emit(ring, (MI_NOOP));
7095 intel_ring_advance(ring);
83d4092b
CW		 7096 return 0;
7097
7098err_unpin:
7099 intel_unpin_fb_obj(obj);
7100err:
7c9017e5
JB		 7101 return ret;
7102}
7103
8c9f3aaf
JB		 7104static int intel_default_queue_flip(struct drm_device *dev,
7105 struct drm_crtc *crtc,
7106 struct drm_framebuffer *fb,
7107 struct drm_i915_gem_object *obj)
7108{
7109 return -ENODEV;
7110}
7111
6b95a207
KH		 7112static int intel_crtc_page_flip(struct drm_crtc *crtc,
7113 struct drm_framebuffer *fb,
7114 struct drm_pending_vblank_event *event)
7115{
7116 struct drm_device *dev = crtc->dev;
7117 struct drm_i915_private *dev_priv = dev->dev_private;
7118 struct intel_framebuffer *intel_fb;
05394f39 7119 struct drm_i915_gem_object *obj;
6b95a207
KH		 7120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7121 struct intel_unpin_work *work;
8c9f3aaf 7122 unsigned long flags;
52e68630 7123 int ret;
6b95a207 7124
e6a595d2
VS		 7125 /* Can't change pixel format via MI display flips. */
7126 if (fb->pixel_format != crtc->fb->pixel_format)
7127 return -EINVAL;
7128
7129 /*
7130 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7131 * Note that pitch changes could also affect these register.
7132 */
7133 if (INTEL_INFO(dev)->gen > 3 &&
7134 (fb->offsets[0] != crtc->fb->offsets[0] ||
7135 fb->pitches[0] != crtc->fb->pitches[0]))
7136 return -EINVAL;
7137
6b95a207
KH		 7138 work = kzalloc(sizeof *work, GFP_KERNEL);
7139 if (work == NULL)
7140 return -ENOMEM;
7141
6b95a207
KH		 7142 work->event = event;
7143 work->dev = crtc->dev;
7144 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7145 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7146 INIT_WORK(&work->work, intel_unpin_work_fn);
7147
7317c75e
JB		 7148 ret = drm_vblank_get(dev, intel_crtc->pipe);
7149 if (ret)
7150 goto free_work;
7151
6b95a207
KH		 7152 /* We borrow the event spin lock for protecting unpin_work */
7153 spin_lock_irqsave(&dev->event_lock, flags);
7154 if (intel_crtc->unpin_work) {
7155 spin_unlock_irqrestore(&dev->event_lock, flags);
7156 kfree(work);
7317c75e 7157 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7158
7159 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7160 return -EBUSY;
7161 }
7162 intel_crtc->unpin_work = work;
7163 spin_unlock_irqrestore(&dev->event_lock, flags);
7164
7165 intel_fb = to_intel_framebuffer(fb);
7166 obj = intel_fb->obj;
7167
79158103
CW		 7168 ret = i915_mutex_lock_interruptible(dev);
7169 if (ret)
7170 goto cleanup;
6b95a207 7171
75dfca80 7172 /* Reference the objects for the scheduled work. */
05394f39
CW		 7173 drm_gem_object_reference(&work->old_fb_obj->base);
7174 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7175
7176 crtc->fb = fb;
96b099fd 7177
e1f99ce6 7178 work->pending_flip_obj = obj;
e1f99ce6 7179
4e5359cd
SF		 7180 work->enable_stall_check = true;
7181
e1f99ce6
CW		 7182 /* Block clients from rendering to the new back buffer until
7183 * the flip occurs and the object is no longer visible.
7184 */
05394f39 7185 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7186
8c9f3aaf
JB		 7187 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7188 if (ret)
7189 goto cleanup_pending;
6b95a207 7190
7782de3b 7191 intel_disable_fbc(dev);
f047e395 7192 intel_mark_fb_busy(obj);
6b95a207
KH		 7193 mutex_unlock(&dev->struct_mutex);
7194
e5510fac
JB		 7195 trace_i915_flip_request(intel_crtc->plane, obj);
7196
6b95a207 7197 return 0;
96b099fd 7198
8c9f3aaf
JB		 7199cleanup_pending:
7200 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7201 drm_gem_object_unreference(&work->old_fb_obj->base);
7202 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7203 mutex_unlock(&dev->struct_mutex);
7204
79158103 7205cleanup:
96b099fd
CW		 7206 spin_lock_irqsave(&dev->event_lock, flags);
7207 intel_crtc->unpin_work = NULL;
7208 spin_unlock_irqrestore(&dev->event_lock, flags);
7209
7317c75e
JB		 7210 drm_vblank_put(dev, intel_crtc->pipe);
7211free_work:
96b099fd
CW		 7212 kfree(work);
7213
7214 return ret;
6b95a207
KH		 7215}
7216
f6e5b160 7217static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7218 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7219 .load_lut = intel_crtc_load_lut,
976f8a20 7220 .disable = intel_crtc_noop,
f6e5b160
CW		 7221};
7222
6ed0f796 7223bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7224{
6ed0f796
DV		 7225 struct intel_encoder *other_encoder;
7226 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7227
6ed0f796
DV		 7228 if (WARN_ON(!crtc))
7229 return false;
7230
7231 list_for_each_entry(other_encoder,
7232 &crtc->dev->mode_config.encoder_list,
7233 base.head) {
7234
7235 if (&other_encoder->new_crtc->base != crtc ||
7236 encoder == other_encoder)
7237 continue;
7238 else
7239 return true;
f47166d2
CW		 7240 }
7241
6ed0f796
DV		 7242 return false;
7243}
47f1c6c9 7244
50f56119
DV		 7245static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7246 struct drm_crtc *crtc)
7247{
7248 struct drm_device *dev;
7249 struct drm_crtc *tmp;
7250 int crtc_mask = 1;
47f1c6c9 7251
50f56119 7252 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7253
50f56119 7254 dev = crtc->dev;
47f1c6c9 7255
50f56119
DV		 7256 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7257 if (tmp == crtc)
7258 break;
7259 crtc_mask <<= 1;
7260 }
47f1c6c9 7261
50f56119
DV		 7262 if (encoder->possible_crtcs & crtc_mask)
7263 return true;
7264 return false;
47f1c6c9 7265}
79e53945 7266
9a935856
DV		 7267/**
7268 * intel_modeset_update_staged_output_state
7269 *
7270 * Updates the staged output configuration state, e.g. after we've read out the
7271 * current hw state.
7272 */
7273static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7274{
9a935856
DV		 7275 struct intel_encoder *encoder;
7276 struct intel_connector *connector;
f6e5b160 7277
9a935856
DV		 7278 list_for_each_entry(connector, &dev->mode_config.connector_list,
7279 base.head) {
7280 connector->new_encoder =
7281 to_intel_encoder(connector->base.encoder);
7282 }
f6e5b160 7283
9a935856
DV		 7284 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7285 base.head) {
7286 encoder->new_crtc =
7287 to_intel_crtc(encoder->base.crtc);
7288 }
f6e5b160
CW		 7289}
7290
9a935856
DV		 7291/**
7292 * intel_modeset_commit_output_state
7293 *
7294 * This function copies the stage display pipe configuration to the real one.
7295 */
7296static void intel_modeset_commit_output_state(struct drm_device *dev)
7297{
7298 struct intel_encoder *encoder;
7299 struct intel_connector *connector;
f6e5b160 7300
9a935856
DV		 7301 list_for_each_entry(connector, &dev->mode_config.connector_list,
7302 base.head) {
7303 connector->base.encoder = &connector->new_encoder->base;
7304 }
f6e5b160 7305
9a935856
DV		 7306 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7307 base.head) {
7308 encoder->base.crtc = &encoder->new_crtc->base;
7309 }
7310}
7311
7758a113
DV		 7312static struct drm_display_mode *
7313intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7314 struct drm_display_mode *mode)
ee7b9f93 7315{
7758a113
DV		 7316 struct drm_device *dev = crtc->dev;
7317 struct drm_display_mode *adjusted_mode;
7318 struct drm_encoder_helper_funcs *encoder_funcs;
7319 struct intel_encoder *encoder;
ee7b9f93 7320
7758a113
DV		 7321 adjusted_mode = drm_mode_duplicate(dev, mode);
7322 if (!adjusted_mode)
7323 return ERR_PTR(-ENOMEM);
7324
7325 /* Pass our mode to the connectors and the CRTC to give them a chance to
7326 * adjust it according to limitations or connector properties, and also
7327 * a chance to reject the mode entirely.
7328 */
7329 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7330 base.head) {
7331
7332 if (&encoder->new_crtc->base != crtc)
7333 continue;
7334 encoder_funcs = encoder->base.helper_private;
7335 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7336 adjusted_mode))) {
7337 DRM_DEBUG_KMS("Encoder fixup failed\n");
7338 goto fail;
7339 }
ee7b9f93
JB		 7340 }
7341
7758a113
DV		 7342 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7343 DRM_DEBUG_KMS("CRTC fixup failed\n");
7344 goto fail;
ee7b9f93 7345 }
7758a113
DV		 7346 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7347
7348 return adjusted_mode;
7349fail:
7350 drm_mode_destroy(dev, adjusted_mode);
7351 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7352}
7353
e2e1ed41
DV		 7354/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7355 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7356static void
7357intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7358 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7359{
7360 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7361 struct drm_device *dev = crtc->dev;
7362 struct intel_encoder *encoder;
7363 struct intel_connector *connector;
7364 struct drm_crtc *tmp_crtc;
79e53945 7365
e2e1ed41 7366 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7367
e2e1ed41
DV		 7368 /* Check which crtcs have changed outputs connected to them, these need
7369 * to be part of the prepare_pipes mask. We don't (yet) support global
7370 * modeset across multiple crtcs, so modeset_pipes will only have one
7371 * bit set at most. */
7372 list_for_each_entry(connector, &dev->mode_config.connector_list,
7373 base.head) {
7374 if (connector->base.encoder == &connector->new_encoder->base)
7375 continue;
79e53945 7376
e2e1ed41
DV		 7377 if (connector->base.encoder) {
7378 tmp_crtc = connector->base.encoder->crtc;
7379
7380 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7381 }
7382
7383 if (connector->new_encoder)
7384 *prepare_pipes |=
7385 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7386 }
7387
e2e1ed41
DV		 7388 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7389 base.head) {
7390 if (encoder->base.crtc == &encoder->new_crtc->base)
7391 continue;
7392
7393 if (encoder->base.crtc) {
7394 tmp_crtc = encoder->base.crtc;
7395
7396 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7397 }
7398
7399 if (encoder->new_crtc)
7400 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7401 }
7402
e2e1ed41
DV		 7403 /* Check for any pipes that will be fully disabled ... */
7404 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7405 base.head) {
7406 bool used = false;
22fd0fab 7407
e2e1ed41
DV		 7408 /* Don't try to disable disabled crtcs. */
7409 if (!intel_crtc->base.enabled)
7410 continue;
7e7d76c3 7411
e2e1ed41
DV		 7412 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7413 base.head) {
7414 if (encoder->new_crtc == intel_crtc)
7415 used = true;
7416 }
7417
7418 if (!used)
7419 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7420 }
7421
e2e1ed41
DV		 7422
7423 /* set_mode is also used to update properties on life display pipes. */
7424 intel_crtc = to_intel_crtc(crtc);
7425 if (crtc->enabled)
7426 *prepare_pipes |= 1 << intel_crtc->pipe;
7427
7428 /* We only support modeset on one single crtc, hence we need to do that
7429 * only for the passed in crtc iff we change anything else than just
7430 * disable crtcs.
7431 *
7432 * This is actually not true, to be fully compatible with the old crtc
7433 * helper we automatically disable _any_ output (i.e. doesn't need to be
7434 * connected to the crtc we're modesetting on) if it's disconnected.
7435 * Which is a rather nutty api (since changed the output configuration
7436 * without userspace's explicit request can lead to confusion), but
7437 * alas. Hence we currently need to modeset on all pipes we prepare. */
7438 if (*prepare_pipes)
7439 *modeset_pipes = *prepare_pipes;
7440
7441 /* ... and mask these out. */
7442 *modeset_pipes &= ~(*disable_pipes);
7443 *prepare_pipes &= ~(*disable_pipes);
7444}
7445
ea9d758d
DV		 7446static bool intel_crtc_in_use(struct drm_crtc *crtc)
7447{
7448 struct drm_encoder *encoder;
7449 struct drm_device *dev = crtc->dev;
7450
7451 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7452 if (encoder->crtc == crtc)
7453 return true;
7454
7455 return false;
7456}
7457
7458static void
7459intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7460{
7461 struct intel_encoder *intel_encoder;
7462 struct intel_crtc *intel_crtc;
7463 struct drm_connector *connector;
7464
7465 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7466 base.head) {
7467 if (!intel_encoder->base.crtc)
7468 continue;
7469
7470 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7471
7472 if (prepare_pipes & (1 << intel_crtc->pipe))
7473 intel_encoder->connectors_active = false;
7474 }
7475
7476 intel_modeset_commit_output_state(dev);
7477
7478 /* Update computed state. */
7479 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7480 base.head) {
7481 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7482 }
7483
7484 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7485 if (!connector->encoder || !connector->encoder->crtc)
7486 continue;
7487
7488 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7489
7490 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7491 struct drm_property *dpms_property =
7492 dev->mode_config.dpms_property;
7493
ea9d758d 7494 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7495 drm_connector_property_set_value(connector,
7496 dpms_property,
7497 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7498
7499 intel_encoder = to_intel_encoder(connector->encoder);
7500 intel_encoder->connectors_active = true;
7501 }
7502 }
7503
7504}
7505
25c5b266
DV		 7506#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7507 list_for_each_entry((intel_crtc), \
7508 &(dev)->mode_config.crtc_list, \
7509 base.head) \
7510 if (mask & (1 <<(intel_crtc)->pipe)) \
7511
b980514c 7512void
8af6cf88
DV		 7513intel_modeset_check_state(struct drm_device *dev)
7514{
7515 struct intel_crtc *crtc;
7516 struct intel_encoder *encoder;
7517 struct intel_connector *connector;
7518
7519 list_for_each_entry(connector, &dev->mode_config.connector_list,
7520 base.head) {
7521 /* This also checks the encoder/connector hw state with the
7522 * ->get_hw_state callbacks. */
7523 intel_connector_check_state(connector);
7524
7525 WARN(&connector->new_encoder->base != connector->base.encoder,
7526 "connector's staged encoder doesn't match current encoder\n");
7527 }
7528
7529 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7530 base.head) {
7531 bool enabled = false;
7532 bool active = false;
7533 enum pipe pipe, tracked_pipe;
7534
7535 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7536 encoder->base.base.id,
7537 drm_get_encoder_name(&encoder->base));
7538
7539 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7540 "encoder's stage crtc doesn't match current crtc\n");
7541 WARN(encoder->connectors_active && !encoder->base.crtc,
7542 "encoder's active_connectors set, but no crtc\n");
7543
7544 list_for_each_entry(connector, &dev->mode_config.connector_list,
7545 base.head) {
7546 if (connector->base.encoder != &encoder->base)
7547 continue;
7548 enabled = true;
7549 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7550 active = true;
7551 }
7552 WARN(!!encoder->base.crtc != enabled,
7553 "encoder's enabled state mismatch "
7554 "(expected %i, found %i)\n",
7555 !!encoder->base.crtc, enabled);
7556 WARN(active && !encoder->base.crtc,
7557 "active encoder with no crtc\n");
7558
7559 WARN(encoder->connectors_active != active,
7560 "encoder's computed active state doesn't match tracked active state "
7561 "(expected %i, found %i)\n", active, encoder->connectors_active);
7562
7563 active = encoder->get_hw_state(encoder, &pipe);
7564 WARN(active != encoder->connectors_active,
7565 "encoder's hw state doesn't match sw tracking "
7566 "(expected %i, found %i)\n",
7567 encoder->connectors_active, active);
7568
7569 if (!encoder->base.crtc)
7570 continue;
7571
7572 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7573 WARN(active && pipe != tracked_pipe,
7574 "active encoder's pipe doesn't match"
7575 "(expected %i, found %i)\n",
7576 tracked_pipe, pipe);
7577
7578 }
7579
7580 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7581 base.head) {
7582 bool enabled = false;
7583 bool active = false;
7584
7585 DRM_DEBUG_KMS("[CRTC:%d]\n",
7586 crtc->base.base.id);
7587
7588 WARN(crtc->active && !crtc->base.enabled,
7589 "active crtc, but not enabled in sw tracking\n");
7590
7591 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7592 base.head) {
7593 if (encoder->base.crtc != &crtc->base)
7594 continue;
7595 enabled = true;
7596 if (encoder->connectors_active)
7597 active = true;
7598 }
7599 WARN(active != crtc->active,
7600 "crtc's computed active state doesn't match tracked active state "
7601 "(expected %i, found %i)\n", active, crtc->active);
7602 WARN(enabled != crtc->base.enabled,
7603 "crtc's computed enabled state doesn't match tracked enabled state "
7604 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7605
7606 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7607 }
7608}
7609
a6778b3c
DV		 7610bool intel_set_mode(struct drm_crtc *crtc,
7611 struct drm_display_mode *mode,
94352cf9 7612 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7613{
7614 struct drm_device *dev = crtc->dev;
dbf2b54e 7615 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7616 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 7617 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 7618 struct drm_encoder *encoder;
25c5b266
DV		 7619 struct intel_crtc *intel_crtc;
7620 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7621 bool ret = true;
7622
e2e1ed41 7623 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7624 &prepare_pipes, &disable_pipes);
7625
7626 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7627 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7628
976f8a20
DV		 7629 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7630 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7631
a6778b3c
DV		 7632 saved_hwmode = crtc->hwmode;
7633 saved_mode = crtc->mode;
a6778b3c 7634
25c5b266
DV		 7635 /* Hack: Because we don't (yet) support global modeset on multiple
7636 * crtcs, we don't keep track of the new mode for more than one crtc.
7637 * Hence simply check whether any bit is set in modeset_pipes in all the
7638 * pieces of code that are not yet converted to deal with mutliple crtcs
7639 * changing their mode at the same time. */
7640 adjusted_mode = NULL;
7641 if (modeset_pipes) {
7642 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7643 if (IS_ERR(adjusted_mode)) {
7644 return false;
7645 }
25c5b266 7646 }
a6778b3c 7647
ea9d758d
DV		 7648 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7649 if (intel_crtc->base.enabled)
7650 dev_priv->display.crtc_disable(&intel_crtc->base);
7651 }
a6778b3c 7652
6c4c86f5
DV		 7653 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7654 * to set it here already despite that we pass it down the callchain.
7655 */
7656 if (modeset_pipes)
25c5b266 7657 crtc->mode = *mode;
7758a113 7658
ea9d758d
DV		 7659 /* Only after disabling all output pipelines that will be changed can we
7660 * update the the output configuration. */
7661 intel_modeset_update_state(dev, prepare_pipes);
7662
47fab737
DV		 7663 if (dev_priv->display.modeset_global_resources)
7664 dev_priv->display.modeset_global_resources(dev);
7665
a6778b3c
DV		 7666 /* Set up the DPLL and any encoders state that needs to adjust or depend
7667 * on the DPLL.
7668 */
25c5b266
DV		 7669 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7670 ret = !intel_crtc_mode_set(&intel_crtc->base,
7671 mode, adjusted_mode,
7672 x, y, fb);
7673 if (!ret)
7674 goto done;
a6778b3c 7675
25c5b266 7676 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7677
25c5b266
DV		 7678 if (encoder->crtc != &intel_crtc->base)
7679 continue;
a6778b3c 7680
25c5b266
DV		 7681 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7682 encoder->base.id, drm_get_encoder_name(encoder),
7683 mode->base.id, mode->name);
7684 encoder_funcs = encoder->helper_private;
7685 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7686 }
a6778b3c
DV		 7687 }
7688
7689 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7690 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7691 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7692
25c5b266
DV		 7693 if (modeset_pipes) {
7694 /* Store real post-adjustment hardware mode. */
7695 crtc->hwmode = *adjusted_mode;
a6778b3c 7696
25c5b266
DV		 7697 /* Calculate and store various constants which
7698 * are later needed by vblank and swap-completion
7699 * timestamping. They are derived from true hwmode.
7700 */
7701 drm_calc_timestamping_constants(crtc);
7702 }
a6778b3c
DV		 7703
7704 /* FIXME: add subpixel order */
7705done:
7706 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7707 if (!ret && crtc->enabled) {
a6778b3c
DV		 7708 crtc->hwmode = saved_hwmode;
7709 crtc->mode = saved_mode;
8af6cf88
DV		 7710 } else {
7711 intel_modeset_check_state(dev);
a6778b3c
DV		 7712 }
7713
7714 return ret;
7715}
7716
25c5b266
DV		 7717#undef for_each_intel_crtc_masked
7718
d9e55608
DV		 7719static void intel_set_config_free(struct intel_set_config *config)
7720{
7721 if (!config)
7722 return;
7723
1aa4b628
DV		 7724 kfree(config->save_connector_encoders);
7725 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7726 kfree(config);
7727}
7728
85f9eb71
DV		 7729static int intel_set_config_save_state(struct drm_device *dev,
7730 struct intel_set_config *config)
7731{
85f9eb71
DV		 7732 struct drm_encoder *encoder;
7733 struct drm_connector *connector;
7734 int count;
7735
1aa4b628
DV		 7736 config->save_encoder_crtcs =
7737 kcalloc(dev->mode_config.num_encoder,
7738 sizeof(struct drm_crtc *), GFP_KERNEL);
7739 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7740 return -ENOMEM;
7741
1aa4b628
DV		 7742 config->save_connector_encoders =
7743 kcalloc(dev->mode_config.num_connector,
7744 sizeof(struct drm_encoder *), GFP_KERNEL);
7745 if (!config->save_connector_encoders)
85f9eb71
DV		 7746 return -ENOMEM;
7747
7748 /* Copy data. Note that driver private data is not affected.
7749 * Should anything bad happen only the expected state is
7750 * restored, not the drivers personal bookkeeping.
7751 */
85f9eb71
DV		 7752 count = 0;
7753 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7754 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7755 }
7756
7757 count = 0;
7758 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7759 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7760 }
7761
7762 return 0;
7763}
7764
7765static void intel_set_config_restore_state(struct drm_device *dev,
7766 struct intel_set_config *config)
7767{
9a935856
DV		 7768 struct intel_encoder *encoder;
7769 struct intel_connector *connector;
85f9eb71
DV		 7770 int count;
7771
85f9eb71 7772 count = 0;
9a935856
DV		 7773 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7774 encoder->new_crtc =
7775 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7776 }
7777
7778 count = 0;
9a935856
DV		 7779 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7780 connector->new_encoder =
7781 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7782 }
7783}
7784
5e2b584e
DV		 7785static void
7786intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7787 struct intel_set_config *config)
7788{
7789
7790 /* We should be able to check here if the fb has the same properties
7791 * and then just flip_or_move it */
7792 if (set->crtc->fb != set->fb) {
7793 /* If we have no fb then treat it as a full mode set */
7794 if (set->crtc->fb == NULL) {
7795 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7796 config->mode_changed = true;
7797 } else if (set->fb == NULL) {
7798 config->mode_changed = true;
7799 } else if (set->fb->depth != set->crtc->fb->depth) {
7800 config->mode_changed = true;
7801 } else if (set->fb->bits_per_pixel !=
7802 set->crtc->fb->bits_per_pixel) {
7803 config->mode_changed = true;
7804 } else
7805 config->fb_changed = true;
7806 }
7807
835c5873 7808 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7809 config->fb_changed = true;
7810
7811 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7812 DRM_DEBUG_KMS("modes are different, full mode set\n");
7813 drm_mode_debug_printmodeline(&set->crtc->mode);
7814 drm_mode_debug_printmodeline(set->mode);
7815 config->mode_changed = true;
7816 }
7817}
7818
2e431051 7819static int
9a935856
DV		 7820intel_modeset_stage_output_state(struct drm_device *dev,
7821 struct drm_mode_set *set,
7822 struct intel_set_config *config)
50f56119 7823{
85f9eb71 7824 struct drm_crtc *new_crtc;
9a935856
DV		 7825 struct intel_connector *connector;
7826 struct intel_encoder *encoder;
2e431051 7827 int count, ro;
50f56119 7828
9a935856
DV		 7829 /* The upper layers ensure that we either disabl a crtc or have a list
7830 * of connectors. For paranoia, double-check this. */
7831 WARN_ON(!set->fb && (set->num_connectors != 0));
7832 WARN_ON(set->fb && (set->num_connectors == 0));
7833
50f56119 7834 count = 0;
9a935856
DV		 7835 list_for_each_entry(connector, &dev->mode_config.connector_list,
7836 base.head) {
7837 /* Otherwise traverse passed in connector list and get encoders
7838 * for them. */
50f56119 7839 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7840 if (set->connectors[ro] == &connector->base) {
7841 connector->new_encoder = connector->encoder;
50f56119
DV		 7842 break;
7843 }
7844 }
7845
9a935856
DV		 7846 /* If we disable the crtc, disable all its connectors. Also, if
7847 * the connector is on the changing crtc but not on the new
7848 * connector list, disable it. */
7849 if ((!set->fb || ro == set->num_connectors) &&
7850 connector->base.encoder &&
7851 connector->base.encoder->crtc == set->crtc) {
7852 connector->new_encoder = NULL;
7853
7854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7855 connector->base.base.id,
7856 drm_get_connector_name(&connector->base));
7857 }
7858
7859
7860 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7861 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7862 config->mode_changed = true;
50f56119 7863 }
9a935856
DV		 7864
7865 /* Disable all disconnected encoders. */
7866 if (connector->base.status == connector_status_disconnected)
7867 connector->new_encoder = NULL;
50f56119 7868 }
9a935856 7869 /* connector->new_encoder is now updated for all connectors. */
50f56119 7870
9a935856 7871 /* Update crtc of enabled connectors. */
50f56119 7872 count = 0;
9a935856
DV		 7873 list_for_each_entry(connector, &dev->mode_config.connector_list,
7874 base.head) {
7875 if (!connector->new_encoder)
50f56119
DV		 7876 continue;
7877
9a935856 7878 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7879
7880 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7881 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7882 new_crtc = set->crtc;
7883 }
7884
7885 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7886 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7887 new_crtc)) {
5e2b584e 7888 return -EINVAL;
50f56119 7889 }
9a935856
DV		 7890 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7891
7892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7893 connector->base.base.id,
7894 drm_get_connector_name(&connector->base),
7895 new_crtc->base.id);
7896 }
7897
7898 /* Check for any encoders that needs to be disabled. */
7899 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7900 base.head) {
7901 list_for_each_entry(connector,
7902 &dev->mode_config.connector_list,
7903 base.head) {
7904 if (connector->new_encoder == encoder) {
7905 WARN_ON(!connector->new_encoder->new_crtc);
7906
7907 goto next_encoder;
7908 }
7909 }
7910 encoder->new_crtc = NULL;
7911next_encoder:
7912 /* Only now check for crtc changes so we don't miss encoders
7913 * that will be disabled. */
7914 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7915 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7916 config->mode_changed = true;
50f56119
DV		 7917 }
7918 }
9a935856 7919 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7920
2e431051
DV		 7921 return 0;
7922}
7923
7924static int intel_crtc_set_config(struct drm_mode_set *set)
7925{
7926 struct drm_device *dev;
2e431051
DV		 7927 struct drm_mode_set save_set;
7928 struct intel_set_config *config;
7929 int ret;
2e431051 7930
8d3e375e
DV		 7931 BUG_ON(!set);
7932 BUG_ON(!set->crtc);
7933 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7934
7935 if (!set->mode)
7936 set->fb = NULL;
7937
431e50f7
DV		 7938 /* The fb helper likes to play gross jokes with ->mode_set_config.
7939 * Unfortunately the crtc helper doesn't do much at all for this case,
7940 * so we have to cope with this madness until the fb helper is fixed up. */
7941 if (set->fb && set->num_connectors == 0)
7942 return 0;
7943
2e431051
DV		 7944 if (set->fb) {
7945 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7946 set->crtc->base.id, set->fb->base.id,
7947 (int)set->num_connectors, set->x, set->y);
7948 } else {
7949 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7950 }
7951
7952 dev = set->crtc->dev;
7953
7954 ret = -ENOMEM;
7955 config = kzalloc(sizeof(*config), GFP_KERNEL);
7956 if (!config)
7957 goto out_config;
7958
7959 ret = intel_set_config_save_state(dev, config);
7960 if (ret)
7961 goto out_config;
7962
7963 save_set.crtc = set->crtc;
7964 save_set.mode = &set->crtc->mode;
7965 save_set.x = set->crtc->x;
7966 save_set.y = set->crtc->y;
7967 save_set.fb = set->crtc->fb;
7968
7969 /* Compute whether we need a full modeset, only an fb base update or no
7970 * change at all. In the future we might also check whether only the
7971 * mode changed, e.g. for LVDS where we only change the panel fitter in
7972 * such cases. */
7973 intel_set_config_compute_mode_changes(set, config);
7974
9a935856 7975 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7976 if (ret)
7977 goto fail;
7978
5e2b584e 7979 if (config->mode_changed) {
87f1faa6 7980 if (set->mode) {
50f56119
DV		 7981 DRM_DEBUG_KMS("attempting to set mode from"
7982 " userspace\n");
7983 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7984 }
7985
7986 if (!intel_set_mode(set->crtc, set->mode,
7987 set->x, set->y, set->fb)) {
7988 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7989 set->crtc->base.id);
7990 ret = -EINVAL;
7991 goto fail;
7992 }
5e2b584e 7993 } else if (config->fb_changed) {
4f660f49 7994 ret = intel_pipe_set_base(set->crtc,
94352cf9 7995 set->x, set->y, set->fb);
50f56119
DV		 7996 }
7997
d9e55608
DV		 7998 intel_set_config_free(config);
7999
50f56119
DV		 8000 return 0;
8001
8002fail:
85f9eb71 8003 intel_set_config_restore_state(dev, config);
50f56119
DV		 8004
8005 /* Try to restore the config */
5e2b584e 8006 if (config->mode_changed &&
a6778b3c
DV		 8007 !intel_set_mode(save_set.crtc, save_set.mode,
8008 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8009 DRM_ERROR("failed to restore config after modeset failure\n");
8010
d9e55608
DV		 8011out_config:
8012 intel_set_config_free(config);
50f56119
DV		 8013 return ret;
8014}
8015
f6e5b160 8016static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8017 .cursor_set = intel_crtc_cursor_set,
8018 .cursor_move = intel_crtc_cursor_move,
8019 .gamma_set = intel_crtc_gamma_set,
50f56119 8020 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8021 .destroy = intel_crtc_destroy,
8022 .page_flip = intel_crtc_page_flip,
8023};
8024
79f689aa
PZ		 8025static void intel_cpu_pll_init(struct drm_device *dev)
8026{
8027 if (IS_HASWELL(dev))
8028 intel_ddi_pll_init(dev);
8029}
8030
ee7b9f93
JB		 8031static void intel_pch_pll_init(struct drm_device *dev)
8032{
8033 drm_i915_private_t *dev_priv = dev->dev_private;
8034 int i;
8035
8036 if (dev_priv->num_pch_pll == 0) {
8037 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8038 return;
8039 }
8040
8041 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8042 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8043 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8044 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8045 }
8046}
8047
b358d0a6 8048static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8049{
22fd0fab 8050 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8051 struct intel_crtc *intel_crtc;
8052 int i;
8053
8054 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8055 if (intel_crtc == NULL)
8056 return;
8057
8058 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8059
8060 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8061 for (i = 0; i < 256; i++) {
8062 intel_crtc->lut_r[i] = i;
8063 intel_crtc->lut_g[i] = i;
8064 intel_crtc->lut_b[i] = i;
8065 }
8066
80824003
JB		 8067 /* Swap pipes & planes for FBC on pre-965 */
8068 intel_crtc->pipe = pipe;
8069 intel_crtc->plane = pipe;
a5c961d1 8070 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8071 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8072 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8073 intel_crtc->plane = !pipe;
80824003
JB		 8074 }
8075
22fd0fab
JB		 8076 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8077 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8078 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8079 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8080
5a354204 8081 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8082
79e53945 8083 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8084}
8085
08d7b3d1 8086int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8087 struct drm_file *file)
08d7b3d1 8088{
08d7b3d1 8089 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8090 struct drm_mode_object *drmmode_obj;
8091 struct intel_crtc *crtc;
08d7b3d1 8092
1cff8f6b
DV		 8093 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8094 return -ENODEV;
08d7b3d1 8095
c05422d5
DV		 8096 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8097 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8098
c05422d5 8099 if (!drmmode_obj) {
08d7b3d1
CW		 8100 DRM_ERROR("no such CRTC id\n");
8101 return -EINVAL;
8102 }
8103
c05422d5
DV		 8104 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8105 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8106
c05422d5 8107 return 0;
08d7b3d1
CW		 8108}
8109
66a9278e 8110static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8111{
66a9278e
DV		 8112 struct drm_device *dev = encoder->base.dev;
8113 struct intel_encoder *source_encoder;
79e53945 8114 int index_mask = 0;
79e53945
JB		 8115 int entry = 0;
8116
66a9278e
DV		 8117 list_for_each_entry(source_encoder,
8118 &dev->mode_config.encoder_list, base.head) {
8119
8120 if (encoder == source_encoder)
79e53945 8121 index_mask |= (1 << entry);
66a9278e
DV		 8122
8123 /* Intel hw has only one MUX where enocoders could be cloned. */
8124 if (encoder->cloneable && source_encoder->cloneable)
8125 index_mask |= (1 << entry);
8126
79e53945
JB		 8127 entry++;
8128 }
4ef69c7a 8129
79e53945
JB		 8130 return index_mask;
8131}
8132
4d302442
CW		 8133static bool has_edp_a(struct drm_device *dev)
8134{
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8136
8137 if (!IS_MOBILE(dev))
8138 return false;
8139
8140 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8141 return false;
8142
8143 if (IS_GEN5(dev) &&
8144 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8145 return false;
8146
8147 return true;
8148}
8149
79e53945
JB		 8150static void intel_setup_outputs(struct drm_device *dev)
8151{
725e30ad 8152 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8153 struct intel_encoder *encoder;
cb0953d7 8154 bool dpd_is_edp = false;
f3cfcba6 8155 bool has_lvds;
79e53945 8156
f3cfcba6 8157 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8158 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8159 /* disable the panel fitter on everything but LVDS */
8160 I915_WRITE(PFIT_CONTROL, 0);
8161 }
79e53945 8162
bad720ff 8163 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8164 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8165
4d302442 8166 if (has_edp_a(dev))
ab9d7c30 8167 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8168
cb0953d7 8169 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8170 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8171 }
8172
8173 intel_crt_init(dev);
8174
0e72a5b5
ED		 8175 if (IS_HASWELL(dev)) {
8176 int found;
8177
8178 /* Haswell uses DDI functions to detect digital outputs */
8179 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8180 /* DDI A only supports eDP */
8181 if (found)
8182 intel_ddi_init(dev, PORT_A);
8183
8184 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8185 * register */
8186 found = I915_READ(SFUSE_STRAP);
8187
8188 if (found & SFUSE_STRAP_DDIB_DETECTED)
8189 intel_ddi_init(dev, PORT_B);
8190 if (found & SFUSE_STRAP_DDIC_DETECTED)
8191 intel_ddi_init(dev, PORT_C);
8192 if (found & SFUSE_STRAP_DDID_DETECTED)
8193 intel_ddi_init(dev, PORT_D);
8194 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8195 int found;
8196
30ad48b7 8197 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8198 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8199 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8200 if (!found)
08d644ad 8201 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8202 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8203 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8204 }
8205
8206 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8207 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8208
b708a1d5 8209 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8210 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8211
5eb08b69 8212 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8213 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8214
cb0953d7 8215 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8216 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8217 } else if (IS_VALLEYVIEW(dev)) {
8218 int found;
8219
19c03924
GB		 8220 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8221 if (I915_READ(DP_C) & DP_DETECTED)
8222 intel_dp_init(dev, DP_C, PORT_C);
8223
4a87d65d
JB		 8224 if (I915_READ(SDVOB) & PORT_DETECTED) {
8225 /* SDVOB multiplex with HDMIB */
8226 found = intel_sdvo_init(dev, SDVOB, true);
8227 if (!found)
08d644ad 8228 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8229 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8230 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8231 }
8232
8233 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8234 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8235
103a196f 8236 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8237 bool found = false;
7d57382e 8238
725e30ad 8239 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8240 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8241 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8242 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8243 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8244 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8245 }
27185ae1 8246
b01f2c3a
JB		 8247 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8248 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8249 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8250 }
725e30ad 8251 }
13520b05
KH		 8252
8253 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8254
b01f2c3a
JB		 8255 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8256 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8257 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8258 }
27185ae1
ML		 8259
8260 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8261
b01f2c3a
JB		 8262 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8263 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8264 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8265 }
8266 if (SUPPORTS_INTEGRATED_DP(dev)) {
8267 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8268 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8269 }
725e30ad 8270 }
27185ae1 8271
b01f2c3a
JB		 8272 if (SUPPORTS_INTEGRATED_DP(dev) &&
8273 (I915_READ(DP_D) & DP_DETECTED)) {
8274 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8275 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8276 }
bad720ff 8277 } else if (IS_GEN2(dev))
79e53945
JB		 8278 intel_dvo_init(dev);
8279
103a196f 8280 if (SUPPORTS_TV(dev))
79e53945
JB		 8281 intel_tv_init(dev);
8282
4ef69c7a
CW		 8283 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8284 encoder->base.possible_crtcs = encoder->crtc_mask;
8285 encoder->base.possible_clones =
66a9278e 8286 intel_encoder_clones(encoder);
79e53945 8287 }
47356eb6 8288
40579abe 8289 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8290 ironlake_init_pch_refclk(dev);
79e53945
JB		 8291}
8292
8293static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8294{
8295 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8296
8297 drm_framebuffer_cleanup(fb);
05394f39 8298 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8299
8300 kfree(intel_fb);
8301}
8302
8303static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8304 struct drm_file *file,
79e53945
JB		 8305 unsigned int *handle)
8306{
8307 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8308 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8309
05394f39 8310 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8311}
8312
8313static const struct drm_framebuffer_funcs intel_fb_funcs = {
8314 .destroy = intel_user_framebuffer_destroy,
8315 .create_handle = intel_user_framebuffer_create_handle,
8316};
8317
38651674
DA		 8318int intel_framebuffer_init(struct drm_device *dev,
8319 struct intel_framebuffer *intel_fb,
308e5bcb 8320 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8321 struct drm_i915_gem_object *obj)
79e53945 8322{
79e53945
JB		 8323 int ret;
8324
05394f39 8325 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8326 return -EINVAL;
8327
308e5bcb 8328 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8329 return -EINVAL;
8330
308e5bcb 8331 switch (mode_cmd->pixel_format) {
04b3924d
VS		 8332 case DRM_FORMAT_RGB332:
8333 case DRM_FORMAT_RGB565:
8334 case DRM_FORMAT_XRGB8888:
b250da79 8335 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 8336 case DRM_FORMAT_ARGB8888:
8337 case DRM_FORMAT_XRGB2101010:
8338 case DRM_FORMAT_ARGB2101010:
308e5bcb 8339 /* RGB formats are common across chipsets */
b5626747 8340 break;
04b3924d
VS		 8341 case DRM_FORMAT_YUYV:
8342 case DRM_FORMAT_UYVY:
8343 case DRM_FORMAT_YVYU:
8344 case DRM_FORMAT_VYUY:
57cd6508
CW		 8345 break;
8346 default:
aca25848
ED		 8347 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8348 mode_cmd->pixel_format);
57cd6508
CW		 8349 return -EINVAL;
8350 }
8351
79e53945
JB		 8352 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8353 if (ret) {
8354 DRM_ERROR("framebuffer init failed %d\n", ret);
8355 return ret;
8356 }
8357
8358 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8359 intel_fb->obj = obj;
79e53945
JB		 8360 return 0;
8361}
8362
79e53945
JB		 8363static struct drm_framebuffer *
8364intel_user_framebuffer_create(struct drm_device *dev,
8365 struct drm_file *filp,
308e5bcb 8366 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8367{
05394f39 8368 struct drm_i915_gem_object *obj;
79e53945 8369
308e5bcb
JB		 8370 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8371 mode_cmd->handles[0]));
c8725226 8372 if (&obj->base == NULL)
cce13ff7 8373 return ERR_PTR(-ENOENT);
79e53945 8374
d2dff872 8375 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8376}
8377
79e53945 8378static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8379 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8380 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8381};
8382
e70236a8
JB		 8383/* Set up chip specific display functions */
8384static void intel_init_display(struct drm_device *dev)
8385{
8386 struct drm_i915_private *dev_priv = dev->dev_private;
8387
8388 /* We always want a DPMS function */
09b4ddf9
PZ		 8389 if (IS_HASWELL(dev)) {
8390 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8391 dev_priv->display.crtc_enable = haswell_crtc_enable;
8392 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8393 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8394 dev_priv->display.update_plane = ironlake_update_plane;
8395 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8396 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8397 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8398 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8399 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8400 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8401 } else {
f564048e 8402 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8403 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8404 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8405 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8406 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8407 }
e70236a8 8408
e70236a8 8409 /* Returns the core display clock speed */
25eb05fc
JB		 8410 if (IS_VALLEYVIEW(dev))
8411 dev_priv->display.get_display_clock_speed =
8412 valleyview_get_display_clock_speed;
8413 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8414 dev_priv->display.get_display_clock_speed =
8415 i945_get_display_clock_speed;
8416 else if (IS_I915G(dev))
8417 dev_priv->display.get_display_clock_speed =
8418 i915_get_display_clock_speed;
f2b115e6 8419 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8420 dev_priv->display.get_display_clock_speed =
8421 i9xx_misc_get_display_clock_speed;
8422 else if (IS_I915GM(dev))
8423 dev_priv->display.get_display_clock_speed =
8424 i915gm_get_display_clock_speed;
8425 else if (IS_I865G(dev))
8426 dev_priv->display.get_display_clock_speed =
8427 i865_get_display_clock_speed;
f0f8a9ce 8428 else if (IS_I85X(dev))
e70236a8
JB		 8429 dev_priv->display.get_display_clock_speed =
8430 i855_get_display_clock_speed;
8431 else /* 852, 830 */
8432 dev_priv->display.get_display_clock_speed =
8433 i830_get_display_clock_speed;
8434
7f8a8569 8435 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8436 if (IS_GEN5(dev)) {
674cf967 8437 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8438 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8439 } else if (IS_GEN6(dev)) {
674cf967 8440 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8441 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8442 } else if (IS_IVYBRIDGE(dev)) {
8443 /* FIXME: detect B0+ stepping and use auto training */
8444 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8445 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8446 dev_priv->display.modeset_global_resources =
8447 ivb_modeset_global_resources;
c82e4d26
ED		 8448 } else if (IS_HASWELL(dev)) {
8449 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8450 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8451 } else
8452 dev_priv->display.update_wm = NULL;
6067aaea 8453 } else if (IS_G4X(dev)) {
e0dac65e 8454 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8455 }
8c9f3aaf
JB		 8456
8457 /* Default just returns -ENODEV to indicate unsupported */
8458 dev_priv->display.queue_flip = intel_default_queue_flip;
8459
8460 switch (INTEL_INFO(dev)->gen) {
8461 case 2:
8462 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8463 break;
8464
8465 case 3:
8466 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8467 break;
8468
8469 case 4:
8470 case 5:
8471 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8472 break;
8473
8474 case 6:
8475 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8476 break;
7c9017e5
JB		 8477 case 7:
8478 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8479 break;
8c9f3aaf 8480 }
e70236a8
JB		 8481}
8482
b690e96c
JB		 8483/*
8484 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8485 * resume, or other times. This quirk makes sure that's the case for
8486 * affected systems.
8487 */
0206e353 8488static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8489{
8490 struct drm_i915_private *dev_priv = dev->dev_private;
8491
8492 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8493 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8494}
8495
435793df
KP		 8496/*
8497 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8498 */
8499static void quirk_ssc_force_disable(struct drm_device *dev)
8500{
8501 struct drm_i915_private *dev_priv = dev->dev_private;
8502 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8503 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8504}
8505
4dca20ef 8506/*
5a15ab5b
CE		 8507 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8508 * brightness value
4dca20ef
CE		 8509 */
8510static void quirk_invert_brightness(struct drm_device *dev)
8511{
8512 struct drm_i915_private *dev_priv = dev->dev_private;
8513 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8514 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8515}
8516
b690e96c
JB		 8517struct intel_quirk {
8518 int device;
8519 int subsystem_vendor;
8520 int subsystem_device;
8521 void (*hook)(struct drm_device *dev);
8522};
8523
c43b5634 8524static struct intel_quirk intel_quirks[] = {
b690e96c 8525 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8526 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8527
b690e96c
JB		 8528 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8529 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8530
b690e96c
JB		 8531 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8532 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8533
ccd0d36e 8534 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8535 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8536 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8537
8538 /* Lenovo U160 cannot use SSC on LVDS */
8539 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8540
8541 /* Sony Vaio Y cannot use SSC on LVDS */
8542 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8543
8544 /* Acer Aspire 5734Z must invert backlight brightness */
8545 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8546};
8547
8548static void intel_init_quirks(struct drm_device *dev)
8549{
8550 struct pci_dev *d = dev->pdev;
8551 int i;
8552
8553 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8554 struct intel_quirk *q = &intel_quirks[i];
8555
8556 if (d->device == q->device &&
8557 (d->subsystem_vendor == q->subsystem_vendor ||
8558 q->subsystem_vendor == PCI_ANY_ID) &&
8559 (d->subsystem_device == q->subsystem_device ||
8560 q->subsystem_device == PCI_ANY_ID))
8561 q->hook(dev);
8562 }
8563}
8564
9cce37f4
JB		 8565/* Disable the VGA plane that we never use */
8566static void i915_disable_vga(struct drm_device *dev)
8567{
8568 struct drm_i915_private *dev_priv = dev->dev_private;
8569 u8 sr1;
8570 u32 vga_reg;
8571
8572 if (HAS_PCH_SPLIT(dev))
8573 vga_reg = CPU_VGACNTRL;
8574 else
8575 vga_reg = VGACNTRL;
8576
8577 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8578 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8579 sr1 = inb(VGA_SR_DATA);
8580 outb(sr1 | 1<<5, VGA_SR_DATA);
8581 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8582 udelay(300);
8583
8584 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8585 POSTING_READ(vga_reg);
8586}
8587
f817586c
DV		 8588void intel_modeset_init_hw(struct drm_device *dev)
8589{
0232e927
ED		 8590 /* We attempt to init the necessary power wells early in the initialization
8591 * time, so the subsystems that expect power to be enabled can work.
8592 */
8593 intel_init_power_wells(dev);
8594
a8f78b58
ED		 8595 intel_prepare_ddi(dev);
8596
f817586c
DV		 8597 intel_init_clock_gating(dev);
8598
79f5b2c7 8599 mutex_lock(&dev->struct_mutex);
8090c6b9 8600 intel_enable_gt_powersave(dev);
79f5b2c7 8601 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8602}
8603
79e53945
JB		 8604void intel_modeset_init(struct drm_device *dev)
8605{
652c393a 8606 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8607 int i, ret;
79e53945
JB		 8608
8609 drm_mode_config_init(dev);
8610
8611 dev->mode_config.min_width = 0;
8612 dev->mode_config.min_height = 0;
8613
019d96cb
DA		 8614 dev->mode_config.preferred_depth = 24;
8615 dev->mode_config.prefer_shadow = 1;
8616
e6ecefaa 8617 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8618
b690e96c
JB		 8619 intel_init_quirks(dev);
8620
1fa61106
ED		 8621 intel_init_pm(dev);
8622
e70236a8
JB		 8623 intel_init_display(dev);
8624
a6c45cf0
CW		 8625 if (IS_GEN2(dev)) {
8626 dev->mode_config.max_width = 2048;
8627 dev->mode_config.max_height = 2048;
8628 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8629 dev->mode_config.max_width = 4096;
8630 dev->mode_config.max_height = 4096;
79e53945 8631 } else {
a6c45cf0
CW		 8632 dev->mode_config.max_width = 8192;
8633 dev->mode_config.max_height = 8192;
79e53945 8634 }
dd2757f8 8635 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8636
28c97730 8637 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8638 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8639
a3524f1b 8640 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8641 intel_crtc_init(dev, i);
00c2064b
JB		 8642 ret = intel_plane_init(dev, i);
8643 if (ret)
8644 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8645 }
8646
79f689aa 8647 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8648 intel_pch_pll_init(dev);
8649
9cce37f4
JB		 8650 /* Just disable it once at startup */
8651 i915_disable_vga(dev);
79e53945 8652 intel_setup_outputs(dev);
2c7111db
CW		 8653}
8654
24929352
DV		 8655static void
8656intel_connector_break_all_links(struct intel_connector *connector)
8657{
8658 connector->base.dpms = DRM_MODE_DPMS_OFF;
8659 connector->base.encoder = NULL;
8660 connector->encoder->connectors_active = false;
8661 connector->encoder->base.crtc = NULL;
8662}
8663
7fad798e
DV		 8664static void intel_enable_pipe_a(struct drm_device *dev)
8665{
8666 struct intel_connector *connector;
8667 struct drm_connector *crt = NULL;
8668 struct intel_load_detect_pipe load_detect_temp;
8669
8670 /* We can't just switch on the pipe A, we need to set things up with a
8671 * proper mode and output configuration. As a gross hack, enable pipe A
8672 * by enabling the load detect pipe once. */
8673 list_for_each_entry(connector,
8674 &dev->mode_config.connector_list,
8675 base.head) {
8676 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8677 crt = &connector->base;
8678 break;
8679 }
8680 }
8681
8682 if (!crt)
8683 return;
8684
8685 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8686 intel_release_load_detect_pipe(crt, &load_detect_temp);
8687
8688
8689}
8690
fa555837
DV		 8691static bool
8692intel_check_plane_mapping(struct intel_crtc *crtc)
8693{
8694 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8695 u32 reg, val;
8696
8697 if (dev_priv->num_pipe == 1)
8698 return true;
8699
8700 reg = DSPCNTR(!crtc->plane);
8701 val = I915_READ(reg);
8702
8703 if ((val & DISPLAY_PLANE_ENABLE) &&
8704 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8705 return false;
8706
8707 return true;
8708}
8709
24929352
DV		 8710static void intel_sanitize_crtc(struct intel_crtc *crtc)
8711{
8712 struct drm_device *dev = crtc->base.dev;
8713 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8714 u32 reg;
24929352 8715
24929352 8716 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8717 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8718 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8719
8720 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8721 * disable the crtc (and hence change the state) if it is wrong. Note
8722 * that gen4+ has a fixed plane -> pipe mapping. */
8723 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8724 struct intel_connector *connector;
8725 bool plane;
8726
24929352
DV		 8727 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8728 crtc->base.base.id);
8729
8730 /* Pipe has the wrong plane attached and the plane is active.
8731 * Temporarily change the plane mapping and disable everything
8732 * ... */
8733 plane = crtc->plane;
8734 crtc->plane = !plane;
8735 dev_priv->display.crtc_disable(&crtc->base);
8736 crtc->plane = plane;
8737
8738 /* ... and break all links. */
8739 list_for_each_entry(connector, &dev->mode_config.connector_list,
8740 base.head) {
8741 if (connector->encoder->base.crtc != &crtc->base)
8742 continue;
8743
8744 intel_connector_break_all_links(connector);
8745 }
8746
8747 WARN_ON(crtc->active);
8748 crtc->base.enabled = false;
8749 }
24929352 8750
7fad798e
DV		 8751 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8752 crtc->pipe == PIPE_A && !crtc->active) {
8753 /* BIOS forgot to enable pipe A, this mostly happens after
8754 * resume. Force-enable the pipe to fix this, the update_dpms
8755 * call below we restore the pipe to the right state, but leave
8756 * the required bits on. */
8757 intel_enable_pipe_a(dev);
8758 }
8759
24929352
DV		 8760 /* Adjust the state of the output pipe according to whether we
8761 * have active connectors/encoders. */
8762 intel_crtc_update_dpms(&crtc->base);
8763
8764 if (crtc->active != crtc->base.enabled) {
8765 struct intel_encoder *encoder;
8766
8767 /* This can happen either due to bugs in the get_hw_state
8768 * functions or because the pipe is force-enabled due to the
8769 * pipe A quirk. */
8770 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8771 crtc->base.base.id,
8772 crtc->base.enabled ? "enabled" : "disabled",
8773 crtc->active ? "enabled" : "disabled");
8774
8775 crtc->base.enabled = crtc->active;
8776
8777 /* Because we only establish the connector -> encoder ->
8778 * crtc links if something is active, this means the
8779 * crtc is now deactivated. Break the links. connector
8780 * -> encoder links are only establish when things are
8781 * actually up, hence no need to break them. */
8782 WARN_ON(crtc->active);
8783
8784 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8785 WARN_ON(encoder->connectors_active);
8786 encoder->base.crtc = NULL;
8787 }
8788 }
8789}
8790
8791static void intel_sanitize_encoder(struct intel_encoder *encoder)
8792{
8793 struct intel_connector *connector;
8794 struct drm_device *dev = encoder->base.dev;
8795
8796 /* We need to check both for a crtc link (meaning that the
8797 * encoder is active and trying to read from a pipe) and the
8798 * pipe itself being active. */
8799 bool has_active_crtc = encoder->base.crtc &&
8800 to_intel_crtc(encoder->base.crtc)->active;
8801
8802 if (encoder->connectors_active && !has_active_crtc) {
8803 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8804 encoder->base.base.id,
8805 drm_get_encoder_name(&encoder->base));
8806
8807 /* Connector is active, but has no active pipe. This is
8808 * fallout from our resume register restoring. Disable
8809 * the encoder manually again. */
8810 if (encoder->base.crtc) {
8811 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8812 encoder->base.base.id,
8813 drm_get_encoder_name(&encoder->base));
8814 encoder->disable(encoder);
8815 }
8816
8817 /* Inconsistent output/port/pipe state happens presumably due to
8818 * a bug in one of the get_hw_state functions. Or someplace else
8819 * in our code, like the register restore mess on resume. Clamp
8820 * things to off as a safer default. */
8821 list_for_each_entry(connector,
8822 &dev->mode_config.connector_list,
8823 base.head) {
8824 if (connector->encoder != encoder)
8825 continue;
8826
8827 intel_connector_break_all_links(connector);
8828 }
8829 }
8830 /* Enabled encoders without active connectors will be fixed in
8831 * the crtc fixup. */
8832}
8833
8834/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8835 * and i915 state tracking structures. */
8836void intel_modeset_setup_hw_state(struct drm_device *dev)
8837{
8838 struct drm_i915_private *dev_priv = dev->dev_private;
8839 enum pipe pipe;
8840 u32 tmp;
8841 struct intel_crtc *crtc;
8842 struct intel_encoder *encoder;
8843 struct intel_connector *connector;
8844
e28d54cb
PZ		 8845 if (IS_HASWELL(dev)) {
8846 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8847
8848 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8849 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8850 case TRANS_DDI_EDP_INPUT_A_ON:
8851 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8852 pipe = PIPE_A;
8853 break;
8854 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8855 pipe = PIPE_B;
8856 break;
8857 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8858 pipe = PIPE_C;
8859 break;
8860 }
8861
8862 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8863 crtc->cpu_transcoder = TRANSCODER_EDP;
8864
8865 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8866 pipe_name(pipe));
8867 }
8868 }
8869
24929352
DV		 8870 for_each_pipe(pipe) {
8871 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8872
702e7a56 8873 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8874 if (tmp & PIPECONF_ENABLE)
8875 crtc->active = true;
8876 else
8877 crtc->active = false;
8878
8879 crtc->base.enabled = crtc->active;
8880
8881 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8882 crtc->base.base.id,
8883 crtc->active ? "enabled" : "disabled");
8884 }
8885
6441ab5f
PZ		 8886 if (IS_HASWELL(dev))
8887 intel_ddi_setup_hw_pll_state(dev);
8888
24929352
DV		 8889 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8890 base.head) {
8891 pipe = 0;
8892
8893 if (encoder->get_hw_state(encoder, &pipe)) {
8894 encoder->base.crtc =
8895 dev_priv->pipe_to_crtc_mapping[pipe];
8896 } else {
8897 encoder->base.crtc = NULL;
8898 }
8899
8900 encoder->connectors_active = false;
8901 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8902 encoder->base.base.id,
8903 drm_get_encoder_name(&encoder->base),
8904 encoder->base.crtc ? "enabled" : "disabled",
8905 pipe);
8906 }
8907
8908 list_for_each_entry(connector, &dev->mode_config.connector_list,
8909 base.head) {
8910 if (connector->get_hw_state(connector)) {
8911 connector->base.dpms = DRM_MODE_DPMS_ON;
8912 connector->encoder->connectors_active = true;
8913 connector->base.encoder = &connector->encoder->base;
8914 } else {
8915 connector->base.dpms = DRM_MODE_DPMS_OFF;
8916 connector->base.encoder = NULL;
8917 }
8918 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8919 connector->base.base.id,
8920 drm_get_connector_name(&connector->base),
8921 connector->base.encoder ? "enabled" : "disabled");
8922 }
8923
8924 /* HW state is read out, now we need to sanitize this mess. */
8925 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8926 base.head) {
8927 intel_sanitize_encoder(encoder);
8928 }
8929
8930 for_each_pipe(pipe) {
8931 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8932 intel_sanitize_crtc(crtc);
8933 }
9a935856
DV		 8934
8935 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8936
8937 intel_modeset_check_state(dev);
2e938892
DV		 8938
8939 drm_mode_config_reset(dev);
24929352
DV		 8940}
8941
2c7111db
CW		 8942void intel_modeset_gem_init(struct drm_device *dev)
8943{
1833b134 8944 intel_modeset_init_hw(dev);
02e792fb
DV		 8945
8946 intel_setup_overlay(dev);
24929352
DV		 8947
8948 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8949}
8950
8951void intel_modeset_cleanup(struct drm_device *dev)
8952{
652c393a
JB		 8953 struct drm_i915_private *dev_priv = dev->dev_private;
8954 struct drm_crtc *crtc;
8955 struct intel_crtc *intel_crtc;
8956
f87ea761 8957 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8958 mutex_lock(&dev->struct_mutex);
8959
723bfd70
JB		 8960 intel_unregister_dsm_handler();
8961
8962
652c393a
JB		 8963 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8964 /* Skip inactive CRTCs */
8965 if (!crtc->fb)
8966 continue;
8967
8968 intel_crtc = to_intel_crtc(crtc);
3dec0095 8969 intel_increase_pllclock(crtc);
652c393a
JB		 8970 }
8971
973d04f9 8972 intel_disable_fbc(dev);
e70236a8 8973
8090c6b9 8974 intel_disable_gt_powersave(dev);
0cdab21f 8975
930ebb46
DV		 8976 ironlake_teardown_rc6(dev);
8977
57f350b6
JB		 8978 if (IS_VALLEYVIEW(dev))
8979 vlv_init_dpio(dev);
8980
69341a5e
KH		 8981 mutex_unlock(&dev->struct_mutex);
8982
6c0d9350
DV		 8983 /* Disable the irq before mode object teardown, for the irq might
8984 * enqueue unpin/hotplug work. */
8985 drm_irq_uninstall(dev);
8986 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8987 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8988
1630fe75
CW		 8989 /* flush any delayed tasks or pending work */
8990 flush_scheduled_work();
8991
79e53945
JB		 8992 drm_mode_config_cleanup(dev);
8993}
8994
f1c79df3
ZW		 8995/*
8996 * Return which encoder is currently attached for connector.
8997 */
df0e9248 8998struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8999{
df0e9248
CW		 9000 return &intel_attached_encoder(connector)->base;
9001}
f1c79df3 9002
df0e9248
CW		 9003void intel_connector_attach_encoder(struct intel_connector *connector,
9004 struct intel_encoder *encoder)
9005{
9006 connector->encoder = encoder;
9007 drm_mode_connector_attach_encoder(&connector->base,
9008 &encoder->base);
79e53945 9009}
28d52043
DA		 9010
9011/*
9012 * set vga decode state - true == enable VGA decode
9013 */
9014int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9015{
9016 struct drm_i915_private *dev_priv = dev->dev_private;
9017 u16 gmch_ctrl;
9018
9019 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9020 if (state)
9021 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9022 else
9023 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9024 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9025 return 0;
9026}
c4a1d9e4
CW		 9027
9028#ifdef CONFIG_DEBUG_FS
9029#include <linux/seq_file.h>
9030
9031struct intel_display_error_state {
9032 struct intel_cursor_error_state {
9033 u32 control;
9034 u32 position;
9035 u32 base;
9036 u32 size;
52331309 9037 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9038
9039 struct intel_pipe_error_state {
9040 u32 conf;
9041 u32 source;
9042
9043 u32 htotal;
9044 u32 hblank;
9045 u32 hsync;
9046 u32 vtotal;
9047 u32 vblank;
9048 u32 vsync;
52331309 9049 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9050
9051 struct intel_plane_error_state {
9052 u32 control;
9053 u32 stride;
9054 u32 size;
9055 u32 pos;
9056 u32 addr;
9057 u32 surface;
9058 u32 tile_offset;
52331309 9059 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9060};
9061
9062struct intel_display_error_state *
9063intel_display_capture_error_state(struct drm_device *dev)
9064{
0206e353 9065 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9066 struct intel_display_error_state *error;
702e7a56 9067 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9068 int i;
9069
9070 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9071 if (error == NULL)
9072 return NULL;
9073
52331309 9074 for_each_pipe(i) {
702e7a56
PZ		 9075 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9076
c4a1d9e4
CW		 9077 error->cursor[i].control = I915_READ(CURCNTR(i));
9078 error->cursor[i].position = I915_READ(CURPOS(i));
9079 error->cursor[i].base = I915_READ(CURBASE(i));
9080
9081 error->plane[i].control = I915_READ(DSPCNTR(i));
9082 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9083 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9084 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9085 error->plane[i].addr = I915_READ(DSPADDR(i));
9086 if (INTEL_INFO(dev)->gen >= 4) {
9087 error->plane[i].surface = I915_READ(DSPSURF(i));
9088 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9089 }
9090
702e7a56 9091 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9092 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9093 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9094 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9095 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9096 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9097 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9098 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9099 }
9100
9101 return error;
9102}
9103
9104void
9105intel_display_print_error_state(struct seq_file *m,
9106 struct drm_device *dev,
9107 struct intel_display_error_state *error)
9108{
52331309 9109 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9110 int i;
9111
52331309
DL		 9112 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9113 for_each_pipe(i) {
c4a1d9e4
CW		 9114 seq_printf(m, "Pipe [%d]:\n", i);
9115 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9116 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9117 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9118 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9119 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9120 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9121 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9122 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9123
9124 seq_printf(m, "Plane [%d]:\n", i);
9125 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9126 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9127 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9128 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9129 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9130 if (INTEL_INFO(dev)->gen >= 4) {
9131 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9132 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9133 }
9134
9135 seq_printf(m, "Cursor [%d]:\n", i);
9136 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9137 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9138 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9139 }
9140}
9141#endif
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