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drm/i915: garbage-collect vlv refclk function
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
18442d08
VS		 50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
f1f644dc 52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
743 * We can ditch the adjusted_mode.clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
750 intel_crtc->config.adjusted_mode.clock;
751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
89b667f8
JB		 1469void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470{
1471 u32 port_mask;
1472
1473 if (!port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1475 else
1476 port_mask = DPLL_PORTC_READY_MASK;
1477
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1481}
1482
92f2584a 1483/**
e72f9fbf 1484 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1487 *
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1490 */
e2b78267 1491static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1492{
e2b78267
DV		 1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1495
48da64a8 1496 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1497 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1498 if (WARN_ON(pll == NULL))
48da64a8
CW		 1499 return;
1500
1501 if (WARN_ON(pll->refcount == 0))
1502 return;
ee7b9f93 1503
46edb027
DV		 1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
e2b78267 1506 crtc->base.base.id);
92f2584a 1507
cdbd2316
DV		 1508 if (pll->active++) {
1509 WARN_ON(!pll->on);
e9d6944e 1510 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1511 return;
1512 }
f4a091c7 1513 WARN_ON(pll->on);
ee7b9f93 1514
46edb027 1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1516 pll->enable(dev_priv, pll);
ee7b9f93 1517 pll->on = true;
92f2584a
JB		 1518}
1519
e2b78267 1520static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1521{
e2b78267
DV		 1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1524
92f2584a
JB		 1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1527 if (WARN_ON(pll == NULL))
ee7b9f93 1528 return;
92f2584a 1529
48da64a8
CW		 1530 if (WARN_ON(pll->refcount == 0))
1531 return;
7a419866 1532
46edb027
DV		 1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
e2b78267 1535 crtc->base.base.id);
7a419866 1536
48da64a8 1537 if (WARN_ON(pll->active == 0)) {
e9d6944e 1538 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1539 return;
1540 }
1541
e9d6944e 1542 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1543 WARN_ON(!pll->on);
cdbd2316 1544 if (--pll->active)
7a419866 1545 return;
ee7b9f93 1546
46edb027 1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1548 pll->disable(dev_priv, pll);
ee7b9f93 1549 pll->on = false;
92f2584a
JB		 1550}
1551
b8a4f404
PZ		 1552static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
040484af 1554{
23670b32 1555 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1558 uint32_t reg, val, pipeconf_val;
040484af
JB		 1559
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1562
1563 /* Make sure PCH DPLL is enabled */
e72f9fbf 1564 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1565 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1566
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1570
23670b32
DV		 1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
59c859d6 1578 }
23670b32 1579
ab9412ba 1580 reg = PCH_TRANSCONF(pipe);
040484af 1581 val = I915_READ(reg);
5f7f726d 1582 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1583
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1585 /*
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1588 */
dfd07d72
DV		 1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1591 }
5f7f726d
PZ		 1592
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1598 else
1599 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1600 else
1601 val |= TRANS_PROGRESSIVE;
1602
040484af
JB		 1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1606}
1607
8fb033d7 1608static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1609 enum transcoder cpu_transcoder)
040484af 1610{
8fb033d7 1611 u32 val, pipeconf_val;
8fb033d7
PZ		 1612
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1615
8fb033d7 1616 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1619
223a6fdf
PZ		 1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1624
25f3ef11 1625 val = TRANS_ENABLE;
937bb610 1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1627
9a76b1c6
PZ		 1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
a35f2679 1630 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
ab9412ba
DV		 1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1636 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1637}
1638
b8a4f404
PZ		 1639static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum pipe pipe)
040484af 1641{
23670b32
DV		 1642 struct drm_device *dev = dev_priv->dev;
1643 uint32_t reg, val;
040484af
JB		 1644
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1648
291906f1
JB		 1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1651
ab9412ba 1652 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1659
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1666 }
040484af
JB		 1667}
1668
ab4d966c 1669static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1670{
8fb033d7
PZ		 1671 u32 val;
1672
ab9412ba 1673 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1674 val &= ~TRANS_ENABLE;
ab9412ba 1675 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1676 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1678 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1679
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1683 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1684}
1685
b24e7179 1686/**
309cfea8 1687 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
040484af 1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1691 *
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1698 * returning.
1699 */
040484af 1700static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1701 bool pch_port, bool dsi)
b24e7179 1702{
702e7a56
PZ		 1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704 pipe);
1a240d4d 1705 enum pipe pch_transcoder;
b24e7179
JB		 1706 int reg;
1707 u32 val;
1708
58c6eaa2 1709 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1710 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1711 assert_sprites_disabled(dev_priv, pipe);
1712
681e5811 1713 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1714 pch_transcoder = TRANSCODER_A;
1715 else
1716 pch_transcoder = pipe;
1717
b24e7179
JB		 1718 /*
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1721 * need the check.
1722 */
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1724 if (dsi)
1725 assert_dsi_pll_enabled(dev_priv);
1726 else
1727 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1728 else {
1729 if (pch_port) {
1730 /* if driving the PCH, we need FDI enabled */
cc391bbb 1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
040484af
JB		 1734 }
1735 /* FIXME: assert CPU port conditions for SNB+ */
1736 }
b24e7179 1737
702e7a56 1738 reg = PIPECONF(cpu_transcoder);
b24e7179 1739 val = I915_READ(reg);
00d70b15
CW		 1740 if (val & PIPECONF_ENABLE)
1741 return;
1742
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
1747/**
309cfea8 1748 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1751 *
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe has shut down before returning.
1758 */
1759static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760 enum pipe pipe)
1761{
702e7a56
PZ		 1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
b24e7179
JB		 1764 int reg;
1765 u32 val;
1766
1767 /*
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1770 */
1771 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1772 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1773 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1774
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777 return;
1778
702e7a56 1779 reg = PIPECONF(cpu_transcoder);
b24e7179 1780 val = I915_READ(reg);
00d70b15
CW		 1781 if ((val & PIPECONF_ENABLE) == 0)
1782 return;
1783
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786}
1787
d74362c9
KP		 1788/*
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1791 */
6f1d69b0 1792void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1793 enum plane plane)
1794{
14f86147
DL		 1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797 else
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1799}
1800
b24e7179
JB		 1801/**
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1806 *
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 */
1809static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1811{
1812 int reg;
1813 u32 val;
1814
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1817
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
00d70b15
CW		 1820 if (val & DISPLAY_PLANE_ENABLE)
1821 return;
1822
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1824 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1826}
1827
b24e7179
JB		 1828/**
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1833 *
1834 * Disable @plane; should be an independent operation.
1835 */
1836static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1838{
1839 int reg;
1840 u32 val;
1841
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
00d70b15
CW		 1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845 return;
1846
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
693db184
CW		 1852static bool need_vtd_wa(struct drm_device *dev)
1853{
1854#ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856 return true;
1857#endif
1858 return false;
1859}
1860
127bd2ac 1861int
48b956c5 1862intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1863 struct drm_i915_gem_object *obj,
919926ae 1864 struct intel_ring_buffer *pipelined)
6b95a207 1865{
ce453d81 1866 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1867 u32 alignment;
1868 int ret;
1869
05394f39 1870 switch (obj->tiling_mode) {
6b95a207 1871 case I915_TILING_NONE:
534843da
CW		 1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
a6c45cf0 1874 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1875 alignment = 4 * 1024;
1876 else
1877 alignment = 64 * 1024;
6b95a207
KH		 1878 break;
1879 case I915_TILING_X:
1880 /* pin() will align the object as required by fence */
1881 alignment = 0;
1882 break;
1883 case I915_TILING_Y:
8bb6e959
DV		 1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
693db184
CW		 1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1896 * the VT-d warning.
1897 */
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1900
ce453d81 1901 dev_priv->mm.interruptible = false;
2da3b9b9 1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1903 if (ret)
ce453d81 1904 goto err_interruptible;
6b95a207
KH		 1905
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1910 */
06d98131 1911 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1912 if (ret)
1913 goto err_unpin;
1690e1eb 1914
9a5a53b3 1915 i915_gem_object_pin_fence(obj);
6b95a207 1916
ce453d81 1917 dev_priv->mm.interruptible = true;
6b95a207 1918 return 0;
48b956c5
CW		 1919
1920err_unpin:
cc98b413 1921 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1922err_interruptible:
1923 dev_priv->mm.interruptible = true;
48b956c5 1924 return ret;
6b95a207
KH		 1925}
1926
1690e1eb
CW		 1927void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928{
1929 i915_gem_object_unpin_fence(obj);
cc98b413 1930 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1931}
1932
c2c75131
DV		 1933/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
bc752862
CW		 1935unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1937 unsigned int cpp,
1938 unsigned int pitch)
c2c75131 1939{
bc752862
CW		 1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
c2c75131 1942
bc752862
CW		 1943 tile_rows = *y / 8;
1944 *y %= 8;
c2c75131 1945
bc752862
CW		 1946 tiles = *x / (512/cpp);
1947 *x %= 512/cpp;
1948
1949 return tile_rows * pitch * 8 + tiles * 4096;
1950 } else {
1951 unsigned int offset;
1952
1953 offset = *y * pitch + *x * cpp;
1954 *y = 0;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1957 }
c2c75131
DV		 1958}
1959
17638cd6
JB		 1960static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961 int x, int y)
81255565
JB		 1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
05394f39 1967 struct drm_i915_gem_object *obj;
81255565 1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
81255565 1970 u32 dspcntr;
5eddb70b 1971 u32 reg;
81255565
JB		 1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 break;
1977 default:
84f44ce7 1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1979 return -EINVAL;
1980 }
1981
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
81255565 1984
5eddb70b
CW		 1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
81255565
JB		 1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1989 switch (fb->pixel_format) {
1990 case DRM_FORMAT_C8:
81255565
JB		 1991 dspcntr |= DISPPLANE_8BPP;
1992 break;
57779d06
VS		 1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
81255565 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
1999 break;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2003 break;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2007 break;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2011 break;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2015 break;
2016 default:
baba133a 2017 BUG();
81255565 2018 }
57779d06 2019
a6c45cf0 2020 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2021 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2022 dspcntr |= DISPPLANE_TILED;
2023 else
2024 dspcntr &= ~DISPPLANE_TILED;
2025 }
2026
de1aa629
VS		 2027 if (IS_G4X(dev))
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
5eddb70b 2030 I915_WRITE(reg, dspcntr);
81255565 2031
e506a0c6 2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2033
c2c75131
DV		 2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
bc752862
CW		 2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2038 fb->pitches[0]);
c2c75131
DV		 2039 linear_offset -= intel_crtc->dspaddr_offset;
2040 } else {
e506a0c6 2041 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2042 }
e506a0c6 2043
f343c5f6
BW		 2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046 fb->pitches[0]);
01f2c773 2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2048 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2053 } else
f343c5f6 2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2055 POSTING_READ(reg);
81255565 2056
17638cd6
JB		 2057 return 0;
2058}
2059
2060static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2062{
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
e506a0c6 2069 unsigned long linear_offset;
17638cd6
JB		 2070 u32 dspcntr;
2071 u32 reg;
2072
2073 switch (plane) {
2074 case 0:
2075 case 1:
27f8227b 2076 case 2:
17638cd6
JB		 2077 break;
2078 default:
84f44ce7 2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2080 return -EINVAL;
2081 }
2082
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2085
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2090 switch (fb->pixel_format) {
2091 case DRM_FORMAT_C8:
17638cd6
JB		 2092 dspcntr |= DISPPLANE_8BPP;
2093 break;
57779d06
VS		 2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2096 break;
57779d06
VS		 2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2100 break;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2104 break;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2108 break;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2112 break;
2113 default:
baba133a 2114 BUG();
17638cd6
JB		 2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
1f5d76db
PZ		 2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124 else
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2126
2127 I915_WRITE(reg, dspcntr);
2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2130 intel_crtc->dspaddr_offset =
bc752862
CW		 2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2133 fb->pitches[0]);
c2c75131 2134 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2135
f343c5f6
BW		 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138 fb->pitches[0]);
01f2c773 2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144 } else {
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147 }
17638cd6
JB		 2148 POSTING_READ(reg);
2149
2150 return 0;
2151}
2152
2153/* Assume fb object is pinned & idle & fenced and just update base pointers */
2154static int
2155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2160
6b8e6ed0
CW		 2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
3dec0095 2163 intel_increase_pllclock(crtc);
81255565 2164
6b8e6ed0 2165 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2166}
2167
96a02917
VS		 2168void intel_display_handle_reset(struct drm_device *dev)
2169{
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2172
2173 /*
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2177 *
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2181 *
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2185 */
2186
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2190
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2193 }
2194
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2201 crtc->x, crtc->y);
2202 mutex_unlock(&crtc->mutex);
2203 }
2204}
2205
14667a4b
CW		 2206static int
2207intel_finish_fb(struct drm_framebuffer *old_fb)
2208{
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2212 int ret;
2213
14667a4b
CW		 2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2217 * framebuffer.
2218 *
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2221 */
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2225
2226 return ret;
2227}
2228
198598d0
VS		 2229static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230{
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 if (!dev->primary->master)
2236 return;
2237
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2240 return;
2241
2242 switch (intel_crtc->pipe) {
2243 case 0:
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2246 break;
2247 case 1:
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2250 break;
2251 default:
2252 break;
2253 }
2254}
2255
5c3b82e2 2256static int
3c4fdcfb 2257intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2258 struct drm_framebuffer *fb)
79e53945
JB		 2259{
2260 struct drm_device *dev = crtc->dev;
6b8e6ed0 2261 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2263 struct drm_framebuffer *old_fb;
5c3b82e2 2264 int ret;
79e53945
JB		 2265
2266 /* no fb bound */
94352cf9 2267 if (!fb) {
a5071c2f 2268 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2269 return 0;
2270 }
2271
7eb552ae 2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2276 return -EINVAL;
79e53945
JB		 2277 }
2278
5c3b82e2 2279 mutex_lock(&dev->struct_mutex);
265db958 2280 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2281 to_intel_framebuffer(fb)->obj,
919926ae 2282 NULL);
5c3b82e2
CW		 2283 if (ret != 0) {
2284 mutex_unlock(&dev->struct_mutex);
a5071c2f 2285 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2286 return ret;
2287 }
79e53945 2288
4d6a3e63
JB		 2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
2294 if (!intel_crtc->config.pch_pfit.size &&
2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300 }
2301 }
2302
94352cf9 2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2304 if (ret) {
94352cf9 2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2306 mutex_unlock(&dev->struct_mutex);
a5071c2f 2307 DRM_ERROR("failed to update base address\n");
4e6cfefc 2308 return ret;
79e53945 2309 }
3c4fdcfb 2310
94352cf9
DV		 2311 old_fb = crtc->fb;
2312 crtc->fb = fb;
6c4c86f5
DV		 2313 crtc->x = x;
2314 crtc->y = y;
94352cf9 2315
b7f1de28 2316 if (old_fb) {
d7697eea
DV		 2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2320 }
652c393a 2321
6b8e6ed0 2322 intel_update_fbc(dev);
4906557e 2323 intel_edp_psr_update(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
139ccd3f 2644 u32 reg, temp, i, j;
357555c0
JB		 2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
139ccd3f
JB		 2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
357555c0 2668
139ccd3f
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
357555c0 2675
139ccd3f 2676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
139ccd3f
JB		 2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2686
139ccd3f
JB		 2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2689
139ccd3f 2690 reg = FDI_RX_CTL(pipe);
357555c0 2691 temp = I915_READ(reg);
139ccd3f
JB		 2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2695
139ccd3f
JB		 2696 POSTING_READ(reg);
2697 udelay(1); /* should be 0.5us */
357555c0 2698
139ccd3f
JB		 2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2703
139ccd3f
JB		 2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708 i);
2709 break;
2710 }
2711 udelay(1); /* should be 0.5us */
2712 }
2713 if (i == 4) {
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715 continue;
2716 }
357555c0 2717
139ccd3f 2718 /* Train 2 */
357555c0
JB		 2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
139ccd3f
JB		 2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2724
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
139ccd3f 2732 udelay(2); /* should be 1.5us */
357555c0 2733
139ccd3f
JB		 2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2738
139ccd3f
JB		 2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743 i);
2744 goto train_done;
2745 }
2746 udelay(2); /* should be 1.5us */
357555c0 2747 }
139ccd3f
JB		 2748 if (i == 4)
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2750 }
357555c0 2751
139ccd3f 2752train_done:
357555c0
JB		 2753 DRM_DEBUG_KMS("FDI train done.\n");
2754}
2755
88cefb6c 2756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2757{
88cefb6c 2758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2760 int pipe = intel_crtc->pipe;
5eddb70b 2761 u32 reg, temp;
79e53945 2762
c64e311e 2763
c98e9dcf 2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
627eb5a3
DV		 2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772 POSTING_READ(reg);
c98e9dcf
JB		 2773 udelay(200);
2774
2775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779 POSTING_READ(reg);
c98e9dcf
JB		 2780 udelay(200);
2781
20749730
PZ		 2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2787
20749730
PZ		 2788 POSTING_READ(reg);
2789 udelay(100);
6be4a607 2790 }
0e23b99d
JB		 2791}
2792
88cefb6c
DV		 2793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794{
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
2811 udelay(100);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817 /* Wait for the clocks to turn off. */
2818 POSTING_READ(reg);
2819 udelay(100);
2820}
2821
0fc932b8
JB		 2822static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 u32 reg, temp;
2829
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 POSTING_READ(reg);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
dfd07d72 2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842 POSTING_READ(reg);
2843 udelay(100);
2844
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2848 }
0fc932b8
JB		 2849
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2856
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862 } else {
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865 }
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
dfd07d72 2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
5bb61643
CW		 2875static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2880 unsigned long flags;
2881 bool pending;
2882
10d83730
VS		 2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2885 return false;
2886
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891 return pending;
2892}
2893
e6c3a2a6
CW		 2894static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895{
0f91128d 2896 struct drm_device *dev = crtc->dev;
5bb61643 2897 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2898
2899 if (crtc->fb == NULL)
2900 return;
2901
2c10d571
DV		 2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
5bb61643
CW		 2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2906
0f91128d
CW		 2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2910}
2911
e615efe4
ED		 2912/* Program iCLKIP clock to the desired frequency */
2913static void lpt_program_iclkip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
12d7ceed 2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
e615efe4
ED		 2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919 u32 temp;
2920
09153000
DV		 2921 mutex_lock(&dev_priv->dpio_lock);
2922
e615efe4
ED		 2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2925 */
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 SBI_SSCCTL_DISABLE,
2932 SBI_ICLK);
e615efe4
ED		 2933
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2935 if (clock == 20000) {
e615efe4
ED		 2936 auxdiv = 1;
2937 divsel = 0x41;
2938 phaseinc = 0x20;
2939 } else {
2940 /* The iCLK virtual clock root frequency is in MHz,
12d7ceed 2941 * but the adjusted_mode->clock in in KHz. To get the divisors,
e615efe4
ED		 2942 * it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2944 * precision.
2945 */
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2949
12d7ceed 2950 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2953
2954 auxdiv = 0;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2957 }
2958
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2966 clock,
e615efe4
ED		 2967 auxdiv,
2968 divsel,
2969 phasedir,
2970 phaseinc);
2971
2972 /* Program SSCDIVINTPHASE6 */
988d6ee8 2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Program SSCAUXDIV */
988d6ee8 2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2987
2988 /* Enable modulator and associated divider */
988d6ee8 2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2990 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2997
2998 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2999}
3000
275f01b2
DV		 3001static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3003{
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3014
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023}
3024
f67a559d
JB		 3025/*
3026 * Enable PCH resources required for PCH ports:
3027 * - PCH PLLs
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3031 * - transcoder
3032 */
3033static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
ee7b9f93 3039 u32 reg, temp;
2c07245f 3040
ab9412ba 3041 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3042
cd986abb
DV		 3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
c98e9dcf 3048 /* For PCH output, training FDI link */
674cf967 3049 dev_priv->display.fdi_link_train(crtc);
2c07245f 3050
3ad8a208
DV		 3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
303b81e0 3053 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3054 u32 sel;
4b645f14 3055
c98e9dcf 3056 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3060 temp |= sel;
3061 else
3062 temp &= ~sel;
c98e9dcf 3063 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3064 }
5eddb70b 3065
3ad8a208
DV		 3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3074
d9b6cb56
JB		 3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3078
303b81e0 3079 intel_fdi_normal_train(crtc);
5e84e1a4 3080
c98e9dcf
JB		 3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3089 TRANS_DP_SYNC_MASK |
3090 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
9325c9f0 3093 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3094
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3099
3100 switch (intel_trans_dp_port_sel(crtc)) {
3101 case PCH_DP_B:
5eddb70b 3102 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3103 break;
3104 case PCH_DP_C:
5eddb70b 3105 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3106 break;
3107 case PCH_DP_D:
5eddb70b 3108 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3109 break;
3110 default:
e95d41e1 3111 BUG();
32f9d658 3112 }
2c07245f 3113
5eddb70b 3114 I915_WRITE(reg, temp);
6be4a607 3115 }
b52eb4dc 3116
b8a4f404 3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3118}
3119
1507e5bd
PZ		 3120static void lpt_pch_enable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3126
ab9412ba 3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3128
8c52b5e8 3129 lpt_program_iclkip(crtc);
1507e5bd 3130
0540e488 3131 /* Set transcoder timing. */
275f01b2 3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3133
937bb610 3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3135}
3136
e2b78267 3137static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3138{
e2b78267 3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3140
3141 if (pll == NULL)
3142 return;
3143
3144 if (pll->refcount == 0) {
46edb027 3145 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3146 return;
3147 }
3148
f4a091c7
DV		 3149 if (--pll->refcount == 0) {
3150 WARN_ON(pll->on);
3151 WARN_ON(pll->active);
3152 }
3153
a43f6e0f 3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3155}
3156
b89a1d39 3157static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3158{
e2b78267
DV		 3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
ee7b9f93 3162
ee7b9f93 3163 if (pll) {
46edb027
DV		 3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
e2b78267 3166 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3167 }
3168
98b6bd99
DV		 3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3171 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3172 pll = &dev_priv->shared_dplls[i];
98b6bd99 3173
46edb027
DV		 3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
98b6bd99
DV		 3176
3177 goto found;
3178 }
3179
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
b89a1d39
DV		 3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
46edb027 3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3190 crtc->base.base.id,
46edb027 3191 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3200 if (pll->refcount == 0) {
46edb027
DV		 3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
a43f6e0f 3210 crtc->config.shared_dpll = i;
46edb027
DV		 3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
ee7b9f93 3213
cdbd2316 3214 if (pll->active == 0) {
66e985c0
DV		 3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3217
46edb027 3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3219 WARN_ON(pll->on);
e9d6944e 3220 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3221
15bdd4cf 3222 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3223 }
3224 pll->refcount++;
e04c7350 3225
ee7b9f93
JB		 3226 return pll;
3227}
3228
a1520318 3229static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3232 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3233 u32 temp;
3234
3235 temp = I915_READ(dslreg);
3236 udelay(500);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3238 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3240 }
3241}
3242
b074cec8
JB		 3243static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3248
0ef37f3f 3249 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3252 * e.g. x201.
3253 */
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3257 else
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3261 }
3262}
3263
bb53d4ae
VS		 3264static void intel_enable_planes(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3269
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3273}
3274
3275static void intel_disable_planes(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3280
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3284}
3285
f67a559d
JB		 3286static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3291 struct intel_encoder *encoder;
f67a559d
JB		 3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
f67a559d 3294
08a48469
DV		 3295 WARN_ON(!crtc->enabled);
3296
f67a559d
JB		 3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
8664281b
PZ		 3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
f6736a1a 3305 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3306 if (encoder->pre_enable)
3307 encoder->pre_enable(encoder);
f67a559d 3308
5bfe2ac0 3309 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3310 /* Note: FDI PLL enabling _must_ be done before we enable the
3311 * cpu pipes, hence this is separate from all the other fdi/pch
3312 * enabling. */
88cefb6c 3313 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3314 } else {
3315 assert_fdi_tx_disabled(dev_priv, pipe);
3316 assert_fdi_rx_disabled(dev_priv, pipe);
3317 }
f67a559d 3318
b074cec8 3319 ironlake_pfit_enable(intel_crtc);
f67a559d 3320
9c54c0dd
JB		 3321 /*
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3323 * clocks enabled
3324 */
3325 intel_crtc_load_lut(crtc);
3326
f37fcc2a 3327 intel_update_watermarks(crtc);
5bfe2ac0 3328 intel_enable_pipe(dev_priv, pipe,
23538ef1 3329 intel_crtc->config.has_pch_encoder, false);
f67a559d 3330 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3331 intel_enable_planes(crtc);
5c38d48c 3332 intel_crtc_update_cursor(crtc, true);
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
f67a559d 3335 ironlake_pch_enable(crtc);
c98e9dcf 3336
d1ebd816 3337 mutex_lock(&dev->struct_mutex);
bed4a673 3338 intel_update_fbc(dev);
d1ebd816
BW		 3339 mutex_unlock(&dev->struct_mutex);
3340
fa5c73b1
DV		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
61b77ddd
DV		 3343
3344 if (HAS_PCH_CPT(dev))
a1520318 3345 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3346
3347 /*
3348 * There seems to be a race in PCH platform hw (at least on some
3349 * outputs) where an enabled pipe still completes any pageflip right
3350 * away (as if the pipe is off) instead of waiting for vblank. As soon
3351 * as the first vblank happend, everything works as expected. Hence just
3352 * wait for one vblank before returning to avoid strange things
3353 * happening.
3354 */
3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3356}
3357
42db64ef
PZ		 3358/* IPS only exists on ULT machines and is tied to pipe A. */
3359static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360{
f5adf94e 3361 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3362}
3363
3364static void hsw_enable_ips(struct intel_crtc *crtc)
3365{
3366 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368 if (!crtc->config.ips_enabled)
3369 return;
3370
3371 /* We can only enable IPS after we enable a plane and wait for a vblank.
3372 * We guarantee that the plane is enabled by calling intel_enable_ips
3373 * only after intel_enable_plane. And intel_enable_plane already waits
3374 * for a vblank, so all we need to do here is to enable the IPS bit. */
3375 assert_plane_enabled(dev_priv, crtc->plane);
3376 I915_WRITE(IPS_CTL, IPS_ENABLE);
3377}
3378
3379static void hsw_disable_ips(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384 if (!crtc->config.ips_enabled)
3385 return;
3386
3387 assert_plane_enabled(dev_priv, crtc->plane);
3388 I915_WRITE(IPS_CTL, 0);
3389
3390 /* We need to wait for a vblank before we can disable the plane. */
3391 intel_wait_for_vblank(dev, crtc->pipe);
3392}
3393
4f771f10
PZ		 3394static void haswell_crtc_enable(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 struct intel_encoder *encoder;
3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
4f771f10
PZ		 3402
3403 WARN_ON(!crtc->enabled);
3404
3405 if (intel_crtc->active)
3406 return;
3407
3408 intel_crtc->active = true;
8664281b
PZ		 3409
3410 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411 if (intel_crtc->config.has_pch_encoder)
3412 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
5bfe2ac0 3414 if (intel_crtc->config.has_pch_encoder)
04945641 3415 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3416
3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 if (encoder->pre_enable)
3419 encoder->pre_enable(encoder);
3420
1f544388 3421 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3422
b074cec8 3423 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3424
3425 /*
3426 * On ILK+ LUT must be loaded before the pipe is running but with
3427 * clocks enabled
3428 */
3429 intel_crtc_load_lut(crtc);
3430
1f544388 3431 intel_ddi_set_pipe_settings(crtc);
8228c251 3432 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3433
f37fcc2a 3434 intel_update_watermarks(crtc);
5bfe2ac0 3435 intel_enable_pipe(dev_priv, pipe,
23538ef1 3436 intel_crtc->config.has_pch_encoder, false);
4f771f10 3437 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3438 intel_enable_planes(crtc);
5c38d48c 3439 intel_crtc_update_cursor(crtc, true);
4f771f10 3440
42db64ef
PZ		 3441 hsw_enable_ips(intel_crtc);
3442
5bfe2ac0 3443 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3444 lpt_pch_enable(crtc);
4f771f10
PZ		 3445
3446 mutex_lock(&dev->struct_mutex);
3447 intel_update_fbc(dev);
3448 mutex_unlock(&dev->struct_mutex);
3449
8807e55b 3450 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3451 encoder->enable(encoder);
8807e55b
JN		 3452 intel_opregion_notify_encoder(encoder, true);
3453 }
4f771f10 3454
4f771f10
PZ		 3455 /*
3456 * There seems to be a race in PCH platform hw (at least on some
3457 * outputs) where an enabled pipe still completes any pageflip right
3458 * away (as if the pipe is off) instead of waiting for vblank. As soon
3459 * as the first vblank happend, everything works as expected. Hence just
3460 * wait for one vblank before returning to avoid strange things
3461 * happening.
3462 */
3463 intel_wait_for_vblank(dev, intel_crtc->pipe);
3464}
3465
3f8dce3a
DV		 3466static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467{
3468 struct drm_device *dev = crtc->base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 int pipe = crtc->pipe;
3471
3472 /* To avoid upsetting the power well on haswell only disable the pfit if
3473 * it's in use. The hw state code will make sure we get this right. */
3474 if (crtc->config.pch_pfit.size) {
3475 I915_WRITE(PF_CTL(pipe), 0);
3476 I915_WRITE(PF_WIN_POS(pipe), 0);
3477 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478 }
3479}
3480
6be4a607
JB		 3481static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482{
3483 struct drm_device *dev = crtc->dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3486 struct intel_encoder *encoder;
6be4a607
JB		 3487 int pipe = intel_crtc->pipe;
3488 int plane = intel_crtc->plane;
5eddb70b 3489 u32 reg, temp;
b52eb4dc 3490
ef9c3aee 3491
f7abfe8b
CW		 3492 if (!intel_crtc->active)
3493 return;
3494
ea9d758d
DV		 3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->disable(encoder);
3497
e6c3a2a6 3498 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3499 drm_vblank_off(dev, pipe);
913d8d11 3500
5c3fe8b0 3501 if (dev_priv->fbc.plane == plane)
973d04f9 3502 intel_disable_fbc(dev);
2c07245f 3503
0d5b8c61 3504 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3505 intel_disable_planes(crtc);
0d5b8c61
VS		 3506 intel_disable_plane(dev_priv, plane, pipe);
3507
d925c59a
DV		 3508 if (intel_crtc->config.has_pch_encoder)
3509 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
b24e7179 3511 intel_disable_pipe(dev_priv, pipe);
32f9d658 3512
3f8dce3a 3513 ironlake_pfit_disable(intel_crtc);
2c07245f 3514
bf49ec8c
DV		 3515 for_each_encoder_on_crtc(dev, crtc, encoder)
3516 if (encoder->post_disable)
3517 encoder->post_disable(encoder);
2c07245f 3518
d925c59a
DV		 3519 if (intel_crtc->config.has_pch_encoder) {
3520 ironlake_fdi_disable(crtc);
913d8d11 3521
d925c59a
DV		 3522 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3524
d925c59a
DV		 3525 if (HAS_PCH_CPT(dev)) {
3526 /* disable TRANS_DP_CTL */
3527 reg = TRANS_DP_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530 TRANS_DP_PORT_SEL_MASK);
3531 temp |= TRANS_DP_PORT_SEL_NONE;
3532 I915_WRITE(reg, temp);
3533
3534 /* disable DPLL_SEL */
3535 temp = I915_READ(PCH_DPLL_SEL);
11887397 3536 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3537 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3538 }
e3421a18 3539
d925c59a 3540 /* disable PCH DPLL */
e72f9fbf 3541 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3542
d925c59a
DV		 3543 ironlake_fdi_pll_disable(intel_crtc);
3544 }
6b383a7f 3545
f7abfe8b 3546 intel_crtc->active = false;
46ba614c 3547 intel_update_watermarks(crtc);
d1ebd816
BW		 3548
3549 mutex_lock(&dev->struct_mutex);
6b383a7f 3550 intel_update_fbc(dev);
d1ebd816 3551 mutex_unlock(&dev->struct_mutex);
6be4a607 3552}
1b3c7a47 3553
4f771f10 3554static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3555{
4f771f10
PZ		 3556 struct drm_device *dev = crtc->dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3559 struct intel_encoder *encoder;
3560 int pipe = intel_crtc->pipe;
3561 int plane = intel_crtc->plane;
3b117c8f 3562 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3563
4f771f10
PZ		 3564 if (!intel_crtc->active)
3565 return;
3566
8807e55b
JN		 3567 for_each_encoder_on_crtc(dev, crtc, encoder) {
3568 intel_opregion_notify_encoder(encoder, false);
4f771f10 3569 encoder->disable(encoder);
8807e55b 3570 }
4f771f10
PZ		 3571
3572 intel_crtc_wait_for_pending_flips(crtc);
3573 drm_vblank_off(dev, pipe);
4f771f10 3574
891348b2 3575 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3576 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3577 intel_disable_fbc(dev);
3578
42db64ef
PZ		 3579 hsw_disable_ips(intel_crtc);
3580
0d5b8c61 3581 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3582 intel_disable_planes(crtc);
891348b2
RV		 3583 intel_disable_plane(dev_priv, plane, pipe);
3584
8664281b
PZ		 3585 if (intel_crtc->config.has_pch_encoder)
3586 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3587 intel_disable_pipe(dev_priv, pipe);
3588
ad80a810 3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3590
3f8dce3a 3591 ironlake_pfit_disable(intel_crtc);
4f771f10 3592
1f544388 3593 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3598
88adfff1 3599 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3600 lpt_disable_pch_transcoder(dev_priv);
8664281b 3601 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3602 intel_ddi_fdi_disable(crtc);
83616634 3603 }
4f771f10
PZ		 3604
3605 intel_crtc->active = false;
46ba614c 3606 intel_update_watermarks(crtc);
4f771f10
PZ		 3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611}
3612
ee7b9f93
JB		 3613static void ironlake_crtc_off(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3616 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3617}
3618
6441ab5f
PZ		 3619static void haswell_crtc_off(struct drm_crtc *crtc)
3620{
3621 intel_ddi_put_crtc_pll(crtc);
3622}
3623
02e792fb
DV		 3624static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625{
02e792fb 3626 if (!enable && intel_crtc->overlay) {
23f09ce3 3627 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3628 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3629
23f09ce3 3630 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3631 dev_priv->mm.interruptible = false;
3632 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633 dev_priv->mm.interruptible = true;
23f09ce3 3634 mutex_unlock(&dev->struct_mutex);
02e792fb 3635 }
02e792fb 3636
5dcdbcb0
CW		 3637 /* Let userspace switch the overlay on again. In most cases userspace
3638 * has to recompute where to put it anyway.
3639 */
02e792fb
DV		 3640}
3641
61bc95c1
EE		 3642/**
3643 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644 * cursor plane briefly if not already running after enabling the display
3645 * plane.
3646 * This workaround avoids occasional blank screens when self refresh is
3647 * enabled.
3648 */
3649static void
3650g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651{
3652 u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654 if ((cntl & CURSOR_MODE) == 0) {
3655 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659 intel_wait_for_vblank(dev_priv->dev, pipe);
3660 I915_WRITE(CURCNTR(pipe), cntl);
3661 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663 }
3664}
3665
2dd24552
JB		 3666static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc_config *pipe_config = &crtc->config;
3671
328d8e82 3672 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3673 return;
3674
2dd24552 3675 /*
c0b03411
DV		 3676 * The panel fitter should only be adjusted whilst the pipe is disabled,
3677 * according to register description and PRM.
2dd24552 3678 */
c0b03411
DV		 3679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3681
b074cec8
JB		 3682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3684
3685 /* Border color in case we don't scale up to the full screen. Black by
3686 * default, change to something else for debugging. */
3687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3688}
3689
89b667f8
JB		 3690static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691{
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
23538ef1 3698 bool is_dsi;
89b667f8
JB		 3699
3700 WARN_ON(!crtc->enabled);
3701
3702 if (intel_crtc->active)
3703 return;
3704
3705 intel_crtc->active = true;
89b667f8 3706
89b667f8
JB		 3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_pll_enable)
3709 encoder->pre_pll_enable(encoder);
3710
23538ef1
JN		 3711 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
e9fd1c02
JN		 3713 if (!is_dsi)
3714 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->pre_enable)
3718 encoder->pre_enable(encoder);
3719
2dd24552
JB		 3720 i9xx_pfit_enable(intel_crtc);
3721
63cbb074
VS		 3722 intel_crtc_load_lut(crtc);
3723
f37fcc2a 3724 intel_update_watermarks(crtc);
23538ef1 3725 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3726 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3727 intel_enable_planes(crtc);
5c38d48c 3728 intel_crtc_update_cursor(crtc, true);
89b667f8 3729
89b667f8 3730 intel_update_fbc(dev);
5004945f
JN		 3731
3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->enable(encoder);
89b667f8
JB		 3734}
3735
0b8765c6 3736static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3737{
3738 struct drm_device *dev = crtc->dev;
79e53945
JB		 3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3741 struct intel_encoder *encoder;
79e53945 3742 int pipe = intel_crtc->pipe;
80824003 3743 int plane = intel_crtc->plane;
79e53945 3744
08a48469
DV		 3745 WARN_ON(!crtc->enabled);
3746
f7abfe8b
CW		 3747 if (intel_crtc->active)
3748 return;
3749
3750 intel_crtc->active = true;
6b383a7f 3751
9d6d9f19
MK		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 if (encoder->pre_enable)
3754 encoder->pre_enable(encoder);
3755
f6736a1a
DV		 3756 i9xx_enable_pll(intel_crtc);
3757
2dd24552
JB		 3758 i9xx_pfit_enable(intel_crtc);
3759
63cbb074
VS		 3760 intel_crtc_load_lut(crtc);
3761
f37fcc2a 3762 intel_update_watermarks(crtc);
23538ef1 3763 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3764 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3765 intel_enable_planes(crtc);
22e407d7 3766 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3767 if (IS_G4X(dev))
3768 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3769 intel_crtc_update_cursor(crtc, true);
79e53945 3770
0b8765c6
JB		 3771 /* Give the overlay scaler a chance to enable if it's on this pipe */
3772 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3773
f440eb13 3774 intel_update_fbc(dev);
ef9c3aee 3775
fa5c73b1
DV		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 encoder->enable(encoder);
0b8765c6 3778}
79e53945 3779
87476d63
DV		 3780static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781{
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3784
328d8e82
DV		 3785 if (!crtc->config.gmch_pfit.control)
3786 return;
87476d63 3787
328d8e82 3788 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3789
328d8e82
DV		 3790 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791 I915_READ(PFIT_CONTROL));
3792 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3793}
3794
0b8765c6
JB		 3795static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3800 struct intel_encoder *encoder;
0b8765c6
JB		 3801 int pipe = intel_crtc->pipe;
3802 int plane = intel_crtc->plane;
ef9c3aee 3803
f7abfe8b
CW		 3804 if (!intel_crtc->active)
3805 return;
3806
ea9d758d
DV		 3807 for_each_encoder_on_crtc(dev, crtc, encoder)
3808 encoder->disable(encoder);
3809
0b8765c6 3810 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3811 intel_crtc_wait_for_pending_flips(crtc);
3812 drm_vblank_off(dev, pipe);
0b8765c6 3813
5c3fe8b0 3814 if (dev_priv->fbc.plane == plane)
973d04f9 3815 intel_disable_fbc(dev);
79e53945 3816
0d5b8c61
VS		 3817 intel_crtc_dpms_overlay(intel_crtc, false);
3818 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3819 intel_disable_planes(crtc);
b24e7179 3820 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3821
b24e7179 3822 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3823
87476d63 3824 i9xx_pfit_disable(intel_crtc);
24a1f16d 3825
89b667f8
JB		 3826 for_each_encoder_on_crtc(dev, crtc, encoder)
3827 if (encoder->post_disable)
3828 encoder->post_disable(encoder);
3829
e9fd1c02
JN		 3830 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3832
f7abfe8b 3833 intel_crtc->active = false;
46ba614c 3834 intel_update_watermarks(crtc);
f37fcc2a
VS		 3835
3836 intel_update_fbc(dev);
0b8765c6
JB		 3837}
3838
ee7b9f93
JB		 3839static void i9xx_crtc_off(struct drm_crtc *crtc)
3840{
3841}
3842
976f8a20
DV		 3843static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844 bool enabled)
2c07245f
ZW		 3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_master_private *master_priv;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 int pipe = intel_crtc->pipe;
79e53945
JB		 3850
3851 if (!dev->primary->master)
3852 return;
3853
3854 master_priv = dev->primary->master->driver_priv;
3855 if (!master_priv->sarea_priv)
3856 return;
3857
79e53945
JB		 3858 switch (pipe) {
3859 case 0:
3860 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862 break;
3863 case 1:
3864 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866 break;
3867 default:
9db4a9c7 3868 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3869 break;
3870 }
79e53945
JB		 3871}
3872
976f8a20
DV		 3873/**
3874 * Sets the power management mode of the pipe and plane.
3875 */
3876void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877{
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_encoder *intel_encoder;
3881 bool enable = false;
3882
3883 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884 enable |= intel_encoder->connectors_active;
3885
3886 if (enable)
3887 dev_priv->display.crtc_enable(crtc);
3888 else
3889 dev_priv->display.crtc_disable(crtc);
3890
3891 intel_crtc_update_sarea(crtc, enable);
3892}
3893
cdd59983
CW		 3894static void intel_crtc_disable(struct drm_crtc *crtc)
3895{
cdd59983 3896 struct drm_device *dev = crtc->dev;
976f8a20 3897 struct drm_connector *connector;
ee7b9f93 3898 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3900
976f8a20
DV		 3901 /* crtc should still be enabled when we disable it. */
3902 WARN_ON(!crtc->enabled);
3903
3904 dev_priv->display.crtc_disable(crtc);
c77bf565 3905 intel_crtc->eld_vld = false;
976f8a20 3906 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3907 dev_priv->display.off(crtc);
3908
931872fc 3909 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3910 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3911 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3912
3913 if (crtc->fb) {
3914 mutex_lock(&dev->struct_mutex);
1690e1eb 3915 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3916 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3917 crtc->fb = NULL;
3918 }
3919
3920 /* Update computed state. */
3921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922 if (!connector->encoder || !connector->encoder->crtc)
3923 continue;
3924
3925 if (connector->encoder->crtc != crtc)
3926 continue;
3927
3928 connector->dpms = DRM_MODE_DPMS_OFF;
3929 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3930 }
3931}
3932
ea5b213a 3933void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3934{
4ef69c7a 3935 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3936
ea5b213a
CW		 3937 drm_encoder_cleanup(encoder);
3938 kfree(intel_encoder);
7e7d76c3
JB		 3939}
3940
9237329d 3941/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3942 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943 * state of the entire output pipe. */
9237329d 3944static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3945{
5ab432ef
DV		 3946 if (mode == DRM_MODE_DPMS_ON) {
3947 encoder->connectors_active = true;
3948
b2cabb0e 3949 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3950 } else {
3951 encoder->connectors_active = false;
3952
b2cabb0e 3953 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3954 }
79e53945
JB		 3955}
3956
0a91ca29
DV		 3957/* Cross check the actual hw state with our own modeset state tracking (and it's
3958 * internal consistency). */
b980514c 3959static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3960{
0a91ca29
DV		 3961 if (connector->get_hw_state(connector)) {
3962 struct intel_encoder *encoder = connector->encoder;
3963 struct drm_crtc *crtc;
3964 bool encoder_enabled;
3965 enum pipe pipe;
3966
3967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968 connector->base.base.id,
3969 drm_get_connector_name(&connector->base));
3970
3971 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972 "wrong connector dpms state\n");
3973 WARN(connector->base.encoder != &encoder->base,
3974 "active connector not linked to encoder\n");
3975 WARN(!encoder->connectors_active,
3976 "encoder->connectors_active not set\n");
3977
3978 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979 WARN(!encoder_enabled, "encoder not enabled\n");
3980 if (WARN_ON(!encoder->base.crtc))
3981 return;
3982
3983 crtc = encoder->base.crtc;
3984
3985 WARN(!crtc->enabled, "crtc not enabled\n");
3986 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988 "encoder active on the wrong pipe\n");
3989 }
79e53945
JB		 3990}
3991
5ab432ef
DV		 3992/* Even simpler default implementation, if there's really no special case to
3993 * consider. */
3994void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3995{
5ab432ef 3996 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3997
5ab432ef
DV		 3998 /* All the simple cases only support two dpms states. */
3999 if (mode != DRM_MODE_DPMS_ON)
4000 mode = DRM_MODE_DPMS_OFF;
d4270e57 4001
5ab432ef
DV		 4002 if (mode == connector->dpms)
4003 return;
4004
4005 connector->dpms = mode;
4006
4007 /* Only need to change hw state when actually enabled */
4008 if (encoder->base.crtc)
4009 intel_encoder_dpms(encoder, mode);
4010 else
8af6cf88 4011 WARN_ON(encoder->connectors_active != false);
0a91ca29 4012
b980514c 4013 intel_modeset_check_state(connector->dev);
79e53945
JB		 4014}
4015
f0947c37
DV		 4016/* Simple connector->get_hw_state implementation for encoders that support only
4017 * one connector and no cloning and hence the encoder state determines the state
4018 * of the connector. */
4019bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4020{
24929352 4021 enum pipe pipe = 0;
f0947c37 4022 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4023
f0947c37 4024 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4025}
4026
1857e1da
DV		 4027static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028 struct intel_crtc_config *pipe_config)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_crtc *pipe_B_crtc =
4032 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 if (pipe_config->fdi_lanes > 4) {
4037 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038 pipe_name(pipe), pipe_config->fdi_lanes);
4039 return false;
4040 }
4041
4042 if (IS_HASWELL(dev)) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045 pipe_config->fdi_lanes);
4046 return false;
4047 } else {
4048 return true;
4049 }
4050 }
4051
4052 if (INTEL_INFO(dev)->num_pipes == 2)
4053 return true;
4054
4055 /* Ivybridge 3 pipe is really complicated */
4056 switch (pipe) {
4057 case PIPE_A:
4058 return true;
4059 case PIPE_B:
4060 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061 pipe_config->fdi_lanes > 2) {
4062 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063 pipe_name(pipe), pipe_config->fdi_lanes);
4064 return false;
4065 }
4066 return true;
4067 case PIPE_C:
1e833f40 4068 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4069 pipe_B_crtc->config.fdi_lanes <= 2) {
4070 if (pipe_config->fdi_lanes > 2) {
4071 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072 pipe_name(pipe), pipe_config->fdi_lanes);
4073 return false;
4074 }
4075 } else {
4076 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077 return false;
4078 }
4079 return true;
4080 default:
4081 BUG();
4082 }
4083}
4084
e29c22c0
DV		 4085#define RETRY 1
4086static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087 struct intel_crtc_config *pipe_config)
877d48d5 4088{
1857e1da 4089 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4090 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4091 int lane, link_bw, fdi_dotclock;
e29c22c0 4092 bool setup_ok, needs_recompute = false;
877d48d5 4093
e29c22c0 4094retry:
877d48d5
DV		 4095 /* FDI is a binary signal running at ~2.7GHz, encoding
4096 * each output octet as 10 bits. The actual frequency
4097 * is stored as a divider into a 100MHz clock, and the
4098 * mode pixel clock is stored in units of 1KHz.
4099 * Hence the bw of each lane in terms of the mode signal
4100 * is:
4101 */
4102 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
ff9a6750 4104 fdi_dotclock = adjusted_mode->clock;
877d48d5 4105
2bd89a07 4106 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4107 pipe_config->pipe_bpp);
4108
4109 pipe_config->fdi_lanes = lane;
4110
2bd89a07 4111 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4112 link_bw, &pipe_config->fdi_m_n);
1857e1da 4113
e29c22c0
DV		 4114 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115 intel_crtc->pipe, pipe_config);
4116 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117 pipe_config->pipe_bpp -= 2*3;
4118 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119 pipe_config->pipe_bpp);
4120 needs_recompute = true;
4121 pipe_config->bw_constrained = true;
4122
4123 goto retry;
4124 }
4125
4126 if (needs_recompute)
4127 return RETRY;
4128
4129 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4130}
4131
42db64ef
PZ		 4132static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133 struct intel_crtc_config *pipe_config)
4134{
3c4ca58c
PZ		 4135 pipe_config->ips_enabled = i915_enable_ips &&
4136 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4137 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4138}
4139
a43f6e0f 4140static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4141 struct intel_crtc_config *pipe_config)
79e53945 4142{
a43f6e0f 4143 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4144 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4145
8693a824
DL		 4146 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4147 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4148 */
4149 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4150 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4151 return -EINVAL;
44f46b42 4152
bd080ee5 4153 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4154 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4155 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4156 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4157 * for lvds. */
4158 pipe_config->pipe_bpp = 8*3;
4159 }
4160
f5adf94e 4161 if (HAS_IPS(dev))
a43f6e0f
DV		 4162 hsw_compute_ips_config(crtc, pipe_config);
4163
4164 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4165 * clock survives for now. */
4166 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4167 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4168
877d48d5 4169 if (pipe_config->has_pch_encoder)
a43f6e0f 4170 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4171
e29c22c0 4172 return 0;
79e53945
JB		 4173}
4174
25eb05fc
JB		 4175static int valleyview_get_display_clock_speed(struct drm_device *dev)
4176{
4177 return 400000; /* FIXME */
4178}
4179
e70236a8
JB		 4180static int i945_get_display_clock_speed(struct drm_device *dev)
4181{
4182 return 400000;
4183}
79e53945 4184
e70236a8 4185static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4186{
e70236a8
JB		 4187 return 333000;
4188}
79e53945 4189
e70236a8
JB		 4190static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4191{
4192 return 200000;
4193}
79e53945 4194
257a7ffc
DV		 4195static int pnv_get_display_clock_speed(struct drm_device *dev)
4196{
4197 u16 gcfgc = 0;
4198
4199 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4200
4201 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4202 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4203 return 267000;
4204 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4205 return 333000;
4206 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4207 return 444000;
4208 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4209 return 200000;
4210 default:
4211 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4212 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4213 return 133000;
4214 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4215 return 167000;
4216 }
4217}
4218
e70236a8
JB		 4219static int i915gm_get_display_clock_speed(struct drm_device *dev)
4220{
4221 u16 gcfgc = 0;
79e53945 4222
e70236a8
JB		 4223 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4224
4225 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4226 return 133000;
4227 else {
4228 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4229 case GC_DISPLAY_CLOCK_333_MHZ:
4230 return 333000;
4231 default:
4232 case GC_DISPLAY_CLOCK_190_200_MHZ:
4233 return 190000;
79e53945 4234 }
e70236a8
JB		 4235 }
4236}
4237
4238static int i865_get_display_clock_speed(struct drm_device *dev)
4239{
4240 return 266000;
4241}
4242
4243static int i855_get_display_clock_speed(struct drm_device *dev)
4244{
4245 u16 hpllcc = 0;
4246 /* Assume that the hardware is in the high speed state. This
4247 * should be the default.
4248 */
4249 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4250 case GC_CLOCK_133_200:
4251 case GC_CLOCK_100_200:
4252 return 200000;
4253 case GC_CLOCK_166_250:
4254 return 250000;
4255 case GC_CLOCK_100_133:
79e53945 4256 return 133000;
e70236a8 4257 }
79e53945 4258
e70236a8
JB		 4259 /* Shouldn't happen */
4260 return 0;
4261}
79e53945 4262
e70236a8
JB		 4263static int i830_get_display_clock_speed(struct drm_device *dev)
4264{
4265 return 133000;
79e53945
JB		 4266}
4267
2c07245f 4268static void
a65851af 4269intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4270{
a65851af
VS		 4271 while (*num > DATA_LINK_M_N_MASK ||
4272 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4273 *num >>= 1;
4274 *den >>= 1;
4275 }
4276}
4277
a65851af
VS		 4278static void compute_m_n(unsigned int m, unsigned int n,
4279 uint32_t *ret_m, uint32_t *ret_n)
4280{
4281 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4282 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4283 intel_reduce_m_n_ratio(ret_m, ret_n);
4284}
4285
e69d0bc1
DV		 4286void
4287intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4288 int pixel_clock, int link_clock,
4289 struct intel_link_m_n *m_n)
2c07245f 4290{
e69d0bc1 4291 m_n->tu = 64;
a65851af
VS		 4292
4293 compute_m_n(bits_per_pixel * pixel_clock,
4294 link_clock * nlanes * 8,
4295 &m_n->gmch_m, &m_n->gmch_n);
4296
4297 compute_m_n(pixel_clock, link_clock,
4298 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4299}
4300
a7615030
CW		 4301static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4302{
72bbe58c
KP		 4303 if (i915_panel_use_ssc >= 0)
4304 return i915_panel_use_ssc != 0;
41aa3448 4305 return dev_priv->vbt.lvds_use_ssc
435793df 4306 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4307}
4308
c65d77d8
JB		 4309static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4310{
4311 struct drm_device *dev = crtc->dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int refclk;
4314
a0c4da24 4315 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4316 refclk = 100000;
a0c4da24 4317 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4318 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4319 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4320 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4321 refclk / 1000);
4322 } else if (!IS_GEN2(dev)) {
4323 refclk = 96000;
4324 } else {
4325 refclk = 48000;
4326 }
4327
4328 return refclk;
4329}
4330
7429e9d4 4331static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4332{
7df00d7a 4333 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4334}
f47709a9 4335
7429e9d4
DV		 4336static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4337{
4338 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4339}
4340
f47709a9 4341static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4342 intel_clock_t *reduced_clock)
4343{
f47709a9 4344 struct drm_device *dev = crtc->base.dev;
a7516a05 4345 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4346 int pipe = crtc->pipe;
a7516a05
JB		 4347 u32 fp, fp2 = 0;
4348
4349 if (IS_PINEVIEW(dev)) {
7429e9d4 4350 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4351 if (reduced_clock)
7429e9d4 4352 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4353 } else {
7429e9d4 4354 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4355 if (reduced_clock)
7429e9d4 4356 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4357 }
4358
4359 I915_WRITE(FP0(pipe), fp);
8bcc2795 4360 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4361
f47709a9
DV		 4362 crtc->lowfreq_avail = false;
4363 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4364 reduced_clock && i915_powersave) {
4365 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4366 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4367 crtc->lowfreq_avail = true;
a7516a05
JB		 4368 } else {
4369 I915_WRITE(FP1(pipe), fp);
8bcc2795 4370 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4371 }
4372}
4373
5e69f97f
CML		 4374static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4375 pipe)
89b667f8
JB		 4376{
4377 u32 reg_val;
4378
4379 /*
4380 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4381 * and set it to a reasonable value instead.
4382 */
5e69f97f 4383 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4384 reg_val &= 0xffffff00;
4385 reg_val |= 0x00000030;
5e69f97f 4386 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4387
5e69f97f 4388 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4389 reg_val &= 0x8cffffff;
4390 reg_val = 0x8c000000;
5e69f97f 4391 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4392
5e69f97f 4393 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4394 reg_val &= 0xffffff00;
5e69f97f 4395 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4396
5e69f97f 4397 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4398 reg_val &= 0x00ffffff;
4399 reg_val |= 0xb0000000;
5e69f97f 4400 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4401}
4402
b551842d
DV		 4403static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4404 struct intel_link_m_n *m_n)
4405{
4406 struct drm_device *dev = crtc->base.dev;
4407 struct drm_i915_private *dev_priv = dev->dev_private;
4408 int pipe = crtc->pipe;
4409
e3b95f1e
DV		 4410 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4411 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4412 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4413 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4414}
4415
4416static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4417 struct intel_link_m_n *m_n)
4418{
4419 struct drm_device *dev = crtc->base.dev;
4420 struct drm_i915_private *dev_priv = dev->dev_private;
4421 int pipe = crtc->pipe;
4422 enum transcoder transcoder = crtc->config.cpu_transcoder;
4423
4424 if (INTEL_INFO(dev)->gen >= 5) {
4425 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4426 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4427 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4428 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4429 } else {
e3b95f1e
DV		 4430 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4431 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4432 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4433 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4434 }
4435}
4436
03afc4a2
DV		 4437static void intel_dp_set_m_n(struct intel_crtc *crtc)
4438{
4439 if (crtc->config.has_pch_encoder)
4440 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4441 else
4442 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4443}
4444
f47709a9 4445static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4446{
f47709a9 4447 struct drm_device *dev = crtc->base.dev;
a0c4da24 4448 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4449 int pipe = crtc->pipe;
89b667f8 4450 u32 dpll, mdiv;
a0c4da24 4451 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4452 u32 coreclk, reg_val, dpll_md;
a0c4da24 4453
09153000
DV		 4454 mutex_lock(&dev_priv->dpio_lock);
4455
f47709a9
DV		 4456 bestn = crtc->config.dpll.n;
4457 bestm1 = crtc->config.dpll.m1;
4458 bestm2 = crtc->config.dpll.m2;
4459 bestp1 = crtc->config.dpll.p1;
4460 bestp2 = crtc->config.dpll.p2;
a0c4da24 4461
89b667f8
JB		 4462 /* See eDP HDMI DPIO driver vbios notes doc */
4463
4464 /* PLL B needs special handling */
4465 if (pipe)
5e69f97f 4466 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4467
4468 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4469 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4470
4471 /* Disable target IRef on PLL */
5e69f97f 4472 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4473 reg_val &= 0x00ffffff;
5e69f97f 4474 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4475
4476 /* Disable fast lock */
5e69f97f 4477 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4478
4479 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4480 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4481 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4482 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4483 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4484
4485 /*
4486 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4487 * but we don't support that).
4488 * Note: don't use the DAC post divider as it seems unstable.
4489 */
4490 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4491 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4492
a0c4da24 4493 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4494 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4495
89b667f8 4496 /* Set HBR and RBR LPF coefficients */
ff9a6750 4497 if (crtc->config.port_clock == 162000 ||
99750bd4 4498 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4499 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4500 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4501 0x009f0003);
89b667f8 4502 else
5e69f97f 4503 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4504 0x00d0000f);
4505
4506 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4507 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4508 /* Use SSC source */
4509 if (!pipe)
5e69f97f 4510 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4511 0x0df40000);
4512 else
5e69f97f 4513 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4514 0x0df70000);
4515 } else { /* HDMI or VGA */
4516 /* Use bend source */
4517 if (!pipe)
5e69f97f 4518 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4519 0x0df70000);
4520 else
5e69f97f 4521 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4522 0x0df40000);
4523 }
a0c4da24 4524
5e69f97f 4525 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4526 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4527 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4528 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4529 coreclk |= 0x01000000;
5e69f97f 4530 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4531
5e69f97f 4532 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4533
89b667f8
JB		 4534 /* Enable DPIO clock input */
4535 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4536 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4537 if (pipe)
4538 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4539
4540 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4541 crtc->config.dpll_hw_state.dpll = dpll;
4542
ef1b460d
DV		 4543 dpll_md = (crtc->config.pixel_multiplier - 1)
4544 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4545 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4546
89b667f8
JB		 4547 if (crtc->config.has_dp_encoder)
4548 intel_dp_set_m_n(crtc);
09153000
DV		 4549
4550 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4551}
4552
f47709a9
DV		 4553static void i9xx_update_pll(struct intel_crtc *crtc,
4554 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4555 int num_connectors)
4556{
f47709a9 4557 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4558 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4559 u32 dpll;
4560 bool is_sdvo;
f47709a9 4561 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4562
f47709a9 4563 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4564
f47709a9
DV		 4565 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4566 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4567
4568 dpll = DPLL_VGA_MODE_DIS;
4569
f47709a9 4570 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4571 dpll |= DPLLB_MODE_LVDS;
4572 else
4573 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4574
ef1b460d 4575 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4576 dpll |= (crtc->config.pixel_multiplier - 1)
4577 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4578 }
198a037f
DV		 4579
4580 if (is_sdvo)
4a33e48d 4581 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4582
f47709a9 4583 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4584 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4585
4586 /* compute bitmask from p1 value */
4587 if (IS_PINEVIEW(dev))
4588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4589 else {
4590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591 if (IS_G4X(dev) && reduced_clock)
4592 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4593 }
4594 switch (clock->p2) {
4595 case 5:
4596 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4597 break;
4598 case 7:
4599 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4600 break;
4601 case 10:
4602 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4603 break;
4604 case 14:
4605 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4606 break;
4607 }
4608 if (INTEL_INFO(dev)->gen >= 4)
4609 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4610
09ede541 4611 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4612 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4613 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4614 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4615 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4616 else
4617 dpll |= PLL_REF_INPUT_DREFCLK;
4618
4619 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4620 crtc->config.dpll_hw_state.dpll = dpll;
4621
eb1cbe48 4622 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4623 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4624 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4625 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4626 }
66e3d5c0
DV		 4627
4628 if (crtc->config.has_dp_encoder)
4629 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4630}
4631
f47709a9 4632static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4633 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4634 int num_connectors)
4635{
f47709a9 4636 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4637 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4638 u32 dpll;
f47709a9 4639 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4640
f47709a9 4641 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4642
eb1cbe48
DV		 4643 dpll = DPLL_VGA_MODE_DIS;
4644
f47709a9 4645 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4646 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4647 } else {
4648 if (clock->p1 == 2)
4649 dpll |= PLL_P1_DIVIDE_BY_TWO;
4650 else
4651 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4652 if (clock->p2 == 4)
4653 dpll |= PLL_P2_DIVIDE_BY_4;
4654 }
4655
4a33e48d
DV		 4656 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4657 dpll |= DPLL_DVO_2X_MODE;
4658
f47709a9 4659 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4660 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4661 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4662 else
4663 dpll |= PLL_REF_INPUT_DREFCLK;
4664
4665 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4666 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4667}
4668
8a654f3b 4669static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4670{
4671 struct drm_device *dev = intel_crtc->base.dev;
4672 struct drm_i915_private *dev_priv = dev->dev_private;
4673 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4674 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4675 struct drm_display_mode *adjusted_mode =
4676 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4677 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4678
4679 /* We need to be careful not to changed the adjusted mode, for otherwise
4680 * the hw state checker will get angry at the mismatch. */
4681 crtc_vtotal = adjusted_mode->crtc_vtotal;
4682 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4683
4684 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4685 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4686 crtc_vtotal -= 1;
4687 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4688 vsyncshift = adjusted_mode->crtc_hsync_start
4689 - adjusted_mode->crtc_htotal / 2;
4690 } else {
4691 vsyncshift = 0;
4692 }
4693
4694 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4695 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4696
fe2b8f9d 4697 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4698 (adjusted_mode->crtc_hdisplay - 1) |
4699 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4700 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4701 (adjusted_mode->crtc_hblank_start - 1) |
4702 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4703 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4704 (adjusted_mode->crtc_hsync_start - 1) |
4705 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4706
fe2b8f9d 4707 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4708 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4709 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4710 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4711 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4712 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4713 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4714 (adjusted_mode->crtc_vsync_start - 1) |
4715 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4716
b5e508d4
PZ		 4717 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4718 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4719 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4720 * bits. */
4721 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4722 (pipe == PIPE_B || pipe == PIPE_C))
4723 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4724
b0e77b9c
PZ		 4725 /* pipesrc controls the size that is scaled from, which should
4726 * always be the user's requested size.
4727 */
4728 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4729 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4730 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4731}
4732
1bd1bd80
DV		 4733static void intel_get_pipe_timings(struct intel_crtc *crtc,
4734 struct intel_crtc_config *pipe_config)
4735{
4736 struct drm_device *dev = crtc->base.dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4739 uint32_t tmp;
4740
4741 tmp = I915_READ(HTOTAL(cpu_transcoder));
4742 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4743 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4744 tmp = I915_READ(HBLANK(cpu_transcoder));
4745 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4746 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4747 tmp = I915_READ(HSYNC(cpu_transcoder));
4748 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4749 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4750
4751 tmp = I915_READ(VTOTAL(cpu_transcoder));
4752 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4754 tmp = I915_READ(VBLANK(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4757 tmp = I915_READ(VSYNC(cpu_transcoder));
4758 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4760
4761 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4762 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4763 pipe_config->adjusted_mode.crtc_vtotal += 1;
4764 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4765 }
4766
4767 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4768 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4769 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4770
4771 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4772 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4773}
4774
babea61d
JB		 4775static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4776 struct intel_crtc_config *pipe_config)
4777{
4778 struct drm_crtc *crtc = &intel_crtc->base;
4779
4780 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4781 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4782 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4783 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4784
4785 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4786 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4787 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4788 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4789
4790 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4791
4792 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4793 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4794}
4795
84b046f3
DV		 4796static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4797{
4798 struct drm_device *dev = intel_crtc->base.dev;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 uint32_t pipeconf;
4801
9f11a9e4 4802 pipeconf = 0;
84b046f3
DV		 4803
4804 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4805 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4806 * core speed.
4807 *
4808 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4809 * pipe == 0 check?
4810 */
a2b076b6 4811 if (intel_crtc->config.adjusted_mode.clock >
84b046f3
DV		 4812 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4813 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4814 }
4815
ff9ce46e
DV		 4816 /* only g4x and later have fancy bpc/dither controls */
4817 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4818 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4819 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4820 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4821 PIPECONF_DITHER_TYPE_SP;
84b046f3 4822
ff9ce46e
DV		 4823 switch (intel_crtc->config.pipe_bpp) {
4824 case 18:
4825 pipeconf |= PIPECONF_6BPC;
4826 break;
4827 case 24:
4828 pipeconf |= PIPECONF_8BPC;
4829 break;
4830 case 30:
4831 pipeconf |= PIPECONF_10BPC;
4832 break;
4833 default:
4834 /* Case prevented by intel_choose_pipe_bpp_dither. */
4835 BUG();
84b046f3
DV		 4836 }
4837 }
4838
4839 if (HAS_PIPE_CXSR(dev)) {
4840 if (intel_crtc->lowfreq_avail) {
4841 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4842 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4843 } else {
4844 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4845 }
4846 }
4847
84b046f3
DV		 4848 if (!IS_GEN2(dev) &&
4849 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4850 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4851 else
4852 pipeconf |= PIPECONF_PROGRESSIVE;
4853
9f11a9e4
DV		 4854 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4855 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4856
84b046f3
DV		 4857 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4858 POSTING_READ(PIPECONF(intel_crtc->pipe));
4859}
4860
f564048e 4861static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4862 int x, int y,
94352cf9 4863 struct drm_framebuffer *fb)
79e53945
JB		 4864{
4865 struct drm_device *dev = crtc->dev;
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4868 int pipe = intel_crtc->pipe;
80824003 4869 int plane = intel_crtc->plane;
c751ce4f 4870 int refclk, num_connectors = 0;
652c393a 4871 intel_clock_t clock, reduced_clock;
84b046f3 4872 u32 dspcntr;
a16af721 4873 bool ok, has_reduced_clock = false;
e9fd1c02 4874 bool is_lvds = false, is_dsi = false;
5eddb70b 4875 struct intel_encoder *encoder;
d4906093 4876 const intel_limit_t *limit;
5c3b82e2 4877 int ret;
79e53945 4878
6c2b7c12 4879 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4880 switch (encoder->type) {
79e53945
JB		 4881 case INTEL_OUTPUT_LVDS:
4882 is_lvds = true;
4883 break;
e9fd1c02
JN		 4884 case INTEL_OUTPUT_DSI:
4885 is_dsi = true;
4886 break;
79e53945 4887 }
43565a06 4888
c751ce4f 4889 num_connectors++;
79e53945
JB		 4890 }
4891
c65d77d8 4892 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4893
65ce4bf5 4894 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4895 /*
4896 * Returns a set of divisors for the desired target clock with
4897 * the given refclk, or FALSE. The returned values represent
4898 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4899 * 2) / p1 / p2.
4900 */
4901 limit = intel_limit(crtc, refclk);
4902 ok = dev_priv->display.find_dpll(limit, crtc,
4903 intel_crtc->config.port_clock,
4904 refclk, NULL, &clock);
4905 if (!ok && !intel_crtc->config.clock_set) {
4906 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4907 return -EINVAL;
4908 }
79e53945
JB		 4909 }
4910
cda4b7d3 4911 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4912 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4913
e9fd1c02 4914 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4915 /*
4916 * Ensure we match the reduced clock's P to the target clock.
4917 * If the clocks don't match, we can't switch the display clock
4918 * by using the FP0/FP1. In such case we will disable the LVDS
4919 * downclock feature.
4920 */
65ce4bf5 4921 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4922 has_reduced_clock =
4923 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4924 dev_priv->lvds_downclock,
ee9300bb 4925 refclk, &clock,
5eddb70b 4926 &reduced_clock);
7026d4ac 4927 }
f47709a9
DV		 4928 /* Compat-code for transition, will disappear. */
4929 if (!intel_crtc->config.clock_set) {
4930 intel_crtc->config.dpll.n = clock.n;
4931 intel_crtc->config.dpll.m1 = clock.m1;
4932 intel_crtc->config.dpll.m2 = clock.m2;
4933 intel_crtc->config.dpll.p1 = clock.p1;
4934 intel_crtc->config.dpll.p2 = clock.p2;
4935 }
7026d4ac 4936
e9fd1c02 4937 if (IS_GEN2(dev)) {
8a654f3b 4938 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4939 has_reduced_clock ? &reduced_clock : NULL,
4940 num_connectors);
e9fd1c02
JN		 4941 } else if (IS_VALLEYVIEW(dev)) {
4942 if (!is_dsi)
4943 vlv_update_pll(intel_crtc);
4944 } else {
f47709a9 4945 i9xx_update_pll(intel_crtc,
eb1cbe48 4946 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4947 num_connectors);
e9fd1c02 4948 }
79e53945 4949
79e53945
JB		 4950 /* Set up the display plane register */
4951 dspcntr = DISPPLANE_GAMMA_ENABLE;
4952
da6ecc5d
JB		 4953 if (!IS_VALLEYVIEW(dev)) {
4954 if (pipe == 0)
4955 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4956 else
4957 dspcntr |= DISPPLANE_SEL_PIPE_B;
4958 }
79e53945 4959
8a654f3b 4960 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4961
4962 /* pipesrc and dspsize control the size that is scaled from,
4963 * which should always be the user's requested size.
79e53945 4964 */
929c77fb 4965 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 4966 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4967 (intel_crtc->config.pipe_src_w - 1));
929c77fb 4968 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4969
84b046f3
DV		 4970 i9xx_set_pipeconf(intel_crtc);
4971
f564048e
EA		 4972 I915_WRITE(DSPCNTR(plane), dspcntr);
4973 POSTING_READ(DSPCNTR(plane));
4974
94352cf9 4975 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4976
f564048e
EA		 4977 return ret;
4978}
4979
2fa2fe9a
DV		 4980static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4981 struct intel_crtc_config *pipe_config)
4982{
4983 struct drm_device *dev = crtc->base.dev;
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 uint32_t tmp;
4986
4987 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4988 if (!(tmp & PFIT_ENABLE))
4989 return;
2fa2fe9a 4990
06922821 4991 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4992 if (INTEL_INFO(dev)->gen < 4) {
4993 if (crtc->pipe != PIPE_B)
4994 return;
2fa2fe9a
DV		 4995 } else {
4996 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4997 return;
4998 }
4999
06922821 5000 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5001 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5002 if (INTEL_INFO(dev)->gen < 5)
5003 pipe_config->gmch_pfit.lvds_border_bits =
5004 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5005}
5006
0e8ffe1b
DV		 5007static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5008 struct intel_crtc_config *pipe_config)
5009{
5010 struct drm_device *dev = crtc->base.dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 uint32_t tmp;
5013
e143a21c 5014 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5015 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5016
0e8ffe1b
DV		 5017 tmp = I915_READ(PIPECONF(crtc->pipe));
5018 if (!(tmp & PIPECONF_ENABLE))
5019 return false;
5020
42571aef
VS		 5021 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5022 switch (tmp & PIPECONF_BPC_MASK) {
5023 case PIPECONF_6BPC:
5024 pipe_config->pipe_bpp = 18;
5025 break;
5026 case PIPECONF_8BPC:
5027 pipe_config->pipe_bpp = 24;
5028 break;
5029 case PIPECONF_10BPC:
5030 pipe_config->pipe_bpp = 30;
5031 break;
5032 default:
5033 break;
5034 }
5035 }
5036
1bd1bd80
DV		 5037 intel_get_pipe_timings(crtc, pipe_config);
5038
2fa2fe9a
DV		 5039 i9xx_get_pfit_config(crtc, pipe_config);
5040
6c49f241
DV		 5041 if (INTEL_INFO(dev)->gen >= 4) {
5042 tmp = I915_READ(DPLL_MD(crtc->pipe));
5043 pipe_config->pixel_multiplier =
5044 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5045 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5046 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5047 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5048 tmp = I915_READ(DPLL(crtc->pipe));
5049 pipe_config->pixel_multiplier =
5050 ((tmp & SDVO_MULTIPLIER_MASK)
5051 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5052 } else {
5053 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5054 * port and will be fixed up in the encoder->get_config
5055 * function. */
5056 pipe_config->pixel_multiplier = 1;
5057 }
8bcc2795
DV		 5058 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5059 if (!IS_VALLEYVIEW(dev)) {
5060 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5061 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5062 } else {
5063 /* Mask out read-only status bits. */
5064 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5065 DPLL_PORTC_READY_MASK |
5066 DPLL_PORTB_READY_MASK);
8bcc2795 5067 }
6c49f241 5068
18442d08
VS		 5069 i9xx_crtc_clock_get(crtc, pipe_config);
5070
0e8ffe1b
DV		 5071 return true;
5072}
5073
dde86e2d 5074static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5075{
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5078 struct intel_encoder *encoder;
74cfd7ac 5079 u32 val, final;
13d83a67 5080 bool has_lvds = false;
199e5d79 5081 bool has_cpu_edp = false;
199e5d79 5082 bool has_panel = false;
99eb6a01
KP		 5083 bool has_ck505 = false;
5084 bool can_ssc = false;
13d83a67
JB		 5085
5086 /* We need to take the global config into account */
199e5d79
KP		 5087 list_for_each_entry(encoder, &mode_config->encoder_list,
5088 base.head) {
5089 switch (encoder->type) {
5090 case INTEL_OUTPUT_LVDS:
5091 has_panel = true;
5092 has_lvds = true;
5093 break;
5094 case INTEL_OUTPUT_EDP:
5095 has_panel = true;
2de6905f 5096 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5097 has_cpu_edp = true;
5098 break;
13d83a67
JB		 5099 }
5100 }
5101
99eb6a01 5102 if (HAS_PCH_IBX(dev)) {
41aa3448 5103 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5104 can_ssc = has_ck505;
5105 } else {
5106 has_ck505 = false;
5107 can_ssc = true;
5108 }
5109
2de6905f
ID		 5110 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5111 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5112
5113 /* Ironlake: try to setup display ref clock before DPLL
5114 * enabling. This is only under driver's control after
5115 * PCH B stepping, previous chipset stepping should be
5116 * ignoring this setting.
5117 */
74cfd7ac
CW		 5118 val = I915_READ(PCH_DREF_CONTROL);
5119
5120 /* As we must carefully and slowly disable/enable each source in turn,
5121 * compute the final state we want first and check if we need to
5122 * make any changes at all.
5123 */
5124 final = val;
5125 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5126 if (has_ck505)
5127 final |= DREF_NONSPREAD_CK505_ENABLE;
5128 else
5129 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5130
5131 final &= ~DREF_SSC_SOURCE_MASK;
5132 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5133 final &= ~DREF_SSC1_ENABLE;
5134
5135 if (has_panel) {
5136 final |= DREF_SSC_SOURCE_ENABLE;
5137
5138 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5139 final |= DREF_SSC1_ENABLE;
5140
5141 if (has_cpu_edp) {
5142 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5143 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5144 else
5145 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5146 } else
5147 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5148 } else {
5149 final |= DREF_SSC_SOURCE_DISABLE;
5150 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5151 }
5152
5153 if (final == val)
5154 return;
5155
13d83a67 5156 /* Always enable nonspread source */
74cfd7ac 5157 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5158
99eb6a01 5159 if (has_ck505)
74cfd7ac 5160 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5161 else
74cfd7ac 5162 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5163
199e5d79 5164 if (has_panel) {
74cfd7ac
CW		 5165 val &= ~DREF_SSC_SOURCE_MASK;
5166 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5167
199e5d79 5168 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5169 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5170 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5171 val |= DREF_SSC1_ENABLE;
e77166b5 5172 } else
74cfd7ac 5173 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5174
5175 /* Get SSC going before enabling the outputs */
74cfd7ac 5176 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5177 POSTING_READ(PCH_DREF_CONTROL);
5178 udelay(200);
5179
74cfd7ac 5180 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5181
5182 /* Enable CPU source on CPU attached eDP */
199e5d79 5183 if (has_cpu_edp) {
99eb6a01 5184 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5185 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5186 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5187 }
13d83a67 5188 else
74cfd7ac 5189 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5190 } else
74cfd7ac 5191 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5192
74cfd7ac 5193 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5194 POSTING_READ(PCH_DREF_CONTROL);
5195 udelay(200);
5196 } else {
5197 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5198
74cfd7ac 5199 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5200
5201 /* Turn off CPU output */
74cfd7ac 5202 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5203
74cfd7ac 5204 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5205 POSTING_READ(PCH_DREF_CONTROL);
5206 udelay(200);
5207
5208 /* Turn off the SSC source */
74cfd7ac
CW		 5209 val &= ~DREF_SSC_SOURCE_MASK;
5210 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5211
5212 /* Turn off SSC1 */
74cfd7ac 5213 val &= ~DREF_SSC1_ENABLE;
199e5d79 5214
74cfd7ac 5215 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5216 POSTING_READ(PCH_DREF_CONTROL);
5217 udelay(200);
5218 }
74cfd7ac
CW		 5219
5220 BUG_ON(val != final);
13d83a67
JB		 5221}
5222
f31f2d55 5223static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5224{
f31f2d55 5225 uint32_t tmp;
dde86e2d 5226
0ff066a9
PZ		 5227 tmp = I915_READ(SOUTH_CHICKEN2);
5228 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5229 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5230
0ff066a9
PZ		 5231 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5232 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5233 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5234
0ff066a9
PZ		 5235 tmp = I915_READ(SOUTH_CHICKEN2);
5236 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5237 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5238
0ff066a9
PZ		 5239 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5240 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5241 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5242}
5243
5244/* WaMPhyProgramming:hsw */
5245static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5246{
5247 uint32_t tmp;
dde86e2d
PZ		 5248
5249 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5250 tmp &= ~(0xFF << 24);
5251 tmp |= (0x12 << 24);
5252 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5253
dde86e2d
PZ		 5254 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5255 tmp |= (1 << 11);
5256 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5259 tmp |= (1 << 11);
5260 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5261
dde86e2d
PZ		 5262 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5263 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5264 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5265
5266 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5267 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5268 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5269
0ff066a9
PZ		 5270 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5271 tmp &= ~(7 << 13);
5272 tmp |= (5 << 13);
5273 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5274
0ff066a9
PZ		 5275 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5276 tmp &= ~(7 << 13);
5277 tmp |= (5 << 13);
5278 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5279
5280 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5281 tmp &= ~0xFF;
5282 tmp |= 0x1C;
5283 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5284
5285 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5286 tmp &= ~0xFF;
5287 tmp |= 0x1C;
5288 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5289
5290 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5291 tmp &= ~(0xFF << 16);
5292 tmp |= (0x1C << 16);
5293 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5294
5295 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5296 tmp &= ~(0xFF << 16);
5297 tmp |= (0x1C << 16);
5298 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5299
0ff066a9
PZ		 5300 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5301 tmp |= (1 << 27);
5302 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5303
0ff066a9
PZ		 5304 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5305 tmp |= (1 << 27);
5306 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5307
0ff066a9
PZ		 5308 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5309 tmp &= ~(0xF << 28);
5310 tmp |= (4 << 28);
5311 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5312
0ff066a9
PZ		 5313 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5314 tmp &= ~(0xF << 28);
5315 tmp |= (4 << 28);
5316 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5317}
5318
2fa86a1f
PZ		 5319/* Implements 3 different sequences from BSpec chapter "Display iCLK
5320 * Programming" based on the parameters passed:
5321 * - Sequence to enable CLKOUT_DP
5322 * - Sequence to enable CLKOUT_DP without spread
5323 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5324 */
5325static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5326 bool with_fdi)
f31f2d55
PZ		 5327{
5328 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5329 uint32_t reg, tmp;
5330
5331 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5332 with_spread = true;
5333 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5334 with_fdi, "LP PCH doesn't have FDI\n"))
5335 with_fdi = false;
f31f2d55
PZ		 5336
5337 mutex_lock(&dev_priv->dpio_lock);
5338
5339 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5340 tmp &= ~SBI_SSCCTL_DISABLE;
5341 tmp |= SBI_SSCCTL_PATHALT;
5342 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5343
5344 udelay(24);
5345
2fa86a1f
PZ		 5346 if (with_spread) {
5347 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5348 tmp &= ~SBI_SSCCTL_PATHALT;
5349 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5350
2fa86a1f
PZ		 5351 if (with_fdi) {
5352 lpt_reset_fdi_mphy(dev_priv);
5353 lpt_program_fdi_mphy(dev_priv);
5354 }
5355 }
dde86e2d 5356
2fa86a1f
PZ		 5357 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5358 SBI_GEN0 : SBI_DBUFF0;
5359 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5360 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5361 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5362
5363 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5364}
5365
47701c3b
PZ		 5366/* Sequence to disable CLKOUT_DP */
5367static void lpt_disable_clkout_dp(struct drm_device *dev)
5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 uint32_t reg, tmp;
5371
5372 mutex_lock(&dev_priv->dpio_lock);
5373
5374 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5375 SBI_GEN0 : SBI_DBUFF0;
5376 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5377 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5378 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5379
5380 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5381 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5382 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5383 tmp |= SBI_SSCCTL_PATHALT;
5384 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5385 udelay(32);
5386 }
5387 tmp |= SBI_SSCCTL_DISABLE;
5388 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5389 }
5390
5391 mutex_unlock(&dev_priv->dpio_lock);
5392}
5393
bf8fa3d3
PZ		 5394static void lpt_init_pch_refclk(struct drm_device *dev)
5395{
5396 struct drm_mode_config *mode_config = &dev->mode_config;
5397 struct intel_encoder *encoder;
5398 bool has_vga = false;
5399
5400 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5401 switch (encoder->type) {
5402 case INTEL_OUTPUT_ANALOG:
5403 has_vga = true;
5404 break;
5405 }
5406 }
5407
47701c3b
PZ		 5408 if (has_vga)
5409 lpt_enable_clkout_dp(dev, true, true);
5410 else
5411 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5412}
5413
dde86e2d
PZ		 5414/*
5415 * Initialize reference clocks when the driver loads
5416 */
5417void intel_init_pch_refclk(struct drm_device *dev)
5418{
5419 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5420 ironlake_init_pch_refclk(dev);
5421 else if (HAS_PCH_LPT(dev))
5422 lpt_init_pch_refclk(dev);
5423}
5424
d9d444cb
JB		 5425static int ironlake_get_refclk(struct drm_crtc *crtc)
5426{
5427 struct drm_device *dev = crtc->dev;
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5429 struct intel_encoder *encoder;
d9d444cb
JB		 5430 int num_connectors = 0;
5431 bool is_lvds = false;
5432
6c2b7c12 5433 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5434 switch (encoder->type) {
5435 case INTEL_OUTPUT_LVDS:
5436 is_lvds = true;
5437 break;
d9d444cb
JB		 5438 }
5439 num_connectors++;
5440 }
5441
5442 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5443 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5444 dev_priv->vbt.lvds_ssc_freq);
5445 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5446 }
5447
5448 return 120000;
5449}
5450
6ff93609 5451static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5452{
c8203565 5453 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5455 int pipe = intel_crtc->pipe;
c8203565
PZ		 5456 uint32_t val;
5457
78114071 5458 val = 0;
c8203565 5459
965e0c48 5460 switch (intel_crtc->config.pipe_bpp) {
c8203565 5461 case 18:
dfd07d72 5462 val |= PIPECONF_6BPC;
c8203565
PZ		 5463 break;
5464 case 24:
dfd07d72 5465 val |= PIPECONF_8BPC;
c8203565
PZ		 5466 break;
5467 case 30:
dfd07d72 5468 val |= PIPECONF_10BPC;
c8203565
PZ		 5469 break;
5470 case 36:
dfd07d72 5471 val |= PIPECONF_12BPC;
c8203565
PZ		 5472 break;
5473 default:
cc769b62
PZ		 5474 /* Case prevented by intel_choose_pipe_bpp_dither. */
5475 BUG();
c8203565
PZ		 5476 }
5477
d8b32247 5478 if (intel_crtc->config.dither)
c8203565
PZ		 5479 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5480
6ff93609 5481 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5482 val |= PIPECONF_INTERLACED_ILK;
5483 else
5484 val |= PIPECONF_PROGRESSIVE;
5485
50f3b016 5486 if (intel_crtc->config.limited_color_range)
3685a8f3 5487 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5488
c8203565
PZ		 5489 I915_WRITE(PIPECONF(pipe), val);
5490 POSTING_READ(PIPECONF(pipe));
5491}
5492
86d3efce
VS		 5493/*
5494 * Set up the pipe CSC unit.
5495 *
5496 * Currently only full range RGB to limited range RGB conversion
5497 * is supported, but eventually this should handle various
5498 * RGB<->YCbCr scenarios as well.
5499 */
50f3b016 5500static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5501{
5502 struct drm_device *dev = crtc->dev;
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5505 int pipe = intel_crtc->pipe;
5506 uint16_t coeff = 0x7800; /* 1.0 */
5507
5508 /*
5509 * TODO: Check what kind of values actually come out of the pipe
5510 * with these coeff/postoff values and adjust to get the best
5511 * accuracy. Perhaps we even need to take the bpc value into
5512 * consideration.
5513 */
5514
50f3b016 5515 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5516 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5517
5518 /*
5519 * GY/GU and RY/RU should be the other way around according
5520 * to BSpec, but reality doesn't agree. Just set them up in
5521 * a way that results in the correct picture.
5522 */
5523 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5524 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5525
5526 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5527 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5528
5529 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5530 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5531
5532 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5533 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5534 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5535
5536 if (INTEL_INFO(dev)->gen > 6) {
5537 uint16_t postoff = 0;
5538
50f3b016 5539 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5540 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5541
5542 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5543 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5544 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5545
5546 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5547 } else {
5548 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5549
50f3b016 5550 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5551 mode |= CSC_BLACK_SCREEN_OFFSET;
5552
5553 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5554 }
5555}
5556
6ff93609 5557static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5558{
5559 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5561 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5562 uint32_t val;
5563
3eff4faa 5564 val = 0;
ee2b0b38 5565
d8b32247 5566 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5567 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5568
6ff93609 5569 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5570 val |= PIPECONF_INTERLACED_ILK;
5571 else
5572 val |= PIPECONF_PROGRESSIVE;
5573
702e7a56
PZ		 5574 I915_WRITE(PIPECONF(cpu_transcoder), val);
5575 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5576
5577 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5578 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5579}
5580
6591c6e4 5581static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5582 intel_clock_t *clock,
5583 bool *has_reduced_clock,
5584 intel_clock_t *reduced_clock)
5585{
5586 struct drm_device *dev = crtc->dev;
5587 struct drm_i915_private *dev_priv = dev->dev_private;
5588 struct intel_encoder *intel_encoder;
5589 int refclk;
d4906093 5590 const intel_limit_t *limit;
a16af721 5591 bool ret, is_lvds = false;
79e53945 5592
6591c6e4
PZ		 5593 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5594 switch (intel_encoder->type) {
79e53945
JB		 5595 case INTEL_OUTPUT_LVDS:
5596 is_lvds = true;
5597 break;
79e53945
JB		 5598 }
5599 }
5600
d9d444cb 5601 refclk = ironlake_get_refclk(crtc);
79e53945 5602
d4906093
ML		 5603 /*
5604 * Returns a set of divisors for the desired target clock with the given
5605 * refclk, or FALSE. The returned values represent the clock equation:
5606 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5607 */
1b894b59 5608 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5609 ret = dev_priv->display.find_dpll(limit, crtc,
5610 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5611 refclk, NULL, clock);
6591c6e4
PZ		 5612 if (!ret)
5613 return false;
cda4b7d3 5614
ddc9003c 5615 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5616 /*
5617 * Ensure we match the reduced clock's P to the target clock.
5618 * If the clocks don't match, we can't switch the display clock
5619 * by using the FP0/FP1. In such case we will disable the LVDS
5620 * downclock feature.
5621 */
ee9300bb
DV		 5622 *has_reduced_clock =
5623 dev_priv->display.find_dpll(limit, crtc,
5624 dev_priv->lvds_downclock,
5625 refclk, clock,
5626 reduced_clock);
652c393a 5627 }
61e9653f 5628
6591c6e4
PZ		 5629 return true;
5630}
5631
01a415fd
DV		 5632static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5633{
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635 uint32_t temp;
5636
5637 temp = I915_READ(SOUTH_CHICKEN1);
5638 if (temp & FDI_BC_BIFURCATION_SELECT)
5639 return;
5640
5641 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5642 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5643
5644 temp |= FDI_BC_BIFURCATION_SELECT;
5645 DRM_DEBUG_KMS("enabling fdi C rx\n");
5646 I915_WRITE(SOUTH_CHICKEN1, temp);
5647 POSTING_READ(SOUTH_CHICKEN1);
5648}
5649
ebfd86fd 5650static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5651{
5652 struct drm_device *dev = intel_crtc->base.dev;
5653 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5654
5655 switch (intel_crtc->pipe) {
5656 case PIPE_A:
ebfd86fd 5657 break;
01a415fd 5658 case PIPE_B:
ebfd86fd 5659 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5660 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5661 else
5662 cpt_enable_fdi_bc_bifurcation(dev);
5663
ebfd86fd 5664 break;
01a415fd 5665 case PIPE_C:
01a415fd
DV		 5666 cpt_enable_fdi_bc_bifurcation(dev);
5667
ebfd86fd 5668 break;
01a415fd
DV		 5669 default:
5670 BUG();
5671 }
5672}
5673
d4b1931c
PZ		 5674int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5675{
5676 /*
5677 * Account for spread spectrum to avoid
5678 * oversubscribing the link. Max center spread
5679 * is 2.5%; use 5% for safety's sake.
5680 */
5681 u32 bps = target_clock * bpp * 21 / 20;
5682 return bps / (link_bw * 8) + 1;
5683}
5684
7429e9d4 5685static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5686{
7429e9d4 5687 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5688}
5689
de13a2e3 5690static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5691 u32 *fp,
9a7c7890 5692 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5693{
de13a2e3 5694 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5695 struct drm_device *dev = crtc->dev;
5696 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5697 struct intel_encoder *intel_encoder;
5698 uint32_t dpll;
6cc5f341 5699 int factor, num_connectors = 0;
09ede541 5700 bool is_lvds = false, is_sdvo = false;
79e53945 5701
de13a2e3
PZ		 5702 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5703 switch (intel_encoder->type) {
79e53945
JB		 5704 case INTEL_OUTPUT_LVDS:
5705 is_lvds = true;
5706 break;
5707 case INTEL_OUTPUT_SDVO:
7d57382e 5708 case INTEL_OUTPUT_HDMI:
79e53945 5709 is_sdvo = true;
79e53945 5710 break;
79e53945 5711 }
43565a06 5712
c751ce4f 5713 num_connectors++;
79e53945 5714 }
79e53945 5715
c1858123 5716 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5717 factor = 21;
5718 if (is_lvds) {
5719 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5720 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5721 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5722 factor = 25;
09ede541 5723 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5724 factor = 20;
c1858123 5725
7429e9d4 5726 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5727 *fp |= FP_CB_TUNE;
2c07245f 5728
9a7c7890
DV		 5729 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5730 *fp2 |= FP_CB_TUNE;
5731
5eddb70b 5732 dpll = 0;
2c07245f 5733
a07d6787
EA		 5734 if (is_lvds)
5735 dpll |= DPLLB_MODE_LVDS;
5736 else
5737 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5738
ef1b460d
DV		 5739 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5740 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5741
5742 if (is_sdvo)
4a33e48d 5743 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5744 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5745 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5746
a07d6787 5747 /* compute bitmask from p1 value */
7429e9d4 5748 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5749 /* also FPA1 */
7429e9d4 5750 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5751
7429e9d4 5752 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5753 case 5:
5754 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5755 break;
5756 case 7:
5757 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5758 break;
5759 case 10:
5760 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5761 break;
5762 case 14:
5763 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5764 break;
79e53945
JB		 5765 }
5766
b4c09f3b 5767 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5768 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5769 else
5770 dpll |= PLL_REF_INPUT_DREFCLK;
5771
959e16d6 5772 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5773}
5774
5775static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5776 int x, int y,
5777 struct drm_framebuffer *fb)
5778{
5779 struct drm_device *dev = crtc->dev;
5780 struct drm_i915_private *dev_priv = dev->dev_private;
5781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5782 int pipe = intel_crtc->pipe;
5783 int plane = intel_crtc->plane;
5784 int num_connectors = 0;
5785 intel_clock_t clock, reduced_clock;
cbbab5bd 5786 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5787 bool ok, has_reduced_clock = false;
8b47047b 5788 bool is_lvds = false;
de13a2e3 5789 struct intel_encoder *encoder;
e2b78267 5790 struct intel_shared_dpll *pll;
de13a2e3 5791 int ret;
de13a2e3
PZ		 5792
5793 for_each_encoder_on_crtc(dev, crtc, encoder) {
5794 switch (encoder->type) {
5795 case INTEL_OUTPUT_LVDS:
5796 is_lvds = true;
5797 break;
de13a2e3
PZ		 5798 }
5799
5800 num_connectors++;
a07d6787 5801 }
79e53945 5802
5dc5298b
PZ		 5803 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5804 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5805
ff9a6750 5806 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5807 &has_reduced_clock, &reduced_clock);
ee9300bb 5808 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5809 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5810 return -EINVAL;
79e53945 5811 }
f47709a9
DV		 5812 /* Compat-code for transition, will disappear. */
5813 if (!intel_crtc->config.clock_set) {
5814 intel_crtc->config.dpll.n = clock.n;
5815 intel_crtc->config.dpll.m1 = clock.m1;
5816 intel_crtc->config.dpll.m2 = clock.m2;
5817 intel_crtc->config.dpll.p1 = clock.p1;
5818 intel_crtc->config.dpll.p2 = clock.p2;
5819 }
79e53945 5820
de13a2e3
PZ		 5821 /* Ensure that the cursor is valid for the new mode before changing... */
5822 intel_crtc_update_cursor(crtc, true);
5823
5dc5298b 5824 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5825 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5826 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5827 if (has_reduced_clock)
7429e9d4 5828 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5829
7429e9d4 5830 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5831 &fp, &reduced_clock,
5832 has_reduced_clock ? &fp2 : NULL);
5833
959e16d6 5834 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5835 intel_crtc->config.dpll_hw_state.fp0 = fp;
5836 if (has_reduced_clock)
5837 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5838 else
5839 intel_crtc->config.dpll_hw_state.fp1 = fp;
5840
b89a1d39 5841 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5842 if (pll == NULL) {
84f44ce7
VS		 5843 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5844 pipe_name(pipe));
4b645f14
JB		 5845 return -EINVAL;
5846 }
ee7b9f93 5847 } else
e72f9fbf 5848 intel_put_shared_dpll(intel_crtc);
79e53945 5849
03afc4a2
DV		 5850 if (intel_crtc->config.has_dp_encoder)
5851 intel_dp_set_m_n(intel_crtc);
79e53945 5852
bcd644e0
DV		 5853 if (is_lvds && has_reduced_clock && i915_powersave)
5854 intel_crtc->lowfreq_avail = true;
5855 else
5856 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5857
5858 if (intel_crtc->config.has_pch_encoder) {
5859 pll = intel_crtc_to_shared_dpll(intel_crtc);
5860
652c393a
JB		 5861 }
5862
8a654f3b 5863 intel_set_pipe_timings(intel_crtc);
5eddb70b 5864
ca3a0ff8 5865 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5866 intel_cpu_transcoder_set_m_n(intel_crtc,
5867 &intel_crtc->config.fdi_m_n);
5868 }
2c07245f 5869
ebfd86fd
DV		 5870 if (IS_IVYBRIDGE(dev))
5871 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5872
6ff93609 5873 ironlake_set_pipeconf(crtc);
79e53945 5874
a1f9e77e
PZ		 5875 /* Set up the display plane register */
5876 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5877 POSTING_READ(DSPCNTR(plane));
79e53945 5878
94352cf9 5879 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5880
1857e1da 5881 return ret;
79e53945
JB		 5882}
5883
eb14cb74
VS		 5884static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5885 struct intel_link_m_n *m_n)
5886{
5887 struct drm_device *dev = crtc->base.dev;
5888 struct drm_i915_private *dev_priv = dev->dev_private;
5889 enum pipe pipe = crtc->pipe;
5890
5891 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5892 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5893 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5894 & ~TU_SIZE_MASK;
5895 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5896 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5897 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5898}
5899
5900static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5901 enum transcoder transcoder,
5902 struct intel_link_m_n *m_n)
72419203
DV		 5903{
5904 struct drm_device *dev = crtc->base.dev;
5905 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5906 enum pipe pipe = crtc->pipe;
5907
5908 if (INTEL_INFO(dev)->gen >= 5) {
5909 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5910 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5911 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5912 & ~TU_SIZE_MASK;
5913 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5914 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5915 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5916 } else {
5917 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5918 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5919 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5920 & ~TU_SIZE_MASK;
5921 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5922 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5923 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5924 }
5925}
5926
5927void intel_dp_get_m_n(struct intel_crtc *crtc,
5928 struct intel_crtc_config *pipe_config)
5929{
5930 if (crtc->config.has_pch_encoder)
5931 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5932 else
5933 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5934 &pipe_config->dp_m_n);
5935}
72419203 5936
eb14cb74
VS		 5937static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5938 struct intel_crtc_config *pipe_config)
5939{
5940 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5941 &pipe_config->fdi_m_n);
72419203
DV		 5942}
5943
2fa2fe9a
DV		 5944static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5945 struct intel_crtc_config *pipe_config)
5946{
5947 struct drm_device *dev = crtc->base.dev;
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949 uint32_t tmp;
5950
5951 tmp = I915_READ(PF_CTL(crtc->pipe));
5952
5953 if (tmp & PF_ENABLE) {
5954 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5955 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5956
5957 /* We currently do not free assignements of panel fitters on
5958 * ivb/hsw (since we don't use the higher upscaling modes which
5959 * differentiates them) so just WARN about this case for now. */
5960 if (IS_GEN7(dev)) {
5961 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5962 PF_PIPE_SEL_IVB(crtc->pipe));
5963 }
2fa2fe9a 5964 }
79e53945
JB		 5965}
5966
0e8ffe1b
DV		 5967static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5968 struct intel_crtc_config *pipe_config)
5969{
5970 struct drm_device *dev = crtc->base.dev;
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 uint32_t tmp;
5973
e143a21c 5974 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5975 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5976
0e8ffe1b
DV		 5977 tmp = I915_READ(PIPECONF(crtc->pipe));
5978 if (!(tmp & PIPECONF_ENABLE))
5979 return false;
5980
42571aef
VS		 5981 switch (tmp & PIPECONF_BPC_MASK) {
5982 case PIPECONF_6BPC:
5983 pipe_config->pipe_bpp = 18;
5984 break;
5985 case PIPECONF_8BPC:
5986 pipe_config->pipe_bpp = 24;
5987 break;
5988 case PIPECONF_10BPC:
5989 pipe_config->pipe_bpp = 30;
5990 break;
5991 case PIPECONF_12BPC:
5992 pipe_config->pipe_bpp = 36;
5993 break;
5994 default:
5995 break;
5996 }
5997
ab9412ba 5998 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5999 struct intel_shared_dpll *pll;
6000
88adfff1
DV		 6001 pipe_config->has_pch_encoder = true;
6002
627eb5a3
DV		 6003 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6004 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6005 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6006
6007 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6008
c0d43d62 6009 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6010 pipe_config->shared_dpll =
6011 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6012 } else {
6013 tmp = I915_READ(PCH_DPLL_SEL);
6014 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6015 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6016 else
6017 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6018 }
66e985c0
DV		 6019
6020 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6021
6022 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6023 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6024
6025 tmp = pipe_config->dpll_hw_state.dpll;
6026 pipe_config->pixel_multiplier =
6027 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6028 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6029
6030 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6031 } else {
6032 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6033 }
6034
1bd1bd80
DV		 6035 intel_get_pipe_timings(crtc, pipe_config);
6036
2fa2fe9a
DV		 6037 ironlake_get_pfit_config(crtc, pipe_config);
6038
0e8ffe1b
DV		 6039 return true;
6040}
6041
be256dc7
PZ		 6042static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6043{
6044 struct drm_device *dev = dev_priv->dev;
6045 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6046 struct intel_crtc *crtc;
6047 unsigned long irqflags;
bd633a7c 6048 uint32_t val;
be256dc7
PZ		 6049
6050 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6051 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6052 pipe_name(crtc->pipe));
6053
6054 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6055 WARN(plls->spll_refcount, "SPLL enabled\n");
6056 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6057 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6058 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6059 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6060 "CPU PWM1 enabled\n");
6061 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6062 "CPU PWM2 enabled\n");
6063 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6064 "PCH PWM1 enabled\n");
6065 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6066 "Utility pin enabled\n");
6067 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6068
6069 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6070 val = I915_READ(DEIMR);
6071 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6072 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6073 val = I915_READ(SDEIMR);
bd633a7c 6074 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6075 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6076 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6077}
6078
6079/*
6080 * This function implements pieces of two sequences from BSpec:
6081 * - Sequence for display software to disable LCPLL
6082 * - Sequence for display software to allow package C8+
6083 * The steps implemented here are just the steps that actually touch the LCPLL
6084 * register. Callers should take care of disabling all the display engine
6085 * functions, doing the mode unset, fixing interrupts, etc.
6086 */
6087void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6088 bool switch_to_fclk, bool allow_power_down)
6089{
6090 uint32_t val;
6091
6092 assert_can_disable_lcpll(dev_priv);
6093
6094 val = I915_READ(LCPLL_CTL);
6095
6096 if (switch_to_fclk) {
6097 val |= LCPLL_CD_SOURCE_FCLK;
6098 I915_WRITE(LCPLL_CTL, val);
6099
6100 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6101 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6102 DRM_ERROR("Switching to FCLK failed\n");
6103
6104 val = I915_READ(LCPLL_CTL);
6105 }
6106
6107 val |= LCPLL_PLL_DISABLE;
6108 I915_WRITE(LCPLL_CTL, val);
6109 POSTING_READ(LCPLL_CTL);
6110
6111 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6112 DRM_ERROR("LCPLL still locked\n");
6113
6114 val = I915_READ(D_COMP);
6115 val |= D_COMP_COMP_DISABLE;
6116 I915_WRITE(D_COMP, val);
6117 POSTING_READ(D_COMP);
6118 ndelay(100);
6119
6120 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6121 DRM_ERROR("D_COMP RCOMP still in progress\n");
6122
6123 if (allow_power_down) {
6124 val = I915_READ(LCPLL_CTL);
6125 val |= LCPLL_POWER_DOWN_ALLOW;
6126 I915_WRITE(LCPLL_CTL, val);
6127 POSTING_READ(LCPLL_CTL);
6128 }
6129}
6130
6131/*
6132 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6133 * source.
6134 */
6135void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6136{
6137 uint32_t val;
6138
6139 val = I915_READ(LCPLL_CTL);
6140
6141 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6142 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6143 return;
6144
215733fa
PZ		 6145 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6146 * we'll hang the machine! */
6147 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6148
be256dc7
PZ		 6149 if (val & LCPLL_POWER_DOWN_ALLOW) {
6150 val &= ~LCPLL_POWER_DOWN_ALLOW;
6151 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6152 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6153 }
6154
6155 val = I915_READ(D_COMP);
6156 val |= D_COMP_COMP_FORCE;
6157 val &= ~D_COMP_COMP_DISABLE;
6158 I915_WRITE(D_COMP, val);
35d8f2eb 6159 POSTING_READ(D_COMP);
be256dc7
PZ		 6160
6161 val = I915_READ(LCPLL_CTL);
6162 val &= ~LCPLL_PLL_DISABLE;
6163 I915_WRITE(LCPLL_CTL, val);
6164
6165 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6166 DRM_ERROR("LCPLL not locked yet\n");
6167
6168 if (val & LCPLL_CD_SOURCE_FCLK) {
6169 val = I915_READ(LCPLL_CTL);
6170 val &= ~LCPLL_CD_SOURCE_FCLK;
6171 I915_WRITE(LCPLL_CTL, val);
6172
6173 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6174 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6175 DRM_ERROR("Switching back to LCPLL failed\n");
6176 }
215733fa
PZ		 6177
6178 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6179}
6180
c67a470b
PZ		 6181void hsw_enable_pc8_work(struct work_struct *__work)
6182{
6183 struct drm_i915_private *dev_priv =
6184 container_of(to_delayed_work(__work), struct drm_i915_private,
6185 pc8.enable_work);
6186 struct drm_device *dev = dev_priv->dev;
6187 uint32_t val;
6188
6189 if (dev_priv->pc8.enabled)
6190 return;
6191
6192 DRM_DEBUG_KMS("Enabling package C8+\n");
6193
6194 dev_priv->pc8.enabled = true;
6195
6196 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6197 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6198 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6199 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6200 }
6201
6202 lpt_disable_clkout_dp(dev);
6203 hsw_pc8_disable_interrupts(dev);
6204 hsw_disable_lcpll(dev_priv, true, true);
6205}
6206
6207static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6208{
6209 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6210 WARN(dev_priv->pc8.disable_count < 1,
6211 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6212
6213 dev_priv->pc8.disable_count--;
6214 if (dev_priv->pc8.disable_count != 0)
6215 return;
6216
6217 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6218 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6219}
6220
6221static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6222{
6223 struct drm_device *dev = dev_priv->dev;
6224 uint32_t val;
6225
6226 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6227 WARN(dev_priv->pc8.disable_count < 0,
6228 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6229
6230 dev_priv->pc8.disable_count++;
6231 if (dev_priv->pc8.disable_count != 1)
6232 return;
6233
6234 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6235 if (!dev_priv->pc8.enabled)
6236 return;
6237
6238 DRM_DEBUG_KMS("Disabling package C8+\n");
6239
6240 hsw_restore_lcpll(dev_priv);
6241 hsw_pc8_restore_interrupts(dev);
6242 lpt_init_pch_refclk(dev);
6243
6244 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6245 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6246 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6247 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6248 }
6249
6250 intel_prepare_ddi(dev);
6251 i915_gem_init_swizzling(dev);
6252 mutex_lock(&dev_priv->rps.hw_lock);
6253 gen6_update_ring_freq(dev);
6254 mutex_unlock(&dev_priv->rps.hw_lock);
6255 dev_priv->pc8.enabled = false;
6256}
6257
6258void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6259{
6260 mutex_lock(&dev_priv->pc8.lock);
6261 __hsw_enable_package_c8(dev_priv);
6262 mutex_unlock(&dev_priv->pc8.lock);
6263}
6264
6265void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6266{
6267 mutex_lock(&dev_priv->pc8.lock);
6268 __hsw_disable_package_c8(dev_priv);
6269 mutex_unlock(&dev_priv->pc8.lock);
6270}
6271
6272static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6273{
6274 struct drm_device *dev = dev_priv->dev;
6275 struct intel_crtc *crtc;
6276 uint32_t val;
6277
6278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6279 if (crtc->base.enabled)
6280 return false;
6281
6282 /* This case is still possible since we have the i915.disable_power_well
6283 * parameter and also the KVMr or something else might be requesting the
6284 * power well. */
6285 val = I915_READ(HSW_PWR_WELL_DRIVER);
6286 if (val != 0) {
6287 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6288 return false;
6289 }
6290
6291 return true;
6292}
6293
6294/* Since we're called from modeset_global_resources there's no way to
6295 * symmetrically increase and decrease the refcount, so we use
6296 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6297 * or not.
6298 */
6299static void hsw_update_package_c8(struct drm_device *dev)
6300{
6301 struct drm_i915_private *dev_priv = dev->dev_private;
6302 bool allow;
6303
6304 if (!i915_enable_pc8)
6305 return;
6306
6307 mutex_lock(&dev_priv->pc8.lock);
6308
6309 allow = hsw_can_enable_package_c8(dev_priv);
6310
6311 if (allow == dev_priv->pc8.requirements_met)
6312 goto done;
6313
6314 dev_priv->pc8.requirements_met = allow;
6315
6316 if (allow)
6317 __hsw_enable_package_c8(dev_priv);
6318 else
6319 __hsw_disable_package_c8(dev_priv);
6320
6321done:
6322 mutex_unlock(&dev_priv->pc8.lock);
6323}
6324
6325static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6326{
6327 if (!dev_priv->pc8.gpu_idle) {
6328 dev_priv->pc8.gpu_idle = true;
6329 hsw_enable_package_c8(dev_priv);
6330 }
6331}
6332
6333static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6334{
6335 if (dev_priv->pc8.gpu_idle) {
6336 dev_priv->pc8.gpu_idle = false;
6337 hsw_disable_package_c8(dev_priv);
6338 }
be256dc7
PZ		 6339}
6340
d6dd9eb1
DV		 6341static void haswell_modeset_global_resources(struct drm_device *dev)
6342{
d6dd9eb1
DV		 6343 bool enable = false;
6344 struct intel_crtc *crtc;
d6dd9eb1
DV		 6345
6346 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6347 if (!crtc->base.enabled)
6348 continue;
d6dd9eb1 6349
e7a639c4
DV		 6350 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6351 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6352 enable = true;
6353 }
6354
d6dd9eb1 6355 intel_set_power_well(dev, enable);
c67a470b
PZ		 6356
6357 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6358}
6359
09b4ddf9 6360static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6361 int x, int y,
6362 struct drm_framebuffer *fb)
6363{
6364 struct drm_device *dev = crtc->dev;
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6367 int plane = intel_crtc->plane;
09b4ddf9 6368 int ret;
09b4ddf9 6369
ff9a6750 6370 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6371 return -EINVAL;
6372
09b4ddf9
PZ		 6373 /* Ensure that the cursor is valid for the new mode before changing... */
6374 intel_crtc_update_cursor(crtc, true);
6375
03afc4a2
DV		 6376 if (intel_crtc->config.has_dp_encoder)
6377 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6378
6379 intel_crtc->lowfreq_avail = false;
09b4ddf9 6380
8a654f3b 6381 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6382
ca3a0ff8 6383 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6384 intel_cpu_transcoder_set_m_n(intel_crtc,
6385 &intel_crtc->config.fdi_m_n);
6386 }
09b4ddf9 6387
6ff93609 6388 haswell_set_pipeconf(crtc);
09b4ddf9 6389
50f3b016 6390 intel_set_pipe_csc(crtc);
86d3efce 6391
09b4ddf9 6392 /* Set up the display plane register */
86d3efce 6393 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6394 POSTING_READ(DSPCNTR(plane));
6395
6396 ret = intel_pipe_set_base(crtc, x, y, fb);
6397
1f803ee5 6398 return ret;
79e53945
JB		 6399}
6400
0e8ffe1b
DV		 6401static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6402 struct intel_crtc_config *pipe_config)
6403{
6404 struct drm_device *dev = crtc->base.dev;
6405 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6406 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6407 uint32_t tmp;
6408
e143a21c 6409 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6410 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6411
eccb140b
DV		 6412 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6413 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6414 enum pipe trans_edp_pipe;
6415 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6416 default:
6417 WARN(1, "unknown pipe linked to edp transcoder\n");
6418 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6419 case TRANS_DDI_EDP_INPUT_A_ON:
6420 trans_edp_pipe = PIPE_A;
6421 break;
6422 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6423 trans_edp_pipe = PIPE_B;
6424 break;
6425 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6426 trans_edp_pipe = PIPE_C;
6427 break;
6428 }
6429
6430 if (trans_edp_pipe == crtc->pipe)
6431 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6432 }
6433
b97186f0 6434 if (!intel_display_power_enabled(dev,
eccb140b 6435 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6436 return false;
6437
eccb140b 6438 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6439 if (!(tmp & PIPECONF_ENABLE))
6440 return false;
6441
88adfff1 6442 /*
f196e6be 6443 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6444 * DDI E. So just check whether this pipe is wired to DDI E and whether
6445 * the PCH transcoder is on.
6446 */
eccb140b 6447 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6448 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6449 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6450 pipe_config->has_pch_encoder = true;
6451
627eb5a3
DV		 6452 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6453 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6454 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6455
6456 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6457 }
6458
1bd1bd80
DV		 6459 intel_get_pipe_timings(crtc, pipe_config);
6460
2fa2fe9a
DV		 6461 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6462 if (intel_display_power_enabled(dev, pfit_domain))
6463 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6464
42db64ef
PZ		 6465 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6466 (I915_READ(IPS_CTL) & IPS_ENABLE);
6467
6c49f241
DV		 6468 pipe_config->pixel_multiplier = 1;
6469
0e8ffe1b
DV		 6470 return true;
6471}
6472
f564048e 6473static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6474 int x, int y,
94352cf9 6475 struct drm_framebuffer *fb)
f564048e
EA		 6476{
6477 struct drm_device *dev = crtc->dev;
6478 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6479 struct intel_encoder *encoder;
0b701d27 6480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6481 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6482 int pipe = intel_crtc->pipe;
f564048e
EA		 6483 int ret;
6484
0b701d27 6485 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6486
b8cecdf5
DV		 6487 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6488
79e53945 6489 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6490
9256aa19
DV		 6491 if (ret != 0)
6492 return ret;
6493
6494 for_each_encoder_on_crtc(dev, crtc, encoder) {
6495 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6496 encoder->base.base.id,
6497 drm_get_encoder_name(&encoder->base),
6498 mode->base.id, mode->name);
36f2d1f1 6499 encoder->mode_set(encoder);
9256aa19
DV		 6500 }
6501
6502 return 0;
79e53945
JB		 6503}
6504
3a9627f4
WF		 6505static bool intel_eld_uptodate(struct drm_connector *connector,
6506 int reg_eldv, uint32_t bits_eldv,
6507 int reg_elda, uint32_t bits_elda,
6508 int reg_edid)
6509{
6510 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6511 uint8_t *eld = connector->eld;
6512 uint32_t i;
6513
6514 i = I915_READ(reg_eldv);
6515 i &= bits_eldv;
6516
6517 if (!eld[0])
6518 return !i;
6519
6520 if (!i)
6521 return false;
6522
6523 i = I915_READ(reg_elda);
6524 i &= ~bits_elda;
6525 I915_WRITE(reg_elda, i);
6526
6527 for (i = 0; i < eld[2]; i++)
6528 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6529 return false;
6530
6531 return true;
6532}
6533
e0dac65e
WF		 6534static void g4x_write_eld(struct drm_connector *connector,
6535 struct drm_crtc *crtc)
6536{
6537 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6538 uint8_t *eld = connector->eld;
6539 uint32_t eldv;
6540 uint32_t len;
6541 uint32_t i;
6542
6543 i = I915_READ(G4X_AUD_VID_DID);
6544
6545 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6546 eldv = G4X_ELDV_DEVCL_DEVBLC;
6547 else
6548 eldv = G4X_ELDV_DEVCTG;
6549
3a9627f4
WF		 6550 if (intel_eld_uptodate(connector,
6551 G4X_AUD_CNTL_ST, eldv,
6552 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6553 G4X_HDMIW_HDMIEDID))
6554 return;
6555
e0dac65e
WF		 6556 i = I915_READ(G4X_AUD_CNTL_ST);
6557 i &= ~(eldv | G4X_ELD_ADDR);
6558 len = (i >> 9) & 0x1f; /* ELD buffer size */
6559 I915_WRITE(G4X_AUD_CNTL_ST, i);
6560
6561 if (!eld[0])
6562 return;
6563
6564 len = min_t(uint8_t, eld[2], len);
6565 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6566 for (i = 0; i < len; i++)
6567 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6568
6569 i = I915_READ(G4X_AUD_CNTL_ST);
6570 i |= eldv;
6571 I915_WRITE(G4X_AUD_CNTL_ST, i);
6572}
6573
83358c85
WX		 6574static void haswell_write_eld(struct drm_connector *connector,
6575 struct drm_crtc *crtc)
6576{
6577 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6578 uint8_t *eld = connector->eld;
6579 struct drm_device *dev = crtc->dev;
7b9f35a6 6580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6581 uint32_t eldv;
6582 uint32_t i;
6583 int len;
6584 int pipe = to_intel_crtc(crtc)->pipe;
6585 int tmp;
6586
6587 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6588 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6589 int aud_config = HSW_AUD_CFG(pipe);
6590 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6591
6592
6593 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6594
6595 /* Audio output enable */
6596 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6597 tmp = I915_READ(aud_cntrl_st2);
6598 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6599 I915_WRITE(aud_cntrl_st2, tmp);
6600
6601 /* Wait for 1 vertical blank */
6602 intel_wait_for_vblank(dev, pipe);
6603
6604 /* Set ELD valid state */
6605 tmp = I915_READ(aud_cntrl_st2);
6606 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6607 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6608 I915_WRITE(aud_cntrl_st2, tmp);
6609 tmp = I915_READ(aud_cntrl_st2);
6610 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6611
6612 /* Enable HDMI mode */
6613 tmp = I915_READ(aud_config);
6614 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6615 /* clear N_programing_enable and N_value_index */
6616 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6617 I915_WRITE(aud_config, tmp);
6618
6619 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6620
6621 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6622 intel_crtc->eld_vld = true;
83358c85
WX		 6623
6624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6625 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6626 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6627 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6628 } else
6629 I915_WRITE(aud_config, 0);
6630
6631 if (intel_eld_uptodate(connector,
6632 aud_cntrl_st2, eldv,
6633 aud_cntl_st, IBX_ELD_ADDRESS,
6634 hdmiw_hdmiedid))
6635 return;
6636
6637 i = I915_READ(aud_cntrl_st2);
6638 i &= ~eldv;
6639 I915_WRITE(aud_cntrl_st2, i);
6640
6641 if (!eld[0])
6642 return;
6643
6644 i = I915_READ(aud_cntl_st);
6645 i &= ~IBX_ELD_ADDRESS;
6646 I915_WRITE(aud_cntl_st, i);
6647 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6648 DRM_DEBUG_DRIVER("port num:%d\n", i);
6649
6650 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6651 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6652 for (i = 0; i < len; i++)
6653 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6654
6655 i = I915_READ(aud_cntrl_st2);
6656 i |= eldv;
6657 I915_WRITE(aud_cntrl_st2, i);
6658
6659}
6660
e0dac65e
WF		 6661static void ironlake_write_eld(struct drm_connector *connector,
6662 struct drm_crtc *crtc)
6663{
6664 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6665 uint8_t *eld = connector->eld;
6666 uint32_t eldv;
6667 uint32_t i;
6668 int len;
6669 int hdmiw_hdmiedid;
b6daa025 6670 int aud_config;
e0dac65e
WF		 6671 int aud_cntl_st;
6672 int aud_cntrl_st2;
9b138a83 6673 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6674
b3f33cbf 6675 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6676 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6677 aud_config = IBX_AUD_CFG(pipe);
6678 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6679 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6680 } else {
9b138a83
WX		 6681 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6682 aud_config = CPT_AUD_CFG(pipe);
6683 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6684 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6685 }
6686
9b138a83 6687 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6688
6689 i = I915_READ(aud_cntl_st);
9b138a83 6690 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6691 if (!i) {
6692 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6693 /* operate blindly on all ports */
1202b4c6
WF		 6694 eldv = IBX_ELD_VALIDB;
6695 eldv |= IBX_ELD_VALIDB << 4;
6696 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6697 } else {
2582a850 6698 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6699 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6700 }
6701
3a9627f4
WF		 6702 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6703 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6704 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6705 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6706 } else
6707 I915_WRITE(aud_config, 0);
e0dac65e 6708
3a9627f4
WF		 6709 if (intel_eld_uptodate(connector,
6710 aud_cntrl_st2, eldv,
6711 aud_cntl_st, IBX_ELD_ADDRESS,
6712 hdmiw_hdmiedid))
6713 return;
6714
e0dac65e
WF		 6715 i = I915_READ(aud_cntrl_st2);
6716 i &= ~eldv;
6717 I915_WRITE(aud_cntrl_st2, i);
6718
6719 if (!eld[0])
6720 return;
6721
e0dac65e 6722 i = I915_READ(aud_cntl_st);
1202b4c6 6723 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6724 I915_WRITE(aud_cntl_st, i);
6725
6726 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6727 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6728 for (i = 0; i < len; i++)
6729 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6730
6731 i = I915_READ(aud_cntrl_st2);
6732 i |= eldv;
6733 I915_WRITE(aud_cntrl_st2, i);
6734}
6735
6736void intel_write_eld(struct drm_encoder *encoder,
6737 struct drm_display_mode *mode)
6738{
6739 struct drm_crtc *crtc = encoder->crtc;
6740 struct drm_connector *connector;
6741 struct drm_device *dev = encoder->dev;
6742 struct drm_i915_private *dev_priv = dev->dev_private;
6743
6744 connector = drm_select_eld(encoder, mode);
6745 if (!connector)
6746 return;
6747
6748 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6749 connector->base.id,
6750 drm_get_connector_name(connector),
6751 connector->encoder->base.id,
6752 drm_get_encoder_name(connector->encoder));
6753
6754 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6755
6756 if (dev_priv->display.write_eld)
6757 dev_priv->display.write_eld(connector, crtc);
6758}
6759
79e53945
JB		 6760/** Loads the palette/gamma unit for the CRTC with the prepared values */
6761void intel_crtc_load_lut(struct drm_crtc *crtc)
6762{
6763 struct drm_device *dev = crtc->dev;
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6766 enum pipe pipe = intel_crtc->pipe;
6767 int palreg = PALETTE(pipe);
79e53945 6768 int i;
42db64ef 6769 bool reenable_ips = false;
79e53945
JB		 6770
6771 /* The clocks have to be on to load the palette. */
aed3f09d 6772 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6773 return;
6774
23538ef1
JN		 6775 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6776 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6777 assert_dsi_pll_enabled(dev_priv);
6778 else
6779 assert_pll_enabled(dev_priv, pipe);
6780 }
14420bd0 6781
f2b115e6 6782 /* use legacy palette for Ironlake */
bad720ff 6783 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6784 palreg = LGC_PALETTE(pipe);
6785
6786 /* Workaround : Do not read or write the pipe palette/gamma data while
6787 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6788 */
6789 if (intel_crtc->config.ips_enabled &&
6790 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6791 GAMMA_MODE_MODE_SPLIT)) {
6792 hsw_disable_ips(intel_crtc);
6793 reenable_ips = true;
6794 }
2c07245f 6795
79e53945
JB		 6796 for (i = 0; i < 256; i++) {
6797 I915_WRITE(palreg + 4 * i,
6798 (intel_crtc->lut_r[i] << 16) |
6799 (intel_crtc->lut_g[i] << 8) |
6800 intel_crtc->lut_b[i]);
6801 }
42db64ef
PZ		 6802
6803 if (reenable_ips)
6804 hsw_enable_ips(intel_crtc);
79e53945
JB		 6805}
6806
560b85bb
CW		 6807static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6808{
6809 struct drm_device *dev = crtc->dev;
6810 struct drm_i915_private *dev_priv = dev->dev_private;
6811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6812 bool visible = base != 0;
6813 u32 cntl;
6814
6815 if (intel_crtc->cursor_visible == visible)
6816 return;
6817
9db4a9c7 6818 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6819 if (visible) {
6820 /* On these chipsets we can only modify the base whilst
6821 * the cursor is disabled.
6822 */
9db4a9c7 6823 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6824
6825 cntl &= ~(CURSOR_FORMAT_MASK);
6826 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6827 cntl |= CURSOR_ENABLE |
6828 CURSOR_GAMMA_ENABLE |
6829 CURSOR_FORMAT_ARGB;
6830 } else
6831 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6832 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6833
6834 intel_crtc->cursor_visible = visible;
6835}
6836
6837static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6838{
6839 struct drm_device *dev = crtc->dev;
6840 struct drm_i915_private *dev_priv = dev->dev_private;
6841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6842 int pipe = intel_crtc->pipe;
6843 bool visible = base != 0;
6844
6845 if (intel_crtc->cursor_visible != visible) {
548f245b 6846 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6847 if (base) {
6848 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6849 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6850 cntl |= pipe << 28; /* Connect to correct pipe */
6851 } else {
6852 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6853 cntl |= CURSOR_MODE_DISABLE;
6854 }
9db4a9c7 6855 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6856
6857 intel_crtc->cursor_visible = visible;
6858 }
6859 /* and commit changes on next vblank */
9db4a9c7 6860 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6861}
6862
65a21cd6
JB		 6863static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6864{
6865 struct drm_device *dev = crtc->dev;
6866 struct drm_i915_private *dev_priv = dev->dev_private;
6867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6868 int pipe = intel_crtc->pipe;
6869 bool visible = base != 0;
6870
6871 if (intel_crtc->cursor_visible != visible) {
6872 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6873 if (base) {
6874 cntl &= ~CURSOR_MODE;
6875 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6876 } else {
6877 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6878 cntl |= CURSOR_MODE_DISABLE;
6879 }
1f5d76db 6880 if (IS_HASWELL(dev)) {
86d3efce 6881 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6882 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6883 }
65a21cd6
JB		 6884 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6885
6886 intel_crtc->cursor_visible = visible;
6887 }
6888 /* and commit changes on next vblank */
6889 I915_WRITE(CURBASE_IVB(pipe), base);
6890}
6891
cda4b7d3 6892/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6893static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6894 bool on)
cda4b7d3
CW		 6895{
6896 struct drm_device *dev = crtc->dev;
6897 struct drm_i915_private *dev_priv = dev->dev_private;
6898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6899 int pipe = intel_crtc->pipe;
6900 int x = intel_crtc->cursor_x;
6901 int y = intel_crtc->cursor_y;
d6e4db15 6902 u32 base = 0, pos = 0;
cda4b7d3
CW		 6903 bool visible;
6904
d6e4db15 6905 if (on)
cda4b7d3 6906 base = intel_crtc->cursor_addr;
cda4b7d3 6907
d6e4db15
VS		 6908 if (x >= intel_crtc->config.pipe_src_w)
6909 base = 0;
6910
6911 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 6912 base = 0;
6913
6914 if (x < 0) {
efc9064e 6915 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 6916 base = 0;
6917
6918 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6919 x = -x;
6920 }
6921 pos |= x << CURSOR_X_SHIFT;
6922
6923 if (y < 0) {
efc9064e 6924 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 6925 base = 0;
6926
6927 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6928 y = -y;
6929 }
6930 pos |= y << CURSOR_Y_SHIFT;
6931
6932 visible = base != 0;
560b85bb 6933 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6934 return;
6935
0cd83aa9 6936 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6937 I915_WRITE(CURPOS_IVB(pipe), pos);
6938 ivb_update_cursor(crtc, base);
6939 } else {
6940 I915_WRITE(CURPOS(pipe), pos);
6941 if (IS_845G(dev) || IS_I865G(dev))
6942 i845_update_cursor(crtc, base);
6943 else
6944 i9xx_update_cursor(crtc, base);
6945 }
cda4b7d3
CW		 6946}
6947
79e53945 6948static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6949 struct drm_file *file,
79e53945
JB		 6950 uint32_t handle,
6951 uint32_t width, uint32_t height)
6952{
6953 struct drm_device *dev = crtc->dev;
6954 struct drm_i915_private *dev_priv = dev->dev_private;
6955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6956 struct drm_i915_gem_object *obj;
cda4b7d3 6957 uint32_t addr;
3f8bc370 6958 int ret;
79e53945 6959
79e53945
JB		 6960 /* if we want to turn off the cursor ignore width and height */
6961 if (!handle) {
28c97730 6962 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6963 addr = 0;
05394f39 6964 obj = NULL;
5004417d 6965 mutex_lock(&dev->struct_mutex);
3f8bc370 6966 goto finish;
79e53945
JB		 6967 }
6968
6969 /* Currently we only support 64x64 cursors */
6970 if (width != 64 || height != 64) {
6971 DRM_ERROR("we currently only support 64x64 cursors\n");
6972 return -EINVAL;
6973 }
6974
05394f39 6975 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6976 if (&obj->base == NULL)
79e53945
JB		 6977 return -ENOENT;
6978
05394f39 6979 if (obj->base.size < width * height * 4) {
79e53945 6980 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6981 ret = -ENOMEM;
6982 goto fail;
79e53945
JB		 6983 }
6984
71acb5eb 6985 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6986 mutex_lock(&dev->struct_mutex);
b295d1b6 6987 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6988 unsigned alignment;
6989
d9e86c0e
CW		 6990 if (obj->tiling_mode) {
6991 DRM_ERROR("cursor cannot be tiled\n");
6992 ret = -EINVAL;
6993 goto fail_locked;
6994 }
6995
693db184
CW		 6996 /* Note that the w/a also requires 2 PTE of padding following
6997 * the bo. We currently fill all unused PTE with the shadow
6998 * page and so we should always have valid PTE following the
6999 * cursor preventing the VT-d warning.
7000 */
7001 alignment = 0;
7002 if (need_vtd_wa(dev))
7003 alignment = 64*1024;
7004
7005 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7006 if (ret) {
7007 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7008 goto fail_locked;
e7b526bb
CW		 7009 }
7010
d9e86c0e
CW		 7011 ret = i915_gem_object_put_fence(obj);
7012 if (ret) {
2da3b9b9 7013 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7014 goto fail_unpin;
7015 }
7016
f343c5f6 7017 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7018 } else {
6eeefaf3 7019 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7020 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7021 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7022 align);
71acb5eb
DA		 7023 if (ret) {
7024 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7025 goto fail_locked;
71acb5eb 7026 }
05394f39 7027 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7028 }
7029
a6c45cf0 7030 if (IS_GEN2(dev))
14b60391
JB		 7031 I915_WRITE(CURSIZE, (height << 12) | width);
7032
3f8bc370 7033 finish:
3f8bc370 7034 if (intel_crtc->cursor_bo) {
b295d1b6 7035 if (dev_priv->info->cursor_needs_physical) {
05394f39 7036 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7037 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7038 } else
cc98b413 7039 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7040 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7041 }
80824003 7042
7f9872e0 7043 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7044
7045 intel_crtc->cursor_addr = addr;
05394f39 7046 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7047 intel_crtc->cursor_width = width;
7048 intel_crtc->cursor_height = height;
7049
40ccc72b 7050 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7051
79e53945 7052 return 0;
e7b526bb 7053fail_unpin:
cc98b413 7054 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7055fail_locked:
34b8686e 7056 mutex_unlock(&dev->struct_mutex);
bc9025bd 7057fail:
05394f39 7058 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7059 return ret;
79e53945
JB		 7060}
7061
7062static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7063{
79e53945 7064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7065
cda4b7d3
CW		 7066 intel_crtc->cursor_x = x;
7067 intel_crtc->cursor_y = y;
652c393a 7068
40ccc72b 7069 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7070
7071 return 0;
7072}
7073
7074/** Sets the color ramps on behalf of RandR */
7075void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7076 u16 blue, int regno)
7077{
7078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079
7080 intel_crtc->lut_r[regno] = red >> 8;
7081 intel_crtc->lut_g[regno] = green >> 8;
7082 intel_crtc->lut_b[regno] = blue >> 8;
7083}
7084
b8c00ac5
DA		 7085void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7086 u16 *blue, int regno)
7087{
7088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7089
7090 *red = intel_crtc->lut_r[regno] << 8;
7091 *green = intel_crtc->lut_g[regno] << 8;
7092 *blue = intel_crtc->lut_b[regno] << 8;
7093}
7094
79e53945 7095static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7096 u16 *blue, uint32_t start, uint32_t size)
79e53945 7097{
7203425a 7098 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7100
7203425a 7101 for (i = start; i < end; i++) {
79e53945
JB		 7102 intel_crtc->lut_r[i] = red[i] >> 8;
7103 intel_crtc->lut_g[i] = green[i] >> 8;
7104 intel_crtc->lut_b[i] = blue[i] >> 8;
7105 }
7106
7107 intel_crtc_load_lut(crtc);
7108}
7109
79e53945
JB		 7110/* VESA 640x480x72Hz mode to set on the pipe */
7111static struct drm_display_mode load_detect_mode = {
7112 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7113 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7114};
7115
d2dff872
CW		 7116static struct drm_framebuffer *
7117intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7118 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7119 struct drm_i915_gem_object *obj)
7120{
7121 struct intel_framebuffer *intel_fb;
7122 int ret;
7123
7124 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7125 if (!intel_fb) {
7126 drm_gem_object_unreference_unlocked(&obj->base);
7127 return ERR_PTR(-ENOMEM);
7128 }
7129
7130 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7131 if (ret) {
7132 drm_gem_object_unreference_unlocked(&obj->base);
7133 kfree(intel_fb);
7134 return ERR_PTR(ret);
7135 }
7136
7137 return &intel_fb->base;
7138}
7139
7140static u32
7141intel_framebuffer_pitch_for_width(int width, int bpp)
7142{
7143 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7144 return ALIGN(pitch, 64);
7145}
7146
7147static u32
7148intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7149{
7150 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7151 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7152}
7153
7154static struct drm_framebuffer *
7155intel_framebuffer_create_for_mode(struct drm_device *dev,
7156 struct drm_display_mode *mode,
7157 int depth, int bpp)
7158{
7159 struct drm_i915_gem_object *obj;
0fed39bd 7160 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7161
7162 obj = i915_gem_alloc_object(dev,
7163 intel_framebuffer_size_for_mode(mode, bpp));
7164 if (obj == NULL)
7165 return ERR_PTR(-ENOMEM);
7166
7167 mode_cmd.width = mode->hdisplay;
7168 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7169 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7170 bpp);
5ca0c34a 7171 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7172
7173 return intel_framebuffer_create(dev, &mode_cmd, obj);
7174}
7175
7176static struct drm_framebuffer *
7177mode_fits_in_fbdev(struct drm_device *dev,
7178 struct drm_display_mode *mode)
7179{
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181 struct drm_i915_gem_object *obj;
7182 struct drm_framebuffer *fb;
7183
7184 if (dev_priv->fbdev == NULL)
7185 return NULL;
7186
7187 obj = dev_priv->fbdev->ifb.obj;
7188 if (obj == NULL)
7189 return NULL;
7190
7191 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7192 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7193 fb->bits_per_pixel))
d2dff872
CW		 7194 return NULL;
7195
01f2c773 7196 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7197 return NULL;
7198
7199 return fb;
7200}
7201
d2434ab7 7202bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7203 struct drm_display_mode *mode,
8261b191 7204 struct intel_load_detect_pipe *old)
79e53945
JB		 7205{
7206 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7207 struct intel_encoder *intel_encoder =
7208 intel_attached_encoder(connector);
79e53945 7209 struct drm_crtc *possible_crtc;
4ef69c7a 7210 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7211 struct drm_crtc *crtc = NULL;
7212 struct drm_device *dev = encoder->dev;
94352cf9 7213 struct drm_framebuffer *fb;
79e53945
JB		 7214 int i = -1;
7215
d2dff872
CW		 7216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7217 connector->base.id, drm_get_connector_name(connector),
7218 encoder->base.id, drm_get_encoder_name(encoder));
7219
79e53945
JB		 7220 /*
7221 * Algorithm gets a little messy:
7a5e4805 7222 *
79e53945
JB		 7223 * - if the connector already has an assigned crtc, use it (but make
7224 * sure it's on first)
7a5e4805 7225 *
79e53945
JB		 7226 * - try to find the first unused crtc that can drive this connector,
7227 * and use that if we find one
79e53945
JB		 7228 */
7229
7230 /* See if we already have a CRTC for this connector */
7231 if (encoder->crtc) {
7232 crtc = encoder->crtc;
8261b191 7233
7b24056b
DV		 7234 mutex_lock(&crtc->mutex);
7235
24218aac 7236 old->dpms_mode = connector->dpms;
8261b191
CW		 7237 old->load_detect_temp = false;
7238
7239 /* Make sure the crtc and connector are running */
24218aac
DV		 7240 if (connector->dpms != DRM_MODE_DPMS_ON)
7241 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7242
7173188d 7243 return true;
79e53945
JB		 7244 }
7245
7246 /* Find an unused one (if possible) */
7247 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7248 i++;
7249 if (!(encoder->possible_crtcs & (1 << i)))
7250 continue;
7251 if (!possible_crtc->enabled) {
7252 crtc = possible_crtc;
7253 break;
7254 }
79e53945
JB		 7255 }
7256
7257 /*
7258 * If we didn't find an unused CRTC, don't use any.
7259 */
7260 if (!crtc) {
7173188d
CW		 7261 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7262 return false;
79e53945
JB		 7263 }
7264
7b24056b 7265 mutex_lock(&crtc->mutex);
fc303101
DV		 7266 intel_encoder->new_crtc = to_intel_crtc(crtc);
7267 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7268
7269 intel_crtc = to_intel_crtc(crtc);
24218aac 7270 old->dpms_mode = connector->dpms;
8261b191 7271 old->load_detect_temp = true;
d2dff872 7272 old->release_fb = NULL;
79e53945 7273
6492711d
CW		 7274 if (!mode)
7275 mode = &load_detect_mode;
79e53945 7276
d2dff872
CW		 7277 /* We need a framebuffer large enough to accommodate all accesses
7278 * that the plane may generate whilst we perform load detection.
7279 * We can not rely on the fbcon either being present (we get called
7280 * during its initialisation to detect all boot displays, or it may
7281 * not even exist) or that it is large enough to satisfy the
7282 * requested mode.
7283 */
94352cf9
DV		 7284 fb = mode_fits_in_fbdev(dev, mode);
7285 if (fb == NULL) {
d2dff872 7286 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7287 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7288 old->release_fb = fb;
d2dff872
CW		 7289 } else
7290 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7291 if (IS_ERR(fb)) {
d2dff872 7292 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7293 mutex_unlock(&crtc->mutex);
0e8b3d3e 7294 return false;
79e53945 7295 }
79e53945 7296
c0c36b94 7297 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7298 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7299 if (old->release_fb)
7300 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7301 mutex_unlock(&crtc->mutex);
0e8b3d3e 7302 return false;
79e53945 7303 }
7173188d 7304
79e53945 7305 /* let the connector get through one full cycle before testing */
9d0498a2 7306 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7307 return true;
79e53945
JB		 7308}
7309
d2434ab7 7310void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7311 struct intel_load_detect_pipe *old)
79e53945 7312{
d2434ab7
DV		 7313 struct intel_encoder *intel_encoder =
7314 intel_attached_encoder(connector);
4ef69c7a 7315 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7316 struct drm_crtc *crtc = encoder->crtc;
79e53945 7317
d2dff872
CW		 7318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7319 connector->base.id, drm_get_connector_name(connector),
7320 encoder->base.id, drm_get_encoder_name(encoder));
7321
8261b191 7322 if (old->load_detect_temp) {
fc303101
DV		 7323 to_intel_connector(connector)->new_encoder = NULL;
7324 intel_encoder->new_crtc = NULL;
7325 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7326
36206361
DV		 7327 if (old->release_fb) {
7328 drm_framebuffer_unregister_private(old->release_fb);
7329 drm_framebuffer_unreference(old->release_fb);
7330 }
d2dff872 7331
67c96400 7332 mutex_unlock(&crtc->mutex);
0622a53c 7333 return;
79e53945
JB		 7334 }
7335
c751ce4f 7336 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7337 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7338 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7339
7340 mutex_unlock(&crtc->mutex);
79e53945
JB		 7341}
7342
da4a1efa
VS		 7343static int i9xx_pll_refclk(struct drm_device *dev,
7344 const struct intel_crtc_config *pipe_config)
7345{
7346 struct drm_i915_private *dev_priv = dev->dev_private;
7347 u32 dpll = pipe_config->dpll_hw_state.dpll;
7348
7349 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7350 return dev_priv->vbt.lvds_ssc_freq * 1000;
7351 else if (HAS_PCH_SPLIT(dev))
7352 return 120000;
7353 else if (!IS_GEN2(dev))
7354 return 96000;
7355 else
7356 return 48000;
7357}
7358
79e53945 7359/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7360static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7361 struct intel_crtc_config *pipe_config)
79e53945 7362{
f1f644dc 7363 struct drm_device *dev = crtc->base.dev;
79e53945 7364 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7365 int pipe = pipe_config->cpu_transcoder;
293623f7 7366 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7367 u32 fp;
7368 intel_clock_t clock;
da4a1efa 7369 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7370
7371 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7372 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7373 else
293623f7 7374 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7375
7376 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7377 if (IS_PINEVIEW(dev)) {
7378 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7379 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7380 } else {
7381 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7382 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7383 }
7384
a6c45cf0 7385 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7386 if (IS_PINEVIEW(dev))
7387 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7388 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7389 else
7390 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7391 DPLL_FPA01_P1_POST_DIV_SHIFT);
7392
7393 switch (dpll & DPLL_MODE_MASK) {
7394 case DPLLB_MODE_DAC_SERIAL:
7395 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7396 5 : 10;
7397 break;
7398 case DPLLB_MODE_LVDS:
7399 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7400 7 : 14;
7401 break;
7402 default:
28c97730 7403 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7404 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7405 return;
79e53945
JB		 7406 }
7407
ac58c3f0 7408 if (IS_PINEVIEW(dev))
da4a1efa 7409 pineview_clock(refclk, &clock);
ac58c3f0 7410 else
da4a1efa 7411 i9xx_clock(refclk, &clock);
79e53945
JB		 7412 } else {
7413 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7414
7415 if (is_lvds) {
7416 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7417 DPLL_FPA01_P1_POST_DIV_SHIFT);
7418 clock.p2 = 14;
79e53945
JB		 7419 } else {
7420 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7421 clock.p1 = 2;
7422 else {
7423 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7424 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7425 }
7426 if (dpll & PLL_P2_DIVIDE_BY_4)
7427 clock.p2 = 4;
7428 else
7429 clock.p2 = 2;
79e53945 7430 }
da4a1efa
VS		 7431
7432 i9xx_clock(refclk, &clock);
79e53945
JB		 7433 }
7434
18442d08
VS		 7435 /*
7436 * This value includes pixel_multiplier. We will use
7437 * port_clock to compute adjusted_mode.clock in the
7438 * encoder's get_config() function.
7439 */
7440 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7441}
7442
6878da05
VS		 7443int intel_dotclock_calculate(int link_freq,
7444 const struct intel_link_m_n *m_n)
f1f644dc 7445{
f1f644dc
JB		 7446 /*
7447 * The calculation for the data clock is:
1041a02f 7448 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7449 * But we want to avoid losing precison if possible, so:
1041a02f 7450 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7451 *
7452 * and the link clock is simpler:
1041a02f 7453 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7454 */
7455
6878da05
VS		 7456 if (!m_n->link_n)
7457 return 0;
7458
7459 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7460}
7461
18442d08
VS		 7462static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7463 struct intel_crtc_config *pipe_config)
6878da05
VS		 7464{
7465 struct drm_device *dev = crtc->base.dev;
18442d08
VS		 7466
7467 /* read out port_clock from the DPLL */
7468 i9xx_crtc_clock_get(crtc, pipe_config);
6878da05 7469
f1f644dc 7470 /*
18442d08
VS		 7471 * This value does not include pixel_multiplier.
7472 * We will check that port_clock and adjusted_mode.clock
7473 * agree once we know their relationship in the encoder's
7474 * get_config() function.
79e53945 7475 */
18442d08
VS		 7476 pipe_config->adjusted_mode.clock =
7477 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7478 &pipe_config->fdi_m_n);
79e53945
JB		 7479}
7480
7481/** Returns the currently programmed mode of the given pipe. */
7482struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7483 struct drm_crtc *crtc)
7484{
548f245b 7485 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7487 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7488 struct drm_display_mode *mode;
f1f644dc 7489 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7490 int htot = I915_READ(HTOTAL(cpu_transcoder));
7491 int hsync = I915_READ(HSYNC(cpu_transcoder));
7492 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7493 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7494 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7495
7496 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7497 if (!mode)
7498 return NULL;
7499
f1f644dc
JB		 7500 /*
7501 * Construct a pipe_config sufficient for getting the clock info
7502 * back out of crtc_clock_get.
7503 *
7504 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7505 * to use a real value here instead.
7506 */
293623f7 7507 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7508 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7509 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7510 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7511 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7512 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7513
7514 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7515 mode->hdisplay = (htot & 0xffff) + 1;
7516 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7517 mode->hsync_start = (hsync & 0xffff) + 1;
7518 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7519 mode->vdisplay = (vtot & 0xffff) + 1;
7520 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7521 mode->vsync_start = (vsync & 0xffff) + 1;
7522 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7523
7524 drm_mode_set_name(mode);
79e53945
JB		 7525
7526 return mode;
7527}
7528
3dec0095 7529static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7530{
7531 struct drm_device *dev = crtc->dev;
7532 drm_i915_private_t *dev_priv = dev->dev_private;
7533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7534 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7535 int dpll_reg = DPLL(pipe);
7536 int dpll;
652c393a 7537
bad720ff 7538 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7539 return;
7540
7541 if (!dev_priv->lvds_downclock_avail)
7542 return;
7543
dbdc6479 7544 dpll = I915_READ(dpll_reg);
652c393a 7545 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7546 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7547
8ac5a6d5 7548 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7549
7550 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7551 I915_WRITE(dpll_reg, dpll);
9d0498a2 7552 intel_wait_for_vblank(dev, pipe);
dbdc6479 7553
652c393a
JB		 7554 dpll = I915_READ(dpll_reg);
7555 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7556 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7557 }
652c393a
JB		 7558}
7559
7560static void intel_decrease_pllclock(struct drm_crtc *crtc)
7561{
7562 struct drm_device *dev = crtc->dev;
7563 drm_i915_private_t *dev_priv = dev->dev_private;
7564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7565
bad720ff 7566 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7567 return;
7568
7569 if (!dev_priv->lvds_downclock_avail)
7570 return;
7571
7572 /*
7573 * Since this is called by a timer, we should never get here in
7574 * the manual case.
7575 */
7576 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7577 int pipe = intel_crtc->pipe;
7578 int dpll_reg = DPLL(pipe);
7579 int dpll;
f6e5b160 7580
44d98a61 7581 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7582
8ac5a6d5 7583 assert_panel_unlocked(dev_priv, pipe);
652c393a 7584
dc257cf1 7585 dpll = I915_READ(dpll_reg);
652c393a
JB		 7586 dpll |= DISPLAY_RATE_SELECT_FPA1;
7587 I915_WRITE(dpll_reg, dpll);
9d0498a2 7588 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7589 dpll = I915_READ(dpll_reg);
7590 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7591 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7592 }
7593
7594}
7595
f047e395
CW		 7596void intel_mark_busy(struct drm_device *dev)
7597{
c67a470b
PZ		 7598 struct drm_i915_private *dev_priv = dev->dev_private;
7599
7600 hsw_package_c8_gpu_busy(dev_priv);
7601 i915_update_gfx_val(dev_priv);
f047e395
CW		 7602}
7603
7604void intel_mark_idle(struct drm_device *dev)
652c393a 7605{
c67a470b 7606 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7607 struct drm_crtc *crtc;
652c393a 7608
c67a470b
PZ		 7609 hsw_package_c8_gpu_idle(dev_priv);
7610
652c393a
JB		 7611 if (!i915_powersave)
7612 return;
7613
652c393a 7614 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7615 if (!crtc->fb)
7616 continue;
7617
725a5b54 7618 intel_decrease_pllclock(crtc);
652c393a 7619 }
652c393a
JB		 7620}
7621
c65355bb
CW		 7622void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7623 struct intel_ring_buffer *ring)
652c393a 7624{
f047e395
CW		 7625 struct drm_device *dev = obj->base.dev;
7626 struct drm_crtc *crtc;
652c393a 7627
f047e395 7628 if (!i915_powersave)
acb87dfb
CW		 7629 return;
7630
652c393a
JB		 7631 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7632 if (!crtc->fb)
7633 continue;
7634
c65355bb
CW		 7635 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7636 continue;
7637
7638 intel_increase_pllclock(crtc);
7639 if (ring && intel_fbc_enabled(dev))
7640 ring->fbc_dirty = true;
652c393a
JB		 7641 }
7642}
7643
79e53945
JB		 7644static void intel_crtc_destroy(struct drm_crtc *crtc)
7645{
7646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7647 struct drm_device *dev = crtc->dev;
7648 struct intel_unpin_work *work;
7649 unsigned long flags;
7650
7651 spin_lock_irqsave(&dev->event_lock, flags);
7652 work = intel_crtc->unpin_work;
7653 intel_crtc->unpin_work = NULL;
7654 spin_unlock_irqrestore(&dev->event_lock, flags);
7655
7656 if (work) {
7657 cancel_work_sync(&work->work);
7658 kfree(work);
7659 }
79e53945 7660
40ccc72b
MK		 7661 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7662
79e53945 7663 drm_crtc_cleanup(crtc);
67e77c5a 7664
79e53945
JB		 7665 kfree(intel_crtc);
7666}
7667
6b95a207
KH		 7668static void intel_unpin_work_fn(struct work_struct *__work)
7669{
7670 struct intel_unpin_work *work =
7671 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7672 struct drm_device *dev = work->crtc->dev;
6b95a207 7673
b4a98e57 7674 mutex_lock(&dev->struct_mutex);
1690e1eb 7675 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7676 drm_gem_object_unreference(&work->pending_flip_obj->base);
7677 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7678
b4a98e57
CW		 7679 intel_update_fbc(dev);
7680 mutex_unlock(&dev->struct_mutex);
7681
7682 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7683 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7684
6b95a207
KH		 7685 kfree(work);
7686}
7687
1afe3e9d 7688static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7689 struct drm_crtc *crtc)
6b95a207
KH		 7690{
7691 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7693 struct intel_unpin_work *work;
6b95a207
KH		 7694 unsigned long flags;
7695
7696 /* Ignore early vblank irqs */
7697 if (intel_crtc == NULL)
7698 return;
7699
7700 spin_lock_irqsave(&dev->event_lock, flags);
7701 work = intel_crtc->unpin_work;
e7d841ca
CW		 7702
7703 /* Ensure we don't miss a work->pending update ... */
7704 smp_rmb();
7705
7706 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7707 spin_unlock_irqrestore(&dev->event_lock, flags);
7708 return;
7709 }
7710
e7d841ca
CW		 7711 /* and that the unpin work is consistent wrt ->pending. */
7712 smp_rmb();
7713
6b95a207 7714 intel_crtc->unpin_work = NULL;
6b95a207 7715
45a066eb
RC		 7716 if (work->event)
7717 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7718
0af7e4df
MK		 7719 drm_vblank_put(dev, intel_crtc->pipe);
7720
6b95a207
KH		 7721 spin_unlock_irqrestore(&dev->event_lock, flags);
7722
2c10d571 7723 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7724
7725 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7726
7727 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7728}
7729
1afe3e9d
JB		 7730void intel_finish_page_flip(struct drm_device *dev, int pipe)
7731{
7732 drm_i915_private_t *dev_priv = dev->dev_private;
7733 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7734
49b14a5c 7735 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7736}
7737
7738void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7739{
7740 drm_i915_private_t *dev_priv = dev->dev_private;
7741 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7742
49b14a5c 7743 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7744}
7745
6b95a207
KH		 7746void intel_prepare_page_flip(struct drm_device *dev, int plane)
7747{
7748 drm_i915_private_t *dev_priv = dev->dev_private;
7749 struct intel_crtc *intel_crtc =
7750 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7751 unsigned long flags;
7752
e7d841ca
CW		 7753 /* NB: An MMIO update of the plane base pointer will also
7754 * generate a page-flip completion irq, i.e. every modeset
7755 * is also accompanied by a spurious intel_prepare_page_flip().
7756 */
6b95a207 7757 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7758 if (intel_crtc->unpin_work)
7759 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7760 spin_unlock_irqrestore(&dev->event_lock, flags);
7761}
7762
e7d841ca
CW		 7763inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7764{
7765 /* Ensure that the work item is consistent when activating it ... */
7766 smp_wmb();
7767 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7768 /* and that it is marked active as soon as the irq could fire. */
7769 smp_wmb();
7770}
7771
8c9f3aaf
JB		 7772static int intel_gen2_queue_flip(struct drm_device *dev,
7773 struct drm_crtc *crtc,
7774 struct drm_framebuffer *fb,
ed8d1975
KP		 7775 struct drm_i915_gem_object *obj,
7776 uint32_t flags)
8c9f3aaf
JB		 7777{
7778 struct drm_i915_private *dev_priv = dev->dev_private;
7779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7780 u32 flip_mask;
6d90c952 7781 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7782 int ret;
7783
6d90c952 7784 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7785 if (ret)
83d4092b 7786 goto err;
8c9f3aaf 7787
6d90c952 7788 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7789 if (ret)
83d4092b 7790 goto err_unpin;
8c9f3aaf
JB		 7791
7792 /* Can't queue multiple flips, so wait for the previous
7793 * one to finish before executing the next.
7794 */
7795 if (intel_crtc->plane)
7796 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7797 else
7798 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7799 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7800 intel_ring_emit(ring, MI_NOOP);
7801 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7802 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7803 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7804 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7805 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7806
7807 intel_mark_page_flip_active(intel_crtc);
09246732 7808 __intel_ring_advance(ring);
83d4092b
CW		 7809 return 0;
7810
7811err_unpin:
7812 intel_unpin_fb_obj(obj);
7813err:
8c9f3aaf
JB		 7814 return ret;
7815}
7816
7817static int intel_gen3_queue_flip(struct drm_device *dev,
7818 struct drm_crtc *crtc,
7819 struct drm_framebuffer *fb,
ed8d1975
KP		 7820 struct drm_i915_gem_object *obj,
7821 uint32_t flags)
8c9f3aaf
JB		 7822{
7823 struct drm_i915_private *dev_priv = dev->dev_private;
7824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7825 u32 flip_mask;
6d90c952 7826 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7827 int ret;
7828
6d90c952 7829 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7830 if (ret)
83d4092b 7831 goto err;
8c9f3aaf 7832
6d90c952 7833 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7834 if (ret)
83d4092b 7835 goto err_unpin;
8c9f3aaf
JB		 7836
7837 if (intel_crtc->plane)
7838 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7839 else
7840 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7841 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7842 intel_ring_emit(ring, MI_NOOP);
7843 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7844 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7845 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7846 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7847 intel_ring_emit(ring, MI_NOOP);
7848
e7d841ca 7849 intel_mark_page_flip_active(intel_crtc);
09246732 7850 __intel_ring_advance(ring);
83d4092b
CW		 7851 return 0;
7852
7853err_unpin:
7854 intel_unpin_fb_obj(obj);
7855err:
8c9f3aaf
JB		 7856 return ret;
7857}
7858
7859static int intel_gen4_queue_flip(struct drm_device *dev,
7860 struct drm_crtc *crtc,
7861 struct drm_framebuffer *fb,
ed8d1975
KP		 7862 struct drm_i915_gem_object *obj,
7863 uint32_t flags)
8c9f3aaf
JB		 7864{
7865 struct drm_i915_private *dev_priv = dev->dev_private;
7866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7867 uint32_t pf, pipesrc;
6d90c952 7868 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7869 int ret;
7870
6d90c952 7871 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7872 if (ret)
83d4092b 7873 goto err;
8c9f3aaf 7874
6d90c952 7875 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7876 if (ret)
83d4092b 7877 goto err_unpin;
8c9f3aaf
JB		 7878
7879 /* i965+ uses the linear or tiled offsets from the
7880 * Display Registers (which do not change across a page-flip)
7881 * so we need only reprogram the base address.
7882 */
6d90c952
DV		 7883 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7884 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7885 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7886 intel_ring_emit(ring,
f343c5f6 7887 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7888 obj->tiling_mode);
8c9f3aaf
JB		 7889
7890 /* XXX Enabling the panel-fitter across page-flip is so far
7891 * untested on non-native modes, so ignore it for now.
7892 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7893 */
7894 pf = 0;
7895 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7896 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7897
7898 intel_mark_page_flip_active(intel_crtc);
09246732 7899 __intel_ring_advance(ring);
83d4092b
CW		 7900 return 0;
7901
7902err_unpin:
7903 intel_unpin_fb_obj(obj);
7904err:
8c9f3aaf
JB		 7905 return ret;
7906}
7907
7908static int intel_gen6_queue_flip(struct drm_device *dev,
7909 struct drm_crtc *crtc,
7910 struct drm_framebuffer *fb,
ed8d1975
KP		 7911 struct drm_i915_gem_object *obj,
7912 uint32_t flags)
8c9f3aaf
JB		 7913{
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7916 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7917 uint32_t pf, pipesrc;
7918 int ret;
7919
6d90c952 7920 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7921 if (ret)
83d4092b 7922 goto err;
8c9f3aaf 7923
6d90c952 7924 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7925 if (ret)
83d4092b 7926 goto err_unpin;
8c9f3aaf 7927
6d90c952
DV		 7928 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7929 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7930 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7931 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7932
dc257cf1
DV		 7933 /* Contrary to the suggestions in the documentation,
7934 * "Enable Panel Fitter" does not seem to be required when page
7935 * flipping with a non-native mode, and worse causes a normal
7936 * modeset to fail.
7937 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7938 */
7939 pf = 0;
8c9f3aaf 7940 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7941 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7942
7943 intel_mark_page_flip_active(intel_crtc);
09246732 7944 __intel_ring_advance(ring);
83d4092b
CW		 7945 return 0;
7946
7947err_unpin:
7948 intel_unpin_fb_obj(obj);
7949err:
8c9f3aaf
JB		 7950 return ret;
7951}
7952
7c9017e5
JB		 7953static int intel_gen7_queue_flip(struct drm_device *dev,
7954 struct drm_crtc *crtc,
7955 struct drm_framebuffer *fb,
ed8d1975
KP		 7956 struct drm_i915_gem_object *obj,
7957 uint32_t flags)
7c9017e5
JB		 7958{
7959 struct drm_i915_private *dev_priv = dev->dev_private;
7960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7961 struct intel_ring_buffer *ring;
cb05d8de 7962 uint32_t plane_bit = 0;
ffe74d75
CW		 7963 int len, ret;
7964
7965 ring = obj->ring;
7966 if (ring == NULL || ring->id != RCS)
7967 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7968
7969 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7970 if (ret)
83d4092b 7971 goto err;
7c9017e5 7972
cb05d8de
DV		 7973 switch(intel_crtc->plane) {
7974 case PLANE_A:
7975 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7976 break;
7977 case PLANE_B:
7978 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7979 break;
7980 case PLANE_C:
7981 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7982 break;
7983 default:
7984 WARN_ONCE(1, "unknown plane in flip command\n");
7985 ret = -ENODEV;
ab3951eb 7986 goto err_unpin;
cb05d8de
DV		 7987 }
7988
ffe74d75
CW		 7989 len = 4;
7990 if (ring->id == RCS)
7991 len += 6;
7992
7993 ret = intel_ring_begin(ring, len);
7c9017e5 7994 if (ret)
83d4092b 7995 goto err_unpin;
7c9017e5 7996
ffe74d75
CW		 7997 /* Unmask the flip-done completion message. Note that the bspec says that
7998 * we should do this for both the BCS and RCS, and that we must not unmask
7999 * more than one flip event at any time (or ensure that one flip message
8000 * can be sent by waiting for flip-done prior to queueing new flips).
8001 * Experimentation says that BCS works despite DERRMR masking all
8002 * flip-done completion events and that unmasking all planes at once
8003 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8004 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8005 */
8006 if (ring->id == RCS) {
8007 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8008 intel_ring_emit(ring, DERRMR);
8009 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8010 DERRMR_PIPEB_PRI_FLIP_DONE |
8011 DERRMR_PIPEC_PRI_FLIP_DONE));
8012 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8013 intel_ring_emit(ring, DERRMR);
8014 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8015 }
8016
cb05d8de 8017 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8018 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8019 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8020 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8021
8022 intel_mark_page_flip_active(intel_crtc);
09246732 8023 __intel_ring_advance(ring);
83d4092b
CW		 8024 return 0;
8025
8026err_unpin:
8027 intel_unpin_fb_obj(obj);
8028err:
7c9017e5
JB		 8029 return ret;
8030}
8031
8c9f3aaf
JB		 8032static int intel_default_queue_flip(struct drm_device *dev,
8033 struct drm_crtc *crtc,
8034 struct drm_framebuffer *fb,
ed8d1975
KP		 8035 struct drm_i915_gem_object *obj,
8036 uint32_t flags)
8c9f3aaf
JB		 8037{
8038 return -ENODEV;
8039}
8040
6b95a207
KH		 8041static int intel_crtc_page_flip(struct drm_crtc *crtc,
8042 struct drm_framebuffer *fb,
ed8d1975
KP		 8043 struct drm_pending_vblank_event *event,
8044 uint32_t page_flip_flags)
6b95a207
KH		 8045{
8046 struct drm_device *dev = crtc->dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8048 struct drm_framebuffer *old_fb = crtc->fb;
8049 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8051 struct intel_unpin_work *work;
8c9f3aaf 8052 unsigned long flags;
52e68630 8053 int ret;
6b95a207 8054
e6a595d2
VS		 8055 /* Can't change pixel format via MI display flips. */
8056 if (fb->pixel_format != crtc->fb->pixel_format)
8057 return -EINVAL;
8058
8059 /*
8060 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8061 * Note that pitch changes could also affect these register.
8062 */
8063 if (INTEL_INFO(dev)->gen > 3 &&
8064 (fb->offsets[0] != crtc->fb->offsets[0] ||
8065 fb->pitches[0] != crtc->fb->pitches[0]))
8066 return -EINVAL;
8067
6b95a207
KH		 8068 work = kzalloc(sizeof *work, GFP_KERNEL);
8069 if (work == NULL)
8070 return -ENOMEM;
8071
6b95a207 8072 work->event = event;
b4a98e57 8073 work->crtc = crtc;
4a35f83b 8074 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8075 INIT_WORK(&work->work, intel_unpin_work_fn);
8076
7317c75e
JB		 8077 ret = drm_vblank_get(dev, intel_crtc->pipe);
8078 if (ret)
8079 goto free_work;
8080
6b95a207
KH		 8081 /* We borrow the event spin lock for protecting unpin_work */
8082 spin_lock_irqsave(&dev->event_lock, flags);
8083 if (intel_crtc->unpin_work) {
8084 spin_unlock_irqrestore(&dev->event_lock, flags);
8085 kfree(work);
7317c75e 8086 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8087
8088 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8089 return -EBUSY;
8090 }
8091 intel_crtc->unpin_work = work;
8092 spin_unlock_irqrestore(&dev->event_lock, flags);
8093
b4a98e57
CW		 8094 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8095 flush_workqueue(dev_priv->wq);
8096
79158103
CW		 8097 ret = i915_mutex_lock_interruptible(dev);
8098 if (ret)
8099 goto cleanup;
6b95a207 8100
75dfca80 8101 /* Reference the objects for the scheduled work. */
05394f39
CW		 8102 drm_gem_object_reference(&work->old_fb_obj->base);
8103 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8104
8105 crtc->fb = fb;
96b099fd 8106
e1f99ce6 8107 work->pending_flip_obj = obj;
e1f99ce6 8108
4e5359cd
SF		 8109 work->enable_stall_check = true;
8110
b4a98e57 8111 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8112 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8113
ed8d1975 8114 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8115 if (ret)
8116 goto cleanup_pending;
6b95a207 8117
7782de3b 8118 intel_disable_fbc(dev);
c65355bb 8119 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8120 mutex_unlock(&dev->struct_mutex);
8121
e5510fac
JB		 8122 trace_i915_flip_request(intel_crtc->plane, obj);
8123
6b95a207 8124 return 0;
96b099fd 8125
8c9f3aaf 8126cleanup_pending:
b4a98e57 8127 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8128 crtc->fb = old_fb;
05394f39
CW		 8129 drm_gem_object_unreference(&work->old_fb_obj->base);
8130 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8131 mutex_unlock(&dev->struct_mutex);
8132
79158103 8133cleanup:
96b099fd
CW		 8134 spin_lock_irqsave(&dev->event_lock, flags);
8135 intel_crtc->unpin_work = NULL;
8136 spin_unlock_irqrestore(&dev->event_lock, flags);
8137
7317c75e
JB		 8138 drm_vblank_put(dev, intel_crtc->pipe);
8139free_work:
96b099fd
CW		 8140 kfree(work);
8141
8142 return ret;
6b95a207
KH		 8143}
8144
f6e5b160 8145static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8146 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8147 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8148};
8149
50f56119
DV		 8150static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8151 struct drm_crtc *crtc)
8152{
8153 struct drm_device *dev;
8154 struct drm_crtc *tmp;
8155 int crtc_mask = 1;
47f1c6c9 8156
50f56119 8157 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8158
50f56119 8159 dev = crtc->dev;
47f1c6c9 8160
50f56119
DV		 8161 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8162 if (tmp == crtc)
8163 break;
8164 crtc_mask <<= 1;
8165 }
47f1c6c9 8166
50f56119
DV		 8167 if (encoder->possible_crtcs & crtc_mask)
8168 return true;
8169 return false;
47f1c6c9 8170}
79e53945 8171
9a935856
DV		 8172/**
8173 * intel_modeset_update_staged_output_state
8174 *
8175 * Updates the staged output configuration state, e.g. after we've read out the
8176 * current hw state.
8177 */
8178static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8179{
9a935856
DV		 8180 struct intel_encoder *encoder;
8181 struct intel_connector *connector;
f6e5b160 8182
9a935856
DV		 8183 list_for_each_entry(connector, &dev->mode_config.connector_list,
8184 base.head) {
8185 connector->new_encoder =
8186 to_intel_encoder(connector->base.encoder);
8187 }
f6e5b160 8188
9a935856
DV		 8189 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8190 base.head) {
8191 encoder->new_crtc =
8192 to_intel_crtc(encoder->base.crtc);
8193 }
f6e5b160
CW		 8194}
8195
9a935856
DV		 8196/**
8197 * intel_modeset_commit_output_state
8198 *
8199 * This function copies the stage display pipe configuration to the real one.
8200 */
8201static void intel_modeset_commit_output_state(struct drm_device *dev)
8202{
8203 struct intel_encoder *encoder;
8204 struct intel_connector *connector;
f6e5b160 8205
9a935856
DV		 8206 list_for_each_entry(connector, &dev->mode_config.connector_list,
8207 base.head) {
8208 connector->base.encoder = &connector->new_encoder->base;
8209 }
f6e5b160 8210
9a935856
DV		 8211 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8212 base.head) {
8213 encoder->base.crtc = &encoder->new_crtc->base;
8214 }
8215}
8216
050f7aeb
DV		 8217static void
8218connected_sink_compute_bpp(struct intel_connector * connector,
8219 struct intel_crtc_config *pipe_config)
8220{
8221 int bpp = pipe_config->pipe_bpp;
8222
8223 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8224 connector->base.base.id,
8225 drm_get_connector_name(&connector->base));
8226
8227 /* Don't use an invalid EDID bpc value */
8228 if (connector->base.display_info.bpc &&
8229 connector->base.display_info.bpc * 3 < bpp) {
8230 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8231 bpp, connector->base.display_info.bpc*3);
8232 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8233 }
8234
8235 /* Clamp bpp to 8 on screens without EDID 1.4 */
8236 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8237 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8238 bpp);
8239 pipe_config->pipe_bpp = 24;
8240 }
8241}
8242
4e53c2e0 8243static int
050f7aeb
DV		 8244compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8245 struct drm_framebuffer *fb,
8246 struct intel_crtc_config *pipe_config)
4e53c2e0 8247{
050f7aeb
DV		 8248 struct drm_device *dev = crtc->base.dev;
8249 struct intel_connector *connector;
4e53c2e0
DV		 8250 int bpp;
8251
d42264b1
DV		 8252 switch (fb->pixel_format) {
8253 case DRM_FORMAT_C8:
4e53c2e0
DV		 8254 bpp = 8*3; /* since we go through a colormap */
8255 break;
d42264b1
DV		 8256 case DRM_FORMAT_XRGB1555:
8257 case DRM_FORMAT_ARGB1555:
8258 /* checked in intel_framebuffer_init already */
8259 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8260 return -EINVAL;
8261 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8262 bpp = 6*3; /* min is 18bpp */
8263 break;
d42264b1
DV		 8264 case DRM_FORMAT_XBGR8888:
8265 case DRM_FORMAT_ABGR8888:
8266 /* checked in intel_framebuffer_init already */
8267 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8268 return -EINVAL;
8269 case DRM_FORMAT_XRGB8888:
8270 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8271 bpp = 8*3;
8272 break;
d42264b1
DV		 8273 case DRM_FORMAT_XRGB2101010:
8274 case DRM_FORMAT_ARGB2101010:
8275 case DRM_FORMAT_XBGR2101010:
8276 case DRM_FORMAT_ABGR2101010:
8277 /* checked in intel_framebuffer_init already */
8278 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8279 return -EINVAL;
4e53c2e0
DV		 8280 bpp = 10*3;
8281 break;
baba133a 8282 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8283 default:
8284 DRM_DEBUG_KMS("unsupported depth\n");
8285 return -EINVAL;
8286 }
8287
4e53c2e0
DV		 8288 pipe_config->pipe_bpp = bpp;
8289
8290 /* Clamp display bpp to EDID value */
8291 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8292 base.head) {
1b829e05
DV		 8293 if (!connector->new_encoder ||
8294 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8295 continue;
8296
050f7aeb 8297 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8298 }
8299
8300 return bpp;
8301}
8302
c0b03411
DV		 8303static void intel_dump_pipe_config(struct intel_crtc *crtc,
8304 struct intel_crtc_config *pipe_config,
8305 const char *context)
8306{
8307 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8308 context, pipe_name(crtc->pipe));
8309
8310 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8311 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8312 pipe_config->pipe_bpp, pipe_config->dither);
8313 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8314 pipe_config->has_pch_encoder,
8315 pipe_config->fdi_lanes,
8316 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8317 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8318 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8319 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8320 pipe_config->has_dp_encoder,
8321 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8322 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8323 pipe_config->dp_m_n.tu);
c0b03411
DV		 8324 DRM_DEBUG_KMS("requested mode:\n");
8325 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8326 DRM_DEBUG_KMS("adjusted mode:\n");
8327 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
d71b8d4a 8328 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8329 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8330 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8331 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8332 pipe_config->gmch_pfit.control,
8333 pipe_config->gmch_pfit.pgm_ratios,
8334 pipe_config->gmch_pfit.lvds_border_bits);
8335 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8336 pipe_config->pch_pfit.pos,
8337 pipe_config->pch_pfit.size);
42db64ef 8338 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8339}
8340
accfc0c5
DV		 8341static bool check_encoder_cloning(struct drm_crtc *crtc)
8342{
8343 int num_encoders = 0;
8344 bool uncloneable_encoders = false;
8345 struct intel_encoder *encoder;
8346
8347 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8348 base.head) {
8349 if (&encoder->new_crtc->base != crtc)
8350 continue;
8351
8352 num_encoders++;
8353 if (!encoder->cloneable)
8354 uncloneable_encoders = true;
8355 }
8356
8357 return !(num_encoders > 1 && uncloneable_encoders);
8358}
8359
b8cecdf5
DV		 8360static struct intel_crtc_config *
8361intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8362 struct drm_framebuffer *fb,
b8cecdf5 8363 struct drm_display_mode *mode)
ee7b9f93 8364{
7758a113 8365 struct drm_device *dev = crtc->dev;
7758a113 8366 struct intel_encoder *encoder;
b8cecdf5 8367 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8368 int plane_bpp, ret = -EINVAL;
8369 bool retry = true;
ee7b9f93 8370
accfc0c5
DV		 8371 if (!check_encoder_cloning(crtc)) {
8372 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8373 return ERR_PTR(-EINVAL);
8374 }
8375
b8cecdf5
DV		 8376 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8377 if (!pipe_config)
7758a113
DV		 8378 return ERR_PTR(-ENOMEM);
8379
b8cecdf5
DV		 8380 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8381 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd
VS		 8382
8383 pipe_config->pipe_src_w = mode->hdisplay;
8384 pipe_config->pipe_src_h = mode->vdisplay;
8385
e143a21c
DV		 8386 pipe_config->cpu_transcoder =
8387 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8388 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8389
2960bc9c
ID		 8390 /*
8391 * Sanitize sync polarity flags based on requested ones. If neither
8392 * positive or negative polarity is requested, treat this as meaning
8393 * negative polarity.
8394 */
8395 if (!(pipe_config->adjusted_mode.flags &
8396 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8397 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8398
8399 if (!(pipe_config->adjusted_mode.flags &
8400 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8401 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8402
050f7aeb
DV		 8403 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8404 * plane pixel format and any sink constraints into account. Returns the
8405 * source plane bpp so that dithering can be selected on mismatches
8406 * after encoders and crtc also have had their say. */
8407 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8408 fb, pipe_config);
4e53c2e0
DV		 8409 if (plane_bpp < 0)
8410 goto fail;
8411
e29c22c0 8412encoder_retry:
ef1b460d 8413 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8414 pipe_config->port_clock = 0;
ef1b460d 8415 pipe_config->pixel_multiplier = 1;
ff9a6750 8416
135c81b8
DV		 8417 /* Fill in default crtc timings, allow encoders to overwrite them. */
8418 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8419
7758a113
DV		 8420 /* Pass our mode to the connectors and the CRTC to give them a chance to
8421 * adjust it according to limitations or connector properties, and also
8422 * a chance to reject the mode entirely.
47f1c6c9 8423 */
7758a113
DV		 8424 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8425 base.head) {
47f1c6c9 8426
7758a113
DV		 8427 if (&encoder->new_crtc->base != crtc)
8428 continue;
7ae89233 8429
efea6e8e
DV		 8430 if (!(encoder->compute_config(encoder, pipe_config))) {
8431 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8432 goto fail;
8433 }
ee7b9f93 8434 }
47f1c6c9 8435
ff9a6750
DV		 8436 /* Set default port clock if not overwritten by the encoder. Needs to be
8437 * done afterwards in case the encoder adjusts the mode. */
8438 if (!pipe_config->port_clock)
3c52f4eb
VS		 8439 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8440 pipe_config->pixel_multiplier;
ff9a6750 8441
a43f6e0f 8442 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8443 if (ret < 0) {
7758a113
DV		 8444 DRM_DEBUG_KMS("CRTC fixup failed\n");
8445 goto fail;
ee7b9f93 8446 }
e29c22c0
DV		 8447
8448 if (ret == RETRY) {
8449 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8450 ret = -EINVAL;
8451 goto fail;
8452 }
8453
8454 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8455 retry = false;
8456 goto encoder_retry;
8457 }
8458
4e53c2e0
DV		 8459 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8460 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8461 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8462
b8cecdf5 8463 return pipe_config;
7758a113 8464fail:
b8cecdf5 8465 kfree(pipe_config);
e29c22c0 8466 return ERR_PTR(ret);
ee7b9f93 8467}
47f1c6c9 8468
e2e1ed41
DV		 8469/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8470 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8471static void
8472intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8473 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8474{
8475 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8476 struct drm_device *dev = crtc->dev;
8477 struct intel_encoder *encoder;
8478 struct intel_connector *connector;
8479 struct drm_crtc *tmp_crtc;
79e53945 8480
e2e1ed41 8481 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8482
e2e1ed41
DV		 8483 /* Check which crtcs have changed outputs connected to them, these need
8484 * to be part of the prepare_pipes mask. We don't (yet) support global
8485 * modeset across multiple crtcs, so modeset_pipes will only have one
8486 * bit set at most. */
8487 list_for_each_entry(connector, &dev->mode_config.connector_list,
8488 base.head) {
8489 if (connector->base.encoder == &connector->new_encoder->base)
8490 continue;
79e53945 8491
e2e1ed41
DV		 8492 if (connector->base.encoder) {
8493 tmp_crtc = connector->base.encoder->crtc;
8494
8495 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8496 }
8497
8498 if (connector->new_encoder)
8499 *prepare_pipes |=
8500 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8501 }
8502
e2e1ed41
DV		 8503 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8504 base.head) {
8505 if (encoder->base.crtc == &encoder->new_crtc->base)
8506 continue;
8507
8508 if (encoder->base.crtc) {
8509 tmp_crtc = encoder->base.crtc;
8510
8511 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8512 }
8513
8514 if (encoder->new_crtc)
8515 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8516 }
8517
e2e1ed41
DV		 8518 /* Check for any pipes that will be fully disabled ... */
8519 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8520 base.head) {
8521 bool used = false;
22fd0fab 8522
e2e1ed41
DV		 8523 /* Don't try to disable disabled crtcs. */
8524 if (!intel_crtc->base.enabled)
8525 continue;
7e7d76c3 8526
e2e1ed41
DV		 8527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8528 base.head) {
8529 if (encoder->new_crtc == intel_crtc)
8530 used = true;
8531 }
8532
8533 if (!used)
8534 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8535 }
8536
e2e1ed41
DV		 8537
8538 /* set_mode is also used to update properties on life display pipes. */
8539 intel_crtc = to_intel_crtc(crtc);
8540 if (crtc->enabled)
8541 *prepare_pipes |= 1 << intel_crtc->pipe;
8542
b6c5164d
DV		 8543 /*
8544 * For simplicity do a full modeset on any pipe where the output routing
8545 * changed. We could be more clever, but that would require us to be
8546 * more careful with calling the relevant encoder->mode_set functions.
8547 */
e2e1ed41
DV		 8548 if (*prepare_pipes)
8549 *modeset_pipes = *prepare_pipes;
8550
8551 /* ... and mask these out. */
8552 *modeset_pipes &= ~(*disable_pipes);
8553 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8554
8555 /*
8556 * HACK: We don't (yet) fully support global modesets. intel_set_config
8557 * obies this rule, but the modeset restore mode of
8558 * intel_modeset_setup_hw_state does not.
8559 */
8560 *modeset_pipes &= 1 << intel_crtc->pipe;
8561 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8562
8563 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8564 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8565}
79e53945 8566
ea9d758d 8567static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8568{
ea9d758d 8569 struct drm_encoder *encoder;
f6e5b160 8570 struct drm_device *dev = crtc->dev;
f6e5b160 8571
ea9d758d
DV		 8572 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8573 if (encoder->crtc == crtc)
8574 return true;
8575
8576 return false;
8577}
8578
8579static void
8580intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8581{
8582 struct intel_encoder *intel_encoder;
8583 struct intel_crtc *intel_crtc;
8584 struct drm_connector *connector;
8585
8586 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8587 base.head) {
8588 if (!intel_encoder->base.crtc)
8589 continue;
8590
8591 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8592
8593 if (prepare_pipes & (1 << intel_crtc->pipe))
8594 intel_encoder->connectors_active = false;
8595 }
8596
8597 intel_modeset_commit_output_state(dev);
8598
8599 /* Update computed state. */
8600 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8601 base.head) {
8602 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8603 }
8604
8605 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8606 if (!connector->encoder || !connector->encoder->crtc)
8607 continue;
8608
8609 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8610
8611 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8612 struct drm_property *dpms_property =
8613 dev->mode_config.dpms_property;
8614
ea9d758d 8615 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8616 drm_object_property_set_value(&connector->base,
68d34720
DV		 8617 dpms_property,
8618 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8619
8620 intel_encoder = to_intel_encoder(connector->encoder);
8621 intel_encoder->connectors_active = true;
8622 }
8623 }
8624
8625}
8626
3bd26263 8627static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8628{
3bd26263 8629 int diff;
f1f644dc
JB		 8630
8631 if (clock1 == clock2)
8632 return true;
8633
8634 if (!clock1 || !clock2)
8635 return false;
8636
8637 diff = abs(clock1 - clock2);
8638
8639 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8640 return true;
8641
8642 return false;
8643}
8644
25c5b266
DV		 8645#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8646 list_for_each_entry((intel_crtc), \
8647 &(dev)->mode_config.crtc_list, \
8648 base.head) \
0973f18f 8649 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8650
0e8ffe1b 8651static bool
2fa2fe9a
DV		 8652intel_pipe_config_compare(struct drm_device *dev,
8653 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8654 struct intel_crtc_config *pipe_config)
8655{
66e985c0
DV		 8656#define PIPE_CONF_CHECK_X(name) \
8657 if (current_config->name != pipe_config->name) { \
8658 DRM_ERROR("mismatch in " #name " " \
8659 "(expected 0x%08x, found 0x%08x)\n", \
8660 current_config->name, \
8661 pipe_config->name); \
8662 return false; \
8663 }
8664
08a24034
DV		 8665#define PIPE_CONF_CHECK_I(name) \
8666 if (current_config->name != pipe_config->name) { \
8667 DRM_ERROR("mismatch in " #name " " \
8668 "(expected %i, found %i)\n", \
8669 current_config->name, \
8670 pipe_config->name); \
8671 return false; \
88adfff1
DV		 8672 }
8673
1bd1bd80
DV		 8674#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8675 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8676 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8677 "(expected %i, found %i)\n", \
8678 current_config->name & (mask), \
8679 pipe_config->name & (mask)); \
8680 return false; \
8681 }
8682
5e550656
VS		 8683#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8684 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8685 DRM_ERROR("mismatch in " #name " " \
8686 "(expected %i, found %i)\n", \
8687 current_config->name, \
8688 pipe_config->name); \
8689 return false; \
8690 }
8691
bb760063
DV		 8692#define PIPE_CONF_QUIRK(quirk) \
8693 ((current_config->quirks | pipe_config->quirks) & (quirk))
8694
eccb140b
DV		 8695 PIPE_CONF_CHECK_I(cpu_transcoder);
8696
08a24034
DV		 8697 PIPE_CONF_CHECK_I(has_pch_encoder);
8698 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8699 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8700 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8701 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8702 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8703 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8704
eb14cb74
VS		 8705 PIPE_CONF_CHECK_I(has_dp_encoder);
8706 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8707 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8708 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8709 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8710 PIPE_CONF_CHECK_I(dp_m_n.tu);
8711
1bd1bd80
DV		 8712 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8713 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8714 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8715 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8716 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8717 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8718
8719 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8720 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8721 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8722 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8723 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8724 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8725
c93f54cf 8726 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8727
1bd1bd80
DV		 8728 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8729 DRM_MODE_FLAG_INTERLACE);
8730
bb760063
DV		 8731 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8732 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8733 DRM_MODE_FLAG_PHSYNC);
8734 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8735 DRM_MODE_FLAG_NHSYNC);
8736 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8737 DRM_MODE_FLAG_PVSYNC);
8738 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8739 DRM_MODE_FLAG_NVSYNC);
8740 }
045ac3b5 8741
37327abd
VS		 8742 PIPE_CONF_CHECK_I(pipe_src_w);
8743 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8744
2fa2fe9a
DV		 8745 PIPE_CONF_CHECK_I(gmch_pfit.control);
8746 /* pfit ratios are autocomputed by the hw on gen4+ */
8747 if (INTEL_INFO(dev)->gen < 4)
8748 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8749 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8750 PIPE_CONF_CHECK_I(pch_pfit.pos);
8751 PIPE_CONF_CHECK_I(pch_pfit.size);
8752
42db64ef
PZ		 8753 PIPE_CONF_CHECK_I(ips_enabled);
8754
c0d43d62 8755 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8756 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8757 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8758 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8759 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8760
42571aef
VS		 8761 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8762 PIPE_CONF_CHECK_I(pipe_bpp);
8763
d71b8d4a 8764 if (!IS_HASWELL(dev)) {
5e550656 8765 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
d71b8d4a
VS		 8766 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8767 }
5e550656 8768
66e985c0 8769#undef PIPE_CONF_CHECK_X
08a24034 8770#undef PIPE_CONF_CHECK_I
1bd1bd80 8771#undef PIPE_CONF_CHECK_FLAGS
5e550656 8772#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8773#undef PIPE_CONF_QUIRK
88adfff1 8774
0e8ffe1b
DV		 8775 return true;
8776}
8777
91d1b4bd
DV		 8778static void
8779check_connector_state(struct drm_device *dev)
8af6cf88 8780{
8af6cf88
DV		 8781 struct intel_connector *connector;
8782
8783 list_for_each_entry(connector, &dev->mode_config.connector_list,
8784 base.head) {
8785 /* This also checks the encoder/connector hw state with the
8786 * ->get_hw_state callbacks. */
8787 intel_connector_check_state(connector);
8788
8789 WARN(&connector->new_encoder->base != connector->base.encoder,
8790 "connector's staged encoder doesn't match current encoder\n");
8791 }
91d1b4bd
DV		 8792}
8793
8794static void
8795check_encoder_state(struct drm_device *dev)
8796{
8797 struct intel_encoder *encoder;
8798 struct intel_connector *connector;
8af6cf88
DV		 8799
8800 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8801 base.head) {
8802 bool enabled = false;
8803 bool active = false;
8804 enum pipe pipe, tracked_pipe;
8805
8806 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8807 encoder->base.base.id,
8808 drm_get_encoder_name(&encoder->base));
8809
8810 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8811 "encoder's stage crtc doesn't match current crtc\n");
8812 WARN(encoder->connectors_active && !encoder->base.crtc,
8813 "encoder's active_connectors set, but no crtc\n");
8814
8815 list_for_each_entry(connector, &dev->mode_config.connector_list,
8816 base.head) {
8817 if (connector->base.encoder != &encoder->base)
8818 continue;
8819 enabled = true;
8820 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8821 active = true;
8822 }
8823 WARN(!!encoder->base.crtc != enabled,
8824 "encoder's enabled state mismatch "
8825 "(expected %i, found %i)\n",
8826 !!encoder->base.crtc, enabled);
8827 WARN(active && !encoder->base.crtc,
8828 "active encoder with no crtc\n");
8829
8830 WARN(encoder->connectors_active != active,
8831 "encoder's computed active state doesn't match tracked active state "
8832 "(expected %i, found %i)\n", active, encoder->connectors_active);
8833
8834 active = encoder->get_hw_state(encoder, &pipe);
8835 WARN(active != encoder->connectors_active,
8836 "encoder's hw state doesn't match sw tracking "
8837 "(expected %i, found %i)\n",
8838 encoder->connectors_active, active);
8839
8840 if (!encoder->base.crtc)
8841 continue;
8842
8843 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8844 WARN(active && pipe != tracked_pipe,
8845 "active encoder's pipe doesn't match"
8846 "(expected %i, found %i)\n",
8847 tracked_pipe, pipe);
8848
8849 }
91d1b4bd
DV		 8850}
8851
8852static void
8853check_crtc_state(struct drm_device *dev)
8854{
8855 drm_i915_private_t *dev_priv = dev->dev_private;
8856 struct intel_crtc *crtc;
8857 struct intel_encoder *encoder;
8858 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8859
8860 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8861 base.head) {
8862 bool enabled = false;
8863 bool active = false;
8864
045ac3b5
JB		 8865 memset(&pipe_config, 0, sizeof(pipe_config));
8866
8af6cf88
DV		 8867 DRM_DEBUG_KMS("[CRTC:%d]\n",
8868 crtc->base.base.id);
8869
8870 WARN(crtc->active && !crtc->base.enabled,
8871 "active crtc, but not enabled in sw tracking\n");
8872
8873 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8874 base.head) {
8875 if (encoder->base.crtc != &crtc->base)
8876 continue;
8877 enabled = true;
8878 if (encoder->connectors_active)
8879 active = true;
8880 }
6c49f241 8881
8af6cf88
DV		 8882 WARN(active != crtc->active,
8883 "crtc's computed active state doesn't match tracked active state "
8884 "(expected %i, found %i)\n", active, crtc->active);
8885 WARN(enabled != crtc->base.enabled,
8886 "crtc's computed enabled state doesn't match tracked enabled state "
8887 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8888
0e8ffe1b
DV		 8889 active = dev_priv->display.get_pipe_config(crtc,
8890 &pipe_config);
d62cf62a
DV		 8891
8892 /* hw state is inconsistent with the pipe A quirk */
8893 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8894 active = crtc->active;
8895
6c49f241
DV		 8896 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8897 base.head) {
3eaba51c 8898 enum pipe pipe;
6c49f241
DV		 8899 if (encoder->base.crtc != &crtc->base)
8900 continue;
3eaba51c
VS		 8901 if (encoder->get_config &&
8902 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8903 encoder->get_config(encoder, &pipe_config);
8904 }
8905
0e8ffe1b
DV		 8906 WARN(crtc->active != active,
8907 "crtc active state doesn't match with hw state "
8908 "(expected %i, found %i)\n", crtc->active, active);
8909
c0b03411
DV		 8910 if (active &&
8911 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8912 WARN(1, "pipe state doesn't match!\n");
8913 intel_dump_pipe_config(crtc, &pipe_config,
8914 "[hw state]");
8915 intel_dump_pipe_config(crtc, &crtc->config,
8916 "[sw state]");
8917 }
8af6cf88
DV		 8918 }
8919}
8920
91d1b4bd
DV		 8921static void
8922check_shared_dpll_state(struct drm_device *dev)
8923{
8924 drm_i915_private_t *dev_priv = dev->dev_private;
8925 struct intel_crtc *crtc;
8926 struct intel_dpll_hw_state dpll_hw_state;
8927 int i;
5358901f
DV		 8928
8929 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8930 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8931 int enabled_crtcs = 0, active_crtcs = 0;
8932 bool active;
8933
8934 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8935
8936 DRM_DEBUG_KMS("%s\n", pll->name);
8937
8938 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8939
8940 WARN(pll->active > pll->refcount,
8941 "more active pll users than references: %i vs %i\n",
8942 pll->active, pll->refcount);
8943 WARN(pll->active && !pll->on,
8944 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8945 WARN(pll->on && !pll->active,
8946 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8947 WARN(pll->on != active,
8948 "pll on state mismatch (expected %i, found %i)\n",
8949 pll->on, active);
8950
8951 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8952 base.head) {
8953 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8954 enabled_crtcs++;
8955 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8956 active_crtcs++;
8957 }
8958 WARN(pll->active != active_crtcs,
8959 "pll active crtcs mismatch (expected %i, found %i)\n",
8960 pll->active, active_crtcs);
8961 WARN(pll->refcount != enabled_crtcs,
8962 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8963 pll->refcount, enabled_crtcs);
66e985c0
DV		 8964
8965 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8966 sizeof(dpll_hw_state)),
8967 "pll hw state mismatch\n");
5358901f 8968 }
8af6cf88
DV		 8969}
8970
91d1b4bd
DV		 8971void
8972intel_modeset_check_state(struct drm_device *dev)
8973{
8974 check_connector_state(dev);
8975 check_encoder_state(dev);
8976 check_crtc_state(dev);
8977 check_shared_dpll_state(dev);
8978}
8979
18442d08
VS		 8980void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
8981 int dotclock)
8982{
8983 /*
8984 * FDI already provided one idea for the dotclock.
8985 * Yell if the encoder disagrees.
8986 */
8987 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
8988 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8989 pipe_config->adjusted_mode.clock, dotclock);
8990}
8991
f30da187
DV		 8992static int __intel_set_mode(struct drm_crtc *crtc,
8993 struct drm_display_mode *mode,
8994 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8995{
8996 struct drm_device *dev = crtc->dev;
dbf2b54e 8997 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8998 struct drm_display_mode *saved_mode, *saved_hwmode;
8999 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9000 struct intel_crtc *intel_crtc;
9001 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9002 int ret = 0;
a6778b3c 9003
3ac18232 9004 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9005 if (!saved_mode)
9006 return -ENOMEM;
3ac18232 9007 saved_hwmode = saved_mode + 1;
a6778b3c 9008
e2e1ed41 9009 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9010 &prepare_pipes, &disable_pipes);
9011
3ac18232
TG		 9012 *saved_hwmode = crtc->hwmode;
9013 *saved_mode = crtc->mode;
a6778b3c 9014
25c5b266
DV		 9015 /* Hack: Because we don't (yet) support global modeset on multiple
9016 * crtcs, we don't keep track of the new mode for more than one crtc.
9017 * Hence simply check whether any bit is set in modeset_pipes in all the
9018 * pieces of code that are not yet converted to deal with mutliple crtcs
9019 * changing their mode at the same time. */
25c5b266 9020 if (modeset_pipes) {
4e53c2e0 9021 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9022 if (IS_ERR(pipe_config)) {
9023 ret = PTR_ERR(pipe_config);
9024 pipe_config = NULL;
9025
3ac18232 9026 goto out;
25c5b266 9027 }
c0b03411
DV		 9028 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9029 "[modeset]");
25c5b266 9030 }
a6778b3c 9031
460da916
DV		 9032 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9033 intel_crtc_disable(&intel_crtc->base);
9034
ea9d758d
DV		 9035 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9036 if (intel_crtc->base.enabled)
9037 dev_priv->display.crtc_disable(&intel_crtc->base);
9038 }
a6778b3c 9039
6c4c86f5
DV		 9040 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9041 * to set it here already despite that we pass it down the callchain.
f6e5b160 9042 */
b8cecdf5 9043 if (modeset_pipes) {
25c5b266 9044 crtc->mode = *mode;
b8cecdf5
DV		 9045 /* mode_set/enable/disable functions rely on a correct pipe
9046 * config. */
9047 to_intel_crtc(crtc)->config = *pipe_config;
9048 }
7758a113 9049
ea9d758d
DV		 9050 /* Only after disabling all output pipelines that will be changed can we
9051 * update the the output configuration. */
9052 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9053
47fab737
DV		 9054 if (dev_priv->display.modeset_global_resources)
9055 dev_priv->display.modeset_global_resources(dev);
9056
a6778b3c
DV		 9057 /* Set up the DPLL and any encoders state that needs to adjust or depend
9058 * on the DPLL.
f6e5b160 9059 */
25c5b266 9060 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9061 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9062 x, y, fb);
9063 if (ret)
9064 goto done;
a6778b3c
DV		 9065 }
9066
9067 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9068 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9069 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9070
25c5b266
DV		 9071 if (modeset_pipes) {
9072 /* Store real post-adjustment hardware mode. */
b8cecdf5 9073 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9074
25c5b266
DV		 9075 /* Calculate and store various constants which
9076 * are later needed by vblank and swap-completion
9077 * timestamping. They are derived from true hwmode.
9078 */
9079 drm_calc_timestamping_constants(crtc);
9080 }
a6778b3c
DV		 9081
9082 /* FIXME: add subpixel order */
9083done:
c0c36b94 9084 if (ret && crtc->enabled) {
3ac18232
TG		 9085 crtc->hwmode = *saved_hwmode;
9086 crtc->mode = *saved_mode;
a6778b3c
DV		 9087 }
9088
3ac18232 9089out:
b8cecdf5 9090 kfree(pipe_config);
3ac18232 9091 kfree(saved_mode);
a6778b3c 9092 return ret;
f6e5b160
CW		 9093}
9094
e7457a9a
DL		 9095static int intel_set_mode(struct drm_crtc *crtc,
9096 struct drm_display_mode *mode,
9097 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9098{
9099 int ret;
9100
9101 ret = __intel_set_mode(crtc, mode, x, y, fb);
9102
9103 if (ret == 0)
9104 intel_modeset_check_state(crtc->dev);
9105
9106 return ret;
9107}
9108
c0c36b94
CW		 9109void intel_crtc_restore_mode(struct drm_crtc *crtc)
9110{
9111 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9112}
9113
25c5b266
DV		 9114#undef for_each_intel_crtc_masked
9115
d9e55608
DV		 9116static void intel_set_config_free(struct intel_set_config *config)
9117{
9118 if (!config)
9119 return;
9120
1aa4b628
DV		 9121 kfree(config->save_connector_encoders);
9122 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9123 kfree(config);
9124}
9125
85f9eb71
DV		 9126static int intel_set_config_save_state(struct drm_device *dev,
9127 struct intel_set_config *config)
9128{
85f9eb71
DV		 9129 struct drm_encoder *encoder;
9130 struct drm_connector *connector;
9131 int count;
9132
1aa4b628
DV		 9133 config->save_encoder_crtcs =
9134 kcalloc(dev->mode_config.num_encoder,
9135 sizeof(struct drm_crtc *), GFP_KERNEL);
9136 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9137 return -ENOMEM;
9138
1aa4b628
DV		 9139 config->save_connector_encoders =
9140 kcalloc(dev->mode_config.num_connector,
9141 sizeof(struct drm_encoder *), GFP_KERNEL);
9142 if (!config->save_connector_encoders)
85f9eb71
DV		 9143 return -ENOMEM;
9144
9145 /* Copy data. Note that driver private data is not affected.
9146 * Should anything bad happen only the expected state is
9147 * restored, not the drivers personal bookkeeping.
9148 */
85f9eb71
DV		 9149 count = 0;
9150 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9151 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9152 }
9153
9154 count = 0;
9155 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9156 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9157 }
9158
9159 return 0;
9160}
9161
9162static void intel_set_config_restore_state(struct drm_device *dev,
9163 struct intel_set_config *config)
9164{
9a935856
DV		 9165 struct intel_encoder *encoder;
9166 struct intel_connector *connector;
85f9eb71
DV		 9167 int count;
9168
85f9eb71 9169 count = 0;
9a935856
DV		 9170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9171 encoder->new_crtc =
9172 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9173 }
9174
9175 count = 0;
9a935856
DV		 9176 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9177 connector->new_encoder =
9178 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9179 }
9180}
9181
e3de42b6 9182static bool
2e57f47d 9183is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9184{
9185 int i;
9186
2e57f47d
CW		 9187 if (set->num_connectors == 0)
9188 return false;
9189
9190 if (WARN_ON(set->connectors == NULL))
9191 return false;
9192
9193 for (i = 0; i < set->num_connectors; i++)
9194 if (set->connectors[i]->encoder &&
9195 set->connectors[i]->encoder->crtc == set->crtc &&
9196 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9197 return true;
9198
9199 return false;
9200}
9201
5e2b584e
DV		 9202static void
9203intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9204 struct intel_set_config *config)
9205{
9206
9207 /* We should be able to check here if the fb has the same properties
9208 * and then just flip_or_move it */
2e57f47d
CW		 9209 if (is_crtc_connector_off(set)) {
9210 config->mode_changed = true;
e3de42b6 9211 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9212 /* If we have no fb then treat it as a full mode set */
9213 if (set->crtc->fb == NULL) {
319d9827
JB		 9214 struct intel_crtc *intel_crtc =
9215 to_intel_crtc(set->crtc);
9216
9217 if (intel_crtc->active && i915_fastboot) {
9218 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9219 config->fb_changed = true;
9220 } else {
9221 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9222 config->mode_changed = true;
9223 }
5e2b584e
DV		 9224 } else if (set->fb == NULL) {
9225 config->mode_changed = true;
72f4901e
DV		 9226 } else if (set->fb->pixel_format !=
9227 set->crtc->fb->pixel_format) {
5e2b584e 9228 config->mode_changed = true;
e3de42b6 9229 } else {
5e2b584e 9230 config->fb_changed = true;
e3de42b6 9231 }
5e2b584e
DV		 9232 }
9233
835c5873 9234 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9235 config->fb_changed = true;
9236
9237 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9238 DRM_DEBUG_KMS("modes are different, full mode set\n");
9239 drm_mode_debug_printmodeline(&set->crtc->mode);
9240 drm_mode_debug_printmodeline(set->mode);
9241 config->mode_changed = true;
9242 }
a1d95703
CW		 9243
9244 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9245 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9246}
9247
2e431051 9248static int
9a935856
DV		 9249intel_modeset_stage_output_state(struct drm_device *dev,
9250 struct drm_mode_set *set,
9251 struct intel_set_config *config)
50f56119 9252{
85f9eb71 9253 struct drm_crtc *new_crtc;
9a935856
DV		 9254 struct intel_connector *connector;
9255 struct intel_encoder *encoder;
f3f08572 9256 int ro;
50f56119 9257
9abdda74 9258 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9259 * of connectors. For paranoia, double-check this. */
9260 WARN_ON(!set->fb && (set->num_connectors != 0));
9261 WARN_ON(set->fb && (set->num_connectors == 0));
9262
9a935856
DV		 9263 list_for_each_entry(connector, &dev->mode_config.connector_list,
9264 base.head) {
9265 /* Otherwise traverse passed in connector list and get encoders
9266 * for them. */
50f56119 9267 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9268 if (set->connectors[ro] == &connector->base) {
9269 connector->new_encoder = connector->encoder;
50f56119
DV		 9270 break;
9271 }
9272 }
9273
9a935856
DV		 9274 /* If we disable the crtc, disable all its connectors. Also, if
9275 * the connector is on the changing crtc but not on the new
9276 * connector list, disable it. */
9277 if ((!set->fb || ro == set->num_connectors) &&
9278 connector->base.encoder &&
9279 connector->base.encoder->crtc == set->crtc) {
9280 connector->new_encoder = NULL;
9281
9282 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9283 connector->base.base.id,
9284 drm_get_connector_name(&connector->base));
9285 }
9286
9287
9288 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9289 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9290 config->mode_changed = true;
50f56119
DV		 9291 }
9292 }
9a935856 9293 /* connector->new_encoder is now updated for all connectors. */
50f56119 9294
9a935856 9295 /* Update crtc of enabled connectors. */
9a935856
DV		 9296 list_for_each_entry(connector, &dev->mode_config.connector_list,
9297 base.head) {
9298 if (!connector->new_encoder)
50f56119
DV		 9299 continue;
9300
9a935856 9301 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9302
9303 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9304 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9305 new_crtc = set->crtc;
9306 }
9307
9308 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9309 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9310 new_crtc)) {
5e2b584e 9311 return -EINVAL;
50f56119 9312 }
9a935856
DV		 9313 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9314
9315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9316 connector->base.base.id,
9317 drm_get_connector_name(&connector->base),
9318 new_crtc->base.id);
9319 }
9320
9321 /* Check for any encoders that needs to be disabled. */
9322 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9323 base.head) {
9324 list_for_each_entry(connector,
9325 &dev->mode_config.connector_list,
9326 base.head) {
9327 if (connector->new_encoder == encoder) {
9328 WARN_ON(!connector->new_encoder->new_crtc);
9329
9330 goto next_encoder;
9331 }
9332 }
9333 encoder->new_crtc = NULL;
9334next_encoder:
9335 /* Only now check for crtc changes so we don't miss encoders
9336 * that will be disabled. */
9337 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9338 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9339 config->mode_changed = true;
50f56119
DV		 9340 }
9341 }
9a935856 9342 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9343
2e431051
DV		 9344 return 0;
9345}
9346
9347static int intel_crtc_set_config(struct drm_mode_set *set)
9348{
9349 struct drm_device *dev;
2e431051
DV		 9350 struct drm_mode_set save_set;
9351 struct intel_set_config *config;
9352 int ret;
2e431051 9353
8d3e375e
DV		 9354 BUG_ON(!set);
9355 BUG_ON(!set->crtc);
9356 BUG_ON(!set->crtc->helper_private);
2e431051 9357
7e53f3a4
DV		 9358 /* Enforce sane interface api - has been abused by the fb helper. */
9359 BUG_ON(!set->mode && set->fb);
9360 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9361
2e431051
DV		 9362 if (set->fb) {
9363 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9364 set->crtc->base.id, set->fb->base.id,
9365 (int)set->num_connectors, set->x, set->y);
9366 } else {
9367 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9368 }
9369
9370 dev = set->crtc->dev;
9371
9372 ret = -ENOMEM;
9373 config = kzalloc(sizeof(*config), GFP_KERNEL);
9374 if (!config)
9375 goto out_config;
9376
9377 ret = intel_set_config_save_state(dev, config);
9378 if (ret)
9379 goto out_config;
9380
9381 save_set.crtc = set->crtc;
9382 save_set.mode = &set->crtc->mode;
9383 save_set.x = set->crtc->x;
9384 save_set.y = set->crtc->y;
9385 save_set.fb = set->crtc->fb;
9386
9387 /* Compute whether we need a full modeset, only an fb base update or no
9388 * change at all. In the future we might also check whether only the
9389 * mode changed, e.g. for LVDS where we only change the panel fitter in
9390 * such cases. */
9391 intel_set_config_compute_mode_changes(set, config);
9392
9a935856 9393 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9394 if (ret)
9395 goto fail;
9396
5e2b584e 9397 if (config->mode_changed) {
c0c36b94
CW		 9398 ret = intel_set_mode(set->crtc, set->mode,
9399 set->x, set->y, set->fb);
5e2b584e 9400 } else if (config->fb_changed) {
4878cae2
VS		 9401 intel_crtc_wait_for_pending_flips(set->crtc);
9402
4f660f49 9403 ret = intel_pipe_set_base(set->crtc,
94352cf9 9404 set->x, set->y, set->fb);
50f56119
DV		 9405 }
9406
2d05eae1 9407 if (ret) {
bf67dfeb
DV		 9408 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9409 set->crtc->base.id, ret);
50f56119 9410fail:
2d05eae1 9411 intel_set_config_restore_state(dev, config);
50f56119 9412
2d05eae1
CW		 9413 /* Try to restore the config */
9414 if (config->mode_changed &&
9415 intel_set_mode(save_set.crtc, save_set.mode,
9416 save_set.x, save_set.y, save_set.fb))
9417 DRM_ERROR("failed to restore config after modeset failure\n");
9418 }
50f56119 9419
d9e55608
DV		 9420out_config:
9421 intel_set_config_free(config);
50f56119
DV		 9422 return ret;
9423}
f6e5b160
CW		 9424
9425static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9426 .cursor_set = intel_crtc_cursor_set,
9427 .cursor_move = intel_crtc_cursor_move,
9428 .gamma_set = intel_crtc_gamma_set,
50f56119 9429 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9430 .destroy = intel_crtc_destroy,
9431 .page_flip = intel_crtc_page_flip,
9432};
9433
79f689aa
PZ		 9434static void intel_cpu_pll_init(struct drm_device *dev)
9435{
affa9354 9436 if (HAS_DDI(dev))
79f689aa
PZ		 9437 intel_ddi_pll_init(dev);
9438}
9439
5358901f
DV		 9440static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9441 struct intel_shared_dpll *pll,
9442 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9443{
5358901f 9444 uint32_t val;
ee7b9f93 9445
5358901f 9446 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9447 hw_state->dpll = val;
9448 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9449 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9450
9451 return val & DPLL_VCO_ENABLE;
9452}
9453
15bdd4cf
DV		 9454static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9455 struct intel_shared_dpll *pll)
9456{
9457 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9458 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9459}
9460
e7b903d2
DV		 9461static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9462 struct intel_shared_dpll *pll)
9463{
e7b903d2
DV		 9464 /* PCH refclock must be enabled first */
9465 assert_pch_refclk_enabled(dev_priv);
9466
15bdd4cf
DV		 9467 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9468
9469 /* Wait for the clocks to stabilize. */
9470 POSTING_READ(PCH_DPLL(pll->id));
9471 udelay(150);
9472
9473 /* The pixel multiplier can only be updated once the
9474 * DPLL is enabled and the clocks are stable.
9475 *
9476 * So write it again.
9477 */
9478 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9479 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9480 udelay(200);
9481}
9482
9483static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9484 struct intel_shared_dpll *pll)
9485{
9486 struct drm_device *dev = dev_priv->dev;
9487 struct intel_crtc *crtc;
e7b903d2
DV		 9488
9489 /* Make sure no transcoder isn't still depending on us. */
9490 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9491 if (intel_crtc_to_shared_dpll(crtc) == pll)
9492 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9493 }
9494
15bdd4cf
DV		 9495 I915_WRITE(PCH_DPLL(pll->id), 0);
9496 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9497 udelay(200);
9498}
9499
46edb027
DV		 9500static char *ibx_pch_dpll_names[] = {
9501 "PCH DPLL A",
9502 "PCH DPLL B",
9503};
9504
7c74ade1 9505static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9506{
e7b903d2 9507 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9508 int i;
9509
7c74ade1 9510 dev_priv->num_shared_dpll = 2;
ee7b9f93 9511
e72f9fbf 9512 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9513 dev_priv->shared_dplls[i].id = i;
9514 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9515 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9516 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9517 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9518 dev_priv->shared_dplls[i].get_hw_state =
9519 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9520 }
9521}
9522
7c74ade1
DV		 9523static void intel_shared_dpll_init(struct drm_device *dev)
9524{
e7b903d2 9525 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9526
9527 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9528 ibx_pch_dpll_init(dev);
9529 else
9530 dev_priv->num_shared_dpll = 0;
9531
9532 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9533 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9534 dev_priv->num_shared_dpll);
9535}
9536
b358d0a6 9537static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9538{
22fd0fab 9539 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9540 struct intel_crtc *intel_crtc;
9541 int i;
9542
9543 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9544 if (intel_crtc == NULL)
9545 return;
9546
9547 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9548
9549 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9550 for (i = 0; i < 256; i++) {
9551 intel_crtc->lut_r[i] = i;
9552 intel_crtc->lut_g[i] = i;
9553 intel_crtc->lut_b[i] = i;
9554 }
9555
80824003
JB		 9556 /* Swap pipes & planes for FBC on pre-965 */
9557 intel_crtc->pipe = pipe;
9558 intel_crtc->plane = pipe;
e2e767ab 9559 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9560 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9561 intel_crtc->plane = !pipe;
80824003
JB		 9562 }
9563
22fd0fab
JB		 9564 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9565 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9566 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9567 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9568
79e53945 9569 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9570}
9571
08d7b3d1 9572int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9573 struct drm_file *file)
08d7b3d1 9574{
08d7b3d1 9575 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9576 struct drm_mode_object *drmmode_obj;
9577 struct intel_crtc *crtc;
08d7b3d1 9578
1cff8f6b
DV		 9579 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9580 return -ENODEV;
08d7b3d1 9581
c05422d5
DV		 9582 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9583 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9584
c05422d5 9585 if (!drmmode_obj) {
08d7b3d1
CW		 9586 DRM_ERROR("no such CRTC id\n");
9587 return -EINVAL;
9588 }
9589
c05422d5
DV		 9590 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9591 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9592
c05422d5 9593 return 0;
08d7b3d1
CW		 9594}
9595
66a9278e 9596static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9597{
66a9278e
DV		 9598 struct drm_device *dev = encoder->base.dev;
9599 struct intel_encoder *source_encoder;
79e53945 9600 int index_mask = 0;
79e53945
JB		 9601 int entry = 0;
9602
66a9278e
DV		 9603 list_for_each_entry(source_encoder,
9604 &dev->mode_config.encoder_list, base.head) {
9605
9606 if (encoder == source_encoder)
79e53945 9607 index_mask |= (1 << entry);
66a9278e
DV		 9608
9609 /* Intel hw has only one MUX where enocoders could be cloned. */
9610 if (encoder->cloneable && source_encoder->cloneable)
9611 index_mask |= (1 << entry);
9612
79e53945
JB		 9613 entry++;
9614 }
4ef69c7a 9615
79e53945
JB		 9616 return index_mask;
9617}
9618
4d302442
CW		 9619static bool has_edp_a(struct drm_device *dev)
9620{
9621 struct drm_i915_private *dev_priv = dev->dev_private;
9622
9623 if (!IS_MOBILE(dev))
9624 return false;
9625
9626 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9627 return false;
9628
9629 if (IS_GEN5(dev) &&
9630 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9631 return false;
9632
9633 return true;
9634}
9635
79e53945
JB		 9636static void intel_setup_outputs(struct drm_device *dev)
9637{
725e30ad 9638 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9639 struct intel_encoder *encoder;
cb0953d7 9640 bool dpd_is_edp = false;
79e53945 9641
c9093354 9642 intel_lvds_init(dev);
79e53945 9643
c40c0f5b 9644 if (!IS_ULT(dev))
79935fca 9645 intel_crt_init(dev);
cb0953d7 9646
affa9354 9647 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9648 int found;
9649
9650 /* Haswell uses DDI functions to detect digital outputs */
9651 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9652 /* DDI A only supports eDP */
9653 if (found)
9654 intel_ddi_init(dev, PORT_A);
9655
9656 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9657 * register */
9658 found = I915_READ(SFUSE_STRAP);
9659
9660 if (found & SFUSE_STRAP_DDIB_DETECTED)
9661 intel_ddi_init(dev, PORT_B);
9662 if (found & SFUSE_STRAP_DDIC_DETECTED)
9663 intel_ddi_init(dev, PORT_C);
9664 if (found & SFUSE_STRAP_DDID_DETECTED)
9665 intel_ddi_init(dev, PORT_D);
9666 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9667 int found;
270b3042
DV		 9668 dpd_is_edp = intel_dpd_is_edp(dev);
9669
9670 if (has_edp_a(dev))
9671 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9672
dc0fa718 9673 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9674 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9675 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9676 if (!found)
e2debe91 9677 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9678 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9679 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9680 }
9681
dc0fa718 9682 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9683 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9684
dc0fa718 9685 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9686 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9687
5eb08b69 9688 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9689 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9690
270b3042 9691 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9692 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9693 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9694 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9695 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9696 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9697 PORT_C);
9698 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9699 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9700 PORT_C);
9701 }
19c03924 9702
dc0fa718 9703 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9704 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9705 PORT_B);
67cfc203
VS		 9706 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9707 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9708 }
3cfca973
JN		 9709
9710 intel_dsi_init(dev);
103a196f 9711 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9712 bool found = false;
7d57382e 9713
e2debe91 9714 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9715 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9716 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9717 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9718 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9719 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9720 }
27185ae1 9721
e7281eab 9722 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9723 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9724 }
13520b05
KH		 9725
9726 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9727
e2debe91 9728 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9729 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9730 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9731 }
27185ae1 9732
e2debe91 9733 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9734
b01f2c3a
JB		 9735 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9736 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9737 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9738 }
e7281eab 9739 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9740 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9741 }
27185ae1 9742
b01f2c3a 9743 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9744 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9745 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9746 } else if (IS_GEN2(dev))
79e53945
JB		 9747 intel_dvo_init(dev);
9748
103a196f 9749 if (SUPPORTS_TV(dev))
79e53945
JB		 9750 intel_tv_init(dev);
9751
4ef69c7a
CW		 9752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9753 encoder->base.possible_crtcs = encoder->crtc_mask;
9754 encoder->base.possible_clones =
66a9278e 9755 intel_encoder_clones(encoder);
79e53945 9756 }
47356eb6 9757
dde86e2d 9758 intel_init_pch_refclk(dev);
270b3042
DV		 9759
9760 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9761}
9762
ddfe1567
CW		 9763void intel_framebuffer_fini(struct intel_framebuffer *fb)
9764{
9765 drm_framebuffer_cleanup(&fb->base);
9766 drm_gem_object_unreference_unlocked(&fb->obj->base);
9767}
9768
79e53945
JB		 9769static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9770{
9771 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9772
ddfe1567 9773 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9774 kfree(intel_fb);
9775}
9776
9777static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9778 struct drm_file *file,
79e53945
JB		 9779 unsigned int *handle)
9780{
9781 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9782 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9783
05394f39 9784 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9785}
9786
9787static const struct drm_framebuffer_funcs intel_fb_funcs = {
9788 .destroy = intel_user_framebuffer_destroy,
9789 .create_handle = intel_user_framebuffer_create_handle,
9790};
9791
38651674
DA		 9792int intel_framebuffer_init(struct drm_device *dev,
9793 struct intel_framebuffer *intel_fb,
308e5bcb 9794 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9795 struct drm_i915_gem_object *obj)
79e53945 9796{
a35cdaa0 9797 int pitch_limit;
79e53945
JB		 9798 int ret;
9799
c16ed4be
CW		 9800 if (obj->tiling_mode == I915_TILING_Y) {
9801 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9802 return -EINVAL;
c16ed4be 9803 }
57cd6508 9804
c16ed4be
CW		 9805 if (mode_cmd->pitches[0] & 63) {
9806 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9807 mode_cmd->pitches[0]);
57cd6508 9808 return -EINVAL;
c16ed4be 9809 }
57cd6508 9810
a35cdaa0
CW		 9811 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9812 pitch_limit = 32*1024;
9813 } else if (INTEL_INFO(dev)->gen >= 4) {
9814 if (obj->tiling_mode)
9815 pitch_limit = 16*1024;
9816 else
9817 pitch_limit = 32*1024;
9818 } else if (INTEL_INFO(dev)->gen >= 3) {
9819 if (obj->tiling_mode)
9820 pitch_limit = 8*1024;
9821 else
9822 pitch_limit = 16*1024;
9823 } else
9824 /* XXX DSPC is limited to 4k tiled */
9825 pitch_limit = 8*1024;
9826
9827 if (mode_cmd->pitches[0] > pitch_limit) {
9828 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9829 obj->tiling_mode ? "tiled" : "linear",
9830 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9831 return -EINVAL;
c16ed4be 9832 }
5d7bd705
VS		 9833
9834 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9835 mode_cmd->pitches[0] != obj->stride) {
9836 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9837 mode_cmd->pitches[0], obj->stride);
5d7bd705 9838 return -EINVAL;
c16ed4be 9839 }
5d7bd705 9840
57779d06 9841 /* Reject formats not supported by any plane early. */
308e5bcb 9842 switch (mode_cmd->pixel_format) {
57779d06 9843 case DRM_FORMAT_C8:
04b3924d
VS		 9844 case DRM_FORMAT_RGB565:
9845 case DRM_FORMAT_XRGB8888:
9846 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9847 break;
9848 case DRM_FORMAT_XRGB1555:
9849 case DRM_FORMAT_ARGB1555:
c16ed4be 9850 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9851 DRM_DEBUG("unsupported pixel format: %s\n",
9852 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9853 return -EINVAL;
c16ed4be 9854 }
57779d06
VS		 9855 break;
9856 case DRM_FORMAT_XBGR8888:
9857 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9858 case DRM_FORMAT_XRGB2101010:
9859 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9860 case DRM_FORMAT_XBGR2101010:
9861 case DRM_FORMAT_ABGR2101010:
c16ed4be 9862 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9863 DRM_DEBUG("unsupported pixel format: %s\n",
9864 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9865 return -EINVAL;
c16ed4be 9866 }
b5626747 9867 break;
04b3924d
VS		 9868 case DRM_FORMAT_YUYV:
9869 case DRM_FORMAT_UYVY:
9870 case DRM_FORMAT_YVYU:
9871 case DRM_FORMAT_VYUY:
c16ed4be 9872 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9873 DRM_DEBUG("unsupported pixel format: %s\n",
9874 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9875 return -EINVAL;
c16ed4be 9876 }
57cd6508
CW		 9877 break;
9878 default:
4ee62c76
VS		 9879 DRM_DEBUG("unsupported pixel format: %s\n",
9880 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9881 return -EINVAL;
9882 }
9883
90f9a336
VS		 9884 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9885 if (mode_cmd->offsets[0] != 0)
9886 return -EINVAL;
9887
c7d73f6a
DV		 9888 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9889 intel_fb->obj = obj;
9890
79e53945
JB		 9891 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9892 if (ret) {
9893 DRM_ERROR("framebuffer init failed %d\n", ret);
9894 return ret;
9895 }
9896
79e53945
JB		 9897 return 0;
9898}
9899
79e53945
JB		 9900static struct drm_framebuffer *
9901intel_user_framebuffer_create(struct drm_device *dev,
9902 struct drm_file *filp,
308e5bcb 9903 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9904{
05394f39 9905 struct drm_i915_gem_object *obj;
79e53945 9906
308e5bcb
JB		 9907 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9908 mode_cmd->handles[0]));
c8725226 9909 if (&obj->base == NULL)
cce13ff7 9910 return ERR_PTR(-ENOENT);
79e53945 9911
d2dff872 9912 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9913}
9914
79e53945 9915static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9916 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9917 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9918};
9919
e70236a8
JB		 9920/* Set up chip specific display functions */
9921static void intel_init_display(struct drm_device *dev)
9922{
9923 struct drm_i915_private *dev_priv = dev->dev_private;
9924
ee9300bb
DV		 9925 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9926 dev_priv->display.find_dpll = g4x_find_best_dpll;
9927 else if (IS_VALLEYVIEW(dev))
9928 dev_priv->display.find_dpll = vlv_find_best_dpll;
9929 else if (IS_PINEVIEW(dev))
9930 dev_priv->display.find_dpll = pnv_find_best_dpll;
9931 else
9932 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9933
affa9354 9934 if (HAS_DDI(dev)) {
0e8ffe1b 9935 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9936 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9937 dev_priv->display.crtc_enable = haswell_crtc_enable;
9938 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9939 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9940 dev_priv->display.update_plane = ironlake_update_plane;
9941 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9942 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9943 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9944 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9945 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9946 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9947 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9948 } else if (IS_VALLEYVIEW(dev)) {
9949 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9950 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9951 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9952 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9953 dev_priv->display.off = i9xx_crtc_off;
9954 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9955 } else {
0e8ffe1b 9956 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9957 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9958 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9959 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9960 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9961 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9962 }
e70236a8 9963
e70236a8 9964 /* Returns the core display clock speed */
25eb05fc
JB		 9965 if (IS_VALLEYVIEW(dev))
9966 dev_priv->display.get_display_clock_speed =
9967 valleyview_get_display_clock_speed;
9968 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9969 dev_priv->display.get_display_clock_speed =
9970 i945_get_display_clock_speed;
9971 else if (IS_I915G(dev))
9972 dev_priv->display.get_display_clock_speed =
9973 i915_get_display_clock_speed;
257a7ffc 9974 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9975 dev_priv->display.get_display_clock_speed =
9976 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9977 else if (IS_PINEVIEW(dev))
9978 dev_priv->display.get_display_clock_speed =
9979 pnv_get_display_clock_speed;
e70236a8
JB		 9980 else if (IS_I915GM(dev))
9981 dev_priv->display.get_display_clock_speed =
9982 i915gm_get_display_clock_speed;
9983 else if (IS_I865G(dev))
9984 dev_priv->display.get_display_clock_speed =
9985 i865_get_display_clock_speed;
f0f8a9ce 9986 else if (IS_I85X(dev))
e70236a8
JB		 9987 dev_priv->display.get_display_clock_speed =
9988 i855_get_display_clock_speed;
9989 else /* 852, 830 */
9990 dev_priv->display.get_display_clock_speed =
9991 i830_get_display_clock_speed;
9992
7f8a8569 9993 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9994 if (IS_GEN5(dev)) {
674cf967 9995 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9996 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9997 } else if (IS_GEN6(dev)) {
674cf967 9998 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9999 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10000 } else if (IS_IVYBRIDGE(dev)) {
10001 /* FIXME: detect B0+ stepping and use auto training */
10002 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10003 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10004 dev_priv->display.modeset_global_resources =
10005 ivb_modeset_global_resources;
c82e4d26
ED		 10006 } else if (IS_HASWELL(dev)) {
10007 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10008 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10009 dev_priv->display.modeset_global_resources =
10010 haswell_modeset_global_resources;
a0e63c22 10011 }
6067aaea 10012 } else if (IS_G4X(dev)) {
e0dac65e 10013 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10014 }
8c9f3aaf
JB		 10015
10016 /* Default just returns -ENODEV to indicate unsupported */
10017 dev_priv->display.queue_flip = intel_default_queue_flip;
10018
10019 switch (INTEL_INFO(dev)->gen) {
10020 case 2:
10021 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10022 break;
10023
10024 case 3:
10025 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10026 break;
10027
10028 case 4:
10029 case 5:
10030 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10031 break;
10032
10033 case 6:
10034 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10035 break;
7c9017e5
JB		 10036 case 7:
10037 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10038 break;
8c9f3aaf 10039 }
e70236a8
JB		 10040}
10041
b690e96c
JB		 10042/*
10043 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10044 * resume, or other times. This quirk makes sure that's the case for
10045 * affected systems.
10046 */
0206e353 10047static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10048{
10049 struct drm_i915_private *dev_priv = dev->dev_private;
10050
10051 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10052 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10053}
10054
435793df
KP		 10055/*
10056 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10057 */
10058static void quirk_ssc_force_disable(struct drm_device *dev)
10059{
10060 struct drm_i915_private *dev_priv = dev->dev_private;
10061 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10062 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10063}
10064
4dca20ef 10065/*
5a15ab5b
CE		 10066 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10067 * brightness value
4dca20ef
CE		 10068 */
10069static void quirk_invert_brightness(struct drm_device *dev)
10070{
10071 struct drm_i915_private *dev_priv = dev->dev_private;
10072 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10073 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10074}
10075
e85843be
KM		 10076/*
10077 * Some machines (Dell XPS13) suffer broken backlight controls if
10078 * BLM_PCH_PWM_ENABLE is set.
10079 */
10080static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10081{
10082 struct drm_i915_private *dev_priv = dev->dev_private;
10083 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10084 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10085}
10086
b690e96c
JB		 10087struct intel_quirk {
10088 int device;
10089 int subsystem_vendor;
10090 int subsystem_device;
10091 void (*hook)(struct drm_device *dev);
10092};
10093
5f85f176
EE		 10094/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10095struct intel_dmi_quirk {
10096 void (*hook)(struct drm_device *dev);
10097 const struct dmi_system_id (*dmi_id_list)[];
10098};
10099
10100static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10101{
10102 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10103 return 1;
10104}
10105
10106static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10107 {
10108 .dmi_id_list = &(const struct dmi_system_id[]) {
10109 {
10110 .callback = intel_dmi_reverse_brightness,
10111 .ident = "NCR Corporation",
10112 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10113 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10114 },
10115 },
10116 { } /* terminating entry */
10117 },
10118 .hook = quirk_invert_brightness,
10119 },
10120};
10121
c43b5634 10122static struct intel_quirk intel_quirks[] = {
b690e96c 10123 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10124 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10125
b690e96c
JB		 10126 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10127 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10128
b690e96c
JB		 10129 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10130 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10131
ccd0d36e 10132 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10133 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10134 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10135
10136 /* Lenovo U160 cannot use SSC on LVDS */
10137 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10138
10139 /* Sony Vaio Y cannot use SSC on LVDS */
10140 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10141
10142 /* Acer Aspire 5734Z must invert backlight brightness */
10143 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10144
10145 /* Acer/eMachines G725 */
10146 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10147
10148 /* Acer/eMachines e725 */
10149 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10150
10151 /* Acer/Packard Bell NCL20 */
10152 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10153
10154 /* Acer Aspire 4736Z */
10155 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10156
10157 /* Dell XPS13 HD Sandy Bridge */
10158 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10159 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10160 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10161};
10162
10163static void intel_init_quirks(struct drm_device *dev)
10164{
10165 struct pci_dev *d = dev->pdev;
10166 int i;
10167
10168 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10169 struct intel_quirk *q = &intel_quirks[i];
10170
10171 if (d->device == q->device &&
10172 (d->subsystem_vendor == q->subsystem_vendor ||
10173 q->subsystem_vendor == PCI_ANY_ID) &&
10174 (d->subsystem_device == q->subsystem_device ||
10175 q->subsystem_device == PCI_ANY_ID))
10176 q->hook(dev);
10177 }
5f85f176
EE		 10178 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10179 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10180 intel_dmi_quirks[i].hook(dev);
10181 }
b690e96c
JB		 10182}
10183
9cce37f4
JB		 10184/* Disable the VGA plane that we never use */
10185static void i915_disable_vga(struct drm_device *dev)
10186{
10187 struct drm_i915_private *dev_priv = dev->dev_private;
10188 u8 sr1;
766aa1c4 10189 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10190
10191 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10192 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10193 sr1 = inb(VGA_SR_DATA);
10194 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10195
10196 /* Disable VGA memory on Intel HD */
10197 if (HAS_PCH_SPLIT(dev)) {
10198 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10199 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10200 VGA_RSRC_NORMAL_IO |
10201 VGA_RSRC_NORMAL_MEM);
10202 }
10203
9cce37f4
JB		 10204 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10205 udelay(300);
10206
10207 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10208 POSTING_READ(vga_reg);
10209}
10210
81b5c7bc
AW		 10211static void i915_enable_vga(struct drm_device *dev)
10212{
10213 /* Enable VGA memory on Intel HD */
10214 if (HAS_PCH_SPLIT(dev)) {
10215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10216 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10217 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10218 VGA_RSRC_LEGACY_MEM |
10219 VGA_RSRC_NORMAL_IO |
10220 VGA_RSRC_NORMAL_MEM);
10221 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10222 }
10223}
10224
f817586c
DV		 10225void intel_modeset_init_hw(struct drm_device *dev)
10226{
fa42e23c 10227 intel_init_power_well(dev);
0232e927 10228
a8f78b58
ED		 10229 intel_prepare_ddi(dev);
10230
f817586c
DV		 10231 intel_init_clock_gating(dev);
10232
79f5b2c7 10233 mutex_lock(&dev->struct_mutex);
8090c6b9 10234 intel_enable_gt_powersave(dev);
79f5b2c7 10235 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10236}
10237
7d708ee4
ID		 10238void intel_modeset_suspend_hw(struct drm_device *dev)
10239{
10240 intel_suspend_hw(dev);
10241}
10242
79e53945
JB		 10243void intel_modeset_init(struct drm_device *dev)
10244{
652c393a 10245 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10246 int i, j, ret;
79e53945
JB		 10247
10248 drm_mode_config_init(dev);
10249
10250 dev->mode_config.min_width = 0;
10251 dev->mode_config.min_height = 0;
10252
019d96cb
DA		 10253 dev->mode_config.preferred_depth = 24;
10254 dev->mode_config.prefer_shadow = 1;
10255
e6ecefaa 10256 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10257
b690e96c
JB		 10258 intel_init_quirks(dev);
10259
1fa61106
ED		 10260 intel_init_pm(dev);
10261
e3c74757
BW		 10262 if (INTEL_INFO(dev)->num_pipes == 0)
10263 return;
10264
e70236a8
JB		 10265 intel_init_display(dev);
10266
a6c45cf0
CW		 10267 if (IS_GEN2(dev)) {
10268 dev->mode_config.max_width = 2048;
10269 dev->mode_config.max_height = 2048;
10270 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10271 dev->mode_config.max_width = 4096;
10272 dev->mode_config.max_height = 4096;
79e53945 10273 } else {
a6c45cf0
CW		 10274 dev->mode_config.max_width = 8192;
10275 dev->mode_config.max_height = 8192;
79e53945 10276 }
5d4545ae 10277 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10278
28c97730 10279 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10280 INTEL_INFO(dev)->num_pipes,
10281 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10282
08e2a7de 10283 for_each_pipe(i) {
79e53945 10284 intel_crtc_init(dev, i);
7f1f3851
JB		 10285 for (j = 0; j < dev_priv->num_plane; j++) {
10286 ret = intel_plane_init(dev, i, j);
10287 if (ret)
06da8da2
VS		 10288 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10289 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10290 }
79e53945
JB		 10291 }
10292
79f689aa 10293 intel_cpu_pll_init(dev);
e72f9fbf 10294 intel_shared_dpll_init(dev);
ee7b9f93 10295
9cce37f4
JB		 10296 /* Just disable it once at startup */
10297 i915_disable_vga(dev);
79e53945 10298 intel_setup_outputs(dev);
11be49eb
CW		 10299
10300 /* Just in case the BIOS is doing something questionable. */
10301 intel_disable_fbc(dev);
2c7111db
CW		 10302}
10303
24929352
DV		 10304static void
10305intel_connector_break_all_links(struct intel_connector *connector)
10306{
10307 connector->base.dpms = DRM_MODE_DPMS_OFF;
10308 connector->base.encoder = NULL;
10309 connector->encoder->connectors_active = false;
10310 connector->encoder->base.crtc = NULL;
10311}
10312
7fad798e
DV		 10313static void intel_enable_pipe_a(struct drm_device *dev)
10314{
10315 struct intel_connector *connector;
10316 struct drm_connector *crt = NULL;
10317 struct intel_load_detect_pipe load_detect_temp;
10318
10319 /* We can't just switch on the pipe A, we need to set things up with a
10320 * proper mode and output configuration. As a gross hack, enable pipe A
10321 * by enabling the load detect pipe once. */
10322 list_for_each_entry(connector,
10323 &dev->mode_config.connector_list,
10324 base.head) {
10325 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10326 crt = &connector->base;
10327 break;
10328 }
10329 }
10330
10331 if (!crt)
10332 return;
10333
10334 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10335 intel_release_load_detect_pipe(crt, &load_detect_temp);
10336
652c393a 10337
7fad798e
DV		 10338}
10339
fa555837
DV		 10340static bool
10341intel_check_plane_mapping(struct intel_crtc *crtc)
10342{
7eb552ae
BW		 10343 struct drm_device *dev = crtc->base.dev;
10344 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10345 u32 reg, val;
10346
7eb552ae 10347 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10348 return true;
10349
10350 reg = DSPCNTR(!crtc->plane);
10351 val = I915_READ(reg);
10352
10353 if ((val & DISPLAY_PLANE_ENABLE) &&
10354 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10355 return false;
10356
10357 return true;
10358}
10359
24929352
DV		 10360static void intel_sanitize_crtc(struct intel_crtc *crtc)
10361{
10362 struct drm_device *dev = crtc->base.dev;
10363 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10364 u32 reg;
24929352 10365
24929352 10366 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10367 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10368 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10369
10370 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10371 * disable the crtc (and hence change the state) if it is wrong. Note
10372 * that gen4+ has a fixed plane -> pipe mapping. */
10373 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10374 struct intel_connector *connector;
10375 bool plane;
10376
24929352
DV		 10377 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10378 crtc->base.base.id);
10379
10380 /* Pipe has the wrong plane attached and the plane is active.
10381 * Temporarily change the plane mapping and disable everything
10382 * ... */
10383 plane = crtc->plane;
10384 crtc->plane = !plane;
10385 dev_priv->display.crtc_disable(&crtc->base);
10386 crtc->plane = plane;
10387
10388 /* ... and break all links. */
10389 list_for_each_entry(connector, &dev->mode_config.connector_list,
10390 base.head) {
10391 if (connector->encoder->base.crtc != &crtc->base)
10392 continue;
10393
10394 intel_connector_break_all_links(connector);
10395 }
10396
10397 WARN_ON(crtc->active);
10398 crtc->base.enabled = false;
10399 }
24929352 10400
7fad798e
DV		 10401 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10402 crtc->pipe == PIPE_A && !crtc->active) {
10403 /* BIOS forgot to enable pipe A, this mostly happens after
10404 * resume. Force-enable the pipe to fix this, the update_dpms
10405 * call below we restore the pipe to the right state, but leave
10406 * the required bits on. */
10407 intel_enable_pipe_a(dev);
10408 }
10409
24929352
DV		 10410 /* Adjust the state of the output pipe according to whether we
10411 * have active connectors/encoders. */
10412 intel_crtc_update_dpms(&crtc->base);
10413
10414 if (crtc->active != crtc->base.enabled) {
10415 struct intel_encoder *encoder;
10416
10417 /* This can happen either due to bugs in the get_hw_state
10418 * functions or because the pipe is force-enabled due to the
10419 * pipe A quirk. */
10420 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10421 crtc->base.base.id,
10422 crtc->base.enabled ? "enabled" : "disabled",
10423 crtc->active ? "enabled" : "disabled");
10424
10425 crtc->base.enabled = crtc->active;
10426
10427 /* Because we only establish the connector -> encoder ->
10428 * crtc links if something is active, this means the
10429 * crtc is now deactivated. Break the links. connector
10430 * -> encoder links are only establish when things are
10431 * actually up, hence no need to break them. */
10432 WARN_ON(crtc->active);
10433
10434 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10435 WARN_ON(encoder->connectors_active);
10436 encoder->base.crtc = NULL;
10437 }
10438 }
10439}
10440
10441static void intel_sanitize_encoder(struct intel_encoder *encoder)
10442{
10443 struct intel_connector *connector;
10444 struct drm_device *dev = encoder->base.dev;
10445
10446 /* We need to check both for a crtc link (meaning that the
10447 * encoder is active and trying to read from a pipe) and the
10448 * pipe itself being active. */
10449 bool has_active_crtc = encoder->base.crtc &&
10450 to_intel_crtc(encoder->base.crtc)->active;
10451
10452 if (encoder->connectors_active && !has_active_crtc) {
10453 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10454 encoder->base.base.id,
10455 drm_get_encoder_name(&encoder->base));
10456
10457 /* Connector is active, but has no active pipe. This is
10458 * fallout from our resume register restoring. Disable
10459 * the encoder manually again. */
10460 if (encoder->base.crtc) {
10461 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10462 encoder->base.base.id,
10463 drm_get_encoder_name(&encoder->base));
10464 encoder->disable(encoder);
10465 }
10466
10467 /* Inconsistent output/port/pipe state happens presumably due to
10468 * a bug in one of the get_hw_state functions. Or someplace else
10469 * in our code, like the register restore mess on resume. Clamp
10470 * things to off as a safer default. */
10471 list_for_each_entry(connector,
10472 &dev->mode_config.connector_list,
10473 base.head) {
10474 if (connector->encoder != encoder)
10475 continue;
10476
10477 intel_connector_break_all_links(connector);
10478 }
10479 }
10480 /* Enabled encoders without active connectors will be fixed in
10481 * the crtc fixup. */
10482}
10483
44cec740 10484void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10485{
10486 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10487 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10488
8dc8a27c
PZ		 10489 /* This function can be called both from intel_modeset_setup_hw_state or
10490 * at a very early point in our resume sequence, where the power well
10491 * structures are not yet restored. Since this function is at a very
10492 * paranoid "someone might have enabled VGA while we were not looking"
10493 * level, just check if the power well is enabled instead of trying to
10494 * follow the "don't touch the power well if we don't need it" policy
10495 * the rest of the driver uses. */
10496 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10497 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10498 return;
10499
0fde901f
KM		 10500 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10501 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10502 i915_disable_vga(dev);
0fde901f
KM		 10503 }
10504}
10505
30e984df 10506static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10507{
10508 struct drm_i915_private *dev_priv = dev->dev_private;
10509 enum pipe pipe;
24929352
DV		 10510 struct intel_crtc *crtc;
10511 struct intel_encoder *encoder;
10512 struct intel_connector *connector;
5358901f 10513 int i;
24929352 10514
0e8ffe1b
DV		 10515 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10516 base.head) {
88adfff1 10517 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10518
0e8ffe1b
DV		 10519 crtc->active = dev_priv->display.get_pipe_config(crtc,
10520 &crtc->config);
24929352
DV		 10521
10522 crtc->base.enabled = crtc->active;
10523
10524 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10525 crtc->base.base.id,
10526 crtc->active ? "enabled" : "disabled");
10527 }
10528
5358901f 10529 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10530 if (HAS_DDI(dev))
6441ab5f
PZ		 10531 intel_ddi_setup_hw_pll_state(dev);
10532
5358901f
DV		 10533 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10534 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10535
10536 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10537 pll->active = 0;
10538 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10539 base.head) {
10540 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10541 pll->active++;
10542 }
10543 pll->refcount = pll->active;
10544
35c95375
DV		 10545 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10546 pll->name, pll->refcount, pll->on);
5358901f
DV		 10547 }
10548
24929352
DV		 10549 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10550 base.head) {
10551 pipe = 0;
10552
10553 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10554 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10555 encoder->base.crtc = &crtc->base;
510d5f2f 10556 if (encoder->get_config)
045ac3b5 10557 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10558 } else {
10559 encoder->base.crtc = NULL;
10560 }
10561
10562 encoder->connectors_active = false;
10563 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10564 encoder->base.base.id,
10565 drm_get_encoder_name(&encoder->base),
10566 encoder->base.crtc ? "enabled" : "disabled",
10567 pipe);
10568 }
10569
10570 list_for_each_entry(connector, &dev->mode_config.connector_list,
10571 base.head) {
10572 if (connector->get_hw_state(connector)) {
10573 connector->base.dpms = DRM_MODE_DPMS_ON;
10574 connector->encoder->connectors_active = true;
10575 connector->base.encoder = &connector->encoder->base;
10576 } else {
10577 connector->base.dpms = DRM_MODE_DPMS_OFF;
10578 connector->base.encoder = NULL;
10579 }
10580 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10581 connector->base.base.id,
10582 drm_get_connector_name(&connector->base),
10583 connector->base.encoder ? "enabled" : "disabled");
10584 }
30e984df
DV		 10585}
10586
10587/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10588 * and i915 state tracking structures. */
10589void intel_modeset_setup_hw_state(struct drm_device *dev,
10590 bool force_restore)
10591{
10592 struct drm_i915_private *dev_priv = dev->dev_private;
10593 enum pipe pipe;
10594 struct drm_plane *plane;
10595 struct intel_crtc *crtc;
10596 struct intel_encoder *encoder;
35c95375 10597 int i;
30e984df
DV		 10598
10599 intel_modeset_readout_hw_state(dev);
24929352 10600
babea61d
JB		 10601 /*
10602 * Now that we have the config, copy it to each CRTC struct
10603 * Note that this could go away if we move to using crtc_config
10604 * checking everywhere.
10605 */
10606 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10607 base.head) {
10608 if (crtc->active && i915_fastboot) {
10609 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10610
10611 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10612 crtc->base.base.id);
10613 drm_mode_debug_printmodeline(&crtc->base.mode);
10614 }
10615 }
10616
24929352
DV		 10617 /* HW state is read out, now we need to sanitize this mess. */
10618 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10619 base.head) {
10620 intel_sanitize_encoder(encoder);
10621 }
10622
10623 for_each_pipe(pipe) {
10624 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10625 intel_sanitize_crtc(crtc);
c0b03411 10626 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10627 }
9a935856 10628
35c95375
DV		 10629 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10630 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10631
10632 if (!pll->on || pll->active)
10633 continue;
10634
10635 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10636
10637 pll->disable(dev_priv, pll);
10638 pll->on = false;
10639 }
10640
45e2b5f6 10641 if (force_restore) {
f30da187
DV		 10642 /*
10643 * We need to use raw interfaces for restoring state to avoid
10644 * checking (bogus) intermediate states.
10645 */
45e2b5f6 10646 for_each_pipe(pipe) {
b5644d05
JB		 10647 struct drm_crtc *crtc =
10648 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10649
10650 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10651 crtc->fb);
45e2b5f6 10652 }
b5644d05
JB		 10653 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10654 intel_plane_restore(plane);
0fde901f
KM		 10655
10656 i915_redisable_vga(dev);
45e2b5f6
DV		 10657 } else {
10658 intel_modeset_update_staged_output_state(dev);
10659 }
8af6cf88
DV		 10660
10661 intel_modeset_check_state(dev);
2e938892
DV		 10662
10663 drm_mode_config_reset(dev);
2c7111db
CW		 10664}
10665
10666void intel_modeset_gem_init(struct drm_device *dev)
10667{
1833b134 10668 intel_modeset_init_hw(dev);
02e792fb
DV		 10669
10670 intel_setup_overlay(dev);
24929352 10671
45e2b5f6 10672 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10673}
10674
10675void intel_modeset_cleanup(struct drm_device *dev)
10676{
652c393a
JB		 10677 struct drm_i915_private *dev_priv = dev->dev_private;
10678 struct drm_crtc *crtc;
652c393a 10679
fd0c0642
DV		 10680 /*
10681 * Interrupts and polling as the first thing to avoid creating havoc.
10682 * Too much stuff here (turning of rps, connectors, ...) would
10683 * experience fancy races otherwise.
10684 */
10685 drm_irq_uninstall(dev);
10686 cancel_work_sync(&dev_priv->hotplug_work);
10687 /*
10688 * Due to the hpd irq storm handling the hotplug work can re-arm the
10689 * poll handlers. Hence disable polling after hpd handling is shut down.
10690 */
f87ea761 10691 drm_kms_helper_poll_fini(dev);
fd0c0642 10692
652c393a
JB		 10693 mutex_lock(&dev->struct_mutex);
10694
723bfd70
JB		 10695 intel_unregister_dsm_handler();
10696
652c393a
JB		 10697 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10698 /* Skip inactive CRTCs */
10699 if (!crtc->fb)
10700 continue;
10701
3dec0095 10702 intel_increase_pllclock(crtc);
652c393a
JB		 10703 }
10704
973d04f9 10705 intel_disable_fbc(dev);
e70236a8 10706
81b5c7bc
AW		 10707 i915_enable_vga(dev);
10708
8090c6b9 10709 intel_disable_gt_powersave(dev);
0cdab21f 10710
930ebb46
DV		 10711 ironlake_teardown_rc6(dev);
10712
69341a5e
KH		 10713 mutex_unlock(&dev->struct_mutex);
10714
1630fe75
CW		 10715 /* flush any delayed tasks or pending work */
10716 flush_scheduled_work();
10717
dc652f90
JN		 10718 /* destroy backlight, if any, before the connectors */
10719 intel_panel_destroy_backlight(dev);
10720
79e53945 10721 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10722
10723 intel_cleanup_overlay(dev);
79e53945
JB		 10724}
10725
f1c79df3
ZW		 10726/*
10727 * Return which encoder is currently attached for connector.
10728 */
df0e9248 10729struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10730{
df0e9248
CW		 10731 return &intel_attached_encoder(connector)->base;
10732}
f1c79df3 10733
df0e9248
CW		 10734void intel_connector_attach_encoder(struct intel_connector *connector,
10735 struct intel_encoder *encoder)
10736{
10737 connector->encoder = encoder;
10738 drm_mode_connector_attach_encoder(&connector->base,
10739 &encoder->base);
79e53945 10740}
28d52043
DA		 10741
10742/*
10743 * set vga decode state - true == enable VGA decode
10744 */
10745int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10746{
10747 struct drm_i915_private *dev_priv = dev->dev_private;
10748 u16 gmch_ctrl;
10749
10750 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10751 if (state)
10752 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10753 else
10754 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10755 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10756 return 0;
10757}
c4a1d9e4 10758
c4a1d9e4 10759struct intel_display_error_state {
ff57f1b0
PZ		 10760
10761 u32 power_well_driver;
10762
63b66e5b
CW		 10763 int num_transcoders;
10764
c4a1d9e4
CW		 10765 struct intel_cursor_error_state {
10766 u32 control;
10767 u32 position;
10768 u32 base;
10769 u32 size;
52331309 10770 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10771
10772 struct intel_pipe_error_state {
c4a1d9e4 10773 u32 source;
52331309 10774 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10775
10776 struct intel_plane_error_state {
10777 u32 control;
10778 u32 stride;
10779 u32 size;
10780 u32 pos;
10781 u32 addr;
10782 u32 surface;
10783 u32 tile_offset;
52331309 10784 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10785
10786 struct intel_transcoder_error_state {
10787 enum transcoder cpu_transcoder;
10788
10789 u32 conf;
10790
10791 u32 htotal;
10792 u32 hblank;
10793 u32 hsync;
10794 u32 vtotal;
10795 u32 vblank;
10796 u32 vsync;
10797 } transcoder[4];
c4a1d9e4
CW		 10798};
10799
10800struct intel_display_error_state *
10801intel_display_capture_error_state(struct drm_device *dev)
10802{
0206e353 10803 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10804 struct intel_display_error_state *error;
63b66e5b
CW		 10805 int transcoders[] = {
10806 TRANSCODER_A,
10807 TRANSCODER_B,
10808 TRANSCODER_C,
10809 TRANSCODER_EDP,
10810 };
c4a1d9e4
CW		 10811 int i;
10812
63b66e5b
CW		 10813 if (INTEL_INFO(dev)->num_pipes == 0)
10814 return NULL;
10815
c4a1d9e4
CW		 10816 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10817 if (error == NULL)
10818 return NULL;
10819
ff57f1b0
PZ		 10820 if (HAS_POWER_WELL(dev))
10821 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10822
52331309 10823 for_each_pipe(i) {
a18c4c3d
PZ		 10824 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10825 error->cursor[i].control = I915_READ(CURCNTR(i));
10826 error->cursor[i].position = I915_READ(CURPOS(i));
10827 error->cursor[i].base = I915_READ(CURBASE(i));
10828 } else {
10829 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10830 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10831 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10832 }
c4a1d9e4
CW		 10833
10834 error->plane[i].control = I915_READ(DSPCNTR(i));
10835 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10836 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10837 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10838 error->plane[i].pos = I915_READ(DSPPOS(i));
10839 }
ca291363
PZ		 10840 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10841 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10842 if (INTEL_INFO(dev)->gen >= 4) {
10843 error->plane[i].surface = I915_READ(DSPSURF(i));
10844 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10845 }
10846
c4a1d9e4 10847 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10848 }
10849
10850 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10851 if (HAS_DDI(dev_priv->dev))
10852 error->num_transcoders++; /* Account for eDP. */
10853
10854 for (i = 0; i < error->num_transcoders; i++) {
10855 enum transcoder cpu_transcoder = transcoders[i];
10856
10857 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10858
10859 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10860 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10861 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10862 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10863 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10864 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10865 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10866 }
10867
12d217c7
PZ		 10868 /* In the code above we read the registers without checking if the power
10869 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10870 * prevent the next I915_WRITE from detecting it and printing an error
10871 * message. */
907b28c5 10872 intel_uncore_clear_errors(dev);
12d217c7 10873
c4a1d9e4
CW		 10874 return error;
10875}
10876
edc3d884
MK		 10877#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10878
c4a1d9e4 10879void
edc3d884 10880intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10881 struct drm_device *dev,
10882 struct intel_display_error_state *error)
10883{
10884 int i;
10885
63b66e5b
CW		 10886 if (!error)
10887 return;
10888
edc3d884 10889 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10890 if (HAS_POWER_WELL(dev))
edc3d884 10891 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10892 error->power_well_driver);
52331309 10893 for_each_pipe(i) {
edc3d884 10894 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10895 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10896
10897 err_printf(m, "Plane [%d]:\n", i);
10898 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10899 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10900 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10901 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10902 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10903 }
4b71a570 10904 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10905 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10906 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10907 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10908 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10909 }
10910
edc3d884
MK		 10911 err_printf(m, "Cursor [%d]:\n", i);
10912 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10913 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10914 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10915 }
63b66e5b
CW		 10916
10917 for (i = 0; i < error->num_transcoders; i++) {
10918 err_printf(m, " CPU transcoder: %c\n",
10919 transcoder_name(error->transcoder[i].cpu_transcoder));
10920 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10921 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10922 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10923 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10924 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10925 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10926 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10927 }
c4a1d9e4 10928}
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